Browse Source

WS cleanup: remove SPACE(s) followed by TAB

Signed-off-by: Wolfgang Denk <wd@denx.de>
Wolfgang Denk 2 years ago
parent
commit
0cf207ec01
100 changed files with 326 additions and 326 deletions
  1. 1 1
      Makefile
  2. 1 1
      arch/arc/lib/libgcc2.h
  3. 1 1
      arch/arm/cpu/arm926ejs/armada100/timer.c
  4. 10 10
      arch/arm/cpu/armv8/fel_utils.S
  5. 18 18
      arch/arm/cpu/armv8/fsl-layerscape/doc/README.lsch3
  6. 2 2
      arch/arm/cpu/armv8/fsl-layerscape/lowlevel.S
  7. 1 1
      arch/arm/dts/vf610-pinfunc.h
  8. 1 1
      arch/arm/include/asm/arch-armada100/mfp.h
  9. 11 11
      arch/arm/include/asm/arch-mx25/imx-regs.h
  10. 2 2
      arch/arm/include/asm/arch-mx5/imx-regs.h
  11. 2 2
      arch/arm/include/asm/arch-mx6/mx6_plugin.S
  12. 1 1
      arch/arm/include/asm/arch-mx7/mx7_plugin.S
  13. 1 1
      arch/arm/include/asm/arch-mx7ulp/mx7ulp_plugin.S
  14. 8 8
      arch/arm/include/asm/arch-rockchip/cru_rk3368.h
  15. 4 4
      arch/arm/include/asm/arch-vf610/iomux-vf610.h
  16. 1 1
      arch/arm/include/asm/macro.h
  17. 3 3
      arch/arm/include/asm/ti-common/davinci_nand.h
  18. 1 1
      arch/arm/lib/ccn504.S
  19. 5 5
      arch/arm/lib/div64.S
  20. 12 12
      arch/arm/mach-at91/include/mach/at91_mc.h
  21. 1 1
      arch/arm/mach-at91/include/mach/at91_st.h
  22. 18 18
      arch/arm/mach-davinci/include/mach/da8xx-usb.h
  23. 1 1
      arch/arm/mach-davinci/include/mach/davinci_misc.h
  24. 2 2
      arch/arm/mach-imx/Makefile
  25. 3 3
      arch/arm/mach-keystone/include/mach/hardware.h
  26. 1 1
      arch/arm/mach-omap2/clocks-common.c
  27. 1 1
      arch/arm/mach-omap2/omap5/prcm-regs.c
  28. 1 1
      arch/arm/mach-orion5x/timer.c
  29. 1 1
      arch/arm/mach-rmobile/pfc-r8a7790.h
  30. 1 1
      arch/arm/mach-rockchip/rk3368/Makefile
  31. 2 2
      arch/arm/mach-s5pc1xx/include/mach/sromc.h
  32. 8 8
      arch/arm/mach-socfpga/include/mach/fpga_manager_arria10.h
  33. 1 1
      arch/arm/mach-sunxi/dram_sun4i.c
  34. 2 2
      arch/arm/mach-sunxi/dram_sun8i_a33.c
  35. 1 1
      arch/arm/mach-sunxi/dram_timings/h6_ddr3_1333.c
  36. 2 2
      arch/m68k/cpu/mcf5227x/start.S
  37. 1 1
      arch/m68k/cpu/mcf523x/cpu.c
  38. 1 1
      arch/m68k/cpu/mcf52x2/cpu.c
  39. 1 1
      arch/m68k/cpu/mcf532x/cpu.c
  40. 1 1
      arch/m68k/cpu/mcf5445x/cpu.c
  41. 3 3
      arch/m68k/cpu/mcf5445x/start.S
  42. 1 1
      arch/m68k/include/asm/m5271.h
  43. 1 1
      arch/m68k/lib/muldi3.c
  44. 16 16
      arch/mips/include/asm/mipsregs.h
  45. 3 3
      arch/nds32/cpu/n1213/ae3xx/lowlevel_init.S
  46. 3 3
      arch/nds32/cpu/n1213/ag101/lowlevel_init.S
  47. 1 1
      arch/nds32/cpu/n1213/ag101/watchdog.S
  48. 4 4
      arch/nds32/cpu/n1213/start.S
  49. 4 4
      arch/powerpc/cpu/mpc85xx/start.S
  50. 2 2
      arch/powerpc/include/asm/fsl_lbc.h
  51. 2 2
      arch/powerpc/include/asm/immap_85xx.h
  52. 1 1
      arch/powerpc/include/asm/processor.h
  53. 1 1
      arch/sandbox/include/asm/gpio.h
  54. 1 1
      arch/x86/cpu/intel_common/car2.S
  55. 2 2
      arch/x86/lib/bios_asm.S
  56. 22 22
      arch/xtensa/include/asm/arch-dc233c/core.h
  57. 26 26
      arch/xtensa/include/asm/arch-de212/core.h
  58. 1 1
      arch/xtensa/lib/Makefile
  59. 1 1
      board/Marvell/guruplug/guruplug.c
  60. 1 1
      board/boundary/nitrogen6x/README
  61. 2 2
      board/freescale/ls1012afrdm/README
  62. 2 2
      board/freescale/ls1012aqds/README
  63. 4 4
      board/freescale/ls1012ardb/README
  64. 2 2
      board/freescale/ls1046afrwy/README
  65. 2 2
      board/freescale/ls1046aqds/README
  66. 3 3
      board/freescale/ls1046ardb/README
  67. 1 1
      board/freescale/m53017evb/README
  68. 1 1
      board/logicpd/am3517evm/am3517evm.h
  69. 1 1
      board/logicpd/omap3som/omap3logic.h
  70. 1 1
      board/sysam/stmark2/sbf_dram_init.S
  71. 12 12
      board/ti/am57xx/board.c
  72. 2 2
      board/ti/am57xx/mux_data.h
  73. 1 1
      cmd/cramfs.c
  74. 3 3
      cmd/spi.c
  75. 1 1
      common/hash.c
  76. 1 1
      common/hwconfig.c
  77. 1 1
      common/usb_storage.c
  78. 1 1
      disk/Makefile
  79. 3 3
      doc/README.commands.spl
  80. 2 2
      doc/README.falcon
  81. 2 2
      doc/README.odroid
  82. 1 1
      doc/device-tree-bindings/mailbox/k3-secure-proxy.txt
  83. 1 1
      doc/device-tree-bindings/memory-controller/k3-j721e-ddrss.txt
  84. 1 1
      doc/device-tree-bindings/memory-controllers/k3-am654-ddrss.txt
  85. 1 1
      doc/device-tree-bindings/net/altera_tse.txt
  86. 1 1
      doc/device-tree-bindings/net/fsl,mcf-dma-fec.txt
  87. 1 1
      doc/device-tree-bindings/net/fsl,mcf-fec.txt
  88. 1 1
      doc/device-tree-bindings/pinctrl/bcm6838-pinctrl.txt
  89. 7 7
      doc/device-tree-bindings/pinctrl/marvell,armada-apn806-pinctrl.txt
  90. 1 1
      doc/device-tree-bindings/pinctrl/marvell,mvebu-pinctrl.txt
  91. 7 7
      doc/device-tree-bindings/regulator/fsl,anatop-regulator.txt
  92. 7 7
      doc/device-tree-bindings/spi/spi-bus.txt
  93. 1 1
      doc/device-tree-bindings/spi/spi-qup.txt
  94. 1 1
      doc/device-tree-bindings/tpm2/sandbox.txt
  95. 2 2
      drivers/cache/cache-v5l2.c
  96. 1 1
      drivers/cache/sandbox_cache.c
  97. 1 1
      drivers/clk/imx/clk-pllv3.c
  98. 1 1
      drivers/crypto/Makefile
  99. 9 9
      drivers/ddr/fsl/ddr3_dimm_params.c
  100. 1 1
      drivers/ddr/marvell/axp/ddr3_spd.c

+ 1 - 1
Makefile

@@ -1739,7 +1739,7 @@ endif
 # May be overridden by arch/$(ARCH)/config.mk
 ifdef CONFIG_LTO
 quiet_cmd_u-boot__ ?= LTO     $@
-      cmd_u-boot__ ?= 								\
+      cmd_u-boot__ ?=								\
 		$(CC) -nostdlib -nostartfiles					\
 		$(LTO_FINAL_LDFLAGS) $(c_flags)					\
 		$(KBUILD_LDFLAGS:%=-Wl,%) $(LDFLAGS_u-boot:%=-Wl,%) -o $@	\

+ 1 - 1
arch/arc/lib/libgcc2.h

@@ -35,7 +35,7 @@ typedef		 int HItype	__attribute__ ((mode (HI)));
 typedef unsigned int UHItype	__attribute__ ((mode (HI)));
 #if MIN_UNITS_PER_WORD > 1
 /* These typedefs are usually forbidden on dsp's with UNITS_PER_WORD 1.  */
-typedef 	 int SItype	__attribute__ ((mode (SI)));
+typedef		 int SItype	__attribute__ ((mode (SI)));
 typedef unsigned int USItype	__attribute__ ((mode (SI)));
 #if __SIZEOF_LONG_LONG__ > 4
 /* These typedefs are usually forbidden on archs with UNITS_PER_WORD 2.  */

+ 1 - 1
arch/arm/cpu/arm926ejs/armada100/timer.c

@@ -45,7 +45,7 @@ struct armd1tmr_registers {
 #define TIMER			0	/* Use TIMER 0 */
 /* Each timer has 3 match registers */
 #define MATCH_CMP(x)		((3 * TIMER) + x)
-#define TIMER_LOAD_VAL 		0xffffffff
+#define TIMER_LOAD_VAL		0xffffffff
 #define	COUNT_RD_REQ		0x1
 
 DECLARE_GLOBAL_DATA_PTR;

+ 10 - 10
arch/arm/cpu/armv8/fel_utils.S

@@ -64,18 +64,18 @@ ENTRY(return_to_fel)
 
 /* AArch32 code to restore the state from fel_stash and return back to FEL. */
 back_in_32:
-	.word	0xe59f0028 	// ldr	r0, [pc, #40]	; load fel_stash address
-	.word	0xe5901008 	// ldr	r1, [r0, #8]
-	.word	0xe129f001 	// msr	CPSR_fc, r1
+	.word	0xe59f0028	// ldr	r0, [pc, #40]	; load fel_stash address
+	.word	0xe5901008	// ldr	r1, [r0, #8]
+	.word	0xe129f001	// msr	CPSR_fc, r1
 	.word	0xf57ff06f	// isb
-	.word	0xe590d000 	// ldr	sp, [r0]
-	.word	0xe590e004 	// ldr	lr, [r0, #4]
-	.word	0xe5901010 	// ldr	r1, [r0, #16]
-	.word	0xee0c1f10 	// mcr	15, 0, r1, cr12, cr0, {0} ; VBAR
-	.word	0xe590100c 	// ldr	r1, [r0, #12]
-	.word	0xee011f10 	// mcr	15, 0, r1, cr1, cr0, {0}  ; SCTLR
+	.word	0xe590d000	// ldr	sp, [r0]
+	.word	0xe590e004	// ldr	lr, [r0, #4]
+	.word	0xe5901010	// ldr	r1, [r0, #16]
+	.word	0xee0c1f10	// mcr	15, 0, r1, cr12, cr0, {0} ; VBAR
+	.word	0xe590100c	// ldr	r1, [r0, #12]
+	.word	0xee011f10	// mcr	15, 0, r1, cr1, cr0, {0}  ; SCTLR
 	.word	0xf57ff06f	// isb
-	.word	0xe12fff1e 	// bx	lr		; return to FEL
+	.word	0xe12fff1e	// bx	lr		; return to FEL
 fel_stash_addr:
 	.word   0x00000000	// receives fel_stash addr, by AA64 code above
 ENDPROC(return_to_fel)

+ 18 - 18
arch/arm/cpu/armv8/fsl-layerscape/doc/README.lsch3

@@ -42,22 +42,22 @@ Flash Layout
    pre-silicon platforms (simulator and emulator):
 
 	-------------------------
-	| 	FIT Image	|
+	|	FIT Image	|
 	| (linux + DTB + RFS)	|
 	------------------------- ----> 0x0120_0000
-	| 	Debug Server FW |
+	|	Debug Server FW |
 	------------------------- ----> 0x00C0_0000
-	|	AIOP FW 	|
+	|	AIOP FW		|
 	------------------------- ----> 0x0070_0000
-	|	MC FW 		|
+	|	MC FW		|
 	------------------------- ----> 0x006C_0000
-	| 	MC DPL Blob 	|
+	|	MC DPL Blob	|
 	------------------------- ----> 0x0020_0000
-	| 	BootLoader + Env|
+	|	BootLoader + Env|
 	------------------------- ----> 0x0000_1000
-	|	PBI 		|
+	|	PBI		|
 	------------------------- ----> 0x0000_0080
-	|	RCW 		|
+	|	RCW		|
 	------------------------- ----> 0x0000_0000
 
 	32-MB NOR flash layout for pre-silicon platforms (simulator and emulator)
@@ -70,45 +70,45 @@ Flash Layout
 	----------------------------------------- ----> 0x5_8790_0000	|
 	| FIT Image (linux + DTB + RFS)	(40M)	|			|
 	----------------------------------------- ----> 0x5_8510_0000	|
-	|	PHY firmware (2M)	 	|			|
+	|	PHY firmware (2M)		|			|
 	----------------------------------------- ----> 0x5_84F0_0000	| 64K
 	|	Debug Server FW (2M)		|			| Alt
 	----------------------------------------- ----> 0x5_84D0_0000	| Bank
 	|	AIOP FW (4M)			|			|
 	----------------------------------------- ----> 0x5_8490_0000 (vbank4)
-	|	MC DPC Blob (1M) 		|			|
+	|	MC DPC Blob (1M)		|			|
 	----------------------------------------- ----> 0x5_8480_0000	|
 	|	MC DPL Blob (1M)		|			|
 	----------------------------------------- ----> 0x5_8470_0000	|
-	| 	MC FW (4M)			|			|
+	|	MC FW (4M)			|			|
 	----------------------------------------- ----> 0x5_8430_0000	|
-	|	BootLoader Environment (1M) 	|			|
+	|	BootLoader Environment (1M)	|			|
 	----------------------------------------- ----> 0x5_8420_0000	|
 	|	BootLoader (1M)			|			|
 	----------------------------------------- ----> 0x5_8410_0000	|
-	|	RCW and PBI (1M) 		|			|
+	|	RCW and PBI (1M)		|			|
 	----------------------------------------- ----> 0x5_8400_0000 ---
 	|	.. Unused .. (7M)		|			|
 	----------------------------------------- ----> 0x5_8390_0000	|
 	| FIT Image (linux + DTB + RFS)	(40M)	|			|
 	----------------------------------------- ----> 0x5_8110_0000	|
-	|	PHY firmware (2M)	 	|			|
+	|	PHY firmware (2M)		|			|
 	----------------------------------------- ----> 0x5_80F0_0000	| 64K
 	|	Debug Server FW (2M)		|			| Bank
 	----------------------------------------- ----> 0x5_80D0_0000	|
 	|	AIOP FW (4M)			|			|
 	----------------------------------------- ----> 0x5_8090_0000 (vbank0)
-	|	MC DPC Blob (1M) 		|			|
+	|	MC DPC Blob (1M)		|			|
 	----------------------------------------- ----> 0x5_8080_0000	|
 	|	MC DPL Blob (1M)		|			|
 	----------------------------------------- ----> 0x5_8070_0000	|
-	| 	MC FW (4M)			|			|
+	|	MC FW (4M)			|			|
 	----------------------------------------- ----> 0x5_8030_0000	|
-	|	BootLoader Environment (1M) 	|			|
+	|	BootLoader Environment (1M)	|			|
 	----------------------------------------- ----> 0x5_8020_0000	|
 	|	BootLoader (1M)			|			|
 	----------------------------------------- ----> 0x5_8010_0000	|
-	|	RCW and PBI (1M) 		|			|
+	|	RCW and PBI (1M)		|			|
 	----------------------------------------- ----> 0x5_8000_0000 ---
 
 	128-MB NOR flash layout for QDS and RDB boards

+ 2 - 2
arch/arm/cpu/armv8/fsl-layerscape/lowlevel.S

@@ -250,7 +250,7 @@ ENTRY(lowlevel_init)
 	 * b. We use only Region0 whose NSAID write/read is EN
 	 *
 	 * NOTE: As per the CCSR map doc, TZASC 3 and TZASC 4 are just
-	 * 	 placeholders.
+	 *	 placeholders.
 	 */
 
 .macro tzasc_prog, xreg
@@ -259,7 +259,7 @@ ENTRY(lowlevel_init)
 	mov     x16, #0x10000
 	mul     x14, \xreg, x16
 	add     x14, x14,x12
-	mov 	x1, #0x8
+	mov	x1, #0x8
 	add     x1, x1, x14
 
 	ldr     w0, [x1]		/* Filter 0 Gate Keeper Register */

+ 1 - 1
arch/arm/dts/vf610-pinfunc.h

@@ -424,7 +424,7 @@
 #define VF610_PAD_PTD29__FTM3_CH2		0x104 0x000 ALT4 0x0
 #define VF610_PAD_PTD29__DSPI2_SIN		0x104 0x000 ALT5 0x0
 #define VF610_PAD_PTD29__DEBUG_OUT11		0x104 0x000 ALT7 0x0
-#define VF610_PAD_PTD28__GPIO_66	 	0x108 0x000 ALT0 0x0
+#define VF610_PAD_PTD28__GPIO_66		0x108 0x000 ALT0 0x0
 #define VF610_PAD_PTD28__FB_AD28		0x108 0x000 ALT1 0x0
 #define VF610_PAD_PTD28__NF_IO12		0x108 0x000 ALT2 0x0
 #define VF610_PAD_PTD28__I2C2_SCL		0x108 0x34C ALT3 0x1

+ 1 - 1
arch/arm/include/asm/arch-armada100/mfp.h

@@ -17,7 +17,7 @@
 /*
  * Frequently used MFP Configuration macros for all ARMADA100 family of SoCs
  *
- * 				    offset, pull,pF, drv,dF, edge,eF ,afn,aF
+ *				    offset, pull,pF, drv,dF, edge,eF ,afn,aF
  */
 /* UART1 */
 #define MFP107_UART1_TXD	(MFP_REG(0x01ac) | MFP_AF1 | MFP_DRIVE_FAST)

+ 11 - 11
arch/arm/include/asm/arch-mx25/imx-regs.h

@@ -50,11 +50,11 @@ struct ccm_regs {
 
 /* Enhanced SDRAM Controller (ESDRAMC) registers */
 struct esdramc_regs {
-	u32 ctl0; 	/* control 0 */
-	u32 cfg0; 	/* configuration 0 */
-	u32 ctl1; 	/* control 1 */
-	u32 cfg1; 	/* configuration 1 */
-	u32 misc; 	/* miscellaneous */
+	u32 ctl0;	/* control 0 */
+	u32 cfg0;	/* configuration 0 */
+	u32 ctl1;	/* control 1 */
+	u32 cfg1;	/* configuration 1 */
+	u32 misc;	/* miscellaneous */
 	u32 pad[3];
 	u32 cdly1;	/* Delay Line 1 configuration debug */
 	u32 cdly2;	/* delay line 2 configuration debug */
@@ -66,11 +66,11 @@ struct esdramc_regs {
 
 /* General Purpose Timer (GPT) registers */
 struct gpt_regs {
-	u32 ctrl;   	/* control */
-	u32 pre;    	/* prescaler */
-	u32 stat;   	/* status */
-	u32 intr;   	/* interrupt */
-	u32 cmp[3]; 	/* output compare 1-3 */
+	u32 ctrl;	/* control */
+	u32 pre;	/* prescaler */
+	u32 stat;	/* status */
+	u32 intr;	/* interrupt */
+	u32 cmp[3];	/* output compare 1-3 */
 	u32 capt[2];	/* input capture 1-2 */
 	u32 counter;	/* counter */
 };
@@ -456,7 +456,7 @@ struct epit_regs {
 #define GPT_CTRL_TEN		1		/* Timer enable	*/
 
 /* WDOG enable */
-#define WCR_WDE 		0x04
+#define WCR_WDE			0x04
 #define WSR_UNLOCK1		0x5555
 #define WSR_UNLOCK2		0xAAAA
 

+ 2 - 2
arch/arm/include/asm/arch-mx5/imx-regs.h

@@ -43,7 +43,7 @@
 #define MMC_SDHC1_BASE_ADDR	(SPBA0_BASE_ADDR + 0x00004000)
 #define MMC_SDHC2_BASE_ADDR	(SPBA0_BASE_ADDR + 0x00008000)
 #define UART3_BASE		(SPBA0_BASE_ADDR + 0x0000C000)
-#define CSPI1_BASE_ADDR 	(SPBA0_BASE_ADDR + 0x00010000)
+#define CSPI1_BASE_ADDR		(SPBA0_BASE_ADDR + 0x00010000)
 #define SSI2_BASE_ADDR		(SPBA0_BASE_ADDR + 0x00014000)
 #define MMC_SDHC3_BASE_ADDR	(SPBA0_BASE_ADDR + 0x00020000)
 #define MMC_SDHC4_BASE_ADDR	(SPBA0_BASE_ADDR + 0x00024000)
@@ -97,7 +97,7 @@
 #define IIM_BASE_ADDR		(AIPS2_BASE_ADDR + 0x00098000)
 #define CSU_BASE_ADDR		(AIPS2_BASE_ADDR + 0x0009C000)
 #define ARM_BASE_ADDR		(AIPS2_BASE_ADDR + 0x000A0000)
-#define OWIRE_BASE_ADDR 	(AIPS2_BASE_ADDR + 0x000A4000)
+#define OWIRE_BASE_ADDR		(AIPS2_BASE_ADDR + 0x000A4000)
 #define FIRI_BASE_ADDR		(AIPS2_BASE_ADDR + 0x000A8000)
 #define CSPI2_BASE_ADDR		(AIPS2_BASE_ADDR + 0x000AC000)
 #define SDMA_BASE_ADDR		(AIPS2_BASE_ADDR + 0x000B0000)

+ 2 - 2
arch/arm/include/asm/arch-mx6/mx6_plugin.S

@@ -7,10 +7,10 @@
 
 #ifdef CONFIG_ROM_UNIFIED_SECTIONS
 #define ROM_API_TABLE_BASE_ADDR_LEGACY		0x180
-#define ROM_VERSION_OFFSET               	0x80
+#define ROM_VERSION_OFFSET			0x80
 #else
 #define ROM_API_TABLE_BASE_ADDR_LEGACY		0xC0
-#define ROM_VERSION_OFFSET               	0x48
+#define ROM_VERSION_OFFSET			0x48
 #endif
 #define ROM_API_TABLE_BASE_ADDR_MX6DQ_TO15	0xC4
 #define ROM_API_TABLE_BASE_ADDR_MX6DL_TO12	0xC4

+ 1 - 1
arch/arm/include/asm/arch-mx7/mx7_plugin.S

@@ -6,7 +6,7 @@
 #include <config.h>
 
 #define ROM_API_TABLE_BASE_ADDR_LEGACY		0x180
-#define ROM_VERSION_OFFSET               	0x80
+#define ROM_VERSION_OFFSET			0x80
 #define ROM_API_HWCNFG_SETUP_OFFSET		0x08
 
 plugin_start:

+ 1 - 1
arch/arm/include/asm/arch-mx7ulp/mx7ulp_plugin.S

@@ -6,7 +6,7 @@
 #include <config.h>
 
 #define ROM_API_TABLE_BASE_ADDR_LEGACY		0x180
-#define ROM_VERSION_OFFSET               	0x80
+#define ROM_VERSION_OFFSET			0x80
 #define ROM_API_HWCNFG_SETUP_OFFSET		0x08
 
 plugin_start:

+ 8 - 8
arch/arm/include/asm/arch-rockchip/cru_rk3368.h

@@ -126,17 +126,17 @@ enum {
 	/* GLB_RST_CON */
 	PMU_GLB_SRST_CTRL_SHIFT		= 2,
 	PMU_GLB_SRST_CTRL_MASK		= GENMASK(3, 2),
-	PMU_RST_BY_FST_GLB_SRST 	= 0,
-	PMU_RST_BY_SND_GLB_SRST 	= 1,
+	PMU_RST_BY_FST_GLB_SRST		= 0,
+	PMU_RST_BY_SND_GLB_SRST		= 1,
 	PMU_RST_DISABLE			= 2,
 	WDT_GLB_SRST_CTRL_SHIFT		= 1,
 	WDT_GLB_SRST_CTRL_MASK		= BIT(1),
-	WDT_TRIGGER_SND_GLB_SRST 	= 0,
-	WDT_TRIGGER_FST_GLB_SRST 	= 1,
-	TSADC_GLB_SRST_CTRL_SHIFT 	= 0,
-	TSADC_GLB_SRST_CTRL_MASK  	= BIT(0),
-	TSADC_TRIGGER_SND_GLB_SRST 	= 0,
-	TSADC_TRIGGER_FST_GLB_SRST 	= 1,
+	WDT_TRIGGER_SND_GLB_SRST	= 0,
+	WDT_TRIGGER_FST_GLB_SRST	= 1,
+	TSADC_GLB_SRST_CTRL_SHIFT	= 0,
+	TSADC_GLB_SRST_CTRL_MASK	= BIT(0),
+	TSADC_TRIGGER_SND_GLB_SRST	= 0,
+	TSADC_TRIGGER_FST_GLB_SRST	= 1,
 
 };
 #endif

+ 4 - 4
arch/arm/include/asm/arch-vf610/iomux-vf610.h

@@ -163,13 +163,13 @@ enum {
 	VF610_PAD_PTB24__NF_WE_B		= IOMUX_PAD(0x0178, 0x0178, 5, __NA_, 0, VF610_NFC_CN_PAD_CTRL),
 	VF610_PAD_PTB25__NF_CE0_B		= IOMUX_PAD(0x017c, 0x017c, 5, __NA_, 0, VF610_NFC_CN_PAD_CTRL),
 
-	VF610_PAD_PTB27__NF_RE_B 		= IOMUX_PAD(0x0184, 0x0184, 6, __NA_, 0, VF610_NFC_CN_PAD_CTRL),
+	VF610_PAD_PTB27__NF_RE_B		= IOMUX_PAD(0x0184, 0x0184, 6, __NA_, 0, VF610_NFC_CN_PAD_CTRL),
 
-	VF610_PAD_PTC26__NF_RB_B 		= IOMUX_PAD(0x018C, 0x018C, 5, __NA_, 0, VF610_NFC_RB_PAD_CTRL),
+	VF610_PAD_PTC26__NF_RB_B		= IOMUX_PAD(0x018C, 0x018C, 5, __NA_, 0, VF610_NFC_RB_PAD_CTRL),
 
-	VF610_PAD_PTC27__NF_ALE  		= IOMUX_PAD(0x0190, 0x0190, 6, __NA_, 0, VF610_NFC_CN_PAD_CTRL),
+	VF610_PAD_PTC27__NF_ALE			= IOMUX_PAD(0x0190, 0x0190, 6, __NA_, 0, VF610_NFC_CN_PAD_CTRL),
 
-	VF610_PAD_PTC28__NF_CLE  		= IOMUX_PAD(0x0194, 0x0194, 6, __NA_, 0, VF610_NFC_CN_PAD_CTRL),
+	VF610_PAD_PTC28__NF_CLE			= IOMUX_PAD(0x0194, 0x0194, 6, __NA_, 0, VF610_NFC_CN_PAD_CTRL),
 
 	VF610_PAD_PTE0__DCU0_HSYNC		= IOMUX_PAD(0x01a4, 0x01a4, 1, __NA_, 0, VF610_DCU_PAD_CTRL),
 	VF610_PAD_PTE1__DCU0_VSYNC		= IOMUX_PAD(0x01a8, 0x01a8, 1, __NA_, 0, VF610_DCU_PAD_CTRL),

+ 1 - 1
arch/arm/include/asm/macro.h

@@ -154,7 +154,7 @@ lr	.req	x30
 	orr	\xreg1, \xreg1, \xreg2
 	cbz	\xreg1, \master_label
 #else
-	b 	\master_label
+	b	\master_label
 #endif
 .endm
 

+ 3 - 3
arch/arm/include/asm/ti-common/davinci_nand.h

@@ -12,9 +12,9 @@
 #include <linux/mtd/rawnand.h>
 #include <asm/arch/hardware.h>
 
-#define NAND_READ_START  	0x00
-#define NAND_READ_END    	0x30
-#define NAND_STATUS      	0x70
+#define NAND_READ_START		0x00
+#define NAND_READ_END		0x30
+#define NAND_STATUS		0x70
 
 #define MASK_CLE		0x10
 #define MASK_ALE		0x08

+ 1 - 1
arch/arm/lib/ccn504.S

@@ -12,7 +12,7 @@
 /*************************************************************************
  *
  * void ccn504_add_masters_to_dvm(CCI_MN_BASE, CCI_MN_RNF_NODEID_LIST,
- * 				  CCI_MN_DVM_DOMAIN_CTL_SET);
+ *				  CCI_MN_DVM_DOMAIN_CTL_SET);
  *
  * Add fully-coherent masters to DVM domain
  *

+ 5 - 5
arch/arm/lib/div64.S

@@ -34,12 +34,12 @@
  *       This is meant to be used by do_div() from include/asm/div64.h only.
  *
  * Input parameters:
- * 	xh-xl	= dividend (clobbered)
- * 	r4	= divisor (preserved)
+ *	xh-xl	= dividend (clobbered)
+ *	r4	= divisor (preserved)
  *
  * Output values:
- * 	yh-yl	= result
- * 	xh	= remainder
+ *	yh-yl	= result
+ *	xh	= remainder
  *
  * Clobbered regs: xl, ip
  */
@@ -85,7 +85,7 @@ UNWIND(.fnstart)
 #endif
 
 	@ The division loop for needed upper bit positions.
- 	@ Break out early if dividend reaches 0.
+	@ Break out early if dividend reaches 0.
 2:	cmp	xh, yl
 	orrcs	yh, yh, ip
 	subscs	xh, xh, yl

+ 12 - 12
arch/arm/mach-at91/include/mach/at91_mc.h

@@ -16,7 +16,7 @@
 #ifndef __ASSEMBLY__
 
 typedef struct at91_ebi {
-	u32 	csa;		/* 0x00 Chip Select Assignment Register */
+	u32	csa;		/* 0x00 Chip Select Assignment Register */
 	u32	cfgr;		/* 0x04 Configuration Register */
 	u32	reserved[2];
 } at91_ebi_t;
@@ -28,20 +28,20 @@ typedef struct at91_ebi {
 #define AT91_EBI_CSA_CS4A	0x0010
 
 typedef struct at91_sdramc {
-	u32	mr; 	/* 0x00 SDRAMC Mode Register */
-	u32	tr; 	/* 0x04 SDRAMC Refresh Timer Register */
-	u32	cr; 	/* 0x08 SDRAMC Configuration Register */
-	u32	ssr; 	/* 0x0C SDRAMC Self Refresh Register */
-	u32	lpr; 	/* 0x10 SDRAMC Low Power Register */
-	u32	ier; 	/* 0x14 SDRAMC Interrupt Enable Register */
-	u32	idr; 	/* 0x18 SDRAMC Interrupt Disable Register */
-	u32	imr; 	/* 0x1C SDRAMC Interrupt Mask Register */
-	u32	icr; 	/* 0x20 SDRAMC Interrupt Status Register */
+	u32	mr;	/* 0x00 SDRAMC Mode Register */
+	u32	tr;	/* 0x04 SDRAMC Refresh Timer Register */
+	u32	cr;	/* 0x08 SDRAMC Configuration Register */
+	u32	ssr;	/* 0x0C SDRAMC Self Refresh Register */
+	u32	lpr;	/* 0x10 SDRAMC Low Power Register */
+	u32	ier;	/* 0x14 SDRAMC Interrupt Enable Register */
+	u32	idr;	/* 0x18 SDRAMC Interrupt Disable Register */
+	u32	imr;	/* 0x1C SDRAMC Interrupt Mask Register */
+	u32	icr;	/* 0x20 SDRAMC Interrupt Status Register */
 	u32	reserved[3];
 } at91_sdramc_t;
 
 typedef struct at91_smc {
-	u32	csr[8]; 	/* 0x00 SDRAMC Mode Register */
+	u32	csr[8];		/* 0x00 SDRAMC Mode Register */
 } at91_smc_t;
 
 #define AT91_SMC_CSR_RWHOLD(x)		((x & 0x7) << 28)
@@ -60,7 +60,7 @@ typedef struct at91_smc {
 #define AT91_SMC_CSR_NWS(x)		(x & 0x7F)
 
 typedef struct at91_bfc {
-	u32	mr; 	/* 0x00 SDRAMC Mode Register */
+	u32	mr;	/* 0x00 SDRAMC Mode Register */
 } at91_bfc_t;
 
 typedef struct at91_mc {

+ 1 - 1
arch/arm/mach-at91/include/mach/at91_st.h

@@ -24,6 +24,6 @@ typedef struct at91_st {
 
 #define AT91_ST_WDMR_WDV(x)	(x & 0xFFFF)
 #define AT91_ST_WDMR_RSTEN	0x00010000
-#define AT91_ST_WDMR_EXTEN 	0x00020000
+#define AT91_ST_WDMR_EXTEN	0x00020000
 
 #endif

+ 18 - 18
arch/arm/mach-davinci/include/mach/da8xx-usb.h

@@ -29,22 +29,22 @@
 struct da8xx_usb_regs {
 	dv_reg	revision;
 	dv_reg	control;
-	dv_reg 	status;
-	dv_reg 	emulation;
-	dv_reg 	mode;
-	dv_reg 	autoreq;
-	dv_reg 	srpfixtime;
-	dv_reg 	teardown;
-	dv_reg 	intsrc;
-	dv_reg 	intsrc_set;
-	dv_reg 	intsrc_clr;
-	dv_reg 	intmsk;
-	dv_reg 	intmsk_set;
-	dv_reg 	intmsk_clr;
-	dv_reg 	intsrcmsk;
-	dv_reg 	eoi;
-	dv_reg 	intvector;
-	dv_reg 	grndis_size[4];
+	dv_reg	status;
+	dv_reg	emulation;
+	dv_reg	mode;
+	dv_reg	autoreq;
+	dv_reg	srpfixtime;
+	dv_reg	teardown;
+	dv_reg	intsrc;
+	dv_reg	intsrc_set;
+	dv_reg	intsrc_clr;
+	dv_reg	intmsk;
+	dv_reg	intmsk_set;
+	dv_reg	intmsk_clr;
+	dv_reg	intsrcmsk;
+	dv_reg	eoi;
+	dv_reg	intvector;
+	dv_reg	grndis_size[4];
 };
 
 #define da8xx_usb_regs ((struct da8xx_usb_regs *)DA8XX_USB_OTG_BASE)
@@ -68,13 +68,13 @@ struct da8xx_usb_regs {
 #define CFGCHIP2_OTGMODE	(3 << 13)
 #define CFGCHIP2_NO_OVERRIDE	(0 << 13)
 #define CFGCHIP2_FORCE_HOST	(1 << 13)
-#define CFGCHIP2_FORCE_DEVICE 	(2 << 13)
+#define CFGCHIP2_FORCE_DEVICE	(2 << 13)
 #define CFGCHIP2_FORCE_HOST_VBUS_LOW (3 << 13)
 #define CFGCHIP2_USB1PHYCLKMUX	(1 << 12)
 #define CFGCHIP2_USB2PHYCLKMUX	(1 << 11)
 #define CFGCHIP2_PHYPWRDN	(1 << 10)
 #define CFGCHIP2_OTGPWRDN	(1 << 9)
-#define CFGCHIP2_DATPOL 	(1 << 8)
+#define CFGCHIP2_DATPOL		(1 << 8)
 #define CFGCHIP2_USB1SUSPENDM	(1 << 7)
 #define CFGCHIP2_PHY_PLLON	(1 << 6)	/* override PLL suspend */
 #define CFGCHIP2_SESENDEN	(1 << 5)	/* Vsess_end comparator */

+ 1 - 1
arch/arm/mach-davinci/include/mach/davinci_misc.h

@@ -23,7 +23,7 @@ struct pinmux_config {
 /* pin table definition */
 struct pinmux_resource {
 	const struct pinmux_config	*pins;
-	const int 			n_pins;
+	const int			n_pins;
 };
 
 #define PINMUX_ITEM(item) { \

+ 2 - 2
arch/arm/mach-imx/Makefile

@@ -34,7 +34,7 @@ obj-$(CONFIG_CMD_PRIBLOB) += priblob.o
 obj-$(CONFIG_SPL_BUILD)	+= spl.o
 endif
 ifeq ($(SOC),$(filter $(SOC),mx7))
-obj-y 	+= cpu.o
+obj-y	+= cpu.o
 obj-$(CONFIG_SYS_I2C_MXC) += i2c-mxv7.o
 obj-$(CONFIG_ENV_IS_IN_MMC) += mmc_env.o
 obj-$(CONFIG_FSL_MFGPROT) += cmd_mfgprot.o
@@ -43,7 +43,7 @@ ifeq ($(SOC),$(filter $(SOC),mx5 mx6 mx7))
 obj-$(CONFIG_IMX_VIDEO_SKIP) += video.o
 endif
 ifeq ($(SOC),$(filter $(SOC),mx6 mx7))
-obj-y 	+= cache.o init.o
+obj-y	+= cache.o init.o
 obj-$(CONFIG_FEC_MXC) += mac.o
 obj-$(CONFIG_IMX_RDC) += rdc-sema.o
 ifneq ($(CONFIG_SPL_BUILD),y)

+ 3 - 3
arch/arm/mach-keystone/include/mach/hardware.h

@@ -148,8 +148,8 @@ typedef volatile unsigned int   *dv_reg_p;
 #define KS2_CIC_HOST_ENABLE_IDX_SET	0x34
 #define KS2_CIC_CHAN_MAP(n)		(0x0400 + (n << 2))
 
-#define KS2_UART0_BASE                	0x02530c00
-#define KS2_UART1_BASE                	0x02531000
+#define KS2_UART0_BASE			0x02530c00
+#define KS2_UART1_BASE			0x02531000
 
 /* Boot Config */
 #define KS2_DEVICE_STATE_CTRL_BASE	0x02620000
@@ -210,7 +210,7 @@ typedef volatile unsigned int   *dv_reg_p;
 #endif
 
 /* AEMIF */
-#define KS2_AEMIF_CNTRL_BASE       	0x21000a00
+#define KS2_AEMIF_CNTRL_BASE		0x21000a00
 #define DAVINCI_ASYNC_EMIF_CNTRL_BASE   KS2_AEMIF_CNTRL_BASE
 
 /* Flag from ks2_debug options to check if DSPs need to stay ON */

+ 1 - 1
arch/arm/mach-omap2/clocks-common.c

@@ -552,7 +552,7 @@ void scale_vcores(struct vcores_data const *vcores)
 		if (pv->value[opp]) {
 			/* Handle non-empty members only */
 			pv->value[opp] = optimize_vcore_voltage(pv, opp);
-     			px = (struct volts *)vcores;
+			px = (struct volts *)vcores;
 			j = 0;
 			while (px < pv) {
 				/*

+ 1 - 1
arch/arm/mach-omap2/omap5/prcm-regs.c

@@ -300,7 +300,7 @@ struct omap_sys_ctrl_regs const omap5_ctrl = {
 	.control_std_fuse_die_id_1		= 0x4A002208,
 	.control_std_fuse_die_id_2		= 0x4A00220C,
 	.control_std_fuse_die_id_3		= 0x4A002210,
-	.control_phy_power_usb 			= 0x4A002370,
+	.control_phy_power_usb			= 0x4A002370,
 	.control_phy_power_sata			= 0x4A002374,
 	.control_padconf_core_base		= 0x4A002800,
 	.control_paconf_global			= 0x4A002DA0,

+ 1 - 1
arch/arm/mach-orion5x/timer.c

@@ -69,7 +69,7 @@ struct orion5x_tmr_registers *orion5x_tmr_regs =
 #define TVR_ARM_TIMER_OFFS		0
 #define TVR_ARM_TIMER_MASK		0xffffffff
 #define TVR_ARM_TIMER_MAX		0xffffffff
-#define TIMER_LOAD_VAL 			0xffffffff
+#define TIMER_LOAD_VAL			0xffffffff
 
 static inline ulong read_timer(void)
 {

+ 1 - 1
arch/arm/mach-rmobile/pfc-r8a7790.h

@@ -82,7 +82,7 @@
 	PORT_1(fn, pfx##26, sfx), PORT_1(fn, pfx##27, sfx)
 
 #define CPU_32_PORT0_16(fn, pfx, sfx)				\
-	PORT_10(fn, pfx, sfx), 					\
+	PORT_10(fn, pfx, sfx),					\
 	PORT_1(fn, pfx##10, sfx),PORT_1(fn, pfx##11, sfx),	\
 	PORT_1(fn, pfx##12, sfx), PORT_1(fn, pfx##13, sfx),	\
 	PORT_1(fn, pfx##14, sfx), PORT_1(fn, pfx##15, sfx),	\

+ 1 - 1
arch/arm/mach-rockchip/rk3368/Makefile

@@ -3,4 +3,4 @@
 # Copyright (c) 2016 Andreas Färber
 obj-y		+= clk_rk3368.o
 obj-y		+= rk3368.o
-obj-y 		+= syscon_rk3368.o
+obj-y		+= syscon_rk3368.o

+ 2 - 2
arch/arm/mach-s5pc1xx/include/mach/sromc.h

@@ -4,9 +4,9 @@
  * Naveen Krishna Ch <ch.naveen@samsung.com>
  *
  * Note: This file contains the register description for Memory subsystem
- * 	 (SROM, NAND Flash, OneNand, DDR, OneDRAM) on S5PC1XX.
+ *	 (SROM, NAND Flash, OneNand, DDR, OneDRAM) on S5PC1XX.
  *
- * 	 Only SROMC is defined as of now
+ *	 Only SROMC is defined as of now
  */
 
 #ifndef __ASM_ARCH_SROMC_H_

+ 8 - 8
arch/arm/mach-socfpga/include/mach/fpga_manager_arria10.h

@@ -14,8 +14,8 @@
 
 #define ALT_FPGAMGR_IMGCFG_STAT_F2S_CRC_ERROR_SET_MSK		BIT(0)
 #define ALT_FPGAMGR_IMGCFG_STAT_F2S_EARLY_USERMODE_SET_MSK	BIT(1)
-#define ALT_FPGAMGR_IMGCFG_STAT_F2S_USERMODE_SET_MSK 		BIT(2)
-#define ALT_FPGAMGR_IMGCFG_STAT_F2S_INITDONE_OE_SET_MSK 	BIT(3)
+#define ALT_FPGAMGR_IMGCFG_STAT_F2S_USERMODE_SET_MSK		BIT(2)
+#define ALT_FPGAMGR_IMGCFG_STAT_F2S_INITDONE_OE_SET_MSK		BIT(3)
 #define ALT_FPGAMGR_IMGCFG_STAT_F2S_NSTATUS_PIN_SET_MSK		BIT(4)
 #define ALT_FPGAMGR_IMGCFG_STAT_F2S_NSTATUS_OE_SET_MSK		BIT(5)
 #define ALT_FPGAMGR_IMGCFG_STAT_F2S_CONDONE_PIN_SET_MSK		BIT(6)
@@ -26,9 +26,9 @@
 #define ALT_FPGAMGR_IMGCFG_STAT_F2S_PR_ERROR_SET_MSK		BIT(11)
 #define ALT_FPGAMGR_IMGCFG_STAT_F2S_NCONFIG_PIN_SET_MSK		BIT(12)
 #define ALT_FPGAMGR_IMGCFG_STAT_F2S_NCEO_OE_SET_MSK		BIT(13)
-#define ALT_FPGAMGR_IMGCFG_STAT_F2S_MSEL0_SET_MSK    		BIT(16)
-#define ALT_FPGAMGR_IMGCFG_STAT_F2S_MSEL1_SET_MSK    		BIT(17)
-#define ALT_FPGAMGR_IMGCFG_STAT_F2S_MSEL2_SET_MSK    		BIT(18)
+#define ALT_FPGAMGR_IMGCFG_STAT_F2S_MSEL0_SET_MSK		BIT(16)
+#define ALT_FPGAMGR_IMGCFG_STAT_F2S_MSEL1_SET_MSK		BIT(17)
+#define ALT_FPGAMGR_IMGCFG_STAT_F2S_MSEL2_SET_MSK		BIT(18)
 #define ALT_FPGAMGR_IMGCFG_STAT_F2S_MSEL_SET_MSD (\
 	ALT_FPGAMGR_IMGCFG_STAT_F2S_MSEL0_SET_MSK |\
 	ALT_FPGAMGR_IMGCFG_STAT_F2S_MSEL1_SET_MSK |\
@@ -50,9 +50,9 @@
 #define ALT_FPGAMGR_IMGCFG_CTL_01_S2F_PR_REQUEST_SET_MSK	BIT(16)
 #define ALT_FPGAMGR_IMGCFG_CTL_01_S2F_NCE_SET_MSK		BIT(24)
 
-#define ALT_FPGAMGR_IMGCFG_CTL_02_EN_CFG_CTRL_SET_MSK    	BIT(0)
-#define ALT_FPGAMGR_IMGCFG_CTL_02_EN_CFG_DATA_SET_MSK    	BIT(8)
-#define ALT_FPGAMGR_IMGCFG_CTL_02_CDRATIO_SET_MSK    		0x00030000
+#define ALT_FPGAMGR_IMGCFG_CTL_02_EN_CFG_CTRL_SET_MSK		BIT(0)
+#define ALT_FPGAMGR_IMGCFG_CTL_02_EN_CFG_DATA_SET_MSK		BIT(8)
+#define ALT_FPGAMGR_IMGCFG_CTL_02_CDRATIO_SET_MSK		0x00030000
 #define ALT_FPGAMGR_IMGCFG_CTL_02_CFGWIDTH_SET_MSK		BIT(24)
 #define ALT_FPGAMGR_IMGCFG_CTL_02_CDRATIO_LSB			16
 

+ 1 - 1
arch/arm/mach-sunxi/dram_sun4i.c

@@ -279,7 +279,7 @@ static void mctl_setup_dram_clock(u32 clk, u32 mbus_clk)
 		reg_val |= CCM_PLL5_CTRL_M(CCM_PLL5_CTRL_M_X(2));
 		reg_val |= CCM_PLL5_CTRL_K(CCM_PLL5_CTRL_K_X(3));
 		reg_val |= CCM_PLL5_CTRL_N(CCM_PLL5_CTRL_N_X(11));
-	} else 	{
+	} else {
 		/* any other frequency that is a multiple of 24 */
 		reg_val |= CCM_PLL5_CTRL_M(CCM_PLL5_CTRL_M_X(2));
 		reg_val |= CCM_PLL5_CTRL_K(CCM_PLL5_CTRL_K_X(2));

+ 2 - 2
arch/arm/mach-sunxi/dram_sun8i_a33.c

@@ -126,8 +126,8 @@ static void auto_set_timing_para(struct dram_para *para)
 	u32 tdinit3	= (1 * CONFIG_DRAM_CLK) + 1;		/* 1us */
 
 	u8 twtp		= tcwl + 2 + twr;	/* WL + BL / 2 + tWR */
-	u8 twr2rd	= tcwl + 2 + twtr; 	/* WL + BL / 2 + tWTR */
-	u8 trd2wr	= tcl + 2 + 1 - tcwl; 	/* RL + BL / 2 + 2 - WL */
+	u8 twr2rd	= tcwl + 2 + twtr;	/* WL + BL / 2 + tWTR */
+	u8 trd2wr	= tcl + 2 + 1 - tcwl;	/* RL + BL / 2 + 2 - WL */
 
 	/* Set work mode register */
 	mctl_set_cr(para);

+ 1 - 1
arch/arm/mach-sunxi/dram_timings/h6_ddr3_1333.c

@@ -30,7 +30,7 @@
  * MR1: DLL enabled, output strength RZQ/6, Rtt_norm RZQ/2,
  *	write levelling disabled, TDQS disabled, output buffer enabled
  * MR2: manual full array self refresh, dynamic ODT off,
- * 	CAS write latency (CWL): 8
+ *	CAS write latency (CWL): 8
  */
 static u32 mr_ddr3[7] = {
 	0x00001c70, 0x00000040, 0x00000018, 0x00000000,

+ 2 - 2
arch/m68k/cpu/mcf5227x/start.S

@@ -37,10 +37,10 @@
 _vectors:
 #if defined(CONFIG_CF_SBF)
 INITSP:	.long	0			/* Initial SP	*/
-INITPC:	.long	ASM_DRAMINIT		/* Initial PC 	*/
+INITPC:	.long	ASM_DRAMINIT		/* Initial PC	*/
 #else
 INITSP:	.long	0			/* Initial SP	*/
-INITPC:	.long	_START			/* Initial PC 	*/
+INITPC:	.long	_START			/* Initial PC	*/
 #endif
 
 vector02_0F:

+ 1 - 1
arch/m68k/cpu/mcf523x/cpu.c

@@ -106,7 +106,7 @@ int watchdog_init(void)
 #if defined(CONFIG_MCFFEC)
 /* Default initializations for MCFFEC controllers.  To override,
  * create a board-specific function called:
- * 	int board_eth_init(struct bd_info *bis)
+ *	int board_eth_init(struct bd_info *bis)
  */
 
 int cpu_eth_init(struct bd_info *bis)

+ 1 - 1
arch/m68k/cpu/mcf52x2/cpu.c

@@ -421,7 +421,7 @@ int do_reset(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[])
 #if defined(CONFIG_MCFFEC)
 /* Default initializations for MCFFEC controllers.  To override,
  * create a board-specific function called:
- * 	int board_eth_init(struct bd_info *bis)
+ *	int board_eth_init(struct bd_info *bis)
  */
 
 int cpu_eth_init(struct bd_info *bis)

+ 1 - 1
arch/m68k/cpu/mcf532x/cpu.c

@@ -148,7 +148,7 @@ int watchdog_init(void)
 #if defined(CONFIG_MCFFEC)
 /* Default initializations for MCFFEC controllers.  To override,
  * create a board-specific function called:
- * 	int board_eth_init(struct bd_info *bis)
+ *	int board_eth_init(struct bd_info *bis)
  */
 int cpu_eth_init(struct bd_info *bis)
 {

+ 1 - 1
arch/m68k/cpu/mcf5445x/cpu.c

@@ -110,7 +110,7 @@ int print_cpuinfo(void)
 #if defined(CONFIG_MCFFEC)
 /* Default initializations for MCFFEC controllers.  To override,
  * create a board-specific function called:
- * 	int board_eth_init(struct bd_info *bis)
+ *	int board_eth_init(struct bd_info *bis)
  */
 
 int cpu_eth_init(struct bd_info *bis)

+ 3 - 3
arch/m68k/cpu/mcf5445x/start.S

@@ -44,16 +44,16 @@ _vectors:
 
 INITSP:	.long	0			/* Initial SP	*/
 #ifdef CONFIG_CF_SBF
-INITPC:	.long	ASM_DRAMINIT		/* Initial PC 	*/
+INITPC:	.long	ASM_DRAMINIT		/* Initial PC	*/
 #endif
 #ifdef CONFIG_SYS_NAND_BOOT
-INITPC:	.long	ASM_DRAMINIT_N		/* Initial PC 	*/
+INITPC:	.long	ASM_DRAMINIT_N		/* Initial PC	*/
 #endif
 
 #else
 
 INITSP:	.long	0			/* Initial SP	*/
-INITPC:	.long	_START			/* Initial PC 	*/
+INITPC:	.long	_START			/* Initial PC	*/
 
 #endif
 

+ 1 - 1
arch/m68k/include/asm/m5271.h

@@ -115,7 +115,7 @@
 #define MCF_GPIO_PAR_TIMER			0x10004C
 
 #define MCF_DSCR_EIM				0x100050
-#define MCF_DCSR_FEC12C 			0x100052
+#define MCF_DCSR_FEC12C				0x100052
 #define MCF_DCSR_UART				0x100053
 #define MCF_DCSR_QSPI				0x100054
 #define MCF_DCSR_TIMER				0x100055

+ 1 - 1
arch/m68k/lib/muldi3.c

@@ -41,7 +41,7 @@
     umul_ppmm (__w.s.high, __w.s.low, u, v);				\
     __w.ll; })
 
-typedef 	 int SItype	__attribute__ ((mode (SI)));
+typedef		 int SItype	__attribute__ ((mode (SI)));
 typedef unsigned int USItype	__attribute__ ((mode (SI)));
 typedef		 int DItype	__attribute__ ((mode (DI)));
 typedef int word_type __attribute__ ((mode (__word__)));

+ 16 - 16
arch/mips/include/asm/mipsregs.h

@@ -2307,8 +2307,8 @@ do {									\
 	"	.set " MIPS_ISA_LEVEL "				\n"	\
 	"	.set dsp					\n"	\
 	"	mflo %0, $ac0					\n"	\
-	"	.set pop					\n" 	\
-	: "=r" (mflo0)); 						\
+	"	.set pop					\n"	\
+	: "=r" (mflo0));						\
 	mflo0;								\
 })
 
@@ -2320,8 +2320,8 @@ do {									\
 	"	.set " MIPS_ISA_LEVEL "				\n"	\
 	"	.set dsp					\n"	\
 	"	mflo %0, $ac1					\n"	\
-	"	.set pop					\n" 	\
-	: "=r" (mflo1)); 						\
+	"	.set pop					\n"	\
+	: "=r" (mflo1));						\
 	mflo1;								\
 })
 
@@ -2333,8 +2333,8 @@ do {									\
 	"	.set " MIPS_ISA_LEVEL "				\n"	\
 	"	.set dsp					\n"	\
 	"	mflo %0, $ac2					\n"	\
-	"	.set pop					\n" 	\
-	: "=r" (mflo2)); 						\
+	"	.set pop					\n"	\
+	: "=r" (mflo2));						\
 	mflo2;								\
 })
 
@@ -2346,8 +2346,8 @@ do {									\
 	"	.set " MIPS_ISA_LEVEL "				\n"	\
 	"	.set dsp					\n"	\
 	"	mflo %0, $ac3					\n"	\
-	"	.set pop					\n" 	\
-	: "=r" (mflo3)); 						\
+	"	.set pop					\n"	\
+	: "=r" (mflo3));						\
 	mflo3;								\
 })
 
@@ -2359,8 +2359,8 @@ do {									\
 	"	.set " MIPS_ISA_LEVEL "				\n"	\
 	"	.set dsp					\n"	\
 	"	mfhi %0, $ac0					\n"	\
-	"	.set pop					\n" 	\
-	: "=r" (mfhi0)); 						\
+	"	.set pop					\n"	\
+	: "=r" (mfhi0));						\
 	mfhi0;								\
 })
 
@@ -2372,8 +2372,8 @@ do {									\
 	"	.set " MIPS_ISA_LEVEL "				\n"	\
 	"	.set dsp					\n"	\
 	"	mfhi %0, $ac1					\n"	\
-	"	.set pop					\n" 	\
-	: "=r" (mfhi1)); 						\
+	"	.set pop					\n"	\
+	: "=r" (mfhi1));						\
 	mfhi1;								\
 })
 
@@ -2385,8 +2385,8 @@ do {									\
 	"	.set " MIPS_ISA_LEVEL "				\n"	\
 	"	.set dsp					\n"	\
 	"	mfhi %0, $ac2					\n"	\
-	"	.set pop					\n" 	\
-	: "=r" (mfhi2)); 						\
+	"	.set pop					\n"	\
+	: "=r" (mfhi2));						\
 	mfhi2;								\
 })
 
@@ -2398,8 +2398,8 @@ do {									\
 	"	.set " MIPS_ISA_LEVEL "				\n"	\
 	"	.set dsp					\n"	\
 	"	mfhi %0, $ac3					\n"	\
-	"	.set pop					\n" 	\
-	: "=r" (mfhi3)); 						\
+	"	.set pop					\n"	\
+	: "=r" (mfhi3));						\
 	mfhi3;								\
 })
 

+ 3 - 3
arch/nds32/cpu/n1213/ae3xx/lowlevel_init.S

@@ -38,9 +38,9 @@
  * for Orca and Emerald
  */
 #define BOARD_ID_REG		0x104
-#define BOARD_ID_FAMILY_MASK 	0xfff000
-#define BOARD_ID_FAMILY_V5   	0x556000
-#define BOARD_ID_FAMILY_K7   	0x74b000
+#define BOARD_ID_FAMILY_MASK	0xfff000
+#define BOARD_ID_FAMILY_V5	0x556000
+#define BOARD_ID_FAMILY_K7	0x74b000
 
 /*
  * parameters for the static memory controller

+ 3 - 3
arch/nds32/cpu/n1213/ag101/lowlevel_init.S

@@ -38,9 +38,9 @@
  * for Orca and Emerald
  */
 #define BOARD_ID_REG		0x104
-#define BOARD_ID_FAMILY_MASK 	0xfff000
-#define BOARD_ID_FAMILY_V5   	0x556000
-#define BOARD_ID_FAMILY_K7   	0x74b000
+#define BOARD_ID_FAMILY_MASK	0xfff000
+#define BOARD_ID_FAMILY_V5	0x556000
+#define BOARD_ID_FAMILY_K7	0x74b000
 
 /*
  * parameters for the static memory controller

+ 1 - 1
arch/nds32/cpu/n1213/ag101/watchdog.S

@@ -16,7 +16,7 @@ ENTRY(turnoff_watchdog)
 #define WD_ENABLE	0x1
 
 	! Turn off the watchdog, according to Faraday FTWDT010 spec
-	li 	$p0, (CONFIG_FTWDT010_BASE+WD_CR)	! Get the addr of WD CR
+	li	$p0, (CONFIG_FTWDT010_BASE+WD_CR)	! Get the addr of WD CR
 	lwi	$p1, [$p0]				! Get the config of WD
 	andi	$p1, $p1, 0x1f				! Wipe out useless bits
 	li	$r0, ~WD_ENABLE

+ 4 - 4
arch/nds32/cpu/n1213/start.S

@@ -20,7 +20,7 @@
  */
 #define ENA_DCAC		2UL
 #define DIS_DCAC		~ENA_DCAC
-#define ICAC_MEM_KBF_ISET	(0x07)	 	! I Cache sets per way
+#define ICAC_MEM_KBF_ISET	(0x07)		! I Cache sets per way
 #define ICAC_MEM_KBF_IWAY	(0x07<<3)	! I cache ways
 #define ICAC_MEM_KBF_ISZ	(0x07<<6)	! I cache line size
 #define DCAC_MEM_KBF_DSET	(0x07)		! D Cache sets per way
@@ -434,21 +434,21 @@ tlb_fill:
 	SAVE_ALL
 	move	$r0, $sp			! To get the kernel stack
 	li	$r1, 1				! Determine interruption type
-	bal 	do_interruption
+	bal	do_interruption
 
 	.align	5
 tlb_not_present:
 	SAVE_ALL
 	move	$r0, $sp			! To get the kernel stack
 	li	$r1, 2				! Determine interruption type
-	bal 	do_interruption
+	bal	do_interruption
 
 	.align	5
 tlb_misc:
 	SAVE_ALL
 	move	$r0, $sp			! To get the kernel stack
 	li	$r1, 3				! Determine interruption type
-	bal 	do_interruption
+	bal	do_interruption
 
 	.align	5
 tlb_vlpt_miss:

+ 4 - 4
arch/powerpc/cpu/mpc85xx/start.S

@@ -76,7 +76,7 @@
 _start_e500:
 /* Enable debug exception */
 	li	r1,MSR_DE
-	mtmsr 	r1
+	mtmsr	r1
 
 	/*
 	 * If we got an ePAPR device tree pointer passed in as r3, we need that
@@ -1159,9 +1159,9 @@ _start_cont:
 
 	li	r0,0
 
-1: 	subi 	r4,r4,4
-	stw 	r0,0(r4)
-	cmplw 	r4,r3
+1:	subi	r4,r4,4
+	stw	r0,0(r4)
+	cmplw	r4,r3
 	bne	1b
 
 #if CONFIG_VAL(SYS_MALLOC_F_LEN)

+ 2 - 2
arch/powerpc/include/asm/fsl_lbc.h

@@ -294,8 +294,8 @@ void lbc_sdram_init(void);
 #define LBCR_EPAR_SHIFT			16
 #define LBCR_BMT			0x0000FF00
 #define LBCR_BMT_SHIFT			8
-#define LBCR_BMTPS	 		0x0000000F
-#define LBCR_BMTPS_SHIFT 		0
+#define LBCR_BMTPS			0x0000000F
+#define LBCR_BMTPS_SHIFT		0
 
 /* LCRR - Clock Ratio Register
  */

+ 2 - 2
arch/powerpc/include/asm/immap_85xx.h

@@ -1510,7 +1510,7 @@ typedef struct par_io {
  */
 
 typedef struct cpc_corenet {
-	u32 	cpccsr0;	/* Config/status reg */
+	u32	cpccsr0;	/* Config/status reg */
 	u32	res1;
 	u32	cpccfg0;	/* Configuration register */
 	u32	res2;
@@ -1573,7 +1573,7 @@ typedef struct cpc_corenet {
 #define CPC_SRCR0_SRAMSZ_16_WAY	0x00000008
 #define CPC_SRCR0_SRAMSZ_32_WAY	0x0000000a
 #define CPC_SRCR0_SRAMEN	0x00000001
-#define	CPC_ERRDIS_TMHITDIS  	0x00000080	/* multi-way hit disable */
+#define	CPC_ERRDIS_TMHITDIS	0x00000080	/* multi-way hit disable */
 #define CPC_HDBCR0_CDQ_SPEC_DIS	0x08000000
 #define CPC_HDBCR0_TAG_ECC_SCRUB_DIS	0x01000000
 #define CPC_HDBCR0_DATA_ECC_SCRUB_DIS	0x00400000

+ 1 - 1
arch/powerpc/include/asm/processor.h

@@ -748,7 +748,7 @@
 #define MAS5	SPRN_MAS5
 #define MAS6	SPRN_MAS6
 #define MAS7	SPRN_MAS7
-#define MAS8 	SPRN_MAS8
+#define MAS8	SPRN_MAS8
 
 #if defined(CONFIG_MPC85xx)
 #define DAR_DEAR DEAR

+ 1 - 1
arch/sandbox/include/asm/gpio.h

@@ -65,7 +65,7 @@ int sandbox_gpio_get_direction(struct udevice *dev, unsigned int offset);
  *
  * @param dev		device to use
  * @param offset	GPIO offset within bank
- * @param output 	0 to set as input, 1 to set as output
+ * @param output	0 to set as input, 1 to set as output
  * @return -1 on error, 0 if ok
  */
 int sandbox_gpio_set_direction(struct udevice *dev, unsigned int offset,

+ 1 - 1
arch/x86/cpu/intel_common/car2.S

@@ -88,7 +88,7 @@ clear_var_mtrr:
 	 *  MTRR_PHYS_MASK_HIGH = 0000000FFh  For 40 bit addressing
 	 */
 
-	movl	$0x80000008, %eax 	/* Address sizes leaf */
+	movl	$0x80000008, %eax	/* Address sizes leaf */
 	cpuid
 	sub	$32, %al
 	movzx	%al, %eax

+ 2 - 2
arch/x86/lib/bios_asm.S

@@ -22,8 +22,8 @@
 	.globl __idt_handler
 __idt_handler:
 	pushal
-	movb 	$0, %al /* This instruction gets modified */
-	ljmp 	$0, $__interrupt_handler_16bit
+	movb	$0, %al /* This instruction gets modified */
+	ljmp	$0, $__interrupt_handler_16bit
 	.globl __idt_handler_size
 __idt_handler_size:
 	.long  . - __idt_handler

+ 22 - 22
arch/xtensa/include/asm/arch-dc233c/core.h

@@ -263,28 +263,28 @@
 						   EXCSAVE/EPS/EPC_n, RFI n) */
 
 /*  Type of each interrupt:  */
-#define XCHAL_INT0_TYPE 	XTHAL_INTTYPE_EXTERN_LEVEL
-#define XCHAL_INT1_TYPE 	XTHAL_INTTYPE_EXTERN_LEVEL
-#define XCHAL_INT2_TYPE 	XTHAL_INTTYPE_EXTERN_LEVEL
-#define XCHAL_INT3_TYPE 	XTHAL_INTTYPE_EXTERN_LEVEL
-#define XCHAL_INT4_TYPE 	XTHAL_INTTYPE_EXTERN_LEVEL
-#define XCHAL_INT5_TYPE 	XTHAL_INTTYPE_EXTERN_LEVEL
-#define XCHAL_INT6_TYPE 	XTHAL_INTTYPE_TIMER
-#define XCHAL_INT7_TYPE 	XTHAL_INTTYPE_SOFTWARE
-#define XCHAL_INT8_TYPE 	XTHAL_INTTYPE_EXTERN_LEVEL
-#define XCHAL_INT9_TYPE 	XTHAL_INTTYPE_EXTERN_LEVEL
-#define XCHAL_INT10_TYPE 	XTHAL_INTTYPE_TIMER
-#define XCHAL_INT11_TYPE 	XTHAL_INTTYPE_SOFTWARE
-#define XCHAL_INT12_TYPE 	XTHAL_INTTYPE_EXTERN_LEVEL
-#define XCHAL_INT13_TYPE 	XTHAL_INTTYPE_TIMER
-#define XCHAL_INT14_TYPE 	XTHAL_INTTYPE_NMI
-#define XCHAL_INT15_TYPE 	XTHAL_INTTYPE_EXTERN_EDGE
-#define XCHAL_INT16_TYPE 	XTHAL_INTTYPE_EXTERN_EDGE
-#define XCHAL_INT17_TYPE 	XTHAL_INTTYPE_EXTERN_EDGE
-#define XCHAL_INT18_TYPE 	XTHAL_INTTYPE_EXTERN_EDGE
-#define XCHAL_INT19_TYPE 	XTHAL_INTTYPE_EXTERN_EDGE
-#define XCHAL_INT20_TYPE 	XTHAL_INTTYPE_EXTERN_EDGE
-#define XCHAL_INT21_TYPE 	XTHAL_INTTYPE_EXTERN_EDGE
+#define XCHAL_INT0_TYPE		XTHAL_INTTYPE_EXTERN_LEVEL
+#define XCHAL_INT1_TYPE		XTHAL_INTTYPE_EXTERN_LEVEL
+#define XCHAL_INT2_TYPE		XTHAL_INTTYPE_EXTERN_LEVEL
+#define XCHAL_INT3_TYPE		XTHAL_INTTYPE_EXTERN_LEVEL
+#define XCHAL_INT4_TYPE		XTHAL_INTTYPE_EXTERN_LEVEL
+#define XCHAL_INT5_TYPE		XTHAL_INTTYPE_EXTERN_LEVEL
+#define XCHAL_INT6_TYPE		XTHAL_INTTYPE_TIMER
+#define XCHAL_INT7_TYPE		XTHAL_INTTYPE_SOFTWARE
+#define XCHAL_INT8_TYPE		XTHAL_INTTYPE_EXTERN_LEVEL
+#define XCHAL_INT9_TYPE		XTHAL_INTTYPE_EXTERN_LEVEL
+#define XCHAL_INT10_TYPE	XTHAL_INTTYPE_TIMER
+#define XCHAL_INT11_TYPE	XTHAL_INTTYPE_SOFTWARE
+#define XCHAL_INT12_TYPE	XTHAL_INTTYPE_EXTERN_LEVEL
+#define XCHAL_INT13_TYPE	XTHAL_INTTYPE_TIMER
+#define XCHAL_INT14_TYPE	XTHAL_INTTYPE_NMI
+#define XCHAL_INT15_TYPE	XTHAL_INTTYPE_EXTERN_EDGE
+#define XCHAL_INT16_TYPE	XTHAL_INTTYPE_EXTERN_EDGE
+#define XCHAL_INT17_TYPE	XTHAL_INTTYPE_EXTERN_EDGE
+#define XCHAL_INT18_TYPE	XTHAL_INTTYPE_EXTERN_EDGE
+#define XCHAL_INT19_TYPE	XTHAL_INTTYPE_EXTERN_EDGE
+#define XCHAL_INT20_TYPE	XTHAL_INTTYPE_EXTERN_EDGE
+#define XCHAL_INT21_TYPE	XTHAL_INTTYPE_EXTERN_EDGE
 
 /*  Masks of interrupts for each type of interrupt:  */
 #define XCHAL_INTTYPE_MASK_UNCONFIGURED	0xFFC00000

+ 26 - 26
arch/xtensa/include/asm/arch-de212/core.h

@@ -108,8 +108,8 @@
 #define XCHAL_HAVE_DFP_ACCEL		0	/* double precision FP acceleration pkg */
 #define XCHAL_HAVE_DFP_accel		XCHAL_HAVE_DFP_ACCEL				/* for backward compatibility */
 
-#define XCHAL_HAVE_DFPU_SINGLE_ONLY    0                 	/* DFPU Coprocessor, single precision only */
-#define XCHAL_HAVE_DFPU_SINGLE_DOUBLE  0               	/* DFPU Coprocessor, single and double precision */
+#define XCHAL_HAVE_DFPU_SINGLE_ONLY	0	/* DFPU Coprocessor, single precision only */
+#define XCHAL_HAVE_DFPU_SINGLE_DOUBLE	0	/* DFPU Coprocessor, single and double precision */
 #define XCHAL_HAVE_VECTRA1		0	/* Vectra I  pkg */
 #define XCHAL_HAVE_VECTRALX		0	/* Vectra LX pkg */
 #define XCHAL_HAVE_PDX4		        0	/* PDX4 */
@@ -127,8 +127,8 @@
 #define XCHAL_HAVE_TURBO16		0	/* ConnX Turbo16 pkg */
 #define XCHAL_HAVE_BBP16		0	/* ConnX BBP16 pkg */
 #define XCHAL_HAVE_FLIX3		0	/* basic 3-way FLIX option */
-#define XCHAL_HAVE_GRIVPEP              0   /*  GRIVPEP is General Release of IVPEP */
-#define XCHAL_HAVE_GRIVPEP_HISTOGRAM    0   /* Histogram option on GRIVPEP */
+#define XCHAL_HAVE_GRIVPEP              0	/*  GRIVPEP is General Release of IVPEP */
+#define XCHAL_HAVE_GRIVPEP_HISTOGRAM    0	/* Histogram option on GRIVPEP */
 
 
 /*----------------------------------------------------------------------
@@ -348,28 +348,28 @@
 						   EXCSAVE/EPS/EPC_n, RFI n) */
 
 /*  Type of each interrupt:  */
-#define XCHAL_INT0_TYPE 	XTHAL_INTTYPE_EXTERN_LEVEL
-#define XCHAL_INT1_TYPE 	XTHAL_INTTYPE_EXTERN_LEVEL
-#define XCHAL_INT2_TYPE 	XTHAL_INTTYPE_EXTERN_LEVEL
-#define XCHAL_INT3_TYPE 	XTHAL_INTTYPE_EXTERN_LEVEL
-#define XCHAL_INT4_TYPE 	XTHAL_INTTYPE_EXTERN_LEVEL
-#define XCHAL_INT5_TYPE 	XTHAL_INTTYPE_EXTERN_LEVEL
-#define XCHAL_INT6_TYPE 	XTHAL_INTTYPE_TIMER
-#define XCHAL_INT7_TYPE 	XTHAL_INTTYPE_SOFTWARE
-#define XCHAL_INT8_TYPE 	XTHAL_INTTYPE_EXTERN_LEVEL
-#define XCHAL_INT9_TYPE 	XTHAL_INTTYPE_EXTERN_LEVEL
-#define XCHAL_INT10_TYPE 	XTHAL_INTTYPE_TIMER
-#define XCHAL_INT11_TYPE 	XTHAL_INTTYPE_SOFTWARE
-#define XCHAL_INT12_TYPE 	XTHAL_INTTYPE_EXTERN_LEVEL
-#define XCHAL_INT13_TYPE 	XTHAL_INTTYPE_TIMER
-#define XCHAL_INT14_TYPE 	XTHAL_INTTYPE_NMI
-#define XCHAL_INT15_TYPE 	XTHAL_INTTYPE_EXTERN_EDGE
-#define XCHAL_INT16_TYPE 	XTHAL_INTTYPE_EXTERN_EDGE
-#define XCHAL_INT17_TYPE 	XTHAL_INTTYPE_EXTERN_EDGE
-#define XCHAL_INT18_TYPE 	XTHAL_INTTYPE_EXTERN_EDGE
-#define XCHAL_INT19_TYPE 	XTHAL_INTTYPE_EXTERN_EDGE
-#define XCHAL_INT20_TYPE 	XTHAL_INTTYPE_EXTERN_EDGE
-#define XCHAL_INT21_TYPE 	XTHAL_INTTYPE_EXTERN_EDGE
+#define XCHAL_INT0_TYPE		XTHAL_INTTYPE_EXTERN_LEVEL
+#define XCHAL_INT1_TYPE		XTHAL_INTTYPE_EXTERN_LEVEL
+#define XCHAL_INT2_TYPE		XTHAL_INTTYPE_EXTERN_LEVEL
+#define XCHAL_INT3_TYPE		XTHAL_INTTYPE_EXTERN_LEVEL
+#define XCHAL_INT4_TYPE		XTHAL_INTTYPE_EXTERN_LEVEL
+#define XCHAL_INT5_TYPE		XTHAL_INTTYPE_EXTERN_LEVEL
+#define XCHAL_INT6_TYPE		XTHAL_INTTYPE_TIMER
+#define XCHAL_INT7_TYPE		XTHAL_INTTYPE_SOFTWARE
+#define XCHAL_INT8_TYPE		XTHAL_INTTYPE_EXTERN_LEVEL
+#define XCHAL_INT9_TYPE		XTHAL_INTTYPE_EXTERN_LEVEL
+#define XCHAL_INT10_TYPE	XTHAL_INTTYPE_TIMER
+#define XCHAL_INT11_TYPE	XTHAL_INTTYPE_SOFTWARE
+#define XCHAL_INT12_TYPE	XTHAL_INTTYPE_EXTERN_LEVEL
+#define XCHAL_INT13_TYPE	XTHAL_INTTYPE_TIMER
+#define XCHAL_INT14_TYPE	XTHAL_INTTYPE_NMI
+#define XCHAL_INT15_TYPE	XTHAL_INTTYPE_EXTERN_EDGE
+#define XCHAL_INT16_TYPE	XTHAL_INTTYPE_EXTERN_EDGE
+#define XCHAL_INT17_TYPE	XTHAL_INTTYPE_EXTERN_EDGE
+#define XCHAL_INT18_TYPE	XTHAL_INTTYPE_EXTERN_EDGE
+#define XCHAL_INT19_TYPE	XTHAL_INTTYPE_EXTERN_EDGE
+#define XCHAL_INT20_TYPE	XTHAL_INTTYPE_EXTERN_EDGE
+#define XCHAL_INT21_TYPE	XTHAL_INTTYPE_EXTERN_EDGE
 
 /*  Masks of interrupts for each type of interrupt:  */
 #define XCHAL_INTTYPE_MASK_UNCONFIGURED	0xFFC00000

+ 1 - 1
arch/xtensa/lib/Makefile

@@ -5,4 +5,4 @@
 
 obj-$(CONFIG_CMD_BOOTM) += bootm.o
 
-obj-y 	+= cache.o misc.o relocate.o time.o
+obj-y	+= cache.o misc.o relocate.o time.o

+ 1 - 1
board/Marvell/guruplug/guruplug.c

@@ -77,7 +77,7 @@ int board_early_init_f(void)
 		MPP43_GPIO,
 		MPP44_GPIO,
 		MPP45_GPIO,
-		MPP46_GPIO, 	/* M_RLED */
+		MPP46_GPIO,	/* M_RLED */
 		MPP47_GPIO,	/* M_GLED */
 		MPP48_GPIO,	/* B_RLED */
 		MPP49_GPIO,	/* B_GLED */

+ 1 - 1
board/boundary/nitrogen6x/README

@@ -74,7 +74,7 @@ board configurations is shown in the boards.cfg file:
 	nitrogen6q		i.MX6Q/6D	1GB
 	nitrogen6dl		i.MX6DL		1GB
 	nitrogen6s		i.MX6S		512MB
-	nitrogen6q2g    	i.MX6Q/6D	2GB
+	nitrogen6q2g		i.MX6Q/6D	2GB
 	nitrogen6dl2g		i.MX6DL		2GB
 	nitrogen6s1g		i.MX6S		1GB
 

+ 2 - 2
board/freescale/ls1012afrdm/README

@@ -52,7 +52,7 @@ QSPI flash map
 Images		| Size	|QSPI Flash Address
 ------------------------------------------
 RCW + PBI	| 1MB	| 0x4000_0000
-U-boot 		| 1MB	| 0x4010_0000
-U-boot Env 	| 1MB	| 0x4020_0000
+U-boot		| 1MB	| 0x4010_0000
+U-boot Env	| 1MB	| 0x4020_0000
 PPA FIT image	| 2MB	| 0x4050_0000
 Linux ITB	| ~53MB | 0x40A0_0000

+ 2 - 2
board/freescale/ls1012aqds/README

@@ -53,7 +53,7 @@ QSPI flash map
 Images		| Size	|QSPI Flash Address
 ------------------------------------------
 RCW + PBI	| 1MB	| 0x4000_0000
-U-boot 		| 1MB	| 0x4010_0000
-U-boot Env 	| 1MB	| 0x4020_0000
+U-boot		| 1MB	| 0x4010_0000
+U-boot Env	| 1MB	| 0x4020_0000
 PPA FIT image	| 2MB	| 0x4050_0000
 Linux ITB	| ~53MB | 0x40A0_0000

+ 4 - 4
board/freescale/ls1012ardb/README

@@ -48,8 +48,8 @@ QSPI flash map
 Images		| Size	|QSPI Flash Address
 ------------------------------------------
 RCW + PBI	| 1MB	| 0x4000_0000
-U-boot 		| 1MB	| 0x4010_0000
-U-boot Env 	| 1MB	| 0x4020_0000
+U-boot		| 1MB	| 0x4010_0000
+U-boot Env	| 1MB	| 0x4020_0000
 PPA FIT image	| 2MB	| 0x4050_0000
 Linux ITB	| ~53MB | 0x40A0_0000
 
@@ -90,8 +90,8 @@ QSPI flash map
 Images		| Size	|QSPI Flash Address
 ------------------------------------------
 RCW + PBI	| 1MB	| 0x4000_0000
-U-boot 		| 1MB	| 0x4010_0000
-U-boot Env 	| 1MB	| 0x4030_0000
+U-boot		| 1MB	| 0x4010_0000
+U-boot Env	| 1MB	| 0x4030_0000
 PPA FIT image	| 2MB	| 0x4040_0000
 PFE firmware	| 20K	| 0x00a0_0000
 Linux ITB	| ~53MB | 0x4100_0000

+ 2 - 2
board/freescale/ls1046afrwy/README

@@ -42,8 +42,8 @@ Memory map from core's view
 Start Address	 End Address	 Description		Size
 0x00_0000_0000 - 0x00_000F_FFFF  Secure Boot ROM	1MB
 0x00_0100_0000 - 0x00_0FFF_FFFF  CCSRBAR		240MB
-0x00_1000_0000 - 0x00_1000_FFFF  OCRAM0 		64KB
-0x00_1001_0000 - 0x00_1001_FFFF  OCRAM1 		64KB
+0x00_1000_0000 - 0x00_1000_FFFF  OCRAM0			64KB
+0x00_1001_0000 - 0x00_1001_FFFF  OCRAM1			64KB
 0x00_2000_0000 - 0x00_20FF_FFFF  DCSR			16MB
 0x00_7E80_0000 - 0x00_7E80_FFFF  IFC - NAND Flash	64KB
 0x00_7FB0_0000 - 0x00_7FB0_0FFF  IFC - CPLD		4KB

+ 2 - 2
board/freescale/ls1046aqds/README

@@ -47,8 +47,8 @@ Memory map from core's view
 Start Address    End Address     Description		Size
 0x00_0000_0000 - 0x00_000F_FFFF  Secure Boot ROM	1MB
 0x00_0100_0000 - 0x00_0FFF_FFFF  CCSRBAR		240MB
-0x00_1000_0000 - 0x00_1000_FFFF  OCRAM0 		64KB
-0x00_1001_0000 - 0x00_1001_FFFF  OCRAM1 		64KB
+0x00_1000_0000 - 0x00_1000_FFFF  OCRAM0			64KB
+0x00_1001_0000 - 0x00_1001_FFFF  OCRAM1			64KB
 0x00_2000_0000 - 0x00_20FF_FFFF  DCSR			16MB
 0x00_6000_0000 - 0x00_67FF_FFFF  IFC - NOR Flash	128MB
 0x00_7E80_0000 - 0x00_7E80_FFFF  IFC - NAND Flash	64KB

+ 3 - 3
board/freescale/ls1046ardb/README

@@ -43,8 +43,8 @@ Memory map from core's view
 Start Address	 End Address	 Description		Size
 0x00_0000_0000 - 0x00_000F_FFFF  Secure Boot ROM	1MB
 0x00_0100_0000 - 0x00_0FFF_FFFF  CCSRBAR		240MB
-0x00_1000_0000 - 0x00_1000_FFFF  OCRAM0 		64KB
-0x00_1001_0000 - 0x00_1001_FFFF  OCRAM1 		64KB
+0x00_1000_0000 - 0x00_1000_FFFF  OCRAM0			64KB
+0x00_1001_0000 - 0x00_1001_FFFF  OCRAM1			64KB
 0x00_2000_0000 - 0x00_20FF_FFFF  DCSR			16MB
 0x00_7E80_0000 - 0x00_7E80_FFFF  IFC - NAND Flash	64KB
 0x00_7FB0_0000 - 0x00_7FB0_0FFF  IFC - CPLD		4KB
@@ -59,7 +59,7 @@ Start Address	 End Address	 Description		Size
 QSPI flash map:
 Start Address    End Address     Description		Size
 0x00_4000_0000 - 0x00_400F_FFFF  RCW + PBI		1MB
-0x00_4010_0000 - 0x00_402F_FFFF  U-Boot 		2MB
+0x00_4010_0000 - 0x00_402F_FFFF  U-Boot			2MB
 0x00_4030_0000 - 0x00_403F_FFFF  U-Boot Env		1MB
 0x00_4040_0000 - 0x00_405F_FFFF  PPA			2MB
 0x00_4060_0000 - 0x00_408F_FFFF  Secure boot header

+ 1 - 1
board/freescale/m53017evb/README

@@ -98,7 +98,7 @@ CONFIG_SYS_IMMR			-- define for MBAR offset
 
 CONFIG_SYS_MBAR			-- define MBAR offset
 
-CONFIG_MONITOR_IS_IN_RAM 	-- Not support
+CONFIG_MONITOR_IS_IN_RAM	-- Not support
 
 CONFIG_SYS_INIT_RAM_ADDR	-- defines the base address of the MCF5301x internal SRAM
 

+ 1 - 1
board/logicpd/am3517evm/am3517evm.h

@@ -314,7 +314,7 @@ const omap3_sysinfo sysinfo = {
 	MUX_VAL(CP(SYS_CLKREQ),		(IEN  | PTD | DIS | M0)) \
 	MUX_VAL(CP(SYS_NIRQ),		(IEN  | PTU | EN  | M0)) \
 	/*SYS_nRESWARM */\
-	MUX_VAL(CP(SYS_NRESWARM),     	(IDIS | PTU | EN | M4)) \
+	MUX_VAL(CP(SYS_NRESWARM),	(IDIS | PTU | EN | M4)) \
 							/* - GPIO30 */\
 	MUX_VAL(CP(SYS_BOOT0),		(IEN  | PTD | DIS | M4)) /*GPIO_2*/\
 							 /* - PEN_IRQ */\

+ 1 - 1
board/logicpd/omap3som/omap3logic.h

@@ -243,7 +243,7 @@ void set_muxconf_regs(void)
 	MUX_VAL(CP(MCSPI2_SOMI),	(IEN  | PTD | DIS | M0));	/*HSUSB2_DATA5*/
 	MUX_VAL(CP(MCSPI2_CS0),		(IEN  | PTD | EN  | M0));	/*HSUSB2_DATA6*/
 	MUX_VAL(CP(MCSPI2_CLK),		(IEN  | PTD | DIS | M0));	/*HSUSB2_DATA7*/
-	MUX_VAL(CP(SYS_BOOT2),      (IEN  | PTD | DIS | M4)) 	/* GPIO_4 */
+	MUX_VAL(CP(SYS_BOOT2),		(IEN  | PTD | DIS | M4))	/* GPIO_4 */
 	MUX_VAL(CP(ETK_D10_ES2),	(IDIS | PTU | DIS | M3));	/*HSUSB2_CLK*/
 	MUX_VAL(CP(ETK_D11_ES2),	(IDIS | PTU | DIS | M3));	/*HSUSB2_STP*/
 	MUX_VAL(CP(ETK_D12_ES2),	(IEN  | PTU | DIS | M3));	/*HSUSB2_DIR*/

+ 1 - 1
board/sysam/stmark2/sbf_dram_init.S

@@ -5,7 +5,7 @@
  * (C) Copyright 2017 Angelo Dureghello <angelo@sysam.it>
  */
 
-.equ	PPMCR0, 	0xfc04002d
+.equ	PPMCR0,		0xfc04002d
 .equ	MSCR_SDRAMC,	0xec094060
 .equ	MISCCR2,	0xec09001a
 .equ	DDR_RCR,	0xfc0b8180

+ 12 - 12
board/ti/am57xx/board.c

@@ -144,13 +144,13 @@ static const struct emif_regs beagle_x15_emif1_ddr3_532mhz_emif_regs = {
 	.read_idle_ctrl			= 0x00050000,
 	.zq_config			= 0x5007190b,
 	.temp_alert_config		= 0x00000000,
-	.emif_ddr_phy_ctlr_1_init 	= 0x0024400b,
+	.emif_ddr_phy_ctlr_1_init	= 0x0024400b,
 	.emif_ddr_phy_ctlr_1		= 0x0e24400b,
-	.emif_ddr_ext_phy_ctrl_1 	= 0x10040100,
-	.emif_ddr_ext_phy_ctrl_2 	= 0x00910091,
-	.emif_ddr_ext_phy_ctrl_3 	= 0x00950095,
-	.emif_ddr_ext_phy_ctrl_4 	= 0x009b009b,
-	.emif_ddr_ext_phy_ctrl_5 	= 0x009e009e,
+	.emif_ddr_ext_phy_ctrl_1	= 0x10040100,
+	.emif_ddr_ext_phy_ctrl_2	= 0x00910091,
+	.emif_ddr_ext_phy_ctrl_3	= 0x00950095,
+	.emif_ddr_ext_phy_ctrl_4	= 0x009b009b,
+	.emif_ddr_ext_phy_ctrl_5	= 0x009e009e,
 	.emif_rd_wr_lvl_rmp_win		= 0x00000000,
 	.emif_rd_wr_lvl_rmp_ctl		= 0x80000000,
 	.emif_rd_wr_lvl_ctl		= 0x00000000,
@@ -208,13 +208,13 @@ static const struct emif_regs beagle_x15_emif2_ddr3_532mhz_emif_regs = {
 	.read_idle_ctrl			= 0x00050000,
 	.zq_config			= 0x5007190b,
 	.temp_alert_config		= 0x00000000,
-	.emif_ddr_phy_ctlr_1_init 	= 0x0024400b,
+	.emif_ddr_phy_ctlr_1_init	= 0x0024400b,
 	.emif_ddr_phy_ctlr_1		= 0x0e24400b,
-	.emif_ddr_ext_phy_ctrl_1 	= 0x10040100,
-	.emif_ddr_ext_phy_ctrl_2 	= 0x00910091,
-	.emif_ddr_ext_phy_ctrl_3 	= 0x00950095,
-	.emif_ddr_ext_phy_ctrl_4 	= 0x009b009b,
-	.emif_ddr_ext_phy_ctrl_5 	= 0x009e009e,
+	.emif_ddr_ext_phy_ctrl_1	= 0x10040100,
+	.emif_ddr_ext_phy_ctrl_2	= 0x00910091,
+	.emif_ddr_ext_phy_ctrl_3	= 0x00950095,
+	.emif_ddr_ext_phy_ctrl_4	= 0x009b009b,
+	.emif_ddr_ext_phy_ctrl_5	= 0x009e009e,
 	.emif_rd_wr_lvl_rmp_win		= 0x00000000,
 	.emif_rd_wr_lvl_rmp_ctl		= 0x80000000,
 	.emif_rd_wr_lvl_ctl		= 0x00000000,

+ 2 - 2
board/ti/am57xx/mux_data.h

@@ -539,7 +539,7 @@ const struct iodelay_cfg_entry iodelay_cfg_array_bbai[] = {
 	{0x0884, 0, 0},         /* CFG_UART2_RTSN_OUT */
 	{0x0888, 683, 0},       /* CFG_UART2_RXD_IN */
 	{0x088C, 0, 0},         /* CFG_UART2_RXD_OEN */
-	{0x0890, 0, 0},	 	/* CFG_UART2_RXD_OUT */
+	{0x0890, 0, 0},		/* CFG_UART2_RXD_OUT */
 	{0x0894, 835, 0},       /* CFG_UART2_TXD_IN */
 	{0x0898, 0, 0},         /* CFG_UART2_TXD_OEN */
 	{0x089C, 0, 0},         /* CFG_UART2_TXD_OUT */
@@ -553,7 +553,7 @@ const struct iodelay_cfg_entry iodelay_cfg_array_bbai[] = {
 	{0x0C48, 0, 404},       /* CFG_VOUT1_D22_IN */
 	{0x0C78, 0, 0},         /* CFG_VOUT1_D4_IN */
 	{0x0C84, 0, 365},       /* CFG_VOUT1_D5_IN */
-	{0x0C90, 0, 0},	 	/* CFG_VOUT1_D6_IN */
+	{0x0C90, 0, 0},		/* CFG_VOUT1_D6_IN */
 	{0x0C9C, 0, 218},       /* CFG_VOUT1_D7_IN */
 };
 

+ 1 - 1
cmd/cramfs.c

@@ -3,7 +3,7 @@
  *
  * based on: cmd_jffs2.c
  *
- * 	Add support for a CRAMFS located in RAM
+ *	Add support for a CRAMFS located in RAM
  */
 
 

+ 3 - 3
cmd/spi.c

@@ -29,9 +29,9 @@ static unsigned int	bus;
 static unsigned int	cs;
 static unsigned int	mode;
 static unsigned int	freq;
-static int   		bitlen;
-static uchar 		dout[MAX_SPI_BYTES];
-static uchar 		din[MAX_SPI_BYTES];
+static int		bitlen;
+static uchar		dout[MAX_SPI_BYTES];
+static uchar		din[MAX_SPI_BYTES];
 
 static int do_spi_xfer(int bus, int cs)
 {

+ 1 - 1
common/hash.c

@@ -228,7 +228,7 @@ static struct hash_algo hash_algo[] = {
 #endif
 #ifdef CONFIG_SHA1
 	{
-		.name 		= "sha1",
+		.name		= "sha1",
 		.digest_size	= SHA1_SUM_LEN,
 		.chunk_size	= CHUNKSZ_SHA1,
 #ifdef CONFIG_SHA_HW_ACCEL

+ 1 - 1
common/hwconfig.c

@@ -179,7 +179,7 @@ int hwconfig_arg_cmp_f(const char *opt, const char *arg, char *buf)
  *
  * This call is similar to hwconfig_f(), except that it takes additional
  * argument @subopt. In this example:
- * 	"dr_usb:mode=peripheral"
+ *	"dr_usb:mode=peripheral"
  * "dr_usb" is an option, "mode" is a sub-option, and "peripheral" is its
  * argument.
  */

+ 1 - 1
common/usb_storage.c

@@ -94,7 +94,7 @@ struct us_data {
 	int		action;			/* what to do */
 	int		ip_wanted;		/* needed */
 	int		*irq_handle;		/* for USB int requests */
-	unsigned int	irqpipe;	 	/* pipe for release_irq */
+	unsigned int	irqpipe;		/* pipe for release_irq */
 	unsigned char	irqmaxp;		/* max packed for irq Pipe */
 	unsigned char	irqinterval;		/* Intervall for IRQ Pipe */
 	struct scsi_cmd	*srb;			/* current srb */

+ 1 - 1
disk/Makefile

@@ -5,7 +5,7 @@
 
 #ccflags-y += -DET_DEBUG -DDEBUG
 
-obj-$(CONFIG_PARTITIONS) 	+= part.o
+obj-$(CONFIG_PARTITIONS)	+= part.o
 obj-$(CONFIG_$(SPL_)MAC_PARTITION)   += part_mac.o
 obj-$(CONFIG_$(SPL_)DOS_PARTITION)   += part_dos.o
 obj-$(CONFIG_$(SPL_)ISO_PARTITION)   += part_iso.o

+ 3 - 3
doc/README.commands.spl

@@ -17,14 +17,14 @@ TYPICAL CALL
 
 on OMAP3:
 nandecc hw
-nand read 0x82000000 0x280000 0x400000 	/* Read kernel image from NAND*/
-spl export atags 			/* export ATAGS */
+nand read 0x82000000 0x280000 0x400000	/* Read kernel image from NAND*/
+spl export atags			/* export ATAGS */
 nand erase 0x680000 0x20000		/* erase - one page */
 nand write 0x80000100 0x680000 0x20000	/* write the image - one page */
 
 call with FDT:
 nandecc hw
-nand read 0x82000000 0x280000 0x400000 	/* Read kernel image from NAND*/
+nand read 0x82000000 0x280000 0x400000	/* Read kernel image from NAND*/
 tftpboot 0x80000100 devkit8000.dtb /* Read fdt */
 spl export fdt 0x82000000 - 0x80000100	/* export FDT */
 nand erase 0x680000 0x20000		/* erase - one page */

+ 2 - 2
doc/README.falcon

@@ -69,7 +69,7 @@ CONFIG_CMD_SPL_NAND_OFS	Offset in NAND where the parameters area was saved.
 
 CONFIG_CMD_SPL_NOR_OFS	Offset in NOR where the parameters area was saved.
 
-CONFIG_CMD_SPL_WRITE_SIZE 	Size of the parameters area to be copied
+CONFIG_CMD_SPL_WRITE_SIZE	Size of the parameters area to be copied
 
 CONFIG_SPL_OS_BOOT	Activate Falcon Mode.
 
@@ -89,7 +89,7 @@ Environment variables
 A board may chose to look at the environment for decisions about falcon
 mode.  In this case the following variables may be supported:
 
-boot_os : 		Set to yes/Yes/true/True/1 to enable booting to OS,
+boot_os :		Set to yes/Yes/true/True/1 to enable booting to OS,
 			any other value to fall back to U-Boot (including
 			unset)
 falcon_args_file :	Filename to load as the 'args' portion of falcon mode

+ 2 - 2
doc/README.odroid

@@ -296,8 +296,8 @@ Odroid # usb part 0
 Partition Map for USB device 0  --   Partition Type: DOS
 
 Part	Start Sector	Num Sectors	UUID		Type
-  1	3072      	263168    	000c4046-01	06
-  2	266240    	13457408  	000c4046-02	83
+  1	3072		263168		000c4046-01	06
+  2	266240		13457408	000c4046-02	83
 
 Odroid # ls usb 0:2 /boot
 <DIR>       4096 .

+ 1 - 1
doc/device-tree-bindings/mailbox/k3-secure-proxy.txt

@@ -10,7 +10,7 @@ Secure Proxy Device Node:
 Required properties:
 --------------------
 - compatible:		Shall be: "ti,am654-secure-proxy"
-- reg-names 		data - Map the data region
+- reg-names		data - Map the data region
 			scfg - Map the secure configuration region
 			rt - Map the Realtime region.
 - reg:			Contains the register map per reg-names.

+ 1 - 1
doc/device-tree-bindings/memory-controller/k3-j721e-ddrss.txt

@@ -11,7 +11,7 @@ Required properties:
 --------------------
 - compatible:		Shall be: "ti,j721e-ddrss" for j721e, j7200
 				  "ti,am64-ddrss" for am642
-- reg-names 		cfg - Map the controller configuration region
+- reg-names		cfg - Map the controller configuration region
 			ctrl_mmr_lp4 - Map LP4 register region in ctrl mmr
 - reg:			Contains the register map per reg-names.
 - power-domains:	Should contain two entries:

+ 1 - 1
doc/device-tree-bindings/memory-controllers/k3-am654-ddrss.txt

@@ -14,7 +14,7 @@ DDRSS device node:
 Required properties:
 --------------------
 - compatible:		Shall be: "ti,am654-ddrss"
-- reg-names 		ss - Map the sub system wrapper logic region
+- reg-names		ss - Map the sub system wrapper logic region
 			ctl - Map the controller region
 			phy - Map the PHY region
 - reg:			Contains the register map per reg-names.

+ 1 - 1
doc/device-tree-bindings/net/altera_tse.txt

@@ -90,7 +90,7 @@ Example:
 
 	tse_sub_1_eth_tse_0: ethernet@0x1,00001000 {
 		compatible = "altr,tse-msgdma-1.0";
-		reg = 	<0x00000001 0x00001000 0x00000400>,
+		reg =	<0x00000001 0x00001000 0x00000400>,
 			<0x00000001 0x00001460 0x00000020>,
 			<0x00000001 0x00001480 0x00000020>,
 			<0x00000001 0x000014A0 0x00000008>,

+ 1 - 1
doc/device-tree-bindings/net/fsl,mcf-dma-fec.txt

@@ -21,7 +21,7 @@ Example:
 
 fec0: ethernet@9000 {
 	compatible = "fsl,mcf-dma-fec";
- 	reg = <0x9000 0x800>;
+	reg = <0x9000 0x800>;
 	mii-base = <0>;
 	phy-addr = <0>;
 	timeout-loop = <5000>;

+ 1 - 1
doc/device-tree-bindings/net/fsl,mcf-fec.txt

@@ -15,7 +15,7 @@ Example:
 
 fec0: ethernet@fc030000 {
 	compatible = "fsl,mcf-fec";
- 	reg = <0xfc030000 0x400>;
+	reg = <0xfc030000 0x400>;
 	mii-base = <0>;
 	phy-addr = <0>;
 	timeout-loop = <5000>;

+ 1 - 1
doc/device-tree-bindings/pinctrl/bcm6838-pinctrl.txt

@@ -2,7 +2,7 @@
 
 Required properties for the pinctrl driver:
 - compatible:	   "brcm,bcm6838-pinctrl"
-- regmap: 		   specify the gpio test port syscon
+- regmap:		   specify the gpio test port syscon
 - brcm,pins-count:      the number of pin
 - brcm,functions-count: the number of function
 

+ 7 - 7
doc/device-tree-bindings/pinctrl/marvell,armada-apn806-pinctrl.txt

@@ -3,19 +3,19 @@
 ----------------------------------------------------------------------
 MPP#	0x1			0x2		0x3		0x4
 ----------------------------------------------------------------------
-0	SDIO_CLK		-		SPI0_CLK 	-
+0	SDIO_CLK		-		SPI0_CLK	-
 1	SDIO_CMD		-		SPI0_MISO	-
-2	SDIO_D[0]		-		SPI0_MOSI 	-
-3	SDIO_D[1]		-		SPI0_CS0n 	-
+2	SDIO_D[0]		-		SPI0_MOSI	-
+3	SDIO_D[1]		-		SPI0_CS0n	-
 4	SDIO_D[2]		-		I2C0_SDA	SPI0_CS1n
 5	SDIO_D[3]		-		I2C0_SCK	-
 6	SDIO_DS			-		-		-
 7	SDIO_D[4]		-		UART1_RXD	-
-8	SDIO_D[5]		-		UART1_TXD 	-
-9	SDIO_D[6]		-		SPI0_CS1n 	-
+8	SDIO_D[5]		-		UART1_TXD	-
+9	SDIO_D[6]		-		SPI0_CS1n	-
 10	SDIO_D[7]		-		-		-
-11	-			-		UART0_TXD 	-
-12	SDIO_CARD_PW_OFF 	SDIO_HW_RST 	-		-
+11	-			-		UART0_TXD	-
+12	SDIO_CARD_PW_OFF	SDIO_HW_RST	-		-
 13	-			-		-		-
 14	-			-		-		-
 15	-			-		-		-

+ 1 - 1
doc/device-tree-bindings/pinctrl/marvell,mvebu-pinctrl.txt

@@ -11,7 +11,7 @@ Required properties for the pinctrl driver:
 		"marvell,armada-8k-cpm-pinctrl",
 		"marvell,armada-8k-cps-pinctrl"
 - bank-name:	A string defining the pinc controller bank name
-- reg: 		A pair of values defining the pin controller base address
+- reg:		A pair of values defining the pin controller base address
 		and the address space
 - pin-count:	Numeric value defining the amount of multi purpose pins
 		included in this bank

+ 7 - 7
doc/device-tree-bindings/regulator/fsl,anatop-regulator.txt

@@ -8,21 +8,21 @@ Required properties:
 - anatop-reg-offset:	u32 value representing the anatop MFD register offset.
 - anatop-vol-bit-shift:	u32 value representing the bit shift for the register.
 - anatop-vol-bit-width:	u32 value representing the number of bits used in the
-  			register.
+			register.
 - anatop-min-bit-val:	u32 value representing the minimum value of this
-  			register.
+			register.
 - anatop-min-voltage:	u32 value representing the minimum voltage of this
-  			regulator.
+			regulator.
 - anatop-max-voltage:	u32 value representing the maximum voltage of this
-  			regulator.
+			regulator.
 
 Optional properties:
 - anatop-delay-reg-offset: u32 value representing the anatop MFD step time
-  			   register offset.
+			   register offset.
 - anatop-delay-bit-shift: u32 value representing the bit shift for the step
-  			  time register.
+			  time register.
 - anatop-delay-bit-width: u32 value representing the number of bits used in
-  			  the step time register.
+			  the step time register.
 - anatop-enable-bit:	  u32 value representing regulator enable bit offset.
 - vin-supply:		  input supply phandle.
 

+ 7 - 7
doc/device-tree-bindings/spi/spi-bus.txt

@@ -8,10 +8,10 @@ in slave mode.
 
 The SPI master node requires the following properties:
 - #address-cells  - number of cells required to define a chip select
-    		address on the SPI bus.
+		address on the SPI bus.
 - #size-cells     - should be zero.
 - compatible      - name of SPI bus controller following generic names
-    		recommended practice.
+		recommended practice.
 - cs-gpios	  - (optional) gpios chip select.
 No other properties are required in the SPI bus node.  It is assumed
 that a driver for an SPI bus device will understand that it is an SPI bus.
@@ -45,16 +45,16 @@ SPI slave nodes must be children of the SPI master node and can
 contain the following properties.
 - reg             - (required) chip select address of device.
 - compatible      - (required) name of SPI device following generic names
-    		recommended practice
+		recommended practice
 - spi-max-frequency - (required) Maximum SPI clocking speed of device in Hz
 - spi-cpol        - (optional) Empty property indicating device requires
-    		inverse clock polarity (CPOL) mode
+		inverse clock polarity (CPOL) mode
 - spi-cpha        - (optional) Empty property indicating device requires
-    		shifted clock phase (CPHA) mode
+		shifted clock phase (CPHA) mode
 - spi-cs-high     - (optional) Empty property indicating device requires
-    		chip select active high
+		chip select active high
 - spi-3wire       - (optional) Empty property indicating device requires
-    		    3-wire mode.
+		    3-wire mode.
 - spi-tx-bus-width - (optional) The bus width(number of data wires) that
                       used for MOSI. Defaults to 1 if not present.
 - spi-rx-bus-width - (optional) The bus width(number of data wires) that

+ 1 - 1
doc/device-tree-bindings/spi/spi-qup.txt

@@ -7,7 +7,7 @@ Required properties:
 - reg : Physical base address and size of SPI registers map.
 - clock	: Clock phandle (see clock bindings for details).
 - #address-cells : Number of cells required to define a chip select
-                	address on the SPI bus. Should be set to 1.
+			address on the SPI bus. Should be set to 1.
 - #size-cells : Should be zero.
 - pinctrl-names : Must be "default"
 - pinctrl-n : At least one pinctrl phandle

+ 1 - 1
doc/device-tree-bindings/tpm2/sandbox.txt

@@ -7,5 +7,5 @@ Required properties:
 Example:
 
 	tpm {
- 		compatible = "sandbox,tpm2";
+		compatible = "sandbox,tpm2";
 	};

+ 2 - 2
drivers/cache/cache-v5l2.c

@@ -68,8 +68,8 @@ struct v5l2_plat {
 	struct l2cache	*regs;
 	u32		iprefetch;
 	u32		dprefetch;
-	u32 		tram_ctl[2];
-	u32 		dram_ctl[2];
+	u32		tram_ctl[2];
+	u32		dram_ctl[2];
 };
 
 static int v5l2_enable(struct udevice *dev)

+ 1 - 1
drivers/cache/sandbox_cache.c

@@ -31,7 +31,7 @@ static int snadbox_disable(struct udevice *dev)
 
 static const struct cache_ops sandbox_cache_ops = {
 	.get_info	= sandbox_get_info,
-	.enable 	= sandbox_enable,
+	.enable		= sandbox_enable,
 	.disable	= snadbox_disable,
 };
 

+ 1 - 1
drivers/clk/imx/clk-pllv3.c

@@ -160,7 +160,7 @@ static ulong clk_pllv3_sys_set_rate(struct clk *clk, ulong rate)
 }
 
 static const struct clk_ops clk_pllv3_sys_ops = {
-	.enable 	= clk_pllv3_generic_enable,
+	.enable		= clk_pllv3_generic_enable,
 	.disable	= clk_pllv3_generic_disable,
 	.get_rate	= clk_pllv3_sys_get_rate,
 	.set_rate	= clk_pllv3_sys_set_rate,

+ 1 - 1
drivers/crypto/Makefile

@@ -1,7 +1,7 @@
 # SPDX-License-Identifier: GPL-2.0+
 #
 # Copyright (c) 2013 Samsung Electronics Co., Ltd.
-# 	http://www.samsung.com
+#	http://www.samsung.com
 
 obj-$(CONFIG_EXYNOS_ACE_SHA)	+= ace_sha.o
 obj-y += rsa_mod_exp/

+ 9 - 9
drivers/ddr/fsl/ddr3_dimm_params.c

@@ -36,18 +36,18 @@
  *	0110		16Gb		2GB
  *
  * SPD byte8 - module memory bus width
- * 	bit[2:0]	primary bus width
+ *	bit[2:0]	primary bus width
  *	000		8bits
- * 	001		16bits
- * 	010		32bits
- * 	011		64bits
+ *	001		16bits
+ *	010		32bits
+ *	011		64bits
  *
  * SPD byte7 - module organiztion
- * 	bit[2:0]	sdram device width
- * 	000		4bits
- * 	001		8bits
- * 	010		16bits
- * 	011		32bits
+ *	bit[2:0]	sdram device width
+ *	000		4bits
+ *	001		8bits
+ *	010		16bits
+ *	011		32bits
  *
  */
 static unsigned long long

+ 1 - 1
drivers/ddr/marvell/axp/ddr3_spd.c

@@ -46,7 +46,7 @@
 #define SPD_COL_NUM_MASK		(7 << SPD_COL_NUM_OFF)
 
 #define SPD_MODULE_ORG_BYTE		7
-#define SPD_MODULE_SDRAM_DEV_WIDTH_OFF 	0
+#define SPD_MODULE_SDRAM_DEV_WIDTH_OFF	0
 #define SPD_MODULE_SDRAM_DEV_WIDTH_MASK	(7 << SPD_MODULE_SDRAM_DEV_WIDTH_OFF)
 #define SPD_MODULE_BANK_NUM_MIN		1
 #define SPD_MODULE_BANK_NUM_OFF		3

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