lowlevel_init.S 3.3 KB

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  1. /* SPDX-License-Identifier: GPL-2.0+ */
  2. /*
  3. * Copyright (C) 2011 Andes Technology Corporation
  4. * Shawn Lin, Andes Technology Corporation <nobuhiro@andestech.com>
  5. * Macpaul Lin, Andes Technology Corporation <macpaul@andestech.com>
  6. */
  7. .pic
  8. .text
  9. #include <common.h>
  10. #include <config.h>
  11. #include <asm/macro.h>
  12. #include <generated/asm-offsets.h>
  13. /*
  14. * parameters for the SDRAM controller
  15. */
  16. #define SDMC_TP1_A (CONFIG_FTSDMC021_BASE + FTSDMC021_TP1)
  17. #define SDMC_TP2_A (CONFIG_FTSDMC021_BASE + FTSDMC021_TP2)
  18. #define SDMC_CR1_A (CONFIG_FTSDMC021_BASE + FTSDMC021_CR1)
  19. #define SDMC_CR2_A (CONFIG_FTSDMC021_BASE + FTSDMC021_CR2)
  20. #define SDMC_B0_BSR_A (CONFIG_FTSDMC021_BASE + FTSDMC021_BANK0_BSR)
  21. #define SDMC_B1_BSR_A (CONFIG_FTSDMC021_BASE + FTSDMC021_BANK1_BSR)
  22. #define SDMC_TP1_D CONFIG_SYS_FTSDMC021_TP1
  23. #define SDMC_TP2_D CONFIG_SYS_FTSDMC021_TP2
  24. #define SDMC_CR1_D CONFIG_SYS_FTSDMC021_CR1
  25. #define SDMC_CR2_D CONFIG_SYS_FTSDMC021_CR2
  26. #define SDMC_B0_BSR_D CONFIG_SYS_FTSDMC021_BANK0_BSR
  27. #define SDMC_B1_BSR_D CONFIG_SYS_FTSDMC021_BANK1_BSR
  28. /*
  29. * for Orca and Emerald
  30. */
  31. #define BOARD_ID_REG 0x104
  32. #define BOARD_ID_FAMILY_MASK 0xfff000
  33. #define BOARD_ID_FAMILY_V5 0x556000
  34. #define BOARD_ID_FAMILY_K7 0x74b000
  35. /*
  36. * parameters for the static memory controller
  37. */
  38. #define SMC_BANK0_CR_A (CONFIG_FTSMC020_BASE + FTSMC020_BANK0_CR)
  39. #define SMC_BANK0_TPR_A (CONFIG_FTSMC020_BASE + FTSMC020_BANK0_TPR)
  40. #define SMC_BANK0_CR_D FTSMC020_BANK0_LOWLV_CONFIG
  41. #define SMC_BANK0_TPR_D FTSMC020_BANK0_LOWLV_TIMING
  42. /*
  43. * for Orca and Emerald
  44. */
  45. #define AHBC_BSR4_A (CONFIG_FTAHBC020S_BASE + FTAHBC020S_SLAVE_BSR_4)
  46. #define AHBC_BSR6_D CONFIG_SYS_FTAHBC020S_SLAVE_BSR_6
  47. /*
  48. * parameters for the pmu controoler
  49. */
  50. #define PMU_PDLLCR0_A (CONFIG_FTPMU010_BASE + FTPMU010_PDLLCR0)
  51. /*
  52. * numeric 7 segment display
  53. */
  54. .macro led, num
  55. write32 CONFIG_DEBUG_LED, \num
  56. .endm
  57. /*
  58. * Waiting for SDRAM to set up
  59. */
  60. .macro wait_sdram
  61. li $r0, CONFIG_FTSDMC021_BASE
  62. 1:
  63. lwi $r1, [$r0+FTSDMC021_CR2]
  64. bnez $r1, 1b
  65. .endm
  66. .globl mem_init
  67. mem_init:
  68. move $r11, $lp
  69. li $r0, SMC_BANK0_CR_A
  70. lwi $r1, [$r0+#0x00]
  71. ori $r1, $r1, 0x8f0
  72. xori $r1, $r1, 0x8f0
  73. /* 16-bit mode */
  74. ori $r1, $r1, 0x60
  75. li $r2, 0x00153153
  76. swi $r1, [$r0+#0x00]
  77. swi $r2, [$r0+#0x04]
  78. move $lp, $r11
  79. ret
  80. #if !CONFIG_IS_ENABLED(SKIP_LOWLEVEL_INIT)
  81. .globl lowlevel_init
  82. lowlevel_init:
  83. move $r10, $lp
  84. jal remap
  85. #if (defined(NDS32_EXT_FPU_DP) || defined(NDS32_EXT_FPU_SP))
  86. jal enable_fpu
  87. #endif
  88. ret $r10
  89. remap:
  90. move $r11, $lp
  91. relo_base:
  92. mfusr $r0, $pc
  93. #ifdef CONFIG_MEM_REMAP
  94. li $r4, 0x00000000
  95. li $r5, 0x80000000
  96. la $r6, _end@GOTOFF
  97. 1:
  98. lmw.bim $r12, [$r5], $r19
  99. smw.bim $r12, [$r4], $r19
  100. blt $r5, $r6, 1b
  101. #endif /* #ifdef CONFIG_MEM_REMAP */
  102. move $lp, $r11
  103. 2:
  104. ret
  105. /*
  106. * enable_fpu:
  107. * Some of Andes CPU version support FPU coprocessor, if so,
  108. * and toolchain support FPU instruction set, we should enable it.
  109. */
  110. #if (defined(NDS32_EXT_FPU_DP) || defined(NDS32_EXT_FPU_SP))
  111. enable_fpu:
  112. mfsr $r0, $CPU_VER /* enable FPU if it exists */
  113. srli $r0, $r0, 3
  114. andi $r0, $r0, 1
  115. beqz $r0, 1f /* skip if no COP */
  116. mfsr $r0, $FUCOP_EXIST
  117. srli $r0, $r0, 31
  118. beqz $r0, 1f /* skip if no FPU */
  119. mfsr $r0, $FUCOP_CTL
  120. ori $r0, $r0, 1
  121. mtsr $r0, $FUCOP_CTL
  122. 1:
  123. ret
  124. #endif
  125. #endif /* #if !CONFIG_IS_ENABLED(SKIP_LOWLEVEL_INIT) */