board.c 31 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright (C) 2014 Texas Instruments Incorporated - http://www.ti.com
  4. *
  5. * Author: Felipe Balbi <balbi@ti.com>
  6. *
  7. * Based on board/ti/dra7xx/evm.c
  8. */
  9. #include <common.h>
  10. #include <env.h>
  11. #include <fastboot.h>
  12. #include <fdt_support.h>
  13. #include <image.h>
  14. #include <init.h>
  15. #include <malloc.h>
  16. #include <net.h>
  17. #include <palmas.h>
  18. #include <sata.h>
  19. #include <serial.h>
  20. #include <usb.h>
  21. #include <errno.h>
  22. #include <asm/global_data.h>
  23. #include <asm/omap_common.h>
  24. #include <asm/omap_sec_common.h>
  25. #include <asm/emif.h>
  26. #include <asm/gpio.h>
  27. #include <asm/arch/gpio.h>
  28. #include <asm/arch/clock.h>
  29. #include <asm/arch/dra7xx_iodelay.h>
  30. #include <asm/arch/sys_proto.h>
  31. #include <asm/arch/mmc_host_def.h>
  32. #include <asm/arch/sata.h>
  33. #include <asm/arch/gpio.h>
  34. #include <asm/arch/omap.h>
  35. #include <usb.h>
  36. #include <linux/usb/gadget.h>
  37. #include <dwc3-uboot.h>
  38. #include <dwc3-omap-uboot.h>
  39. #include <ti-usb-phy-uboot.h>
  40. #include <mmc.h>
  41. #include <dm/uclass.h>
  42. #include <hang.h>
  43. #include "../common/board_detect.h"
  44. #include "../common/cape_detect.h"
  45. #include "mux_data.h"
  46. #ifdef CONFIG_SUPPORT_EMMC_BOOT
  47. static int board_bootmode_has_emmc(void);
  48. #endif
  49. #define board_is_x15() board_ti_is("BBRDX15_")
  50. #define board_is_x15_revb1() (board_ti_is("BBRDX15_") && \
  51. !strncmp("B.10", board_ti_get_rev(), 3))
  52. #define board_is_x15_revc() (board_ti_is("BBRDX15_") && \
  53. !strncmp("C.00", board_ti_get_rev(), 3))
  54. #define board_is_am572x_evm() board_ti_is("AM572PM_")
  55. #define board_is_am572x_evm_reva3() \
  56. (board_ti_is("AM572PM_") && \
  57. !strncmp("A.30", board_ti_get_rev(), 3))
  58. #define board_is_am574x_idk() board_ti_is("AM574IDK")
  59. #define board_is_am572x_idk() board_ti_is("AM572IDK")
  60. #define board_is_am571x_idk() board_ti_is("AM571IDK")
  61. #define board_is_bbai() board_ti_is("BBONE-AI")
  62. #define board_is_ti_idk() board_is_am574x_idk() || \
  63. board_is_am572x_idk() || \
  64. board_is_am571x_idk()
  65. #ifdef CONFIG_DRIVER_TI_CPSW
  66. #include <cpsw.h>
  67. #endif
  68. DECLARE_GLOBAL_DATA_PTR;
  69. #define GPIO_ETH_LCD GPIO_TO_PIN(2, 22)
  70. #define GPIO_DDR_VTT_EN GPIO_TO_PIN(7, 11)
  71. /* Touch screen controller to identify the LCD */
  72. #define OSD_TS_FT_BUS_ADDRESS 0
  73. #define OSD_TS_FT_CHIP_ADDRESS 0x38
  74. #define OSD_TS_FT_REG_ID 0xA3
  75. /*
  76. * Touchscreen IDs for various OSD panels
  77. * Ref: http://www.osddisplays.com/TI/OSD101T2587-53TS_A.1.pdf
  78. */
  79. /* Used on newer osd101t2587 Panels */
  80. #define OSD_TS_FT_ID_5x46 0x54
  81. /* Used on older osd101t2045 Panels */
  82. #define OSD_TS_FT_ID_5606 0x08
  83. #define SYSINFO_BOARD_NAME_MAX_LEN 45
  84. #define TPS65903X_PRIMARY_SECONDARY_PAD2 0xFB
  85. #define TPS65903X_PAD2_POWERHOLD_MASK 0x20
  86. const struct omap_sysinfo sysinfo = {
  87. "Board: UNKNOWN(BeagleBoard X15?) REV UNKNOWN\n"
  88. };
  89. static const struct dmm_lisa_map_regs beagle_x15_lisa_regs = {
  90. .dmm_lisa_map_3 = 0x80740300,
  91. .is_ma_present = 0x1
  92. };
  93. static const struct dmm_lisa_map_regs am571x_idk_lisa_regs = {
  94. .dmm_lisa_map_3 = 0x80640100,
  95. .is_ma_present = 0x1
  96. };
  97. static const struct dmm_lisa_map_regs am574x_idk_lisa_regs = {
  98. .dmm_lisa_map_2 = 0xc0600200,
  99. .dmm_lisa_map_3 = 0x80600100,
  100. .is_ma_present = 0x1
  101. };
  102. static const struct dmm_lisa_map_regs bbai_lisa_regs = {
  103. .dmm_lisa_map_3 = 0x80640100,
  104. .is_ma_present = 0x1
  105. };
  106. void emif_get_dmm_regs(const struct dmm_lisa_map_regs **dmm_lisa_regs)
  107. {
  108. if (board_is_am571x_idk())
  109. *dmm_lisa_regs = &am571x_idk_lisa_regs;
  110. else if (board_is_am574x_idk())
  111. *dmm_lisa_regs = &am574x_idk_lisa_regs;
  112. else if (board_is_bbai())
  113. *dmm_lisa_regs = &bbai_lisa_regs;
  114. else
  115. *dmm_lisa_regs = &beagle_x15_lisa_regs;
  116. }
  117. static const struct emif_regs beagle_x15_emif1_ddr3_532mhz_emif_regs = {
  118. .sdram_config_init = 0x61851b32,
  119. .sdram_config = 0x61851b32,
  120. .sdram_config2 = 0x08000000,
  121. .ref_ctrl = 0x000040F1,
  122. .ref_ctrl_final = 0x00001035,
  123. .sdram_tim1 = 0xcccf36ab,
  124. .sdram_tim2 = 0x308f7fda,
  125. .sdram_tim3 = 0x409f88a8,
  126. .read_idle_ctrl = 0x00050000,
  127. .zq_config = 0x5007190b,
  128. .temp_alert_config = 0x00000000,
  129. .emif_ddr_phy_ctlr_1_init = 0x0024400b,
  130. .emif_ddr_phy_ctlr_1 = 0x0e24400b,
  131. .emif_ddr_ext_phy_ctrl_1 = 0x10040100,
  132. .emif_ddr_ext_phy_ctrl_2 = 0x00910091,
  133. .emif_ddr_ext_phy_ctrl_3 = 0x00950095,
  134. .emif_ddr_ext_phy_ctrl_4 = 0x009b009b,
  135. .emif_ddr_ext_phy_ctrl_5 = 0x009e009e,
  136. .emif_rd_wr_lvl_rmp_win = 0x00000000,
  137. .emif_rd_wr_lvl_rmp_ctl = 0x80000000,
  138. .emif_rd_wr_lvl_ctl = 0x00000000,
  139. .emif_rd_wr_exec_thresh = 0x00000305
  140. };
  141. /* Ext phy ctrl regs 1-35 */
  142. static const u32 beagle_x15_emif1_ddr3_ext_phy_ctrl_const_regs[] = {
  143. 0x10040100,
  144. 0x00910091,
  145. 0x00950095,
  146. 0x009B009B,
  147. 0x009E009E,
  148. 0x00980098,
  149. 0x00340034,
  150. 0x00350035,
  151. 0x00340034,
  152. 0x00310031,
  153. 0x00340034,
  154. 0x007F007F,
  155. 0x007F007F,
  156. 0x007F007F,
  157. 0x007F007F,
  158. 0x007F007F,
  159. 0x00480048,
  160. 0x004A004A,
  161. 0x00520052,
  162. 0x00550055,
  163. 0x00500050,
  164. 0x00000000,
  165. 0x00600020,
  166. 0x40011080,
  167. 0x08102040,
  168. 0x0,
  169. 0x0,
  170. 0x0,
  171. 0x0,
  172. 0x0,
  173. 0x0,
  174. 0x0,
  175. 0x0,
  176. 0x0,
  177. 0x0
  178. };
  179. static const struct emif_regs beagle_x15_emif2_ddr3_532mhz_emif_regs = {
  180. .sdram_config_init = 0x61851b32,
  181. .sdram_config = 0x61851b32,
  182. .sdram_config2 = 0x08000000,
  183. .ref_ctrl = 0x000040F1,
  184. .ref_ctrl_final = 0x00001035,
  185. .sdram_tim1 = 0xcccf36b3,
  186. .sdram_tim2 = 0x308f7fda,
  187. .sdram_tim3 = 0x407f88a8,
  188. .read_idle_ctrl = 0x00050000,
  189. .zq_config = 0x5007190b,
  190. .temp_alert_config = 0x00000000,
  191. .emif_ddr_phy_ctlr_1_init = 0x0024400b,
  192. .emif_ddr_phy_ctlr_1 = 0x0e24400b,
  193. .emif_ddr_ext_phy_ctrl_1 = 0x10040100,
  194. .emif_ddr_ext_phy_ctrl_2 = 0x00910091,
  195. .emif_ddr_ext_phy_ctrl_3 = 0x00950095,
  196. .emif_ddr_ext_phy_ctrl_4 = 0x009b009b,
  197. .emif_ddr_ext_phy_ctrl_5 = 0x009e009e,
  198. .emif_rd_wr_lvl_rmp_win = 0x00000000,
  199. .emif_rd_wr_lvl_rmp_ctl = 0x80000000,
  200. .emif_rd_wr_lvl_ctl = 0x00000000,
  201. .emif_rd_wr_exec_thresh = 0x00000305
  202. };
  203. static const u32 beagle_x15_emif2_ddr3_ext_phy_ctrl_const_regs[] = {
  204. 0x10040100,
  205. 0x00910091,
  206. 0x00950095,
  207. 0x009B009B,
  208. 0x009E009E,
  209. 0x00980098,
  210. 0x00340034,
  211. 0x00350035,
  212. 0x00340034,
  213. 0x00310031,
  214. 0x00340034,
  215. 0x007F007F,
  216. 0x007F007F,
  217. 0x007F007F,
  218. 0x007F007F,
  219. 0x007F007F,
  220. 0x00480048,
  221. 0x004A004A,
  222. 0x00520052,
  223. 0x00550055,
  224. 0x00500050,
  225. 0x00000000,
  226. 0x00600020,
  227. 0x40011080,
  228. 0x08102040,
  229. 0x0,
  230. 0x0,
  231. 0x0,
  232. 0x0,
  233. 0x0,
  234. 0x0,
  235. 0x0,
  236. 0x0,
  237. 0x0,
  238. 0x0
  239. };
  240. static const struct emif_regs am571x_emif1_ddr3_666mhz_emif_regs = {
  241. .sdram_config_init = 0x61863332,
  242. .sdram_config = 0x61863332,
  243. .sdram_config2 = 0x08000000,
  244. .ref_ctrl = 0x0000514d,
  245. .ref_ctrl_final = 0x0000144a,
  246. .sdram_tim1 = 0xd333887c,
  247. .sdram_tim2 = 0x30b37fe3,
  248. .sdram_tim3 = 0x409f8ad8,
  249. .read_idle_ctrl = 0x00050000,
  250. .zq_config = 0x5007190b,
  251. .temp_alert_config = 0x00000000,
  252. .emif_ddr_phy_ctlr_1_init = 0x0024400f,
  253. .emif_ddr_phy_ctlr_1 = 0x0e24400f,
  254. .emif_ddr_ext_phy_ctrl_1 = 0x10040100,
  255. .emif_ddr_ext_phy_ctrl_2 = 0x00910091,
  256. .emif_ddr_ext_phy_ctrl_3 = 0x00950095,
  257. .emif_ddr_ext_phy_ctrl_4 = 0x009b009b,
  258. .emif_ddr_ext_phy_ctrl_5 = 0x009e009e,
  259. .emif_rd_wr_lvl_rmp_win = 0x00000000,
  260. .emif_rd_wr_lvl_rmp_ctl = 0x80000000,
  261. .emif_rd_wr_lvl_ctl = 0x00000000,
  262. .emif_rd_wr_exec_thresh = 0x00000305
  263. };
  264. static const struct emif_regs am574x_emif1_ddr3_666mhz_emif_ecc_regs = {
  265. .sdram_config_init = 0x61863332,
  266. .sdram_config = 0x61863332,
  267. .sdram_config2 = 0x08000000,
  268. .ref_ctrl = 0x0000514d,
  269. .ref_ctrl_final = 0x0000144a,
  270. .sdram_tim1 = 0xd333887c,
  271. .sdram_tim2 = 0x30b37fe3,
  272. .sdram_tim3 = 0x409f8ad8,
  273. .read_idle_ctrl = 0x00050000,
  274. .zq_config = 0x5007190b,
  275. .temp_alert_config = 0x00000000,
  276. .emif_ddr_phy_ctlr_1_init = 0x0024400f,
  277. .emif_ddr_phy_ctlr_1 = 0x0e24400f,
  278. .emif_ddr_ext_phy_ctrl_1 = 0x10040100,
  279. .emif_ddr_ext_phy_ctrl_2 = 0x00910091,
  280. .emif_ddr_ext_phy_ctrl_3 = 0x00950095,
  281. .emif_ddr_ext_phy_ctrl_4 = 0x009b009b,
  282. .emif_ddr_ext_phy_ctrl_5 = 0x009e009e,
  283. .emif_rd_wr_lvl_rmp_win = 0x00000000,
  284. .emif_rd_wr_lvl_rmp_ctl = 0x80000000,
  285. .emif_rd_wr_lvl_ctl = 0x00000000,
  286. .emif_rd_wr_exec_thresh = 0x00000305,
  287. .emif_ecc_ctrl_reg = 0xD0000001,
  288. .emif_ecc_address_range_1 = 0x3FFF0000,
  289. .emif_ecc_address_range_2 = 0x00000000
  290. };
  291. void emif_get_reg_dump(u32 emif_nr, const struct emif_regs **regs)
  292. {
  293. switch (emif_nr) {
  294. case 1:
  295. if (board_is_am571x_idk())
  296. *regs = &am571x_emif1_ddr3_666mhz_emif_regs;
  297. else if (board_is_am574x_idk())
  298. *regs = &am574x_emif1_ddr3_666mhz_emif_ecc_regs;
  299. else
  300. *regs = &beagle_x15_emif1_ddr3_532mhz_emif_regs;
  301. break;
  302. case 2:
  303. if (board_is_am574x_idk())
  304. *regs = &am571x_emif1_ddr3_666mhz_emif_regs;
  305. else
  306. *regs = &beagle_x15_emif2_ddr3_532mhz_emif_regs;
  307. break;
  308. }
  309. }
  310. void emif_get_ext_phy_ctrl_const_regs(u32 emif_nr, const u32 **regs, u32 *size)
  311. {
  312. switch (emif_nr) {
  313. case 1:
  314. *regs = beagle_x15_emif1_ddr3_ext_phy_ctrl_const_regs;
  315. *size = ARRAY_SIZE(beagle_x15_emif1_ddr3_ext_phy_ctrl_const_regs);
  316. break;
  317. case 2:
  318. *regs = beagle_x15_emif2_ddr3_ext_phy_ctrl_const_regs;
  319. *size = ARRAY_SIZE(beagle_x15_emif2_ddr3_ext_phy_ctrl_const_regs);
  320. break;
  321. }
  322. }
  323. struct vcores_data beagle_x15_volts = {
  324. .mpu.value[OPP_NOM] = VDD_MPU_DRA7_NOM,
  325. .mpu.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_MPU_NOM,
  326. .mpu.efuse.reg_bits = DRA752_EFUSE_REGBITS,
  327. .mpu.addr = TPS659038_REG_ADDR_SMPS12,
  328. .mpu.pmic = &tps659038,
  329. .mpu.abb_tx_done_mask = OMAP_ABB_MPU_TXDONE_MASK,
  330. .eve.value[OPP_NOM] = VDD_EVE_DRA7_NOM,
  331. .eve.value[OPP_OD] = VDD_EVE_DRA7_OD,
  332. .eve.value[OPP_HIGH] = VDD_EVE_DRA7_HIGH,
  333. .eve.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_DSPEVE_NOM,
  334. .eve.efuse.reg[OPP_OD] = STD_FUSE_OPP_VMIN_DSPEVE_OD,
  335. .eve.efuse.reg[OPP_HIGH] = STD_FUSE_OPP_VMIN_DSPEVE_HIGH,
  336. .eve.efuse.reg_bits = DRA752_EFUSE_REGBITS,
  337. .eve.addr = TPS659038_REG_ADDR_SMPS45,
  338. .eve.pmic = &tps659038,
  339. .eve.abb_tx_done_mask = OMAP_ABB_EVE_TXDONE_MASK,
  340. .gpu.value[OPP_NOM] = VDD_GPU_DRA7_NOM,
  341. .gpu.value[OPP_OD] = VDD_GPU_DRA7_OD,
  342. .gpu.value[OPP_HIGH] = VDD_GPU_DRA7_HIGH,
  343. .gpu.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_GPU_NOM,
  344. .gpu.efuse.reg[OPP_OD] = STD_FUSE_OPP_VMIN_GPU_OD,
  345. .gpu.efuse.reg[OPP_HIGH] = STD_FUSE_OPP_VMIN_GPU_HIGH,
  346. .gpu.efuse.reg_bits = DRA752_EFUSE_REGBITS,
  347. .gpu.addr = TPS659038_REG_ADDR_SMPS45,
  348. .gpu.pmic = &tps659038,
  349. .gpu.abb_tx_done_mask = OMAP_ABB_GPU_TXDONE_MASK,
  350. .core.value[OPP_NOM] = VDD_CORE_DRA7_NOM,
  351. .core.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_CORE_NOM,
  352. .core.efuse.reg_bits = DRA752_EFUSE_REGBITS,
  353. .core.addr = TPS659038_REG_ADDR_SMPS6,
  354. .core.pmic = &tps659038,
  355. .iva.value[OPP_NOM] = VDD_IVA_DRA7_NOM,
  356. .iva.value[OPP_OD] = VDD_IVA_DRA7_OD,
  357. .iva.value[OPP_HIGH] = VDD_IVA_DRA7_HIGH,
  358. .iva.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_IVA_NOM,
  359. .iva.efuse.reg[OPP_OD] = STD_FUSE_OPP_VMIN_IVA_OD,
  360. .iva.efuse.reg[OPP_HIGH] = STD_FUSE_OPP_VMIN_IVA_HIGH,
  361. .iva.efuse.reg_bits = DRA752_EFUSE_REGBITS,
  362. .iva.addr = TPS659038_REG_ADDR_SMPS45,
  363. .iva.pmic = &tps659038,
  364. .iva.abb_tx_done_mask = OMAP_ABB_IVA_TXDONE_MASK,
  365. };
  366. struct vcores_data am572x_idk_volts = {
  367. .mpu.value[OPP_NOM] = VDD_MPU_DRA7_NOM,
  368. .mpu.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_MPU_NOM,
  369. .mpu.efuse.reg_bits = DRA752_EFUSE_REGBITS,
  370. .mpu.addr = TPS659038_REG_ADDR_SMPS12,
  371. .mpu.pmic = &tps659038,
  372. .mpu.abb_tx_done_mask = OMAP_ABB_MPU_TXDONE_MASK,
  373. .eve.value[OPP_NOM] = VDD_EVE_DRA7_NOM,
  374. .eve.value[OPP_OD] = VDD_EVE_DRA7_OD,
  375. .eve.value[OPP_HIGH] = VDD_EVE_DRA7_HIGH,
  376. .eve.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_DSPEVE_NOM,
  377. .eve.efuse.reg[OPP_OD] = STD_FUSE_OPP_VMIN_DSPEVE_OD,
  378. .eve.efuse.reg[OPP_HIGH] = STD_FUSE_OPP_VMIN_DSPEVE_HIGH,
  379. .eve.efuse.reg_bits = DRA752_EFUSE_REGBITS,
  380. .eve.addr = TPS659038_REG_ADDR_SMPS45,
  381. .eve.pmic = &tps659038,
  382. .eve.abb_tx_done_mask = OMAP_ABB_EVE_TXDONE_MASK,
  383. .gpu.value[OPP_NOM] = VDD_GPU_DRA7_NOM,
  384. .gpu.value[OPP_OD] = VDD_GPU_DRA7_OD,
  385. .gpu.value[OPP_HIGH] = VDD_GPU_DRA7_HIGH,
  386. .gpu.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_GPU_NOM,
  387. .gpu.efuse.reg[OPP_OD] = STD_FUSE_OPP_VMIN_GPU_OD,
  388. .gpu.efuse.reg[OPP_HIGH] = STD_FUSE_OPP_VMIN_GPU_HIGH,
  389. .gpu.efuse.reg_bits = DRA752_EFUSE_REGBITS,
  390. .gpu.addr = TPS659038_REG_ADDR_SMPS6,
  391. .gpu.pmic = &tps659038,
  392. .gpu.abb_tx_done_mask = OMAP_ABB_GPU_TXDONE_MASK,
  393. .core.value[OPP_NOM] = VDD_CORE_DRA7_NOM,
  394. .core.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_CORE_NOM,
  395. .core.efuse.reg_bits = DRA752_EFUSE_REGBITS,
  396. .core.addr = TPS659038_REG_ADDR_SMPS7,
  397. .core.pmic = &tps659038,
  398. .iva.value[OPP_NOM] = VDD_IVA_DRA7_NOM,
  399. .iva.value[OPP_OD] = VDD_IVA_DRA7_OD,
  400. .iva.value[OPP_HIGH] = VDD_IVA_DRA7_HIGH,
  401. .iva.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_IVA_NOM,
  402. .iva.efuse.reg[OPP_OD] = STD_FUSE_OPP_VMIN_IVA_OD,
  403. .iva.efuse.reg[OPP_HIGH] = STD_FUSE_OPP_VMIN_IVA_HIGH,
  404. .iva.efuse.reg_bits = DRA752_EFUSE_REGBITS,
  405. .iva.addr = TPS659038_REG_ADDR_SMPS8,
  406. .iva.pmic = &tps659038,
  407. .iva.abb_tx_done_mask = OMAP_ABB_IVA_TXDONE_MASK,
  408. };
  409. struct vcores_data am571x_idk_volts = {
  410. .mpu.value[OPP_NOM] = VDD_MPU_DRA7_NOM,
  411. .mpu.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_MPU_NOM,
  412. .mpu.efuse.reg_bits = DRA752_EFUSE_REGBITS,
  413. .mpu.addr = TPS659038_REG_ADDR_SMPS12,
  414. .mpu.pmic = &tps659038,
  415. .mpu.abb_tx_done_mask = OMAP_ABB_MPU_TXDONE_MASK,
  416. .eve.value[OPP_NOM] = VDD_EVE_DRA7_NOM,
  417. .eve.value[OPP_OD] = VDD_EVE_DRA7_OD,
  418. .eve.value[OPP_HIGH] = VDD_EVE_DRA7_HIGH,
  419. .eve.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_DSPEVE_NOM,
  420. .eve.efuse.reg[OPP_OD] = STD_FUSE_OPP_VMIN_DSPEVE_OD,
  421. .eve.efuse.reg[OPP_HIGH] = STD_FUSE_OPP_VMIN_DSPEVE_HIGH,
  422. .eve.efuse.reg_bits = DRA752_EFUSE_REGBITS,
  423. .eve.addr = TPS659038_REG_ADDR_SMPS45,
  424. .eve.pmic = &tps659038,
  425. .eve.abb_tx_done_mask = OMAP_ABB_EVE_TXDONE_MASK,
  426. .gpu.value[OPP_NOM] = VDD_GPU_DRA7_NOM,
  427. .gpu.value[OPP_OD] = VDD_GPU_DRA7_OD,
  428. .gpu.value[OPP_HIGH] = VDD_GPU_DRA7_HIGH,
  429. .gpu.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_GPU_NOM,
  430. .gpu.efuse.reg[OPP_OD] = STD_FUSE_OPP_VMIN_GPU_OD,
  431. .gpu.efuse.reg[OPP_HIGH] = STD_FUSE_OPP_VMIN_GPU_HIGH,
  432. .gpu.efuse.reg_bits = DRA752_EFUSE_REGBITS,
  433. .gpu.addr = TPS659038_REG_ADDR_SMPS6,
  434. .gpu.pmic = &tps659038,
  435. .gpu.abb_tx_done_mask = OMAP_ABB_GPU_TXDONE_MASK,
  436. .core.value[OPP_NOM] = VDD_CORE_DRA7_NOM,
  437. .core.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_CORE_NOM,
  438. .core.efuse.reg_bits = DRA752_EFUSE_REGBITS,
  439. .core.addr = TPS659038_REG_ADDR_SMPS7,
  440. .core.pmic = &tps659038,
  441. .iva.value[OPP_NOM] = VDD_IVA_DRA7_NOM,
  442. .iva.value[OPP_OD] = VDD_IVA_DRA7_OD,
  443. .iva.value[OPP_HIGH] = VDD_IVA_DRA7_HIGH,
  444. .iva.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_IVA_NOM,
  445. .iva.efuse.reg[OPP_OD] = STD_FUSE_OPP_VMIN_IVA_OD,
  446. .iva.efuse.reg[OPP_HIGH] = STD_FUSE_OPP_VMIN_IVA_HIGH,
  447. .iva.efuse.reg_bits = DRA752_EFUSE_REGBITS,
  448. .iva.addr = TPS659038_REG_ADDR_SMPS45,
  449. .iva.pmic = &tps659038,
  450. .iva.abb_tx_done_mask = OMAP_ABB_IVA_TXDONE_MASK,
  451. };
  452. int get_voltrail_opp(int rail_offset)
  453. {
  454. int opp;
  455. switch (rail_offset) {
  456. case VOLT_MPU:
  457. opp = DRA7_MPU_OPP;
  458. break;
  459. case VOLT_CORE:
  460. opp = DRA7_CORE_OPP;
  461. break;
  462. case VOLT_GPU:
  463. opp = DRA7_GPU_OPP;
  464. break;
  465. case VOLT_EVE:
  466. opp = DRA7_DSPEVE_OPP;
  467. break;
  468. case VOLT_IVA:
  469. opp = DRA7_IVA_OPP;
  470. break;
  471. default:
  472. opp = OPP_NOM;
  473. }
  474. return opp;
  475. }
  476. #ifdef CONFIG_SPL_BUILD
  477. /* No env to setup for SPL */
  478. static inline void setup_board_eeprom_env(void) { }
  479. /* Override function to read eeprom information */
  480. void do_board_detect(void)
  481. {
  482. int rc;
  483. rc = ti_i2c_eeprom_am_get(CONFIG_EEPROM_BUS_ADDRESS,
  484. CONFIG_EEPROM_CHIP_ADDRESS);
  485. if (rc)
  486. printf("ti_i2c_eeprom_init failed %d\n", rc);
  487. #ifdef CONFIG_SUPPORT_EMMC_BOOT
  488. rc = board_bootmode_has_emmc();
  489. if (!rc)
  490. rc = ti_emmc_boardid_get();
  491. if (rc)
  492. printf("ti_emmc_boardid_get failed %d\n", rc);
  493. #endif
  494. }
  495. #else /* CONFIG_SPL_BUILD */
  496. /* Override function to read eeprom information: actual i2c read done by SPL*/
  497. void do_board_detect(void)
  498. {
  499. char *bname = NULL;
  500. int rc;
  501. rc = ti_i2c_eeprom_am_get(CONFIG_EEPROM_BUS_ADDRESS,
  502. CONFIG_EEPROM_CHIP_ADDRESS);
  503. if (rc)
  504. printf("ti_i2c_eeprom_init failed %d\n", rc);
  505. #ifdef CONFIG_SUPPORT_EMMC_BOOT
  506. rc = board_bootmode_has_emmc();
  507. if (!rc)
  508. rc = ti_emmc_boardid_get();
  509. if (rc)
  510. printf("ti_emmc_boardid_get failed %d\n", rc);
  511. #endif
  512. if (board_is_x15())
  513. bname = "BeagleBoard X15";
  514. else if (board_is_am572x_evm())
  515. bname = "AM572x EVM";
  516. else if (board_is_am574x_idk())
  517. bname = "AM574x IDK";
  518. else if (board_is_am572x_idk())
  519. bname = "AM572x IDK";
  520. else if (board_is_am571x_idk())
  521. bname = "AM571x IDK";
  522. else if (board_is_bbai())
  523. bname = "BeagleBone AI";
  524. if (bname)
  525. snprintf(sysinfo.board_string, SYSINFO_BOARD_NAME_MAX_LEN,
  526. "Board: %s REV %s\n", bname, board_ti_get_rev());
  527. }
  528. static void setup_board_eeprom_env(void)
  529. {
  530. char *name = "beagle_x15";
  531. int rc;
  532. rc = ti_i2c_eeprom_am_get(CONFIG_EEPROM_BUS_ADDRESS,
  533. CONFIG_EEPROM_CHIP_ADDRESS);
  534. if (rc)
  535. goto invalid_eeprom;
  536. if (board_is_x15()) {
  537. if (board_is_x15_revb1())
  538. name = "beagle_x15_revb1";
  539. else if (board_is_x15_revc())
  540. name = "beagle_x15_revc";
  541. else
  542. name = "beagle_x15";
  543. } else if (board_is_am572x_evm()) {
  544. if (board_is_am572x_evm_reva3())
  545. name = "am57xx_evm_reva3";
  546. else
  547. name = "am57xx_evm";
  548. } else if (board_is_am574x_idk()) {
  549. name = "am574x_idk";
  550. } else if (board_is_am572x_idk()) {
  551. name = "am572x_idk";
  552. } else if (board_is_am571x_idk()) {
  553. name = "am571x_idk";
  554. } else if (board_is_bbai()) {
  555. name = "am5729_beagleboneai";
  556. } else {
  557. printf("Unidentified board claims %s in eeprom header\n",
  558. board_ti_get_name());
  559. }
  560. invalid_eeprom:
  561. set_board_info_env(name);
  562. }
  563. #endif /* CONFIG_SPL_BUILD */
  564. void vcores_init(void)
  565. {
  566. if (board_is_am572x_idk() || board_is_am574x_idk())
  567. *omap_vcores = &am572x_idk_volts;
  568. else if (board_is_am571x_idk())
  569. *omap_vcores = &am571x_idk_volts;
  570. else
  571. *omap_vcores = &beagle_x15_volts;
  572. }
  573. void hw_data_init(void)
  574. {
  575. *prcm = &dra7xx_prcm;
  576. if (is_dra72x())
  577. *dplls_data = &dra72x_dplls;
  578. else if (is_dra76x())
  579. *dplls_data = &dra76x_dplls;
  580. else
  581. *dplls_data = &dra7xx_dplls;
  582. *ctrl = &dra7xx_ctrl;
  583. }
  584. bool am571x_idk_needs_lcd(void)
  585. {
  586. bool needs_lcd;
  587. gpio_request(GPIO_ETH_LCD, "nLCD_Detect");
  588. if (gpio_get_value(GPIO_ETH_LCD))
  589. needs_lcd = false;
  590. else
  591. needs_lcd = true;
  592. gpio_free(GPIO_ETH_LCD);
  593. return needs_lcd;
  594. }
  595. int board_init(void)
  596. {
  597. gpmc_init();
  598. gd->bd->bi_boot_params = (CONFIG_SYS_SDRAM_BASE + 0x100);
  599. return 0;
  600. }
  601. void am57x_idk_lcd_detect(void)
  602. {
  603. int r = -ENODEV;
  604. char *idk_lcd = "no";
  605. struct udevice *dev;
  606. /* Only valid for IDKs */
  607. if (!board_is_ti_idk())
  608. return;
  609. /* Only AM571x IDK has gpio control detect.. so check that */
  610. if (board_is_am571x_idk() && !am571x_idk_needs_lcd())
  611. goto out;
  612. r = i2c_get_chip_for_busnum(OSD_TS_FT_BUS_ADDRESS,
  613. OSD_TS_FT_CHIP_ADDRESS, 1, &dev);
  614. if (r) {
  615. printf("%s: Failed to get I2C device %d/%d (ret %d)\n",
  616. __func__, OSD_TS_FT_BUS_ADDRESS, OSD_TS_FT_CHIP_ADDRESS,
  617. r);
  618. /* AM572x IDK has no explicit settings for optional LCD kit */
  619. if (board_is_am571x_idk())
  620. printf("%s: Touch screen detect failed: %d!\n",
  621. __func__, r);
  622. goto out;
  623. }
  624. /* Read FT ID */
  625. r = dm_i2c_reg_read(dev, OSD_TS_FT_REG_ID);
  626. if (r < 0) {
  627. printf("%s: Touch screen ID read %d:0x%02x[0x%02x] failed:%d\n",
  628. __func__, OSD_TS_FT_BUS_ADDRESS, OSD_TS_FT_CHIP_ADDRESS,
  629. OSD_TS_FT_REG_ID, r);
  630. goto out;
  631. }
  632. switch (r) {
  633. case OSD_TS_FT_ID_5606:
  634. idk_lcd = "osd101t2045";
  635. break;
  636. case OSD_TS_FT_ID_5x46:
  637. idk_lcd = "osd101t2587";
  638. break;
  639. default:
  640. printf("%s: Unidentifed Touch screen ID 0x%02x\n",
  641. __func__, r);
  642. /* we will let default be "no lcd" */
  643. }
  644. out:
  645. env_set("idk_lcd", idk_lcd);
  646. /*
  647. * On AM571x_IDK, no Display with J51 set to LCD is considered as an
  648. * invalid configuration and we prevent boot to get user attention.
  649. */
  650. if (board_is_am571x_idk() && am571x_idk_needs_lcd() &&
  651. !strncmp(idk_lcd, "no", 2)) {
  652. printf("%s: Invalid HW configuration: display not detected/supported but J51 is set. Remove J51 to boot without display.\n",
  653. __func__);
  654. hang();
  655. }
  656. return;
  657. }
  658. #if CONFIG_IS_ENABLED(DM_USB) && CONFIG_IS_ENABLED(OF_CONTROL)
  659. static int device_okay(const char *path)
  660. {
  661. int node;
  662. node = fdt_path_offset(gd->fdt_blob, path);
  663. if (node < 0)
  664. return 0;
  665. return fdtdec_get_is_enabled(gd->fdt_blob, node);
  666. }
  667. #endif
  668. int board_late_init(void)
  669. {
  670. setup_board_eeprom_env();
  671. u8 val;
  672. struct udevice *dev;
  673. /*
  674. * DEV_CTRL.DEV_ON = 1 please - else palmas switches off in 8 seconds
  675. * This is the POWERHOLD-in-Low behavior.
  676. */
  677. palmas_i2c_write_u8(TPS65903X_CHIP_P1, 0xA0, 0x1);
  678. /*
  679. * Default FIT boot on HS devices. Non FIT images are not allowed
  680. * on HS devices.
  681. */
  682. if (get_device_type() == HS_DEVICE)
  683. env_set("boot_fit", "1");
  684. /*
  685. * Set the GPIO7 Pad to POWERHOLD. This has higher priority
  686. * over DEV_CTRL.DEV_ON bit. This can be reset in case of
  687. * PMIC Power off. So to be on the safer side set it back
  688. * to POWERHOLD mode irrespective of the current state.
  689. */
  690. palmas_i2c_read_u8(TPS65903X_CHIP_P1, TPS65903X_PRIMARY_SECONDARY_PAD2,
  691. &val);
  692. val = val | TPS65903X_PAD2_POWERHOLD_MASK;
  693. palmas_i2c_write_u8(TPS65903X_CHIP_P1, TPS65903X_PRIMARY_SECONDARY_PAD2,
  694. val);
  695. omap_die_id_serial();
  696. omap_set_fastboot_vars();
  697. am57x_idk_lcd_detect();
  698. /* Just probe the potentially supported cdce913 device */
  699. uclass_get_device(UCLASS_CLK, 0, &dev);
  700. if (board_is_bbai())
  701. env_set("console", "ttyS0,115200n8");
  702. #if !defined(CONFIG_SPL_BUILD)
  703. board_ti_set_ethaddr(2);
  704. #endif
  705. #if CONFIG_IS_ENABLED(DM_USB) && CONFIG_IS_ENABLED(OF_CONTROL)
  706. if (device_okay("/ocp/omap_dwc3_1@48880000"))
  707. enable_usb_clocks(0);
  708. if (device_okay("/ocp/omap_dwc3_2@488c0000"))
  709. enable_usb_clocks(1);
  710. #endif
  711. return 0;
  712. }
  713. void set_muxconf_regs(void)
  714. {
  715. do_set_mux32((*ctrl)->control_padconf_core_base,
  716. early_padconf, ARRAY_SIZE(early_padconf));
  717. #ifdef CONFIG_SUPPORT_EMMC_BOOT
  718. do_set_mux32((*ctrl)->control_padconf_core_base,
  719. emmc_padconf, ARRAY_SIZE(emmc_padconf));
  720. #endif
  721. }
  722. #ifdef CONFIG_IODELAY_RECALIBRATION
  723. void recalibrate_iodelay(void)
  724. {
  725. const struct pad_conf_entry *pconf;
  726. const struct iodelay_cfg_entry *iod, *delta_iod;
  727. int pconf_sz, iod_sz, delta_iod_sz = 0;
  728. int ret;
  729. if (board_is_am572x_idk()) {
  730. pconf = core_padconf_array_essential_am572x_idk;
  731. pconf_sz = ARRAY_SIZE(core_padconf_array_essential_am572x_idk);
  732. iod = iodelay_cfg_array_am572x_idk;
  733. iod_sz = ARRAY_SIZE(iodelay_cfg_array_am572x_idk);
  734. } else if (board_is_am574x_idk()) {
  735. pconf = core_padconf_array_essential_am574x_idk;
  736. pconf_sz = ARRAY_SIZE(core_padconf_array_essential_am574x_idk);
  737. iod = iodelay_cfg_array_am574x_idk;
  738. iod_sz = ARRAY_SIZE(iodelay_cfg_array_am574x_idk);
  739. } else if (board_is_am571x_idk()) {
  740. pconf = core_padconf_array_essential_am571x_idk;
  741. pconf_sz = ARRAY_SIZE(core_padconf_array_essential_am571x_idk);
  742. iod = iodelay_cfg_array_am571x_idk;
  743. iod_sz = ARRAY_SIZE(iodelay_cfg_array_am571x_idk);
  744. } else if (board_is_bbai()) {
  745. pconf = core_padconf_array_essential_bbai;
  746. pconf_sz = ARRAY_SIZE(core_padconf_array_essential_bbai);
  747. iod = iodelay_cfg_array_bbai;
  748. iod_sz = ARRAY_SIZE(iodelay_cfg_array_bbai);
  749. } else {
  750. /* Common for X15/GPEVM */
  751. pconf = core_padconf_array_essential_x15;
  752. pconf_sz = ARRAY_SIZE(core_padconf_array_essential_x15);
  753. /* There never was an SR1.0 X15.. So.. */
  754. if (omap_revision() == DRA752_ES1_1) {
  755. iod = iodelay_cfg_array_x15_sr1_1;
  756. iod_sz = ARRAY_SIZE(iodelay_cfg_array_x15_sr1_1);
  757. } else {
  758. /* Since full production should switch to SR2.0 */
  759. iod = iodelay_cfg_array_x15_sr2_0;
  760. iod_sz = ARRAY_SIZE(iodelay_cfg_array_x15_sr2_0);
  761. }
  762. }
  763. /* Setup I/O isolation */
  764. ret = __recalibrate_iodelay_start();
  765. if (ret)
  766. goto err;
  767. /* Do the muxing here */
  768. do_set_mux32((*ctrl)->control_padconf_core_base, pconf, pconf_sz);
  769. /* Now do the weird minor deltas that should be safe */
  770. if (board_is_x15() || board_is_am572x_evm()) {
  771. if (board_is_x15_revb1() || board_is_am572x_evm_reva3() ||
  772. board_is_x15_revc()) {
  773. pconf = core_padconf_array_delta_x15_sr2_0;
  774. pconf_sz = ARRAY_SIZE(core_padconf_array_delta_x15_sr2_0);
  775. } else {
  776. pconf = core_padconf_array_delta_x15_sr1_1;
  777. pconf_sz = ARRAY_SIZE(core_padconf_array_delta_x15_sr1_1);
  778. }
  779. do_set_mux32((*ctrl)->control_padconf_core_base, pconf, pconf_sz);
  780. }
  781. if (board_is_am571x_idk()) {
  782. if (am571x_idk_needs_lcd()) {
  783. pconf = core_padconf_array_vout_am571x_idk;
  784. pconf_sz = ARRAY_SIZE(core_padconf_array_vout_am571x_idk);
  785. delta_iod = iodelay_cfg_array_am571x_idk_4port;
  786. delta_iod_sz = ARRAY_SIZE(iodelay_cfg_array_am571x_idk_4port);
  787. } else {
  788. pconf = core_padconf_array_icss1eth_am571x_idk;
  789. pconf_sz = ARRAY_SIZE(core_padconf_array_icss1eth_am571x_idk);
  790. }
  791. do_set_mux32((*ctrl)->control_padconf_core_base, pconf, pconf_sz);
  792. }
  793. /* Setup IOdelay configuration */
  794. ret = do_set_iodelay((*ctrl)->iodelay_config_base, iod, iod_sz);
  795. if (delta_iod_sz)
  796. ret = do_set_iodelay((*ctrl)->iodelay_config_base, delta_iod,
  797. delta_iod_sz);
  798. err:
  799. /* Closeup.. remove isolation */
  800. __recalibrate_iodelay_end(ret);
  801. }
  802. #endif
  803. #if defined(CONFIG_MMC)
  804. int board_mmc_init(struct bd_info *bis)
  805. {
  806. omap_mmc_init(0, 0, 0, -1, -1);
  807. omap_mmc_init(1, 0, 0, -1, -1);
  808. return 0;
  809. }
  810. static const struct mmc_platform_fixups am57x_es1_1_mmc1_fixups = {
  811. .hw_rev = "rev11",
  812. .unsupported_caps = MMC_CAP(MMC_HS_200) |
  813. MMC_CAP(UHS_SDR104),
  814. .max_freq = 96000000,
  815. };
  816. static const struct mmc_platform_fixups am57x_es1_1_mmc23_fixups = {
  817. .hw_rev = "rev11",
  818. .unsupported_caps = MMC_CAP(MMC_HS_200) |
  819. MMC_CAP(UHS_SDR104) |
  820. MMC_CAP(UHS_SDR50),
  821. .max_freq = 48000000,
  822. };
  823. const struct mmc_platform_fixups *platform_fixups_mmc(uint32_t addr)
  824. {
  825. switch (omap_revision()) {
  826. case DRA752_ES1_0:
  827. case DRA752_ES1_1:
  828. if (addr == OMAP_HSMMC1_BASE)
  829. return &am57x_es1_1_mmc1_fixups;
  830. else
  831. return &am57x_es1_1_mmc23_fixups;
  832. default:
  833. return NULL;
  834. }
  835. }
  836. #endif
  837. #if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_OS_BOOT)
  838. int spl_start_uboot(void)
  839. {
  840. /* break into full u-boot on 'c' */
  841. if (serial_tstc() && serial_getc() == 'c')
  842. return 1;
  843. #ifdef CONFIG_SPL_ENV_SUPPORT
  844. env_init();
  845. env_load();
  846. if (env_get_yesno("boot_os") != 1)
  847. return 1;
  848. #endif
  849. return 0;
  850. }
  851. #endif
  852. #ifdef CONFIG_DRIVER_TI_CPSW
  853. /* Delay value to add to calibrated value */
  854. #define RGMII0_TXCTL_DLY_VAL ((0x3 << 5) + 0x8)
  855. #define RGMII0_TXD0_DLY_VAL ((0x3 << 5) + 0x8)
  856. #define RGMII0_TXD1_DLY_VAL ((0x3 << 5) + 0x2)
  857. #define RGMII0_TXD2_DLY_VAL ((0x4 << 5) + 0x0)
  858. #define RGMII0_TXD3_DLY_VAL ((0x4 << 5) + 0x0)
  859. #define VIN2A_D13_DLY_VAL ((0x3 << 5) + 0x8)
  860. #define VIN2A_D17_DLY_VAL ((0x3 << 5) + 0x8)
  861. #define VIN2A_D16_DLY_VAL ((0x3 << 5) + 0x2)
  862. #define VIN2A_D15_DLY_VAL ((0x4 << 5) + 0x0)
  863. #define VIN2A_D14_DLY_VAL ((0x4 << 5) + 0x0)
  864. static void cpsw_control(int enabled)
  865. {
  866. /* VTP can be added here */
  867. }
  868. static struct cpsw_slave_data cpsw_slaves[] = {
  869. {
  870. .slave_reg_ofs = 0x208,
  871. .sliver_reg_ofs = 0xd80,
  872. .phy_addr = 1,
  873. },
  874. {
  875. .slave_reg_ofs = 0x308,
  876. .sliver_reg_ofs = 0xdc0,
  877. .phy_addr = 2,
  878. },
  879. };
  880. static struct cpsw_platform_data cpsw_data = {
  881. .mdio_base = CPSW_MDIO_BASE,
  882. .cpsw_base = CPSW_BASE,
  883. .mdio_div = 0xff,
  884. .channels = 8,
  885. .cpdma_reg_ofs = 0x800,
  886. .slaves = 1,
  887. .slave_data = cpsw_slaves,
  888. .ale_reg_ofs = 0xd00,
  889. .ale_entries = 1024,
  890. .host_port_reg_ofs = 0x108,
  891. .hw_stats_reg_ofs = 0x900,
  892. .bd_ram_ofs = 0x2000,
  893. .mac_control = (1 << 5),
  894. .control = cpsw_control,
  895. .host_port_num = 0,
  896. .version = CPSW_CTRL_VERSION_2,
  897. };
  898. static u64 mac_to_u64(u8 mac[6])
  899. {
  900. int i;
  901. u64 addr = 0;
  902. for (i = 0; i < 6; i++) {
  903. addr <<= 8;
  904. addr |= mac[i];
  905. }
  906. return addr;
  907. }
  908. static void u64_to_mac(u64 addr, u8 mac[6])
  909. {
  910. mac[5] = addr;
  911. mac[4] = addr >> 8;
  912. mac[3] = addr >> 16;
  913. mac[2] = addr >> 24;
  914. mac[1] = addr >> 32;
  915. mac[0] = addr >> 40;
  916. }
  917. int board_eth_init(struct bd_info *bis)
  918. {
  919. int ret;
  920. uint8_t mac_addr[6];
  921. uint32_t mac_hi, mac_lo;
  922. uint32_t ctrl_val;
  923. int i;
  924. u64 mac1, mac2;
  925. u8 mac_addr1[6], mac_addr2[6];
  926. int num_macs;
  927. /* try reading mac address from efuse */
  928. mac_lo = readl((*ctrl)->control_core_mac_id_0_lo);
  929. mac_hi = readl((*ctrl)->control_core_mac_id_0_hi);
  930. mac_addr[0] = (mac_hi & 0xFF0000) >> 16;
  931. mac_addr[1] = (mac_hi & 0xFF00) >> 8;
  932. mac_addr[2] = mac_hi & 0xFF;
  933. mac_addr[3] = (mac_lo & 0xFF0000) >> 16;
  934. mac_addr[4] = (mac_lo & 0xFF00) >> 8;
  935. mac_addr[5] = mac_lo & 0xFF;
  936. if (!env_get("ethaddr")) {
  937. printf("<ethaddr> not set. Validating first E-fuse MAC\n");
  938. if (is_valid_ethaddr(mac_addr))
  939. eth_env_set_enetaddr("ethaddr", mac_addr);
  940. }
  941. mac_lo = readl((*ctrl)->control_core_mac_id_1_lo);
  942. mac_hi = readl((*ctrl)->control_core_mac_id_1_hi);
  943. mac_addr[0] = (mac_hi & 0xFF0000) >> 16;
  944. mac_addr[1] = (mac_hi & 0xFF00) >> 8;
  945. mac_addr[2] = mac_hi & 0xFF;
  946. mac_addr[3] = (mac_lo & 0xFF0000) >> 16;
  947. mac_addr[4] = (mac_lo & 0xFF00) >> 8;
  948. mac_addr[5] = mac_lo & 0xFF;
  949. if (!env_get("eth1addr")) {
  950. if (is_valid_ethaddr(mac_addr))
  951. eth_env_set_enetaddr("eth1addr", mac_addr);
  952. }
  953. ctrl_val = readl((*ctrl)->control_core_control_io1) & (~0x33);
  954. ctrl_val |= 0x22;
  955. writel(ctrl_val, (*ctrl)->control_core_control_io1);
  956. /* The phy address for the AM57xx IDK are different than x15 */
  957. if (board_is_am572x_idk() || board_is_am571x_idk() ||
  958. board_is_am574x_idk()) {
  959. cpsw_data.slave_data[0].phy_addr = 0;
  960. cpsw_data.slave_data[1].phy_addr = 1;
  961. }
  962. ret = cpsw_register(&cpsw_data);
  963. if (ret < 0)
  964. printf("Error %d registering CPSW switch\n", ret);
  965. /*
  966. * Export any Ethernet MAC addresses from EEPROM.
  967. * On AM57xx the 2 MAC addresses define the address range
  968. */
  969. board_ti_get_eth_mac_addr(0, mac_addr1);
  970. board_ti_get_eth_mac_addr(1, mac_addr2);
  971. if (is_valid_ethaddr(mac_addr1) && is_valid_ethaddr(mac_addr2)) {
  972. mac1 = mac_to_u64(mac_addr1);
  973. mac2 = mac_to_u64(mac_addr2);
  974. /* must contain an address range */
  975. num_macs = mac2 - mac1 + 1;
  976. /* <= 50 to protect against user programming error */
  977. if (num_macs > 0 && num_macs <= 50) {
  978. for (i = 0; i < num_macs; i++) {
  979. u64_to_mac(mac1 + i, mac_addr);
  980. if (is_valid_ethaddr(mac_addr)) {
  981. eth_env_set_enetaddr_by_index("eth",
  982. i + 2,
  983. mac_addr);
  984. }
  985. }
  986. }
  987. }
  988. return ret;
  989. }
  990. #endif
  991. #ifdef CONFIG_BOARD_EARLY_INIT_F
  992. /* VTT regulator enable */
  993. static inline void vtt_regulator_enable(void)
  994. {
  995. if (omap_hw_init_context() == OMAP_INIT_CONTEXT_UBOOT_AFTER_SPL)
  996. return;
  997. gpio_request(GPIO_DDR_VTT_EN, "ddr_vtt_en");
  998. gpio_direction_output(GPIO_DDR_VTT_EN, 1);
  999. }
  1000. int board_early_init_f(void)
  1001. {
  1002. vtt_regulator_enable();
  1003. return 0;
  1004. }
  1005. #endif
  1006. #if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP)
  1007. int ft_board_setup(void *blob, struct bd_info *bd)
  1008. {
  1009. ft_cpu_setup(blob, bd);
  1010. return 0;
  1011. }
  1012. #endif
  1013. #ifdef CONFIG_SPL_LOAD_FIT
  1014. int board_fit_config_name_match(const char *name)
  1015. {
  1016. if (board_is_x15()) {
  1017. if (board_is_x15_revb1()) {
  1018. if (!strcmp(name, "am57xx-beagle-x15-revb1"))
  1019. return 0;
  1020. } else if (board_is_x15_revc()) {
  1021. if (!strcmp(name, "am57xx-beagle-x15-revc"))
  1022. return 0;
  1023. } else if (!strcmp(name, "am57xx-beagle-x15")) {
  1024. return 0;
  1025. }
  1026. } else if (board_is_am572x_evm() &&
  1027. !strcmp(name, "am57xx-beagle-x15")) {
  1028. return 0;
  1029. } else if (board_is_am572x_idk() && !strcmp(name, "am572x-idk")) {
  1030. return 0;
  1031. } else if (board_is_am574x_idk() && !strcmp(name, "am574x-idk")) {
  1032. return 0;
  1033. } else if (board_is_am571x_idk() && !strcmp(name, "am571x-idk")) {
  1034. return 0;
  1035. } else if (board_is_bbai() && !strcmp(name, "am5729-beagleboneai")) {
  1036. return 0;
  1037. }
  1038. return -1;
  1039. }
  1040. #endif
  1041. #if CONFIG_IS_ENABLED(FASTBOOT) && !CONFIG_IS_ENABLED(ENV_IS_NOWHERE)
  1042. int fastboot_set_reboot_flag(enum fastboot_reboot_reason reason)
  1043. {
  1044. if (reason != FASTBOOT_REBOOT_REASON_BOOTLOADER)
  1045. return -ENOTSUPP;
  1046. printf("Setting reboot to fastboot flag ...\n");
  1047. env_set("dofastboot", "1");
  1048. env_save();
  1049. return 0;
  1050. }
  1051. #endif
  1052. #ifdef CONFIG_SUPPORT_EMMC_BOOT
  1053. static int board_bootmode_has_emmc(void)
  1054. {
  1055. /* Check that boot mode is same as BBAI */
  1056. if (gd->arch.omap_boot_mode != 2)
  1057. return -EIO;
  1058. return 0;
  1059. }
  1060. #endif
  1061. #ifdef CONFIG_TI_SECURE_DEVICE
  1062. void board_fit_image_post_process(const void *fit, int node, void **p_image,
  1063. size_t *p_size)
  1064. {
  1065. secure_boot_verify_image(p_image, p_size);
  1066. }
  1067. void board_tee_image_process(ulong tee_image, size_t tee_size)
  1068. {
  1069. secure_tee_install((u32)tee_image);
  1070. }
  1071. U_BOOT_FIT_LOADABLE_HANDLER(IH_TYPE_TEE, board_tee_image_process);
  1072. #endif