core.h 26 KB

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  1. /* SPDX-License-Identifier: GPL-2.0+ */
  2. /*
  3. * Xtensa processor core configuration information.
  4. * This file is autogenerated, please do not edit.
  5. *
  6. * Copyright (C) 1999-2015 Tensilica Inc.
  7. */
  8. #ifndef _XTENSA_CORE_CONFIGURATION_H
  9. #define _XTENSA_CORE_CONFIGURATION_H
  10. /****************************************************************************
  11. Parameters Useful for Any Code, USER or PRIVILEGED
  12. ****************************************************************************/
  13. /*
  14. * Note: Macros of the form XCHAL_HAVE_*** have a value of 1 if the option is
  15. * configured, and a value of 0 otherwise. These macros are always defined.
  16. */
  17. /*----------------------------------------------------------------------
  18. ISA
  19. ----------------------------------------------------------------------*/
  20. #define XCHAL_HAVE_BE 0 /* big-endian byte ordering */
  21. #define XCHAL_HAVE_WINDOWED 1 /* windowed registers option */
  22. #define XCHAL_NUM_AREGS 32 /* num of physical addr regs */
  23. #define XCHAL_NUM_AREGS_LOG2 5 /* log2(XCHAL_NUM_AREGS) */
  24. #define XCHAL_MAX_INSTRUCTION_SIZE 3 /* max instr bytes (3..8) */
  25. #define XCHAL_HAVE_DEBUG 1 /* debug option */
  26. #define XCHAL_HAVE_DENSITY 1 /* 16-bit instructions */
  27. #define XCHAL_HAVE_LOOPS 1 /* zero-overhead loops */
  28. #define XCHAL_LOOP_BUFFER_SIZE 0 /* zero-ov. loop instr buffer size */
  29. #define XCHAL_HAVE_NSA 1 /* NSA/NSAU instructions */
  30. #define XCHAL_HAVE_MINMAX 1 /* MIN/MAX instructions */
  31. #define XCHAL_HAVE_SEXT 1 /* SEXT instruction */
  32. #define XCHAL_HAVE_DEPBITS 0 /* DEPBITS instruction */
  33. #define XCHAL_HAVE_CLAMPS 1 /* CLAMPS instruction */
  34. #define XCHAL_HAVE_MUL16 1 /* MUL16S/MUL16U instructions */
  35. #define XCHAL_HAVE_MUL32 1 /* MULL instruction */
  36. #define XCHAL_HAVE_MUL32_HIGH 0 /* MULUH/MULSH instructions */
  37. #define XCHAL_HAVE_DIV32 1 /* QUOS/QUOU/REMS/REMU instructions */
  38. #define XCHAL_HAVE_L32R 1 /* L32R instruction */
  39. #define XCHAL_HAVE_ABSOLUTE_LITERALS 0 /* non-PC-rel (extended) L32R */
  40. #define XCHAL_HAVE_CONST16 0 /* CONST16 instruction */
  41. #define XCHAL_HAVE_ADDX 1 /* ADDX#/SUBX# instructions */
  42. #define XCHAL_HAVE_WIDE_BRANCHES 0 /* B*.W18 or B*.W15 instr's */
  43. #define XCHAL_HAVE_PREDICTED_BRANCHES 0 /* B[EQ/EQZ/NE/NEZ]T instr's */
  44. #define XCHAL_HAVE_CALL4AND12 1 /* (obsolete option) */
  45. #define XCHAL_HAVE_ABS 1 /* ABS instruction */
  46. /*#define XCHAL_HAVE_POPC 0*/ /* POPC instruction */
  47. /*#define XCHAL_HAVE_CRC 0*/ /* CRC instruction */
  48. #define XCHAL_HAVE_RELEASE_SYNC 1 /* L32AI/S32RI instructions */
  49. #define XCHAL_HAVE_S32C1I 1 /* S32C1I instruction */
  50. #define XCHAL_HAVE_SPECULATION 0 /* speculation */
  51. #define XCHAL_HAVE_FULL_RESET 1 /* all regs/state reset */
  52. #define XCHAL_NUM_CONTEXTS 1 /* */
  53. #define XCHAL_NUM_MISC_REGS 2 /* num of scratch regs (0..4) */
  54. #define XCHAL_HAVE_TAP_MASTER 0 /* JTAG TAP control instr's */
  55. #define XCHAL_HAVE_PRID 1 /* processor ID register */
  56. #define XCHAL_HAVE_EXTERN_REGS 1 /* WER/RER instructions */
  57. #define XCHAL_HAVE_MX 0 /* MX core (Tensilica internal) */
  58. #define XCHAL_HAVE_MP_INTERRUPTS 0 /* interrupt distributor port */
  59. #define XCHAL_HAVE_MP_RUNSTALL 0 /* core RunStall control port */
  60. #define XCHAL_HAVE_PSO 0 /* Power Shut-Off */
  61. #define XCHAL_HAVE_PSO_CDM 0 /* core/debug/mem pwr domains */
  62. #define XCHAL_HAVE_PSO_FULL_RETENTION 0 /* all regs preserved on PSO */
  63. #define XCHAL_HAVE_THREADPTR 0 /* THREADPTR register */
  64. #define XCHAL_HAVE_BOOLEANS 0 /* boolean registers */
  65. #define XCHAL_HAVE_CP 0 /* CPENABLE reg (coprocessor) */
  66. #define XCHAL_CP_MAXCFG 0 /* max allowed cp id plus one */
  67. #define XCHAL_HAVE_MAC16 1 /* MAC16 package */
  68. #define XCHAL_HAVE_FUSION 0 /* Fusion*/
  69. #define XCHAL_HAVE_FUSION_FP 0 /* Fusion FP option */
  70. #define XCHAL_HAVE_FUSION_LOW_POWER 0 /* Fusion Low Power option */
  71. #define XCHAL_HAVE_FUSION_AES 0 /* Fusion BLE/Wifi AES-128 CCM option */
  72. #define XCHAL_HAVE_FUSION_CONVENC 0 /* Fusion Conv Encode option */
  73. #define XCHAL_HAVE_FUSION_LFSR_CRC 0 /* Fusion LFSR-CRC option */
  74. #define XCHAL_HAVE_FUSION_BITOPS 0 /* Fusion Bit Operations Support option */
  75. #define XCHAL_HAVE_FUSION_AVS 0 /* Fusion AVS option */
  76. #define XCHAL_HAVE_FUSION_16BIT_BASEBAND 0 /* Fusion 16-bit Baseband option */
  77. #define XCHAL_HAVE_HIFIPRO 0 /* HiFiPro Audio Engine pkg */
  78. #define XCHAL_HAVE_HIFI4 0 /* HiFi4 Audio Engine pkg */
  79. #define XCHAL_HAVE_HIFI4_VFPU 0 /* HiFi4 Audio Engine VFPU option */
  80. #define XCHAL_HAVE_HIFI3 0 /* HiFi3 Audio Engine pkg */
  81. #define XCHAL_HAVE_HIFI3_VFPU 0 /* HiFi3 Audio Engine VFPU option */
  82. #define XCHAL_HAVE_HIFI2 0 /* HiFi2 Audio Engine pkg */
  83. #define XCHAL_HAVE_HIFI2EP 0 /* HiFi2EP */
  84. #define XCHAL_HAVE_HIFI_MINI 0
  85. #define XCHAL_HAVE_VECTORFPU2005 0 /* vector or user floating-point pkg */
  86. #define XCHAL_HAVE_USER_DPFPU 0 /* user DP floating-point pkg */
  87. #define XCHAL_HAVE_USER_SPFPU 0 /* user DP floating-point pkg */
  88. #define XCHAL_HAVE_FP 0 /* single prec floating point */
  89. #define XCHAL_HAVE_FP_DIV 0 /* FP with DIV instructions */
  90. #define XCHAL_HAVE_FP_RECIP 0 /* FP with RECIP instructions */
  91. #define XCHAL_HAVE_FP_SQRT 0 /* FP with SQRT instructions */
  92. #define XCHAL_HAVE_FP_RSQRT 0 /* FP with RSQRT instructions */
  93. #define XCHAL_HAVE_DFP 0 /* double precision FP pkg */
  94. #define XCHAL_HAVE_DFP_DIV 0 /* DFP with DIV instructions */
  95. #define XCHAL_HAVE_DFP_RECIP 0 /* DFP with RECIP instructions*/
  96. #define XCHAL_HAVE_DFP_SQRT 0 /* DFP with SQRT instructions */
  97. #define XCHAL_HAVE_DFP_RSQRT 0 /* DFP with RSQRT instructions*/
  98. #define XCHAL_HAVE_DFP_ACCEL 0 /* double precision FP acceleration pkg */
  99. #define XCHAL_HAVE_DFP_accel XCHAL_HAVE_DFP_ACCEL /* for backward compatibility */
  100. #define XCHAL_HAVE_DFPU_SINGLE_ONLY 0 /* DFPU Coprocessor, single precision only */
  101. #define XCHAL_HAVE_DFPU_SINGLE_DOUBLE 0 /* DFPU Coprocessor, single and double precision */
  102. #define XCHAL_HAVE_VECTRA1 0 /* Vectra I pkg */
  103. #define XCHAL_HAVE_VECTRALX 0 /* Vectra LX pkg */
  104. #define XCHAL_HAVE_PDX4 0 /* PDX4 */
  105. #define XCHAL_HAVE_CONNXD2 0 /* ConnX D2 pkg */
  106. #define XCHAL_HAVE_CONNXD2_DUALLSFLIX 0 /* ConnX D2 & Dual LoadStore Flix */
  107. #define XCHAL_HAVE_BBE16 0 /* ConnX BBE16 pkg */
  108. #define XCHAL_HAVE_BBE16_RSQRT 0 /* BBE16 & vector recip sqrt */
  109. #define XCHAL_HAVE_BBE16_VECDIV 0 /* BBE16 & vector divide */
  110. #define XCHAL_HAVE_BBE16_DESPREAD 0 /* BBE16 & despread */
  111. #define XCHAL_HAVE_BBENEP 0 /* ConnX BBENEP pkgs */
  112. #define XCHAL_HAVE_BSP3 0 /* ConnX BSP3 pkg */
  113. #define XCHAL_HAVE_BSP3_TRANSPOSE 0 /* BSP3 & transpose32x32 */
  114. #define XCHAL_HAVE_SSP16 0 /* ConnX SSP16 pkg */
  115. #define XCHAL_HAVE_SSP16_VITERBI 0 /* SSP16 & viterbi */
  116. #define XCHAL_HAVE_TURBO16 0 /* ConnX Turbo16 pkg */
  117. #define XCHAL_HAVE_BBP16 0 /* ConnX BBP16 pkg */
  118. #define XCHAL_HAVE_FLIX3 0 /* basic 3-way FLIX option */
  119. #define XCHAL_HAVE_GRIVPEP 0 /* GRIVPEP is General Release of IVPEP */
  120. #define XCHAL_HAVE_GRIVPEP_HISTOGRAM 0 /* Histogram option on GRIVPEP */
  121. /*----------------------------------------------------------------------
  122. MISC
  123. ----------------------------------------------------------------------*/
  124. #define XCHAL_NUM_LOADSTORE_UNITS 1 /* load/store units */
  125. #define XCHAL_NUM_WRITEBUFFER_ENTRIES 8 /* size of write buffer */
  126. #define XCHAL_INST_FETCH_WIDTH 4 /* instr-fetch width in bytes */
  127. #define XCHAL_DATA_WIDTH 4 /* data width in bytes */
  128. #define XCHAL_DATA_PIPE_DELAY 1 /* d-side pipeline delay
  129. (1 = 5-stage, 2 = 7-stage) */
  130. #define XCHAL_CLOCK_GATING_GLOBAL 0 /* global clock gating */
  131. #define XCHAL_CLOCK_GATING_FUNCUNIT 0 /* funct. unit clock gating */
  132. /* In T1050, applies to selected core load and store instructions (see ISA): */
  133. #define XCHAL_UNALIGNED_LOAD_EXCEPTION 1 /* unaligned loads cause exc. */
  134. #define XCHAL_UNALIGNED_STORE_EXCEPTION 1 /* unaligned stores cause exc.*/
  135. #define XCHAL_UNALIGNED_LOAD_HW 0 /* unaligned loads work in hw */
  136. #define XCHAL_UNALIGNED_STORE_HW 0 /* unaligned stores work in hw*/
  137. #define XCHAL_SW_VERSION 1100002 /* sw version of this header */
  138. #define XCHAL_CORE_ID "de212" /* alphanum core name
  139. (CoreID) set in the Xtensa
  140. Processor Generator */
  141. #define XCHAL_BUILD_UNIQUE_ID 0x0005A985 /* 22-bit sw build ID */
  142. /*
  143. * These definitions describe the hardware targeted by this software.
  144. */
  145. #define XCHAL_HW_CONFIGID0 0xC283DFFE /* ConfigID hi 32 bits*/
  146. #define XCHAL_HW_CONFIGID1 0x1C85A985 /* ConfigID lo 32 bits*/
  147. #define XCHAL_HW_VERSION_NAME "LX6.0.2" /* full version name */
  148. #define XCHAL_HW_VERSION_MAJOR 2600 /* major ver# of targeted hw */
  149. #define XCHAL_HW_VERSION_MINOR 2 /* minor ver# of targeted hw */
  150. #define XCHAL_HW_VERSION 260002 /* major*100+minor */
  151. #define XCHAL_HW_REL_LX6 1
  152. #define XCHAL_HW_REL_LX6_0 1
  153. #define XCHAL_HW_REL_LX6_0_2 1
  154. #define XCHAL_HW_CONFIGID_RELIABLE 1
  155. /* If software targets a *range* of hardware versions, these are the bounds: */
  156. #define XCHAL_HW_MIN_VERSION_MAJOR 2600 /* major v of earliest tgt hw */
  157. #define XCHAL_HW_MIN_VERSION_MINOR 2 /* minor v of earliest tgt hw */
  158. #define XCHAL_HW_MIN_VERSION 260002 /* earliest targeted hw */
  159. #define XCHAL_HW_MAX_VERSION_MAJOR 2600 /* major v of latest tgt hw */
  160. #define XCHAL_HW_MAX_VERSION_MINOR 2 /* minor v of latest tgt hw */
  161. #define XCHAL_HW_MAX_VERSION 260002 /* latest targeted hw */
  162. /*----------------------------------------------------------------------
  163. CACHE
  164. ----------------------------------------------------------------------*/
  165. #define XCHAL_ICACHE_LINESIZE 32 /* I-cache line size in bytes */
  166. #define XCHAL_DCACHE_LINESIZE 32 /* D-cache line size in bytes */
  167. #define XCHAL_ICACHE_LINEWIDTH 5 /* log2(I line size in bytes) */
  168. #define XCHAL_DCACHE_LINEWIDTH 5 /* log2(D line size in bytes) */
  169. #define XCHAL_ICACHE_SIZE 8192 /* I-cache size in bytes or 0 */
  170. #define XCHAL_DCACHE_SIZE 8192 /* D-cache size in bytes or 0 */
  171. #define XCHAL_DCACHE_IS_WRITEBACK 1 /* writeback feature */
  172. #define XCHAL_DCACHE_IS_COHERENT 0 /* MP coherence feature */
  173. #define XCHAL_HAVE_PREFETCH 0 /* PREFCTL register */
  174. #define XCHAL_HAVE_PREFETCH_L1 0 /* prefetch to L1 dcache */
  175. #define XCHAL_PREFETCH_CASTOUT_LINES 0 /* dcache pref. castout bufsz */
  176. #define XCHAL_PREFETCH_ENTRIES 0 /* cache prefetch entries */
  177. #define XCHAL_PREFETCH_BLOCK_ENTRIES 0 /* prefetch block streams */
  178. #define XCHAL_HAVE_CACHE_BLOCKOPS 0 /* block prefetch for caches */
  179. #define XCHAL_HAVE_ICACHE_TEST 1 /* Icache test instructions */
  180. #define XCHAL_HAVE_DCACHE_TEST 1 /* Dcache test instructions */
  181. #define XCHAL_HAVE_ICACHE_DYN_WAYS 0 /* Icache dynamic way support */
  182. #define XCHAL_HAVE_DCACHE_DYN_WAYS 0 /* Dcache dynamic way support */
  183. /****************************************************************************
  184. Parameters Useful for PRIVILEGED (Supervisory or Non-Virtualized) Code
  185. ****************************************************************************/
  186. #ifndef XTENSA_HAL_NON_PRIVILEGED_ONLY
  187. /*----------------------------------------------------------------------
  188. CACHE
  189. ----------------------------------------------------------------------*/
  190. #define XCHAL_HAVE_PIF 1 /* any outbound PIF present */
  191. /* If present, cache size in bytes == (ways * 2^(linewidth + setwidth)). */
  192. /* Number of cache sets in log2(lines per way): */
  193. #define XCHAL_ICACHE_SETWIDTH 7
  194. #define XCHAL_DCACHE_SETWIDTH 7
  195. /* Cache set associativity (number of ways): */
  196. #define XCHAL_ICACHE_WAYS 2
  197. #define XCHAL_DCACHE_WAYS 2
  198. /* Cache features: */
  199. #define XCHAL_ICACHE_LINE_LOCKABLE 1
  200. #define XCHAL_DCACHE_LINE_LOCKABLE 1
  201. #define XCHAL_ICACHE_ECC_PARITY 0
  202. #define XCHAL_DCACHE_ECC_PARITY 0
  203. /* Cache access size in bytes (affects operation of SICW instruction): */
  204. #define XCHAL_ICACHE_ACCESS_SIZE 4
  205. #define XCHAL_DCACHE_ACCESS_SIZE 4
  206. #define XCHAL_DCACHE_BANKS 1 /* number of banks */
  207. /* Number of encoded cache attr bits (see <xtensa/hal.h> for decoded bits): */
  208. #define XCHAL_CA_BITS 4
  209. /* Whether MEMCTL register has anything useful */
  210. #define XCHAL_USE_MEMCTL (((XCHAL_LOOP_BUFFER_SIZE > 0) || \
  211. XCHAL_DCACHE_IS_COHERENT || \
  212. XCHAL_HAVE_ICACHE_DYN_WAYS || \
  213. XCHAL_HAVE_DCACHE_DYN_WAYS) && \
  214. (XCHAL_HW_MIN_VERSION >= XTENSA_HWVERSION_RE_2012_0))
  215. /*----------------------------------------------------------------------
  216. INTERNAL I/D RAM/ROMs and XLMI
  217. ----------------------------------------------------------------------*/
  218. #define XCHAL_NUM_INSTROM 0 /* number of core instr. ROMs */
  219. #define XCHAL_NUM_INSTRAM 1 /* number of core instr. RAMs */
  220. #define XCHAL_NUM_DATAROM 0 /* number of core data ROMs */
  221. #define XCHAL_NUM_DATARAM 1 /* number of core data RAMs */
  222. #define XCHAL_NUM_URAM 0 /* number of core unified RAMs*/
  223. #define XCHAL_NUM_XLMI 1 /* number of core XLMI ports */
  224. /* Instruction RAM 0: */
  225. #define XCHAL_INSTRAM0_VADDR 0x40000000 /* virtual address */
  226. #define XCHAL_INSTRAM0_PADDR 0x40000000 /* physical address */
  227. #define XCHAL_INSTRAM0_SIZE 131072 /* size in bytes */
  228. #define XCHAL_INSTRAM0_ECC_PARITY 0 /* ECC/parity type, 0=none */
  229. /* Data RAM 0: */
  230. #define XCHAL_DATARAM0_VADDR 0x3FFE0000 /* virtual address */
  231. #define XCHAL_DATARAM0_PADDR 0x3FFE0000 /* physical address */
  232. #define XCHAL_DATARAM0_SIZE 131072 /* size in bytes */
  233. #define XCHAL_DATARAM0_ECC_PARITY 0 /* ECC/parity type, 0=none */
  234. #define XCHAL_DATARAM0_BANKS 1 /* number of banks */
  235. /* XLMI Port 0: */
  236. #define XCHAL_XLMI0_VADDR 0x3FFC0000 /* virtual address */
  237. #define XCHAL_XLMI0_PADDR 0x3FFC0000 /* physical address */
  238. #define XCHAL_XLMI0_SIZE 131072 /* size in bytes */
  239. #define XCHAL_XLMI0_ECC_PARITY 0 /* ECC/parity type, 0=none */
  240. #define XCHAL_HAVE_IMEM_LOADSTORE 1 /* can load/store to IROM/IRAM*/
  241. /*----------------------------------------------------------------------
  242. INTERRUPTS and TIMERS
  243. ----------------------------------------------------------------------*/
  244. #define XCHAL_HAVE_INTERRUPTS 1 /* interrupt option */
  245. #define XCHAL_HAVE_HIGHPRI_INTERRUPTS 1 /* med/high-pri. interrupts */
  246. #define XCHAL_HAVE_NMI 1 /* non-maskable interrupt */
  247. #define XCHAL_HAVE_CCOUNT 1 /* CCOUNT reg. (timer option) */
  248. #define XCHAL_NUM_TIMERS 3 /* number of CCOMPAREn regs */
  249. #define XCHAL_NUM_INTERRUPTS 22 /* number of interrupts */
  250. #define XCHAL_NUM_INTERRUPTS_LOG2 5 /* ceil(log2(NUM_INTERRUPTS)) */
  251. #define XCHAL_NUM_EXTINTERRUPTS 17 /* num of external interrupts */
  252. #define XCHAL_NUM_INTLEVELS 6 /* number of interrupt levels
  253. (not including level zero) */
  254. #define XCHAL_EXCM_LEVEL 3 /* level masked by PS.EXCM */
  255. /* (always 1 in XEA1; levels 2 .. EXCM_LEVEL are "medium priority") */
  256. /* Masks of interrupts at each interrupt level: */
  257. #define XCHAL_INTLEVEL1_MASK 0x001F80FF
  258. #define XCHAL_INTLEVEL2_MASK 0x00000100
  259. #define XCHAL_INTLEVEL3_MASK 0x00200E00
  260. #define XCHAL_INTLEVEL4_MASK 0x00001000
  261. #define XCHAL_INTLEVEL5_MASK 0x00002000
  262. #define XCHAL_INTLEVEL6_MASK 0x00000000
  263. #define XCHAL_INTLEVEL7_MASK 0x00004000
  264. /* Masks of interrupts at each range 1..n of interrupt levels: */
  265. #define XCHAL_INTLEVEL1_ANDBELOW_MASK 0x001F80FF
  266. #define XCHAL_INTLEVEL2_ANDBELOW_MASK 0x001F81FF
  267. #define XCHAL_INTLEVEL3_ANDBELOW_MASK 0x003F8FFF
  268. #define XCHAL_INTLEVEL4_ANDBELOW_MASK 0x003F9FFF
  269. #define XCHAL_INTLEVEL5_ANDBELOW_MASK 0x003FBFFF
  270. #define XCHAL_INTLEVEL6_ANDBELOW_MASK 0x003FBFFF
  271. #define XCHAL_INTLEVEL7_ANDBELOW_MASK 0x003FFFFF
  272. /* Level of each interrupt: */
  273. #define XCHAL_INT0_LEVEL 1
  274. #define XCHAL_INT1_LEVEL 1
  275. #define XCHAL_INT2_LEVEL 1
  276. #define XCHAL_INT3_LEVEL 1
  277. #define XCHAL_INT4_LEVEL 1
  278. #define XCHAL_INT5_LEVEL 1
  279. #define XCHAL_INT6_LEVEL 1
  280. #define XCHAL_INT7_LEVEL 1
  281. #define XCHAL_INT8_LEVEL 2
  282. #define XCHAL_INT9_LEVEL 3
  283. #define XCHAL_INT10_LEVEL 3
  284. #define XCHAL_INT11_LEVEL 3
  285. #define XCHAL_INT12_LEVEL 4
  286. #define XCHAL_INT13_LEVEL 5
  287. #define XCHAL_INT14_LEVEL 7
  288. #define XCHAL_INT15_LEVEL 1
  289. #define XCHAL_INT16_LEVEL 1
  290. #define XCHAL_INT17_LEVEL 1
  291. #define XCHAL_INT18_LEVEL 1
  292. #define XCHAL_INT19_LEVEL 1
  293. #define XCHAL_INT20_LEVEL 1
  294. #define XCHAL_INT21_LEVEL 3
  295. #define XCHAL_DEBUGLEVEL 6 /* debug interrupt level */
  296. #define XCHAL_HAVE_DEBUG_EXTERN_INT 1 /* OCD external db interrupt */
  297. #define XCHAL_NMILEVEL 7 /* NMI "level" (for use with
  298. EXCSAVE/EPS/EPC_n, RFI n) */
  299. /* Type of each interrupt: */
  300. #define XCHAL_INT0_TYPE XTHAL_INTTYPE_EXTERN_LEVEL
  301. #define XCHAL_INT1_TYPE XTHAL_INTTYPE_EXTERN_LEVEL
  302. #define XCHAL_INT2_TYPE XTHAL_INTTYPE_EXTERN_LEVEL
  303. #define XCHAL_INT3_TYPE XTHAL_INTTYPE_EXTERN_LEVEL
  304. #define XCHAL_INT4_TYPE XTHAL_INTTYPE_EXTERN_LEVEL
  305. #define XCHAL_INT5_TYPE XTHAL_INTTYPE_EXTERN_LEVEL
  306. #define XCHAL_INT6_TYPE XTHAL_INTTYPE_TIMER
  307. #define XCHAL_INT7_TYPE XTHAL_INTTYPE_SOFTWARE
  308. #define XCHAL_INT8_TYPE XTHAL_INTTYPE_EXTERN_LEVEL
  309. #define XCHAL_INT9_TYPE XTHAL_INTTYPE_EXTERN_LEVEL
  310. #define XCHAL_INT10_TYPE XTHAL_INTTYPE_TIMER
  311. #define XCHAL_INT11_TYPE XTHAL_INTTYPE_SOFTWARE
  312. #define XCHAL_INT12_TYPE XTHAL_INTTYPE_EXTERN_LEVEL
  313. #define XCHAL_INT13_TYPE XTHAL_INTTYPE_TIMER
  314. #define XCHAL_INT14_TYPE XTHAL_INTTYPE_NMI
  315. #define XCHAL_INT15_TYPE XTHAL_INTTYPE_EXTERN_EDGE
  316. #define XCHAL_INT16_TYPE XTHAL_INTTYPE_EXTERN_EDGE
  317. #define XCHAL_INT17_TYPE XTHAL_INTTYPE_EXTERN_EDGE
  318. #define XCHAL_INT18_TYPE XTHAL_INTTYPE_EXTERN_EDGE
  319. #define XCHAL_INT19_TYPE XTHAL_INTTYPE_EXTERN_EDGE
  320. #define XCHAL_INT20_TYPE XTHAL_INTTYPE_EXTERN_EDGE
  321. #define XCHAL_INT21_TYPE XTHAL_INTTYPE_EXTERN_EDGE
  322. /* Masks of interrupts for each type of interrupt: */
  323. #define XCHAL_INTTYPE_MASK_UNCONFIGURED 0xFFC00000
  324. #define XCHAL_INTTYPE_MASK_SOFTWARE 0x00000880
  325. #define XCHAL_INTTYPE_MASK_EXTERN_EDGE 0x003F8000
  326. #define XCHAL_INTTYPE_MASK_EXTERN_LEVEL 0x0000133F
  327. #define XCHAL_INTTYPE_MASK_TIMER 0x00002440
  328. #define XCHAL_INTTYPE_MASK_NMI 0x00004000
  329. #define XCHAL_INTTYPE_MASK_WRITE_ERROR 0x00000000
  330. #define XCHAL_INTTYPE_MASK_PROFILING 0x00000000
  331. /* Interrupt numbers assigned to specific interrupt sources: */
  332. #define XCHAL_TIMER0_INTERRUPT 6 /* CCOMPARE0 */
  333. #define XCHAL_TIMER1_INTERRUPT 10 /* CCOMPARE1 */
  334. #define XCHAL_TIMER2_INTERRUPT 13 /* CCOMPARE2 */
  335. #define XCHAL_TIMER3_INTERRUPT XTHAL_TIMER_UNCONFIGURED
  336. #define XCHAL_NMI_INTERRUPT 14 /* non-maskable interrupt */
  337. /* Interrupt numbers for levels at which only one interrupt is configured: */
  338. #define XCHAL_INTLEVEL2_NUM 8
  339. #define XCHAL_INTLEVEL4_NUM 12
  340. #define XCHAL_INTLEVEL5_NUM 13
  341. #define XCHAL_INTLEVEL7_NUM 14
  342. /* (There are many interrupts each at level(s) 1, 3.) */
  343. /*
  344. * External interrupt mapping.
  345. * These macros describe how Xtensa processor interrupt numbers
  346. * (as numbered internally, eg. in INTERRUPT and INTENABLE registers)
  347. * map to external BInterrupt<n> pins, for those interrupts
  348. * configured as external (level-triggered, edge-triggered, or NMI).
  349. * See the Xtensa processor databook for more details.
  350. */
  351. /* Core interrupt numbers mapped to each EXTERNAL BInterrupt pin number: */
  352. #define XCHAL_EXTINT0_NUM 0 /* (intlevel 1) */
  353. #define XCHAL_EXTINT1_NUM 1 /* (intlevel 1) */
  354. #define XCHAL_EXTINT2_NUM 2 /* (intlevel 1) */
  355. #define XCHAL_EXTINT3_NUM 3 /* (intlevel 1) */
  356. #define XCHAL_EXTINT4_NUM 4 /* (intlevel 1) */
  357. #define XCHAL_EXTINT5_NUM 5 /* (intlevel 1) */
  358. #define XCHAL_EXTINT6_NUM 8 /* (intlevel 2) */
  359. #define XCHAL_EXTINT7_NUM 9 /* (intlevel 3) */
  360. #define XCHAL_EXTINT8_NUM 12 /* (intlevel 4) */
  361. #define XCHAL_EXTINT9_NUM 14 /* (intlevel 7) */
  362. #define XCHAL_EXTINT10_NUM 15 /* (intlevel 1) */
  363. #define XCHAL_EXTINT11_NUM 16 /* (intlevel 1) */
  364. #define XCHAL_EXTINT12_NUM 17 /* (intlevel 1) */
  365. #define XCHAL_EXTINT13_NUM 18 /* (intlevel 1) */
  366. #define XCHAL_EXTINT14_NUM 19 /* (intlevel 1) */
  367. #define XCHAL_EXTINT15_NUM 20 /* (intlevel 1) */
  368. #define XCHAL_EXTINT16_NUM 21 /* (intlevel 3) */
  369. /* EXTERNAL BInterrupt pin numbers mapped to each core interrupt number: */
  370. #define XCHAL_INT0_EXTNUM 0 /* (intlevel 1) */
  371. #define XCHAL_INT1_EXTNUM 1 /* (intlevel 1) */
  372. #define XCHAL_INT2_EXTNUM 2 /* (intlevel 1) */
  373. #define XCHAL_INT3_EXTNUM 3 /* (intlevel 1) */
  374. #define XCHAL_INT4_EXTNUM 4 /* (intlevel 1) */
  375. #define XCHAL_INT5_EXTNUM 5 /* (intlevel 1) */
  376. #define XCHAL_INT8_EXTNUM 6 /* (intlevel 2) */
  377. #define XCHAL_INT9_EXTNUM 7 /* (intlevel 3) */
  378. #define XCHAL_INT12_EXTNUM 8 /* (intlevel 4) */
  379. #define XCHAL_INT14_EXTNUM 9 /* (intlevel 7) */
  380. #define XCHAL_INT15_EXTNUM 10 /* (intlevel 1) */
  381. #define XCHAL_INT16_EXTNUM 11 /* (intlevel 1) */
  382. #define XCHAL_INT17_EXTNUM 12 /* (intlevel 1) */
  383. #define XCHAL_INT18_EXTNUM 13 /* (intlevel 1) */
  384. #define XCHAL_INT19_EXTNUM 14 /* (intlevel 1) */
  385. #define XCHAL_INT20_EXTNUM 15 /* (intlevel 1) */
  386. #define XCHAL_INT21_EXTNUM 16 /* (intlevel 3) */
  387. /*----------------------------------------------------------------------
  388. EXCEPTIONS and VECTORS
  389. ----------------------------------------------------------------------*/
  390. #define XCHAL_XEA_VERSION 2 /* Xtensa Exception Architecture
  391. number: 1 == XEA1 (old)
  392. 2 == XEA2 (new)
  393. 0 == XEAX (extern) or TX */
  394. #define XCHAL_HAVE_XEA1 0 /* Exception Architecture 1 */
  395. #define XCHAL_HAVE_XEA2 1 /* Exception Architecture 2 */
  396. #define XCHAL_HAVE_XEAX 0 /* External Exception Arch. */
  397. #define XCHAL_HAVE_EXCEPTIONS 1 /* exception option */
  398. #define XCHAL_HAVE_HALT 0 /* halt architecture option */
  399. #define XCHAL_HAVE_BOOTLOADER 0 /* boot loader (for TX) */
  400. #define XCHAL_HAVE_MEM_ECC_PARITY 0 /* local memory ECC/parity */
  401. #define XCHAL_HAVE_VECTOR_SELECT 1 /* relocatable vectors */
  402. #define XCHAL_HAVE_VECBASE 1 /* relocatable vectors */
  403. #define XCHAL_VECBASE_RESET_VADDR 0x60000000 /* VECBASE reset value */
  404. #define XCHAL_VECBASE_RESET_PADDR 0x60000000
  405. #define XCHAL_RESET_VECBASE_OVERLAP 0
  406. #define XCHAL_RESET_VECTOR0_VADDR 0x50000000
  407. #define XCHAL_RESET_VECTOR0_PADDR 0x50000000
  408. #define XCHAL_RESET_VECTOR1_VADDR 0x40000400
  409. #define XCHAL_RESET_VECTOR1_PADDR 0x40000400
  410. #define XCHAL_RESET_VECTOR_VADDR 0x50000000
  411. #define XCHAL_RESET_VECTOR_PADDR 0x50000000
  412. #define XCHAL_USER_VECOFS 0x00000340
  413. #define XCHAL_USER_VECTOR_VADDR 0x60000340
  414. #define XCHAL_USER_VECTOR_PADDR 0x60000340
  415. #define XCHAL_KERNEL_VECOFS 0x00000300
  416. #define XCHAL_KERNEL_VECTOR_VADDR 0x60000300
  417. #define XCHAL_KERNEL_VECTOR_PADDR 0x60000300
  418. #define XCHAL_DOUBLEEXC_VECOFS 0x000003C0
  419. #define XCHAL_DOUBLEEXC_VECTOR_VADDR 0x600003C0
  420. #define XCHAL_DOUBLEEXC_VECTOR_PADDR 0x600003C0
  421. #define XCHAL_WINDOW_OF4_VECOFS 0x00000000
  422. #define XCHAL_WINDOW_UF4_VECOFS 0x00000040
  423. #define XCHAL_WINDOW_OF8_VECOFS 0x00000080
  424. #define XCHAL_WINDOW_UF8_VECOFS 0x000000C0
  425. #define XCHAL_WINDOW_OF12_VECOFS 0x00000100
  426. #define XCHAL_WINDOW_UF12_VECOFS 0x00000140
  427. #define XCHAL_WINDOW_VECTORS_VADDR 0x60000000
  428. #define XCHAL_WINDOW_VECTORS_PADDR 0x60000000
  429. #define XCHAL_INTLEVEL2_VECOFS 0x00000180
  430. #define XCHAL_INTLEVEL2_VECTOR_VADDR 0x60000180
  431. #define XCHAL_INTLEVEL2_VECTOR_PADDR 0x60000180
  432. #define XCHAL_INTLEVEL3_VECOFS 0x000001C0
  433. #define XCHAL_INTLEVEL3_VECTOR_VADDR 0x600001C0
  434. #define XCHAL_INTLEVEL3_VECTOR_PADDR 0x600001C0
  435. #define XCHAL_INTLEVEL4_VECOFS 0x00000200
  436. #define XCHAL_INTLEVEL4_VECTOR_VADDR 0x60000200
  437. #define XCHAL_INTLEVEL4_VECTOR_PADDR 0x60000200
  438. #define XCHAL_INTLEVEL5_VECOFS 0x00000240
  439. #define XCHAL_INTLEVEL5_VECTOR_VADDR 0x60000240
  440. #define XCHAL_INTLEVEL5_VECTOR_PADDR 0x60000240
  441. #define XCHAL_INTLEVEL6_VECOFS 0x00000280
  442. #define XCHAL_INTLEVEL6_VECTOR_VADDR 0x60000280
  443. #define XCHAL_INTLEVEL6_VECTOR_PADDR 0x60000280
  444. #define XCHAL_DEBUG_VECOFS XCHAL_INTLEVEL6_VECOFS
  445. #define XCHAL_DEBUG_VECTOR_VADDR XCHAL_INTLEVEL6_VECTOR_VADDR
  446. #define XCHAL_DEBUG_VECTOR_PADDR XCHAL_INTLEVEL6_VECTOR_PADDR
  447. #define XCHAL_NMI_VECOFS 0x000002C0
  448. #define XCHAL_NMI_VECTOR_VADDR 0x600002C0
  449. #define XCHAL_NMI_VECTOR_PADDR 0x600002C0
  450. #define XCHAL_INTLEVEL7_VECOFS XCHAL_NMI_VECOFS
  451. #define XCHAL_INTLEVEL7_VECTOR_VADDR XCHAL_NMI_VECTOR_VADDR
  452. #define XCHAL_INTLEVEL7_VECTOR_PADDR XCHAL_NMI_VECTOR_PADDR
  453. /*----------------------------------------------------------------------
  454. DEBUG MODULE
  455. ----------------------------------------------------------------------*/
  456. /* Misc */
  457. #define XCHAL_HAVE_DEBUG_ERI 1 /* ERI to debug module */
  458. #define XCHAL_HAVE_DEBUG_APB 0 /* APB to debug module */
  459. #define XCHAL_HAVE_DEBUG_JTAG 1 /* JTAG to debug module */
  460. /* On-Chip Debug (OCD) */
  461. #define XCHAL_HAVE_OCD 1 /* OnChipDebug option */
  462. #define XCHAL_NUM_IBREAK 2 /* number of IBREAKn regs */
  463. #define XCHAL_NUM_DBREAK 2 /* number of DBREAKn regs */
  464. #define XCHAL_HAVE_OCD_DIR_ARRAY 0 /* faster OCD option (to LX4) */
  465. #define XCHAL_HAVE_OCD_LS32DDR 1 /* L32DDR/S32DDR (faster OCD) */
  466. /* TRAX (in core) */
  467. #define XCHAL_HAVE_TRAX 1 /* TRAX in debug module */
  468. #define XCHAL_TRAX_MEM_SIZE 262144 /* TRAX memory size in bytes */
  469. #define XCHAL_TRAX_MEM_SHAREABLE 0 /* start/end regs; ready sig. */
  470. #define XCHAL_TRAX_ATB_WIDTH 0 /* ATB width (bits), 0=no ATB */
  471. #define XCHAL_TRAX_TIME_WIDTH 0 /* timestamp bitwidth, 0=none */
  472. /* Perf counters */
  473. #define XCHAL_NUM_PERF_COUNTERS 0 /* performance counters */
  474. /*----------------------------------------------------------------------
  475. MMU
  476. ----------------------------------------------------------------------*/
  477. /* See core-matmap.h header file for more details. */
  478. #define XCHAL_HAVE_TLBS 1 /* inverse of HAVE_CACHEATTR */
  479. #define XCHAL_HAVE_SPANNING_WAY 1 /* one way maps I+D 4GB vaddr */
  480. #define XCHAL_SPANNING_WAY 0 /* TLB spanning way number */
  481. #define XCHAL_HAVE_IDENTITY_MAP 1 /* vaddr == paddr always */
  482. #define XCHAL_HAVE_CACHEATTR 0 /* CACHEATTR register present */
  483. #define XCHAL_HAVE_MIMIC_CACHEATTR 1 /* region protection */
  484. #define XCHAL_HAVE_XLT_CACHEATTR 0 /* region prot. w/translation */
  485. #define XCHAL_HAVE_PTP_MMU 0 /* full MMU (with page table
  486. [autorefill] and protection)
  487. usable for an MMU-based OS */
  488. /* If none of the above last 4 are set, it's a custom TLB configuration. */
  489. #define XCHAL_MMU_ASID_BITS 0 /* number of bits in ASIDs */
  490. #define XCHAL_MMU_RINGS 1 /* number of rings (1..4) */
  491. #define XCHAL_MMU_RING_BITS 0 /* num of bits in RING field */
  492. #endif /* !XTENSA_HAL_NON_PRIVILEGED_ONLY */
  493. #endif /* _XTENSA_CORE_CONFIGURATION_H */