sromc.h 1.4 KB

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  1. /* SPDX-License-Identifier: GPL-2.0+ */
  2. /*
  3. * (C) Copyright 2010 Samsung Electronics
  4. * Naveen Krishna Ch <ch.naveen@samsung.com>
  5. *
  6. * Note: This file contains the register description for Memory subsystem
  7. * (SROM, NAND Flash, OneNand, DDR, OneDRAM) on S5PC1XX.
  8. *
  9. * Only SROMC is defined as of now
  10. */
  11. #ifndef __ASM_ARCH_SROMC_H_
  12. #define __ASM_ARCH_SROMC_H_
  13. #define SMC_DATA16_WIDTH(x) (1<<((x*4)+0))
  14. #define SMC_BYTE_ADDR_MODE(x) (1<<((x*4)+1)) /* 0-> Half-word base address*/
  15. /* 1-> Byte base address*/
  16. #define SMC_WAIT_ENABLE(x) (1<<((x*4)+2))
  17. #define SMC_BYTE_ENABLE(x) (1<<((x*4)+3))
  18. #define SMC_BC_TACS(x) (x << 28) /* 0clk address set-up */
  19. #define SMC_BC_TCOS(x) (x << 24) /* 4clk chip selection set-up */
  20. #define SMC_BC_TACC(x) (x << 16) /* 14clk access cycle */
  21. #define SMC_BC_TCOH(x) (x << 12) /* 1clk chip selection hold */
  22. #define SMC_BC_TAH(x) (x << 8) /* 4clk address holding time */
  23. #define SMC_BC_TACP(x) (x << 4) /* 6clk page mode access cycle */
  24. #define SMC_BC_PMC(x) (x << 0) /* normal(1data)page mode configuration */
  25. #ifndef __ASSEMBLY__
  26. struct s5p_sromc {
  27. unsigned int bw;
  28. unsigned int bc[6];
  29. };
  30. #endif /* __ASSEMBLY__ */
  31. /* Configure the Band Width and Bank Control Regs for required SROMC Bank */
  32. void s5p_config_sromc(u32 srom_bank, u32 srom_bw_conf, u32 srom_bc_conf);
  33. #endif /* __ASM_ARCH_SMC_H_ */