mx6_plugin.S 4.2 KB

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  1. /* SPDX-License-Identifier: GPL-2.0+ */
  2. /*
  3. * Copyright (C) 2016 Freescale Semiconductor, Inc.
  4. */
  5. #include <config.h>
  6. #ifdef CONFIG_ROM_UNIFIED_SECTIONS
  7. #define ROM_API_TABLE_BASE_ADDR_LEGACY 0x180
  8. #define ROM_VERSION_OFFSET 0x80
  9. #else
  10. #define ROM_API_TABLE_BASE_ADDR_LEGACY 0xC0
  11. #define ROM_VERSION_OFFSET 0x48
  12. #endif
  13. #define ROM_API_TABLE_BASE_ADDR_MX6DQ_TO15 0xC4
  14. #define ROM_API_TABLE_BASE_ADDR_MX6DL_TO12 0xC4
  15. #define ROM_API_HWCNFG_SETUP_OFFSET 0x08
  16. #define ROM_VERSION_TO10 0x10
  17. #define ROM_VERSION_TO12 0x12
  18. #define ROM_VERSION_TO15 0x15
  19. plugin_start:
  20. push {r0-r4, lr}
  21. imx6_ddr_setting
  22. imx6_clock_gating
  23. imx6_qos_setting
  24. /*
  25. * The following is to fill in those arguments for this ROM function
  26. * pu_irom_hwcnfg_setup(void **start, size_t *bytes, const void *boot_data)
  27. * This function is used to copy data from the storage media into DDR.
  28. * start - Initial (possibly partial) image load address on entry.
  29. * Final image load address on exit.
  30. * bytes - Initial (possibly partial) image size on entry.
  31. * Final image size on exit.
  32. * boot_data - Initial @ref ivt Boot Data load address.
  33. */
  34. adr r0, boot_data2
  35. adr r1, image_len2
  36. adr r2, boot_data2
  37. #ifdef CONFIG_NOR_BOOT
  38. #ifdef CONFIG_MX6SX
  39. ldr r3, =ROM_VERSION_OFFSET
  40. ldr r4, [r3]
  41. cmp r4, #ROM_VERSION_TO10
  42. bgt before_calling_rom___pu_irom_hwcnfg_setup
  43. ldr r3, =0x00900b00
  44. ldr r4, =0x50000000
  45. str r4, [r3, #0x5c]
  46. #else
  47. ldr r3, =0x00900800
  48. ldr r4, =0x08000000
  49. str r4, [r3, #0xc0]
  50. #endif
  51. #endif
  52. /*
  53. * check the _pu_irom_api_table for the address
  54. */
  55. before_calling_rom___pu_irom_hwcnfg_setup:
  56. ldr r3, =ROM_VERSION_OFFSET
  57. ldr r4, [r3]
  58. #if defined(CONFIG_MX6SOLO) || defined(CONFIG_MX6DL)
  59. ldr r3, =ROM_VERSION_TO12
  60. cmp r4, r3
  61. ldrge r3, =ROM_API_TABLE_BASE_ADDR_MX6DL_TO12
  62. ldrlt r3, =ROM_API_TABLE_BASE_ADDR_LEGACY
  63. #elif defined(CONFIG_MX6Q)
  64. ldr r3, =ROM_VERSION_TO15
  65. cmp r4, r3
  66. ldrge r3, =ROM_API_TABLE_BASE_ADDR_MX6DQ_TO15
  67. ldrlt r3, =ROM_API_TABLE_BASE_ADDR_LEGACY
  68. #else
  69. ldr r3, =ROM_API_TABLE_BASE_ADDR_LEGACY
  70. #endif
  71. ldr r4, [r3, #ROM_API_HWCNFG_SETUP_OFFSET]
  72. blx r4
  73. after_calling_rom___pu_irom_hwcnfg_setup:
  74. /*
  75. * ROM_API_HWCNFG_SETUP function enables MMU & Caches.
  76. * Thus disable MMU & Caches.
  77. */
  78. mrc p15, 0, r0, c1, c0, 0 /* read CP15 register 1 into r0*/
  79. ands r0, r0, #0x1 /* check if MMU is enabled */
  80. beq mmu_disable_notreq /* exit if MMU is already disabled */
  81. /* Disable caches, MMU */
  82. mrc p15, 0, r0, c1, c0, 0 /* read CP15 register 1 into r0 */
  83. bic r0, r0, #(1 << 2) /* disable D Cache */
  84. bic r0, r0, #0x1 /* clear bit 0 ; MMU off */
  85. bic r0, r0, #(0x1 << 11) /* disable Z, branch prediction */
  86. bic r0, r0, #(0x1 << 1) /* disable A, Strict alignment */
  87. /* check enabled. */
  88. mcr p15, 0, r0, c1, c0, 0 /* write CP15 register 1 */
  89. mov r0, r0
  90. mov r0, r0
  91. mov r0, r0
  92. mov r0, r0
  93. mmu_disable_notreq:
  94. NOP
  95. /* To return to ROM from plugin, we need to fill in these argument.
  96. * Here is what need to do:
  97. * Need to construct the paramters for this function before return to ROM:
  98. * plugin_download(void **start, size_t *bytes, UINT32 *ivt_offset)
  99. */
  100. pop {r0-r4, lr}
  101. push {r5}
  102. ldr r5, boot_data2
  103. str r5, [r0]
  104. ldr r5, image_len2
  105. str r5, [r1]
  106. ldr r5, second_ivt_offset
  107. str r5, [r2]
  108. mov r0, #1
  109. pop {r5}
  110. /* return back to ROM code */
  111. bx lr
  112. /* make the following data right in the end of the output*/
  113. .ltorg
  114. #if (defined(CONFIG_NOR_BOOT) || defined(CONFIG_QSPI_BOOT))
  115. #define FLASH_OFFSET 0x1000
  116. #else
  117. #define FLASH_OFFSET 0x400
  118. #endif
  119. /*
  120. * second_ivt_offset is the offset from the "second_ivt_header" to
  121. * "image_copy_start", which involves FLASH_OFFSET, plus the first
  122. * ivt_header, the plugin code size itself recorded by "ivt2_header"
  123. */
  124. second_ivt_offset: .long (ivt2_header + 0x2C + FLASH_OFFSET)
  125. /*
  126. * The following is the second IVT header plus the second boot data
  127. */
  128. ivt2_header: .long 0x0
  129. app2_code_jump_v: .long 0x0
  130. reserv3: .long 0x0
  131. dcd2_ptr: .long 0x0
  132. boot_data2_ptr: .long 0x0
  133. self_ptr2: .long 0x0
  134. app_code_csf2: .long 0x0
  135. reserv4: .long 0x0
  136. boot_data2: .long 0x0
  137. image_len2: .long 0x0
  138. plugin2: .long 0x0