timer.c 3.9 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright (C) 2010 Albert ARIBAUD <albert.u.boot@aribaud.net>
  4. *
  5. * Based on original Kirkwood support which is
  6. * Copyright (C) Marvell International Ltd. and its affiliates
  7. * Written-by: Prafulla Wadaskar <prafulla@marvell.com>
  8. */
  9. #include <common.h>
  10. #include <init.h>
  11. #include <time.h>
  12. #include <asm/global_data.h>
  13. #include <asm/io.h>
  14. #include <linux/delay.h>
  15. #define UBOOT_CNTR 0 /* counter to use for uboot timer */
  16. /* Timer reload and current value registers */
  17. struct orion5x_tmr_val {
  18. u32 reload; /* Timer reload reg */
  19. u32 val; /* Timer value reg */
  20. };
  21. /* Timer registers */
  22. struct orion5x_tmr_registers {
  23. u32 ctrl; /* Timer control reg */
  24. u32 pad[3];
  25. struct orion5x_tmr_val tmr[2];
  26. u32 wdt_reload;
  27. u32 wdt_val;
  28. };
  29. struct orion5x_tmr_registers *orion5x_tmr_regs =
  30. (struct orion5x_tmr_registers *)ORION5X_TIMER_BASE;
  31. /*
  32. * ARM Timers Registers Map
  33. */
  34. #define CNTMR_CTRL_REG (&orion5x_tmr_regs->ctrl)
  35. #define CNTMR_RELOAD_REG(tmrnum) (&orion5x_tmr_regs->tmr[tmrnum].reload)
  36. #define CNTMR_VAL_REG(tmrnum) (&orion5x_tmr_regs->tmr[tmrnum].val)
  37. /*
  38. * ARM Timers Control Register
  39. * CPU_TIMERS_CTRL_REG (CTCR)
  40. */
  41. #define CTCR_ARM_TIMER_EN_OFFS(cntr) (cntr * 2)
  42. #define CTCR_ARM_TIMER_EN_MASK(cntr) (1 << CTCR_ARM_TIMER_EN_OFFS)
  43. #define CTCR_ARM_TIMER_EN(cntr) (1 << CTCR_ARM_TIMER_EN_OFFS(cntr))
  44. #define CTCR_ARM_TIMER_DIS(cntr) (0 << CTCR_ARM_TIMER_EN_OFFS(cntr))
  45. #define CTCR_ARM_TIMER_AUTO_OFFS(cntr) ((cntr * 2) + 1)
  46. #define CTCR_ARM_TIMER_AUTO_MASK(cntr) (1 << 1)
  47. #define CTCR_ARM_TIMER_AUTO_EN(cntr) (1 << CTCR_ARM_TIMER_AUTO_OFFS(cntr))
  48. #define CTCR_ARM_TIMER_AUTO_DIS(cntr) (0 << CTCR_ARM_TIMER_AUTO_OFFS(cntr))
  49. /*
  50. * ARM Timer\Watchdog Reload Register
  51. * CNTMR_RELOAD_REG (TRR)
  52. */
  53. #define TRG_ARM_TIMER_REL_OFFS 0
  54. #define TRG_ARM_TIMER_REL_MASK 0xffffffff
  55. /*
  56. * ARM Timer\Watchdog Register
  57. * CNTMR_VAL_REG (TVRG)
  58. */
  59. #define TVR_ARM_TIMER_OFFS 0
  60. #define TVR_ARM_TIMER_MASK 0xffffffff
  61. #define TVR_ARM_TIMER_MAX 0xffffffff
  62. #define TIMER_LOAD_VAL 0xffffffff
  63. static inline ulong read_timer(void)
  64. {
  65. return readl(CNTMR_VAL_REG(UBOOT_CNTR))
  66. / (CONFIG_SYS_TCLK / 1000);
  67. }
  68. DECLARE_GLOBAL_DATA_PTR;
  69. #define timestamp gd->arch.tbl
  70. #define lastdec gd->arch.lastinc
  71. static ulong get_timer_masked(void)
  72. {
  73. ulong now = read_timer();
  74. if (lastdec >= now) {
  75. /* normal mode */
  76. timestamp += lastdec - now;
  77. } else {
  78. /* we have an overflow ... */
  79. timestamp += lastdec +
  80. (TIMER_LOAD_VAL / (CONFIG_SYS_TCLK / 1000)) - now;
  81. }
  82. lastdec = now;
  83. return timestamp;
  84. }
  85. ulong get_timer(ulong base)
  86. {
  87. return get_timer_masked() - base;
  88. }
  89. static inline ulong uboot_cntr_val(void)
  90. {
  91. return readl(CNTMR_VAL_REG(UBOOT_CNTR));
  92. }
  93. void __udelay(unsigned long usec)
  94. {
  95. uint current;
  96. ulong delayticks;
  97. current = uboot_cntr_val();
  98. delayticks = (usec * (CONFIG_SYS_TCLK / 1000000));
  99. if (current < delayticks) {
  100. delayticks -= current;
  101. while (uboot_cntr_val() < current)
  102. ;
  103. while ((TIMER_LOAD_VAL - delayticks) < uboot_cntr_val())
  104. ;
  105. } else {
  106. while (uboot_cntr_val() > (current - delayticks))
  107. ;
  108. }
  109. }
  110. /*
  111. * init the counter
  112. */
  113. int timer_init(void)
  114. {
  115. unsigned int cntmrctrl;
  116. /* load value into timer */
  117. writel(TIMER_LOAD_VAL, CNTMR_RELOAD_REG(UBOOT_CNTR));
  118. writel(TIMER_LOAD_VAL, CNTMR_VAL_REG(UBOOT_CNTR));
  119. /* enable timer in auto reload mode */
  120. cntmrctrl = readl(CNTMR_CTRL_REG);
  121. cntmrctrl |= CTCR_ARM_TIMER_EN(UBOOT_CNTR);
  122. cntmrctrl |= CTCR_ARM_TIMER_AUTO_EN(UBOOT_CNTR);
  123. writel(cntmrctrl, CNTMR_CTRL_REG);
  124. return 0;
  125. }
  126. void timer_init_r(void)
  127. {
  128. /* init the timestamp and lastdec value */
  129. lastdec = read_timer();
  130. timestamp = 0;
  131. }
  132. /*
  133. * This function is derived from PowerPC code (read timebase as long long).
  134. * On ARM it just returns the timer value.
  135. */
  136. unsigned long long get_ticks(void)
  137. {
  138. return get_timer(0);
  139. }
  140. /*
  141. * This function is derived from PowerPC code (timebase clock frequency).
  142. * On ARM it returns the number of timer ticks per second.
  143. */
  144. ulong get_tbclk(void)
  145. {
  146. return (ulong)CONFIG_SYS_HZ;
  147. }