start.S 42 KB

1234567891011121314151617181920212223242526272829303132333435363738394041424344454647484950515253545556575859606162636465666768697071727374757677787980818283848586878889909192939495969798991001011021031041051061071081091101111121131141151161171181191201211221231241251261271281291301311321331341351361371381391401411421431441451461471481491501511521531541551561571581591601611621631641651661671681691701711721731741751761771781791801811821831841851861871881891901911921931941951961971981992002012022032042052062072082092102112122132142152162172182192202212222232242252262272282292302312322332342352362372382392402412422432442452462472482492502512522532542552562572582592602612622632642652662672682692702712722732742752762772782792802812822832842852862872882892902912922932942952962972982993003013023033043053063073083093103113123133143153163173183193203213223233243253263273283293303313323333343353363373383393403413423433443453463473483493503513523533543553563573583593603613623633643653663673683693703713723733743753763773783793803813823833843853863873883893903913923933943953963973983994004014024034044054064074084094104114124134144154164174184194204214224234244254264274284294304314324334344354364374384394404414424434444454464474484494504514524534544554564574584594604614624634644654664674684694704714724734744754764774784794804814824834844854864874884894904914924934944954964974984995005015025035045055065075085095105115125135145155165175185195205215225235245255265275285295305315325335345355365375385395405415425435445455465475485495505515525535545555565575585595605615625635645655665675685695705715725735745755765775785795805815825835845855865875885895905915925935945955965975985996006016026036046056066076086096106116126136146156166176186196206216226236246256266276286296306316326336346356366376386396406416426436446456466476486496506516526536546556566576586596606616626636646656666676686696706716726736746756766776786796806816826836846856866876886896906916926936946956966976986997007017027037047057067077087097107117127137147157167177187197207217227237247257267277287297307317327337347357367377387397407417427437447457467477487497507517527537547557567577587597607617627637647657667677687697707717727737747757767777787797807817827837847857867877887897907917927937947957967977987998008018028038048058068078088098108118128138148158168178188198208218228238248258268278288298308318328338348358368378388398408418428438448458468478488498508518528538548558568578588598608618628638648658668678688698708718728738748758768778788798808818828838848858868878888898908918928938948958968978988999009019029039049059069079089099109119129139149159169179189199209219229239249259269279289299309319329339349359369379389399409419429439449459469479489499509519529539549559569579589599609619629639649659669679689699709719729739749759769779789799809819829839849859869879889899909919929939949959969979989991000100110021003100410051006100710081009101010111012101310141015101610171018101910201021102210231024102510261027102810291030103110321033103410351036103710381039104010411042104310441045104610471048104910501051105210531054105510561057105810591060106110621063106410651066106710681069107010711072107310741075107610771078107910801081108210831084108510861087108810891090109110921093109410951096109710981099110011011102110311041105110611071108110911101111111211131114111511161117111811191120112111221123112411251126112711281129113011311132113311341135113611371138113911401141114211431144114511461147114811491150115111521153115411551156115711581159116011611162116311641165116611671168116911701171117211731174117511761177117811791180118111821183118411851186118711881189119011911192119311941195119611971198119912001201120212031204120512061207120812091210121112121213121412151216121712181219122012211222122312241225122612271228122912301231123212331234123512361237123812391240124112421243124412451246124712481249125012511252125312541255125612571258125912601261126212631264126512661267126812691270127112721273127412751276127712781279128012811282128312841285128612871288128912901291129212931294129512961297129812991300130113021303130413051306130713081309131013111312131313141315131613171318131913201321132213231324132513261327132813291330133113321333133413351336133713381339134013411342134313441345134613471348134913501351135213531354135513561357135813591360136113621363136413651366136713681369137013711372137313741375137613771378137913801381138213831384138513861387138813891390139113921393139413951396139713981399140014011402140314041405140614071408140914101411141214131414141514161417141814191420142114221423142414251426142714281429143014311432143314341435143614371438143914401441144214431444144514461447144814491450145114521453145414551456145714581459146014611462146314641465146614671468146914701471147214731474147514761477147814791480148114821483148414851486148714881489149014911492149314941495149614971498149915001501150215031504150515061507150815091510151115121513151415151516151715181519152015211522152315241525152615271528152915301531153215331534153515361537153815391540154115421543154415451546154715481549155015511552155315541555155615571558155915601561156215631564156515661567156815691570157115721573157415751576157715781579158015811582158315841585158615871588158915901591159215931594159515961597159815991600160116021603160416051606160716081609161016111612161316141615161616171618161916201621162216231624162516261627162816291630163116321633163416351636163716381639164016411642164316441645164616471648164916501651165216531654165516561657165816591660166116621663166416651666166716681669167016711672167316741675167616771678167916801681168216831684168516861687168816891690169116921693169416951696169716981699170017011702170317041705170617071708170917101711171217131714171517161717171817191720172117221723172417251726172717281729173017311732173317341735173617371738173917401741174217431744174517461747174817491750175117521753175417551756175717581759176017611762176317641765176617671768176917701771177217731774177517761777177817791780178117821783178417851786178717881789179017911792179317941795179617971798179918001801180218031804180518061807180818091810181118121813181418151816
  1. /* SPDX-License-Identifier: GPL-2.0+ */
  2. /*
  3. * Copyright 2004, 2007-2012 Freescale Semiconductor, Inc.
  4. * Copyright (C) 2003 Motorola,Inc.
  5. */
  6. /* U-Boot Startup Code for Motorola 85xx PowerPC based Embedded Boards
  7. *
  8. * The processor starts at 0xfffffffc and the code is first executed in the
  9. * last 4K page(0xfffff000-0xffffffff) in flash/rom.
  10. *
  11. */
  12. #include <asm-offsets.h>
  13. #include <config.h>
  14. #include <mpc85xx.h>
  15. #include <ppc_asm.tmpl>
  16. #include <ppc_defs.h>
  17. #include <asm/cache.h>
  18. #include <asm/mmu.h>
  19. #undef MSR_KERNEL
  20. #define MSR_KERNEL ( MSR_ME ) /* Machine Check */
  21. #define LAW_EN 0x80000000
  22. #if defined(CONFIG_NAND_SPL) || \
  23. (defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_INIT_MINIMAL))
  24. #define MINIMAL_SPL
  25. #endif
  26. #if !defined(CONFIG_SPL) && !defined(CONFIG_SYS_RAMBOOT) && \
  27. !defined(CONFIG_NXP_ESBC) && !defined(CONFIG_SRIO_PCIE_BOOT_SLAVE)
  28. #define NOR_BOOT
  29. #endif
  30. /*
  31. * Set up GOT: Global Offset Table
  32. *
  33. * Use r12 to access the GOT
  34. */
  35. START_GOT
  36. GOT_ENTRY(_GOT2_TABLE_)
  37. GOT_ENTRY(_FIXUP_TABLE_)
  38. #ifndef MINIMAL_SPL
  39. GOT_ENTRY(_start)
  40. GOT_ENTRY(_start_of_vectors)
  41. GOT_ENTRY(_end_of_vectors)
  42. GOT_ENTRY(transfer_to_handler)
  43. #endif
  44. GOT_ENTRY(__init_end)
  45. GOT_ENTRY(__bss_end)
  46. GOT_ENTRY(__bss_start)
  47. END_GOT
  48. /*
  49. * e500 Startup -- after reset only the last 4KB of the effective
  50. * address space is mapped in the MMU L2 TLB1 Entry0. The .bootpg
  51. * section is located at THIS LAST page and basically does three
  52. * things: clear some registers, set up exception tables and
  53. * add more TLB entries for 'larger spaces'(e.g. the boot rom) to
  54. * continue the boot procedure.
  55. * Once the boot rom is mapped by TLB entries we can proceed
  56. * with normal startup.
  57. *
  58. */
  59. .section .bootpg,"ax"
  60. .globl _start_e500
  61. _start_e500:
  62. /* Enable debug exception */
  63. li r1,MSR_DE
  64. mtmsr r1
  65. /*
  66. * If we got an ePAPR device tree pointer passed in as r3, we need that
  67. * later in cpu_init_early_f(). Save it to a safe register before we
  68. * clobber it so that we can fetch it from there later.
  69. */
  70. mr r24, r3
  71. #ifdef CONFIG_SYS_FSL_ERRATUM_A004510
  72. mfspr r3,SPRN_SVR
  73. rlwinm r3,r3,0,0xff
  74. li r4,CONFIG_SYS_FSL_ERRATUM_A004510_SVR_REV
  75. cmpw r3,r4
  76. beq 1f
  77. #ifdef CONFIG_SYS_FSL_ERRATUM_A004510_SVR_REV2
  78. li r4,CONFIG_SYS_FSL_ERRATUM_A004510_SVR_REV2
  79. cmpw r3,r4
  80. beq 1f
  81. #endif
  82. /* Not a supported revision affected by erratum */
  83. li r27,0
  84. b 2f
  85. 1: li r27,1 /* Remember for later that we have the erratum */
  86. /* Erratum says set bits 55:60 to 001001 */
  87. msync
  88. isync
  89. mfspr r3,SPRN_HDBCR0
  90. li r4,0x48
  91. rlwimi r3,r4,0,0x1f8
  92. mtspr SPRN_HDBCR0,r3
  93. isync
  94. 2:
  95. #endif
  96. #ifdef CONFIG_SYS_FSL_ERRATUM_A005125
  97. msync
  98. isync
  99. mfspr r3, SPRN_HDBCR0
  100. oris r3, r3, 0x0080
  101. mtspr SPRN_HDBCR0, r3
  102. #endif
  103. #if defined(CONFIG_NXP_ESBC) && defined(CONFIG_E500MC) && \
  104. !defined(CONFIG_E6500)
  105. /* ISBC uses L2 as stack.
  106. * Disable L2 cache here so that u-boot can enable it later
  107. * as part of it's normal flow
  108. */
  109. /* Check if L2 is enabled */
  110. mfspr r3, SPRN_L2CSR0
  111. lis r2, L2CSR0_L2E@h
  112. ori r2, r2, L2CSR0_L2E@l
  113. and. r4, r3, r2
  114. beq l2_disabled
  115. mfspr r3, SPRN_L2CSR0
  116. /* Flush L2 cache */
  117. lis r2,(L2CSR0_L2FL)@h
  118. ori r2, r2, (L2CSR0_L2FL)@l
  119. or r3, r2, r3
  120. sync
  121. isync
  122. mtspr SPRN_L2CSR0,r3
  123. isync
  124. 1:
  125. mfspr r3, SPRN_L2CSR0
  126. and. r1, r3, r2
  127. bne 1b
  128. mfspr r3, SPRN_L2CSR0
  129. lis r2, L2CSR0_L2E@h
  130. ori r2, r2, L2CSR0_L2E@l
  131. andc r4, r3, r2
  132. sync
  133. isync
  134. mtspr SPRN_L2CSR0,r4
  135. isync
  136. l2_disabled:
  137. #endif
  138. /* clear registers/arrays not reset by hardware */
  139. /* L1 */
  140. li r0,2
  141. mtspr L1CSR0,r0 /* invalidate d-cache */
  142. mtspr L1CSR1,r0 /* invalidate i-cache */
  143. mfspr r1,DBSR
  144. mtspr DBSR,r1 /* Clear all valid bits */
  145. .macro create_tlb1_entry esel ts tsize epn wimg rpn perm phy_high scratch
  146. lis \scratch, FSL_BOOKE_MAS0(1, \esel, 0)@h
  147. ori \scratch, \scratch, FSL_BOOKE_MAS0(1, \esel, 0)@l
  148. mtspr MAS0, \scratch
  149. lis \scratch, FSL_BOOKE_MAS1(1, 1, 0, \ts, \tsize)@h
  150. ori \scratch, \scratch, FSL_BOOKE_MAS1(1, 1, 0, \ts, \tsize)@l
  151. mtspr MAS1, \scratch
  152. lis \scratch, FSL_BOOKE_MAS2(\epn, \wimg)@h
  153. ori \scratch, \scratch, FSL_BOOKE_MAS2(\epn, \wimg)@l
  154. mtspr MAS2, \scratch
  155. lis \scratch, FSL_BOOKE_MAS3(\rpn, 0, \perm)@h
  156. ori \scratch, \scratch, FSL_BOOKE_MAS3(\rpn, 0, \perm)@l
  157. mtspr MAS3, \scratch
  158. lis \scratch, \phy_high@h
  159. ori \scratch, \scratch, \phy_high@l
  160. mtspr MAS7, \scratch
  161. isync
  162. msync
  163. tlbwe
  164. isync
  165. .endm
  166. .macro create_tlb0_entry esel ts tsize epn wimg rpn perm phy_high scratch
  167. lis \scratch, FSL_BOOKE_MAS0(0, \esel, 0)@h
  168. ori \scratch, \scratch, FSL_BOOKE_MAS0(0, \esel, 0)@l
  169. mtspr MAS0, \scratch
  170. lis \scratch, FSL_BOOKE_MAS1(1, 0, 0, \ts, \tsize)@h
  171. ori \scratch, \scratch, FSL_BOOKE_MAS1(1, 0, 0, \ts, \tsize)@l
  172. mtspr MAS1, \scratch
  173. lis \scratch, FSL_BOOKE_MAS2(\epn, \wimg)@h
  174. ori \scratch, \scratch, FSL_BOOKE_MAS2(\epn, \wimg)@l
  175. mtspr MAS2, \scratch
  176. lis \scratch, FSL_BOOKE_MAS3(\rpn, 0, \perm)@h
  177. ori \scratch, \scratch, FSL_BOOKE_MAS3(\rpn, 0, \perm)@l
  178. mtspr MAS3, \scratch
  179. lis \scratch, \phy_high@h
  180. ori \scratch, \scratch, \phy_high@l
  181. mtspr MAS7, \scratch
  182. isync
  183. msync
  184. tlbwe
  185. isync
  186. .endm
  187. .macro delete_tlb1_entry esel scratch
  188. lis \scratch, FSL_BOOKE_MAS0(1, \esel, 0)@h
  189. ori \scratch, \scratch, FSL_BOOKE_MAS0(1, \esel, 0)@l
  190. mtspr MAS0, \scratch
  191. li \scratch, 0
  192. mtspr MAS1, \scratch
  193. isync
  194. msync
  195. tlbwe
  196. isync
  197. .endm
  198. .macro delete_tlb0_entry esel epn wimg scratch
  199. lis \scratch, FSL_BOOKE_MAS0(0, \esel, 0)@h
  200. ori \scratch, \scratch, FSL_BOOKE_MAS0(0, \esel, 0)@l
  201. mtspr MAS0, \scratch
  202. li \scratch, 0
  203. mtspr MAS1, \scratch
  204. lis \scratch, FSL_BOOKE_MAS2(\epn, \wimg)@h
  205. ori \scratch, \scratch, FSL_BOOKE_MAS2(\epn, \wimg)@l
  206. mtspr MAS2, \scratch
  207. isync
  208. msync
  209. tlbwe
  210. isync
  211. .endm
  212. /* Interrupt vectors do not fit in minimal SPL. */
  213. #if !defined(MINIMAL_SPL)
  214. /* Setup interrupt vectors */
  215. lis r1,CONFIG_SYS_MONITOR_BASE@h
  216. mtspr IVPR,r1
  217. li r4,CriticalInput@l
  218. mtspr IVOR0,r4 /* 0: Critical input */
  219. li r4,MachineCheck@l
  220. mtspr IVOR1,r4 /* 1: Machine check */
  221. li r4,DataStorage@l
  222. mtspr IVOR2,r4 /* 2: Data storage */
  223. li r4,InstStorage@l
  224. mtspr IVOR3,r4 /* 3: Instruction storage */
  225. li r4,ExtInterrupt@l
  226. mtspr IVOR4,r4 /* 4: External interrupt */
  227. li r4,Alignment@l
  228. mtspr IVOR5,r4 /* 5: Alignment */
  229. li r4,ProgramCheck@l
  230. mtspr IVOR6,r4 /* 6: Program check */
  231. li r4,FPUnavailable@l
  232. mtspr IVOR7,r4 /* 7: floating point unavailable */
  233. li r4,SystemCall@l
  234. mtspr IVOR8,r4 /* 8: System call */
  235. /* 9: Auxiliary processor unavailable(unsupported) */
  236. li r4,Decrementer@l
  237. mtspr IVOR10,r4 /* 10: Decrementer */
  238. li r4,IntervalTimer@l
  239. mtspr IVOR11,r4 /* 11: Interval timer */
  240. li r4,WatchdogTimer@l
  241. mtspr IVOR12,r4 /* 12: Watchdog timer */
  242. li r4,DataTLBError@l
  243. mtspr IVOR13,r4 /* 13: Data TLB error */
  244. li r4,InstructionTLBError@l
  245. mtspr IVOR14,r4 /* 14: Instruction TLB error */
  246. li r4,DebugBreakpoint@l
  247. mtspr IVOR15,r4 /* 15: Debug */
  248. #endif
  249. /* Clear and set up some registers. */
  250. li r0,0x0000
  251. lis r1,0xffff
  252. mtspr DEC,r0 /* prevent dec exceptions */
  253. mttbl r0 /* prevent fit & wdt exceptions */
  254. mttbu r0
  255. mtspr TSR,r1 /* clear all timer exception status */
  256. mtspr TCR,r0 /* disable all */
  257. mtspr ESR,r0 /* clear exception syndrome register */
  258. mtspr MCSR,r0 /* machine check syndrome register */
  259. mtxer r0 /* clear integer exception register */
  260. #ifdef CONFIG_SYS_BOOK3E_HV
  261. mtspr MAS8,r0 /* make sure MAS8 is clear */
  262. #endif
  263. /* Enable Time Base and Select Time Base Clock */
  264. lis r0,HID0_EMCP@h /* Enable machine check */
  265. #if defined(CONFIG_ENABLE_36BIT_PHYS)
  266. ori r0,r0,HID0_ENMAS7@l /* Enable MAS7 */
  267. #endif
  268. #ifndef CONFIG_E500MC
  269. ori r0,r0,HID0_TBEN@l /* Enable Timebase */
  270. #endif
  271. mtspr HID0,r0
  272. #if !defined(CONFIG_E500MC) && !defined(CONFIG_ARCH_QEMU_E500)
  273. li r0,(HID1_ASTME|HID1_ABE)@l /* Addr streaming & broadcast */
  274. mfspr r3,PVR
  275. andi. r3,r3, 0xff
  276. cmpwi r3,0x50@l /* if we are rev 5.0 or greater set MBDD */
  277. blt 1f
  278. /* Set MBDD bit also */
  279. ori r0, r0, HID1_MBDD@l
  280. 1:
  281. mtspr HID1,r0
  282. #endif
  283. #ifdef CONFIG_SYS_FSL_ERRATUM_CPU_A003999
  284. mfspr r3,SPRN_HDBCR1
  285. oris r3,r3,0x0100
  286. mtspr SPRN_HDBCR1,r3
  287. #endif
  288. /* Enable Branch Prediction */
  289. #if defined(CONFIG_BTB)
  290. lis r0,BUCSR_ENABLE@h
  291. ori r0,r0,BUCSR_ENABLE@l
  292. mtspr SPRN_BUCSR,r0
  293. #endif
  294. #if defined(CONFIG_SYS_INIT_DBCR)
  295. lis r1,0xffff
  296. ori r1,r1,0xffff
  297. mtspr DBSR,r1 /* Clear all status bits */
  298. lis r0,CONFIG_SYS_INIT_DBCR@h /* DBCR0[IDM] must be set */
  299. ori r0,r0,CONFIG_SYS_INIT_DBCR@l
  300. mtspr DBCR0,r0
  301. #endif
  302. /*
  303. * Search for the TLB that covers the code we're executing, and shrink it
  304. * so that it covers only this 4K page. That will ensure that any other
  305. * TLB we create won't interfere with it. We assume that the TLB exists,
  306. * which is why we don't check the Valid bit of MAS1. We also assume
  307. * it is in TLB1.
  308. *
  309. * This is necessary, for example, when booting from the on-chip ROM,
  310. * which (oddly) creates a single 4GB TLB that covers CCSR and DDR.
  311. */
  312. bl nexti /* Find our address */
  313. nexti: mflr r1 /* R1 = our PC */
  314. li r2, 0
  315. mtspr MAS6, r2 /* Assume the current PID and AS are 0 */
  316. isync
  317. msync
  318. tlbsx 0, r1 /* This must succeed */
  319. mfspr r14, MAS0 /* Save ESEL for later */
  320. rlwinm r14, r14, 16, 0xfff
  321. /* Set the size of the TLB to 4KB */
  322. mfspr r3, MAS1
  323. li r2, 0xF80
  324. andc r3, r3, r2 /* Clear the TSIZE bits */
  325. ori r3, r3, MAS1_TSIZE(BOOKE_PAGESZ_4K)@l
  326. oris r3, r3, MAS1_IPROT@h
  327. mtspr MAS1, r3
  328. /*
  329. * Set the base address of the TLB to our PC. We assume that
  330. * virtual == physical. We also assume that MAS2_EPN == MAS3_RPN.
  331. */
  332. lis r3, MAS2_EPN@h
  333. ori r3, r3, MAS2_EPN@l /* R3 = MAS2_EPN */
  334. and r1, r1, r3 /* Our PC, rounded down to the nearest page */
  335. mfspr r2, MAS2
  336. andc r2, r2, r3
  337. or r2, r2, r1
  338. #ifdef CONFIG_SYS_FSL_ERRATUM_A004510
  339. cmpwi r27,0
  340. beq 1f
  341. andi. r15, r2, MAS2_I|MAS2_G /* save the old I/G for later */
  342. rlwinm r2, r2, 0, ~MAS2_I
  343. ori r2, r2, MAS2_G
  344. 1:
  345. #endif
  346. mtspr MAS2, r2 /* Set the EPN to our PC base address */
  347. mfspr r2, MAS3
  348. andc r2, r2, r3
  349. or r2, r2, r1
  350. mtspr MAS3, r2 /* Set the RPN to our PC base address */
  351. isync
  352. msync
  353. tlbwe
  354. /*
  355. * Clear out any other TLB entries that may exist, to avoid conflicts.
  356. * Our TLB entry is in r14.
  357. */
  358. li r0, TLBIVAX_ALL | TLBIVAX_TLB0
  359. tlbivax 0, r0
  360. tlbsync
  361. mfspr r4, SPRN_TLB1CFG
  362. rlwinm r4, r4, 0, TLBnCFG_NENTRY_MASK
  363. li r3, 0
  364. mtspr MAS1, r3
  365. 1: cmpw r3, r14
  366. rlwinm r5, r3, 16, MAS0_ESEL_MSK
  367. addi r3, r3, 1
  368. beq 2f /* skip the entry we're executing from */
  369. oris r5, r5, MAS0_TLBSEL(1)@h
  370. mtspr MAS0, r5
  371. isync
  372. tlbwe
  373. isync
  374. msync
  375. 2: cmpw r3, r4
  376. blt 1b
  377. #if defined(CONFIG_SYS_PPC_E500_DEBUG_TLB) && !defined(MINIMAL_SPL) && \
  378. !defined(CONFIG_NXP_ESBC)
  379. /*
  380. * TLB entry for debuggging in AS1
  381. * Create temporary TLB entry in AS0 to handle debug exception
  382. * As on debug exception MSR is cleared i.e. Address space is changed
  383. * to 0. A TLB entry (in AS0) is required to handle debug exception generated
  384. * in AS1.
  385. */
  386. #ifdef NOR_BOOT
  387. /*
  388. * TLB entry is created for IVPR + IVOR15 to map on valid OP code address
  389. * bacause flash's virtual address maps to 0xff800000 - 0xffffffff.
  390. * and this window is outside of 4K boot window.
  391. */
  392. create_tlb1_entry CONFIG_SYS_PPC_E500_DEBUG_TLB, \
  393. 0, BOOKE_PAGESZ_4M, \
  394. CONFIG_SYS_MONITOR_BASE & 0xffc00000, MAS2_I|MAS2_G, \
  395. 0xffc00000, MAS3_SX|MAS3_SW|MAS3_SR, \
  396. 0, r6
  397. #else
  398. /*
  399. * TLB entry is created for IVPR + IVOR15 to map on valid OP code address
  400. * because "nexti" will resize TLB to 4K
  401. */
  402. create_tlb1_entry CONFIG_SYS_PPC_E500_DEBUG_TLB, \
  403. 0, BOOKE_PAGESZ_256K, \
  404. CONFIG_SYS_MONITOR_BASE & 0xfffc0000, MAS2_I, \
  405. CONFIG_SYS_MONITOR_BASE & 0xfffc0000, MAS3_SX|MAS3_SW|MAS3_SR, \
  406. 0, r6
  407. #endif
  408. #endif
  409. /*
  410. * Relocate CCSR, if necessary. We relocate CCSR if (obviously) the default
  411. * location is not where we want it. This typically happens on a 36-bit
  412. * system, where we want to move CCSR to near the top of 36-bit address space.
  413. *
  414. * To move CCSR, we create two temporary TLBs, one for the old location, and
  415. * another for the new location. On CoreNet systems, we also need to create
  416. * a special, temporary LAW.
  417. *
  418. * As a general rule, TLB0 is used for short-term TLBs, and TLB1 is used for
  419. * long-term TLBs, so we use TLB0 here.
  420. */
  421. #if (CONFIG_SYS_CCSRBAR_DEFAULT != CONFIG_SYS_CCSRBAR_PHYS)
  422. #if !defined(CONFIG_SYS_CCSRBAR_PHYS_HIGH) || !defined(CONFIG_SYS_CCSRBAR_PHYS_LOW)
  423. #error "CONFIG_SYS_CCSRBAR_PHYS_HIGH and CONFIG_SYS_CCSRBAR_PHYS_LOW) must be defined."
  424. #endif
  425. create_ccsr_new_tlb:
  426. /*
  427. * Create a TLB for the new location of CCSR. Register R8 is reserved
  428. * for the virtual address of this TLB (CONFIG_SYS_CCSRBAR).
  429. */
  430. lis r8, CONFIG_SYS_CCSRBAR@h
  431. ori r8, r8, CONFIG_SYS_CCSRBAR@l
  432. lis r9, (CONFIG_SYS_CCSRBAR + 0x1000)@h
  433. ori r9, r9, (CONFIG_SYS_CCSRBAR + 0x1000)@l
  434. create_tlb0_entry 0, \
  435. 0, BOOKE_PAGESZ_4K, \
  436. CONFIG_SYS_CCSRBAR, MAS2_I|MAS2_G, \
  437. CONFIG_SYS_CCSRBAR_PHYS_LOW, MAS3_SW|MAS3_SR, \
  438. CONFIG_SYS_CCSRBAR_PHYS_HIGH, r3
  439. /*
  440. * Create a TLB for the current location of CCSR. Register R9 is reserved
  441. * for the virtual address of this TLB (CONFIG_SYS_CCSRBAR + 0x1000).
  442. */
  443. create_ccsr_old_tlb:
  444. create_tlb0_entry 1, \
  445. 0, BOOKE_PAGESZ_4K, \
  446. CONFIG_SYS_CCSRBAR + 0x1000, MAS2_I|MAS2_G, \
  447. CONFIG_SYS_CCSRBAR_DEFAULT, MAS3_SW|MAS3_SR, \
  448. 0, r3 /* The default CCSR address is always a 32-bit number */
  449. /*
  450. * We have a TLB for what we think is the current (old) CCSR. Let's
  451. * verify that, otherwise we won't be able to move it.
  452. * CONFIG_SYS_CCSRBAR_DEFAULT is always a 32-bit number, so we only
  453. * need to compare the lower 32 bits of CCSRBAR on CoreNet systems.
  454. */
  455. verify_old_ccsr:
  456. lis r0, CONFIG_SYS_CCSRBAR_DEFAULT@h
  457. ori r0, r0, CONFIG_SYS_CCSRBAR_DEFAULT@l
  458. #ifdef CONFIG_FSL_CORENET
  459. lwz r1, 4(r9) /* CCSRBARL */
  460. #else
  461. lwz r1, 0(r9) /* CCSRBAR, shifted right by 12 */
  462. slwi r1, r1, 12
  463. #endif
  464. cmpl 0, r0, r1
  465. /*
  466. * If the value we read from CCSRBARL is not what we expect, then
  467. * enter an infinite loop. This will at least allow a debugger to
  468. * halt execution and examine TLBs, etc. There's no point in going
  469. * on.
  470. */
  471. infinite_debug_loop:
  472. bne infinite_debug_loop
  473. #ifdef CONFIG_FSL_CORENET
  474. #define CCSR_LAWBARH0 (CONFIG_SYS_CCSRBAR + 0x1000)
  475. #define LAW_SIZE_4K 0xb
  476. #define CCSRBAR_LAWAR (LAW_EN | (0x1e << 20) | LAW_SIZE_4K)
  477. #define CCSRAR_C 0x80000000 /* Commit */
  478. create_temp_law:
  479. /*
  480. * On CoreNet systems, we create the temporary LAW using a special LAW
  481. * target ID of 0x1e. LAWBARH is at offset 0xc00 in CCSR.
  482. */
  483. lis r0, CONFIG_SYS_CCSRBAR_PHYS_HIGH@h
  484. ori r0, r0, CONFIG_SYS_CCSRBAR_PHYS_HIGH@l
  485. lis r1, CONFIG_SYS_CCSRBAR_PHYS_LOW@h
  486. ori r1, r1, CONFIG_SYS_CCSRBAR_PHYS_LOW@l
  487. lis r2, CCSRBAR_LAWAR@h
  488. ori r2, r2, CCSRBAR_LAWAR@l
  489. stw r0, 0xc00(r9) /* LAWBARH0 */
  490. stw r1, 0xc04(r9) /* LAWBARL0 */
  491. sync
  492. stw r2, 0xc08(r9) /* LAWAR0 */
  493. /*
  494. * Read back from LAWAR to ensure the update is complete. e500mc
  495. * cores also require an isync.
  496. */
  497. lwz r0, 0xc08(r9) /* LAWAR0 */
  498. isync
  499. /*
  500. * Read the current CCSRBARH and CCSRBARL using load word instructions.
  501. * Follow this with an isync instruction. This forces any outstanding
  502. * accesses to configuration space to completion.
  503. */
  504. read_old_ccsrbar:
  505. lwz r0, 0(r9) /* CCSRBARH */
  506. lwz r0, 4(r9) /* CCSRBARL */
  507. isync
  508. /*
  509. * Write the new values for CCSRBARH and CCSRBARL to their old
  510. * locations. The CCSRBARH has a shadow register. When the CCSRBARH
  511. * has a new value written it loads a CCSRBARH shadow register. When
  512. * the CCSRBARL is written, the CCSRBARH shadow register contents
  513. * along with the CCSRBARL value are loaded into the CCSRBARH and
  514. * CCSRBARL registers, respectively. Follow this with a sync
  515. * instruction.
  516. */
  517. write_new_ccsrbar:
  518. lis r0, CONFIG_SYS_CCSRBAR_PHYS_HIGH@h
  519. ori r0, r0, CONFIG_SYS_CCSRBAR_PHYS_HIGH@l
  520. lis r1, CONFIG_SYS_CCSRBAR_PHYS_LOW@h
  521. ori r1, r1, CONFIG_SYS_CCSRBAR_PHYS_LOW@l
  522. lis r2, CCSRAR_C@h
  523. ori r2, r2, CCSRAR_C@l
  524. stw r0, 0(r9) /* Write to CCSRBARH */
  525. sync /* Make sure we write to CCSRBARH first */
  526. stw r1, 4(r9) /* Write to CCSRBARL */
  527. sync
  528. /*
  529. * Write a 1 to the commit bit (C) of CCSRAR at the old location.
  530. * Follow this with a sync instruction.
  531. */
  532. stw r2, 8(r9)
  533. sync
  534. /* Delete the temporary LAW */
  535. delete_temp_law:
  536. li r1, 0
  537. stw r1, 0xc08(r8)
  538. sync
  539. stw r1, 0xc00(r8)
  540. stw r1, 0xc04(r8)
  541. sync
  542. #else /* #ifdef CONFIG_FSL_CORENET */
  543. write_new_ccsrbar:
  544. /*
  545. * Read the current value of CCSRBAR using a load word instruction
  546. * followed by an isync. This forces all accesses to configuration
  547. * space to complete.
  548. */
  549. sync
  550. lwz r0, 0(r9)
  551. isync
  552. /* CONFIG_SYS_CCSRBAR_PHYS right shifted by 12 */
  553. #define CCSRBAR_PHYS_RS12 ((CONFIG_SYS_CCSRBAR_PHYS_HIGH << 20) | \
  554. (CONFIG_SYS_CCSRBAR_PHYS_LOW >> 12))
  555. /* Write the new value to CCSRBAR. */
  556. lis r0, CCSRBAR_PHYS_RS12@h
  557. ori r0, r0, CCSRBAR_PHYS_RS12@l
  558. stw r0, 0(r9)
  559. sync
  560. /*
  561. * The manual says to perform a load of an address that does not
  562. * access configuration space or the on-chip SRAM using an existing TLB,
  563. * but that doesn't appear to be necessary. We will do the isync,
  564. * though.
  565. */
  566. isync
  567. /*
  568. * Read the contents of CCSRBAR from its new location, followed by
  569. * another isync.
  570. */
  571. lwz r0, 0(r8)
  572. isync
  573. #endif /* #ifdef CONFIG_FSL_CORENET */
  574. /* Delete the temporary TLBs */
  575. delete_temp_tlbs:
  576. delete_tlb0_entry 0, CONFIG_SYS_CCSRBAR, MAS2_I|MAS2_G, r3
  577. delete_tlb0_entry 1, CONFIG_SYS_CCSRBAR + 0x1000, MAS2_I|MAS2_G, r3
  578. #endif /* #if (CONFIG_SYS_CCSRBAR_DEFAULT != CONFIG_SYS_CCSRBAR_PHYS) */
  579. #if defined(CONFIG_SYS_FSL_QORIQ_CHASSIS2) && defined(CONFIG_E6500)
  580. create_ccsr_l2_tlb:
  581. /*
  582. * Create a TLB for the MMR location of CCSR
  583. * to access L2CSR0 register
  584. */
  585. create_tlb0_entry 0, \
  586. 0, BOOKE_PAGESZ_4K, \
  587. CONFIG_SYS_CCSRBAR + 0xC20000, MAS2_I|MAS2_G, \
  588. CONFIG_SYS_CCSRBAR_PHYS_LOW + 0xC20000, MAS3_SW|MAS3_SR, \
  589. CONFIG_SYS_CCSRBAR_PHYS_HIGH, r3
  590. enable_l2_cluster_l2:
  591. /* enable L2 cache */
  592. lis r3, (CONFIG_SYS_CCSRBAR + 0xC20000)@h
  593. ori r3, r3, (CONFIG_SYS_CCSRBAR + 0xC20000)@l
  594. li r4, 33 /* stash id */
  595. stw r4, 4(r3)
  596. lis r4, (L2CSR0_L2FI|L2CSR0_L2LFC)@h
  597. ori r4, r4, (L2CSR0_L2FI|L2CSR0_L2LFC)@l
  598. sync
  599. stw r4, 0(r3) /* invalidate L2 */
  600. /* Poll till the bits are cleared */
  601. 1: sync
  602. lwz r0, 0(r3)
  603. twi 0, r0, 0
  604. isync
  605. and. r1, r0, r4
  606. bne 1b
  607. /* L2PE must be set before L2 cache is enabled */
  608. lis r4, (L2CSR0_L2PE)@h
  609. ori r4, r4, (L2CSR0_L2PE)@l
  610. sync
  611. stw r4, 0(r3) /* enable L2 parity/ECC error checking */
  612. /* Poll till the bit is set */
  613. 1: sync
  614. lwz r0, 0(r3)
  615. twi 0, r0, 0
  616. isync
  617. and. r1, r0, r4
  618. beq 1b
  619. lis r4, (L2CSR0_L2E|L2CSR0_L2PE)@h
  620. ori r4, r4, (L2CSR0_L2REP_MODE)@l
  621. sync
  622. stw r4, 0(r3) /* enable L2 */
  623. /* Poll till the bit is set */
  624. 1: sync
  625. lwz r0, 0(r3)
  626. twi 0, r0, 0
  627. isync
  628. and. r1, r0, r4
  629. beq 1b
  630. delete_ccsr_l2_tlb:
  631. delete_tlb0_entry 0, CONFIG_SYS_CCSRBAR + 0xC20000, MAS2_I|MAS2_G, r3
  632. #endif
  633. /*
  634. * Enable the L1. On e6500, this has to be done
  635. * after the L2 is up.
  636. */
  637. #ifdef CONFIG_SYS_CACHE_STASHING
  638. /* set stash id to (coreID) * 2 + 32 + L1 CT (0) */
  639. li r2,(32 + 0)
  640. mtspr L1CSR2,r2
  641. #endif
  642. /* Enable/invalidate the I-Cache */
  643. lis r2,(L1CSR1_ICFI|L1CSR1_ICLFR)@h
  644. ori r2,r2,(L1CSR1_ICFI|L1CSR1_ICLFR)@l
  645. mtspr SPRN_L1CSR1,r2
  646. 1:
  647. mfspr r3,SPRN_L1CSR1
  648. and. r1,r3,r2
  649. bne 1b
  650. lis r3,(L1CSR1_CPE|L1CSR1_ICE)@h
  651. ori r3,r3,(L1CSR1_CPE|L1CSR1_ICE)@l
  652. mtspr SPRN_L1CSR1,r3
  653. isync
  654. 2:
  655. mfspr r3,SPRN_L1CSR1
  656. andi. r1,r3,L1CSR1_ICE@l
  657. beq 2b
  658. /* Enable/invalidate the D-Cache */
  659. lis r2,(L1CSR0_DCFI|L1CSR0_DCLFR)@h
  660. ori r2,r2,(L1CSR0_DCFI|L1CSR0_DCLFR)@l
  661. mtspr SPRN_L1CSR0,r2
  662. 1:
  663. mfspr r3,SPRN_L1CSR0
  664. and. r1,r3,r2
  665. bne 1b
  666. lis r3,(L1CSR0_CPE|L1CSR0_DCE)@h
  667. ori r3,r3,(L1CSR0_CPE|L1CSR0_DCE)@l
  668. mtspr SPRN_L1CSR0,r3
  669. isync
  670. 2:
  671. mfspr r3,SPRN_L1CSR0
  672. andi. r1,r3,L1CSR0_DCE@l
  673. beq 2b
  674. #ifdef CONFIG_SYS_FSL_ERRATUM_A004510
  675. #define DCSR_LAWBARH0 (CONFIG_SYS_CCSRBAR + 0x1000)
  676. #define LAW_SIZE_1M 0x13
  677. #define DCSRBAR_LAWAR (LAW_EN | (0x1d << 20) | LAW_SIZE_1M)
  678. cmpwi r27,0
  679. beq 9f
  680. /*
  681. * Create a TLB entry for CCSR
  682. *
  683. * We're executing out of TLB1 entry in r14, and that's the only
  684. * TLB entry that exists. To allocate some TLB entries for our
  685. * own use, flip a bit high enough that we won't flip it again
  686. * via incrementing.
  687. */
  688. xori r8, r14, 32
  689. lis r0, MAS0_TLBSEL(1)@h
  690. rlwimi r0, r8, 16, MAS0_ESEL_MSK
  691. lis r1, FSL_BOOKE_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_16M)@h
  692. ori r1, r1, FSL_BOOKE_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_16M)@l
  693. lis r7, CONFIG_SYS_CCSRBAR@h
  694. ori r7, r7, CONFIG_SYS_CCSRBAR@l
  695. ori r2, r7, MAS2_I|MAS2_G
  696. lis r3, FSL_BOOKE_MAS3(CONFIG_SYS_CCSRBAR_PHYS_LOW, 0, (MAS3_SW|MAS3_SR))@h
  697. ori r3, r3, FSL_BOOKE_MAS3(CONFIG_SYS_CCSRBAR_PHYS_LOW, 0, (MAS3_SW|MAS3_SR))@l
  698. lis r4, CONFIG_SYS_CCSRBAR_PHYS_HIGH@h
  699. ori r4, r4, CONFIG_SYS_CCSRBAR_PHYS_HIGH@l
  700. mtspr MAS0, r0
  701. mtspr MAS1, r1
  702. mtspr MAS2, r2
  703. mtspr MAS3, r3
  704. mtspr MAS7, r4
  705. isync
  706. tlbwe
  707. isync
  708. msync
  709. /* Map DCSR temporarily to physical address zero */
  710. li r0, 0
  711. lis r3, DCSRBAR_LAWAR@h
  712. ori r3, r3, DCSRBAR_LAWAR@l
  713. stw r0, 0xc00(r7) /* LAWBARH0 */
  714. stw r0, 0xc04(r7) /* LAWBARL0 */
  715. sync
  716. stw r3, 0xc08(r7) /* LAWAR0 */
  717. /* Read back from LAWAR to ensure the update is complete. */
  718. lwz r3, 0xc08(r7) /* LAWAR0 */
  719. isync
  720. /* Create a TLB entry for DCSR at zero */
  721. addi r9, r8, 1
  722. lis r0, MAS0_TLBSEL(1)@h
  723. rlwimi r0, r9, 16, MAS0_ESEL_MSK
  724. lis r1, FSL_BOOKE_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_1M)@h
  725. ori r1, r1, FSL_BOOKE_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_1M)@l
  726. li r6, 0 /* DCSR effective address */
  727. ori r2, r6, MAS2_I|MAS2_G
  728. li r3, MAS3_SW|MAS3_SR
  729. li r4, 0
  730. mtspr MAS0, r0
  731. mtspr MAS1, r1
  732. mtspr MAS2, r2
  733. mtspr MAS3, r3
  734. mtspr MAS7, r4
  735. isync
  736. tlbwe
  737. isync
  738. msync
  739. /* enable the timebase */
  740. #define CTBENR 0xe2084
  741. li r3, 1
  742. addis r4, r7, CTBENR@ha
  743. stw r3, CTBENR@l(r4)
  744. lwz r3, CTBENR@l(r4)
  745. twi 0,r3,0
  746. isync
  747. .macro erratum_set_ccsr offset value
  748. addis r3, r7, \offset@ha
  749. lis r4, \value@h
  750. addi r3, r3, \offset@l
  751. ori r4, r4, \value@l
  752. bl erratum_set_value
  753. .endm
  754. .macro erratum_set_dcsr offset value
  755. addis r3, r6, \offset@ha
  756. lis r4, \value@h
  757. addi r3, r3, \offset@l
  758. ori r4, r4, \value@l
  759. bl erratum_set_value
  760. .endm
  761. erratum_set_dcsr 0xb0e08 0xe0201800
  762. erratum_set_dcsr 0xb0e18 0xe0201800
  763. erratum_set_dcsr 0xb0e38 0xe0400000
  764. erratum_set_dcsr 0xb0008 0x00900000
  765. erratum_set_dcsr 0xb0e40 0xe00a0000
  766. erratum_set_ccsr 0x18600 CONFIG_SYS_FSL_CORENET_SNOOPVEC_COREONLY
  767. #ifdef CONFIG_RAMBOOT_PBL
  768. erratum_set_ccsr 0x10f00 0x495e5000
  769. #else
  770. erratum_set_ccsr 0x10f00 0x415e5000
  771. #endif
  772. erratum_set_ccsr 0x11f00 0x415e5000
  773. /* Make temp mapping uncacheable again, if it was initially */
  774. bl 2f
  775. 2: mflr r3
  776. tlbsx 0, r3
  777. mfspr r4, MAS2
  778. rlwimi r4, r15, 0, MAS2_I
  779. rlwimi r4, r15, 0, MAS2_G
  780. mtspr MAS2, r4
  781. isync
  782. tlbwe
  783. isync
  784. msync
  785. /* Clear the cache */
  786. lis r3,(L1CSR1_ICFI|L1CSR1_ICLFR)@h
  787. ori r3,r3,(L1CSR1_ICFI|L1CSR1_ICLFR)@l
  788. sync
  789. isync
  790. mtspr SPRN_L1CSR1,r3
  791. isync
  792. 2: sync
  793. mfspr r4,SPRN_L1CSR1
  794. and. r4,r4,r3
  795. bne 2b
  796. lis r3,(L1CSR1_CPE|L1CSR1_ICE)@h
  797. ori r3,r3,(L1CSR1_CPE|L1CSR1_ICE)@l
  798. sync
  799. isync
  800. mtspr SPRN_L1CSR1,r3
  801. isync
  802. 2: sync
  803. mfspr r4,SPRN_L1CSR1
  804. and. r4,r4,r3
  805. beq 2b
  806. /* Remove temporary mappings */
  807. lis r0, MAS0_TLBSEL(1)@h
  808. rlwimi r0, r9, 16, MAS0_ESEL_MSK
  809. li r3, 0
  810. mtspr MAS0, r0
  811. mtspr MAS1, r3
  812. isync
  813. tlbwe
  814. isync
  815. msync
  816. li r3, 0
  817. stw r3, 0xc08(r7) /* LAWAR0 */
  818. lwz r3, 0xc08(r7)
  819. isync
  820. lis r0, MAS0_TLBSEL(1)@h
  821. rlwimi r0, r8, 16, MAS0_ESEL_MSK
  822. li r3, 0
  823. mtspr MAS0, r0
  824. mtspr MAS1, r3
  825. isync
  826. tlbwe
  827. isync
  828. msync
  829. b 9f
  830. /* r3 = addr, r4 = value, clobbers r5, r11, r12 */
  831. erratum_set_value:
  832. /* Lock two cache lines into I-Cache */
  833. sync
  834. mfspr r11, SPRN_L1CSR1
  835. rlwinm r11, r11, 0, ~L1CSR1_ICUL
  836. sync
  837. isync
  838. mtspr SPRN_L1CSR1, r11
  839. isync
  840. mflr r12
  841. bl 5f
  842. 5: mflr r5
  843. addi r5, r5, 2f - 5b
  844. icbtls 0, 0, r5
  845. addi r5, r5, 64
  846. sync
  847. mfspr r11, SPRN_L1CSR1
  848. 3: andi. r11, r11, L1CSR1_ICUL
  849. bne 3b
  850. icbtls 0, 0, r5
  851. addi r5, r5, 64
  852. sync
  853. mfspr r11, SPRN_L1CSR1
  854. 3: andi. r11, r11, L1CSR1_ICUL
  855. bne 3b
  856. b 2f
  857. .align 6
  858. /* Inside a locked cacheline, wait a while, write, then wait a while */
  859. 2: sync
  860. mfspr r5, SPRN_TBRL
  861. addis r11, r5, 0x10000@h /* wait 65536 timebase ticks */
  862. 4: mfspr r5, SPRN_TBRL
  863. subf. r5, r5, r11
  864. bgt 4b
  865. stw r4, 0(r3)
  866. mfspr r5, SPRN_TBRL
  867. addis r11, r5, 0x10000@h /* wait 65536 timebase ticks */
  868. 4: mfspr r5, SPRN_TBRL
  869. subf. r5, r5, r11
  870. bgt 4b
  871. sync
  872. /*
  873. * Fill out the rest of this cache line and the next with nops,
  874. * to ensure that nothing outside the locked area will be
  875. * fetched due to a branch.
  876. */
  877. .rept 19
  878. nop
  879. .endr
  880. sync
  881. mfspr r11, SPRN_L1CSR1
  882. rlwinm r11, r11, 0, ~L1CSR1_ICUL
  883. sync
  884. isync
  885. mtspr SPRN_L1CSR1, r11
  886. isync
  887. mtlr r12
  888. blr
  889. 9:
  890. #endif
  891. create_init_ram_area:
  892. lis r6,FSL_BOOKE_MAS0(1, 15, 0)@h
  893. ori r6,r6,FSL_BOOKE_MAS0(1, 15, 0)@l
  894. #ifdef NOR_BOOT
  895. /* create a temp mapping in AS=1 to the 4M boot window */
  896. create_tlb1_entry 15, \
  897. 1, BOOKE_PAGESZ_4M, \
  898. CONFIG_SYS_MONITOR_BASE & 0xffc00000, MAS2_I|MAS2_G, \
  899. 0xffc00000, MAS3_SX|MAS3_SW|MAS3_SR, \
  900. 0, r6
  901. #elif !defined(CONFIG_SYS_RAMBOOT) && defined(CONFIG_NXP_ESBC)
  902. /* create a temp mapping in AS = 1 for Flash mapping
  903. * created by PBL for ISBC code
  904. */
  905. create_tlb1_entry 15, \
  906. 1, BOOKE_PAGESZ_1M, \
  907. CONFIG_SYS_MONITOR_BASE & 0xfff00000, MAS2_I|MAS2_G, \
  908. CONFIG_SYS_PBI_FLASH_WINDOW & 0xfff00000, MAS3_SX|MAS3_SW|MAS3_SR, \
  909. 0, r6
  910. /*
  911. * For Targets without CONFIG_SPL like P3, P5
  912. * and for targets with CONFIG_SPL like T1, T2, T4, only for
  913. * u-boot-spl i.e. CONFIG_SPL_BUILD
  914. */
  915. #elif defined(CONFIG_RAMBOOT_PBL) && defined(CONFIG_NXP_ESBC) && \
  916. (!defined(CONFIG_SPL) || defined(CONFIG_SPL_BUILD))
  917. /* create a temp mapping in AS = 1 for mapping CONFIG_SYS_MONITOR_BASE
  918. * to L3 Address configured by PBL for ISBC code
  919. */
  920. create_tlb1_entry 15, \
  921. 1, BOOKE_PAGESZ_1M, \
  922. CONFIG_SYS_MONITOR_BASE & 0xfff00000, MAS2_I|MAS2_G, \
  923. CONFIG_SYS_INIT_L3_ADDR & 0xfff00000, MAS3_SX|MAS3_SW|MAS3_SR, \
  924. 0, r6
  925. #else
  926. /*
  927. * create a temp mapping in AS=1 to the 1M CONFIG_SYS_MONITOR_BASE space, the main
  928. * image has been relocated to CONFIG_SYS_MONITOR_BASE on the second stage.
  929. */
  930. create_tlb1_entry 15, \
  931. 1, BOOKE_PAGESZ_1M, \
  932. CONFIG_SYS_MONITOR_BASE & 0xfff00000, MAS2_I|MAS2_G, \
  933. CONFIG_SYS_MONITOR_BASE & 0xfff00000, MAS3_SX|MAS3_SW|MAS3_SR, \
  934. 0, r6
  935. #endif
  936. /* create a temp mapping in AS=1 to the stack */
  937. #if defined(CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW) && \
  938. defined(CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH)
  939. create_tlb1_entry 14, \
  940. 1, BOOKE_PAGESZ_16K, \
  941. CONFIG_SYS_INIT_RAM_ADDR, 0, \
  942. CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW, MAS3_SX|MAS3_SW|MAS3_SR, \
  943. CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH, r6
  944. #else
  945. create_tlb1_entry 14, \
  946. 1, BOOKE_PAGESZ_16K, \
  947. CONFIG_SYS_INIT_RAM_ADDR, 0, \
  948. CONFIG_SYS_INIT_RAM_ADDR, MAS3_SX|MAS3_SW|MAS3_SR, \
  949. 0, r6
  950. #endif
  951. lis r6,MSR_IS|MSR_DS|MSR_DE@h
  952. ori r6,r6,MSR_IS|MSR_DS|MSR_DE@l
  953. lis r7,switch_as@h
  954. ori r7,r7,switch_as@l
  955. mtspr SPRN_SRR0,r7
  956. mtspr SPRN_SRR1,r6
  957. rfi
  958. switch_as:
  959. /* L1 DCache is used for initial RAM */
  960. /* Allocate Initial RAM in data cache.
  961. */
  962. lis r3,CONFIG_SYS_INIT_RAM_ADDR@h
  963. ori r3,r3,CONFIG_SYS_INIT_RAM_ADDR@l
  964. mfspr r2, L1CFG0
  965. andi. r2, r2, 0x1ff
  966. /* cache size * 1024 / (2 * L1 line size) */
  967. slwi r2, r2, (10 - 1 - L1_CACHE_SHIFT)
  968. mtctr r2
  969. li r0,0
  970. 1:
  971. dcbz r0,r3
  972. #ifdef CONFIG_E6500 /* Lock/unlock L2 cache long with L1 */
  973. dcbtls 2, r0, r3
  974. dcbtls 0, r0, r3
  975. #else
  976. dcbtls 0, r0, r3
  977. #endif
  978. addi r3,r3,CONFIG_SYS_CACHELINE_SIZE
  979. bdnz 1b
  980. /* Jump out the last 4K page and continue to 'normal' start */
  981. #if defined(CONFIG_SYS_RAMBOOT) || defined(CONFIG_SPL)
  982. /* We assume that we're already running at the address we're linked at */
  983. b _start_cont
  984. #else
  985. /* Calculate absolute address in FLASH and jump there */
  986. /*--------------------------------------------------------------*/
  987. lis r3,CONFIG_SYS_MONITOR_BASE@h
  988. ori r3,r3,CONFIG_SYS_MONITOR_BASE@l
  989. addi r3,r3,_start_cont - _start
  990. mtlr r3
  991. blr
  992. #endif
  993. .text
  994. .globl _start
  995. _start:
  996. .long 0x27051956 /* U-BOOT Magic Number */
  997. .globl _start_cont
  998. _start_cont:
  999. /* Setup the stack in initial RAM,could be L2-as-SRAM or L1 dcache*/
  1000. lis r3,(CONFIG_SYS_INIT_RAM_ADDR)@h
  1001. ori r3,r3,((CONFIG_SYS_INIT_SP_OFFSET-16)&~0xf)@l /* Align to 16 */
  1002. #if CONFIG_VAL(SYS_MALLOC_F_LEN)
  1003. #if CONFIG_VAL(SYS_MALLOC_F_LEN) + GENERATED_GBL_DATA_SIZE > CONFIG_SYS_INIT_RAM_SIZE
  1004. #error "SYS_MALLOC_F_LEN too large to fit into initial RAM."
  1005. #endif
  1006. /* Leave 16+ byte for back chain termination and NULL return address */
  1007. subi r3,r3,((CONFIG_VAL(SYS_MALLOC_F_LEN)+16+15)&~0xf)
  1008. #endif
  1009. /* End of RAM */
  1010. lis r4,(CONFIG_SYS_INIT_RAM_ADDR)@h
  1011. ori r4,r4,(CONFIG_SYS_INIT_RAM_SIZE)@l
  1012. li r0,0
  1013. 1: subi r4,r4,4
  1014. stw r0,0(r4)
  1015. cmplw r4,r3
  1016. bne 1b
  1017. #if CONFIG_VAL(SYS_MALLOC_F_LEN)
  1018. lis r4,(CONFIG_SYS_INIT_RAM_ADDR)@h
  1019. ori r4,r4,(CONFIG_SYS_GBL_DATA_OFFSET)@l
  1020. addi r3,r3,16 /* Pre-relocation malloc area */
  1021. stw r3,GD_MALLOC_BASE(r4)
  1022. subi r3,r3,16
  1023. #endif
  1024. li r0,0
  1025. stw r0,0(r3) /* Terminate Back Chain */
  1026. stw r0,+4(r3) /* NULL return address. */
  1027. mr r1,r3 /* Transfer to SP(r1) */
  1028. GET_GOT
  1029. /* Needed for -msingle-pic-base */
  1030. bl _GLOBAL_OFFSET_TABLE_@local-4
  1031. mflr r30
  1032. /* Pass our potential ePAPR device tree pointer to cpu_init_early_f */
  1033. mr r3, r24
  1034. bl cpu_init_early_f
  1035. /* switch back to AS = 0 */
  1036. lis r3,(MSR_CE|MSR_ME|MSR_DE)@h
  1037. ori r3,r3,(MSR_CE|MSR_ME|MSR_DE)@l
  1038. mtmsr r3
  1039. isync
  1040. bl cpu_init_f /* return boot_flag for calling board_init_f */
  1041. bl board_init_f
  1042. isync
  1043. /* NOTREACHED - board_init_f() does not return */
  1044. #ifndef MINIMAL_SPL
  1045. .globl _start_of_vectors
  1046. _start_of_vectors:
  1047. /* Critical input. */
  1048. CRIT_EXCEPTION(0x0100, CriticalInput, CritcalInputException)
  1049. /* Machine check */
  1050. MCK_EXCEPTION(0x200, MachineCheck, MachineCheckException)
  1051. /* Data Storage exception. */
  1052. STD_EXCEPTION(0x0300, DataStorage, UnknownException)
  1053. /* Instruction Storage exception. */
  1054. STD_EXCEPTION(0x0400, InstStorage, UnknownException)
  1055. /* External Interrupt exception. */
  1056. STD_EXCEPTION(0x0500, ExtInterrupt, ExtIntException)
  1057. /* Alignment exception. */
  1058. Alignment:
  1059. EXCEPTION_PROLOG(SRR0, SRR1)
  1060. mfspr r4,DAR
  1061. stw r4,_DAR(r21)
  1062. mfspr r5,DSISR
  1063. stw r5,_DSISR(r21)
  1064. addi r3,r1,STACK_FRAME_OVERHEAD
  1065. EXC_XFER_TEMPLATE(0x600, Alignment, AlignmentException,
  1066. MSR_KERNEL, COPY_EE)
  1067. /* Program check exception */
  1068. ProgramCheck:
  1069. EXCEPTION_PROLOG(SRR0, SRR1)
  1070. addi r3,r1,STACK_FRAME_OVERHEAD
  1071. EXC_XFER_TEMPLATE(0x700, ProgramCheck, ProgramCheckException,
  1072. MSR_KERNEL, COPY_EE)
  1073. /* No FPU on MPC85xx. This exception is not supposed to happen.
  1074. */
  1075. STD_EXCEPTION(0x0800, FPUnavailable, UnknownException)
  1076. STD_EXCEPTION(0x0900, SystemCall, UnknownException)
  1077. STD_EXCEPTION(0x0a00, Decrementer, timer_interrupt)
  1078. STD_EXCEPTION(0x0b00, IntervalTimer, UnknownException)
  1079. STD_EXCEPTION(0x0c00, WatchdogTimer, UnknownException)
  1080. STD_EXCEPTION(0x0d00, DataTLBError, UnknownException)
  1081. STD_EXCEPTION(0x0e00, InstructionTLBError, UnknownException)
  1082. CRIT_EXCEPTION(0x0f00, DebugBreakpoint, DebugException )
  1083. .globl _end_of_vectors
  1084. _end_of_vectors:
  1085. . = . + (0x100 - ( . & 0xff )) /* align for debug */
  1086. /*
  1087. * This code finishes saving the registers to the exception frame
  1088. * and jumps to the appropriate handler for the exception.
  1089. * Register r21 is pointer into trap frame, r1 has new stack pointer.
  1090. * r23 is the address of the handler.
  1091. */
  1092. .globl transfer_to_handler
  1093. transfer_to_handler:
  1094. SAVE_GPR(7, r21)
  1095. SAVE_4GPRS(8, r21)
  1096. SAVE_8GPRS(12, r21)
  1097. SAVE_8GPRS(24, r21)
  1098. li r22,0
  1099. stw r22,RESULT(r21)
  1100. mtspr SPRG2,r22 /* r1 is now kernel sp */
  1101. mtctr r23 /* virtual address of handler */
  1102. mtmsr r20
  1103. bctrl
  1104. int_return:
  1105. mfmsr r28 /* Disable interrupts */
  1106. li r4,0
  1107. ori r4,r4,MSR_EE
  1108. andc r28,r28,r4
  1109. SYNC /* Some chip revs need this... */
  1110. mtmsr r28
  1111. SYNC
  1112. lwz r2,_CTR(r1)
  1113. lwz r0,_LINK(r1)
  1114. mtctr r2
  1115. mtlr r0
  1116. lwz r2,_XER(r1)
  1117. lwz r0,_CCR(r1)
  1118. mtspr XER,r2
  1119. mtcrf 0xFF,r0
  1120. REST_10GPRS(3, r1)
  1121. REST_10GPRS(13, r1)
  1122. REST_8GPRS(23, r1)
  1123. REST_GPR(31, r1)
  1124. lwz r2,_NIP(r1) /* Restore environment */
  1125. lwz r0,_MSR(r1)
  1126. mtspr SRR0,r2
  1127. mtspr SRR1,r0
  1128. lwz r0,GPR0(r1)
  1129. lwz r2,GPR2(r1)
  1130. lwz r1,GPR1(r1)
  1131. SYNC
  1132. rfi
  1133. /* Cache functions.
  1134. */
  1135. .globl flush_icache
  1136. flush_icache:
  1137. .globl invalidate_icache
  1138. invalidate_icache:
  1139. mfspr r0,L1CSR1
  1140. ori r0,r0,L1CSR1_ICFI
  1141. msync
  1142. isync
  1143. mtspr L1CSR1,r0
  1144. isync
  1145. blr /* entire I cache */
  1146. .globl invalidate_dcache
  1147. invalidate_dcache:
  1148. mfspr r0,L1CSR0
  1149. ori r0,r0,L1CSR0_DCFI
  1150. msync
  1151. isync
  1152. mtspr L1CSR0,r0
  1153. isync
  1154. blr
  1155. .globl icache_enable
  1156. icache_enable:
  1157. mflr r8
  1158. bl invalidate_icache
  1159. mtlr r8
  1160. isync
  1161. mfspr r4,L1CSR1
  1162. ori r4,r4,(L1CSR1_CPE | L1CSR1_ICE)@l
  1163. oris r4,r4,(L1CSR1_CPE | L1CSR1_ICE)@h
  1164. mtspr L1CSR1,r4
  1165. isync
  1166. blr
  1167. .globl icache_disable
  1168. icache_disable:
  1169. mfspr r0,L1CSR1
  1170. lis r3,0
  1171. ori r3,r3,L1CSR1_ICE
  1172. andc r0,r0,r3
  1173. mtspr L1CSR1,r0
  1174. isync
  1175. blr
  1176. .globl icache_status
  1177. icache_status:
  1178. mfspr r3,L1CSR1
  1179. andi. r3,r3,L1CSR1_ICE
  1180. blr
  1181. .globl dcache_enable
  1182. dcache_enable:
  1183. mflr r8
  1184. bl invalidate_dcache
  1185. mtlr r8
  1186. isync
  1187. mfspr r0,L1CSR0
  1188. ori r0,r0,(L1CSR0_CPE | L1CSR0_DCE)@l
  1189. oris r0,r0,(L1CSR0_CPE | L1CSR0_DCE)@h
  1190. msync
  1191. isync
  1192. mtspr L1CSR0,r0
  1193. isync
  1194. blr
  1195. .globl dcache_disable
  1196. dcache_disable:
  1197. mfspr r3,L1CSR0
  1198. lis r4,0
  1199. ori r4,r4,L1CSR0_DCE
  1200. andc r3,r3,r4
  1201. mtspr L1CSR0,r3
  1202. isync
  1203. blr
  1204. .globl dcache_status
  1205. dcache_status:
  1206. mfspr r3,L1CSR0
  1207. andi. r3,r3,L1CSR0_DCE
  1208. blr
  1209. /*------------------------------------------------------------------------------- */
  1210. /* Function: in8 */
  1211. /* Description: Input 8 bits */
  1212. /*------------------------------------------------------------------------------- */
  1213. .globl in8
  1214. in8:
  1215. lbz r3,0x0000(r3)
  1216. blr
  1217. /*------------------------------------------------------------------------------- */
  1218. /* Function: out8 */
  1219. /* Description: Output 8 bits */
  1220. /*------------------------------------------------------------------------------- */
  1221. .globl out8
  1222. out8:
  1223. stb r4,0x0000(r3)
  1224. sync
  1225. blr
  1226. /*------------------------------------------------------------------------------- */
  1227. /* Function: out16 */
  1228. /* Description: Output 16 bits */
  1229. /*------------------------------------------------------------------------------- */
  1230. .globl out16
  1231. out16:
  1232. sth r4,0x0000(r3)
  1233. sync
  1234. blr
  1235. /*------------------------------------------------------------------------------- */
  1236. /* Function: out16r */
  1237. /* Description: Byte reverse and output 16 bits */
  1238. /*------------------------------------------------------------------------------- */
  1239. .globl out16r
  1240. out16r:
  1241. sthbrx r4,r0,r3
  1242. sync
  1243. blr
  1244. /*------------------------------------------------------------------------------- */
  1245. /* Function: out32 */
  1246. /* Description: Output 32 bits */
  1247. /*------------------------------------------------------------------------------- */
  1248. .globl out32
  1249. out32:
  1250. stw r4,0x0000(r3)
  1251. sync
  1252. blr
  1253. /*------------------------------------------------------------------------------- */
  1254. /* Function: out32r */
  1255. /* Description: Byte reverse and output 32 bits */
  1256. /*------------------------------------------------------------------------------- */
  1257. .globl out32r
  1258. out32r:
  1259. stwbrx r4,r0,r3
  1260. sync
  1261. blr
  1262. /*------------------------------------------------------------------------------- */
  1263. /* Function: in16 */
  1264. /* Description: Input 16 bits */
  1265. /*------------------------------------------------------------------------------- */
  1266. .globl in16
  1267. in16:
  1268. lhz r3,0x0000(r3)
  1269. blr
  1270. /*------------------------------------------------------------------------------- */
  1271. /* Function: in16r */
  1272. /* Description: Input 16 bits and byte reverse */
  1273. /*------------------------------------------------------------------------------- */
  1274. .globl in16r
  1275. in16r:
  1276. lhbrx r3,r0,r3
  1277. blr
  1278. /*------------------------------------------------------------------------------- */
  1279. /* Function: in32 */
  1280. /* Description: Input 32 bits */
  1281. /*------------------------------------------------------------------------------- */
  1282. .globl in32
  1283. in32:
  1284. lwz 3,0x0000(3)
  1285. blr
  1286. /*------------------------------------------------------------------------------- */
  1287. /* Function: in32r */
  1288. /* Description: Input 32 bits and byte reverse */
  1289. /*------------------------------------------------------------------------------- */
  1290. .globl in32r
  1291. in32r:
  1292. lwbrx r3,r0,r3
  1293. blr
  1294. #endif /* !MINIMAL_SPL */
  1295. /*------------------------------------------------------------------------------*/
  1296. /*
  1297. * void write_tlb(mas0, mas1, mas2, mas3, mas7)
  1298. */
  1299. .globl write_tlb
  1300. write_tlb:
  1301. mtspr MAS0,r3
  1302. mtspr MAS1,r4
  1303. mtspr MAS2,r5
  1304. mtspr MAS3,r6
  1305. #ifdef CONFIG_ENABLE_36BIT_PHYS
  1306. mtspr MAS7,r7
  1307. #endif
  1308. li r3,0
  1309. #ifdef CONFIG_SYS_BOOK3E_HV
  1310. mtspr MAS8,r3
  1311. #endif
  1312. isync
  1313. tlbwe
  1314. msync
  1315. isync
  1316. blr
  1317. /*
  1318. * void relocate_code(addr_sp, gd, addr_moni)
  1319. *
  1320. * This "function" does not return, instead it continues in RAM
  1321. * after relocating the monitor code.
  1322. *
  1323. * r3 = dest
  1324. * r4 = src
  1325. * r5 = length in bytes
  1326. * r6 = cachelinesize
  1327. */
  1328. .globl relocate_code
  1329. relocate_code:
  1330. mr r1,r3 /* Set new stack pointer */
  1331. mr r9,r4 /* Save copy of Init Data pointer */
  1332. mr r10,r5 /* Save copy of Destination Address */
  1333. GET_GOT
  1334. #ifndef CONFIG_SPL_SKIP_RELOCATE
  1335. mr r3,r5 /* Destination Address */
  1336. lis r4,CONFIG_SYS_MONITOR_BASE@h /* Source Address */
  1337. ori r4,r4,CONFIG_SYS_MONITOR_BASE@l
  1338. lwz r5,GOT(__init_end)
  1339. sub r5,r5,r4
  1340. li r6,CONFIG_SYS_CACHELINE_SIZE /* Cache Line Size */
  1341. /*
  1342. * Fix GOT pointer:
  1343. *
  1344. * New GOT-PTR = (old GOT-PTR - CONFIG_SYS_MONITOR_BASE) + Destination Address
  1345. *
  1346. * Offset:
  1347. */
  1348. sub r15,r10,r4
  1349. /* First our own GOT */
  1350. add r12,r12,r15
  1351. /* the the one used by the C code */
  1352. add r30,r30,r15
  1353. /*
  1354. * Now relocate code
  1355. */
  1356. cmplw cr1,r3,r4
  1357. addi r0,r5,3
  1358. srwi. r0,r0,2
  1359. beq cr1,4f /* In place copy is not necessary */
  1360. beq 7f /* Protect against 0 count */
  1361. mtctr r0
  1362. bge cr1,2f
  1363. la r8,-4(r4)
  1364. la r7,-4(r3)
  1365. 1: lwzu r0,4(r8)
  1366. stwu r0,4(r7)
  1367. bdnz 1b
  1368. b 4f
  1369. 2: slwi r0,r0,2
  1370. add r8,r4,r0
  1371. add r7,r3,r0
  1372. 3: lwzu r0,-4(r8)
  1373. stwu r0,-4(r7)
  1374. bdnz 3b
  1375. /*
  1376. * Now flush the cache: note that we must start from a cache aligned
  1377. * address. Otherwise we might miss one cache line.
  1378. */
  1379. 4: cmpwi r6,0
  1380. add r5,r3,r5
  1381. beq 7f /* Always flush prefetch queue in any case */
  1382. subi r0,r6,1
  1383. andc r3,r3,r0
  1384. mr r4,r3
  1385. 5: dcbst 0,r4
  1386. add r4,r4,r6
  1387. cmplw r4,r5
  1388. blt 5b
  1389. sync /* Wait for all dcbst to complete on bus */
  1390. mr r4,r3
  1391. 6: icbi 0,r4
  1392. add r4,r4,r6
  1393. cmplw r4,r5
  1394. blt 6b
  1395. 7: sync /* Wait for all icbi to complete on bus */
  1396. isync
  1397. /*
  1398. * We are done. Do not return, instead branch to second part of board
  1399. * initialization, now running from RAM.
  1400. */
  1401. addi r0,r10,in_ram - _start
  1402. /*
  1403. * As IVPR is going to point RAM address,
  1404. * Make sure IVOR15 has valid opcode to support debugger
  1405. */
  1406. mtspr IVOR15,r0
  1407. /*
  1408. * Re-point the IVPR at RAM
  1409. */
  1410. mtspr IVPR,r10
  1411. mtlr r0
  1412. blr /* NEVER RETURNS! */
  1413. #endif
  1414. .globl in_ram
  1415. in_ram:
  1416. /*
  1417. * Relocation Function, r12 point to got2+0x8000
  1418. *
  1419. * Adjust got2 pointers, no need to check for 0, this code
  1420. * already puts a few entries in the table.
  1421. */
  1422. li r0,__got2_entries@sectoff@l
  1423. la r3,GOT(_GOT2_TABLE_)
  1424. lwz r11,GOT(_GOT2_TABLE_)
  1425. mtctr r0
  1426. sub r11,r3,r11
  1427. addi r3,r3,-4
  1428. 1: lwzu r0,4(r3)
  1429. cmpwi r0,0
  1430. beq- 2f
  1431. add r0,r0,r11
  1432. stw r0,0(r3)
  1433. 2: bdnz 1b
  1434. /*
  1435. * Now adjust the fixups and the pointers to the fixups
  1436. * in case we need to move ourselves again.
  1437. */
  1438. li r0,__fixup_entries@sectoff@l
  1439. lwz r3,GOT(_FIXUP_TABLE_)
  1440. cmpwi r0,0
  1441. mtctr r0
  1442. addi r3,r3,-4
  1443. beq 4f
  1444. 3: lwzu r4,4(r3)
  1445. lwzux r0,r4,r11
  1446. cmpwi r0,0
  1447. add r0,r0,r11
  1448. stw r4,0(r3)
  1449. beq- 5f
  1450. stw r0,0(r4)
  1451. 5: bdnz 3b
  1452. 4:
  1453. clear_bss:
  1454. /*
  1455. * Now clear BSS segment
  1456. */
  1457. lwz r3,GOT(__bss_start)
  1458. lwz r4,GOT(__bss_end)
  1459. cmplw 0,r3,r4
  1460. beq 6f
  1461. li r0,0
  1462. 5:
  1463. stw r0,0(r3)
  1464. addi r3,r3,4
  1465. cmplw 0,r3,r4
  1466. blt 5b
  1467. 6:
  1468. mr r3,r9 /* Init Data pointer */
  1469. mr r4,r10 /* Destination Address */
  1470. bl board_init_r
  1471. #ifndef MINIMAL_SPL
  1472. /*
  1473. * Copy exception vector code to low memory
  1474. *
  1475. * r3: dest_addr
  1476. * r7: source address, r8: end address, r9: target address
  1477. */
  1478. .globl trap_init
  1479. trap_init:
  1480. mflr r11
  1481. bl _GLOBAL_OFFSET_TABLE_-4
  1482. mflr r12
  1483. /* Update IVORs as per relocation */
  1484. mtspr IVPR,r3
  1485. lwz r4,CriticalInput@got(r12)
  1486. mtspr IVOR0,r4 /* 0: Critical input */
  1487. lwz r4,MachineCheck@got(r12)
  1488. mtspr IVOR1,r4 /* 1: Machine check */
  1489. lwz r4,DataStorage@got(r12)
  1490. mtspr IVOR2,r4 /* 2: Data storage */
  1491. lwz r4,InstStorage@got(r12)
  1492. mtspr IVOR3,r4 /* 3: Instruction storage */
  1493. lwz r4,ExtInterrupt@got(r12)
  1494. mtspr IVOR4,r4 /* 4: External interrupt */
  1495. lwz r4,Alignment@got(r12)
  1496. mtspr IVOR5,r4 /* 5: Alignment */
  1497. lwz r4,ProgramCheck@got(r12)
  1498. mtspr IVOR6,r4 /* 6: Program check */
  1499. lwz r4,FPUnavailable@got(r12)
  1500. mtspr IVOR7,r4 /* 7: floating point unavailable */
  1501. lwz r4,SystemCall@got(r12)
  1502. mtspr IVOR8,r4 /* 8: System call */
  1503. /* 9: Auxiliary processor unavailable(unsupported) */
  1504. lwz r4,Decrementer@got(r12)
  1505. mtspr IVOR10,r4 /* 10: Decrementer */
  1506. lwz r4,IntervalTimer@got(r12)
  1507. mtspr IVOR11,r4 /* 11: Interval timer */
  1508. lwz r4,WatchdogTimer@got(r12)
  1509. mtspr IVOR12,r4 /* 12: Watchdog timer */
  1510. lwz r4,DataTLBError@got(r12)
  1511. mtspr IVOR13,r4 /* 13: Data TLB error */
  1512. lwz r4,InstructionTLBError@got(r12)
  1513. mtspr IVOR14,r4 /* 14: Instruction TLB error */
  1514. lwz r4,DebugBreakpoint@got(r12)
  1515. mtspr IVOR15,r4 /* 15: Debug */
  1516. mtlr r11
  1517. blr
  1518. .globl unlock_ram_in_cache
  1519. unlock_ram_in_cache:
  1520. /* invalidate the INIT_RAM section */
  1521. lis r3,(CONFIG_SYS_INIT_RAM_ADDR & ~(CONFIG_SYS_CACHELINE_SIZE-1))@h
  1522. ori r3,r3,(CONFIG_SYS_INIT_RAM_ADDR & ~(CONFIG_SYS_CACHELINE_SIZE-1))@l
  1523. mfspr r4,L1CFG0
  1524. andi. r4,r4,0x1ff
  1525. slwi r4,r4,(10 - 1 - L1_CACHE_SHIFT)
  1526. mtctr r4
  1527. 1: dcbi r0,r3
  1528. #ifdef CONFIG_E6500 /* lock/unlock L2 cache long with L1 */
  1529. dcblc 2, r0, r3
  1530. dcblc 0, r0, r3
  1531. #else
  1532. dcblc r0,r3
  1533. #endif
  1534. addi r3,r3,CONFIG_SYS_CACHELINE_SIZE
  1535. bdnz 1b
  1536. sync
  1537. /* Invalidate the TLB entries for the cache */
  1538. lis r3,CONFIG_SYS_INIT_RAM_ADDR@h
  1539. ori r3,r3,CONFIG_SYS_INIT_RAM_ADDR@l
  1540. tlbivax 0,r3
  1541. addi r3,r3,0x1000
  1542. tlbivax 0,r3
  1543. addi r3,r3,0x1000
  1544. tlbivax 0,r3
  1545. addi r3,r3,0x1000
  1546. tlbivax 0,r3
  1547. isync
  1548. blr
  1549. .globl flush_dcache
  1550. flush_dcache:
  1551. mfspr r3,SPRN_L1CFG0
  1552. rlwinm r5,r3,9,3 /* Extract cache block size */
  1553. twlgti r5,1 /* Only 32 and 64 byte cache blocks
  1554. * are currently defined.
  1555. */
  1556. li r4,32
  1557. subfic r6,r5,2 /* r6 = log2(1KiB / cache block size) -
  1558. * log2(number of ways)
  1559. */
  1560. slw r5,r4,r5 /* r5 = cache block size */
  1561. rlwinm r7,r3,0,0xff /* Extract number of KiB in the cache */
  1562. mulli r7,r7,13 /* An 8-way cache will require 13
  1563. * loads per set.
  1564. */
  1565. slw r7,r7,r6
  1566. /* save off HID0 and set DCFA */
  1567. mfspr r8,SPRN_HID0
  1568. ori r9,r8,HID0_DCFA@l
  1569. mtspr SPRN_HID0,r9
  1570. isync
  1571. lis r4,0
  1572. mtctr r7
  1573. 1: lwz r3,0(r4) /* Load... */
  1574. add r4,r4,r5
  1575. bdnz 1b
  1576. msync
  1577. lis r4,0
  1578. mtctr r7
  1579. 1: dcbf 0,r4 /* ...and flush. */
  1580. add r4,r4,r5
  1581. bdnz 1b
  1582. /* restore HID0 */
  1583. mtspr SPRN_HID0,r8
  1584. isync
  1585. blr
  1586. #endif /* !MINIMAL_SPL */