lowlevel.S 9.0 KB

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  1. /* SPDX-License-Identifier: GPL-2.0+ */
  2. /*
  3. * (C) Copyright 2014-2015 Freescale Semiconductor
  4. * Copyright 2019 NXP
  5. *
  6. * Extracted from armv8/start.S
  7. */
  8. #include <config.h>
  9. #include <linux/linkage.h>
  10. #include <asm/gic.h>
  11. #include <asm/macro.h>
  12. #include <asm/arch-fsl-layerscape/soc.h>
  13. #ifdef CONFIG_FSL_LSCH3
  14. #include <asm/arch-fsl-layerscape/immap_lsch3.h>
  15. #endif
  16. #include <asm/u-boot.h>
  17. .align 3
  18. .weak secondary_boot_addr
  19. secondary_boot_addr:
  20. .quad 0
  21. /* Get GIC offset
  22. * For LS1043a rev1.0, GIC base address align with 4k.
  23. * For LS1043a rev1.1, if DCFG_GIC400_ALIGN[GIC_ADDR_BIT]
  24. * is set, GIC base address align with 4K, or else align
  25. * with 64k.
  26. * output:
  27. * x0: the base address of GICD
  28. * x1: the base address of GICC
  29. */
  30. ENTRY(get_gic_offset)
  31. ldr x0, =GICD_BASE
  32. #ifdef CONFIG_GICV2
  33. ldr x1, =GICC_BASE
  34. #endif
  35. #ifdef CONFIG_HAS_FEATURE_GIC64K_ALIGN
  36. ldr x2, =DCFG_CCSR_SVR
  37. ldr w2, [x2]
  38. rev w2, w2
  39. lsr w3, w2, #16
  40. ldr w4, =SVR_DEV(SVR_LS1043A)
  41. cmp w3, w4
  42. b.ne 1f
  43. ands w2, w2, #0xff
  44. cmp w2, #REV1_0
  45. b.eq 1f
  46. ldr x2, =SCFG_GIC400_ALIGN
  47. ldr w2, [x2]
  48. rev w2, w2
  49. tbnz w2, #GIC_ADDR_BIT, 1f
  50. ldr x0, =GICD_BASE_64K
  51. #ifdef CONFIG_GICV2
  52. ldr x1, =GICC_BASE_64K
  53. #endif
  54. 1:
  55. #endif
  56. ret
  57. ENDPROC(get_gic_offset)
  58. ENTRY(smp_kick_all_cpus)
  59. /* Kick secondary cpus up by SGI 0 interrupt */
  60. #if defined(CONFIG_GICV2) || defined(CONFIG_GICV3)
  61. mov x29, lr /* Save LR */
  62. bl get_gic_offset
  63. bl gic_kick_secondary_cpus
  64. mov lr, x29 /* Restore LR */
  65. #endif
  66. ret
  67. ENDPROC(smp_kick_all_cpus)
  68. ENTRY(lowlevel_init)
  69. mov x29, lr /* Save LR */
  70. /* unmask SError and abort */
  71. msr daifclr, #4
  72. /* Set HCR_EL2[AMO] so SError @EL2 is taken */
  73. mrs x0, hcr_el2
  74. orr x0, x0, #0x20 /* AMO */
  75. msr hcr_el2, x0
  76. isb
  77. switch_el x1, 1f, 100f, 100f /* skip if not in EL3 */
  78. 1:
  79. #if defined (CONFIG_SYS_FSL_HAS_CCN504)
  80. /* Set Wuo bit for RN-I 20 */
  81. #ifdef CONFIG_ARCH_LS2080A
  82. ldr x0, =CCI_AUX_CONTROL_BASE(20)
  83. ldr x1, =0x00000010
  84. bl ccn504_set_aux
  85. /*
  86. * Set forced-order mode in RNI-6, RNI-20
  87. * This is required for performance optimization on LS2088A
  88. * LS2080A family does not support setting forced-order mode,
  89. * so skip this operation for LS2080A family
  90. */
  91. bl get_svr
  92. lsr w0, w0, #16
  93. ldr w1, =SVR_DEV(SVR_LS2080A)
  94. cmp w0, w1
  95. b.eq 1f
  96. ldr x0, =CCI_AUX_CONTROL_BASE(6)
  97. ldr x1, =0x00000020
  98. bl ccn504_set_aux
  99. ldr x0, =CCI_AUX_CONTROL_BASE(20)
  100. ldr x1, =0x00000020
  101. bl ccn504_set_aux
  102. 1:
  103. #endif
  104. /* Add fully-coherent masters to DVM domain */
  105. ldr x0, =CCI_MN_BASE
  106. ldr x1, =CCI_MN_RNF_NODEID_LIST
  107. ldr x2, =CCI_MN_DVM_DOMAIN_CTL_SET
  108. bl ccn504_add_masters_to_dvm
  109. /* Set all RN-I ports to QoS of 15 */
  110. ldr x0, =CCI_S0_QOS_CONTROL_BASE(0)
  111. ldr x1, =0x00FF000C
  112. bl ccn504_set_qos
  113. ldr x0, =CCI_S1_QOS_CONTROL_BASE(0)
  114. ldr x1, =0x00FF000C
  115. bl ccn504_set_qos
  116. ldr x0, =CCI_S2_QOS_CONTROL_BASE(0)
  117. ldr x1, =0x00FF000C
  118. bl ccn504_set_qos
  119. ldr x0, =CCI_S0_QOS_CONTROL_BASE(2)
  120. ldr x1, =0x00FF000C
  121. bl ccn504_set_qos
  122. ldr x0, =CCI_S1_QOS_CONTROL_BASE(2)
  123. ldr x1, =0x00FF000C
  124. bl ccn504_set_qos
  125. ldr x0, =CCI_S2_QOS_CONTROL_BASE(2)
  126. ldr x1, =0x00FF000C
  127. bl ccn504_set_qos
  128. ldr x0, =CCI_S0_QOS_CONTROL_BASE(6)
  129. ldr x1, =0x00FF000C
  130. bl ccn504_set_qos
  131. ldr x0, =CCI_S1_QOS_CONTROL_BASE(6)
  132. ldr x1, =0x00FF000C
  133. bl ccn504_set_qos
  134. ldr x0, =CCI_S2_QOS_CONTROL_BASE(6)
  135. ldr x1, =0x00FF000C
  136. bl ccn504_set_qos
  137. ldr x0, =CCI_S0_QOS_CONTROL_BASE(12)
  138. ldr x1, =0x00FF000C
  139. bl ccn504_set_qos
  140. ldr x0, =CCI_S1_QOS_CONTROL_BASE(12)
  141. ldr x1, =0x00FF000C
  142. bl ccn504_set_qos
  143. ldr x0, =CCI_S2_QOS_CONTROL_BASE(12)
  144. ldr x1, =0x00FF000C
  145. bl ccn504_set_qos
  146. ldr x0, =CCI_S0_QOS_CONTROL_BASE(16)
  147. ldr x1, =0x00FF000C
  148. bl ccn504_set_qos
  149. ldr x0, =CCI_S1_QOS_CONTROL_BASE(16)
  150. ldr x1, =0x00FF000C
  151. bl ccn504_set_qos
  152. ldr x0, =CCI_S2_QOS_CONTROL_BASE(16)
  153. ldr x1, =0x00FF000C
  154. bl ccn504_set_qos
  155. ldr x0, =CCI_S0_QOS_CONTROL_BASE(20)
  156. ldr x1, =0x00FF000C
  157. bl ccn504_set_qos
  158. ldr x0, =CCI_S1_QOS_CONTROL_BASE(20)
  159. ldr x1, =0x00FF000C
  160. bl ccn504_set_qos
  161. ldr x0, =CCI_S2_QOS_CONTROL_BASE(20)
  162. ldr x1, =0x00FF000C
  163. bl ccn504_set_qos
  164. #endif /* CONFIG_SYS_FSL_HAS_CCN504 */
  165. #ifdef SMMU_BASE
  166. /* Set the SMMU page size in the sACR register */
  167. ldr x1, =SMMU_BASE
  168. ldr w0, [x1, #0x10]
  169. orr w0, w0, #1 << 16 /* set sACR.pagesize to indicate 64K page */
  170. str w0, [x1, #0x10]
  171. #endif
  172. /* Initialize GIC Secure Bank Status */
  173. #if !defined(CONFIG_SPL_BUILD)
  174. #if defined(CONFIG_GICV2) || defined(CONFIG_GICV3)
  175. branch_if_slave x0, 1f
  176. bl get_gic_offset
  177. bl gic_init_secure
  178. 1:
  179. #ifdef CONFIG_GICV3
  180. ldr x0, =GICR_BASE
  181. bl gic_init_secure_percpu
  182. #elif defined(CONFIG_GICV2)
  183. bl get_gic_offset
  184. bl gic_init_secure_percpu
  185. #endif
  186. #endif
  187. #endif
  188. 100:
  189. branch_if_master x0, x1, 2f
  190. #if defined(CONFIG_MP) && defined(CONFIG_ARMV8_MULTIENTRY)
  191. /*
  192. * Formerly, here was a jump to secondary_boot_func, but we just
  193. * return early here and let the generic code in start.S handle
  194. * the jump to secondary_boot_func.
  195. */
  196. mov lr, x29 /* Restore LR */
  197. ret
  198. #endif
  199. 2:
  200. switch_el x1, 1f, 100f, 100f /* skip if not in EL3 */
  201. 1:
  202. #ifdef CONFIG_FSL_TZPC_BP147
  203. /* Set Non Secure access for all devices protected via TZPC */
  204. ldr x1, =TZPCDECPROT_0_SET_BASE /* Decode Protection-0 Set Reg */
  205. orr w0, w0, #1 << 3 /* DCFG_RESET is accessible from NS world */
  206. str w0, [x1]
  207. isb
  208. dsb sy
  209. #endif
  210. #ifdef CONFIG_FSL_TZASC_400
  211. /*
  212. * LS2080 and its personalities does not support TZASC
  213. * So skip TZASC related operations
  214. */
  215. bl get_svr
  216. lsr w0, w0, #16
  217. ldr w1, =SVR_DEV(SVR_LS2080A)
  218. cmp w0, w1
  219. b.eq 1f
  220. /* Set TZASC so that:
  221. * a. We use only Region0 whose global secure write/read is EN
  222. * b. We use only Region0 whose NSAID write/read is EN
  223. *
  224. * NOTE: As per the CCSR map doc, TZASC 3 and TZASC 4 are just
  225. * placeholders.
  226. */
  227. .macro tzasc_prog, xreg
  228. mov x12, TZASC1_BASE
  229. mov x16, #0x10000
  230. mul x14, \xreg, x16
  231. add x14, x14,x12
  232. mov x1, #0x8
  233. add x1, x1, x14
  234. ldr w0, [x1] /* Filter 0 Gate Keeper Register */
  235. orr w0, w0, #1 << 0 /* Set open_request for Filter 0 */
  236. str w0, [x1]
  237. mov x1, #0x110
  238. add x1, x1, x14
  239. ldr w0, [x1] /* Region-0 Attributes Register */
  240. orr w0, w0, #1 << 31 /* Set Sec global write en, Bit[31] */
  241. orr w0, w0, #1 << 30 /* Set Sec global read en, Bit[30] */
  242. str w0, [x1]
  243. mov x1, #0x114
  244. add x1, x1, x14
  245. ldr w0, [x1] /* Region-0 Access Register */
  246. mov w0, #0xFFFFFFFF /* Set nsaid_wr_en and nsaid_rd_en */
  247. str w0, [x1]
  248. .endm
  249. #ifdef CONFIG_FSL_TZASC_1
  250. mov x13, #0
  251. tzasc_prog x13
  252. #endif
  253. #ifdef CONFIG_FSL_TZASC_2
  254. mov x13, #1
  255. tzasc_prog x13
  256. #endif
  257. isb
  258. dsb sy
  259. #endif
  260. 100:
  261. 1:
  262. #ifdef CONFIG_ARCH_LS1046A
  263. switch_el x1, 1f, 100f, 100f /* skip if not in EL3 */
  264. 1:
  265. /* Initialize the L2 RAM latency */
  266. mrs x1, S3_1_c11_c0_2
  267. mov x0, #0x1C7
  268. /* Clear L2 Tag RAM latency and L2 Data RAM latency */
  269. bic x1, x1, x0
  270. /* Set L2 data ram latency bits [2:0] */
  271. orr x1, x1, #0x2
  272. /* set L2 tag ram latency bits [8:6] */
  273. orr x1, x1, #0x80
  274. msr S3_1_c11_c0_2, x1
  275. isb
  276. 100:
  277. #endif
  278. #if !defined(CONFIG_TFABOOT) && \
  279. (defined(CONFIG_FSL_LSCH2) && !defined(CONFIG_SPL_BUILD))
  280. bl fsl_ocram_init
  281. #endif
  282. mov lr, x29 /* Restore LR */
  283. ret
  284. ENDPROC(lowlevel_init)
  285. #if defined(CONFIG_FSL_LSCH2) && !defined(CONFIG_SPL_BUILD)
  286. ENTRY(fsl_ocram_init)
  287. mov x28, lr /* Save LR */
  288. bl fsl_clear_ocram
  289. bl fsl_ocram_clear_ecc_err
  290. mov lr, x28 /* Restore LR */
  291. ret
  292. ENDPROC(fsl_ocram_init)
  293. ENTRY(fsl_clear_ocram)
  294. /* Clear OCRAM */
  295. ldr x0, =CONFIG_SYS_FSL_OCRAM_BASE
  296. ldr x1, =(CONFIG_SYS_FSL_OCRAM_BASE + CONFIG_SYS_FSL_OCRAM_SIZE)
  297. mov x2, #0
  298. clear_loop:
  299. str x2, [x0]
  300. add x0, x0, #8
  301. cmp x0, x1
  302. b.lo clear_loop
  303. ret
  304. ENDPROC(fsl_clear_ocram)
  305. ENTRY(fsl_ocram_clear_ecc_err)
  306. /* OCRAM1/2 ECC status bit */
  307. mov w1, #0x60
  308. ldr x0, =DCSR_DCFG_SBEESR2
  309. str w1, [x0]
  310. ldr x0, =DCSR_DCFG_MBEESR2
  311. str w1, [x0]
  312. ret
  313. ENDPROC(fsl_ocram_init)
  314. #endif
  315. #ifdef CONFIG_FSL_LSCH3
  316. .globl get_svr
  317. get_svr:
  318. ldr x1, =FSL_LSCH3_SVR
  319. ldr w0, [x1]
  320. ret
  321. #endif
  322. #if defined(CONFIG_SYS_FSL_HAS_CCN504) || defined(CONFIG_SYS_FSL_HAS_CCN508)
  323. hnf_pstate_poll:
  324. /* x0 has the desired status, return only if operation succeed
  325. * clobber x1, x2, x6
  326. */
  327. mov x1, x0
  328. mov w6, #8 /* HN-F node count */
  329. mov x0, #0x18
  330. movk x0, #0x420, lsl #16 /* HNF0_PSTATE_STATUS */
  331. 1:
  332. ldr x2, [x0]
  333. cmp x2, x1 /* check status */
  334. b.eq 2f
  335. b 1b
  336. 2:
  337. add x0, x0, #0x10000 /* move to next node */
  338. subs w6, w6, #1
  339. cbnz w6, 1b
  340. ret
  341. hnf_set_pstate:
  342. /* x0 has the desired state, clobber x1, x2, x6 */
  343. mov x1, x0
  344. /* power state to SFONLY */
  345. mov w6, #8 /* HN-F node count */
  346. mov x0, #0x10
  347. movk x0, #0x420, lsl #16 /* HNF0_PSTATE_REQ */
  348. 1: /* set pstate to sfonly */
  349. ldr x2, [x0]
  350. and x2, x2, #0xfffffffffffffffc /* & HNFPSTAT_MASK */
  351. orr x2, x2, x1
  352. str x2, [x0]
  353. add x0, x0, #0x10000 /* move to next node */
  354. subs w6, w6, #1
  355. cbnz w6, 1b
  356. ret
  357. ENTRY(__asm_flush_l3_dcache)
  358. /*
  359. * Return status in x0
  360. * success 0
  361. */
  362. mov x29, lr
  363. dsb sy
  364. mov x0, #0x1 /* HNFPSTAT_SFONLY */
  365. bl hnf_set_pstate
  366. mov x0, #0x4 /* SFONLY status */
  367. bl hnf_pstate_poll
  368. dsb sy
  369. mov x0, #0x3 /* HNFPSTAT_FAM */
  370. bl hnf_set_pstate
  371. mov x0, #0xc /* FAM status */
  372. bl hnf_pstate_poll
  373. mov x0, #0
  374. mov lr, x29
  375. ret
  376. ENDPROC(__asm_flush_l3_dcache)
  377. #endif /* CONFIG_SYS_FSL_HAS_CCN504 */