clk-pllv3.c 7.4 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright (C) 2019 DENX Software Engineering
  4. * Lukasz Majewski, DENX Software Engineering, lukma@denx.de
  5. */
  6. #include <common.h>
  7. #include <asm/io.h>
  8. #include <div64.h>
  9. #include <malloc.h>
  10. #include <clk-uclass.h>
  11. #include <dm/device.h>
  12. #include <dm/devres.h>
  13. #include <dm/uclass.h>
  14. #include <clk.h>
  15. #include "clk.h"
  16. #include <linux/err.h>
  17. #define UBOOT_DM_CLK_IMX_PLLV3_GENERIC "imx_clk_pllv3_generic"
  18. #define UBOOT_DM_CLK_IMX_PLLV3_SYS "imx_clk_pllv3_sys"
  19. #define UBOOT_DM_CLK_IMX_PLLV3_USB "imx_clk_pllv3_usb"
  20. #define UBOOT_DM_CLK_IMX_PLLV3_AV "imx_clk_pllv3_av"
  21. #define UBOOT_DM_CLK_IMX_PLLV3_ENET "imx_clk_pllv3_enet"
  22. #define PLL_NUM_OFFSET 0x10
  23. #define PLL_DENOM_OFFSET 0x20
  24. #define BM_PLL_POWER (0x1 << 12)
  25. #define BM_PLL_ENABLE (0x1 << 13)
  26. #define BM_PLL_LOCK (0x1 << 31)
  27. struct clk_pllv3 {
  28. struct clk clk;
  29. void __iomem *base;
  30. u32 power_bit;
  31. bool powerup_set;
  32. u32 enable_bit;
  33. u32 div_mask;
  34. u32 div_shift;
  35. unsigned long ref_clock;
  36. };
  37. #define to_clk_pllv3(_clk) container_of(_clk, struct clk_pllv3, clk)
  38. static ulong clk_pllv3_generic_get_rate(struct clk *clk)
  39. {
  40. struct clk_pllv3 *pll = to_clk_pllv3(dev_get_clk_ptr(clk->dev));
  41. unsigned long parent_rate = clk_get_parent_rate(clk);
  42. u32 div = (readl(pll->base) >> pll->div_shift) & pll->div_mask;
  43. return (div == 1) ? parent_rate * 22 : parent_rate * 20;
  44. }
  45. static ulong clk_pllv3_generic_set_rate(struct clk *clk, ulong rate)
  46. {
  47. struct clk_pllv3 *pll = to_clk_pllv3(clk);
  48. unsigned long parent_rate = clk_get_parent_rate(clk);
  49. u32 val, div;
  50. if (rate == parent_rate * 22)
  51. div = 1;
  52. else if (rate == parent_rate * 20)
  53. div = 0;
  54. else
  55. return -EINVAL;
  56. val = readl(pll->base);
  57. val &= ~(pll->div_mask << pll->div_shift);
  58. val |= (div << pll->div_shift);
  59. writel(val, pll->base);
  60. /* Wait for PLL to lock */
  61. while (!(readl(pll->base) & BM_PLL_LOCK))
  62. ;
  63. return 0;
  64. }
  65. static int clk_pllv3_generic_enable(struct clk *clk)
  66. {
  67. struct clk_pllv3 *pll = to_clk_pllv3(clk);
  68. u32 val;
  69. val = readl(pll->base);
  70. if (pll->powerup_set)
  71. val |= pll->power_bit;
  72. else
  73. val &= ~pll->power_bit;
  74. val |= pll->enable_bit;
  75. writel(val, pll->base);
  76. return 0;
  77. }
  78. static int clk_pllv3_generic_disable(struct clk *clk)
  79. {
  80. struct clk_pllv3 *pll = to_clk_pllv3(clk);
  81. u32 val;
  82. val = readl(pll->base);
  83. if (pll->powerup_set)
  84. val &= ~pll->power_bit;
  85. else
  86. val |= pll->power_bit;
  87. val &= ~pll->enable_bit;
  88. writel(val, pll->base);
  89. return 0;
  90. }
  91. static const struct clk_ops clk_pllv3_generic_ops = {
  92. .get_rate = clk_pllv3_generic_get_rate,
  93. .enable = clk_pllv3_generic_enable,
  94. .disable = clk_pllv3_generic_disable,
  95. .set_rate = clk_pllv3_generic_set_rate,
  96. };
  97. static ulong clk_pllv3_sys_get_rate(struct clk *clk)
  98. {
  99. struct clk_pllv3 *pll = to_clk_pllv3(clk);
  100. unsigned long parent_rate = clk_get_parent_rate(clk);
  101. u32 div = readl(pll->base) & pll->div_mask;
  102. return parent_rate * div / 2;
  103. }
  104. static ulong clk_pllv3_sys_set_rate(struct clk *clk, ulong rate)
  105. {
  106. struct clk_pllv3 *pll = to_clk_pllv3(clk);
  107. unsigned long parent_rate = clk_get_parent_rate(clk);
  108. unsigned long min_rate;
  109. unsigned long max_rate;
  110. u32 val, div;
  111. if (parent_rate == 0)
  112. return -EINVAL;
  113. min_rate = parent_rate * 54 / 2;
  114. max_rate = parent_rate * 108 / 2;
  115. if (rate < min_rate || rate > max_rate)
  116. return -EINVAL;
  117. div = rate * 2 / parent_rate;
  118. val = readl(pll->base);
  119. val &= ~pll->div_mask;
  120. val |= div;
  121. writel(val, pll->base);
  122. /* Wait for PLL to lock */
  123. while (!(readl(pll->base) & BM_PLL_LOCK))
  124. ;
  125. return 0;
  126. }
  127. static const struct clk_ops clk_pllv3_sys_ops = {
  128. .enable = clk_pllv3_generic_enable,
  129. .disable = clk_pllv3_generic_disable,
  130. .get_rate = clk_pllv3_sys_get_rate,
  131. .set_rate = clk_pllv3_sys_set_rate,
  132. };
  133. static ulong clk_pllv3_av_get_rate(struct clk *clk)
  134. {
  135. struct clk_pllv3 *pll = to_clk_pllv3(clk);
  136. unsigned long parent_rate = clk_get_parent_rate(clk);
  137. u32 mfn = readl(pll->base + PLL_NUM_OFFSET);
  138. u32 mfd = readl(pll->base + PLL_DENOM_OFFSET);
  139. u32 div = readl(pll->base) & pll->div_mask;
  140. u64 temp64 = (u64)parent_rate;
  141. if (mfd == 0)
  142. return -EIO;
  143. temp64 *= mfn;
  144. do_div(temp64, mfd);
  145. return parent_rate * div + (unsigned long)temp64;
  146. }
  147. static ulong clk_pllv3_av_set_rate(struct clk *clk, ulong rate)
  148. {
  149. struct clk_pllv3 *pll = to_clk_pllv3(clk);
  150. unsigned long parent_rate = clk_get_parent_rate(clk);
  151. unsigned long min_rate;
  152. unsigned long max_rate;
  153. u32 val, div;
  154. u32 mfn, mfd = 1000000;
  155. u32 max_mfd = 0x3FFFFFFF;
  156. u64 temp64;
  157. if (parent_rate == 0)
  158. return -EINVAL;
  159. min_rate = parent_rate * 27;
  160. max_rate = parent_rate * 54;
  161. if (rate < min_rate || rate > max_rate)
  162. return -EINVAL;
  163. if (parent_rate <= max_mfd)
  164. mfd = parent_rate;
  165. div = rate / parent_rate;
  166. temp64 = (u64)(rate - div * parent_rate);
  167. temp64 *= mfd;
  168. do_div(temp64, parent_rate);
  169. mfn = temp64;
  170. val = readl(pll->base);
  171. val &= ~pll->div_mask;
  172. val |= div;
  173. writel(val, pll->base);
  174. writel(mfn, pll->base + PLL_NUM_OFFSET);
  175. writel(mfd, pll->base + PLL_DENOM_OFFSET);
  176. /* Wait for PLL to lock */
  177. while (!(readl(pll->base) & BM_PLL_LOCK))
  178. ;
  179. return 0;
  180. }
  181. static const struct clk_ops clk_pllv3_av_ops = {
  182. .enable = clk_pllv3_generic_enable,
  183. .disable = clk_pllv3_generic_disable,
  184. .get_rate = clk_pllv3_av_get_rate,
  185. .set_rate = clk_pllv3_av_set_rate,
  186. };
  187. static ulong clk_pllv3_enet_get_rate(struct clk *clk)
  188. {
  189. struct clk_pllv3 *pll = to_clk_pllv3(clk);
  190. return pll->ref_clock;
  191. }
  192. static const struct clk_ops clk_pllv3_enet_ops = {
  193. .enable = clk_pllv3_generic_enable,
  194. .disable = clk_pllv3_generic_disable,
  195. .get_rate = clk_pllv3_enet_get_rate,
  196. };
  197. struct clk *imx_clk_pllv3(enum imx_pllv3_type type, const char *name,
  198. const char *parent_name, void __iomem *base,
  199. u32 div_mask)
  200. {
  201. struct clk_pllv3 *pll;
  202. struct clk *clk;
  203. char *drv_name;
  204. int ret;
  205. pll = kzalloc(sizeof(*pll), GFP_KERNEL);
  206. if (!pll)
  207. return ERR_PTR(-ENOMEM);
  208. pll->power_bit = BM_PLL_POWER;
  209. pll->enable_bit = BM_PLL_ENABLE;
  210. switch (type) {
  211. case IMX_PLLV3_GENERIC:
  212. drv_name = UBOOT_DM_CLK_IMX_PLLV3_GENERIC;
  213. pll->div_shift = 0;
  214. pll->powerup_set = false;
  215. break;
  216. case IMX_PLLV3_SYS:
  217. drv_name = UBOOT_DM_CLK_IMX_PLLV3_SYS;
  218. pll->div_shift = 0;
  219. pll->powerup_set = false;
  220. break;
  221. case IMX_PLLV3_USB:
  222. drv_name = UBOOT_DM_CLK_IMX_PLLV3_USB;
  223. pll->div_shift = 1;
  224. pll->powerup_set = true;
  225. break;
  226. case IMX_PLLV3_AV:
  227. drv_name = UBOOT_DM_CLK_IMX_PLLV3_AV;
  228. pll->div_shift = 0;
  229. pll->powerup_set = false;
  230. break;
  231. case IMX_PLLV3_ENET:
  232. drv_name = UBOOT_DM_CLK_IMX_PLLV3_ENET;
  233. pll->ref_clock = 500000000;
  234. break;
  235. default:
  236. kfree(pll);
  237. return ERR_PTR(-EINVAL);
  238. }
  239. pll->base = base;
  240. pll->div_mask = div_mask;
  241. clk = &pll->clk;
  242. ret = clk_register(clk, drv_name, name, parent_name);
  243. if (ret) {
  244. kfree(pll);
  245. return ERR_PTR(ret);
  246. }
  247. return clk;
  248. }
  249. U_BOOT_DRIVER(clk_pllv3_generic) = {
  250. .name = UBOOT_DM_CLK_IMX_PLLV3_GENERIC,
  251. .id = UCLASS_CLK,
  252. .ops = &clk_pllv3_generic_ops,
  253. .flags = DM_FLAG_PRE_RELOC,
  254. };
  255. U_BOOT_DRIVER(clk_pllv3_sys) = {
  256. .name = UBOOT_DM_CLK_IMX_PLLV3_SYS,
  257. .id = UCLASS_CLK,
  258. .ops = &clk_pllv3_sys_ops,
  259. .flags = DM_FLAG_PRE_RELOC,
  260. };
  261. U_BOOT_DRIVER(clk_pllv3_usb) = {
  262. .name = UBOOT_DM_CLK_IMX_PLLV3_USB,
  263. .id = UCLASS_CLK,
  264. .ops = &clk_pllv3_generic_ops,
  265. .flags = DM_FLAG_PRE_RELOC,
  266. };
  267. U_BOOT_DRIVER(clk_pllv3_av) = {
  268. .name = UBOOT_DM_CLK_IMX_PLLV3_AV,
  269. .id = UCLASS_CLK,
  270. .ops = &clk_pllv3_av_ops,
  271. .flags = DM_FLAG_PRE_RELOC,
  272. };
  273. U_BOOT_DRIVER(clk_pllv3_enet) = {
  274. .name = UBOOT_DM_CLK_IMX_PLLV3_ENET,
  275. .id = UCLASS_CLK,
  276. .ops = &clk_pllv3_enet_ops,
  277. };