da8xx-usb.h 2.5 KB

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  1. /* SPDX-License-Identifier: GPL-2.0+ */
  2. /*
  3. * da8xx-usb.h -- TI's DA8xx platform specific usb wrapper definitions.
  4. *
  5. * Author: Ajay Kumar Gupta <ajay.gupta@ti.com>
  6. *
  7. * Based on drivers/usb/musb/davinci.h
  8. *
  9. * Copyright (C) 2009 Texas Instruments Incorporated
  10. */
  11. #ifndef __DA8XX_MUSB_H__
  12. #define __DA8XX_MUSB_H__
  13. #include <asm/arch/hardware.h>
  14. #include <asm/arch/gpio.h>
  15. /* Base address of da8xx usb0 wrapper */
  16. #define DA8XX_USB_OTG_BASE 0x01E00000
  17. /* Base address of da8xx musb core */
  18. #define DA8XX_USB_OTG_CORE_BASE (DA8XX_USB_OTG_BASE + 0x400)
  19. /* Timeout for DA8xx usb module */
  20. #define DA8XX_USB_OTG_TIMEOUT 0x3FFFFFF
  21. /*
  22. * DA8xx platform USB wrapper register overlay.
  23. */
  24. struct da8xx_usb_regs {
  25. dv_reg revision;
  26. dv_reg control;
  27. dv_reg status;
  28. dv_reg emulation;
  29. dv_reg mode;
  30. dv_reg autoreq;
  31. dv_reg srpfixtime;
  32. dv_reg teardown;
  33. dv_reg intsrc;
  34. dv_reg intsrc_set;
  35. dv_reg intsrc_clr;
  36. dv_reg intmsk;
  37. dv_reg intmsk_set;
  38. dv_reg intmsk_clr;
  39. dv_reg intsrcmsk;
  40. dv_reg eoi;
  41. dv_reg intvector;
  42. dv_reg grndis_size[4];
  43. };
  44. #define da8xx_usb_regs ((struct da8xx_usb_regs *)DA8XX_USB_OTG_BASE)
  45. /* DA8XX interrupt bits definitions */
  46. #define DA8XX_USB_TX_ENDPTS_MASK 0x1f /* ep0 + 4 tx */
  47. #define DA8XX_USB_RX_ENDPTS_MASK 0x1e /* 4 rx */
  48. #define DA8XX_USB_TXINT_SHIFT 0
  49. #define DA8XX_USB_RXINT_SHIFT 8
  50. #define DA8XX_USB_USBINT_MASK 0x01ff0000 /* 8 Mentor, DRVVBUS */
  51. #define DA8XX_USB_TXINT_MASK \
  52. (DA8XX_USB_TX_ENDPTS_MASK << DA8XX_USB_TXINT_SHIFT)
  53. #define DA8XX_USB_RXINT_MASK \
  54. (DA8XX_USB_RX_ENDPTS_MASK << DA8XX_USB_RXINT_SHIFT)
  55. /* DA8xx CFGCHIP2 (USB 2.0 PHY Control) register bits */
  56. #define CFGCHIP2_PHYCLKGD (1 << 17)
  57. #define CFGCHIP2_VBUSSENSE (1 << 16)
  58. #define CFGCHIP2_RESET (1 << 15)
  59. #define CFGCHIP2_OTGMODE (3 << 13)
  60. #define CFGCHIP2_NO_OVERRIDE (0 << 13)
  61. #define CFGCHIP2_FORCE_HOST (1 << 13)
  62. #define CFGCHIP2_FORCE_DEVICE (2 << 13)
  63. #define CFGCHIP2_FORCE_HOST_VBUS_LOW (3 << 13)
  64. #define CFGCHIP2_USB1PHYCLKMUX (1 << 12)
  65. #define CFGCHIP2_USB2PHYCLKMUX (1 << 11)
  66. #define CFGCHIP2_PHYPWRDN (1 << 10)
  67. #define CFGCHIP2_OTGPWRDN (1 << 9)
  68. #define CFGCHIP2_DATPOL (1 << 8)
  69. #define CFGCHIP2_USB1SUSPENDM (1 << 7)
  70. #define CFGCHIP2_PHY_PLLON (1 << 6) /* override PLL suspend */
  71. #define CFGCHIP2_SESENDEN (1 << 5) /* Vsess_end comparator */
  72. #define CFGCHIP2_VBDTCTEN (1 << 4) /* Vbus comparator */
  73. #define CFGCHIP2_REFFREQ (0xf << 0)
  74. #define CFGCHIP2_REFFREQ_12MHZ (1 << 0)
  75. #define CFGCHIP2_REFFREQ_24MHZ (2 << 0)
  76. #define CFGCHIP2_REFFREQ_48MHZ (3 << 0)
  77. #define DA8XX_USB_VBUS_GPIO (1 << 15)
  78. #endif /* __DA8XX_MUSB_H__ */