macro.h 9.0 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233234235236237238239240241242243244245246247248249250251252253254255256257258259260261262263264265266267268269270271272273274275276277278279280281282283284285286287288289290291292293294295296297298299300301302303304305306307308309310311312313314315316317318319320321322323324325326327328329330331332333334335336337338339340341342343344345346347348349350351352353354355356357358359360361362
  1. /* SPDX-License-Identifier: GPL-2.0+ */
  2. /*
  3. * include/asm-arm/macro.h
  4. *
  5. * Copyright (C) 2009 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
  6. */
  7. #ifndef __ASM_ARM_MACRO_H__
  8. #define __ASM_ARM_MACRO_H__
  9. #ifdef CONFIG_ARM64
  10. #include <asm/system.h>
  11. #endif
  12. #ifdef __ASSEMBLY__
  13. /*
  14. * These macros provide a convenient way to write 8, 16 and 32 bit data
  15. * to any address.
  16. * Registers r4 and r5 are used, any data in these registers are
  17. * overwritten by the macros.
  18. * The macros are valid for any ARM architecture, they do not implement
  19. * any memory barriers so caution is recommended when using these when the
  20. * caches are enabled or on a multi-core system.
  21. */
  22. .macro write32, addr, data
  23. ldr r4, =\addr
  24. ldr r5, =\data
  25. str r5, [r4]
  26. .endm
  27. .macro write16, addr, data
  28. ldr r4, =\addr
  29. ldrh r5, =\data
  30. strh r5, [r4]
  31. .endm
  32. .macro write8, addr, data
  33. ldr r4, =\addr
  34. ldrb r5, =\data
  35. strb r5, [r4]
  36. .endm
  37. /*
  38. * This macro generates a loop that can be used for delays in the code.
  39. * Register r4 is used, any data in this register is overwritten by the
  40. * macro.
  41. * The macro is valid for any ARM architeture. The actual time spent in the
  42. * loop will vary from CPU to CPU though.
  43. */
  44. .macro wait_timer, time
  45. ldr r4, =\time
  46. 1:
  47. nop
  48. subs r4, r4, #1
  49. bcs 1b
  50. .endm
  51. #ifdef CONFIG_ARM64
  52. /*
  53. * Register aliases.
  54. */
  55. lr .req x30
  56. /*
  57. * Branch according to exception level
  58. */
  59. .macro switch_el, xreg, el3_label, el2_label, el1_label
  60. mrs \xreg, CurrentEL
  61. cmp \xreg, 0xc
  62. b.eq \el3_label
  63. cmp \xreg, 0x8
  64. b.eq \el2_label
  65. cmp \xreg, 0x4
  66. b.eq \el1_label
  67. .endm
  68. /*
  69. * Branch if we are not in the highest exception level
  70. */
  71. .macro branch_if_not_highest_el, xreg, label
  72. switch_el \xreg, 3f, 2f, 1f
  73. 2: mrs \xreg, ID_AA64PFR0_EL1
  74. and \xreg, \xreg, #(ID_AA64PFR0_EL1_EL3)
  75. cbnz \xreg, \label
  76. b 3f
  77. 1: mrs \xreg, ID_AA64PFR0_EL1
  78. and \xreg, \xreg, #(ID_AA64PFR0_EL1_EL3 | ID_AA64PFR0_EL1_EL2)
  79. cbnz \xreg, \label
  80. 3:
  81. .endm
  82. /*
  83. * Branch if current processor is a Cortex-A57 core.
  84. */
  85. .macro branch_if_a57_core, xreg, a57_label
  86. mrs \xreg, midr_el1
  87. lsr \xreg, \xreg, #4
  88. and \xreg, \xreg, #0x00000FFF
  89. cmp \xreg, #0xD07 /* Cortex-A57 MPCore processor. */
  90. b.eq \a57_label
  91. .endm
  92. /*
  93. * Branch if current processor is a Cortex-A53 core.
  94. */
  95. .macro branch_if_a53_core, xreg, a53_label
  96. mrs \xreg, midr_el1
  97. lsr \xreg, \xreg, #4
  98. and \xreg, \xreg, #0x00000FFF
  99. cmp \xreg, #0xD03 /* Cortex-A53 MPCore processor. */
  100. b.eq \a53_label
  101. .endm
  102. /*
  103. * Branch if current processor is a slave,
  104. * choose processor with all zero affinity value as the master.
  105. */
  106. .macro branch_if_slave, xreg, slave_label
  107. #ifdef CONFIG_ARMV8_MULTIENTRY
  108. /* NOTE: MPIDR handling will be erroneous on multi-cluster machines */
  109. mrs \xreg, mpidr_el1
  110. tst \xreg, #0xff /* Test Affinity 0 */
  111. b.ne \slave_label
  112. lsr \xreg, \xreg, #8
  113. tst \xreg, #0xff /* Test Affinity 1 */
  114. b.ne \slave_label
  115. lsr \xreg, \xreg, #8
  116. tst \xreg, #0xff /* Test Affinity 2 */
  117. b.ne \slave_label
  118. lsr \xreg, \xreg, #16
  119. tst \xreg, #0xff /* Test Affinity 3 */
  120. b.ne \slave_label
  121. #endif
  122. .endm
  123. /*
  124. * Branch if current processor is a master,
  125. * choose processor with all zero affinity value as the master.
  126. */
  127. .macro branch_if_master, xreg1, xreg2, master_label
  128. #ifdef CONFIG_ARMV8_MULTIENTRY
  129. /* NOTE: MPIDR handling will be erroneous on multi-cluster machines */
  130. mrs \xreg1, mpidr_el1
  131. lsr \xreg2, \xreg1, #32
  132. lsl \xreg2, \xreg2, #32
  133. lsl \xreg1, \xreg1, #40
  134. lsr \xreg1, \xreg1, #40
  135. orr \xreg1, \xreg1, \xreg2
  136. cbz \xreg1, \master_label
  137. #else
  138. b \master_label
  139. #endif
  140. .endm
  141. /*
  142. * Switch from EL3 to EL2 for ARMv8
  143. * @ep: kernel entry point
  144. * @flag: The execution state flag for lower exception
  145. * level, ES_TO_AARCH64 or ES_TO_AARCH32
  146. * @tmp: temporary register
  147. *
  148. * For loading 32-bit OS, x1 is machine nr and x2 is ftaddr.
  149. * For loading 64-bit OS, x0 is physical address to the FDT blob.
  150. * They will be passed to the guest.
  151. */
  152. .macro armv8_switch_to_el2_m, ep, flag, tmp
  153. msr cptr_el3, xzr /* Disable coprocessor traps to EL3 */
  154. mov \tmp, #CPTR_EL2_RES1
  155. msr cptr_el2, \tmp /* Disable coprocessor traps to EL2 */
  156. /* Initialize Generic Timers */
  157. msr cntvoff_el2, xzr
  158. /* Initialize SCTLR_EL2
  159. *
  160. * setting RES1 bits (29,28,23,22,18,16,11,5,4) to 1
  161. * and RES0 bits (31,30,27,26,24,21,20,17,15-13,10-6) +
  162. * EE,WXN,I,SA,C,A,M to 0
  163. */
  164. ldr \tmp, =(SCTLR_EL2_RES1 | SCTLR_EL2_EE_LE |\
  165. SCTLR_EL2_WXN_DIS | SCTLR_EL2_ICACHE_DIS |\
  166. SCTLR_EL2_SA_DIS | SCTLR_EL2_DCACHE_DIS |\
  167. SCTLR_EL2_ALIGN_DIS | SCTLR_EL2_MMU_DIS)
  168. msr sctlr_el2, \tmp
  169. mov \tmp, sp
  170. msr sp_el2, \tmp /* Migrate SP */
  171. mrs \tmp, vbar_el3
  172. msr vbar_el2, \tmp /* Migrate VBAR */
  173. /* Check switch to AArch64 EL2 or AArch32 Hypervisor mode */
  174. cmp \flag, #ES_TO_AARCH32
  175. b.eq 1f
  176. /*
  177. * The next lower exception level is AArch64, 64bit EL2 | HCE |
  178. * RES1 (Bits[5:4]) | Non-secure EL0/EL1.
  179. * and the SMD depends on requirements.
  180. */
  181. #ifdef CONFIG_ARMV8_PSCI
  182. ldr \tmp, =(SCR_EL3_RW_AARCH64 | SCR_EL3_HCE_EN |\
  183. SCR_EL3_RES1 | SCR_EL3_NS_EN)
  184. #else
  185. ldr \tmp, =(SCR_EL3_RW_AARCH64 | SCR_EL3_HCE_EN |\
  186. SCR_EL3_SMD_DIS | SCR_EL3_RES1 |\
  187. SCR_EL3_NS_EN)
  188. #endif
  189. #ifdef CONFIG_ARMV8_EA_EL3_FIRST
  190. orr \tmp, \tmp, #SCR_EL3_EA_EN
  191. #endif
  192. msr scr_el3, \tmp
  193. /* Return to the EL2_SP2 mode from EL3 */
  194. ldr \tmp, =(SPSR_EL_DEBUG_MASK | SPSR_EL_SERR_MASK |\
  195. SPSR_EL_IRQ_MASK | SPSR_EL_FIQ_MASK |\
  196. SPSR_EL_M_AARCH64 | SPSR_EL_M_EL2H)
  197. msr spsr_el3, \tmp
  198. msr elr_el3, \ep
  199. eret
  200. 1:
  201. /*
  202. * The next lower exception level is AArch32, 32bit EL2 | HCE |
  203. * SMD | RES1 (Bits[5:4]) | Non-secure EL0/EL1.
  204. */
  205. ldr \tmp, =(SCR_EL3_RW_AARCH32 | SCR_EL3_HCE_EN |\
  206. SCR_EL3_SMD_DIS | SCR_EL3_RES1 |\
  207. SCR_EL3_NS_EN)
  208. msr scr_el3, \tmp
  209. /* Return to AArch32 Hypervisor mode */
  210. ldr \tmp, =(SPSR_EL_END_LE | SPSR_EL_ASYN_MASK |\
  211. SPSR_EL_IRQ_MASK | SPSR_EL_FIQ_MASK |\
  212. SPSR_EL_T_A32 | SPSR_EL_M_AARCH32 |\
  213. SPSR_EL_M_HYP)
  214. msr spsr_el3, \tmp
  215. msr elr_el3, \ep
  216. eret
  217. .endm
  218. /*
  219. * Switch from EL2 to EL1 for ARMv8
  220. * @ep: kernel entry point
  221. * @flag: The execution state flag for lower exception
  222. * level, ES_TO_AARCH64 or ES_TO_AARCH32
  223. * @tmp: temporary register
  224. *
  225. * For loading 32-bit OS, x1 is machine nr and x2 is ftaddr.
  226. * For loading 64-bit OS, x0 is physical address to the FDT blob.
  227. * They will be passed to the guest.
  228. */
  229. .macro armv8_switch_to_el1_m, ep, flag, tmp, tmp2
  230. /* Initialize Generic Timers */
  231. mrs \tmp, cnthctl_el2
  232. /* Enable EL1 access to timers */
  233. orr \tmp, \tmp, #(CNTHCTL_EL2_EL1PCEN_EN |\
  234. CNTHCTL_EL2_EL1PCTEN_EN)
  235. msr cnthctl_el2, \tmp
  236. msr cntvoff_el2, xzr
  237. /* Initilize MPID/MPIDR registers */
  238. mrs \tmp, midr_el1
  239. msr vpidr_el2, \tmp
  240. mrs \tmp, mpidr_el1
  241. msr vmpidr_el2, \tmp
  242. /* Disable coprocessor traps */
  243. mov \tmp, #CPTR_EL2_RES1
  244. msr cptr_el2, \tmp /* Disable coprocessor traps to EL2 */
  245. msr hstr_el2, xzr /* Disable coprocessor traps to EL2 */
  246. mov \tmp, #CPACR_EL1_FPEN_EN
  247. msr cpacr_el1, \tmp /* Enable FP/SIMD at EL1 */
  248. /* SCTLR_EL1 initialization
  249. *
  250. * setting RES1 bits (29,28,23,22,20,11) to 1
  251. * and RES0 bits (31,30,27,21,17,13,10,6) +
  252. * UCI,EE,EOE,WXN,nTWE,nTWI,UCT,DZE,I,UMA,SED,ITD,
  253. * CP15BEN,SA0,SA,C,A,M to 0
  254. */
  255. ldr \tmp, =(SCTLR_EL1_RES1 | SCTLR_EL1_UCI_DIS |\
  256. SCTLR_EL1_EE_LE | SCTLR_EL1_WXN_DIS |\
  257. SCTLR_EL1_NTWE_DIS | SCTLR_EL1_NTWI_DIS |\
  258. SCTLR_EL1_UCT_DIS | SCTLR_EL1_DZE_DIS |\
  259. SCTLR_EL1_ICACHE_DIS | SCTLR_EL1_UMA_DIS |\
  260. SCTLR_EL1_SED_EN | SCTLR_EL1_ITD_EN |\
  261. SCTLR_EL1_CP15BEN_DIS | SCTLR_EL1_SA0_DIS |\
  262. SCTLR_EL1_SA_DIS | SCTLR_EL1_DCACHE_DIS |\
  263. SCTLR_EL1_ALIGN_DIS | SCTLR_EL1_MMU_DIS)
  264. msr sctlr_el1, \tmp
  265. mov \tmp, sp
  266. msr sp_el1, \tmp /* Migrate SP */
  267. mrs \tmp, vbar_el2
  268. msr vbar_el1, \tmp /* Migrate VBAR */
  269. /* Check switch to AArch64 EL1 or AArch32 Supervisor mode */
  270. cmp \flag, #ES_TO_AARCH32
  271. b.eq 1f
  272. /* Initialize HCR_EL2 */
  273. /* Only disable PAuth traps if PAuth is supported */
  274. mrs \tmp, id_aa64isar1_el1
  275. ldr \tmp2, =(ID_AA64ISAR1_EL1_GPI | ID_AA64ISAR1_EL1_GPA | \
  276. ID_AA64ISAR1_EL1_API | ID_AA64ISAR1_EL1_APA)
  277. tst \tmp, \tmp2
  278. mov \tmp2, #(HCR_EL2_RW_AARCH64 | HCR_EL2_HCD_DIS)
  279. orr \tmp, \tmp2, #(HCR_EL2_APK | HCR_EL2_API)
  280. csel \tmp, \tmp2, \tmp, eq
  281. msr hcr_el2, \tmp
  282. /* Return to the EL1_SP1 mode from EL2 */
  283. ldr \tmp, =(SPSR_EL_DEBUG_MASK | SPSR_EL_SERR_MASK |\
  284. SPSR_EL_IRQ_MASK | SPSR_EL_FIQ_MASK |\
  285. SPSR_EL_M_AARCH64 | SPSR_EL_M_EL1H)
  286. msr spsr_el2, \tmp
  287. msr elr_el2, \ep
  288. eret
  289. 1:
  290. /* Initialize HCR_EL2 */
  291. ldr \tmp, =(HCR_EL2_RW_AARCH32 | HCR_EL2_HCD_DIS)
  292. msr hcr_el2, \tmp
  293. /* Return to AArch32 Supervisor mode from EL2 */
  294. ldr \tmp, =(SPSR_EL_END_LE | SPSR_EL_ASYN_MASK |\
  295. SPSR_EL_IRQ_MASK | SPSR_EL_FIQ_MASK |\
  296. SPSR_EL_T_A32 | SPSR_EL_M_AARCH32 |\
  297. SPSR_EL_M_SVC)
  298. msr spsr_el2, \tmp
  299. msr elr_el2, \ep
  300. eret
  301. .endm
  302. #if defined(CONFIG_GICV3)
  303. .macro gic_wait_for_interrupt_m xreg1
  304. 0 : wfi
  305. mrs \xreg1, ICC_IAR1_EL1
  306. msr ICC_EOIR1_EL1, \xreg1
  307. cbnz \xreg1, 0b
  308. .endm
  309. #elif defined(CONFIG_GICV2)
  310. .macro gic_wait_for_interrupt_m xreg1, wreg2
  311. 0 : wfi
  312. ldr \wreg2, [\xreg1, GICC_AIAR]
  313. str \wreg2, [\xreg1, GICC_AEOIR]
  314. and \wreg2, \wreg2, #0x3ff
  315. cbnz \wreg2, 0b
  316. .endm
  317. #endif
  318. #endif /* CONFIG_ARM64 */
  319. #endif /* __ASSEMBLY__ */
  320. #endif /* __ASM_ARM_MACRO_H__ */