ddr3_dimm_params.c 8.8 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. /*
  3. * Copyright 2008-2012 Freescale Semiconductor, Inc.
  4. * Dave Liu <daveliu@freescale.com>
  5. *
  6. * calculate the organization and timing parameter
  7. * from ddr3 spd, please refer to the spec
  8. * JEDEC standard No.21-C 4_01_02_11R18.pdf
  9. */
  10. #include <common.h>
  11. #include <fsl_ddr_sdram.h>
  12. #include <log.h>
  13. #include <fsl_ddr.h>
  14. /*
  15. * Calculate the Density of each Physical Rank.
  16. * Returned size is in bytes.
  17. *
  18. * each rank size =
  19. * sdram capacity(bit) / 8 * primary bus width / sdram width
  20. *
  21. * where: sdram capacity = spd byte4[3:0]
  22. * primary bus width = spd byte8[2:0]
  23. * sdram width = spd byte7[2:0]
  24. *
  25. * SPD byte4 - sdram density and banks
  26. * bit[3:0] size(bit) size(byte)
  27. * 0000 256Mb 32MB
  28. * 0001 512Mb 64MB
  29. * 0010 1Gb 128MB
  30. * 0011 2Gb 256MB
  31. * 0100 4Gb 512MB
  32. * 0101 8Gb 1GB
  33. * 0110 16Gb 2GB
  34. *
  35. * SPD byte8 - module memory bus width
  36. * bit[2:0] primary bus width
  37. * 000 8bits
  38. * 001 16bits
  39. * 010 32bits
  40. * 011 64bits
  41. *
  42. * SPD byte7 - module organiztion
  43. * bit[2:0] sdram device width
  44. * 000 4bits
  45. * 001 8bits
  46. * 010 16bits
  47. * 011 32bits
  48. *
  49. */
  50. static unsigned long long
  51. compute_ranksize(const ddr3_spd_eeprom_t *spd)
  52. {
  53. unsigned long long bsize;
  54. int nbit_sdram_cap_bsize = 0;
  55. int nbit_primary_bus_width = 0;
  56. int nbit_sdram_width = 0;
  57. if ((spd->density_banks & 0xf) < 7)
  58. nbit_sdram_cap_bsize = (spd->density_banks & 0xf) + 28;
  59. if ((spd->bus_width & 0x7) < 4)
  60. nbit_primary_bus_width = (spd->bus_width & 0x7) + 3;
  61. if ((spd->organization & 0x7) < 4)
  62. nbit_sdram_width = (spd->organization & 0x7) + 2;
  63. bsize = 1ULL << (nbit_sdram_cap_bsize - 3
  64. + nbit_primary_bus_width - nbit_sdram_width);
  65. debug("DDR: DDR III rank density = 0x%16llx\n", bsize);
  66. return bsize;
  67. }
  68. /*
  69. * ddr_compute_dimm_parameters for DDR3 SPD
  70. *
  71. * Compute DIMM parameters based upon the SPD information in spd.
  72. * Writes the results to the dimm_params_t structure pointed by pdimm.
  73. *
  74. */
  75. unsigned int ddr_compute_dimm_parameters(const unsigned int ctrl_num,
  76. const ddr3_spd_eeprom_t *spd,
  77. dimm_params_t *pdimm,
  78. unsigned int dimm_number)
  79. {
  80. unsigned int retval;
  81. unsigned int mtb_ps;
  82. int ftb_10th_ps;
  83. int i;
  84. if (spd->mem_type) {
  85. if (spd->mem_type != SPD_MEMTYPE_DDR3) {
  86. printf("DIMM %u: is not a DDR3 SPD.\n", dimm_number);
  87. return 1;
  88. }
  89. } else {
  90. memset(pdimm, 0, sizeof(dimm_params_t));
  91. return 1;
  92. }
  93. retval = ddr3_spd_check(spd);
  94. if (retval) {
  95. printf("DIMM %u: failed checksum\n", dimm_number);
  96. return 2;
  97. }
  98. /*
  99. * The part name in ASCII in the SPD EEPROM is not null terminated.
  100. * Guarantee null termination here by presetting all bytes to 0
  101. * and copying the part name in ASCII from the SPD onto it
  102. */
  103. memset(pdimm->mpart, 0, sizeof(pdimm->mpart));
  104. if ((spd->info_size_crc & 0xF) > 1)
  105. memcpy(pdimm->mpart, spd->mpart, sizeof(pdimm->mpart) - 1);
  106. /* DIMM organization parameters */
  107. pdimm->n_ranks = ((spd->organization >> 3) & 0x7) + 1;
  108. pdimm->rank_density = compute_ranksize(spd);
  109. pdimm->capacity = pdimm->n_ranks * pdimm->rank_density;
  110. pdimm->primary_sdram_width = 1 << (3 + (spd->bus_width & 0x7));
  111. if ((spd->bus_width >> 3) & 0x3)
  112. pdimm->ec_sdram_width = 8;
  113. else
  114. pdimm->ec_sdram_width = 0;
  115. pdimm->data_width = pdimm->primary_sdram_width
  116. + pdimm->ec_sdram_width;
  117. pdimm->device_width = 1 << ((spd->organization & 0x7) + 2);
  118. /* These are the types defined by the JEDEC DDR3 SPD spec */
  119. pdimm->mirrored_dimm = 0;
  120. pdimm->registered_dimm = 0;
  121. switch (spd->module_type & DDR3_SPD_MODULETYPE_MASK) {
  122. case DDR3_SPD_MODULETYPE_RDIMM:
  123. case DDR3_SPD_MODULETYPE_MINI_RDIMM:
  124. case DDR3_SPD_MODULETYPE_72B_SO_RDIMM:
  125. /* Registered/buffered DIMMs */
  126. pdimm->registered_dimm = 1;
  127. for (i = 0; i < 16; i += 2) {
  128. u8 rcw = spd->mod_section.registered.rcw[i/2];
  129. pdimm->rcw[i] = (rcw >> 0) & 0x0F;
  130. pdimm->rcw[i+1] = (rcw >> 4) & 0x0F;
  131. }
  132. break;
  133. case DDR3_SPD_MODULETYPE_UDIMM:
  134. case DDR3_SPD_MODULETYPE_SO_DIMM:
  135. case DDR3_SPD_MODULETYPE_MICRO_DIMM:
  136. case DDR3_SPD_MODULETYPE_MINI_UDIMM:
  137. case DDR3_SPD_MODULETYPE_MINI_CDIMM:
  138. case DDR3_SPD_MODULETYPE_72B_SO_UDIMM:
  139. case DDR3_SPD_MODULETYPE_72B_SO_CDIMM:
  140. case DDR3_SPD_MODULETYPE_LRDIMM:
  141. case DDR3_SPD_MODULETYPE_16B_SO_DIMM:
  142. case DDR3_SPD_MODULETYPE_32B_SO_DIMM:
  143. /* Unbuffered DIMMs */
  144. if (spd->mod_section.unbuffered.addr_mapping & 0x1)
  145. pdimm->mirrored_dimm = 1;
  146. break;
  147. default:
  148. printf("unknown module_type 0x%02X\n", spd->module_type);
  149. return 1;
  150. }
  151. /* SDRAM device parameters */
  152. pdimm->n_row_addr = ((spd->addressing >> 3) & 0x7) + 12;
  153. pdimm->n_col_addr = (spd->addressing & 0x7) + 9;
  154. pdimm->n_banks_per_sdram_device = 8 << ((spd->density_banks >> 4) & 0x7);
  155. /*
  156. * The SPD spec has not the ECC bit,
  157. * We consider the DIMM as ECC capability
  158. * when the extension bus exist
  159. */
  160. if (pdimm->ec_sdram_width)
  161. pdimm->edc_config = 0x02;
  162. else
  163. pdimm->edc_config = 0x00;
  164. /*
  165. * The SPD spec has not the burst length byte
  166. * but DDR3 spec has nature BL8 and BC4,
  167. * BL8 -bit3, BC4 -bit2
  168. */
  169. pdimm->burst_lengths_bitmask = 0x0c;
  170. /* MTB - medium timebase
  171. * The unit in the SPD spec is ns,
  172. * We convert it to ps.
  173. * eg: MTB = 0.125ns (125ps)
  174. */
  175. mtb_ps = (spd->mtb_dividend * 1000) /spd->mtb_divisor;
  176. pdimm->mtb_ps = mtb_ps;
  177. /*
  178. * FTB - fine timebase
  179. * use 1/10th of ps as our unit to avoid floating point
  180. * eg, 10 for 1ps, 25 for 2.5ps, 50 for 5ps
  181. */
  182. ftb_10th_ps =
  183. ((spd->ftb_div & 0xf0) >> 4) * 10 / (spd->ftb_div & 0x0f);
  184. pdimm->ftb_10th_ps = ftb_10th_ps;
  185. /*
  186. * sdram minimum cycle time
  187. * we assume the MTB is 0.125ns
  188. * eg:
  189. * tck_min=15 MTB (1.875ns) ->DDR3-1066
  190. * =12 MTB (1.5ns) ->DDR3-1333
  191. * =10 MTB (1.25ns) ->DDR3-1600
  192. */
  193. pdimm->tckmin_x_ps = spd->tck_min * mtb_ps +
  194. (spd->fine_tck_min * ftb_10th_ps) / 10;
  195. /*
  196. * CAS latency supported
  197. * bit4 - CL4
  198. * bit5 - CL5
  199. * bit18 - CL18
  200. */
  201. pdimm->caslat_x = ((spd->caslat_msb << 8) | spd->caslat_lsb) << 4;
  202. /*
  203. * min CAS latency time
  204. * eg: taa_min =
  205. * DDR3-800D 100 MTB (12.5ns)
  206. * DDR3-1066F 105 MTB (13.125ns)
  207. * DDR3-1333H 108 MTB (13.5ns)
  208. * DDR3-1600H 90 MTB (11.25ns)
  209. */
  210. pdimm->taa_ps = spd->taa_min * mtb_ps +
  211. (spd->fine_taa_min * ftb_10th_ps) / 10;
  212. /*
  213. * min write recovery time
  214. * eg:
  215. * twr_min = 120 MTB (15ns) -> all speed grades.
  216. */
  217. pdimm->twr_ps = spd->twr_min * mtb_ps;
  218. /*
  219. * min RAS to CAS delay time
  220. * eg: trcd_min =
  221. * DDR3-800 100 MTB (12.5ns)
  222. * DDR3-1066F 105 MTB (13.125ns)
  223. * DDR3-1333H 108 MTB (13.5ns)
  224. * DDR3-1600H 90 MTB (11.25)
  225. */
  226. pdimm->trcd_ps = spd->trcd_min * mtb_ps +
  227. (spd->fine_trcd_min * ftb_10th_ps) / 10;
  228. /*
  229. * min row active to row active delay time
  230. * eg: trrd_min =
  231. * DDR3-800(1KB page) 80 MTB (10ns)
  232. * DDR3-1333(1KB page) 48 MTB (6ns)
  233. */
  234. pdimm->trrd_ps = spd->trrd_min * mtb_ps;
  235. /*
  236. * min row precharge delay time
  237. * eg: trp_min =
  238. * DDR3-800D 100 MTB (12.5ns)
  239. * DDR3-1066F 105 MTB (13.125ns)
  240. * DDR3-1333H 108 MTB (13.5ns)
  241. * DDR3-1600H 90 MTB (11.25ns)
  242. */
  243. pdimm->trp_ps = spd->trp_min * mtb_ps +
  244. (spd->fine_trp_min * ftb_10th_ps) / 10;
  245. /* min active to precharge delay time
  246. * eg: tRAS_min =
  247. * DDR3-800D 300 MTB (37.5ns)
  248. * DDR3-1066F 300 MTB (37.5ns)
  249. * DDR3-1333H 288 MTB (36ns)
  250. * DDR3-1600H 280 MTB (35ns)
  251. */
  252. pdimm->tras_ps = (((spd->tras_trc_ext & 0xf) << 8) | spd->tras_min_lsb)
  253. * mtb_ps;
  254. /*
  255. * min active to actice/refresh delay time
  256. * eg: tRC_min =
  257. * DDR3-800D 400 MTB (50ns)
  258. * DDR3-1066F 405 MTB (50.625ns)
  259. * DDR3-1333H 396 MTB (49.5ns)
  260. * DDR3-1600H 370 MTB (46.25ns)
  261. */
  262. pdimm->trc_ps = (((spd->tras_trc_ext & 0xf0) << 4) | spd->trc_min_lsb)
  263. * mtb_ps + (spd->fine_trc_min * ftb_10th_ps) / 10;
  264. /*
  265. * min refresh recovery delay time
  266. * eg: tRFC_min =
  267. * 512Mb 720 MTB (90ns)
  268. * 1Gb 880 MTB (110ns)
  269. * 2Gb 1280 MTB (160ns)
  270. */
  271. pdimm->trfc_ps = ((spd->trfc_min_msb << 8) | spd->trfc_min_lsb)
  272. * mtb_ps;
  273. /*
  274. * min internal write to read command delay time
  275. * eg: twtr_min = 40 MTB (7.5ns) - all speed bins.
  276. * tWRT is at least 4 mclk independent of operating freq.
  277. */
  278. pdimm->twtr_ps = spd->twtr_min * mtb_ps;
  279. /*
  280. * min internal read to precharge command delay time
  281. * eg: trtp_min = 40 MTB (7.5ns) - all speed bins.
  282. * tRTP is at least 4 mclk independent of operating freq.
  283. */
  284. pdimm->trtp_ps = spd->trtp_min * mtb_ps;
  285. /*
  286. * Average periodic refresh interval
  287. * tREFI = 7.8 us at normal temperature range
  288. * = 3.9 us at ext temperature range
  289. */
  290. pdimm->refresh_rate_ps = 7800000;
  291. if ((spd->therm_ref_opt & 0x1) && !(spd->therm_ref_opt & 0x2)) {
  292. pdimm->refresh_rate_ps = 3900000;
  293. pdimm->extended_op_srt = 1;
  294. }
  295. /*
  296. * min four active window delay time
  297. * eg: tfaw_min =
  298. * DDR3-800(1KB page) 320 MTB (40ns)
  299. * DDR3-1066(1KB page) 300 MTB (37.5ns)
  300. * DDR3-1333(1KB page) 240 MTB (30ns)
  301. * DDR3-1600(1KB page) 240 MTB (30ns)
  302. */
  303. pdimm->tfaw_ps = (((spd->tfaw_msb & 0xf) << 8) | spd->tfaw_min)
  304. * mtb_ps;
  305. return 0;
  306. }