fpga_manager_arria10.h 4.3 KB

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  1. /* SPDX-License-Identifier: GPL-2.0 */
  2. /*
  3. * Copyright (C) 2017-2019 Intel Corporation <www.intel.com>
  4. * All rights reserved.
  5. */
  6. #include <asm/cache.h>
  7. #include <altera.h>
  8. #include <image.h>
  9. #include <linux/bitops.h>
  10. #ifndef _FPGA_MANAGER_ARRIA10_H_
  11. #define _FPGA_MANAGER_ARRIA10_H_
  12. #define ALT_FPGAMGR_IMGCFG_STAT_F2S_CRC_ERROR_SET_MSK BIT(0)
  13. #define ALT_FPGAMGR_IMGCFG_STAT_F2S_EARLY_USERMODE_SET_MSK BIT(1)
  14. #define ALT_FPGAMGR_IMGCFG_STAT_F2S_USERMODE_SET_MSK BIT(2)
  15. #define ALT_FPGAMGR_IMGCFG_STAT_F2S_INITDONE_OE_SET_MSK BIT(3)
  16. #define ALT_FPGAMGR_IMGCFG_STAT_F2S_NSTATUS_PIN_SET_MSK BIT(4)
  17. #define ALT_FPGAMGR_IMGCFG_STAT_F2S_NSTATUS_OE_SET_MSK BIT(5)
  18. #define ALT_FPGAMGR_IMGCFG_STAT_F2S_CONDONE_PIN_SET_MSK BIT(6)
  19. #define ALT_FPGAMGR_IMGCFG_STAT_F2S_CONDONE_OE_SET_MSK BIT(7)
  20. #define ALT_FPGAMGR_IMGCFG_STAT_F2S_CVP_CONF_DONE_SET_MSK BIT(8)
  21. #define ALT_FPGAMGR_IMGCFG_STAT_F2S_PR_READY_SET_MSK BIT(9)
  22. #define ALT_FPGAMGR_IMGCFG_STAT_F2S_PR_DONE_SET_MSK BIT(10)
  23. #define ALT_FPGAMGR_IMGCFG_STAT_F2S_PR_ERROR_SET_MSK BIT(11)
  24. #define ALT_FPGAMGR_IMGCFG_STAT_F2S_NCONFIG_PIN_SET_MSK BIT(12)
  25. #define ALT_FPGAMGR_IMGCFG_STAT_F2S_NCEO_OE_SET_MSK BIT(13)
  26. #define ALT_FPGAMGR_IMGCFG_STAT_F2S_MSEL0_SET_MSK BIT(16)
  27. #define ALT_FPGAMGR_IMGCFG_STAT_F2S_MSEL1_SET_MSK BIT(17)
  28. #define ALT_FPGAMGR_IMGCFG_STAT_F2S_MSEL2_SET_MSK BIT(18)
  29. #define ALT_FPGAMGR_IMGCFG_STAT_F2S_MSEL_SET_MSD (\
  30. ALT_FPGAMGR_IMGCFG_STAT_F2S_MSEL0_SET_MSK |\
  31. ALT_FPGAMGR_IMGCFG_STAT_F2S_MSEL1_SET_MSK |\
  32. ALT_FPGAMGR_IMGCFG_STAT_F2S_MSEL2_SET_MSK)
  33. #define ALT_FPGAMGR_IMGCFG_STAT_F2S_IMGCFG_FIFOEMPTY_SET_MSK BIT(24)
  34. #define ALT_FPGAMGR_IMGCFG_STAT_F2S_IMGCFG_FIFOFULL_SET_MSK BIT(25)
  35. #define ALT_FPGAMGR_IMGCFG_STAT_F2S_JTAGM_SET_MSK BIT(28)
  36. #define ALT_FPGAMGR_IMGCFG_STAT_F2S_EMR_SET_MSK BIT(29)
  37. #define ALT_FPGAMGR_IMGCFG_STAT_F2S_MSEL0_LSB 16
  38. #define ALT_FPGAMGR_IMGCFG_CTL_00_S2F_NENABLE_NCONFIG_SET_MSK BIT(0)
  39. #define ALT_FPGAMGR_IMGCFG_CTL_00_S2F_NENABLE_NSTATUS_SET_MSK BIT(1)
  40. #define ALT_FPGAMGR_IMGCFG_CTL_00_S2F_NENABLE_CONDONE_SET_MSK BIT(2)
  41. #define ALT_FPGAMGR_IMGCFG_CTL_00_S2F_NCONFIG_SET_MSK BIT(8)
  42. #define ALT_FPGAMGR_IMGCFG_CTL_00_S2F_NSTATUS_OE_SET_MSK BIT(16)
  43. #define ALT_FPGAMGR_IMGCFG_CTL_00_S2F_CONDONE_OE_SET_MSK BIT(24)
  44. #define ALT_FPGAMGR_IMGCFG_CTL_01_S2F_NENABLE_CONFIG_SET_MSK BIT(0)
  45. #define ALT_FPGAMGR_IMGCFG_CTL_01_S2F_PR_REQUEST_SET_MSK BIT(16)
  46. #define ALT_FPGAMGR_IMGCFG_CTL_01_S2F_NCE_SET_MSK BIT(24)
  47. #define ALT_FPGAMGR_IMGCFG_CTL_02_EN_CFG_CTRL_SET_MSK BIT(0)
  48. #define ALT_FPGAMGR_IMGCFG_CTL_02_EN_CFG_DATA_SET_MSK BIT(8)
  49. #define ALT_FPGAMGR_IMGCFG_CTL_02_CDRATIO_SET_MSK 0x00030000
  50. #define ALT_FPGAMGR_IMGCFG_CTL_02_CFGWIDTH_SET_MSK BIT(24)
  51. #define ALT_FPGAMGR_IMGCFG_CTL_02_CDRATIO_LSB 16
  52. #define FPGA_SOCFPGA_A10_RBF_UNENCRYPTED 0xa65c
  53. #define FPGA_SOCFPGA_A10_RBF_ENCRYPTED 0xa65d
  54. #define FPGA_SOCFPGA_A10_RBF_PERIPH 0x0001
  55. #define FPGA_SOCFPGA_A10_RBF_CORE 0x8001
  56. #ifndef __ASSEMBLY__
  57. struct socfpga_fpga_manager {
  58. u32 _pad_0x0_0x7[2];
  59. u32 dclkcnt;
  60. u32 dclkstat;
  61. u32 gpo;
  62. u32 gpi;
  63. u32 misci;
  64. u32 _pad_0x1c_0x2f[5];
  65. u32 emr_data0;
  66. u32 emr_data1;
  67. u32 emr_data2;
  68. u32 emr_data3;
  69. u32 emr_data4;
  70. u32 emr_data5;
  71. u32 emr_valid;
  72. u32 emr_en;
  73. u32 jtag_config;
  74. u32 jtag_status;
  75. u32 jtag_kick;
  76. u32 _pad_0x5c_0x5f;
  77. u32 jtag_data_w;
  78. u32 jtag_data_r;
  79. u32 _pad_0x68_0x6f[2];
  80. u32 imgcfg_ctrl_00;
  81. u32 imgcfg_ctrl_01;
  82. u32 imgcfg_ctrl_02;
  83. u32 _pad_0x7c_0x7f;
  84. u32 imgcfg_stat;
  85. u32 intr_masked_status;
  86. u32 intr_mask;
  87. u32 intr_polarity;
  88. u32 dma_config;
  89. u32 imgcfg_fifo_status;
  90. };
  91. enum rbf_type {
  92. unknown,
  93. periph_section,
  94. core_section
  95. };
  96. enum rbf_security {
  97. invalid,
  98. unencrypted,
  99. encrypted
  100. };
  101. struct rbf_info {
  102. enum rbf_type section;
  103. enum rbf_security security;
  104. };
  105. struct fpga_loadfs_info {
  106. fpga_fs_info *fpga_fsinfo;
  107. u32 remaining;
  108. u32 offset;
  109. struct rbf_info rbfinfo;
  110. };
  111. /* Functions */
  112. int fpgamgr_program_init(u32 * rbf_data, size_t rbf_size);
  113. int fpgamgr_program_finish(void);
  114. int is_fpgamgr_user_mode(void);
  115. int fpgamgr_wait_early_user_mode(void);
  116. const char *get_fpga_filename(void);
  117. int is_fpgamgr_early_user_mode(void);
  118. int socfpga_loadfs(fpga_fs_info *fpga_fsinfo, const void *buf, size_t bsize,
  119. u32 offset);
  120. void fpgamgr_program(const void *buf, size_t bsize, u32 offset);
  121. #endif /* __ASSEMBLY__ */
  122. #endif /* _FPGA_MANAGER_ARRIA10_H_ */