mipsregs.h 91 KB

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  1. /* SPDX-License-Identifier: GPL-2.0 */
  2. /*
  3. * Copyright (C) 1994, 1995, 1996, 1997, 2000, 2001 by Ralf Baechle
  4. * Copyright (C) 2000 Silicon Graphics, Inc.
  5. * Modified for further R[236]000 support by Paul M. Antoine, 1996.
  6. * Kevin D. Kissell, kevink@mips.com and Carsten Langgaard, carstenl@mips.com
  7. * Copyright (C) 2000, 07 MIPS Technologies, Inc.
  8. * Copyright (C) 2003, 2004 Maciej W. Rozycki
  9. */
  10. #ifndef _ASM_MIPSREGS_H
  11. #define _ASM_MIPSREGS_H
  12. #include <asm/compiler.h>
  13. #include <asm/isa-rev.h>
  14. /*
  15. * The following macros are especially useful for __asm__
  16. * inline assembler.
  17. */
  18. #ifndef __STR
  19. #define __STR(x) #x
  20. #endif
  21. #ifndef STR
  22. #define STR(x) __STR(x)
  23. #endif
  24. /*
  25. * Configure language
  26. */
  27. #ifdef __ASSEMBLY__
  28. #define _ULCAST_
  29. #define _U64CAST_
  30. #else
  31. #define _ULCAST_ (unsigned long)
  32. #define _U64CAST_ (u64)
  33. #endif
  34. /*
  35. * Coprocessor 0 register names
  36. */
  37. #define CP0_INDEX $0
  38. #define CP0_RANDOM $1
  39. #define CP0_ENTRYLO0 $2
  40. #define CP0_ENTRYLO1 $3
  41. #define CP0_CONF $3
  42. #define CP0_GLOBALNUMBER $3, 1
  43. #define CP0_CONTEXT $4
  44. #define CP0_PAGEMASK $5
  45. #define CP0_PAGEGRAIN $5, 1
  46. #define CP0_SEGCTL0 $5, 2
  47. #define CP0_SEGCTL1 $5, 3
  48. #define CP0_SEGCTL2 $5, 4
  49. #define CP0_WIRED $6
  50. #define CP0_INFO $7
  51. #define CP0_HWRENA $7
  52. #define CP0_BADVADDR $8
  53. #define CP0_BADINSTR $8, 1
  54. #define CP0_COUNT $9
  55. #define CP0_ENTRYHI $10
  56. #define CP0_GUESTCTL1 $10, 4
  57. #define CP0_GUESTCTL2 $10, 5
  58. #define CP0_GUESTCTL3 $10, 6
  59. #define CP0_COMPARE $11
  60. #define CP0_GUESTCTL0EXT $11, 4
  61. #define CP0_STATUS $12
  62. #define CP0_GUESTCTL0 $12, 6
  63. #define CP0_GTOFFSET $12, 7
  64. #define CP0_CAUSE $13
  65. #define CP0_EPC $14
  66. #define CP0_PRID $15
  67. #define CP0_EBASE $15, 1
  68. #define CP0_CMGCRBASE $15, 3
  69. #define CP0_CONFIG $16
  70. #define CP0_CONFIG3 $16, 3
  71. #define CP0_CONFIG5 $16, 5
  72. #define CP0_CONFIG6 $16, 6
  73. #define CP0_LLADDR $17
  74. #define CP0_WATCHLO $18
  75. #define CP0_WATCHHI $19
  76. #define CP0_XCONTEXT $20
  77. #define CP0_FRAMEMASK $21
  78. #define CP0_DIAGNOSTIC $22
  79. #define CP0_DEBUG $23
  80. #define CP0_DEPC $24
  81. #define CP0_PERFORMANCE $25
  82. #define CP0_ECC $26
  83. #define CP0_CACHEERR $27
  84. #define CP0_TAGLO $28
  85. #define CP0_TAGHI $29
  86. #define CP0_ERROREPC $30
  87. #define CP0_DESAVE $31
  88. /*
  89. * R4640/R4650 cp0 register names. These registers are listed
  90. * here only for completeness; without MMU these CPUs are not useable
  91. * by Linux. A future ELKS port might take make Linux run on them
  92. * though ...
  93. */
  94. #define CP0_IBASE $0
  95. #define CP0_IBOUND $1
  96. #define CP0_DBASE $2
  97. #define CP0_DBOUND $3
  98. #define CP0_CALG $17
  99. #define CP0_IWATCH $18
  100. #define CP0_DWATCH $19
  101. /*
  102. * Coprocessor 0 Set 1 register names
  103. */
  104. #define CP0_S1_DERRADDR0 $26
  105. #define CP0_S1_DERRADDR1 $27
  106. #define CP0_S1_INTCONTROL $20
  107. /*
  108. * Coprocessor 0 Set 2 register names
  109. */
  110. #define CP0_S2_SRSCTL $12 /* MIPSR2 */
  111. /*
  112. * Coprocessor 0 Set 3 register names
  113. */
  114. #define CP0_S3_SRSMAP $12 /* MIPSR2 */
  115. /*
  116. * TX39 Series
  117. */
  118. #define CP0_TX39_CACHE $7
  119. /* Generic EntryLo bit definitions */
  120. #define ENTRYLO_G (_ULCAST_(1) << 0)
  121. #define ENTRYLO_V (_ULCAST_(1) << 1)
  122. #define ENTRYLO_D (_ULCAST_(1) << 2)
  123. #define ENTRYLO_C_SHIFT 3
  124. #define ENTRYLO_C (_ULCAST_(7) << ENTRYLO_C_SHIFT)
  125. /* R3000 EntryLo bit definitions */
  126. #define R3K_ENTRYLO_G (_ULCAST_(1) << 8)
  127. #define R3K_ENTRYLO_V (_ULCAST_(1) << 9)
  128. #define R3K_ENTRYLO_D (_ULCAST_(1) << 10)
  129. #define R3K_ENTRYLO_N (_ULCAST_(1) << 11)
  130. /* MIPS32/64 EntryLo bit definitions */
  131. #define MIPS_ENTRYLO_PFN_SHIFT 6
  132. #define MIPS_ENTRYLO_XI (_ULCAST_(1) << (BITS_PER_LONG - 2))
  133. #define MIPS_ENTRYLO_RI (_ULCAST_(1) << (BITS_PER_LONG - 1))
  134. /*
  135. * MIPSr6+ GlobalNumber register definitions
  136. */
  137. #define MIPS_GLOBALNUMBER_VP_SHF 0
  138. #define MIPS_GLOBALNUMBER_VP (_ULCAST_(0xff) << MIPS_GLOBALNUMBER_VP_SHF)
  139. #define MIPS_GLOBALNUMBER_CORE_SHF 8
  140. #define MIPS_GLOBALNUMBER_CORE (_ULCAST_(0xff) << MIPS_GLOBALNUMBER_CORE_SHF)
  141. #define MIPS_GLOBALNUMBER_CLUSTER_SHF 16
  142. #define MIPS_GLOBALNUMBER_CLUSTER (_ULCAST_(0xf) << MIPS_GLOBALNUMBER_CLUSTER_SHF)
  143. /*
  144. * Values for PageMask register
  145. */
  146. #ifdef CONFIG_CPU_VR41XX
  147. /* Why doesn't stupidity hurt ... */
  148. #define PM_1K 0x00000000
  149. #define PM_4K 0x00001800
  150. #define PM_16K 0x00007800
  151. #define PM_64K 0x0001f800
  152. #define PM_256K 0x0007f800
  153. #else
  154. #define PM_4K 0x00000000
  155. #define PM_8K 0x00002000
  156. #define PM_16K 0x00006000
  157. #define PM_32K 0x0000e000
  158. #define PM_64K 0x0001e000
  159. #define PM_128K 0x0003e000
  160. #define PM_256K 0x0007e000
  161. #define PM_512K 0x000fe000
  162. #define PM_1M 0x001fe000
  163. #define PM_2M 0x003fe000
  164. #define PM_4M 0x007fe000
  165. #define PM_8M 0x00ffe000
  166. #define PM_16M 0x01ffe000
  167. #define PM_32M 0x03ffe000
  168. #define PM_64M 0x07ffe000
  169. #define PM_256M 0x1fffe000
  170. #define PM_1G 0x7fffe000
  171. #endif
  172. /*
  173. * Values used for computation of new tlb entries
  174. */
  175. #define PL_4K 12
  176. #define PL_16K 14
  177. #define PL_64K 16
  178. #define PL_256K 18
  179. #define PL_1M 20
  180. #define PL_4M 22
  181. #define PL_16M 24
  182. #define PL_64M 26
  183. #define PL_256M 28
  184. /*
  185. * PageGrain bits
  186. */
  187. #define PG_RIE (_ULCAST_(1) << 31)
  188. #define PG_XIE (_ULCAST_(1) << 30)
  189. #define PG_ELPA (_ULCAST_(1) << 29)
  190. #define PG_ESP (_ULCAST_(1) << 28)
  191. #define PG_IEC (_ULCAST_(1) << 27)
  192. /* MIPS32/64 EntryHI bit definitions */
  193. #define MIPS_ENTRYHI_EHINV (_ULCAST_(1) << 10)
  194. #define MIPS_ENTRYHI_ASIDX (_ULCAST_(0x3) << 8)
  195. #define MIPS_ENTRYHI_ASID (_ULCAST_(0xff) << 0)
  196. /*
  197. * R4x00 interrupt enable / cause bits
  198. */
  199. #define IE_SW0 (_ULCAST_(1) << 8)
  200. #define IE_SW1 (_ULCAST_(1) << 9)
  201. #define IE_IRQ0 (_ULCAST_(1) << 10)
  202. #define IE_IRQ1 (_ULCAST_(1) << 11)
  203. #define IE_IRQ2 (_ULCAST_(1) << 12)
  204. #define IE_IRQ3 (_ULCAST_(1) << 13)
  205. #define IE_IRQ4 (_ULCAST_(1) << 14)
  206. #define IE_IRQ5 (_ULCAST_(1) << 15)
  207. /*
  208. * R4x00 interrupt cause bits
  209. */
  210. #define C_SW0 (_ULCAST_(1) << 8)
  211. #define C_SW1 (_ULCAST_(1) << 9)
  212. #define C_IRQ0 (_ULCAST_(1) << 10)
  213. #define C_IRQ1 (_ULCAST_(1) << 11)
  214. #define C_IRQ2 (_ULCAST_(1) << 12)
  215. #define C_IRQ3 (_ULCAST_(1) << 13)
  216. #define C_IRQ4 (_ULCAST_(1) << 14)
  217. #define C_IRQ5 (_ULCAST_(1) << 15)
  218. /*
  219. * Bitfields in the R4xx0 cp0 status register
  220. */
  221. #define ST0_IE 0x00000001
  222. #define ST0_EXL 0x00000002
  223. #define ST0_ERL 0x00000004
  224. #define ST0_KSU 0x00000018
  225. # define KSU_USER 0x00000010
  226. # define KSU_SUPERVISOR 0x00000008
  227. # define KSU_KERNEL 0x00000000
  228. #define ST0_UX 0x00000020
  229. #define ST0_SX 0x00000040
  230. #define ST0_KX 0x00000080
  231. #define ST0_DE 0x00010000
  232. #define ST0_CE 0x00020000
  233. /*
  234. * Setting c0_status.co enables Hit_Writeback and Hit_Writeback_Invalidate
  235. * cacheops in userspace. This bit exists only on RM7000 and RM9000
  236. * processors.
  237. */
  238. #define ST0_CO 0x08000000
  239. /*
  240. * Bitfields in the R[23]000 cp0 status register.
  241. */
  242. #define ST0_IEC 0x00000001
  243. #define ST0_KUC 0x00000002
  244. #define ST0_IEP 0x00000004
  245. #define ST0_KUP 0x00000008
  246. #define ST0_IEO 0x00000010
  247. #define ST0_KUO 0x00000020
  248. /* bits 6 & 7 are reserved on R[23]000 */
  249. #define ST0_ISC 0x00010000
  250. #define ST0_SWC 0x00020000
  251. #define ST0_CM 0x00080000
  252. /*
  253. * Bits specific to the R4640/R4650
  254. */
  255. #define ST0_UM (_ULCAST_(1) << 4)
  256. #define ST0_IL (_ULCAST_(1) << 23)
  257. #define ST0_DL (_ULCAST_(1) << 24)
  258. /*
  259. * Enable the MIPS MDMX and DSP ASEs
  260. */
  261. #define ST0_MX 0x01000000
  262. /*
  263. * Status register bits available in all MIPS CPUs.
  264. */
  265. #define ST0_IM 0x0000ff00
  266. #define STATUSB_IP0 8
  267. #define STATUSF_IP0 (_ULCAST_(1) << 8)
  268. #define STATUSB_IP1 9
  269. #define STATUSF_IP1 (_ULCAST_(1) << 9)
  270. #define STATUSB_IP2 10
  271. #define STATUSF_IP2 (_ULCAST_(1) << 10)
  272. #define STATUSB_IP3 11
  273. #define STATUSF_IP3 (_ULCAST_(1) << 11)
  274. #define STATUSB_IP4 12
  275. #define STATUSF_IP4 (_ULCAST_(1) << 12)
  276. #define STATUSB_IP5 13
  277. #define STATUSF_IP5 (_ULCAST_(1) << 13)
  278. #define STATUSB_IP6 14
  279. #define STATUSF_IP6 (_ULCAST_(1) << 14)
  280. #define STATUSB_IP7 15
  281. #define STATUSF_IP7 (_ULCAST_(1) << 15)
  282. #define STATUSB_IP8 0
  283. #define STATUSF_IP8 (_ULCAST_(1) << 0)
  284. #define STATUSB_IP9 1
  285. #define STATUSF_IP9 (_ULCAST_(1) << 1)
  286. #define STATUSB_IP10 2
  287. #define STATUSF_IP10 (_ULCAST_(1) << 2)
  288. #define STATUSB_IP11 3
  289. #define STATUSF_IP11 (_ULCAST_(1) << 3)
  290. #define STATUSB_IP12 4
  291. #define STATUSF_IP12 (_ULCAST_(1) << 4)
  292. #define STATUSB_IP13 5
  293. #define STATUSF_IP13 (_ULCAST_(1) << 5)
  294. #define STATUSB_IP14 6
  295. #define STATUSF_IP14 (_ULCAST_(1) << 6)
  296. #define STATUSB_IP15 7
  297. #define STATUSF_IP15 (_ULCAST_(1) << 7)
  298. #define ST0_IMPL (_ULCAST_(3) << 16)
  299. #define ST0_CH 0x00040000
  300. #define ST0_NMI 0x00080000
  301. #define ST0_SR 0x00100000
  302. #define ST0_TS 0x00200000
  303. #define ST0_BEV 0x00400000
  304. #define ST0_RE 0x02000000
  305. #define ST0_FR 0x04000000
  306. #define ST0_CU 0xf0000000
  307. #define ST0_CU0 0x10000000
  308. #define ST0_CU1 0x20000000
  309. #define ST0_CU2 0x40000000
  310. #define ST0_CU3 0x80000000
  311. #define ST0_XX 0x80000000 /* MIPS IV naming */
  312. /*
  313. * Bitfields and bit numbers in the coprocessor 0 IntCtl register. (MIPSR2)
  314. */
  315. #define INTCTLB_IPFDC 23
  316. #define INTCTLF_IPFDC (_ULCAST_(7) << INTCTLB_IPFDC)
  317. #define INTCTLB_IPPCI 26
  318. #define INTCTLF_IPPCI (_ULCAST_(7) << INTCTLB_IPPCI)
  319. #define INTCTLB_IPTI 29
  320. #define INTCTLF_IPTI (_ULCAST_(7) << INTCTLB_IPTI)
  321. /*
  322. * Bitfields and bit numbers in the coprocessor 0 cause register.
  323. *
  324. * Refer to your MIPS R4xx0 manual, chapter 5 for explanation.
  325. */
  326. #define CAUSEB_EXCCODE 2
  327. #define CAUSEF_EXCCODE (_ULCAST_(31) << 2)
  328. #define CAUSEB_IP 8
  329. #define CAUSEF_IP (_ULCAST_(255) << 8)
  330. #define CAUSEB_IP0 8
  331. #define CAUSEF_IP0 (_ULCAST_(1) << 8)
  332. #define CAUSEB_IP1 9
  333. #define CAUSEF_IP1 (_ULCAST_(1) << 9)
  334. #define CAUSEB_IP2 10
  335. #define CAUSEF_IP2 (_ULCAST_(1) << 10)
  336. #define CAUSEB_IP3 11
  337. #define CAUSEF_IP3 (_ULCAST_(1) << 11)
  338. #define CAUSEB_IP4 12
  339. #define CAUSEF_IP4 (_ULCAST_(1) << 12)
  340. #define CAUSEB_IP5 13
  341. #define CAUSEF_IP5 (_ULCAST_(1) << 13)
  342. #define CAUSEB_IP6 14
  343. #define CAUSEF_IP6 (_ULCAST_(1) << 14)
  344. #define CAUSEB_IP7 15
  345. #define CAUSEF_IP7 (_ULCAST_(1) << 15)
  346. #define CAUSEB_FDCI 21
  347. #define CAUSEF_FDCI (_ULCAST_(1) << 21)
  348. #define CAUSEB_WP 22
  349. #define CAUSEF_WP (_ULCAST_(1) << 22)
  350. #define CAUSEB_IV 23
  351. #define CAUSEF_IV (_ULCAST_(1) << 23)
  352. #define CAUSEB_PCI 26
  353. #define CAUSEF_PCI (_ULCAST_(1) << 26)
  354. #define CAUSEB_DC 27
  355. #define CAUSEF_DC (_ULCAST_(1) << 27)
  356. #define CAUSEB_CE 28
  357. #define CAUSEF_CE (_ULCAST_(3) << 28)
  358. #define CAUSEB_TI 30
  359. #define CAUSEF_TI (_ULCAST_(1) << 30)
  360. #define CAUSEB_BD 31
  361. #define CAUSEF_BD (_ULCAST_(1) << 31)
  362. /*
  363. * Cause.ExcCode trap codes.
  364. */
  365. #define EXCCODE_INT 0 /* Interrupt pending */
  366. #define EXCCODE_MOD 1 /* TLB modified fault */
  367. #define EXCCODE_TLBL 2 /* TLB miss on load or ifetch */
  368. #define EXCCODE_TLBS 3 /* TLB miss on a store */
  369. #define EXCCODE_ADEL 4 /* Address error on a load or ifetch */
  370. #define EXCCODE_ADES 5 /* Address error on a store */
  371. #define EXCCODE_IBE 6 /* Bus error on an ifetch */
  372. #define EXCCODE_DBE 7 /* Bus error on a load or store */
  373. #define EXCCODE_SYS 8 /* System call */
  374. #define EXCCODE_BP 9 /* Breakpoint */
  375. #define EXCCODE_RI 10 /* Reserved instruction exception */
  376. #define EXCCODE_CPU 11 /* Coprocessor unusable */
  377. #define EXCCODE_OV 12 /* Arithmetic overflow */
  378. #define EXCCODE_TR 13 /* Trap instruction */
  379. #define EXCCODE_MSAFPE 14 /* MSA floating point exception */
  380. #define EXCCODE_FPE 15 /* Floating point exception */
  381. #define EXCCODE_TLBRI 19 /* TLB Read-Inhibit exception */
  382. #define EXCCODE_TLBXI 20 /* TLB Execution-Inhibit exception */
  383. #define EXCCODE_MSADIS 21 /* MSA disabled exception */
  384. #define EXCCODE_MDMX 22 /* MDMX unusable exception */
  385. #define EXCCODE_WATCH 23 /* Watch address reference */
  386. #define EXCCODE_MCHECK 24 /* Machine check */
  387. #define EXCCODE_THREAD 25 /* Thread exceptions (MT) */
  388. #define EXCCODE_DSPDIS 26 /* DSP disabled exception */
  389. #define EXCCODE_GE 27 /* Virtualized guest exception (VZ) */
  390. /* Implementation specific trap codes used by MIPS cores */
  391. #define MIPS_EXCCODE_TLBPAR 16 /* TLB parity error exception */
  392. /*
  393. * Bits in the coprocessor 0 config register.
  394. */
  395. /* Generic bits. */
  396. #define CONF_CM_CACHABLE_NO_WA 0
  397. #define CONF_CM_CACHABLE_WA 1
  398. #define CONF_CM_UNCACHED 2
  399. #define CONF_CM_CACHABLE_NONCOHERENT 3
  400. #define CONF_CM_CACHABLE_CE 4
  401. #define CONF_CM_CACHABLE_COW 5
  402. #define CONF_CM_CACHABLE_CUW 6
  403. #define CONF_CM_CACHABLE_ACCELERATED 7
  404. #define CONF_CM_CMASK 7
  405. #define CONF_BE (_ULCAST_(1) << 15)
  406. /* Bits common to various processors. */
  407. #define CONF_CU (_ULCAST_(1) << 3)
  408. #define CONF_DB (_ULCAST_(1) << 4)
  409. #define CONF_IB (_ULCAST_(1) << 5)
  410. #define CONF_DC (_ULCAST_(7) << 6)
  411. #define CONF_IC (_ULCAST_(7) << 9)
  412. #define CONF_EB (_ULCAST_(1) << 13)
  413. #define CONF_EM (_ULCAST_(1) << 14)
  414. #define CONF_SM (_ULCAST_(1) << 16)
  415. #define CONF_SC (_ULCAST_(1) << 17)
  416. #define CONF_EW (_ULCAST_(3) << 18)
  417. #define CONF_EP (_ULCAST_(15)<< 24)
  418. #define CONF_EC (_ULCAST_(7) << 28)
  419. #define CONF_CM (_ULCAST_(1) << 31)
  420. /* Bits specific to the R4xx0. */
  421. #define R4K_CONF_SW (_ULCAST_(1) << 20)
  422. #define R4K_CONF_SS (_ULCAST_(1) << 21)
  423. #define R4K_CONF_SB (_ULCAST_(3) << 22)
  424. /* Bits specific to the R5000. */
  425. #define R5K_CONF_SE (_ULCAST_(1) << 12)
  426. #define R5K_CONF_SS (_ULCAST_(3) << 20)
  427. /* Bits specific to the RM7000. */
  428. #define RM7K_CONF_SE (_ULCAST_(1) << 3)
  429. #define RM7K_CONF_TE (_ULCAST_(1) << 12)
  430. #define RM7K_CONF_CLK (_ULCAST_(1) << 16)
  431. #define RM7K_CONF_TC (_ULCAST_(1) << 17)
  432. #define RM7K_CONF_SI (_ULCAST_(3) << 20)
  433. #define RM7K_CONF_SC (_ULCAST_(1) << 31)
  434. /* Bits specific to the R10000. */
  435. #define R10K_CONF_DN (_ULCAST_(3) << 3)
  436. #define R10K_CONF_CT (_ULCAST_(1) << 5)
  437. #define R10K_CONF_PE (_ULCAST_(1) << 6)
  438. #define R10K_CONF_PM (_ULCAST_(3) << 7)
  439. #define R10K_CONF_EC (_ULCAST_(15)<< 9)
  440. #define R10K_CONF_SB (_ULCAST_(1) << 13)
  441. #define R10K_CONF_SK (_ULCAST_(1) << 14)
  442. #define R10K_CONF_SS (_ULCAST_(7) << 16)
  443. #define R10K_CONF_SC (_ULCAST_(7) << 19)
  444. #define R10K_CONF_DC (_ULCAST_(7) << 26)
  445. #define R10K_CONF_IC (_ULCAST_(7) << 29)
  446. /* Bits specific to the VR41xx. */
  447. #define VR41_CONF_CS (_ULCAST_(1) << 12)
  448. #define VR41_CONF_P4K (_ULCAST_(1) << 13)
  449. #define VR41_CONF_BP (_ULCAST_(1) << 16)
  450. #define VR41_CONF_M16 (_ULCAST_(1) << 20)
  451. #define VR41_CONF_AD (_ULCAST_(1) << 23)
  452. /* Bits specific to the R30xx. */
  453. #define R30XX_CONF_FDM (_ULCAST_(1) << 19)
  454. #define R30XX_CONF_REV (_ULCAST_(1) << 22)
  455. #define R30XX_CONF_AC (_ULCAST_(1) << 23)
  456. #define R30XX_CONF_RF (_ULCAST_(1) << 24)
  457. #define R30XX_CONF_HALT (_ULCAST_(1) << 25)
  458. #define R30XX_CONF_FPINT (_ULCAST_(7) << 26)
  459. #define R30XX_CONF_DBR (_ULCAST_(1) << 29)
  460. #define R30XX_CONF_SB (_ULCAST_(1) << 30)
  461. #define R30XX_CONF_LOCK (_ULCAST_(1) << 31)
  462. /* Bits specific to the TX49. */
  463. #define TX49_CONF_DC (_ULCAST_(1) << 16)
  464. #define TX49_CONF_IC (_ULCAST_(1) << 17) /* conflict with CONF_SC */
  465. #define TX49_CONF_HALT (_ULCAST_(1) << 18)
  466. #define TX49_CONF_CWFON (_ULCAST_(1) << 27)
  467. /* Bits specific to the MIPS32/64 PRA. */
  468. #define MIPS_CONF_VI (_ULCAST_(1) << 3)
  469. #define MIPS_CONF_MT (_ULCAST_(7) << 7)
  470. #define MIPS_CONF_MT_TLB (_ULCAST_(1) << 7)
  471. #define MIPS_CONF_MT_FTLB (_ULCAST_(4) << 7)
  472. #define MIPS_CONF_AR (_ULCAST_(7) << 10)
  473. #define MIPS_CONF_AT (_ULCAST_(3) << 13)
  474. #define MIPS_CONF_IMPL (_ULCAST_(0x1ff) << 16)
  475. #define MIPS_CONF_M (_ULCAST_(1) << 31)
  476. /*
  477. * Bits in the MIPS32/64 PRA coprocessor 0 config registers 1 and above.
  478. */
  479. #define MIPS_CONF1_FP (_ULCAST_(1) << 0)
  480. #define MIPS_CONF1_EP (_ULCAST_(1) << 1)
  481. #define MIPS_CONF1_CA (_ULCAST_(1) << 2)
  482. #define MIPS_CONF1_WR (_ULCAST_(1) << 3)
  483. #define MIPS_CONF1_PC (_ULCAST_(1) << 4)
  484. #define MIPS_CONF1_MD (_ULCAST_(1) << 5)
  485. #define MIPS_CONF1_C2 (_ULCAST_(1) << 6)
  486. #define MIPS_CONF1_DA_SHF 7
  487. #define MIPS_CONF1_DA_SZ 3
  488. #define MIPS_CONF1_DA (_ULCAST_(7) << 7)
  489. #define MIPS_CONF1_DL_SHF 10
  490. #define MIPS_CONF1_DL_SZ 3
  491. #define MIPS_CONF1_DL (_ULCAST_(7) << 10)
  492. #define MIPS_CONF1_DS_SHF 13
  493. #define MIPS_CONF1_DS_SZ 3
  494. #define MIPS_CONF1_DS (_ULCAST_(7) << 13)
  495. #define MIPS_CONF1_IA_SHF 16
  496. #define MIPS_CONF1_IA_SZ 3
  497. #define MIPS_CONF1_IA (_ULCAST_(7) << 16)
  498. #define MIPS_CONF1_IL_SHF 19
  499. #define MIPS_CONF1_IL_SZ 3
  500. #define MIPS_CONF1_IL (_ULCAST_(7) << 19)
  501. #define MIPS_CONF1_IS_SHF 22
  502. #define MIPS_CONF1_IS_SZ 3
  503. #define MIPS_CONF1_IS (_ULCAST_(7) << 22)
  504. #define MIPS_CONF1_TLBS_SHIFT (25)
  505. #define MIPS_CONF1_TLBS_SIZE (6)
  506. #define MIPS_CONF1_TLBS (_ULCAST_(63) << MIPS_CONF1_TLBS_SHIFT)
  507. #define MIPS_CONF2_SA_SHF 0
  508. #define MIPS_CONF2_SA (_ULCAST_(15) << 0)
  509. #define MIPS_CONF2_SL_SHF 4
  510. #define MIPS_CONF2_SL (_ULCAST_(15) << 4)
  511. #define MIPS_CONF2_SS_SHF 8
  512. #define MIPS_CONF2_SS (_ULCAST_(15) << 8)
  513. #define MIPS_CONF2_L2B (_ULCAST_(1) << 12)
  514. #define MIPS_CONF2_SU (_ULCAST_(15) << 12)
  515. #define MIPS_CONF2_TA (_ULCAST_(15) << 16)
  516. #define MIPS_CONF2_TL (_ULCAST_(15) << 20)
  517. #define MIPS_CONF2_TS (_ULCAST_(15) << 24)
  518. #define MIPS_CONF2_TU (_ULCAST_(7) << 28)
  519. #define MIPS_CONF3_TL (_ULCAST_(1) << 0)
  520. #define MIPS_CONF3_SM (_ULCAST_(1) << 1)
  521. #define MIPS_CONF3_MT (_ULCAST_(1) << 2)
  522. #define MIPS_CONF3_CDMM (_ULCAST_(1) << 3)
  523. #define MIPS_CONF3_SP (_ULCAST_(1) << 4)
  524. #define MIPS_CONF3_VINT (_ULCAST_(1) << 5)
  525. #define MIPS_CONF3_VEIC (_ULCAST_(1) << 6)
  526. #define MIPS_CONF3_LPA (_ULCAST_(1) << 7)
  527. #define MIPS_CONF3_ITL (_ULCAST_(1) << 8)
  528. #define MIPS_CONF3_CTXTC (_ULCAST_(1) << 9)
  529. #define MIPS_CONF3_DSP (_ULCAST_(1) << 10)
  530. #define MIPS_CONF3_DSP2P (_ULCAST_(1) << 11)
  531. #define MIPS_CONF3_RXI (_ULCAST_(1) << 12)
  532. #define MIPS_CONF3_ULRI (_ULCAST_(1) << 13)
  533. #define MIPS_CONF3_ISA (_ULCAST_(3) << 14)
  534. #define MIPS_CONF3_ISA_OE (_ULCAST_(1) << 16)
  535. #define MIPS_CONF3_MCU (_ULCAST_(1) << 17)
  536. #define MIPS_CONF3_MMAR (_ULCAST_(7) << 18)
  537. #define MIPS_CONF3_IPLW (_ULCAST_(3) << 21)
  538. #define MIPS_CONF3_VZ (_ULCAST_(1) << 23)
  539. #define MIPS_CONF3_PW (_ULCAST_(1) << 24)
  540. #define MIPS_CONF3_SC (_ULCAST_(1) << 25)
  541. #define MIPS_CONF3_BI (_ULCAST_(1) << 26)
  542. #define MIPS_CONF3_BP (_ULCAST_(1) << 27)
  543. #define MIPS_CONF3_MSA (_ULCAST_(1) << 28)
  544. #define MIPS_CONF3_CMGCR (_ULCAST_(1) << 29)
  545. #define MIPS_CONF3_BPG (_ULCAST_(1) << 30)
  546. #define MIPS_CONF4_MMUSIZEEXT_SHIFT (0)
  547. #define MIPS_CONF4_MMUSIZEEXT (_ULCAST_(255) << 0)
  548. #define MIPS_CONF4_FTLBSETS_SHIFT (0)
  549. #define MIPS_CONF4_FTLBSETS (_ULCAST_(15) << MIPS_CONF4_FTLBSETS_SHIFT)
  550. #define MIPS_CONF4_FTLBWAYS_SHIFT (4)
  551. #define MIPS_CONF4_FTLBWAYS (_ULCAST_(15) << MIPS_CONF4_FTLBWAYS_SHIFT)
  552. #define MIPS_CONF4_FTLBPAGESIZE_SHIFT (8)
  553. /* bits 10:8 in FTLB-only configurations */
  554. #define MIPS_CONF4_FTLBPAGESIZE (_ULCAST_(7) << MIPS_CONF4_FTLBPAGESIZE_SHIFT)
  555. /* bits 12:8 in VTLB-FTLB only configurations */
  556. #define MIPS_CONF4_VFTLBPAGESIZE (_ULCAST_(31) << MIPS_CONF4_FTLBPAGESIZE_SHIFT)
  557. #define MIPS_CONF4_MMUEXTDEF (_ULCAST_(3) << 14)
  558. #define MIPS_CONF4_MMUEXTDEF_MMUSIZEEXT (_ULCAST_(1) << 14)
  559. #define MIPS_CONF4_MMUEXTDEF_FTLBSIZEEXT (_ULCAST_(2) << 14)
  560. #define MIPS_CONF4_MMUEXTDEF_VTLBSIZEEXT (_ULCAST_(3) << 14)
  561. #define MIPS_CONF4_KSCREXIST_SHIFT (16)
  562. #define MIPS_CONF4_KSCREXIST (_ULCAST_(255) << MIPS_CONF4_KSCREXIST_SHIFT)
  563. #define MIPS_CONF4_VTLBSIZEEXT_SHIFT (24)
  564. #define MIPS_CONF4_VTLBSIZEEXT (_ULCAST_(15) << MIPS_CONF4_VTLBSIZEEXT_SHIFT)
  565. #define MIPS_CONF4_AE (_ULCAST_(1) << 28)
  566. #define MIPS_CONF4_IE (_ULCAST_(3) << 29)
  567. #define MIPS_CONF4_TLBINV (_ULCAST_(2) << 29)
  568. #define MIPS_CONF5_NF (_ULCAST_(1) << 0)
  569. #define MIPS_CONF5_UFR (_ULCAST_(1) << 2)
  570. #define MIPS_CONF5_MRP (_ULCAST_(1) << 3)
  571. #define MIPS_CONF5_LLB (_ULCAST_(1) << 4)
  572. #define MIPS_CONF5_MVH (_ULCAST_(1) << 5)
  573. #define MIPS_CONF5_VP (_ULCAST_(1) << 7)
  574. #define MIPS_CONF5_SBRI (_ULCAST_(1) << 6)
  575. #define MIPS_CONF5_FRE (_ULCAST_(1) << 8)
  576. #define MIPS_CONF5_UFE (_ULCAST_(1) << 9)
  577. #define MIPS_CONF5_L2C (_ULCAST_(1) << 10)
  578. #define MIPS_CONF5_CA2 (_ULCAST_(1) << 14)
  579. #define MIPS_CONF5_MI (_ULCAST_(1) << 17)
  580. #define MIPS_CONF5_CRCP (_ULCAST_(1) << 18)
  581. #define MIPS_CONF5_MSAEN (_ULCAST_(1) << 27)
  582. #define MIPS_CONF5_EVA (_ULCAST_(1) << 28)
  583. #define MIPS_CONF5_CV (_ULCAST_(1) << 29)
  584. #define MIPS_CONF5_K (_ULCAST_(1) << 30)
  585. #define MIPS_CONF6_SYND (_ULCAST_(1) << 13)
  586. /* proAptiv FTLB on/off bit */
  587. #define MIPS_CONF6_FTLBEN (_ULCAST_(1) << 15)
  588. /* Loongson-3 FTLB on/off bit */
  589. #define MIPS_CONF6_FTLBDIS (_ULCAST_(1) << 22)
  590. /* FTLB probability bits */
  591. #define MIPS_CONF6_FTLBP_SHIFT (16)
  592. #define MIPS_CONF7_WII (_ULCAST_(1) << 31)
  593. #define MIPS_CONF7_RPS (_ULCAST_(1) << 2)
  594. #define MIPS_CONF7_IAR (_ULCAST_(1) << 10)
  595. #define MIPS_CONF7_AR (_ULCAST_(1) << 16)
  596. /* Ingenic HPTLB off bits */
  597. #define XBURST_PAGECTRL_HPTLB_DIS 0xa9000000
  598. /* Ingenic Config7 bits */
  599. #define MIPS_CONF7_BTB_LOOP_EN (_ULCAST_(1) << 4)
  600. /* Config7 Bits specific to MIPS Technologies. */
  601. /* Performance counters implemented Per TC */
  602. #define MTI_CONF7_PTC (_ULCAST_(1) << 19)
  603. /* WatchLo* register definitions */
  604. #define MIPS_WATCHLO_IRW (_ULCAST_(0x7) << 0)
  605. /* WatchHi* register definitions */
  606. #define MIPS_WATCHHI_M (_ULCAST_(1) << 31)
  607. #define MIPS_WATCHHI_G (_ULCAST_(1) << 30)
  608. #define MIPS_WATCHHI_WM (_ULCAST_(0x3) << 28)
  609. #define MIPS_WATCHHI_WM_R_RVA (_ULCAST_(0) << 28)
  610. #define MIPS_WATCHHI_WM_R_GPA (_ULCAST_(1) << 28)
  611. #define MIPS_WATCHHI_WM_G_GVA (_ULCAST_(2) << 28)
  612. #define MIPS_WATCHHI_EAS (_ULCAST_(0x3) << 24)
  613. #define MIPS_WATCHHI_ASID (_ULCAST_(0xff) << 16)
  614. #define MIPS_WATCHHI_MASK (_ULCAST_(0x1ff) << 3)
  615. #define MIPS_WATCHHI_I (_ULCAST_(1) << 2)
  616. #define MIPS_WATCHHI_R (_ULCAST_(1) << 1)
  617. #define MIPS_WATCHHI_W (_ULCAST_(1) << 0)
  618. #define MIPS_WATCHHI_IRW (_ULCAST_(0x7) << 0)
  619. /* PerfCnt control register definitions */
  620. #define MIPS_PERFCTRL_EXL (_ULCAST_(1) << 0)
  621. #define MIPS_PERFCTRL_K (_ULCAST_(1) << 1)
  622. #define MIPS_PERFCTRL_S (_ULCAST_(1) << 2)
  623. #define MIPS_PERFCTRL_U (_ULCAST_(1) << 3)
  624. #define MIPS_PERFCTRL_IE (_ULCAST_(1) << 4)
  625. #define MIPS_PERFCTRL_EVENT_S 5
  626. #define MIPS_PERFCTRL_EVENT (_ULCAST_(0x3ff) << MIPS_PERFCTRL_EVENT_S)
  627. #define MIPS_PERFCTRL_PCTD (_ULCAST_(1) << 15)
  628. #define MIPS_PERFCTRL_EC (_ULCAST_(0x3) << 23)
  629. #define MIPS_PERFCTRL_EC_R (_ULCAST_(0) << 23)
  630. #define MIPS_PERFCTRL_EC_RI (_ULCAST_(1) << 23)
  631. #define MIPS_PERFCTRL_EC_G (_ULCAST_(2) << 23)
  632. #define MIPS_PERFCTRL_EC_GRI (_ULCAST_(3) << 23)
  633. #define MIPS_PERFCTRL_W (_ULCAST_(1) << 30)
  634. #define MIPS_PERFCTRL_M (_ULCAST_(1) << 31)
  635. /* PerfCnt control register MT extensions used by MIPS cores */
  636. #define MIPS_PERFCTRL_VPEID_S 16
  637. #define MIPS_PERFCTRL_VPEID (_ULCAST_(0xf) << MIPS_PERFCTRL_VPEID_S)
  638. #define MIPS_PERFCTRL_TCID_S 22
  639. #define MIPS_PERFCTRL_TCID (_ULCAST_(0xff) << MIPS_PERFCTRL_TCID_S)
  640. #define MIPS_PERFCTRL_MT_EN (_ULCAST_(0x3) << 20)
  641. #define MIPS_PERFCTRL_MT_EN_ALL (_ULCAST_(0) << 20)
  642. #define MIPS_PERFCTRL_MT_EN_VPE (_ULCAST_(1) << 20)
  643. #define MIPS_PERFCTRL_MT_EN_TC (_ULCAST_(2) << 20)
  644. /* PerfCnt control register MT extensions used by BMIPS5000 */
  645. #define BRCM_PERFCTRL_TC (_ULCAST_(1) << 30)
  646. /* PerfCnt control register MT extensions used by Netlogic XLR */
  647. #define XLR_PERFCTRL_ALLTHREADS (_ULCAST_(1) << 13)
  648. /* MAAR bit definitions */
  649. #define MIPS_MAAR_VH (_U64CAST_(1) << 63)
  650. #define MIPS_MAAR_ADDR ((BIT_ULL(BITS_PER_LONG - 12) - 1) << 12)
  651. #define MIPS_MAAR_ADDR_SHIFT 12
  652. #define MIPS_MAAR_S (_ULCAST_(1) << 1)
  653. #define MIPS_MAAR_VL (_ULCAST_(1) << 0)
  654. /* MAARI bit definitions */
  655. #define MIPS_MAARI_INDEX (_ULCAST_(0x3f) << 0)
  656. /* EBase bit definitions */
  657. #define MIPS_EBASE_CPUNUM_SHIFT 0
  658. #define MIPS_EBASE_CPUNUM (_ULCAST_(0x3ff) << 0)
  659. #define MIPS_EBASE_WG_SHIFT 11
  660. #define MIPS_EBASE_WG (_ULCAST_(1) << 11)
  661. #define MIPS_EBASE_BASE_SHIFT 12
  662. #define MIPS_EBASE_BASE (~_ULCAST_((1 << MIPS_EBASE_BASE_SHIFT) - 1))
  663. /* CMGCRBase bit definitions */
  664. #define MIPS_CMGCRB_BASE 11
  665. #define MIPS_CMGCRF_BASE (~_ULCAST_((1 << MIPS_CMGCRB_BASE) - 1))
  666. /* LLAddr bit definitions */
  667. #define MIPS_LLADDR_LLB_SHIFT 0
  668. #define MIPS_LLADDR_LLB (_ULCAST_(1) << MIPS_LLADDR_LLB_SHIFT)
  669. /*
  670. * Bits in the MIPS32 Memory Segmentation registers.
  671. */
  672. #define MIPS_SEGCFG_PA_SHIFT 9
  673. #define MIPS_SEGCFG_PA (_ULCAST_(127) << MIPS_SEGCFG_PA_SHIFT)
  674. #define MIPS_SEGCFG_AM_SHIFT 4
  675. #define MIPS_SEGCFG_AM (_ULCAST_(7) << MIPS_SEGCFG_AM_SHIFT)
  676. #define MIPS_SEGCFG_EU_SHIFT 3
  677. #define MIPS_SEGCFG_EU (_ULCAST_(1) << MIPS_SEGCFG_EU_SHIFT)
  678. #define MIPS_SEGCFG_C_SHIFT 0
  679. #define MIPS_SEGCFG_C (_ULCAST_(7) << MIPS_SEGCFG_C_SHIFT)
  680. #define MIPS_SEGCFG_UUSK _ULCAST_(7)
  681. #define MIPS_SEGCFG_USK _ULCAST_(5)
  682. #define MIPS_SEGCFG_MUSUK _ULCAST_(4)
  683. #define MIPS_SEGCFG_MUSK _ULCAST_(3)
  684. #define MIPS_SEGCFG_MSK _ULCAST_(2)
  685. #define MIPS_SEGCFG_MK _ULCAST_(1)
  686. #define MIPS_SEGCFG_UK _ULCAST_(0)
  687. #define MIPS_PWFIELD_GDI_SHIFT 24
  688. #define MIPS_PWFIELD_GDI_MASK 0x3f000000
  689. #define MIPS_PWFIELD_UDI_SHIFT 18
  690. #define MIPS_PWFIELD_UDI_MASK 0x00fc0000
  691. #define MIPS_PWFIELD_MDI_SHIFT 12
  692. #define MIPS_PWFIELD_MDI_MASK 0x0003f000
  693. #define MIPS_PWFIELD_PTI_SHIFT 6
  694. #define MIPS_PWFIELD_PTI_MASK 0x00000fc0
  695. #define MIPS_PWFIELD_PTEI_SHIFT 0
  696. #define MIPS_PWFIELD_PTEI_MASK 0x0000003f
  697. #define MIPS_PWSIZE_PS_SHIFT 30
  698. #define MIPS_PWSIZE_PS_MASK 0x40000000
  699. #define MIPS_PWSIZE_GDW_SHIFT 24
  700. #define MIPS_PWSIZE_GDW_MASK 0x3f000000
  701. #define MIPS_PWSIZE_UDW_SHIFT 18
  702. #define MIPS_PWSIZE_UDW_MASK 0x00fc0000
  703. #define MIPS_PWSIZE_MDW_SHIFT 12
  704. #define MIPS_PWSIZE_MDW_MASK 0x0003f000
  705. #define MIPS_PWSIZE_PTW_SHIFT 6
  706. #define MIPS_PWSIZE_PTW_MASK 0x00000fc0
  707. #define MIPS_PWSIZE_PTEW_SHIFT 0
  708. #define MIPS_PWSIZE_PTEW_MASK 0x0000003f
  709. #define MIPS_PWCTL_PWEN_SHIFT 31
  710. #define MIPS_PWCTL_PWEN_MASK 0x80000000
  711. #define MIPS_PWCTL_XK_SHIFT 28
  712. #define MIPS_PWCTL_XK_MASK 0x10000000
  713. #define MIPS_PWCTL_XS_SHIFT 27
  714. #define MIPS_PWCTL_XS_MASK 0x08000000
  715. #define MIPS_PWCTL_XU_SHIFT 26
  716. #define MIPS_PWCTL_XU_MASK 0x04000000
  717. #define MIPS_PWCTL_DPH_SHIFT 7
  718. #define MIPS_PWCTL_DPH_MASK 0x00000080
  719. #define MIPS_PWCTL_HUGEPG_SHIFT 6
  720. #define MIPS_PWCTL_HUGEPG_MASK 0x00000060
  721. #define MIPS_PWCTL_PSN_SHIFT 0
  722. #define MIPS_PWCTL_PSN_MASK 0x0000003f
  723. /* GuestCtl0 fields */
  724. #define MIPS_GCTL0_GM_SHIFT 31
  725. #define MIPS_GCTL0_GM (_ULCAST_(1) << MIPS_GCTL0_GM_SHIFT)
  726. #define MIPS_GCTL0_RI_SHIFT 30
  727. #define MIPS_GCTL0_RI (_ULCAST_(1) << MIPS_GCTL0_RI_SHIFT)
  728. #define MIPS_GCTL0_MC_SHIFT 29
  729. #define MIPS_GCTL0_MC (_ULCAST_(1) << MIPS_GCTL0_MC_SHIFT)
  730. #define MIPS_GCTL0_CP0_SHIFT 28
  731. #define MIPS_GCTL0_CP0 (_ULCAST_(1) << MIPS_GCTL0_CP0_SHIFT)
  732. #define MIPS_GCTL0_AT_SHIFT 26
  733. #define MIPS_GCTL0_AT (_ULCAST_(0x3) << MIPS_GCTL0_AT_SHIFT)
  734. #define MIPS_GCTL0_GT_SHIFT 25
  735. #define MIPS_GCTL0_GT (_ULCAST_(1) << MIPS_GCTL0_GT_SHIFT)
  736. #define MIPS_GCTL0_CG_SHIFT 24
  737. #define MIPS_GCTL0_CG (_ULCAST_(1) << MIPS_GCTL0_CG_SHIFT)
  738. #define MIPS_GCTL0_CF_SHIFT 23
  739. #define MIPS_GCTL0_CF (_ULCAST_(1) << MIPS_GCTL0_CF_SHIFT)
  740. #define MIPS_GCTL0_G1_SHIFT 22
  741. #define MIPS_GCTL0_G1 (_ULCAST_(1) << MIPS_GCTL0_G1_SHIFT)
  742. #define MIPS_GCTL0_G0E_SHIFT 19
  743. #define MIPS_GCTL0_G0E (_ULCAST_(1) << MIPS_GCTL0_G0E_SHIFT)
  744. #define MIPS_GCTL0_PT_SHIFT 18
  745. #define MIPS_GCTL0_PT (_ULCAST_(1) << MIPS_GCTL0_PT_SHIFT)
  746. #define MIPS_GCTL0_RAD_SHIFT 9
  747. #define MIPS_GCTL0_RAD (_ULCAST_(1) << MIPS_GCTL0_RAD_SHIFT)
  748. #define MIPS_GCTL0_DRG_SHIFT 8
  749. #define MIPS_GCTL0_DRG (_ULCAST_(1) << MIPS_GCTL0_DRG_SHIFT)
  750. #define MIPS_GCTL0_G2_SHIFT 7
  751. #define MIPS_GCTL0_G2 (_ULCAST_(1) << MIPS_GCTL0_G2_SHIFT)
  752. #define MIPS_GCTL0_GEXC_SHIFT 2
  753. #define MIPS_GCTL0_GEXC (_ULCAST_(0x1f) << MIPS_GCTL0_GEXC_SHIFT)
  754. #define MIPS_GCTL0_SFC2_SHIFT 1
  755. #define MIPS_GCTL0_SFC2 (_ULCAST_(1) << MIPS_GCTL0_SFC2_SHIFT)
  756. #define MIPS_GCTL0_SFC1_SHIFT 0
  757. #define MIPS_GCTL0_SFC1 (_ULCAST_(1) << MIPS_GCTL0_SFC1_SHIFT)
  758. /* GuestCtl0.AT Guest address translation control */
  759. #define MIPS_GCTL0_AT_ROOT 1 /* Guest MMU under Root control */
  760. #define MIPS_GCTL0_AT_GUEST 3 /* Guest MMU under Guest control */
  761. /* GuestCtl0.GExcCode Hypervisor exception cause codes */
  762. #define MIPS_GCTL0_GEXC_GPSI 0 /* Guest Privileged Sensitive Instruction */
  763. #define MIPS_GCTL0_GEXC_GSFC 1 /* Guest Software Field Change */
  764. #define MIPS_GCTL0_GEXC_HC 2 /* Hypercall */
  765. #define MIPS_GCTL0_GEXC_GRR 3 /* Guest Reserved Instruction Redirect */
  766. #define MIPS_GCTL0_GEXC_GVA 8 /* Guest Virtual Address available */
  767. #define MIPS_GCTL0_GEXC_GHFC 9 /* Guest Hardware Field Change */
  768. #define MIPS_GCTL0_GEXC_GPA 10 /* Guest Physical Address available */
  769. /* GuestCtl0Ext fields */
  770. #define MIPS_GCTL0EXT_RPW_SHIFT 8
  771. #define MIPS_GCTL0EXT_RPW (_ULCAST_(0x3) << MIPS_GCTL0EXT_RPW_SHIFT)
  772. #define MIPS_GCTL0EXT_NCC_SHIFT 6
  773. #define MIPS_GCTL0EXT_NCC (_ULCAST_(0x3) << MIPS_GCTL0EXT_NCC_SHIFT)
  774. #define MIPS_GCTL0EXT_CGI_SHIFT 4
  775. #define MIPS_GCTL0EXT_CGI (_ULCAST_(1) << MIPS_GCTL0EXT_CGI_SHIFT)
  776. #define MIPS_GCTL0EXT_FCD_SHIFT 3
  777. #define MIPS_GCTL0EXT_FCD (_ULCAST_(1) << MIPS_GCTL0EXT_FCD_SHIFT)
  778. #define MIPS_GCTL0EXT_OG_SHIFT 2
  779. #define MIPS_GCTL0EXT_OG (_ULCAST_(1) << MIPS_GCTL0EXT_OG_SHIFT)
  780. #define MIPS_GCTL0EXT_BG_SHIFT 1
  781. #define MIPS_GCTL0EXT_BG (_ULCAST_(1) << MIPS_GCTL0EXT_BG_SHIFT)
  782. #define MIPS_GCTL0EXT_MG_SHIFT 0
  783. #define MIPS_GCTL0EXT_MG (_ULCAST_(1) << MIPS_GCTL0EXT_MG_SHIFT)
  784. /* GuestCtl0Ext.RPW Root page walk configuration */
  785. #define MIPS_GCTL0EXT_RPW_BOTH 0 /* Root PW for GPA->RPA and RVA->RPA */
  786. #define MIPS_GCTL0EXT_RPW_GPA 2 /* Root PW for GPA->RPA */
  787. #define MIPS_GCTL0EXT_RPW_RVA 3 /* Root PW for RVA->RPA */
  788. /* GuestCtl0Ext.NCC Nested cache coherency attributes */
  789. #define MIPS_GCTL0EXT_NCC_IND 0 /* Guest CCA independent of Root CCA */
  790. #define MIPS_GCTL0EXT_NCC_MOD 1 /* Guest CCA modified by Root CCA */
  791. /* GuestCtl1 fields */
  792. #define MIPS_GCTL1_ID_SHIFT 0
  793. #define MIPS_GCTL1_ID_WIDTH 8
  794. #define MIPS_GCTL1_ID (_ULCAST_(0xff) << MIPS_GCTL1_ID_SHIFT)
  795. #define MIPS_GCTL1_RID_SHIFT 16
  796. #define MIPS_GCTL1_RID_WIDTH 8
  797. #define MIPS_GCTL1_RID (_ULCAST_(0xff) << MIPS_GCTL1_RID_SHIFT)
  798. #define MIPS_GCTL1_EID_SHIFT 24
  799. #define MIPS_GCTL1_EID_WIDTH 8
  800. #define MIPS_GCTL1_EID (_ULCAST_(0xff) << MIPS_GCTL1_EID_SHIFT)
  801. /* GuestID reserved for root context */
  802. #define MIPS_GCTL1_ROOT_GUESTID 0
  803. /* CDMMBase register bit definitions */
  804. #define MIPS_CDMMBASE_SIZE_SHIFT 0
  805. #define MIPS_CDMMBASE_SIZE (_ULCAST_(511) << MIPS_CDMMBASE_SIZE_SHIFT)
  806. #define MIPS_CDMMBASE_CI (_ULCAST_(1) << 9)
  807. #define MIPS_CDMMBASE_EN (_ULCAST_(1) << 10)
  808. #define MIPS_CDMMBASE_ADDR_SHIFT 11
  809. #define MIPS_CDMMBASE_ADDR_START 15
  810. /* RDHWR register numbers */
  811. #define MIPS_HWR_CPUNUM 0 /* CPU number */
  812. #define MIPS_HWR_SYNCISTEP 1 /* SYNCI step size */
  813. #define MIPS_HWR_CC 2 /* Cycle counter */
  814. #define MIPS_HWR_CCRES 3 /* Cycle counter resolution */
  815. #define MIPS_HWR_ULR 29 /* UserLocal */
  816. #define MIPS_HWR_IMPL1 30 /* Implementation dependent */
  817. #define MIPS_HWR_IMPL2 31 /* Implementation dependent */
  818. /* Bits in HWREna register */
  819. #define MIPS_HWRENA_CPUNUM (_ULCAST_(1) << MIPS_HWR_CPUNUM)
  820. #define MIPS_HWRENA_SYNCISTEP (_ULCAST_(1) << MIPS_HWR_SYNCISTEP)
  821. #define MIPS_HWRENA_CC (_ULCAST_(1) << MIPS_HWR_CC)
  822. #define MIPS_HWRENA_CCRES (_ULCAST_(1) << MIPS_HWR_CCRES)
  823. #define MIPS_HWRENA_ULR (_ULCAST_(1) << MIPS_HWR_ULR)
  824. #define MIPS_HWRENA_IMPL1 (_ULCAST_(1) << MIPS_HWR_IMPL1)
  825. #define MIPS_HWRENA_IMPL2 (_ULCAST_(1) << MIPS_HWR_IMPL2)
  826. /*
  827. * Bitfields in the TX39 family CP0 Configuration Register 3
  828. */
  829. #define TX39_CONF_ICS_SHIFT 19
  830. #define TX39_CONF_ICS_MASK 0x00380000
  831. #define TX39_CONF_ICS_1KB 0x00000000
  832. #define TX39_CONF_ICS_2KB 0x00080000
  833. #define TX39_CONF_ICS_4KB 0x00100000
  834. #define TX39_CONF_ICS_8KB 0x00180000
  835. #define TX39_CONF_ICS_16KB 0x00200000
  836. #define TX39_CONF_DCS_SHIFT 16
  837. #define TX39_CONF_DCS_MASK 0x00070000
  838. #define TX39_CONF_DCS_1KB 0x00000000
  839. #define TX39_CONF_DCS_2KB 0x00010000
  840. #define TX39_CONF_DCS_4KB 0x00020000
  841. #define TX39_CONF_DCS_8KB 0x00030000
  842. #define TX39_CONF_DCS_16KB 0x00040000
  843. #define TX39_CONF_CWFON 0x00004000
  844. #define TX39_CONF_WBON 0x00002000
  845. #define TX39_CONF_RF_SHIFT 10
  846. #define TX39_CONF_RF_MASK 0x00000c00
  847. #define TX39_CONF_DOZE 0x00000200
  848. #define TX39_CONF_HALT 0x00000100
  849. #define TX39_CONF_LOCK 0x00000080
  850. #define TX39_CONF_ICE 0x00000020
  851. #define TX39_CONF_DCE 0x00000010
  852. #define TX39_CONF_IRSIZE_SHIFT 2
  853. #define TX39_CONF_IRSIZE_MASK 0x0000000c
  854. #define TX39_CONF_DRSIZE_SHIFT 0
  855. #define TX39_CONF_DRSIZE_MASK 0x00000003
  856. /*
  857. * Interesting Bits in the R10K CP0 Branch Diagnostic Register
  858. */
  859. /* Disable Branch Target Address Cache */
  860. #define R10K_DIAG_D_BTAC (_ULCAST_(1) << 27)
  861. /* Enable Branch Prediction Global History */
  862. #define R10K_DIAG_E_GHIST (_ULCAST_(1) << 26)
  863. /* Disable Branch Return Cache */
  864. #define R10K_DIAG_D_BRC (_ULCAST_(1) << 22)
  865. /* Flush ITLB */
  866. #define LOONGSON_DIAG_ITLB (_ULCAST_(1) << 2)
  867. /* Flush DTLB */
  868. #define LOONGSON_DIAG_DTLB (_ULCAST_(1) << 3)
  869. /* Flush VTLB */
  870. #define LOONGSON_DIAG_VTLB (_ULCAST_(1) << 12)
  871. /* Flush FTLB */
  872. #define LOONGSON_DIAG_FTLB (_ULCAST_(1) << 13)
  873. /* CvmCtl register field definitions */
  874. #define CVMCTL_IPPCI_SHIFT 7
  875. #define CVMCTL_IPPCI (_U64CAST_(0x7) << CVMCTL_IPPCI_SHIFT)
  876. #define CVMCTL_IPTI_SHIFT 4
  877. #define CVMCTL_IPTI (_U64CAST_(0x7) << CVMCTL_IPTI_SHIFT)
  878. /* CvmMemCtl2 register field definitions */
  879. #define CVMMEMCTL2_INHIBITTS (_U64CAST_(1) << 17)
  880. /* CvmVMConfig register field definitions */
  881. #define CVMVMCONF_DGHT (_U64CAST_(1) << 60)
  882. #define CVMVMCONF_MMUSIZEM1_S 12
  883. #define CVMVMCONF_MMUSIZEM1 (_U64CAST_(0xff) << CVMVMCONF_MMUSIZEM1_S)
  884. #define CVMVMCONF_RMMUSIZEM1_S 0
  885. #define CVMVMCONF_RMMUSIZEM1 (_U64CAST_(0xff) << CVMVMCONF_RMMUSIZEM1_S)
  886. /*
  887. * Coprocessor 1 (FPU) register names
  888. */
  889. #define CP1_REVISION $0
  890. #define CP1_UFR $1
  891. #define CP1_UNFR $4
  892. #define CP1_FCCR $25
  893. #define CP1_FEXR $26
  894. #define CP1_FENR $28
  895. #define CP1_STATUS $31
  896. /*
  897. * Bits in the MIPS32/64 coprocessor 1 (FPU) revision register.
  898. */
  899. #define MIPS_FPIR_S (_ULCAST_(1) << 16)
  900. #define MIPS_FPIR_D (_ULCAST_(1) << 17)
  901. #define MIPS_FPIR_PS (_ULCAST_(1) << 18)
  902. #define MIPS_FPIR_3D (_ULCAST_(1) << 19)
  903. #define MIPS_FPIR_W (_ULCAST_(1) << 20)
  904. #define MIPS_FPIR_L (_ULCAST_(1) << 21)
  905. #define MIPS_FPIR_F64 (_ULCAST_(1) << 22)
  906. #define MIPS_FPIR_HAS2008 (_ULCAST_(1) << 23)
  907. #define MIPS_FPIR_UFRP (_ULCAST_(1) << 28)
  908. #define MIPS_FPIR_FREP (_ULCAST_(1) << 29)
  909. /*
  910. * Bits in the MIPS32/64 coprocessor 1 (FPU) condition codes register.
  911. */
  912. #define MIPS_FCCR_CONDX_S 0
  913. #define MIPS_FCCR_CONDX (_ULCAST_(255) << MIPS_FCCR_CONDX_S)
  914. #define MIPS_FCCR_COND0_S 0
  915. #define MIPS_FCCR_COND0 (_ULCAST_(1) << MIPS_FCCR_COND0_S)
  916. #define MIPS_FCCR_COND1_S 1
  917. #define MIPS_FCCR_COND1 (_ULCAST_(1) << MIPS_FCCR_COND1_S)
  918. #define MIPS_FCCR_COND2_S 2
  919. #define MIPS_FCCR_COND2 (_ULCAST_(1) << MIPS_FCCR_COND2_S)
  920. #define MIPS_FCCR_COND3_S 3
  921. #define MIPS_FCCR_COND3 (_ULCAST_(1) << MIPS_FCCR_COND3_S)
  922. #define MIPS_FCCR_COND4_S 4
  923. #define MIPS_FCCR_COND4 (_ULCAST_(1) << MIPS_FCCR_COND4_S)
  924. #define MIPS_FCCR_COND5_S 5
  925. #define MIPS_FCCR_COND5 (_ULCAST_(1) << MIPS_FCCR_COND5_S)
  926. #define MIPS_FCCR_COND6_S 6
  927. #define MIPS_FCCR_COND6 (_ULCAST_(1) << MIPS_FCCR_COND6_S)
  928. #define MIPS_FCCR_COND7_S 7
  929. #define MIPS_FCCR_COND7 (_ULCAST_(1) << MIPS_FCCR_COND7_S)
  930. /*
  931. * Bits in the MIPS32/64 coprocessor 1 (FPU) enables register.
  932. */
  933. #define MIPS_FENR_FS_S 2
  934. #define MIPS_FENR_FS (_ULCAST_(1) << MIPS_FENR_FS_S)
  935. /*
  936. * FPU Status Register Values
  937. */
  938. #define FPU_CSR_COND_S 23 /* $fcc0 */
  939. #define FPU_CSR_COND (_ULCAST_(1) << FPU_CSR_COND_S)
  940. #define FPU_CSR_FS_S 24 /* flush denormalised results to 0 */
  941. #define FPU_CSR_FS (_ULCAST_(1) << FPU_CSR_FS_S)
  942. #define FPU_CSR_CONDX_S 25 /* $fcc[7:1] */
  943. #define FPU_CSR_CONDX (_ULCAST_(127) << FPU_CSR_CONDX_S)
  944. #define FPU_CSR_COND1_S 25 /* $fcc1 */
  945. #define FPU_CSR_COND1 (_ULCAST_(1) << FPU_CSR_COND1_S)
  946. #define FPU_CSR_COND2_S 26 /* $fcc2 */
  947. #define FPU_CSR_COND2 (_ULCAST_(1) << FPU_CSR_COND2_S)
  948. #define FPU_CSR_COND3_S 27 /* $fcc3 */
  949. #define FPU_CSR_COND3 (_ULCAST_(1) << FPU_CSR_COND3_S)
  950. #define FPU_CSR_COND4_S 28 /* $fcc4 */
  951. #define FPU_CSR_COND4 (_ULCAST_(1) << FPU_CSR_COND4_S)
  952. #define FPU_CSR_COND5_S 29 /* $fcc5 */
  953. #define FPU_CSR_COND5 (_ULCAST_(1) << FPU_CSR_COND5_S)
  954. #define FPU_CSR_COND6_S 30 /* $fcc6 */
  955. #define FPU_CSR_COND6 (_ULCAST_(1) << FPU_CSR_COND6_S)
  956. #define FPU_CSR_COND7_S 31 /* $fcc7 */
  957. #define FPU_CSR_COND7 (_ULCAST_(1) << FPU_CSR_COND7_S)
  958. /*
  959. * Bits 22:20 of the FPU Status Register will be read as 0,
  960. * and should be written as zero.
  961. * MAC2008 was removed in Release 5 so we still treat it as
  962. * reserved.
  963. */
  964. #define FPU_CSR_RSVD (_ULCAST_(7) << 20)
  965. #define FPU_CSR_MAC2008 (_ULCAST_(1) << 20)
  966. #define FPU_CSR_ABS2008 (_ULCAST_(1) << 19)
  967. #define FPU_CSR_NAN2008 (_ULCAST_(1) << 18)
  968. /*
  969. * X the exception cause indicator
  970. * E the exception enable
  971. * S the sticky/flag bit
  972. */
  973. #define FPU_CSR_ALL_X 0x0003f000
  974. #define FPU_CSR_UNI_X 0x00020000
  975. #define FPU_CSR_INV_X 0x00010000
  976. #define FPU_CSR_DIV_X 0x00008000
  977. #define FPU_CSR_OVF_X 0x00004000
  978. #define FPU_CSR_UDF_X 0x00002000
  979. #define FPU_CSR_INE_X 0x00001000
  980. #define FPU_CSR_ALL_E 0x00000f80
  981. #define FPU_CSR_INV_E 0x00000800
  982. #define FPU_CSR_DIV_E 0x00000400
  983. #define FPU_CSR_OVF_E 0x00000200
  984. #define FPU_CSR_UDF_E 0x00000100
  985. #define FPU_CSR_INE_E 0x00000080
  986. #define FPU_CSR_ALL_S 0x0000007c
  987. #define FPU_CSR_INV_S 0x00000040
  988. #define FPU_CSR_DIV_S 0x00000020
  989. #define FPU_CSR_OVF_S 0x00000010
  990. #define FPU_CSR_UDF_S 0x00000008
  991. #define FPU_CSR_INE_S 0x00000004
  992. /* Bits 0 and 1 of FPU Status Register specify the rounding mode */
  993. #define FPU_CSR_RM 0x00000003
  994. #define FPU_CSR_RN 0x0 /* nearest */
  995. #define FPU_CSR_RZ 0x1 /* towards zero */
  996. #define FPU_CSR_RU 0x2 /* towards +Infinity */
  997. #define FPU_CSR_RD 0x3 /* towards -Infinity */
  998. #ifndef __ASSEMBLY__
  999. /*
  1000. * Macros for handling the ISA mode bit for MIPS16 and microMIPS.
  1001. */
  1002. #if defined(CONFIG_SYS_SUPPORTS_MIPS16) || \
  1003. defined(CONFIG_SYS_SUPPORTS_MICROMIPS)
  1004. #define get_isa16_mode(x) ((x) & 0x1)
  1005. #define msk_isa16_mode(x) ((x) & ~0x1)
  1006. #define set_isa16_mode(x) do { (x) |= 0x1; } while(0)
  1007. #else
  1008. #define get_isa16_mode(x) 0
  1009. #define msk_isa16_mode(x) (x)
  1010. #define set_isa16_mode(x) do { } while(0)
  1011. #endif
  1012. /*
  1013. * microMIPS instructions can be 16-bit or 32-bit in length. This
  1014. * returns a 1 if the instruction is 16-bit and a 0 if 32-bit.
  1015. */
  1016. static inline int mm_insn_16bit(u16 insn)
  1017. {
  1018. u16 opcode = (insn >> 10) & 0x7;
  1019. return (opcode >= 1 && opcode <= 3) ? 1 : 0;
  1020. }
  1021. /*
  1022. * Helper macros for generating raw instruction encodings in inline asm.
  1023. */
  1024. #ifdef CONFIG_CPU_MICROMIPS
  1025. #define _ASM_INSN16_IF_MM(_enc) \
  1026. ".insn\n\t" \
  1027. ".hword (" #_enc ")\n\t"
  1028. #define _ASM_INSN32_IF_MM(_enc) \
  1029. ".insn\n\t" \
  1030. ".hword ((" #_enc ") >> 16)\n\t" \
  1031. ".hword ((" #_enc ") & 0xffff)\n\t"
  1032. #else
  1033. #define _ASM_INSN_IF_MIPS(_enc) \
  1034. ".insn\n\t" \
  1035. ".word (" #_enc ")\n\t"
  1036. #endif
  1037. #ifndef _ASM_INSN16_IF_MM
  1038. #define _ASM_INSN16_IF_MM(_enc)
  1039. #endif
  1040. #ifndef _ASM_INSN32_IF_MM
  1041. #define _ASM_INSN32_IF_MM(_enc)
  1042. #endif
  1043. #ifndef _ASM_INSN_IF_MIPS
  1044. #define _ASM_INSN_IF_MIPS(_enc)
  1045. #endif
  1046. /*
  1047. * parse_r var, r - Helper assembler macro for parsing register names.
  1048. *
  1049. * This converts the register name in $n form provided in \r to the
  1050. * corresponding register number, which is assigned to the variable \var. It is
  1051. * needed to allow explicit encoding of instructions in inline assembly where
  1052. * registers are chosen by the compiler in $n form, allowing us to avoid using
  1053. * fixed register numbers.
  1054. *
  1055. * It also allows newer instructions (not implemented by the assembler) to be
  1056. * transparently implemented using assembler macros, instead of needing separate
  1057. * cases depending on toolchain support.
  1058. *
  1059. * Simple usage example:
  1060. * __asm__ __volatile__("parse_r __rt, %0\n\t"
  1061. * ".insn\n\t"
  1062. * "# di %0\n\t"
  1063. * ".word (0x41606000 | (__rt << 16))"
  1064. * : "=r" (status);
  1065. */
  1066. /* Match an individual register number and assign to \var */
  1067. #define _IFC_REG(n) \
  1068. ".ifc \\r, $" #n "\n\t" \
  1069. "\\var = " #n "\n\t" \
  1070. ".endif\n\t"
  1071. __asm__(".macro parse_r var r\n\t"
  1072. "\\var = -1\n\t"
  1073. _IFC_REG(0) _IFC_REG(1) _IFC_REG(2) _IFC_REG(3)
  1074. _IFC_REG(4) _IFC_REG(5) _IFC_REG(6) _IFC_REG(7)
  1075. _IFC_REG(8) _IFC_REG(9) _IFC_REG(10) _IFC_REG(11)
  1076. _IFC_REG(12) _IFC_REG(13) _IFC_REG(14) _IFC_REG(15)
  1077. _IFC_REG(16) _IFC_REG(17) _IFC_REG(18) _IFC_REG(19)
  1078. _IFC_REG(20) _IFC_REG(21) _IFC_REG(22) _IFC_REG(23)
  1079. _IFC_REG(24) _IFC_REG(25) _IFC_REG(26) _IFC_REG(27)
  1080. _IFC_REG(28) _IFC_REG(29) _IFC_REG(30) _IFC_REG(31)
  1081. ".iflt \\var\n\t"
  1082. ".error \"Unable to parse register name \\r\"\n\t"
  1083. ".endif\n\t"
  1084. ".endm");
  1085. #undef _IFC_REG
  1086. /*
  1087. * C macros for generating assembler macros for common instruction formats.
  1088. *
  1089. * The names of the operands can be chosen by the caller, and the encoding of
  1090. * register operand \<Rn> is assigned to __<Rn> where it can be accessed from
  1091. * the ENC encodings.
  1092. */
  1093. /* Instructions with no operands */
  1094. #define _ASM_MACRO_0(OP, ENC) \
  1095. __asm__(".macro " #OP "\n\t" \
  1096. ENC \
  1097. ".endm")
  1098. /* Instructions with 1 register operand & 1 immediate operand */
  1099. #define _ASM_MACRO_1R1I(OP, R1, I2, ENC) \
  1100. __asm__(".macro " #OP " " #R1 ", " #I2 "\n\t" \
  1101. "parse_r __" #R1 ", \\" #R1 "\n\t" \
  1102. ENC \
  1103. ".endm")
  1104. /* Instructions with 2 register operands */
  1105. #define _ASM_MACRO_2R(OP, R1, R2, ENC) \
  1106. __asm__(".macro " #OP " " #R1 ", " #R2 "\n\t" \
  1107. "parse_r __" #R1 ", \\" #R1 "\n\t" \
  1108. "parse_r __" #R2 ", \\" #R2 "\n\t" \
  1109. ENC \
  1110. ".endm")
  1111. /* Instructions with 3 register operands */
  1112. #define _ASM_MACRO_3R(OP, R1, R2, R3, ENC) \
  1113. __asm__(".macro " #OP " " #R1 ", " #R2 ", " #R3 "\n\t" \
  1114. "parse_r __" #R1 ", \\" #R1 "\n\t" \
  1115. "parse_r __" #R2 ", \\" #R2 "\n\t" \
  1116. "parse_r __" #R3 ", \\" #R3 "\n\t" \
  1117. ENC \
  1118. ".endm")
  1119. /* Instructions with 2 register operands and 1 optional select operand */
  1120. #define _ASM_MACRO_2R_1S(OP, R1, R2, SEL3, ENC) \
  1121. __asm__(".macro " #OP " " #R1 ", " #R2 ", " #SEL3 " = 0\n\t" \
  1122. "parse_r __" #R1 ", \\" #R1 "\n\t" \
  1123. "parse_r __" #R2 ", \\" #R2 "\n\t" \
  1124. ENC \
  1125. ".endm")
  1126. /*
  1127. * TLB Invalidate Flush
  1128. */
  1129. static inline void tlbinvf(void)
  1130. {
  1131. __asm__ __volatile__(
  1132. ".set push\n\t"
  1133. ".set noreorder\n\t"
  1134. "# tlbinvf\n\t"
  1135. _ASM_INSN_IF_MIPS(0x42000004)
  1136. _ASM_INSN32_IF_MM(0x0000537c)
  1137. ".set pop");
  1138. }
  1139. /*
  1140. * Functions to access the R10000 performance counters. These are basically
  1141. * mfc0 and mtc0 instructions from and to coprocessor register with a 5-bit
  1142. * performance counter number encoded into bits 1 ... 5 of the instruction.
  1143. * Only performance counters 0 to 1 actually exist, so for a non-R10000 aware
  1144. * disassembler these will look like an access to sel 0 or 1.
  1145. */
  1146. #define read_r10k_perf_cntr(counter) \
  1147. ({ \
  1148. unsigned int __res; \
  1149. __asm__ __volatile__( \
  1150. "mfpc\t%0, %1" \
  1151. : "=r" (__res) \
  1152. : "i" (counter)); \
  1153. \
  1154. __res; \
  1155. })
  1156. #define write_r10k_perf_cntr(counter,val) \
  1157. do { \
  1158. __asm__ __volatile__( \
  1159. "mtpc\t%0, %1" \
  1160. : \
  1161. : "r" (val), "i" (counter)); \
  1162. } while (0)
  1163. #define read_r10k_perf_event(counter) \
  1164. ({ \
  1165. unsigned int __res; \
  1166. __asm__ __volatile__( \
  1167. "mfps\t%0, %1" \
  1168. : "=r" (__res) \
  1169. : "i" (counter)); \
  1170. \
  1171. __res; \
  1172. })
  1173. #define write_r10k_perf_cntl(counter,val) \
  1174. do { \
  1175. __asm__ __volatile__( \
  1176. "mtps\t%0, %1" \
  1177. : \
  1178. : "r" (val), "i" (counter)); \
  1179. } while (0)
  1180. /*
  1181. * Macros to access the system control coprocessor
  1182. */
  1183. #define ___read_32bit_c0_register(source, sel, vol) \
  1184. ({ unsigned int __res; \
  1185. if (sel == 0) \
  1186. __asm__ vol( \
  1187. "mfc0\t%0, " #source "\n\t" \
  1188. : "=r" (__res)); \
  1189. else \
  1190. __asm__ vol( \
  1191. ".set\tpush\n\t" \
  1192. ".set\tmips32\n\t" \
  1193. "mfc0\t%0, " #source ", " #sel "\n\t" \
  1194. ".set\tpop\n\t" \
  1195. : "=r" (__res)); \
  1196. __res; \
  1197. })
  1198. #define ___read_64bit_c0_register(source, sel, vol) \
  1199. ({ unsigned long long __res; \
  1200. if (sizeof(unsigned long) == 4) \
  1201. __res = __read_64bit_c0_split(source, sel, vol); \
  1202. else if (sel == 0) \
  1203. __asm__ vol( \
  1204. ".set\tpush\n\t" \
  1205. ".set\tmips3\n\t" \
  1206. "dmfc0\t%0, " #source "\n\t" \
  1207. ".set\tpop" \
  1208. : "=r" (__res)); \
  1209. else \
  1210. __asm__ vol( \
  1211. ".set\tpush\n\t" \
  1212. ".set\tmips64\n\t" \
  1213. "dmfc0\t%0, " #source ", " #sel "\n\t" \
  1214. ".set\tpop" \
  1215. : "=r" (__res)); \
  1216. __res; \
  1217. })
  1218. #define __read_32bit_c0_register(source, sel) \
  1219. ___read_32bit_c0_register(source, sel, __volatile__)
  1220. #define __read_const_32bit_c0_register(source, sel) \
  1221. ___read_32bit_c0_register(source, sel,)
  1222. #define __read_64bit_c0_register(source, sel) \
  1223. ___read_64bit_c0_register(source, sel, __volatile__)
  1224. #define __read_const_64bit_c0_register(source, sel) \
  1225. ___read_64bit_c0_register(source, sel,)
  1226. #define __write_32bit_c0_register(register, sel, value) \
  1227. do { \
  1228. if (sel == 0) \
  1229. __asm__ __volatile__( \
  1230. "mtc0\t%z0, " #register "\n\t" \
  1231. : : "Jr" ((unsigned int)(value))); \
  1232. else \
  1233. __asm__ __volatile__( \
  1234. ".set\tpush\n\t" \
  1235. ".set\tmips32\n\t" \
  1236. "mtc0\t%z0, " #register ", " #sel "\n\t" \
  1237. ".set\tpop" \
  1238. : : "Jr" ((unsigned int)(value))); \
  1239. } while (0)
  1240. #define __write_64bit_c0_register(register, sel, value) \
  1241. do { \
  1242. if (sizeof(unsigned long) == 4) \
  1243. __write_64bit_c0_split(register, sel, value); \
  1244. else if (sel == 0) \
  1245. __asm__ __volatile__( \
  1246. ".set\tpush\n\t" \
  1247. ".set\tmips3\n\t" \
  1248. "dmtc0\t%z0, " #register "\n\t" \
  1249. ".set\tpop" \
  1250. : : "Jr" (value)); \
  1251. else \
  1252. __asm__ __volatile__( \
  1253. ".set\tpush\n\t" \
  1254. ".set\tmips64\n\t" \
  1255. "dmtc0\t%z0, " #register ", " #sel "\n\t" \
  1256. ".set\tpop" \
  1257. : : "Jr" (value)); \
  1258. } while (0)
  1259. #define __read_ulong_c0_register(reg, sel) \
  1260. ((sizeof(unsigned long) == 4) ? \
  1261. (unsigned long) __read_32bit_c0_register(reg, sel) : \
  1262. (unsigned long) __read_64bit_c0_register(reg, sel))
  1263. #define __read_const_ulong_c0_register(reg, sel) \
  1264. ((sizeof(unsigned long) == 4) ? \
  1265. (unsigned long) __read_const_32bit_c0_register(reg, sel) : \
  1266. (unsigned long) __read_const_64bit_c0_register(reg, sel))
  1267. #define __write_ulong_c0_register(reg, sel, val) \
  1268. do { \
  1269. if (sizeof(unsigned long) == 4) \
  1270. __write_32bit_c0_register(reg, sel, val); \
  1271. else \
  1272. __write_64bit_c0_register(reg, sel, val); \
  1273. } while (0)
  1274. /*
  1275. * On RM7000/RM9000 these are uses to access cop0 set 1 registers
  1276. */
  1277. #define __read_32bit_c0_ctrl_register(source) \
  1278. ({ unsigned int __res; \
  1279. __asm__ __volatile__( \
  1280. "cfc0\t%0, " #source "\n\t" \
  1281. : "=r" (__res)); \
  1282. __res; \
  1283. })
  1284. #define __write_32bit_c0_ctrl_register(register, value) \
  1285. do { \
  1286. __asm__ __volatile__( \
  1287. "ctc0\t%z0, " #register "\n\t" \
  1288. : : "Jr" ((unsigned int)(value))); \
  1289. } while (0)
  1290. /*
  1291. * These versions are only needed for systems with more than 38 bits of
  1292. * physical address space running the 32-bit kernel. That's none atm :-)
  1293. */
  1294. #define __read_64bit_c0_split(source, sel, vol) \
  1295. ({ \
  1296. unsigned long long __val; \
  1297. \
  1298. if (sel == 0) \
  1299. __asm__ vol( \
  1300. ".set\tpush\n\t" \
  1301. ".set\tmips64\n\t" \
  1302. "dmfc0\t%L0, " #source "\n\t" \
  1303. "dsra\t%M0, %L0, 32\n\t" \
  1304. "sll\t%L0, %L0, 0\n\t" \
  1305. ".set\tpop" \
  1306. : "=r" (__val)); \
  1307. else \
  1308. __asm__ vol( \
  1309. ".set\tpush\n\t" \
  1310. ".set\tmips64\n\t" \
  1311. "dmfc0\t%L0, " #source ", " #sel "\n\t" \
  1312. "dsra\t%M0, %L0, 32\n\t" \
  1313. "sll\t%L0, %L0, 0\n\t" \
  1314. ".set\tpop" \
  1315. : "=r" (__val)); \
  1316. \
  1317. __val; \
  1318. })
  1319. #define __write_64bit_c0_split(source, sel, val) \
  1320. do { \
  1321. unsigned long long __tmp = (val); \
  1322. if (MIPS_ISA_REV >= 2) \
  1323. __asm__ __volatile__( \
  1324. ".set\tpush\n\t" \
  1325. ".set\t" MIPS_ISA_LEVEL "\n\t" \
  1326. "dins\t%L0, %M0, 32, 32\n\t" \
  1327. "dmtc0\t%L0, " #source ", " #sel "\n\t" \
  1328. ".set\tpop" \
  1329. : "+r" (__tmp)); \
  1330. else if (sel == 0) \
  1331. __asm__ __volatile__( \
  1332. ".set\tpush\n\t" \
  1333. ".set\tmips64\n\t" \
  1334. "dsll\t%L0, %L0, 32\n\t" \
  1335. "dsrl\t%L0, %L0, 32\n\t" \
  1336. "dsll\t%M0, %M0, 32\n\t" \
  1337. "or\t%L0, %L0, %M0\n\t" \
  1338. "dmtc0\t%L0, " #source "\n\t" \
  1339. ".set\tpop" \
  1340. : "+r" (__tmp)); \
  1341. else \
  1342. __asm__ __volatile__( \
  1343. ".set\tpush\n\t" \
  1344. ".set\tmips64\n\t" \
  1345. "dsll\t%L0, %L0, 32\n\t" \
  1346. "dsrl\t%L0, %L0, 32\n\t" \
  1347. "dsll\t%M0, %M0, 32\n\t" \
  1348. "or\t%L0, %L0, %M0\n\t" \
  1349. "dmtc0\t%L0, " #source ", " #sel "\n\t" \
  1350. ".set\tpop" \
  1351. : "+r" (__tmp)); \
  1352. } while (0)
  1353. #ifndef TOOLCHAIN_SUPPORTS_XPA
  1354. _ASM_MACRO_2R_1S(mfhc0, rt, rs, sel,
  1355. _ASM_INSN_IF_MIPS(0x40400000 | __rt << 16 | __rs << 11 | \\sel)
  1356. _ASM_INSN32_IF_MM(0x000000f4 | __rt << 21 | __rs << 16 | \\sel << 11));
  1357. _ASM_MACRO_2R_1S(mthc0, rt, rd, sel,
  1358. _ASM_INSN_IF_MIPS(0x40c00000 | __rt << 16 | __rd << 11 | \\sel)
  1359. _ASM_INSN32_IF_MM(0x000002f4 | __rt << 21 | __rd << 16 | \\sel << 11));
  1360. #define _ASM_SET_XPA ""
  1361. #else /* !TOOLCHAIN_SUPPORTS_XPA */
  1362. #define _ASM_SET_XPA ".set\txpa\n\t"
  1363. #endif
  1364. #define __readx_32bit_c0_register(source, sel) \
  1365. ({ \
  1366. unsigned int __res; \
  1367. \
  1368. __asm__ __volatile__( \
  1369. " .set push \n" \
  1370. " .set mips32r2 \n" \
  1371. _ASM_SET_XPA \
  1372. " mfhc0 %0, " #source ", %1 \n" \
  1373. " .set pop \n" \
  1374. : "=r" (__res) \
  1375. : "i" (sel)); \
  1376. __res; \
  1377. })
  1378. #define __writex_32bit_c0_register(register, sel, value) \
  1379. do { \
  1380. __asm__ __volatile__( \
  1381. " .set push \n" \
  1382. " .set mips32r2 \n" \
  1383. _ASM_SET_XPA \
  1384. " mthc0 %z0, " #register ", %1 \n" \
  1385. " .set pop \n" \
  1386. : \
  1387. : "Jr" (value), "i" (sel)); \
  1388. } while (0)
  1389. #define read_c0_index() __read_32bit_c0_register($0, 0)
  1390. #define write_c0_index(val) __write_32bit_c0_register($0, 0, val)
  1391. #define read_c0_random() __read_32bit_c0_register($1, 0)
  1392. #define write_c0_random(val) __write_32bit_c0_register($1, 0, val)
  1393. #define read_c0_entrylo0() __read_ulong_c0_register($2, 0)
  1394. #define write_c0_entrylo0(val) __write_ulong_c0_register($2, 0, val)
  1395. #define readx_c0_entrylo0() __readx_32bit_c0_register($2, 0)
  1396. #define writex_c0_entrylo0(val) __writex_32bit_c0_register($2, 0, val)
  1397. #define read_c0_entrylo1() __read_ulong_c0_register($3, 0)
  1398. #define write_c0_entrylo1(val) __write_ulong_c0_register($3, 0, val)
  1399. #define readx_c0_entrylo1() __readx_32bit_c0_register($3, 0)
  1400. #define writex_c0_entrylo1(val) __writex_32bit_c0_register($3, 0, val)
  1401. #define read_c0_conf() __read_32bit_c0_register($3, 0)
  1402. #define write_c0_conf(val) __write_32bit_c0_register($3, 0, val)
  1403. #define read_c0_globalnumber() __read_32bit_c0_register($3, 1)
  1404. #define read_c0_context() __read_ulong_c0_register($4, 0)
  1405. #define write_c0_context(val) __write_ulong_c0_register($4, 0, val)
  1406. #define read_c0_contextconfig() __read_32bit_c0_register($4, 1)
  1407. #define write_c0_contextconfig(val) __write_32bit_c0_register($4, 1, val)
  1408. #define read_c0_userlocal() __read_ulong_c0_register($4, 2)
  1409. #define write_c0_userlocal(val) __write_ulong_c0_register($4, 2, val)
  1410. #define read_c0_xcontextconfig() __read_ulong_c0_register($4, 3)
  1411. #define write_c0_xcontextconfig(val) __write_ulong_c0_register($4, 3, val)
  1412. #define read_c0_memorymapid() __read_32bit_c0_register($4, 5)
  1413. #define write_c0_memorymapid(val) __write_32bit_c0_register($4, 5, val)
  1414. #define read_c0_pagemask() __read_32bit_c0_register($5, 0)
  1415. #define write_c0_pagemask(val) __write_32bit_c0_register($5, 0, val)
  1416. #define read_c0_pagegrain() __read_32bit_c0_register($5, 1)
  1417. #define write_c0_pagegrain(val) __write_32bit_c0_register($5, 1, val)
  1418. #define read_c0_wired() __read_32bit_c0_register($6, 0)
  1419. #define write_c0_wired(val) __write_32bit_c0_register($6, 0, val)
  1420. #define read_c0_info() __read_32bit_c0_register($7, 0)
  1421. #define read_c0_cache() __read_32bit_c0_register($7, 0) /* TX39xx */
  1422. #define write_c0_cache(val) __write_32bit_c0_register($7, 0, val)
  1423. #define read_c0_badvaddr() __read_ulong_c0_register($8, 0)
  1424. #define write_c0_badvaddr(val) __write_ulong_c0_register($8, 0, val)
  1425. #define read_c0_badinstr() __read_32bit_c0_register($8, 1)
  1426. #define read_c0_badinstrp() __read_32bit_c0_register($8, 2)
  1427. #define read_c0_count() __read_32bit_c0_register($9, 0)
  1428. #define write_c0_count(val) __write_32bit_c0_register($9, 0, val)
  1429. #define read_c0_count2() __read_32bit_c0_register($9, 6) /* pnx8550 */
  1430. #define write_c0_count2(val) __write_32bit_c0_register($9, 6, val)
  1431. #define read_c0_count3() __read_32bit_c0_register($9, 7) /* pnx8550 */
  1432. #define write_c0_count3(val) __write_32bit_c0_register($9, 7, val)
  1433. #define read_c0_entryhi() __read_ulong_c0_register($10, 0)
  1434. #define write_c0_entryhi(val) __write_ulong_c0_register($10, 0, val)
  1435. #define read_c0_guestctl1() __read_32bit_c0_register($10, 4)
  1436. #define write_c0_guestctl1(val) __write_32bit_c0_register($10, 4, val)
  1437. #define read_c0_guestctl2() __read_32bit_c0_register($10, 5)
  1438. #define write_c0_guestctl2(val) __write_32bit_c0_register($10, 5, val)
  1439. #define read_c0_guestctl3() __read_32bit_c0_register($10, 6)
  1440. #define write_c0_guestctl3(val) __write_32bit_c0_register($10, 6, val)
  1441. #define read_c0_compare() __read_32bit_c0_register($11, 0)
  1442. #define write_c0_compare(val) __write_32bit_c0_register($11, 0, val)
  1443. #define read_c0_guestctl0ext() __read_32bit_c0_register($11, 4)
  1444. #define write_c0_guestctl0ext(val) __write_32bit_c0_register($11, 4, val)
  1445. #define read_c0_compare2() __read_32bit_c0_register($11, 6) /* pnx8550 */
  1446. #define write_c0_compare2(val) __write_32bit_c0_register($11, 6, val)
  1447. #define read_c0_compare3() __read_32bit_c0_register($11, 7) /* pnx8550 */
  1448. #define write_c0_compare3(val) __write_32bit_c0_register($11, 7, val)
  1449. #define read_c0_status() __read_32bit_c0_register($12, 0)
  1450. #define write_c0_status(val) __write_32bit_c0_register($12, 0, val)
  1451. #define read_c0_guestctl0() __read_32bit_c0_register($12, 6)
  1452. #define write_c0_guestctl0(val) __write_32bit_c0_register($12, 6, val)
  1453. #define read_c0_gtoffset() __read_32bit_c0_register($12, 7)
  1454. #define write_c0_gtoffset(val) __write_32bit_c0_register($12, 7, val)
  1455. #define read_c0_cause() __read_32bit_c0_register($13, 0)
  1456. #define write_c0_cause(val) __write_32bit_c0_register($13, 0, val)
  1457. #define read_c0_epc() __read_ulong_c0_register($14, 0)
  1458. #define write_c0_epc(val) __write_ulong_c0_register($14, 0, val)
  1459. #define read_c0_prid() __read_const_32bit_c0_register($15, 0)
  1460. #define read_c0_cmgcrbase() __read_ulong_c0_register($15, 3)
  1461. #define read_c0_config() __read_32bit_c0_register($16, 0)
  1462. #define read_c0_config1() __read_32bit_c0_register($16, 1)
  1463. #define read_c0_config2() __read_32bit_c0_register($16, 2)
  1464. #define read_c0_config3() __read_32bit_c0_register($16, 3)
  1465. #define read_c0_config4() __read_32bit_c0_register($16, 4)
  1466. #define read_c0_config5() __read_32bit_c0_register($16, 5)
  1467. #define read_c0_config6() __read_32bit_c0_register($16, 6)
  1468. #define read_c0_config7() __read_32bit_c0_register($16, 7)
  1469. #define write_c0_config(val) __write_32bit_c0_register($16, 0, val)
  1470. #define write_c0_config1(val) __write_32bit_c0_register($16, 1, val)
  1471. #define write_c0_config2(val) __write_32bit_c0_register($16, 2, val)
  1472. #define write_c0_config3(val) __write_32bit_c0_register($16, 3, val)
  1473. #define write_c0_config4(val) __write_32bit_c0_register($16, 4, val)
  1474. #define write_c0_config5(val) __write_32bit_c0_register($16, 5, val)
  1475. #define write_c0_config6(val) __write_32bit_c0_register($16, 6, val)
  1476. #define write_c0_config7(val) __write_32bit_c0_register($16, 7, val)
  1477. #define read_c0_lladdr() __read_ulong_c0_register($17, 0)
  1478. #define write_c0_lladdr(val) __write_ulong_c0_register($17, 0, val)
  1479. #define read_c0_maar() __read_ulong_c0_register($17, 1)
  1480. #define write_c0_maar(val) __write_ulong_c0_register($17, 1, val)
  1481. #define read_c0_maari() __read_32bit_c0_register($17, 2)
  1482. #define write_c0_maari(val) __write_32bit_c0_register($17, 2, val)
  1483. /*
  1484. * The WatchLo register. There may be up to 8 of them.
  1485. */
  1486. #define read_c0_watchlo0() __read_ulong_c0_register($18, 0)
  1487. #define read_c0_watchlo1() __read_ulong_c0_register($18, 1)
  1488. #define read_c0_watchlo2() __read_ulong_c0_register($18, 2)
  1489. #define read_c0_watchlo3() __read_ulong_c0_register($18, 3)
  1490. #define read_c0_watchlo4() __read_ulong_c0_register($18, 4)
  1491. #define read_c0_watchlo5() __read_ulong_c0_register($18, 5)
  1492. #define read_c0_watchlo6() __read_ulong_c0_register($18, 6)
  1493. #define read_c0_watchlo7() __read_ulong_c0_register($18, 7)
  1494. #define write_c0_watchlo0(val) __write_ulong_c0_register($18, 0, val)
  1495. #define write_c0_watchlo1(val) __write_ulong_c0_register($18, 1, val)
  1496. #define write_c0_watchlo2(val) __write_ulong_c0_register($18, 2, val)
  1497. #define write_c0_watchlo3(val) __write_ulong_c0_register($18, 3, val)
  1498. #define write_c0_watchlo4(val) __write_ulong_c0_register($18, 4, val)
  1499. #define write_c0_watchlo5(val) __write_ulong_c0_register($18, 5, val)
  1500. #define write_c0_watchlo6(val) __write_ulong_c0_register($18, 6, val)
  1501. #define write_c0_watchlo7(val) __write_ulong_c0_register($18, 7, val)
  1502. /*
  1503. * The WatchHi register. There may be up to 8 of them.
  1504. */
  1505. #define read_c0_watchhi0() __read_32bit_c0_register($19, 0)
  1506. #define read_c0_watchhi1() __read_32bit_c0_register($19, 1)
  1507. #define read_c0_watchhi2() __read_32bit_c0_register($19, 2)
  1508. #define read_c0_watchhi3() __read_32bit_c0_register($19, 3)
  1509. #define read_c0_watchhi4() __read_32bit_c0_register($19, 4)
  1510. #define read_c0_watchhi5() __read_32bit_c0_register($19, 5)
  1511. #define read_c0_watchhi6() __read_32bit_c0_register($19, 6)
  1512. #define read_c0_watchhi7() __read_32bit_c0_register($19, 7)
  1513. #define write_c0_watchhi0(val) __write_32bit_c0_register($19, 0, val)
  1514. #define write_c0_watchhi1(val) __write_32bit_c0_register($19, 1, val)
  1515. #define write_c0_watchhi2(val) __write_32bit_c0_register($19, 2, val)
  1516. #define write_c0_watchhi3(val) __write_32bit_c0_register($19, 3, val)
  1517. #define write_c0_watchhi4(val) __write_32bit_c0_register($19, 4, val)
  1518. #define write_c0_watchhi5(val) __write_32bit_c0_register($19, 5, val)
  1519. #define write_c0_watchhi6(val) __write_32bit_c0_register($19, 6, val)
  1520. #define write_c0_watchhi7(val) __write_32bit_c0_register($19, 7, val)
  1521. #define read_c0_xcontext() __read_ulong_c0_register($20, 0)
  1522. #define write_c0_xcontext(val) __write_ulong_c0_register($20, 0, val)
  1523. #define read_c0_intcontrol() __read_32bit_c0_ctrl_register($20)
  1524. #define write_c0_intcontrol(val) __write_32bit_c0_ctrl_register($20, val)
  1525. #define read_c0_framemask() __read_32bit_c0_register($21, 0)
  1526. #define write_c0_framemask(val) __write_32bit_c0_register($21, 0, val)
  1527. #define read_c0_diag() __read_32bit_c0_register($22, 0)
  1528. #define write_c0_diag(val) __write_32bit_c0_register($22, 0, val)
  1529. /* R10K CP0 Branch Diagnostic register is 64bits wide */
  1530. #define read_c0_r10k_diag() __read_64bit_c0_register($22, 0)
  1531. #define write_c0_r10k_diag(val) __write_64bit_c0_register($22, 0, val)
  1532. #define read_c0_diag1() __read_32bit_c0_register($22, 1)
  1533. #define write_c0_diag1(val) __write_32bit_c0_register($22, 1, val)
  1534. #define read_c0_diag2() __read_32bit_c0_register($22, 2)
  1535. #define write_c0_diag2(val) __write_32bit_c0_register($22, 2, val)
  1536. #define read_c0_diag3() __read_32bit_c0_register($22, 3)
  1537. #define write_c0_diag3(val) __write_32bit_c0_register($22, 3, val)
  1538. #define read_c0_diag4() __read_32bit_c0_register($22, 4)
  1539. #define write_c0_diag4(val) __write_32bit_c0_register($22, 4, val)
  1540. #define read_c0_diag5() __read_32bit_c0_register($22, 5)
  1541. #define write_c0_diag5(val) __write_32bit_c0_register($22, 5, val)
  1542. #define read_c0_debug() __read_32bit_c0_register($23, 0)
  1543. #define write_c0_debug(val) __write_32bit_c0_register($23, 0, val)
  1544. #define read_c0_depc() __read_ulong_c0_register($24, 0)
  1545. #define write_c0_depc(val) __write_ulong_c0_register($24, 0, val)
  1546. /*
  1547. * MIPS32 / MIPS64 performance counters
  1548. */
  1549. #define read_c0_perfctrl0() __read_32bit_c0_register($25, 0)
  1550. #define write_c0_perfctrl0(val) __write_32bit_c0_register($25, 0, val)
  1551. #define read_c0_perfcntr0() __read_32bit_c0_register($25, 1)
  1552. #define write_c0_perfcntr0(val) __write_32bit_c0_register($25, 1, val)
  1553. #define read_c0_perfcntr0_64() __read_64bit_c0_register($25, 1)
  1554. #define write_c0_perfcntr0_64(val) __write_64bit_c0_register($25, 1, val)
  1555. #define read_c0_perfctrl1() __read_32bit_c0_register($25, 2)
  1556. #define write_c0_perfctrl1(val) __write_32bit_c0_register($25, 2, val)
  1557. #define read_c0_perfcntr1() __read_32bit_c0_register($25, 3)
  1558. #define write_c0_perfcntr1(val) __write_32bit_c0_register($25, 3, val)
  1559. #define read_c0_perfcntr1_64() __read_64bit_c0_register($25, 3)
  1560. #define write_c0_perfcntr1_64(val) __write_64bit_c0_register($25, 3, val)
  1561. #define read_c0_perfctrl2() __read_32bit_c0_register($25, 4)
  1562. #define write_c0_perfctrl2(val) __write_32bit_c0_register($25, 4, val)
  1563. #define read_c0_perfcntr2() __read_32bit_c0_register($25, 5)
  1564. #define write_c0_perfcntr2(val) __write_32bit_c0_register($25, 5, val)
  1565. #define read_c0_perfcntr2_64() __read_64bit_c0_register($25, 5)
  1566. #define write_c0_perfcntr2_64(val) __write_64bit_c0_register($25, 5, val)
  1567. #define read_c0_perfctrl3() __read_32bit_c0_register($25, 6)
  1568. #define write_c0_perfctrl3(val) __write_32bit_c0_register($25, 6, val)
  1569. #define read_c0_perfcntr3() __read_32bit_c0_register($25, 7)
  1570. #define write_c0_perfcntr3(val) __write_32bit_c0_register($25, 7, val)
  1571. #define read_c0_perfcntr3_64() __read_64bit_c0_register($25, 7)
  1572. #define write_c0_perfcntr3_64(val) __write_64bit_c0_register($25, 7, val)
  1573. #define read_c0_ecc() __read_32bit_c0_register($26, 0)
  1574. #define write_c0_ecc(val) __write_32bit_c0_register($26, 0, val)
  1575. #define read_c0_derraddr0() __read_ulong_c0_register($26, 1)
  1576. #define write_c0_derraddr0(val) __write_ulong_c0_register($26, 1, val)
  1577. #define read_c0_cacheerr() __read_32bit_c0_register($27, 0)
  1578. #define read_c0_derraddr1() __read_ulong_c0_register($27, 1)
  1579. #define write_c0_derraddr1(val) __write_ulong_c0_register($27, 1, val)
  1580. #define read_c0_taglo() __read_32bit_c0_register($28, 0)
  1581. #define write_c0_taglo(val) __write_32bit_c0_register($28, 0, val)
  1582. #define read_c0_dtaglo() __read_32bit_c0_register($28, 2)
  1583. #define write_c0_dtaglo(val) __write_32bit_c0_register($28, 2, val)
  1584. #define read_c0_ddatalo() __read_32bit_c0_register($28, 3)
  1585. #define write_c0_ddatalo(val) __write_32bit_c0_register($28, 3, val)
  1586. #define read_c0_staglo() __read_32bit_c0_register($28, 4)
  1587. #define write_c0_staglo(val) __write_32bit_c0_register($28, 4, val)
  1588. #define read_c0_taghi() __read_32bit_c0_register($29, 0)
  1589. #define write_c0_taghi(val) __write_32bit_c0_register($29, 0, val)
  1590. #define read_c0_errorepc() __read_ulong_c0_register($30, 0)
  1591. #define write_c0_errorepc(val) __write_ulong_c0_register($30, 0, val)
  1592. /* MIPSR2 */
  1593. #define read_c0_hwrena() __read_32bit_c0_register($7, 0)
  1594. #define write_c0_hwrena(val) __write_32bit_c0_register($7, 0, val)
  1595. #define read_c0_intctl() __read_32bit_c0_register($12, 1)
  1596. #define write_c0_intctl(val) __write_32bit_c0_register($12, 1, val)
  1597. #define read_c0_srsctl() __read_32bit_c0_register($12, 2)
  1598. #define write_c0_srsctl(val) __write_32bit_c0_register($12, 2, val)
  1599. #define read_c0_srsmap() __read_32bit_c0_register($12, 3)
  1600. #define write_c0_srsmap(val) __write_32bit_c0_register($12, 3, val)
  1601. #define read_c0_ebase() __read_32bit_c0_register($15, 1)
  1602. #define write_c0_ebase(val) __write_32bit_c0_register($15, 1, val)
  1603. #define read_c0_ebase_64() __read_64bit_c0_register($15, 1)
  1604. #define write_c0_ebase_64(val) __write_64bit_c0_register($15, 1, val)
  1605. #define read_c0_cdmmbase() __read_ulong_c0_register($15, 2)
  1606. #define write_c0_cdmmbase(val) __write_ulong_c0_register($15, 2, val)
  1607. /* MIPSR3 */
  1608. #define read_c0_segctl0() __read_32bit_c0_register($5, 2)
  1609. #define write_c0_segctl0(val) __write_32bit_c0_register($5, 2, val)
  1610. #define read_c0_segctl1() __read_32bit_c0_register($5, 3)
  1611. #define write_c0_segctl1(val) __write_32bit_c0_register($5, 3, val)
  1612. #define read_c0_segctl2() __read_32bit_c0_register($5, 4)
  1613. #define write_c0_segctl2(val) __write_32bit_c0_register($5, 4, val)
  1614. /* Hardware Page Table Walker */
  1615. #define read_c0_pwbase() __read_ulong_c0_register($5, 5)
  1616. #define write_c0_pwbase(val) __write_ulong_c0_register($5, 5, val)
  1617. #define read_c0_pwfield() __read_ulong_c0_register($5, 6)
  1618. #define write_c0_pwfield(val) __write_ulong_c0_register($5, 6, val)
  1619. #define read_c0_pwsize() __read_ulong_c0_register($5, 7)
  1620. #define write_c0_pwsize(val) __write_ulong_c0_register($5, 7, val)
  1621. #define read_c0_pwctl() __read_32bit_c0_register($6, 6)
  1622. #define write_c0_pwctl(val) __write_32bit_c0_register($6, 6, val)
  1623. #define read_c0_pgd() __read_64bit_c0_register($9, 7)
  1624. #define write_c0_pgd(val) __write_64bit_c0_register($9, 7, val)
  1625. #define read_c0_kpgd() __read_64bit_c0_register($31, 7)
  1626. #define write_c0_kpgd(val) __write_64bit_c0_register($31, 7, val)
  1627. /* Cavium OCTEON (cnMIPS) */
  1628. #define read_c0_cvmcount() __read_ulong_c0_register($9, 6)
  1629. #define write_c0_cvmcount(val) __write_ulong_c0_register($9, 6, val)
  1630. #define read_c0_cvmctl() __read_64bit_c0_register($9, 7)
  1631. #define write_c0_cvmctl(val) __write_64bit_c0_register($9, 7, val)
  1632. #define read_c0_cvmmemctl() __read_64bit_c0_register($11, 7)
  1633. #define write_c0_cvmmemctl(val) __write_64bit_c0_register($11, 7, val)
  1634. #define read_c0_cvmmemctl2() __read_64bit_c0_register($16, 6)
  1635. #define write_c0_cvmmemctl2(val) __write_64bit_c0_register($16, 6, val)
  1636. #define read_c0_cvmvmconfig() __read_64bit_c0_register($16, 7)
  1637. #define write_c0_cvmvmconfig(val) __write_64bit_c0_register($16, 7, val)
  1638. /*
  1639. * The cacheerr registers are not standardized. On OCTEON, they are
  1640. * 64 bits wide.
  1641. */
  1642. #define read_octeon_c0_icacheerr() __read_64bit_c0_register($27, 0)
  1643. #define write_octeon_c0_icacheerr(val) __write_64bit_c0_register($27, 0, val)
  1644. #define read_octeon_c0_dcacheerr() __read_64bit_c0_register($27, 1)
  1645. #define write_octeon_c0_dcacheerr(val) __write_64bit_c0_register($27, 1, val)
  1646. /* BMIPS3300 */
  1647. #define read_c0_brcm_config_0() __read_32bit_c0_register($22, 0)
  1648. #define write_c0_brcm_config_0(val) __write_32bit_c0_register($22, 0, val)
  1649. #define read_c0_brcm_bus_pll() __read_32bit_c0_register($22, 4)
  1650. #define write_c0_brcm_bus_pll(val) __write_32bit_c0_register($22, 4, val)
  1651. #define read_c0_brcm_reset() __read_32bit_c0_register($22, 5)
  1652. #define write_c0_brcm_reset(val) __write_32bit_c0_register($22, 5, val)
  1653. /* BMIPS43xx */
  1654. #define read_c0_brcm_cmt_intr() __read_32bit_c0_register($22, 1)
  1655. #define write_c0_brcm_cmt_intr(val) __write_32bit_c0_register($22, 1, val)
  1656. #define read_c0_brcm_cmt_ctrl() __read_32bit_c0_register($22, 2)
  1657. #define write_c0_brcm_cmt_ctrl(val) __write_32bit_c0_register($22, 2, val)
  1658. #define read_c0_brcm_cmt_local() __read_32bit_c0_register($22, 3)
  1659. #define write_c0_brcm_cmt_local(val) __write_32bit_c0_register($22, 3, val)
  1660. #define read_c0_brcm_config_1() __read_32bit_c0_register($22, 5)
  1661. #define write_c0_brcm_config_1(val) __write_32bit_c0_register($22, 5, val)
  1662. #define read_c0_brcm_cbr() __read_32bit_c0_register($22, 6)
  1663. #define write_c0_brcm_cbr(val) __write_32bit_c0_register($22, 6, val)
  1664. /* BMIPS5000 */
  1665. #define read_c0_brcm_config() __read_32bit_c0_register($22, 0)
  1666. #define write_c0_brcm_config(val) __write_32bit_c0_register($22, 0, val)
  1667. #define read_c0_brcm_mode() __read_32bit_c0_register($22, 1)
  1668. #define write_c0_brcm_mode(val) __write_32bit_c0_register($22, 1, val)
  1669. #define read_c0_brcm_action() __read_32bit_c0_register($22, 2)
  1670. #define write_c0_brcm_action(val) __write_32bit_c0_register($22, 2, val)
  1671. #define read_c0_brcm_edsp() __read_32bit_c0_register($22, 3)
  1672. #define write_c0_brcm_edsp(val) __write_32bit_c0_register($22, 3, val)
  1673. #define read_c0_brcm_bootvec() __read_32bit_c0_register($22, 4)
  1674. #define write_c0_brcm_bootvec(val) __write_32bit_c0_register($22, 4, val)
  1675. #define read_c0_brcm_sleepcount() __read_32bit_c0_register($22, 7)
  1676. #define write_c0_brcm_sleepcount(val) __write_32bit_c0_register($22, 7, val)
  1677. /* Ingenic page ctrl register */
  1678. #define write_c0_page_ctrl(val) __write_32bit_c0_register($5, 4, val)
  1679. /*
  1680. * Macros to access the guest system control coprocessor
  1681. */
  1682. #ifndef TOOLCHAIN_SUPPORTS_VIRT
  1683. _ASM_MACRO_2R_1S(mfgc0, rt, rs, sel,
  1684. _ASM_INSN_IF_MIPS(0x40600000 | __rt << 16 | __rs << 11 | \\sel)
  1685. _ASM_INSN32_IF_MM(0x000004fc | __rt << 21 | __rs << 16 | \\sel << 11));
  1686. _ASM_MACRO_2R_1S(dmfgc0, rt, rs, sel,
  1687. _ASM_INSN_IF_MIPS(0x40600100 | __rt << 16 | __rs << 11 | \\sel)
  1688. _ASM_INSN32_IF_MM(0x580004fc | __rt << 21 | __rs << 16 | \\sel << 11));
  1689. _ASM_MACRO_2R_1S(mtgc0, rt, rd, sel,
  1690. _ASM_INSN_IF_MIPS(0x40600200 | __rt << 16 | __rd << 11 | \\sel)
  1691. _ASM_INSN32_IF_MM(0x000006fc | __rt << 21 | __rd << 16 | \\sel << 11));
  1692. _ASM_MACRO_2R_1S(dmtgc0, rt, rd, sel,
  1693. _ASM_INSN_IF_MIPS(0x40600300 | __rt << 16 | __rd << 11 | \\sel)
  1694. _ASM_INSN32_IF_MM(0x580006fc | __rt << 21 | __rd << 16 | \\sel << 11));
  1695. _ASM_MACRO_0(tlbgp, _ASM_INSN_IF_MIPS(0x42000010)
  1696. _ASM_INSN32_IF_MM(0x0000017c));
  1697. _ASM_MACRO_0(tlbgr, _ASM_INSN_IF_MIPS(0x42000009)
  1698. _ASM_INSN32_IF_MM(0x0000117c));
  1699. _ASM_MACRO_0(tlbgwi, _ASM_INSN_IF_MIPS(0x4200000a)
  1700. _ASM_INSN32_IF_MM(0x0000217c));
  1701. _ASM_MACRO_0(tlbgwr, _ASM_INSN_IF_MIPS(0x4200000e)
  1702. _ASM_INSN32_IF_MM(0x0000317c));
  1703. _ASM_MACRO_0(tlbginvf, _ASM_INSN_IF_MIPS(0x4200000c)
  1704. _ASM_INSN32_IF_MM(0x0000517c));
  1705. #define _ASM_SET_VIRT ""
  1706. #else /* !TOOLCHAIN_SUPPORTS_VIRT */
  1707. #define _ASM_SET_VIRT ".set\tvirt\n\t"
  1708. #endif
  1709. #define __read_32bit_gc0_register(source, sel) \
  1710. ({ int __res; \
  1711. __asm__ __volatile__( \
  1712. ".set\tpush\n\t" \
  1713. ".set\tmips32r2\n\t" \
  1714. _ASM_SET_VIRT \
  1715. "mfgc0\t%0, " #source ", %1\n\t" \
  1716. ".set\tpop" \
  1717. : "=r" (__res) \
  1718. : "i" (sel)); \
  1719. __res; \
  1720. })
  1721. #define __read_64bit_gc0_register(source, sel) \
  1722. ({ unsigned long long __res; \
  1723. __asm__ __volatile__( \
  1724. ".set\tpush\n\t" \
  1725. ".set\tmips64r2\n\t" \
  1726. _ASM_SET_VIRT \
  1727. "dmfgc0\t%0, " #source ", %1\n\t" \
  1728. ".set\tpop" \
  1729. : "=r" (__res) \
  1730. : "i" (sel)); \
  1731. __res; \
  1732. })
  1733. #define __write_32bit_gc0_register(register, sel, value) \
  1734. do { \
  1735. __asm__ __volatile__( \
  1736. ".set\tpush\n\t" \
  1737. ".set\tmips32r2\n\t" \
  1738. _ASM_SET_VIRT \
  1739. "mtgc0\t%z0, " #register ", %1\n\t" \
  1740. ".set\tpop" \
  1741. : : "Jr" ((unsigned int)(value)), \
  1742. "i" (sel)); \
  1743. } while (0)
  1744. #define __write_64bit_gc0_register(register, sel, value) \
  1745. do { \
  1746. __asm__ __volatile__( \
  1747. ".set\tpush\n\t" \
  1748. ".set\tmips64r2\n\t" \
  1749. _ASM_SET_VIRT \
  1750. "dmtgc0\t%z0, " #register ", %1\n\t" \
  1751. ".set\tpop" \
  1752. : : "Jr" (value), \
  1753. "i" (sel)); \
  1754. } while (0)
  1755. #define __read_ulong_gc0_register(reg, sel) \
  1756. ((sizeof(unsigned long) == 4) ? \
  1757. (unsigned long) __read_32bit_gc0_register(reg, sel) : \
  1758. (unsigned long) __read_64bit_gc0_register(reg, sel))
  1759. #define __write_ulong_gc0_register(reg, sel, val) \
  1760. do { \
  1761. if (sizeof(unsigned long) == 4) \
  1762. __write_32bit_gc0_register(reg, sel, val); \
  1763. else \
  1764. __write_64bit_gc0_register(reg, sel, val); \
  1765. } while (0)
  1766. #define read_gc0_index() __read_32bit_gc0_register($0, 0)
  1767. #define write_gc0_index(val) __write_32bit_gc0_register($0, 0, val)
  1768. #define read_gc0_entrylo0() __read_ulong_gc0_register($2, 0)
  1769. #define write_gc0_entrylo0(val) __write_ulong_gc0_register($2, 0, val)
  1770. #define read_gc0_entrylo1() __read_ulong_gc0_register($3, 0)
  1771. #define write_gc0_entrylo1(val) __write_ulong_gc0_register($3, 0, val)
  1772. #define read_gc0_context() __read_ulong_gc0_register($4, 0)
  1773. #define write_gc0_context(val) __write_ulong_gc0_register($4, 0, val)
  1774. #define read_gc0_contextconfig() __read_32bit_gc0_register($4, 1)
  1775. #define write_gc0_contextconfig(val) __write_32bit_gc0_register($4, 1, val)
  1776. #define read_gc0_userlocal() __read_ulong_gc0_register($4, 2)
  1777. #define write_gc0_userlocal(val) __write_ulong_gc0_register($4, 2, val)
  1778. #define read_gc0_xcontextconfig() __read_ulong_gc0_register($4, 3)
  1779. #define write_gc0_xcontextconfig(val) __write_ulong_gc0_register($4, 3, val)
  1780. #define read_gc0_pagemask() __read_32bit_gc0_register($5, 0)
  1781. #define write_gc0_pagemask(val) __write_32bit_gc0_register($5, 0, val)
  1782. #define read_gc0_pagegrain() __read_32bit_gc0_register($5, 1)
  1783. #define write_gc0_pagegrain(val) __write_32bit_gc0_register($5, 1, val)
  1784. #define read_gc0_segctl0() __read_ulong_gc0_register($5, 2)
  1785. #define write_gc0_segctl0(val) __write_ulong_gc0_register($5, 2, val)
  1786. #define read_gc0_segctl1() __read_ulong_gc0_register($5, 3)
  1787. #define write_gc0_segctl1(val) __write_ulong_gc0_register($5, 3, val)
  1788. #define read_gc0_segctl2() __read_ulong_gc0_register($5, 4)
  1789. #define write_gc0_segctl2(val) __write_ulong_gc0_register($5, 4, val)
  1790. #define read_gc0_pwbase() __read_ulong_gc0_register($5, 5)
  1791. #define write_gc0_pwbase(val) __write_ulong_gc0_register($5, 5, val)
  1792. #define read_gc0_pwfield() __read_ulong_gc0_register($5, 6)
  1793. #define write_gc0_pwfield(val) __write_ulong_gc0_register($5, 6, val)
  1794. #define read_gc0_pwsize() __read_ulong_gc0_register($5, 7)
  1795. #define write_gc0_pwsize(val) __write_ulong_gc0_register($5, 7, val)
  1796. #define read_gc0_wired() __read_32bit_gc0_register($6, 0)
  1797. #define write_gc0_wired(val) __write_32bit_gc0_register($6, 0, val)
  1798. #define read_gc0_pwctl() __read_32bit_gc0_register($6, 6)
  1799. #define write_gc0_pwctl(val) __write_32bit_gc0_register($6, 6, val)
  1800. #define read_gc0_hwrena() __read_32bit_gc0_register($7, 0)
  1801. #define write_gc0_hwrena(val) __write_32bit_gc0_register($7, 0, val)
  1802. #define read_gc0_badvaddr() __read_ulong_gc0_register($8, 0)
  1803. #define write_gc0_badvaddr(val) __write_ulong_gc0_register($8, 0, val)
  1804. #define read_gc0_badinstr() __read_32bit_gc0_register($8, 1)
  1805. #define write_gc0_badinstr(val) __write_32bit_gc0_register($8, 1, val)
  1806. #define read_gc0_badinstrp() __read_32bit_gc0_register($8, 2)
  1807. #define write_gc0_badinstrp(val) __write_32bit_gc0_register($8, 2, val)
  1808. #define read_gc0_count() __read_32bit_gc0_register($9, 0)
  1809. #define read_gc0_entryhi() __read_ulong_gc0_register($10, 0)
  1810. #define write_gc0_entryhi(val) __write_ulong_gc0_register($10, 0, val)
  1811. #define read_gc0_compare() __read_32bit_gc0_register($11, 0)
  1812. #define write_gc0_compare(val) __write_32bit_gc0_register($11, 0, val)
  1813. #define read_gc0_status() __read_32bit_gc0_register($12, 0)
  1814. #define write_gc0_status(val) __write_32bit_gc0_register($12, 0, val)
  1815. #define read_gc0_intctl() __read_32bit_gc0_register($12, 1)
  1816. #define write_gc0_intctl(val) __write_32bit_gc0_register($12, 1, val)
  1817. #define read_gc0_cause() __read_32bit_gc0_register($13, 0)
  1818. #define write_gc0_cause(val) __write_32bit_gc0_register($13, 0, val)
  1819. #define read_gc0_epc() __read_ulong_gc0_register($14, 0)
  1820. #define write_gc0_epc(val) __write_ulong_gc0_register($14, 0, val)
  1821. #define read_gc0_prid() __read_32bit_gc0_register($15, 0)
  1822. #define read_gc0_ebase() __read_32bit_gc0_register($15, 1)
  1823. #define write_gc0_ebase(val) __write_32bit_gc0_register($15, 1, val)
  1824. #define read_gc0_ebase_64() __read_64bit_gc0_register($15, 1)
  1825. #define write_gc0_ebase_64(val) __write_64bit_gc0_register($15, 1, val)
  1826. #define read_gc0_config() __read_32bit_gc0_register($16, 0)
  1827. #define read_gc0_config1() __read_32bit_gc0_register($16, 1)
  1828. #define read_gc0_config2() __read_32bit_gc0_register($16, 2)
  1829. #define read_gc0_config3() __read_32bit_gc0_register($16, 3)
  1830. #define read_gc0_config4() __read_32bit_gc0_register($16, 4)
  1831. #define read_gc0_config5() __read_32bit_gc0_register($16, 5)
  1832. #define read_gc0_config6() __read_32bit_gc0_register($16, 6)
  1833. #define read_gc0_config7() __read_32bit_gc0_register($16, 7)
  1834. #define write_gc0_config(val) __write_32bit_gc0_register($16, 0, val)
  1835. #define write_gc0_config1(val) __write_32bit_gc0_register($16, 1, val)
  1836. #define write_gc0_config2(val) __write_32bit_gc0_register($16, 2, val)
  1837. #define write_gc0_config3(val) __write_32bit_gc0_register($16, 3, val)
  1838. #define write_gc0_config4(val) __write_32bit_gc0_register($16, 4, val)
  1839. #define write_gc0_config5(val) __write_32bit_gc0_register($16, 5, val)
  1840. #define write_gc0_config6(val) __write_32bit_gc0_register($16, 6, val)
  1841. #define write_gc0_config7(val) __write_32bit_gc0_register($16, 7, val)
  1842. #define read_gc0_lladdr() __read_ulong_gc0_register($17, 0)
  1843. #define write_gc0_lladdr(val) __write_ulong_gc0_register($17, 0, val)
  1844. #define read_gc0_watchlo0() __read_ulong_gc0_register($18, 0)
  1845. #define read_gc0_watchlo1() __read_ulong_gc0_register($18, 1)
  1846. #define read_gc0_watchlo2() __read_ulong_gc0_register($18, 2)
  1847. #define read_gc0_watchlo3() __read_ulong_gc0_register($18, 3)
  1848. #define read_gc0_watchlo4() __read_ulong_gc0_register($18, 4)
  1849. #define read_gc0_watchlo5() __read_ulong_gc0_register($18, 5)
  1850. #define read_gc0_watchlo6() __read_ulong_gc0_register($18, 6)
  1851. #define read_gc0_watchlo7() __read_ulong_gc0_register($18, 7)
  1852. #define write_gc0_watchlo0(val) __write_ulong_gc0_register($18, 0, val)
  1853. #define write_gc0_watchlo1(val) __write_ulong_gc0_register($18, 1, val)
  1854. #define write_gc0_watchlo2(val) __write_ulong_gc0_register($18, 2, val)
  1855. #define write_gc0_watchlo3(val) __write_ulong_gc0_register($18, 3, val)
  1856. #define write_gc0_watchlo4(val) __write_ulong_gc0_register($18, 4, val)
  1857. #define write_gc0_watchlo5(val) __write_ulong_gc0_register($18, 5, val)
  1858. #define write_gc0_watchlo6(val) __write_ulong_gc0_register($18, 6, val)
  1859. #define write_gc0_watchlo7(val) __write_ulong_gc0_register($18, 7, val)
  1860. #define read_gc0_watchhi0() __read_32bit_gc0_register($19, 0)
  1861. #define read_gc0_watchhi1() __read_32bit_gc0_register($19, 1)
  1862. #define read_gc0_watchhi2() __read_32bit_gc0_register($19, 2)
  1863. #define read_gc0_watchhi3() __read_32bit_gc0_register($19, 3)
  1864. #define read_gc0_watchhi4() __read_32bit_gc0_register($19, 4)
  1865. #define read_gc0_watchhi5() __read_32bit_gc0_register($19, 5)
  1866. #define read_gc0_watchhi6() __read_32bit_gc0_register($19, 6)
  1867. #define read_gc0_watchhi7() __read_32bit_gc0_register($19, 7)
  1868. #define write_gc0_watchhi0(val) __write_32bit_gc0_register($19, 0, val)
  1869. #define write_gc0_watchhi1(val) __write_32bit_gc0_register($19, 1, val)
  1870. #define write_gc0_watchhi2(val) __write_32bit_gc0_register($19, 2, val)
  1871. #define write_gc0_watchhi3(val) __write_32bit_gc0_register($19, 3, val)
  1872. #define write_gc0_watchhi4(val) __write_32bit_gc0_register($19, 4, val)
  1873. #define write_gc0_watchhi5(val) __write_32bit_gc0_register($19, 5, val)
  1874. #define write_gc0_watchhi6(val) __write_32bit_gc0_register($19, 6, val)
  1875. #define write_gc0_watchhi7(val) __write_32bit_gc0_register($19, 7, val)
  1876. #define read_gc0_xcontext() __read_ulong_gc0_register($20, 0)
  1877. #define write_gc0_xcontext(val) __write_ulong_gc0_register($20, 0, val)
  1878. #define read_gc0_perfctrl0() __read_32bit_gc0_register($25, 0)
  1879. #define write_gc0_perfctrl0(val) __write_32bit_gc0_register($25, 0, val)
  1880. #define read_gc0_perfcntr0() __read_32bit_gc0_register($25, 1)
  1881. #define write_gc0_perfcntr0(val) __write_32bit_gc0_register($25, 1, val)
  1882. #define read_gc0_perfcntr0_64() __read_64bit_gc0_register($25, 1)
  1883. #define write_gc0_perfcntr0_64(val) __write_64bit_gc0_register($25, 1, val)
  1884. #define read_gc0_perfctrl1() __read_32bit_gc0_register($25, 2)
  1885. #define write_gc0_perfctrl1(val) __write_32bit_gc0_register($25, 2, val)
  1886. #define read_gc0_perfcntr1() __read_32bit_gc0_register($25, 3)
  1887. #define write_gc0_perfcntr1(val) __write_32bit_gc0_register($25, 3, val)
  1888. #define read_gc0_perfcntr1_64() __read_64bit_gc0_register($25, 3)
  1889. #define write_gc0_perfcntr1_64(val) __write_64bit_gc0_register($25, 3, val)
  1890. #define read_gc0_perfctrl2() __read_32bit_gc0_register($25, 4)
  1891. #define write_gc0_perfctrl2(val) __write_32bit_gc0_register($25, 4, val)
  1892. #define read_gc0_perfcntr2() __read_32bit_gc0_register($25, 5)
  1893. #define write_gc0_perfcntr2(val) __write_32bit_gc0_register($25, 5, val)
  1894. #define read_gc0_perfcntr2_64() __read_64bit_gc0_register($25, 5)
  1895. #define write_gc0_perfcntr2_64(val) __write_64bit_gc0_register($25, 5, val)
  1896. #define read_gc0_perfctrl3() __read_32bit_gc0_register($25, 6)
  1897. #define write_gc0_perfctrl3(val) __write_32bit_gc0_register($25, 6, val)
  1898. #define read_gc0_perfcntr3() __read_32bit_gc0_register($25, 7)
  1899. #define write_gc0_perfcntr3(val) __write_32bit_gc0_register($25, 7, val)
  1900. #define read_gc0_perfcntr3_64() __read_64bit_gc0_register($25, 7)
  1901. #define write_gc0_perfcntr3_64(val) __write_64bit_gc0_register($25, 7, val)
  1902. #define read_gc0_errorepc() __read_ulong_gc0_register($30, 0)
  1903. #define write_gc0_errorepc(val) __write_ulong_gc0_register($30, 0, val)
  1904. #define read_gc0_kscratch1() __read_ulong_gc0_register($31, 2)
  1905. #define read_gc0_kscratch2() __read_ulong_gc0_register($31, 3)
  1906. #define read_gc0_kscratch3() __read_ulong_gc0_register($31, 4)
  1907. #define read_gc0_kscratch4() __read_ulong_gc0_register($31, 5)
  1908. #define read_gc0_kscratch5() __read_ulong_gc0_register($31, 6)
  1909. #define read_gc0_kscratch6() __read_ulong_gc0_register($31, 7)
  1910. #define write_gc0_kscratch1(val) __write_ulong_gc0_register($31, 2, val)
  1911. #define write_gc0_kscratch2(val) __write_ulong_gc0_register($31, 3, val)
  1912. #define write_gc0_kscratch3(val) __write_ulong_gc0_register($31, 4, val)
  1913. #define write_gc0_kscratch4(val) __write_ulong_gc0_register($31, 5, val)
  1914. #define write_gc0_kscratch5(val) __write_ulong_gc0_register($31, 6, val)
  1915. #define write_gc0_kscratch6(val) __write_ulong_gc0_register($31, 7, val)
  1916. /* Cavium OCTEON (cnMIPS) */
  1917. #define read_gc0_cvmcount() __read_ulong_gc0_register($9, 6)
  1918. #define write_gc0_cvmcount(val) __write_ulong_gc0_register($9, 6, val)
  1919. #define read_gc0_cvmctl() __read_64bit_gc0_register($9, 7)
  1920. #define write_gc0_cvmctl(val) __write_64bit_gc0_register($9, 7, val)
  1921. #define read_gc0_cvmmemctl() __read_64bit_gc0_register($11, 7)
  1922. #define write_gc0_cvmmemctl(val) __write_64bit_gc0_register($11, 7, val)
  1923. #define read_gc0_cvmmemctl2() __read_64bit_gc0_register($16, 6)
  1924. #define write_gc0_cvmmemctl2(val) __write_64bit_gc0_register($16, 6, val)
  1925. /*
  1926. * Macros to access the floating point coprocessor control registers
  1927. */
  1928. #define _read_32bit_cp1_register(source, gas_hardfloat) \
  1929. ({ \
  1930. unsigned int __res; \
  1931. \
  1932. __asm__ __volatile__( \
  1933. " .set push \n" \
  1934. " .set reorder \n" \
  1935. " # gas fails to assemble cfc1 for some archs, \n" \
  1936. " # like Octeon. \n" \
  1937. " .set mips1 \n" \
  1938. " "STR(gas_hardfloat)" \n" \
  1939. " cfc1 %0,"STR(source)" \n" \
  1940. " .set pop \n" \
  1941. : "=r" (__res)); \
  1942. __res; \
  1943. })
  1944. #define _write_32bit_cp1_register(dest, val, gas_hardfloat) \
  1945. do { \
  1946. __asm__ __volatile__( \
  1947. " .set push \n" \
  1948. " .set reorder \n" \
  1949. " "STR(gas_hardfloat)" \n" \
  1950. " ctc1 %0,"STR(dest)" \n" \
  1951. " .set pop \n" \
  1952. : : "r" (val)); \
  1953. } while (0)
  1954. #ifdef GAS_HAS_SET_HARDFLOAT
  1955. #define read_32bit_cp1_register(source) \
  1956. _read_32bit_cp1_register(source, .set hardfloat)
  1957. #define write_32bit_cp1_register(dest, val) \
  1958. _write_32bit_cp1_register(dest, val, .set hardfloat)
  1959. #else
  1960. #define read_32bit_cp1_register(source) \
  1961. _read_32bit_cp1_register(source, )
  1962. #define write_32bit_cp1_register(dest, val) \
  1963. _write_32bit_cp1_register(dest, val, )
  1964. #endif
  1965. #ifdef TOOLCHAIN_SUPPORTS_DSP
  1966. #define rddsp(mask) \
  1967. ({ \
  1968. unsigned int __dspctl; \
  1969. \
  1970. __asm__ __volatile__( \
  1971. " .set push \n" \
  1972. " .set " MIPS_ISA_LEVEL " \n" \
  1973. " .set dsp \n" \
  1974. " rddsp %0, %x1 \n" \
  1975. " .set pop \n" \
  1976. : "=r" (__dspctl) \
  1977. : "i" (mask)); \
  1978. __dspctl; \
  1979. })
  1980. #define wrdsp(val, mask) \
  1981. do { \
  1982. __asm__ __volatile__( \
  1983. " .set push \n" \
  1984. " .set " MIPS_ISA_LEVEL " \n" \
  1985. " .set dsp \n" \
  1986. " wrdsp %0, %x1 \n" \
  1987. " .set pop \n" \
  1988. : \
  1989. : "r" (val), "i" (mask)); \
  1990. } while (0)
  1991. #define mflo0() \
  1992. ({ \
  1993. long mflo0; \
  1994. __asm__( \
  1995. " .set push \n" \
  1996. " .set " MIPS_ISA_LEVEL " \n" \
  1997. " .set dsp \n" \
  1998. " mflo %0, $ac0 \n" \
  1999. " .set pop \n" \
  2000. : "=r" (mflo0)); \
  2001. mflo0; \
  2002. })
  2003. #define mflo1() \
  2004. ({ \
  2005. long mflo1; \
  2006. __asm__( \
  2007. " .set push \n" \
  2008. " .set " MIPS_ISA_LEVEL " \n" \
  2009. " .set dsp \n" \
  2010. " mflo %0, $ac1 \n" \
  2011. " .set pop \n" \
  2012. : "=r" (mflo1)); \
  2013. mflo1; \
  2014. })
  2015. #define mflo2() \
  2016. ({ \
  2017. long mflo2; \
  2018. __asm__( \
  2019. " .set push \n" \
  2020. " .set " MIPS_ISA_LEVEL " \n" \
  2021. " .set dsp \n" \
  2022. " mflo %0, $ac2 \n" \
  2023. " .set pop \n" \
  2024. : "=r" (mflo2)); \
  2025. mflo2; \
  2026. })
  2027. #define mflo3() \
  2028. ({ \
  2029. long mflo3; \
  2030. __asm__( \
  2031. " .set push \n" \
  2032. " .set " MIPS_ISA_LEVEL " \n" \
  2033. " .set dsp \n" \
  2034. " mflo %0, $ac3 \n" \
  2035. " .set pop \n" \
  2036. : "=r" (mflo3)); \
  2037. mflo3; \
  2038. })
  2039. #define mfhi0() \
  2040. ({ \
  2041. long mfhi0; \
  2042. __asm__( \
  2043. " .set push \n" \
  2044. " .set " MIPS_ISA_LEVEL " \n" \
  2045. " .set dsp \n" \
  2046. " mfhi %0, $ac0 \n" \
  2047. " .set pop \n" \
  2048. : "=r" (mfhi0)); \
  2049. mfhi0; \
  2050. })
  2051. #define mfhi1() \
  2052. ({ \
  2053. long mfhi1; \
  2054. __asm__( \
  2055. " .set push \n" \
  2056. " .set " MIPS_ISA_LEVEL " \n" \
  2057. " .set dsp \n" \
  2058. " mfhi %0, $ac1 \n" \
  2059. " .set pop \n" \
  2060. : "=r" (mfhi1)); \
  2061. mfhi1; \
  2062. })
  2063. #define mfhi2() \
  2064. ({ \
  2065. long mfhi2; \
  2066. __asm__( \
  2067. " .set push \n" \
  2068. " .set " MIPS_ISA_LEVEL " \n" \
  2069. " .set dsp \n" \
  2070. " mfhi %0, $ac2 \n" \
  2071. " .set pop \n" \
  2072. : "=r" (mfhi2)); \
  2073. mfhi2; \
  2074. })
  2075. #define mfhi3() \
  2076. ({ \
  2077. long mfhi3; \
  2078. __asm__( \
  2079. " .set push \n" \
  2080. " .set " MIPS_ISA_LEVEL " \n" \
  2081. " .set dsp \n" \
  2082. " mfhi %0, $ac3 \n" \
  2083. " .set pop \n" \
  2084. : "=r" (mfhi3)); \
  2085. mfhi3; \
  2086. })
  2087. #define mtlo0(x) \
  2088. ({ \
  2089. __asm__( \
  2090. " .set push \n" \
  2091. " .set " MIPS_ISA_LEVEL " \n" \
  2092. " .set dsp \n" \
  2093. " mtlo %0, $ac0 \n" \
  2094. " .set pop \n" \
  2095. : \
  2096. : "r" (x)); \
  2097. })
  2098. #define mtlo1(x) \
  2099. ({ \
  2100. __asm__( \
  2101. " .set push \n" \
  2102. " .set " MIPS_ISA_LEVEL " \n" \
  2103. " .set dsp \n" \
  2104. " mtlo %0, $ac1 \n" \
  2105. " .set pop \n" \
  2106. : \
  2107. : "r" (x)); \
  2108. })
  2109. #define mtlo2(x) \
  2110. ({ \
  2111. __asm__( \
  2112. " .set push \n" \
  2113. " .set " MIPS_ISA_LEVEL " \n" \
  2114. " .set dsp \n" \
  2115. " mtlo %0, $ac2 \n" \
  2116. " .set pop \n" \
  2117. : \
  2118. : "r" (x)); \
  2119. })
  2120. #define mtlo3(x) \
  2121. ({ \
  2122. __asm__( \
  2123. " .set push \n" \
  2124. " .set " MIPS_ISA_LEVEL " \n" \
  2125. " .set dsp \n" \
  2126. " mtlo %0, $ac3 \n" \
  2127. " .set pop \n" \
  2128. : \
  2129. : "r" (x)); \
  2130. })
  2131. #define mthi0(x) \
  2132. ({ \
  2133. __asm__( \
  2134. " .set push \n" \
  2135. " .set " MIPS_ISA_LEVEL " \n" \
  2136. " .set dsp \n" \
  2137. " mthi %0, $ac0 \n" \
  2138. " .set pop \n" \
  2139. : \
  2140. : "r" (x)); \
  2141. })
  2142. #define mthi1(x) \
  2143. ({ \
  2144. __asm__( \
  2145. " .set push \n" \
  2146. " .set " MIPS_ISA_LEVEL " \n" \
  2147. " .set dsp \n" \
  2148. " mthi %0, $ac1 \n" \
  2149. " .set pop \n" \
  2150. : \
  2151. : "r" (x)); \
  2152. })
  2153. #define mthi2(x) \
  2154. ({ \
  2155. __asm__( \
  2156. " .set push \n" \
  2157. " .set " MIPS_ISA_LEVEL " \n" \
  2158. " .set dsp \n" \
  2159. " mthi %0, $ac2 \n" \
  2160. " .set pop \n" \
  2161. : \
  2162. : "r" (x)); \
  2163. })
  2164. #define mthi3(x) \
  2165. ({ \
  2166. __asm__( \
  2167. " .set push \n" \
  2168. " .set " MIPS_ISA_LEVEL " \n" \
  2169. " .set dsp \n" \
  2170. " mthi %0, $ac3 \n" \
  2171. " .set pop \n" \
  2172. : \
  2173. : "r" (x)); \
  2174. })
  2175. #else
  2176. #define rddsp(mask) \
  2177. ({ \
  2178. unsigned int __res; \
  2179. \
  2180. __asm__ __volatile__( \
  2181. " .set push \n" \
  2182. " .set noat \n" \
  2183. " # rddsp $1, %x1 \n" \
  2184. _ASM_INSN_IF_MIPS(0x7c000cb8 | (%x1 << 16)) \
  2185. _ASM_INSN32_IF_MM(0x0020067c | (%x1 << 14)) \
  2186. " move %0, $1 \n" \
  2187. " .set pop \n" \
  2188. : "=r" (__res) \
  2189. : "i" (mask)); \
  2190. __res; \
  2191. })
  2192. #define wrdsp(val, mask) \
  2193. do { \
  2194. __asm__ __volatile__( \
  2195. " .set push \n" \
  2196. " .set noat \n" \
  2197. " move $1, %0 \n" \
  2198. " # wrdsp $1, %x1 \n" \
  2199. _ASM_INSN_IF_MIPS(0x7c2004f8 | (%x1 << 11)) \
  2200. _ASM_INSN32_IF_MM(0x0020167c | (%x1 << 14)) \
  2201. " .set pop \n" \
  2202. : \
  2203. : "r" (val), "i" (mask)); \
  2204. } while (0)
  2205. #define _dsp_mfxxx(ins) \
  2206. ({ \
  2207. unsigned long __treg; \
  2208. \
  2209. __asm__ __volatile__( \
  2210. " .set push \n" \
  2211. " .set noat \n" \
  2212. _ASM_INSN_IF_MIPS(0x00000810 | %X1) \
  2213. _ASM_INSN32_IF_MM(0x0001007c | %x1) \
  2214. " move %0, $1 \n" \
  2215. " .set pop \n" \
  2216. : "=r" (__treg) \
  2217. : "i" (ins)); \
  2218. __treg; \
  2219. })
  2220. #define _dsp_mtxxx(val, ins) \
  2221. do { \
  2222. __asm__ __volatile__( \
  2223. " .set push \n" \
  2224. " .set noat \n" \
  2225. " move $1, %0 \n" \
  2226. _ASM_INSN_IF_MIPS(0x00200011 | %X1) \
  2227. _ASM_INSN32_IF_MM(0x0001207c | %x1) \
  2228. " .set pop \n" \
  2229. : \
  2230. : "r" (val), "i" (ins)); \
  2231. } while (0)
  2232. #ifdef CONFIG_CPU_MICROMIPS
  2233. #define _dsp_mflo(reg) _dsp_mfxxx((reg << 14) | 0x1000)
  2234. #define _dsp_mfhi(reg) _dsp_mfxxx((reg << 14) | 0x0000)
  2235. #define _dsp_mtlo(val, reg) _dsp_mtxxx(val, ((reg << 14) | 0x1000))
  2236. #define _dsp_mthi(val, reg) _dsp_mtxxx(val, ((reg << 14) | 0x0000))
  2237. #else /* !CONFIG_CPU_MICROMIPS */
  2238. #define _dsp_mflo(reg) _dsp_mfxxx((reg << 21) | 0x0002)
  2239. #define _dsp_mfhi(reg) _dsp_mfxxx((reg << 21) | 0x0000)
  2240. #define _dsp_mtlo(val, reg) _dsp_mtxxx(val, ((reg << 11) | 0x0002))
  2241. #define _dsp_mthi(val, reg) _dsp_mtxxx(val, ((reg << 11) | 0x0000))
  2242. #endif /* CONFIG_CPU_MICROMIPS */
  2243. #define mflo0() _dsp_mflo(0)
  2244. #define mflo1() _dsp_mflo(1)
  2245. #define mflo2() _dsp_mflo(2)
  2246. #define mflo3() _dsp_mflo(3)
  2247. #define mfhi0() _dsp_mfhi(0)
  2248. #define mfhi1() _dsp_mfhi(1)
  2249. #define mfhi2() _dsp_mfhi(2)
  2250. #define mfhi3() _dsp_mfhi(3)
  2251. #define mtlo0(x) _dsp_mtlo(x, 0)
  2252. #define mtlo1(x) _dsp_mtlo(x, 1)
  2253. #define mtlo2(x) _dsp_mtlo(x, 2)
  2254. #define mtlo3(x) _dsp_mtlo(x, 3)
  2255. #define mthi0(x) _dsp_mthi(x, 0)
  2256. #define mthi1(x) _dsp_mthi(x, 1)
  2257. #define mthi2(x) _dsp_mthi(x, 2)
  2258. #define mthi3(x) _dsp_mthi(x, 3)
  2259. #endif
  2260. /*
  2261. * TLB operations.
  2262. *
  2263. * It is responsibility of the caller to take care of any TLB hazards.
  2264. */
  2265. static inline void tlb_probe(void)
  2266. {
  2267. __asm__ __volatile__(
  2268. ".set noreorder\n\t"
  2269. "tlbp\n\t"
  2270. ".set reorder");
  2271. }
  2272. static inline void tlb_read(void)
  2273. {
  2274. #if MIPS34K_MISSED_ITLB_WAR
  2275. int res = 0;
  2276. __asm__ __volatile__(
  2277. " .set push \n"
  2278. " .set noreorder \n"
  2279. " .set noat \n"
  2280. " .set mips32r2 \n"
  2281. " .word 0x41610001 # dvpe $1 \n"
  2282. " move %0, $1 \n"
  2283. " ehb \n"
  2284. " .set pop \n"
  2285. : "=r" (res));
  2286. instruction_hazard();
  2287. #endif
  2288. __asm__ __volatile__(
  2289. ".set noreorder\n\t"
  2290. "tlbr\n\t"
  2291. ".set reorder");
  2292. #if MIPS34K_MISSED_ITLB_WAR
  2293. if ((res & _ULCAST_(1)))
  2294. __asm__ __volatile__(
  2295. " .set push \n"
  2296. " .set noreorder \n"
  2297. " .set noat \n"
  2298. " .set mips32r2 \n"
  2299. " .word 0x41600021 # evpe \n"
  2300. " ehb \n"
  2301. " .set pop \n");
  2302. #endif
  2303. }
  2304. static inline void tlb_write_indexed(void)
  2305. {
  2306. __asm__ __volatile__(
  2307. ".set noreorder\n\t"
  2308. "tlbwi\n\t"
  2309. ".set reorder");
  2310. }
  2311. static inline void tlb_write_random(void)
  2312. {
  2313. __asm__ __volatile__(
  2314. ".set noreorder\n\t"
  2315. "tlbwr\n\t"
  2316. ".set reorder");
  2317. }
  2318. /*
  2319. * Guest TLB operations.
  2320. *
  2321. * It is responsibility of the caller to take care of any TLB hazards.
  2322. */
  2323. static inline void guest_tlb_probe(void)
  2324. {
  2325. __asm__ __volatile__(
  2326. ".set push\n\t"
  2327. ".set noreorder\n\t"
  2328. _ASM_SET_VIRT
  2329. "tlbgp\n\t"
  2330. ".set pop");
  2331. }
  2332. static inline void guest_tlb_read(void)
  2333. {
  2334. __asm__ __volatile__(
  2335. ".set push\n\t"
  2336. ".set noreorder\n\t"
  2337. _ASM_SET_VIRT
  2338. "tlbgr\n\t"
  2339. ".set pop");
  2340. }
  2341. static inline void guest_tlb_write_indexed(void)
  2342. {
  2343. __asm__ __volatile__(
  2344. ".set push\n\t"
  2345. ".set noreorder\n\t"
  2346. _ASM_SET_VIRT
  2347. "tlbgwi\n\t"
  2348. ".set pop");
  2349. }
  2350. static inline void guest_tlb_write_random(void)
  2351. {
  2352. __asm__ __volatile__(
  2353. ".set push\n\t"
  2354. ".set noreorder\n\t"
  2355. _ASM_SET_VIRT
  2356. "tlbgwr\n\t"
  2357. ".set pop");
  2358. }
  2359. /*
  2360. * Guest TLB Invalidate Flush
  2361. */
  2362. static inline void guest_tlbinvf(void)
  2363. {
  2364. __asm__ __volatile__(
  2365. ".set push\n\t"
  2366. ".set noreorder\n\t"
  2367. _ASM_SET_VIRT
  2368. "tlbginvf\n\t"
  2369. ".set pop");
  2370. }
  2371. /*
  2372. * Manipulate bits in a register.
  2373. */
  2374. #define __BUILD_SET_COMMON(name) \
  2375. static inline unsigned int \
  2376. set_##name(unsigned int set) \
  2377. { \
  2378. unsigned int res, new; \
  2379. \
  2380. res = read_##name(); \
  2381. new = res | set; \
  2382. write_##name(new); \
  2383. \
  2384. return res; \
  2385. } \
  2386. \
  2387. static inline unsigned int \
  2388. clear_##name(unsigned int clear) \
  2389. { \
  2390. unsigned int res, new; \
  2391. \
  2392. res = read_##name(); \
  2393. new = res & ~clear; \
  2394. write_##name(new); \
  2395. \
  2396. return res; \
  2397. } \
  2398. \
  2399. static inline unsigned int \
  2400. change_##name(unsigned int change, unsigned int val) \
  2401. { \
  2402. unsigned int res, new; \
  2403. \
  2404. res = read_##name(); \
  2405. new = res & ~change; \
  2406. new |= (val & change); \
  2407. write_##name(new); \
  2408. \
  2409. return res; \
  2410. }
  2411. /*
  2412. * Manipulate bits in a c0 register.
  2413. */
  2414. #define __BUILD_SET_C0(name) __BUILD_SET_COMMON(c0_##name)
  2415. __BUILD_SET_C0(status)
  2416. __BUILD_SET_C0(cause)
  2417. __BUILD_SET_C0(config)
  2418. __BUILD_SET_C0(config5)
  2419. __BUILD_SET_C0(config7)
  2420. __BUILD_SET_C0(intcontrol)
  2421. __BUILD_SET_C0(intctl)
  2422. __BUILD_SET_C0(srsmap)
  2423. __BUILD_SET_C0(pagegrain)
  2424. __BUILD_SET_C0(guestctl0)
  2425. __BUILD_SET_C0(guestctl0ext)
  2426. __BUILD_SET_C0(guestctl1)
  2427. __BUILD_SET_C0(guestctl2)
  2428. __BUILD_SET_C0(guestctl3)
  2429. __BUILD_SET_C0(brcm_config_0)
  2430. __BUILD_SET_C0(brcm_bus_pll)
  2431. __BUILD_SET_C0(brcm_reset)
  2432. __BUILD_SET_C0(brcm_cmt_intr)
  2433. __BUILD_SET_C0(brcm_cmt_ctrl)
  2434. __BUILD_SET_C0(brcm_config)
  2435. __BUILD_SET_C0(brcm_mode)
  2436. /*
  2437. * Manipulate bits in a guest c0 register.
  2438. */
  2439. #define __BUILD_SET_GC0(name) __BUILD_SET_COMMON(gc0_##name)
  2440. __BUILD_SET_GC0(wired)
  2441. __BUILD_SET_GC0(status)
  2442. __BUILD_SET_GC0(cause)
  2443. __BUILD_SET_GC0(ebase)
  2444. __BUILD_SET_GC0(config1)
  2445. /*
  2446. * Return low 10 bits of ebase.
  2447. * Note that under KVM (MIPSVZ) this returns vcpu id.
  2448. */
  2449. static inline unsigned int get_ebase_cpunum(void)
  2450. {
  2451. return read_c0_ebase() & MIPS_EBASE_CPUNUM;
  2452. }
  2453. static inline void write_one_tlb(int index, u32 pagemask, u32 hi, u32 low0,
  2454. u32 low1)
  2455. {
  2456. write_c0_entrylo0(low0);
  2457. write_c0_pagemask(pagemask);
  2458. write_c0_entrylo1(low1);
  2459. write_c0_entryhi(hi);
  2460. write_c0_index(index);
  2461. tlb_write_indexed();
  2462. }
  2463. #endif /* !__ASSEMBLY__ */
  2464. #endif /* _ASM_MIPSREGS_H */