guruplug.c 2.8 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * (C) Copyright 2009
  4. * Marvell Semiconductor <www.marvell.com>
  5. * Written-by: Siddarth Gore <gores@marvell.com>
  6. */
  7. #include <common.h>
  8. #include <init.h>
  9. #include <miiphy.h>
  10. #include <net.h>
  11. #include <asm/global_data.h>
  12. #include <asm/mach-types.h>
  13. #include <asm/arch/cpu.h>
  14. #include <asm/arch/soc.h>
  15. #include <asm/arch/mpp.h>
  16. #include "guruplug.h"
  17. DECLARE_GLOBAL_DATA_PTR;
  18. int board_early_init_f(void)
  19. {
  20. /*
  21. * default gpio configuration
  22. * There are maximum 64 gpios controlled through 2 sets of registers
  23. * the below configuration configures mainly initial LED status
  24. */
  25. mvebu_config_gpio(GURUPLUG_OE_VAL_LOW,
  26. GURUPLUG_OE_VAL_HIGH,
  27. GURUPLUG_OE_LOW, GURUPLUG_OE_HIGH);
  28. /* Multi-Purpose Pins Functionality configuration */
  29. static const u32 kwmpp_config[] = {
  30. MPP0_NF_IO2,
  31. MPP1_NF_IO3,
  32. MPP2_NF_IO4,
  33. MPP3_NF_IO5,
  34. MPP4_NF_IO6,
  35. MPP5_NF_IO7,
  36. MPP6_SYSRST_OUTn,
  37. MPP7_GPO, /* GPIO_RST */
  38. MPP8_TW_SDA,
  39. MPP9_TW_SCK,
  40. MPP10_UART0_TXD,
  41. MPP11_UART0_RXD,
  42. MPP12_SD_CLK,
  43. MPP13_SD_CMD,
  44. MPP14_SD_D0,
  45. MPP15_SD_D1,
  46. MPP16_SD_D2,
  47. MPP17_SD_D3,
  48. MPP18_NF_IO0,
  49. MPP19_NF_IO1,
  50. MPP20_GE1_0,
  51. MPP21_GE1_1,
  52. MPP22_GE1_2,
  53. MPP23_GE1_3,
  54. MPP24_GE1_4,
  55. MPP25_GE1_5,
  56. MPP26_GE1_6,
  57. MPP27_GE1_7,
  58. MPP28_GE1_8,
  59. MPP29_GE1_9,
  60. MPP30_GE1_10,
  61. MPP31_GE1_11,
  62. MPP32_GE1_12,
  63. MPP33_GE1_13,
  64. MPP34_GE1_14,
  65. MPP35_GE1_15,
  66. MPP36_GPIO,
  67. MPP37_GPIO,
  68. MPP38_GPIO,
  69. MPP39_GPIO,
  70. MPP40_TDM_SPI_SCK,
  71. MPP41_TDM_SPI_MISO,
  72. MPP42_TDM_SPI_MOSI,
  73. MPP43_GPIO,
  74. MPP44_GPIO,
  75. MPP45_GPIO,
  76. MPP46_GPIO, /* M_RLED */
  77. MPP47_GPIO, /* M_GLED */
  78. MPP48_GPIO, /* B_RLED */
  79. MPP49_GPIO, /* B_GLED */
  80. 0
  81. };
  82. kirkwood_mpp_conf(kwmpp_config, NULL);
  83. return 0;
  84. }
  85. int board_init(void)
  86. {
  87. /*
  88. * arch number of board
  89. */
  90. gd->bd->bi_arch_number = MACH_TYPE_GURUPLUG;
  91. /* adress of boot parameters */
  92. gd->bd->bi_boot_params = mvebu_sdram_bar(0) + 0x100;
  93. return 0;
  94. }
  95. #ifdef CONFIG_RESET_PHY_R
  96. void mv_phy_88e1121_init(char *name)
  97. {
  98. u16 reg;
  99. u16 devadr;
  100. if (miiphy_set_current_dev(name))
  101. return;
  102. /* command to read PHY dev address */
  103. if (miiphy_read(name, 0xEE, 0xEE, (u16 *) &devadr)) {
  104. printf("Err..%s could not read PHY dev address\n",
  105. __FUNCTION__);
  106. return;
  107. }
  108. /*
  109. * Enable RGMII delay on Tx and Rx for CPU port
  110. * Ref: sec 4.7.2 of chip datasheet
  111. */
  112. miiphy_write(name, devadr, MV88E1121_PGADR_REG, 2);
  113. miiphy_read(name, devadr, MV88E1121_MAC_CTRL2_REG, &reg);
  114. reg |= (MV88E1121_RGMII_RXTM_CTRL | MV88E1121_RGMII_TXTM_CTRL);
  115. miiphy_write(name, devadr, MV88E1121_MAC_CTRL2_REG, reg);
  116. miiphy_write(name, devadr, MV88E1121_PGADR_REG, 0);
  117. /* reset the phy */
  118. miiphy_reset(name, devadr);
  119. printf("88E1121 Initialized on %s\n", name);
  120. }
  121. void reset_phy(void)
  122. {
  123. /* configure and initialize both PHY's */
  124. mv_phy_88e1121_init("egiga0");
  125. mv_phy_88e1121_init("egiga1");
  126. }
  127. #endif /* CONFIG_RESET_PHY_R */