README 3.0 KB

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  1. Overview
  2. --------
  3. QorIQ LS1012A Reference Design System (LS1012ARDB) is a high-performance
  4. development platform, with a complete debugging environment.
  5. The LS1012ARDB board supports the QorIQ LS1012A processor and is
  6. optimized to support the high-bandwidth DDR3L memory and
  7. a full complement of high-speed SerDes ports.
  8. LS1012A SoC Overview
  9. --------------------
  10. Please refer arch/arm/cpu/armv8/fsl-layerscape/doc/README.soc for LS2080A
  11. SoC overview.
  12. LS1012ARDB board Overview
  13. -----------------------
  14. - SERDES Connections, 4 lanes supporting:
  15. - PCI Express - 3.0
  16. - SGMII, SGMII 2.5
  17. - SATA 3.0
  18. - DDR Controller
  19. - 16-bit, 1 GB DDR3L SDRAM memory, running at data rates up to 1 GT/s
  20. -QSPI: A dual 1:3 switch, NX3L4357GM,115 (U35) drives the QSPI chip-select
  21. signals to
  22. - QSPI NOR flash memory (2 virtual banks)
  23. - the QSPI emulator.s
  24. - USB 3.0
  25. - one high-speed USB 2.0/3.0 port.
  26. - Two enhanced secure digital host controllers:
  27. - SDHC1 controller can be connected to onboard SDHC connector
  28. - SDHC2 controller: Three dual 1:4 mux/demux devices,
  29. 74CBTLV3253DS (U30, U31, U33) drive the SDHC2 signals to eMMC,
  30. SDIO WiFi, SPI, and Ardiuno shield
  31. - 2 I2C controllers
  32. - One SATA onboard connectors
  33. - UART
  34. - The LS1012A processor consists of two UART controllers,
  35. out of which only UART1 is used on RDB.
  36. - ARM JTAG support
  37. Booting Options
  38. ---------------
  39. a) QSPI Flash Emu Boot
  40. b) QSPI Flash 1
  41. c) QSPI Flash 2
  42. QSPI flash map
  43. --------------
  44. Images | Size |QSPI Flash Address
  45. ------------------------------------------
  46. RCW + PBI | 1MB | 0x4000_0000
  47. U-boot | 1MB | 0x4010_0000
  48. U-boot Env | 1MB | 0x4020_0000
  49. PPA FIT image | 2MB | 0x4050_0000
  50. Linux ITB | ~53MB | 0x40A0_0000
  51. LS1012A2G5RDB board Overview
  52. -----------------------
  53. - SERDES Connections, 3 lanes supporting:
  54. - SGMII, SGMII 2.5
  55. - SATA 3.0
  56. - DDR Controller
  57. - 16-bit, 1 GB DDR3L SDRAM memory, running at data rates up to 1 GT/s
  58. -QSPI: A dual 1:3 switch, NX3L4357GM,115 (U35) drives the QSPI chip-select
  59. signals to
  60. - QSPI NOR flash memory
  61. - USB 3.0
  62. - one high-speed USB 2.0/3.0 port.
  63. - SDIO WiFi, SPI
  64. - 2 I2C controllers
  65. - One SATA onboard connectors
  66. - UART
  67. - The LS1012A processor consists of two UART controllers,
  68. out of which only UART1 is used on 2G5RDB.
  69. - ARM JTAG support
  70. Major Difference between LS1012ARDB and LS1012A-2G5RDB
  71. ------------------------------------------------------
  72. 1. LS1012A-2G5RDB has Type C USB connector unlike USB Type A/B of LS1012ARDB
  73. 2. LS1012A-2G5RDB has 2 2.5G AQR PHY unlike 2 1G Realtek RTL8211FS PHYs
  74. of LS1012ARDB
  75. 3. LS1012A-2G5RDB is not having Arduino header
  76. 4. LS1012A-2G5RDB doesn't have PCI slot
  77. Booting Options
  78. ---------------
  79. QSPI Flash
  80. QSPI flash map
  81. --------------
  82. Images | Size |QSPI Flash Address
  83. ------------------------------------------
  84. RCW + PBI | 1MB | 0x4000_0000
  85. U-boot | 1MB | 0x4010_0000
  86. U-boot Env | 1MB | 0x4030_0000
  87. PPA FIT image | 2MB | 0x4040_0000
  88. PFE firmware | 20K | 0x00a0_0000
  89. Linux ITB | ~53MB | 0x4100_0000