dram_sun8i_a33.c 9.9 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Sun8i a33 platform dram controller init.
  4. *
  5. * (C) Copyright 2007-2015 Allwinner Technology Co.
  6. * Jerry Wang <wangflord@allwinnertech.com>
  7. * (C) Copyright 2015 Vishnu Patekar <vishnupatekar0510@gmail.com>
  8. * (C) Copyright 2015 Hans de Goede <hdegoede@redhat.com>
  9. */
  10. #include <common.h>
  11. #include <errno.h>
  12. #include <init.h>
  13. #include <asm/io.h>
  14. #include <asm/arch/clock.h>
  15. #include <asm/arch/dram.h>
  16. #include <asm/arch/prcm.h>
  17. #include <linux/delay.h>
  18. /* PLL runs at 2x dram-clk, controller runs at PLL / 4 (dram-clk / 2) */
  19. #define DRAM_CLK_MUL 2
  20. #define DRAM_CLK_DIV 4
  21. #define DRAM_SIGMA_DELTA_ENABLE 1
  22. struct dram_para {
  23. u8 cs1;
  24. u8 seq;
  25. u8 bank;
  26. u8 rank;
  27. u8 rows;
  28. u8 bus_width;
  29. u16 page_size;
  30. };
  31. static void mctl_set_cr(struct dram_para *para)
  32. {
  33. struct sunxi_mctl_com_reg * const mctl_com =
  34. (struct sunxi_mctl_com_reg *)SUNXI_DRAM_COM_BASE;
  35. writel(MCTL_CR_CS1_CONTROL(para->cs1) | MCTL_CR_UNKNOWN |
  36. MCTL_CR_CHANNEL(1) | MCTL_CR_DDR3 |
  37. (para->seq ? MCTL_CR_SEQUENCE : 0) |
  38. ((para->bus_width == 16) ? MCTL_CR_BUSW16 : MCTL_CR_BUSW8) |
  39. MCTL_CR_PAGE_SIZE(para->page_size) | MCTL_CR_ROW(para->rows) |
  40. MCTL_CR_BANK(para->bank) | MCTL_CR_RANK(para->rank),
  41. &mctl_com->cr);
  42. }
  43. static void auto_detect_dram_size(struct dram_para *para)
  44. {
  45. u8 orig_rank = para->rank;
  46. int rows, columns;
  47. /* Row detect */
  48. para->page_size = 512;
  49. para->seq = 1;
  50. para->rows = 16;
  51. para->rank = 1;
  52. mctl_set_cr(para);
  53. for (rows = 11 ; rows < 16 ; rows++) {
  54. if (mctl_mem_matches(1 << (rows + 9))) /* row-column */
  55. break;
  56. }
  57. /* Column (page size) detect */
  58. para->rows = 11;
  59. para->page_size = 8192;
  60. mctl_set_cr(para);
  61. for (columns = 9 ; columns < 13 ; columns++) {
  62. if (mctl_mem_matches(1 << columns))
  63. break;
  64. }
  65. para->seq = 0;
  66. para->rank = orig_rank;
  67. para->rows = rows;
  68. para->page_size = 1 << columns;
  69. mctl_set_cr(para);
  70. }
  71. static inline int ns_to_t(int nanoseconds)
  72. {
  73. const unsigned int ctrl_freq =
  74. CONFIG_DRAM_CLK * DRAM_CLK_MUL / DRAM_CLK_DIV;
  75. return (ctrl_freq * nanoseconds + 999) / 1000;
  76. }
  77. static void auto_set_timing_para(struct dram_para *para)
  78. {
  79. struct sunxi_mctl_ctl_reg * const mctl_ctl =
  80. (struct sunxi_mctl_ctl_reg *)SUNXI_DRAM_CTL0_BASE;
  81. u32 reg_val;
  82. u8 tccd = 2;
  83. u8 tfaw = ns_to_t(50);
  84. u8 trrd = max(ns_to_t(10), 4);
  85. u8 trcd = ns_to_t(15);
  86. u8 trc = ns_to_t(53);
  87. u8 txp = max(ns_to_t(8), 3);
  88. u8 twtr = max(ns_to_t(8), 4);
  89. u8 trtp = max(ns_to_t(8), 4);
  90. u8 twr = max(ns_to_t(15), 3);
  91. u8 trp = ns_to_t(15);
  92. u8 tras = ns_to_t(38);
  93. u16 trefi = ns_to_t(7800) / 32;
  94. u16 trfc = ns_to_t(350);
  95. /* Fixed timing parameters */
  96. u8 tmrw = 0;
  97. u8 tmrd = 4;
  98. u8 tmod = 12;
  99. u8 tcke = 3;
  100. u8 tcksrx = 5;
  101. u8 tcksre = 5;
  102. u8 tckesr = 4;
  103. u8 trasmax = 24;
  104. u8 tcl = 6; /* CL 12 */
  105. u8 tcwl = 4; /* CWL 8 */
  106. u8 t_rdata_en = 4;
  107. u8 wr_latency = 2;
  108. u32 tdinit0 = (500 * CONFIG_DRAM_CLK) + 1; /* 500us */
  109. u32 tdinit1 = (360 * CONFIG_DRAM_CLK) / 1000 + 1; /* 360ns */
  110. u32 tdinit2 = (200 * CONFIG_DRAM_CLK) + 1; /* 200us */
  111. u32 tdinit3 = (1 * CONFIG_DRAM_CLK) + 1; /* 1us */
  112. u8 twtp = tcwl + 2 + twr; /* WL + BL / 2 + tWR */
  113. u8 twr2rd = tcwl + 2 + twtr; /* WL + BL / 2 + tWTR */
  114. u8 trd2wr = tcl + 2 + 1 - tcwl; /* RL + BL / 2 + 2 - WL */
  115. /* Set work mode register */
  116. mctl_set_cr(para);
  117. /* Set mode register */
  118. writel(MCTL_MR0, &mctl_ctl->mr0);
  119. writel(MCTL_MR1, &mctl_ctl->mr1);
  120. writel(MCTL_MR2, &mctl_ctl->mr2);
  121. writel(MCTL_MR3, &mctl_ctl->mr3);
  122. /* Set dram timing */
  123. reg_val = (twtp << 24) | (tfaw << 16) | (trasmax << 8) | (tras << 0);
  124. writel(reg_val, &mctl_ctl->dramtmg0);
  125. reg_val = (txp << 16) | (trtp << 8) | (trc << 0);
  126. writel(reg_val, &mctl_ctl->dramtmg1);
  127. reg_val = (tcwl << 24) | (tcl << 16) | (trd2wr << 8) | (twr2rd << 0);
  128. writel(reg_val, &mctl_ctl->dramtmg2);
  129. reg_val = (tmrw << 16) | (tmrd << 12) | (tmod << 0);
  130. writel(reg_val, &mctl_ctl->dramtmg3);
  131. reg_val = (trcd << 24) | (tccd << 16) | (trrd << 8) | (trp << 0);
  132. writel(reg_val, &mctl_ctl->dramtmg4);
  133. reg_val = (tcksrx << 24) | (tcksre << 16) | (tckesr << 8) | (tcke << 0);
  134. writel(reg_val, &mctl_ctl->dramtmg5);
  135. /* Set two rank timing and exit self-refresh timing */
  136. reg_val = readl(&mctl_ctl->dramtmg8);
  137. reg_val &= ~(0xff << 8);
  138. reg_val &= ~(0xff << 0);
  139. reg_val |= (0x33 << 8);
  140. reg_val |= (0x10 << 0);
  141. writel(reg_val, &mctl_ctl->dramtmg8);
  142. /* Set phy interface time */
  143. reg_val = (0x2 << 24) | (t_rdata_en << 16) | (0x1 << 8)
  144. | (wr_latency << 0);
  145. /* PHY interface write latency and read latency configure */
  146. writel(reg_val, &mctl_ctl->pitmg0);
  147. /* Set phy time PTR0-2 use default */
  148. writel(((tdinit0 << 0) | (tdinit1 << 20)), &mctl_ctl->ptr3);
  149. writel(((tdinit2 << 0) | (tdinit3 << 20)), &mctl_ctl->ptr4);
  150. /* Set refresh timing */
  151. reg_val = (trefi << 16) | (trfc << 0);
  152. writel(reg_val, &mctl_ctl->rfshtmg);
  153. }
  154. static void mctl_set_pir(u32 val)
  155. {
  156. struct sunxi_mctl_ctl_reg * const mctl_ctl =
  157. (struct sunxi_mctl_ctl_reg *)SUNXI_DRAM_CTL0_BASE;
  158. writel(val, &mctl_ctl->pir);
  159. mctl_await_completion(&mctl_ctl->pgsr0, 0x1, 0x1);
  160. }
  161. static void mctl_data_train_cfg(struct dram_para *para)
  162. {
  163. struct sunxi_mctl_ctl_reg * const mctl_ctl =
  164. (struct sunxi_mctl_ctl_reg *)SUNXI_DRAM_CTL0_BASE;
  165. if (para->rank == 2)
  166. clrsetbits_le32(&mctl_ctl->dtcr, 0x3 << 24, 0x3 << 24);
  167. else
  168. clrsetbits_le32(&mctl_ctl->dtcr, 0x3 << 24, 0x1 << 24);
  169. }
  170. static int mctl_train_dram(struct dram_para *para)
  171. {
  172. struct sunxi_mctl_ctl_reg * const mctl_ctl =
  173. (struct sunxi_mctl_ctl_reg *)SUNXI_DRAM_CTL0_BASE;
  174. mctl_data_train_cfg(para);
  175. mctl_set_pir(0x5f3);
  176. return ((readl(&mctl_ctl->pgsr0) >> 20) & 0xff) ? -EIO : 0;
  177. }
  178. static int mctl_channel_init(struct dram_para *para)
  179. {
  180. struct sunxi_mctl_ctl_reg * const mctl_ctl =
  181. (struct sunxi_mctl_ctl_reg *)SUNXI_DRAM_CTL0_BASE;
  182. struct sunxi_mctl_com_reg * const mctl_com =
  183. (struct sunxi_mctl_com_reg *)SUNXI_DRAM_COM_BASE;
  184. u32 low_data_lines_status; /* Training status of datalines 0 - 7 */
  185. u32 high_data_lines_status; /* Training status of datalines 8 - 15 */
  186. auto_set_timing_para(para);
  187. /* Disable dram VTC */
  188. clrbits_le32(&mctl_ctl->pgcr0, 0x3f << 0);
  189. /* Set ODT */
  190. if ((CONFIG_DRAM_CLK > 400) && IS_ENABLED(CONFIG_DRAM_ODT_EN)) {
  191. setbits_le32(DXnGCR0(0), 0x3 << 9);
  192. setbits_le32(DXnGCR0(1), 0x3 << 9);
  193. } else {
  194. clrbits_le32(DXnGCR0(0), 0x3 << 9);
  195. clrbits_le32(DXnGCR0(1), 0x3 << 9);
  196. }
  197. /* set PLL configuration */
  198. if (CONFIG_DRAM_CLK >= 480)
  199. setbits_le32(&mctl_ctl->pllgcr, 0x1 << 18);
  200. else
  201. setbits_le32(&mctl_ctl->pllgcr, 0x3 << 18);
  202. /* Auto detect dram config, set 2 rank and 16bit bus-width */
  203. para->cs1 = 0;
  204. para->rank = 2;
  205. para->bus_width = 16;
  206. mctl_set_cr(para);
  207. /* Open DQS gating */
  208. clrbits_le32(&mctl_ctl->pgcr2, (0x3 << 6));
  209. clrbits_le32(&mctl_ctl->dqsgmr, (0x1 << 8) | (0x7));
  210. mctl_data_train_cfg(para);
  211. /* ZQ calibration */
  212. writel(CONFIG_DRAM_ZQ & 0xff, &mctl_ctl->zqcr1);
  213. /* CA calibration */
  214. mctl_set_pir(0x00000003);
  215. /* More ZQ calibration */
  216. writel(readl(&mctl_ctl->zqsr0) | 0x10000000, &mctl_ctl->zqcr2);
  217. writel((CONFIG_DRAM_ZQ >> 8) & 0xff, &mctl_ctl->zqcr1);
  218. /* DQS gate training */
  219. if (mctl_train_dram(para) != 0) {
  220. low_data_lines_status = (readl(DXnGSR0(0)) >> 24) & 0x03;
  221. high_data_lines_status = (readl(DXnGSR0(1)) >> 24) & 0x03;
  222. if (low_data_lines_status == 0x3)
  223. return -EIO;
  224. /* DRAM has only one rank */
  225. para->rank = 1;
  226. mctl_set_cr(para);
  227. if (low_data_lines_status == high_data_lines_status)
  228. goto done; /* 16 bit bus, 1 rank */
  229. if (!(low_data_lines_status & high_data_lines_status)) {
  230. /* Retry 16 bit bus-width with CS1 set */
  231. para->cs1 = 1;
  232. mctl_set_cr(para);
  233. if (mctl_train_dram(para) == 0)
  234. goto done;
  235. }
  236. /* Try 8 bit bus-width */
  237. writel(0x0, DXnGCR0(1)); /* Disable high DQ */
  238. para->cs1 = 0;
  239. para->bus_width = 8;
  240. mctl_set_cr(para);
  241. if (mctl_train_dram(para) != 0)
  242. return -EIO;
  243. }
  244. done:
  245. /* Check the dramc status */
  246. mctl_await_completion(&mctl_ctl->statr, 0x1, 0x1);
  247. /* Close DQS gating */
  248. setbits_le32(&mctl_ctl->pgcr2, 0x3 << 6);
  249. /* Enable master access */
  250. writel(0xffffffff, &mctl_com->maer);
  251. return 0;
  252. }
  253. static void mctl_sys_init(struct dram_para *para)
  254. {
  255. struct sunxi_ccm_reg * const ccm =
  256. (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
  257. struct sunxi_mctl_ctl_reg * const mctl_ctl =
  258. (struct sunxi_mctl_ctl_reg *)SUNXI_DRAM_CTL0_BASE;
  259. struct sunxi_mctl_com_reg * const mctl_com =
  260. (struct sunxi_mctl_com_reg *)SUNXI_DRAM_COM_BASE;
  261. clrsetbits_le32(&ccm->dram_pll_cfg, CCM_DRAMPLL_CFG_SRC_MASK,
  262. CCM_DRAMPLL_CFG_SRC_PLL11);
  263. clock_set_pll11(CONFIG_DRAM_CLK * 1000000 * DRAM_CLK_MUL,
  264. DRAM_SIGMA_DELTA_ENABLE);
  265. clrsetbits_le32(&ccm->dram_clk_cfg, CCM_DRAMCLK_CFG_DIV_MASK,
  266. CCM_DRAMCLK_CFG_DIV(DRAM_CLK_DIV) |
  267. CCM_DRAMCLK_CFG_RST | CCM_DRAMCLK_CFG_UPD);
  268. mctl_await_completion(&ccm->dram_clk_cfg, CCM_DRAMCLK_CFG_UPD, 0);
  269. setbits_le32(&ccm->ahb_reset0_cfg, 1 << AHB_RESET_OFFSET_MCTL);
  270. setbits_le32(&ccm->ahb_gate0, 1 << AHB_GATE_OFFSET_MCTL);
  271. setbits_le32(&ccm->mbus_reset, CCM_MBUS_RESET_RESET);
  272. setbits_le32(&ccm->mbus0_clk_cfg, MBUS_CLK_GATE);
  273. /* Set dram master access priority */
  274. writel(0x0, &mctl_com->mapr);
  275. writel(0x0f802f01, &mctl_ctl->sched);
  276. writel(0x0000400f, &mctl_ctl->clken); /* normal */
  277. udelay(250);
  278. }
  279. unsigned long sunxi_dram_init(void)
  280. {
  281. struct sunxi_mctl_com_reg * const mctl_com =
  282. (struct sunxi_mctl_com_reg *)SUNXI_DRAM_COM_BASE;
  283. struct sunxi_mctl_ctl_reg * const mctl_ctl =
  284. (struct sunxi_mctl_ctl_reg *)SUNXI_DRAM_CTL0_BASE;
  285. struct dram_para para = {
  286. .cs1 = 0,
  287. .bank = 1,
  288. .rank = 2,
  289. .rows = 15,
  290. .bus_width = 16,
  291. .page_size = 2048,
  292. };
  293. mctl_sys_init(&para);
  294. if (mctl_channel_init(&para) != 0)
  295. return 0;
  296. auto_detect_dram_size(&para);
  297. /* Enable master software clk */
  298. writel(readl(&mctl_com->swonr) | 0x3ffff, &mctl_com->swonr);
  299. /* Set DRAM ODT MAP */
  300. if (para.rank == 2)
  301. writel(0x00000303, &mctl_ctl->odtmap);
  302. else
  303. writel(0x00000201, &mctl_ctl->odtmap);
  304. return para.page_size * (para.bus_width / 8) *
  305. (1 << (para.bank + para.rank + para.rows));
  306. }