imx-regs.h 15 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233234235236237238239240241242243244245246247248249250251252253254255256257258259260261262263264265266267268269270271272273274275276277278279280281282283284285286287288289290291292293294295296297298299300301302303304305306307308309310311312313314315316317318319320321322323324325326327328329330331332333334335336337338339340341342343344345346347348349350351352353354355356357358359360361362363364365366367368369370371372373374375376377378379380381382383384385386387388389390391392393394395396397398399400401402403404405406407408409410411412413414415416417418419420421422423424425426427428429430431432433434435436437438439440441442443444445446447448449450451452453454455456457458459460461462463464465466467468469470471472473474475476477478479480481482483484485486487488489490491492493494495496497498499500501502503504
  1. /* SPDX-License-Identifier: GPL-2.0+ */
  2. /*
  3. * Copyright (C) 2009, DENX Software Engineering
  4. * Author: John Rigby <jcrigby@gmail.com
  5. *
  6. * Based on arch-mx31/imx-regs.h
  7. * Copyright (C) 2009 Ilya Yanok,
  8. * Emcraft Systems <yanok@emcraft.com>
  9. * and arch-mx27/imx-regs.h
  10. * Copyright (C) 2007 Pengutronix,
  11. * Sascha Hauer <s.hauer@pengutronix.de>
  12. * Copyright (C) 2009 Ilya Yanok,
  13. * Emcraft Systems <yanok@emcraft.com>
  14. */
  15. #ifndef _IMX_REGS_H
  16. #define _IMX_REGS_H
  17. #if !(defined(__KERNEL_STRICT_NAMES) || defined(__ASSEMBLY__))
  18. #include <asm/types.h>
  19. /* Clock Control Module (CCM) registers */
  20. struct ccm_regs {
  21. u32 mpctl; /* Core PLL Control */
  22. u32 upctl; /* USB PLL Control */
  23. u32 cctl; /* Clock Control */
  24. u32 cgr0; /* Clock Gating Control 0 */
  25. u32 cgr1; /* Clock Gating Control 1 */
  26. u32 cgr2; /* Clock Gating Control 2 */
  27. u32 pcdr[4]; /* PER Clock Dividers */
  28. u32 rcsr; /* CCM Status */
  29. u32 crdr; /* CCM Reset and Debug */
  30. u32 dcvr0; /* DPTC Comparator Value 0 */
  31. u32 dcvr1; /* DPTC Comparator Value 1 */
  32. u32 dcvr2; /* DPTC Comparator Value 2 */
  33. u32 dcvr3; /* DPTC Comparator Value 3 */
  34. u32 ltr0; /* Load Tracking 0 */
  35. u32 ltr1; /* Load Tracking 1 */
  36. u32 ltr2; /* Load Tracking 2 */
  37. u32 ltr3; /* Load Tracking 3 */
  38. u32 ltbr0; /* Load Tracking Buffer 0 */
  39. u32 ltbr1; /* Load Tracking Buffer 1 */
  40. u32 pcmr0; /* Power Management Control 0 */
  41. u32 pcmr1; /* Power Management Control 1 */
  42. u32 pcmr2; /* Power Management Control 2 */
  43. u32 mcr; /* Miscellaneous Control */
  44. u32 lpimr0; /* Low Power Interrupt Mask 0 */
  45. u32 lpimr1; /* Low Power Interrupt Mask 1 */
  46. };
  47. /* Enhanced SDRAM Controller (ESDRAMC) registers */
  48. struct esdramc_regs {
  49. u32 ctl0; /* control 0 */
  50. u32 cfg0; /* configuration 0 */
  51. u32 ctl1; /* control 1 */
  52. u32 cfg1; /* configuration 1 */
  53. u32 misc; /* miscellaneous */
  54. u32 pad[3];
  55. u32 cdly1; /* Delay Line 1 configuration debug */
  56. u32 cdly2; /* delay line 2 configuration debug */
  57. u32 cdly3; /* delay line 3 configuration debug */
  58. u32 cdly4; /* delay line 4 configuration debug */
  59. u32 cdly5; /* delay line 5 configuration debug */
  60. u32 cdlyl; /* delay line cycle length debug */
  61. };
  62. /* General Purpose Timer (GPT) registers */
  63. struct gpt_regs {
  64. u32 ctrl; /* control */
  65. u32 pre; /* prescaler */
  66. u32 stat; /* status */
  67. u32 intr; /* interrupt */
  68. u32 cmp[3]; /* output compare 1-3 */
  69. u32 capt[2]; /* input capture 1-2 */
  70. u32 counter; /* counter */
  71. };
  72. /* Watchdog Timer (WDOG) registers */
  73. struct wdog_regs {
  74. u16 wcr; /* Control */
  75. u16 wsr; /* Service */
  76. u16 wrsr; /* Reset Status */
  77. u16 wicr; /* Interrupt Control */
  78. u16 wmcr; /* Misc Control */
  79. };
  80. /* IIM control registers */
  81. struct iim_regs {
  82. u32 iim_stat;
  83. u32 iim_statm;
  84. u32 iim_err;
  85. u32 iim_emask;
  86. u32 iim_fctl;
  87. u32 iim_ua;
  88. u32 iim_la;
  89. u32 iim_sdat;
  90. u32 iim_prev;
  91. u32 iim_srev;
  92. u32 iim_prg_p;
  93. u32 iim_scs0;
  94. u32 iim_scs1;
  95. u32 iim_scs2;
  96. u32 iim_scs3;
  97. u32 res1[0x1f1];
  98. struct fuse_bank {
  99. u32 fuse_regs[0x20];
  100. u32 fuse_rsvd[0xe0];
  101. } bank[3];
  102. };
  103. struct fuse_bank0_regs {
  104. u32 fuse0_7[8];
  105. u32 uid[8];
  106. u32 fuse16_25[0xa];
  107. u32 mac_addr[6];
  108. };
  109. struct fuse_bank1_regs {
  110. u32 fuse0_21[0x16];
  111. u32 usr5;
  112. u32 fuse23_29[7];
  113. u32 usr6[2];
  114. };
  115. /* Multi-Layer AHB Crossbar Switch (MAX) registers */
  116. struct max_regs {
  117. u32 mpr0;
  118. u32 pad00[3];
  119. u32 sgpcr0;
  120. u32 pad01[59];
  121. u32 mpr1;
  122. u32 pad02[3];
  123. u32 sgpcr1;
  124. u32 pad03[59];
  125. u32 mpr2;
  126. u32 pad04[3];
  127. u32 sgpcr2;
  128. u32 pad05[59];
  129. u32 mpr3;
  130. u32 pad06[3];
  131. u32 sgpcr3;
  132. u32 pad07[59];
  133. u32 mpr4;
  134. u32 pad08[3];
  135. u32 sgpcr4;
  136. u32 pad09[251];
  137. u32 mgpcr0;
  138. u32 pad10[63];
  139. u32 mgpcr1;
  140. u32 pad11[63];
  141. u32 mgpcr2;
  142. u32 pad12[63];
  143. u32 mgpcr3;
  144. u32 pad13[63];
  145. u32 mgpcr4;
  146. };
  147. /* AHB <-> IP-Bus Interface (AIPS) */
  148. struct aips_regs {
  149. u32 mpr_0_7;
  150. u32 mpr_8_15;
  151. };
  152. /* LCD controller registers */
  153. struct lcdc_regs {
  154. u32 lssar; /* Screen Start Address */
  155. u32 lsr; /* Size */
  156. u32 lvpwr; /* Virtual Page Width */
  157. u32 lcpr; /* Cursor Position */
  158. u32 lcwhb; /* Cursor Width Height and Blink */
  159. u32 lccmr; /* Color Cursor Mapping */
  160. u32 lpcr; /* Panel Configuration */
  161. u32 lhcr; /* Horizontal Configuration */
  162. u32 lvcr; /* Vertical Configuration */
  163. u32 lpor; /* Panning Offset */
  164. u32 lscr; /* Sharp Configuration */
  165. u32 lpccr; /* PWM Contrast Control */
  166. u32 ldcr; /* DMA Control */
  167. u32 lrmcr; /* Refresh Mode Control */
  168. u32 licr; /* Interrupt Configuration */
  169. u32 lier; /* Interrupt Enable */
  170. u32 lisr; /* Interrupt Status */
  171. u32 res0[3];
  172. u32 lgwsar; /* Graphic Window Start Address */
  173. u32 lgwsr; /* Graphic Window Size */
  174. u32 lgwvpwr; /* Graphic Window Virtual Page Width Regist */
  175. u32 lgwpor; /* Graphic Window Panning Offset */
  176. u32 lgwpr; /* Graphic Window Position */
  177. u32 lgwcr; /* Graphic Window Control */
  178. u32 lgwdcr; /* Graphic Window DMA Control */
  179. u32 res1[5];
  180. u32 lauscr; /* AUS Mode Control */
  181. u32 lausccr; /* AUS mode Cursor Control */
  182. u32 res2[31 + 64*7];
  183. u32 bglut; /* Background Lookup Table */
  184. u32 gwlut; /* Graphic Window Lookup Table */
  185. };
  186. /* Wireless External Interface Module Registers */
  187. struct weim_regs {
  188. u32 cscr0u; /* Chip Select 0 Upper Register */
  189. u32 cscr0l; /* Chip Select 0 Lower Register */
  190. u32 cscr0a; /* Chip Select 0 Addition Register */
  191. u32 pad0;
  192. u32 cscr1u; /* Chip Select 1 Upper Register */
  193. u32 cscr1l; /* Chip Select 1 Lower Register */
  194. u32 cscr1a; /* Chip Select 1 Addition Register */
  195. u32 pad1;
  196. u32 cscr2u; /* Chip Select 2 Upper Register */
  197. u32 cscr2l; /* Chip Select 2 Lower Register */
  198. u32 cscr2a; /* Chip Select 2 Addition Register */
  199. u32 pad2;
  200. u32 cscr3u; /* Chip Select 3 Upper Register */
  201. u32 cscr3l; /* Chip Select 3 Lower Register */
  202. u32 cscr3a; /* Chip Select 3 Addition Register */
  203. u32 pad3;
  204. u32 cscr4u; /* Chip Select 4 Upper Register */
  205. u32 cscr4l; /* Chip Select 4 Lower Register */
  206. u32 cscr4a; /* Chip Select 4 Addition Register */
  207. u32 pad4;
  208. u32 cscr5u; /* Chip Select 5 Upper Register */
  209. u32 cscr5l; /* Chip Select 5 Lower Register */
  210. u32 cscr5a; /* Chip Select 5 Addition Register */
  211. u32 pad5;
  212. u32 wcr; /* WEIM Configuration Register */
  213. };
  214. /* Multi-Master Memory Interface */
  215. struct m3if_regs {
  216. u32 ctl; /* Control Register */
  217. u32 wcfg0; /* Watermark Configuration Register 0 */
  218. u32 wcfg1; /* Watermark Configuration Register1 */
  219. u32 wcfg2; /* Watermark Configuration Register2 */
  220. u32 wcfg3; /* Watermark Configuration Register 3 */
  221. u32 wcfg4; /* Watermark Configuration Register 4 */
  222. u32 wcfg5; /* Watermark Configuration Register 5 */
  223. u32 wcfg6; /* Watermark Configuration Register 6 */
  224. u32 wcfg7; /* Watermark Configuration Register 7 */
  225. u32 wcsr; /* Watermark Control and Status Register */
  226. u32 scfg0; /* Snooping Configuration Register 0 */
  227. u32 scfg1; /* Snooping Configuration Register 1 */
  228. u32 scfg2; /* Snooping Configuration Register 2 */
  229. u32 ssr0; /* Snooping Status Register 0 */
  230. u32 ssr1; /* Snooping Status Register 1 */
  231. u32 res0;
  232. u32 mlwe0; /* Master Lock WEIM CS0 Register */
  233. u32 mlwe1; /* Master Lock WEIM CS1 Register */
  234. u32 mlwe2; /* Master Lock WEIM CS2 Register */
  235. u32 mlwe3; /* Master Lock WEIM CS3 Register */
  236. u32 mlwe4; /* Master Lock WEIM CS4 Register */
  237. u32 mlwe5; /* Master Lock WEIM CS5 Register */
  238. };
  239. /* Pulse width modulation */
  240. struct pwm_regs {
  241. u32 cr; /* Control Register */
  242. u32 sr; /* Status Register */
  243. u32 ir; /* Interrupt Register */
  244. u32 sar; /* Sample Register */
  245. u32 pr; /* Period Register */
  246. u32 cnr; /* Counter Register */
  247. };
  248. /* Enhanced Periodic Interrupt Timer */
  249. struct epit_regs {
  250. u32 cr; /* Control register */
  251. u32 sr; /* Status register */
  252. u32 lr; /* Load register */
  253. u32 cmpr; /* Compare register */
  254. u32 cnr; /* Counter register */
  255. };
  256. #endif
  257. #define ARCH_MXC
  258. /* AIPS 1 */
  259. #define IMX_AIPS1_BASE (0x43F00000)
  260. #define IMX_MAX_BASE (0x43F04000)
  261. #define IMX_CLKCTL_BASE (0x43F08000)
  262. #define IMX_ETB_SLOT4_BASE (0x43F0C000)
  263. #define IMX_ETB_SLOT5_BASE (0x43F10000)
  264. #define IMX_ECT_CTIO_BASE (0x43F18000)
  265. #define I2C1_BASE_ADDR (0x43F80000)
  266. #define I2C3_BASE_ADDR (0x43F84000)
  267. #define IMX_CAN1_BASE (0x43F88000)
  268. #define IMX_CAN2_BASE (0x43F8C000)
  269. #define UART1_BASE (0x43F90000)
  270. #define UART2_BASE (0x43F94000)
  271. #define I2C2_BASE_ADDR (0x43F98000)
  272. #define IMX_OWIRE_BASE (0x43F9C000)
  273. #define IMX_CSPI1_BASE (0x43FA4000)
  274. #define IMX_KPP_BASE (0x43FA8000)
  275. #define IMX_IOPADMUX_BASE (0x43FAC000)
  276. #define IOMUXC_BASE_ADDR IMX_IOPADMUX_BASE
  277. #define IMX_IOPADCTL_BASE (0x43FAC22C)
  278. #define IMX_IOPADGRPCTL_BASE (0x43FAC418)
  279. #define IMX_IOPADINPUTSEL_BASE (0x43FAC460)
  280. #define IMX_AUDMUX_BASE (0x43FB0000)
  281. #define IMX_ECT_IP1_BASE (0x43FB8000)
  282. #define IMX_ECT_IP2_BASE (0x43FBC000)
  283. /* SPBA */
  284. #define IMX_SPBA_BASE (0x50000000)
  285. #define IMX_CSPI3_BASE (0x50004000)
  286. #define UART4_BASE (0x50008000)
  287. #define UART3_BASE (0x5000C000)
  288. #define IMX_CSPI2_BASE (0x50010000)
  289. #define IMX_SSI2_BASE (0x50014000)
  290. #define IMX_ESAI_BASE (0x50018000)
  291. #define IMX_ATA_DMA_BASE (0x50020000)
  292. #define IMX_SIM1_BASE (0x50024000)
  293. #define IMX_SIM2_BASE (0x50028000)
  294. #define UART5_BASE (0x5002C000)
  295. #define IMX_TSC_BASE (0x50030000)
  296. #define IMX_SSI1_BASE (0x50034000)
  297. #define IMX_FEC_BASE (0x50038000)
  298. #define IMX_SPBA_CTRL_BASE (0x5003C000)
  299. /* AIPS 2 */
  300. #define IMX_AIPS2_BASE (0x53F00000)
  301. #define IMX_CCM_BASE (0x53F80000)
  302. #define IMX_GPT4_BASE (0x53F84000)
  303. #define IMX_GPT3_BASE (0x53F88000)
  304. #define IMX_GPT2_BASE (0x53F8C000)
  305. #define IMX_GPT1_BASE (0x53F90000)
  306. #define IMX_EPIT1_BASE (0x53F94000)
  307. #define IMX_EPIT2_BASE (0x53F98000)
  308. #define IMX_GPIO4_BASE (0x53F9C000)
  309. #define IMX_PWM2_BASE (0x53FA0000)
  310. #define IMX_GPIO3_BASE (0x53FA4000)
  311. #define IMX_PWM3_BASE (0x53FA8000)
  312. #define IMX_SCC_BASE (0x53FAC000)
  313. #define IMX_SCM_BASE (0x53FAE000)
  314. #define IMX_SMN_BASE (0x53FAF000)
  315. #define IMX_RNGD_BASE (0x53FB0000)
  316. #define IMX_MMC_SDHC1_BASE (0x53FB4000)
  317. #define IMX_MMC_SDHC2_BASE (0x53FB8000)
  318. #define IMX_LCDC_BASE (0x53FBC000)
  319. #define IMX_SLCDC_BASE (0x53FC0000)
  320. #define IMX_PWM4_BASE (0x53FC8000)
  321. #define IMX_GPIO1_BASE (0x53FCC000)
  322. #define IMX_GPIO2_BASE (0x53FD0000)
  323. #define IMX_SDMA_BASE (0x53FD4000)
  324. #define IMX_WDT_BASE (0x53FDC000)
  325. #define WDOG1_BASE_ADDR IMX_WDT_BASE
  326. #define IMX_PWM1_BASE (0x53FE0000)
  327. #define IMX_RTIC_BASE (0x53FEC000)
  328. #define IMX_IIM_BASE (0x53FF0000)
  329. #define IIM_BASE_ADDR IMX_IIM_BASE
  330. #define IMX_USB_BASE (0x53FF4000)
  331. /*
  332. * This is in contradiction to the imx25 reference manual, which says that
  333. * port 1's registers start at 0x53FF4200. The correct base address for
  334. * port 1 is 0x53FF4400. The kernel uses 0x53FF4400 as well.
  335. */
  336. #define IMX_USB_PORT_OFFSET 0x400
  337. #define IMX_CSI_BASE (0x53FF8000)
  338. #define IMX_DRYICE_BASE (0x53FFC000)
  339. #define IMX_ARM926_ROMPATCH (0x60000000)
  340. #define IMX_ARM926_ASIC (0x68000000)
  341. /* 128K Internal Static RAM */
  342. #define IMX_RAM_BASE (0x78000000)
  343. #define IMX_RAM_SIZE (128 * 1024)
  344. /* SDRAM BANKS */
  345. #define IMX_SDRAM_BANK0_BASE (0x80000000)
  346. #define IMX_SDRAM_BANK1_BASE (0x90000000)
  347. #define IMX_WEIM_CS0 (0xA0000000)
  348. #define IMX_WEIM_CS1 (0xA8000000)
  349. #define IMX_WEIM_CS2 (0xB0000000)
  350. #define IMX_WEIM_CS3 (0xB2000000)
  351. #define IMX_WEIM_CS4 (0xB4000000)
  352. #define IMX_ESDRAMC_BASE (0xB8001000)
  353. #define IMX_WEIM_CTRL_BASE (0xB8002000)
  354. #define IMX_M3IF_CTRL_BASE (0xB8003000)
  355. #define IMX_EMI_CTRL_BASE (0xB8004000)
  356. /* NAND Flash Controller */
  357. #define IMX_NFC_BASE (0xBB000000)
  358. #define NFC_BASE_ADDR IMX_NFC_BASE
  359. /* CCM bitfields */
  360. #define CCM_PLL_MFI_SHIFT 10
  361. #define CCM_PLL_MFI_MASK 0xf
  362. #define CCM_PLL_MFN_SHIFT 0
  363. #define CCM_PLL_MFN_MASK 0x3ff
  364. #define CCM_PLL_MFD_SHIFT 16
  365. #define CCM_PLL_MFD_MASK 0x3ff
  366. #define CCM_PLL_PD_SHIFT 26
  367. #define CCM_PLL_PD_MASK 0xf
  368. #define CCM_CCTL_ARM_DIV_SHIFT 30
  369. #define CCM_CCTL_ARM_DIV_MASK 3
  370. #define CCM_CCTL_AHB_DIV_SHIFT 28
  371. #define CCM_CCTL_AHB_DIV_MASK 3
  372. #define CCM_CCTL_ARM_SRC (1 << 14)
  373. #define CCM_CGR1_GPT1 (1 << 19)
  374. #define CCM_PERCLK_REG(clk) (clk / 4)
  375. #define CCM_PERCLK_SHIFT(clk) (8 * (clk % 4))
  376. #define CCM_PERCLK_MASK 0x3f
  377. #define CCM_RCSR_NF_16BIT_SEL (1 << 14)
  378. #define CCM_RCSR_NF_PS(v) ((v >> 26) & 3)
  379. #define CCM_CRDR_BT_UART_SRC_SHIFT 29
  380. #define CCM_CRDR_BT_UART_SRC_MASK 7
  381. /* ESDRAM Controller register bitfields */
  382. #define ESDCTL_PRCT(x) (((x) & 0x3f) << 0)
  383. #define ESDCTL_BL (1 << 7)
  384. #define ESDCTL_FP (1 << 8)
  385. #define ESDCTL_PWDT(x) (((x) & 3) << 10)
  386. #define ESDCTL_SREFR(x) (((x) & 7) << 13)
  387. #define ESDCTL_DSIZ_16_UPPER (0 << 16)
  388. #define ESDCTL_DSIZ_16_LOWER (1 << 16)
  389. #define ESDCTL_DSIZ_32 (2 << 16)
  390. #define ESDCTL_COL8 (0 << 20)
  391. #define ESDCTL_COL9 (1 << 20)
  392. #define ESDCTL_COL10 (2 << 20)
  393. #define ESDCTL_ROW11 (0 << 24)
  394. #define ESDCTL_ROW12 (1 << 24)
  395. #define ESDCTL_ROW13 (2 << 24)
  396. #define ESDCTL_ROW14 (3 << 24)
  397. #define ESDCTL_ROW15 (4 << 24)
  398. #define ESDCTL_SP (1 << 27)
  399. #define ESDCTL_SMODE_NORMAL (0 << 28)
  400. #define ESDCTL_SMODE_PRECHARGE (1 << 28)
  401. #define ESDCTL_SMODE_AUTO_REF (2 << 28)
  402. #define ESDCTL_SMODE_LOAD_MODE (3 << 28)
  403. #define ESDCTL_SMODE_MAN_REF (4 << 28)
  404. #define ESDCTL_SDE (1 << 31)
  405. #define ESDCFG_TRC(x) (((x) & 0xf) << 0)
  406. #define ESDCFG_TRCD(x) (((x) & 0x7) << 4)
  407. #define ESDCFG_TCAS(x) (((x) & 0x3) << 8)
  408. #define ESDCFG_TRRD(x) (((x) & 0x3) << 10)
  409. #define ESDCFG_TRAS(x) (((x) & 0x7) << 12)
  410. #define ESDCFG_TWR (1 << 15)
  411. #define ESDCFG_TMRD(x) (((x) & 0x3) << 16)
  412. #define ESDCFG_TRP(x) (((x) & 0x3) << 18)
  413. #define ESDCFG_TWTR (1 << 20)
  414. #define ESDCFG_TXP(x) (((x) & 0x3) << 21)
  415. #define ESDMISC_RST (1 << 1)
  416. #define ESDMISC_MDDREN (1 << 2)
  417. #define ESDMISC_MDDR_DL_RST (1 << 3)
  418. #define ESDMISC_MDDR_MDIS (1 << 4)
  419. #define ESDMISC_LHD (1 << 5)
  420. #define ESDMISC_MA10_SHARE (1 << 6)
  421. #define ESDMISC_SDRAM_RDY (1 << 31)
  422. /* GPT bits */
  423. #define GPT_CTRL_SWR (1 << 15) /* Software reset */
  424. #define GPT_CTRL_FRR (1 << 9) /* Freerun / restart */
  425. #define GPT_CTRL_CLKSOURCE_32 (4 << 6) /* Clock source */
  426. #define GPT_CTRL_TEN 1 /* Timer enable */
  427. /* WDOG enable */
  428. #define WCR_WDE 0x04
  429. #define WSR_UNLOCK1 0x5555
  430. #define WSR_UNLOCK2 0xAAAA
  431. /* MAX bits */
  432. #define MAX_MGPCR_AULB(x) (((x) & 0x7) << 0)
  433. /* M3IF bits */
  434. #define M3IF_CTL_MRRP(x) (((x) & 0xff) << 0)
  435. /* WEIM bits */
  436. /* 13 fields of the upper CS control register */
  437. #define WEIM_CSCR_U(sp, wp, bcd, bcs, psz, pme, sync, dol, \
  438. cnc, wsc, ew, wws, edc) \
  439. ((sp) << 31 | (wp) << 30 | (bcd) << 28 | (bcs) << 24 | \
  440. (psz) << 22 | (pme) << 21 | (sync) << 20 | (dol) << 16 | \
  441. (cnc) << 14 | (wsc) << 8 | (ew) << 7 | (wws) << 4 | (edc) << 0)
  442. /* 12 fields of the lower CS control register */
  443. #define WEIM_CSCR_L(oea, oen, ebwa, ebwn, \
  444. csa, ebc, dsz, csn, psr, cre, wrap, csen) \
  445. ((oea) << 28 | (oen) << 24 | (ebwa) << 20 | (ebwn) << 16 |\
  446. (csa) << 12 | (ebc) << 11 | (dsz) << 8 | (csn) << 4 |\
  447. (psr) << 3 | (cre) << 2 | (wrap) << 1 | (csen) << 0)
  448. /* 14 fields of the additional CS control register */
  449. #define WEIM_CSCR_A(ebra, ebrn, rwa, rwn, mum, lah, lbn, lba, dww, dct, \
  450. wwu, age, cnc2, fce) \
  451. ((ebra) << 28 | (ebrn) << 24 | (rwa) << 20 | (rwn) << 16 |\
  452. (mum) << 15 | (lah) << 13 | (lbn) << 10 | (lba) << 8 |\
  453. (dww) << 6 | (dct) << 4 | (wwu) << 3 |\
  454. (age) << 2 | (cnc2) << 1 | (fce) << 0)
  455. /* Names used in GPIO driver */
  456. #define GPIO1_BASE_ADDR IMX_GPIO1_BASE
  457. #define GPIO2_BASE_ADDR IMX_GPIO2_BASE
  458. #define GPIO3_BASE_ADDR IMX_GPIO3_BASE
  459. #define GPIO4_BASE_ADDR IMX_GPIO4_BASE
  460. /*
  461. * CSPI register definitions
  462. */
  463. #define MXC_SPI_BASE_ADDRESSES \
  464. IMX_CSPI1_BASE, \
  465. IMX_CSPI2_BASE, \
  466. IMX_CSPI3_BASE
  467. #endif /* _IMX_REGS_H */