Selaa lähdekoodia

cleanup: Fix typos and misspellings in various files.

Recieve/Receive
recieve/receive
Interupt/Interrupt
interupt/interrupt
Addres/Address
addres/address

Signed-off-by: Mike Williams <mike@mikebwilliams.com>
Mike Williams 13 vuotta sitten
vanhempi
commit
1626308797
48 muutettua tiedostoa jossa 57 lisäystä ja 57 poistoa
  1. 2 2
      arch/arm/cpu/arm720t/lpc2292/mmc_hw.c
  2. 1 1
      arch/arm/cpu/arm720t/start.S
  3. 1 1
      arch/arm/cpu/arm920t/at91/timer.c
  4. 2 2
      arch/arm/cpu/arm920t/start.S
  5. 1 1
      arch/arm/cpu/ixp/npe/IxQMgrDispatcher.c
  6. 1 1
      arch/arm/cpu/ixp/npe/include/IxEthAcc_p.h
  7. 1 1
      arch/arm/cpu/ixp/npe/include/IxNpeA.h
  8. 1 1
      arch/arm/cpu/ixp/npe/include/IxQMgr.h
  9. 1 1
      arch/arm/cpu/ixp/npe/include/IxQueueAssignments.h
  10. 1 1
      arch/arm/cpu/lh7a40x/start.S
  11. 1 1
      arch/arm/cpu/sa1100/start.S
  12. 1 1
      arch/m68k/include/asm/fec.h
  13. 1 1
      arch/powerpc/include/asm/cpm_8260.h
  14. 1 1
      arch/powerpc/include/asm/cpm_85xx.h
  15. 2 2
      arch/powerpc/include/asm/ppc440ep_gr.h
  16. 2 2
      arch/powerpc/include/asm/ppc440epx_grx.h
  17. 2 2
      arch/powerpc/include/asm/ppc440gx.h
  18. 2 2
      arch/powerpc/include/asm/ppc440sp.h
  19. 2 2
      arch/powerpc/include/asm/ppc440spe.h
  20. 1 1
      arch/sparc/cpu/leon3/usb_uhci.c
  21. 1 1
      arch/x86/cpu/start.S
  22. 1 1
      arch/x86/include/asm/interrupt.h
  23. 1 1
      board/Marvell/common/bootseq.txt
  24. 1 1
      board/Marvell/common/i2c.c
  25. 1 1
      board/Marvell/common/ns16550.h
  26. 1 1
      board/Marvell/include/mv_gen_reg.h
  27. 1 1
      board/bmw/ns16550.h
  28. 1 1
      board/evb64260/bootseq.txt
  29. 1 1
      board/evb64260/i2c.c
  30. 1 1
      board/freescale/mpc8266ads/mpc8266ads.c
  31. 1 1
      board/intercontrol/digsy_mtc/eeprom.h
  32. 1 1
      board/mpl/common/usb_uhci.c
  33. 1 1
      common/cmd_flash.c
  34. 1 1
      common/xyzModem.c
  35. 2 2
      doc/README.m68k
  36. 1 1
      doc/README.qemu_mips
  37. 1 1
      drivers/net/4xx_enet.c
  38. 1 1
      drivers/net/greth.c
  39. 1 1
      drivers/net/natsemi.c
  40. 1 1
      drivers/net/ns8382x.c
  41. 1 1
      drivers/pci/fsl_pci_init.c
  42. 1 1
      drivers/rtc/mpc5xxx.c
  43. 1 1
      include/commproc.h
  44. 1 1
      include/configs/NETTA.h
  45. 1 1
      include/configs/TQM834x.h
  46. 1 1
      include/galileo/gt64260R.h
  47. 2 2
      include/mpc5xxx_sdma.h
  48. 1 1
      include/mpc824x.h

+ 2 - 2
arch/arm/cpu/arm720t/lpc2292/mmc_hw.c

@@ -148,7 +148,7 @@ unsigned char mmc_read_sector (unsigned long addr,unsigned char *Buffer)
 	/* Command 16 to read aBlocks from the MMC/SD - caed */
 	/* Command 16 to read aBlocks from the MMC/SD - caed */
 	unsigned char CMD[] = {0x51,0x00,0x00,0x00,0x00,0xFF};
 	unsigned char CMD[] = {0x51,0x00,0x00,0x00,0x00,0xFF};
 
 
-	/* The addres on the MMC/SD-card is in bytes,
+	/* The address on the MMC/SD-card is in bytes,
 	addr is transformed from blocks to bytes and the result is
 	addr is transformed from blocks to bytes and the result is
 	placed into the command */
 	placed into the command */
 
 
@@ -173,7 +173,7 @@ unsigned char mmc_write_sector (unsigned long addr,unsigned char *Buffer)
 	/* Command 24 to write a block to the MMC/SD - card */
 	/* Command 24 to write a block to the MMC/SD - card */
 	unsigned char CMD[] = {0x58, 0x00, 0x00, 0x00, 0x00, 0xFF};
 	unsigned char CMD[] = {0x58, 0x00, 0x00, 0x00, 0x00, 0xFF};
 
 
-	/* The addres on the MMC/SD-card is in bytes,
+	/* The address on the MMC/SD-card is in bytes,
 	addr is transformed from blocks to bytes and the result is
 	addr is transformed from blocks to bytes and the result is
 	placed into the command */
 	placed into the command */
 
 

+ 1 - 1
arch/arm/cpu/arm720t/start.S

@@ -274,7 +274,7 @@ _dynsym_start_ofs:
 
 
 #if defined(CONFIG_IMPA7) || defined(CONFIG_EP7312) || defined(CONFIG_ARMADILLO)
 #if defined(CONFIG_IMPA7) || defined(CONFIG_EP7312) || defined(CONFIG_ARMADILLO)
 
 
-/* Interupt-Controller base addresses */
+/* Interrupt-Controller base addresses */
 INTMR1:		.word	0x80000280 @ 32 bit size
 INTMR1:		.word	0x80000280 @ 32 bit size
 INTMR2:		.word	0x80001280 @ 16 bit size
 INTMR2:		.word	0x80001280 @ 16 bit size
 INTMR3:		.word	0x80002280 @  8 bit size
 INTMR3:		.word	0x80002280 @  8 bit size

+ 1 - 1
arch/arm/cpu/arm920t/at91/timer.c

@@ -59,7 +59,7 @@ int timer_init(void)
 	when the value in TC_RC is reached */
 	when the value in TC_RC is reached */
 	writel(AT91_TC_CMR_TCCLKS_CLOCK1 | AT91_TC_CMR_CPCTRG, &tc->tc[0].cmr);
 	writel(AT91_TC_CMR_TCCLKS_CLOCK1 | AT91_TC_CMR_CPCTRG, &tc->tc[0].cmr);
 
 
-	writel(0xFFFFFFFF, &tc->tc[0].idr); /* disable interupts */
+	writel(0xFFFFFFFF, &tc->tc[0].idr); /* disable interrupts */
 	writel(TIMER_LOAD_VAL, &tc->tc[0].rc);
 	writel(TIMER_LOAD_VAL, &tc->tc[0].rc);
 
 
 	writel(AT91_TC_CCR_SWTRG | AT91_TC_CCR_CLKEN, &tc->tc[0].ccr);
 	writel(AT91_TC_CCR_SWTRG | AT91_TC_CCR_CLKEN, &tc->tc[0].ccr);

+ 2 - 2
arch/arm/cpu/arm920t/start.S

@@ -142,11 +142,11 @@ copyex:
 
 
 # if defined(CONFIG_S3C2400)
 # if defined(CONFIG_S3C2400)
 #  define pWTCON	0x15300000
 #  define pWTCON	0x15300000
-#  define INTMSK	0x14400008	/* Interupt-Controller base addresses */
+#  define INTMSK	0x14400008	/* Interrupt-Controller base addresses */
 #  define CLKDIVN	0x14800014	/* clock divisor register */
 #  define CLKDIVN	0x14800014	/* clock divisor register */
 #else
 #else
 #  define pWTCON	0x53000000
 #  define pWTCON	0x53000000
-#  define INTMSK	0x4A000008	/* Interupt-Controller base addresses */
+#  define INTMSK	0x4A000008	/* Interrupt-Controller base addresses */
 #  define INTSUBMSK	0x4A00001C
 #  define INTSUBMSK	0x4A00001C
 #  define CLKDIVN	0x4C000014	/* clock divisor register */
 #  define CLKDIVN	0x4C000014	/* clock divisor register */
 # endif
 # endif

+ 1 - 1
arch/arm/cpu/ixp/npe/IxQMgrDispatcher.c

@@ -386,7 +386,7 @@ ixQMgrNotificationEnable (IxQMgrQId qId,
 				     &dispatchQInfo[qId].statusMask);
 				     &dispatchQInfo[qId].statusMask);
 
 
 
 
-    /* Set the interupt source is this queue is in the range 0-31 */
+    /* Set the interrupt source is this queue is in the range 0-31 */
     if (qId < IX_QMGR_MIN_QUEUPP_QID)
     if (qId < IX_QMGR_MIN_QUEUPP_QID)
     {
     {
 	ixQMgrAqmIfIntSrcSelWrite (qId, srcSel);
 	ixQMgrAqmIfIntSrcSelWrite (qId, srcSel);

+ 1 - 1
arch/arm/cpu/ixp/npe/include/IxEthAcc_p.h

@@ -279,7 +279,7 @@ typedef struct
     BOOL               portInitialized;
     BOOL               portInitialized;
     UINT32 npeId; /**< NpeId for this port */
     UINT32 npeId; /**< NpeId for this port */
     IxEthAccTxDataInfo ixEthAccTxData; /**< Transmit data control structures */
     IxEthAccTxDataInfo ixEthAccTxData; /**< Transmit data control structures */
-    IxEthAccRxDataInfo ixEthAccRxData; /**< Recieve data control structures */
+    IxEthAccRxDataInfo ixEthAccRxData; /**< Receive data control structures */
 } IxEthAccPortDataInfo; 
 } IxEthAccPortDataInfo; 
 
 
 extern IxEthAccPortDataInfo  ixEthAccPortData[];
 extern IxEthAccPortDataInfo  ixEthAccPortData[];

+ 1 - 1
arch/arm/cpu/ixp/npe/include/IxNpeA.h

@@ -717,7 +717,7 @@ typedef struct
  */
  */
 typedef struct
 typedef struct
 {
 {
-    UINT32  rxBitField;			/**< Recieved bit field */
+    UINT32  rxBitField;			/**< Received bit field */
     UINT32  atmCellHeader;		/**< ATM Cell Header */
     UINT32  atmCellHeader;		/**< ATM Cell Header */
     UINT32  rsvdWord0;                  /**< Reserved field */
     UINT32  rsvdWord0;                  /**< Reserved field */
     UINT16  currMbufLen;		/**< Mbuf Length */
     UINT16  currMbufLen;		/**< Mbuf Length */

+ 1 - 1
arch/arm/cpu/ixp/npe/include/IxQMgr.h

@@ -570,7 +570,7 @@ typedef enum
  * @brief Queue interrupt source select.
  * @brief Queue interrupt source select.
  *
  *
  * This enum defines the different source conditions on a queue that result in
  * This enum defines the different source conditions on a queue that result in
- * an interupt being fired by the AQM. Interrupt source is configurable for
+ * an interrupt being fired by the AQM. Interrupt source is configurable for
  * queues 0-31 only. The interrupt source for queues 32-63 is hardwired to the
  * queues 0-31 only. The interrupt source for queues 32-63 is hardwired to the
  * NE(Nearly Empty) status flag.
  * NE(Nearly Empty) status flag.
  *
  *

+ 1 - 1
arch/arm/cpu/ixp/npe/include/IxQueueAssignments.h

@@ -404,7 +404,7 @@
 *
 *
 * @def IX_ETH_ACC_RX_FRAME_ETH_Q 
 * @def IX_ETH_ACC_RX_FRAME_ETH_Q 
 *
 *
-* @brief  Eth0/Eth1 NPE Frame Recieve Q.
+* @brief  Eth0/Eth1 NPE Frame Receive Q.
 *
 *
 * @note THIS IS NOT USED - the Rx queues are read from EthDB QoS configuration
 * @note THIS IS NOT USED - the Rx queues are read from EthDB QoS configuration
 * 
 * 

+ 1 - 1
arch/arm/cpu/lh7a40x/start.S

@@ -124,7 +124,7 @@ reset:
 	msr	cpsr,r0
 	msr	cpsr,r0
 
 
 #define pWDTCTL		0x80001400  /* Watchdog Timer control register */
 #define pWDTCTL		0x80001400  /* Watchdog Timer control register */
-#define pINTENC		0x8000050C  /* Interupt-Controller enable clear register */
+#define pINTENC		0x8000050C  /* Interrupt-Controller enable clear register */
 #define pCLKSET		0x80000420  /* clock divisor register */
 #define pCLKSET		0x80000420  /* clock divisor register */
 
 
 	/* disable watchdog, set watchdog control register to
 	/* disable watchdog, set watchdog control register to

+ 1 - 1
arch/arm/cpu/sa1100/start.S

@@ -263,7 +263,7 @@ _dynsym_start_ofs:
  */
  */
 
 
 
 
-/* Interupt-Controller base address */
+/* Interrupt-Controller base address */
 IC_BASE:	.word	0x90050000
 IC_BASE:	.word	0x90050000
 #define ICMR	0x04
 #define ICMR	0x04
 
 

+ 1 - 1
arch/m68k/include/asm/fec.h

@@ -39,7 +39,7 @@ typedef struct cpm_buf_desc {
 	uint cbd_bufaddr;	/* Buffer address in host memory */
 	uint cbd_bufaddr;	/* Buffer address in host memory */
 } cbd_t;
 } cbd_t;
 
 
-#define BD_SC_EMPTY		((ushort)0x8000)	/* Recieve is empty */
+#define BD_SC_EMPTY		((ushort)0x8000)	/* Receive is empty */
 #define BD_SC_READY		((ushort)0x8000)	/* Transmit is ready */
 #define BD_SC_READY		((ushort)0x8000)	/* Transmit is ready */
 #define BD_SC_WRAP		((ushort)0x2000)	/* Last buffer descriptor */
 #define BD_SC_WRAP		((ushort)0x2000)	/* Last buffer descriptor */
 #define BD_SC_INTRPT		((ushort)0x1000)	/* Interrupt on change */
 #define BD_SC_INTRPT		((ushort)0x1000)	/* Interrupt on change */

+ 1 - 1
arch/powerpc/include/asm/cpm_8260.h

@@ -117,7 +117,7 @@ typedef struct cpm_buf_desc {
 	uint	cbd_bufaddr;	/* Buffer address in host memory */
 	uint	cbd_bufaddr;	/* Buffer address in host memory */
 } cbd_t;
 } cbd_t;
 
 
-#define BD_SC_EMPTY	((ushort)0x8000)	/* Recieve is empty */
+#define BD_SC_EMPTY	((ushort)0x8000)	/* Receive is empty */
 #define BD_SC_READY	((ushort)0x8000)	/* Transmit is ready */
 #define BD_SC_READY	((ushort)0x8000)	/* Transmit is ready */
 #define BD_SC_WRAP	((ushort)0x2000)	/* Last buffer descriptor */
 #define BD_SC_WRAP	((ushort)0x2000)	/* Last buffer descriptor */
 #define BD_SC_INTRPT	((ushort)0x1000)	/* Interrupt on change */
 #define BD_SC_INTRPT	((ushort)0x1000)	/* Interrupt on change */

+ 1 - 1
arch/powerpc/include/asm/cpm_85xx.h

@@ -110,7 +110,7 @@ typedef struct cpm_buf_desc {
 	uint	cbd_bufaddr;	/* Buffer address in host memory */
 	uint	cbd_bufaddr;	/* Buffer address in host memory */
 } cbd_t;
 } cbd_t;
 
 
-#define BD_SC_EMPTY	((ushort)0x8000)	/* Recieve is empty */
+#define BD_SC_EMPTY	((ushort)0x8000)	/* Receive is empty */
 #define BD_SC_READY	((ushort)0x8000)	/* Transmit is ready */
 #define BD_SC_READY	((ushort)0x8000)	/* Transmit is ready */
 #define BD_SC_WRAP	((ushort)0x2000)	/* Last buffer descriptor */
 #define BD_SC_WRAP	((ushort)0x2000)	/* Last buffer descriptor */
 #define BD_SC_INTRPT	((ushort)0x1000)	/* Interrupt on change */
 #define BD_SC_INTRPT	((ushort)0x1000)	/* Interrupt on change */

+ 2 - 2
arch/powerpc/include/asm/ppc440ep_gr.h

@@ -182,7 +182,7 @@
 #define PLLD_LFBDV_MASK		0x0000003f  /* PLL Local Feedback Divisor */
 #define PLLD_LFBDV_MASK		0x0000003f  /* PLL Local Feedback Divisor */
 
 
 #define OPBDDV_MASK		0x03000000  /* OPB Clock Divisor Register */
 #define OPBDDV_MASK		0x03000000  /* OPB Clock Divisor Register */
-#define PERDV_MASK		0x07000000  /* Periferal Clock Divisor */
+#define PERDV_MASK		0x07000000  /* Peripheral Clock Divisor */
 #define PRADV_MASK		0x07000000  /* Primary Divisor A */
 #define PRADV_MASK		0x07000000  /* Primary Divisor A */
 #define PRBDV_MASK		0x07000000  /* Primary Divisor B */
 #define PRBDV_MASK		0x07000000  /* Primary Divisor B */
 #define SPCID_MASK		0x03000000  /* Sync PCI Divisor  */
 #define SPCID_MASK		0x03000000  /* Sync PCI Divisor  */
@@ -192,7 +192,7 @@
 #define PLLSYS1_PERCLK_DIV_MASK 0x03000000	/* Peripheral Clk Divisor */
 #define PLLSYS1_PERCLK_DIV_MASK 0x03000000	/* Peripheral Clk Divisor */
 #define PLLSYS1_MAL_DIV_MASK	0x00c00000	/* MAL Clk Divisor */
 #define PLLSYS1_MAL_DIV_MASK	0x00c00000	/* MAL Clk Divisor */
 #define PLLSYS1_RW_MASK		0x00300000	/* ROM width */
 #define PLLSYS1_RW_MASK		0x00300000	/* ROM width */
-#define PLLSYS1_EAR_MASK	0x00080000	/* ERAP Addres reset vector */
+#define PLLSYS1_EAR_MASK	0x00080000	/* ERAP Address reset vector */
 #define PLLSYS1_PAE_MASK	0x00040000	/* PCI arbitor enable */
 #define PLLSYS1_PAE_MASK	0x00040000	/* PCI arbitor enable */
 #define PLLSYS1_PCHE_MASK	0x00020000	/* PCI host config enable */
 #define PLLSYS1_PCHE_MASK	0x00020000	/* PCI host config enable */
 #define PLLSYS1_PISE_MASK	0x00010000	/* PCI init seq. enable */
 #define PLLSYS1_PISE_MASK	0x00010000	/* PCI init seq. enable */

+ 2 - 2
arch/powerpc/include/asm/ppc440epx_grx.h

@@ -398,7 +398,7 @@
 #define PLLD_LFBDV_MASK		0x0000003f  /* PLL Local Feedback Divisor */
 #define PLLD_LFBDV_MASK		0x0000003f  /* PLL Local Feedback Divisor */
 
 
 #define OPBDDV_MASK		0x03000000  /* OPB Clock Divisor Register */
 #define OPBDDV_MASK		0x03000000  /* OPB Clock Divisor Register */
-#define PERDV_MASK		0x07000000  /* Periferal Clock Divisor */
+#define PERDV_MASK		0x07000000  /* Peripheral Clock Divisor */
 #define PRADV_MASK		0x07000000  /* Primary Divisor A */
 #define PRADV_MASK		0x07000000  /* Primary Divisor A */
 #define PRBDV_MASK		0x07000000  /* Primary Divisor B */
 #define PRBDV_MASK		0x07000000  /* Primary Divisor B */
 #define SPCID_MASK		0x03000000  /* Sync PCI Divisor  */
 #define SPCID_MASK		0x03000000  /* Sync PCI Divisor  */
@@ -408,7 +408,7 @@
 #define PLLSYS1_PERCLK_DIV_MASK 0x03000000	/* Peripheral Clk Divisor */
 #define PLLSYS1_PERCLK_DIV_MASK 0x03000000	/* Peripheral Clk Divisor */
 #define PLLSYS1_MAL_DIV_MASK	0x00c00000	/* MAL Clk Divisor */
 #define PLLSYS1_MAL_DIV_MASK	0x00c00000	/* MAL Clk Divisor */
 #define PLLSYS1_RW_MASK		0x00300000	/* ROM width */
 #define PLLSYS1_RW_MASK		0x00300000	/* ROM width */
-#define PLLSYS1_EAR_MASK	0x00080000	/* ERAP Addres reset vector */
+#define PLLSYS1_EAR_MASK	0x00080000	/* ERAP Address reset vector */
 #define PLLSYS1_PAE_MASK	0x00040000	/* PCI arbitor enable */
 #define PLLSYS1_PAE_MASK	0x00040000	/* PCI arbitor enable */
 #define PLLSYS1_PCHE_MASK	0x00020000	/* PCI host config enable */
 #define PLLSYS1_PCHE_MASK	0x00020000	/* PCI host config enable */
 #define PLLSYS1_PISE_MASK	0x00010000	/* PCI init seq. enable */
 #define PLLSYS1_PISE_MASK	0x00010000	/* PCI init seq. enable */

+ 2 - 2
arch/powerpc/include/asm/ppc440gx.h

@@ -71,7 +71,7 @@
 #define PLLD_LFBDV_MASK		0x0000003f  /* PLL Local Feedback Divisor */
 #define PLLD_LFBDV_MASK		0x0000003f  /* PLL Local Feedback Divisor */
 
 
 #define OPBDDV_MASK		0x03000000  /* OPB Clock Divisor Register */
 #define OPBDDV_MASK		0x03000000  /* OPB Clock Divisor Register */
-#define PERDV_MASK		0x07000000  /* Periferal Clock Divisor */
+#define PERDV_MASK		0x07000000  /* Peripheral Clock Divisor */
 #define PRADV_MASK		0x07000000  /* Primary Divisor A */
 #define PRADV_MASK		0x07000000  /* Primary Divisor A */
 #define PRBDV_MASK		0x07000000  /* Primary Divisor B */
 #define PRBDV_MASK		0x07000000  /* Primary Divisor B */
 #define SPCID_MASK		0x03000000  /* Sync PCI Divisor  */
 #define SPCID_MASK		0x03000000  /* Sync PCI Divisor  */
@@ -81,7 +81,7 @@
 #define PLLSYS1_PERCLK_DIV_MASK 0x03000000	/* Peripheral Clk Divisor */
 #define PLLSYS1_PERCLK_DIV_MASK 0x03000000	/* Peripheral Clk Divisor */
 #define PLLSYS1_MAL_DIV_MASK	0x00c00000	/* MAL Clk Divisor */
 #define PLLSYS1_MAL_DIV_MASK	0x00c00000	/* MAL Clk Divisor */
 #define PLLSYS1_RW_MASK		0x00300000	/* ROM width */
 #define PLLSYS1_RW_MASK		0x00300000	/* ROM width */
-#define PLLSYS1_EAR_MASK	0x00080000	/* ERAP Addres reset vector */
+#define PLLSYS1_EAR_MASK	0x00080000	/* ERAP Address reset vector */
 #define PLLSYS1_PAE_MASK	0x00040000	/* PCI arbitor enable */
 #define PLLSYS1_PAE_MASK	0x00040000	/* PCI arbitor enable */
 #define PLLSYS1_PCHE_MASK	0x00020000	/* PCI host config enable */
 #define PLLSYS1_PCHE_MASK	0x00020000	/* PCI host config enable */
 #define PLLSYS1_PISE_MASK	0x00010000	/* PCI init seq. enable */
 #define PLLSYS1_PISE_MASK	0x00010000	/* PCI init seq. enable */

+ 2 - 2
arch/powerpc/include/asm/ppc440sp.h

@@ -67,7 +67,7 @@
 #define PLLD_LFBDV_MASK		0x0000003f  /* PLL Local Feedback Divisor */
 #define PLLD_LFBDV_MASK		0x0000003f  /* PLL Local Feedback Divisor */
 
 
 #define OPBDDV_MASK		0x03000000  /* OPB Clock Divisor Register */
 #define OPBDDV_MASK		0x03000000  /* OPB Clock Divisor Register */
-#define PERDV_MASK		0x07000000  /* Periferal Clock Divisor */
+#define PERDV_MASK		0x07000000  /* Peripheral Clock Divisor */
 #define PRADV_MASK		0x07000000  /* Primary Divisor A */
 #define PRADV_MASK		0x07000000  /* Primary Divisor A */
 #define PRBDV_MASK		0x07000000  /* Primary Divisor B */
 #define PRBDV_MASK		0x07000000  /* Primary Divisor B */
 #define SPCID_MASK		0x03000000  /* Sync PCI Divisor  */
 #define SPCID_MASK		0x03000000  /* Sync PCI Divisor  */
@@ -77,7 +77,7 @@
 #define PLLSYS1_PERCLK_DIV_MASK 0x03000000	/* Peripheral Clk Divisor */
 #define PLLSYS1_PERCLK_DIV_MASK 0x03000000	/* Peripheral Clk Divisor */
 #define PLLSYS1_MAL_DIV_MASK	0x00c00000	/* MAL Clk Divisor */
 #define PLLSYS1_MAL_DIV_MASK	0x00c00000	/* MAL Clk Divisor */
 #define PLLSYS1_RW_MASK		0x00300000	/* ROM width */
 #define PLLSYS1_RW_MASK		0x00300000	/* ROM width */
-#define PLLSYS1_EAR_MASK	0x00080000	/* ERAP Addres reset vector */
+#define PLLSYS1_EAR_MASK	0x00080000	/* ERAP Address reset vector */
 #define PLLSYS1_PAE_MASK	0x00040000	/* PCI arbitor enable */
 #define PLLSYS1_PAE_MASK	0x00040000	/* PCI arbitor enable */
 #define PLLSYS1_PCHE_MASK	0x00020000	/* PCI host config enable */
 #define PLLSYS1_PCHE_MASK	0x00020000	/* PCI host config enable */
 #define PLLSYS1_PISE_MASK	0x00010000	/* PCI init seq. enable */
 #define PLLSYS1_PISE_MASK	0x00010000	/* PCI init seq. enable */

+ 2 - 2
arch/powerpc/include/asm/ppc440spe.h

@@ -83,7 +83,7 @@
 #define PLLD_LFBDV_MASK		0x0000003f  /* PLL Local Feedback Divisor */
 #define PLLD_LFBDV_MASK		0x0000003f  /* PLL Local Feedback Divisor */
 
 
 #define OPBDDV_MASK		0x03000000  /* OPB Clock Divisor Register */
 #define OPBDDV_MASK		0x03000000  /* OPB Clock Divisor Register */
-#define PERDV_MASK		0x07000000  /* Periferal Clock Divisor */
+#define PERDV_MASK		0x07000000  /* Peripheral Clock Divisor */
 #define PRADV_MASK		0x07000000  /* Primary Divisor A */
 #define PRADV_MASK		0x07000000  /* Primary Divisor A */
 #define PRBDV_MASK		0x07000000  /* Primary Divisor B */
 #define PRBDV_MASK		0x07000000  /* Primary Divisor B */
 #define SPCID_MASK		0x03000000  /* Sync PCI Divisor  */
 #define SPCID_MASK		0x03000000  /* Sync PCI Divisor  */
@@ -93,7 +93,7 @@
 #define PLLSYS1_PERCLK_DIV_MASK 0x03000000	/* Peripheral Clk Divisor */
 #define PLLSYS1_PERCLK_DIV_MASK 0x03000000	/* Peripheral Clk Divisor */
 #define PLLSYS1_MAL_DIV_MASK	0x00c00000	/* MAL Clk Divisor */
 #define PLLSYS1_MAL_DIV_MASK	0x00c00000	/* MAL Clk Divisor */
 #define PLLSYS1_RW_MASK		0x00300000	/* ROM width */
 #define PLLSYS1_RW_MASK		0x00300000	/* ROM width */
-#define PLLSYS1_EAR_MASK	0x00080000	/* ERAP Addres reset vector */
+#define PLLSYS1_EAR_MASK	0x00080000	/* ERAP Address reset vector */
 #define PLLSYS1_PAE_MASK	0x00040000	/* PCI arbitor enable */
 #define PLLSYS1_PAE_MASK	0x00040000	/* PCI arbitor enable */
 #define PLLSYS1_PCHE_MASK	0x00020000	/* PCI host config enable */
 #define PLLSYS1_PCHE_MASK	0x00020000	/* PCI host config enable */
 #define PLLSYS1_PISE_MASK	0x00010000	/* PCI init seq. enable */
 #define PLLSYS1_PISE_MASK	0x00010000	/* PCI init seq. enable */

+ 1 - 1
arch/sparc/cpu/leon3/usb_uhci.c

@@ -70,7 +70,7 @@
  *
  *
  * Interrupt Transfers.
  * Interrupt Transfers.
  * --------------------
  * --------------------
- * For Interupt transfers USB_MAX_TEMP_INT_TD Transfer descriptor are available. They
+ * For Interrupt transfers USB_MAX_TEMP_INT_TD Transfer descriptor are available. They
  * will be inserted after the appropriate (depending the interval setting) skeleton TD.
  * will be inserted after the appropriate (depending the interval setting) skeleton TD.
  * If an interrupt has been detected the dev->irqhandler is called. The status and number
  * If an interrupt has been detected the dev->irqhandler is called. The status and number
  * of transfered bytes is stored in dev->irq_status resp. dev->irq_act_len. If the
  * of transfered bytes is stored in dev->irq_status resp. dev->irq_act_len. If the

+ 1 - 1
arch/x86/cpu/start.S

@@ -66,7 +66,7 @@ _start:
 	movw	%ax, %es
 	movw	%ax, %es
 	movw	%ax, %ss
 	movw	%ax, %ss
 
 
-	/* Clear the interupt vectors */
+	/* Clear the interrupt vectors */
 	lidt	blank_idt_ptr
 	lidt	blank_idt_ptr
 
 
 	/* Early platform init (setup gpio, etc ) */
 	/* Early platform init (setup gpio, etc ) */

+ 1 - 1
arch/x86/include/asm/interrupt.h

@@ -32,7 +32,7 @@
 /* arch/x86/cpu/interrupts.c */
 /* arch/x86/cpu/interrupts.c */
 void set_vector(u8 intnum, void *routine);
 void set_vector(u8 intnum, void *routine);
 
 
-/* arch/x86/lib/interupts.c */
+/* arch/x86/lib/interrupts.c */
 void disable_irq(int irq);
 void disable_irq(int irq);
 void enable_irq(int irq);
 void enable_irq(int irq);
 
 

+ 1 - 1
board/Marvell/common/bootseq.txt

@@ -62,7 +62,7 @@ in_flash:
 	    remap gt regs?
 	    remap gt regs?
 	    map PCI mem/io
 	    map PCI mem/io
 	    map device space
 	    map device space
-	    clear out interupts
+	    clear out interrupts
 	init_timebase
 	init_timebase
 	env_init
 	env_init
 	serial_init
 	serial_init

+ 1 - 1
board/Marvell/common/i2c.c

@@ -420,7 +420,7 @@ i2c_read (uchar dev_addr, unsigned int offset, int alen, uchar * data,
 	status = i2c_get_data (data, len);
 	status = i2c_get_data (data, len);
 	if (status) {
 	if (status) {
 #ifdef DEBUG_I2C
 #ifdef DEBUG_I2C
-		printf ("Data not recieved: 0x%02x\n", status);
+		printf ("Data not received: 0x%02x\n", status);
 #endif
 #endif
 		return status;
 		return status;
 	}
 	}

+ 1 - 1
board/Marvell/common/ns16550.h

@@ -51,7 +51,7 @@ struct NS16550
 #define dlm ier
 #define dlm ier
 
 
 #define FCR_FIFO_EN     0x01    /*fifo enable*/
 #define FCR_FIFO_EN     0x01    /*fifo enable*/
-#define FCR_RXSR        0x02    /*reciever soft reset*/
+#define FCR_RXSR        0x02    /*receiver soft reset*/
 #define FCR_TXSR        0x04    /*transmitter soft reset*/
 #define FCR_TXSR        0x04    /*transmitter soft reset*/
 
 
 
 

+ 1 - 1
board/Marvell/include/mv_gen_reg.h

@@ -2237,7 +2237,7 @@
 #define CHANNEL2_REGISTER10				    0x9070
 #define CHANNEL2_REGISTER10				    0x9070
 #define CHANNEL2_REGISTER11				    0x9074
 #define CHANNEL2_REGISTER11				    0x9074
 
 
-/* MPSCs Interupts  */
+/* MPSCs Interrupts  */
 
 
 #define MPSC0_CAUSE						0xb824
 #define MPSC0_CAUSE						0xb824
 #define MPSC0_MASK						0xb8a4
 #define MPSC0_MASK						0xb8a4

+ 1 - 1
board/bmw/ns16550.h

@@ -37,7 +37,7 @@ struct NS16550 {
 #define afr iirfcrafr
 #define afr iirfcrafr
 
 
 #define FCR_FIFO_EN     0x01	/*fifo enable */
 #define FCR_FIFO_EN     0x01	/*fifo enable */
-#define FCR_RXSR        0x02	/*reciever soft reset */
+#define FCR_RXSR        0x02	/*receiver soft reset */
 #define FCR_TXSR        0x04	/*transmitter soft reset */
 #define FCR_TXSR        0x04	/*transmitter soft reset */
 #define FCR_DMS		0x08	/* DMA Mode Select */
 #define FCR_DMS		0x08	/* DMA Mode Select */
 
 

+ 1 - 1
board/evb64260/bootseq.txt

@@ -62,7 +62,7 @@ in_flash:
 	    remap gt regs?
 	    remap gt regs?
 	    map PCI mem/io
 	    map PCI mem/io
 	    map device space
 	    map device space
-	    clear out interupts
+	    clear out interrupts
 	init_timebase
 	init_timebase
 	env_init
 	env_init
 	serial_init
 	serial_init

+ 1 - 1
board/evb64260/i2c.c

@@ -306,7 +306,7 @@ i2c_read(uchar dev_addr, unsigned int offset, int len, uchar* data,
 	status = i2c_get_data(data, len);
 	status = i2c_get_data(data, len);
 	if (status) {
 	if (status) {
 #ifdef DEBUG_I2C
 #ifdef DEBUG_I2C
-		printf("Data not recieved: 0x%02x\n", status);
+		printf("Data not received: 0x%02x\n", status);
 #endif
 #endif
 		return status;
 		return status;
 	}
 	}

+ 1 - 1
board/freescale/mpc8266ads/mpc8266ads.c

@@ -392,7 +392,7 @@ phys_size_t initdram(int board_type)
        The 11th column addre will still be mucxed correctly onto the bus.
        The 11th column addre will still be mucxed correctly onto the bus.
 
 
        Also be aware that the MPC8266ADS board Rev B has not connected
        Also be aware that the MPC8266ADS board Rev B has not connected
-       Row addres 13 to anything.
+       Row address 13 to anything.
 
 
        The fix is to connect ADD16 (from U37-47) to SADDR12 (U28-126)
        The fix is to connect ADD16 (from U37-47) to SADDR12 (U28-126)
     */
     */

+ 1 - 1
board/intercontrol/digsy_mtc/eeprom.h

@@ -27,6 +27,6 @@
 #define EEPROM_ADDR_IDENT	0	/* identification word offset */
 #define EEPROM_ADDR_IDENT	0	/* identification word offset */
 #define EEPROM_ADDR_LEN_SYS	2	/* system area lenght offset */
 #define EEPROM_ADDR_LEN_SYS	2	/* system area lenght offset */
 #define EEPROM_ADDR_LEN_SYSCFG	4	/* system config area length offset */
 #define EEPROM_ADDR_LEN_SYSCFG	4	/* system config area length offset */
-#define EEPROM_ADDR_ETHADDR	23	/* ethernet addres offset */
+#define EEPROM_ADDR_ETHADDR	23	/* ethernet address offset */
 
 
 #endif
 #endif

+ 1 - 1
board/mpl/common/usb_uhci.c

@@ -67,7 +67,7 @@
  *
  *
  * Interrupt Transfers.
  * Interrupt Transfers.
  * --------------------
  * --------------------
- * For Interupt transfers USB_MAX_TEMP_INT_TD Transfer descriptor are available. They
+ * For Interrupt transfers USB_MAX_TEMP_INT_TD Transfer descriptor are available. They
  * will be inserted after the appropriate (depending the interval setting) skeleton TD.
  * will be inserted after the appropriate (depending the interval setting) skeleton TD.
  * If an interrupt has been detected the dev->irqhandler is called. The status and number
  * If an interrupt has been detected the dev->irqhandler is called. The status and number
  * of transfered bytes is stored in dev->irq_status resp. dev->irq_act_len. If the
  * of transfered bytes is stored in dev->irq_status resp. dev->irq_act_len. If the

+ 1 - 1
common/cmd_flash.c

@@ -139,7 +139,7 @@ int flash_sect_roundb (ulong *addr)
 		} /* bank */
 		} /* bank */
 	}
 	}
 	if (!found) {
 	if (!found) {
-		/* error, addres not in flash */
+		/* error, address not in flash */
 		printf("Error: end address (0x%08lx) not in flash!\n", *addr);
 		printf("Error: end address (0x%08lx) not in flash!\n", *addr);
 		return 1;
 		return 1;
 	}
 	}

+ 1 - 1
common/xyzModem.c

@@ -786,7 +786,7 @@ xyzModem_stream_terminate (bool abort, int (*getc) (void))
       ZM_DEBUG (zm_dprintf ("Engaging cleanup mode...\n"));
       ZM_DEBUG (zm_dprintf ("Engaging cleanup mode...\n"));
       /*
       /*
        * Consume any trailing crap left in the inbuffer from
        * Consume any trailing crap left in the inbuffer from
-       * previous recieved blocks. Since very few files are an exact multiple
+       * previous received blocks. Since very few files are an exact multiple
        * of the transfer block size, there will almost always be some gunk here.
        * of the transfer block size, there will almost always be some gunk here.
        * If we don't eat it now, RedBoot will think the user typed it.
        * If we don't eat it now, RedBoot will think the user typed it.
        */
        */

+ 2 - 2
doc/README.m68k

@@ -111,7 +111,7 @@ CONFIG_SYS_MBAR	-- defines the base address of the MCF5272 configuration registe
 CONFIG_SYS_INIT_RAM_ADDR
 CONFIG_SYS_INIT_RAM_ADDR
 		-- defines the base address of the MCF5272 internal SRAM
 		-- defines the base address of the MCF5272 internal SRAM
 CONFIG_SYS_ENET_BD_BASE
 CONFIG_SYS_ENET_BD_BASE
-		-- defines the base addres of the FEC buffer descriptors
+		-- defines the base address of the FEC buffer descriptors
 
 
 CONFIG_SYS_SCR		-- defines the contents of the System Configuration Register
 CONFIG_SYS_SCR		-- defines the contents of the System Configuration Register
 CONFIG_SYS_SPR		-- defines the contents of the System Protection Register
 CONFIG_SYS_SPR		-- defines the contents of the System Protection Register
@@ -138,7 +138,7 @@ CONFIG_SYS_INIT_RAM_ADDR
 CONFIG_SYS_INT_FLASH_BASE
 CONFIG_SYS_INT_FLASH_BASE
 		-- defines the base address of the MCF5282 internal Flash memory
 		-- defines the base address of the MCF5282 internal Flash memory
 CONFIG_SYS_ENET_BD_BASE
 CONFIG_SYS_ENET_BD_BASE
-		-- defines the base addres of the FEC buffer descriptors
+		-- defines the base address of the FEC buffer descriptors
 
 
 CONFIG_SYS_MFD
 CONFIG_SYS_MFD
 		-- defines the PLL Multiplication Factor Devider
 		-- defines the PLL Multiplication Factor Devider

+ 1 - 1
doc/README.qemu_mips

@@ -24,7 +24,7 @@ you can downland
 
 
 #config to build the kernel
 #config to build the kernel
 qemu_mips_defconfig
 qemu_mips_defconfig
-#patch to fix mips interupt init on 2.6.24.y kernel
+#patch to fix mips interrupt init on 2.6.24.y kernel
 qemu_mips_kernel.patch
 qemu_mips_kernel.patch
 initrd.gz
 initrd.gz
 vmlinux
 vmlinux

+ 1 - 1
drivers/net/4xx_enet.c

@@ -1704,7 +1704,7 @@ int enetInt (struct eth_device *dev)
 			rc = 0;
 			rc = 0;
 		}
 		}
 
 
-		/* handle MAL RX EOB interupt from a receive */
+		/* handle MAL RX EOB interrupt from a receive */
 		/* check for EOB on valid channels	     */
 		/* check for EOB on valid channels	     */
 		if (uic_mal & UIC_MAL_RXEOB) {
 		if (uic_mal & UIC_MAL_RXEOB) {
 			mal_eob = mfdcr(MAL0_RXEOBISR);
 			mal_eob = mfdcr(MAL0_RXEOBISR);

+ 1 - 1
drivers/net/greth.c

@@ -576,7 +576,7 @@ int greth_recv(struct eth_device *dev)
 		GRETH_REGORIN(&regs->control, GRETH_RXEN);
 		GRETH_REGORIN(&regs->control, GRETH_RXEN);
 	}
 	}
       done:
       done:
-	/* return positive length of packet or 0 if non recieved */
+	/* return positive length of packet or 0 if non received */
 	return len;
 	return len;
 }
 }
 
 

+ 1 - 1
drivers/net/natsemi.c

@@ -282,7 +282,7 @@ OUTL(struct eth_device *dev, int command, u_long addr)
  * ready to send and receive packets.
  * ready to send and receive packets.
  *
  *
  * Side effects:
  * Side effects:
- *            leaves the natsemi initialized, and ready to recieve packets.
+ *            leaves the natsemi initialized, and ready to receive packets.
  *
  *
  * Returns:   struct eth_device *:          pointer to NIC data structure
  * Returns:   struct eth_device *:          pointer to NIC data structure
  */
  */

+ 1 - 1
drivers/net/ns8382x.c

@@ -299,7 +299,7 @@ OUTL(struct eth_device *dev, int command, u_long addr)
  * Description: Retrieves the MAC address of the card, and sets up some
  * Description: Retrieves the MAC address of the card, and sets up some
  *  globals required by other routines, and initializes the NIC, making it
  *  globals required by other routines, and initializes the NIC, making it
  *  ready to send and receive packets.
  *  ready to send and receive packets.
- * Side effects: initializes ns8382xs, ready to recieve packets.
+ * Side effects: initializes ns8382xs, ready to receive packets.
  * Returns:   int:          number of cards found
  * Returns:   int:          number of cards found
  */
  */
 
 

+ 1 - 1
drivers/pci/fsl_pci_init.c

@@ -316,7 +316,7 @@ void fsl_pci_init(struct pci_controller *hose, struct fsl_pci_info *pci_info)
 	hose->current_busno = hose->first_busno;
 	hose->current_busno = hose->first_busno;
 
 
 	out_be32(&pci->pedr, 0xffffffff);	/* Clear any errors */
 	out_be32(&pci->pedr, 0xffffffff);	/* Clear any errors */
-	out_be32(&pci->peer, ~0x20140);	/* Enable All Error Interupts except
+	out_be32(&pci->peer, ~0x20140);	/* Enable All Error Interrupts except
 					 * - Master abort (pci)
 					 * - Master abort (pci)
 					 * - Master PERR (pci)
 					 * - Master PERR (pci)
 					 * - ICCA (PCIe)
 					 * - ICCA (PCIe)

+ 1 - 1
drivers/rtc/mpc5xxx.c

@@ -44,7 +44,7 @@ typedef struct rtc5200 {
 	volatile ulong	aier;	/* MBAR+0x80C: alarm and interrupt enable register */
 	volatile ulong	aier;	/* MBAR+0x80C: alarm and interrupt enable register */
 	volatile ulong	ctr;	/* MBAR+0x810: current time register */
 	volatile ulong	ctr;	/* MBAR+0x810: current time register */
 	volatile ulong	cdr;	/* MBAR+0x814: current data register */
 	volatile ulong	cdr;	/* MBAR+0x814: current data register */
-	volatile ulong	asir;	/* MBAR+0x818: alarm and stopwatch interupt register */
+	volatile ulong	asir;	/* MBAR+0x818: alarm and stopwatch interrupt register */
 	volatile ulong	piber;	/* MBAR+0x81C: periodic interrupt and bus error register */
 	volatile ulong	piber;	/* MBAR+0x81C: periodic interrupt and bus error register */
 	volatile ulong	trdr;	/* MBAR+0x820: test register/divides register */
 	volatile ulong	trdr;	/* MBAR+0x820: test register/divides register */
 } RTC5200;
 } RTC5200;

+ 1 - 1
include/commproc.h

@@ -108,7 +108,7 @@ typedef struct cpm_buf_desc {
 	uint	cbd_bufaddr;	/* Buffer address in host memory */
 	uint	cbd_bufaddr;	/* Buffer address in host memory */
 } cbd_t;
 } cbd_t;
 
 
-#define BD_SC_EMPTY	((ushort)0x8000)	/* Recieve is empty */
+#define BD_SC_EMPTY	((ushort)0x8000)	/* Receive is empty */
 #define BD_SC_READY	((ushort)0x8000)	/* Transmit is ready */
 #define BD_SC_READY	((ushort)0x8000)	/* Transmit is ready */
 #define BD_SC_WRAP	((ushort)0x2000)	/* Last buffer descriptor */
 #define BD_SC_WRAP	((ushort)0x2000)	/* Last buffer descriptor */
 #define BD_SC_INTRPT	((ushort)0x1000)	/* Interrupt on change */
 #define BD_SC_INTRPT	((ushort)0x1000)	/* Interrupt on change */

+ 1 - 1
include/configs/NETTA.h

@@ -589,7 +589,7 @@
  +------+----------------+------------------------------------------------------------
  +------+----------------+------------------------------------------------------------
  |  #   | Name           | Comment
  |  #   | Name           | Comment
  +------+----------------+------------------------------------------------------------
  +------+----------------+------------------------------------------------------------
- | IRQ1 | UINTER_3V      | S interupt chips interrupt (common)
+ | IRQ1 | UINTER_3V      | S interrupt chips interrupt (common)
  | IRQ3 | IRQ_DSP        | DSP interrupt
  | IRQ3 | IRQ_DSP        | DSP interrupt
  | IRQ4 | IRQ_DSP1       | Extra DSP interrupt
  | IRQ4 | IRQ_DSP1       | Extra DSP interrupt
  +------+----------------+------------------------------------------------------------
  +------+----------------+------------------------------------------------------------

+ 1 - 1
include/configs/TQM834x.h

@@ -39,7 +39,7 @@
 
 
 #define	CONFIG_SYS_TEXT_BASE	0x80000000
 #define	CONFIG_SYS_TEXT_BASE	0x80000000
 
 
-/* IMMR Base Addres Register, use Freescale default: 0xff400000 */
+/* IMMR Base Address Register, use Freescale default: 0xff400000 */
 #define CONFIG_SYS_IMMR		0xff400000
 #define CONFIG_SYS_IMMR		0xff400000
 
 
 /* System clock. Primary input clock when in PCI host mode */
 /* System clock. Primary input clock when in PCI host mode */

+ 1 - 1
include/galileo/gt64260R.h

@@ -1182,7 +1182,7 @@
 #define CHANNEL2_REGISTER10				0x9070
 #define CHANNEL2_REGISTER10				0x9070
 #define CHANNEL2_REGISTER11				0x9074
 #define CHANNEL2_REGISTER11				0x9074
 
 
-/* MPSCs Interupts  */
+/* MPSCs Interrupts  */
 
 
 #define MPSC0_CAUSE					0xb824
 #define MPSC0_CAUSE					0xb824
 #define MPSC0_MASK					0xb8a4
 #define MPSC0_MASK					0xb8a4

+ 2 - 2
include/mpc5xxx_sdma.h

@@ -82,11 +82,11 @@ ALL PARAMETERS ARE ALL LONGWORDS (FOUR BYTES EACH).
     sdma->IntPend = (1 << tasknum);                    \
     sdma->IntPend = (1 << tasknum);                    \
 }
 }
 
 
-/* get interupt pending bit of a task */
+/* get interrupt pending bit of a task */
 #define SDMA_GET_PENDINGBIT(tasknum)                   \
 #define SDMA_GET_PENDINGBIT(tasknum)                   \
 	((*(vu_long *)(MPC5XXX_SDMA + 0x14)) & (1<<(tasknum)))
 	((*(vu_long *)(MPC5XXX_SDMA + 0x14)) & (1<<(tasknum)))
 
 
-/* get interupt mask bit of a task */
+/* get interrupt mask bit of a task */
 #define SDMA_GET_MASKBIT(tasknum)                      \
 #define SDMA_GET_MASKBIT(tasknum)                      \
 	((*(vu_long *)(MPC5XXX_SDMA + 0x18)) & (1<<(tasknum)))
 	((*(vu_long *)(MPC5XXX_SDMA + 0x18)) & (1<<(tasknum)))
 
 

+ 1 - 1
include/mpc824x.h

@@ -258,7 +258,7 @@
 #define PLTR		0x8000000d  /* PCI Latancy Timer Register */
 #define PLTR		0x8000000d  /* PCI Latancy Timer Register */
 #define PHTR		0x8000000e  /* PCI Header Type Register */
 #define PHTR		0x8000000e  /* PCI Header Type Register */
 #define BISTCTRL	0x8000000f  /* BIST Control */
 #define BISTCTRL	0x8000000f  /* BIST Control */
-#define LMBAR		0x80000010  /* Local Base Addres Register */
+#define LMBAR		0x80000010  /* Local Base Address Register */
 #define PCSRBAR		0x80000014  /* PCSR Base Address Register */
 #define PCSRBAR		0x80000014  /* PCSR Base Address Register */
 #define ILR		0x8000003c  /* PCI Interrupt Line Register */
 #define ILR		0x8000003c  /* PCI Interrupt Line Register */
 #define IPR		0x8000003d  /* Interrupt Pin Register */
 #define IPR		0x8000003d  /* Interrupt Pin Register */