commproc.h 61 KB

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  1. /*
  2. * MPC8xx Communication Processor Module.
  3. * Copyright (c) 1997 Dan Malek (dmalek@jlc.net)
  4. *
  5. * (C) Copyright 2000-2006
  6. * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
  7. *
  8. * This file contains structures and information for the communication
  9. * processor channels. Some CPM control and status is available
  10. * throught the MPC8xx internal memory map. See immap.h for details.
  11. * This file only contains what I need for the moment, not the total
  12. * CPM capabilities. I (or someone else) will add definitions as they
  13. * are needed. -- Dan
  14. *
  15. * On the MBX board, EPPC-Bug loads CPM microcode into the first 512
  16. * bytes of the DP RAM and relocates the I2C parameter area to the
  17. * IDMA1 space. The remaining DP RAM is available for buffer descriptors
  18. * or other use.
  19. */
  20. #ifndef __CPM_8XX__
  21. #define __CPM_8XX__
  22. #include <linux/config.h>
  23. #include <asm/8xx_immap.h>
  24. /* CPM Command register.
  25. */
  26. #define CPM_CR_RST ((ushort)0x8000)
  27. #define CPM_CR_OPCODE ((ushort)0x0f00)
  28. #define CPM_CR_CHAN ((ushort)0x00f0)
  29. #define CPM_CR_FLG ((ushort)0x0001)
  30. /* Some commands (there are more...later)
  31. */
  32. #define CPM_CR_INIT_TRX ((ushort)0x0000)
  33. #define CPM_CR_INIT_RX ((ushort)0x0001)
  34. #define CPM_CR_INIT_TX ((ushort)0x0002)
  35. #define CPM_CR_HUNT_MODE ((ushort)0x0003)
  36. #define CPM_CR_STOP_TX ((ushort)0x0004)
  37. #define CPM_CR_RESTART_TX ((ushort)0x0006)
  38. #define CPM_CR_SET_GADDR ((ushort)0x0008)
  39. /* Channel numbers.
  40. */
  41. #define CPM_CR_CH_SCC1 ((ushort)0x0000)
  42. #define CPM_CR_CH_I2C ((ushort)0x0001) /* I2C and IDMA1 */
  43. #define CPM_CR_CH_SCC2 ((ushort)0x0004)
  44. #define CPM_CR_CH_SPI ((ushort)0x0005) /* SPI/IDMA2/Timers */
  45. #define CPM_CR_CH_SCC3 ((ushort)0x0008)
  46. #define CPM_CR_CH_SMC1 ((ushort)0x0009) /* SMC1 / DSP1 */
  47. #define CPM_CR_CH_SCC4 ((ushort)0x000c)
  48. #define CPM_CR_CH_SMC2 ((ushort)0x000d) /* SMC2 / DSP2 */
  49. #define mk_cr_cmd(CH, CMD) ((CMD << 8) | (CH << 4))
  50. /*
  51. * DPRAM defines and allocation functions
  52. */
  53. /* The dual ported RAM is multi-functional. Some areas can be (and are
  54. * being) used for microcode. There is an area that can only be used
  55. * as data ram for buffer descriptors, which is all we use right now.
  56. * Currently the first 512 and last 256 bytes are used for microcode.
  57. */
  58. #ifdef CONFIG_SYS_ALLOC_DPRAM
  59. #define CPM_DATAONLY_BASE ((uint)0x0800)
  60. #define CPM_DATAONLY_SIZE ((uint)0x0700)
  61. #define CPM_DP_NOSPACE ((uint)0x7fffffff)
  62. #else
  63. #define CPM_SERIAL_BASE 0x0800
  64. #define CPM_I2C_BASE 0x0820
  65. #define CPM_SPI_BASE 0x0840
  66. #define CPM_FEC_BASE 0x0860
  67. #define CPM_SERIAL2_BASE 0x08E0
  68. #define CPM_SCC_BASE 0x0900
  69. #define CPM_POST_BASE 0x0980
  70. #define CPM_WLKBD_BASE 0x0a00
  71. #endif
  72. #ifndef CONFIG_SYS_CPM_POST_WORD_ADDR
  73. #define CPM_POST_WORD_ADDR 0x07FC
  74. #else
  75. #define CPM_POST_WORD_ADDR CONFIG_SYS_CPM_POST_WORD_ADDR
  76. #endif
  77. #ifndef CONFIG_SYS_CPM_BOOTCOUNT_ADDR
  78. #define CPM_BOOTCOUNT_ADDR (CPM_POST_WORD_ADDR - 2*sizeof(ulong))
  79. #else
  80. #define CPM_BOOTCOUNT_ADDR CONFIG_SYS_CPM_BOOTCOUNT_ADDR
  81. #endif
  82. #define BD_IIC_START ((uint) 0x0400) /* <- please use CPM_I2C_BASE !! */
  83. /* Export the base address of the communication processor registers
  84. * and dual port ram.
  85. */
  86. extern cpm8xx_t *cpmp; /* Pointer to comm processor */
  87. /* Buffer descriptors used by many of the CPM protocols.
  88. */
  89. typedef struct cpm_buf_desc {
  90. ushort cbd_sc; /* Status and Control */
  91. ushort cbd_datlen; /* Data length in buffer */
  92. uint cbd_bufaddr; /* Buffer address in host memory */
  93. } cbd_t;
  94. #define BD_SC_EMPTY ((ushort)0x8000) /* Receive is empty */
  95. #define BD_SC_READY ((ushort)0x8000) /* Transmit is ready */
  96. #define BD_SC_WRAP ((ushort)0x2000) /* Last buffer descriptor */
  97. #define BD_SC_INTRPT ((ushort)0x1000) /* Interrupt on change */
  98. #define BD_SC_LAST ((ushort)0x0800) /* Last buffer in frame */
  99. #define BD_SC_TC ((ushort)0x0400) /* Transmit CRC */
  100. #define BD_SC_CM ((ushort)0x0200) /* Continous mode */
  101. #define BD_SC_ID ((ushort)0x0100) /* Rec'd too many idles */
  102. #define BD_SC_P ((ushort)0x0100) /* xmt preamble */
  103. #define BD_SC_BR ((ushort)0x0020) /* Break received */
  104. #define BD_SC_FR ((ushort)0x0010) /* Framing error */
  105. #define BD_SC_PR ((ushort)0x0008) /* Parity error */
  106. #define BD_SC_OV ((ushort)0x0002) /* Overrun */
  107. #define BD_SC_CD ((ushort)0x0001) /* Carrier Detect lost */
  108. /* Parameter RAM offsets.
  109. */
  110. #define PROFF_SCC1 ((uint)0x0000)
  111. #define PROFF_IIC ((uint)0x0080)
  112. #define PROFF_SCC2 ((uint)0x0100)
  113. #define PROFF_SPI ((uint)0x0180)
  114. #define PROFF_SCC3 ((uint)0x0200)
  115. #define PROFF_SMC1 ((uint)0x0280)
  116. #define PROFF_SCC4 ((uint)0x0300)
  117. #define PROFF_SMC2 ((uint)0x0380)
  118. /* Define enough so I can at least use the serial port as a UART.
  119. * The MBX uses SMC1 as the host serial port.
  120. */
  121. typedef struct smc_uart {
  122. ushort smc_rbase; /* Rx Buffer descriptor base address */
  123. ushort smc_tbase; /* Tx Buffer descriptor base address */
  124. u_char smc_rfcr; /* Rx function code */
  125. u_char smc_tfcr; /* Tx function code */
  126. ushort smc_mrblr; /* Max receive buffer length */
  127. uint smc_rstate; /* Internal */
  128. uint smc_idp; /* Internal */
  129. ushort smc_rbptr; /* Internal */
  130. ushort smc_ibc; /* Internal */
  131. uint smc_rxtmp; /* Internal */
  132. uint smc_tstate; /* Internal */
  133. uint smc_tdp; /* Internal */
  134. ushort smc_tbptr; /* Internal */
  135. ushort smc_tbc; /* Internal */
  136. uint smc_txtmp; /* Internal */
  137. ushort smc_maxidl; /* Maximum idle characters */
  138. ushort smc_tmpidl; /* Temporary idle counter */
  139. ushort smc_brklen; /* Last received break length */
  140. ushort smc_brkec; /* rcv'd break condition counter */
  141. ushort smc_brkcr; /* xmt break count register */
  142. ushort smc_rmask; /* Temporary bit mask */
  143. u_char res1[8];
  144. ushort smc_rpbase; /* Relocation pointer */
  145. } smc_uart_t;
  146. /* Function code bits.
  147. */
  148. #define SMC_EB ((u_char)0x10) /* Set big endian byte order */
  149. /* SMC uart mode register.
  150. */
  151. #define SMCMR_REN ((ushort)0x0001)
  152. #define SMCMR_TEN ((ushort)0x0002)
  153. #define SMCMR_DM ((ushort)0x000c)
  154. #define SMCMR_SM_GCI ((ushort)0x0000)
  155. #define SMCMR_SM_UART ((ushort)0x0020)
  156. #define SMCMR_SM_TRANS ((ushort)0x0030)
  157. #define SMCMR_SM_MASK ((ushort)0x0030)
  158. #define SMCMR_PM_EVEN ((ushort)0x0100) /* Even parity, else odd */
  159. #define SMCMR_REVD SMCMR_PM_EVEN
  160. #define SMCMR_PEN ((ushort)0x0200) /* Parity enable */
  161. #define SMCMR_BS SMCMR_PEN
  162. #define SMCMR_SL ((ushort)0x0400) /* Two stops, else one */
  163. #define SMCR_CLEN_MASK ((ushort)0x7800) /* Character length */
  164. #define smcr_mk_clen(C) (((C) << 11) & SMCR_CLEN_MASK)
  165. /* SMC2 as Centronics parallel printer. It is half duplex, in that
  166. * it can only receive or transmit. The parameter ram values for
  167. * each direction are either unique or properly overlap, so we can
  168. * include them in one structure.
  169. */
  170. typedef struct smc_centronics {
  171. ushort scent_rbase;
  172. ushort scent_tbase;
  173. u_char scent_cfcr;
  174. u_char scent_smask;
  175. ushort scent_mrblr;
  176. uint scent_rstate;
  177. uint scent_r_ptr;
  178. ushort scent_rbptr;
  179. ushort scent_r_cnt;
  180. uint scent_rtemp;
  181. uint scent_tstate;
  182. uint scent_t_ptr;
  183. ushort scent_tbptr;
  184. ushort scent_t_cnt;
  185. uint scent_ttemp;
  186. ushort scent_max_sl;
  187. ushort scent_sl_cnt;
  188. ushort scent_character1;
  189. ushort scent_character2;
  190. ushort scent_character3;
  191. ushort scent_character4;
  192. ushort scent_character5;
  193. ushort scent_character6;
  194. ushort scent_character7;
  195. ushort scent_character8;
  196. ushort scent_rccm;
  197. ushort scent_rccr;
  198. } smc_cent_t;
  199. /* Centronics Status Mask Register.
  200. */
  201. #define SMC_CENT_F ((u_char)0x08)
  202. #define SMC_CENT_PE ((u_char)0x04)
  203. #define SMC_CENT_S ((u_char)0x02)
  204. /* SMC Event and Mask register.
  205. */
  206. #define SMCM_BRKE ((unsigned char)0x40) /* When in UART Mode */
  207. #define SMCM_BRK ((unsigned char)0x10) /* When in UART Mode */
  208. #define SMCM_TXE ((unsigned char)0x10) /* When in Transparent Mode */
  209. #define SMCM_BSY ((unsigned char)0x04)
  210. #define SMCM_TX ((unsigned char)0x02)
  211. #define SMCM_RX ((unsigned char)0x01)
  212. /* Baud rate generators.
  213. */
  214. #define CPM_BRG_RST ((uint)0x00020000)
  215. #define CPM_BRG_EN ((uint)0x00010000)
  216. #define CPM_BRG_EXTC_INT ((uint)0x00000000)
  217. #define CPM_BRG_EXTC_CLK2 ((uint)0x00004000)
  218. #define CPM_BRG_EXTC_CLK6 ((uint)0x00008000)
  219. #define CPM_BRG_ATB ((uint)0x00002000)
  220. #define CPM_BRG_CD_MASK ((uint)0x00001ffe)
  221. #define CPM_BRG_DIV16 ((uint)0x00000001)
  222. /* SI Clock Route Register
  223. */
  224. #define SICR_RCLK_SCC1_BRG1 ((uint)0x00000000)
  225. #define SICR_TCLK_SCC1_BRG1 ((uint)0x00000000)
  226. #define SICR_RCLK_SCC2_BRG2 ((uint)0x00000800)
  227. #define SICR_TCLK_SCC2_BRG2 ((uint)0x00000100)
  228. #define SICR_RCLK_SCC3_BRG3 ((uint)0x00100000)
  229. #define SICR_TCLK_SCC3_BRG3 ((uint)0x00020000)
  230. #define SICR_RCLK_SCC4_BRG4 ((uint)0x18000000)
  231. #define SICR_TCLK_SCC4_BRG4 ((uint)0x03000000)
  232. /* SCCs.
  233. */
  234. #define SCC_GSMRH_IRP ((uint)0x00040000)
  235. #define SCC_GSMRH_GDE ((uint)0x00010000)
  236. #define SCC_GSMRH_TCRC_CCITT ((uint)0x00008000)
  237. #define SCC_GSMRH_TCRC_BISYNC ((uint)0x00004000)
  238. #define SCC_GSMRH_TCRC_HDLC ((uint)0x00000000)
  239. #define SCC_GSMRH_REVD ((uint)0x00002000)
  240. #define SCC_GSMRH_TRX ((uint)0x00001000)
  241. #define SCC_GSMRH_TTX ((uint)0x00000800)
  242. #define SCC_GSMRH_CDP ((uint)0x00000400)
  243. #define SCC_GSMRH_CTSP ((uint)0x00000200)
  244. #define SCC_GSMRH_CDS ((uint)0x00000100)
  245. #define SCC_GSMRH_CTSS ((uint)0x00000080)
  246. #define SCC_GSMRH_TFL ((uint)0x00000040)
  247. #define SCC_GSMRH_RFW ((uint)0x00000020)
  248. #define SCC_GSMRH_TXSY ((uint)0x00000010)
  249. #define SCC_GSMRH_SYNL16 ((uint)0x0000000c)
  250. #define SCC_GSMRH_SYNL8 ((uint)0x00000008)
  251. #define SCC_GSMRH_SYNL4 ((uint)0x00000004)
  252. #define SCC_GSMRH_RTSM ((uint)0x00000002)
  253. #define SCC_GSMRH_RSYN ((uint)0x00000001)
  254. #define SCC_GSMRL_SIR ((uint)0x80000000) /* SCC2 only */
  255. #define SCC_GSMRL_EDGE_NONE ((uint)0x60000000)
  256. #define SCC_GSMRL_EDGE_NEG ((uint)0x40000000)
  257. #define SCC_GSMRL_EDGE_POS ((uint)0x20000000)
  258. #define SCC_GSMRL_EDGE_BOTH ((uint)0x00000000)
  259. #define SCC_GSMRL_TCI ((uint)0x10000000)
  260. #define SCC_GSMRL_TSNC_3 ((uint)0x0c000000)
  261. #define SCC_GSMRL_TSNC_4 ((uint)0x08000000)
  262. #define SCC_GSMRL_TSNC_14 ((uint)0x04000000)
  263. #define SCC_GSMRL_TSNC_INF ((uint)0x00000000)
  264. #define SCC_GSMRL_RINV ((uint)0x02000000)
  265. #define SCC_GSMRL_TINV ((uint)0x01000000)
  266. #define SCC_GSMRL_TPL_128 ((uint)0x00c00000)
  267. #define SCC_GSMRL_TPL_64 ((uint)0x00a00000)
  268. #define SCC_GSMRL_TPL_48 ((uint)0x00800000)
  269. #define SCC_GSMRL_TPL_32 ((uint)0x00600000)
  270. #define SCC_GSMRL_TPL_16 ((uint)0x00400000)
  271. #define SCC_GSMRL_TPL_8 ((uint)0x00200000)
  272. #define SCC_GSMRL_TPL_NONE ((uint)0x00000000)
  273. #define SCC_GSMRL_TPP_ALL1 ((uint)0x00180000)
  274. #define SCC_GSMRL_TPP_01 ((uint)0x00100000)
  275. #define SCC_GSMRL_TPP_10 ((uint)0x00080000)
  276. #define SCC_GSMRL_TPP_ZEROS ((uint)0x00000000)
  277. #define SCC_GSMRL_TEND ((uint)0x00040000)
  278. #define SCC_GSMRL_TDCR_32 ((uint)0x00030000)
  279. #define SCC_GSMRL_TDCR_16 ((uint)0x00020000)
  280. #define SCC_GSMRL_TDCR_8 ((uint)0x00010000)
  281. #define SCC_GSMRL_TDCR_1 ((uint)0x00000000)
  282. #define SCC_GSMRL_RDCR_32 ((uint)0x0000c000)
  283. #define SCC_GSMRL_RDCR_16 ((uint)0x00008000)
  284. #define SCC_GSMRL_RDCR_8 ((uint)0x00004000)
  285. #define SCC_GSMRL_RDCR_1 ((uint)0x00000000)
  286. #define SCC_GSMRL_RENC_DFMAN ((uint)0x00003000)
  287. #define SCC_GSMRL_RENC_MANCH ((uint)0x00002000)
  288. #define SCC_GSMRL_RENC_FM0 ((uint)0x00001000)
  289. #define SCC_GSMRL_RENC_NRZI ((uint)0x00000800)
  290. #define SCC_GSMRL_RENC_NRZ ((uint)0x00000000)
  291. #define SCC_GSMRL_TENC_DFMAN ((uint)0x00000600)
  292. #define SCC_GSMRL_TENC_MANCH ((uint)0x00000400)
  293. #define SCC_GSMRL_TENC_FM0 ((uint)0x00000200)
  294. #define SCC_GSMRL_TENC_NRZI ((uint)0x00000100)
  295. #define SCC_GSMRL_TENC_NRZ ((uint)0x00000000)
  296. #define SCC_GSMRL_DIAG_LE ((uint)0x000000c0) /* Loop and echo */
  297. #define SCC_GSMRL_DIAG_ECHO ((uint)0x00000080)
  298. #define SCC_GSMRL_DIAG_LOOP ((uint)0x00000040)
  299. #define SCC_GSMRL_DIAG_NORM ((uint)0x00000000)
  300. #define SCC_GSMRL_ENR ((uint)0x00000020)
  301. #define SCC_GSMRL_ENT ((uint)0x00000010)
  302. #define SCC_GSMRL_MODE_ENET ((uint)0x0000000c)
  303. #define SCC_GSMRL_MODE_DDCMP ((uint)0x00000009)
  304. #define SCC_GSMRL_MODE_BISYNC ((uint)0x00000008)
  305. #define SCC_GSMRL_MODE_V14 ((uint)0x00000007)
  306. #define SCC_GSMRL_MODE_AHDLC ((uint)0x00000006)
  307. #define SCC_GSMRL_MODE_PROFIBUS ((uint)0x00000005)
  308. #define SCC_GSMRL_MODE_UART ((uint)0x00000004)
  309. #define SCC_GSMRL_MODE_SS7 ((uint)0x00000003)
  310. #define SCC_GSMRL_MODE_ATALK ((uint)0x00000002)
  311. #define SCC_GSMRL_MODE_HDLC ((uint)0x00000000)
  312. #define SCC_TODR_TOD ((ushort)0x8000)
  313. /* SCC Event and Mask register.
  314. */
  315. #define SCCM_TXE ((unsigned char)0x10)
  316. #define SCCM_BSY ((unsigned char)0x04)
  317. #define SCCM_TX ((unsigned char)0x02)
  318. #define SCCM_RX ((unsigned char)0x01)
  319. typedef struct scc_param {
  320. ushort scc_rbase; /* Rx Buffer descriptor base address */
  321. ushort scc_tbase; /* Tx Buffer descriptor base address */
  322. u_char scc_rfcr; /* Rx function code */
  323. u_char scc_tfcr; /* Tx function code */
  324. ushort scc_mrblr; /* Max receive buffer length */
  325. uint scc_rstate; /* Internal */
  326. uint scc_idp; /* Internal */
  327. ushort scc_rbptr; /* Internal */
  328. ushort scc_ibc; /* Internal */
  329. uint scc_rxtmp; /* Internal */
  330. uint scc_tstate; /* Internal */
  331. uint scc_tdp; /* Internal */
  332. ushort scc_tbptr; /* Internal */
  333. ushort scc_tbc; /* Internal */
  334. uint scc_txtmp; /* Internal */
  335. uint scc_rcrc; /* Internal */
  336. uint scc_tcrc; /* Internal */
  337. } sccp_t;
  338. /* Function code bits.
  339. */
  340. #define SCC_EB ((u_char)0x10) /* Set big endian byte order */
  341. /* CPM Ethernet through SCCx.
  342. */
  343. typedef struct scc_enet {
  344. sccp_t sen_genscc;
  345. uint sen_cpres; /* Preset CRC */
  346. uint sen_cmask; /* Constant mask for CRC */
  347. uint sen_crcec; /* CRC Error counter */
  348. uint sen_alec; /* alignment error counter */
  349. uint sen_disfc; /* discard frame counter */
  350. ushort sen_pads; /* Tx short frame pad character */
  351. ushort sen_retlim; /* Retry limit threshold */
  352. ushort sen_retcnt; /* Retry limit counter */
  353. ushort sen_maxflr; /* maximum frame length register */
  354. ushort sen_minflr; /* minimum frame length register */
  355. ushort sen_maxd1; /* maximum DMA1 length */
  356. ushort sen_maxd2; /* maximum DMA2 length */
  357. ushort sen_maxd; /* Rx max DMA */
  358. ushort sen_dmacnt; /* Rx DMA counter */
  359. ushort sen_maxb; /* Max BD byte count */
  360. ushort sen_gaddr1; /* Group address filter */
  361. ushort sen_gaddr2;
  362. ushort sen_gaddr3;
  363. ushort sen_gaddr4;
  364. uint sen_tbuf0data0; /* Save area 0 - current frame */
  365. uint sen_tbuf0data1; /* Save area 1 - current frame */
  366. uint sen_tbuf0rba; /* Internal */
  367. uint sen_tbuf0crc; /* Internal */
  368. ushort sen_tbuf0bcnt; /* Internal */
  369. ushort sen_paddrh; /* physical address (MSB) */
  370. ushort sen_paddrm;
  371. ushort sen_paddrl; /* physical address (LSB) */
  372. ushort sen_pper; /* persistence */
  373. ushort sen_rfbdptr; /* Rx first BD pointer */
  374. ushort sen_tfbdptr; /* Tx first BD pointer */
  375. ushort sen_tlbdptr; /* Tx last BD pointer */
  376. uint sen_tbuf1data0; /* Save area 0 - current frame */
  377. uint sen_tbuf1data1; /* Save area 1 - current frame */
  378. uint sen_tbuf1rba; /* Internal */
  379. uint sen_tbuf1crc; /* Internal */
  380. ushort sen_tbuf1bcnt; /* Internal */
  381. ushort sen_txlen; /* Tx Frame length counter */
  382. ushort sen_iaddr1; /* Individual address filter */
  383. ushort sen_iaddr2;
  384. ushort sen_iaddr3;
  385. ushort sen_iaddr4;
  386. ushort sen_boffcnt; /* Backoff counter */
  387. /* NOTE: Some versions of the manual have the following items
  388. * incorrectly documented. Below is the proper order.
  389. */
  390. ushort sen_taddrh; /* temp address (MSB) */
  391. ushort sen_taddrm;
  392. ushort sen_taddrl; /* temp address (LSB) */
  393. } scc_enet_t;
  394. /**********************************************************************
  395. *
  396. * Board specific configuration settings.
  397. *
  398. * Please note that we use the presence of a #define SCC_ENET and/or
  399. * #define FEC_ENET to enable the SCC resp. FEC ethernet drivers.
  400. **********************************************************************/
  401. /*** ADS *************************************************************/
  402. #if defined(CONFIG_MPC860) && defined(CONFIG_ADS)
  403. /* This ENET stuff is for the MPC860ADS with ethernet on SCC1.
  404. */
  405. #define PROFF_ENET PROFF_SCC1
  406. #define CPM_CR_ENET CPM_CR_CH_SCC1
  407. #define SCC_ENET 0
  408. #define PA_ENET_RXD ((ushort)0x0001)
  409. #define PA_ENET_TXD ((ushort)0x0002)
  410. #define PA_ENET_TCLK ((ushort)0x0100)
  411. #define PA_ENET_RCLK ((ushort)0x0200)
  412. #define PB_ENET_TENA ((uint)0x00001000)
  413. #define PC_ENET_CLSN ((ushort)0x0010)
  414. #define PC_ENET_RENA ((ushort)0x0020)
  415. #define SICR_ENET_MASK ((uint)0x000000ff)
  416. #define SICR_ENET_CLKRT ((uint)0x0000002c)
  417. /* 68160 PHY control */
  418. #define PC_ENET_ETHLOOP ((ushort)0x0800)
  419. #define PC_ENET_TPFLDL ((ushort)0x0400)
  420. #define PC_ENET_TPSQEL ((ushort)0x0200)
  421. #endif /* MPC860ADS */
  422. /*** AMX860 **********************************************/
  423. #if defined(CONFIG_AMX860)
  424. /* This ENET stuff is for the AMX860 with ethernet on SCC1.
  425. */
  426. #define PROFF_ENET PROFF_SCC1
  427. #define CPM_CR_ENET CPM_CR_CH_SCC1
  428. #define SCC_ENET 0
  429. #define PA_ENET_RXD ((ushort)0x0001)
  430. #define PA_ENET_TXD ((ushort)0x0002)
  431. #define PA_ENET_TCLK ((ushort)0x0400)
  432. #define PA_ENET_RCLK ((ushort)0x0800)
  433. #define PB_ENET_TENA ((uint)0x00001000)
  434. #define PC_ENET_CLSN ((ushort)0x0010)
  435. #define PC_ENET_RENA ((ushort)0x0020)
  436. #define SICR_ENET_MASK ((uint)0x000000ff)
  437. #define SICR_ENET_CLKRT ((uint)0x0000003e)
  438. /* 68160 PHY control */
  439. #define PB_ENET_ETHLOOP ((uint)0x00020000)
  440. #define PB_ENET_TPFLDL ((uint)0x00010000)
  441. #define PB_ENET_TPSQEL ((uint)0x00008000)
  442. #define PD_ENET_ETH_EN ((ushort)0x0004)
  443. #endif /* CONFIG_AMX860 */
  444. /*** BSEIP **********************************************************/
  445. #ifdef CONFIG_BSEIP
  446. /* This ENET stuff is for the MPC823 with ethernet on SCC2.
  447. * This is unique to the BSE ip-Engine board.
  448. */
  449. #define PROFF_ENET PROFF_SCC2
  450. #define CPM_CR_ENET CPM_CR_CH_SCC2
  451. #define SCC_ENET 1
  452. #define PA_ENET_RXD ((ushort)0x0004)
  453. #define PA_ENET_TXD ((ushort)0x0008)
  454. #define PA_ENET_TCLK ((ushort)0x0100)
  455. #define PA_ENET_RCLK ((ushort)0x0200)
  456. #define PB_ENET_TENA ((uint)0x00002000)
  457. #define PC_ENET_CLSN ((ushort)0x0040)
  458. #define PC_ENET_RENA ((ushort)0x0080)
  459. /* BSE uses port B and C bits for PHY control also.
  460. */
  461. #define PB_BSE_POWERUP ((uint)0x00000004)
  462. #define PB_BSE_FDXDIS ((uint)0x00008000)
  463. #define PC_BSE_LOOPBACK ((ushort)0x0800)
  464. #define SICR_ENET_MASK ((uint)0x0000ff00)
  465. #define SICR_ENET_CLKRT ((uint)0x00002c00)
  466. #endif /* CONFIG_BSEIP */
  467. /*** BSEIP **********************************************************/
  468. #ifdef CONFIG_FLAGADM
  469. /* Enet configuration for the FLAGADM */
  470. /* Enet on SCC2 */
  471. #define PROFF_ENET PROFF_SCC2
  472. #define CPM_CR_ENET CPM_CR_CH_SCC2
  473. #define SCC_ENET 1
  474. #define PA_ENET_RXD ((ushort)0x0004)
  475. #define PA_ENET_TXD ((ushort)0x0008)
  476. #define PA_ENET_TCLK ((ushort)0x0100)
  477. #define PA_ENET_RCLK ((ushort)0x0400)
  478. #define PB_ENET_TENA ((uint)0x00002000)
  479. #define PC_ENET_CLSN ((ushort)0x0040)
  480. #define PC_ENET_RENA ((ushort)0x0080)
  481. #define SICR_ENET_MASK ((uint)0x0000ff00)
  482. #define SICR_ENET_CLKRT ((uint)0x00003400)
  483. #endif /* CONFIG_FLAGADM */
  484. /*** C2MON **********************************************************/
  485. #ifdef CONFIG_C2MON
  486. # ifndef CONFIG_FEC_ENET /* use SCC for 10Mbps Ethernet */
  487. # error "Ethernet on SCC not supported on C2MON Board!"
  488. # else /* Use FEC for Fast Ethernet */
  489. #undef SCC_ENET
  490. #define FEC_ENET
  491. #define PD_MII_TXD1 ((ushort)0x1000) /* PD 3 */
  492. #define PD_MII_TXD2 ((ushort)0x0800) /* PD 4 */
  493. #define PD_MII_TXD3 ((ushort)0x0400) /* PD 5 */
  494. #define PD_MII_RX_DV ((ushort)0x0200) /* PD 6 */
  495. #define PD_MII_RX_ERR ((ushort)0x0100) /* PD 7 */
  496. #define PD_MII_RX_CLK ((ushort)0x0080) /* PD 8 */
  497. #define PD_MII_TXD0 ((ushort)0x0040) /* PD 9 */
  498. #define PD_MII_RXD0 ((ushort)0x0020) /* PD 10 */
  499. #define PD_MII_TX_ERR ((ushort)0x0010) /* PD 11 */
  500. #define PD_MII_MDC ((ushort)0x0008) /* PD 12 */
  501. #define PD_MII_RXD1 ((ushort)0x0004) /* PD 13 */
  502. #define PD_MII_RXD2 ((ushort)0x0002) /* PD 14 */
  503. #define PD_MII_RXD3 ((ushort)0x0001) /* PD 15 */
  504. #define PD_MII_MASK ((ushort)0x1FFF) /* PD 3...15 */
  505. # endif /* CONFIG_FEC_ENET */
  506. #endif /* CONFIG_C2MON */
  507. /*********************************************************************/
  508. /*** ELPT860 *********************************************************/
  509. #ifdef CONFIG_ELPT860
  510. /* Bits in parallel I/O port registers that have to be set/cleared
  511. * to configure the pins for SCC1 use.
  512. */
  513. # define PROFF_ENET PROFF_SCC1
  514. # define CPM_CR_ENET CPM_CR_CH_SCC1
  515. # define SCC_ENET 0
  516. # define PA_ENET_RXD ((ushort)0x0001) /* PA 15 */
  517. # define PA_ENET_TXD ((ushort)0x0002) /* PA 14 */
  518. # define PA_ENET_RCLK ((ushort)0x0100) /* PA 7 */
  519. # define PA_ENET_TCLK ((ushort)0x0200) /* PA 6 */
  520. # define PC_ENET_TENA ((ushort)0x0001) /* PC 15 */
  521. # define PC_ENET_CLSN ((ushort)0x0010) /* PC 11 */
  522. # define PC_ENET_RENA ((ushort)0x0020) /* PC 10 */
  523. /* Control bits in the SICR to route TCLK (CLK2) and RCLK (CLK1) to
  524. * SCC1. Also, make sure GR1 (bit 24) and SC1 (bit 25) are zero.
  525. */
  526. # define SICR_ENET_MASK ((uint)0x000000FF)
  527. # define SICR_ENET_CLKRT ((uint)0x00000025)
  528. #endif /* CONFIG_ELPT860 */
  529. /*** ESTEEM 192E **************************************************/
  530. #ifdef CONFIG_ESTEEM192E
  531. /* ESTEEM192E
  532. * This ENET stuff is for the MPC850 with ethernet on SCC2. This
  533. * is very similar to the RPX-Lite configuration.
  534. * Note TENA , LOOPBACK , FDPLEX_DIS on Port B.
  535. */
  536. #define PROFF_ENET PROFF_SCC2
  537. #define CPM_CR_ENET CPM_CR_CH_SCC2
  538. #define SCC_ENET 1
  539. #define PA_ENET_RXD ((ushort)0x0004)
  540. #define PA_ENET_TXD ((ushort)0x0008)
  541. #define PA_ENET_TCLK ((ushort)0x0200)
  542. #define PA_ENET_RCLK ((ushort)0x0800)
  543. #define PB_ENET_TENA ((uint)0x00002000)
  544. #define PC_ENET_CLSN ((ushort)0x0040)
  545. #define PC_ENET_RENA ((ushort)0x0080)
  546. #define SICR_ENET_MASK ((uint)0x0000ff00)
  547. #define SICR_ENET_CLKRT ((uint)0x00003d00)
  548. #define PB_ENET_LOOPBACK ((uint)0x00004000)
  549. #define PB_ENET_FDPLEX_DIS ((uint)0x00008000)
  550. #endif
  551. /*** FADS823 ********************************************************/
  552. #if defined(CONFIG_MPC823FADS) && defined(CONFIG_FADS)
  553. /* This ENET stuff is for the MPC823FADS with ethernet on SCC2.
  554. */
  555. #ifdef CONFIG_SCC2_ENET
  556. #define PROFF_ENET PROFF_SCC2
  557. #define CPM_CR_ENET CPM_CR_CH_SCC2
  558. #define SCC_ENET 1
  559. #define CPMVEC_ENET CPMVEC_SCC2
  560. #endif
  561. #ifdef CONFIG_SCC1_ENET
  562. #define PROFF_ENET PROFF_SCC1
  563. #define CPM_CR_ENET CPM_CR_CH_SCC1
  564. #define SCC_ENET 0
  565. #define CPMVEC_ENET CPMVEC_SCC1
  566. #endif
  567. #define PA_ENET_RXD ((ushort)0x0004)
  568. #define PA_ENET_TXD ((ushort)0x0008)
  569. #define PA_ENET_TCLK ((ushort)0x0400)
  570. #define PA_ENET_RCLK ((ushort)0x0200)
  571. #define PB_ENET_TENA ((uint)0x00002000)
  572. #define PC_ENET_CLSN ((ushort)0x0040)
  573. #define PC_ENET_RENA ((ushort)0x0080)
  574. #define SICR_ENET_MASK ((uint)0x0000ff00)
  575. #define SICR_ENET_CLKRT ((uint)0x00002e00)
  576. #endif /* CONFIG_FADS823FADS */
  577. /*** FADS850SAR ********************************************************/
  578. #if defined(CONFIG_MPC850SAR) && defined(CONFIG_FADS)
  579. /* This ENET stuff is for the MPC850SAR with ethernet on SCC2. Some of
  580. * this may be unique to the FADS850SAR configuration.
  581. * Note TENA is on Port B.
  582. */
  583. #define PROFF_ENET PROFF_SCC2
  584. #define CPM_CR_ENET CPM_CR_CH_SCC2
  585. #define SCC_ENET 1
  586. #define PA_ENET_RXD ((ushort)0x0004) /* PA 13 */
  587. #define PA_ENET_TXD ((ushort)0x0008) /* PA 12 */
  588. #define PA_ENET_RCLK ((ushort)0x0200) /* PA 6 */
  589. #define PA_ENET_TCLK ((ushort)0x0800) /* PA 4 */
  590. #define PB_ENET_TENA ((uint)0x00002000) /* PB 18 */
  591. #define PC_ENET_CLSN ((ushort)0x0040) /* PC 9 */
  592. #define PC_ENET_RENA ((ushort)0x0080) /* PC 8 */
  593. #define SICR_ENET_MASK ((uint)0x0000ff00)
  594. #define SICR_ENET_CLKRT ((uint)0x00002f00) /* RCLK-CLK2, TCLK-CLK4 */
  595. #endif /* CONFIG_FADS850SAR */
  596. /*** FADS860T********************************************************/
  597. #if defined(CONFIG_FADS) && defined(CONFIG_MPC86x)
  598. /*
  599. * This ENET stuff is for the MPC86xFADS/MPC8xxADS with ethernet on SCC1.
  600. */
  601. #ifdef CONFIG_SCC1_ENET
  602. #define SCC_ENET 0
  603. #define PROFF_ENET PROFF_SCC1
  604. #define CPM_CR_ENET CPM_CR_CH_SCC1
  605. #define PA_ENET_RXD ((ushort)0x0001)
  606. #define PA_ENET_TXD ((ushort)0x0002)
  607. #define PA_ENET_TCLK ((ushort)0x0100)
  608. #define PA_ENET_RCLK ((ushort)0x0200)
  609. #define PB_ENET_TENA ((uint)0x00001000)
  610. #define PC_ENET_CLSN ((ushort)0x0010)
  611. #define PC_ENET_RENA ((ushort)0x0020)
  612. #define SICR_ENET_MASK ((uint)0x000000ff)
  613. #define SICR_ENET_CLKRT ((uint)0x0000002c)
  614. #endif /* CONFIG_SCC1_ETHERNET */
  615. /*
  616. * This ENET stuff is for the MPC860TFADS/MPC86xADS/MPC885ADS
  617. * with ethernet on FEC.
  618. */
  619. #ifdef CONFIG_FEC_ENET
  620. #define FEC_ENET /* Use FEC for Ethernet */
  621. #endif /* CONFIG_FEC_ENET */
  622. #endif /* CONFIG_FADS && CONFIG_MPC86x */
  623. /*** FPS850L, FPS860L ************************************************/
  624. #if defined(CONFIG_FPS850L) || defined(CONFIG_FPS860L)
  625. /* Bits in parallel I/O port registers that have to be set/cleared
  626. * to configure the pins for SCC2 use.
  627. */
  628. #define PROFF_ENET PROFF_SCC2
  629. #define CPM_CR_ENET CPM_CR_CH_SCC2
  630. #define SCC_ENET 1
  631. #define PA_ENET_RXD ((ushort)0x0004) /* PA 13 */
  632. #define PA_ENET_TXD ((ushort)0x0008) /* PA 12 */
  633. #define PA_ENET_RCLK ((ushort)0x0100) /* PA 7 */
  634. #define PA_ENET_TCLK ((ushort)0x0400) /* PA 5 */
  635. #define PC_ENET_TENA ((ushort)0x0002) /* PC 14 */
  636. #define PC_ENET_CLSN ((ushort)0x0040) /* PC 9 */
  637. #define PC_ENET_RENA ((ushort)0x0080) /* PC 8 */
  638. /* Control bits in the SICR to route TCLK (CLK2) and RCLK (CLK4) to
  639. * SCC2. Also, make sure GR2 (bit 16) and SC2 (bit 17) are zero.
  640. */
  641. #define SICR_ENET_MASK ((uint)0x0000ff00)
  642. #define SICR_ENET_CLKRT ((uint)0x00002600)
  643. #endif /* CONFIG_FPS850L, CONFIG_FPS860L */
  644. /*** GEN860T **********************************************************/
  645. #if defined(CONFIG_GEN860T)
  646. #undef SCC_ENET
  647. #define FEC_ENET
  648. #define PD_MII_TXD1 ((ushort)0x1000) /* PD 3 */
  649. #define PD_MII_TXD2 ((ushort)0x0800) /* PD 4 */
  650. #define PD_MII_TXD3 ((ushort)0x0400) /* PD 5 */
  651. #define PD_MII_RX_DV ((ushort)0x0200) /* PD 6 */
  652. #define PD_MII_RX_ERR ((ushort)0x0100) /* PD 7 */
  653. #define PD_MII_RX_CLK ((ushort)0x0080) /* PD 8 */
  654. #define PD_MII_TXD0 ((ushort)0x0040) /* PD 9 */
  655. #define PD_MII_RXD0 ((ushort)0x0020) /* PD 10 */
  656. #define PD_MII_TX_ERR ((ushort)0x0010) /* PD 11 */
  657. #define PD_MII_MDC ((ushort)0x0008) /* PD 12 */
  658. #define PD_MII_RXD1 ((ushort)0x0004) /* PD 13 */
  659. #define PD_MII_RXD2 ((ushort)0x0002) /* PD 14 */
  660. #define PD_MII_RXD3 ((ushort)0x0001) /* PD 15 */
  661. #define PD_MII_MASK ((ushort)0x1FFF) /* PD 3-15 */
  662. #endif /* CONFIG_GEN860T */
  663. /*** GENIETV ********************************************************/
  664. #if defined(CONFIG_GENIETV)
  665. /* Ethernet is only on SCC2 */
  666. #define CONFIG_SCC2_ENET
  667. #define PROFF_ENET PROFF_SCC2
  668. #define CPM_CR_ENET CPM_CR_CH_SCC2
  669. #define SCC_ENET 1
  670. #define CPMVEC_ENET CPMVEC_SCC2
  671. #define PA_ENET_RXD ((ushort)0x0004) /* PA 13 */
  672. #define PA_ENET_TXD ((ushort)0x0008) /* PA 12 */
  673. #define PA_ENET_TCLK ((ushort)0x0400) /* PA 5 */
  674. #define PA_ENET_RCLK ((ushort)0x0200) /* PA 6 */
  675. #define PB_ENET_TENA ((uint)0x00002000) /* PB 18 */
  676. #define PC_ENET_CLSN ((ushort)0x0040) /* PC 9 */
  677. #define PC_ENET_RENA ((ushort)0x0080) /* PC 8 */
  678. #define SICR_ENET_MASK ((uint)0x0000ff00)
  679. #define SICR_ENET_CLKRT ((uint)0x00002e00)
  680. #endif /* CONFIG_GENIETV */
  681. /*** HERMES-PRO ******************************************************/
  682. /* The HERMES-PRO uses the FEC on a MPC860T for Ethernet */
  683. #ifdef CONFIG_HERMES
  684. #define FEC_ENET /* use FEC for EThernet */
  685. #undef SCC_ENET
  686. #define PD_MII_TXD1 ((ushort)0x1000) /* PD 3 */
  687. #define PD_MII_TXD2 ((ushort)0x0800) /* PD 4 */
  688. #define PD_MII_TXD3 ((ushort)0x0400) /* PD 5 */
  689. #define PD_MII_RX_DV ((ushort)0x0200) /* PD 6 */
  690. #define PD_MII_RX_ERR ((ushort)0x0100) /* PD 7 */
  691. #define PD_MII_RX_CLK ((ushort)0x0080) /* PD 8 */
  692. #define PD_MII_TXD0 ((ushort)0x0040) /* PD 9 */
  693. #define PD_MII_RXD0 ((ushort)0x0020) /* PD 10 */
  694. #define PD_MII_TX_ERR ((ushort)0x0010) /* PD 11 */
  695. #define PD_MII_MDC ((ushort)0x0008) /* PD 12 */
  696. #define PD_MII_RXD1 ((ushort)0x0004) /* PD 13 */
  697. #define PD_MII_RXD2 ((ushort)0x0002) /* PD 14 */
  698. #define PD_MII_RXD3 ((ushort)0x0001) /* PD 15 */
  699. #define PD_MII_MASK ((ushort)0x1FFF) /* PD 3...15 */
  700. #endif /* CONFIG_HERMES */
  701. /*** IAD210 **********************************************************/
  702. /* The IAD210 uses the FEC on a MPC860P for Ethernet */
  703. #if defined(CONFIG_IAD210)
  704. # define FEC_ENET /* use FEC for Ethernet */
  705. # undef SCC_ENET
  706. # define PD_MII_TXD1 ((ushort) 0x1000 ) /* PD 3 */
  707. # define PD_MII_TXD2 ((ushort) 0x0800 ) /* PD 4 */
  708. # define PD_MII_TXD3 ((ushort) 0x0400 ) /* PD 5 */
  709. # define PD_MII_RX_DV ((ushort) 0x0200 ) /* PD 6 */
  710. # define PD_MII_RX_ERR ((ushort) 0x0100 ) /* PD 7 */
  711. # define PD_MII_RX_CLK ((ushort) 0x0080 ) /* PD 8 */
  712. # define PD_MII_TXD0 ((ushort) 0x0040 ) /* PD 9 */
  713. # define PD_MII_RXD0 ((ushort) 0x0020 ) /* PD 10 */
  714. # define PD_MII_TX_ERR ((ushort) 0x0010 ) /* PD 11 */
  715. # define PD_MII_MDC ((ushort) 0x0008 ) /* PD 12 */
  716. # define PD_MII_RXD1 ((ushort) 0x0004 ) /* PD 13 */
  717. # define PD_MII_RXD2 ((ushort) 0x0002 ) /* PD 14 */
  718. # define PD_MII_RXD3 ((ushort) 0x0001 ) /* PD 15 */
  719. # define PD_MII_MASK ((ushort) 0x1FFF ) /* PD 3...15 */
  720. #endif /* CONFIG_IAD210 */
  721. /*** ICU862 **********************************************************/
  722. #if defined(CONFIG_ICU862)
  723. #ifdef CONFIG_FEC_ENET
  724. #define FEC_ENET /* use FEC for EThernet */
  725. #endif /* CONFIG_FEC_ETHERNET */
  726. #endif /* CONFIG_ICU862 */
  727. /*** IP860 **********************************************************/
  728. #if defined(CONFIG_IP860)
  729. /* Bits in parallel I/O port registers that have to be set/cleared
  730. * to configure the pins for SCC1 use.
  731. */
  732. #define PROFF_ENET PROFF_SCC1
  733. #define CPM_CR_ENET CPM_CR_CH_SCC1
  734. #define SCC_ENET 0
  735. #define PA_ENET_RXD ((ushort)0x0001) /* PA 15 */
  736. #define PA_ENET_TXD ((ushort)0x0002) /* PA 14 */
  737. #define PA_ENET_RCLK ((ushort)0x0200) /* PA 6 */
  738. #define PA_ENET_TCLK ((ushort)0x0100) /* PA 7 */
  739. #define PC_ENET_TENA ((ushort)0x0001) /* PC 15 */
  740. #define PC_ENET_CLSN ((ushort)0x0010) /* PC 11 */
  741. #define PC_ENET_RENA ((ushort)0x0020) /* PC 10 */
  742. #define PB_ENET_RESET (uint)0x00000008 /* PB 28 */
  743. #define PB_ENET_JABD (uint)0x00000004 /* PB 29 */
  744. /* Control bits in the SICR to route TCLK (CLK1) and RCLK (CLK2) to
  745. * SCC1. Also, make sure GR1 (bit 24) and SC1 (bit 25) are zero.
  746. */
  747. #define SICR_ENET_MASK ((uint)0x000000ff)
  748. #define SICR_ENET_CLKRT ((uint)0x0000002C)
  749. #endif /* CONFIG_IP860 */
  750. /*** IVMS8 **********************************************************/
  751. /* The IVMS8 uses the FEC on a MPC860T for Ethernet */
  752. #if defined(CONFIG_IVMS8) || defined(CONFIG_IVML24)
  753. #define FEC_ENET /* use FEC for EThernet */
  754. #undef SCC_ENET
  755. #define PB_ENET_POWER ((uint)0x00010000) /* PB 15 */
  756. #define PC_ENET_RESET ((ushort)0x0010) /* PC 11 */
  757. #define PD_MII_TXD1 ((ushort)0x1000) /* PD 3 */
  758. #define PD_MII_TXD2 ((ushort)0x0800) /* PD 4 */
  759. #define PD_MII_TXD3 ((ushort)0x0400) /* PD 5 */
  760. #define PD_MII_RX_DV ((ushort)0x0200) /* PD 6 */
  761. #define PD_MII_RX_ERR ((ushort)0x0100) /* PD 7 */
  762. #define PD_MII_RX_CLK ((ushort)0x0080) /* PD 8 */
  763. #define PD_MII_TXD0 ((ushort)0x0040) /* PD 9 */
  764. #define PD_MII_RXD0 ((ushort)0x0020) /* PD 10 */
  765. #define PD_MII_TX_ERR ((ushort)0x0010) /* PD 11 */
  766. #define PD_MII_MDC ((ushort)0x0008) /* PD 12 */
  767. #define PD_MII_RXD1 ((ushort)0x0004) /* PD 13 */
  768. #define PD_MII_RXD2 ((ushort)0x0002) /* PD 14 */
  769. #define PD_MII_RXD3 ((ushort)0x0001) /* PD 15 */
  770. #define PD_MII_MASK ((ushort)0x1FFF) /* PD 3...15 */
  771. #endif /* CONFIG_IVMS8, CONFIG_IVML24 */
  772. /*** KUP4K, KUP4X ****************************************************/
  773. /* The KUP4 boards uses the FEC on a MPC8xx for Ethernet */
  774. #if defined(CONFIG_KUP4K) || defined(CONFIG_KUP4X)
  775. #define FEC_ENET /* use FEC for EThernet */
  776. #undef SCC_ENET
  777. #define PB_ENET_POWER ((uint)0x00010000) /* PB 15 */
  778. #define PC_ENET_RESET ((ushort)0x0010) /* PC 11 */
  779. #define PD_MII_TXD1 ((ushort)0x1000) /* PD 3 */
  780. #define PD_MII_TXD2 ((ushort)0x0800) /* PD 4 */
  781. #define PD_MII_TXD3 ((ushort)0x0400) /* PD 5 */
  782. #define PD_MII_RX_DV ((ushort)0x0200) /* PD 6 */
  783. #define PD_MII_RX_ERR ((ushort)0x0100) /* PD 7 */
  784. #define PD_MII_RX_CLK ((ushort)0x0080) /* PD 8 */
  785. #define PD_MII_TXD0 ((ushort)0x0040) /* PD 9 */
  786. #define PD_MII_RXD0 ((ushort)0x0020) /* PD 10 */
  787. #define PD_MII_TX_ERR ((ushort)0x0010) /* PD 11 */
  788. #define PD_MII_MDC ((ushort)0x0008) /* PD 12 */
  789. #define PD_MII_RXD1 ((ushort)0x0004) /* PD 13 */
  790. #define PD_MII_RXD2 ((ushort)0x0002) /* PD 14 */
  791. #define PD_MII_RXD3 ((ushort)0x0001) /* PD 15 */
  792. #define PD_MII_MASK ((ushort)0x1FFF) /* PD 3...15 */
  793. #endif /* CONFIG_KUP4K */
  794. /*** LANTEC *********************************************************/
  795. #if defined(CONFIG_LANTEC) && CONFIG_LANTEC >= 2
  796. /* Bits in parallel I/O port registers that have to be set/cleared
  797. * to configure the pins for SCC2 use.
  798. */
  799. #define PROFF_ENET PROFF_SCC2
  800. #define CPM_CR_ENET CPM_CR_CH_SCC2
  801. #define SCC_ENET 1
  802. #define PA_ENET_RXD ((ushort)0x0004) /* PA 13 */
  803. #define PA_ENET_TXD ((ushort)0x0008) /* PA 12 */
  804. #define PA_ENET_RCLK ((ushort)0x0200) /* PA 6 */
  805. #define PA_ENET_TCLK ((ushort)0x0400) /* PA 5 */
  806. #define PB_ENET_TENA ((uint)0x00002000) /* PB 18 */
  807. #define PC_ENET_LBK ((ushort)0x0010) /* PC 11 */
  808. #define PC_ENET_CLSN ((ushort)0x0040) /* PC 9 */
  809. #define PC_ENET_RENA ((ushort)0x0080) /* PC 8 */
  810. /* Control bits in the SICR to route TCLK (CLK3) and RCLK (CLK2) to
  811. * SCC2. Also, make sure GR2 (bit 16) and SC2 (bit 17) are zero.
  812. */
  813. #define SICR_ENET_MASK ((uint)0x0000FF00)
  814. #define SICR_ENET_CLKRT ((uint)0x00002E00)
  815. #endif /* CONFIG_LANTEC v2 */
  816. /*** LWMON **********************************************************/
  817. #if defined(CONFIG_LWMON)
  818. /* Bits in parallel I/O port registers that have to be set/cleared
  819. * to configure the pins for SCC2 use.
  820. */
  821. #define PROFF_ENET PROFF_SCC2
  822. #define CPM_CR_ENET CPM_CR_CH_SCC2
  823. #define SCC_ENET 1
  824. #define PA_ENET_RXD ((ushort)0x0004) /* PA 13 */
  825. #define PA_ENET_TXD ((ushort)0x0008) /* PA 12 */
  826. #define PA_ENET_RCLK ((ushort)0x0800) /* PA 4 */
  827. #define PA_ENET_TCLK ((ushort)0x0400) /* PA 5 */
  828. #define PB_ENET_TENA ((uint)0x00002000) /* PB 18 */
  829. #define PC_ENET_CLSN ((ushort)0x0040) /* PC 9 */
  830. #define PC_ENET_RENA ((ushort)0x0080) /* PC 8 */
  831. /* Control bits in the SICR to route TCLK (CLK3) and RCLK (CLK4) to
  832. * SCC2. Also, make sure GR2 (bit 16) and SC2 (bit 17) are zero.
  833. */
  834. #define SICR_ENET_MASK ((uint)0x0000ff00)
  835. #define SICR_ENET_CLKRT ((uint)0x00003E00)
  836. #endif /* CONFIG_LWMON */
  837. /*** NX823 ***********************************************/
  838. #if defined(CONFIG_NX823)
  839. /* Bits in parallel I/O port registers that have to be set/cleared
  840. * to configure the pins for SCC1 use.
  841. */
  842. #define PROFF_ENET PROFF_SCC2
  843. #define CPM_CR_ENET CPM_CR_CH_SCC2
  844. #define SCC_ENET 1
  845. #define PA_ENET_RXD ((ushort)0x0004) /* PA 13 */
  846. #define PA_ENET_TXD ((ushort)0x0008) /* PA 12 */
  847. #define PA_ENET_RCLK ((ushort)0x0200) /* PA 6 */
  848. #define PA_ENET_TCLK ((ushort)0x0800) /* PA 4 */
  849. #define PB_ENET_TENA ((uint)0x00002000) /* PB 18 */
  850. #define PC_ENET_CLSN ((ushort)0x0040) /* PC 9 */
  851. #define PC_ENET_RENA ((ushort)0x0080) /* PC 8 */
  852. /* Control bits in the SICR to route TCLK (CLK3) and RCLK (CLK1) to
  853. * SCC2. Also, make sure GR2 (bit 16) and SC2 (bit 17) are zero.
  854. */
  855. #define SICR_ENET_MASK ((uint)0x0000ff00)
  856. #define SICR_ENET_CLKRT ((uint)0x00002f00)
  857. #endif /* CONFIG_NX823 */
  858. /*** MBX ************************************************************/
  859. #ifdef CONFIG_MBX
  860. /* Bits in parallel I/O port registers that have to be set/cleared
  861. * to configure the pins for SCC1 use. The TCLK and RCLK seem unique
  862. * to the MBX860 board. Any two of the four available clocks could be
  863. * used, and the MPC860 cookbook manual has an example using different
  864. * clock pins.
  865. */
  866. #define PROFF_ENET PROFF_SCC1
  867. #define CPM_CR_ENET CPM_CR_CH_SCC1
  868. #define SCC_ENET 0
  869. #define PA_ENET_RXD ((ushort)0x0001)
  870. #define PA_ENET_TXD ((ushort)0x0002)
  871. #define PA_ENET_TCLK ((ushort)0x0200)
  872. #define PA_ENET_RCLK ((ushort)0x0800)
  873. #define PC_ENET_TENA ((ushort)0x0001)
  874. #define PC_ENET_CLSN ((ushort)0x0010)
  875. #define PC_ENET_RENA ((ushort)0x0020)
  876. /* Control bits in the SICR to route TCLK (CLK2) and RCLK (CLK4) to
  877. * SCC1. Also, make sure GR1 (bit 24) and SC1 (bit 25) are zero.
  878. */
  879. #define SICR_ENET_MASK ((uint)0x000000ff)
  880. #define SICR_ENET_CLKRT ((uint)0x0000003d)
  881. #endif /* CONFIG_MBX */
  882. /*** KM8XX *********************************************************/
  883. /* The KM8XX Service Module uses SCC3 for Ethernet */
  884. #ifdef CONFIG_KM8XX
  885. #define PROFF_ENET PROFF_SCC3 /* Ethernet on SCC3 */
  886. #define CPM_CR_ENET CPM_CR_CH_SCC3
  887. #define SCC_ENET 2
  888. #define PA_ENET_RXD ((ushort)0x0010) /* PA 11 */
  889. #define PA_ENET_TXD ((ushort)0x0020) /* PA 10 */
  890. #define PA_ENET_RCLK ((ushort)0x1000) /* PA 3 CLK 5 */
  891. #define PA_ENET_TCLK ((ushort)0x2000) /* PA 2 CLK 6 */
  892. #define PC_ENET_TENA ((ushort)0x0004) /* PC 13 */
  893. #define PC_ENET_RENA ((ushort)0x0200) /* PC 6 */
  894. #define PC_ENET_CLSN ((ushort)0x0100) /* PC 7 */
  895. /* Control bits in the SICR to route TCLK (CLK6) and RCLK (CLK5) to
  896. * SCC3. Also, make sure GR3 (bit 8) and SC3 (bit 9) are zero.
  897. */
  898. #define SICR_ENET_MASK ((uint)0x00FF0000)
  899. #define SICR_ENET_CLKRT ((uint)0x00250000)
  900. #endif /* CONFIG_KM8XX */
  901. /*** MHPC ********************************************************/
  902. #if defined(CONFIG_MHPC)
  903. /* This ENET stuff is for the MHPC with ethernet on SCC2.
  904. * Note TENA is on Port B.
  905. */
  906. #define PROFF_ENET PROFF_SCC2
  907. #define CPM_CR_ENET CPM_CR_CH_SCC2
  908. #define SCC_ENET 1
  909. #define PA_ENET_RXD ((ushort)0x0004) /* PA 13 */
  910. #define PA_ENET_TXD ((ushort)0x0008) /* PA 12 */
  911. #define PA_ENET_RCLK ((ushort)0x0200) /* PA 6 */
  912. #define PA_ENET_TCLK ((ushort)0x0400) /* PA 5 */
  913. #define PB_ENET_TENA ((uint)0x00002000) /* PB 18 */
  914. #define PC_ENET_CLSN ((ushort)0x0040) /* PC 9 */
  915. #define PC_ENET_RENA ((ushort)0x0080) /* PC 8 */
  916. #define SICR_ENET_MASK ((uint)0x0000ff00)
  917. #define SICR_ENET_CLKRT ((uint)0x00002e00) /* RCLK-CLK2, TCLK-CLK3 */
  918. #endif /* CONFIG_MHPC */
  919. /*** NETVIA *******************************************************/
  920. /* SinoVee Microsystems SC8xx series FEL8xx-AT,SC823,SC850,SC855T,SC860T */
  921. #if ( defined CONFIG_SVM_SC8xx )
  922. # ifndef CONFIG_FEC_ENET
  923. #define PROFF_ENET PROFF_SCC2
  924. #define CPM_CR_ENET CPM_CR_CH_SCC2
  925. #define SCC_ENET 1
  926. /* Bits in parallel I/O port registers that have to be set/cleared
  927. * * * * to configure the pins for SCC2 use.
  928. * * * */
  929. #define PA_ENET_RXD ((ushort)0x0004) /* PA 13 */
  930. #define PA_ENET_TXD ((ushort)0x0008) /* PA 12 */
  931. #define PA_ENET_RCLK ((ushort)0x0400) /* PA 5 */
  932. #define PA_ENET_TCLK ((ushort)0x0800) /* PA 4 */
  933. #define PB_ENET_TENA ((uint)0x00002000) /* PB 18 */
  934. #define PC_ENET_CLSN ((ushort)0x0040) /* PC 9 */
  935. #define PC_ENET_RENA ((ushort)0x0080) /* PC 8 */
  936. /* Control bits in the SICR to route TCLK (CLK3) and RCLK (CLK1) to
  937. * * * * SCC2. Also, make sure GR2 (bit 16) and SC2 (bit 17) are zero.
  938. * * * */
  939. #define SICR_ENET_MASK ((uint)0x0000ff00)
  940. #define SICR_ENET_CLKRT ((uint)0x00003700)
  941. # else /* Use FEC for Fast Ethernet */
  942. #undef SCC_ENET
  943. #define FEC_ENET
  944. #define PD_MII_TXD1 ((ushort)0x1000) /* PD 3 */
  945. #define PD_MII_TXD2 ((ushort)0x0800) /* PD 4 */
  946. #define PD_MII_TXD3 ((ushort)0x0400) /* PD 5 */
  947. #define PD_MII_RX_DV ((ushort)0x0200) /* PD 6 */
  948. #define PD_MII_RX_ERR ((ushort)0x0100) /* PD 7 */
  949. #define PD_MII_RX_CLK ((ushort)0x0080) /* PD 8 */
  950. #define PD_MII_TXD0 ((ushort)0x0040) /* PD 9 */
  951. #define PD_MII_RXD0 ((ushort)0x0020) /* PD 10 */
  952. #define PD_MII_TX_ERR ((ushort)0x0010) /* PD 11 */
  953. #define PD_MII_MDC ((ushort)0x0008) /* PD 12 */
  954. #define PD_MII_RXD1 ((ushort)0x0004) /* PD 13 */
  955. #define PD_MII_RXD2 ((ushort)0x0002) /* PD 14 */
  956. #define PD_MII_RXD3 ((ushort)0x0001) /* PD 15 */
  957. #define PD_MII_MASK ((ushort)0x1FFF) /* PD 3...15 */
  958. # endif /* CONFIG_FEC_ENET */
  959. #endif /* CONFIG_SVM_SC8xx */
  960. #if defined(CONFIG_NETVIA)
  961. /* Bits in parallel I/O port registers that have to be set/cleared
  962. * to configure the pins for SCC2 use.
  963. */
  964. #define PROFF_ENET PROFF_SCC2
  965. #define CPM_CR_ENET CPM_CR_CH_SCC2
  966. #define SCC_ENET 1
  967. #define PA_ENET_RXD ((ushort)0x0004) /* PA 13 */
  968. #define PA_ENET_TXD ((ushort)0x0008) /* PA 12 */
  969. #define PA_ENET_RCLK ((ushort)0x0200) /* PA 6 */
  970. #define PA_ENET_TCLK ((ushort)0x0800) /* PA 4 */
  971. #if !defined(CONFIG_NETVIA_VERSION) || CONFIG_NETVIA_VERSION == 1
  972. # define PB_ENET_PDN ((ushort)0x4000) /* PB 17 */
  973. #elif CONFIG_NETVIA_VERSION >= 2
  974. # define PC_ENET_PDN ((ushort)0x0008) /* PC 12 */
  975. #endif
  976. #define PB_ENET_TENA ((ushort)0x2000) /* PB 18 */
  977. #define PC_ENET_CLSN ((ushort)0x0040) /* PC 9 */
  978. #define PC_ENET_RENA ((ushort)0x0080) /* PC 8 */
  979. /* Control bits in the SICR to route TCLK (CLK3) and RCLK (CLK1) to
  980. * SCC2. Also, make sure GR2 (bit 16) and SC2 (bit 17) are zero.
  981. */
  982. #define SICR_ENET_MASK ((uint)0x0000ff00)
  983. #define SICR_ENET_CLKRT ((uint)0x00002f00)
  984. #endif /* CONFIG_NETVIA */
  985. /*** QS850/QS823 ***************************************************/
  986. #if defined(CONFIG_QS850) || defined(CONFIG_QS823)
  987. #undef FEC_ENET /* Don't use FEC for EThernet */
  988. #define PROFF_ENET PROFF_SCC2
  989. #define CPM_CR_ENET CPM_CR_CH_SCC2
  990. #define SCC_ENET 1
  991. #define PA_ENET_RXD ((ushort)0x0004) /* RXD on PA13 (Pin D9) */
  992. #define PA_ENET_TXD ((ushort)0x0008) /* TXD on PA12 (Pin D7) */
  993. #define PC_ENET_RENA ((ushort)0x0080) /* RENA on PC8 (Pin D12) */
  994. #define PC_ENET_CLSN ((ushort)0x0040) /* CLSN on PC9 (Pin C12) */
  995. #define PA_ENET_TCLK ((ushort)0x0200) /* TCLK on PA6 (Pin D8) */
  996. #define PA_ENET_RCLK ((ushort)0x0800) /* RCLK on PA4 (Pin D10) */
  997. #define PB_ENET_TENA ((uint)0x00002000) /* TENA on PB18 (Pin D11) */
  998. #define PC_ENET_LBK ((ushort)0x0010) /* Loopback control on PC11 (Pin B14) */
  999. #define PC_ENET_LI ((ushort)0x0020) /* Link Integrity control PC10 (A15) */
  1000. #define PC_ENET_SQE ((ushort)0x0100) /* SQE Disable control PC7 (B15) */
  1001. /* SCC2 TXCLK from CLK2
  1002. * SCC2 RXCLK from CLK4
  1003. * SCC2 Connected to NMSI */
  1004. #define SICR_ENET_MASK ((uint)0x00007F00)
  1005. #define SICR_ENET_CLKRT ((uint)0x00003D00)
  1006. #endif /* CONFIG_QS850/QS823 */
  1007. /*** QS860T ***************************************************/
  1008. #ifdef CONFIG_QS860T
  1009. #ifdef CONFIG_FEC_ENET
  1010. #define FEC_ENET /* use FEC for EThernet */
  1011. #endif /* CONFIG_FEC_ETHERNET */
  1012. /* This ENET stuff is for GTH 10 Mbit ( SCC ) */
  1013. #define PROFF_ENET PROFF_SCC1
  1014. #define CPM_CR_ENET CPM_CR_CH_SCC1
  1015. #define SCC_ENET 0
  1016. #define PA_ENET_RXD ((ushort)0x0001) /* PA15 */
  1017. #define PA_ENET_TXD ((ushort)0x0002) /* PA14 */
  1018. #define PA_ENET_TCLK ((ushort)0x0800) /* PA4 */
  1019. #define PA_ENET_RCLK ((ushort)0x0200) /* PA6 */
  1020. #define PB_ENET_TENA ((uint)0x00001000) /* PB19 */
  1021. #define PC_ENET_CLSN ((ushort)0x0010) /* PC11 */
  1022. #define PC_ENET_RENA ((ushort)0x0020) /* PC10 */
  1023. #define SICR_ENET_MASK ((uint)0x000000ff)
  1024. /* RCLK PA4 -->CLK4, TCLK PA6 -->CLK2 */
  1025. #define SICR_ENET_CLKRT ((uint)0x0000003D)
  1026. #endif /* CONFIG_QS860T */
  1027. /*** RPXCLASSIC *****************************************************/
  1028. #ifdef CONFIG_RPXCLASSIC
  1029. #ifdef CONFIG_FEC_ENET
  1030. # define FEC_ENET /* use FEC for EThernet */
  1031. # undef SCC_ENET
  1032. #else /* ! CONFIG_FEC_ENET */
  1033. /* Bits in parallel I/O port registers that have to be set/cleared
  1034. * to configure the pins for SCC1 use.
  1035. */
  1036. #define PROFF_ENET PROFF_SCC1
  1037. #define CPM_CR_ENET CPM_CR_CH_SCC1
  1038. #define SCC_ENET 0
  1039. #define PA_ENET_RXD ((ushort)0x0001)
  1040. #define PA_ENET_TXD ((ushort)0x0002)
  1041. #define PA_ENET_TCLK ((ushort)0x0200)
  1042. #define PA_ENET_RCLK ((ushort)0x0800)
  1043. #define PB_ENET_TENA ((uint)0x00001000)
  1044. #define PC_ENET_CLSN ((ushort)0x0010)
  1045. #define PC_ENET_RENA ((ushort)0x0020)
  1046. /* Control bits in the SICR to route TCLK (CLK2) and RCLK (CLK4) to
  1047. * SCC1. Also, make sure GR1 (bit 24) and SC1 (bit 25) are zero.
  1048. */
  1049. #define SICR_ENET_MASK ((uint)0x000000ff)
  1050. #define SICR_ENET_CLKRT ((uint)0x0000003d)
  1051. #endif /* CONFIG_FEC_ENET */
  1052. #endif /* CONFIG_RPXCLASSIC */
  1053. /*** RPXLITE ********************************************************/
  1054. #ifdef CONFIG_RPXLITE
  1055. /* This ENET stuff is for the MPC850 with ethernet on SCC2. Some of
  1056. * this may be unique to the RPX-Lite configuration.
  1057. * Note TENA is on Port B.
  1058. */
  1059. #define PROFF_ENET PROFF_SCC2
  1060. #define CPM_CR_ENET CPM_CR_CH_SCC2
  1061. #define SCC_ENET 1
  1062. #define PA_ENET_RXD ((ushort)0x0004)
  1063. #define PA_ENET_TXD ((ushort)0x0008)
  1064. #define PA_ENET_TCLK ((ushort)0x0200)
  1065. #define PA_ENET_RCLK ((ushort)0x0800)
  1066. #if defined(CONFIG_RMU)
  1067. #define PC_ENET_TENA ((uint)0x00000002) /* PC14 */
  1068. #else
  1069. #define PB_ENET_TENA ((uint)0x00002000)
  1070. #endif
  1071. #define PC_ENET_CLSN ((ushort)0x0040)
  1072. #define PC_ENET_RENA ((ushort)0x0080)
  1073. #define SICR_ENET_MASK ((uint)0x0000ff00)
  1074. #define SICR_ENET_CLKRT ((uint)0x00003d00)
  1075. #endif /* CONFIG_RPXLITE */
  1076. /*** SM850 *********************************************************/
  1077. /* The SM850 Service Module uses SCC2 for IrDA and SCC3 for Ethernet */
  1078. #ifdef CONFIG_SM850
  1079. #define PROFF_ENET PROFF_SCC3 /* Ethernet on SCC3 */
  1080. #define CPM_CR_ENET CPM_CR_CH_SCC3
  1081. #define SCC_ENET 2
  1082. #define PB_ENET_RXD ((uint)0x00000004) /* PB 29 */
  1083. #define PB_ENET_TXD ((uint)0x00000002) /* PB 30 */
  1084. #define PA_ENET_RCLK ((ushort)0x0100) /* PA 7 */
  1085. #define PA_ENET_TCLK ((ushort)0x0400) /* PA 5 */
  1086. #define PC_ENET_LBK ((ushort)0x0008) /* PC 12 */
  1087. #define PC_ENET_TENA ((ushort)0x0004) /* PC 13 */
  1088. #define PC_ENET_RENA ((ushort)0x0800) /* PC 4 */
  1089. #define PC_ENET_CLSN ((ushort)0x0400) /* PC 5 */
  1090. /* Control bits in the SICR to route TCLK (CLK3) and RCLK (CLK1) to
  1091. * SCC3. Also, make sure GR3 (bit 8) and SC3 (bit 9) are zero.
  1092. */
  1093. #define SICR_ENET_MASK ((uint)0x00FF0000)
  1094. #define SICR_ENET_CLKRT ((uint)0x00260000)
  1095. #endif /* CONFIG_SM850 */
  1096. /*** SPD823TS ******************************************************/
  1097. #ifdef CONFIG_SPD823TS
  1098. /* Bits in parallel I/O port registers that have to be set/cleared
  1099. * to configure the pins for SCC2 use.
  1100. */
  1101. #define PROFF_ENET PROFF_SCC2 /* Ethernet on SCC2 */
  1102. #define CPM_CR_ENET CPM_CR_CH_SCC2
  1103. #define SCC_ENET 1
  1104. #define PA_ENET_MDC ((ushort)0x0001) /* PA 15 !!! */
  1105. #define PA_ENET_MDIO ((ushort)0x0002) /* PA 14 !!! */
  1106. #define PA_ENET_RXD ((ushort)0x0004) /* PA 13 */
  1107. #define PA_ENET_TXD ((ushort)0x0008) /* PA 12 */
  1108. #define PA_ENET_RCLK ((ushort)0x0200) /* PA 6 */
  1109. #define PA_ENET_TCLK ((ushort)0x0400) /* PA 5 */
  1110. #define PB_ENET_TENA ((uint)0x00002000) /* PB 18 */
  1111. #define PC_ENET_CLSN ((ushort)0x0040) /* PC 9 */
  1112. #define PC_ENET_RENA ((ushort)0x0080) /* PC 8 */
  1113. #define PC_ENET_RESET ((ushort)0x0100) /* PC 7 !!! */
  1114. /* Control bits in the SICR to route TCLK (CLK3) and RCLK (CLK2) to
  1115. * SCC2. Also, make sure GR2 (bit 16) and SC2 (bit 17) are zero.
  1116. */
  1117. #define SICR_ENET_MASK ((uint)0x0000ff00)
  1118. #define SICR_ENET_CLKRT ((uint)0x00002E00)
  1119. #endif /* CONFIG_SPD823TS */
  1120. /*** SXNI855T ******************************************************/
  1121. #if defined(CONFIG_SXNI855T)
  1122. #ifdef CONFIG_FEC_ENET
  1123. #define FEC_ENET /* use FEC for Ethernet */
  1124. #endif /* CONFIG_FEC_ETHERNET */
  1125. #endif /* CONFIG_SXNI855T */
  1126. /*** MVS1, TQM823L/M, TQM850L/M, TQM885D, ETX094, R360MPI **********/
  1127. #if (defined(CONFIG_MVS) && CONFIG_MVS < 2) || \
  1128. defined(CONFIG_R360MPI) || defined(CONFIG_RBC823) || \
  1129. defined(CONFIG_TQM823L) || defined(CONFIG_TQM823M) || \
  1130. defined(CONFIG_TQM850L) || defined(CONFIG_TQM850M) || \
  1131. defined(CONFIG_TQM885D) || defined(CONFIG_ETX094) || \
  1132. defined(CONFIG_RRVISION)|| defined(CONFIG_VIRTLAB2)|| \
  1133. (defined(CONFIG_LANTEC) && CONFIG_LANTEC < 2)
  1134. /* Bits in parallel I/O port registers that have to be set/cleared
  1135. * to configure the pins for SCC2 use.
  1136. */
  1137. #define PROFF_ENET PROFF_SCC2
  1138. #define CPM_CR_ENET CPM_CR_CH_SCC2
  1139. #if (!defined(CONFIG_TK885D)) /* TK885D does not use SCC Ethernet */
  1140. #define SCC_ENET 1
  1141. #endif
  1142. #define PA_ENET_RXD ((ushort)0x0004) /* PA 13 */
  1143. #define PA_ENET_TXD ((ushort)0x0008) /* PA 12 */
  1144. #define PA_ENET_RCLK ((ushort)0x0100) /* PA 7 */
  1145. #define PA_ENET_TCLK ((ushort)0x0400) /* PA 5 */
  1146. #define PB_ENET_TENA ((uint)0x00002000) /* PB 18 */
  1147. #define PC_ENET_CLSN ((ushort)0x0040) /* PC 9 */
  1148. #define PC_ENET_RENA ((ushort)0x0080) /* PC 8 */
  1149. #if defined(CONFIG_R360MPI)
  1150. #define PC_ENET_LBK ((ushort)0x0008) /* PC 12 */
  1151. #endif /* CONFIG_R360MPI */
  1152. /* Control bits in the SICR to route TCLK (CLK3) and RCLK (CLK1) to
  1153. * SCC2. Also, make sure GR2 (bit 16) and SC2 (bit 17) are zero.
  1154. */
  1155. #define SICR_ENET_MASK ((uint)0x0000ff00)
  1156. #define SICR_ENET_CLKRT ((uint)0x00002600)
  1157. # ifdef CONFIG_FEC_ENET /* Use FEC for Fast Ethernet */
  1158. #define FEC_ENET
  1159. # endif /* CONFIG_FEC_ENET */
  1160. #endif /* CONFIG_MVS v1, CONFIG_TQM823L/M, CONFIG_TQM850L/M, etc. */
  1161. /*** TQM855L/M, TQM860L/M, TQM862L/M, TQM866L/M *********************/
  1162. #if defined(CONFIG_TQM855L) || defined(CONFIG_TQM855M) || \
  1163. defined(CONFIG_TQM860L) || defined(CONFIG_TQM860M) || \
  1164. defined(CONFIG_TQM862L) || defined(CONFIG_TQM862M) || \
  1165. defined(CONFIG_TQM866L) || defined(CONFIG_TQM866M)
  1166. # ifdef CONFIG_SCC1_ENET /* use SCC for 10Mbps Ethernet */
  1167. /* Bits in parallel I/O port registers that have to be set/cleared
  1168. * to configure the pins for SCC1 use.
  1169. */
  1170. #define PROFF_ENET PROFF_SCC1
  1171. #define CPM_CR_ENET CPM_CR_CH_SCC1
  1172. #define SCC_ENET 0
  1173. #define PA_ENET_RXD ((ushort)0x0001) /* PA 15 */
  1174. #define PA_ENET_TXD ((ushort)0x0002) /* PA 14 */
  1175. #define PA_ENET_RCLK ((ushort)0x0100) /* PA 7 */
  1176. #define PA_ENET_TCLK ((ushort)0x0400) /* PA 5 */
  1177. #define PC_ENET_TENA ((ushort)0x0001) /* PC 15 */
  1178. #define PC_ENET_CLSN ((ushort)0x0010) /* PC 11 */
  1179. #define PC_ENET_RENA ((ushort)0x0020) /* PC 10 */
  1180. /* Control bits in the SICR to route TCLK (CLK3) and RCLK (CLK1) to
  1181. * SCC1. Also, make sure GR1 (bit 24) and SC1 (bit 25) are zero.
  1182. */
  1183. #define SICR_ENET_MASK ((uint)0x000000ff)
  1184. #define SICR_ENET_CLKRT ((uint)0x00000026)
  1185. # endif /* CONFIG_SCC1_ENET */
  1186. # ifdef CONFIG_FEC_ENET /* Use FEC for Fast Ethernet */
  1187. #define FEC_ENET
  1188. #define PD_MII_TXD1 ((ushort)0x1000) /* PD 3 */
  1189. #define PD_MII_TXD2 ((ushort)0x0800) /* PD 4 */
  1190. #define PD_MII_TXD3 ((ushort)0x0400) /* PD 5 */
  1191. #define PD_MII_RX_DV ((ushort)0x0200) /* PD 6 */
  1192. #define PD_MII_RX_ERR ((ushort)0x0100) /* PD 7 */
  1193. #define PD_MII_RX_CLK ((ushort)0x0080) /* PD 8 */
  1194. #define PD_MII_TXD0 ((ushort)0x0040) /* PD 9 */
  1195. #define PD_MII_RXD0 ((ushort)0x0020) /* PD 10 */
  1196. #define PD_MII_TX_ERR ((ushort)0x0010) /* PD 11 */
  1197. #define PD_MII_MDC ((ushort)0x0008) /* PD 12 */
  1198. #define PD_MII_RXD1 ((ushort)0x0004) /* PD 13 */
  1199. #define PD_MII_RXD2 ((ushort)0x0002) /* PD 14 */
  1200. #define PD_MII_RXD3 ((ushort)0x0001) /* PD 15 */
  1201. #define PD_MII_MASK ((ushort)0x1FFF) /* PD 3...15 */
  1202. # endif /* CONFIG_FEC_ENET */
  1203. #endif /* CONFIG_TQM855L/M, TQM860L/M, TQM862L/M */
  1204. /*** V37 **********************************************************/
  1205. #ifdef CONFIG_V37
  1206. /* This ENET stuff is for the MPC823 with ethernet on SCC2. Some of
  1207. * this may be unique to the Marel V37 configuration.
  1208. * Note TENA is on Port B.
  1209. */
  1210. #define PROFF_ENET PROFF_SCC2
  1211. #define CPM_CR_ENET CPM_CR_CH_SCC2
  1212. #define SCC_ENET 1
  1213. #define PA_ENET_RXD ((ushort)0x0004)
  1214. #define PA_ENET_TXD ((ushort)0x0008)
  1215. #define PA_ENET_TCLK ((ushort)0x0400)
  1216. #define PA_ENET_RCLK ((ushort)0x0200)
  1217. #define PB_ENET_TENA ((uint)0x00002000)
  1218. #define PC_ENET_CLSN ((ushort)0x0040)
  1219. #define PC_ENET_RENA ((ushort)0x0080)
  1220. #define SICR_ENET_MASK ((uint)0x0000ff00)
  1221. #define SICR_ENET_CLKRT ((uint)0x00002e00)
  1222. #endif /* CONFIG_V37 */
  1223. /*********************************************************************/
  1224. /* SCC Event register as used by Ethernet.
  1225. */
  1226. #define SCCE_ENET_GRA ((ushort)0x0080) /* Graceful stop complete */
  1227. #define SCCE_ENET_TXE ((ushort)0x0010) /* Transmit Error */
  1228. #define SCCE_ENET_RXF ((ushort)0x0008) /* Full frame received */
  1229. #define SCCE_ENET_BSY ((ushort)0x0004) /* All incoming buffers full */
  1230. #define SCCE_ENET_TXB ((ushort)0x0002) /* A buffer was transmitted */
  1231. #define SCCE_ENET_RXB ((ushort)0x0001) /* A buffer was received */
  1232. /* SCC Mode Register (PSMR) as used by Ethernet.
  1233. */
  1234. #define SCC_PSMR_HBC ((ushort)0x8000) /* Enable heartbeat */
  1235. #define SCC_PSMR_FC ((ushort)0x4000) /* Force collision */
  1236. #define SCC_PSMR_RSH ((ushort)0x2000) /* Receive short frames */
  1237. #define SCC_PSMR_IAM ((ushort)0x1000) /* Check individual hash */
  1238. #define SCC_PSMR_ENCRC ((ushort)0x0800) /* Ethernet CRC mode */
  1239. #define SCC_PSMR_PRO ((ushort)0x0200) /* Promiscuous mode */
  1240. #define SCC_PSMR_BRO ((ushort)0x0100) /* Catch broadcast pkts */
  1241. #define SCC_PSMR_SBT ((ushort)0x0080) /* Special backoff timer */
  1242. #define SCC_PSMR_LPB ((ushort)0x0040) /* Set Loopback mode */
  1243. #define SCC_PSMR_SIP ((ushort)0x0020) /* Sample Input Pins */
  1244. #define SCC_PSMR_LCW ((ushort)0x0010) /* Late collision window */
  1245. #define SCC_PSMR_NIB22 ((ushort)0x000a) /* Start frame search */
  1246. #define SCC_PSMR_FDE ((ushort)0x0001) /* Full duplex enable */
  1247. /* Buffer descriptor control/status used by Ethernet receive.
  1248. */
  1249. #define BD_ENET_RX_EMPTY ((ushort)0x8000)
  1250. #define BD_ENET_RX_WRAP ((ushort)0x2000)
  1251. #define BD_ENET_RX_INTR ((ushort)0x1000)
  1252. #define BD_ENET_RX_LAST ((ushort)0x0800)
  1253. #define BD_ENET_RX_FIRST ((ushort)0x0400)
  1254. #define BD_ENET_RX_MISS ((ushort)0x0100)
  1255. #define BD_ENET_RX_LG ((ushort)0x0020)
  1256. #define BD_ENET_RX_NO ((ushort)0x0010)
  1257. #define BD_ENET_RX_SH ((ushort)0x0008)
  1258. #define BD_ENET_RX_CR ((ushort)0x0004)
  1259. #define BD_ENET_RX_OV ((ushort)0x0002)
  1260. #define BD_ENET_RX_CL ((ushort)0x0001)
  1261. #define BD_ENET_RX_STATS ((ushort)0x013f) /* All status bits */
  1262. /* Buffer descriptor control/status used by Ethernet transmit.
  1263. */
  1264. #define BD_ENET_TX_READY ((ushort)0x8000)
  1265. #define BD_ENET_TX_PAD ((ushort)0x4000)
  1266. #define BD_ENET_TX_WRAP ((ushort)0x2000)
  1267. #define BD_ENET_TX_INTR ((ushort)0x1000)
  1268. #define BD_ENET_TX_LAST ((ushort)0x0800)
  1269. #define BD_ENET_TX_TC ((ushort)0x0400)
  1270. #define BD_ENET_TX_DEF ((ushort)0x0200)
  1271. #define BD_ENET_TX_HB ((ushort)0x0100)
  1272. #define BD_ENET_TX_LC ((ushort)0x0080)
  1273. #define BD_ENET_TX_RL ((ushort)0x0040)
  1274. #define BD_ENET_TX_RCMASK ((ushort)0x003c)
  1275. #define BD_ENET_TX_UN ((ushort)0x0002)
  1276. #define BD_ENET_TX_CSL ((ushort)0x0001)
  1277. #define BD_ENET_TX_STATS ((ushort)0x03ff) /* All status bits */
  1278. /* SCC as UART
  1279. */
  1280. typedef struct scc_uart {
  1281. sccp_t scc_genscc;
  1282. uint scc_res1; /* Reserved */
  1283. uint scc_res2; /* Reserved */
  1284. ushort scc_maxidl; /* Maximum idle chars */
  1285. ushort scc_idlc; /* temp idle counter */
  1286. ushort scc_brkcr; /* Break count register */
  1287. ushort scc_parec; /* receive parity error counter */
  1288. ushort scc_frmec; /* receive framing error counter */
  1289. ushort scc_nosec; /* receive noise counter */
  1290. ushort scc_brkec; /* receive break condition counter */
  1291. ushort scc_brkln; /* last received break length */
  1292. ushort scc_uaddr1; /* UART address character 1 */
  1293. ushort scc_uaddr2; /* UART address character 2 */
  1294. ushort scc_rtemp; /* Temp storage */
  1295. ushort scc_toseq; /* Transmit out of sequence char */
  1296. ushort scc_char1; /* control character 1 */
  1297. ushort scc_char2; /* control character 2 */
  1298. ushort scc_char3; /* control character 3 */
  1299. ushort scc_char4; /* control character 4 */
  1300. ushort scc_char5; /* control character 5 */
  1301. ushort scc_char6; /* control character 6 */
  1302. ushort scc_char7; /* control character 7 */
  1303. ushort scc_char8; /* control character 8 */
  1304. ushort scc_rccm; /* receive control character mask */
  1305. ushort scc_rccr; /* receive control character register */
  1306. ushort scc_rlbc; /* receive last break character */
  1307. } scc_uart_t;
  1308. /* SCC Event and Mask registers when it is used as a UART.
  1309. */
  1310. #define UART_SCCM_GLR ((ushort)0x1000)
  1311. #define UART_SCCM_GLT ((ushort)0x0800)
  1312. #define UART_SCCM_AB ((ushort)0x0200)
  1313. #define UART_SCCM_IDL ((ushort)0x0100)
  1314. #define UART_SCCM_GRA ((ushort)0x0080)
  1315. #define UART_SCCM_BRKE ((ushort)0x0040)
  1316. #define UART_SCCM_BRKS ((ushort)0x0020)
  1317. #define UART_SCCM_CCR ((ushort)0x0008)
  1318. #define UART_SCCM_BSY ((ushort)0x0004)
  1319. #define UART_SCCM_TX ((ushort)0x0002)
  1320. #define UART_SCCM_RX ((ushort)0x0001)
  1321. /* The SCC PSMR when used as a UART.
  1322. */
  1323. #define SCU_PSMR_FLC ((ushort)0x8000)
  1324. #define SCU_PSMR_SL ((ushort)0x4000)
  1325. #define SCU_PSMR_CL ((ushort)0x3000)
  1326. #define SCU_PSMR_UM ((ushort)0x0c00)
  1327. #define SCU_PSMR_FRZ ((ushort)0x0200)
  1328. #define SCU_PSMR_RZS ((ushort)0x0100)
  1329. #define SCU_PSMR_SYN ((ushort)0x0080)
  1330. #define SCU_PSMR_DRT ((ushort)0x0040)
  1331. #define SCU_PSMR_PEN ((ushort)0x0010)
  1332. #define SCU_PSMR_RPM ((ushort)0x000c)
  1333. #define SCU_PSMR_REVP ((ushort)0x0008)
  1334. #define SCU_PSMR_TPM ((ushort)0x0003)
  1335. #define SCU_PSMR_TEVP ((ushort)0x0003)
  1336. /* CPM Transparent mode SCC.
  1337. */
  1338. typedef struct scc_trans {
  1339. sccp_t st_genscc;
  1340. uint st_cpres; /* Preset CRC */
  1341. uint st_cmask; /* Constant mask for CRC */
  1342. } scc_trans_t;
  1343. #define BD_SCC_TX_LAST ((ushort)0x0800)
  1344. /* IIC parameter RAM.
  1345. */
  1346. typedef struct iic {
  1347. ushort iic_rbase; /* Rx Buffer descriptor base address */
  1348. ushort iic_tbase; /* Tx Buffer descriptor base address */
  1349. u_char iic_rfcr; /* Rx function code */
  1350. u_char iic_tfcr; /* Tx function code */
  1351. ushort iic_mrblr; /* Max receive buffer length */
  1352. uint iic_rstate; /* Internal */
  1353. uint iic_rdp; /* Internal */
  1354. ushort iic_rbptr; /* Internal */
  1355. ushort iic_rbc; /* Internal */
  1356. uint iic_rxtmp; /* Internal */
  1357. uint iic_tstate; /* Internal */
  1358. uint iic_tdp; /* Internal */
  1359. ushort iic_tbptr; /* Internal */
  1360. ushort iic_tbc; /* Internal */
  1361. uint iic_txtmp; /* Internal */
  1362. uint iic_res; /* reserved */
  1363. ushort iic_rpbase; /* Relocation pointer */
  1364. ushort iic_res2; /* reserved */
  1365. } iic_t;
  1366. /* SPI parameter RAM.
  1367. */
  1368. typedef struct spi {
  1369. ushort spi_rbase; /* Rx Buffer descriptor base address */
  1370. ushort spi_tbase; /* Tx Buffer descriptor base address */
  1371. u_char spi_rfcr; /* Rx function code */
  1372. u_char spi_tfcr; /* Tx function code */
  1373. ushort spi_mrblr; /* Max receive buffer length */
  1374. uint spi_rstate; /* Internal */
  1375. uint spi_rdp; /* Internal */
  1376. ushort spi_rbptr; /* Internal */
  1377. ushort spi_rbc; /* Internal */
  1378. uint spi_rxtmp; /* Internal */
  1379. uint spi_tstate; /* Internal */
  1380. uint spi_tdp; /* Internal */
  1381. ushort spi_tbptr; /* Internal */
  1382. ushort spi_tbc; /* Internal */
  1383. uint spi_txtmp; /* Internal */
  1384. uint spi_res;
  1385. ushort spi_rpbase; /* Relocation pointer */
  1386. ushort spi_res2;
  1387. } spi_t;
  1388. /* SPI Mode register.
  1389. */
  1390. #define SPMODE_LOOP ((ushort)0x4000) /* Loopback */
  1391. #define SPMODE_CI ((ushort)0x2000) /* Clock Invert */
  1392. #define SPMODE_CP ((ushort)0x1000) /* Clock Phase */
  1393. #define SPMODE_DIV16 ((ushort)0x0800) /* BRG/16 mode */
  1394. #define SPMODE_REV ((ushort)0x0400) /* Reversed Data */
  1395. #define SPMODE_MSTR ((ushort)0x0200) /* SPI Master */
  1396. #define SPMODE_EN ((ushort)0x0100) /* Enable */
  1397. #define SPMODE_LENMSK ((ushort)0x00f0) /* character length */
  1398. #define SPMODE_PMMSK ((ushort)0x000f) /* prescale modulus */
  1399. #define SPMODE_LEN(x) ((((x)-1)&0xF)<<4)
  1400. #define SPMODE_PM(x) ((x) &0xF)
  1401. /* HDLC parameter RAM.
  1402. */
  1403. typedef struct hdlc_pram_s {
  1404. /*
  1405. * SCC parameter RAM
  1406. */
  1407. ushort rbase; /* Rx Buffer descriptor base address */
  1408. ushort tbase; /* Tx Buffer descriptor base address */
  1409. uchar rfcr; /* Rx function code */
  1410. uchar tfcr; /* Tx function code */
  1411. ushort mrblr; /* Rx buffer length */
  1412. ulong rstate; /* Rx internal state */
  1413. ulong rptr; /* Rx internal data pointer */
  1414. ushort rbptr; /* rb BD Pointer */
  1415. ushort rcount; /* Rx internal byte count */
  1416. ulong rtemp; /* Rx temp */
  1417. ulong tstate; /* Tx internal state */
  1418. ulong tptr; /* Tx internal data pointer */
  1419. ushort tbptr; /* Tx BD pointer */
  1420. ushort tcount; /* Tx byte count */
  1421. ulong ttemp; /* Tx temp */
  1422. ulong rcrc; /* temp receive CRC */
  1423. ulong tcrc; /* temp transmit CRC */
  1424. /*
  1425. * HDLC specific parameter RAM
  1426. */
  1427. uchar res[4]; /* reserved */
  1428. ulong c_mask; /* CRC constant */
  1429. ulong c_pres; /* CRC preset */
  1430. ushort disfc; /* discarded frame counter */
  1431. ushort crcec; /* CRC error counter */
  1432. ushort abtsc; /* abort sequence counter */
  1433. ushort nmarc; /* nonmatching address rx cnt */
  1434. ushort retrc; /* frame retransmission cnt */
  1435. ushort mflr; /* maximum frame length reg */
  1436. ushort max_cnt; /* maximum length counter */
  1437. ushort rfthr; /* received frames threshold */
  1438. ushort rfcnt; /* received frames count */
  1439. ushort hmask; /* user defined frm addr mask */
  1440. ushort haddr1; /* user defined frm address 1 */
  1441. ushort haddr2; /* user defined frm address 2 */
  1442. ushort haddr3; /* user defined frm address 3 */
  1443. ushort haddr4; /* user defined frm address 4 */
  1444. ushort tmp; /* temp */
  1445. ushort tmp_mb; /* temp */
  1446. } hdlc_pram_t;
  1447. /* CPM interrupts. There are nearly 32 interrupts generated by CPM
  1448. * channels or devices. All of these are presented to the PPC core
  1449. * as a single interrupt. The CPM interrupt handler dispatches its
  1450. * own handlers, in a similar fashion to the PPC core handler. We
  1451. * use the table as defined in the manuals (i.e. no special high
  1452. * priority and SCC1 == SCCa, etc...).
  1453. */
  1454. #define CPMVEC_NR 32
  1455. #define CPMVEC_OFFSET 0x00010000
  1456. #define CPMVEC_PIO_PC15 ((ushort)0x1f | CPMVEC_OFFSET)
  1457. #define CPMVEC_SCC1 ((ushort)0x1e | CPMVEC_OFFSET)
  1458. #define CPMVEC_SCC2 ((ushort)0x1d | CPMVEC_OFFSET)
  1459. #define CPMVEC_SCC3 ((ushort)0x1c | CPMVEC_OFFSET)
  1460. #define CPMVEC_SCC4 ((ushort)0x1b | CPMVEC_OFFSET)
  1461. #define CPMVEC_PIO_PC14 ((ushort)0x1a | CPMVEC_OFFSET)
  1462. #define CPMVEC_TIMER1 ((ushort)0x19 | CPMVEC_OFFSET)
  1463. #define CPMVEC_PIO_PC13 ((ushort)0x18 | CPMVEC_OFFSET)
  1464. #define CPMVEC_PIO_PC12 ((ushort)0x17 | CPMVEC_OFFSET)
  1465. #define CPMVEC_SDMA_CB_ERR ((ushort)0x16 | CPMVEC_OFFSET)
  1466. #define CPMVEC_IDMA1 ((ushort)0x15 | CPMVEC_OFFSET)
  1467. #define CPMVEC_IDMA2 ((ushort)0x14 | CPMVEC_OFFSET)
  1468. #define CPMVEC_TIMER2 ((ushort)0x12 | CPMVEC_OFFSET)
  1469. #define CPMVEC_RISCTIMER ((ushort)0x11 | CPMVEC_OFFSET)
  1470. #define CPMVEC_I2C ((ushort)0x10 | CPMVEC_OFFSET)
  1471. #define CPMVEC_PIO_PC11 ((ushort)0x0f | CPMVEC_OFFSET)
  1472. #define CPMVEC_PIO_PC10 ((ushort)0x0e | CPMVEC_OFFSET)
  1473. #define CPMVEC_TIMER3 ((ushort)0x0c | CPMVEC_OFFSET)
  1474. #define CPMVEC_PIO_PC9 ((ushort)0x0b | CPMVEC_OFFSET)
  1475. #define CPMVEC_PIO_PC8 ((ushort)0x0a | CPMVEC_OFFSET)
  1476. #define CPMVEC_PIO_PC7 ((ushort)0x09 | CPMVEC_OFFSET)
  1477. #define CPMVEC_TIMER4 ((ushort)0x07 | CPMVEC_OFFSET)
  1478. #define CPMVEC_PIO_PC6 ((ushort)0x06 | CPMVEC_OFFSET)
  1479. #define CPMVEC_SPI ((ushort)0x05 | CPMVEC_OFFSET)
  1480. #define CPMVEC_SMC1 ((ushort)0x04 | CPMVEC_OFFSET)
  1481. #define CPMVEC_SMC2 ((ushort)0x03 | CPMVEC_OFFSET)
  1482. #define CPMVEC_PIO_PC5 ((ushort)0x02 | CPMVEC_OFFSET)
  1483. #define CPMVEC_PIO_PC4 ((ushort)0x01 | CPMVEC_OFFSET)
  1484. #define CPMVEC_ERROR ((ushort)0x00 | CPMVEC_OFFSET)
  1485. extern void irq_install_handler(int vec, void (*handler)(void *), void *dev_id);
  1486. /* CPM interrupt configuration vector.
  1487. */
  1488. #define CICR_SCD_SCC4 ((uint)0x00c00000) /* SCC4 @ SCCd */
  1489. #define CICR_SCC_SCC3 ((uint)0x00200000) /* SCC3 @ SCCc */
  1490. #define CICR_SCB_SCC2 ((uint)0x00040000) /* SCC2 @ SCCb */
  1491. #define CICR_SCA_SCC1 ((uint)0x00000000) /* SCC1 @ SCCa */
  1492. #define CICR_IRL_MASK ((uint)0x0000e000) /* Core interrrupt */
  1493. #define CICR_HP_MASK ((uint)0x00001f00) /* Hi-pri int. */
  1494. #define CICR_IEN ((uint)0x00000080) /* Int. enable */
  1495. #define CICR_SPS ((uint)0x00000001) /* SCC Spread */
  1496. #endif /* __CPM_8XX__ */