cpm_8260.h 30 KB

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  1. /*
  2. * MPC8260 Communication Processor Module.
  3. * Copyright (c) 1999 Dan Malek (dmalek@jlc.net)
  4. *
  5. * This file contains structures and information for the communication
  6. * processor channels found in the dual port RAM or parameter RAM.
  7. * All CPM control and status is available through the MPC8260 internal
  8. * memory map. See immap.h for details.
  9. */
  10. #ifndef __CPM_82XX__
  11. #define __CPM_82XX__
  12. #include <asm/immap_8260.h>
  13. /* CPM Command register.
  14. */
  15. #define CPM_CR_RST ((uint)0x80000000)
  16. #define CPM_CR_PAGE ((uint)0x7c000000)
  17. #define CPM_CR_SBLOCK ((uint)0x03e00000)
  18. #define CPM_CR_FLG ((uint)0x00010000)
  19. #define CPM_CR_MCN ((uint)0x00003fc0)
  20. #define CPM_CR_OPCODE ((uint)0x0000000f)
  21. /* Device sub-block and page codes.
  22. */
  23. #define CPM_CR_SCC1_SBLOCK (0x04)
  24. #define CPM_CR_SCC2_SBLOCK (0x05)
  25. #define CPM_CR_SCC3_SBLOCK (0x06)
  26. #define CPM_CR_SCC4_SBLOCK (0x07)
  27. #define CPM_CR_SMC1_SBLOCK (0x08)
  28. #define CPM_CR_SMC2_SBLOCK (0x09)
  29. #define CPM_CR_SPI_SBLOCK (0x0a)
  30. #define CPM_CR_I2C_SBLOCK (0x0b)
  31. #define CPM_CR_TIMER_SBLOCK (0x0f)
  32. #define CPM_CR_RAND_SBLOCK (0x0e)
  33. #define CPM_CR_FCC1_SBLOCK (0x10)
  34. #define CPM_CR_FCC2_SBLOCK (0x11)
  35. #define CPM_CR_FCC3_SBLOCK (0x12)
  36. #define CPM_CR_IDMA1_SBLOCK (0x14)
  37. #define CPM_CR_IDMA2_SBLOCK (0x15)
  38. #define CPM_CR_IDMA3_SBLOCK (0x16)
  39. #define CPM_CR_IDMA4_SBLOCK (0x17)
  40. #define CPM_CR_MCC1_SBLOCK (0x1c)
  41. #define CPM_CR_SCC1_PAGE (0x00)
  42. #define CPM_CR_SCC2_PAGE (0x01)
  43. #define CPM_CR_SCC3_PAGE (0x02)
  44. #define CPM_CR_SCC4_PAGE (0x03)
  45. #define CPM_CR_SMC1_PAGE (0x07)
  46. #define CPM_CR_SMC2_PAGE (0x08)
  47. #define CPM_CR_SPI_PAGE (0x09)
  48. #define CPM_CR_I2C_PAGE (0x0a)
  49. #define CPM_CR_TIMER_PAGE (0x0a)
  50. #define CPM_CR_RAND_PAGE (0x0a)
  51. #define CPM_CR_FCC1_PAGE (0x04)
  52. #define CPM_CR_FCC2_PAGE (0x05)
  53. #define CPM_CR_FCC3_PAGE (0x06)
  54. #define CPM_CR_IDMA1_PAGE (0x07)
  55. #define CPM_CR_IDMA2_PAGE (0x08)
  56. #define CPM_CR_IDMA3_PAGE (0x09)
  57. #define CPM_CR_IDMA4_PAGE (0x0a)
  58. #define CPM_CR_MCC1_PAGE (0x07)
  59. #define CPM_CR_MCC2_PAGE (0x08)
  60. /* Some opcodes (there are more...later)
  61. */
  62. #define CPM_CR_INIT_TRX ((ushort)0x0000)
  63. #define CPM_CR_INIT_RX ((ushort)0x0001)
  64. #define CPM_CR_INIT_TX ((ushort)0x0002)
  65. #define CPM_CR_HUNT_MODE ((ushort)0x0003)
  66. #define CPM_CR_STOP_TX ((ushort)0x0004)
  67. #define CPM_CR_RESTART_TX ((ushort)0x0006)
  68. #define CPM_CR_SET_GADDR ((ushort)0x0008)
  69. #define mk_cr_cmd(PG, SBC, MCN, OP) \
  70. ((PG << 26) | (SBC << 21) | (MCN << 6) | OP)
  71. /* Dual Port RAM addresses. The first 16K is available for almost
  72. * any CPM use, so we put the BDs there. The first 128 bytes are
  73. * used for SMC1 and SMC2 parameter RAM, so we start allocating
  74. * BDs above that. All of this must change when we start
  75. * downloading RAM microcode.
  76. */
  77. #define CPM_DATAONLY_BASE ((uint)128)
  78. #define CPM_DP_NOSPACE ((uint)0x7fffffff)
  79. #ifndef CONFIG_MPC8272_FAMILY
  80. #define CPM_DATAONLY_SIZE ((uint)(8 * 1024) - CPM_DATAONLY_BASE)
  81. #define CPM_FCC_SPECIAL_BASE ((uint)0x0000b000)
  82. #else /* 8247/48/71/72 */
  83. #define CPM_DATAONLY_SIZE ((uint)(4 * 1024) - CPM_DATAONLY_BASE)
  84. #define CPM_FCC_SPECIAL_BASE ((uint)0x00009000)
  85. #endif /* !CONFIG_MPC8272_FAMILY */
  86. /* The number of pages of host memory we allocate for CPM. This is
  87. * done early in kernel initialization to get physically contiguous
  88. * pages.
  89. */
  90. #define NUM_CPM_HOST_PAGES 2
  91. /* Export the base address of the communication processor registers
  92. * and dual port ram.
  93. */
  94. extern cpm8260_t *cpmp; /* Pointer to comm processor */
  95. uint m8260_cpm_dpalloc(uint size, uint align);
  96. uint m8260_cpm_hostalloc(uint size, uint align);
  97. void m8260_cpm_setbrg(uint brg, uint rate);
  98. void m8260_cpm_fastbrg(uint brg, uint rate, int div16);
  99. void m8260_cpm_extcbrg(uint brg, uint rate, uint extclk, int pinsel);
  100. /* Buffer descriptors used by many of the CPM protocols.
  101. */
  102. typedef struct cpm_buf_desc {
  103. ushort cbd_sc; /* Status and Control */
  104. ushort cbd_datlen; /* Data length in buffer */
  105. uint cbd_bufaddr; /* Buffer address in host memory */
  106. } cbd_t;
  107. #define BD_SC_EMPTY ((ushort)0x8000) /* Receive is empty */
  108. #define BD_SC_READY ((ushort)0x8000) /* Transmit is ready */
  109. #define BD_SC_WRAP ((ushort)0x2000) /* Last buffer descriptor */
  110. #define BD_SC_INTRPT ((ushort)0x1000) /* Interrupt on change */
  111. #define BD_SC_LAST ((ushort)0x0800) /* Last buffer in frame */
  112. #define BD_SC_CM ((ushort)0x0200) /* Continous mode */
  113. #define BD_SC_ID ((ushort)0x0100) /* Rec'd too many idles */
  114. #define BD_SC_P ((ushort)0x0100) /* xmt preamble */
  115. #define BD_SC_BR ((ushort)0x0020) /* Break received */
  116. #define BD_SC_FR ((ushort)0x0010) /* Framing error */
  117. #define BD_SC_PR ((ushort)0x0008) /* Parity error */
  118. #define BD_SC_OV ((ushort)0x0002) /* Overrun */
  119. #define BD_SC_CD ((ushort)0x0001) /* ?? */
  120. /* Function code bits, usually generic to devices.
  121. */
  122. #define CPMFCR_GBL ((u_char)0x20) /* Set memory snooping */
  123. #define CPMFCR_EB ((u_char)0x10) /* Set big endian byte order */
  124. #define CPMFCR_TC2 ((u_char)0x04) /* Transfer code 2 value */
  125. #define CPMFCR_DTB ((u_char)0x02) /* Use local bus for data when set */
  126. #define CPMFCR_BDB ((u_char)0x01) /* Use local bus for BD when set */
  127. /* Parameter RAM offsets from the base.
  128. */
  129. #ifndef CONFIG_SYS_CPM_POST_WORD_ADDR
  130. #define CPM_POST_WORD_ADDR 0x80FC /* steal a long at the end of SCC1 */
  131. #else
  132. #define CPM_POST_WORD_ADDR CONFIG_SYS_CPM_POST_WORD_ADDR
  133. #endif
  134. #ifndef CONFIG_SYS_CPM_BOOTCOUNT_ADDR
  135. #define CPM_BOOTCOUNT_ADDR (CPM_POST_WORD_ADDR - 2*sizeof(ulong))
  136. #else
  137. #define CPM_BOOTCOUNT_ADDR CONFIG_SYS_CPM_BOOTCOUNT_ADDR
  138. #endif
  139. #define PROFF_SCC1 ((uint)0x8000)
  140. #define PROFF_SCC2 ((uint)0x8100)
  141. #define PROFF_SCC3 ((uint)0x8200)
  142. #define PROFF_SCC4 ((uint)0x8300)
  143. #define PROFF_FCC1 ((uint)0x8400)
  144. #define PROFF_FCC2 ((uint)0x8500)
  145. #define PROFF_FCC3 ((uint)0x8600)
  146. #define PROFF_MCC1 ((uint)0x8700)
  147. #define PROFF_SMC1_BASE ((uint)0x87fc)
  148. #define PROFF_IDMA1_BASE ((uint)0x87fe)
  149. #define PROFF_MCC2 ((uint)0x8800)
  150. #define PROFF_SMC2_BASE ((uint)0x88fc)
  151. #define PROFF_IDMA2_BASE ((uint)0x88fe)
  152. #define PROFF_SPI_BASE ((uint)0x89fc)
  153. #define PROFF_IDMA3_BASE ((uint)0x89fe)
  154. #define PROFF_TIMERS ((uint)0x8ae0)
  155. #define PROFF_REVNUM ((uint)0x8af0)
  156. #define PROFF_RAND ((uint)0x8af8)
  157. #define PROFF_I2C_BASE ((uint)0x8afc)
  158. #define PROFF_IDMA4_BASE ((uint)0x8afe)
  159. /* The SMCs are relocated to any of the first eight DPRAM pages.
  160. * We will fix these at the first locations of DPRAM, until we
  161. * get some microcode patches :-).
  162. * The parameter ram space for the SMCs is fifty-some bytes, and
  163. * they are required to start on a 64 byte boundary.
  164. */
  165. #define PROFF_SMC1 (0)
  166. #define PROFF_SMC2 (64)
  167. #define PROFF_SPI ((16*1024) - 128)
  168. /* Define enough so I can at least use the serial port as a UART.
  169. */
  170. typedef struct smc_uart {
  171. ushort smc_rbase; /* Rx Buffer descriptor base address */
  172. ushort smc_tbase; /* Tx Buffer descriptor base address */
  173. u_char smc_rfcr; /* Rx function code */
  174. u_char smc_tfcr; /* Tx function code */
  175. ushort smc_mrblr; /* Max receive buffer length */
  176. uint smc_rstate; /* Internal */
  177. uint smc_idp; /* Internal */
  178. ushort smc_rbptr; /* Internal */
  179. ushort smc_ibc; /* Internal */
  180. uint smc_rxtmp; /* Internal */
  181. uint smc_tstate; /* Internal */
  182. uint smc_tdp; /* Internal */
  183. ushort smc_tbptr; /* Internal */
  184. ushort smc_tbc; /* Internal */
  185. uint smc_txtmp; /* Internal */
  186. ushort smc_maxidl; /* Maximum idle characters */
  187. ushort smc_tmpidl; /* Temporary idle counter */
  188. ushort smc_brklen; /* Last received break length */
  189. ushort smc_brkec; /* rcv'd break condition counter */
  190. ushort smc_brkcr; /* xmt break count register */
  191. ushort smc_rmask; /* Temporary bit mask */
  192. uint smc_stmp; /* SDMA Temp */
  193. } smc_uart_t;
  194. /* SMC uart mode register (Internal memory map).
  195. */
  196. #define SMCMR_REN ((ushort)0x0001)
  197. #define SMCMR_TEN ((ushort)0x0002)
  198. #define SMCMR_DM ((ushort)0x000c)
  199. #define SMCMR_SM_GCI ((ushort)0x0000)
  200. #define SMCMR_SM_UART ((ushort)0x0020)
  201. #define SMCMR_SM_TRANS ((ushort)0x0030)
  202. #define SMCMR_SM_MASK ((ushort)0x0030)
  203. #define SMCMR_PM_EVEN ((ushort)0x0100) /* Even parity, else odd */
  204. #define SMCMR_REVD SMCMR_PM_EVEN
  205. #define SMCMR_PEN ((ushort)0x0200) /* Parity enable */
  206. #define SMCMR_BS SMCMR_PEN
  207. #define SMCMR_SL ((ushort)0x0400) /* Two stops, else one */
  208. #define SMCR_CLEN_MASK ((ushort)0x7800) /* Character length */
  209. #define smcr_mk_clen(C) (((C) << 11) & SMCR_CLEN_MASK)
  210. /* SMC Event and Mask register.
  211. */
  212. #define SMCM_TXE ((unsigned char)0x10)
  213. #define SMCM_BSY ((unsigned char)0x04)
  214. #define SMCM_TX ((unsigned char)0x02)
  215. #define SMCM_RX ((unsigned char)0x01)
  216. /* Baud rate generators.
  217. */
  218. #define CPM_BRG_RST ((uint)0x00020000)
  219. #define CPM_BRG_EN ((uint)0x00010000)
  220. #define CPM_BRG_EXTC_INT ((uint)0x00000000)
  221. #define CPM_BRG_EXTC_CLK3_9 ((uint)0x00004000)
  222. #define CPM_BRG_EXTC_CLK5_15 ((uint)0x00008000)
  223. #define CPM_BRG_ATB ((uint)0x00002000)
  224. #define CPM_BRG_CD_MASK ((uint)0x00001ffe)
  225. #define CPM_BRG_DIV16 ((uint)0x00000001)
  226. /* SCCs.
  227. */
  228. #define SCC_GSMRH_IRP ((uint)0x00040000)
  229. #define SCC_GSMRH_GDE ((uint)0x00010000)
  230. #define SCC_GSMRH_TCRC_CCITT ((uint)0x00008000)
  231. #define SCC_GSMRH_TCRC_BISYNC ((uint)0x00004000)
  232. #define SCC_GSMRH_TCRC_HDLC ((uint)0x00000000)
  233. #define SCC_GSMRH_REVD ((uint)0x00002000)
  234. #define SCC_GSMRH_TRX ((uint)0x00001000)
  235. #define SCC_GSMRH_TTX ((uint)0x00000800)
  236. #define SCC_GSMRH_CDP ((uint)0x00000400)
  237. #define SCC_GSMRH_CTSP ((uint)0x00000200)
  238. #define SCC_GSMRH_CDS ((uint)0x00000100)
  239. #define SCC_GSMRH_CTSS ((uint)0x00000080)
  240. #define SCC_GSMRH_TFL ((uint)0x00000040)
  241. #define SCC_GSMRH_RFW ((uint)0x00000020)
  242. #define SCC_GSMRH_TXSY ((uint)0x00000010)
  243. #define SCC_GSMRH_SYNL16 ((uint)0x0000000c)
  244. #define SCC_GSMRH_SYNL8 ((uint)0x00000008)
  245. #define SCC_GSMRH_SYNL4 ((uint)0x00000004)
  246. #define SCC_GSMRH_RTSM ((uint)0x00000002)
  247. #define SCC_GSMRH_RSYN ((uint)0x00000001)
  248. #define SCC_GSMRL_SIR ((uint)0x80000000) /* SCC2 only */
  249. #define SCC_GSMRL_EDGE_NONE ((uint)0x60000000)
  250. #define SCC_GSMRL_EDGE_NEG ((uint)0x40000000)
  251. #define SCC_GSMRL_EDGE_POS ((uint)0x20000000)
  252. #define SCC_GSMRL_EDGE_BOTH ((uint)0x00000000)
  253. #define SCC_GSMRL_TCI ((uint)0x10000000)
  254. #define SCC_GSMRL_TSNC_3 ((uint)0x0c000000)
  255. #define SCC_GSMRL_TSNC_4 ((uint)0x08000000)
  256. #define SCC_GSMRL_TSNC_14 ((uint)0x04000000)
  257. #define SCC_GSMRL_TSNC_INF ((uint)0x00000000)
  258. #define SCC_GSMRL_RINV ((uint)0x02000000)
  259. #define SCC_GSMRL_TINV ((uint)0x01000000)
  260. #define SCC_GSMRL_TPL_128 ((uint)0x00c00000)
  261. #define SCC_GSMRL_TPL_64 ((uint)0x00a00000)
  262. #define SCC_GSMRL_TPL_48 ((uint)0x00800000)
  263. #define SCC_GSMRL_TPL_32 ((uint)0x00600000)
  264. #define SCC_GSMRL_TPL_16 ((uint)0x00400000)
  265. #define SCC_GSMRL_TPL_8 ((uint)0x00200000)
  266. #define SCC_GSMRL_TPL_NONE ((uint)0x00000000)
  267. #define SCC_GSMRL_TPP_ALL1 ((uint)0x00180000)
  268. #define SCC_GSMRL_TPP_01 ((uint)0x00100000)
  269. #define SCC_GSMRL_TPP_10 ((uint)0x00080000)
  270. #define SCC_GSMRL_TPP_ZEROS ((uint)0x00000000)
  271. #define SCC_GSMRL_TEND ((uint)0x00040000)
  272. #define SCC_GSMRL_TDCR_32 ((uint)0x00030000)
  273. #define SCC_GSMRL_TDCR_16 ((uint)0x00020000)
  274. #define SCC_GSMRL_TDCR_8 ((uint)0x00010000)
  275. #define SCC_GSMRL_TDCR_1 ((uint)0x00000000)
  276. #define SCC_GSMRL_RDCR_32 ((uint)0x0000c000)
  277. #define SCC_GSMRL_RDCR_16 ((uint)0x00008000)
  278. #define SCC_GSMRL_RDCR_8 ((uint)0x00004000)
  279. #define SCC_GSMRL_RDCR_1 ((uint)0x00000000)
  280. #define SCC_GSMRL_RENC_DFMAN ((uint)0x00003000)
  281. #define SCC_GSMRL_RENC_MANCH ((uint)0x00002000)
  282. #define SCC_GSMRL_RENC_FM0 ((uint)0x00001000)
  283. #define SCC_GSMRL_RENC_NRZI ((uint)0x00000800)
  284. #define SCC_GSMRL_RENC_NRZ ((uint)0x00000000)
  285. #define SCC_GSMRL_TENC_DFMAN ((uint)0x00000600)
  286. #define SCC_GSMRL_TENC_MANCH ((uint)0x00000400)
  287. #define SCC_GSMRL_TENC_FM0 ((uint)0x00000200)
  288. #define SCC_GSMRL_TENC_NRZI ((uint)0x00000100)
  289. #define SCC_GSMRL_TENC_NRZ ((uint)0x00000000)
  290. #define SCC_GSMRL_DIAG_LE ((uint)0x000000c0) /* Loop and echo */
  291. #define SCC_GSMRL_DIAG_ECHO ((uint)0x00000080)
  292. #define SCC_GSMRL_DIAG_LOOP ((uint)0x00000040)
  293. #define SCC_GSMRL_DIAG_NORM ((uint)0x00000000)
  294. #define SCC_GSMRL_ENR ((uint)0x00000020)
  295. #define SCC_GSMRL_ENT ((uint)0x00000010)
  296. #define SCC_GSMRL_MODE_ENET ((uint)0x0000000c)
  297. #define SCC_GSMRL_MODE_DDCMP ((uint)0x00000009)
  298. #define SCC_GSMRL_MODE_BISYNC ((uint)0x00000008)
  299. #define SCC_GSMRL_MODE_V14 ((uint)0x00000007)
  300. #define SCC_GSMRL_MODE_AHDLC ((uint)0x00000006)
  301. #define SCC_GSMRL_MODE_PROFIBUS ((uint)0x00000005)
  302. #define SCC_GSMRL_MODE_UART ((uint)0x00000004)
  303. #define SCC_GSMRL_MODE_SS7 ((uint)0x00000003)
  304. #define SCC_GSMRL_MODE_ATALK ((uint)0x00000002)
  305. #define SCC_GSMRL_MODE_HDLC ((uint)0x00000000)
  306. #define SCC_TODR_TOD ((ushort)0x8000)
  307. /* SCC Event and Mask register.
  308. */
  309. #define SCCM_TXE ((unsigned char)0x10)
  310. #define SCCM_BSY ((unsigned char)0x04)
  311. #define SCCM_TX ((unsigned char)0x02)
  312. #define SCCM_RX ((unsigned char)0x01)
  313. typedef struct scc_param {
  314. ushort scc_rbase; /* Rx Buffer descriptor base address */
  315. ushort scc_tbase; /* Tx Buffer descriptor base address */
  316. u_char scc_rfcr; /* Rx function code */
  317. u_char scc_tfcr; /* Tx function code */
  318. ushort scc_mrblr; /* Max receive buffer length */
  319. uint scc_rstate; /* Internal */
  320. uint scc_idp; /* Internal */
  321. ushort scc_rbptr; /* Internal */
  322. ushort scc_ibc; /* Internal */
  323. uint scc_rxtmp; /* Internal */
  324. uint scc_tstate; /* Internal */
  325. uint scc_tdp; /* Internal */
  326. ushort scc_tbptr; /* Internal */
  327. ushort scc_tbc; /* Internal */
  328. uint scc_txtmp; /* Internal */
  329. uint scc_rcrc; /* Internal */
  330. uint scc_tcrc; /* Internal */
  331. } sccp_t;
  332. /* CPM Ethernet through SCC1.
  333. */
  334. typedef struct scc_enet {
  335. sccp_t sen_genscc;
  336. uint sen_cpres; /* Preset CRC */
  337. uint sen_cmask; /* Constant mask for CRC */
  338. uint sen_crcec; /* CRC Error counter */
  339. uint sen_alec; /* alignment error counter */
  340. uint sen_disfc; /* discard frame counter */
  341. ushort sen_pads; /* Tx short frame pad character */
  342. ushort sen_retlim; /* Retry limit threshold */
  343. ushort sen_retcnt; /* Retry limit counter */
  344. ushort sen_maxflr; /* maximum frame length register */
  345. ushort sen_minflr; /* minimum frame length register */
  346. ushort sen_maxd1; /* maximum DMA1 length */
  347. ushort sen_maxd2; /* maximum DMA2 length */
  348. ushort sen_maxd; /* Rx max DMA */
  349. ushort sen_dmacnt; /* Rx DMA counter */
  350. ushort sen_maxb; /* Max BD byte count */
  351. ushort sen_gaddr1; /* Group address filter */
  352. ushort sen_gaddr2;
  353. ushort sen_gaddr3;
  354. ushort sen_gaddr4;
  355. uint sen_tbuf0data0; /* Save area 0 - current frame */
  356. uint sen_tbuf0data1; /* Save area 1 - current frame */
  357. uint sen_tbuf0rba; /* Internal */
  358. uint sen_tbuf0crc; /* Internal */
  359. ushort sen_tbuf0bcnt; /* Internal */
  360. ushort sen_paddrh; /* physical address (MSB) */
  361. ushort sen_paddrm;
  362. ushort sen_paddrl; /* physical address (LSB) */
  363. ushort sen_pper; /* persistence */
  364. ushort sen_rfbdptr; /* Rx first BD pointer */
  365. ushort sen_tfbdptr; /* Tx first BD pointer */
  366. ushort sen_tlbdptr; /* Tx last BD pointer */
  367. uint sen_tbuf1data0; /* Save area 0 - current frame */
  368. uint sen_tbuf1data1; /* Save area 1 - current frame */
  369. uint sen_tbuf1rba; /* Internal */
  370. uint sen_tbuf1crc; /* Internal */
  371. ushort sen_tbuf1bcnt; /* Internal */
  372. ushort sen_txlen; /* Tx Frame length counter */
  373. ushort sen_iaddr1; /* Individual address filter */
  374. ushort sen_iaddr2;
  375. ushort sen_iaddr3;
  376. ushort sen_iaddr4;
  377. ushort sen_boffcnt; /* Backoff counter */
  378. /* NOTE: Some versions of the manual have the following items
  379. * incorrectly documented. Below is the proper order.
  380. */
  381. ushort sen_taddrh; /* temp address (MSB) */
  382. ushort sen_taddrm;
  383. ushort sen_taddrl; /* temp address (LSB) */
  384. } scc_enet_t;
  385. /* SCC Event register as used by Ethernet.
  386. */
  387. #define SCCE_ENET_GRA ((ushort)0x0080) /* Graceful stop complete */
  388. #define SCCE_ENET_TXE ((ushort)0x0010) /* Transmit Error */
  389. #define SCCE_ENET_RXF ((ushort)0x0008) /* Full frame received */
  390. #define SCCE_ENET_BSY ((ushort)0x0004) /* All incoming buffers full */
  391. #define SCCE_ENET_TXB ((ushort)0x0002) /* A buffer was transmitted */
  392. #define SCCE_ENET_RXB ((ushort)0x0001) /* A buffer was received */
  393. /* SCC Mode Register (PSMR) as used by Ethernet.
  394. */
  395. #define SCC_PSMR_HBC ((ushort)0x8000) /* Enable heartbeat */
  396. #define SCC_PSMR_FC ((ushort)0x4000) /* Force collision */
  397. #define SCC_PSMR_RSH ((ushort)0x2000) /* Receive short frames */
  398. #define SCC_PSMR_IAM ((ushort)0x1000) /* Check individual hash */
  399. #define SCC_PSMR_ENCRC ((ushort)0x0800) /* Ethernet CRC mode */
  400. #define SCC_PSMR_PRO ((ushort)0x0200) /* Promiscuous mode */
  401. #define SCC_PSMR_BRO ((ushort)0x0100) /* Catch broadcast pkts */
  402. #define SCC_PSMR_SBT ((ushort)0x0080) /* Special backoff timer */
  403. #define SCC_PSMR_LPB ((ushort)0x0040) /* Set Loopback mode */
  404. #define SCC_PSMR_SIP ((ushort)0x0020) /* Sample Input Pins */
  405. #define SCC_PSMR_LCW ((ushort)0x0010) /* Late collision window */
  406. #define SCC_PSMR_NIB22 ((ushort)0x000a) /* Start frame search */
  407. #define SCC_PSMR_FDE ((ushort)0x0001) /* Full duplex enable */
  408. /* Buffer descriptor control/status used by Ethernet receive.
  409. * Common to SCC and FCC.
  410. */
  411. #define BD_ENET_RX_EMPTY ((ushort)0x8000)
  412. #define BD_ENET_RX_WRAP ((ushort)0x2000)
  413. #define BD_ENET_RX_INTR ((ushort)0x1000)
  414. #define BD_ENET_RX_LAST ((ushort)0x0800)
  415. #define BD_ENET_RX_FIRST ((ushort)0x0400)
  416. #define BD_ENET_RX_MISS ((ushort)0x0100)
  417. #define BD_ENET_RX_BC ((ushort)0x0080) /* FCC Only */
  418. #define BD_ENET_RX_MC ((ushort)0x0040) /* FCC Only */
  419. #define BD_ENET_RX_LG ((ushort)0x0020)
  420. #define BD_ENET_RX_NO ((ushort)0x0010)
  421. #define BD_ENET_RX_SH ((ushort)0x0008)
  422. #define BD_ENET_RX_CR ((ushort)0x0004)
  423. #define BD_ENET_RX_OV ((ushort)0x0002)
  424. #define BD_ENET_RX_CL ((ushort)0x0001)
  425. #define BD_ENET_RX_STATS ((ushort)0x01ff) /* All status bits */
  426. /* Buffer descriptor control/status used by Ethernet transmit.
  427. * Common to SCC and FCC.
  428. */
  429. #define BD_ENET_TX_READY ((ushort)0x8000)
  430. #define BD_ENET_TX_PAD ((ushort)0x4000)
  431. #define BD_ENET_TX_WRAP ((ushort)0x2000)
  432. #define BD_ENET_TX_INTR ((ushort)0x1000)
  433. #define BD_ENET_TX_LAST ((ushort)0x0800)
  434. #define BD_ENET_TX_TC ((ushort)0x0400)
  435. #define BD_ENET_TX_DEF ((ushort)0x0200)
  436. #define BD_ENET_TX_HB ((ushort)0x0100)
  437. #define BD_ENET_TX_LC ((ushort)0x0080)
  438. #define BD_ENET_TX_RL ((ushort)0x0040)
  439. #define BD_ENET_TX_RCMASK ((ushort)0x003c)
  440. #define BD_ENET_TX_UN ((ushort)0x0002)
  441. #define BD_ENET_TX_CSL ((ushort)0x0001)
  442. #define BD_ENET_TX_STATS ((ushort)0x03ff) /* All status bits */
  443. /* SCC as UART
  444. */
  445. typedef struct scc_uart {
  446. sccp_t scc_genscc;
  447. uint scc_res1; /* Reserved */
  448. uint scc_res2; /* Reserved */
  449. ushort scc_maxidl; /* Maximum idle chars */
  450. ushort scc_idlc; /* temp idle counter */
  451. ushort scc_brkcr; /* Break count register */
  452. ushort scc_parec; /* receive parity error counter */
  453. ushort scc_frmec; /* receive framing error counter */
  454. ushort scc_nosec; /* receive noise counter */
  455. ushort scc_brkec; /* receive break condition counter */
  456. ushort scc_brkln; /* last received break length */
  457. ushort scc_uaddr1; /* UART address character 1 */
  458. ushort scc_uaddr2; /* UART address character 2 */
  459. ushort scc_rtemp; /* Temp storage */
  460. ushort scc_toseq; /* Transmit out of sequence char */
  461. ushort scc_char1; /* control character 1 */
  462. ushort scc_char2; /* control character 2 */
  463. ushort scc_char3; /* control character 3 */
  464. ushort scc_char4; /* control character 4 */
  465. ushort scc_char5; /* control character 5 */
  466. ushort scc_char6; /* control character 6 */
  467. ushort scc_char7; /* control character 7 */
  468. ushort scc_char8; /* control character 8 */
  469. ushort scc_rccm; /* receive control character mask */
  470. ushort scc_rccr; /* receive control character register */
  471. ushort scc_rlbc; /* receive last break character */
  472. } scc_uart_t;
  473. /* SCC Event and Mask registers when it is used as a UART.
  474. */
  475. #define UART_SCCM_GLR ((ushort)0x1000)
  476. #define UART_SCCM_GLT ((ushort)0x0800)
  477. #define UART_SCCM_AB ((ushort)0x0200)
  478. #define UART_SCCM_IDL ((ushort)0x0100)
  479. #define UART_SCCM_GRA ((ushort)0x0080)
  480. #define UART_SCCM_BRKE ((ushort)0x0040)
  481. #define UART_SCCM_BRKS ((ushort)0x0020)
  482. #define UART_SCCM_CCR ((ushort)0x0008)
  483. #define UART_SCCM_BSY ((ushort)0x0004)
  484. #define UART_SCCM_TX ((ushort)0x0002)
  485. #define UART_SCCM_RX ((ushort)0x0001)
  486. /* The SCC PSMR when used as a UART.
  487. */
  488. #define SCU_PSMR_FLC ((ushort)0x8000)
  489. #define SCU_PSMR_SL ((ushort)0x4000)
  490. #define SCU_PSMR_CL ((ushort)0x3000)
  491. #define SCU_PSMR_UM ((ushort)0x0c00)
  492. #define SCU_PSMR_FRZ ((ushort)0x0200)
  493. #define SCU_PSMR_RZS ((ushort)0x0100)
  494. #define SCU_PSMR_SYN ((ushort)0x0080)
  495. #define SCU_PSMR_DRT ((ushort)0x0040)
  496. #define SCU_PSMR_PEN ((ushort)0x0010)
  497. #define SCU_PSMR_RPM ((ushort)0x000c)
  498. #define SCU_PSMR_REVP ((ushort)0x0008)
  499. #define SCU_PSMR_TPM ((ushort)0x0003)
  500. #define SCU_PSMR_TEVP ((ushort)0x0003)
  501. /* CPM Transparent mode SCC.
  502. */
  503. typedef struct scc_trans {
  504. sccp_t st_genscc;
  505. uint st_cpres; /* Preset CRC */
  506. uint st_cmask; /* Constant mask for CRC */
  507. } scc_trans_t;
  508. #define BD_SCC_TX_LAST ((ushort)0x0800)
  509. /* SCC as HDLC controller - taken from commproc.h
  510. */
  511. typedef struct scc_hdlc {
  512. sccp_t sh_genscc;
  513. /*
  514. * HDLC specific parameter RAM
  515. */
  516. uchar res[4]; /* reserved */
  517. ulong sh_cmask; /* CRC constant */
  518. ulong sh_cpres; /* CRC preset */
  519. ushort sh_disfc; /* discarded frame counter */
  520. ushort sh_crcec; /* CRC error counter */
  521. ushort sh_abtsc; /* abort sequence counter */
  522. ushort sh_nmarc; /* nonmatching address rx cnt */
  523. ushort sh_retrc; /* frame retransmission cnt */
  524. ushort sh_mflr; /* maximum frame length reg */
  525. ushort sh_maxcnt; /* maximum length counter */
  526. ushort sh_rfthr; /* received frames threshold */
  527. ushort sh_rfcnt; /* received frames count */
  528. ushort sh_hmask; /* user defined frm addr mask */
  529. ushort sh_haddr1; /* user defined frm address 1 */
  530. ushort sh_haddr2; /* user defined frm address 2 */
  531. ushort sh_haddr3; /* user defined frm address 3 */
  532. ushort sh_haddr4; /* user defined frm address 4 */
  533. ushort tmp; /* temp */
  534. ushort tmp_mb; /* temp */
  535. } scc_hdlc_t;
  536. /* How about some FCCs.....
  537. */
  538. #define FCC_GFMR_DIAG_NORM ((uint)0x00000000)
  539. #define FCC_GFMR_DIAG_LE ((uint)0x40000000)
  540. #define FCC_GFMR_DIAG_AE ((uint)0x80000000)
  541. #define FCC_GFMR_DIAG_ALE ((uint)0xc0000000)
  542. #define FCC_GFMR_TCI ((uint)0x20000000)
  543. #define FCC_GFMR_TRX ((uint)0x10000000)
  544. #define FCC_GFMR_TTX ((uint)0x08000000)
  545. #define FCC_GFMR_TTX ((uint)0x08000000)
  546. #define FCC_GFMR_CDP ((uint)0x04000000)
  547. #define FCC_GFMR_CTSP ((uint)0x02000000)
  548. #define FCC_GFMR_CDS ((uint)0x01000000)
  549. #define FCC_GFMR_CTSS ((uint)0x00800000)
  550. #define FCC_GFMR_SYNL_NONE ((uint)0x00000000)
  551. #define FCC_GFMR_SYNL_AUTO ((uint)0x00004000)
  552. #define FCC_GFMR_SYNL_8 ((uint)0x00008000)
  553. #define FCC_GFMR_SYNL_16 ((uint)0x0000c000)
  554. #define FCC_GFMR_RTSM ((uint)0x00002000)
  555. #define FCC_GFMR_RENC_NRZ ((uint)0x00000000)
  556. #define FCC_GFMR_RENC_NRZI ((uint)0x00000800)
  557. #define FCC_GFMR_REVD ((uint)0x00000400)
  558. #define FCC_GFMR_TENC_NRZ ((uint)0x00000000)
  559. #define FCC_GFMR_TENC_NRZI ((uint)0x00000100)
  560. #define FCC_GFMR_TCRC_16 ((uint)0x00000000)
  561. #define FCC_GFMR_TCRC_32 ((uint)0x00000080)
  562. #define FCC_GFMR_ENR ((uint)0x00000020)
  563. #define FCC_GFMR_ENT ((uint)0x00000010)
  564. #define FCC_GFMR_MODE_ENET ((uint)0x0000000c)
  565. #define FCC_GFMR_MODE_ATM ((uint)0x0000000a)
  566. #define FCC_GFMR_MODE_HDLC ((uint)0x00000000)
  567. /* Generic FCC parameter ram.
  568. */
  569. typedef struct fcc_param {
  570. ushort fcc_riptr; /* Rx Internal temp pointer */
  571. ushort fcc_tiptr; /* Tx Internal temp pointer */
  572. ushort fcc_res1;
  573. ushort fcc_mrblr; /* Max receive buffer length, mod 32 bytes */
  574. uint fcc_rstate; /* Upper byte is Func code, must be set */
  575. uint fcc_rbase; /* Receive BD base */
  576. ushort fcc_rbdstat; /* RxBD status */
  577. ushort fcc_rbdlen; /* RxBD down counter */
  578. uint fcc_rdptr; /* RxBD internal data pointer */
  579. uint fcc_tstate; /* Upper byte is Func code, must be set */
  580. uint fcc_tbase; /* Transmit BD base */
  581. ushort fcc_tbdstat; /* TxBD status */
  582. ushort fcc_tbdlen; /* TxBD down counter */
  583. uint fcc_tdptr; /* TxBD internal data pointer */
  584. uint fcc_rbptr; /* Rx BD Internal buf pointer */
  585. uint fcc_tbptr; /* Tx BD Internal buf pointer */
  586. uint fcc_rcrc; /* Rx temp CRC */
  587. uint fcc_res2;
  588. uint fcc_tcrc; /* Tx temp CRC */
  589. } fccp_t;
  590. /* Ethernet controller through FCC.
  591. */
  592. typedef struct fcc_enet {
  593. fccp_t fen_genfcc;
  594. uint fen_statbuf; /* Internal status buffer */
  595. uint fen_camptr; /* CAM address */
  596. uint fen_cmask; /* Constant mask for CRC */
  597. uint fen_cpres; /* Preset CRC */
  598. uint fen_crcec; /* CRC Error counter */
  599. uint fen_alec; /* alignment error counter */
  600. uint fen_disfc; /* discard frame counter */
  601. ushort fen_retlim; /* Retry limit */
  602. ushort fen_retcnt; /* Retry counter */
  603. ushort fen_pper; /* Persistence */
  604. ushort fen_boffcnt; /* backoff counter */
  605. uint fen_gaddrh; /* Group address filter, high 32-bits */
  606. uint fen_gaddrl; /* Group address filter, low 32-bits */
  607. ushort fen_tfcstat; /* out of sequence TxBD */
  608. ushort fen_tfclen;
  609. uint fen_tfcptr;
  610. ushort fen_mflr; /* Maximum frame length (1518) */
  611. ushort fen_paddrh; /* MAC address */
  612. ushort fen_paddrm;
  613. ushort fen_paddrl;
  614. ushort fen_ibdcount; /* Internal BD counter */
  615. ushort fen_idbstart; /* Internal BD start pointer */
  616. ushort fen_ibdend; /* Internal BD end pointer */
  617. ushort fen_txlen; /* Internal Tx frame length counter */
  618. uint fen_ibdbase[8]; /* Internal use */
  619. uint fen_iaddrh; /* Individual address filter */
  620. uint fen_iaddrl;
  621. ushort fen_minflr; /* Minimum frame length (64) */
  622. ushort fen_taddrh; /* Filter transfer MAC address */
  623. ushort fen_taddrm;
  624. ushort fen_taddrl;
  625. ushort fen_padptr; /* Pointer to pad byte buffer */
  626. ushort fen_cftype; /* control frame type */
  627. ushort fen_cfrange; /* control frame range */
  628. ushort fen_maxb; /* maximum BD count */
  629. ushort fen_maxd1; /* Max DMA1 length (1520) */
  630. ushort fen_maxd2; /* Max DMA2 length (1520) */
  631. ushort fen_maxd; /* internal max DMA count */
  632. ushort fen_dmacnt; /* internal DMA counter */
  633. uint fen_octc; /* Total octect counter */
  634. uint fen_colc; /* Total collision counter */
  635. uint fen_broc; /* Total broadcast packet counter */
  636. uint fen_mulc; /* Total multicast packet count */
  637. uint fen_uspc; /* Total packets < 64 bytes */
  638. uint fen_frgc; /* Total packets < 64 bytes with errors */
  639. uint fen_ospc; /* Total packets > 1518 */
  640. uint fen_jbrc; /* Total packets > 1518 with errors */
  641. uint fen_p64c; /* Total packets == 64 bytes */
  642. uint fen_p65c; /* Total packets 64 < bytes <= 127 */
  643. uint fen_p128c; /* Total packets 127 < bytes <= 255 */
  644. uint fen_p256c; /* Total packets 256 < bytes <= 511 */
  645. uint fen_p512c; /* Total packets 512 < bytes <= 1023 */
  646. uint fen_p1024c; /* Total packets 1024 < bytes <= 1518 */
  647. uint fen_cambuf; /* Internal CAM buffer poiner */
  648. ushort fen_rfthr; /* Received frames threshold */
  649. ushort fen_rfcnt; /* Received frames count */
  650. } fcc_enet_t;
  651. /* FCC Event/Mask register as used by Ethernet.
  652. */
  653. #define FCC_ENET_GRA ((ushort)0x0080) /* Graceful stop complete */
  654. #define FCC_ENET_RXC ((ushort)0x0040) /* Control Frame Received */
  655. #define FCC_ENET_TXC ((ushort)0x0020) /* Out of seq. Tx sent */
  656. #define FCC_ENET_TXE ((ushort)0x0010) /* Transmit Error */
  657. #define FCC_ENET_RXF ((ushort)0x0008) /* Full frame received */
  658. #define FCC_ENET_BSY ((ushort)0x0004) /* Busy. Rx Frame dropped */
  659. #define FCC_ENET_TXB ((ushort)0x0002) /* A buffer was transmitted */
  660. #define FCC_ENET_RXB ((ushort)0x0001) /* A buffer was received */
  661. /* FCC Mode Register (FPSMR) as used by Ethernet.
  662. */
  663. #define FCC_PSMR_HBC ((uint)0x80000000) /* Enable heartbeat */
  664. #define FCC_PSMR_FC ((uint)0x40000000) /* Force Collision */
  665. #define FCC_PSMR_SBT ((uint)0x20000000) /* Stop backoff timer */
  666. #define FCC_PSMR_LPB ((uint)0x10000000) /* Local protect. 1 = FDX */
  667. #define FCC_PSMR_LCW ((uint)0x08000000) /* Late collision select */
  668. #define FCC_PSMR_FDE ((uint)0x04000000) /* Full Duplex Enable */
  669. #define FCC_PSMR_MON ((uint)0x02000000) /* RMON Enable */
  670. #define FCC_PSMR_PRO ((uint)0x00400000) /* Promiscuous Enable */
  671. #define FCC_PSMR_FCE ((uint)0x00200000) /* Flow Control Enable */
  672. #define FCC_PSMR_RSH ((uint)0x00100000) /* Receive Short Frames */
  673. #define FCC_PSMR_RMII ((uint)0x00020000) /* Use RMII interface */
  674. #define FCC_PSMR_CAM ((uint)0x00000400) /* CAM enable */
  675. #define FCC_PSMR_BRO ((uint)0x00000200) /* Broadcast pkt discard */
  676. #define FCC_PSMR_ENCRC ((uint)0x00000080) /* Use 32-bit CRC */
  677. /* IIC parameter RAM.
  678. */
  679. typedef struct iic {
  680. ushort iic_rbase; /* Rx Buffer descriptor base address */
  681. ushort iic_tbase; /* Tx Buffer descriptor base address */
  682. u_char iic_rfcr; /* Rx function code */
  683. u_char iic_tfcr; /* Tx function code */
  684. ushort iic_mrblr; /* Max receive buffer length */
  685. uint iic_rstate; /* Internal */
  686. uint iic_rdp; /* Internal */
  687. ushort iic_rbptr; /* Internal */
  688. ushort iic_rbc; /* Internal */
  689. uint iic_rxtmp; /* Internal */
  690. uint iic_tstate; /* Internal */
  691. uint iic_tdp; /* Internal */
  692. ushort iic_tbptr; /* Internal */
  693. ushort iic_tbc; /* Internal */
  694. uint iic_txtmp; /* Internal */
  695. } iic_t;
  696. /* SPI parameter RAM.
  697. */
  698. typedef struct spi {
  699. ushort spi_rbase; /* Rx Buffer descriptor base address */
  700. ushort spi_tbase; /* Tx Buffer descriptor base address */
  701. u_char spi_rfcr; /* Rx function code */
  702. u_char spi_tfcr; /* Tx function code */
  703. ushort spi_mrblr; /* Max receive buffer length */
  704. uint spi_rstate; /* Internal */
  705. uint spi_rdp; /* Internal */
  706. ushort spi_rbptr; /* Internal */
  707. ushort spi_rbc; /* Internal */
  708. uint spi_rxtmp; /* Internal */
  709. uint spi_tstate; /* Internal */
  710. uint spi_tdp; /* Internal */
  711. ushort spi_tbptr; /* Internal */
  712. ushort spi_tbc; /* Internal */
  713. uint spi_txtmp; /* Internal */
  714. uint spi_res; /* Tx temp. */
  715. uint spi_res1[4]; /* SDMA temp. */
  716. } spi_t;
  717. /* SPI Mode register.
  718. */
  719. #define SPMODE_LOOP ((ushort)0x4000) /* Loopback */
  720. #define SPMODE_CI ((ushort)0x2000) /* Clock Invert */
  721. #define SPMODE_CP ((ushort)0x1000) /* Clock Phase */
  722. #define SPMODE_DIV16 ((ushort)0x0800) /* BRG/16 mode */
  723. #define SPMODE_REV ((ushort)0x0400) /* Reversed Data */
  724. #define SPMODE_MSTR ((ushort)0x0200) /* SPI Master */
  725. #define SPMODE_EN ((ushort)0x0100) /* Enable */
  726. #define SPMODE_LENMSK ((ushort)0x00f0) /* character length */
  727. #define SPMODE_PMMSK ((ushort)0x000f) /* prescale modulus */
  728. #define SPMODE_LEN(x) ((((x)-1)&0xF)<<4)
  729. #define SPMODE_PM(x) ((x) &0xF)
  730. /* SPI Event/Mask register.
  731. */
  732. #define SPI_EMASK 0x37 /* Event Mask */
  733. #define SPI_MME 0x20 /* Multi-Master Error */
  734. #define SPI_TXE 0x10 /* Transmit Error */
  735. #define SPI_BSY 0x04 /* Busy */
  736. #define SPI_TXB 0x02 /* Tx Buffer Empty */
  737. #define SPI_RXB 0x01 /* RX Buffer full/closed */
  738. #define SPI_STR 0x80 /* SPCOM: Start transmit */
  739. #define SPI_EB ((u_char)0x10) /* big endian byte order */
  740. #define BD_IIC_START ((ushort)0x0400)
  741. #endif /* __CPM_82XX__ */