IxEthAcc_p.h 11 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233234235236237238239240241242243244245246247248249250251252253254255256257258259260261262263264265266267268269270271272273274275276277278279280281282283284285286287288289290291292293294295296297298299300301302303304305306307308309310311312313314315316317318319320321322323324325
  1. /**
  2. * @file IxEthAcc_p.h
  3. *
  4. * @author Intel Corporation
  5. * @date 12-Feb-2002
  6. *
  7. * @brief Internal Header file for IXP425 Ethernet Access component.
  8. *
  9. * Design Notes:
  10. *
  11. *
  12. * @par
  13. * IXP400 SW Release version 2.0
  14. *
  15. * -- Copyright Notice --
  16. *
  17. * @par
  18. * Copyright 2001-2005, Intel Corporation.
  19. * All rights reserved.
  20. *
  21. * @par
  22. * Redistribution and use in source and binary forms, with or without
  23. * modification, are permitted provided that the following conditions
  24. * are met:
  25. * 1. Redistributions of source code must retain the above copyright
  26. * notice, this list of conditions and the following disclaimer.
  27. * 2. Redistributions in binary form must reproduce the above copyright
  28. * notice, this list of conditions and the following disclaimer in the
  29. * documentation and/or other materials provided with the distribution.
  30. * 3. Neither the name of the Intel Corporation nor the names of its contributors
  31. * may be used to endorse or promote products derived from this software
  32. * without specific prior written permission.
  33. *
  34. * @par
  35. * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS ``AS IS''
  36. * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  37. * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  38. * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE
  39. * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
  40. * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
  41. * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
  42. * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
  43. * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
  44. * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
  45. * SUCH DAMAGE.
  46. *
  47. * @par
  48. * -- End of Copyright Notice --
  49. */
  50. /**
  51. * @addtogroup IxEthAccPri
  52. *@{
  53. */
  54. #ifndef IxEthAcc_p_H
  55. #define IxEthAcc_p_H
  56. /*
  57. * Os/System dependancies.
  58. */
  59. #include "IxOsal.h"
  60. /*
  61. * Intermodule dependancies
  62. */
  63. #include "IxNpeDl.h"
  64. #include "IxQMgr.h"
  65. #include "IxEthNpe.h"
  66. /*
  67. * Intra module dependancies
  68. */
  69. #include "IxEthAccDataPlane_p.h"
  70. #include "IxEthAccMac_p.h"
  71. #define INLINE __inline__
  72. #ifdef NDEBUG
  73. #define IX_ETH_ACC_PRIVATE static
  74. #else
  75. #define IX_ETH_ACC_PRIVATE
  76. #endif /* ndef NDEBUG */
  77. #define IX_ETH_ACC_PUBLIC
  78. #define IX_ETH_ACC_IS_PORT_VALID(port) ((port) < IX_ETH_ACC_NUMBER_OF_PORTS ? TRUE : FALSE )
  79. #ifndef NDEBUG
  80. #define IX_ETH_ACC_FATAL_LOG(a,b,c,d,e,f,g) { ixOsalLog ( IX_OSAL_LOG_LVL_FATAL,IX_OSAL_LOG_DEV_STDOUT,a,b,c,d,e,f,g);}
  81. #define IX_ETH_ACC_WARNING_LOG(a,b,c,d,e,f,g) { ixOsalLog ( IX_OSAL_LOG_LVL_WARNING,IX_OSAL_LOG_DEV_STDOUT,a,b,c,d,e,f,g);}
  82. #define IX_ETH_ACC_DEBUG_LOG(a,b,c,d,e,f,g) { ixOsalLog ( IX_OSAL_LOG_LVL_FATAL,IX_OSAL_LOG_DEV_STDOUT,a,b,c,d,e,f,g);}
  83. #else
  84. #define IX_ETH_ACC_FATAL_LOG(a,b,c,d,e,f,g) { ixOsalLog ( IX_OSAL_LOG_LVL_FATAL,IX_OSAL_LOG_DEV_STDOUT,a,b,c,d,e,f,g);}
  85. #define IX_ETH_ACC_WARNING_LOG(a,b,c,d,e,f,g) { ixOsalLog ( IX_OSAL_LOG_LVL_WARNING,IX_OSAL_LOG_DEV_STDOUT,a,b,c,d,e,f,g);}
  86. #define IX_ETH_ACC_DEBUG_LOG(a,b,c,d,e,f,g) {}
  87. #endif
  88. IX_ETH_ACC_PUBLIC IxEthAccStatus ixEthAccInitDataPlane(void);
  89. IX_ETH_ACC_PUBLIC IxEthAccStatus ixEthAccQMgrQueuesConfig(void);
  90. IX_ETH_ACC_PUBLIC IxEthAccStatus ixEthAccQMgrRxCallbacksRegister(IxQMgrCallback ixQMgrCallback);
  91. IX_ETH_ACC_PUBLIC IxEthAccStatus ixEthAccSingleEthNpeCheck(IxEthAccPortId portId);
  92. IX_ETH_ACC_PUBLIC void ixEthAccQMgrRxQEntryGet(UINT32 *numRxQueueEntries);
  93. /* prototypes for the private control plane functions (used by the control interface wrapper) */
  94. IX_ETH_ACC_PUBLIC IxEthAccStatus ixEthAccPortEnablePriv(IxEthAccPortId portId);
  95. IX_ETH_ACC_PUBLIC IxEthAccStatus ixEthAccPortDisablePriv(IxEthAccPortId portId);
  96. IX_ETH_ACC_PUBLIC IxEthAccStatus ixEthAccPortEnabledQueryPriv(IxEthAccPortId portId, BOOL *enabled);
  97. IX_ETH_ACC_PUBLIC IxEthAccStatus ixEthAccPortPromiscuousModeClearPriv(IxEthAccPortId portId);
  98. IX_ETH_ACC_PUBLIC IxEthAccStatus ixEthAccPortPromiscuousModeSetPriv(IxEthAccPortId portId);
  99. IX_ETH_ACC_PUBLIC IxEthAccStatus ixEthAccPortUnicastMacAddressSetPriv(IxEthAccPortId portId, IxEthAccMacAddr *macAddr);
  100. IX_ETH_ACC_PUBLIC IxEthAccStatus ixEthAccPortUnicastMacAddressGetPriv(IxEthAccPortId portId, IxEthAccMacAddr *macAddr);
  101. IX_ETH_ACC_PUBLIC IxEthAccStatus ixEthAccPortMulticastAddressJoinPriv(IxEthAccPortId portId, IxEthAccMacAddr *macAddr);
  102. IX_ETH_ACC_PUBLIC IxEthAccStatus ixEthAccPortMulticastAddressJoinAllPriv(IxEthAccPortId portId);
  103. IX_ETH_ACC_PUBLIC IxEthAccStatus ixEthAccPortMulticastAddressLeavePriv(IxEthAccPortId portId, IxEthAccMacAddr *macAddr);
  104. IX_ETH_ACC_PUBLIC IxEthAccStatus ixEthAccPortMulticastAddressLeaveAllPriv(IxEthAccPortId portId);
  105. IX_ETH_ACC_PUBLIC IxEthAccStatus ixEthAccPortUnicastAddressShowPriv(IxEthAccPortId portId);
  106. IX_ETH_ACC_PUBLIC void ixEthAccPortMulticastAddressShowPriv(IxEthAccPortId portId);
  107. IX_ETH_ACC_PUBLIC IxEthAccStatus ixEthAccPortDuplexModeSetPriv(IxEthAccPortId portId, IxEthAccDuplexMode mode);
  108. IX_ETH_ACC_PUBLIC IxEthAccStatus ixEthAccPortDuplexModeGetPriv(IxEthAccPortId portId, IxEthAccDuplexMode *mode);
  109. IX_ETH_ACC_PUBLIC IxEthAccStatus ixEthAccPortTxFrameAppendPaddingEnablePriv(IxEthAccPortId portId);
  110. IX_ETH_ACC_PUBLIC IxEthAccStatus ixEthAccPortTxFrameAppendPaddingDisablePriv(IxEthAccPortId portId);
  111. IX_ETH_ACC_PUBLIC IxEthAccStatus ixEthAccPortTxFrameAppendFCSEnablePriv(IxEthAccPortId portId);
  112. IX_ETH_ACC_PUBLIC IxEthAccStatus ixEthAccPortTxFrameAppendFCSDisablePriv(IxEthAccPortId portId);
  113. IX_ETH_ACC_PUBLIC IxEthAccStatus ixEthAccPortRxFrameAppendFCSEnablePriv(IxEthAccPortId portId);
  114. IX_ETH_ACC_PUBLIC IxEthAccStatus ixEthAccPortRxFrameAppendFCSDisablePriv(IxEthAccPortId portId);
  115. IX_ETH_ACC_PUBLIC IxEthAccStatus ixEthAccTxSchedulingDisciplineSetPriv(IxEthAccPortId portId, IxEthAccSchedulerDiscipline sched);
  116. IX_ETH_ACC_PUBLIC IxEthAccStatus ixEthAccRxSchedulingDisciplineSetPriv(IxEthAccSchedulerDiscipline sched);
  117. /**
  118. * @struct ixEthAccRxDataStats
  119. * @brief Stats data structures for data path. - Not obtained from h/w
  120. *
  121. */
  122. typedef struct
  123. {
  124. UINT32 rxFrameClientCallback;
  125. UINT32 rxFreeRepOK;
  126. UINT32 rxFreeRepDelayed;
  127. UINT32 rxFreeRepFromSwQOK;
  128. UINT32 rxFreeRepFromSwQDelayed;
  129. UINT32 rxFreeLateNotificationEnabled;
  130. UINT32 rxFreeLowCallback;
  131. UINT32 rxFreeOverflow;
  132. UINT32 rxFreeLock;
  133. UINT32 rxDuringDisable;
  134. UINT32 rxSwQDuringDisable;
  135. UINT32 rxUnlearnedMacAddress;
  136. UINT32 rxPriority[IX_ETH_ACC_TX_PRIORITY_7 + 1];
  137. UINT32 rxUnexpectedError;
  138. UINT32 rxFiltered;
  139. } IxEthAccRxDataStats;
  140. /**
  141. * @struct IxEthAccTxDataStats
  142. * @brief Stats data structures for data path. - Not obtained from h/w
  143. *
  144. */
  145. typedef struct
  146. {
  147. UINT32 txQOK;
  148. UINT32 txQDelayed;
  149. UINT32 txFromSwQOK;
  150. UINT32 txFromSwQDelayed;
  151. UINT32 txLowThreshCallback;
  152. UINT32 txDoneClientCallback;
  153. UINT32 txDoneClientCallbackDisable;
  154. UINT32 txOverflow;
  155. UINT32 txLock;
  156. UINT32 txPriority[IX_ETH_ACC_TX_PRIORITY_7 + 1];
  157. UINT32 txLateNotificationEnabled;
  158. UINT32 txDoneDuringDisable;
  159. UINT32 txDoneSwQDuringDisable;
  160. UINT32 txUnexpectedError;
  161. } IxEthAccTxDataStats;
  162. /* port Disable state machine : list of states */
  163. typedef enum
  164. {
  165. /* general port states */
  166. DISABLED = 0,
  167. ACTIVE,
  168. /* particular Tx/Rx states */
  169. REPLENISH,
  170. RECEIVE,
  171. TRANSMIT,
  172. TRANSMIT_DONE
  173. } IxEthAccPortDisableState;
  174. typedef struct
  175. {
  176. BOOL fullDuplex;
  177. BOOL rxFCSAppend;
  178. BOOL txFCSAppend;
  179. BOOL txPADAppend;
  180. BOOL enabled;
  181. BOOL promiscuous;
  182. BOOL joinAll;
  183. IxOsalMutex ackMIBStatsLock;
  184. IxOsalMutex ackMIBStatsResetLock;
  185. IxOsalMutex MIBStatsGetAccessLock;
  186. IxOsalMutex MIBStatsGetResetAccessLock;
  187. IxOsalMutex npeLoopbackMessageLock;
  188. IxEthAccMacAddr mcastAddrsTable[IX_ETH_ACC_MAX_MULTICAST_ADDRESSES];
  189. UINT32 mcastAddrIndex;
  190. IX_OSAL_MBUF *portDisableTxMbufPtr;
  191. IX_OSAL_MBUF *portDisableRxMbufPtr;
  192. volatile IxEthAccPortDisableState portDisableState;
  193. volatile IxEthAccPortDisableState rxState;
  194. volatile IxEthAccPortDisableState txState;
  195. BOOL initDone;
  196. BOOL macInitialised;
  197. } IxEthAccMacState;
  198. /**
  199. * @struct IxEthAccRxInfo
  200. * @brief System-wide data structures associated with the data plane.
  201. *
  202. */
  203. typedef struct
  204. {
  205. IxQMgrQId higherPriorityQueue[IX_QMGR_MAX_NUM_QUEUES]; /**< higher priority queue list */
  206. IxEthAccSchedulerDiscipline schDiscipline; /**< Receive Xscale QoS type */
  207. } IxEthAccInfo;
  208. /**
  209. * @struct IxEthAccRxDataInfo
  210. * @brief Per Port data structures associated with the receive data plane.
  211. *
  212. */
  213. typedef struct
  214. {
  215. IxQMgrQId rxFreeQueue; /**< rxFree Queue for this port */
  216. IxEthAccPortRxCallback rxCallbackFn;
  217. UINT32 rxCallbackTag;
  218. IxEthAccDataPlaneQList freeBufferList;
  219. IxEthAccPortMultiBufferRxCallback rxMultiBufferCallbackFn;
  220. UINT32 rxMultiBufferCallbackTag;
  221. BOOL rxMultiBufferCallbackInUse;
  222. IxEthAccRxDataStats stats; /**< Receive s/w stats */
  223. } IxEthAccRxDataInfo;
  224. /**
  225. * @struct IxEthAccTxDataInfo
  226. * @brief Per Port data structures associated with the transmit data plane.
  227. *
  228. */
  229. typedef struct
  230. {
  231. IxEthAccPortTxDoneCallback txBufferDoneCallbackFn;
  232. UINT32 txCallbackTag;
  233. IxEthAccDataPlaneQList txQ[IX_ETH_ACC_NUM_TX_PRIORITIES]; /**< Transmit Q */
  234. IxEthAccSchedulerDiscipline schDiscipline; /**< Transmit Xscale QoS */
  235. IxQMgrQId txQueue; /**< txQueue for this port */
  236. IxEthAccTxDataStats stats; /**< Transmit s/w stats */
  237. } IxEthAccTxDataInfo;
  238. /**
  239. * @struct IxEthAccPortDataInfo
  240. * @brief Per Port data structures associated with the port data plane.
  241. *
  242. */
  243. typedef struct
  244. {
  245. BOOL portInitialized;
  246. UINT32 npeId; /**< NpeId for this port */
  247. IxEthAccTxDataInfo ixEthAccTxData; /**< Transmit data control structures */
  248. IxEthAccRxDataInfo ixEthAccRxData; /**< Receive data control structures */
  249. } IxEthAccPortDataInfo;
  250. extern IxEthAccPortDataInfo ixEthAccPortData[];
  251. #define IX_ETH_IS_PORT_INITIALIZED(port) (ixEthAccPortData[port].portInitialized)
  252. extern BOOL ixEthAccServiceInit;
  253. #define IX_ETH_ACC_IS_SERVICE_INITIALIZED() (ixEthAccServiceInit == TRUE )
  254. /*
  255. * Maximum number of frames to consume from the Rx Frame Q.
  256. */
  257. #define IX_ETH_ACC_MAX_RX_FRAME_CONSUME_PER_CALLBACK (128)
  258. /*
  259. * Max number of times to load the Rx Free Q from callback.
  260. */
  261. #define IX_ETH_ACC_MAX_RX_FREE_BUFFERS_LOAD (256) /* Set greater than depth of h/w Q + drain time at line rate */
  262. /*
  263. * Max number of times to read from the Tx Done Q in one sitting.
  264. */
  265. #define IX_ETH_ACC_MAX_TX_FRAME_DONE_CONSUME_PER_CALLBACK (256)
  266. /*
  267. * Max number of times to take buffers from S/w queues and write them to the H/w Tx
  268. * queues on receipt of a Tx low threshold callback
  269. */
  270. #define IX_ETH_ACC_MAX_TX_FRAME_TX_CONSUME_PER_CALLBACK (16)
  271. #define IX_ETH_ACC_FLUSH_CACHE(addr,size) IX_OSAL_CACHE_FLUSH((addr),(size))
  272. #define IX_ETH_ACC_INVALIDATE_CACHE(addr,size) IX_OSAL_CACHE_INVALIDATE((addr),(size))
  273. #define IX_ETH_ACC_MEMSET(start,value,size) memset(start,value,size)
  274. #endif /* ndef IxEthAcc_p_H */