IxNpeA.h 22 KB

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  1. #ifndef __doxygen_HIDE /* This file is not part of the API */
  2. /**
  3. * @file IxNpeA.h
  4. *
  5. * @date 22-Mar-2002
  6. *
  7. * @brief Header file for the IXP400 ATM NPE API
  8. *
  9. *
  10. * @par
  11. * IXP400 SW Release version 2.0
  12. *
  13. * -- Copyright Notice --
  14. *
  15. * @par
  16. * Copyright 2001-2005, Intel Corporation.
  17. * All rights reserved.
  18. *
  19. * @par
  20. * Redistribution and use in source and binary forms, with or without
  21. * modification, are permitted provided that the following conditions
  22. * are met:
  23. * 1. Redistributions of source code must retain the above copyright
  24. * notice, this list of conditions and the following disclaimer.
  25. * 2. Redistributions in binary form must reproduce the above copyright
  26. * notice, this list of conditions and the following disclaimer in the
  27. * documentation and/or other materials provided with the distribution.
  28. * 3. Neither the name of the Intel Corporation nor the names of its contributors
  29. * may be used to endorse or promote products derived from this software
  30. * without specific prior written permission.
  31. *
  32. * @par
  33. * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS ``AS IS''
  34. * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  35. * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  36. * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE
  37. * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
  38. * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
  39. * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
  40. * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
  41. * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
  42. * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
  43. * SUCH DAMAGE.
  44. *
  45. * @par
  46. * -- End of Copyright Notice --
  47. */
  48. /**
  49. * @defgroup IxNpeA IXP400 NPE-A (IxNpeA) API
  50. *
  51. * @brief The Public API for the IXP400 NPE-A
  52. *
  53. * @{
  54. */
  55. #ifndef IX_NPE_A_H
  56. #define IX_NPE_A_H
  57. #include "IxQMgr.h"
  58. #include "IxOsal.h"
  59. #include "IxQueueAssignments.h"
  60. /* General Message Ids */
  61. /* ATM Message Ids */
  62. /**
  63. * @def IX_NPE_A_MSSG_ATM_UTOPIA_CONFIG_WRITE
  64. *
  65. * @brief ATM Message ID command to write the data to the offset in the
  66. * Utopia Configuration Table
  67. */
  68. #define IX_NPE_A_MSSG_ATM_UTOPIA_CONFIG_WRITE 0x20
  69. /**
  70. * @def IX_NPE_A_MSSG_ATM_UTOPIA_CONFIG_LOAD
  71. *
  72. * @brief ATM Message ID command triggers the NPE to copy the Utopia
  73. * Configuration Table to the Utopia coprocessor
  74. */
  75. #define IX_NPE_A_MSSG_ATM_UTOPIA_CONFIG_LOAD 0x21
  76. /**
  77. * @def IX_NPE_A_MSSG_ATM_UTOPIA_STATUS_UPLOAD
  78. *
  79. * @brief ATM Message ID command triggers the NPE to read-back the Utopia
  80. * status registers and update the Utopia Status Table.
  81. */
  82. #define IX_NPE_A_MSSG_ATM_UTOPIA_STATUS_UPLOAD 0x22
  83. /**
  84. * @def IX_NPE_A_MSSG_ATM_UTOPIA_STATUS_READ
  85. *
  86. * @brief ATM Message ID command to read the Utopia Status Table at the
  87. * specified offset.
  88. */
  89. #define IX_NPE_A_MSSG_ATM_UTOPIA_STATUS_READ 0x23
  90. /**
  91. * @def IX_NPE_A_MSSG_ATM_TX_ENABLE
  92. *
  93. * @brief ATM Message ID command triggers the NPE to re-enable processing
  94. * of any entries on the TxVcQ for this port.
  95. *
  96. * This command will be ignored for a port already enabled
  97. */
  98. #define IX_NPE_A_MSSG_ATM_TX_ENABLE 0x25
  99. /**
  100. * @def IX_NPE_A_MSSG_ATM_TX_DISABLE
  101. *
  102. * @brief ATM Message ID command triggers the NPE to disable processing on
  103. * this port
  104. *
  105. * This command will be ignored for a port already disabled
  106. */
  107. #define IX_NPE_A_MSSG_ATM_TX_DISABLE 0x26
  108. /**
  109. * @def IX_NPE_A_MSSG_ATM_RX_ENABLE
  110. *
  111. * @brief ATM Message ID command triggers the NPE to process any received
  112. * cells for this VC according to the VC Lookup Table.
  113. *
  114. * Re-issuing this command with different contents for a VC that is not
  115. * disabled will cause unpredictable behavior.
  116. */
  117. #define IX_NPE_A_MSSG_ATM_RX_ENABLE 0x27
  118. /**
  119. * @def IX_NPE_A_MSSG_ATM_RX_DISABLE
  120. *
  121. * @brief ATM Message ID command triggers the NPE to disable processing for
  122. * this VC.
  123. *
  124. * This command will be ignored for a VC already disabled
  125. */
  126. #define IX_NPE_A_MSSG_ATM_RX_DISABLE 0x28
  127. /**
  128. * @def IX_NPE_A_MSSG_ATM_STATUS_READ
  129. *
  130. * @brief ATM Message ID command to read the ATM status. The data is returned via
  131. * a response message
  132. */
  133. #define IX_NPE_A_MSSG_ATM_STATUS_READ 0x29
  134. /*--------------------------------------------------------------------------
  135. * HSS Message IDs
  136. *--------------------------------------------------------------------------*/
  137. /**
  138. * @def IX_NPE_A_MSSG_HSS_PORT_CONFIG_WRITE
  139. *
  140. * @brief HSS Message ID command writes the ConfigWord value to the location
  141. * in the HSS_CONFIG_TABLE specified by offset for HSS port hPort.
  142. */
  143. #define IX_NPE_A_MSSG_HSS_PORT_CONFIG_WRITE 0x40
  144. /**
  145. * @def IX_NPE_A_MSSG_HSS_PORT_CONFIG_LOAD
  146. *
  147. * @brief HSS Message ID command triggers the NPE to copy the contents of the
  148. * HSS Configuration Table to the appropriate configuration registers in the
  149. * HSS coprocessor for the port specified by hPort.
  150. */
  151. #define IX_NPE_A_MSSG_HSS_PORT_CONFIG_LOAD 0x41
  152. /**
  153. * @def IX_NPE_A_MSSG_HSS_PORT_ERROR_READ
  154. *
  155. * @brief HSS Message ID command triggers the NPE to return an HssErrorReadResponse
  156. * message for HSS port hPort.
  157. */
  158. #define IX_NPE_A_MSSG_HSS_PORT_ERROR_READ 0x42
  159. /**
  160. * @def IX_NPE_A_MSSG_HSS_CHAN_FLOW_ENABLE
  161. *
  162. * @brief HSS Message ID command triggers the NPE to reset internal status and
  163. * enable the HssChannelized operation on the HSS port specified by hPort.
  164. */
  165. #define IX_NPE_A_MSSG_HSS_CHAN_FLOW_ENABLE 0x43
  166. /**
  167. * @def IX_NPE_A_MSSG_HSS_CHAN_FLOW_DISABLE
  168. *
  169. * @brief HSS Message ID command triggers the NPE to disable the HssChannelized
  170. * operation on the HSS port specified by hPort.
  171. */
  172. #define IX_NPE_A_MSSG_HSS_CHAN_FLOW_DISABLE 0x44
  173. /**
  174. * @def IX_NPE_A_MSSG_HSS_CHAN_IDLE_PATTERN_WRITE
  175. *
  176. * @brief HSS Message ID command writes the HSSnC_IDLE_PATTERN value for HSS
  177. * port hPort. (n=hPort)
  178. */
  179. #define IX_NPE_A_MSSG_HSS_CHAN_IDLE_PATTERN_WRITE 0x45
  180. /**
  181. * @def IX_NPE_A_MSSG_HSS_CHAN_NUM_CHANS_WRITE
  182. *
  183. * @brief HSS Message ID command writes the HSSnC_NUM_CHANNELS value for HSS
  184. * port hPort. (n=hPort)
  185. */
  186. #define IX_NPE_A_MSSG_HSS_CHAN_NUM_CHANS_WRITE 0x46
  187. /**
  188. * @def IX_NPE_A_MSSG_HSS_CHAN_RX_BUF_ADDR_WRITE
  189. *
  190. * @brief HSS Message ID command writes the HSSnC_RX_BUF_ADDR value for HSS
  191. * port hPort. (n=hPort)
  192. */
  193. #define IX_NPE_A_MSSG_HSS_CHAN_RX_BUF_ADDR_WRITE 0x47
  194. /**
  195. * @def IX_NPE_A_MSSG_HSS_CHAN_RX_BUF_CFG_WRITE
  196. *
  197. * @brief HSS Message ID command writes the HSSnC_RX_BUF_SIZEB and
  198. * HSSnC_RX_TRIG_PERIOD values for HSS port hPort. (n=hPort)
  199. */
  200. #define IX_NPE_A_MSSG_HSS_CHAN_RX_BUF_CFG_WRITE 0x48
  201. /**
  202. * @def IX_NPE_A_MSSG_HSS_CHAN_TX_BLK_CFG_WRITE
  203. *
  204. * @brief HSS Message ID command writes the HSSnC_TX_BLK1_SIZEB,
  205. * HSSnC_TX_BLK1_SIZEW, HSSnC_TX_BLK2_SIZEB, and HSSnC_TX_BLK2_SIZEW values
  206. * for HSS port hPort. (n=hPort)
  207. */
  208. #define IX_NPE_A_MSSG_HSS_CHAN_TX_BLK_CFG_WRITE 0x49
  209. /**
  210. * @def IX_NPE_A_MSSG_HSS_CHAN_TX_BUF_ADDR_WRITE
  211. * @brief HSS Message ID command writes the HSSnC_TX_BUF_ADDR value for HSS
  212. * port hPort. (n=hPort)
  213. */
  214. #define IX_NPE_A_MSSG_HSS_CHAN_TX_BUF_ADDR_WRITE 0x4A
  215. /**
  216. * @def IX_NPE_A_MSSG_HSS_CHAN_TX_BUF_SIZE_WRITE
  217. *
  218. * @brief HSS Message ID command writes the HSSnC_TX_BUF_SIZEN value for HSS
  219. * port hPort. (n=hPort)
  220. */
  221. #define IX_NPE_A_MSSG_HSS_CHAN_TX_BUF_SIZE_WRITE 0x4B
  222. /**
  223. * @def IX_NPE_A_MSSG_HSS_PKT_PIPE_FLOW_ENABLE
  224. *
  225. * @brief HSS Message ID command triggers the NPE to reset internal status and
  226. * enable the HssPacketized operation for the flow specified by pPipe on
  227. * the HSS port specified by hPort.
  228. */
  229. #define IX_NPE_A_MSSG_HSS_PKT_PIPE_FLOW_ENABLE 0x50
  230. /**
  231. * @def IX_NPE_A_MSSG_HSS_PKT_PIPE_FLOW_DISABLE
  232. * @brief HSS Message ID command triggers the NPE to disable the HssPacketized
  233. * operation for the flow specified by pPipe on the HSS port specified by hPort.
  234. */
  235. #define IX_NPE_A_MSSG_HSS_PKT_PIPE_FLOW_DISABLE 0x51
  236. /**
  237. * @def IX_NPE_A_MSSG_HSS_PKT_NUM_PIPES_WRITE
  238. * @brief HSS Message ID command writes the HSSnP_NUM_PIPES value for HSS
  239. * port hPort.(n=hPort)
  240. */
  241. #define IX_NPE_A_MSSG_HSS_PKT_NUM_PIPES_WRITE 0x52
  242. /**
  243. * @def IX_NPE_A_MSSG_HSS_PKT_PIPE_FIFO_SIZEW_WRITE
  244. *
  245. * @brief HSS Message ID command writes the HSSnP_PIPEp_FIFOSIZEW value for
  246. * packet-pipe pPipe on HSS port hPort. (n=hPort, p=pPipe)
  247. */
  248. #define IX_NPE_A_MSSG_HSS_PKT_PIPE_FIFO_SIZEW_WRITE 0x53
  249. /**
  250. * @def IX_NPE_A_MSSG_HSS_PKT_PIPE_HDLC_CFG_WRITE
  251. *
  252. * @brief HSS Message ID command writes the HSSnP_PIPEp_HDLC_RXCFG and
  253. * HSSnP_PIPEp_HDLC_TXCFG values for packet-pipe pPipe on HSS port hPort.
  254. * (n=hPort, p=pPipe)
  255. */
  256. #define IX_NPE_A_MSSG_HSS_PKT_PIPE_HDLC_CFG_WRITE 0x54
  257. /**
  258. * @def IX_NPE_A_MSSG_HSS_PKT_PIPE_IDLE_PATTERN_WRITE
  259. *
  260. * @brief HSS Message ID command writes the HSSnP_PIPEp_IDLE_PATTERN value
  261. * for packet-pipe pPipe on HSS port hPort. (n=hPort, p=pPipe)
  262. */
  263. #define IX_NPE_A_MSSG_HSS_PKT_PIPE_IDLE_PATTERN_WRITE 0x55
  264. /**
  265. * @def IX_NPE_A_MSSG_HSS_PKT_PIPE_RX_SIZE_WRITE
  266. *
  267. * @brief HSS Message ID command writes the HSSnP_PIPEp_RXSIZEB value for
  268. * packet-pipe pPipe on HSS port hPort. (n=hPort, p=pPipe)
  269. */
  270. #define IX_NPE_A_MSSG_HSS_PKT_PIPE_RX_SIZE_WRITE 0x56
  271. /**
  272. * @def IX_NPE_A_MSSG_HSS_PKT_PIPE_MODE_WRITE
  273. *
  274. * @brief HSS Message ID command writes the HSSnP_PIPEp_MODE value for
  275. * packet-pipe pPipe on HSS port hPort. (n=hPort, p=pPipe)
  276. */
  277. #define IX_NPE_A_MSSG_HSS_PKT_PIPE_MODE_WRITE 0x57
  278. /* Queue Entry Masks */
  279. /*--------------------------------------------------------------------------
  280. * ATM Descriptor Structure offsets
  281. *--------------------------------------------------------------------------*/
  282. /**
  283. * @def IX_NPE_A_RXDESCRIPTOR_STATUS_OFFSET
  284. *
  285. * @brief ATM Descriptor structure offset for Receive Descriptor Status field
  286. *
  287. * It is used for descriptor error reporting.
  288. */
  289. #define IX_NPE_A_RXDESCRIPTOR_STATUS_OFFSET 0
  290. /**
  291. * @def IX_NPE_A_RXDESCRIPTOR_VCID_OFFSET
  292. *
  293. * @brief ATM Descriptor structure offset for Receive Descriptor VC ID field
  294. *
  295. * It is used to hold an identifier number for this VC
  296. */
  297. #define IX_NPE_A_RXDESCRIPTOR_VCID_OFFSET 1
  298. /**
  299. * @def IX_NPE_A_RXDESCRIPTOR_CURRMBUFSIZE_OFFSET
  300. *
  301. * @brief ATM Descriptor structure offset for Receive Descriptor Current Mbuf
  302. * Size field
  303. *
  304. * Number of bytes the current mbuf data buffer can hold
  305. */
  306. #define IX_NPE_A_RXDESCRIPTOR_CURRMBUFSIZE_OFFSET 2
  307. /**
  308. * @def IX_NPE_A_RXDESCRIPTOR_ATMHEADER_OFFSET
  309. *
  310. * @brief ATM Descriptor structure offset for Receive Descriptor ATM Header
  311. */
  312. #define IX_NPE_A_RXDESCRIPTOR_ATMHEADER_OFFSET 4
  313. /**
  314. * @def IX_NPE_A_RXDESCRIPTOR_CURRMBUFLEN_OFFSET
  315. *
  316. * @brief ATM Descriptor structure offset for Receive Descriptor Current MBuf length
  317. *
  318. *
  319. * RX - Initialized to zero. The NPE updates this field as each cell is received and
  320. * zeroes it with every new mbuf for chaining. Will not be bigger than currBbufSize.
  321. */
  322. #define IX_NPE_A_RXDESCRIPTOR_CURRMBUFLEN_OFFSET 12
  323. /**
  324. * @def IX_NPE_A_RXDESCRIPTOR_TIMELIMIT__OFFSET
  325. *
  326. * @brief ATM Descriptor structure offset for Receive Descriptor Time Limit field
  327. *
  328. * Contains the Payload Reassembly Time Limit (used for aal0_xx only)
  329. */
  330. #define IX_NPE_A_RXDESCRIPTOR_TIMELIMIT_OFFSET 14
  331. /**
  332. * @def IX_NPE_A_RXDESCRIPTOR_PCURRMBUFF_OFFSET
  333. *
  334. * @brief ATM Descriptor structure offset for Receive Descriptor Current MBuf Pointer
  335. *
  336. * The current mbuf pointer of a chain of mbufs.
  337. */
  338. #define IX_NPE_A_RXDESCRIPTOR_PCURRMBUFF_OFFSET 20
  339. /**
  340. * @def IX_NPE_A_RXDESCRIPTOR_PCURRMBUFDATA_OFFSET
  341. *
  342. * @brief ATM Descriptor structure offset for Receive Descriptor Current MBuf Pointer
  343. *
  344. * Pointer to the next byte to be read or next free location to be written.
  345. */
  346. #define IX_NPE_A_RXDESCRIPTOR_PCURRMBUFDATA_OFFSET 24
  347. /**
  348. * @def IX_NPE_A_RXDESCRIPTOR_PNEXTMBUF_OFFSET
  349. *
  350. * @brief ATM Descriptor structure offset for Receive Descriptor Next MBuf Pointer
  351. *
  352. * Pointer to the next MBuf in a chain of MBufs.
  353. */
  354. #define IX_NPE_A_RXDESCRIPTOR_PNEXTMBUF_OFFSET 28
  355. /**
  356. * @def IX_NPE_A_RXDESCRIPTOR_TOTALLENGTH_OFFSET
  357. *
  358. * @brief ATM Descriptor structure offset for Receive Descriptor Total Length
  359. *
  360. * Total number of bytes written to the chain of MBufs by the NPE
  361. */
  362. #define IX_NPE_A_RXDESCRIPTOR_TOTALLENGTH_OFFSET 32
  363. /**
  364. * @def IX_NPE_A_RXDESCRIPTOR_AAL5CRCRESIDUE_OFFSET
  365. *
  366. * @brief ATM Descriptor structure offset for Receive Descriptor AAL5 CRC Residue
  367. *
  368. * Current CRC value for a PDU
  369. */
  370. #define IX_NPE_A_RXDESCRIPTOR_AAL5CRCRESIDUE_OFFSET 36
  371. /**
  372. * @def IX_NPE_A_RXDESCRIPTOR_SIZE
  373. *
  374. * @brief ATM Descriptor structure offset for Receive Descriptor Size
  375. *
  376. * The size of the Receive descriptor
  377. */
  378. #define IX_NPE_A_RXDESCRIPTOR_SIZE 40
  379. /**
  380. * @def IX_NPE_A_TXDESCRIPTOR_PORT_OFFSET
  381. *
  382. * @brief ATM Descriptor structure offset for Transmit Descriptor Port
  383. *
  384. * Port identifier.
  385. */
  386. #define IX_NPE_A_TXDESCRIPTOR_PORT_OFFSET 0
  387. /**
  388. * @def IX_NPE_A_TXDESCRIPTOR_RSVD_OFFSET
  389. *
  390. * @brief ATM Descriptor structure offset for Transmit Descriptor RSVD
  391. */
  392. #define IX_NPE_A_TXDESCRIPTOR_RSVD_OFFSET 1
  393. /**
  394. * @def IX_NPE_A_TXDESCRIPTOR_CURRMBUFLEN_OFFSET
  395. *
  396. * @brief ATM Descriptor structure offset for Transmit Descriptor Current MBuf Length
  397. *
  398. * TX - Initialized by the XScale to the number of bytes in the current MBuf data buffer.
  399. * The NPE decrements this field for every transmitted cell. Thus, when the NPE writes a
  400. * descriptor the TxDone queue, this field will equal zero.
  401. */
  402. #define IX_NPE_A_TXDESCRIPTOR_CURRMBUFLEN_OFFSET 2
  403. /**
  404. * @def IX_NPE_A_TXDESCRIPTOR_ATMHEADER_OFFSET
  405. * @brief ATM Descriptor structure offset for Transmit Descriptor ATM Header
  406. */
  407. #define IX_NPE_A_TXDESCRIPTOR_ATMHEADER_OFFSET 4
  408. /**
  409. * @def IX_NPE_A_TXDESCRIPTOR_PCURRMBUFF_OFFSET
  410. *
  411. * @brief ATM Descriptor structure offset for Transmit Descriptor Pointer to the current MBuf chain
  412. */
  413. #define IX_NPE_A_TXDESCRIPTOR_PCURRMBUFF_OFFSET 8
  414. /**
  415. * @def IX_NPE_A_TXDESCRIPTOR_PCURRMBUFDATA_OFFSET
  416. *
  417. * @brief ATM Descriptor structure offset for Transmit Descriptor Pointer to the current MBuf Data
  418. *
  419. * Pointer to the next byte to be read or next free location to be written.
  420. */
  421. #define IX_NPE_A_TXDESCRIPTOR_PCURRMBUFDATA_OFFSET 12
  422. /**
  423. * @def IX_NPE_A_TXDESCRIPTOR_PNEXTMBUF_OFFSET
  424. *
  425. * @brief ATM Descriptor structure offset for Transmit Descriptor Pointer to the Next MBuf chain
  426. */
  427. #define IX_NPE_A_TXDESCRIPTOR_PNEXTMBUF_OFFSET 16
  428. /**
  429. * @def IX_NPE_A_TXDESCRIPTOR_TOTALLENGTH_OFFSET
  430. *
  431. * @brief ATM Descriptor structure offset for Transmit Descriptor Total Length
  432. *
  433. * Total number of bytes written to the chain of MBufs by the NPE
  434. */
  435. #define IX_NPE_A_TXDESCRIPTOR_TOTALLENGTH_OFFSET 20
  436. /**
  437. * @def IX_NPE_A_TXDESCRIPTOR_AAL5CRCRESIDUE_OFFSET
  438. *
  439. * @brief ATM Descriptor structure offset for Transmit Descriptor AAL5 CRC Residue
  440. *
  441. * Current CRC value for a PDU
  442. */
  443. #define IX_NPE_A_TXDESCRIPTOR_AAL5CRCRESIDUE_OFFSET 24
  444. /**
  445. * @def IX_NPE_A_TXDESCRIPTOR_SIZE
  446. *
  447. * @brief ATM Descriptor structure offset for Transmit Descriptor Size
  448. */
  449. #define IX_NPE_A_TXDESCRIPTOR_SIZE 28
  450. /**
  451. * @def IX_NPE_A_CHAIN_DESC_COUNT_MAX
  452. *
  453. * @brief Maximum number of chained MBufs that can be chained together
  454. */
  455. #define IX_NPE_A_CHAIN_DESC_COUNT_MAX 256
  456. /*
  457. * Definition of the ATM cell header
  458. *
  459. * This would most conviently be defined as the bit field shown below.
  460. * Endian portability prevents this, therefore a set of macros
  461. * are defined to access the fields within the cell header assumed to
  462. * be passed as a UINT32.
  463. *
  464. * Changes to field sizes or orders must be reflected in the offset
  465. * definitions above.
  466. *
  467. * typedef struct
  468. * {
  469. * unsigned int gfc:4;
  470. * unsigned int vpi:8;
  471. * unsigned int vci:16;
  472. * unsigned int pti:3;
  473. * unsigned int clp:1;
  474. * } IxNpeA_AtmCellHeader;
  475. *
  476. */
  477. /** Mask to acess GFC */
  478. #define GFC_MASK 0xf0000000
  479. /** return GFC from ATM cell header */
  480. #define IX_NPE_A_ATMCELLHEADER_GFC_GET( header ) \
  481. (((header) & GFC_MASK) >> 28)
  482. /** set GFC into ATM cell header */
  483. #define IX_NPE_A_ATMCELLHEADER_GFC_SET( header,gfc ) \
  484. do { \
  485. (header) &= ~GFC_MASK; \
  486. (header) |= (((gfc) << 28) & GFC_MASK); \
  487. } while(0)
  488. /** Mask to acess VPI */
  489. #define VPI_MASK 0x0ff00000
  490. /** return VPI from ATM cell header */
  491. #define IX_NPE_A_ATMCELLHEADER_VPI_GET( header ) \
  492. (((header) & VPI_MASK) >> 20)
  493. /** set VPI into ATM cell header */
  494. #define IX_NPE_A_ATMCELLHEADER_VPI_SET( header, vpi ) \
  495. do { \
  496. (header) &= ~VPI_MASK; \
  497. (header) |= (((vpi) << 20) & VPI_MASK); \
  498. } while(0)
  499. /** Mask to acess VCI */
  500. #define VCI_MASK 0x000ffff0
  501. /** return VCI from ATM cell header */
  502. #define IX_NPE_A_ATMCELLHEADER_VCI_GET( header ) \
  503. (((header) & VCI_MASK) >> 4)
  504. /** set VCI into ATM cell header */
  505. #define IX_NPE_A_ATMCELLHEADER_VCI_SET( header, vci ) \
  506. do { \
  507. (header) &= ~VCI_MASK; \
  508. (header) |= (((vci) << 4) & VCI_MASK); \
  509. } while(0)
  510. /** Mask to acess PTI */
  511. #define PTI_MASK 0x0000000e
  512. /** return PTI from ATM cell header */
  513. #define IX_NPE_A_ATMCELLHEADER_PTI_GET( header ) \
  514. (((header) & PTI_MASK) >> 1)
  515. /** set PTI into ATM cell header */
  516. #define IX_NPE_A_ATMCELLHEADER_PTI_SET( header, pti ) \
  517. do { \
  518. (header) &= ~PTI_MASK; \
  519. (header) |= (((pti) << 1) & PTI_MASK); \
  520. } while(0)
  521. /** Mask to acess CLP */
  522. #define CLP_MASK 0x00000001
  523. /** return CLP from ATM cell header */
  524. #define IX_NPE_A_ATMCELLHEADER_CLP_GET( header ) \
  525. ((header) & CLP_MASK)
  526. /** set CLP into ATM cell header */
  527. #define IX_NPE_A_ATMCELLHEADER_CLP_SET( header, clp ) \
  528. do { \
  529. (header) &= ~CLP_MASK; \
  530. (header) |= ((clp) & CLP_MASK); \
  531. } while(0)
  532. /*
  533. * Definition of the Rx bitfield
  534. *
  535. * This would most conviently be defined as the bit field shown below.
  536. * Endian portability prevents this, therefore a set of macros
  537. * are defined to access the fields within the rxBitfield assumed to
  538. * be passed as a UINT32.
  539. *
  540. * Changes to field sizes or orders must be reflected in the offset
  541. * definitions above.
  542. *
  543. * Rx bitfield
  544. * struct
  545. * { IX_NPEA_RXBITFIELD(
  546. * unsigned int status:1,
  547. * unsigned int port:7,
  548. * unsigned int vcId:8,
  549. * unsigned int currMbufSize:16);
  550. * } rxBitField;
  551. *
  552. */
  553. /** Mask to acess the rxBitField status */
  554. #define STATUS_MASK 0x80000000
  555. /** return the rxBitField status */
  556. #define IX_NPE_A_RXBITFIELD_STATUS_GET( rxbitfield ) \
  557. (((rxbitfield) & STATUS_MASK) >> 31)
  558. /** set the rxBitField status */
  559. #define IX_NPE_A_RXBITFIELD_STATUS_SET( rxbitfield, status ) \
  560. do { \
  561. (rxbitfield) &= ~STATUS_MASK; \
  562. (rxbitfield) |= (((status) << 31) & STATUS_MASK); \
  563. } while(0)
  564. /** Mask to acess the rxBitField port */
  565. #define PORT_MASK 0x7f000000
  566. /** return the rxBitField port */
  567. #define IX_NPE_A_RXBITFIELD_PORT_GET( rxbitfield ) \
  568. (((rxbitfield) & PORT_MASK) >> 24)
  569. /** set the rxBitField port */
  570. #define IX_NPE_A_RXBITFIELD_PORT_SET( rxbitfield, port ) \
  571. do { \
  572. (rxbitfield) &= ~PORT_MASK; \
  573. (rxbitfield) |= (((port) << 24) & PORT_MASK); \
  574. } while(0)
  575. /** Mask to acess the rxBitField vcId */
  576. #define VCID_MASK 0x00ff0000
  577. /** return the rxBitField vcId */
  578. #define IX_NPE_A_RXBITFIELD_VCID_GET( rxbitfield ) \
  579. (((rxbitfield) & VCID_MASK) >> 16)
  580. /** set the rxBitField vcId */
  581. #define IX_NPE_A_RXBITFIELD_VCID_SET( rxbitfield, vcid ) \
  582. do { \
  583. (rxbitfield) &= ~VCID_MASK; \
  584. (rxbitfield) |= (((vcid) << 16) & VCID_MASK); \
  585. } while(0)
  586. /** Mask to acess the rxBitField mbuf size */
  587. #define CURRMBUFSIZE_MASK 0x0000ffff
  588. /** return the rxBitField mbuf size */
  589. #define IX_NPE_A_RXBITFIELD_CURRMBUFSIZE_GET( rxbitfield ) \
  590. ((rxbitfield) & CURRMBUFSIZE_MASK)
  591. /** set the rxBitField mbuf size */
  592. #define IX_NPE_A_RXBITFIELD_CURRMBUFSIZE_SET( rxbitfield, currmbufsize ) \
  593. do { \
  594. (rxbitfield) &= ~CURRMBUFSIZE_MASK; \
  595. (rxbitfield) |= ((currmbufsize) & CURRMBUFSIZE_MASK); \
  596. } while(0)
  597. /**
  598. * @brief Tx Descriptor definition
  599. */
  600. typedef struct
  601. {
  602. UINT8 port; /**< Tx Port number */
  603. UINT8 aalType; /**< AAL Type */
  604. UINT16 currMbufLen; /**< mbuf length */
  605. UINT32 atmCellHeader; /**< ATM cell header */
  606. IX_OSAL_MBUF *pCurrMbuf; /**< pointer to mbuf */
  607. unsigned char *pCurrMbufData; /**< Pointer to mbuf->dat */
  608. IX_OSAL_MBUF *pNextMbuf; /**< Pointer to next mbuf */
  609. UINT32 totalLen; /**< Total Length */
  610. UINT32 aal5CrcResidue; /**< AAL5 CRC Residue */
  611. } IxNpeA_TxAtmVc;
  612. /* Changes to field sizes or orders must be reflected in the offset
  613. * definitions above. */
  614. /**
  615. * @brief Rx Descriptor definition
  616. */
  617. typedef struct
  618. {
  619. UINT32 rxBitField; /**< Received bit field */
  620. UINT32 atmCellHeader; /**< ATM Cell Header */
  621. UINT32 rsvdWord0; /**< Reserved field */
  622. UINT16 currMbufLen; /**< Mbuf Length */
  623. UINT8 timeLimit; /**< Payload Reassembly timeLimit (used for aal0_xx only) */
  624. UINT8 rsvdByte0; /**< Reserved field */
  625. UINT32 rsvdWord1; /**< Reserved field */
  626. IX_OSAL_MBUF *pCurrMbuf; /**< Pointer to current mbuf */
  627. unsigned char *pCurrMbufData; /**< Pointer to current mbuf->data */
  628. IX_OSAL_MBUF *pNextMbuf; /**< Pointer to next mbuf */
  629. UINT32 totalLen; /**< Total Length */
  630. UINT32 aal5CrcResidue; /**< AAL5 CRC Residue */
  631. } IxNpeA_RxAtmVc;
  632. /**
  633. * @brief NPE-A AAL Type
  634. */
  635. typedef enum
  636. {
  637. IX_NPE_A_AAL_TYPE_INVALID = 0, /**< Invalid AAL type */
  638. IX_NPE_A_AAL_TYPE_0_48 = 0x1, /**< AAL0 - 48 byte */
  639. IX_NPE_A_AAL_TYPE_0_52 = 0x2, /**< AAL0 - 52 byte */
  640. IX_NPE_A_AAL_TYPE_5 = 0x5, /**< AAL5 */
  641. IX_NPE_A_AAL_TYPE_OAM = 0xF /**< OAM */
  642. } IxNpeA_AalType;
  643. /**
  644. * @brief NPE-A Payload format 52-bytes & 48-bytes
  645. */
  646. typedef enum
  647. {
  648. IX_NPE_A_52_BYTE_PAYLOAD = 0, /**< 52 byte payload */
  649. IX_NPE_A_48_BYTE_PAYLOAD /**< 48 byte payload */
  650. } IxNpeA_PayloadFormat;
  651. /**
  652. * @brief HSS Packetized NpePacket Descriptor Structure
  653. */
  654. typedef struct
  655. {
  656. UINT8 status; /**< Status of the packet passed to the client */
  657. UINT8 errorCount; /**< Number of errors */
  658. UINT8 chainCount; /**< Mbuf chain count e.g. 0 - No mbuf chain */
  659. UINT8 rsvdByte0; /**< Reserved byte to make the descriptor word align */
  660. UINT16 packetLength; /**< Packet Length */
  661. UINT16 rsvdShort0; /**< Reserved short to make the descriptor a word align */
  662. IX_OSAL_MBUF *pRootMbuf; /**< Pointer to Root mbuf */
  663. IX_OSAL_MBUF *pNextMbuf; /**< Pointer to next mbuf */
  664. UINT8 *pMbufData; /**< Pointer to the current mbuf->data */
  665. UINT32 mbufLength; /**< Current mbuf length */
  666. } IxNpeA_NpePacketDescriptor;
  667. #endif
  668. /**
  669. *@}
  670. */
  671. #endif /* __doxygen_HIDE */