ppc440epx_grx.h 23 KB

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  1. /*
  2. * (C) Copyright 2010
  3. * Stefan Roese, DENX Software Engineering, sr@denx.de.
  4. *
  5. * This program is free software; you can redistribute it and/or
  6. * modify it under the terms of the GNU General Public License as
  7. * published by the Free Software Foundation; either version 2 of
  8. * the License, or (at your option) any later version.
  9. *
  10. * This program is distributed in the hope that it will be useful,
  11. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  12. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  13. * GNU General Public License for more details.
  14. *
  15. * You should have received a copy of the GNU General Public License
  16. * along with this program; if not, write to the Free Software
  17. * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  18. * MA 02111-1307 USA
  19. */
  20. #ifndef _PPC440EPX_GRX_H_
  21. #define _PPC440EPX_GRX_H_
  22. #define CONFIG_SDRAM_PPC4xx_DENALI_DDR2 /* Denali DDR(2) controller */
  23. #define CONFIG_NAND_NDFC
  24. /*
  25. * Some SoC specific registers (not common for all 440 SoC's)
  26. */
  27. /* Memory mapped registers */
  28. #define CONFIG_SYS_PERIPHERAL_BASE 0xef600000 /* Internal Peripherals */
  29. #define SPI0_MODE (CONFIG_SYS_PERIPHERAL_BASE + 0x0090)
  30. #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_PERIPHERAL_BASE + 0x0300)
  31. #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_PERIPHERAL_BASE + 0x0400)
  32. #define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_PERIPHERAL_BASE + 0x0500)
  33. #define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_PERIPHERAL_BASE + 0x0600)
  34. #define GPIO0_BASE (CONFIG_SYS_PERIPHERAL_BASE + 0x0b00)
  35. #define GPIO1_BASE (CONFIG_SYS_PERIPHERAL_BASE + 0x0c00)
  36. /* DCR */
  37. #define CPM0_ER 0x00b0
  38. #define CPM1_ER 0x00f0
  39. #define PLB3A0_ACR 0x0077
  40. #define PLB4A0_ACR 0x0081
  41. #define PLB4A1_ACR 0x0089
  42. #define OPB2PLB40_BCTRL 0x0350
  43. #define P4P3BO0_CFG 0x0026
  44. /* SDR */
  45. #define SDR0_DDRCFG 0x00e0
  46. #define SDR0_PCI0 0x0300
  47. #define SDR0_SDSTP2 0x4001
  48. #define SDR0_SDSTP3 0x4003
  49. #define SDR0_EMAC0RXST 0x4301
  50. #define SDR0_EMAC0TXST 0x4302
  51. #define SDR0_CRYP0 0x4500
  52. #define SDR0_SDSTP1_PAE_MASK (0x80000000 >> 21)
  53. #define SDR0_SDSTP1_PAME_MASK (0x80000000 >> 27)
  54. /* Pin Function Control Register 1 */
  55. #define SDR0_PFC1_U1ME_MASK 0x02000000 /* UART1 Mode Enable */
  56. #define SDR0_PFC1_U1ME_DSR_DTR 0x00000000 /* UART1 in DSR/DTR Mode */
  57. #define SDR0_PFC1_U1ME_CTS_RTS 0x02000000 /* UART1 in CTS/RTS Mode */
  58. #define SDR0_PFC1_SELECT_MASK 0x01C00000 /* Ethernet Pin Select
  59. EMAC 0 */
  60. #define SDR0_PFC1_SELECT_CONFIG_1_1 0x00C00000 /* 1xMII using RGMII
  61. bridge */
  62. #define SDR0_PFC1_SELECT_CONFIG_1_2 0x00000000 /* 1xMII using ZMII
  63. bridge */
  64. #define SDR0_PFC1_SELECT_CONFIG_2 0x00C00000 /* 1xGMII using RGMII
  65. bridge */
  66. #define SDR0_PFC1_SELECT_CONFIG_3 0x01000000 /* 1xTBI using RGMII
  67. bridge */
  68. #define SDR0_PFC1_SELECT_CONFIG_4 0x01400000 /* 2xRGMII using RGMII
  69. bridge */
  70. #define SDR0_PFC1_SELECT_CONFIG_5 0x01800000 /* 2xRTBI using RGMII
  71. bridge */
  72. #define SDR0_PFC1_SELECT_CONFIG_6 0x00800000 /* 2xSMII using ZMII
  73. bridge */
  74. #define SDR0_PFC1_U0ME_MASK 0x00080000 /* UART0 Mode Enable */
  75. #define SDR0_PFC1_U0ME_DSR_DTR 0x00000000 /* UART0 in DSR/DTR Mode */
  76. #define SDR0_PFC1_U0ME_CTS_RTS 0x00080000 /* UART0 in CTS/RTS Mode */
  77. #define SDR0_PFC1_U0IM_MASK 0x00040000 /* UART0 Interface Mode */
  78. #define SDR0_PFC1_U0IM_8PINS 0x00000000 /* UART0 Interface Mode 8 pins */
  79. #define SDR0_PFC1_U0IM_4PINS 0x00040000 /* UART0 Interface Mode 4 pins */
  80. #define SDR0_PFC1_SIS_MASK 0x00020000 /* SCP or IIC1 Selection */
  81. #define SDR0_PFC1_SIS_SCP_SEL 0x00000000 /* SCP Selected */
  82. #define SDR0_PFC1_SIS_IIC1_SEL 0x00020000 /* IIC1 Selected */
  83. #define SDR0_PFC1_UES_MASK 0x00010000 /* USB2D_RX_Active / EBC_Hold
  84. Req Selection */
  85. #define SDR0_PFC1_UES_USB2D_SEL 0x00000000 /* USB2D_RX_Active Selected */
  86. #define SDR0_PFC1_UES_EBCHR_SEL 0x00010000 /* EBC_Hold Req Selected */
  87. #define SDR0_PFC1_DIS_MASK 0x00008000 /* DMA_Req(1) / UIC_IRQ(5)
  88. Selection */
  89. #define SDR0_PFC1_DIS_DMAR_SEL 0x00000000 /* DMA_Req(1) Selected */
  90. #define SDR0_PFC1_DIS_UICIRQ5_SEL 0x00008000 /* UIC_IRQ(5) Selected */
  91. #define SDR0_PFC1_ERE_MASK 0x00004000 /* EBC Mast.Ext.Req.En./GPIO0(27)
  92. Selection */
  93. #define SDR0_PFC1_ERE_EXTR_SEL 0x00000000 /* EBC Mast.Ext.Req.En.
  94. Selected */
  95. #define SDR0_PFC1_ERE_GPIO0_27_SEL 0x00004000 /* GPIO0(27) Selected */
  96. #define SDR0_PFC1_UPR_MASK 0x00002000 /* USB2 Device Packet Reject
  97. Selection */
  98. #define SDR0_PFC1_UPR_DISABLE 0x00000000 /* USB2 Device Packet Reject
  99. Disable */
  100. #define SDR0_PFC1_UPR_ENABLE 0x00002000 /* USB2 Device Packet Reject
  101. Enable */
  102. #define SDR0_PFC1_PLB_PME_MASK 0x00001000 /* PLB3/PLB4 Perf. Monitor Enable
  103. Selection */
  104. #define SDR0_PFC1_PLB_PME_PLB3_SEL 0x00000000 /* PLB3 Performance Monitor
  105. Enable */
  106. #define SDR0_PFC1_PLB_PME_PLB4_SEL 0x00001000 /* PLB3 Performance Monitor
  107. Enable */
  108. #define SDR0_PFC1_GFGGI_MASK 0x0000000F /* GPT Frequency Generation
  109. Gated In */
  110. #define SDR0_PFC2_SELECT_MASK 0xe0000000 /* Ethernet Pin select EMAC1 */
  111. #define SDR0_PFC2_SELECT_CONFIG_1_1 0x60000000 /* 1xMII using RGMII bridge */
  112. #define SDR0_PFC2_SELECT_CONFIG_1_2 0x00000000 /* 1xMII using ZMII bridge */
  113. #define SDR0_PFC2_SELECT_CONFIG_2 0x60000000 /* 1xGMII using RGMII bridge */
  114. #define SDR0_PFC2_SELECT_CONFIG_3 0x80000000 /* 1xTBI using RGMII bridge */
  115. #define SDR0_PFC2_SELECT_CONFIG_4 0xa0000000 /* 2xRGMII using RGMII bridge */
  116. #define SDR0_PFC2_SELECT_CONFIG_5 0xc0000000 /* 2xRTBI using RGMII bridge */
  117. #define SDR0_PFC2_SELECT_CONFIG_6 0x40000000 /* 2xSMII using ZMII bridge */
  118. #define SDR0_USB2D0CR 0x0320
  119. #define SDR0_USB2D0CR_USB2DEV_EBC_SEL_MASK 0x00000004 /* USB 2.0 Device/EBC
  120. Master Selection */
  121. #define SDR0_USB2D0CR_USB2DEV_SELECTION 0x00000004 /* USB 2.0 Device Selection*/
  122. #define SDR0_USB2D0CR_EBC_SELECTION 0x00000000 /* EBC Selection */
  123. #define SDR0_USB2D0CR_USB_DEV_INT_SEL_MASK 0x00000002 /* USB Device Interface
  124. Selection */
  125. #define SDR0_USB2D0CR_USB20D_DEVSEL 0x00000000 /* USB2.0 Device Selected */
  126. #define SDR0_USB2D0CR_USB11D_DEVSEL 0x00000002 /* USB1.1 Device Selected */
  127. #define SDR0_USB2D0CR_LEEN_MASK 0x00000001 /* Little Endian selection */
  128. #define SDR0_USB2D0CR_LEEN_DISABLE 0x00000000 /* Little Endian Disable */
  129. #define SDR0_USB2D0CR_LEEN_ENABLE 0x00000001 /* Little Endian Enable */
  130. /* USB2 Host Control Register */
  131. #define SDR0_USB2H0CR 0x0340
  132. #define SDR0_USB2H0CR_WDINT_MASK 0x00000001 /* Host UTMI Word Interface*/
  133. #define SDR0_USB2H0CR_WDINT_8BIT_60MHZ 0x00000000 /* 8-bit/60MHz */
  134. #define SDR0_USB2H0CR_WDINT_16BIT_30MHZ 0x00000001 /* 16-bit/30MHz */
  135. #define SDR0_USB2H0CR_EFLADJ_MASK 0x0000007e /* EHCI Frame Length
  136. Adjustment */
  137. /* USB2PHY0 Control Register */
  138. #define SDR0_USB2PHY0CR 0x4103
  139. #define SDR0_USB2PHY0CR_UTMICN_MASK 0x00100000
  140. /* PHY UTMI interface connection */
  141. #define SDR0_USB2PHY0CR_UTMICN_DEV 0x00000000 /* Device support */
  142. #define SDR0_USB2PHY0CR_UTMICN_HOST 0x00100000 /* Host support */
  143. #define SDR0_USB2PHY0CR_DWNSTR_MASK 0x00400000 /* Select downstream port mode */
  144. #define SDR0_USB2PHY0CR_DWNSTR_DEV 0x00000000 /* Device */
  145. #define SDR0_USB2PHY0CR_DWNSTR_HOST 0x00400000 /* Host */
  146. /* VBus detect (Device mode only) */
  147. #define SDR0_USB2PHY0CR_DVBUS_MASK 0x00800000
  148. /* Pull-up resistance on D+ is disabled */
  149. #define SDR0_USB2PHY0CR_DVBUS_PURDIS 0x00000000
  150. /* Pull-up resistance on D+ is enabled */
  151. #define SDR0_USB2PHY0CR_DVBUS_PUREN 0x00800000
  152. /* PHY UTMI data width and clock select */
  153. #define SDR0_USB2PHY0CR_WDINT_MASK 0x01000000
  154. #define SDR0_USB2PHY0CR_WDINT_8BIT_60MHZ 0x00000000 /* 8-bit data/60MHz */
  155. #define SDR0_USB2PHY0CR_WDINT_16BIT_30MHZ 0x01000000 /* 16-bit data/30MHz */
  156. #define SDR0_USB2PHY0CR_LOOPEN_MASK 0x02000000 /* Loop back test enable */
  157. #define SDR0_USB2PHY0CR_LOOP_ENABLE 0x00000000 /* Loop back disabled */
  158. /* Loop back enabled (only test purposes) */
  159. #define SDR0_USB2PHY0CR_LOOP_DISABLE 0x02000000
  160. /* Force XO block on during a suspend */
  161. #define SDR0_USB2PHY0CR_XOON_MASK 0x04000000
  162. #define SDR0_USB2PHY0CR_XO_ON 0x00000000 /* PHY XO block is powered-on */
  163. /* PHY XO block is powered-off when all ports are suspended */
  164. #define SDR0_USB2PHY0CR_XO_OFF 0x04000000
  165. #define SDR0_USB2PHY0CR_PWRSAV_MASK 0x08000000 /* Select PHY power-save mode */
  166. #define SDR0_USB2PHY0CR_PWRSAV_OFF 0x00000000 /* Non-power-save mode */
  167. #define SDR0_USB2PHY0CR_PWRSAV_ON 0x08000000 /* Power-save mode. Valid only
  168. for full-speed operation */
  169. #define SDR0_USB2PHY0CR_XOREF_MASK 0x10000000 /* Select reference clock
  170. source */
  171. #define SDR0_USB2PHY0CR_XOREF_INTERNAL 0x00000000 /* PHY PLL uses chip internal
  172. 48M clock as a reference */
  173. #define SDR0_USB2PHY0CR_XOREF_XO 0x10000000 /* PHY PLL uses internal XO
  174. block output as a reference */
  175. #define SDR0_USB2PHY0CR_XOCLK_MASK 0x20000000 /* Select clock for XO
  176. block*/
  177. #define SDR0_USB2PHY0CR_XOCLK_EXTERNAL 0x00000000 /* PHY macro used an external
  178. clock */
  179. #define SDR0_USB2PHY0CR_XOCLK_CRYSTAL 0x20000000 /* PHY macro uses the clock
  180. from a crystal */
  181. #define SDR0_USB2PHY0CR_CLKSEL_MASK 0xc0000000 /* Select ref clk freq */
  182. #define SDR0_USB2PHY0CR_CLKSEL_12MHZ 0x00000000 /* Select ref clk freq
  183. = 12 MHz */
  184. #define SDR0_USB2PHY0CR_CLKSEL_48MHZ 0x40000000 /* Select ref clk freq
  185. = 48 MHz */
  186. #define SDR0_USB2PHY0CR_CLKSEL_24MHZ 0x80000000 /* Select ref clk freq
  187. = 24 MHz */
  188. /* USB2.0 Device */
  189. /*
  190. * todo: check if this can be completely removed, only used in
  191. * cpu/ppc4xx/usbdev.c. And offsets are completely wrong. This could
  192. * never have actually worked. Best probably is to remove this
  193. * usbdev.c file completely (and these defines).
  194. */
  195. #define USB2D0_BASE CONFIG_SYS_USB2D0_BASE
  196. #define USB2D0_INTRIN (USB2D0_BASE + 0x00000000)
  197. #define USB2D0_INTRIN (USB2D0_BASE + 0x00000000) /* Interrupt register for
  198. Endpoint 0 plus IN Endpoints 1 to 3 */
  199. #define USB2D0_POWER (USB2D0_BASE + 0x00000000) /* Power management
  200. register */
  201. #define USB2D0_FADDR (USB2D0_BASE + 0x00000000) /* Function address
  202. register */
  203. #define USB2D0_INTRINE (USB2D0_BASE + 0x00000000) /* Interrupt enable
  204. register for USB2D0_INTRIN */
  205. #define USB2D0_INTROUT (USB2D0_BASE + 0x00000000) /* Interrupt register for
  206. OUT Endpoints 1 to 3 */
  207. #define USB2D0_INTRUSBE (USB2D0_BASE + 0x00000000) /* Interrupt enable
  208. register for USB2D0_INTRUSB */
  209. #define USB2D0_INTRUSB (USB2D0_BASE + 0x00000000) /* Interrupt register for
  210. common USB interrupts */
  211. #define USB2D0_INTROUTE (USB2D0_BASE + 0x00000000) /* Interrupt enable
  212. register for IntrOut */
  213. #define USB2D0_TSTMODE (USB2D0_BASE + 0x00000000) /* Enables the USB 2.0
  214. test modes */
  215. #define USB2D0_INDEX (USB2D0_BASE + 0x00000000) /* Index register for
  216. selecting the Endpoint status/control registers */
  217. #define USB2D0_FRAME (USB2D0_BASE + 0x00000000) /* Frame number */
  218. #define USB2D0_INCSR0 (USB2D0_BASE + 0x00000000) /* Control Status
  219. register for Endpoint 0. (Index register set to select Endpoint 0) */
  220. #define USB2D0_INCSR (USB2D0_BASE + 0x00000000) /* Control Status
  221. register for IN Endpoint. (Index register set to select Endpoints 13) */
  222. #define USB2D0_INMAXP (USB2D0_BASE + 0x00000000) /* Maximum packet
  223. size for IN Endpoint. (Index register set to select Endpoints 13) */
  224. #define USB2D0_OUTCSR (USB2D0_BASE + 0x00000000) /* Control Status
  225. register for OUT Endpoint. (Index register set to select Endpoints 13) */
  226. #define USB2D0_OUTMAXP (USB2D0_BASE + 0x00000000) /* Maximum packet
  227. size for OUT Endpoint. (Index register set to select Endpoints 13) */
  228. #define USB2D0_OUTCOUNT0 (USB2D0_BASE + 0x00000000) /* Number of received
  229. bytes in Endpoint 0 FIFO. (Index register set to select Endpoint 0) */
  230. #define USB2D0_OUTCOUNT (USB2D0_BASE + 0x00000000) /* Number of bytes in
  231. OUT Endpoint FIFO. (Index register set to select Endpoints 13) */
  232. /* Miscealleneaous Function Reg. */
  233. #define SDR0_MFR_ETH0_CLK_SEL_MASK 0x08000000 /* Ethernet0 Clock Select */
  234. #define SDR0_MFR_ETH0_CLK_SEL_EXT 0x00000000
  235. #define SDR0_MFR_ETH1_CLK_SEL_MASK 0x04000000 /* Ethernet1 Clock Select */
  236. #define SDR0_MFR_ETH1_CLK_SEL_EXT 0x00000000
  237. #define SDR0_MFR_ZMII_MODE_MASK 0x03000000 /* ZMII Mode Mask */
  238. #define SDR0_MFR_ZMII_MODE_MII 0x00000000 /* ZMII Mode MII */
  239. #define SDR0_MFR_ZMII_MODE_SMII 0x01000000 /* ZMII Mode SMII */
  240. #define SDR0_MFR_ZMII_MODE_BIT0 0x02000000 /* ZMII Mode Bit0 */
  241. #define SDR0_MFR_ZMII_MODE_BIT1 0x01000000 /* ZMII Mode Bit1 */
  242. #define SDR0_MFR_ZM_ENCODE(n) ((((u32)(n)) & 0x3) << 24)
  243. #define SDR0_MFR_ZM_DECODE(n) ((((u32)(n)) << 24) & 0x3)
  244. #define SDR0_MFR_PKT_REJ_MASK 0x00300000 /* Pkt Rej. Enable Mask */
  245. #define SDR0_MFR_PKT_REJ_EN 0x00300000 /* Pkt Rej. Ena. on both EMAC3 0-1 */
  246. #define SDR0_MFR_PKT_REJ_EN0 0x00200000 /* Pkt Rej. Enable on EMAC3(0) */
  247. #define SDR0_MFR_PKT_REJ_EN1 0x00100000 /* Pkt Rej. Enable on EMAC3(1) */
  248. #define SDR0_MFR_PKT_REJ_POL 0x00080000 /* Packet Reject Polarity */
  249. /* CUST0 Customer Configuration Register0 */
  250. #define SDR0_CUST0_MUX_E_N_G_MASK 0xC0000000 /* Mux_Emac_NDFC_GPIO */
  251. #define SDR0_CUST0_MUX_EMAC_SEL 0x40000000 /* Emac Selection */
  252. #define SDR0_CUST0_MUX_NDFC_SEL 0x80000000 /* NDFC Selection */
  253. #define SDR0_CUST0_MUX_GPIO_SEL 0xC0000000 /* GPIO Selection */
  254. #define SDR0_CUST0_NDFC_EN_MASK 0x20000000 /* NDFC Enable Mask */
  255. #define SDR0_CUST0_NDFC_ENABLE 0x20000000 /* NDFC Enable */
  256. #define SDR0_CUST0_NDFC_DISABLE 0x00000000 /* NDFC Disable */
  257. #define SDR0_CUST0_NDFC_BW_MASK 0x10000000 /* NDFC Boot Width */
  258. #define SDR0_CUST0_NDFC_BW_16_BIT 0x10000000 /* NDFC Boot Width = 16 Bit */
  259. #define SDR0_CUST0_NDFC_BW_8_BIT 0x00000000 /* NDFC Boot Width = 8 Bit */
  260. #define SDR0_CUST0_NDFC_BP_MASK 0x0F000000 /* NDFC Boot Page */
  261. #define SDR0_CUST0_NDFC_BP_ENCODE(n) ((((u32)(n)) & 0xF) << 24)
  262. #define SDR0_CUST0_NDFC_BP_DECODE(n) ((((u32)(n)) >> 24) & 0xF)
  263. #define SDR0_CUST0_NDFC_BAC_MASK 0x00C00000 /* NDFC Boot Address Cycle */
  264. #define SDR0_CUST0_NDFC_BAC_ENCODE(n) ((((u32)(n)) & 0x3) << 22)
  265. #define SDR0_CUST0_NDFC_BAC_DECODE(n) ((((u32)(n)) >> 22) & 0x3)
  266. #define SDR0_CUST0_NDFC_ARE_MASK 0x00200000 /* NDFC Auto Read Enable */
  267. #define SDR0_CUST0_NDFC_ARE_ENABLE 0x00200000 /* NDFC Auto Read Enable */
  268. #define SDR0_CUST0_NDFC_ARE_DISABLE 0x00000000 /* NDFC Auto Read Disable */
  269. #define SDR0_CUST0_NRB_MASK 0x00100000 /* NDFC Ready / Busy */
  270. #define SDR0_CUST0_NRB_BUSY 0x00100000 /* Busy */
  271. #define SDR0_CUST0_NRB_READY 0x00000000 /* Ready */
  272. #define SDR0_CUST0_NDRSC_MASK 0x0000FFF0 /* NDFC Device Reset Count Mask */
  273. #define SDR0_CUST0_NDRSC_ENCODE(n) ((((u32)(n)) & 0xFFF) << 4)
  274. #define SDR0_CUST0_NDRSC_DECODE(n) ((((u32)(n)) >> 4) & 0xFFF)
  275. #define SDR0_CUST0_CHIPSELGAT_MASK 0x0000000F /* Chip Select Gating Mask */
  276. #define SDR0_CUST0_CHIPSELGAT_DIS 0x00000000 /* Chip Select Gating Disable */
  277. #define SDR0_CUST0_CHIPSELGAT_ENALL 0x0000000F /*All Chip Select Gating Enable*/
  278. #define SDR0_CUST0_CHIPSELGAT_EN0 0x00000008 /* Chip Select0 Gating Enable */
  279. #define SDR0_CUST0_CHIPSELGAT_EN1 0x00000004 /* Chip Select1 Gating Enable */
  280. #define SDR0_CUST0_CHIPSELGAT_EN2 0x00000002 /* Chip Select2 Gating Enable */
  281. #define SDR0_CUST0_CHIPSELGAT_EN3 0x00000001 /* Chip Select3 Gating Enable */
  282. #define SDR0_SRST0_BGO 0x80000000 /* PLB to OPB bridge */
  283. #define SDR0_SRST0_PLB4 0x40000000 /* PLB4 arbiter */
  284. #define SDR0_SRST0_EBC 0x20000000 /* External bus controller */
  285. #define SDR0_SRST0_OPB 0x10000000 /* OPB arbiter */
  286. #define SDR0_SRST0_UART0 0x08000000 /* Universal asynchronous receiver/
  287. transmitter 0 */
  288. #define SDR0_SRST0_UART1 0x04000000 /* Universal asynchronous receiver/
  289. transmitter 1 */
  290. #define SDR0_SRST0_IIC0 0x02000000 /* Inter integrated circuit 0 */
  291. #define SDR0_SRST0_USB2H 0x01000000 /* USB2.0 Host */
  292. #define SDR0_SRST0_GPIO 0x00800000 /* General purpose I/O */
  293. #define SDR0_SRST0_GPT 0x00400000 /* General purpose timer */
  294. #define SDR0_SRST0_DMC 0x00200000 /* DDR SDRAM memory controller */
  295. #define SDR0_SRST0_PCI 0x00100000 /* PCI */
  296. #define SDR0_SRST0_EMAC0 0x00080000 /* Ethernet media access controller 0 */
  297. #define SDR0_SRST0_EMAC1 0x00040000 /* Ethernet media access controller 1 */
  298. #define SDR0_SRST0_CPM0 0x00020000 /* Clock and power management */
  299. #define SDR0_SRST0_ZMII 0x00010000 /* ZMII bridge */
  300. #define SDR0_SRST0_UIC0 0x00008000 /* Universal interrupt controller 0 */
  301. #define SDR0_SRST0_UIC1 0x00004000 /* Universal interrupt controller 1 */
  302. #define SDR0_SRST0_IIC1 0x00002000 /* Inter integrated circuit 1 */
  303. #define SDR0_SRST0_SCP 0x00001000 /* Serial communications port */
  304. #define SDR0_SRST0_BGI 0x00000800 /* OPB to PLB bridge */
  305. #define SDR0_SRST0_DMA 0x00000400 /* Direct memory access controller */
  306. #define SDR0_SRST0_DMAC 0x00000200 /* DMA channel */
  307. #define SDR0_SRST0_MAL 0x00000100 /* Media access layer */
  308. #define SDR0_SRST0_USB2D 0x00000080 /* USB2.0 device */
  309. #define SDR0_SRST0_GPTR 0x00000040 /* General purpose timer */
  310. #define SDR0_SRST0_P4P3 0x00000010 /* PLB4 to PLB3 bridge */
  311. #define SDR0_SRST0_P3P4 0x00000008 /* PLB3 to PLB4 bridge */
  312. #define SDR0_SRST0_PLB3 0x00000004 /* PLB3 arbiter */
  313. #define SDR0_SRST0_UART2 0x00000002 /* Universal asynchronous receiver/
  314. transmitter 2 */
  315. #define SDR0_SRST0_UART3 0x00000001 /* Universal asynchronous receiver/
  316. transmitter 3 */
  317. #define SDR0_SRST1_NDFC 0x80000000 /* Nand flash controller */
  318. #define SDR0_SRST1_OPBA1 0x40000000 /* OPB Arbiter attached to PLB4 */
  319. #define SDR0_SRST1_P4OPB0 0x20000000 /* PLB4 to OPB Bridge0 */
  320. #define SDR0_SRST1_PLB42OPB0 SDR0_SRST1_P4OPB0
  321. #define SDR0_SRST1_DMA4 0x10000000 /* DMA to PLB4 */
  322. #define SDR0_SRST1_DMA4CH 0x08000000 /* DMA Channel to PLB4 */
  323. #define SDR0_SRST1_OPBA2 0x04000000 /* OPB Arbiter attached to PLB4
  324. USB 2.0 Host */
  325. #define SDR0_SRST1_OPB2PLB40 0x02000000 /* OPB to PLB4 Bridge attached to
  326. USB 2.0 Host */
  327. #define SDR0_SRST1_PLB42OPB1 0x01000000 /* PLB4 to OPB Bridge attached to
  328. USB 2.0 Host */
  329. #define SDR0_SRST1_CPM1 0x00800000 /* Clock and Power management 1 */
  330. #define SDR0_SRST1_UIC2 0x00400000 /* Universal Interrupt Controller 2*/
  331. #define SDR0_SRST1_CRYP0 0x00200000 /* Security Engine */
  332. #define SDR0_SRST1_USB20PHY 0x00100000 /* USB 2.0 Phy */
  333. #define SDR0_SRST1_USB2HUTMI 0x00080000 /* USB 2.0 Host UTMI Interface */
  334. #define SDR0_SRST1_USB2HPHY 0x00040000 /* USB 2.0 Host Phy Interface */
  335. #define SDR0_SRST1_SRAM0 0x00020000 /* Internal SRAM Controller */
  336. #define SDR0_SRST1_RGMII0 0x00010000 /* RGMII Bridge */
  337. #define SDR0_SRST1_ETHPLL 0x00008000 /* Ethernet PLL */
  338. #define SDR0_SRST1_FPU 0x00004000 /* Floating Point Unit */
  339. #define SDR0_SRST1_KASU0 0x00002000 /* Kasumi Engine */
  340. #define PLLSYS0_ENG_MASK 0x80000000 /* 0 = SysClk, 1 = PLL VCO */
  341. #define PLLSYS0_SRC_MASK 0x40000000 /* 0 = PLL A, 1 = PLL B */
  342. #define PLLSYS0_SEL_MASK 0x38000000 /* 0 = PLL, 1 = CPU, 5 = PerClk */
  343. #define PLLSYS0_TUNE_MASK 0x07fe0000 /* PLL Tune bits */
  344. #define PLLSYS0_FB_DIV_MASK 0x0001f000 /* Feedback divisor */
  345. #define PLLSYS0_FWD_DIV_A_MASK 0x00000f00 /* Fwd Div A */
  346. #define PLLSYS0_FWD_DIV_B_MASK 0x000000e0 /* Fwd Div B */
  347. #define PLLSYS0_PRI_DIV_B_MASK 0x0000001c /* PLL Primary Divisor B */
  348. #define PLLSYS0_OPB_DIV_MASK 0x00000003 /* OPB Divisor */
  349. #define PLLC_ENG_MASK 0x20000000 /* PLL primary forward divisor source */
  350. #define PLLC_SRC_MASK 0x20000000 /* PLL feedback source */
  351. #define PLLD_FBDV_MASK 0x1f000000 /* PLL Feedback Divisor */
  352. #define PLLD_FWDVA_MASK 0x000f0000 /* PLL Forward Divisor A */
  353. #define PLLD_FWDVB_MASK 0x00000700 /* PLL Forward Divisor B */
  354. #define PLLD_LFBDV_MASK 0x0000003f /* PLL Local Feedback Divisor */
  355. #define OPBDDV_MASK 0x03000000 /* OPB Clock Divisor Register */
  356. #define PERDV_MASK 0x07000000 /* Peripheral Clock Divisor */
  357. #define PRADV_MASK 0x07000000 /* Primary Divisor A */
  358. #define PRBDV_MASK 0x07000000 /* Primary Divisor B */
  359. #define SPCID_MASK 0x03000000 /* Sync PCI Divisor */
  360. /* Strap 1 Register */
  361. #define PLLSYS1_LF_DIV_MASK 0xfc000000 /* PLL Local Feedback Divisor */
  362. #define PLLSYS1_PERCLK_DIV_MASK 0x03000000 /* Peripheral Clk Divisor */
  363. #define PLLSYS1_MAL_DIV_MASK 0x00c00000 /* MAL Clk Divisor */
  364. #define PLLSYS1_RW_MASK 0x00300000 /* ROM width */
  365. #define PLLSYS1_EAR_MASK 0x00080000 /* ERAP Address reset vector */
  366. #define PLLSYS1_PAE_MASK 0x00040000 /* PCI arbitor enable */
  367. #define PLLSYS1_PCHE_MASK 0x00020000 /* PCI host config enable */
  368. #define PLLSYS1_PISE_MASK 0x00010000 /* PCI init seq. enable */
  369. #define PLLSYS1_PCWE_MASK 0x00008000 /* PCI local cpu wait enable */
  370. #define PLLSYS1_PPIM_MASK 0x00007800 /* PCI inbound map */
  371. #define PLLSYS1_PR64E_MASK 0x00000400 /* PCI init Req64 enable */
  372. #define PLLSYS1_PXFS_MASK 0x00000300 /* PCI-X Freq Sel */
  373. #define PLLSYS1_RSVD_MASK 0x00000080 /* RSVD */
  374. #define PLLSYS1_PDM_MASK 0x00000040 /* PCI-X Driver Mode */
  375. #define PLLSYS1_EPS_MASK 0x00000038 /* Ethernet Pin Select */
  376. #define PLLSYS1_RMII_MASK 0x00000004 /* RMII Mode */
  377. #define PLLSYS1_TRE_MASK 0x00000002 /* GPIO Trace Enable */
  378. #define PLLSYS1_NTO1_MASK 0x00000001 /* CPU:PLB N-to-1 ratio */
  379. #define CPR0_ICFG_RLI_MASK 0x80000000
  380. #define CPR0_ICFG_ICS_MASK 0x00000007
  381. #define CPR0_SPCID_SPCIDV0_MASK 0x03000000
  382. #define CPR0_SPCID_SPCIDV0_DIV1 0x01000000
  383. #define CPR0_SPCID_SPCIDV0_DIV2 0x02000000
  384. #define CPR0_SPCID_SPCIDV0_DIV3 0x03000000
  385. #define CPR0_SPCID_SPCIDV0_DIV4 0x00000000
  386. #define CPR0_PERD_PERDV0_MASK 0x07000000
  387. #define PCI_MMIO_LCR_BASE (CONFIG_SYS_PCI_BASE + 0x0f400000) /* Real =>
  388. 0x0EF400000 */
  389. /* PCI Master Local Configuration Registers */
  390. #define PCIL0_PMM0LA (PCI_MMIO_LCR_BASE + 0x00) /* PMM0 Local Address */
  391. #define PCIL0_PMM0MA (PCI_MMIO_LCR_BASE + 0x04) /* PMM0 Mask/Attribute */
  392. #define PCIL0_PMM0PCILA (PCI_MMIO_LCR_BASE + 0x08) /* PMM0 PCI Low Address */
  393. #define PCIL0_PMM0PCIHA (PCI_MMIO_LCR_BASE + 0x0C) /* PMM0 PCI High Address */
  394. #define PCIL0_PMM1LA (PCI_MMIO_LCR_BASE + 0x10) /* PMM1 Local Address */
  395. #define PCIL0_PMM1MA (PCI_MMIO_LCR_BASE + 0x14) /* PMM1 Mask/Attribute */
  396. #define PCIL0_PMM1PCILA (PCI_MMIO_LCR_BASE + 0x18) /* PMM1 PCI Low Address */
  397. #define PCIL0_PMM1PCIHA (PCI_MMIO_LCR_BASE + 0x1C) /* PMM1 PCI High Address */
  398. #define PCIL0_PMM2LA (PCI_MMIO_LCR_BASE + 0x20) /* PMM2 Local Address */
  399. #define PCIL0_PMM2MA (PCI_MMIO_LCR_BASE + 0x24) /* PMM2 Mask/Attribute */
  400. #define PCIL0_PMM2PCILA (PCI_MMIO_LCR_BASE + 0x28) /* PMM2 PCI Low Address */
  401. #define PCIL0_PMM2PCIHA (PCI_MMIO_LCR_BASE + 0x2C) /* PMM2 PCI High Address */
  402. /* PCI Target Local Configuration Registers */
  403. #define PCIL0_PTM1MS (PCI_MMIO_LCR_BASE + 0x30) /* PTM1 Memory Size/
  404. Attribute */
  405. #define PCIL0_PTM1LA (PCI_MMIO_LCR_BASE + 0x34) /* PTM1 Local Addr. Reg */
  406. #define PCIL0_PTM2MS (PCI_MMIO_LCR_BASE + 0x38) /* PTM2 Memory Size/
  407. Attribute */
  408. #define PCIL0_PTM2LA (PCI_MMIO_LCR_BASE + 0x3C) /* PTM2 Local Addr. Reg */
  409. /* 440EPx boot strap options */
  410. #define BOOT_STRAP_OPTION_A 0x00000000
  411. #define BOOT_STRAP_OPTION_B 0x00000001
  412. #define BOOT_STRAP_OPTION_D 0x00000003
  413. #define BOOT_STRAP_OPTION_E 0x00000004
  414. #endif /* _PPC440EPX_GRX_H_ */