mpc5xxx_sdma.h 3.1 KB

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  1. /*
  2. * (C) Copyright 2003
  3. * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
  4. *
  5. * This file is based on code
  6. * (C) Copyright Motorola, Inc., 2000
  7. *
  8. * odin smartdma header file
  9. */
  10. #ifndef __MPC5XXX_SDMA_H
  11. #define __MPC5XXX_SDMA_H
  12. #include <common.h>
  13. #include <mpc5xxx.h>
  14. /* Task number assignment */
  15. #define FEC_RECV_TASK_NO 0
  16. #define FEC_XMIT_TASK_NO 1
  17. /*---------------------------------------------------------------------*/
  18. /* Stuff for Ethernet Tx/Rx tasks */
  19. /*---------------------------------------------------------------------*/
  20. /* Layout of Ethernet controller Parameter SRAM area:
  21. ----------------------------------------------------------------
  22. 0x00: TBD_BASE, base address of TX BD ring
  23. 0x04: TBD_NEXT, address of next TX BD to be processed
  24. 0x08: RBD_BASE, base address of RX BD ring
  25. 0x0C: RBD_NEXT, address of next RX BD to be processed
  26. ---------------------------------------------------------------
  27. ALL PARAMETERS ARE ALL LONGWORDS (FOUR BYTES EACH).
  28. */
  29. /* base address of SRAM area to store parameters used by Ethernet tasks */
  30. #define FEC_PARAM_BASE (MPC5XXX_SRAM + 0x0800)
  31. /* base address of SRAM area for buffer descriptors */
  32. #define FEC_BD_BASE (MPC5XXX_SRAM + 0x0820)
  33. /*---------------------------------------------------------------------*/
  34. /* common shortcuts used by driver C code */
  35. /*---------------------------------------------------------------------*/
  36. /* Disable SmartDMA task */
  37. #define SDMA_TASK_DISABLE(tasknum) \
  38. { \
  39. volatile ushort *tcr = (ushort *)(MPC5XXX_SDMA + 0x0000001c + 2 * tasknum); \
  40. *tcr = (*tcr) & (~0x8000); \
  41. }
  42. /* Enable SmartDMA task */
  43. #define SDMA_TASK_ENABLE(tasknum) \
  44. { \
  45. volatile ushort *tcr = (ushort *) (MPC5XXX_SDMA + 0x0000001c + 2 * tasknum); \
  46. *tcr = (*tcr) | 0x8000; \
  47. }
  48. /* Enable interrupt */
  49. #define SDMA_INT_ENABLE(tasknum) \
  50. { \
  51. struct mpc5xxx_sdma *sdma = (struct mpc5xxx_sdma *)MPC5XXX_SDMA; \
  52. sdma->IntMask &= ~(1 << tasknum); \
  53. }
  54. /* Disable interrupt */
  55. #define SDMA_INT_DISABLE(tasknum) \
  56. { \
  57. struct mpc5xxx_sdma *sdma = (struct mpc5xxx_sdma *)MPC5XXX_SDMA; \
  58. sdma->IntMask |= (1 << tasknum); \
  59. }
  60. /* Clear interrupt pending bits */
  61. #define SDMA_CLEAR_IEVENT(tasknum) \
  62. { \
  63. struct mpc5xxx_sdma *sdma = (struct mpc5xxx_sdma *)MPC5XXX_SDMA; \
  64. sdma->IntPend = (1 << tasknum); \
  65. }
  66. /* get interrupt pending bit of a task */
  67. #define SDMA_GET_PENDINGBIT(tasknum) \
  68. ((*(vu_long *)(MPC5XXX_SDMA + 0x14)) & (1<<(tasknum)))
  69. /* get interrupt mask bit of a task */
  70. #define SDMA_GET_MASKBIT(tasknum) \
  71. ((*(vu_long *)(MPC5XXX_SDMA + 0x18)) & (1<<(tasknum)))
  72. #endif /* __MPC5XXX_SDMA_H */