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  1. /*
  2. * armboot - Startup Code for ARM720 CPU-core
  3. *
  4. * Copyright (c) 2001 Marius Gröger <mag@sysgo.de>
  5. * Copyright (c) 2002 Alex Züpke <azu@sysgo.de>
  6. *
  7. * See file CREDITS for list of people who contributed to this
  8. * project.
  9. *
  10. * This program is free software; you can redistribute it and/or
  11. * modify it under the terms of the GNU General Public License as
  12. * published by the Free Software Foundation; either version 2 of
  13. * the License, or (at your option) any later version.
  14. *
  15. * This program is distributed in the hope that it will be useful,
  16. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  17. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  18. * GNU General Public License for more details.
  19. *
  20. * You should have received a copy of the GNU General Public License
  21. * along with this program; if not, write to the Free Software
  22. * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  23. * MA 02111-1307 USA
  24. */
  25. #include <asm-offsets.h>
  26. #include <config.h>
  27. #include <version.h>
  28. #include <asm/hardware.h>
  29. /*
  30. *************************************************************************
  31. *
  32. * Jump vector table as in table 3.1 in [1]
  33. *
  34. *************************************************************************
  35. */
  36. .globl _start
  37. _start: b reset
  38. ldr pc, _undefined_instruction
  39. ldr pc, _software_interrupt
  40. ldr pc, _prefetch_abort
  41. ldr pc, _data_abort
  42. #ifdef CONFIG_LPC2292
  43. .word 0xB4405F76 /* 2's complement of the checksum of the vectors */
  44. #else
  45. ldr pc, _not_used
  46. #endif
  47. ldr pc, _irq
  48. ldr pc, _fiq
  49. _undefined_instruction: .word undefined_instruction
  50. _software_interrupt: .word software_interrupt
  51. _prefetch_abort: .word prefetch_abort
  52. _data_abort: .word data_abort
  53. _not_used: .word not_used
  54. _irq: .word irq
  55. _fiq: .word fiq
  56. .balignl 16,0xdeadbeef
  57. /*
  58. *************************************************************************
  59. *
  60. * Startup Code (reset vector)
  61. *
  62. * do important init only if we don't start from RAM!
  63. * relocate armboot to ram
  64. * setup stack
  65. * jump to second stage
  66. *
  67. *************************************************************************
  68. */
  69. .globl _TEXT_BASE
  70. _TEXT_BASE:
  71. .word CONFIG_SYS_TEXT_BASE
  72. /*
  73. * These are defined in the board-specific linker script.
  74. * Subtracting _start from them lets the linker put their
  75. * relative position in the executable instead of leaving
  76. * them null.
  77. */
  78. .globl _bss_start_ofs
  79. _bss_start_ofs:
  80. .word __bss_start - _start
  81. .globl _bss_end_ofs
  82. _bss_end_ofs:
  83. .word __bss_end__ - _start
  84. .globl _end_ofs
  85. _end_ofs:
  86. .word _end - _start
  87. #ifdef CONFIG_USE_IRQ
  88. /* IRQ stack memory (calculated at run-time) */
  89. .globl IRQ_STACK_START
  90. IRQ_STACK_START:
  91. .word 0x0badc0de
  92. /* IRQ stack memory (calculated at run-time) */
  93. .globl FIQ_STACK_START
  94. FIQ_STACK_START:
  95. .word 0x0badc0de
  96. #endif
  97. /* IRQ stack memory (calculated at run-time) + 8 bytes */
  98. .globl IRQ_STACK_START_IN
  99. IRQ_STACK_START_IN:
  100. .word 0x0badc0de
  101. /*
  102. * the actual reset code
  103. */
  104. reset:
  105. /*
  106. * set the cpu to SVC32 mode
  107. */
  108. mrs r0,cpsr
  109. bic r0,r0,#0x1f
  110. orr r0,r0,#0xd3
  111. msr cpsr,r0
  112. /*
  113. * we do sys-critical inits only at reboot,
  114. * not when booting from ram!
  115. */
  116. #ifndef CONFIG_SKIP_LOWLEVEL_INIT
  117. bl cpu_init_crit
  118. #endif
  119. #ifdef CONFIG_LPC2292
  120. bl lowlevel_init
  121. #endif
  122. /* Set stackpointer in internal RAM to call board_init_f */
  123. call_board_init_f:
  124. ldr sp, =(CONFIG_SYS_INIT_SP_ADDR)
  125. bic sp, sp, #7 /* 8-byte alignment for ABI compliance */
  126. ldr r0,=0x00000000
  127. bl board_init_f
  128. /*------------------------------------------------------------------------------*/
  129. /*
  130. * void relocate_code (addr_sp, gd, addr_moni)
  131. *
  132. * This "function" does not return, instead it continues in RAM
  133. * after relocating the monitor code.
  134. *
  135. */
  136. .globl relocate_code
  137. relocate_code:
  138. mov r4, r0 /* save addr_sp */
  139. mov r5, r1 /* save addr of gd */
  140. mov r6, r2 /* save addr of destination */
  141. /* Set up the stack */
  142. stack_setup:
  143. mov sp, r4
  144. adr r0, _start
  145. cmp r0, r6
  146. beq clear_bss /* skip relocation */
  147. mov r1, r6 /* r1 <- scratch for copy_loop */
  148. ldr r3, _bss_start_ofs
  149. add r2, r0, r3 /* r2 <- source end address */
  150. copy_loop:
  151. ldmia r0!, {r9-r10} /* copy from source address [r0] */
  152. stmia r1!, {r9-r10} /* copy to target address [r1] */
  153. cmp r0, r2 /* until source end address [r2] */
  154. blo copy_loop
  155. #ifndef CONFIG_SPL_BUILD
  156. /*
  157. * fix .rel.dyn relocations
  158. */
  159. ldr r0, _TEXT_BASE /* r0 <- Text base */
  160. sub r9, r6, r0 /* r9 <- relocation offset */
  161. ldr r10, _dynsym_start_ofs /* r10 <- sym table ofs */
  162. add r10, r10, r0 /* r10 <- sym table in FLASH */
  163. ldr r2, _rel_dyn_start_ofs /* r2 <- rel dyn start ofs */
  164. add r2, r2, r0 /* r2 <- rel dyn start in FLASH */
  165. ldr r3, _rel_dyn_end_ofs /* r3 <- rel dyn end ofs */
  166. add r3, r3, r0 /* r3 <- rel dyn end in FLASH */
  167. fixloop:
  168. ldr r0, [r2] /* r0 <- location to fix up, IN FLASH! */
  169. add r0, r0, r9 /* r0 <- location to fix up in RAM */
  170. ldr r1, [r2, #4]
  171. and r7, r1, #0xff
  172. cmp r7, #23 /* relative fixup? */
  173. beq fixrel
  174. cmp r7, #2 /* absolute fixup? */
  175. beq fixabs
  176. /* ignore unknown type of fixup */
  177. b fixnext
  178. fixabs:
  179. /* absolute fix: set location to (offset) symbol value */
  180. mov r1, r1, LSR #4 /* r1 <- symbol index in .dynsym */
  181. add r1, r10, r1 /* r1 <- address of symbol in table */
  182. ldr r1, [r1, #4] /* r1 <- symbol value */
  183. add r1, r1, r9 /* r1 <- relocated sym addr */
  184. b fixnext
  185. fixrel:
  186. /* relative fix: increase location by offset */
  187. ldr r1, [r0]
  188. add r1, r1, r9
  189. fixnext:
  190. str r1, [r0]
  191. add r2, r2, #8 /* each rel.dyn entry is 8 bytes */
  192. cmp r2, r3
  193. blo fixloop
  194. #endif
  195. clear_bss:
  196. #ifndef CONFIG_SPL_BUILD
  197. ldr r0, _bss_start_ofs
  198. ldr r1, _bss_end_ofs
  199. mov r4, r6 /* reloc addr */
  200. add r0, r0, r4
  201. add r1, r1, r4
  202. mov r2, #0x00000000 /* clear */
  203. clbss_l:str r2, [r0] /* clear loop... */
  204. add r0, r0, #4
  205. cmp r0, r1
  206. bne clbss_l
  207. bl coloured_LED_init
  208. bl red_LED_on
  209. #endif
  210. /*
  211. * We are done. Do not return, instead branch to second part of board
  212. * initialization, now running from RAM.
  213. */
  214. ldr r0, _board_init_r_ofs
  215. adr r1, _start
  216. add lr, r0, r1
  217. add lr, lr, r9
  218. /* setup parameters for board_init_r */
  219. mov r0, r5 /* gd_t */
  220. mov r1, r6 /* dest_addr */
  221. /* jump to it ... */
  222. mov pc, lr
  223. _board_init_r_ofs:
  224. .word board_init_r - _start
  225. _rel_dyn_start_ofs:
  226. .word __rel_dyn_start - _start
  227. _rel_dyn_end_ofs:
  228. .word __rel_dyn_end - _start
  229. _dynsym_start_ofs:
  230. .word __dynsym_start - _start
  231. /*
  232. *************************************************************************
  233. *
  234. * CPU_init_critical registers
  235. *
  236. * setup important registers
  237. * setup memory timing
  238. *
  239. *************************************************************************
  240. */
  241. #if defined(CONFIG_IMPA7) || defined(CONFIG_EP7312) || defined(CONFIG_ARMADILLO)
  242. /* Interrupt-Controller base addresses */
  243. INTMR1: .word 0x80000280 @ 32 bit size
  244. INTMR2: .word 0x80001280 @ 16 bit size
  245. INTMR3: .word 0x80002280 @ 8 bit size
  246. /* SYSCONs */
  247. SYSCON1: .word 0x80000100
  248. SYSCON2: .word 0x80001100
  249. SYSCON3: .word 0x80002200
  250. #define CLKCTL 0x6 /* mask */
  251. #define CLKCTL_18 0x0 /* 18.432 MHz */
  252. #define CLKCTL_36 0x2 /* 36.864 MHz */
  253. #define CLKCTL_49 0x4 /* 49.152 MHz */
  254. #define CLKCTL_73 0x6 /* 73.728 MHz */
  255. #elif defined(CONFIG_LPC2292)
  256. PLLCFG_ADR: .word PLLCFG
  257. PLLFEED_ADR: .word PLLFEED
  258. PLLCON_ADR: .word PLLCON
  259. PLLSTAT_ADR: .word PLLSTAT
  260. VPBDIV_ADR: .word VPBDIV
  261. MEMMAP_ADR: .word MEMMAP
  262. #endif
  263. cpu_init_crit:
  264. #if defined(CONFIG_IMPA7) || defined(CONFIG_EP7312) || defined(CONFIG_ARMADILLO)
  265. /*
  266. * mask all IRQs by clearing all bits in the INTMRs
  267. */
  268. mov r1, #0x00
  269. ldr r0, INTMR1
  270. str r1, [r0]
  271. ldr r0, INTMR2
  272. str r1, [r0]
  273. ldr r0, INTMR3
  274. str r1, [r0]
  275. /*
  276. * flush v4 I/D caches
  277. */
  278. mov r0, #0
  279. mcr p15, 0, r0, c7, c7, 0 /* flush v3/v4 cache */
  280. mcr p15, 0, r0, c8, c7, 0 /* flush v4 TLB */
  281. /*
  282. * disable MMU stuff and caches
  283. */
  284. mrc p15,0,r0,c1,c0
  285. bic r0, r0, #0x00002300 @ clear bits 13, 9:8 (--V- --RS)
  286. bic r0, r0, #0x0000008f @ clear bits 7, 3:0 (B--- WCAM)
  287. orr r0, r0, #0x00000002 @ set bit 2 (A) Align
  288. mcr p15,0,r0,c1,c0
  289. #elif defined(CONFIG_NETARM)
  290. /*
  291. * prior to software reset : need to set pin PORTC4 to be *HRESET
  292. */
  293. ldr r0, =NETARM_GEN_MODULE_BASE
  294. ldr r1, =(NETARM_GEN_PORT_MODE(0x10) | \
  295. NETARM_GEN_PORT_DIR(0x10))
  296. str r1, [r0, #+NETARM_GEN_PORTC]
  297. /*
  298. * software reset : see HW Ref. Guide 8.2.4 : Software Service register
  299. * for an explanation of this process
  300. */
  301. ldr r0, =NETARM_GEN_MODULE_BASE
  302. ldr r1, =NETARM_GEN_SW_SVC_RESETA
  303. str r1, [r0, #+NETARM_GEN_SOFTWARE_SERVICE]
  304. ldr r1, =NETARM_GEN_SW_SVC_RESETB
  305. str r1, [r0, #+NETARM_GEN_SOFTWARE_SERVICE]
  306. ldr r1, =NETARM_GEN_SW_SVC_RESETA
  307. str r1, [r0, #+NETARM_GEN_SOFTWARE_SERVICE]
  308. ldr r1, =NETARM_GEN_SW_SVC_RESETB
  309. str r1, [r0, #+NETARM_GEN_SOFTWARE_SERVICE]
  310. /*
  311. * setup PLL and System Config
  312. */
  313. ldr r0, =NETARM_GEN_MODULE_BASE
  314. ldr r1, =( NETARM_GEN_SYS_CFG_LENDIAN | \
  315. NETARM_GEN_SYS_CFG_BUSFULL | \
  316. NETARM_GEN_SYS_CFG_USER_EN | \
  317. NETARM_GEN_SYS_CFG_ALIGN_ABORT | \
  318. NETARM_GEN_SYS_CFG_BUSARB_INT | \
  319. NETARM_GEN_SYS_CFG_BUSMON_EN )
  320. str r1, [r0, #+NETARM_GEN_SYSTEM_CONTROL]
  321. #ifndef CONFIG_NETARM_PLL_BYPASS
  322. ldr r1, =( NETARM_GEN_PLL_CTL_PLLCNT(NETARM_PLL_COUNT_VAL) | \
  323. NETARM_GEN_PLL_CTL_POLTST_DEF | \
  324. NETARM_GEN_PLL_CTL_INDIV(1) | \
  325. NETARM_GEN_PLL_CTL_ICP_DEF | \
  326. NETARM_GEN_PLL_CTL_OUTDIV(2) )
  327. str r1, [r0, #+NETARM_GEN_PLL_CONTROL]
  328. #endif
  329. /*
  330. * mask all IRQs by clearing all bits in the INTMRs
  331. */
  332. mov r1, #0
  333. ldr r0, =NETARM_GEN_MODULE_BASE
  334. str r1, [r0, #+NETARM_GEN_INTR_ENABLE]
  335. #elif defined(CONFIG_S3C4510B)
  336. /*
  337. * Mask off all IRQ sources
  338. */
  339. ldr r1, =REG_INTMASK
  340. ldr r0, =0x3FFFFF
  341. str r0, [r1]
  342. /*
  343. * Disable Cache
  344. */
  345. ldr r0, =REG_SYSCFG
  346. ldr r1, =0x83ffffa0 /* cache-disabled */
  347. str r1, [r0]
  348. #elif defined(CONFIG_INTEGRATOR) && defined(CONFIG_ARCH_INTEGRATOR)
  349. /* No specific initialisation for IntegratorAP/CM720T as yet */
  350. #elif defined(CONFIG_LPC2292)
  351. /* Set-up PLL */
  352. mov r3, #0xAA
  353. mov r4, #0x55
  354. /* First disconnect and disable the PLL */
  355. ldr r0, PLLCON_ADR
  356. mov r1, #0x00
  357. str r1, [r0]
  358. ldr r0, PLLFEED_ADR /* start feed sequence */
  359. str r3, [r0]
  360. str r4, [r0] /* feed sequence done */
  361. /* Set new M and P values */
  362. ldr r0, PLLCFG_ADR
  363. mov r1, #0x23 /* M=4 and P=2 */
  364. str r1, [r0]
  365. ldr r0, PLLFEED_ADR /* start feed sequence */
  366. str r3, [r0]
  367. str r4, [r0] /* feed sequence done */
  368. /* Then enable the PLL */
  369. ldr r0, PLLCON_ADR
  370. mov r1, #0x01 /* PLL enable bit */
  371. str r1, [r0]
  372. ldr r0, PLLFEED_ADR /* start feed sequence */
  373. str r3, [r0]
  374. str r4, [r0] /* feed sequence done */
  375. /* Wait for the lock */
  376. ldr r0, PLLSTAT_ADR
  377. mov r1, #0x400 /* lock bit */
  378. lock_loop:
  379. ldr r2, [r0]
  380. and r2, r1, r2
  381. cmp r2, #0
  382. beq lock_loop
  383. /* And finally connect the PLL */
  384. ldr r0, PLLCON_ADR
  385. mov r1, #0x03 /* PLL enable bit and connect bit */
  386. str r1, [r0]
  387. ldr r0, PLLFEED_ADR /* start feed sequence */
  388. str r3, [r0]
  389. str r4, [r0] /* feed sequence done */
  390. /* Set-up VPBDIV register */
  391. ldr r0, VPBDIV_ADR
  392. mov r1, #0x01 /* VPB clock is same as process clock */
  393. str r1, [r0]
  394. #else
  395. #error No cpu_init_crit() defined for current CPU type
  396. #endif
  397. #ifdef CONFIG_ARM7_REVD
  398. /* set clock speed */
  399. /* !!! we run @ 36 MHz due to a hardware flaw in Rev. D processors */
  400. /* !!! not doing DRAM refresh properly! */
  401. ldr r0, SYSCON3
  402. ldr r1, [r0]
  403. bic r1, r1, #CLKCTL
  404. orr r1, r1, #CLKCTL_36
  405. str r1, [r0]
  406. #endif
  407. #ifndef CONFIG_LPC2292
  408. mov ip, lr
  409. /*
  410. * before relocating, we have to setup RAM timing
  411. * because memory timing is board-dependent, you will
  412. * find a lowlevel_init.S in your board directory.
  413. */
  414. bl lowlevel_init
  415. mov lr, ip
  416. #endif
  417. mov pc, lr
  418. /*
  419. *************************************************************************
  420. *
  421. * Interrupt handling
  422. *
  423. *************************************************************************
  424. */
  425. @
  426. @ IRQ stack frame.
  427. @
  428. #define S_FRAME_SIZE 72
  429. #define S_OLD_R0 68
  430. #define S_PSR 64
  431. #define S_PC 60
  432. #define S_LR 56
  433. #define S_SP 52
  434. #define S_IP 48
  435. #define S_FP 44
  436. #define S_R10 40
  437. #define S_R9 36
  438. #define S_R8 32
  439. #define S_R7 28
  440. #define S_R6 24
  441. #define S_R5 20
  442. #define S_R4 16
  443. #define S_R3 12
  444. #define S_R2 8
  445. #define S_R1 4
  446. #define S_R0 0
  447. #define MODE_SVC 0x13
  448. #define I_BIT 0x80
  449. /*
  450. * use bad_save_user_regs for abort/prefetch/undef/swi ...
  451. * use irq_save_user_regs / irq_restore_user_regs for IRQ/FIQ handling
  452. */
  453. .macro bad_save_user_regs
  454. sub sp, sp, #S_FRAME_SIZE
  455. stmia sp, {r0 - r12} @ Calling r0-r12
  456. add r8, sp, #S_PC
  457. ldr r2, IRQ_STACK_START_IN
  458. ldmia r2, {r2 - r4} @ get pc, cpsr, old_r0
  459. add r0, sp, #S_FRAME_SIZE @ restore sp_SVC
  460. add r5, sp, #S_SP
  461. mov r1, lr
  462. stmia r5, {r0 - r4} @ save sp_SVC, lr_SVC, pc, cpsr, old_r
  463. mov r0, sp
  464. .endm
  465. .macro irq_save_user_regs
  466. sub sp, sp, #S_FRAME_SIZE
  467. stmia sp, {r0 - r12} @ Calling r0-r12
  468. add r8, sp, #S_PC
  469. stmdb r8, {sp, lr}^ @ Calling SP, LR
  470. str lr, [r8, #0] @ Save calling PC
  471. mrs r6, spsr
  472. str r6, [r8, #4] @ Save CPSR
  473. str r0, [r8, #8] @ Save OLD_R0
  474. mov r0, sp
  475. .endm
  476. .macro irq_restore_user_regs
  477. ldmia sp, {r0 - lr}^ @ Calling r0 - lr
  478. mov r0, r0
  479. ldr lr, [sp, #S_PC] @ Get PC
  480. add sp, sp, #S_FRAME_SIZE
  481. subs pc, lr, #4 @ return & move spsr_svc into cpsr
  482. .endm
  483. .macro get_bad_stack
  484. ldr r13, IRQ_STACK_START_IN @ setup our mode stack
  485. str lr, [r13] @ save caller lr / spsr
  486. mrs lr, spsr
  487. str lr, [r13, #4]
  488. mov r13, #MODE_SVC @ prepare SVC-Mode
  489. msr spsr_c, r13
  490. mov lr, pc
  491. movs pc, lr
  492. .endm
  493. .macro get_irq_stack @ setup IRQ stack
  494. ldr sp, IRQ_STACK_START
  495. .endm
  496. .macro get_fiq_stack @ setup FIQ stack
  497. ldr sp, FIQ_STACK_START
  498. .endm
  499. /*
  500. * exception handlers
  501. */
  502. .align 5
  503. undefined_instruction:
  504. get_bad_stack
  505. bad_save_user_regs
  506. bl do_undefined_instruction
  507. .align 5
  508. software_interrupt:
  509. get_bad_stack
  510. bad_save_user_regs
  511. bl do_software_interrupt
  512. .align 5
  513. prefetch_abort:
  514. get_bad_stack
  515. bad_save_user_regs
  516. bl do_prefetch_abort
  517. .align 5
  518. data_abort:
  519. get_bad_stack
  520. bad_save_user_regs
  521. bl do_data_abort
  522. .align 5
  523. not_used:
  524. get_bad_stack
  525. bad_save_user_regs
  526. bl do_not_used
  527. #ifdef CONFIG_USE_IRQ
  528. .align 5
  529. irq:
  530. get_irq_stack
  531. irq_save_user_regs
  532. bl do_irq
  533. irq_restore_user_regs
  534. .align 5
  535. fiq:
  536. get_fiq_stack
  537. /* someone ought to write a more effiction fiq_save_user_regs */
  538. irq_save_user_regs
  539. bl do_fiq
  540. irq_restore_user_regs
  541. #else
  542. .align 5
  543. irq:
  544. get_bad_stack
  545. bad_save_user_regs
  546. bl do_irq
  547. .align 5
  548. fiq:
  549. get_bad_stack
  550. bad_save_user_regs
  551. bl do_fiq
  552. #endif
  553. #if defined(CONFIG_IMPA7) || defined(CONFIG_EP7312) || defined(CONFIG_ARMADILLO)
  554. .align 5
  555. .globl reset_cpu
  556. reset_cpu:
  557. mov ip, #0
  558. mcr p15, 0, ip, c7, c7, 0 @ invalidate cache
  559. mcr p15, 0, ip, c8, c7, 0 @ flush TLB (v4)
  560. mrc p15, 0, ip, c1, c0, 0 @ get ctrl register
  561. bic ip, ip, #0x000f @ ............wcam
  562. bic ip, ip, #0x2100 @ ..v....s........
  563. mcr p15, 0, ip, c1, c0, 0 @ ctrl register
  564. mov pc, r0
  565. #elif defined(CONFIG_NETARM)
  566. .align 5
  567. .globl reset_cpu
  568. reset_cpu:
  569. ldr r1, =NETARM_MEM_MODULE_BASE
  570. ldr r0, [r1, #+NETARM_MEM_CS0_BASE_ADDR]
  571. ldr r1, =0xFFFFF000
  572. and r0, r1, r0
  573. ldr r1, =(relocate-CONFIG_SYS_TEXT_BASE)
  574. add r0, r1, r0
  575. ldr r4, =NETARM_GEN_MODULE_BASE
  576. ldr r1, =NETARM_GEN_SW_SVC_RESETA
  577. str r1, [r4, #+NETARM_GEN_SOFTWARE_SERVICE]
  578. ldr r1, =NETARM_GEN_SW_SVC_RESETB
  579. str r1, [r4, #+NETARM_GEN_SOFTWARE_SERVICE]
  580. ldr r1, =NETARM_GEN_SW_SVC_RESETA
  581. str r1, [r4, #+NETARM_GEN_SOFTWARE_SERVICE]
  582. ldr r1, =NETARM_GEN_SW_SVC_RESETB
  583. str r1, [r4, #+NETARM_GEN_SOFTWARE_SERVICE]
  584. mov pc, r0
  585. #elif defined(CONFIG_S3C4510B)
  586. /* Nothing done here as reseting the CPU is board specific, depending
  587. * on external peripherals such as watchdog timers, etc. */
  588. #elif defined(CONFIG_INTEGRATOR) && defined(CONFIG_ARCH_INTEGRATOR)
  589. /* No specific reset actions for IntegratorAP/CM720T as yet */
  590. #elif defined(CONFIG_LPC2292)
  591. .align 5
  592. .globl reset_cpu
  593. reset_cpu:
  594. mov pc, r0
  595. #else
  596. #error No reset_cpu() defined for current CPU type
  597. #endif