mv_gen_reg.h 101 KB

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  1. /* mv_gen_reg.h - Internal registers definition file */
  2. /* Copyright - Galileo technology. */
  3. /*******************************************************************************
  4. * Copyright 2002, GALILEO TECHNOLOGY, LTD. *
  5. * THIS CODE CONTAINS CONFIDENTIAL INFORMATION OF MARVELL. *
  6. * NO RIGHTS ARE GRANTED HEREIN UNDER ANY PATENT, MASK WORK RIGHT OR COPYRIGHT *
  7. * OF MARVELL OR ANY THIRD PARTY. MARVELL RESERVES THE RIGHT AT ITS SOLE *
  8. * DISCRETION TO REQUEST THAT THIS CODE BE IMMEDIATELY RETURNED TO MARVELL. *
  9. * THIS CODE IS PROVIDED "AS IS". MARVELL MAKES NO WARRANTIES, EXPRESSED, *
  10. * IMPLIED OR OTHERWISE, REGARDING ITS ACCURACY, COMPLETENESS OR PERFORMANCE. *
  11. * *
  12. * MARVELL COMPRISES MARVELL TECHNOLOGY GROUP LTD. (MTGL) AND ITS SUBSIDIARIES, *
  13. * MARVELL INTERNATIONAL LTD. (MIL), MARVELL TECHNOLOGY, INC. (MTI), MARVELL *
  14. * SEMICONDUCTOR, INC. (MSI), MARVELL ASIA PTE LTD. (MAPL), MARVELL JAPAN K.K. *
  15. * (MJKK), GALILEO TECHNOLOGY LTD. (GTL) AND GALILEO TECHNOLOGY, INC. (GTI). *
  16. ********************************************************************************
  17. * mv_gen_reg.h - Marvell 64360 and 64460 Internal registers definition file.
  18. *
  19. * DESCRIPTION:
  20. * None.
  21. *
  22. * DEPENDENCIES:
  23. * None.
  24. *
  25. *******************************************************************************/
  26. #ifndef __INCmv_gen_regh
  27. #define __INCmv_gen_regh
  28. /* Supported by the Atlantis */
  29. #define INCLUDE_PCI_1
  30. #define INCLUDE_PCI_0_ARBITER
  31. #define INCLUDE_PCI_1_ARBITER
  32. #define INCLUDE_SNOOP_SUPPORT
  33. #define INCLUDE_P2P
  34. #define INCLUDE_ETH_PORT_2
  35. #define INCLUDE_CPU_MAPPING
  36. #define INCLUDE_MPSC
  37. /* Not supported features */
  38. #undef INCLUDE_CNTMR_4_7
  39. #undef INCLUDE_DMA_4_7
  40. /****************************************/
  41. /* Processor Address Space */
  42. /****************************************/
  43. /* DDR SDRAM BAR and size registers */
  44. /* Sdram's BAR'S */
  45. #define SCS_0_LOW_DECODE_ADDRESS 0x008
  46. #define SCS_0_HIGH_DECODE_ADDRESS 0x010
  47. #define SCS_1_LOW_DECODE_ADDRESS 0x208
  48. #define SCS_1_HIGH_DECODE_ADDRESS 0x210
  49. #define SCS_2_LOW_DECODE_ADDRESS 0x018
  50. #define SCS_2_HIGH_DECODE_ADDRESS 0x020
  51. #define SCS_3_LOW_DECODE_ADDRESS 0x218
  52. #define SCS_3_HIGH_DECODE_ADDRESS 0x220
  53. /* Make it fit the MV64360 and MV64460 Lowlevel driver */
  54. #define CS_0_BASE_ADDR SCS_0_LOW_DECODE_ADDRESS
  55. #define CS_0_SIZE SCS_0_HIGH_DECODE_ADDRESS
  56. #define CS_1_BASE_ADDR SCS_1_LOW_DECODE_ADDRESS
  57. #define CS_1_SIZE SCS_1_HIGH_DECODE_ADDRESS
  58. #define CS_2_BASE_ADDR SCS_2_LOW_DECODE_ADDRESS
  59. #define CS_2_SIZE SCS_2_HIGH_DECODE_ADDRESS
  60. #define CS_3_BASE_ADDR SCS_3_LOW_DECODE_ADDRESS
  61. #define CS_3_SIZE SCS_3_HIGH_DECODE_ADDRESS
  62. /* Devices BAR'S */
  63. #define CS_0_LOW_DECODE_ADDRESS 0x028
  64. #define CS_0_HIGH_DECODE_ADDRESS 0x030
  65. #define CS_1_LOW_DECODE_ADDRESS 0x228
  66. #define CS_1_HIGH_DECODE_ADDRESS 0x230
  67. #define CS_2_LOW_DECODE_ADDRESS 0x248
  68. #define CS_2_HIGH_DECODE_ADDRESS 0x250
  69. #define CS_3_LOW_DECODE_ADDRESS 0x038
  70. #define CS_3_HIGH_DECODE_ADDRESS 0x040
  71. #define BOOTCS_LOW_DECODE_ADDRESS 0x238
  72. #define BOOTCS_HIGH_DECODE_ADDRESS 0x240
  73. /* Make it fit the MV64360 and MV64460 Lowlevel driver */
  74. /* Devices BAR and size registers */
  75. #define DEV_CS0_BASE_ADDR CS_0_LOW_DECODE_ADDRESS
  76. #define DEV_CS0_SIZE CS_0_HIGH_DECODE_ADDRESS
  77. #define DEV_CS1_BASE_ADDR CS_1_LOW_DECODE_ADDRESS
  78. #define DEV_CS1_SIZE CS_1_HIGH_DECODE_ADDRESS
  79. #define DEV_CS2_BASE_ADDR CS_2_LOW_DECODE_ADDRESS
  80. #define DEV_CS2_SIZE CS_2_HIGH_DECODE_ADDRESS
  81. #define DEV_CS3_BASE_ADDR CS_3_LOW_DECODE_ADDRESS
  82. #define DEV_CS3_SIZE CS_3_HIGH_DECODE_ADDRESS
  83. #define BOOTCS_BASE_ADDR BOOTCS_LOW_DECODE_ADDRESS
  84. #define BOOTCS_SIZE BOOTCS_HIGH_DECODE_ADDRESS
  85. /* PCI 0 BAR and size registers old names of evb64260*/
  86. #define PCI_0I_O_LOW_DECODE_ADDRESS 0x048
  87. #define PCI_0I_O_HIGH_DECODE_ADDRESS 0x050
  88. #define PCI_0MEMORY0_LOW_DECODE_ADDRESS 0x058
  89. #define PCI_0MEMORY0_HIGH_DECODE_ADDRESS 0x060
  90. #define PCI_0MEMORY1_LOW_DECODE_ADDRESS 0x080
  91. #define PCI_0MEMORY1_HIGH_DECODE_ADDRESS 0x088
  92. #define PCI_0MEMORY2_LOW_DECODE_ADDRESS 0x258
  93. #define PCI_0MEMORY2_HIGH_DECODE_ADDRESS 0x260
  94. #define PCI_0MEMORY3_LOW_DECODE_ADDRESS 0x280
  95. #define PCI_0MEMORY3_HIGH_DECODE_ADDRESS 0x288
  96. /* Make it fit the MV64360 and MV64460 Lowlevel driver */
  97. #define PCI_0_IO_BASE_ADDR 0x048
  98. #define PCI_0_IO_SIZE 0x050
  99. #define PCI_0_MEMORY0_BASE_ADDR 0x058
  100. #define PCI_0_MEMORY0_SIZE 0x060
  101. #define PCI_0_MEMORY1_BASE_ADDR 0x080
  102. #define PCI_0_MEMORY1_SIZE 0x088
  103. #define PCI_0_MEMORY2_BASE_ADDR 0x258
  104. #define PCI_0_MEMORY2_SIZE 0x260
  105. #define PCI_0_MEMORY3_BASE_ADDR 0x280
  106. #define PCI_0_MEMORY3_SIZE 0x288
  107. /* PCI 1 BAR and size registers old names of evb64260*/
  108. #define PCI_1I_O_LOW_DECODE_ADDRESS 0x090
  109. #define PCI_1I_O_HIGH_DECODE_ADDRESS 0x098
  110. #define PCI_1MEMORY0_LOW_DECODE_ADDRESS 0x0a0
  111. #define PCI_1MEMORY0_HIGH_DECODE_ADDRESS 0x0a8
  112. #define PCI_1MEMORY1_LOW_DECODE_ADDRESS 0x0b0
  113. #define PCI_1MEMORY1_HIGH_DECODE_ADDRESS 0x0b8
  114. #define PCI_1MEMORY2_LOW_DECODE_ADDRESS 0x2a0
  115. #define PCI_1MEMORY2_HIGH_DECODE_ADDRESS 0x2a8
  116. #define PCI_1MEMORY3_LOW_DECODE_ADDRESS 0x2b0
  117. #define PCI_1MEMORY3_HIGH_DECODE_ADDRESS 0x2b8
  118. /* Make it fit the MV64360 and MV64460 Lowlevel driver */
  119. #define PCI_1_IO_BASE_ADDR 0x090
  120. #define PCI_1_IO_SIZE 0x098
  121. #define PCI_1_MEMORY0_BASE_ADDR 0x0a0
  122. #define PCI_1_MEMORY0_SIZE 0x0a8
  123. #define PCI_1_MEMORY1_BASE_ADDR 0x0b0
  124. #define PCI_1_MEMORY1_SIZE 0x0b8
  125. #define PCI_1_MEMORY2_BASE_ADDR 0x2a0
  126. #define PCI_1_MEMORY2_SIZE 0x2a8
  127. #define PCI_1_MEMORY3_BASE_ADDR 0x2b0
  128. #define PCI_1_MEMORY3_SIZE 0x2b8
  129. /* internal registers space base address */
  130. #define INTERNAL_SPACE_DECODE 0x068
  131. #define INTERNAL_SPACE_BASE_ADDR INTERNAL_SPACE_DECODE
  132. /* SRAM base address */
  133. #define INTEGRATED_SRAM_BASE_ADDR 0x268
  134. /* Enables the CS , DEV_CS , PCI 0 and PCI 1
  135. windows above */
  136. #define BASE_ADDR_ENABLE 0x278
  137. #define CPU_0_LOW_DECODE_ADDRESS 0x290
  138. #define CPU_0_HIGH_DECODE_ADDRESS 0x298
  139. #define CPU_1_LOW_DECODE_ADDRESS 0x2c0
  140. #define CPU_1_HIGH_DECODE_ADDRESS 0x2c8
  141. /****************************************/
  142. /* PCI remap registers */
  143. /****************************************/
  144. /*****************************************************************************************/
  145. /* PCI 0 */
  146. /* old fashion evb 64260 */
  147. #define PCI_0I_O_ADDRESS_REMAP 0x0f0
  148. #define PCI_0MEMORY0_ADDRESS_REMAP 0x0f8
  149. #define PCI_0MEMORY0_HIGH_ADDRESS_REMAP 0x320
  150. #define PCI_0MEMORY1_ADDRESS_REMAP 0x100
  151. #define PCI_0MEMORY1_HIGH_ADDRESS_REMAP 0x328
  152. #define PCI_0MEMORY2_ADDRESS_REMAP 0x2f8
  153. #define PCI_0MEMORY2_HIGH_ADDRESS_REMAP 0x330
  154. #define PCI_0MEMORY3_ADDRESS_REMAP 0x300
  155. #define PCI_0MEMORY3_HIGH_ADDRESS_REMAP 0x338
  156. #define PCI_0_IO_ADDR_REMAP PCI_0I_O_ADDRESS_REMAP
  157. #define PCI_0_MEMORY0_LOW_ADDR_REMAP PCI_0MEMORY0_ADDRESS_REMAP
  158. #define PCI_0_MEMORY0_HIGH_ADDR_REMAP PCI_0MEMORY0_HIGH_ADDRESS_REMAP
  159. #define PCI_0_MEMORY1_LOW_ADDR_REMAP PCI_0MEMORY1_ADDRESS_REMAP
  160. #define PCI_0_MEMORY1_HIGH_ADDR_REMAP PCI_0MEMORY1_HIGH_ADDRESS_REMAP
  161. #define PCI_0_MEMORY2_LOW_ADDR_REMAP PCI_0MEMORY2_ADDRESS_REMAP
  162. #define PCI_0_MEMORY2_HIGH_ADDR_REMAP PCI_0MEMORY2_HIGH_ADDRESS_REMAP
  163. #define PCI_0_MEMORY3_LOW_ADDR_REMAP PCI_0MEMORY3_ADDRESS_REMAP
  164. #define PCI_0_MEMORY3_HIGH_ADDR_REMAP PCI_0MEMORY3_HIGH_ADDRESS_REMAP
  165. /* PCI 1 */
  166. /* old fashion evb 64260 */
  167. #define PCI_1I_O_ADDRESS_REMAP 0x108
  168. #define PCI_1MEMORY0_ADDRESS_REMAP 0x110
  169. #define PCI_1MEMORY0_HIGH_ADDRESS_REMAP 0x340
  170. #define PCI_1MEMORY1_ADDRESS_REMAP 0x118
  171. #define PCI_1MEMORY1_HIGH_ADDRESS_REMAP 0x348
  172. #define PCI_1MEMORY2_ADDRESS_REMAP 0x310
  173. #define PCI_1MEMORY2_HIGH_ADDRESS_REMAP 0x350
  174. #define PCI_1MEMORY3_ADDRESS_REMAP 0x318
  175. #define PCI_1MEMORY3_HIGH_ADDRESS_REMAP 0x358
  176. #define PCI_1_IO_ADDR_REMAP PCI_1I_O_ADDRESS_REMAP
  177. #define PCI_1_MEMORY0_LOW_ADDR_REMAP PCI_1MEMORY0_ADDRESS_REMAP
  178. #define PCI_1_MEMORY0_HIGH_ADDR_REMAP PCI_1MEMORY0_HIGH_ADDRESS_REMAP
  179. #define PCI_1_MEMORY1_LOW_ADDR_REMAP PCI_1MEMORY1_ADDRESS_REMAP
  180. #define PCI_1_MEMORY1_HIGH_ADDR_REMAP PCI_1MEMORY1_HIGH_ADDRESS_REMAP
  181. #define PCI_1_MEMORY2_LOW_ADDR_REMAP PCI_1MEMORY2_ADDRESS_REMAP
  182. #define PCI_1_MEMORY2_HIGH_ADDR_REMAP PCI_1MEMORY2_HIGH_ADDRESS_REMAP
  183. #define PCI_1_MEMORY3_LOW_ADDR_REMAP PCI_1MEMORY3_ADDRESS_REMAP
  184. #define PCI_1_MEMORY3_HIGH_ADDR_REMAP PCI_1MEMORY3_HIGH_ADDRESS_REMAP
  185. /* old fashion evb 64260 */
  186. #define CPU_PCI_0_HEADERS_RETARGET_CONTROL 0x3b0
  187. #define CPU_PCI_0_HEADERS_RETARGET_BASE 0x3b8
  188. #define CPU_PCI_1_HEADERS_RETARGET_CONTROL 0x3c0
  189. #define CPU_PCI_1_HEADERS_RETARGET_BASE 0x3c8
  190. #define CPU_GE_HEADERS_RETARGET_CONTROL 0x3d0
  191. #define CPU_GE_HEADERS_RETARGET_BASE 0x3d8
  192. /* MV64360 and MV64460 no changes needed*/
  193. /*****************************************************************************************/
  194. /****************************************/
  195. /* CPU Control Registers */
  196. /****************************************/
  197. /* CPU MASTER CONTROL REGISTER */
  198. #define CPU_CONFIGURATION 0x000
  199. #define CPU_MASTER_CONTROL 0x160
  200. #define CPU_CONFIG 0x000
  201. #define CPU_MODE 0x120
  202. #define CPU_MASTER_CONTROL 0x160
  203. /* new in MV64360 and MV64460 */
  204. #define CPU_CROSS_BAR_CONTROL_LOW 0x150
  205. #define CPU_CROSS_BAR_CONTROL_HIGH 0x158
  206. #define CPU_CROSS_BAR_TIMEOUT 0x168
  207. /****************************************/
  208. /* SMP RegisterS */
  209. /****************************************/
  210. #define SMP_WHO_AM_I 0x200
  211. #define SMP_CPU0_DOORBELL 0x214
  212. #define SMP_CPU0_DOORBELL_CLEAR 0x21C
  213. #define SMP_CPU1_DOORBELL 0x224
  214. #define SMP_CPU1_DOORBELL_CLEAR 0x22C
  215. #define SMP_CPU0_DOORBELL_MASK 0x234
  216. #define SMP_CPU1_DOORBELL_MASK 0x23C
  217. #define SMP_SEMAPHOR0 0x244
  218. #define SMP_SEMAPHOR1 0x24c
  219. #define SMP_SEMAPHOR2 0x254
  220. #define SMP_SEMAPHOR3 0x25c
  221. #define SMP_SEMAPHOR4 0x264
  222. #define SMP_SEMAPHOR5 0x26c
  223. #define SMP_SEMAPHOR6 0x274
  224. #define SMP_SEMAPHOR7 0x27c
  225. /****************************************/
  226. /* CPU Sync Barrier */
  227. /****************************************/
  228. #define CPU_0_SYNC_BARRIER_TRIGGER 0x0c0
  229. #define CPU_0_SYNC_BARRIER_VIRTUAL 0x0c8
  230. #define CPU_1_SYNC_BARRIER_TRIGGER 0x0d0
  231. #define CPU_1_SYNC_BARRIER_VIRTUAL 0x0d8
  232. /****************************************/
  233. /* CPU Access Protect */
  234. /****************************************/
  235. #define CPU_LOW_PROTECT_ADDRESS_0 0x180
  236. #define CPU_HIGH_PROTECT_ADDRESS_0 0x188
  237. #define CPU_LOW_PROTECT_ADDRESS_1 0x190
  238. #define CPU_HIGH_PROTECT_ADDRESS_1 0x198
  239. #define CPU_LOW_PROTECT_ADDRESS_2 0x1a0
  240. #define CPU_HIGH_PROTECT_ADDRESS_2 0x1a8
  241. #define CPU_LOW_PROTECT_ADDRESS_3 0x1b0
  242. #define CPU_HIGH_PROTECT_ADDRESS_3 0x1b8
  243. /*#define CPU_LOW_PROTECT_ADDRESS_4 0x1c0
  244. #define CPU_HIGH_PROTECT_ADDRESS_4 0x1c8
  245. #define CPU_LOW_PROTECT_ADDRESS_5 0x1d0
  246. #define CPU_HIGH_PROTECT_ADDRESS_5 0x1d8
  247. #define CPU_LOW_PROTECT_ADDRESS_6 0x1e0
  248. #define CPU_HIGH_PROTECT_ADDRESS_6 0x1e8
  249. #define CPU_LOW_PROTECT_ADDRESS_7 0x1f0
  250. #define CPU_HIGH_PROTECT_ADDRESS_7 0x1f8
  251. */
  252. #define CPU_PROTECT_WINDOW_0_BASE_ADDR CPU_LOW_PROTECT_ADDRESS_0 /* 0x180 */
  253. #define CPU_PROTECT_WINDOW_0_SIZE CPU_HIGH_PROTECT_ADDRESS_0 /* 0x188 */
  254. #define CPU_PROTECT_WINDOW_1_BASE_ADDR CPU_LOW_PROTECT_ADDRESS_1 /* 0x190 */
  255. #define CPU_PROTECT_WINDOW_1_SIZE CPU_HIGH_PROTECT_ADDRESS_1 /* 0x198 */
  256. #define CPU_PROTECT_WINDOW_2_BASE_ADDR CPU_LOW_PROTECT_ADDRESS_2 /*0x1a0 */
  257. #define CPU_PROTECT_WINDOW_2_SIZE CPU_HIGH_PROTECT_ADDRESS_2 /* 0x1a8 */
  258. #define CPU_PROTECT_WINDOW_3_BASE_ADDR CPU_LOW_PROTECT_ADDRESS_3 /* 0x1b0 */
  259. #define CPU_PROTECT_WINDOW_3_SIZE CPU_HIGH_PROTECT_ADDRESS_3 /* 0x1b8 */
  260. /****************************************/
  261. /* Snoop Control */
  262. /****************************************/
  263. /*#define SNOOP_BASE_ADDRESS_0 0x380
  264. #define SNOOP_TOP_ADDRESS_0 0x388
  265. #define SNOOP_BASE_ADDRESS_1 0x390
  266. #define SNOOP_TOP_ADDRESS_1 0x398
  267. #define SNOOP_BASE_ADDRESS_2 0x3a0
  268. #define SNOOP_TOP_ADDRESS_2 0x3a8
  269. #define SNOOP_BASE_ADDRESS_3 0x3b0
  270. #define SNOOP_TOP_ADDRESS_3 0x3b8
  271. */
  272. /****************************************/
  273. /* Integrated SRAM Registers */
  274. /****************************************/
  275. #define SRAM_CONFIG 0x380
  276. #define SRAM_TEST_MODE 0x3F4
  277. #define SRAM_ERROR_CAUSE 0x388
  278. #define SRAM_ERROR_ADDR 0x390
  279. #define SRAM_ERROR_ADDR_HIGH 0x3F8
  280. #define SRAM_ERROR_DATA_LOW 0x398
  281. #define SRAM_ERROR_DATA_HIGH 0x3a0
  282. #define SRAM_ERROR_DATA_PARITY 0x3a8
  283. /****************************************/
  284. /* CPU Error Report */
  285. /****************************************/
  286. #define CPU_ERROR_ADDRESS_LOW 0x070
  287. #define CPU_ERROR_ADDRESS_HIGH 0x078
  288. #define CPU_ERROR_DATA_LOW 0x128
  289. #define CPU_ERROR_DATA_HIGH 0x130
  290. #define CPU_ERROR_PARITY 0x138
  291. #define CPU_ERROR_CAUSE 0x140
  292. #define CPU_ERROR_MASK 0x148
  293. #define CPU_ERROR_ADDR_LOW CPU_ERROR_ADDRESS_LOW /* 0x0701 */
  294. #define CPU_ERROR_ADDR_HIGH CPU_ERROR_ADDRESS_HIGH /* 0x0781 */
  295. /****************************************/
  296. /* Pslave Debug */
  297. /* CPU Interface Debug Registers */
  298. /****************************************/
  299. #define X_0_ADDRESS 0x360
  300. #define X_0_COMMAND_ID 0x368
  301. #define X_1_ADDRESS 0x370
  302. #define X_1_COMMAND_ID 0x378
  303. /*#define WRITE_DATA_LOW 0x3c01 */
  304. /*#define WRITE_DATA_HIGH 0x3c81 */
  305. /*#define WRITE_BYTE_ENABLE 0x3e01 */
  306. /*#define READ_DATA_LOW 0x3d01 */
  307. /*#define READ_DATA_HIGH 0x3d81 */
  308. /*#define READ_ID 0x3e81 */
  309. #define PUNIT_SLAVE_DEBUG_LOW X_0_ADDRESS /* 0x3601 */
  310. #define PUNIT_SLAVE_DEBUG_HIGH X_0_COMMAND_ID /* 0x3681 */
  311. #define PUNIT_MASTER_DEBUG_LOW X_1_ADDRESS /* 0x3701 */
  312. #define PUNIT_MASTER_DEBUG_HIGH X_1_COMMAND_ID /* 0x3781 */
  313. #define PUNIT_MMASK 0x3e4
  314. /****************************************/
  315. /* SDRAM and Device Address Space */
  316. /****************************************/
  317. /****************************************/
  318. /* SDRAM Configuration */
  319. /****************************************/
  320. #define SDRAM_CONFIG 0x1400 /* MV64260 0x448 some changes*/
  321. #define D_UNIT_CONTROL_LOW 0x1404 /* NEW in MV64360 and MV64460 */
  322. #define D_UNIT_CONTROL_HIGH 0x1424 /* NEW in MV64360 and MV64460 */
  323. #define SDRAM_TIMING_CONTROL_LOW 0x1408 /* MV64260 0x4b4 new SDRAM TIMING REGISTER */
  324. #define SDRAM_TIMING_CONTROL_HIGH 0x140c /* MV64260 0x4b4 new SDRAM TIMING REGISTER */
  325. #define SDRAM_ADDR_CONTROL 0x1410 /* MV64260 0x47c some changes*/
  326. #define SDRAM_OPEN_PAGES_CONTROL 0x1414 /* NEW in MV64360 and MV64460 */
  327. #define SDRAM_OPERATION 0x1418 /* MV64260 0x474 some changes*/
  328. #define SDRAM_MODE 0x141c /* NEW in MV64360 and MV64460 */
  329. #define EXTENDED_DRAM_MODE 0x1420 /* NEW in MV64360 and MV64460 */
  330. #define SDRAM_CROSS_BAR_CONTROL_LOW 0x1430 /* MV64260 0x4a8 NO changes*/
  331. #define SDRAM_CROSS_BAR_CONTROL_HIGH 0x1434 /* MV64260 0x4ac NO changes*/
  332. #define SDRAM_CROSS_BAR_TIMEOUT 0x1438 /* MV64260 0x4b0 NO changes*/
  333. #define SDRAM_ADDR_CTRL_PADS_CALIBRATION 0x14c0 /* what is this ??? */
  334. #define SDRAM_DATA_PADS_CALIBRATION 0x14c4 /* what is this ??? */
  335. /****************************************/
  336. /* SDRAM Configuration MV64260 */
  337. /****************************************/
  338. /*#define SDRAM_CONFIGURATION 0x4481 */
  339. /*#define SDRAM_OPERATION_MODE 0x4741 */
  340. /*#define SDRAM_ADDRESS_DECODE 0x47c1 */
  341. /*#define SDRAM_UMA_CONTROL 0x4a4 eliminated in MV64360 and MV64460 */
  342. /*#define SDRAM_CROSS_BAR_CONTROL_LOW 0x4a81 */
  343. /*#define SDRAM_CROSS_BAR_CONTROL_HIGH 0x4ac1 */
  344. /*#define SDRAM_CROSS_BAR_TIMEOUT 0x4b01 */
  345. /*#define SDRAM_TIMING 0x4b41 */
  346. /****************************************/
  347. /* SDRAM Error Report */
  348. /****************************************/
  349. #define SDRAM_ERROR_DATA_LOW 0x1444 /* MV64260 0x484 NO changes*/
  350. #define SDRAM_ERROR_DATA_HIGH 0x1440 /* MV64260 0x480 NO changes*/
  351. #define SDRAM_ERROR_ADDR 0x1450 /* MV64260 0x490 NO changes*/
  352. #define SDRAM_RECEIVED_ECC 0x1448 /* MV64260 0x488 NO changes*/
  353. #define SDRAM_CALCULATED_ECC 0x144c /* MV64260 0x48c NO changes*/
  354. #define SDRAM_ECC_CONTROL 0x1454 /* MV64260 0x494 NO changes*/
  355. #define SDRAM_ECC_ERROR_COUNTER 0x1458 /* MV64260 0x498 NO changes*/
  356. #define SDRAM_MMASK 0x1B40 /* NEW Register in MV64360 and MV64460 DO NOT USE !!!*/
  357. /****************************************/
  358. /* SDRAM Error Report MV64260 */
  359. /****************************************/
  360. /*#define SDRAM_ERROR_DATA_LOW 0x4841 */
  361. /*#define SDRAM_ERROR_DATA_HIGH 0x4801 */
  362. /*#define SDRAM_AND_DEVICE_ERROR_ADDRESS 0x4901 */
  363. /*#define SDRAM_RECEIVED_ECC 0x4881 */
  364. /*#define SDRAM_CALCULATED_ECC 0x48c1 */
  365. /*#define SDRAM_ECC_CONTROL 0x4941 */
  366. /*#define SDRAM_ECC_ERROR_COUNTER 0x4981 */
  367. /******************************************/
  368. /* Controlled Delay Line (CDL) Registers */
  369. /******************************************/
  370. #define DFCDL_CONFIG0 0x1480
  371. #define DFCDL_CONFIG1 0x1484
  372. #define DLL_WRITE 0x1488
  373. #define DLL_READ 0x148c
  374. #define SRAM_ADDR 0x1490
  375. #define SRAM_DATA0 0x1494
  376. #define SRAM_DATA1 0x1498
  377. #define SRAM_DATA2 0x149c
  378. #define DFCL_PROBE 0x14a0
  379. /****************************************/
  380. /* SDRAM Parameters only in MV64260 */
  381. /****************************************/
  382. /*#define SDRAM_BANK0PARAMETERS 0x44C eliminated in MV64360 and MV64460 */
  383. /*#define SDRAM_BANK1PARAMETERS 0x450 eliminated in MV64360 and MV64460 */
  384. /*#define SDRAM_BANK2PARAMETERS 0x454 eliminated in MV64360 and MV64460 */
  385. /*#define SDRAM_BANK3PARAMETERS 0x458 eliminated in MV64360 and MV64460 */
  386. /******************************************/
  387. /* Debug Registers */
  388. /******************************************/
  389. #define DUNIT_DEBUG_LOW 0x1460
  390. #define DUNIT_DEBUG_HIGH 0x1464
  391. #define DUNIT_MMASK 0x1b40
  392. /****************************************/
  393. /* SDunit Debug (for internal use) */
  394. /****************************************/
  395. #define X0_ADDRESS 0x500
  396. #define X0_COMMAND_AND_ID 0x504
  397. #define X0_WRITE_DATA_LOW 0x508
  398. #define X0_WRITE_DATA_HIGH 0x50c
  399. #define X0_WRITE_BYTE_ENABLE 0x518
  400. #define X0_READ_DATA_LOW 0x510
  401. #define X0_READ_DATA_HIGH 0x514
  402. #define X0_READ_ID 0x51c
  403. #define X1_ADDRESS 0x520
  404. #define X1_COMMAND_AND_ID 0x524
  405. #define X1_WRITE_DATA_LOW 0x528
  406. #define X1_WRITE_DATA_HIGH 0x52c
  407. #define X1_WRITE_BYTE_ENABLE 0x538
  408. #define X1_READ_DATA_LOW 0x530
  409. #define X1_READ_DATA_HIGH 0x534
  410. #define X1_READ_ID 0x53c
  411. #define X0_SNOOP_ADDRESS 0x540
  412. #define X0_SNOOP_COMMAND 0x544
  413. #define X1_SNOOP_ADDRESS 0x548
  414. #define X1_SNOOP_COMMAND 0x54c
  415. /****************************************/
  416. /* Device Parameters */
  417. /****************************************/
  418. #define DEVICE_BANK0PARAMETERS 0x45c
  419. #define DEVICE_BANK1PARAMETERS 0x460
  420. #define DEVICE_BANK2PARAMETERS 0x464
  421. #define DEVICE_BANK3PARAMETERS 0x468
  422. #define DEVICE_BOOT_BANK_PARAMETERS 0x46c
  423. #define DEVICE_CONTROL 0x4c0
  424. #define DEVICE_CROSS_BAR_CONTROL_LOW 0x4c8
  425. #define DEVICE_CROSS_BAR_CONTROL_HIGH 0x4cc
  426. #define DEVICE_CROSS_BAR_TIMEOUT 0x4c4
  427. /****************************************/
  428. /* Device Parameters */
  429. /****************************************/
  430. #define DEVICE_BANK0_PARAMETERS DEVICE_BANK0PARAMETERS /* 0x45c1 */
  431. #define DEVICE_BANK1_PARAMETERS DEVICE_BANK1PARAMETERS /* 0x4601 */
  432. #define DEVICE_BANK2_PARAMETERS DEVICE_BANK2PARAMETERS /* 0x4641 */
  433. #define DEVICE_BANK3_PARAMETERS DEVICE_BANK3PARAMETERS /* 0x4681 */
  434. /*#define DEVICE_BOOT_BANK_PARAMETERS 0x46c1 */
  435. #define DEVICE_INTERFACE_CONTROL DEVICE_CONTROL /* 0x4c01 */
  436. #define DEVICE_INTERFACE_CROSS_BAR_CONTROL_LOW DEVICE_CROSS_BAR_CONTROL_LOW /* 0x4c81 */
  437. #define DEVICE_INTERFACE_CROSS_BAR_CONTROL_HIGH DEVICE_CROSS_BAR_CONTROL_HIGH /* 0x4cc1 */
  438. #define DEVICE_INTERFACE_CROSS_BAR_TIMEOUT DEVICE_CROSS_BAR_TIMEOUT /* 0x4c41 */
  439. /****************************************/
  440. /* Device Interrupt */
  441. /****************************************/
  442. #define DEVICE_INTERRUPT_CAUSE 0x4d0
  443. #define DEVICE_INTERRUPT_MASK 0x4d4
  444. #define DEVICE_ERROR_ADDRESS 0x4d8
  445. /*#define DEVICE_INTERRUPT_CAUSE 0x4d01 */
  446. /*#define DEVICE_INTERRUPT_MASK 0x4d41 */
  447. #define DEVICE_ERROR_ADDR DEVICE_ERROR_ADDRESS /*0x4d81 */
  448. #define DEVICE_ERROR_DATA 0x4dc
  449. #define DEVICE_ERROR_PARITY 0x4e0
  450. /****************************************/
  451. /* Device debug registers */
  452. /****************************************/
  453. #define DEVICE_DEBUG_LOW 0x4e4
  454. #define DEVICE_DEBUG_HIGH 0x4e8
  455. #define RUNIT_MMASK 0x4f0
  456. /****************************************/
  457. /* DMA Record */
  458. /****************************************/
  459. /*#define CHANNEL4_DMA_BYTE_COUNT 0x9001 */
  460. /*#define CHANNEL5_DMA_BYTE_COUNT 0x9041 */
  461. /*#define CHANNEL6_DMA_BYTE_COUNT 0x9081 */
  462. /*#define CHANNEL7_DMA_BYTE_COUNT 0x90C1 */
  463. /*#define CHANNEL4_DMA_SOURCE_ADDRESS 0x9101 */
  464. /*#define CHANNEL5_DMA_SOURCE_ADDRESS 0x9141 */
  465. /*#define CHANNEL6_DMA_SOURCE_ADDRESS 0x9181 */
  466. /*#define CHANNEL7_DMA_SOURCE_ADDRESS 0x91C1 */
  467. /*#define CHANNEL4_DMA_DESTINATION_ADDRESS 0x9201 */
  468. /*#define CHANNEL5_DMA_DESTINATION_ADDRESS 0x9241 */
  469. /*#define CHANNEL6_DMA_DESTINATION_ADDRESS 0x9281 */
  470. /*#define CHANNEL7_DMA_DESTINATION_ADDRESS 0x92C1 */
  471. /*#define CHANNEL4NEXT_RECORD_POINTER 0x9301 */
  472. /*#define CHANNEL5NEXT_RECORD_POINTER 0x9341 */
  473. /*#define CHANNEL6NEXT_RECORD_POINTER 0x9381 */
  474. /*#define CHANNEL7NEXT_RECORD_POINTER 0x93C1 */
  475. /*#define CHANNEL4CURRENT_DESCRIPTOR_POINTER 0x9701 */
  476. /*#define CHANNEL5CURRENT_DESCRIPTOR_POINTER 0x9741 */
  477. /*#define CHANNEL6CURRENT_DESCRIPTOR_POINTER 0x9781 */
  478. /*#define CHANNEL7CURRENT_DESCRIPTOR_POINTER 0x97C1 */
  479. /*#define CHANNEL0_DMA_SOURCE_HIGH_PCI_ADDRESS 0x8901 */
  480. /*#define CHANNEL1_DMA_SOURCE_HIGH_PCI_ADDRESS 0x8941 */
  481. /*#define CHANNEL2_DMA_SOURCE_HIGH_PCI_ADDRESS 0x8981 */
  482. /*#define CHANNEL3_DMA_SOURCE_HIGH_PCI_ADDRESS 0x89c1 */
  483. /*#define CHANNEL4_DMA_SOURCE_HIGH_PCI_ADDRESS 0x9901 */
  484. /*#define CHANNEL5_DMA_SOURCE_HIGH_PCI_ADDRESS 0x9941 */
  485. /*#define CHANNEL6_DMA_SOURCE_HIGH_PCI_ADDRESS 0x9981 */
  486. /*#define CHANNEL7_DMA_SOURCE_HIGH_PCI_ADDRESS 0x99c1 */
  487. /*#define CHANNEL0_DMA_DESTINATION_HIGH_PCI_ADDRESS 0x8a01 */
  488. /*#define CHANNEL1_DMA_DESTINATION_HIGH_PCI_ADDRESS 0x8a41 */
  489. /*#define CHANNEL2_DMA_DESTINATION_HIGH_PCI_ADDRESS 0x8a81 */
  490. /*#define CHANNEL3_DMA_DESTINATION_HIGH_PCI_ADDRESS 0x8ac1 */
  491. /*#define CHANNEL4_DMA_DESTINATION_HIGH_PCI_ADDRESS 0x9a01 */
  492. /*#define CHANNEL5_DMA_DESTINATION_HIGH_PCI_ADDRESS 0x9a41 */
  493. /*#define CHANNEL6_DMA_DESTINATION_HIGH_PCI_ADDRESS 0x9a81 */
  494. /*#define CHANNEL7_DMA_DESTINATION_HIGH_PCI_ADDRESS 0x9ac1 */
  495. /*#define CHANNEL0_DMA_NEXT_RECORD_POINTER_HIGH_PCI_ADDRESS 0x8b01 */
  496. /*#define CHANNEL1_DMA_NEXT_RECORD_POINTER_HIGH_PCI_ADDRESS 0x8b41 */
  497. /*#define CHANNEL2_DMA_NEXT_RECORD_POINTER_HIGH_PCI_ADDRESS 0x8b81 */
  498. /*#define CHANNEL3_DMA_NEXT_RECORD_POINTER_HIGH_PCI_ADDRESS 0x8bc1 */
  499. /*#define CHANNEL4_DMA_NEXT_RECORD_POINTER_HIGH_PCI_ADDRESS 0x9b01 */
  500. /*#define CHANNEL5_DMA_NEXT_RECORD_POINTER_HIGH_PCI_ADDRESS 0x9b41 */
  501. /*#define CHANNEL6_DMA_NEXT_RECORD_POINTER_HIGH_PCI_ADDRESS 0x9b81 */
  502. /*#define CHANNEL7_DMA_NEXT_RECORD_POINTER_HIGH_PCI_ADDRESS 0x9bc1 */
  503. /****************************************/
  504. /* DMA Channel Control */
  505. /****************************************/
  506. #define CHANNEL0CONTROL 0x840
  507. #define CHANNEL0CONTROL_HIGH 0x880
  508. #define CHANNEL1CONTROL 0x844
  509. #define CHANNEL1CONTROL_HIGH 0x884
  510. #define CHANNEL2CONTROL 0x848
  511. #define CHANNEL2CONTROL_HIGH 0x888
  512. #define CHANNEL3CONTROL 0x84C
  513. #define CHANNEL3CONTROL_HIGH 0x88C
  514. #define DMA_CHANNEL0_CONTROL CHANNEL0CONTROL /*0x8401 */
  515. #define DMA_CHANNEL0_CONTROL_HIGH CHANNEL0CONTROL_HIGH /*0x8801 */
  516. #define DMA_CHANNEL1_CONTROL CHANNEL1CONTROL /* 0x8441 */
  517. #define DMA_CHANNEL1_CONTROL_HIGH CHANNEL1CONTROL_HIGH /*0x8841 */
  518. #define DMA_CHANNEL2_CONTROL CHANNEL2CONTROL /*0x8481 */
  519. #define DMA_CHANNEL2_CONTROL_HIGH CHANNEL2CONTROL_HIGH /*0x8881 */
  520. #define DMA_CHANNEL3_CONTROL CHANNEL3CONTROL /*0x84C1 */
  521. #define DMA_CHANNEL3_CONTROL_HIGH CHANNEL3CONTROL_HIGH /*0x88C1 */
  522. /*#define CHANNEL4CONTROL 0x9401 */
  523. /*#define CHANNEL4CONTROL_HIGH 0x9801 */
  524. /*#define CHANNEL5CONTROL 0x9441 */
  525. /*#define CHANNEL5CONTROL_HIGH 0x9841 */
  526. /*#define CHANNEL6CONTROL 0x9481 */
  527. /*#define CHANNEL6CONTROL_HIGH 0x9881 */
  528. /*#define CHANNEL7CONTROL 0x94C1 */
  529. /*#define CHANNEL7CONTROL_HIGH 0x98C1 */
  530. /****************************************/
  531. /* DMA Arbiter */
  532. /****************************************/
  533. /*#define ARBITER_CONTROL_0_3 0x8601 */
  534. #define ARBITER_CONTROL_4_7 0x960
  535. /****************************************/
  536. /* IDMA Registers */
  537. /****************************************/
  538. #define DMA_CHANNEL0_BYTE_COUNT CHANNEL0_DMA_BYTE_COUNT /*0x8001 */
  539. #define DMA_CHANNEL1_BYTE_COUNT CHANNEL1_DMA_BYTE_COUNT /*0x8041 */
  540. #define DMA_CHANNEL2_BYTE_COUNT CHANNEL2_DMA_BYTE_COUNT /*0x8081 */
  541. #define DMA_CHANNEL3_BYTE_COUNT CHANNEL3_DMA_BYTE_COUNT /*0x80C1 */
  542. #define DMA_CHANNEL0_SOURCE_ADDR CHANNEL0_DMA_SOURCE_ADDRESS /*0x8101 */
  543. #define DMA_CHANNEL1_SOURCE_ADDR CHANNEL1_DMA_SOURCE_ADDRESS /*0x8141 */
  544. #define DMA_CHANNEL2_SOURCE_ADDR CHANNEL2_DMA_SOURCE_ADDRESS /*0x8181 */
  545. #define DMA_CHANNEL3_SOURCE_ADDR CHANNEL3_DMA_SOURCE_ADDRESS /*0x81c1 */
  546. #define DMA_CHANNEL0_DESTINATION_ADDR CHANNEL0_DMA_DESTINATION_ADDRESS /*0x8201 */
  547. #define DMA_CHANNEL1_DESTINATION_ADDR CHANNEL1_DMA_DESTINATION_ADDRESS /*0x8241 */
  548. #define DMA_CHANNEL2_DESTINATION_ADDR CHANNEL2_DMA_DESTINATION_ADDRESS /*0x8281 */
  549. #define DMA_CHANNEL3_DESTINATION_ADDR CHANNEL3_DMA_DESTINATION_ADDRESS /*0x82C1 */
  550. #define DMA_CHANNEL0_NEXT_DESCRIPTOR_POINTER CHANNEL0NEXT_RECORD_POINTER /*0x8301 */
  551. #define DMA_CHANNEL1_NEXT_DESCRIPTOR_POINTER CHANNEL1NEXT_RECORD_POINTER /*0x8341 */
  552. #define DMA_CHANNEL2_NEXT_DESCRIPTOR_POINTER CHANNEL2NEXT_RECORD_POINTER /*0x8381 */
  553. #define DMA_CHANNEL3_NEXT_DESCRIPTOR_POINTER CHANNEL3NEXT_RECORD_POINTER /*0x83C1 */
  554. #define DMA_CHANNEL0_CURRENT_DESCRIPTOR_POINTER CHANNEL0CURRENT_DESCRIPTOR_POINTER /*0x8701 */
  555. #define DMA_CHANNEL1_CURRENT_DESCRIPTOR_POINTER CHANNEL1CURRENT_DESCRIPTOR_POINTER /*0x8741 */
  556. #define DMA_CHANNEL2_CURRENT_DESCRIPTOR_POINTER CHANNEL2CURRENT_DESCRIPTOR_POINTER /*0x8781 */
  557. #define DMA_CHANNEL3_CURRENT_DESCRIPTOR_POINTER CHANNEL3CURRENT_DESCRIPTOR_POINTER /*0x87C1 */
  558. #define CHANNEL3CURRENT_DESCRIPTOR_POINTER 0x87C
  559. #define CHANNEL2CURRENT_DESCRIPTOR_POINTER 0x878
  560. #define CHANNEL1CURRENT_DESCRIPTOR_POINTER 0x874
  561. #define CHANNEL0CURRENT_DESCRIPTOR_POINTER 0x870
  562. #define CHANNEL0NEXT_RECORD_POINTER 0x830
  563. #define CHANNEL1NEXT_RECORD_POINTER 0x834
  564. #define CHANNEL2NEXT_RECORD_POINTER 0x838
  565. #define CHANNEL3NEXT_RECORD_POINTER 0x83C
  566. #define CHANNEL0_DMA_DESTINATION_ADDRESS 0x820
  567. #define CHANNEL1_DMA_DESTINATION_ADDRESS 0x824
  568. #define CHANNEL2_DMA_DESTINATION_ADDRESS 0x828
  569. #define CHANNEL3_DMA_DESTINATION_ADDRESS 0x82C
  570. #define CHANNEL0_DMA_SOURCE_ADDRESS 0x810
  571. #define CHANNEL1_DMA_SOURCE_ADDRESS 0x814
  572. #define CHANNEL2_DMA_SOURCE_ADDRESS 0x818
  573. #define CHANNEL3_DMA_SOURCE_ADDRESS 0x81C
  574. #define CHANNEL0_DMA_BYTE_COUNT 0x800
  575. #define CHANNEL1_DMA_BYTE_COUNT 0x804
  576. #define CHANNEL2_DMA_BYTE_COUNT 0x808
  577. #define CHANNEL3_DMA_BYTE_COUNT 0x80C
  578. /* IDMA Address Decoding Base Address Registers */
  579. #define DMA_BASE_ADDR_REG0 0xa00
  580. #define DMA_BASE_ADDR_REG1 0xa08
  581. #define DMA_BASE_ADDR_REG2 0xa10
  582. #define DMA_BASE_ADDR_REG3 0xa18
  583. #define DMA_BASE_ADDR_REG4 0xa20
  584. #define DMA_BASE_ADDR_REG5 0xa28
  585. #define DMA_BASE_ADDR_REG6 0xa30
  586. #define DMA_BASE_ADDR_REG7 0xa38
  587. /* IDMA Address Decoding Size Address Register */
  588. #define DMA_SIZE_REG0 0xa04
  589. #define DMA_SIZE_REG1 0xa0c
  590. #define DMA_SIZE_REG2 0xa14
  591. #define DMA_SIZE_REG3 0xa1c
  592. #define DMA_SIZE_REG4 0xa24
  593. #define DMA_SIZE_REG5 0xa2c
  594. #define DMA_SIZE_REG6 0xa34
  595. #define DMA_SIZE_REG7 0xa3C
  596. /* IDMA Address Decoding High Address Remap and Access
  597. Protection Registers */
  598. #define DMA_HIGH_ADDR_REMAP_REG0 0xa60
  599. #define DMA_HIGH_ADDR_REMAP_REG1 0xa64
  600. #define DMA_HIGH_ADDR_REMAP_REG2 0xa68
  601. #define DMA_HIGH_ADDR_REMAP_REG3 0xa6C
  602. #define DMA_BASE_ADDR_ENABLE_REG 0xa80
  603. #define DMA_CHANNEL0_ACCESS_PROTECTION_REG 0xa70
  604. #define DMA_CHANNEL1_ACCESS_PROTECTION_REG 0xa74
  605. #define DMA_CHANNEL2_ACCESS_PROTECTION_REG 0xa78
  606. #define DMA_CHANNEL3_ACCESS_PROTECTION_REG 0xa7c
  607. #define DMA_ARBITER_CONTROL 0x860
  608. #define DMA_CROSS_BAR_TIMEOUT 0x8d0
  609. /* IDMA Headers Retarget Registers */
  610. /*#define CPU_IDMA_HEADERS_RETARGET_CONTROL 0x3e01 */
  611. /*#define CPU_IDMA_HEADERS_RETARGET_BASE 0x3e81 */
  612. #define DMA_HEADERS_RETARGET_CONTROL 0xa84
  613. #define DMA_HEADERS_RETARGET_BASE 0xa88
  614. /****************************************/
  615. /* DMA Interrupt */
  616. /****************************************/
  617. #define CHANELS0_3_INTERRUPT_CAUSE 0x8c0
  618. #define CHANELS0_3_INTERRUPT_MASK 0x8c4
  619. #define CHANELS0_3_ERROR_ADDRESS 0x8c8
  620. #define CHANELS0_3_ERROR_SELECT 0x8cc
  621. /*#define CHANELS4_7_INTERRUPT_CAUSE 0x9c01 */
  622. /*#define CHANELS4_7_INTERRUPT_MASK 0x9c41 */
  623. /*#define CHANELS4_7_ERROR_ADDRESS 0x9c81 */
  624. /*#define CHANELS4_7_ERROR_SELECT 0x9cc1 */
  625. #define DMA_INTERRUPT_CAUSE_REG CHANELS0_3_INTERRUPT_CAUSE /*0x8c01 */
  626. #define DMA_INTERRUPT_CAUSE_MASK CHANELS0_3_INTERRUPT_MASK /*0x8c41 */
  627. #define DMA_ERROR_ADDR CHANELS0_3_ERROR_ADDRESS /*0x8c81 */
  628. #define DMA_ERROR_SELECT CHANELS0_3_ERROR_SELECT /*0x8cc1 */
  629. /****************************************/
  630. /* DMA Debug (for internal use) */
  631. /****************************************/
  632. #define DMA_X0_ADDRESS 0x8e0
  633. #define DMA_X0_COMMAND_AND_ID 0x8e4
  634. /*#define DMA_X0_WRITE_DATA_LOW 0x8e81 */
  635. /*#define DMA_X0_WRITE_DATA_HIGH 0x8ec1 */
  636. /*#define DMA_X0_WRITE_BYTE_ENABLE 0x8f81 */
  637. /*#define DMA_X0_READ_DATA_LOW 0x8f01 */
  638. /*#define DMA_X0_READ_DATA_HIGH 0x8f41 */
  639. /*#define DMA_X0_READ_ID 0x8fc1 */
  640. /*#define DMA_X1_ADDRESS 0x9e01 */
  641. /*#define DMA_X1_COMMAND_AND_ID 0x9e41 */
  642. /*#define DMA_X1_WRITE_DATA_LOW 0x9e81 */
  643. /*#define DMA_X1_WRITE_DATA_HIGH 0x9ec1 */
  644. /*#define DMA_X1_WRITE_BYTE_ENABLE 0x9f81 */
  645. /*#define DMA_X1_READ_DATA_LOW 0x9f01 */
  646. /*#define DMA_X1_READ_DATA_HIGH 0x9f41 */
  647. /*#define DMA_X1_READ_ID 0x9fc1 */
  648. /* IDMA Debug Register ( for internal use ) */
  649. #define DMA_DEBUG_LOW DMA_X0_ADDRESS /* 0x8e01 */
  650. #define DMA_DEBUG_HIGH DMA_X0_COMMAND_AND_ID /*0x8e41 */
  651. #define DMA_SPARE 0xA8C
  652. /****************************************/
  653. /* Timer_Counter */
  654. /****************************************/
  655. #define TIMER_COUNTER0 0x850
  656. #define TIMER_COUNTER1 0x854
  657. #define TIMER_COUNTER2 0x858
  658. #define TIMER_COUNTER3 0x85C
  659. #define TIMER_COUNTER_0_3_CONTROL 0x864
  660. #define TIMER_COUNTER_0_3_INTERRUPT_CAUSE 0x868
  661. #define TIMER_COUNTER_0_3_INTERRUPT_MASK 0x86c
  662. /*#define TIMER_COUNTER4 0x9501 */
  663. /*#define TIMER_COUNTER5 0x9541 */
  664. /*#define TIMER_COUNTER6 0x9581 */
  665. /*#define TIMER_COUNTER7 0x95C1 */
  666. /*#define TIMER_COUNTER_4_7_CONTROL 0x9641 */
  667. /*#define TIMER_COUNTER_4_7_INTERRUPT_CAUSE 0x9681 */
  668. /*#define TIMER_COUNTER_4_7_INTERRUPT_MASK 0x96c1 */
  669. /****************************************/
  670. /* PCI Slave Address Decoding */
  671. /****************************************/
  672. /****************************************/
  673. /* PCI Slave Address Decoding registers */
  674. /****************************************/
  675. #define PCI_0_CS_0_BANK_SIZE PCI_0SCS_0_BANK_SIZE /*0xc081 */
  676. #define PCI_1_CS_0_BANK_SIZE PCI_1SCS_0_BANK_SIZE /* 0xc881 */
  677. #define PCI_0_CS_1_BANK_SIZE PCI_0SCS_1_BANK_SIZE /*0xd081 */
  678. #define PCI_1_CS_1_BANK_SIZE PCI_1SCS_1_BANK_SIZE /* 0xd881 */
  679. #define PCI_0_CS_2_BANK_SIZE PCI_0SCS_2_BANK_SIZE /*0xc0c1 */
  680. #define PCI_1_CS_2_BANK_SIZE PCI_1SCS_2_BANK_SIZE /*0xc8c1 */
  681. #define PCI_0_CS_3_BANK_SIZE PCI_0SCS_3_BANK_SIZE /*0xd0c1 */
  682. #define PCI_1_CS_3_BANK_SIZE PCI_1SCS_3_BANK_SIZE /*0xd8c1 */
  683. #define PCI_0_DEVCS_0_BANK_SIZE PCI_0CS_0_BANK_SIZE /*0xc101 */
  684. #define PCI_1_DEVCS_0_BANK_SIZE PCI_1CS_0_BANK_SIZE /*0xc901 */
  685. #define PCI_0_DEVCS_1_BANK_SIZE PCI_0CS_1_BANK_SIZE /*0xd101 */
  686. #define PCI_1_DEVCS_1_BANK_SIZE PCI_1CS_1_BANK_SIZE /* 0xd901 */
  687. #define PCI_0_DEVCS_2_BANK_SIZE PCI_0CS_2_BANK_SIZE /* 0xd181 */
  688. #define PCI_1_DEVCS_2_BANK_SIZE PCI_1CS_2_BANK_SIZE /*0xd981 */
  689. #define PCI_0_DEVCS_3_BANK_SIZE PCI_0CS_3_BANK_SIZE /* 0xc141 */
  690. #define PCI_1_DEVCS_3_BANK_SIZE PCI_1CS_3_BANK_SIZE /*0xc941 */
  691. #define PCI_0_DEVCS_BOOT_BANK_SIZE PCI_0CS_BOOT_BANK_SIZE /*0xd141 */
  692. #define PCI_1_DEVCS_BOOT_BANK_SIZE PCI_1CS_BOOT_BANK_SIZE /* 0xd941 */
  693. #define PCI_0_P2P_MEM0_BAR_SIZE PCI_0P2P_MEM0_BAR_SIZE /*0xd1c1 */
  694. #define PCI_1_P2P_MEM0_BAR_SIZE PCI_1P2P_MEM0_BAR_SIZE /*0xd9c1 */
  695. #define PCI_0_P2P_MEM1_BAR_SIZE PCI_0P2P_MEM1_BAR_SIZE /*0xd201 */
  696. #define PCI_1_P2P_MEM1_BAR_SIZE PCI_1P2P_MEM1_BAR_SIZE /*0xda01 */
  697. #define PCI_0_P2P_I_O_BAR_SIZE PCI_0P2P_I_O_BAR_SIZE /*0xd241 */
  698. #define PCI_1_P2P_I_O_BAR_SIZE PCI_1P2P_I_O_BAR_SIZE /*0xda41 */
  699. #define PCI_0_CPU_BAR_SIZE PCI_0CPU_BAR_SIZE /*0xd281 */
  700. #define PCI_1_CPU_BAR_SIZE PCI_1CPU_BAR_SIZE /*0xda81 */
  701. #define PCI_0_INTERNAL_SRAM_BAR_SIZE PCI_0DAC_SCS_0_BANK_SIZE /*0xe001 */
  702. #define PCI_1_INTERNAL_SRAM_BAR_SIZE PCI_1DAC_SCS_0_BANK_SIZE /*0xe801 */
  703. #define PCI_0_EXPANSION_ROM_BAR_SIZE PCI_0EXPANSION_ROM_BAR_SIZE /*0xd2c1 */
  704. #define PCI_1_EXPANSION_ROM_BAR_SIZE PCI_1EXPANSION_ROM_BAR_SIZE /*0xd9c1 */
  705. #define PCI_0_BASE_ADDR_REG_ENABLE PCI_0BASE_ADDRESS_REGISTERS_ENABLE /*0xc3c1 */
  706. #define PCI_1_BASE_ADDR_REG_ENABLE PCI_1BASE_ADDRESS_REGISTERS_ENABLE /*0xcbc1 */
  707. #define PCI_0_CS_0_BASE_ADDR_REMAP PCI_0SCS_0_BASE_ADDRESS_REMAP /*0xc481 */
  708. #define PCI_1_CS_0_BASE_ADDR_REMAP PCI_1SCS_0_BASE_ADDRESS_REMAP /*0xcc81 */
  709. #define PCI_0_CS_1_BASE_ADDR_REMAP PCI_0SCS_1_BASE_ADDRESS_REMAP /*0xd481 */
  710. #define PCI_1_CS_1_BASE_ADDR_REMAP PCI_1SCS_1_BASE_ADDRESS_REMAP /*0xdc81 */
  711. #define PCI_0_CS_2_BASE_ADDR_REMAP PCI_0SCS_2_BASE_ADDRESS_REMAP /*0xc4c1 */
  712. #define PCI_1_CS_2_BASE_ADDR_REMAP PCI_1SCS_2_BASE_ADDRESS_REMAP /*0xccc1 */
  713. #define PCI_0_CS_3_BASE_ADDR_REMAP PCI_0SCS_3_BASE_ADDRESS_REMAP /*0xd4c1 */
  714. #define PCI_1_CS_3_BASE_ADDR_REMAP PCI_1SCS_3_BASE_ADDRESS_REMAP /* 0xdcc1 */
  715. #define PCI_0_CS_0_BASE_HIGH_ADDR_REMAP PCI_0DAC_SCS_0_BASE_ADDRESS_REMAP
  716. #define PCI_1_CS_0_BASE_HIGH_ADDR_REMAP PCI_1DAC_SCS_0_BASE_ADDRESS_REMAP
  717. #define PCI_0_CS_1_BASE_HIGH_ADDR_REMAP PCI_0DAC_SCS_1_BASE_ADDRESS_REMAP
  718. #define PCI_1_CS_1_BASE_HIGH_ADDR_REMAP PCI_1DAC_SCS_1_BASE_ADDRESS_REMAP
  719. #define PCI_0_CS_2_BASE_HIGH_ADDR_REMAP PCI_0DAC_SCS_2_BASE_ADDRESS_REMAP
  720. #define PCI_1_CS_2_BASE_HIGH_ADDR_REMAP PCI_1DAC_SCS_2_BASE_ADDRESS_REMAP
  721. #define PCI_0_CS_3_BASE_HIGH_ADDR_REMAP PCI_0DAC_SCS_3_BASE_ADDRESS_REMAP
  722. #define PCI_1_CS_3_BASE_HIGH_ADDR_REMAP PCI_1DAC_SCS_3_BASE_ADDRESS_REMAP
  723. #define PCI_0_DEVCS_0_BASE_ADDR_REMAP PCI_0CS_0_BASE_ADDRESS_REMAP /*0xc501 */
  724. #define PCI_1_DEVCS_0_BASE_ADDR_REMAP PCI_1CS_0_BASE_ADDRESS_REMAP /*0xcd01 */
  725. #define PCI_0_DEVCS_1_BASE_ADDR_REMAP PCI_0CS_1_BASE_ADDRESS_REMAP /*0xd501 */
  726. #define PCI_1_DEVCS_1_BASE_ADDR_REMAP PCI_1CS_1_BASE_ADDRESS_REMAP /*0xdd01 */
  727. #define PCI_0_DEVCS_2_BASE_ADDR_REMAP PCI_0CS_2_BASE_ADDRESS_REMAP /*0xd581 */
  728. #define PCI_1_DEVCS_2_BASE_ADDR_REMAP PCI_1CS_2_BASE_ADDRESS_REMAP /*0xdd81 */
  729. #define PCI_0_DEVCS_3_BASE_ADDR_REMAP PCI_0CS_3_BASE_ADDRESS_REMAP /*0xc541 */
  730. #define PCI_1_DEVCS_3_BASE_ADDR_REMAP PCI_1CS_3_BASE_ADDRESS_REMAP /*0xcd41 */
  731. #define PCI_0_DEVCS_BOOTCS_BASE_ADDR_REMAP PCI_0CS_BOOTCS_BASE_ADDRESS_REMAP /*0xd541 */
  732. #define PCI_1_DEVCS_BOOTCS_BASE_ADDR_REMAP PCI_1CS_BOOTCS_BASE_ADDRESS_REMAP /*0xdd41 */
  733. #define PCI_0_P2P_MEM0_BASE_ADDR_REMAP_LOW PCI_0P2P_MEM0_BASE_ADDRESS_REMAP_LOW /*0xd5c1 */
  734. #define PCI_1_P2P_MEM0_BASE_ADDR_REMAP_LOW PCI_1P2P_MEM0_BASE_ADDRESS_REMAP_LOW /*0xddc1 */
  735. #define PCI_0_P2P_MEM0_BASE_ADDR_REMAP_HIGH PCI_0P2P_MEM0_BASE_ADDRESS_REMAP_HIGH /*0xd601 */
  736. #define PCI_1_P2P_MEM0_BASE_ADDR_REMAP_HIGH PCI_1P2P_MEM0_BASE_ADDRESS_REMAP_HIGH /*0xde01 */
  737. #define PCI_0_P2P_MEM1_BASE_ADDR_REMAP_LOW PCI_0P2P_MEM1_BASE_ADDRESS_REMAP_LOW /*0xd641 */
  738. #define PCI_1_P2P_MEM1_BASE_ADDR_REMAP_LOW PCI_1P2P_MEM1_BASE_ADDRESS_REMAP_LOW /*0xde41 */
  739. #define PCI_0_P2P_MEM1_BASE_ADDR_REMAP_HIGH PCI_0P2P_MEM1_BASE_ADDRESS_REMAP_HIGH /*0xd681 */
  740. #define PCI_1_P2P_MEM1_BASE_ADDR_REMAP_HIGH PCI_1P2P_MEM1_BASE_ADDRESS_REMAP_HIGH /*0xde81 */
  741. #define PCI_0_P2P_I_O_BASE_ADDR_REMAP PCI_0P2P_I_O_BASE_ADDRESS_REMAP /*0xd6c1 */
  742. #define PCI_1_P2P_I_O_BASE_ADDR_REMAP PCI_1P2P_I_O_BASE_ADDRESS_REMAP /*0xdec 1 */
  743. #define PCI_0_CPU_BASE_ADDR_REMAP_LOW PCI_0CPU_BASE_ADDRESS_REMAP /*0xd701 */
  744. #define PCI_1_CPU_BASE_ADDR_REMAP_LOW PCI_1CPU_BASE_ADDRESS_REMAP /*0xdf01 */
  745. #define PCI_0_CPU_BASE_ADDR_REMAP_HIGH 0xd74
  746. #define PCI_1_CPU_BASE_ADDR_REMAP_HIGH 0xdf4
  747. #define PCI_0_INTEGRATED_SRAM_BASE_ADDR_REMAP PCI_0DAC_SCS_0_BASE_ADDRESS_REMAP /*0xf001 */
  748. #define PCI_1_INTEGRATED_SRAM_BASE_ADDR_REMAP 0xf80
  749. #define PCI_0_EXPANSION_ROM_BASE_ADDR_REMAP PCI_0EXPANSION_ROM_BASE_ADDRESS_REMAP /*0xf381 */
  750. #define PCI_1_EXPANSION_ROM_BASE_ADDR_REMAP PCI_1EXPANSION_ROM_BASE_ADDRESS_REMAP /*0xfb81 */
  751. #define PCI_0_ADDR_DECODE_CONTROL PCI_0ADDRESS_DECODE_CONTROL /*0xd3c1 */
  752. #define PCI_1_ADDR_DECODE_CONTROL PCI_1ADDRESS_DECODE_CONTROL /*0xdbc1 */
  753. #define PCI_0_HEADERS_RETARGET_CONTROL 0xF40
  754. #define PCI_1_HEADERS_RETARGET_CONTROL 0xFc0
  755. #define PCI_0_HEADERS_RETARGET_BASE 0xF44
  756. #define PCI_1_HEADERS_RETARGET_BASE 0xFc4
  757. #define PCI_0_HEADERS_RETARGET_HIGH 0xF48
  758. #define PCI_1_HEADERS_RETARGET_HIGH 0xFc8
  759. #define PCI_0SCS_0_BANK_SIZE 0xc08
  760. #define PCI_1SCS_0_BANK_SIZE 0xc88
  761. #define PCI_0SCS_1_BANK_SIZE 0xd08
  762. #define PCI_1SCS_1_BANK_SIZE 0xd88
  763. #define PCI_0SCS_2_BANK_SIZE 0xc0c
  764. #define PCI_1SCS_2_BANK_SIZE 0xc8c
  765. #define PCI_0SCS_3_BANK_SIZE 0xd0c
  766. #define PCI_1SCS_3_BANK_SIZE 0xd8c
  767. #define PCI_0CS_0_BANK_SIZE 0xc10
  768. #define PCI_1CS_0_BANK_SIZE 0xc90
  769. #define PCI_0CS_1_BANK_SIZE 0xd10
  770. #define PCI_1CS_1_BANK_SIZE 0xd90
  771. #define PCI_0CS_2_BANK_SIZE 0xd18
  772. #define PCI_1CS_2_BANK_SIZE 0xd98
  773. #define PCI_0CS_3_BANK_SIZE 0xc14
  774. #define PCI_1CS_3_BANK_SIZE 0xc94
  775. #define PCI_0CS_BOOT_BANK_SIZE 0xd14
  776. #define PCI_1CS_BOOT_BANK_SIZE 0xd94
  777. #define PCI_0P2P_MEM0_BAR_SIZE 0xd1c
  778. #define PCI_1P2P_MEM0_BAR_SIZE 0xd9c
  779. #define PCI_0P2P_MEM1_BAR_SIZE 0xd20
  780. #define PCI_1P2P_MEM1_BAR_SIZE 0xda0
  781. #define PCI_0P2P_I_O_BAR_SIZE 0xd24
  782. #define PCI_1P2P_I_O_BAR_SIZE 0xda4
  783. #define PCI_0CPU_BAR_SIZE 0xd28
  784. #define PCI_1CPU_BAR_SIZE 0xda8
  785. #define PCI_0DAC_SCS_0_BANK_SIZE 0xe00
  786. #define PCI_1DAC_SCS_0_BANK_SIZE 0xe80
  787. #define PCI_0DAC_SCS_1_BANK_SIZE 0xe04
  788. #define PCI_1DAC_SCS_1_BANK_SIZE 0xe84
  789. #define PCI_0DAC_SCS_2_BANK_SIZE 0xe08
  790. #define PCI_1DAC_SCS_2_BANK_SIZE 0xe88
  791. #define PCI_0DAC_SCS_3_BANK_SIZE 0xe0c
  792. #define PCI_1DAC_SCS_3_BANK_SIZE 0xe8c
  793. #define PCI_0DAC_CS_0_BANK_SIZE 0xe10
  794. #define PCI_1DAC_CS_0_BANK_SIZE 0xe90
  795. #define PCI_0DAC_CS_1_BANK_SIZE 0xe14
  796. #define PCI_1DAC_CS_1_BANK_SIZE 0xe94
  797. #define PCI_0DAC_CS_2_BANK_SIZE 0xe18
  798. #define PCI_1DAC_CS_2_BANK_SIZE 0xe98
  799. #define PCI_0DAC_CS_3_BANK_SIZE 0xe1c
  800. #define PCI_1DAC_CS_3_BANK_SIZE 0xe9c
  801. #define PCI_0DAC_BOOTCS_BANK_SIZE 0xe20
  802. #define PCI_1DAC_BOOTCS_BANK_SIZE 0xea0
  803. #define PCI_0DAC_P2P_MEM0_BAR_SIZE 0xe24
  804. #define PCI_1DAC_P2P_MEM0_BAR_SIZE 0xea4
  805. #define PCI_0DAC_P2P_MEM1_BAR_SIZE 0xe28
  806. #define PCI_1DAC_P2P_MEM1_BAR_SIZE 0xea8
  807. #define PCI_0DAC_CPU_BAR_SIZE 0xe2c
  808. #define PCI_1DAC_CPU_BAR_SIZE 0xeac
  809. #define PCI_0EXPANSION_ROM_BAR_SIZE 0xd2c
  810. #define PCI_1EXPANSION_ROM_BAR_SIZE 0xdac
  811. #define PCI_0BASE_ADDRESS_REGISTERS_ENABLE 0xc3c
  812. #define PCI_1BASE_ADDRESS_REGISTERS_ENABLE 0xcbc
  813. #define PCI_0SCS_0_BASE_ADDRESS_REMAP 0xc48
  814. #define PCI_1SCS_0_BASE_ADDRESS_REMAP 0xcc8
  815. #define PCI_0SCS_1_BASE_ADDRESS_REMAP 0xd48
  816. #define PCI_1SCS_1_BASE_ADDRESS_REMAP 0xdc8
  817. #define PCI_0SCS_2_BASE_ADDRESS_REMAP 0xc4c
  818. #define PCI_1SCS_2_BASE_ADDRESS_REMAP 0xccc
  819. #define PCI_0SCS_3_BASE_ADDRESS_REMAP 0xd4c
  820. #define PCI_1SCS_3_BASE_ADDRESS_REMAP 0xdcc
  821. #define PCI_0CS_0_BASE_ADDRESS_REMAP 0xc50
  822. #define PCI_1CS_0_BASE_ADDRESS_REMAP 0xcd0
  823. #define PCI_0CS_1_BASE_ADDRESS_REMAP 0xd50
  824. #define PCI_1CS_1_BASE_ADDRESS_REMAP 0xdd0
  825. #define PCI_0CS_2_BASE_ADDRESS_REMAP 0xd58
  826. #define PCI_1CS_2_BASE_ADDRESS_REMAP 0xdd8
  827. #define PCI_0CS_3_BASE_ADDRESS_REMAP 0xc54
  828. #define PCI_1CS_3_BASE_ADDRESS_REMAP 0xcd4
  829. #define PCI_0CS_BOOTCS_BASE_ADDRESS_REMAP 0xd54
  830. #define PCI_1CS_BOOTCS_BASE_ADDRESS_REMAP 0xdd4
  831. #define PCI_0P2P_MEM0_BASE_ADDRESS_REMAP_LOW 0xd5c
  832. #define PCI_1P2P_MEM0_BASE_ADDRESS_REMAP_LOW 0xddc
  833. #define PCI_0P2P_MEM0_BASE_ADDRESS_REMAP_HIGH 0xd60
  834. #define PCI_1P2P_MEM0_BASE_ADDRESS_REMAP_HIGH 0xde0
  835. #define PCI_0P2P_MEM1_BASE_ADDRESS_REMAP_LOW 0xd64
  836. #define PCI_1P2P_MEM1_BASE_ADDRESS_REMAP_LOW 0xde4
  837. #define PCI_0P2P_MEM1_BASE_ADDRESS_REMAP_HIGH 0xd68
  838. #define PCI_1P2P_MEM1_BASE_ADDRESS_REMAP_HIGH 0xde8
  839. #define PCI_0P2P_I_O_BASE_ADDRESS_REMAP 0xd6c
  840. #define PCI_1P2P_I_O_BASE_ADDRESS_REMAP 0xdec
  841. #define PCI_0CPU_BASE_ADDRESS_REMAP 0xd70
  842. #define PCI_1CPU_BASE_ADDRESS_REMAP 0xdf0
  843. #define PCI_0DAC_SCS_0_BASE_ADDRESS_REMAP 0xf00
  844. #define PCI_1DAC_SCS_0_BASE_ADDRESS_REMAP 0xff0
  845. #define PCI_0DAC_SCS_1_BASE_ADDRESS_REMAP 0xf04
  846. #define PCI_1DAC_SCS_1_BASE_ADDRESS_REMAP 0xf84
  847. #define PCI_0DAC_SCS_2_BASE_ADDRESS_REMAP 0xf08
  848. #define PCI_1DAC_SCS_2_BASE_ADDRESS_REMAP 0xf88
  849. #define PCI_0DAC_SCS_3_BASE_ADDRESS_REMAP 0xf0c
  850. #define PCI_1DAC_SCS_3_BASE_ADDRESS_REMAP 0xf8c
  851. #define PCI_0DAC_CS_0_BASE_ADDRESS_REMAP 0xf10
  852. #define PCI_1DAC_CS_0_BASE_ADDRESS_REMAP 0xf90
  853. #define PCI_0DAC_CS_1_BASE_ADDRESS_REMAP 0xf14
  854. #define PCI_1DAC_CS_1_BASE_ADDRESS_REMAP 0xf94
  855. #define PCI_0DAC_CS_2_BASE_ADDRESS_REMAP 0xf18
  856. #define PCI_1DAC_CS_2_BASE_ADDRESS_REMAP 0xf98
  857. #define PCI_0DAC_CS_3_BASE_ADDRESS_REMAP 0xf1c
  858. #define PCI_1DAC_CS_3_BASE_ADDRESS_REMAP 0xf9c
  859. #define PCI_0DAC_BOOTCS_BASE_ADDRESS_REMAP 0xf20
  860. #define PCI_1DAC_BOOTCS_BASE_ADDRESS_REMAP 0xfa0
  861. #define PCI_0DAC_P2P_MEM0_BASE_ADDRESS_REMAP_LOW 0xf24
  862. #define PCI_1DAC_P2P_MEM0_BASE_ADDRESS_REMAP_LOW 0xfa4
  863. #define PCI_0DAC_P2P_MEM0_BASE_ADDRESS_REMAP_HIGH 0xf28
  864. #define PCI_1DAC_P2P_MEM0_BASE_ADDRESS_REMAP_HIGH 0xfa8
  865. #define PCI_0DAC_P2P_MEM1_BASE_ADDRESS_REMAP_LOW 0xf2c
  866. #define PCI_1DAC_P2P_MEM1_BASE_ADDRESS_REMAP_LOW 0xfac
  867. #define PCI_0DAC_P2P_MEM1_BASE_ADDRESS_REMAP_HIGH 0xf30
  868. #define PCI_1DAC_P2P_MEM1_BASE_ADDRESS_REMAP_HIGH 0xfb0
  869. #define PCI_0DAC_CPU_BASE_ADDRESS_REMAP 0xf34
  870. #define PCI_1DAC_CPU_BASE_ADDRESS_REMAP 0xfb4
  871. #define PCI_0EXPANSION_ROM_BASE_ADDRESS_REMAP 0xf38
  872. #define PCI_1EXPANSION_ROM_BASE_ADDRESS_REMAP 0xfb8
  873. #define PCI_0ADDRESS_DECODE_CONTROL 0xd3c
  874. #define PCI_1ADDRESS_DECODE_CONTROL 0xdbc
  875. /****************************************/
  876. /* PCI Control */
  877. /****************************************/
  878. #define PCI_0COMMAND 0xc00
  879. #define PCI_1COMMAND 0xc80
  880. #define PCI_0MODE 0xd00
  881. #define PCI_1MODE 0xd80
  882. #define PCI_0TIMEOUT_RETRY 0xc04
  883. #define PCI_1TIMEOUT_RETRY 0xc84
  884. #define PCI_0READ_BUFFER_DISCARD_TIMER 0xd04
  885. #define PCI_1READ_BUFFER_DISCARD_TIMER 0xd84
  886. #define MSI_0TRIGGER_TIMER 0xc38
  887. #define MSI_1TRIGGER_TIMER 0xcb8
  888. #define PCI_0ARBITER_CONTROL 0x1d00
  889. #define PCI_1ARBITER_CONTROL 0x1d80
  890. /* changing untill here */
  891. #define PCI_0CROSS_BAR_CONTROL_LOW 0x1d08
  892. #define PCI_0CROSS_BAR_CONTROL_HIGH 0x1d0c
  893. #define PCI_0CROSS_BAR_TIMEOUT 0x1d04
  894. #define PCI_0READ_RESPONSE_CROSS_BAR_CONTROL_LOW 0x1d18
  895. #define PCI_0READ_RESPONSE_CROSS_BAR_CONTROL_HIGH 0x1d1c
  896. #define PCI_0SYNC_BARRIER_VIRTUAL_REGISTER 0x1d10
  897. #define PCI_0P2P_CONFIGURATION 0x1d14
  898. #define PCI_0ACCESS_CONTROL_BASE_0_LOW 0x1e00
  899. #define PCI_0ACCESS_CONTROL_BASE_0_HIGH 0x1e04
  900. #define PCI_0ACCESS_CONTROL_TOP_0 0x1e08
  901. #define PCI_0ACCESS_CONTROL_BASE_1_LOW 0x1e10
  902. #define PCI_0ACCESS_CONTROL_BASE_1_HIGH 0x1e14
  903. #define PCI_0ACCESS_CONTROL_TOP_1 0x1e18
  904. #define PCI_0ACCESS_CONTROL_BASE_2_LOW 0x1e20
  905. #define PCI_0ACCESS_CONTROL_BASE_2_HIGH 0x1e24
  906. #define PCI_0ACCESS_CONTROL_TOP_2 0x1e28
  907. #define PCI_0ACCESS_CONTROL_BASE_3_LOW 0x1e30
  908. #define PCI_0ACCESS_CONTROL_BASE_3_HIGH 0x1e34
  909. #define PCI_0ACCESS_CONTROL_TOP_3 0x1e38
  910. #define PCI_0ACCESS_CONTROL_BASE_4_LOW 0x1e40
  911. #define PCI_0ACCESS_CONTROL_BASE_4_HIGH 0x1e44
  912. #define PCI_0ACCESS_CONTROL_TOP_4 0x1e48
  913. #define PCI_0ACCESS_CONTROL_BASE_5_LOW 0x1e50
  914. #define PCI_0ACCESS_CONTROL_BASE_5_HIGH 0x1e54
  915. #define PCI_0ACCESS_CONTROL_TOP_5 0x1e58
  916. #define PCI_0ACCESS_CONTROL_BASE_6_LOW 0x1e60
  917. #define PCI_0ACCESS_CONTROL_BASE_6_HIGH 0x1e64
  918. #define PCI_0ACCESS_CONTROL_TOP_6 0x1e68
  919. #define PCI_0ACCESS_CONTROL_BASE_7_LOW 0x1e70
  920. #define PCI_0ACCESS_CONTROL_BASE_7_HIGH 0x1e74
  921. #define PCI_0ACCESS_CONTROL_TOP_7 0x1e78
  922. #define PCI_1CROSS_BAR_CONTROL_LOW 0x1d88
  923. #define PCI_1CROSS_BAR_CONTROL_HIGH 0x1d8c
  924. #define PCI_1CROSS_BAR_TIMEOUT 0x1d84
  925. #define PCI_1READ_RESPONSE_CROSS_BAR_CONTROL_LOW 0x1d98
  926. #define PCI_1READ_RESPONSE_CROSS_BAR_CONTROL_HIGH 0x1d9c
  927. #define PCI_1SYNC_BARRIER_VIRTUAL_REGISTER 0x1d90
  928. #define PCI_1P2P_CONFIGURATION 0x1d94
  929. #define PCI_1ACCESS_CONTROL_BASE_0_LOW 0x1e80
  930. #define PCI_1ACCESS_CONTROL_BASE_0_HIGH 0x1e84
  931. #define PCI_1ACCESS_CONTROL_TOP_0 0x1e88
  932. #define PCI_1ACCESS_CONTROL_BASE_1_LOW 0x1e90
  933. #define PCI_1ACCESS_CONTROL_BASE_1_HIGH 0x1e94
  934. #define PCI_1ACCESS_CONTROL_TOP_1 0x1e98
  935. #define PCI_1ACCESS_CONTROL_BASE_2_LOW 0x1ea0
  936. #define PCI_1ACCESS_CONTROL_BASE_2_HIGH 0x1ea4
  937. #define PCI_1ACCESS_CONTROL_TOP_2 0x1ea8
  938. #define PCI_1ACCESS_CONTROL_BASE_3_LOW 0x1eb0
  939. #define PCI_1ACCESS_CONTROL_BASE_3_HIGH 0x1eb4
  940. #define PCI_1ACCESS_CONTROL_TOP_3 0x1eb8
  941. #define PCI_1ACCESS_CONTROL_BASE_4_LOW 0x1ec0
  942. #define PCI_1ACCESS_CONTROL_BASE_4_HIGH 0x1ec4
  943. #define PCI_1ACCESS_CONTROL_TOP_4 0x1ec8
  944. #define PCI_1ACCESS_CONTROL_BASE_5_LOW 0x1ed0
  945. #define PCI_1ACCESS_CONTROL_BASE_5_HIGH 0x1ed4
  946. #define PCI_1ACCESS_CONTROL_TOP_5 0x1ed8
  947. #define PCI_1ACCESS_CONTROL_BASE_6_LOW 0x1ee0
  948. #define PCI_1ACCESS_CONTROL_BASE_6_HIGH 0x1ee4
  949. #define PCI_1ACCESS_CONTROL_TOP_6 0x1ee8
  950. #define PCI_1ACCESS_CONTROL_BASE_7_LOW 0x1ef0
  951. #define PCI_1ACCESS_CONTROL_BASE_7_HIGH 0x1ef4
  952. #define PCI_1ACCESS_CONTROL_TOP_7 0x1ef8
  953. /****************************************/
  954. /* PCI Snoop Control */
  955. /****************************************/
  956. #define PCI_0SNOOP_CONTROL_BASE_0_LOW 0x1f00
  957. #define PCI_0SNOOP_CONTROL_BASE_0_HIGH 0x1f04
  958. #define PCI_0SNOOP_CONTROL_TOP_0 0x1f08
  959. #define PCI_0SNOOP_CONTROL_BASE_1_0_LOW 0x1f10
  960. #define PCI_0SNOOP_CONTROL_BASE_1_0_HIGH 0x1f14
  961. #define PCI_0SNOOP_CONTROL_TOP_1 0x1f18
  962. #define PCI_0SNOOP_CONTROL_BASE_2_0_LOW 0x1f20
  963. #define PCI_0SNOOP_CONTROL_BASE_2_0_HIGH 0x1f24
  964. #define PCI_0SNOOP_CONTROL_TOP_2 0x1f28
  965. #define PCI_0SNOOP_CONTROL_BASE_3_0_LOW 0x1f30
  966. #define PCI_0SNOOP_CONTROL_BASE_3_0_HIGH 0x1f34
  967. #define PCI_0SNOOP_CONTROL_TOP_3 0x1f38
  968. #define PCI_1SNOOP_CONTROL_BASE_0_LOW 0x1f80
  969. #define PCI_1SNOOP_CONTROL_BASE_0_HIGH 0x1f84
  970. #define PCI_1SNOOP_CONTROL_TOP_0 0x1f88
  971. #define PCI_1SNOOP_CONTROL_BASE_1_0_LOW 0x1f90
  972. #define PCI_1SNOOP_CONTROL_BASE_1_0_HIGH 0x1f94
  973. #define PCI_1SNOOP_CONTROL_TOP_1 0x1f98
  974. #define PCI_1SNOOP_CONTROL_BASE_2_0_LOW 0x1fa0
  975. #define PCI_1SNOOP_CONTROL_BASE_2_0_HIGH 0x1fa4
  976. #define PCI_1SNOOP_CONTROL_TOP_2 0x1fa8
  977. #define PCI_1SNOOP_CONTROL_BASE_3_0_LOW 0x1fb0
  978. #define PCI_1SNOOP_CONTROL_BASE_3_0_HIGH 0x1fb4
  979. #define PCI_1SNOOP_CONTROL_TOP_3 0x1fb8
  980. /****************************************/
  981. /* PCI Configuration Address */
  982. /****************************************/
  983. #define PCI_0CONFIGURATION_ADDRESS 0xcf8
  984. #define PCI_0CONFIGURATION_DATA_VIRTUAL_REGISTER 0xcfc
  985. #define PCI_1CONFIGURATION_ADDRESS 0xc78
  986. #define PCI_1CONFIGURATION_DATA_VIRTUAL_REGISTER 0xc7c
  987. #define PCI_0INTERRUPT_ACKNOWLEDGE_VIRTUAL_REGISTER 0xc34
  988. #define PCI_1INTERRUPT_ACKNOWLEDGE_VIRTUAL_REGISTER 0xcb4
  989. /****************************************/
  990. /* PCI Error Report */
  991. /****************************************/
  992. #define PCI_0SERR_MASK 0xc28
  993. #define PCI_0ERROR_ADDRESS_LOW 0x1d40
  994. #define PCI_0ERROR_ADDRESS_HIGH 0x1d44
  995. #define PCI_0ERROR_DATA_LOW 0x1d48
  996. #define PCI_0ERROR_DATA_HIGH 0x1d4c
  997. #define PCI_0ERROR_COMMAND 0x1d50
  998. #define PCI_0ERROR_CAUSE 0x1d58
  999. #define PCI_0ERROR_MASK 0x1d5c
  1000. #define PCI_1SERR_MASK 0xca8
  1001. #define PCI_1ERROR_ADDRESS_LOW 0x1dc0
  1002. #define PCI_1ERROR_ADDRESS_HIGH 0x1dc4
  1003. #define PCI_1ERROR_DATA_LOW 0x1dc8
  1004. #define PCI_1ERROR_DATA_HIGH 0x1dcc
  1005. #define PCI_1ERROR_COMMAND 0x1dd0
  1006. #define PCI_1ERROR_CAUSE 0x1dd8
  1007. #define PCI_1ERROR_MASK 0x1ddc
  1008. /****************************************/
  1009. /* Lslave Debug (for internal use) */
  1010. /****************************************/
  1011. #define L_SLAVE_X0_ADDRESS 0x1d20
  1012. #define L_SLAVE_X0_COMMAND_AND_ID 0x1d24
  1013. #define L_SLAVE_X1_ADDRESS 0x1d28
  1014. #define L_SLAVE_X1_COMMAND_AND_ID 0x1d2c
  1015. #define L_SLAVE_WRITE_DATA_LOW 0x1d30
  1016. #define L_SLAVE_WRITE_DATA_HIGH 0x1d34
  1017. #define L_SLAVE_WRITE_BYTE_ENABLE 0x1d60
  1018. #define L_SLAVE_READ_DATA_LOW 0x1d38
  1019. #define L_SLAVE_READ_DATA_HIGH 0x1d3c
  1020. #define L_SLAVE_READ_ID 0x1d64
  1021. /****************************************/
  1022. /* PCI Configuration Function 0 */
  1023. /****************************************/
  1024. #define PCI_DEVICE_AND_VENDOR_ID 0x000
  1025. #define PCI_STATUS_AND_COMMAND 0x004
  1026. #define PCI_CLASS_CODE_AND_REVISION_ID 0x008
  1027. #define PCI_BIST_HEADER_TYPE_LATENCY_TIMER_CACHE_LINE 0x00C
  1028. #define PCI_SCS_0_BASE_ADDRESS 0x010
  1029. #define PCI_SCS_1_BASE_ADDRESS 0x014
  1030. #define PCI_SCS_2_BASE_ADDRESS 0x018
  1031. #define PCI_SCS_3_BASE_ADDRESS 0x01C
  1032. #define PCI_INTERNAL_REGISTERS_MEMORY_MAPPED_BASE_ADDRESS 0x020
  1033. #define PCI_INTERNAL_REGISTERS_I_OMAPPED_BASE_ADDRESS 0x024
  1034. #define PCI_SUBSYSTEM_ID_AND_SUBSYSTEM_VENDOR_ID 0x02C
  1035. #define PCI_EXPANSION_ROM_BASE_ADDRESS_REGISTER 0x030
  1036. #define PCI_CAPABILTY_LIST_POINTER 0x034
  1037. #define PCI_INTERRUPT_PIN_AND_LINE 0x03C
  1038. #define PCI_POWER_MANAGEMENT_CAPABILITY 0x040
  1039. #define PCI_POWER_MANAGEMENT_STATUS_AND_CONTROL 0x044
  1040. #define PCI_VPD_ADDRESS 0x048
  1041. #define PCI_VPD_DATA 0x04c
  1042. #define PCI_MSI_MESSAGE_CONTROL 0x050
  1043. #define PCI_MSI_MESSAGE_ADDRESS 0x054
  1044. #define PCI_MSI_MESSAGE_UPPER_ADDRESS 0x058
  1045. #define PCI_MSI_MESSAGE_DATA 0x05c
  1046. #define PCI_COMPACT_PCI_HOT_SWAP_CAPABILITY 0x058
  1047. /****************************************/
  1048. /* PCI Configuration Function 1 */
  1049. /****************************************/
  1050. #define PCI_CS_0_BASE_ADDRESS 0x110
  1051. #define PCI_CS_1_BASE_ADDRESS 0x114
  1052. #define PCI_CS_2_BASE_ADDRESS 0x118
  1053. #define PCI_CS_3_BASE_ADDRESS 0x11c
  1054. #define PCI_BOOTCS_BASE_ADDRESS 0x120
  1055. /****************************************/
  1056. /* PCI Configuration Function 2 */
  1057. /****************************************/
  1058. #define PCI_P2P_MEM0_BASE_ADDRESS 0x210
  1059. /*#define PCI_P2P_MEM1_BASE_ADDRESS 0x2141 */
  1060. #define PCI_P2P_I_O_BASE_ADDRESS 0x218
  1061. /*#define PCI_CPU_BASE_ADDRESS 0x21c1 */
  1062. /****************************************/
  1063. /* PCI Configuration Function 4 */
  1064. /****************************************/
  1065. #define PCI_DAC_SCS_0_BASE_ADDRESS_LOW 0x410
  1066. #define PCI_DAC_SCS_0_BASE_ADDRESS_HIGH 0x414
  1067. #define PCI_DAC_SCS_1_BASE_ADDRESS_LOW 0x418
  1068. #define PCI_DAC_SCS_1_BASE_ADDRESS_HIGH 0x41c
  1069. #define PCI_DAC_P2P_MEM0_BASE_ADDRESS_LOW 0x420
  1070. #define PCI_DAC_P2P_MEM0_BASE_ADDRESS_HIGH 0x424
  1071. /****************************************/
  1072. /* PCI Configuration Function 5 */
  1073. /****************************************/
  1074. #define PCI_DAC_SCS_2_BASE_ADDRESS_LOW 0x510
  1075. #define PCI_DAC_SCS_2_BASE_ADDRESS_HIGH 0x514
  1076. #define PCI_DAC_SCS_3_BASE_ADDRESS_LOW 0x518
  1077. #define PCI_DAC_SCS_3_BASE_ADDRESS_HIGH 0x51c
  1078. #define PCI_DAC_P2P_MEM1_BASE_ADDRESS_LOW 0x520
  1079. #define PCI_DAC_P2P_MEM1_BASE_ADDRESS_HIGH 0x524
  1080. /****************************************/
  1081. /* PCI Configuration Function 6 */
  1082. /****************************************/
  1083. #define PCI_DAC_CS_0_BASE_ADDRESS_LOW 0x610
  1084. #define PCI_DAC_CS_0_BASE_ADDRESS_HIGH 0x614
  1085. #define PCI_DAC_CS_1_BASE_ADDRESS_LOW 0x618
  1086. #define PCI_DAC_CS_1_BASE_ADDRESS_HIGH 0x61c
  1087. #define PCI_DAC_CS_2_BASE_ADDRESS_LOW 0x620
  1088. #define PCI_DAC_CS_2_BASE_ADDRESS_HIGH 0x624
  1089. /****************************************/
  1090. /* PCI Configuration Function 7 */
  1091. /****************************************/
  1092. #define PCI_DAC_CS_3_BASE_ADDRESS_LOW 0x710
  1093. #define PCI_DAC_CS_3_BASE_ADDRESS_HIGH 0x714
  1094. #define PCI_DAC_BOOTCS_BASE_ADDRESS_LOW 0x718
  1095. #define PCI_DAC_BOOTCS_BASE_ADDRESS_HIGH 0x71c
  1096. #define PCI_DAC_CPU_BASE_ADDRESS_LOW 0x720
  1097. #define PCI_DAC_CPU_BASE_ADDRESS_HIGH 0x724
  1098. /****************************** MV64360 and MV64460 PCI ***************************/
  1099. /***********************************/
  1100. /* PCI Control Register Map */
  1101. /***********************************/
  1102. #define PCI_0_DLL_STATUS_AND_COMMAND 0x1d20
  1103. #define PCI_1_DLL_STATUS_AND_COMMAND 0x1da0
  1104. #define PCI_0_MPP_PADS_DRIVE_CONTROL 0x1d1C
  1105. #define PCI_1_MPP_PADS_DRIVE_CONTROL 0x1d9C
  1106. #define PCI_0_COMMAND 0xc00
  1107. #define PCI_1_COMMAND 0xc80
  1108. #define PCI_0_MODE 0xd00
  1109. #define PCI_1_MODE 0xd80
  1110. #define PCI_0_RETRY 0xc04
  1111. #define PCI_1_RETRY 0xc84
  1112. #define PCI_0_READ_BUFFER_DISCARD_TIMER 0xd04
  1113. #define PCI_1_READ_BUFFER_DISCARD_TIMER 0xd84
  1114. #define PCI_0_MSI_TRIGGER_TIMER 0xc38
  1115. #define PCI_1_MSI_TRIGGER_TIMER 0xcb8
  1116. #define PCI_0_ARBITER_CONTROL 0x1d00
  1117. #define PCI_1_ARBITER_CONTROL 0x1d80
  1118. #define PCI_0_CROSS_BAR_CONTROL_LOW 0x1d08
  1119. #define PCI_1_CROSS_BAR_CONTROL_LOW 0x1d88
  1120. #define PCI_0_CROSS_BAR_CONTROL_HIGH 0x1d0c
  1121. #define PCI_1_CROSS_BAR_CONTROL_HIGH 0x1d8c
  1122. #define PCI_0_CROSS_BAR_TIMEOUT 0x1d04
  1123. #define PCI_1_CROSS_BAR_TIMEOUT 0x1d84
  1124. #define PCI_0_SYNC_BARRIER_TRIGGER_REG 0x1D18
  1125. #define PCI_1_SYNC_BARRIER_TRIGGER_REG 0x1D98
  1126. #define PCI_0_SYNC_BARRIER_VIRTUAL_REG 0x1d10
  1127. #define PCI_1_SYNC_BARRIER_VIRTUAL_REG 0x1d90
  1128. #define PCI_0_P2P_CONFIG 0x1d14
  1129. #define PCI_1_P2P_CONFIG 0x1d94
  1130. #define PCI_0_ACCESS_CONTROL_BASE_0_LOW 0x1e00
  1131. #define PCI_0_ACCESS_CONTROL_BASE_0_HIGH 0x1e04
  1132. #define PCI_0_ACCESS_CONTROL_SIZE_0 0x1e08
  1133. #define PCI_0_ACCESS_CONTROL_BASE_1_LOW 0x1e10
  1134. #define PCI_0_ACCESS_CONTROL_BASE_1_HIGH 0x1e14
  1135. #define PCI_0_ACCESS_CONTROL_SIZE_1 0x1e18
  1136. #define PCI_0_ACCESS_CONTROL_BASE_2_LOW 0x1e20
  1137. #define PCI_0_ACCESS_CONTROL_BASE_2_HIGH 0x1e24
  1138. #define PCI_0_ACCESS_CONTROL_SIZE_2 0x1e28
  1139. #define PCI_0_ACCESS_CONTROL_BASE_3_LOW 0x1e30
  1140. #define PCI_0_ACCESS_CONTROL_BASE_3_HIGH 0x1e34
  1141. #define PCI_0_ACCESS_CONTROL_SIZE_3 0x1e38
  1142. #define PCI_0_ACCESS_CONTROL_BASE_4_LOW 0x1e40
  1143. #define PCI_0_ACCESS_CONTROL_BASE_4_HIGH 0x1e44
  1144. #define PCI_0_ACCESS_CONTROL_SIZE_4 0x1e48
  1145. #define PCI_0_ACCESS_CONTROL_BASE_5_LOW 0x1e50
  1146. #define PCI_0_ACCESS_CONTROL_BASE_5_HIGH 0x1e54
  1147. #define PCI_0_ACCESS_CONTROL_SIZE_5 0x1e58
  1148. #define PCI_1_ACCESS_CONTROL_BASE_0_LOW 0x1e80
  1149. #define PCI_1_ACCESS_CONTROL_BASE_0_HIGH 0x1e84
  1150. #define PCI_1_ACCESS_CONTROL_SIZE_0 0x1e88
  1151. #define PCI_1_ACCESS_CONTROL_BASE_1_LOW 0x1e90
  1152. #define PCI_1_ACCESS_CONTROL_BASE_1_HIGH 0x1e94
  1153. #define PCI_1_ACCESS_CONTROL_SIZE_1 0x1e98
  1154. #define PCI_1_ACCESS_CONTROL_BASE_2_LOW 0x1ea0
  1155. #define PCI_1_ACCESS_CONTROL_BASE_2_HIGH 0x1ea4
  1156. #define PCI_1_ACCESS_CONTROL_SIZE_2 0x1ea8
  1157. #define PCI_1_ACCESS_CONTROL_BASE_3_LOW 0x1eb0
  1158. #define PCI_1_ACCESS_CONTROL_BASE_3_HIGH 0x1eb4
  1159. #define PCI_1_ACCESS_CONTROL_SIZE_3 0x1eb8
  1160. #define PCI_1_ACCESS_CONTROL_BASE_4_LOW 0x1ec0
  1161. #define PCI_1_ACCESS_CONTROL_BASE_4_HIGH 0x1ec4
  1162. #define PCI_1_ACCESS_CONTROL_SIZE_4 0x1ec8
  1163. #define PCI_1_ACCESS_CONTROL_BASE_5_LOW 0x1ed0
  1164. #define PCI_1_ACCESS_CONTROL_BASE_5_HIGH 0x1ed4
  1165. #define PCI_1_ACCESS_CONTROL_SIZE_5 0x1ed8
  1166. /****************************************/
  1167. /* PCI Configuration Access Registers */
  1168. /****************************************/
  1169. #define PCI_0_CONFIG_ADDR 0xcf8
  1170. #define PCI_0_CONFIG_DATA_VIRTUAL_REG 0xcfc
  1171. #define PCI_1_CONFIG_ADDR 0xc78
  1172. #define PCI_1_CONFIG_DATA_VIRTUAL_REG 0xc7c
  1173. #define PCI_0_INTERRUPT_ACKNOWLEDGE_VIRTUAL_REG 0xc34
  1174. #define PCI_1_INTERRUPT_ACKNOWLEDGE_VIRTUAL_REG 0xcb4
  1175. /****************************************/
  1176. /* PCI Error Report Registers */
  1177. /****************************************/
  1178. #define PCI_0_SERR_MASK 0xc28
  1179. #define PCI_1_SERR_MASK 0xca8
  1180. #define PCI_0_ERROR_ADDR_LOW 0x1d40
  1181. #define PCI_1_ERROR_ADDR_LOW 0x1dc0
  1182. #define PCI_0_ERROR_ADDR_HIGH 0x1d44
  1183. #define PCI_1_ERROR_ADDR_HIGH 0x1dc4
  1184. #define PCI_0_ERROR_ATTRIBUTE 0x1d48
  1185. #define PCI_1_ERROR_ATTRIBUTE 0x1dc8
  1186. #define PCI_0_ERROR_COMMAND 0x1d50
  1187. #define PCI_1_ERROR_COMMAND 0x1dd0
  1188. #define PCI_0_ERROR_CAUSE 0x1d58
  1189. #define PCI_1_ERROR_CAUSE 0x1dd8
  1190. #define PCI_0_ERROR_MASK 0x1d5c
  1191. #define PCI_1_ERROR_MASK 0x1ddc
  1192. /****************************************/
  1193. /* PCI Debug Registers */
  1194. /****************************************/
  1195. #define PCI_0_MMASK 0X1D24
  1196. #define PCI_1_MMASK 0X1DA4
  1197. /*********************************************/
  1198. /* PCI Configuration, Function 0, Registers */
  1199. /*********************************************/
  1200. #define PCI_DEVICE_AND_VENDOR_ID 0x000
  1201. #define PCI_STATUS_AND_COMMAND 0x004
  1202. #define PCI_CLASS_CODE_AND_REVISION_ID 0x008
  1203. #define PCI_BIST_HEADER_TYPE_LATENCY_TIMER_CACHE_LINE 0x00C
  1204. #define PCI_SCS_0_BASE_ADDR_LOW 0x010
  1205. #define PCI_SCS_0_BASE_ADDR_HIGH 0x014
  1206. #define PCI_SCS_1_BASE_ADDR_LOW 0x018
  1207. #define PCI_SCS_1_BASE_ADDR_HIGH 0x01C
  1208. #define PCI_INTERNAL_REG_MEM_MAPPED_BASE_ADDR_LOW 0x020
  1209. #define PCI_INTERNAL_REG_MEM_MAPPED_BASE_ADDR_HIGH 0x024
  1210. /*#define PCI_SUBSYSTEM_ID_AND_SUBSYSTEM_VENDOR_ID 0x02c1 */
  1211. #define PCI_EXPANSION_ROM_BASE_ADDR_REG 0x030
  1212. #define PCI_CAPABILTY_LIST_POINTER 0x034
  1213. #define PCI_INTERRUPT_PIN_AND_LINE 0x03C
  1214. /* capability list */
  1215. #define PCI_POWER_MANAGEMENT_CAPABILITY 0x040
  1216. #define PCI_POWER_MANAGEMENT_STATUS_AND_CONTROL 0x044
  1217. #define PCI_VPD_ADDR 0x048
  1218. #define PCI_VPD_DATA 0x04c
  1219. #define PCI_MSI_MESSAGE_CONTROL 0x050
  1220. #define PCI_MSI_MESSAGE_ADDR 0x054
  1221. #define PCI_MSI_MESSAGE_UPPER_ADDR 0x058
  1222. #define PCI_MSI_MESSAGE_DATA 0x05c
  1223. #define PCI_X_COMMAND 0x060
  1224. #define PCI_X_STATUS 0x064
  1225. #define PCI_COMPACT_PCI_HOT_SWAP 0x068
  1226. /***********************************************/
  1227. /* PCI Configuration, Function 1, Registers */
  1228. /***********************************************/
  1229. #define PCI_SCS_2_BASE_ADDR_LOW 0x110
  1230. #define PCI_SCS_2_BASE_ADDR_HIGH 0x114
  1231. #define PCI_SCS_3_BASE_ADDR_LOW 0x118
  1232. #define PCI_SCS_3_BASE_ADDR_HIGH 0x11c
  1233. #define PCI_INTERNAL_SRAM_BASE_ADDR_LOW 0x120
  1234. #define PCI_INTERNAL_SRAM_BASE_ADDR_HIGH 0x124
  1235. /***********************************************/
  1236. /* PCI Configuration, Function 2, Registers */
  1237. /***********************************************/
  1238. #define PCI_DEVCS_0_BASE_ADDR_LOW 0x210
  1239. #define PCI_DEVCS_0_BASE_ADDR_HIGH 0x214
  1240. #define PCI_DEVCS_1_BASE_ADDR_LOW 0x218
  1241. #define PCI_DEVCS_1_BASE_ADDR_HIGH 0x21c
  1242. #define PCI_DEVCS_2_BASE_ADDR_LOW 0x220
  1243. #define PCI_DEVCS_2_BASE_ADDR_HIGH 0x224
  1244. /***********************************************/
  1245. /* PCI Configuration, Function 3, Registers */
  1246. /***********************************************/
  1247. #define PCI_DEVCS_3_BASE_ADDR_LOW 0x310
  1248. #define PCI_DEVCS_3_BASE_ADDR_HIGH 0x314
  1249. #define PCI_BOOT_CS_BASE_ADDR_LOW 0x318
  1250. #define PCI_BOOT_CS_BASE_ADDR_HIGH 0x31c
  1251. #define PCI_CPU_BASE_ADDR_LOW 0x220
  1252. #define PCI_CPU_BASE_ADDR_HIGH 0x224
  1253. /***********************************************/
  1254. /* PCI Configuration, Function 4, Registers */
  1255. /***********************************************/
  1256. #define PCI_P2P_MEM0_BASE_ADDR_LOW 0x410
  1257. #define PCI_P2P_MEM0_BASE_ADDR_HIGH 0x414
  1258. #define PCI_P2P_MEM1_BASE_ADDR_LOW 0x418
  1259. #define PCI_P2P_MEM1_BASE_ADDR_HIGH 0x41c
  1260. #define PCI_P2P_I_O_BASE_ADDR 0x420
  1261. #define PCI_INTERNAL_REGS_I_O_MAPPED_BASE_ADDR 0x424
  1262. /****************************** MV64360 and MV64460 PCI End ***************************/
  1263. /****************************************/
  1264. /* I20 Support registers */
  1265. /****************************************/
  1266. #define INBOUND_MESSAGE_REGISTER0_PCI_SIDE 0x010
  1267. #define INBOUND_MESSAGE_REGISTER1_PCI_SIDE 0x014
  1268. #define OUTBOUND_MESSAGE_REGISTER0_PCI_SIDE 0x018
  1269. #define OUTBOUND_MESSAGE_REGISTER1_PCI_SIDE 0x01C
  1270. #define INBOUND_DOORBELL_REGISTER_PCI_SIDE 0x020
  1271. #define INBOUND_INTERRUPT_CAUSE_REGISTER_PCI_SIDE 0x024
  1272. #define INBOUND_INTERRUPT_MASK_REGISTER_PCI_SIDE 0x028
  1273. #define OUTBOUND_DOORBELL_REGISTER_PCI_SIDE 0x02C
  1274. #define OUTBOUND_INTERRUPT_CAUSE_REGISTER_PCI_SIDE 0x030
  1275. #define OUTBOUND_INTERRUPT_MASK_REGISTER_PCI_SIDE 0x034
  1276. #define INBOUND_QUEUE_PORT_VIRTUAL_REGISTER_PCI_SIDE 0x040
  1277. #define OUTBOUND_QUEUE_PORT_VIRTUAL_REGISTER_PCI_SIDE 0x044
  1278. #define QUEUE_CONTROL_REGISTER_PCI_SIDE 0x050
  1279. #define QUEUE_BASE_ADDRESS_REGISTER_PCI_SIDE 0x054
  1280. #define INBOUND_FREE_HEAD_POINTER_REGISTER_PCI_SIDE 0x060
  1281. #define INBOUND_FREE_TAIL_POINTER_REGISTER_PCI_SIDE 0x064
  1282. #define INBOUND_POST_HEAD_POINTER_REGISTER_PCI_SIDE 0x068
  1283. #define INBOUND_POST_TAIL_POINTER_REGISTER_PCI_SIDE 0x06C
  1284. #define OUTBOUND_FREE_HEAD_POINTER_REGISTER_PCI_SIDE 0x070
  1285. #define OUTBOUND_FREE_TAIL_POINTER_REGISTER_PCI_SIDE 0x074
  1286. #define OUTBOUND_POST_HEAD_POINTER_REGISTER_PCI_SIDE 0x078
  1287. #define OUTBOUND_POST_TAIL_POINTER_REGISTER_PCI_SIDE 0x07C
  1288. #define INBOUND_MESSAGE_REGISTER0_CPU_SIDE 0x1C10
  1289. #define INBOUND_MESSAGE_REGISTER1_CPU_SIDE 0x1C14
  1290. #define OUTBOUND_MESSAGE_REGISTER0_CPU_SIDE 0x1C18
  1291. #define OUTBOUND_MESSAGE_REGISTER1_CPU_SIDE 0x1C1C
  1292. #define INBOUND_DOORBELL_REGISTER_CPU_SIDE 0x1C20
  1293. #define INBOUND_INTERRUPT_CAUSE_REGISTER_CPU_SIDE 0x1C24
  1294. #define INBOUND_INTERRUPT_MASK_REGISTER_CPU_SIDE 0x1C28
  1295. #define OUTBOUND_DOORBELL_REGISTER_CPU_SIDE 0x1C2C
  1296. #define OUTBOUND_INTERRUPT_CAUSE_REGISTER_CPU_SIDE 0x1C30
  1297. #define OUTBOUND_INTERRUPT_MASK_REGISTER_CPU_SIDE 0x1C34
  1298. #define INBOUND_QUEUE_PORT_VIRTUAL_REGISTER_CPU_SIDE 0x1C40
  1299. #define OUTBOUND_QUEUE_PORT_VIRTUAL_REGISTER_CPU_SIDE 0x1C44
  1300. #define QUEUE_CONTROL_REGISTER_CPU_SIDE 0x1C50
  1301. #define QUEUE_BASE_ADDRESS_REGISTER_CPU_SIDE 0x1C54
  1302. #define INBOUND_FREE_HEAD_POINTER_REGISTER_CPU_SIDE 0x1C60
  1303. #define INBOUND_FREE_TAIL_POINTER_REGISTER_CPU_SIDE 0x1C64
  1304. #define INBOUND_POST_HEAD_POINTER_REGISTER_CPU_SIDE 0x1C68
  1305. #define INBOUND_POST_TAIL_POINTER_REGISTER_CPU_SIDE 0x1C6C
  1306. #define OUTBOUND_FREE_HEAD_POINTER_REGISTER_CPU_SIDE 0x1C70
  1307. #define OUTBOUND_FREE_TAIL_POINTER_REGISTER_CPU_SIDE 0x1C74
  1308. #define OUTBOUND_POST_HEAD_POINTER_REGISTER_CPU_SIDE 0x1C78
  1309. #define OUTBOUND_POST_TAIL_POINTER_REGISTER_CPU_SIDE 0x1C7C
  1310. /****************************************/
  1311. /* Messaging Unit Registers (I20) */
  1312. /****************************************/
  1313. #define I2O_INBOUND_MESSAGE_REG0_PCI_0_SIDE 0x010
  1314. #define I2O_INBOUND_MESSAGE_REG1_PCI_0_SIDE 0x014
  1315. #define I2O_OUTBOUND_MESSAGE_REG0_PCI_0_SIDE 0x018
  1316. #define I2O_OUTBOUND_MESSAGE_REG1_PCI_0_SIDE 0x01C
  1317. #define I2O_INBOUND_DOORBELL_REG_PCI_0_SIDE 0x020
  1318. #define I2O_INBOUND_INTERRUPT_CAUSE_REG_PCI_0_SIDE 0x024
  1319. #define I2O_INBOUND_INTERRUPT_MASK_REG_PCI_0_SIDE 0x028
  1320. #define I2O_OUTBOUND_DOORBELL_REG_PCI_0_SIDE 0x02C
  1321. #define I2O_OUTBOUND_INTERRUPT_CAUSE_REG_PCI_0_SIDE 0x030
  1322. #define I2O_OUTBOUND_INTERRUPT_MASK_REG_PCI_0_SIDE 0x034
  1323. #define I2O_INBOUND_QUEUE_PORT_VIRTUAL_REG_PCI_0_SIDE 0x040
  1324. #define I2O_OUTBOUND_QUEUE_PORT_VIRTUAL_REG_PCI_0_SIDE 0x044
  1325. #define I2O_QUEUE_CONTROL_REG_PCI_0_SIDE 0x050
  1326. #define I2O_QUEUE_BASE_ADDR_REG_PCI_0_SIDE 0x054
  1327. #define I2O_INBOUND_FREE_HEAD_POINTER_REG_PCI_0_SIDE 0x060
  1328. #define I2O_INBOUND_FREE_TAIL_POINTER_REG_PCI_0_SIDE 0x064
  1329. #define I2O_INBOUND_POST_HEAD_POINTER_REG_PCI_0_SIDE 0x068
  1330. #define I2O_INBOUND_POST_TAIL_POINTER_REG_PCI_0_SIDE 0x06C
  1331. #define I2O_OUTBOUND_FREE_HEAD_POINTER_REG_PCI_0_SIDE 0x070
  1332. #define I2O_OUTBOUND_FREE_TAIL_POINTER_REG_PCI_0_SIDE 0x074
  1333. #define I2O_OUTBOUND_POST_HEAD_POINTER_REG_PCI_0_SIDE 0x0F8
  1334. #define I2O_OUTBOUND_POST_TAIL_POINTER_REG_PCI_0_SIDE 0x0FC
  1335. #define I2O_INBOUND_MESSAGE_REG0_PCI_1_SIDE 0x090
  1336. #define I2O_INBOUND_MESSAGE_REG1_PCI_1_SIDE 0x094
  1337. #define I2O_OUTBOUND_MESSAGE_REG0_PCI_1_SIDE 0x098
  1338. #define I2O_OUTBOUND_MESSAGE_REG1_PCI_1_SIDE 0x09C
  1339. #define I2O_INBOUND_DOORBELL_REG_PCI_1_SIDE 0x0A0
  1340. #define I2O_INBOUND_INTERRUPT_CAUSE_REG_PCI_1_SIDE 0x0A4
  1341. #define I2O_INBOUND_INTERRUPT_MASK_REG_PCI_1_SIDE 0x0A8
  1342. #define I2O_OUTBOUND_DOORBELL_REG_PCI_1_SIDE 0x0AC
  1343. #define I2O_OUTBOUND_INTERRUPT_CAUSE_REG_PCI_1_SIDE 0x0B0
  1344. #define I2O_OUTBOUND_INTERRUPT_MASK_REG_PCI_1_SIDE 0x0B4
  1345. #define I2O_INBOUND_QUEUE_PORT_VIRTUAL_REG_PCI_1_SIDE 0x0C0
  1346. #define I2O_OUTBOUND_QUEUE_PORT_VIRTUAL_REG_PCI_1_SIDE 0x0C4
  1347. #define I2O_QUEUE_CONTROL_REG_PCI_1_SIDE 0x0D0
  1348. #define I2O_QUEUE_BASE_ADDR_REG_PCI_1_SIDE 0x0D4
  1349. #define I2O_INBOUND_FREE_HEAD_POINTER_REG_PCI_1_SIDE 0x0E0
  1350. #define I2O_INBOUND_FREE_TAIL_POINTER_REG_PCI_1_SIDE 0x0E4
  1351. #define I2O_INBOUND_POST_HEAD_POINTER_REG_PCI_1_SIDE 0x0E8
  1352. #define I2O_INBOUND_POST_TAIL_POINTER_REG_PCI_1_SIDE 0x0EC
  1353. #define I2O_OUTBOUND_FREE_HEAD_POINTER_REG_PCI_1_SIDE 0x0F0
  1354. #define I2O_OUTBOUND_FREE_TAIL_POINTER_REG_PCI_1_SIDE 0x0F4
  1355. #define I2O_OUTBOUND_POST_HEAD_POINTER_REG_PCI_1_SIDE 0x078
  1356. #define I2O_OUTBOUND_POST_TAIL_POINTER_REG_PCI_1_SIDE 0x07C
  1357. #define I2O_INBOUND_MESSAGE_REG0_CPU0_SIDE 0x1C10
  1358. #define I2O_INBOUND_MESSAGE_REG1_CPU0_SIDE 0x1C14
  1359. #define I2O_OUTBOUND_MESSAGE_REG0_CPU0_SIDE 0x1C18
  1360. #define I2O_OUTBOUND_MESSAGE_REG1_CPU0_SIDE 0x1C1C
  1361. #define I2O_INBOUND_DOORBELL_REG_CPU0_SIDE 0x1C20
  1362. #define I2O_INBOUND_INTERRUPT_CAUSE_REG_CPU0_SIDE 0x1C24
  1363. #define I2O_INBOUND_INTERRUPT_MASK_REG_CPU0_SIDE 0x1C28
  1364. #define I2O_OUTBOUND_DOORBELL_REG_CPU0_SIDE 0x1C2C
  1365. #define I2O_OUTBOUND_INTERRUPT_CAUSE_REG_CPU0_SIDE 0x1C30
  1366. #define I2O_OUTBOUND_INTERRUPT_MASK_REG_CPU0_SIDE 0x1C34
  1367. #define I2O_INBOUND_QUEUE_PORT_VIRTUAL_REG_CPU0_SIDE 0x1C40
  1368. #define I2O_OUTBOUND_QUEUE_PORT_VIRTUAL_REG_CPU0_SIDE 0x1C44
  1369. #define I2O_QUEUE_CONTROL_REG_CPU0_SIDE 0x1C50
  1370. #define I2O_QUEUE_BASE_ADDR_REG_CPU0_SIDE 0x1C54
  1371. #define I2O_INBOUND_FREE_HEAD_POINTER_REG_CPU0_SIDE 0x1C60
  1372. #define I2O_INBOUND_FREE_TAIL_POINTER_REG_CPU0_SIDE 0x1C64
  1373. #define I2O_INBOUND_POST_HEAD_POINTER_REG_CPU0_SIDE 0x1C68
  1374. #define I2O_INBOUND_POST_TAIL_POINTER_REG_CPU0_SIDE 0x1C6C
  1375. #define I2O_OUTBOUND_FREE_HEAD_POINTER_REG_CPU0_SIDE 0x1C70
  1376. #define I2O_OUTBOUND_FREE_TAIL_POINTER_REG_CPU0_SIDE 0x1C74
  1377. #define I2O_OUTBOUND_POST_HEAD_POINTER_REG_CPU0_SIDE 0x1CF8
  1378. #define I2O_OUTBOUND_POST_TAIL_POINTER_REG_CPU0_SIDE 0x1CFC
  1379. #define I2O_INBOUND_MESSAGE_REG0_CPU1_SIDE 0x1C90
  1380. #define I2O_INBOUND_MESSAGE_REG1_CPU1_SIDE 0x1C94
  1381. #define I2O_OUTBOUND_MESSAGE_REG0_CPU1_SIDE 0x1C98
  1382. #define I2O_OUTBOUND_MESSAGE_REG1_CPU1_SIDE 0x1C9C
  1383. #define I2O_INBOUND_DOORBELL_REG_CPU1_SIDE 0x1CA0
  1384. #define I2O_INBOUND_INTERRUPT_CAUSE_REG_CPU1_SIDE 0x1CA4
  1385. #define I2O_INBOUND_INTERRUPT_MASK_REG_CPU1_SIDE 0x1CA8
  1386. #define I2O_OUTBOUND_DOORBELL_REG_CPU1_SIDE 0x1CAC
  1387. #define I2O_OUTBOUND_INTERRUPT_CAUSE_REG_CPU1_SIDE 0x1CB0
  1388. #define I2O_OUTBOUND_INTERRUPT_MASK_REG_CPU1_SIDE 0x1CB4
  1389. #define I2O_INBOUND_QUEUE_PORT_VIRTUAL_REG_CPU1_SIDE 0x1CC0
  1390. #define I2O_OUTBOUND_QUEUE_PORT_VIRTUAL_REG_CPU1_SIDE 0x1CC4
  1391. #define I2O_QUEUE_CONTROL_REG_CPU1_SIDE 0x1CD0
  1392. #define I2O_QUEUE_BASE_ADDR_REG_CPU1_SIDE 0x1CD4
  1393. #define I2O_INBOUND_FREE_HEAD_POINTER_REG_CPU1_SIDE 0x1CE0
  1394. #define I2O_INBOUND_FREE_TAIL_POINTER_REG_CPU1_SIDE 0x1CE4
  1395. #define I2O_INBOUND_POST_HEAD_POINTER_REG_CPU1_SIDE 0x1CE8
  1396. #define I2O_INBOUND_POST_TAIL_POINTER_REG_CPU1_SIDE 0x1CEC
  1397. #define I2O_OUTBOUND_FREE_HEAD_POINTER_REG_CPU1_SIDE 0x1CF0
  1398. #define I2O_OUTBOUND_FREE_TAIL_POINTER_REG_CPU1_SIDE 0x1CF4
  1399. #define I2O_OUTBOUND_POST_HEAD_POINTER_REG_CPU1_SIDE 0x1C78
  1400. #define I2O_OUTBOUND_POST_TAIL_POINTER_REG_CPU1_SIDE 0x1C7C
  1401. /****************************************/
  1402. /* Communication Unit Registers */
  1403. /****************************************/
  1404. /*
  1405. #define ETHERNET_0_ADDRESS_CONTROL_LOW 0xf200
  1406. #define ETHERNET_0_ADDRESS_CONTROL_HIGH 0xf204
  1407. #define ETHERNET_0_RECEIVE_BUFFER_PCI_HIGH_ADDRESS 0xf208
  1408. #define ETHERNET_0_TRANSMIT_BUFFER_PCI_HIGH_ADDRESS 0xf20c
  1409. #define ETHERNET_0_RECEIVE_DESCRIPTOR_PCI_HIGH_ADDRESS 0xf210
  1410. #define ETHERNET_0_TRANSMIT_DESCRIPTOR_PCI_HIGH_ADDRESS 0xf214
  1411. #define ETHERNET_0_HASH_TABLE_PCI_HIGH_ADDRESS 0xf218
  1412. #define ETHERNET_1_ADDRESS_CONTROL_LOW 0xf220
  1413. #define ETHERNET_1_ADDRESS_CONTROL_HIGH 0xf224
  1414. #define ETHERNET_1_RECEIVE_BUFFER_PCI_HIGH_ADDRESS 0xf228
  1415. #define ETHERNET_1_TRANSMIT_BUFFER_PCI_HIGH_ADDRESS 0xf22c
  1416. #define ETHERNET_1_RECEIVE_DESCRIPTOR_PCI_HIGH_ADDRESS 0xf230
  1417. #define ETHERNET_1_TRANSMIT_DESCRIPTOR_PCI_HIGH_ADDRESS 0xf234
  1418. #define ETHERNET_1_HASH_TABLE_PCI_HIGH_ADDRESS 0xf238
  1419. #define ETHERNET_2_ADDRESS_CONTROL_LOW 0xf240
  1420. #define ETHERNET_2_ADDRESS_CONTROL_HIGH 0xf244
  1421. #define ETHERNET_2_RECEIVE_BUFFER_PCI_HIGH_ADDRESS 0xf248
  1422. #define ETHERNET_2_TRANSMIT_BUFFER_PCI_HIGH_ADDRESS 0xf24c
  1423. #define ETHERNET_2_RECEIVE_DESCRIPTOR_PCI_HIGH_ADDRESS 0xf250
  1424. #define ETHERNET_2_TRANSMIT_DESCRIPTOR_PCI_HIGH_ADDRESS 0xf254
  1425. #define ETHERNET_2_HASH_TABLE_PCI_HIGH_ADDRESS 0xf258
  1426. */
  1427. #define MPSC_0_ADDRESS_CONTROL_LOW 0xf280
  1428. #define MPSC_0_ADDRESS_CONTROL_HIGH 0xf284
  1429. #define MPSC_0_RECEIVE_BUFFER_PCI_HIGH_ADDRESS 0xf288
  1430. #define MPSC_0_TRANSMIT_BUFFER_PCI_HIGH_ADDRESS 0xf28c
  1431. #define MPSC_0_RECEIVE_DESCRIPTOR_PCI_HIGH_ADDRESS 0xf290
  1432. #define MPSC_0_TRANSMIT_DESCRIPTOR_PCI_HIGH_ADDRESS 0xf294
  1433. #define MPSC_1_ADDRESS_CONTROL_LOW 0xf2c0
  1434. #define MPSC_1_ADDRESS_CONTROL_HIGH 0xf2c4
  1435. #define MPSC_1_RECEIVE_BUFFER_PCI_HIGH_ADDRESS 0xf2c8
  1436. #define MPSC_1_TRANSMIT_BUFFER_PCI_HIGH_ADDRESS 0xf2cc
  1437. #define MPSC_1_RECEIVE_DESCRIPTOR_PCI_HIGH_ADDRESS 0xf2d0
  1438. #define MPSC_1_TRANSMIT_DESCRIPTOR_PCI_HIGH_ADDRESS 0xf2d4
  1439. /*#define SERIAL_INIT_PCI_HIGH_ADDRESS 0xf3201 */
  1440. #define COMM_UNIT_ARBITER_CONTROL 0xf300
  1441. #define COMM_UNIT_CROSS_BAR_TIMEOUT 0xf304
  1442. #define COMM_UNIT_INTERRUPT_CAUSE 0xf310
  1443. #define COMM_UNIT_INTERRUPT_MASK 0xf314
  1444. #define COMM_UNIT_ERROR_ADDRESS 0xf314
  1445. /****************************************/
  1446. /* Serial Initialization registers */
  1447. /****************************************/
  1448. /*#define SERIAL_INIT_LAST_DATA 0xf3241 */
  1449. /*#define SERIAL_INIT_STATUS_AND_CONTROL 0xf3281 */
  1450. #define SERIAL_INIT_LAST_DATA 0xf324
  1451. #define SERIAL_INIT_CONTROL 0xf328
  1452. #define SERIAL_INIT_STATUS 0xf32c
  1453. /****************************************/
  1454. /* Ethernet Unit Registers */
  1455. /****************************************/
  1456. #define ETH_PHY_ADDR_REG 0x2000
  1457. #define ETH_SMI_REG 0x2004
  1458. #define ETH_UNIT_DEFAULT_ADDR_REG 0x2008
  1459. #define ETH_UNIT_DEFAULTID_REG 0x200c
  1460. #define ETH_UNIT_INTERRUPT_CAUSE_REG 0x2080
  1461. #define ETH_UNIT_INTERRUPT_MASK_REG 0x2084
  1462. #define ETH_UNIT_INTERNAL_USE_REG 0x24fc
  1463. #define ETH_UNIT_ERROR_ADDR_REG 0x2094
  1464. #define ETH_BAR_0 0x2200
  1465. #define ETH_BAR_1 0x2208
  1466. #define ETH_BAR_2 0x2210
  1467. #define ETH_BAR_3 0x2218
  1468. #define ETH_BAR_4 0x2220
  1469. #define ETH_BAR_5 0x2228
  1470. #define ETH_SIZE_REG_0 0x2204
  1471. #define ETH_SIZE_REG_1 0x220c
  1472. #define ETH_SIZE_REG_2 0x2214
  1473. #define ETH_SIZE_REG_3 0x221c
  1474. #define ETH_SIZE_REG_4 0x2224
  1475. #define ETH_SIZE_REG_5 0x222c
  1476. #define ETH_HEADERS_RETARGET_BASE_REG 0x2230
  1477. #define ETH_HEADERS_RETARGET_CONTROL_REG 0x2234
  1478. #define ETH_HIGH_ADDR_REMAP_REG_0 0x2280
  1479. #define ETH_HIGH_ADDR_REMAP_REG_1 0x2284
  1480. #define ETH_HIGH_ADDR_REMAP_REG_2 0x2288
  1481. #define ETH_HIGH_ADDR_REMAP_REG_3 0x228c
  1482. #define ETH_BASE_ADDR_ENABLE_REG 0x2290
  1483. #define ETH_ACCESS_PROTECTION_REG(port) (0x2294 + (port<<2))
  1484. #define ETH_MIB_COUNTERS_BASE(port) (0x3000 + (port<<7))
  1485. #define ETH_PORT_CONFIG_REG(port) (0x2400 + (port<<10))
  1486. #define ETH_PORT_CONFIG_EXTEND_REG(port) (0x2404 + (port<<10))
  1487. #define ETH_MII_SERIAL_PARAMETRS_REG(port) (0x2408 + (port<<10))
  1488. #define ETH_GMII_SERIAL_PARAMETRS_REG(port) (0x240c + (port<<10))
  1489. #define ETH_VLAN_ETHERTYPE_REG(port) (0x2410 + (port<<10))
  1490. #define ETH_MAC_ADDR_LOW(port) (0x2414 + (port<<10))
  1491. #define ETH_MAC_ADDR_HIGH(port) (0x2418 + (port<<10))
  1492. #define ETH_SDMA_CONFIG_REG(port) (0x241c + (port<<10))
  1493. #define ETH_DSCP_0(port) (0x2420 + (port<<10))
  1494. #define ETH_DSCP_1(port) (0x2424 + (port<<10))
  1495. #define ETH_DSCP_2(port) (0x2428 + (port<<10))
  1496. #define ETH_DSCP_3(port) (0x242c + (port<<10))
  1497. #define ETH_DSCP_4(port) (0x2430 + (port<<10))
  1498. #define ETH_DSCP_5(port) (0x2434 + (port<<10))
  1499. #define ETH_DSCP_6(port) (0x2438 + (port<<10))
  1500. #define ETH_PORT_SERIAL_CONTROL_REG(port) (0x243c + (port<<10))
  1501. #define ETH_VLAN_PRIORITY_TAG_TO_PRIORITY(port) (0x2440 + (port<<10))
  1502. #define ETH_PORT_STATUS_REG(port) (0x2444 + (port<<10))
  1503. #define ETH_TRANSMIT_QUEUE_COMMAND_REG(port) (0x2448 + (port<<10))
  1504. #define ETH_TX_QUEUE_FIXED_PRIORITY(port) (0x244c + (port<<10))
  1505. #define ETH_PORT_TX_TOKEN_BUCKET_RATE_CONFIG(port) (0x2450 + (port<<10))
  1506. #define ETH_MAXIMUM_TRANSMIT_UNIT(port) (0x2458 + (port<<10))
  1507. #define ETH_PORT_MAXIMUM_TOKEN_BUCKET_SIZE(port) (0x245c + (port<<10))
  1508. #define ETH_INTERRUPT_CAUSE_REG(port) (0x2460 + (port<<10))
  1509. #define ETH_INTERRUPT_CAUSE_EXTEND_REG(port) (0x2464 + (port<<10))
  1510. #define ETH_INTERRUPT_MASK_REG(port) (0x2468 + (port<<10))
  1511. #define ETH_INTERRUPT_EXTEND_MASK_REG(port) (0x246c + (port<<10))
  1512. #define ETH_RX_FIFO_URGENT_THRESHOLD_REG(port) (0x2470 + (port<<10))
  1513. #define ETH_TX_FIFO_URGENT_THRESHOLD_REG(port) (0x2474 + (port<<10))
  1514. #define ETH_RX_MINIMAL_FRAME_SIZE_REG(port) (0x247c + (port<<10))
  1515. #define ETH_RX_DISCARDED_FRAMES_COUNTER(port) (0x2484 + (port<<10)
  1516. #define ETH_PORT_DEBUG_0_REG(port) (0x248c + (port<<10))
  1517. #define ETH_PORT_DEBUG_1_REG(port) (0x2490 + (port<<10))
  1518. #define ETH_PORT_INTERNAL_ADDR_ERROR_REG(port) (0x2494 + (port<<10))
  1519. #define ETH_INTERNAL_USE_REG(port) (0x24fc + (port<<10))
  1520. #define ETH_RECEIVE_QUEUE_COMMAND_REG(port) (0x2680 + (port<<10))
  1521. #define ETH_CURRENT_SERVED_TX_DESC_PTR(port) (0x2684 + (port<<10))
  1522. #define ETH_RX_CURRENT_QUEUE_DESC_PTR_0(port) (0x260c + (port<<10))
  1523. #define ETH_RX_CURRENT_QUEUE_DESC_PTR_1(port) (0x261c + (port<<10))
  1524. #define ETH_RX_CURRENT_QUEUE_DESC_PTR_2(port) (0x262c + (port<<10))
  1525. #define ETH_RX_CURRENT_QUEUE_DESC_PTR_3(port) (0x263c + (port<<10))
  1526. #define ETH_RX_CURRENT_QUEUE_DESC_PTR_4(port) (0x264c + (port<<10))
  1527. #define ETH_RX_CURRENT_QUEUE_DESC_PTR_5(port) (0x265c + (port<<10))
  1528. #define ETH_RX_CURRENT_QUEUE_DESC_PTR_6(port) (0x266c + (port<<10))
  1529. #define ETH_RX_CURRENT_QUEUE_DESC_PTR_7(port) (0x267c + (port<<10))
  1530. #define ETH_TX_CURRENT_QUEUE_DESC_PTR_0(port) (0x26c0 + (port<<10))
  1531. #define ETH_TX_CURRENT_QUEUE_DESC_PTR_1(port) (0x26c4 + (port<<10))
  1532. #define ETH_TX_CURRENT_QUEUE_DESC_PTR_2(port) (0x26c8 + (port<<10))
  1533. #define ETH_TX_CURRENT_QUEUE_DESC_PTR_3(port) (0x26cc + (port<<10))
  1534. #define ETH_TX_CURRENT_QUEUE_DESC_PTR_4(port) (0x26d0 + (port<<10))
  1535. #define ETH_TX_CURRENT_QUEUE_DESC_PTR_5(port) (0x26d4 + (port<<10))
  1536. #define ETH_TX_CURRENT_QUEUE_DESC_PTR_6(port) (0x26d8 + (port<<10))
  1537. #define ETH_TX_CURRENT_QUEUE_DESC_PTR_7(port) (0x26dc + (port<<10))
  1538. #define ETH_TX_QUEUE_0_TOKEN_BUCKET_COUNT(port) (0x2700 + (port<<10))
  1539. #define ETH_TX_QUEUE_1_TOKEN_BUCKET_COUNT(port) (0x2710 + (port<<10))
  1540. #define ETH_TX_QUEUE_2_TOKEN_BUCKET_COUNT(port) (0x2720 + (port<<10))
  1541. #define ETH_TX_QUEUE_3_TOKEN_BUCKET_COUNT(port) (0x2730 + (port<<10))
  1542. #define ETH_TX_QUEUE_4_TOKEN_BUCKET_COUNT(port) (0x2740 + (port<<10))
  1543. #define ETH_TX_QUEUE_5_TOKEN_BUCKET_COUNT(port) (0x2750 + (port<<10))
  1544. #define ETH_TX_QUEUE_6_TOKEN_BUCKET_COUNT(port) (0x2760 + (port<<10))
  1545. #define ETH_TX_QUEUE_7_TOKEN_BUCKET_COUNT(port) (0x2770 + (port<<10))
  1546. #define ETH_TX_QUEUE_0_TOKEN_BUCKET_CONFIG(port) (0x2704 + (port<<10))
  1547. #define ETH_TX_QUEUE_1_TOKEN_BUCKET_CONFIG(port) (0x2714 + (port<<10))
  1548. #define ETH_TX_QUEUE_2_TOKEN_BUCKET_CONFIG(port) (0x2724 + (port<<10))
  1549. #define ETH_TX_QUEUE_3_TOKEN_BUCKET_CONFIG(port) (0x2734 + (port<<10))
  1550. #define ETH_TX_QUEUE_4_TOKEN_BUCKET_CONFIG(port) (0x2744 + (port<<10))
  1551. #define ETH_TX_QUEUE_5_TOKEN_BUCKET_CONFIG(port) (0x2754 + (port<<10))
  1552. #define ETH_TX_QUEUE_6_TOKEN_BUCKET_CONFIG(port) (0x2764 + (port<<10))
  1553. #define ETH_TX_QUEUE_7_TOKEN_BUCKET_CONFIG(port) (0x2774 + (port<<10))
  1554. #define ETH_TX_QUEUE_0_ARBITER_CONFIG(port) (0x2708 + (port<<10))
  1555. #define ETH_TX_QUEUE_1_ARBITER_CONFIG(port) (0x2718 + (port<<10))
  1556. #define ETH_TX_QUEUE_2_ARBITER_CONFIG(port) (0x2728 + (port<<10))
  1557. #define ETH_TX_QUEUE_3_ARBITER_CONFIG(port) (0x2738 + (port<<10))
  1558. #define ETH_TX_QUEUE_4_ARBITER_CONFIG(port) (0x2748 + (port<<10))
  1559. #define ETH_TX_QUEUE_5_ARBITER_CONFIG(port) (0x2758 + (port<<10))
  1560. #define ETH_TX_QUEUE_6_ARBITER_CONFIG(port) (0x2768 + (port<<10))
  1561. #define ETH_TX_QUEUE_7_ARBITER_CONFIG(port) (0x2778 + (port<<10))
  1562. #define ETH_PORT_TX_TOKEN_BUCKET_COUNT(port) (0x2780 + (port<<10))
  1563. #define ETH_DA_FILTER_SPECIAL_MULTICAST_TABLE_BASE(port) (0x3400 + (port<<10))
  1564. #define ETH_DA_FILTER_OTHER_MULTICAST_TABLE_BASE(port) (0x3500 + (port<<10))
  1565. #define ETH_DA_FILTER_UNICAST_TABLE_BASE(port) (0x3600 + (port<<10))
  1566. /****************************************/
  1567. /* Cunit Debug (for internal use) */
  1568. /****************************************/
  1569. #define CUNIT_ADDRESS 0xf340
  1570. #define CUNIT_COMMAND_AND_ID 0xf344
  1571. #define CUNIT_WRITE_DATA_LOW 0xf348
  1572. #define CUNIT_WRITE_DATA_HIGH 0xf34c
  1573. #define CUNIT_WRITE_BYTE_ENABLE 0xf358
  1574. #define CUNIT_READ_DATA_LOW 0xf350
  1575. #define CUNIT_READ_DATA_HIGH 0xf354
  1576. #define CUNIT_READ_ID 0xf35c
  1577. /****************************************/
  1578. /* Fast Ethernet Unit Registers */
  1579. /****************************************/
  1580. /****************************************/
  1581. /* Ethernet Unit Registers */
  1582. /****************************************/
  1583. #define ETH_PHY_ADDR_REG 0x2000
  1584. #define ETH_SMI_REG 0x2004
  1585. #define ETH_UNIT_DEFAULT_ADDR_REG 0x2008
  1586. #define ETH_UNIT_DEFAULTID_REG 0x200c
  1587. #define ETH_UNIT_INTERRUPT_CAUSE_REG 0x2080
  1588. #define ETH_UNIT_INTERRUPT_MASK_REG 0x2084
  1589. #define ETH_UNIT_INTERNAL_USE_REG 0x24fc
  1590. #define ETH_UNIT_ERROR_ADDR_REG 0x2094
  1591. #define ETH_BAR_0 0x2200
  1592. #define ETH_BAR_1 0x2208
  1593. #define ETH_BAR_2 0x2210
  1594. #define ETH_BAR_3 0x2218
  1595. #define ETH_BAR_4 0x2220
  1596. #define ETH_BAR_5 0x2228
  1597. #define ETH_SIZE_REG_0 0x2204
  1598. #define ETH_SIZE_REG_1 0x220c
  1599. #define ETH_SIZE_REG_2 0x2214
  1600. #define ETH_SIZE_REG_3 0x221c
  1601. #define ETH_SIZE_REG_4 0x2224
  1602. #define ETH_SIZE_REG_5 0x222c
  1603. #define ETH_HEADERS_RETARGET_BASE_REG 0x2230
  1604. #define ETH_HEADERS_RETARGET_CONTROL_REG 0x2234
  1605. #define ETH_HIGH_ADDR_REMAP_REG_0 0x2280
  1606. #define ETH_HIGH_ADDR_REMAP_REG_1 0x2284
  1607. #define ETH_HIGH_ADDR_REMAP_REG_2 0x2288
  1608. #define ETH_HIGH_ADDR_REMAP_REG_3 0x228c
  1609. #define ETH_BASE_ADDR_ENABLE_REG 0x2290
  1610. #define ETH_ACCESS_PROTECTION_REG(port) (0x2294 + (port<<2))
  1611. #define ETH_MIB_COUNTERS_BASE(port) (0x3000 + (port<<7))
  1612. #define ETH_PORT_CONFIG_REG(port) (0x2400 + (port<<10))
  1613. #define ETH_PORT_CONFIG_EXTEND_REG(port) (0x2404 + (port<<10))
  1614. #define ETH_MII_SERIAL_PARAMETRS_REG(port) (0x2408 + (port<<10))
  1615. #define ETH_GMII_SERIAL_PARAMETRS_REG(port) (0x240c + (port<<10))
  1616. #define ETH_VLAN_ETHERTYPE_REG(port) (0x2410 + (port<<10))
  1617. #define ETH_MAC_ADDR_LOW(port) (0x2414 + (port<<10))
  1618. #define ETH_MAC_ADDR_HIGH(port) (0x2418 + (port<<10))
  1619. #define ETH_SDMA_CONFIG_REG(port) (0x241c + (port<<10))
  1620. #define ETH_DSCP_0(port) (0x2420 + (port<<10))
  1621. #define ETH_DSCP_1(port) (0x2424 + (port<<10))
  1622. #define ETH_DSCP_2(port) (0x2428 + (port<<10))
  1623. #define ETH_DSCP_3(port) (0x242c + (port<<10))
  1624. #define ETH_DSCP_4(port) (0x2430 + (port<<10))
  1625. #define ETH_DSCP_5(port) (0x2434 + (port<<10))
  1626. #define ETH_DSCP_6(port) (0x2438 + (port<<10))
  1627. #define ETH_PORT_SERIAL_CONTROL_REG(port) (0x243c + (port<<10))
  1628. #define ETH_VLAN_PRIORITY_TAG_TO_PRIORITY(port) (0x2440 + (port<<10))
  1629. #define ETH_PORT_STATUS_REG(port) (0x2444 + (port<<10))
  1630. #define ETH_TRANSMIT_QUEUE_COMMAND_REG(port) (0x2448 + (port<<10))
  1631. #define ETH_TX_QUEUE_FIXED_PRIORITY(port) (0x244c + (port<<10))
  1632. #define ETH_PORT_TX_TOKEN_BUCKET_RATE_CONFIG(port) (0x2450 + (port<<10))
  1633. #define ETH_MAXIMUM_TRANSMIT_UNIT(port) (0x2458 + (port<<10))
  1634. #define ETH_PORT_MAXIMUM_TOKEN_BUCKET_SIZE(port) (0x245c + (port<<10))
  1635. #define ETH_INTERRUPT_CAUSE_REG(port) (0x2460 + (port<<10))
  1636. #define ETH_INTERRUPT_CAUSE_EXTEND_REG(port) (0x2464 + (port<<10))
  1637. #define ETH_INTERRUPT_MASK_REG(port) (0x2468 + (port<<10))
  1638. #define ETH_INTERRUPT_EXTEND_MASK_REG(port) (0x246c + (port<<10))
  1639. #define ETH_RX_FIFO_URGENT_THRESHOLD_REG(port) (0x2470 + (port<<10))
  1640. #define ETH_TX_FIFO_URGENT_THRESHOLD_REG(port) (0x2474 + (port<<10))
  1641. #define ETH_RX_MINIMAL_FRAME_SIZE_REG(port) (0x247c + (port<<10))
  1642. #define ETH_RX_DISCARDED_FRAMES_COUNTER(port) (0x2484 + (port<<10)
  1643. #define ETH_PORT_DEBUG_0_REG(port) (0x248c + (port<<10))
  1644. #define ETH_PORT_DEBUG_1_REG(port) (0x2490 + (port<<10))
  1645. #define ETH_PORT_INTERNAL_ADDR_ERROR_REG(port) (0x2494 + (port<<10))
  1646. #define ETH_INTERNAL_USE_REG(port) (0x24fc + (port<<10))
  1647. #define ETH_RECEIVE_QUEUE_COMMAND_REG(port) (0x2680 + (port<<10))
  1648. #define ETH_CURRENT_SERVED_TX_DESC_PTR(port) (0x2684 + (port<<10))
  1649. #define ETH_RX_CURRENT_QUEUE_DESC_PTR_0(port) (0x260c + (port<<10))
  1650. #define ETH_RX_CURRENT_QUEUE_DESC_PTR_1(port) (0x261c + (port<<10))
  1651. #define ETH_RX_CURRENT_QUEUE_DESC_PTR_2(port) (0x262c + (port<<10))
  1652. #define ETH_RX_CURRENT_QUEUE_DESC_PTR_3(port) (0x263c + (port<<10))
  1653. #define ETH_RX_CURRENT_QUEUE_DESC_PTR_4(port) (0x264c + (port<<10))
  1654. #define ETH_RX_CURRENT_QUEUE_DESC_PTR_5(port) (0x265c + (port<<10))
  1655. #define ETH_RX_CURRENT_QUEUE_DESC_PTR_6(port) (0x266c + (port<<10))
  1656. #define ETH_RX_CURRENT_QUEUE_DESC_PTR_7(port) (0x267c + (port<<10))
  1657. #define ETH_TX_CURRENT_QUEUE_DESC_PTR_0(port) (0x26c0 + (port<<10))
  1658. #define ETH_TX_CURRENT_QUEUE_DESC_PTR_1(port) (0x26c4 + (port<<10))
  1659. #define ETH_TX_CURRENT_QUEUE_DESC_PTR_2(port) (0x26c8 + (port<<10))
  1660. #define ETH_TX_CURRENT_QUEUE_DESC_PTR_3(port) (0x26cc + (port<<10))
  1661. #define ETH_TX_CURRENT_QUEUE_DESC_PTR_4(port) (0x26d0 + (port<<10))
  1662. #define ETH_TX_CURRENT_QUEUE_DESC_PTR_5(port) (0x26d4 + (port<<10))
  1663. #define ETH_TX_CURRENT_QUEUE_DESC_PTR_6(port) (0x26d8 + (port<<10))
  1664. #define ETH_TX_CURRENT_QUEUE_DESC_PTR_7(port) (0x26dc + (port<<10))
  1665. #define ETH_TX_QUEUE_0_TOKEN_BUCKET_COUNT(port) (0x2700 + (port<<10))
  1666. #define ETH_TX_QUEUE_1_TOKEN_BUCKET_COUNT(port) (0x2710 + (port<<10))
  1667. #define ETH_TX_QUEUE_2_TOKEN_BUCKET_COUNT(port) (0x2720 + (port<<10))
  1668. #define ETH_TX_QUEUE_3_TOKEN_BUCKET_COUNT(port) (0x2730 + (port<<10))
  1669. #define ETH_TX_QUEUE_4_TOKEN_BUCKET_COUNT(port) (0x2740 + (port<<10))
  1670. #define ETH_TX_QUEUE_5_TOKEN_BUCKET_COUNT(port) (0x2750 + (port<<10))
  1671. #define ETH_TX_QUEUE_6_TOKEN_BUCKET_COUNT(port) (0x2760 + (port<<10))
  1672. #define ETH_TX_QUEUE_7_TOKEN_BUCKET_COUNT(port) (0x2770 + (port<<10))
  1673. #define ETH_TX_QUEUE_0_TOKEN_BUCKET_CONFIG(port) (0x2704 + (port<<10))
  1674. #define ETH_TX_QUEUE_1_TOKEN_BUCKET_CONFIG(port) (0x2714 + (port<<10))
  1675. #define ETH_TX_QUEUE_2_TOKEN_BUCKET_CONFIG(port) (0x2724 + (port<<10))
  1676. #define ETH_TX_QUEUE_3_TOKEN_BUCKET_CONFIG(port) (0x2734 + (port<<10))
  1677. #define ETH_TX_QUEUE_4_TOKEN_BUCKET_CONFIG(port) (0x2744 + (port<<10))
  1678. #define ETH_TX_QUEUE_5_TOKEN_BUCKET_CONFIG(port) (0x2754 + (port<<10))
  1679. #define ETH_TX_QUEUE_6_TOKEN_BUCKET_CONFIG(port) (0x2764 + (port<<10))
  1680. #define ETH_TX_QUEUE_7_TOKEN_BUCKET_CONFIG(port) (0x2774 + (port<<10))
  1681. #define ETH_TX_QUEUE_0_ARBITER_CONFIG(port) (0x2708 + (port<<10))
  1682. #define ETH_TX_QUEUE_1_ARBITER_CONFIG(port) (0x2718 + (port<<10))
  1683. #define ETH_TX_QUEUE_2_ARBITER_CONFIG(port) (0x2728 + (port<<10))
  1684. #define ETH_TX_QUEUE_3_ARBITER_CONFIG(port) (0x2738 + (port<<10))
  1685. #define ETH_TX_QUEUE_4_ARBITER_CONFIG(port) (0x2748 + (port<<10))
  1686. #define ETH_TX_QUEUE_5_ARBITER_CONFIG(port) (0x2758 + (port<<10))
  1687. #define ETH_TX_QUEUE_6_ARBITER_CONFIG(port) (0x2768 + (port<<10))
  1688. #define ETH_TX_QUEUE_7_ARBITER_CONFIG(port) (0x2778 + (port<<10))
  1689. #define ETH_PORT_TX_TOKEN_BUCKET_COUNT(port) (0x2780 + (port<<10))
  1690. #define ETH_DA_FILTER_SPECIAL_MULTICAST_TABLE_BASE(port) (0x3400 + (port<<10))
  1691. #define ETH_DA_FILTER_OTHER_MULTICAST_TABLE_BASE(port) (0x3500 + (port<<10))
  1692. #define ETH_DA_FILTER_UNICAST_TABLE_BASE(port) (0x3600 + (port<<10))
  1693. /* Ethernet GT64260 */
  1694. /*
  1695. #define ETHERNET_PHY_ADDRESS_REGISTER 0x2000
  1696. #define ETHERNET_SMI_REGISTER 0x2010
  1697. */
  1698. /* Ethernet 0 */
  1699. /*
  1700. #define ETHERNET0_PORT_CONFIGURATION_REGISTER 0x2400
  1701. #define ETHERNET0_PORT_CONFIGURATION_EXTEND_REGISTER 0x2408
  1702. #define ETHERNET0_PORT_COMMAND_REGISTER 0x2410
  1703. #define ETHERNET0_PORT_STATUS_REGISTER 0x2418
  1704. #define ETHERNET0_SERIAL_PARAMETRS_REGISTER 0x2420
  1705. #define ETHERNET0_HASH_TABLE_POINTER_REGISTER 0x2428
  1706. #define ETHERNET0_FLOW_CONTROL_SOURCE_ADDRESS_LOW 0x2430
  1707. #define ETHERNET0_FLOW_CONTROL_SOURCE_ADDRESS_HIGH 0x2438
  1708. #define ETHERNET0_SDMA_CONFIGURATION_REGISTER 0x2440
  1709. #define ETHERNET0_SDMA_COMMAND_REGISTER 0x2448
  1710. #define ETHERNET0_INTERRUPT_CAUSE_REGISTER 0x2450
  1711. #define ETHERNET0_INTERRUPT_MASK_REGISTER 0x2458
  1712. #define ETHERNET0_FIRST_RX_DESCRIPTOR_POINTER0 0x2480
  1713. #define ETHERNET0_FIRST_RX_DESCRIPTOR_POINTER1 0x2484
  1714. #define ETHERNET0_FIRST_RX_DESCRIPTOR_POINTER2 0x2488
  1715. #define ETHERNET0_FIRST_RX_DESCRIPTOR_POINTER3 0x248c
  1716. #define ETHERNET0_CURRENT_RX_DESCRIPTOR_POINTER0 0x24a0
  1717. #define ETHERNET0_CURRENT_RX_DESCRIPTOR_POINTER1 0x24a4
  1718. #define ETHERNET0_CURRENT_RX_DESCRIPTOR_POINTER2 0x24a8
  1719. #define ETHERNET0_CURRENT_RX_DESCRIPTOR_POINTER3 0x24ac
  1720. #define ETHERNET0_CURRENT_TX_DESCRIPTOR_POINTER0 0x24e0
  1721. #define ETHERNET0_CURRENT_TX_DESCRIPTOR_POINTER1 0x24e4
  1722. #define ETHERNET0_MIB_COUNTER_BASE 0x2500
  1723. */
  1724. /* Ethernet 1 */
  1725. /*
  1726. #define ETHERNET1_PORT_CONFIGURATION_REGISTER 0x2800
  1727. #define ETHERNET1_PORT_CONFIGURATION_EXTEND_REGISTER 0x2808
  1728. #define ETHERNET1_PORT_COMMAND_REGISTER 0x2810
  1729. #define ETHERNET1_PORT_STATUS_REGISTER 0x2818
  1730. #define ETHERNET1_SERIAL_PARAMETRS_REGISTER 0x2820
  1731. #define ETHERNET1_HASH_TABLE_POINTER_REGISTER 0x2828
  1732. #define ETHERNET1_FLOW_CONTROL_SOURCE_ADDRESS_LOW 0x2830
  1733. #define ETHERNET1_FLOW_CONTROL_SOURCE_ADDRESS_HIGH 0x2838
  1734. #define ETHERNET1_SDMA_CONFIGURATION_REGISTER 0x2840
  1735. #define ETHERNET1_SDMA_COMMAND_REGISTER 0x2848
  1736. #define ETHERNET1_INTERRUPT_CAUSE_REGISTER 0x2850
  1737. #define ETHERNET1_INTERRUPT_MASK_REGISTER 0x2858
  1738. #define ETHERNET1_FIRST_RX_DESCRIPTOR_POINTER0 0x2880
  1739. #define ETHERNET1_FIRST_RX_DESCRIPTOR_POINTER1 0x2884
  1740. #define ETHERNET1_FIRST_RX_DESCRIPTOR_POINTER2 0x2888
  1741. #define ETHERNET1_FIRST_RX_DESCRIPTOR_POINTER3 0x288c
  1742. #define ETHERNET1_CURRENT_RX_DESCRIPTOR_POINTER0 0x28a0
  1743. #define ETHERNET1_CURRENT_RX_DESCRIPTOR_POINTER1 0x28a4
  1744. #define ETHERNET1_CURRENT_RX_DESCRIPTOR_POINTER2 0x28a8
  1745. #define ETHERNET1_CURRENT_RX_DESCRIPTOR_POINTER3 0x28ac
  1746. #define ETHERNET1_CURRENT_TX_DESCRIPTOR_POINTER0 0x28e0
  1747. #define ETHERNET1_CURRENT_TX_DESCRIPTOR_POINTER1 0x28e4
  1748. #define ETHERNET1_MIB_COUNTER_BASE 0x2900
  1749. */
  1750. /* Ethernet 2 */
  1751. /*
  1752. #define ETHERNET2_PORT_CONFIGURATION_REGISTER 0x2c00
  1753. #define ETHERNET2_PORT_CONFIGURATION_EXTEND_REGISTER 0x2c08
  1754. #define ETHERNET2_PORT_COMMAND_REGISTER 0x2c10
  1755. #define ETHERNET2_PORT_STATUS_REGISTER 0x2c18
  1756. #define ETHERNET2_SERIAL_PARAMETRS_REGISTER 0x2c20
  1757. #define ETHERNET2_HASH_TABLE_POINTER_REGISTER 0x2c28
  1758. #define ETHERNET2_FLOW_CONTROL_SOURCE_ADDRESS_LOW 0x2c30
  1759. #define ETHERNET2_FLOW_CONTROL_SOURCE_ADDRESS_HIGH 0x2c38
  1760. #define ETHERNET2_SDMA_CONFIGURATION_REGISTER 0x2c40
  1761. #define ETHERNET2_SDMA_COMMAND_REGISTER 0x2c48
  1762. #define ETHERNET2_INTERRUPT_CAUSE_REGISTER 0x2c50
  1763. #define ETHERNET2_INTERRUPT_MASK_REGISTER 0x2c58
  1764. #define ETHERNET2_FIRST_RX_DESCRIPTOR_POINTER0 0x2c80
  1765. #define ETHERNET2_FIRST_RX_DESCRIPTOR_POINTER1 0x2c84
  1766. #define ETHERNET2_FIRST_RX_DESCRIPTOR_POINTER2 0x2c88
  1767. #define ETHERNET2_FIRST_RX_DESCRIPTOR_POINTER3 0x2c8c
  1768. #define ETHERNET2_CURRENT_RX_DESCRIPTOR_POINTER0 0x2ca0
  1769. #define ETHERNET2_CURRENT_RX_DESCRIPTOR_POINTER1 0x2ca4
  1770. #define ETHERNET2_CURRENT_RX_DESCRIPTOR_POINTER2 0x2ca8
  1771. #define ETHERNET2_CURRENT_RX_DESCRIPTOR_POINTER3 0x2cac
  1772. #define ETHERNET2_CURRENT_TX_DESCRIPTOR_POINTER0 0x2ce0
  1773. #define ETHERNET2_CURRENT_TX_DESCRIPTOR_POINTER1 0x2ce4
  1774. #define ETHERNET2_MIB_COUNTER_BASE 0x2d00
  1775. */
  1776. /****************************************/
  1777. /* SDMA Registers */
  1778. /****************************************/
  1779. #define SDMA_GROUP_CONFIGURATION_REGISTER 0xb1f0
  1780. #define CHANNEL0_CONFIGURATION_REGISTER 0x4000
  1781. #define CHANNEL0_COMMAND_REGISTER 0x4008
  1782. #define CHANNEL0_RX_CMD_STATUS 0x4800
  1783. #define CHANNEL0_RX_PACKET_AND_BUFFER_SIZES 0x4804
  1784. #define CHANNEL0_RX_BUFFER_POINTER 0x4808
  1785. #define CHANNEL0_RX_NEXT_POINTER 0x480c
  1786. #define CHANNEL0_CURRENT_RX_DESCRIPTOR_POINTER 0x4810
  1787. #define CHANNEL0_TX_CMD_STATUS 0x4C00
  1788. #define CHANNEL0_TX_PACKET_SIZE 0x4C04
  1789. #define CHANNEL0_TX_BUFFER_POINTER 0x4C08
  1790. #define CHANNEL0_TX_NEXT_POINTER 0x4C0c
  1791. #define CHANNEL0_CURRENT_TX_DESCRIPTOR_POINTER 0x4c10
  1792. #define CHANNEL0_FIRST_TX_DESCRIPTOR_POINTER 0x4c14
  1793. /*
  1794. #define CHANNEL1_CONFIGURATION_REGISTER 0x5000
  1795. #define CHANNEL1_COMMAND_REGISTER 0x5008
  1796. #define CHANNEL1_RX_CMD_STATUS 0x5800
  1797. #define CHANNEL1_RX_PACKET_AND_BUFFER_SIZES 0x5804
  1798. #define CHANNEL1_RX_BUFFER_POINTER 0x5808
  1799. #define CHANNEL1_RX_NEXT_POINTER 0x580c
  1800. #define CHANNEL1_TX_CMD_STATUS 0x5C00
  1801. #define CHANNEL1_TX_PACKET_SIZE 0x5C04
  1802. #define CHANNEL1_TX_BUFFER_POINTER 0x5C08
  1803. #define CHANNEL1_TX_NEXT_POINTER 0x5C0c
  1804. #define CHANNEL1_CURRENT_RX_DESCRIPTOR_POINTER 0x5810
  1805. #define CHANNEL1_CURRENT_TX_DESCRIPTOR_POINTER 0x5c10
  1806. #define CHANNEL1_FIRST_TX_DESCRIPTOR_POINTER 0x5c14
  1807. #define CHANNEL2_CONFIGURATION_REGISTER 0x6000
  1808. #define CHANNEL2_COMMAND_REGISTER 0x6008
  1809. #define CHANNEL2_RX_CMD_STATUS 0x6800
  1810. #define CHANNEL2_RX_PACKET_AND_BUFFER_SIZES 0x6804
  1811. #define CHANNEL2_RX_BUFFER_POINTER 0x6808
  1812. #define CHANNEL2_RX_NEXT_POINTER 0x680c
  1813. #define CHANNEL2_CURRENT_RX_DESCRIPTOR_POINTER 0x6810
  1814. #define CHANNEL2_TX_CMD_STATUS 0x6C00
  1815. #define CHANNEL2_TX_PACKET_SIZE 0x6C04
  1816. #define CHANNEL2_TX_BUFFER_POINTER 0x6C08
  1817. #define CHANNEL2_TX_NEXT_POINTER 0x6C0c
  1818. #define CHANNEL2_CURRENT_RX_DESCRIPTOR_POINTER 0x6810
  1819. #define CHANNEL2_CURRENT_TX_DESCRIPTOR_POINTER 0x6c10
  1820. #define CHANNEL2_FIRST_TX_DESCRIPTOR_POINTER 0x6c14
  1821. */
  1822. /* SDMA Interrupt */
  1823. /*
  1824. #define SDMA_CAUSE 0xb820
  1825. #define SDMA_MASK 0xb8a0
  1826. */
  1827. /***************************************/
  1828. /* SDMA Registers */
  1829. /***************************************/
  1830. #define SDMA_CONFIG_REG(channel) (0x4000 + (channel<<13))
  1831. #define SDMA_COMMAND_REG(channel) (0x4008 + (channel<<13))
  1832. #define SDMA_CURRENT_RX_DESCRIPTOR_POINTER(channel) (0x4810 + (channel<<13))
  1833. #define SDMA_CURRENT_TX_DESCRIPTOR_POINTER(channel) (0x4c10 + (channel<<13))
  1834. #define SDMA_FIRST_TX_DESCRIPTOR_POINTER(channel) (0x4c14 + (channel<<13))
  1835. #define SDMA_CAUSE_REG 0xb800
  1836. #define SDMA_MASK_REG 0xb880
  1837. /****************************************/
  1838. /* Baude Rate Generators Registers */
  1839. /****************************************/
  1840. /* BRG 0 */
  1841. #define BRG0_CONFIGURATION_REGISTER 0xb200
  1842. #define BRG0_BAUDE_TUNING_REGISTER 0xb204
  1843. /* BRG 1 */
  1844. #define BRG1_CONFIGURATION_REGISTER 0xb208
  1845. #define BRG1_BAUDE_TUNING_REGISTER 0xb20c
  1846. /* BRG 2 */
  1847. #define BRG2_CONFIGURATION_REGISTER 0xb210
  1848. #define BRG2_BAUDE_TUNING_REGISTER 0xb214
  1849. /* BRG Interrupts */
  1850. #define BRG_CAUSE_REGISTER 0xb834
  1851. #define BRG_MASK_REGISTER 0xb8b4
  1852. #define BRG_CONFIG_REG(brg) (0xb200 + (brg<<3))
  1853. #define BRG_BAUDE_TUNING_REG(brg) (0xb208 + (brg<<3))
  1854. #define BRG_CAUSE_REG BRG_CAUSE_REGISTER /*0xb8341 */
  1855. #define BRG_MASK_REG BRG_MASK_REGISTER /*0xb8b41 */
  1856. /* MISC */
  1857. #define MAIN_ROUTING_REGISTER 0xb400
  1858. #define RECEIVE_CLOCK_ROUTING_REGISTER 0xb404
  1859. #define TRANSMIT_CLOCK_ROUTING_REGISTER 0xb408
  1860. #define COMM_UNIT_ARBITER_CONFIGURATION_REGISTER 0xb40c
  1861. /****************************************/
  1862. /* Watchdog registers */
  1863. /****************************************/
  1864. #define WATCHDOG_CONFIGURATION_REGISTER 0xb410
  1865. #define WATCHDOG_VALUE_REGISTER 0xb414
  1866. #define WATCHDOG_CONFIG_REG WATCHDOG_CONFIGURATION_REGISTER /*0xb4101 */
  1867. #define WATCHDOG_VALUE_REG WATCHDOG_VALUE_REGISTER /*0xb4141 */
  1868. /****************************************/
  1869. /* Flex TDM Registers */
  1870. /****************************************/
  1871. /* FTDM Port */
  1872. #define FLEXTDM_TRANSMIT_READ_POINTER 0xa800
  1873. #define FLEXTDM_RECEIVE_READ_POINTER 0xa804
  1874. #define FLEXTDM_CONFIGURATION_REGISTER 0xa808
  1875. #define FLEXTDM_AUX_CHANNELA_TX_REGISTER 0xa80c
  1876. #define FLEXTDM_AUX_CHANNELA_RX_REGISTER 0xa810
  1877. #define FLEXTDM_AUX_CHANNELB_TX_REGISTER 0xa814
  1878. #define FLEXTDM_AUX_CHANNELB_RX_REGISTER 0xa818
  1879. /* FTDM Interrupts */
  1880. #define FTDM_CAUSE_REGISTER 0xb830
  1881. #define FTDM_MASK_REGISTER 0xb8b0
  1882. /****************************************/
  1883. /* GPP Interface Registers */
  1884. /****************************************/
  1885. #define GPP_IO_CONTROL 0xf100
  1886. #define GPP_LEVEL_CONTROL 0xf110
  1887. #define GPP_VALUE 0xf104
  1888. #define GPP_INTERRUPT_CAUSE 0xf108
  1889. #define GPP_INTERRUPT_MASK 0xf10c
  1890. #define GPP_INTERRUPT_MASK0 GPP_INTERRUPT_MASK /* 0xf10c1 */
  1891. #define GPP_INTERRUPT_MASK1 0xf114
  1892. #define GPP_VALUE_SET 0xf118
  1893. #define GPP_VALUE_CLEAR 0xf11c
  1894. /****************************************/
  1895. /* MPP Interface Registers */
  1896. /****************************************/
  1897. #define MPP_CONTROL0 0xf000
  1898. #define MPP_CONTROL1 0xf004
  1899. #define MPP_CONTROL2 0xf008
  1900. #define MPP_CONTROL3 0xf00c
  1901. #define DEBUG_PORT_MULTIPLEX 0xf014
  1902. /*#define SERIAL_PORT_MULTIPLEX 0xf0101 */
  1903. /****************************************/
  1904. /* Interrupt Controller Registers */
  1905. /****************************************/
  1906. /****************************************/
  1907. /* Interrupts */
  1908. /****************************************/
  1909. /****************************************/
  1910. /* Interrupts (checked I.A. 14.10.02) */
  1911. /****************************************/
  1912. #define LOW_INTERRUPT_CAUSE_REGISTER 0x004 /* gt64260: 0xc181 */
  1913. #define HIGH_INTERRUPT_CAUSE_REGISTER 0x00c /* gt64260: 0xc681 */
  1914. #define CPU_INTERRUPT_MASK_REGISTER_LOW 0x014 /* gt64260: 0xc1c1 */
  1915. #define CPU_INTERRUPT_MASK_REGISTER_HIGH 0x01c /* gt64260: 0xc6c1 */
  1916. #define CPU_SELECT_CAUSE_REGISTER 0x024 /* gt64260: 0xc701 */
  1917. #define CPU_INTERRUPT_1_MASK_REGISTER_LOW 0x034 /* new in the MV64360 and MV64460 */
  1918. #define CPU_INTERRUPT_1_MASK_REGISTER_HIGH 0x03c /* new in the MV64360 and MV64460 */
  1919. #define CPU_SELECT_1_CAUSE_REGISTER 0x044 /* new in the MV64360 and MV64460 */
  1920. #define PCI_0INTERRUPT_CAUSE_MASK_REGISTER_LOW 0x054 /* gt64260: 0xc241 */
  1921. #define PCI_0INTERRUPT_CAUSE_MASK_REGISTER_HIGH 0x05c /* gt64260: 0xc641 */
  1922. #define PCI_0SELECT_CAUSE 0x064 /* gt64260: 0xc741 */
  1923. #define PCI_1INTERRUPT_CAUSE_MASK_REGISTER_LOW 0x074 /* gt64260: 0xca41 */
  1924. #define PCI_1INTERRUPT_CAUSE_MASK_REGISTER_HIGH 0x07c /* gt64260: 0xce41 */
  1925. #define PCI_1SELECT_CAUSE 0x084 /* gt64260: 0xcf41 */
  1926. /*#define CPU_INT_0_MASK 0xe60 signal is not multiplexed on MPP in the MV64360 and MV64460 */
  1927. /*#define CPU_INT_1_MASK 0xe64 signal is not multiplexed on MPP in the MV64360 and MV64460 */
  1928. /*#define CPU_INT_2_MASK 0xe68 signal is not multiplexed on MPP in the MV64360 and MV64460 */
  1929. /*#define CPU_INT_3_MASK 0xe6c signal is not multiplexed on MPP in the MV64360 and MV64460 */
  1930. #define MAIN_INTERRUPT_CAUSE_LOW LOW_INTERRUPT_CAUSE_REGISTER /* 0x0041 */
  1931. #define MAIN_INTERRUPT_CAUSE_HIGH HIGH_INTERRUPT_CAUSE_REGISTER /* 0x00c1 */
  1932. #define CPU_INTERRUPT0_MASK_LOW CPU_INTERRUPT_MASK_REGISTER_LOW /* 0x0141 */
  1933. #define CPU_INTERRUPT0_MASK_HIGH CPU_INTERRUPT_MASK_REGISTER_HIGH /*0x01c1 */
  1934. #define CPU_INTERRUPT0_SELECT_CAUSE CPU_SELECT_CAUSE_REGISTER /* 0x0241 */
  1935. #define CPU_INTERRUPT1_MASK_LOW CPU_INTERRUPT_1_MASK_REGISTER_LOW /* 0x0341 */
  1936. #define CPU_INTERRUPT1_MASK_HIGH CPU_INTERRUPT_1_MASK_REGISTER_HIGH /* 0x03c1 */
  1937. #define CPU_INTERRUPT1_SELECT_CAUSE CPU_SELECT_1_CAUSE_REGISTER /* 0x0441 */
  1938. #define INTERRUPT0_MASK_0_LOW PCI_0INTERRUPT_CAUSE_MASK_REGISTER_LOW /* 0x0541 */
  1939. #define INTERRUPT0_MASK_0_HIGH PCI_0INTERRUPT_CAUSE_MASK_REGISTER_HIGH /* 0x05c1 */
  1940. #define INTERRUPT0_SELECT_CAUSE PCI_0SELECT_CAUSE /* 0x0641 */
  1941. #define INTERRUPT1_MASK_0_LOW PCI_1INTERRUPT_CAUSE_MASK_REGISTER_LOW /* 0x0741 */
  1942. #define INTERRUPT1_MASK_0_HIGH PCI_1INTERRUPT_CAUSE_MASK_REGISTER_HIGH /* 0x07c1 */
  1943. #define INTERRUPT1_SELECT_CAUSE PCI_1SELECT_CAUSE /* 0x0841 */
  1944. /****************************************/
  1945. /* I2C Registers */
  1946. /****************************************/
  1947. #define I2C_SLAVE_ADDRESS 0xc000
  1948. #define I2C_EXTENDED_SLAVE_ADDRESS 0xc040
  1949. #define I2C_DATA 0xc004
  1950. #define I2C_CONTROL 0xc008
  1951. #define I2C_STATUS_BAUDE_RATE 0xc00C
  1952. #define I2C_SOFT_RESET 0xc01c
  1953. #define I2C_SLAVE_ADDR I2C_SLAVE_ADDRESS /* 0xc0001 */
  1954. #define I2C_EXTENDED_SLAVE_ADDR I2C_EXTENDED_SLAVE_ADDRESS /*0xc0101 */
  1955. /****************************************/
  1956. /* MPSC Registers */
  1957. /****************************************/
  1958. /* MPSCs Clocks Routing Registers */
  1959. #define MPSC_ROUTING_REG 0xb400
  1960. #define MPSC_RX_CLOCK_ROUTING_REG 0xb404
  1961. #define MPSC_TX_CLOCK_ROUTING_REG 0xb408
  1962. /* MPSCs Interrupts Registers */
  1963. #define MPSC_CAUSE_REG(port) (0xb804 + (port<<3))
  1964. #define MPSC_MASK_REG(port) (0xb884 + (port<<3))
  1965. #define MPSC_MAIN_CONFIG_LOW(port) (0x8000 + (port<<12))
  1966. #define MPSC_MAIN_CONFIG_HIGH(port) (0x8004 + (port<<12))
  1967. #define MPSC_PROTOCOL_CONFIG(port) (0x8008 + (port<<12))
  1968. #define MPSC_CHANNEL_REG1(port) (0x800c + (port<<12))
  1969. #define MPSC_CHANNEL_REG2(port) (0x8010 + (port<<12))
  1970. #define MPSC_CHANNEL_REG3(port) (0x8014 + (port<<12))
  1971. #define MPSC_CHANNEL_REG4(port) (0x8018 + (port<<12))
  1972. #define MPSC_CHANNEL_REG5(port) (0x801c + (port<<12))
  1973. #define MPSC_CHANNEL_REG6(port) (0x8020 + (port<<12))
  1974. #define MPSC_CHANNEL_REG7(port) (0x8024 + (port<<12))
  1975. #define MPSC_CHANNEL_REG8(port) (0x8028 + (port<<12))
  1976. #define MPSC_CHANNEL_REG9(port) (0x802c + (port<<12))
  1977. #define MPSC_CHANNEL_REG10(port) (0x8030 + (port<<12))
  1978. /* MPSC0 */
  1979. #define MPSC0_MAIN_CONFIGURATION_LOW 0x8000
  1980. #define MPSC0_MAIN_CONFIGURATION_HIGH 0x8004
  1981. #define MPSC0_PROTOCOL_CONFIGURATION 0x8008
  1982. #define CHANNEL0_REGISTER1 0x800c
  1983. #define CHANNEL0_REGISTER2 0x8010
  1984. #define CHANNEL0_REGISTER3 0x8014
  1985. #define CHANNEL0_REGISTER4 0x8018
  1986. #define CHANNEL0_REGISTER5 0x801c
  1987. #define CHANNEL0_REGISTER6 0x8020
  1988. #define CHANNEL0_REGISTER7 0x8024
  1989. #define CHANNEL0_REGISTER8 0x8028
  1990. #define CHANNEL0_REGISTER9 0x802c
  1991. #define CHANNEL0_REGISTER10 0x8030
  1992. #define CHANNEL0_REGISTER11 0x8034
  1993. /* MPSC1 */
  1994. #define MPSC1_MAIN_CONFIGURATION_LOW 0x8840
  1995. #define MPSC1_MAIN_CONFIGURATION_HIGH 0x8844
  1996. #define MPSC1_PROTOCOL_CONFIGURATION 0x8848
  1997. #define CHANNEL1_REGISTER1 0x884c
  1998. #define CHANNEL1_REGISTER2 0x8850
  1999. #define CHANNEL1_REGISTER3 0x8854
  2000. #define CHANNEL1_REGISTER4 0x8858
  2001. #define CHANNEL1_REGISTER5 0x885c
  2002. #define CHANNEL1_REGISTER6 0x8860
  2003. #define CHANNEL1_REGISTER7 0x8864
  2004. #define CHANNEL1_REGISTER8 0x8868
  2005. #define CHANNEL1_REGISTER9 0x886c
  2006. #define CHANNEL1_REGISTER10 0x8870
  2007. #define CHANNEL1_REGISTER11 0x8874
  2008. /* MPSC2 */
  2009. #define MPSC2_MAIN_CONFIGURATION_LOW 0x9040
  2010. #define MPSC2_MAIN_CONFIGURATION_HIGH 0x9044
  2011. #define MPSC2_PROTOCOL_CONFIGURATION 0x9048
  2012. #define CHANNEL2_REGISTER1 0x904c
  2013. #define CHANNEL2_REGISTER2 0x9050
  2014. #define CHANNEL2_REGISTER3 0x9054
  2015. #define CHANNEL2_REGISTER4 0x9058
  2016. #define CHANNEL2_REGISTER5 0x905c
  2017. #define CHANNEL2_REGISTER6 0x9060
  2018. #define CHANNEL2_REGISTER7 0x9064
  2019. #define CHANNEL2_REGISTER8 0x9068
  2020. #define CHANNEL2_REGISTER9 0x906c
  2021. #define CHANNEL2_REGISTER10 0x9070
  2022. #define CHANNEL2_REGISTER11 0x9074
  2023. /* MPSCs Interrupts */
  2024. #define MPSC0_CAUSE 0xb824
  2025. #define MPSC0_MASK 0xb8a4
  2026. #define MPSC1_CAUSE 0xb828
  2027. #define MPSC1_MASK 0xb8a8
  2028. #define MPSC2_CAUSE 0xb82c
  2029. #define MPSC2_MASK 0xb8ac
  2030. /*******************************************/
  2031. /* CUNIT Registers */
  2032. /*******************************************/
  2033. /* Address Decoding Register Map */
  2034. #define CUNIT_BASE_ADDR_REG0 0xf200
  2035. #define CUNIT_BASE_ADDR_REG1 0xf208
  2036. #define CUNIT_BASE_ADDR_REG2 0xf210
  2037. #define CUNIT_BASE_ADDR_REG3 0xf218
  2038. #define CUNIT_SIZE0 0xf204
  2039. #define CUNIT_SIZE1 0xf20c
  2040. #define CUNIT_SIZE2 0xf214
  2041. #define CUNIT_SIZE3 0xf21c
  2042. #define CUNIT_HIGH_ADDR_REMAP_REG0 0xf240
  2043. #define CUNIT_HIGH_ADDR_REMAP_REG1 0xf244
  2044. #define CUNIT_BASE_ADDR_ENABLE_REG 0xf250
  2045. #define MPSC0_ACCESS_PROTECTION_REG 0xf254
  2046. #define MPSC1_ACCESS_PROTECTION_REG 0xf258
  2047. #define CUNIT_INTERNAL_SPACE_BASE_ADDR_REG 0xf25C
  2048. /* Error Report Registers */
  2049. #define CUNIT_INTERRUPT_CAUSE_REG 0xf310
  2050. #define CUNIT_INTERRUPT_MASK_REG 0xf314
  2051. #define CUNIT_ERROR_ADDR 0xf318
  2052. /* Cunit Control Registers */
  2053. #define CUNIT_ARBITER_CONTROL_REG 0xf300
  2054. #define CUNIT_CONFIG_REG 0xb40c
  2055. #define CUNIT_CRROSBAR_TIMEOUT_REG 0xf304
  2056. /* Cunit Debug Registers */
  2057. #define CUNIT_DEBUG_LOW 0xf340
  2058. #define CUNIT_DEBUG_HIGH 0xf344
  2059. #define CUNIT_MMASK 0xf380
  2060. #endif /* __INCmv_gen_regh */