fec.h 10 KB

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  1. /*
  2. * fec.h -- Fast Ethernet Controller definitions
  3. *
  4. * Some definitions copied from commproc.h for MPC8xx:
  5. * MPC8xx Communication Processor Module.
  6. * Copyright (c) 1997 Dan Malek (dmalek@jlc.net)
  7. *
  8. * Add FEC Structure and definitions
  9. * Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
  10. * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
  11. *
  12. * See file CREDITS for list of people who contributed to this
  13. * project.
  14. *
  15. * This program is free software; you can redistribute it and/or
  16. * modify it under the terms of the GNU General Public License as
  17. * published by the Free Software Foundation; either version 2 of
  18. * the License, or (at your option) any later version.
  19. *
  20. * This program is distributed in the hope that it will be useful,
  21. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  22. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  23. * GNU General Public License for more details.
  24. *
  25. * You should have received a copy of the GNU General Public License
  26. * along with this program; if not, write to the Free Software
  27. * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  28. * MA 02111-1307 USA
  29. */
  30. #ifndef fec_h
  31. #define fec_h
  32. /* Buffer descriptors used FEC.
  33. */
  34. typedef struct cpm_buf_desc {
  35. ushort cbd_sc; /* Status and Control */
  36. ushort cbd_datlen; /* Data length in buffer */
  37. uint cbd_bufaddr; /* Buffer address in host memory */
  38. } cbd_t;
  39. #define BD_SC_EMPTY ((ushort)0x8000) /* Receive is empty */
  40. #define BD_SC_READY ((ushort)0x8000) /* Transmit is ready */
  41. #define BD_SC_WRAP ((ushort)0x2000) /* Last buffer descriptor */
  42. #define BD_SC_INTRPT ((ushort)0x1000) /* Interrupt on change */
  43. #define BD_SC_LAST ((ushort)0x0800) /* Last buffer in frame */
  44. #define BD_SC_TC ((ushort)0x0400) /* Transmit CRC */
  45. #define BD_SC_CM ((ushort)0x0200) /* Continous mode */
  46. #define BD_SC_ID ((ushort)0x0100) /* Rec'd too many idles */
  47. #define BD_SC_P ((ushort)0x0100) /* xmt preamble */
  48. #define BD_SC_BR ((ushort)0x0020) /* Break received */
  49. #define BD_SC_FR ((ushort)0x0010) /* Framing error */
  50. #define BD_SC_PR ((ushort)0x0008) /* Parity error */
  51. #define BD_SC_OV ((ushort)0x0002) /* Overrun */
  52. #define BD_SC_CD ((ushort)0x0001) /* Carrier Detect lost */
  53. /* Buffer descriptor control/status used by Ethernet receive.
  54. */
  55. #define BD_ENET_RX_EMPTY ((ushort)0x8000)
  56. #define BD_ENET_RX_RO1 ((ushort)0x4000)
  57. #define BD_ENET_RX_WRAP ((ushort)0x2000)
  58. #define BD_ENET_RX_INTR ((ushort)0x1000)
  59. #define BD_ENET_RX_RO2 BD_ENET_RX_INTR
  60. #define BD_ENET_RX_LAST ((ushort)0x0800)
  61. #define BD_ENET_RX_FIRST ((ushort)0x0400)
  62. #define BD_ENET_RX_MISS ((ushort)0x0100)
  63. #define BD_ENET_RX_BC ((ushort)0x0080)
  64. #define BD_ENET_RX_MC ((ushort)0x0040)
  65. #define BD_ENET_RX_LG ((ushort)0x0020)
  66. #define BD_ENET_RX_NO ((ushort)0x0010)
  67. #define BD_ENET_RX_SH ((ushort)0x0008)
  68. #define BD_ENET_RX_CR ((ushort)0x0004)
  69. #define BD_ENET_RX_OV ((ushort)0x0002)
  70. #define BD_ENET_RX_CL ((ushort)0x0001)
  71. #define BD_ENET_RX_TR BD_ENET_RX_CL
  72. #define BD_ENET_RX_STATS ((ushort)0x013f) /* All status bits */
  73. /* Buffer descriptor control/status used by Ethernet transmit.
  74. */
  75. #define BD_ENET_TX_READY ((ushort)0x8000)
  76. #define BD_ENET_TX_PAD ((ushort)0x4000)
  77. #define BD_ENET_TX_TO1 BD_ENET_TX_PAD
  78. #define BD_ENET_TX_WRAP ((ushort)0x2000)
  79. #define BD_ENET_TX_INTR ((ushort)0x1000)
  80. #define BD_ENET_TX_TO2 BD_ENET_TX_INTR_
  81. #define BD_ENET_TX_LAST ((ushort)0x0800)
  82. #define BD_ENET_TX_TC ((ushort)0x0400)
  83. #define BD_ENET_TX_DEF ((ushort)0x0200)
  84. #define BD_ENET_TX_ABC BD_ENET_TX_DEF
  85. #define BD_ENET_TX_HB ((ushort)0x0100)
  86. #define BD_ENET_TX_LC ((ushort)0x0080)
  87. #define BD_ENET_TX_RL ((ushort)0x0040)
  88. #define BD_ENET_TX_RCMASK ((ushort)0x003c)
  89. #define BD_ENET_TX_UN ((ushort)0x0002)
  90. #define BD_ENET_TX_CSL ((ushort)0x0001)
  91. #define BD_ENET_TX_STATS ((ushort)0x03ff) /* All status bits */
  92. /*********************************************************************
  93. * Fast Ethernet Controller (FEC)
  94. *********************************************************************/
  95. /* FEC private information */
  96. struct fec_info_s {
  97. int index;
  98. u32 iobase;
  99. u32 pinmux;
  100. u32 miibase;
  101. int phy_addr;
  102. int dup_spd;
  103. char *phy_name;
  104. int phyname_init;
  105. cbd_t *rxbd; /* Rx BD */
  106. cbd_t *txbd; /* Tx BD */
  107. uint rxIdx;
  108. uint txIdx;
  109. char *txbuf;
  110. int initialized;
  111. struct fec_info_s *next;
  112. };
  113. #ifdef CONFIG_MCFFEC
  114. /* Register read/write struct */
  115. typedef struct fec {
  116. #ifdef CONFIG_M5272
  117. u32 ecr; /* 0x00 */
  118. u32 eir; /* 0x04 */
  119. u32 eimr; /* 0x08 */
  120. u32 ivsr; /* 0x0C */
  121. u32 rdar; /* 0x10 */
  122. u32 tdar; /* 0x14 */
  123. u8 resv1[0x28]; /* 0x18 */
  124. u32 mmfr; /* 0x40 */
  125. u32 mscr; /* 0x44 */
  126. u8 resv2[0x44]; /* 0x48 */
  127. u32 frbr; /* 0x8C */
  128. u32 frsr; /* 0x90 */
  129. u8 resv3[0x10]; /* 0x94 */
  130. u32 tfwr; /* 0xA4 */
  131. u32 res4; /* 0xA8 */
  132. u32 tfsr; /* 0xAC */
  133. u8 resv4[0x50]; /* 0xB0 */
  134. u32 opd; /* 0x100 - dummy */
  135. u32 rcr; /* 0x104 */
  136. u32 mibc; /* 0x108 */
  137. u8 resv5[0x38]; /* 0x10C */
  138. u32 tcr; /* 0x144 */
  139. u8 resv6[0x270]; /* 0x148 */
  140. u32 iaur; /* 0x3B8 - dummy */
  141. u32 ialr; /* 0x3BC - dummy */
  142. u32 palr; /* 0x3C0 */
  143. u32 paur; /* 0x3C4 */
  144. u32 gaur; /* 0x3C8 */
  145. u32 galr; /* 0x3CC */
  146. u32 erdsr; /* 0x3D0 */
  147. u32 etdsr; /* 0x3D4 */
  148. u32 emrbr; /* 0x3D8 */
  149. u8 resv12[0x74]; /* 0x18C */
  150. #else
  151. u8 resv0[0x4];
  152. u32 eir;
  153. u32 eimr;
  154. u8 resv1[0x4];
  155. u32 rdar;
  156. u32 tdar;
  157. u8 resv2[0xC];
  158. u32 ecr;
  159. u8 resv3[0x18];
  160. u32 mmfr;
  161. u32 mscr;
  162. u8 resv4[0x1C];
  163. u32 mibc;
  164. u8 resv5[0x1C];
  165. u32 rcr;
  166. u8 resv6[0x3C];
  167. u32 tcr;
  168. u8 resv7[0x1C];
  169. u32 palr;
  170. u32 paur;
  171. u32 opd;
  172. u8 resv8[0x28];
  173. u32 iaur;
  174. u32 ialr;
  175. u32 gaur;
  176. u32 galr;
  177. u8 resv9[0x1C];
  178. u32 tfwr;
  179. u8 resv10[0x4];
  180. u32 frbr;
  181. u32 frsr;
  182. u8 resv11[0x2C];
  183. u32 erdsr;
  184. u32 etdsr;
  185. u32 emrbr;
  186. u8 resv12[0x74];
  187. #endif
  188. u32 rmon_t_drop;
  189. u32 rmon_t_packets;
  190. u32 rmon_t_bc_pkt;
  191. u32 rmon_t_mc_pkt;
  192. u32 rmon_t_crc_align;
  193. u32 rmon_t_undersize;
  194. u32 rmon_t_oversize;
  195. u32 rmon_t_frag;
  196. u32 rmon_t_jab;
  197. u32 rmon_t_col;
  198. u32 rmon_t_p64;
  199. u32 rmon_t_p65to127;
  200. u32 rmon_t_p128to255;
  201. u32 rmon_t_p256to511;
  202. u32 rmon_t_p512to1023;
  203. u32 rmon_t_p1024to2047;
  204. u32 rmon_t_p_gte2048;
  205. u32 rmon_t_octets;
  206. u32 ieee_t_drop;
  207. u32 ieee_t_frame_ok;
  208. u32 ieee_t_1col;
  209. u32 ieee_t_mcol;
  210. u32 ieee_t_def;
  211. u32 ieee_t_lcol;
  212. u32 ieee_t_excol;
  213. u32 ieee_t_macerr;
  214. u32 ieee_t_cserr;
  215. u32 ieee_t_sqe;
  216. u32 ieee_t_fdxfc;
  217. u32 ieee_t_octets_ok;
  218. u8 resv13[0x8];
  219. u32 rmon_r_drop;
  220. u32 rmon_r_packets;
  221. u32 rmon_r_bc_pkt;
  222. u32 rmon_r_mc_pkt;
  223. u32 rmon_r_crc_align;
  224. u32 rmon_r_undersize;
  225. u32 rmon_r_oversize;
  226. u32 rmon_r_frag;
  227. u32 rmon_r_jab;
  228. u32 rmon_r_resvd_0;
  229. u32 rmon_r_p64;
  230. u32 rmon_r_p65to127;
  231. u32 rmon_r_p128to255;
  232. u32 rmon_r_p256to511;
  233. u32 rmon_r_p512to1023;
  234. u32 rmon_r_p1024to2047;
  235. u32 rmon_r_p_gte2048;
  236. u32 rmon_r_octets;
  237. u32 ieee_r_drop;
  238. u32 ieee_r_frame_ok;
  239. u32 ieee_r_crc;
  240. u32 ieee_r_align;
  241. u32 ieee_r_macerr;
  242. u32 ieee_r_fdxfc;
  243. u32 ieee_r_octets_ok;
  244. } fec_t;
  245. #endif /* CONFIG_MCFFEC */
  246. /*********************************************************************
  247. * Fast Ethernet Controller (FEC)
  248. *********************************************************************/
  249. /* Bit definitions and macros for FEC_EIR */
  250. #define FEC_EIR_CLEAR_ALL (0xFFF80000)
  251. #define FEC_EIR_HBERR (0x80000000)
  252. #define FEC_EIR_BABR (0x40000000)
  253. #define FEC_EIR_BABT (0x20000000)
  254. #define FEC_EIR_GRA (0x10000000)
  255. #define FEC_EIR_TXF (0x08000000)
  256. #define FEC_EIR_TXB (0x04000000)
  257. #define FEC_EIR_RXF (0x02000000)
  258. #define FEC_EIR_RXB (0x01000000)
  259. #define FEC_EIR_MII (0x00800000)
  260. #define FEC_EIR_EBERR (0x00400000)
  261. #define FEC_EIR_LC (0x00200000)
  262. #define FEC_EIR_RL (0x00100000)
  263. #define FEC_EIR_UN (0x00080000)
  264. /* Bit definitions and macros for FEC_RDAR */
  265. #define FEC_RDAR_R_DES_ACTIVE (0x01000000)
  266. /* Bit definitions and macros for FEC_TDAR */
  267. #define FEC_TDAR_X_DES_ACTIVE (0x01000000)
  268. /* Bit definitions and macros for FEC_ECR */
  269. #define FEC_ECR_ETHER_EN (0x00000002)
  270. #define FEC_ECR_RESET (0x00000001)
  271. /* Bit definitions and macros for FEC_MMFR */
  272. #define FEC_MMFR_DATA(x) (((x)&0xFFFF))
  273. #define FEC_MMFR_ST(x) (((x)&0x03)<<30)
  274. #define FEC_MMFR_ST_01 (0x40000000)
  275. #define FEC_MMFR_OP_RD (0x20000000)
  276. #define FEC_MMFR_OP_WR (0x10000000)
  277. #define FEC_MMFR_PA(x) (((x)&0x1F)<<23)
  278. #define FEC_MMFR_RA(x) (((x)&0x1F)<<18)
  279. #define FEC_MMFR_TA(x) (((x)&0x03)<<16)
  280. #define FEC_MMFR_TA_10 (0x00020000)
  281. /* Bit definitions and macros for FEC_MSCR */
  282. #define FEC_MSCR_DIS_PREAMBLE (0x00000080)
  283. #define FEC_MSCR_MII_SPEED(x) (((x)&0x3F)<<1)
  284. /* Bit definitions and macros for FEC_MIBC */
  285. #define FEC_MIBC_MIB_DISABLE (0x80000000)
  286. #define FEC_MIBC_MIB_IDLE (0x40000000)
  287. /* Bit definitions and macros for FEC_RCR */
  288. #define FEC_RCR_MAX_FL(x) (((x)&0x7FF)<<16)
  289. #define FEC_RCR_FCE (0x00000020)
  290. #define FEC_RCR_BC_REJ (0x00000010)
  291. #define FEC_RCR_PROM (0x00000008)
  292. #define FEC_RCR_MII_MODE (0x00000004)
  293. #define FEC_RCR_DRT (0x00000002)
  294. #define FEC_RCR_LOOP (0x00000001)
  295. /* Bit definitions and macros for FEC_TCR */
  296. #define FEC_TCR_RFC_PAUSE (0x00000010)
  297. #define FEC_TCR_TFC_PAUSE (0x00000008)
  298. #define FEC_TCR_FDEN (0x00000004)
  299. #define FEC_TCR_HBC (0x00000002)
  300. #define FEC_TCR_GTS (0x00000001)
  301. /* Bit definitions and macros for FEC_PAUR */
  302. #define FEC_PAUR_PADDR2(x) (((x)&0xFFFF)<<16)
  303. #define FEC_PAUR_TYPE(x) ((x)&0xFFFF)
  304. /* Bit definitions and macros for FEC_OPD */
  305. #define FEC_OPD_PAUSE_DUR(x) (((x)&0x0000FFFF)<<0)
  306. #define FEC_OPD_OPCODE(x) (((x)&0x0000FFFF)<<16)
  307. /* Bit definitions and macros for FEC_TFWR */
  308. #define FEC_TFWR_X_WMRK(x) ((x)&0x03)
  309. #define FEC_TFWR_X_WMRK_64 (0x01)
  310. #define FEC_TFWR_X_WMRK_128 (0x02)
  311. #define FEC_TFWR_X_WMRK_192 (0x03)
  312. /* Bit definitions and macros for FEC_FRBR */
  313. #define FEC_FRBR_R_BOUND(x) (((x)&0xFF)<<2)
  314. /* Bit definitions and macros for FEC_FRSR */
  315. #define FEC_FRSR_R_FSTART(x) (((x)&0xFF)<<2)
  316. /* Bit definitions and macros for FEC_ERDSR */
  317. #define FEC_ERDSR_R_DES_START(x) (((x)&0x3FFFFFFF)<<2)
  318. /* Bit definitions and macros for FEC_ETDSR */
  319. #define FEC_ETDSR_X_DES_START(x) (((x)&0x3FFFFFFF)<<2)
  320. /* Bit definitions and macros for FEC_EMRBR */
  321. #define FEC_EMRBR_R_BUF_SIZE(x) (((x)&0x7F)<<4)
  322. #define FEC_RESET_DELAY 100
  323. #define FEC_RX_TOUT 100
  324. int fecpin_setclear(struct eth_device *dev, int setclear);
  325. #ifdef CONFIG_SYS_DISCOVER_PHY
  326. void __mii_init(void);
  327. uint mii_send(uint mii_cmd);
  328. int mii_discover_phy(struct eth_device *dev);
  329. int mcffec_miiphy_read(const char *devname, unsigned char addr,
  330. unsigned char reg, unsigned short *value);
  331. int mcffec_miiphy_write(const char *devname, unsigned char addr,
  332. unsigned char reg, unsigned short value);
  333. #endif
  334. #endif /* fec_h */