4xx_enet.c 62 KB

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  1. /*-----------------------------------------------------------------------------+
  2. * This source code is dual-licensed. You may use it under the terms of the
  3. * GNU General Public License version 2, or under the license below.
  4. *
  5. * This source code has been made available to you by IBM on an AS-IS
  6. * basis. Anyone receiving this source is licensed under IBM
  7. * copyrights to use it in any way he or she deems fit, including
  8. * copying it, modifying it, compiling it, and redistributing it either
  9. * with or without modifications. No license under IBM patents or
  10. * patent applications is to be implied by the copyright license.
  11. *
  12. * Any user of this software should understand that IBM cannot provide
  13. * technical support for this software and will not be responsible for
  14. * any consequences resulting from the use of this software.
  15. *
  16. * Any person who transfers this source code or any derivative work
  17. * must include the IBM copyright notice, this paragraph, and the
  18. * preceding two paragraphs in the transferred software.
  19. *
  20. * COPYRIGHT I B M CORPORATION 1995
  21. * LICENSED MATERIAL - PROGRAM PROPERTY OF I B M
  22. *-----------------------------------------------------------------------------*/
  23. /*-----------------------------------------------------------------------------+
  24. *
  25. * File Name: enetemac.c
  26. *
  27. * Function: Device driver for the ethernet EMAC3 macro on the 405GP.
  28. *
  29. * Author: Mark Wisner
  30. *
  31. * Change Activity-
  32. *
  33. * Date Description of Change BY
  34. * --------- --------------------- ---
  35. * 05-May-99 Created MKW
  36. * 27-Jun-99 Clean up JWB
  37. * 16-Jul-99 Added MAL error recovery and better IP packet handling MKW
  38. * 29-Jul-99 Added Full duplex support MKW
  39. * 06-Aug-99 Changed names for Mal CR reg MKW
  40. * 23-Aug-99 Turned off SYE when running at 10Mbs MKW
  41. * 24-Aug-99 Marked descriptor empty after call_xlc MKW
  42. * 07-Sep-99 Set MAL RX buffer size reg to ENET_MAX_MTU_ALIGNED / 16 MCG
  43. * to avoid chaining maximum sized packets. Push starting
  44. * RX descriptor address up to the next cache line boundary.
  45. * 16-Jan-00 Added support for booting with IP of 0x0 MKW
  46. * 15-Mar-00 Updated enetInit() to enable broadcast addresses in the
  47. * EMAC0_RXM register. JWB
  48. * 12-Mar-01 anne-sophie.harnois@nextream.fr
  49. * - Variables are compatible with those already defined in
  50. * include/net.h
  51. * - Receive buffer descriptor ring is used to send buffers
  52. * to the user
  53. * - Info print about send/received/handled packet number if
  54. * INFO_405_ENET is set
  55. * 17-Apr-01 stefan.roese@esd-electronics.com
  56. * - MAL reset in "eth_halt" included
  57. * - Enet speed and duplex output now in one line
  58. * 08-May-01 stefan.roese@esd-electronics.com
  59. * - MAL error handling added (eth_init called again)
  60. * 13-Nov-01 stefan.roese@esd-electronics.com
  61. * - Set IST bit in EMAC0_MR1 reg upon 100MBit or full duplex
  62. * 04-Jan-02 stefan.roese@esd-electronics.com
  63. * - Wait for PHY auto negotiation to complete added
  64. * 06-Feb-02 stefan.roese@esd-electronics.com
  65. * - Bug fixed in waiting for auto negotiation to complete
  66. * 26-Feb-02 stefan.roese@esd-electronics.com
  67. * - rx and tx buffer descriptors now allocated (no fixed address
  68. * used anymore)
  69. * 17-Jun-02 stefan.roese@esd-electronics.com
  70. * - MAL error debug printf 'M' removed (rx de interrupt may
  71. * occur upon many incoming packets with only 4 rx buffers).
  72. *-----------------------------------------------------------------------------*
  73. * 17-Nov-03 travis.sawyer@sandburst.com
  74. * - ported from 405gp_enet.c to utilized upto 4 EMAC ports
  75. * in the 440GX. This port should work with the 440GP
  76. * (2 EMACs) also
  77. * 15-Aug-05 sr@denx.de
  78. * - merged 405gp_enet.c and 440gx_enet.c to generic 4xx_enet.c
  79. now handling all 4xx cpu's.
  80. *-----------------------------------------------------------------------------*/
  81. #include <config.h>
  82. #include <common.h>
  83. #include <net.h>
  84. #include <asm/processor.h>
  85. #include <asm/io.h>
  86. #include <asm/cache.h>
  87. #include <asm/mmu.h>
  88. #include <commproc.h>
  89. #include <asm/ppc4xx.h>
  90. #include <asm/ppc4xx-emac.h>
  91. #include <asm/ppc4xx-mal.h>
  92. #include <miiphy.h>
  93. #include <malloc.h>
  94. #if !(defined(CONFIG_MII) || defined(CONFIG_CMD_MII))
  95. #error "CONFIG_MII has to be defined!"
  96. #endif
  97. #if defined(CONFIG_NETCONSOLE) && !defined(CONFIG_NET_MULTI)
  98. #error "CONFIG_NET_MULTI has to be defined for NetConsole"
  99. #endif
  100. #define EMAC_RESET_TIMEOUT 1000 /* 1000 ms reset timeout */
  101. #define PHY_AUTONEGOTIATE_TIMEOUT 5000 /* 5000 ms autonegotiate timeout */
  102. /* Ethernet Transmit and Receive Buffers */
  103. /* AS.HARNOIS
  104. * In the same way ENET_MAX_MTU and ENET_MAX_MTU_ALIGNED are set from
  105. * PKTSIZE and PKTSIZE_ALIGN (include/net.h)
  106. */
  107. #define ENET_MAX_MTU PKTSIZE
  108. #define ENET_MAX_MTU_ALIGNED PKTSIZE_ALIGN
  109. /*-----------------------------------------------------------------------------+
  110. * Defines for MAL/EMAC interrupt conditions as reported in the UIC (Universal
  111. * Interrupt Controller).
  112. *-----------------------------------------------------------------------------*/
  113. #define ETH_IRQ_NUM(dev) (VECNUM_ETH0 + ((dev) * VECNUM_ETH1_OFFS))
  114. #if defined(CONFIG_HAS_ETH3)
  115. #if !defined(CONFIG_440GX)
  116. #define UIC_ETHx (UIC_MASK(ETH_IRQ_NUM(0)) || UIC_MASK(ETH_IRQ_NUM(1)) || \
  117. UIC_MASK(ETH_IRQ_NUM(2)) || UIC_MASK(ETH_IRQ_NUM(3)))
  118. #else
  119. /* Unfortunately 440GX spreads EMAC interrupts on multiple UIC's */
  120. #define UIC_ETHx (UIC_MASK(ETH_IRQ_NUM(0)) || UIC_MASK(ETH_IRQ_NUM(1)))
  121. #define UIC_ETHxB (UIC_MASK(ETH_IRQ_NUM(2)) || UIC_MASK(ETH_IRQ_NUM(3)))
  122. #endif /* !defined(CONFIG_440GX) */
  123. #elif defined(CONFIG_HAS_ETH2)
  124. #define UIC_ETHx (UIC_MASK(ETH_IRQ_NUM(0)) || UIC_MASK(ETH_IRQ_NUM(1)) || \
  125. UIC_MASK(ETH_IRQ_NUM(2)))
  126. #elif defined(CONFIG_HAS_ETH1)
  127. #define UIC_ETHx (UIC_MASK(ETH_IRQ_NUM(0)) || UIC_MASK(ETH_IRQ_NUM(1)))
  128. #else
  129. #define UIC_ETHx UIC_MASK(ETH_IRQ_NUM(0))
  130. #endif
  131. /*
  132. * Define a default version for UIC_ETHxB for non 440GX so that we can
  133. * use common code for all 4xx variants
  134. */
  135. #if !defined(UIC_ETHxB)
  136. #define UIC_ETHxB 0
  137. #endif
  138. #define UIC_MAL_SERR UIC_MASK(VECNUM_MAL_SERR)
  139. #define UIC_MAL_TXDE UIC_MASK(VECNUM_MAL_TXDE)
  140. #define UIC_MAL_RXDE UIC_MASK(VECNUM_MAL_RXDE)
  141. #define UIC_MAL_TXEOB UIC_MASK(VECNUM_MAL_TXEOB)
  142. #define UIC_MAL_RXEOB UIC_MASK(VECNUM_MAL_RXEOB)
  143. #define MAL_UIC_ERR (UIC_MAL_SERR | UIC_MAL_TXDE | UIC_MAL_RXDE)
  144. #define MAL_UIC_DEF (UIC_MAL_RXEOB | MAL_UIC_ERR)
  145. /*
  146. * We have 3 different interrupt types:
  147. * - MAL interrupts indicating successful transfer
  148. * - MAL error interrupts indicating MAL related errors
  149. * - EMAC interrupts indicating EMAC related errors
  150. *
  151. * All those interrupts can be on different UIC's, but since
  152. * now at least all interrupts from one type are on the same
  153. * UIC. Only exception is 440GX where the EMAC interrupts are
  154. * spread over two UIC's!
  155. */
  156. #if defined(CONFIG_440GX)
  157. #define UIC_BASE_MAL UIC1_DCR_BASE
  158. #define UIC_BASE_MAL_ERR UIC2_DCR_BASE
  159. #define UIC_BASE_EMAC UIC2_DCR_BASE
  160. #define UIC_BASE_EMAC_B UIC3_DCR_BASE
  161. #else
  162. #define UIC_BASE_MAL (UIC0_DCR_BASE + (UIC_NR(VECNUM_MAL_TXEOB) * 0x10))
  163. #define UIC_BASE_MAL_ERR (UIC0_DCR_BASE + (UIC_NR(VECNUM_MAL_SERR) * 0x10))
  164. #define UIC_BASE_EMAC (UIC0_DCR_BASE + (UIC_NR(ETH_IRQ_NUM(0)) * 0x10))
  165. #define UIC_BASE_EMAC_B (UIC0_DCR_BASE + (UIC_NR(ETH_IRQ_NUM(0)) * 0x10))
  166. #endif
  167. #undef INFO_4XX_ENET
  168. #define BI_PHYMODE_NONE 0
  169. #define BI_PHYMODE_ZMII 1
  170. #define BI_PHYMODE_RGMII 2
  171. #define BI_PHYMODE_GMII 3
  172. #define BI_PHYMODE_RTBI 4
  173. #define BI_PHYMODE_TBI 5
  174. #if defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \
  175. defined(CONFIG_460EX) || defined(CONFIG_460GT) || \
  176. defined(CONFIG_405EX)
  177. #define BI_PHYMODE_SMII 6
  178. #define BI_PHYMODE_MII 7
  179. #if defined(CONFIG_460EX) || defined(CONFIG_460GT)
  180. #define BI_PHYMODE_RMII 8
  181. #endif
  182. #endif
  183. #define BI_PHYMODE_SGMII 9
  184. #if defined(CONFIG_440SP) || defined(CONFIG_440SPE) || \
  185. defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \
  186. defined(CONFIG_460EX) || defined(CONFIG_460GT) || \
  187. defined(CONFIG_405EX)
  188. #define SDR0_MFR_ETH_CLK_SEL_V(n) ((0x01<<27) / (n+1))
  189. #endif
  190. #if defined(CONFIG_460EX) || defined(CONFIG_460GT)
  191. #define SDR0_ETH_CFG_CLK_SEL_V(n) (0x01 << (8 + n))
  192. #endif
  193. #if defined(CONFIG_460EX) || defined(CONFIG_460GT)
  194. #define MAL_RX_CHAN_MUL 8 /* 460EX/GT uses MAL channel 8 for EMAC1 */
  195. #else
  196. #define MAL_RX_CHAN_MUL 1
  197. #endif
  198. /*--------------------------------------------------------------------+
  199. * Fixed PHY (PHY-less) support for Ethernet Ports.
  200. *--------------------------------------------------------------------*/
  201. /*
  202. * Some boards do not have a PHY for each ethernet port. These ports
  203. * are known as Fixed PHY (or PHY-less) ports. For such ports, set
  204. * the appropriate CONFIG_PHY_ADDR equal to CONFIG_FIXED_PHY and
  205. * then define CONFIG_SYS_FIXED_PHY_PORTS to define what the speed and
  206. * duplex should be for these ports in the board configuration
  207. * file.
  208. *
  209. * For Example:
  210. * #define CONFIG_FIXED_PHY 0xFFFFFFFF
  211. *
  212. * #define CONFIG_PHY_ADDR CONFIG_FIXED_PHY
  213. * #define CONFIG_PHY1_ADDR 1
  214. * #define CONFIG_PHY2_ADDR CONFIG_FIXED_PHY
  215. * #define CONFIG_PHY3_ADDR 3
  216. *
  217. * #define CONFIG_SYS_FIXED_PHY_PORT(devnum,speed,duplex) \
  218. * {devnum, speed, duplex},
  219. *
  220. * #define CONFIG_SYS_FIXED_PHY_PORTS \
  221. * CONFIG_SYS_FIXED_PHY_PORT(0,1000,FULL) \
  222. * CONFIG_SYS_FIXED_PHY_PORT(2,100,HALF)
  223. */
  224. #ifndef CONFIG_FIXED_PHY
  225. #define CONFIG_FIXED_PHY 0xFFFFFFFF /* Fixed PHY (PHY-less) */
  226. #endif
  227. #ifndef CONFIG_SYS_FIXED_PHY_PORTS
  228. #define CONFIG_SYS_FIXED_PHY_PORTS /* default is an empty array */
  229. #endif
  230. struct fixed_phy_port {
  231. unsigned int devnum; /* ethernet port */
  232. unsigned int speed; /* specified speed 10,100 or 1000 */
  233. unsigned int duplex; /* specified duplex FULL or HALF */
  234. };
  235. static const struct fixed_phy_port fixed_phy_port[] = {
  236. CONFIG_SYS_FIXED_PHY_PORTS /* defined in board configuration file */
  237. };
  238. /*-----------------------------------------------------------------------------+
  239. * Global variables. TX and RX descriptors and buffers.
  240. *-----------------------------------------------------------------------------*/
  241. /*
  242. * Get count of EMAC devices (doesn't have to be the max. possible number
  243. * supported by the cpu)
  244. *
  245. * CONFIG_BOARD_EMAC_COUNT added so now a "dynamic" way to configure the
  246. * EMAC count is possible. As it is needed for the Kilauea/Haleakala
  247. * 405EX/405EXr eval board, using the same binary.
  248. */
  249. #if defined(CONFIG_BOARD_EMAC_COUNT)
  250. #define LAST_EMAC_NUM board_emac_count()
  251. #else /* CONFIG_BOARD_EMAC_COUNT */
  252. #if defined(CONFIG_HAS_ETH3)
  253. #define LAST_EMAC_NUM 4
  254. #elif defined(CONFIG_HAS_ETH2)
  255. #define LAST_EMAC_NUM 3
  256. #elif defined(CONFIG_HAS_ETH1)
  257. #define LAST_EMAC_NUM 2
  258. #else
  259. #define LAST_EMAC_NUM 1
  260. #endif
  261. #endif /* CONFIG_BOARD_EMAC_COUNT */
  262. /* normal boards start with EMAC0 */
  263. #if !defined(CONFIG_EMAC_NR_START)
  264. #define CONFIG_EMAC_NR_START 0
  265. #endif
  266. #define MAL_RX_DESC_SIZE 2048
  267. #define MAL_TX_DESC_SIZE 2048
  268. #define MAL_ALLOC_SIZE (MAL_TX_DESC_SIZE + MAL_RX_DESC_SIZE)
  269. /*-----------------------------------------------------------------------------+
  270. * Prototypes and externals.
  271. *-----------------------------------------------------------------------------*/
  272. static void enet_rcv (struct eth_device *dev, unsigned long malisr);
  273. int enetInt (struct eth_device *dev);
  274. static void mal_err (struct eth_device *dev, unsigned long isr,
  275. unsigned long uic, unsigned long maldef,
  276. unsigned long mal_errr);
  277. static void emac_err (struct eth_device *dev, unsigned long isr);
  278. extern int phy_setup_aneg (char *devname, unsigned char addr);
  279. extern int emac4xx_miiphy_read (const char *devname, unsigned char addr,
  280. unsigned char reg, unsigned short *value);
  281. extern int emac4xx_miiphy_write (const char *devname, unsigned char addr,
  282. unsigned char reg, unsigned short value);
  283. int board_emac_count(void);
  284. static void emac_loopback_enable(EMAC_4XX_HW_PST hw_p)
  285. {
  286. #if defined(CONFIG_440SPE) || \
  287. defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \
  288. defined(CONFIG_405EX)
  289. u32 val;
  290. mfsdr(SDR0_MFR, val);
  291. val |= SDR0_MFR_ETH_CLK_SEL_V(hw_p->devnum);
  292. mtsdr(SDR0_MFR, val);
  293. #elif defined(CONFIG_460EX) || defined(CONFIG_460GT)
  294. u32 val;
  295. mfsdr(SDR0_ETH_CFG, val);
  296. val |= SDR0_ETH_CFG_CLK_SEL_V(hw_p->devnum);
  297. mtsdr(SDR0_ETH_CFG, val);
  298. #endif
  299. }
  300. static void emac_loopback_disable(EMAC_4XX_HW_PST hw_p)
  301. {
  302. #if defined(CONFIG_440SPE) || \
  303. defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \
  304. defined(CONFIG_405EX)
  305. u32 val;
  306. mfsdr(SDR0_MFR, val);
  307. val &= ~SDR0_MFR_ETH_CLK_SEL_V(hw_p->devnum);
  308. mtsdr(SDR0_MFR, val);
  309. #elif defined(CONFIG_460EX) || defined(CONFIG_460GT)
  310. u32 val;
  311. mfsdr(SDR0_ETH_CFG, val);
  312. val &= ~SDR0_ETH_CFG_CLK_SEL_V(hw_p->devnum);
  313. mtsdr(SDR0_ETH_CFG, val);
  314. #endif
  315. }
  316. /*-----------------------------------------------------------------------------+
  317. | ppc_4xx_eth_halt
  318. | Disable MAL channel, and EMACn
  319. +-----------------------------------------------------------------------------*/
  320. static void ppc_4xx_eth_halt (struct eth_device *dev)
  321. {
  322. EMAC_4XX_HW_PST hw_p = dev->priv;
  323. u32 val = 10000;
  324. out_be32((void *)EMAC0_IER + hw_p->hw_addr, 0x00000000); /* disable emac interrupts */
  325. /* 1st reset MAL channel */
  326. /* Note: writing a 0 to a channel has no effect */
  327. #if defined(CONFIG_405EP) || defined(CONFIG_440EP) || defined(CONFIG_440GR)
  328. mtdcr (MAL0_TXCARR, (MAL_CR_MMSR >> (hw_p->devnum * 2)));
  329. #else
  330. mtdcr (MAL0_TXCARR, (MAL_CR_MMSR >> hw_p->devnum));
  331. #endif
  332. mtdcr (MAL0_RXCARR, (MAL_CR_MMSR >> hw_p->devnum));
  333. /* wait for reset */
  334. while (mfdcr (MAL0_RXCASR) & (MAL_CR_MMSR >> hw_p->devnum)) {
  335. udelay (1000); /* Delay 1 MS so as not to hammer the register */
  336. val--;
  337. if (val == 0)
  338. break;
  339. }
  340. /* provide clocks for EMAC internal loopback */
  341. emac_loopback_enable(hw_p);
  342. /* EMAC RESET */
  343. out_be32((void *)EMAC0_MR0 + hw_p->hw_addr, EMAC_MR0_SRST);
  344. /* remove clocks for EMAC internal loopback */
  345. emac_loopback_disable(hw_p);
  346. #ifndef CONFIG_NETCONSOLE
  347. hw_p->print_speed = 1; /* print speed message again next time */
  348. #endif
  349. #if defined(CONFIG_460EX) || defined(CONFIG_460GT)
  350. /* don't bypass the TAHOE0/TAHOE1 cores for Linux */
  351. mfsdr(SDR0_ETH_CFG, val);
  352. val &= ~(SDR0_ETH_CFG_TAHOE0_BYPASS | SDR0_ETH_CFG_TAHOE1_BYPASS);
  353. mtsdr(SDR0_ETH_CFG, val);
  354. #endif
  355. return;
  356. }
  357. #if defined (CONFIG_440GX)
  358. int ppc_4xx_eth_setup_bridge(int devnum, bd_t * bis)
  359. {
  360. unsigned long pfc1;
  361. unsigned long zmiifer;
  362. unsigned long rmiifer;
  363. mfsdr(SDR0_PFC1, pfc1);
  364. pfc1 = SDR0_PFC1_EPS_DECODE(pfc1);
  365. zmiifer = 0;
  366. rmiifer = 0;
  367. switch (pfc1) {
  368. case 1:
  369. zmiifer |= ZMII_FER_RMII << ZMII_FER_V(0);
  370. zmiifer |= ZMII_FER_RMII << ZMII_FER_V(1);
  371. zmiifer |= ZMII_FER_RMII << ZMII_FER_V(2);
  372. zmiifer |= ZMII_FER_RMII << ZMII_FER_V(3);
  373. bis->bi_phymode[0] = BI_PHYMODE_ZMII;
  374. bis->bi_phymode[1] = BI_PHYMODE_ZMII;
  375. bis->bi_phymode[2] = BI_PHYMODE_ZMII;
  376. bis->bi_phymode[3] = BI_PHYMODE_ZMII;
  377. break;
  378. case 2:
  379. zmiifer |= ZMII_FER_SMII << ZMII_FER_V(0);
  380. zmiifer |= ZMII_FER_SMII << ZMII_FER_V(1);
  381. zmiifer |= ZMII_FER_SMII << ZMII_FER_V(2);
  382. zmiifer |= ZMII_FER_SMII << ZMII_FER_V(3);
  383. bis->bi_phymode[0] = BI_PHYMODE_ZMII;
  384. bis->bi_phymode[1] = BI_PHYMODE_ZMII;
  385. bis->bi_phymode[2] = BI_PHYMODE_ZMII;
  386. bis->bi_phymode[3] = BI_PHYMODE_ZMII;
  387. break;
  388. case 3:
  389. zmiifer |= ZMII_FER_RMII << ZMII_FER_V(0);
  390. rmiifer |= RGMII_FER_RGMII << RGMII_FER_V(2);
  391. bis->bi_phymode[0] = BI_PHYMODE_ZMII;
  392. bis->bi_phymode[1] = BI_PHYMODE_NONE;
  393. bis->bi_phymode[2] = BI_PHYMODE_RGMII;
  394. bis->bi_phymode[3] = BI_PHYMODE_NONE;
  395. break;
  396. case 4:
  397. zmiifer |= ZMII_FER_SMII << ZMII_FER_V(0);
  398. zmiifer |= ZMII_FER_SMII << ZMII_FER_V(1);
  399. rmiifer |= RGMII_FER_RGMII << RGMII_FER_V (2);
  400. rmiifer |= RGMII_FER_RGMII << RGMII_FER_V (3);
  401. bis->bi_phymode[0] = BI_PHYMODE_ZMII;
  402. bis->bi_phymode[1] = BI_PHYMODE_ZMII;
  403. bis->bi_phymode[2] = BI_PHYMODE_RGMII;
  404. bis->bi_phymode[3] = BI_PHYMODE_RGMII;
  405. break;
  406. case 5:
  407. zmiifer |= ZMII_FER_SMII << ZMII_FER_V (0);
  408. zmiifer |= ZMII_FER_SMII << ZMII_FER_V (1);
  409. zmiifer |= ZMII_FER_SMII << ZMII_FER_V (2);
  410. rmiifer |= RGMII_FER_RGMII << RGMII_FER_V(3);
  411. bis->bi_phymode[0] = BI_PHYMODE_ZMII;
  412. bis->bi_phymode[1] = BI_PHYMODE_ZMII;
  413. bis->bi_phymode[2] = BI_PHYMODE_ZMII;
  414. bis->bi_phymode[3] = BI_PHYMODE_RGMII;
  415. break;
  416. case 6:
  417. zmiifer |= ZMII_FER_SMII << ZMII_FER_V (0);
  418. zmiifer |= ZMII_FER_SMII << ZMII_FER_V (1);
  419. rmiifer |= RGMII_FER_RGMII << RGMII_FER_V(2);
  420. bis->bi_phymode[0] = BI_PHYMODE_ZMII;
  421. bis->bi_phymode[1] = BI_PHYMODE_ZMII;
  422. bis->bi_phymode[2] = BI_PHYMODE_RGMII;
  423. break;
  424. case 0:
  425. default:
  426. zmiifer = ZMII_FER_MII << ZMII_FER_V(devnum);
  427. rmiifer = 0x0;
  428. bis->bi_phymode[0] = BI_PHYMODE_ZMII;
  429. bis->bi_phymode[1] = BI_PHYMODE_ZMII;
  430. bis->bi_phymode[2] = BI_PHYMODE_ZMII;
  431. bis->bi_phymode[3] = BI_PHYMODE_ZMII;
  432. break;
  433. }
  434. /* Ensure we setup mdio for this devnum and ONLY this devnum */
  435. zmiifer |= (ZMII_FER_MDI) << ZMII_FER_V(devnum);
  436. out_be32((void *)ZMII0_FER, zmiifer);
  437. out_be32((void *)RGMII_FER, rmiifer);
  438. return ((int)pfc1);
  439. }
  440. #endif /* CONFIG_440_GX */
  441. #if defined(CONFIG_440EPX) || defined(CONFIG_440GRX)
  442. int ppc_4xx_eth_setup_bridge(int devnum, bd_t * bis)
  443. {
  444. unsigned long zmiifer=0x0;
  445. unsigned long pfc1;
  446. mfsdr(SDR0_PFC1, pfc1);
  447. pfc1 &= SDR0_PFC1_SELECT_MASK;
  448. switch (pfc1) {
  449. case SDR0_PFC1_SELECT_CONFIG_2:
  450. /* 1 x GMII port */
  451. out_be32((void *)ZMII0_FER, 0x00);
  452. out_be32((void *)RGMII_FER, 0x00000037);
  453. bis->bi_phymode[0] = BI_PHYMODE_GMII;
  454. bis->bi_phymode[1] = BI_PHYMODE_NONE;
  455. break;
  456. case SDR0_PFC1_SELECT_CONFIG_4:
  457. /* 2 x RGMII ports */
  458. out_be32((void *)ZMII0_FER, 0x00);
  459. out_be32((void *)RGMII_FER, 0x00000055);
  460. bis->bi_phymode[0] = BI_PHYMODE_RGMII;
  461. bis->bi_phymode[1] = BI_PHYMODE_RGMII;
  462. break;
  463. case SDR0_PFC1_SELECT_CONFIG_6:
  464. /* 2 x SMII ports */
  465. out_be32((void *)ZMII0_FER,
  466. ((ZMII_FER_SMII) << ZMII_FER_V(0)) |
  467. ((ZMII_FER_SMII) << ZMII_FER_V(1)));
  468. out_be32((void *)RGMII_FER, 0x00000000);
  469. bis->bi_phymode[0] = BI_PHYMODE_SMII;
  470. bis->bi_phymode[1] = BI_PHYMODE_SMII;
  471. break;
  472. case SDR0_PFC1_SELECT_CONFIG_1_2:
  473. /* only 1 x MII supported */
  474. out_be32((void *)ZMII0_FER, (ZMII_FER_MII) << ZMII_FER_V(0));
  475. out_be32((void *)RGMII_FER, 0x00000000);
  476. bis->bi_phymode[0] = BI_PHYMODE_MII;
  477. bis->bi_phymode[1] = BI_PHYMODE_NONE;
  478. break;
  479. default:
  480. break;
  481. }
  482. /* Ensure we setup mdio for this devnum and ONLY this devnum */
  483. zmiifer = in_be32((void *)ZMII0_FER);
  484. zmiifer |= (ZMII_FER_MDI) << ZMII_FER_V(devnum);
  485. out_be32((void *)ZMII0_FER, zmiifer);
  486. return ((int)0x0);
  487. }
  488. #endif /* CONFIG_440EPX */
  489. #if defined(CONFIG_405EX)
  490. int ppc_4xx_eth_setup_bridge(int devnum, bd_t * bis)
  491. {
  492. u32 rgmiifer = 0;
  493. /*
  494. * The 405EX(r)'s RGMII bridge can operate in one of several
  495. * modes, only one of which (2 x RGMII) allows the
  496. * simultaneous use of both EMACs on the 405EX.
  497. */
  498. switch (CONFIG_EMAC_PHY_MODE) {
  499. case EMAC_PHY_MODE_NONE:
  500. /* No ports */
  501. rgmiifer |= RGMII_FER_DIS << 0;
  502. rgmiifer |= RGMII_FER_DIS << 4;
  503. out_be32((void *)RGMII_FER, rgmiifer);
  504. bis->bi_phymode[0] = BI_PHYMODE_NONE;
  505. bis->bi_phymode[1] = BI_PHYMODE_NONE;
  506. break;
  507. case EMAC_PHY_MODE_NONE_RGMII:
  508. /* 1 x RGMII port on channel 0 */
  509. rgmiifer |= RGMII_FER_RGMII << 0;
  510. rgmiifer |= RGMII_FER_DIS << 4;
  511. out_be32((void *)RGMII_FER, rgmiifer);
  512. bis->bi_phymode[0] = BI_PHYMODE_RGMII;
  513. bis->bi_phymode[1] = BI_PHYMODE_NONE;
  514. break;
  515. case EMAC_PHY_MODE_RGMII_NONE:
  516. /* 1 x RGMII port on channel 1 */
  517. rgmiifer |= RGMII_FER_DIS << 0;
  518. rgmiifer |= RGMII_FER_RGMII << 4;
  519. out_be32((void *)RGMII_FER, rgmiifer);
  520. bis->bi_phymode[0] = BI_PHYMODE_NONE;
  521. bis->bi_phymode[1] = BI_PHYMODE_RGMII;
  522. break;
  523. case EMAC_PHY_MODE_RGMII_RGMII:
  524. /* 2 x RGMII ports */
  525. rgmiifer |= RGMII_FER_RGMII << 0;
  526. rgmiifer |= RGMII_FER_RGMII << 4;
  527. out_be32((void *)RGMII_FER, rgmiifer);
  528. bis->bi_phymode[0] = BI_PHYMODE_RGMII;
  529. bis->bi_phymode[1] = BI_PHYMODE_RGMII;
  530. break;
  531. case EMAC_PHY_MODE_NONE_GMII:
  532. /* 1 x GMII port on channel 0 */
  533. rgmiifer |= RGMII_FER_GMII << 0;
  534. rgmiifer |= RGMII_FER_DIS << 4;
  535. out_be32((void *)RGMII_FER, rgmiifer);
  536. bis->bi_phymode[0] = BI_PHYMODE_GMII;
  537. bis->bi_phymode[1] = BI_PHYMODE_NONE;
  538. break;
  539. case EMAC_PHY_MODE_NONE_MII:
  540. /* 1 x MII port on channel 0 */
  541. rgmiifer |= RGMII_FER_MII << 0;
  542. rgmiifer |= RGMII_FER_DIS << 4;
  543. out_be32((void *)RGMII_FER, rgmiifer);
  544. bis->bi_phymode[0] = BI_PHYMODE_MII;
  545. bis->bi_phymode[1] = BI_PHYMODE_NONE;
  546. break;
  547. case EMAC_PHY_MODE_GMII_NONE:
  548. /* 1 x GMII port on channel 1 */
  549. rgmiifer |= RGMII_FER_DIS << 0;
  550. rgmiifer |= RGMII_FER_GMII << 4;
  551. out_be32((void *)RGMII_FER, rgmiifer);
  552. bis->bi_phymode[0] = BI_PHYMODE_NONE;
  553. bis->bi_phymode[1] = BI_PHYMODE_GMII;
  554. break;
  555. case EMAC_PHY_MODE_MII_NONE:
  556. /* 1 x MII port on channel 1 */
  557. rgmiifer |= RGMII_FER_DIS << 0;
  558. rgmiifer |= RGMII_FER_MII << 4;
  559. out_be32((void *)RGMII_FER, rgmiifer);
  560. bis->bi_phymode[0] = BI_PHYMODE_NONE;
  561. bis->bi_phymode[1] = BI_PHYMODE_MII;
  562. break;
  563. default:
  564. break;
  565. }
  566. /* Ensure we setup mdio for this devnum and ONLY this devnum */
  567. rgmiifer = in_be32((void *)RGMII_FER);
  568. rgmiifer |= (1 << (19-devnum));
  569. out_be32((void *)RGMII_FER, rgmiifer);
  570. return ((int)0x0);
  571. }
  572. #endif /* CONFIG_405EX */
  573. #if defined(CONFIG_460EX) || defined(CONFIG_460GT)
  574. int ppc_4xx_eth_setup_bridge(int devnum, bd_t * bis)
  575. {
  576. u32 eth_cfg;
  577. u32 zmiifer; /* ZMII0_FER reg. */
  578. u32 rmiifer; /* RGMII0_FER reg. Bridge 0 */
  579. u32 rmiifer1; /* RGMII0_FER reg. Bridge 1 */
  580. int mode;
  581. zmiifer = 0;
  582. rmiifer = 0;
  583. rmiifer1 = 0;
  584. #if defined(CONFIG_460EX)
  585. mode = 9;
  586. mfsdr(SDR0_ETH_CFG, eth_cfg);
  587. if (((eth_cfg & SDR0_ETH_CFG_SGMII0_ENABLE) > 0) &&
  588. ((eth_cfg & SDR0_ETH_CFG_SGMII1_ENABLE) > 0))
  589. mode = 11; /* config SGMII */
  590. #else
  591. mode = 10;
  592. mfsdr(SDR0_ETH_CFG, eth_cfg);
  593. if (((eth_cfg & SDR0_ETH_CFG_SGMII0_ENABLE) > 0) &&
  594. ((eth_cfg & SDR0_ETH_CFG_SGMII1_ENABLE) > 0) &&
  595. ((eth_cfg & SDR0_ETH_CFG_SGMII2_ENABLE) > 0))
  596. mode = 12; /* config SGMII */
  597. #endif
  598. /* TODO:
  599. * NOTE: 460GT has 2 RGMII bridge cores:
  600. * emac0 ------ RGMII0_BASE
  601. * |
  602. * emac1 -----+
  603. *
  604. * emac2 ------ RGMII1_BASE
  605. * |
  606. * emac3 -----+
  607. *
  608. * 460EX has 1 RGMII bridge core:
  609. * and RGMII1_BASE is disabled
  610. * emac0 ------ RGMII0_BASE
  611. * |
  612. * emac1 -----+
  613. */
  614. /*
  615. * Right now only 2*RGMII is supported. Please extend when needed.
  616. * sr - 2008-02-19
  617. * Add SGMII support.
  618. * vg - 2008-07-28
  619. */
  620. switch (mode) {
  621. case 1:
  622. /* 1 MII - 460EX */
  623. /* GMC0 EMAC4_0, ZMII Bridge */
  624. zmiifer |= ZMII_FER_MII << ZMII_FER_V(0);
  625. bis->bi_phymode[0] = BI_PHYMODE_MII;
  626. bis->bi_phymode[1] = BI_PHYMODE_NONE;
  627. bis->bi_phymode[2] = BI_PHYMODE_NONE;
  628. bis->bi_phymode[3] = BI_PHYMODE_NONE;
  629. break;
  630. case 2:
  631. /* 2 MII - 460GT */
  632. /* GMC0 EMAC4_0, GMC1 EMAC4_2, ZMII Bridge */
  633. zmiifer |= ZMII_FER_MII << ZMII_FER_V(0);
  634. zmiifer |= ZMII_FER_MII << ZMII_FER_V(2);
  635. bis->bi_phymode[0] = BI_PHYMODE_MII;
  636. bis->bi_phymode[1] = BI_PHYMODE_NONE;
  637. bis->bi_phymode[2] = BI_PHYMODE_MII;
  638. bis->bi_phymode[3] = BI_PHYMODE_NONE;
  639. break;
  640. case 3:
  641. /* 2 RMII - 460EX */
  642. /* GMC0 EMAC4_0, GMC0 EMAC4_1, ZMII Bridge */
  643. zmiifer |= ZMII_FER_RMII << ZMII_FER_V(0);
  644. zmiifer |= ZMII_FER_RMII << ZMII_FER_V(1);
  645. bis->bi_phymode[0] = BI_PHYMODE_RMII;
  646. bis->bi_phymode[1] = BI_PHYMODE_RMII;
  647. bis->bi_phymode[2] = BI_PHYMODE_NONE;
  648. bis->bi_phymode[3] = BI_PHYMODE_NONE;
  649. break;
  650. case 4:
  651. /* 4 RMII - 460GT */
  652. /* GMC0 EMAC4_0, GMC0 EMAC4_1, GMC1 EMAC4_2, GMC1, EMAC4_3 */
  653. /* ZMII Bridge */
  654. zmiifer |= ZMII_FER_RMII << ZMII_FER_V(0);
  655. zmiifer |= ZMII_FER_RMII << ZMII_FER_V(1);
  656. zmiifer |= ZMII_FER_RMII << ZMII_FER_V(2);
  657. zmiifer |= ZMII_FER_RMII << ZMII_FER_V(3);
  658. bis->bi_phymode[0] = BI_PHYMODE_RMII;
  659. bis->bi_phymode[1] = BI_PHYMODE_RMII;
  660. bis->bi_phymode[2] = BI_PHYMODE_RMII;
  661. bis->bi_phymode[3] = BI_PHYMODE_RMII;
  662. break;
  663. case 5:
  664. /* 2 SMII - 460EX */
  665. /* GMC0 EMAC4_0, GMC0 EMAC4_1, ZMII Bridge */
  666. zmiifer |= ZMII_FER_SMII << ZMII_FER_V(0);
  667. zmiifer |= ZMII_FER_SMII << ZMII_FER_V(1);
  668. bis->bi_phymode[0] = BI_PHYMODE_SMII;
  669. bis->bi_phymode[1] = BI_PHYMODE_SMII;
  670. bis->bi_phymode[2] = BI_PHYMODE_NONE;
  671. bis->bi_phymode[3] = BI_PHYMODE_NONE;
  672. break;
  673. case 6:
  674. /* 4 SMII - 460GT */
  675. /* GMC0 EMAC4_0, GMC0 EMAC4_1, GMC0 EMAC4_3, GMC0 EMAC4_3 */
  676. /* ZMII Bridge */
  677. zmiifer |= ZMII_FER_SMII << ZMII_FER_V(0);
  678. zmiifer |= ZMII_FER_SMII << ZMII_FER_V(1);
  679. zmiifer |= ZMII_FER_SMII << ZMII_FER_V(2);
  680. zmiifer |= ZMII_FER_SMII << ZMII_FER_V(3);
  681. bis->bi_phymode[0] = BI_PHYMODE_SMII;
  682. bis->bi_phymode[1] = BI_PHYMODE_SMII;
  683. bis->bi_phymode[2] = BI_PHYMODE_SMII;
  684. bis->bi_phymode[3] = BI_PHYMODE_SMII;
  685. break;
  686. case 7:
  687. /* This is the default mode that we want for board bringup - Maple */
  688. /* 1 GMII - 460EX */
  689. /* GMC0 EMAC4_0, RGMII Bridge 0 */
  690. rmiifer |= RGMII_FER_MDIO(0);
  691. if (devnum == 0) {
  692. rmiifer |= RGMII_FER_GMII << RGMII_FER_V(2); /* CH0CFG - EMAC0 */
  693. bis->bi_phymode[0] = BI_PHYMODE_GMII;
  694. bis->bi_phymode[1] = BI_PHYMODE_NONE;
  695. bis->bi_phymode[2] = BI_PHYMODE_NONE;
  696. bis->bi_phymode[3] = BI_PHYMODE_NONE;
  697. } else {
  698. rmiifer |= RGMII_FER_GMII << RGMII_FER_V(3); /* CH1CFG - EMAC1 */
  699. bis->bi_phymode[0] = BI_PHYMODE_NONE;
  700. bis->bi_phymode[1] = BI_PHYMODE_GMII;
  701. bis->bi_phymode[2] = BI_PHYMODE_NONE;
  702. bis->bi_phymode[3] = BI_PHYMODE_NONE;
  703. }
  704. break;
  705. case 8:
  706. /* 2 GMII - 460GT */
  707. /* GMC0 EMAC4_0, RGMII Bridge 0 */
  708. /* GMC1 EMAC4_2, RGMII Bridge 1 */
  709. rmiifer |= RGMII_FER_GMII << RGMII_FER_V(2); /* CH0CFG - EMAC0 */
  710. rmiifer1 |= RGMII_FER_GMII << RGMII_FER_V(2); /* CH0CFG - EMAC2 */
  711. rmiifer |= RGMII_FER_MDIO(0); /* enable MDIO - EMAC0 */
  712. rmiifer1 |= RGMII_FER_MDIO(0); /* enable MDIO - EMAC2 */
  713. bis->bi_phymode[0] = BI_PHYMODE_GMII;
  714. bis->bi_phymode[1] = BI_PHYMODE_NONE;
  715. bis->bi_phymode[2] = BI_PHYMODE_GMII;
  716. bis->bi_phymode[3] = BI_PHYMODE_NONE;
  717. break;
  718. case 9:
  719. /* 2 RGMII - 460EX */
  720. /* GMC0 EMAC4_0, GMC0 EMAC4_1, RGMII Bridge 0 */
  721. rmiifer |= RGMII_FER_RGMII << RGMII_FER_V(2);
  722. rmiifer |= RGMII_FER_RGMII << RGMII_FER_V(3);
  723. rmiifer |= RGMII_FER_MDIO(0); /* enable MDIO - EMAC0 */
  724. bis->bi_phymode[0] = BI_PHYMODE_RGMII;
  725. bis->bi_phymode[1] = BI_PHYMODE_RGMII;
  726. bis->bi_phymode[2] = BI_PHYMODE_NONE;
  727. bis->bi_phymode[3] = BI_PHYMODE_NONE;
  728. break;
  729. case 10:
  730. /* 4 RGMII - 460GT */
  731. /* GMC0 EMAC4_0, GMC0 EMAC4_1, RGMII Bridge 0 */
  732. /* GMC1 EMAC4_2, GMC1 EMAC4_3, RGMII Bridge 1 */
  733. rmiifer |= RGMII_FER_RGMII << RGMII_FER_V(2);
  734. rmiifer |= RGMII_FER_RGMII << RGMII_FER_V(3);
  735. rmiifer1 |= RGMII_FER_RGMII << RGMII_FER_V(2);
  736. rmiifer1 |= RGMII_FER_RGMII << RGMII_FER_V(3);
  737. bis->bi_phymode[0] = BI_PHYMODE_RGMII;
  738. bis->bi_phymode[1] = BI_PHYMODE_RGMII;
  739. bis->bi_phymode[2] = BI_PHYMODE_RGMII;
  740. bis->bi_phymode[3] = BI_PHYMODE_RGMII;
  741. break;
  742. case 11:
  743. /* 2 SGMII - 460EX */
  744. bis->bi_phymode[0] = BI_PHYMODE_SGMII;
  745. bis->bi_phymode[1] = BI_PHYMODE_SGMII;
  746. bis->bi_phymode[2] = BI_PHYMODE_NONE;
  747. bis->bi_phymode[3] = BI_PHYMODE_NONE;
  748. break;
  749. case 12:
  750. /* 3 SGMII - 460GT */
  751. bis->bi_phymode[0] = BI_PHYMODE_SGMII;
  752. bis->bi_phymode[1] = BI_PHYMODE_SGMII;
  753. bis->bi_phymode[2] = BI_PHYMODE_SGMII;
  754. bis->bi_phymode[3] = BI_PHYMODE_NONE;
  755. break;
  756. default:
  757. break;
  758. }
  759. /* Set EMAC for MDIO */
  760. mfsdr(SDR0_ETH_CFG, eth_cfg);
  761. eth_cfg |= SDR0_ETH_CFG_MDIO_SEL_EMAC0;
  762. mtsdr(SDR0_ETH_CFG, eth_cfg);
  763. out_be32((void *)RGMII_FER, rmiifer);
  764. #if defined(CONFIG_460GT)
  765. out_be32((void *)RGMII_FER + RGMII1_BASE_OFFSET, rmiifer1);
  766. #endif
  767. /* bypass the TAHOE0/TAHOE1 cores for U-Boot */
  768. mfsdr(SDR0_ETH_CFG, eth_cfg);
  769. eth_cfg |= (SDR0_ETH_CFG_TAHOE0_BYPASS | SDR0_ETH_CFG_TAHOE1_BYPASS);
  770. mtsdr(SDR0_ETH_CFG, eth_cfg);
  771. return 0;
  772. }
  773. #endif /* CONFIG_460EX || CONFIG_460GT */
  774. static inline void *malloc_aligned(u32 size, u32 align)
  775. {
  776. return (void *)(((u32)malloc(size + align) + align - 1) &
  777. ~(align - 1));
  778. }
  779. static int ppc_4xx_eth_init (struct eth_device *dev, bd_t * bis)
  780. {
  781. int i;
  782. unsigned long reg = 0;
  783. unsigned long msr;
  784. unsigned long speed;
  785. unsigned long duplex;
  786. unsigned long failsafe;
  787. unsigned mode_reg;
  788. unsigned short devnum;
  789. unsigned short reg_short;
  790. #if defined(CONFIG_440GX) || \
  791. defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \
  792. defined(CONFIG_440SP) || defined(CONFIG_440SPE) || \
  793. defined(CONFIG_460EX) || defined(CONFIG_460GT) || \
  794. defined(CONFIG_405EX)
  795. u32 opbfreq;
  796. sys_info_t sysinfo;
  797. #if defined(CONFIG_440GX) || \
  798. defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \
  799. defined(CONFIG_460EX) || defined(CONFIG_460GT) || \
  800. defined(CONFIG_405EX)
  801. int ethgroup = -1;
  802. #endif
  803. #endif
  804. u32 bd_cached;
  805. u32 bd_uncached = 0;
  806. #ifdef CONFIG_4xx_DCACHE
  807. static u32 last_used_ea = 0;
  808. #endif
  809. #if defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \
  810. defined(CONFIG_460EX) || defined(CONFIG_460GT) || \
  811. defined(CONFIG_405EX)
  812. int rgmii_channel;
  813. #endif
  814. EMAC_4XX_HW_PST hw_p = dev->priv;
  815. /* before doing anything, figure out if we have a MAC address */
  816. /* if not, bail */
  817. if (memcmp (dev->enetaddr, "\0\0\0\0\0\0", 6) == 0) {
  818. printf("ERROR: ethaddr not set!\n");
  819. return -1;
  820. }
  821. #if defined(CONFIG_440GX) || \
  822. defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \
  823. defined(CONFIG_440SP) || defined(CONFIG_440SPE) || \
  824. defined(CONFIG_460EX) || defined(CONFIG_460GT) || \
  825. defined(CONFIG_405EX)
  826. /* Need to get the OPB frequency so we can access the PHY */
  827. get_sys_info (&sysinfo);
  828. #endif
  829. msr = mfmsr ();
  830. mtmsr (msr & ~(MSR_EE)); /* disable interrupts */
  831. devnum = hw_p->devnum;
  832. #ifdef INFO_4XX_ENET
  833. /* AS.HARNOIS
  834. * We should have :
  835. * hw_p->stats.pkts_handled <= hw_p->stats.pkts_rx <= hw_p->stats.pkts_handled+PKTBUFSRX
  836. * In the most cases hw_p->stats.pkts_handled = hw_p->stats.pkts_rx, but it
  837. * is possible that new packets (without relationship with
  838. * current transfer) have got the time to arrived before
  839. * netloop calls eth_halt
  840. */
  841. printf ("About preceeding transfer (eth%d):\n"
  842. "- Sent packet number %d\n"
  843. "- Received packet number %d\n"
  844. "- Handled packet number %d\n",
  845. hw_p->devnum,
  846. hw_p->stats.pkts_tx,
  847. hw_p->stats.pkts_rx, hw_p->stats.pkts_handled);
  848. hw_p->stats.pkts_tx = 0;
  849. hw_p->stats.pkts_rx = 0;
  850. hw_p->stats.pkts_handled = 0;
  851. hw_p->print_speed = 1; /* print speed message again next time */
  852. #endif
  853. hw_p->tx_err_index = 0; /* Transmit Error Index for tx_err_log */
  854. hw_p->rx_err_index = 0; /* Receive Error Index for rx_err_log */
  855. hw_p->rx_slot = 0; /* MAL Receive Slot */
  856. hw_p->rx_i_index = 0; /* Receive Interrupt Queue Index */
  857. hw_p->rx_u_index = 0; /* Receive User Queue Index */
  858. hw_p->tx_slot = 0; /* MAL Transmit Slot */
  859. hw_p->tx_i_index = 0; /* Transmit Interrupt Queue Index */
  860. hw_p->tx_u_index = 0; /* Transmit User Queue Index */
  861. #if defined(CONFIG_440) && !defined(CONFIG_440SP) && !defined(CONFIG_440SPE)
  862. /* set RMII mode */
  863. /* NOTE: 440GX spec states that mode is mutually exclusive */
  864. /* NOTE: Therefore, disable all other EMACS, since we handle */
  865. /* NOTE: only one emac at a time */
  866. reg = 0;
  867. out_be32((void *)ZMII0_FER, 0);
  868. udelay (100);
  869. #if defined(CONFIG_440GP) || defined(CONFIG_440EP) || defined(CONFIG_440GR)
  870. out_be32((void *)ZMII0_FER, (ZMII_FER_RMII | ZMII_FER_MDI) << ZMII_FER_V (devnum));
  871. #elif defined(CONFIG_440GX) || \
  872. defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \
  873. defined(CONFIG_460EX) || defined(CONFIG_460GT)
  874. ethgroup = ppc_4xx_eth_setup_bridge(devnum, bis);
  875. #endif
  876. out_be32((void *)ZMII0_SSR, ZMII0_SSR_SP << ZMII0_SSR_V(devnum));
  877. #endif /* defined(CONFIG_440) && !defined(CONFIG_440SP) */
  878. #if defined(CONFIG_405EX)
  879. ethgroup = ppc_4xx_eth_setup_bridge(devnum, bis);
  880. #endif
  881. sync();
  882. /* provide clocks for EMAC internal loopback */
  883. emac_loopback_enable(hw_p);
  884. /* EMAC RESET */
  885. out_be32((void *)EMAC0_MR0 + hw_p->hw_addr, EMAC_MR0_SRST);
  886. /* remove clocks for EMAC internal loopback */
  887. emac_loopback_disable(hw_p);
  888. failsafe = 1000;
  889. while ((in_be32((void *)EMAC0_MR0 + hw_p->hw_addr) & (EMAC_MR0_SRST)) && failsafe) {
  890. udelay (1000);
  891. failsafe--;
  892. }
  893. if (failsafe <= 0)
  894. printf("\nProblem resetting EMAC!\n");
  895. #if defined(CONFIG_440GX) || \
  896. defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \
  897. defined(CONFIG_440SP) || defined(CONFIG_440SPE) || \
  898. defined(CONFIG_460EX) || defined(CONFIG_460GT) || \
  899. defined(CONFIG_405EX)
  900. /* Whack the M1 register */
  901. mode_reg = 0x0;
  902. mode_reg &= ~0x00000038;
  903. opbfreq = sysinfo.freqOPB / 1000000;
  904. if (opbfreq <= 50);
  905. else if (opbfreq <= 66)
  906. mode_reg |= EMAC_MR1_OBCI_66;
  907. else if (opbfreq <= 83)
  908. mode_reg |= EMAC_MR1_OBCI_83;
  909. else if (opbfreq <= 100)
  910. mode_reg |= EMAC_MR1_OBCI_100;
  911. else
  912. mode_reg |= EMAC_MR1_OBCI_GT100;
  913. out_be32((void *)EMAC0_MR1 + hw_p->hw_addr, mode_reg);
  914. #endif /* defined(CONFIG_440GX) || defined(CONFIG_440SP) */
  915. #if defined(CONFIG_GPCS_PHY_ADDR) || defined(CONFIG_GPCS_PHY1_ADDR) || \
  916. defined(CONFIG_GPCS_PHY2_ADDR) || defined(CONFIG_GPCS_PHY3_ADDR)
  917. if (bis->bi_phymode[devnum] == BI_PHYMODE_SGMII) {
  918. /*
  919. * In SGMII mode, GPCS access is needed for
  920. * communication with the internal SGMII SerDes.
  921. */
  922. switch (devnum) {
  923. #if defined(CONFIG_GPCS_PHY_ADDR)
  924. case 0:
  925. reg = CONFIG_GPCS_PHY_ADDR;
  926. break;
  927. #endif
  928. #if defined(CONFIG_GPCS_PHY1_ADDR)
  929. case 1:
  930. reg = CONFIG_GPCS_PHY1_ADDR;
  931. break;
  932. #endif
  933. #if defined(CONFIG_GPCS_PHY2_ADDR)
  934. case 2:
  935. reg = CONFIG_GPCS_PHY2_ADDR;
  936. break;
  937. #endif
  938. #if defined(CONFIG_GPCS_PHY3_ADDR)
  939. case 3:
  940. reg = CONFIG_GPCS_PHY3_ADDR;
  941. break;
  942. #endif
  943. }
  944. mode_reg = in_be32((void *)EMAC0_MR1 + hw_p->hw_addr);
  945. mode_reg |= EMAC_MR1_MF_1000GPCS | EMAC_MR1_IPPA_SET(reg);
  946. out_be32((void *)EMAC0_MR1 + hw_p->hw_addr, mode_reg);
  947. /* Configure GPCS interface to recommended setting for SGMII */
  948. miiphy_reset(dev->name, reg);
  949. miiphy_write(dev->name, reg, 0x04, 0x8120); /* AsymPause, FDX */
  950. miiphy_write(dev->name, reg, 0x07, 0x2801); /* msg_pg, toggle */
  951. miiphy_write(dev->name, reg, 0x00, 0x0140); /* 1Gbps, FDX */
  952. }
  953. #endif /* defined(CONFIG_GPCS_PHY_ADDR) */
  954. /* wait for PHY to complete auto negotiation */
  955. reg_short = 0;
  956. switch (devnum) {
  957. case 0:
  958. reg = CONFIG_PHY_ADDR;
  959. break;
  960. #if defined (CONFIG_PHY1_ADDR)
  961. case 1:
  962. reg = CONFIG_PHY1_ADDR;
  963. break;
  964. #endif
  965. #if defined (CONFIG_PHY2_ADDR)
  966. case 2:
  967. reg = CONFIG_PHY2_ADDR;
  968. break;
  969. #endif
  970. #if defined (CONFIG_PHY3_ADDR)
  971. case 3:
  972. reg = CONFIG_PHY3_ADDR;
  973. break;
  974. #endif
  975. default:
  976. reg = CONFIG_PHY_ADDR;
  977. break;
  978. }
  979. bis->bi_phynum[devnum] = reg;
  980. if (reg == CONFIG_FIXED_PHY)
  981. goto get_speed;
  982. #if defined(CONFIG_PHY_RESET)
  983. /*
  984. * Reset the phy, only if its the first time through
  985. * otherwise, just check the speeds & feeds
  986. */
  987. if (hw_p->first_init == 0) {
  988. #if defined(CONFIG_M88E1111_PHY)
  989. miiphy_write (dev->name, reg, 0x14, 0x0ce3);
  990. miiphy_write (dev->name, reg, 0x18, 0x4101);
  991. miiphy_write (dev->name, reg, 0x09, 0x0e00);
  992. miiphy_write (dev->name, reg, 0x04, 0x01e1);
  993. #if defined(CONFIG_M88E1111_DISABLE_FIBER)
  994. miiphy_read(dev->name, reg, 0x1b, &reg_short);
  995. reg_short |= 0x8000;
  996. miiphy_write(dev->name, reg, 0x1b, reg_short);
  997. #endif
  998. #endif
  999. #if defined(CONFIG_M88E1112_PHY)
  1000. if (bis->bi_phymode[devnum] == BI_PHYMODE_SGMII) {
  1001. /*
  1002. * Marvell 88E1112 PHY needs to have the SGMII MAC
  1003. * interace (page 2) properly configured to
  1004. * communicate with the 460EX/GT GPCS interface.
  1005. */
  1006. /* Set access to Page 2 */
  1007. miiphy_write(dev->name, reg, 0x16, 0x0002);
  1008. miiphy_write(dev->name, reg, 0x00, 0x0040); /* 1Gbps */
  1009. miiphy_read(dev->name, reg, 0x1a, &reg_short);
  1010. reg_short |= 0x8000; /* bypass Auto-Negotiation */
  1011. miiphy_write(dev->name, reg, 0x1a, reg_short);
  1012. miiphy_reset(dev->name, reg); /* reset MAC interface */
  1013. /* Reset access to Page 0 */
  1014. miiphy_write(dev->name, reg, 0x16, 0x0000);
  1015. }
  1016. #endif /* defined(CONFIG_M88E1112_PHY) */
  1017. miiphy_reset (dev->name, reg);
  1018. #if defined(CONFIG_440GX) || \
  1019. defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \
  1020. defined(CONFIG_460EX) || defined(CONFIG_460GT) || \
  1021. defined(CONFIG_405EX)
  1022. #if defined(CONFIG_CIS8201_PHY)
  1023. /*
  1024. * Cicada 8201 PHY needs to have an extended register whacked
  1025. * for RGMII mode.
  1026. */
  1027. if (((devnum == 2) || (devnum == 3)) && (4 == ethgroup)) {
  1028. #if defined(CONFIG_CIS8201_SHORT_ETCH)
  1029. miiphy_write (dev->name, reg, 23, 0x1300);
  1030. #else
  1031. miiphy_write (dev->name, reg, 23, 0x1000);
  1032. #endif
  1033. /*
  1034. * Vitesse VSC8201/Cicada CIS8201 errata:
  1035. * Interoperability problem with Intel 82547EI phys
  1036. * This work around (provided by Vitesse) changes
  1037. * the default timer convergence from 8ms to 12ms
  1038. */
  1039. miiphy_write (dev->name, reg, 0x1f, 0x2a30);
  1040. miiphy_write (dev->name, reg, 0x08, 0x0200);
  1041. miiphy_write (dev->name, reg, 0x1f, 0x52b5);
  1042. miiphy_write (dev->name, reg, 0x02, 0x0004);
  1043. miiphy_write (dev->name, reg, 0x01, 0x0671);
  1044. miiphy_write (dev->name, reg, 0x00, 0x8fae);
  1045. miiphy_write (dev->name, reg, 0x1f, 0x2a30);
  1046. miiphy_write (dev->name, reg, 0x08, 0x0000);
  1047. miiphy_write (dev->name, reg, 0x1f, 0x0000);
  1048. /* end Vitesse/Cicada errata */
  1049. }
  1050. #endif /* defined(CONFIG_CIS8201_PHY) */
  1051. #if defined(CONFIG_ET1011C_PHY)
  1052. /*
  1053. * Agere ET1011c PHY needs to have an extended register whacked
  1054. * for RGMII mode.
  1055. */
  1056. if (((devnum == 2) || (devnum ==3)) && (4 == ethgroup)) {
  1057. miiphy_read (dev->name, reg, 0x16, &reg_short);
  1058. reg_short &= ~(0x7);
  1059. reg_short |= 0x6; /* RGMII DLL Delay*/
  1060. miiphy_write (dev->name, reg, 0x16, reg_short);
  1061. miiphy_read (dev->name, reg, 0x17, &reg_short);
  1062. reg_short &= ~(0x40);
  1063. miiphy_write (dev->name, reg, 0x17, reg_short);
  1064. miiphy_write(dev->name, reg, 0x1c, 0x74f0);
  1065. }
  1066. #endif /* defined(CONFIG_ET1011C_PHY) */
  1067. #endif /* defined(CONFIG_440GX) ... */
  1068. /* Start/Restart autonegotiation */
  1069. phy_setup_aneg (dev->name, reg);
  1070. udelay (1000);
  1071. }
  1072. #endif /* defined(CONFIG_PHY_RESET) */
  1073. miiphy_read (dev->name, reg, MII_BMSR, &reg_short);
  1074. /*
  1075. * Wait if PHY is capable of autonegotiation and autonegotiation is not complete
  1076. */
  1077. if ((reg_short & BMSR_ANEGCAPABLE)
  1078. && !(reg_short & BMSR_ANEGCOMPLETE)) {
  1079. puts ("Waiting for PHY auto negotiation to complete");
  1080. i = 0;
  1081. while (!(reg_short & BMSR_ANEGCOMPLETE)) {
  1082. /*
  1083. * Timeout reached ?
  1084. */
  1085. if (i > PHY_AUTONEGOTIATE_TIMEOUT) {
  1086. puts (" TIMEOUT !\n");
  1087. break;
  1088. }
  1089. if ((i++ % 1000) == 0) {
  1090. putc ('.');
  1091. }
  1092. udelay (1000); /* 1 ms */
  1093. miiphy_read (dev->name, reg, MII_BMSR, &reg_short);
  1094. }
  1095. puts (" done\n");
  1096. udelay (500000); /* another 500 ms (results in faster booting) */
  1097. }
  1098. get_speed:
  1099. if (reg == CONFIG_FIXED_PHY) {
  1100. for (i = 0; i < ARRAY_SIZE(fixed_phy_port); i++) {
  1101. if (devnum == fixed_phy_port[i].devnum) {
  1102. speed = fixed_phy_port[i].speed;
  1103. duplex = fixed_phy_port[i].duplex;
  1104. break;
  1105. }
  1106. }
  1107. if (i == ARRAY_SIZE(fixed_phy_port)) {
  1108. printf("ERROR: PHY (%s) not configured correctly!\n",
  1109. dev->name);
  1110. return -1;
  1111. }
  1112. } else {
  1113. speed = miiphy_speed(dev->name, reg);
  1114. duplex = miiphy_duplex(dev->name, reg);
  1115. }
  1116. if (hw_p->print_speed) {
  1117. hw_p->print_speed = 0;
  1118. printf ("ENET Speed is %d Mbps - %s duplex connection (EMAC%d)\n",
  1119. (int) speed, (duplex == HALF) ? "HALF" : "FULL",
  1120. hw_p->devnum);
  1121. }
  1122. #if defined(CONFIG_440) && \
  1123. !defined(CONFIG_440SP) && !defined(CONFIG_440SPE) && \
  1124. !defined(CONFIG_440EPX) && !defined(CONFIG_440GRX) && \
  1125. !defined(CONFIG_460EX) && !defined(CONFIG_460GT)
  1126. #if defined(CONFIG_440EP) || defined(CONFIG_440GR)
  1127. mfsdr(SDR0_MFR, reg);
  1128. if (speed == 100) {
  1129. reg = (reg & ~SDR0_MFR_ZMII_MODE_MASK) | SDR0_MFR_ZMII_MODE_RMII_100M;
  1130. } else {
  1131. reg = (reg & ~SDR0_MFR_ZMII_MODE_MASK) | SDR0_MFR_ZMII_MODE_RMII_10M;
  1132. }
  1133. mtsdr(SDR0_MFR, reg);
  1134. #endif
  1135. /* Set ZMII/RGMII speed according to the phy link speed */
  1136. reg = in_be32((void *)ZMII0_SSR);
  1137. if ( (speed == 100) || (speed == 1000) )
  1138. out_be32((void *)ZMII0_SSR, reg | (ZMII0_SSR_SP << ZMII0_SSR_V (devnum)));
  1139. else
  1140. out_be32((void *)ZMII0_SSR, reg & (~(ZMII0_SSR_SP << ZMII0_SSR_V (devnum))));
  1141. if ((devnum == 2) || (devnum == 3)) {
  1142. if (speed == 1000)
  1143. reg = (RGMII_SSR_SP_1000MBPS << RGMII_SSR_V (devnum));
  1144. else if (speed == 100)
  1145. reg = (RGMII_SSR_SP_100MBPS << RGMII_SSR_V (devnum));
  1146. else if (speed == 10)
  1147. reg = (RGMII_SSR_SP_10MBPS << RGMII_SSR_V (devnum));
  1148. else {
  1149. printf("Error in RGMII Speed\n");
  1150. return -1;
  1151. }
  1152. out_be32((void *)RGMII_SSR, reg);
  1153. }
  1154. #endif /* defined(CONFIG_440) && !defined(CONFIG_440SP) */
  1155. #if defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \
  1156. defined(CONFIG_460EX) || defined(CONFIG_460GT) || \
  1157. defined(CONFIG_405EX)
  1158. if (devnum >= 2)
  1159. rgmii_channel = devnum - 2;
  1160. else
  1161. rgmii_channel = devnum;
  1162. if (speed == 1000)
  1163. reg = (RGMII_SSR_SP_1000MBPS << RGMII_SSR_V(rgmii_channel));
  1164. else if (speed == 100)
  1165. reg = (RGMII_SSR_SP_100MBPS << RGMII_SSR_V(rgmii_channel));
  1166. else if (speed == 10)
  1167. reg = (RGMII_SSR_SP_10MBPS << RGMII_SSR_V(rgmii_channel));
  1168. else {
  1169. printf("Error in RGMII Speed\n");
  1170. return -1;
  1171. }
  1172. out_be32((void *)RGMII_SSR, reg);
  1173. #if defined(CONFIG_460GT)
  1174. if ((devnum == 2) || (devnum == 3))
  1175. out_be32((void *)RGMII_SSR + RGMII1_BASE_OFFSET, reg);
  1176. #endif
  1177. #endif
  1178. /* set the Mal configuration reg */
  1179. #if defined(CONFIG_440GX) || \
  1180. defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \
  1181. defined(CONFIG_440SP) || defined(CONFIG_440SPE) || \
  1182. defined(CONFIG_460EX) || defined(CONFIG_460GT) || \
  1183. defined(CONFIG_405EX)
  1184. mtdcr (MAL0_CFG, MAL_CR_PLBB | MAL_CR_OPBBL | MAL_CR_LEA |
  1185. MAL_CR_PLBLT_DEFAULT | MAL_CR_EOPIE | 0x00330000);
  1186. #else
  1187. mtdcr (MAL0_CFG, MAL_CR_PLBB | MAL_CR_OPBBL | MAL_CR_LEA | MAL_CR_PLBLT_DEFAULT);
  1188. /* Errata 1.12: MAL_1 -- Disable MAL bursting */
  1189. if (get_pvr() == PVR_440GP_RB) {
  1190. mtdcr (MAL0_CFG, mfdcr(MAL0_CFG) & ~MAL_CR_PLBB);
  1191. }
  1192. #endif
  1193. /*
  1194. * Malloc MAL buffer desciptors, make sure they are
  1195. * aligned on cache line boundary size
  1196. * (401/403/IOP480 = 16, 405 = 32)
  1197. * and doesn't cross cache block boundaries.
  1198. */
  1199. if (hw_p->first_init == 0) {
  1200. debug("*** Allocating descriptor memory ***\n");
  1201. bd_cached = (u32)malloc_aligned(MAL_ALLOC_SIZE, 4096);
  1202. if (!bd_cached) {
  1203. printf("%s: Error allocating MAL descriptor buffers!\n", __func__);
  1204. return -1;
  1205. }
  1206. #ifdef CONFIG_4xx_DCACHE
  1207. flush_dcache_range(bd_cached, bd_cached + MAL_ALLOC_SIZE);
  1208. if (!last_used_ea)
  1209. #if defined(CONFIG_SYS_MEM_TOP_HIDE)
  1210. bd_uncached = bis->bi_memsize + CONFIG_SYS_MEM_TOP_HIDE;
  1211. #else
  1212. bd_uncached = bis->bi_memsize;
  1213. #endif
  1214. else
  1215. bd_uncached = last_used_ea + MAL_ALLOC_SIZE;
  1216. last_used_ea = bd_uncached;
  1217. program_tlb(bd_cached, bd_uncached, MAL_ALLOC_SIZE,
  1218. TLB_WORD2_I_ENABLE);
  1219. #else
  1220. bd_uncached = bd_cached;
  1221. #endif
  1222. hw_p->tx_phys = bd_cached;
  1223. hw_p->rx_phys = bd_cached + MAL_TX_DESC_SIZE;
  1224. hw_p->tx = (mal_desc_t *)(bd_uncached);
  1225. hw_p->rx = (mal_desc_t *)(bd_uncached + MAL_TX_DESC_SIZE);
  1226. debug("hw_p->tx=%08x, hw_p->rx=%08x\n", hw_p->tx, hw_p->rx);
  1227. }
  1228. for (i = 0; i < NUM_TX_BUFF; i++) {
  1229. hw_p->tx[i].ctrl = 0;
  1230. hw_p->tx[i].data_len = 0;
  1231. if (hw_p->first_init == 0)
  1232. hw_p->txbuf_ptr = malloc_aligned(MAL_ALLOC_SIZE,
  1233. L1_CACHE_BYTES);
  1234. hw_p->tx[i].data_ptr = hw_p->txbuf_ptr;
  1235. if ((NUM_TX_BUFF - 1) == i)
  1236. hw_p->tx[i].ctrl |= MAL_TX_CTRL_WRAP;
  1237. hw_p->tx_run[i] = -1;
  1238. debug("TX_BUFF %d @ 0x%08lx\n", i, (u32)hw_p->tx[i].data_ptr);
  1239. }
  1240. for (i = 0; i < NUM_RX_BUFF; i++) {
  1241. hw_p->rx[i].ctrl = 0;
  1242. hw_p->rx[i].data_len = 0;
  1243. hw_p->rx[i].data_ptr = (char *)NetRxPackets[i];
  1244. if ((NUM_RX_BUFF - 1) == i)
  1245. hw_p->rx[i].ctrl |= MAL_RX_CTRL_WRAP;
  1246. hw_p->rx[i].ctrl |= MAL_RX_CTRL_EMPTY | MAL_RX_CTRL_INTR;
  1247. hw_p->rx_ready[i] = -1;
  1248. debug("RX_BUFF %d @ 0x%08lx\n", i, (u32)hw_p->rx[i].data_ptr);
  1249. }
  1250. reg = 0x00000000;
  1251. reg |= dev->enetaddr[0]; /* set high address */
  1252. reg = reg << 8;
  1253. reg |= dev->enetaddr[1];
  1254. out_be32((void *)EMAC0_IAH + hw_p->hw_addr, reg);
  1255. reg = 0x00000000;
  1256. reg |= dev->enetaddr[2]; /* set low address */
  1257. reg = reg << 8;
  1258. reg |= dev->enetaddr[3];
  1259. reg = reg << 8;
  1260. reg |= dev->enetaddr[4];
  1261. reg = reg << 8;
  1262. reg |= dev->enetaddr[5];
  1263. out_be32((void *)EMAC0_IAL + hw_p->hw_addr, reg);
  1264. switch (devnum) {
  1265. case 1:
  1266. /* setup MAL tx & rx channel pointers */
  1267. #if defined (CONFIG_405EP) || defined (CONFIG_440EP) || defined (CONFIG_440GR)
  1268. mtdcr (MAL0_TXCTP2R, hw_p->tx_phys);
  1269. #else
  1270. mtdcr (MAL0_TXCTP1R, hw_p->tx_phys);
  1271. #endif
  1272. #if defined(CONFIG_440)
  1273. mtdcr (MAL0_TXBADDR, 0x0);
  1274. mtdcr (MAL0_RXBADDR, 0x0);
  1275. #endif
  1276. #if defined(CONFIG_460EX) || defined(CONFIG_460GT)
  1277. mtdcr (MAL0_RXCTP8R, hw_p->rx_phys);
  1278. /* set RX buffer size */
  1279. mtdcr (MAL0_RCBS8, ENET_MAX_MTU_ALIGNED / 16);
  1280. #else
  1281. mtdcr (MAL0_RXCTP1R, hw_p->rx_phys);
  1282. /* set RX buffer size */
  1283. mtdcr (MAL0_RCBS1, ENET_MAX_MTU_ALIGNED / 16);
  1284. #endif
  1285. break;
  1286. #if defined (CONFIG_440GX)
  1287. case 2:
  1288. /* setup MAL tx & rx channel pointers */
  1289. mtdcr (MAL0_TXBADDR, 0x0);
  1290. mtdcr (MAL0_RXBADDR, 0x0);
  1291. mtdcr (MAL0_TXCTP2R, hw_p->tx_phys);
  1292. mtdcr (MAL0_RXCTP2R, hw_p->rx_phys);
  1293. /* set RX buffer size */
  1294. mtdcr (MAL0_RCBS2, ENET_MAX_MTU_ALIGNED / 16);
  1295. break;
  1296. case 3:
  1297. /* setup MAL tx & rx channel pointers */
  1298. mtdcr (MAL0_TXBADDR, 0x0);
  1299. mtdcr (MAL0_TXCTP3R, hw_p->tx_phys);
  1300. mtdcr (MAL0_RXBADDR, 0x0);
  1301. mtdcr (MAL0_RXCTP3R, hw_p->rx_phys);
  1302. /* set RX buffer size */
  1303. mtdcr (MAL0_RCBS3, ENET_MAX_MTU_ALIGNED / 16);
  1304. break;
  1305. #endif /* CONFIG_440GX */
  1306. #if defined (CONFIG_460GT)
  1307. case 2:
  1308. /* setup MAL tx & rx channel pointers */
  1309. mtdcr (MAL0_TXBADDR, 0x0);
  1310. mtdcr (MAL0_RXBADDR, 0x0);
  1311. mtdcr (MAL0_TXCTP2R, hw_p->tx_phys);
  1312. mtdcr (MAL0_RXCTP16R, hw_p->rx_phys);
  1313. /* set RX buffer size */
  1314. mtdcr (MAL0_RCBS16, ENET_MAX_MTU_ALIGNED / 16);
  1315. break;
  1316. case 3:
  1317. /* setup MAL tx & rx channel pointers */
  1318. mtdcr (MAL0_TXBADDR, 0x0);
  1319. mtdcr (MAL0_RXBADDR, 0x0);
  1320. mtdcr (MAL0_TXCTP3R, hw_p->tx_phys);
  1321. mtdcr (MAL0_RXCTP24R, hw_p->rx_phys);
  1322. /* set RX buffer size */
  1323. mtdcr (MAL0_RCBS24, ENET_MAX_MTU_ALIGNED / 16);
  1324. break;
  1325. #endif /* CONFIG_460GT */
  1326. case 0:
  1327. default:
  1328. /* setup MAL tx & rx channel pointers */
  1329. #if defined(CONFIG_440)
  1330. mtdcr (MAL0_TXBADDR, 0x0);
  1331. mtdcr (MAL0_RXBADDR, 0x0);
  1332. #endif
  1333. mtdcr (MAL0_TXCTP0R, hw_p->tx_phys);
  1334. mtdcr (MAL0_RXCTP0R, hw_p->rx_phys);
  1335. /* set RX buffer size */
  1336. mtdcr (MAL0_RCBS0, ENET_MAX_MTU_ALIGNED / 16);
  1337. break;
  1338. }
  1339. /* Enable MAL transmit and receive channels */
  1340. #if defined(CONFIG_405EP) || defined(CONFIG_440EP) || defined(CONFIG_440GR)
  1341. mtdcr (MAL0_TXCASR, (MAL_TXRX_CASR >> (hw_p->devnum*2)));
  1342. #else
  1343. mtdcr (MAL0_TXCASR, (MAL_TXRX_CASR >> hw_p->devnum));
  1344. #endif
  1345. mtdcr (MAL0_RXCASR, (MAL_TXRX_CASR >> hw_p->devnum));
  1346. /* set transmit enable & receive enable */
  1347. out_be32((void *)EMAC0_MR0 + hw_p->hw_addr, EMAC_MR0_TXE | EMAC_MR0_RXE);
  1348. mode_reg = in_be32((void *)EMAC0_MR1 + hw_p->hw_addr);
  1349. /* set rx-/tx-fifo size */
  1350. mode_reg = (mode_reg & ~EMAC_MR1_FIFO_MASK) | EMAC_MR1_FIFO_SIZE;
  1351. /* set speed */
  1352. if (speed == _1000BASET) {
  1353. #if defined(CONFIG_440SP) || defined(CONFIG_440SPE)
  1354. unsigned long pfc1;
  1355. mfsdr (SDR0_PFC1, pfc1);
  1356. pfc1 |= SDR0_PFC1_EM_1000;
  1357. mtsdr (SDR0_PFC1, pfc1);
  1358. #endif
  1359. mode_reg = mode_reg | EMAC_MR1_MF_1000MBPS | EMAC_MR1_IST;
  1360. } else if (speed == _100BASET)
  1361. mode_reg = mode_reg | EMAC_MR1_MF_100MBPS | EMAC_MR1_IST;
  1362. else
  1363. mode_reg = mode_reg & ~0x00C00000; /* 10 MBPS */
  1364. if (duplex == FULL)
  1365. mode_reg = mode_reg | 0x80000000 | EMAC_MR1_IST;
  1366. out_be32((void *)EMAC0_MR1 + hw_p->hw_addr, mode_reg);
  1367. /* Enable broadcast and indvidual address */
  1368. /* TBS: enabling runts as some misbehaved nics will send runts */
  1369. out_be32((void *)EMAC0_RXM + hw_p->hw_addr, EMAC_RMR_BAE | EMAC_RMR_IAE);
  1370. /* we probably need to set the tx mode1 reg? maybe at tx time */
  1371. /* set transmit request threshold register */
  1372. out_be32((void *)EMAC0_TRTR + hw_p->hw_addr, 0x18000000); /* 256 byte threshold */
  1373. /* set receive low/high water mark register */
  1374. #if defined(CONFIG_440)
  1375. /* 440s has a 64 byte burst length */
  1376. out_be32((void *)EMAC0_RX_HI_LO_WMARK + hw_p->hw_addr, 0x80009000);
  1377. #else
  1378. /* 405s have a 16 byte burst length */
  1379. out_be32((void *)EMAC0_RX_HI_LO_WMARK + hw_p->hw_addr, 0x0f002000);
  1380. #endif /* defined(CONFIG_440) */
  1381. out_be32((void *)EMAC0_TMR1 + hw_p->hw_addr, 0xf8640000);
  1382. /* Set fifo limit entry in tx mode 0 */
  1383. out_be32((void *)EMAC0_TMR0 + hw_p->hw_addr, 0x00000003);
  1384. /* Frame gap set */
  1385. out_be32((void *)EMAC0_I_FRAME_GAP_REG + hw_p->hw_addr, 0x00000008);
  1386. /* Set EMAC IER */
  1387. hw_p->emac_ier = EMAC_ISR_PTLE | EMAC_ISR_BFCS | EMAC_ISR_ORE | EMAC_ISR_IRE;
  1388. if (speed == _100BASET)
  1389. hw_p->emac_ier = hw_p->emac_ier | EMAC_ISR_SYE;
  1390. out_be32((void *)EMAC0_ISR + hw_p->hw_addr, 0xffffffff); /* clear pending interrupts */
  1391. out_be32((void *)EMAC0_IER + hw_p->hw_addr, hw_p->emac_ier);
  1392. if (hw_p->first_init == 0) {
  1393. /*
  1394. * Connect interrupt service routines
  1395. */
  1396. irq_install_handler(ETH_IRQ_NUM(hw_p->devnum),
  1397. (interrupt_handler_t *) enetInt, dev);
  1398. }
  1399. mtmsr (msr); /* enable interrupts again */
  1400. hw_p->bis = bis;
  1401. hw_p->first_init = 1;
  1402. return 0;
  1403. }
  1404. static int ppc_4xx_eth_send (struct eth_device *dev, volatile void *ptr,
  1405. int len)
  1406. {
  1407. struct enet_frame *ef_ptr;
  1408. ulong time_start, time_now;
  1409. unsigned long temp_txm0;
  1410. EMAC_4XX_HW_PST hw_p = dev->priv;
  1411. ef_ptr = (struct enet_frame *) ptr;
  1412. /*-----------------------------------------------------------------------+
  1413. * Copy in our address into the frame.
  1414. *-----------------------------------------------------------------------*/
  1415. (void) memcpy (ef_ptr->source_addr, dev->enetaddr, ENET_ADDR_LENGTH);
  1416. /*-----------------------------------------------------------------------+
  1417. * If frame is too long or too short, modify length.
  1418. *-----------------------------------------------------------------------*/
  1419. /* TBS: where does the fragment go???? */
  1420. if (len > ENET_MAX_MTU)
  1421. len = ENET_MAX_MTU;
  1422. /* memcpy ((void *) &tx_buff[tx_slot], (const void *) ptr, len); */
  1423. memcpy ((void *) hw_p->txbuf_ptr, (const void *) ptr, len);
  1424. flush_dcache_range((u32)hw_p->txbuf_ptr, (u32)hw_p->txbuf_ptr + len);
  1425. /*-----------------------------------------------------------------------+
  1426. * set TX Buffer busy, and send it
  1427. *-----------------------------------------------------------------------*/
  1428. hw_p->tx[hw_p->tx_slot].ctrl = (MAL_TX_CTRL_LAST |
  1429. EMAC_TX_CTRL_GFCS | EMAC_TX_CTRL_GP) &
  1430. ~(EMAC_TX_CTRL_ISA | EMAC_TX_CTRL_RSA);
  1431. if ((NUM_TX_BUFF - 1) == hw_p->tx_slot)
  1432. hw_p->tx[hw_p->tx_slot].ctrl |= MAL_TX_CTRL_WRAP;
  1433. hw_p->tx[hw_p->tx_slot].data_len = (short) len;
  1434. hw_p->tx[hw_p->tx_slot].ctrl |= MAL_TX_CTRL_READY;
  1435. sync();
  1436. out_be32((void *)EMAC0_TMR0 + hw_p->hw_addr,
  1437. in_be32((void *)EMAC0_TMR0 + hw_p->hw_addr) | EMAC_TMR0_GNP0);
  1438. #ifdef INFO_4XX_ENET
  1439. hw_p->stats.pkts_tx++;
  1440. #endif
  1441. /*-----------------------------------------------------------------------+
  1442. * poll unitl the packet is sent and then make sure it is OK
  1443. *-----------------------------------------------------------------------*/
  1444. time_start = get_timer (0);
  1445. while (1) {
  1446. temp_txm0 = in_be32((void *)EMAC0_TMR0 + hw_p->hw_addr);
  1447. /* loop until either TINT turns on or 3 seconds elapse */
  1448. if ((temp_txm0 & EMAC_TMR0_GNP0) != 0) {
  1449. /* transmit is done, so now check for errors
  1450. * If there is an error, an interrupt should
  1451. * happen when we return
  1452. */
  1453. time_now = get_timer (0);
  1454. if ((time_now - time_start) > 3000) {
  1455. return (-1);
  1456. }
  1457. } else {
  1458. return (len);
  1459. }
  1460. }
  1461. }
  1462. int enetInt (struct eth_device *dev)
  1463. {
  1464. int serviced;
  1465. int rc = -1; /* default to not us */
  1466. u32 mal_isr;
  1467. u32 emac_isr = 0;
  1468. u32 mal_eob;
  1469. u32 uic_mal;
  1470. u32 uic_mal_err;
  1471. u32 uic_emac;
  1472. u32 uic_emac_b;
  1473. EMAC_4XX_HW_PST hw_p;
  1474. /*
  1475. * Because the mal is generic, we need to get the current
  1476. * eth device
  1477. */
  1478. dev = eth_get_dev();
  1479. hw_p = dev->priv;
  1480. /* enter loop that stays in interrupt code until nothing to service */
  1481. do {
  1482. serviced = 0;
  1483. uic_mal = mfdcr(UIC_BASE_MAL + UIC_MSR);
  1484. uic_mal_err = mfdcr(UIC_BASE_MAL_ERR + UIC_MSR);
  1485. uic_emac = mfdcr(UIC_BASE_EMAC + UIC_MSR);
  1486. uic_emac_b = mfdcr(UIC_BASE_EMAC_B + UIC_MSR);
  1487. if (!(uic_mal & (UIC_MAL_RXEOB | UIC_MAL_TXEOB))
  1488. && !(uic_mal_err & (UIC_MAL_SERR | UIC_MAL_TXDE | UIC_MAL_RXDE))
  1489. && !(uic_emac & UIC_ETHx) && !(uic_emac_b & UIC_ETHxB)) {
  1490. /* not for us */
  1491. return (rc);
  1492. }
  1493. /* get and clear controller status interrupts */
  1494. /* look at MAL and EMAC error interrupts */
  1495. if (uic_mal_err & (UIC_MAL_SERR | UIC_MAL_TXDE | UIC_MAL_RXDE)) {
  1496. /* we have a MAL error interrupt */
  1497. mal_isr = mfdcr(MAL0_ESR);
  1498. mal_err(dev, mal_isr, uic_mal_err,
  1499. MAL_UIC_DEF, MAL_UIC_ERR);
  1500. /* clear MAL error interrupt status bits */
  1501. mtdcr(UIC_BASE_MAL_ERR + UIC_SR,
  1502. UIC_MAL_SERR | UIC_MAL_TXDE | UIC_MAL_RXDE);
  1503. return -1;
  1504. }
  1505. /* look for EMAC errors */
  1506. if ((uic_emac & UIC_ETHx) || (uic_emac_b & UIC_ETHxB)) {
  1507. emac_isr = in_be32((void *)EMAC0_ISR + hw_p->hw_addr);
  1508. emac_err(dev, emac_isr);
  1509. /* clear EMAC error interrupt status bits */
  1510. mtdcr(UIC_BASE_EMAC + UIC_SR, UIC_ETHx);
  1511. mtdcr(UIC_BASE_EMAC_B + UIC_SR, UIC_ETHxB);
  1512. return -1;
  1513. }
  1514. /* handle MAX TX EOB interrupt from a tx */
  1515. if (uic_mal & UIC_MAL_TXEOB) {
  1516. /* clear MAL interrupt status bits */
  1517. mal_eob = mfdcr(MAL0_TXEOBISR);
  1518. mtdcr(MAL0_TXEOBISR, mal_eob);
  1519. mtdcr(UIC_BASE_MAL + UIC_SR, UIC_MAL_TXEOB);
  1520. /* indicate that we serviced an interrupt */
  1521. serviced = 1;
  1522. rc = 0;
  1523. }
  1524. /* handle MAL RX EOB interrupt from a receive */
  1525. /* check for EOB on valid channels */
  1526. if (uic_mal & UIC_MAL_RXEOB) {
  1527. mal_eob = mfdcr(MAL0_RXEOBISR);
  1528. if (mal_eob &
  1529. (0x80000000 >> (hw_p->devnum * MAL_RX_CHAN_MUL))) {
  1530. /* push packet to upper layer */
  1531. enet_rcv(dev, emac_isr);
  1532. /* clear MAL interrupt status bits */
  1533. mtdcr(UIC_BASE_MAL + UIC_SR, UIC_MAL_RXEOB);
  1534. /* indicate that we serviced an interrupt */
  1535. serviced = 1;
  1536. rc = 0;
  1537. }
  1538. }
  1539. #if defined(CONFIG_405EZ)
  1540. /*
  1541. * On 405EZ the RX-/TX-interrupts are coalesced into
  1542. * one IRQ bit in the UIC. We need to acknowledge the
  1543. * RX-/TX-interrupts in the SDR0_ICINTSTAT reg as well.
  1544. */
  1545. mtsdr(SDR0_ICINTSTAT,
  1546. SDR_ICRX_STAT | SDR_ICTX0_STAT | SDR_ICTX1_STAT);
  1547. #endif /* defined(CONFIG_405EZ) */
  1548. } while (serviced);
  1549. return (rc);
  1550. }
  1551. /*-----------------------------------------------------------------------------+
  1552. * MAL Error Routine
  1553. *-----------------------------------------------------------------------------*/
  1554. static void mal_err (struct eth_device *dev, unsigned long isr,
  1555. unsigned long uic, unsigned long maldef,
  1556. unsigned long mal_errr)
  1557. {
  1558. EMAC_4XX_HW_PST hw_p = dev->priv;
  1559. mtdcr (MAL0_ESR, isr); /* clear interrupt */
  1560. /* clear DE interrupt */
  1561. mtdcr (MAL0_TXDEIR, 0xC0000000);
  1562. mtdcr (MAL0_RXDEIR, 0x80000000);
  1563. #ifdef INFO_4XX_ENET
  1564. printf ("\nMAL error occured.... ISR = %lx UIC = = %lx MAL_DEF = %lx MAL_ERR= %lx \n", isr, uic, maldef, mal_errr);
  1565. #endif
  1566. eth_init (hw_p->bis); /* start again... */
  1567. }
  1568. /*-----------------------------------------------------------------------------+
  1569. * EMAC Error Routine
  1570. *-----------------------------------------------------------------------------*/
  1571. static void emac_err (struct eth_device *dev, unsigned long isr)
  1572. {
  1573. EMAC_4XX_HW_PST hw_p = dev->priv;
  1574. printf ("EMAC%d error occured.... ISR = %lx\n", hw_p->devnum, isr);
  1575. out_be32((void *)EMAC0_ISR + hw_p->hw_addr, isr);
  1576. }
  1577. /*-----------------------------------------------------------------------------+
  1578. * enet_rcv() handles the ethernet receive data
  1579. *-----------------------------------------------------------------------------*/
  1580. static void enet_rcv (struct eth_device *dev, unsigned long malisr)
  1581. {
  1582. struct enet_frame *ef_ptr;
  1583. unsigned long data_len;
  1584. unsigned long rx_eob_isr;
  1585. EMAC_4XX_HW_PST hw_p = dev->priv;
  1586. int handled = 0;
  1587. int i;
  1588. int loop_count = 0;
  1589. rx_eob_isr = mfdcr (MAL0_RXEOBISR);
  1590. if ((0x80000000 >> (hw_p->devnum * MAL_RX_CHAN_MUL)) & rx_eob_isr) {
  1591. /* clear EOB */
  1592. mtdcr (MAL0_RXEOBISR, rx_eob_isr);
  1593. /* EMAC RX done */
  1594. while (1) { /* do all */
  1595. i = hw_p->rx_slot;
  1596. if ((MAL_RX_CTRL_EMPTY & hw_p->rx[i].ctrl)
  1597. || (loop_count >= NUM_RX_BUFF))
  1598. break;
  1599. loop_count++;
  1600. handled++;
  1601. data_len = (unsigned long) hw_p->rx[i].data_len & 0x0fff; /* Get len */
  1602. if (data_len) {
  1603. if (data_len > ENET_MAX_MTU) /* Check len */
  1604. data_len = 0;
  1605. else {
  1606. if (EMAC_RX_ERRORS & hw_p->rx[i].ctrl) { /* Check Errors */
  1607. data_len = 0;
  1608. hw_p->stats.rx_err_log[hw_p->
  1609. rx_err_index]
  1610. = hw_p->rx[i].ctrl;
  1611. hw_p->rx_err_index++;
  1612. if (hw_p->rx_err_index ==
  1613. MAX_ERR_LOG)
  1614. hw_p->rx_err_index =
  1615. 0;
  1616. } /* emac_erros */
  1617. } /* data_len < max mtu */
  1618. } /* if data_len */
  1619. if (!data_len) { /* no data */
  1620. hw_p->rx[i].ctrl |= MAL_RX_CTRL_EMPTY; /* Free Recv Buffer */
  1621. hw_p->stats.data_len_err++; /* Error at Rx */
  1622. }
  1623. /* !data_len */
  1624. /* AS.HARNOIS */
  1625. /* Check if user has already eaten buffer */
  1626. /* if not => ERROR */
  1627. else if (hw_p->rx_ready[hw_p->rx_i_index] != -1) {
  1628. if (hw_p->is_receiving)
  1629. printf ("ERROR : Receive buffers are full!\n");
  1630. break;
  1631. } else {
  1632. hw_p->stats.rx_frames++;
  1633. hw_p->stats.rx += data_len;
  1634. ef_ptr = (struct enet_frame *) hw_p->rx[i].
  1635. data_ptr;
  1636. #ifdef INFO_4XX_ENET
  1637. hw_p->stats.pkts_rx++;
  1638. #endif
  1639. /* AS.HARNOIS
  1640. * use ring buffer
  1641. */
  1642. hw_p->rx_ready[hw_p->rx_i_index] = i;
  1643. hw_p->rx_i_index++;
  1644. if (NUM_RX_BUFF == hw_p->rx_i_index)
  1645. hw_p->rx_i_index = 0;
  1646. hw_p->rx_slot++;
  1647. if (NUM_RX_BUFF == hw_p->rx_slot)
  1648. hw_p->rx_slot = 0;
  1649. /* AS.HARNOIS
  1650. * free receive buffer only when
  1651. * buffer has been handled (eth_rx)
  1652. rx[i].ctrl |= MAL_RX_CTRL_EMPTY;
  1653. */
  1654. } /* if data_len */
  1655. } /* while */
  1656. } /* if EMACK_RXCHL */
  1657. }
  1658. static int ppc_4xx_eth_rx (struct eth_device *dev)
  1659. {
  1660. int length;
  1661. int user_index;
  1662. unsigned long msr;
  1663. EMAC_4XX_HW_PST hw_p = dev->priv;
  1664. hw_p->is_receiving = 1; /* tell driver */
  1665. for (;;) {
  1666. /* AS.HARNOIS
  1667. * use ring buffer and
  1668. * get index from rx buffer desciptor queue
  1669. */
  1670. user_index = hw_p->rx_ready[hw_p->rx_u_index];
  1671. if (user_index == -1) {
  1672. length = -1;
  1673. break; /* nothing received - leave for() loop */
  1674. }
  1675. msr = mfmsr ();
  1676. mtmsr (msr & ~(MSR_EE));
  1677. length = hw_p->rx[user_index].data_len & 0x0fff;
  1678. /* Pass the packet up to the protocol layers. */
  1679. /* NetReceive(NetRxPackets[rxIdx], length - 4); */
  1680. /* NetReceive(NetRxPackets[i], length); */
  1681. invalidate_dcache_range((u32)hw_p->rx[user_index].data_ptr,
  1682. (u32)hw_p->rx[user_index].data_ptr +
  1683. length - 4);
  1684. NetReceive (NetRxPackets[user_index], length - 4);
  1685. /* Free Recv Buffer */
  1686. hw_p->rx[user_index].ctrl |= MAL_RX_CTRL_EMPTY;
  1687. /* Free rx buffer descriptor queue */
  1688. hw_p->rx_ready[hw_p->rx_u_index] = -1;
  1689. hw_p->rx_u_index++;
  1690. if (NUM_RX_BUFF == hw_p->rx_u_index)
  1691. hw_p->rx_u_index = 0;
  1692. #ifdef INFO_4XX_ENET
  1693. hw_p->stats.pkts_handled++;
  1694. #endif
  1695. mtmsr (msr); /* Enable IRQ's */
  1696. }
  1697. hw_p->is_receiving = 0; /* tell driver */
  1698. return length;
  1699. }
  1700. int ppc_4xx_eth_initialize (bd_t * bis)
  1701. {
  1702. static int virgin = 0;
  1703. struct eth_device *dev;
  1704. int eth_num = 0;
  1705. EMAC_4XX_HW_PST hw = NULL;
  1706. u8 ethaddr[4 + CONFIG_EMAC_NR_START][6];
  1707. u32 hw_addr[4];
  1708. u32 mal_ier;
  1709. #if defined(CONFIG_440GX)
  1710. unsigned long pfc1;
  1711. mfsdr (SDR0_PFC1, pfc1);
  1712. pfc1 &= ~(0x01e00000);
  1713. pfc1 |= 0x01200000;
  1714. mtsdr (SDR0_PFC1, pfc1);
  1715. #endif
  1716. /* first clear all mac-addresses */
  1717. for (eth_num = 0; eth_num < LAST_EMAC_NUM; eth_num++)
  1718. memcpy(ethaddr[eth_num], "\0\0\0\0\0\0", 6);
  1719. for (eth_num = 0; eth_num < LAST_EMAC_NUM; eth_num++) {
  1720. int ethaddr_idx = eth_num + CONFIG_EMAC_NR_START;
  1721. switch (eth_num) {
  1722. default: /* fall through */
  1723. case 0:
  1724. eth_getenv_enetaddr("ethaddr", ethaddr[ethaddr_idx]);
  1725. hw_addr[eth_num] = 0x0;
  1726. break;
  1727. #ifdef CONFIG_HAS_ETH1
  1728. case 1:
  1729. eth_getenv_enetaddr("eth1addr", ethaddr[ethaddr_idx]);
  1730. hw_addr[eth_num] = 0x100;
  1731. break;
  1732. #endif
  1733. #ifdef CONFIG_HAS_ETH2
  1734. case 2:
  1735. eth_getenv_enetaddr("eth2addr", ethaddr[ethaddr_idx]);
  1736. #if defined(CONFIG_460GT)
  1737. hw_addr[eth_num] = 0x300;
  1738. #else
  1739. hw_addr[eth_num] = 0x400;
  1740. #endif
  1741. break;
  1742. #endif
  1743. #ifdef CONFIG_HAS_ETH3
  1744. case 3:
  1745. eth_getenv_enetaddr("eth3addr", ethaddr[ethaddr_idx]);
  1746. #if defined(CONFIG_460GT)
  1747. hw_addr[eth_num] = 0x400;
  1748. #else
  1749. hw_addr[eth_num] = 0x600;
  1750. #endif
  1751. break;
  1752. #endif
  1753. }
  1754. }
  1755. /* set phy num and mode */
  1756. bis->bi_phynum[0] = CONFIG_PHY_ADDR;
  1757. bis->bi_phymode[0] = 0;
  1758. #if defined(CONFIG_PHY1_ADDR)
  1759. bis->bi_phynum[1] = CONFIG_PHY1_ADDR;
  1760. bis->bi_phymode[1] = 0;
  1761. #endif
  1762. #if defined(CONFIG_440GX)
  1763. bis->bi_phynum[2] = CONFIG_PHY2_ADDR;
  1764. bis->bi_phynum[3] = CONFIG_PHY3_ADDR;
  1765. bis->bi_phymode[2] = 2;
  1766. bis->bi_phymode[3] = 2;
  1767. #endif
  1768. #if defined(CONFIG_440GX) || \
  1769. defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \
  1770. defined(CONFIG_405EX)
  1771. ppc_4xx_eth_setup_bridge(0, bis);
  1772. #endif
  1773. for (eth_num = 0; eth_num < LAST_EMAC_NUM; eth_num++) {
  1774. /*
  1775. * See if we can actually bring up the interface,
  1776. * otherwise, skip it
  1777. */
  1778. if (memcmp (ethaddr[eth_num], "\0\0\0\0\0\0", 6) == 0) {
  1779. bis->bi_phymode[eth_num] = BI_PHYMODE_NONE;
  1780. continue;
  1781. }
  1782. /* Allocate device structure */
  1783. dev = (struct eth_device *) malloc (sizeof (*dev));
  1784. if (dev == NULL) {
  1785. printf ("ppc_4xx_eth_initialize: "
  1786. "Cannot allocate eth_device %d\n", eth_num);
  1787. return (-1);
  1788. }
  1789. memset(dev, 0, sizeof(*dev));
  1790. /* Allocate our private use data */
  1791. hw = (EMAC_4XX_HW_PST) malloc (sizeof (*hw));
  1792. if (hw == NULL) {
  1793. printf ("ppc_4xx_eth_initialize: "
  1794. "Cannot allocate private hw data for eth_device %d",
  1795. eth_num);
  1796. free (dev);
  1797. return (-1);
  1798. }
  1799. memset(hw, 0, sizeof(*hw));
  1800. hw->hw_addr = hw_addr[eth_num];
  1801. memcpy (dev->enetaddr, ethaddr[eth_num], 6);
  1802. hw->devnum = eth_num;
  1803. hw->print_speed = 1;
  1804. sprintf (dev->name, "ppc_4xx_eth%d", eth_num - CONFIG_EMAC_NR_START);
  1805. dev->priv = (void *) hw;
  1806. dev->init = ppc_4xx_eth_init;
  1807. dev->halt = ppc_4xx_eth_halt;
  1808. dev->send = ppc_4xx_eth_send;
  1809. dev->recv = ppc_4xx_eth_rx;
  1810. if (0 == virgin) {
  1811. /* set the MAL IER ??? names may change with new spec ??? */
  1812. #if defined(CONFIG_440SPE) || \
  1813. defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \
  1814. defined(CONFIG_460EX) || defined(CONFIG_460GT) || \
  1815. defined(CONFIG_405EX)
  1816. mal_ier =
  1817. MAL_IER_PT | MAL_IER_PRE | MAL_IER_PWE |
  1818. MAL_IER_DE | MAL_IER_OTE | MAL_IER_OE | MAL_IER_PE ;
  1819. #else
  1820. mal_ier =
  1821. MAL_IER_DE | MAL_IER_NE | MAL_IER_TE |
  1822. MAL_IER_OPBE | MAL_IER_PLBE;
  1823. #endif
  1824. mtdcr (MAL0_ESR, 0xffffffff); /* clear pending interrupts */
  1825. mtdcr (MAL0_TXDEIR, 0xffffffff); /* clear pending interrupts */
  1826. mtdcr (MAL0_RXDEIR, 0xffffffff); /* clear pending interrupts */
  1827. mtdcr (MAL0_IER, mal_ier);
  1828. /* install MAL interrupt handler */
  1829. irq_install_handler (VECNUM_MAL_SERR,
  1830. (interrupt_handler_t *) enetInt,
  1831. dev);
  1832. irq_install_handler (VECNUM_MAL_TXEOB,
  1833. (interrupt_handler_t *) enetInt,
  1834. dev);
  1835. irq_install_handler (VECNUM_MAL_RXEOB,
  1836. (interrupt_handler_t *) enetInt,
  1837. dev);
  1838. irq_install_handler (VECNUM_MAL_TXDE,
  1839. (interrupt_handler_t *) enetInt,
  1840. dev);
  1841. irq_install_handler (VECNUM_MAL_RXDE,
  1842. (interrupt_handler_t *) enetInt,
  1843. dev);
  1844. virgin = 1;
  1845. }
  1846. eth_register (dev);
  1847. #if defined(CONFIG_MII) || defined(CONFIG_CMD_MII)
  1848. miiphy_register (dev->name,
  1849. emac4xx_miiphy_read, emac4xx_miiphy_write);
  1850. #endif
  1851. } /* end for each supported device */
  1852. return 0;
  1853. }