cpm_85xx.h 36 KB

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  1. /*
  2. * MPC85xx Communication Processor Module
  3. * Copyright (c) 2003,Motorola Inc.
  4. * Xianghua Xiao (X.Xiao@motorola.com)
  5. *
  6. * MPC8260 Communication Processor Module.
  7. * Copyright (c) 1999 Dan Malek (dmalek@jlc.net)
  8. *
  9. * This file contains structures and information for the communication
  10. * processor channels found in the dual port RAM or parameter RAM.
  11. * All CPM control and status is available through the MPC8260 internal
  12. * memory map. See immap.h for details.
  13. */
  14. #ifndef __CPM_85XX__
  15. #define __CPM_85XX__
  16. #include <asm/immap_85xx.h>
  17. /* CPM Command register.
  18. */
  19. #define CPM_CR_RST ((uint)0x80000000)
  20. #define CPM_CR_PAGE ((uint)0x7c000000)
  21. #define CPM_CR_SBLOCK ((uint)0x03e00000)
  22. #define CPM_CR_FLG ((uint)0x00010000)
  23. #define CPM_CR_MCN ((uint)0x00003fc0)
  24. #define CPM_CR_OPCODE ((uint)0x0000000f)
  25. /* Device sub-block and page codes.
  26. */
  27. #define CPM_CR_SCC1_SBLOCK (0x04)
  28. #define CPM_CR_SCC2_SBLOCK (0x05)
  29. #define CPM_CR_SCC3_SBLOCK (0x06)
  30. #define CPM_CR_SCC4_SBLOCK (0x07)
  31. #define CPM_CR_SMC1_SBLOCK (0x08)
  32. #define CPM_CR_SMC2_SBLOCK (0x09)
  33. #define CPM_CR_SPI_SBLOCK (0x0a)
  34. #define CPM_CR_I2C_SBLOCK (0x0b)
  35. #define CPM_CR_TIMER_SBLOCK (0x0f)
  36. #define CPM_CR_RAND_SBLOCK (0x0e)
  37. #define CPM_CR_FCC1_SBLOCK (0x10)
  38. #define CPM_CR_FCC2_SBLOCK (0x11)
  39. #define CPM_CR_FCC3_SBLOCK (0x12)
  40. #define CPM_CR_MCC1_SBLOCK (0x1c)
  41. #define CPM_CR_SCC1_PAGE (0x00)
  42. #define CPM_CR_SCC2_PAGE (0x01)
  43. #define CPM_CR_SCC3_PAGE (0x02)
  44. #define CPM_CR_SCC4_PAGE (0x03)
  45. #define CPM_CR_SPI_PAGE (0x09)
  46. #define CPM_CR_I2C_PAGE (0x0a)
  47. #define CPM_CR_TIMER_PAGE (0x0a)
  48. #define CPM_CR_RAND_PAGE (0x0a)
  49. #define CPM_CR_FCC1_PAGE (0x04)
  50. #define CPM_CR_FCC2_PAGE (0x05)
  51. #define CPM_CR_FCC3_PAGE (0x06)
  52. #define CPM_CR_MCC1_PAGE (0x07)
  53. #define CPM_CR_MCC2_PAGE (0x08)
  54. /* Some opcodes (there are more...later)
  55. */
  56. #define CPM_CR_INIT_TRX ((ushort)0x0000)
  57. #define CPM_CR_INIT_RX ((ushort)0x0001)
  58. #define CPM_CR_INIT_TX ((ushort)0x0002)
  59. #define CPM_CR_HUNT_MODE ((ushort)0x0003)
  60. #define CPM_CR_STOP_TX ((ushort)0x0004)
  61. #define CPM_CR_RESTART_TX ((ushort)0x0006)
  62. #define CPM_CR_SET_GADDR ((ushort)0x0008)
  63. #define mk_cr_cmd(PG, SBC, MCN, OP) \
  64. ((PG << 26) | (SBC << 21) | (MCN << 6) | OP)
  65. /* Dual Port RAM addresses. The first 16K is available for almost
  66. * any CPM use, so we put the BDs there. The first 128 bytes are
  67. * used for SMC1 and SMC2 parameter RAM, so we start allocating
  68. * BDs above that. All of this must change when we start
  69. * downloading RAM microcode.
  70. */
  71. #define CPM_DATAONLY_BASE ((uint)128)
  72. #define CPM_DP_NOSPACE ((uint)0x7FFFFFFF)
  73. #if defined(CONFIG_MPC8541) || defined(CONFIG_MPC8555)
  74. #define CPM_FCC_SPECIAL_BASE ((uint)0x00009000)
  75. #define CPM_DATAONLY_SIZE ((uint)(8 * 1024) - CPM_DATAONLY_BASE)
  76. #else /* MPC8540, MPC8560 */
  77. #define CPM_FCC_SPECIAL_BASE ((uint)0x0000B000)
  78. #define CPM_DATAONLY_SIZE ((uint)(16 * 1024) - CPM_DATAONLY_BASE)
  79. #endif
  80. /* The number of pages of host memory we allocate for CPM. This is
  81. * done early in kernel initialization to get physically contiguous
  82. * pages.
  83. */
  84. #define NUM_CPM_HOST_PAGES 2
  85. /* Export the base address of the communication processor registers
  86. * and dual port ram.
  87. */
  88. /*extern cpm8560_t *cpmp; Pointer to comm processor */
  89. uint m8560_cpm_dpalloc(uint size, uint align);
  90. uint m8560_cpm_hostalloc(uint size, uint align);
  91. void m8560_cpm_setbrg(uint brg, uint rate);
  92. void m8560_cpm_fastbrg(uint brg, uint rate, int div16);
  93. void m8560_cpm_extcbrg(uint brg, uint rate, uint extclk, int pinsel);
  94. /* Buffer descriptors used by many of the CPM protocols.
  95. */
  96. typedef struct cpm_buf_desc {
  97. ushort cbd_sc; /* Status and Control */
  98. ushort cbd_datlen; /* Data length in buffer */
  99. uint cbd_bufaddr; /* Buffer address in host memory */
  100. } cbd_t;
  101. #define BD_SC_EMPTY ((ushort)0x8000) /* Receive is empty */
  102. #define BD_SC_READY ((ushort)0x8000) /* Transmit is ready */
  103. #define BD_SC_WRAP ((ushort)0x2000) /* Last buffer descriptor */
  104. #define BD_SC_INTRPT ((ushort)0x1000) /* Interrupt on change */
  105. #define BD_SC_LAST ((ushort)0x0800) /* Last buffer in frame */
  106. #define BD_SC_CM ((ushort)0x0200) /* Continous mode */
  107. #define BD_SC_ID ((ushort)0x0100) /* Rec'd too many idles */
  108. #define BD_SC_P ((ushort)0x0100) /* xmt preamble */
  109. #define BD_SC_BR ((ushort)0x0020) /* Break received */
  110. #define BD_SC_FR ((ushort)0x0010) /* Framing error */
  111. #define BD_SC_PR ((ushort)0x0008) /* Parity error */
  112. #define BD_SC_OV ((ushort)0x0002) /* Overrun */
  113. #define BD_SC_CD ((ushort)0x0001) /* ?? */
  114. /* Function code bits, usually generic to devices.
  115. */
  116. #define CPMFCR_GBL ((u_char)0x20) /* Set memory snooping */
  117. #define CPMFCR_EB ((u_char)0x10) /* Set big endian byte order */
  118. #define CPMFCR_TC2 ((u_char)0x04) /* Transfer code 2 value */
  119. #define CPMFCR_DTB ((u_char)0x02) /* Use local bus for data when set */
  120. #define CPMFCR_BDB ((u_char)0x01) /* Use local bus for BD when set */
  121. /* Parameter RAM offsets from the base.
  122. */
  123. #define CPM_POST_WORD_ADDR 0x80FC /* steal a long at the end of SCC1 */
  124. #define PROFF_SCC1 ((uint)0x8000)
  125. #define PROFF_SCC2 ((uint)0x8100)
  126. #define PROFF_SCC3 ((uint)0x8200)
  127. #define PROFF_SCC4 ((uint)0x8300)
  128. #define PROFF_FCC1 ((uint)0x8400)
  129. #define PROFF_FCC2 ((uint)0x8500)
  130. #define PROFF_FCC3 ((uint)0x8600)
  131. #define PROFF_MCC1 ((uint)0x8700)
  132. #define PROFF_MCC2 ((uint)0x8800)
  133. #define PROFF_SPI_BASE ((uint)0x89fc)
  134. #define PROFF_TIMERS ((uint)0x8ae0)
  135. #define PROFF_REVNUM ((uint)0x8af0)
  136. #define PROFF_RAND ((uint)0x8af8)
  137. #define PROFF_I2C_BASE ((uint)0x8afc)
  138. /* Baud rate generators.
  139. */
  140. #define CPM_BRG_RST ((uint)0x00020000)
  141. #define CPM_BRG_EN ((uint)0x00010000)
  142. #define CPM_BRG_EXTC_INT ((uint)0x00000000)
  143. #define CPM_BRG_EXTC_CLK3_9 ((uint)0x00004000)
  144. #define CPM_BRG_EXTC_CLK5_15 ((uint)0x00008000)
  145. #define CPM_BRG_ATB ((uint)0x00002000)
  146. #define CPM_BRG_CD_MASK ((uint)0x00001ffe)
  147. #define CPM_BRG_DIV16 ((uint)0x00000001)
  148. /* SCCs.
  149. */
  150. #define SCC_GSMRH_IRP ((uint)0x00040000)
  151. #define SCC_GSMRH_GDE ((uint)0x00010000)
  152. #define SCC_GSMRH_TCRC_CCITT ((uint)0x00008000)
  153. #define SCC_GSMRH_TCRC_BISYNC ((uint)0x00004000)
  154. #define SCC_GSMRH_TCRC_HDLC ((uint)0x00000000)
  155. #define SCC_GSMRH_REVD ((uint)0x00002000)
  156. #define SCC_GSMRH_TRX ((uint)0x00001000)
  157. #define SCC_GSMRH_TTX ((uint)0x00000800)
  158. #define SCC_GSMRH_CDP ((uint)0x00000400)
  159. #define SCC_GSMRH_CTSP ((uint)0x00000200)
  160. #define SCC_GSMRH_CDS ((uint)0x00000100)
  161. #define SCC_GSMRH_CTSS ((uint)0x00000080)
  162. #define SCC_GSMRH_TFL ((uint)0x00000040)
  163. #define SCC_GSMRH_RFW ((uint)0x00000020)
  164. #define SCC_GSMRH_TXSY ((uint)0x00000010)
  165. #define SCC_GSMRH_SYNL16 ((uint)0x0000000c)
  166. #define SCC_GSMRH_SYNL8 ((uint)0x00000008)
  167. #define SCC_GSMRH_SYNL4 ((uint)0x00000004)
  168. #define SCC_GSMRH_RTSM ((uint)0x00000002)
  169. #define SCC_GSMRH_RSYN ((uint)0x00000001)
  170. #define SCC_GSMRL_SIR ((uint)0x80000000) /* SCC2 only */
  171. #define SCC_GSMRL_EDGE_NONE ((uint)0x60000000)
  172. #define SCC_GSMRL_EDGE_NEG ((uint)0x40000000)
  173. #define SCC_GSMRL_EDGE_POS ((uint)0x20000000)
  174. #define SCC_GSMRL_EDGE_BOTH ((uint)0x00000000)
  175. #define SCC_GSMRL_TCI ((uint)0x10000000)
  176. #define SCC_GSMRL_TSNC_3 ((uint)0x0c000000)
  177. #define SCC_GSMRL_TSNC_4 ((uint)0x08000000)
  178. #define SCC_GSMRL_TSNC_14 ((uint)0x04000000)
  179. #define SCC_GSMRL_TSNC_INF ((uint)0x00000000)
  180. #define SCC_GSMRL_RINV ((uint)0x02000000)
  181. #define SCC_GSMRL_TINV ((uint)0x01000000)
  182. #define SCC_GSMRL_TPL_128 ((uint)0x00c00000)
  183. #define SCC_GSMRL_TPL_64 ((uint)0x00a00000)
  184. #define SCC_GSMRL_TPL_48 ((uint)0x00800000)
  185. #define SCC_GSMRL_TPL_32 ((uint)0x00600000)
  186. #define SCC_GSMRL_TPL_16 ((uint)0x00400000)
  187. #define SCC_GSMRL_TPL_8 ((uint)0x00200000)
  188. #define SCC_GSMRL_TPL_NONE ((uint)0x00000000)
  189. #define SCC_GSMRL_TPP_ALL1 ((uint)0x00180000)
  190. #define SCC_GSMRL_TPP_01 ((uint)0x00100000)
  191. #define SCC_GSMRL_TPP_10 ((uint)0x00080000)
  192. #define SCC_GSMRL_TPP_ZEROS ((uint)0x00000000)
  193. #define SCC_GSMRL_TEND ((uint)0x00040000)
  194. #define SCC_GSMRL_TDCR_32 ((uint)0x00030000)
  195. #define SCC_GSMRL_TDCR_16 ((uint)0x00020000)
  196. #define SCC_GSMRL_TDCR_8 ((uint)0x00010000)
  197. #define SCC_GSMRL_TDCR_1 ((uint)0x00000000)
  198. #define SCC_GSMRL_RDCR_32 ((uint)0x0000c000)
  199. #define SCC_GSMRL_RDCR_16 ((uint)0x00008000)
  200. #define SCC_GSMRL_RDCR_8 ((uint)0x00004000)
  201. #define SCC_GSMRL_RDCR_1 ((uint)0x00000000)
  202. #define SCC_GSMRL_RENC_DFMAN ((uint)0x00003000)
  203. #define SCC_GSMRL_RENC_MANCH ((uint)0x00002000)
  204. #define SCC_GSMRL_RENC_FM0 ((uint)0x00001000)
  205. #define SCC_GSMRL_RENC_NRZI ((uint)0x00000800)
  206. #define SCC_GSMRL_RENC_NRZ ((uint)0x00000000)
  207. #define SCC_GSMRL_TENC_DFMAN ((uint)0x00000600)
  208. #define SCC_GSMRL_TENC_MANCH ((uint)0x00000400)
  209. #define SCC_GSMRL_TENC_FM0 ((uint)0x00000200)
  210. #define SCC_GSMRL_TENC_NRZI ((uint)0x00000100)
  211. #define SCC_GSMRL_TENC_NRZ ((uint)0x00000000)
  212. #define SCC_GSMRL_DIAG_LE ((uint)0x000000c0) /* Loop and echo */
  213. #define SCC_GSMRL_DIAG_ECHO ((uint)0x00000080)
  214. #define SCC_GSMRL_DIAG_LOOP ((uint)0x00000040)
  215. #define SCC_GSMRL_DIAG_NORM ((uint)0x00000000)
  216. #define SCC_GSMRL_ENR ((uint)0x00000020)
  217. #define SCC_GSMRL_ENT ((uint)0x00000010)
  218. #define SCC_GSMRL_MODE_ENET ((uint)0x0000000c)
  219. #define SCC_GSMRL_MODE_DDCMP ((uint)0x00000009)
  220. #define SCC_GSMRL_MODE_BISYNC ((uint)0x00000008)
  221. #define SCC_GSMRL_MODE_V14 ((uint)0x00000007)
  222. #define SCC_GSMRL_MODE_AHDLC ((uint)0x00000006)
  223. #define SCC_GSMRL_MODE_PROFIBUS ((uint)0x00000005)
  224. #define SCC_GSMRL_MODE_UART ((uint)0x00000004)
  225. #define SCC_GSMRL_MODE_SS7 ((uint)0x00000003)
  226. #define SCC_GSMRL_MODE_ATALK ((uint)0x00000002)
  227. #define SCC_GSMRL_MODE_HDLC ((uint)0x00000000)
  228. #define SCC_TODR_TOD ((ushort)0x8000)
  229. /* SCC Event and Mask register.
  230. */
  231. #define SCCM_TXE ((unsigned char)0x10)
  232. #define SCCM_BSY ((unsigned char)0x04)
  233. #define SCCM_TX ((unsigned char)0x02)
  234. #define SCCM_RX ((unsigned char)0x01)
  235. typedef struct scc_param {
  236. ushort scc_rbase; /* Rx Buffer descriptor base address */
  237. ushort scc_tbase; /* Tx Buffer descriptor base address */
  238. u_char scc_rfcr; /* Rx function code */
  239. u_char scc_tfcr; /* Tx function code */
  240. ushort scc_mrblr; /* Max receive buffer length */
  241. uint scc_rstate; /* Internal */
  242. uint scc_idp; /* Internal */
  243. ushort scc_rbptr; /* Internal */
  244. ushort scc_ibc; /* Internal */
  245. uint scc_rxtmp; /* Internal */
  246. uint scc_tstate; /* Internal */
  247. uint scc_tdp; /* Internal */
  248. ushort scc_tbptr; /* Internal */
  249. ushort scc_tbc; /* Internal */
  250. uint scc_txtmp; /* Internal */
  251. uint scc_rcrc; /* Internal */
  252. uint scc_tcrc; /* Internal */
  253. } sccp_t;
  254. /* CPM Ethernet through SCC1.
  255. */
  256. typedef struct scc_enet {
  257. sccp_t sen_genscc;
  258. uint sen_cpres; /* Preset CRC */
  259. uint sen_cmask; /* Constant mask for CRC */
  260. uint sen_crcec; /* CRC Error counter */
  261. uint sen_alec; /* alignment error counter */
  262. uint sen_disfc; /* discard frame counter */
  263. ushort sen_pads; /* Tx short frame pad character */
  264. ushort sen_retlim; /* Retry limit threshold */
  265. ushort sen_retcnt; /* Retry limit counter */
  266. ushort sen_maxflr; /* maximum frame length register */
  267. ushort sen_minflr; /* minimum frame length register */
  268. ushort sen_maxd1; /* maximum DMA1 length */
  269. ushort sen_maxd2; /* maximum DMA2 length */
  270. ushort sen_maxd; /* Rx max DMA */
  271. ushort sen_dmacnt; /* Rx DMA counter */
  272. ushort sen_maxb; /* Max BD byte count */
  273. ushort sen_gaddr1; /* Group address filter */
  274. ushort sen_gaddr2;
  275. ushort sen_gaddr3;
  276. ushort sen_gaddr4;
  277. uint sen_tbuf0data0; /* Save area 0 - current frame */
  278. uint sen_tbuf0data1; /* Save area 1 - current frame */
  279. uint sen_tbuf0rba; /* Internal */
  280. uint sen_tbuf0crc; /* Internal */
  281. ushort sen_tbuf0bcnt; /* Internal */
  282. ushort sen_paddrh; /* physical address (MSB) */
  283. ushort sen_paddrm;
  284. ushort sen_paddrl; /* physical address (LSB) */
  285. ushort sen_pper; /* persistence */
  286. ushort sen_rfbdptr; /* Rx first BD pointer */
  287. ushort sen_tfbdptr; /* Tx first BD pointer */
  288. ushort sen_tlbdptr; /* Tx last BD pointer */
  289. uint sen_tbuf1data0; /* Save area 0 - current frame */
  290. uint sen_tbuf1data1; /* Save area 1 - current frame */
  291. uint sen_tbuf1rba; /* Internal */
  292. uint sen_tbuf1crc; /* Internal */
  293. ushort sen_tbuf1bcnt; /* Internal */
  294. ushort sen_txlen; /* Tx Frame length counter */
  295. ushort sen_iaddr1; /* Individual address filter */
  296. ushort sen_iaddr2;
  297. ushort sen_iaddr3;
  298. ushort sen_iaddr4;
  299. ushort sen_boffcnt; /* Backoff counter */
  300. /* NOTE: Some versions of the manual have the following items
  301. * incorrectly documented. Below is the proper order.
  302. */
  303. ushort sen_taddrh; /* temp address (MSB) */
  304. ushort sen_taddrm;
  305. ushort sen_taddrl; /* temp address (LSB) */
  306. } scc_enet_t;
  307. /* SCC Event register as used by Ethernet.
  308. */
  309. #define SCCE_ENET_GRA ((ushort)0x0080) /* Graceful stop complete */
  310. #define SCCE_ENET_TXE ((ushort)0x0010) /* Transmit Error */
  311. #define SCCE_ENET_RXF ((ushort)0x0008) /* Full frame received */
  312. #define SCCE_ENET_BSY ((ushort)0x0004) /* All incoming buffers full */
  313. #define SCCE_ENET_TXB ((ushort)0x0002) /* A buffer was transmitted */
  314. #define SCCE_ENET_RXB ((ushort)0x0001) /* A buffer was received */
  315. /* SCC Mode Register (PSMR) as used by Ethernet.
  316. */
  317. #define SCC_PSMR_HBC ((ushort)0x8000) /* Enable heartbeat */
  318. #define SCC_PSMR_FC ((ushort)0x4000) /* Force collision */
  319. #define SCC_PSMR_RSH ((ushort)0x2000) /* Receive short frames */
  320. #define SCC_PSMR_IAM ((ushort)0x1000) /* Check individual hash */
  321. #define SCC_PSMR_ENCRC ((ushort)0x0800) /* Ethernet CRC mode */
  322. #define SCC_PSMR_PRO ((ushort)0x0200) /* Promiscuous mode */
  323. #define SCC_PSMR_BRO ((ushort)0x0100) /* Catch broadcast pkts */
  324. #define SCC_PSMR_SBT ((ushort)0x0080) /* Special backoff timer */
  325. #define SCC_PSMR_LPB ((ushort)0x0040) /* Set Loopback mode */
  326. #define SCC_PSMR_SIP ((ushort)0x0020) /* Sample Input Pins */
  327. #define SCC_PSMR_LCW ((ushort)0x0010) /* Late collision window */
  328. #define SCC_PSMR_NIB22 ((ushort)0x000a) /* Start frame search */
  329. #define SCC_PSMR_FDE ((ushort)0x0001) /* Full duplex enable */
  330. /* Buffer descriptor control/status used by Ethernet receive.
  331. * Common to SCC and FCC.
  332. */
  333. #define BD_ENET_RX_EMPTY ((ushort)0x8000)
  334. #define BD_ENET_RX_WRAP ((ushort)0x2000)
  335. #define BD_ENET_RX_INTR ((ushort)0x1000)
  336. #define BD_ENET_RX_LAST ((ushort)0x0800)
  337. #define BD_ENET_RX_FIRST ((ushort)0x0400)
  338. #define BD_ENET_RX_MISS ((ushort)0x0100)
  339. #define BD_ENET_RX_BC ((ushort)0x0080) /* FCC Only */
  340. #define BD_ENET_RX_MC ((ushort)0x0040) /* FCC Only */
  341. #define BD_ENET_RX_LG ((ushort)0x0020)
  342. #define BD_ENET_RX_NO ((ushort)0x0010)
  343. #define BD_ENET_RX_SH ((ushort)0x0008)
  344. #define BD_ENET_RX_CR ((ushort)0x0004)
  345. #define BD_ENET_RX_OV ((ushort)0x0002)
  346. #define BD_ENET_RX_CL ((ushort)0x0001)
  347. #define BD_ENET_RX_STATS ((ushort)0x01ff) /* All status bits */
  348. /* Buffer descriptor control/status used by Ethernet transmit.
  349. * Common to SCC and FCC.
  350. */
  351. #define BD_ENET_TX_READY ((ushort)0x8000)
  352. #define BD_ENET_TX_PAD ((ushort)0x4000)
  353. #define BD_ENET_TX_WRAP ((ushort)0x2000)
  354. #define BD_ENET_TX_INTR ((ushort)0x1000)
  355. #define BD_ENET_TX_LAST ((ushort)0x0800)
  356. #define BD_ENET_TX_TC ((ushort)0x0400)
  357. #define BD_ENET_TX_DEF ((ushort)0x0200)
  358. #define BD_ENET_TX_HB ((ushort)0x0100)
  359. #define BD_ENET_TX_LC ((ushort)0x0080)
  360. #define BD_ENET_TX_RL ((ushort)0x0040)
  361. #define BD_ENET_TX_RCMASK ((ushort)0x003c)
  362. #define BD_ENET_TX_UN ((ushort)0x0002)
  363. #define BD_ENET_TX_CSL ((ushort)0x0001)
  364. #define BD_ENET_TX_STATS ((ushort)0x03ff) /* All status bits */
  365. /* SCC as UART
  366. */
  367. typedef struct scc_uart {
  368. sccp_t scc_genscc;
  369. uint scc_res1; /* Reserved */
  370. uint scc_res2; /* Reserved */
  371. ushort scc_maxidl; /* Maximum idle chars */
  372. ushort scc_idlc; /* temp idle counter */
  373. ushort scc_brkcr; /* Break count register */
  374. ushort scc_parec; /* receive parity error counter */
  375. ushort scc_frmec; /* receive framing error counter */
  376. ushort scc_nosec; /* receive noise counter */
  377. ushort scc_brkec; /* receive break condition counter */
  378. ushort scc_brkln; /* last received break length */
  379. ushort scc_uaddr1; /* UART address character 1 */
  380. ushort scc_uaddr2; /* UART address character 2 */
  381. ushort scc_rtemp; /* Temp storage */
  382. ushort scc_toseq; /* Transmit out of sequence char */
  383. ushort scc_char1; /* control character 1 */
  384. ushort scc_char2; /* control character 2 */
  385. ushort scc_char3; /* control character 3 */
  386. ushort scc_char4; /* control character 4 */
  387. ushort scc_char5; /* control character 5 */
  388. ushort scc_char6; /* control character 6 */
  389. ushort scc_char7; /* control character 7 */
  390. ushort scc_char8; /* control character 8 */
  391. ushort scc_rccm; /* receive control character mask */
  392. ushort scc_rccr; /* receive control character register */
  393. ushort scc_rlbc; /* receive last break character */
  394. } scc_uart_t;
  395. /* SCC Event and Mask registers when it is used as a UART.
  396. */
  397. #define UART_SCCM_GLR ((ushort)0x1000)
  398. #define UART_SCCM_GLT ((ushort)0x0800)
  399. #define UART_SCCM_AB ((ushort)0x0200)
  400. #define UART_SCCM_IDL ((ushort)0x0100)
  401. #define UART_SCCM_GRA ((ushort)0x0080)
  402. #define UART_SCCM_BRKE ((ushort)0x0040)
  403. #define UART_SCCM_BRKS ((ushort)0x0020)
  404. #define UART_SCCM_CCR ((ushort)0x0008)
  405. #define UART_SCCM_BSY ((ushort)0x0004)
  406. #define UART_SCCM_TX ((ushort)0x0002)
  407. #define UART_SCCM_RX ((ushort)0x0001)
  408. /* The SCC PSMR when used as a UART.
  409. */
  410. #define SCU_PSMR_FLC ((ushort)0x8000)
  411. #define SCU_PSMR_SL ((ushort)0x4000)
  412. #define SCU_PSMR_CL ((ushort)0x3000)
  413. #define SCU_PSMR_UM ((ushort)0x0c00)
  414. #define SCU_PSMR_FRZ ((ushort)0x0200)
  415. #define SCU_PSMR_RZS ((ushort)0x0100)
  416. #define SCU_PSMR_SYN ((ushort)0x0080)
  417. #define SCU_PSMR_DRT ((ushort)0x0040)
  418. #define SCU_PSMR_PEN ((ushort)0x0010)
  419. #define SCU_PSMR_RPM ((ushort)0x000c)
  420. #define SCU_PSMR_REVP ((ushort)0x0008)
  421. #define SCU_PSMR_TPM ((ushort)0x0003)
  422. #define SCU_PSMR_TEVP ((ushort)0x0003)
  423. /* CPM Transparent mode SCC.
  424. */
  425. typedef struct scc_trans {
  426. sccp_t st_genscc;
  427. uint st_cpres; /* Preset CRC */
  428. uint st_cmask; /* Constant mask for CRC */
  429. } scc_trans_t;
  430. #define BD_SCC_TX_LAST ((ushort)0x0800)
  431. /* How about some FCCs.....
  432. */
  433. #define FCC_GFMR_DIAG_NORM ((uint)0x00000000)
  434. #define FCC_GFMR_DIAG_LE ((uint)0x40000000)
  435. #define FCC_GFMR_DIAG_AE ((uint)0x80000000)
  436. #define FCC_GFMR_DIAG_ALE ((uint)0xc0000000)
  437. #define FCC_GFMR_TCI ((uint)0x20000000)
  438. #define FCC_GFMR_TRX ((uint)0x10000000)
  439. #define FCC_GFMR_TTX ((uint)0x08000000)
  440. #define FCC_GFMR_TTX ((uint)0x08000000)
  441. #define FCC_GFMR_CDP ((uint)0x04000000)
  442. #define FCC_GFMR_CTSP ((uint)0x02000000)
  443. #define FCC_GFMR_CDS ((uint)0x01000000)
  444. #define FCC_GFMR_CTSS ((uint)0x00800000)
  445. #define FCC_GFMR_SYNL_NONE ((uint)0x00000000)
  446. #define FCC_GFMR_SYNL_AUTO ((uint)0x00004000)
  447. #define FCC_GFMR_SYNL_8 ((uint)0x00008000)
  448. #define FCC_GFMR_SYNL_16 ((uint)0x0000c000)
  449. #define FCC_GFMR_RTSM ((uint)0x00002000)
  450. #define FCC_GFMR_RENC_NRZ ((uint)0x00000000)
  451. #define FCC_GFMR_RENC_NRZI ((uint)0x00000800)
  452. #define FCC_GFMR_REVD ((uint)0x00000400)
  453. #define FCC_GFMR_TENC_NRZ ((uint)0x00000000)
  454. #define FCC_GFMR_TENC_NRZI ((uint)0x00000100)
  455. #define FCC_GFMR_TCRC_16 ((uint)0x00000000)
  456. #define FCC_GFMR_TCRC_32 ((uint)0x00000080)
  457. #define FCC_GFMR_ENR ((uint)0x00000020)
  458. #define FCC_GFMR_ENT ((uint)0x00000010)
  459. #define FCC_GFMR_MODE_ENET ((uint)0x0000000c)
  460. #define FCC_GFMR_MODE_ATM ((uint)0x0000000a)
  461. #define FCC_GFMR_MODE_HDLC ((uint)0x00000000)
  462. /* Generic FCC parameter ram.
  463. */
  464. typedef struct fcc_param {
  465. ushort fcc_riptr; /* Rx Internal temp pointer */
  466. ushort fcc_tiptr; /* Tx Internal temp pointer */
  467. ushort fcc_res1;
  468. ushort fcc_mrblr; /* Max receive buffer length, mod 32 bytes */
  469. uint fcc_rstate; /* Upper byte is Func code, must be set */
  470. uint fcc_rbase; /* Receive BD base */
  471. ushort fcc_rbdstat; /* RxBD status */
  472. ushort fcc_rbdlen; /* RxBD down counter */
  473. uint fcc_rdptr; /* RxBD internal data pointer */
  474. uint fcc_tstate; /* Upper byte is Func code, must be set */
  475. uint fcc_tbase; /* Transmit BD base */
  476. ushort fcc_tbdstat; /* TxBD status */
  477. ushort fcc_tbdlen; /* TxBD down counter */
  478. uint fcc_tdptr; /* TxBD internal data pointer */
  479. uint fcc_rbptr; /* Rx BD Internal buf pointer */
  480. uint fcc_tbptr; /* Tx BD Internal buf pointer */
  481. uint fcc_rcrc; /* Rx temp CRC */
  482. uint fcc_res2;
  483. uint fcc_tcrc; /* Tx temp CRC */
  484. } fccp_t;
  485. /* Ethernet controller through FCC.
  486. */
  487. typedef struct fcc_enet {
  488. fccp_t fen_genfcc;
  489. uint fen_statbuf; /* Internal status buffer */
  490. uint fen_camptr; /* CAM address */
  491. uint fen_cmask; /* Constant mask for CRC */
  492. uint fen_cpres; /* Preset CRC */
  493. uint fen_crcec; /* CRC Error counter */
  494. uint fen_alec; /* alignment error counter */
  495. uint fen_disfc; /* discard frame counter */
  496. ushort fen_retlim; /* Retry limit */
  497. ushort fen_retcnt; /* Retry counter */
  498. ushort fen_pper; /* Persistence */
  499. ushort fen_boffcnt; /* backoff counter */
  500. uint fen_gaddrh; /* Group address filter, high 32-bits */
  501. uint fen_gaddrl; /* Group address filter, low 32-bits */
  502. ushort fen_tfcstat; /* out of sequence TxBD */
  503. ushort fen_tfclen;
  504. uint fen_tfcptr;
  505. ushort fen_mflr; /* Maximum frame length (1518) */
  506. ushort fen_paddrh; /* MAC address */
  507. ushort fen_paddrm;
  508. ushort fen_paddrl;
  509. ushort fen_ibdcount; /* Internal BD counter */
  510. ushort fen_ibdstart; /* Internal BD start pointer */
  511. ushort fen_ibdend; /* Internal BD end pointer */
  512. ushort fen_txlen; /* Internal Tx frame length counter */
  513. uint fen_ibdbase[8]; /* Internal use */
  514. uint fen_iaddrh; /* Individual address filter */
  515. uint fen_iaddrl;
  516. ushort fen_minflr; /* Minimum frame length (64) */
  517. ushort fen_taddrh; /* Filter transfer MAC address */
  518. ushort fen_taddrm;
  519. ushort fen_taddrl;
  520. ushort fen_padptr; /* Pointer to pad byte buffer */
  521. ushort fen_cftype; /* control frame type */
  522. ushort fen_cfrange; /* control frame range */
  523. ushort fen_maxb; /* maximum BD count */
  524. ushort fen_maxd1; /* Max DMA1 length (1520) */
  525. ushort fen_maxd2; /* Max DMA2 length (1520) */
  526. ushort fen_maxd; /* internal max DMA count */
  527. ushort fen_dmacnt; /* internal DMA counter */
  528. uint fen_octc; /* Total octect counter */
  529. uint fen_colc; /* Total collision counter */
  530. uint fen_broc; /* Total broadcast packet counter */
  531. uint fen_mulc; /* Total multicast packet count */
  532. uint fen_uspc; /* Total packets < 64 bytes */
  533. uint fen_frgc; /* Total packets < 64 bytes with errors */
  534. uint fen_ospc; /* Total packets > 1518 */
  535. uint fen_jbrc; /* Total packets > 1518 with errors */
  536. uint fen_p64c; /* Total packets == 64 bytes */
  537. uint fen_p65c; /* Total packets 64 < bytes <= 127 */
  538. uint fen_p128c; /* Total packets 127 < bytes <= 255 */
  539. uint fen_p256c; /* Total packets 256 < bytes <= 511 */
  540. uint fen_p512c; /* Total packets 512 < bytes <= 1023 */
  541. uint fen_p1024c; /* Total packets 1024 < bytes <= 1518 */
  542. uint fen_cambuf; /* Internal CAM buffer poiner */
  543. ushort fen_rfthr; /* Received frames threshold */
  544. ushort fen_rfcnt; /* Received frames count */
  545. } fcc_enet_t;
  546. /* FCC Event/Mask register as used by Ethernet.
  547. */
  548. #define FCC_ENET_GRA ((ushort)0x0080) /* Graceful stop complete */
  549. #define FCC_ENET_RXC ((ushort)0x0040) /* Control Frame Received */
  550. #define FCC_ENET_TXC ((ushort)0x0020) /* Out of seq. Tx sent */
  551. #define FCC_ENET_TXE ((ushort)0x0010) /* Transmit Error */
  552. #define FCC_ENET_RXF ((ushort)0x0008) /* Full frame received */
  553. #define FCC_ENET_BSY ((ushort)0x0004) /* Busy. Rx Frame dropped */
  554. #define FCC_ENET_TXB ((ushort)0x0002) /* A buffer was transmitted */
  555. #define FCC_ENET_RXB ((ushort)0x0001) /* A buffer was received */
  556. /* FCC Mode Register (FPSMR) as used by Ethernet.
  557. */
  558. #define FCC_PSMR_HBC ((uint)0x80000000) /* Enable heartbeat */
  559. #define FCC_PSMR_FC ((uint)0x40000000) /* Force Collision */
  560. #define FCC_PSMR_SBT ((uint)0x20000000) /* Stop backoff timer */
  561. #define FCC_PSMR_LPB ((uint)0x10000000) /* Local protect. 1 = FDX */
  562. #define FCC_PSMR_LCW ((uint)0x08000000) /* Late collision select */
  563. #define FCC_PSMR_FDE ((uint)0x04000000) /* Full Duplex Enable */
  564. #define FCC_PSMR_MON ((uint)0x02000000) /* RMON Enable */
  565. #define FCC_PSMR_PRO ((uint)0x00400000) /* Promiscuous Enable */
  566. #define FCC_PSMR_FCE ((uint)0x00200000) /* Flow Control Enable */
  567. #define FCC_PSMR_RSH ((uint)0x00100000) /* Receive Short Frames */
  568. #define FCC_PSMR_CAM ((uint)0x00000400) /* CAM enable */
  569. #define FCC_PSMR_BRO ((uint)0x00000200) /* Broadcast pkt discard */
  570. #define FCC_PSMR_ENCRC ((uint)0x00000080) /* Use 32-bit CRC */
  571. /* IIC parameter RAM.
  572. */
  573. typedef struct iic {
  574. ushort iic_rbase; /* Rx Buffer descriptor base address */
  575. ushort iic_tbase; /* Tx Buffer descriptor base address */
  576. u_char iic_rfcr; /* Rx function code */
  577. u_char iic_tfcr; /* Tx function code */
  578. ushort iic_mrblr; /* Max receive buffer length */
  579. uint iic_rstate; /* Internal */
  580. uint iic_rdp; /* Internal */
  581. ushort iic_rbptr; /* Internal */
  582. ushort iic_rbc; /* Internal */
  583. uint iic_rxtmp; /* Internal */
  584. uint iic_tstate; /* Internal */
  585. uint iic_tdp; /* Internal */
  586. ushort iic_tbptr; /* Internal */
  587. ushort iic_tbc; /* Internal */
  588. uint iic_txtmp; /* Internal */
  589. } iic_t;
  590. /* SPI parameter RAM.
  591. */
  592. typedef struct spi {
  593. ushort spi_rbase; /* Rx Buffer descriptor base address */
  594. ushort spi_tbase; /* Tx Buffer descriptor base address */
  595. u_char spi_rfcr; /* Rx function code */
  596. u_char spi_tfcr; /* Tx function code */
  597. ushort spi_mrblr; /* Max receive buffer length */
  598. uint spi_rstate; /* Internal */
  599. uint spi_rdp; /* Internal */
  600. ushort spi_rbptr; /* Internal */
  601. ushort spi_rbc; /* Internal */
  602. uint spi_rxtmp; /* Internal */
  603. uint spi_tstate; /* Internal */
  604. uint spi_tdp; /* Internal */
  605. ushort spi_tbptr; /* Internal */
  606. ushort spi_tbc; /* Internal */
  607. uint spi_txtmp; /* Internal */
  608. uint spi_res; /* Tx temp. */
  609. uint spi_res1[4]; /* SDMA temp. */
  610. } spi_t;
  611. /* SPI Mode register.
  612. */
  613. #define SPMODE_LOOP ((ushort)0x4000) /* Loopback */
  614. #define SPMODE_CI ((ushort)0x2000) /* Clock Invert */
  615. #define SPMODE_CP ((ushort)0x1000) /* Clock Phase */
  616. #define SPMODE_DIV16 ((ushort)0x0800) /* BRG/16 mode */
  617. #define SPMODE_REV ((ushort)0x0400) /* Reversed Data */
  618. #define SPMODE_MSTR ((ushort)0x0200) /* SPI Master */
  619. #define SPMODE_EN ((ushort)0x0100) /* Enable */
  620. #define SPMODE_LENMSK ((ushort)0x00f0) /* character length */
  621. #define SPMODE_PMMSK ((ushort)0x000f) /* prescale modulus */
  622. #define SPMODE_LEN(x) ((((x)-1)&0xF)<<4)
  623. #define SPMODE_PM(x) ((x) &0xF)
  624. #define SPI_EB ((u_char)0x10) /* big endian byte order */
  625. #define BD_IIC_START ((ushort)0x0400)
  626. /*-----------------------------------------------------------------------
  627. * CMXFCR - CMX FCC Clock Route Register 15-12
  628. */
  629. #define CMXFCR_FC1 0x40000000 /* FCC1 connection */
  630. #define CMXFCR_RF1CS_MSK 0x38000000 /* Receive FCC1 Clock Source Mask */
  631. #define CMXFCR_TF1CS_MSK 0x07000000 /* Transmit FCC1 Clock Source Mask */
  632. #define CMXFCR_FC2 0x00400000 /* FCC2 connection */
  633. #define CMXFCR_RF2CS_MSK 0x00380000 /* Receive FCC2 Clock Source Mask */
  634. #define CMXFCR_TF2CS_MSK 0x00070000 /* Transmit FCC2 Clock Source Mask */
  635. #define CMXFCR_FC3 0x00004000 /* FCC3 connection */
  636. #define CMXFCR_RF3CS_MSK 0x00003800 /* Receive FCC3 Clock Source Mask */
  637. #define CMXFCR_TF3CS_MSK 0x00000700 /* Transmit FCC3 Clock Source Mask */
  638. #define CMXFCR_RF1CS_BRG5 0x00000000 /* Receive FCC1 Clock Source is BRG5 */
  639. #define CMXFCR_RF1CS_BRG6 0x08000000 /* Receive FCC1 Clock Source is BRG6 */
  640. #define CMXFCR_RF1CS_BRG7 0x10000000 /* Receive FCC1 Clock Source is BRG7 */
  641. #define CMXFCR_RF1CS_BRG8 0x18000000 /* Receive FCC1 Clock Source is BRG8 */
  642. #define CMXFCR_RF1CS_CLK9 0x20000000 /* Receive FCC1 Clock Source is CLK9 */
  643. #define CMXFCR_RF1CS_CLK10 0x28000000 /* Receive FCC1 Clock Source is CLK10 */
  644. #define CMXFCR_RF1CS_CLK11 0x30000000 /* Receive FCC1 Clock Source is CLK11 */
  645. #define CMXFCR_RF1CS_CLK12 0x38000000 /* Receive FCC1 Clock Source is CLK12 */
  646. #define CMXFCR_TF1CS_BRG5 0x00000000 /* Transmit FCC1 Clock Source is BRG5 */
  647. #define CMXFCR_TF1CS_BRG6 0x01000000 /* Transmit FCC1 Clock Source is BRG6 */
  648. #define CMXFCR_TF1CS_BRG7 0x02000000 /* Transmit FCC1 Clock Source is BRG7 */
  649. #define CMXFCR_TF1CS_BRG8 0x03000000 /* Transmit FCC1 Clock Source is BRG8 */
  650. #define CMXFCR_TF1CS_CLK9 0x04000000 /* Transmit FCC1 Clock Source is CLK9 */
  651. #define CMXFCR_TF1CS_CLK10 0x05000000 /* Transmit FCC1 Clock Source is CLK10 */
  652. #define CMXFCR_TF1CS_CLK11 0x06000000 /* Transmit FCC1 Clock Source is CLK11 */
  653. #define CMXFCR_TF1CS_CLK12 0x07000000 /* Transmit FCC1 Clock Source is CLK12 */
  654. #define CMXFCR_RF2CS_BRG5 0x00000000 /* Receive FCC2 Clock Source is BRG5 */
  655. #define CMXFCR_RF2CS_BRG6 0x00080000 /* Receive FCC2 Clock Source is BRG6 */
  656. #define CMXFCR_RF2CS_BRG7 0x00100000 /* Receive FCC2 Clock Source is BRG7 */
  657. #define CMXFCR_RF2CS_BRG8 0x00180000 /* Receive FCC2 Clock Source is BRG8 */
  658. #define CMXFCR_RF2CS_CLK13 0x00200000 /* Receive FCC2 Clock Source is CLK13 */
  659. #define CMXFCR_RF2CS_CLK14 0x00280000 /* Receive FCC2 Clock Source is CLK14 */
  660. #define CMXFCR_RF2CS_CLK15 0x00300000 /* Receive FCC2 Clock Source is CLK15 */
  661. #define CMXFCR_RF2CS_CLK16 0x00380000 /* Receive FCC2 Clock Source is CLK16 */
  662. #define CMXFCR_TF2CS_BRG5 0x00000000 /* Transmit FCC2 Clock Source is BRG5 */
  663. #define CMXFCR_TF2CS_BRG6 0x00010000 /* Transmit FCC2 Clock Source is BRG6 */
  664. #define CMXFCR_TF2CS_BRG7 0x00020000 /* Transmit FCC2 Clock Source is BRG7 */
  665. #define CMXFCR_TF2CS_BRG8 0x00030000 /* Transmit FCC2 Clock Source is BRG8 */
  666. #define CMXFCR_TF2CS_CLK13 0x00040000 /* Transmit FCC2 Clock Source is CLK13 */
  667. #define CMXFCR_TF2CS_CLK14 0x00050000 /* Transmit FCC2 Clock Source is CLK14 */
  668. #define CMXFCR_TF2CS_CLK15 0x00060000 /* Transmit FCC2 Clock Source is CLK15 */
  669. #define CMXFCR_TF2CS_CLK16 0x00070000 /* Transmit FCC2 Clock Source is CLK16 */
  670. #define CMXFCR_RF3CS_BRG5 0x00000000 /* Receive FCC3 Clock Source is BRG5 */
  671. #define CMXFCR_RF3CS_BRG6 0x00000800 /* Receive FCC3 Clock Source is BRG6 */
  672. #define CMXFCR_RF3CS_BRG7 0x00001000 /* Receive FCC3 Clock Source is BRG7 */
  673. #define CMXFCR_RF3CS_BRG8 0x00001800 /* Receive FCC3 Clock Source is BRG8 */
  674. #define CMXFCR_RF3CS_CLK13 0x00002000 /* Receive FCC3 Clock Source is CLK13 */
  675. #define CMXFCR_RF3CS_CLK14 0x00002800 /* Receive FCC3 Clock Source is CLK14 */
  676. #define CMXFCR_RF3CS_CLK15 0x00003000 /* Receive FCC3 Clock Source is CLK15 */
  677. #define CMXFCR_RF3CS_CLK16 0x00003800 /* Receive FCC3 Clock Source is CLK16 */
  678. #define CMXFCR_TF3CS_BRG5 0x00000000 /* Transmit FCC3 Clock Source is BRG5 */
  679. #define CMXFCR_TF3CS_BRG6 0x00000100 /* Transmit FCC3 Clock Source is BRG6 */
  680. #define CMXFCR_TF3CS_BRG7 0x00000200 /* Transmit FCC3 Clock Source is BRG7 */
  681. #define CMXFCR_TF3CS_BRG8 0x00000300 /* Transmit FCC3 Clock Source is BRG8 */
  682. #define CMXFCR_TF3CS_CLK13 0x00000400 /* Transmit FCC3 Clock Source is CLK13 */
  683. #define CMXFCR_TF3CS_CLK14 0x00000500 /* Transmit FCC3 Clock Source is CLK14 */
  684. #define CMXFCR_TF3CS_CLK15 0x00000600 /* Transmit FCC3 Clock Source is CLK15 */
  685. #define CMXFCR_TF3CS_CLK16 0x00000700 /* Transmit FCC3 Clock Source is CLK16 */
  686. /*-----------------------------------------------------------------------
  687. * CMXSCR - CMX SCC Clock Route Register 15-14
  688. */
  689. #define CMXSCR_GR1 0x80000000 /* Grant Support of SCC1 */
  690. #define CMXSCR_SC1 0x40000000 /* SCC1 connection */
  691. #define CMXSCR_RS1CS_MSK 0x38000000 /* Receive SCC1 Clock Source Mask */
  692. #define CMXSCR_TS1CS_MSK 0x07000000 /* Transmit SCC1 Clock Source Mask */
  693. #define CMXSCR_GR2 0x00800000 /* Grant Support of SCC2 */
  694. #define CMXSCR_SC2 0x00400000 /* SCC2 connection */
  695. #define CMXSCR_RS2CS_MSK 0x00380000 /* Receive SCC2 Clock Source Mask */
  696. #define CMXSCR_TS2CS_MSK 0x00070000 /* Transmit SCC2 Clock Source Mask */
  697. #define CMXSCR_GR3 0x00008000 /* Grant Support of SCC3 */
  698. #define CMXSCR_SC3 0x00004000 /* SCC3 connection */
  699. #define CMXSCR_RS3CS_MSK 0x00003800 /* Receive SCC3 Clock Source Mask */
  700. #define CMXSCR_TS3CS_MSK 0x00000700 /* Transmit SCC3 Clock Source Mask */
  701. #define CMXSCR_GR4 0x00000080 /* Grant Support of SCC4 */
  702. #define CMXSCR_SC4 0x00000040 /* SCC4 connection */
  703. #define CMXSCR_RS4CS_MSK 0x00000038 /* Receive SCC4 Clock Source Mask */
  704. #define CMXSCR_TS4CS_MSK 0x00000007 /* Transmit SCC4 Clock Source Mask */
  705. #define CMXSCR_RS1CS_BRG1 0x00000000 /* SCC1 Rx Clock Source is BRG1 */
  706. #define CMXSCR_RS1CS_BRG2 0x08000000 /* SCC1 Rx Clock Source is BRG2 */
  707. #define CMXSCR_RS1CS_BRG3 0x10000000 /* SCC1 Rx Clock Source is BRG3 */
  708. #define CMXSCR_RS1CS_BRG4 0x18000000 /* SCC1 Rx Clock Source is BRG4 */
  709. #define CMXSCR_RS1CS_CLK11 0x20000000 /* SCC1 Rx Clock Source is CLK11 */
  710. #define CMXSCR_RS1CS_CLK12 0x28000000 /* SCC1 Rx Clock Source is CLK12 */
  711. #define CMXSCR_RS1CS_CLK3 0x30000000 /* SCC1 Rx Clock Source is CLK3 */
  712. #define CMXSCR_RS1CS_CLK4 0x38000000 /* SCC1 Rx Clock Source is CLK4 */
  713. #define CMXSCR_TS1CS_BRG1 0x00000000 /* SCC1 Tx Clock Source is BRG1 */
  714. #define CMXSCR_TS1CS_BRG2 0x01000000 /* SCC1 Tx Clock Source is BRG2 */
  715. #define CMXSCR_TS1CS_BRG3 0x02000000 /* SCC1 Tx Clock Source is BRG3 */
  716. #define CMXSCR_TS1CS_BRG4 0x03000000 /* SCC1 Tx Clock Source is BRG4 */
  717. #define CMXSCR_TS1CS_CLK11 0x04000000 /* SCC1 Tx Clock Source is CLK11 */
  718. #define CMXSCR_TS1CS_CLK12 0x05000000 /* SCC1 Tx Clock Source is CLK12 */
  719. #define CMXSCR_TS1CS_CLK3 0x06000000 /* SCC1 Tx Clock Source is CLK3 */
  720. #define CMXSCR_TS1CS_CLK4 0x07000000 /* SCC1 Tx Clock Source is CLK4 */
  721. #define CMXSCR_RS2CS_BRG1 0x00000000 /* SCC2 Rx Clock Source is BRG1 */
  722. #define CMXSCR_RS2CS_BRG2 0x00080000 /* SCC2 Rx Clock Source is BRG2 */
  723. #define CMXSCR_RS2CS_BRG3 0x00100000 /* SCC2 Rx Clock Source is BRG3 */
  724. #define CMXSCR_RS2CS_BRG4 0x00180000 /* SCC2 Rx Clock Source is BRG4 */
  725. #define CMXSCR_RS2CS_CLK11 0x00200000 /* SCC2 Rx Clock Source is CLK11 */
  726. #define CMXSCR_RS2CS_CLK12 0x00280000 /* SCC2 Rx Clock Source is CLK12 */
  727. #define CMXSCR_RS2CS_CLK3 0x00300000 /* SCC2 Rx Clock Source is CLK3 */
  728. #define CMXSCR_RS2CS_CLK4 0x00380000 /* SCC2 Rx Clock Source is CLK4 */
  729. #define CMXSCR_TS2CS_BRG1 0x00000000 /* SCC2 Tx Clock Source is BRG1 */
  730. #define CMXSCR_TS2CS_BRG2 0x00010000 /* SCC2 Tx Clock Source is BRG2 */
  731. #define CMXSCR_TS2CS_BRG3 0x00020000 /* SCC2 Tx Clock Source is BRG3 */
  732. #define CMXSCR_TS2CS_BRG4 0x00030000 /* SCC2 Tx Clock Source is BRG4 */
  733. #define CMXSCR_TS2CS_CLK11 0x00040000 /* SCC2 Tx Clock Source is CLK11 */
  734. #define CMXSCR_TS2CS_CLK12 0x00050000 /* SCC2 Tx Clock Source is CLK12 */
  735. #define CMXSCR_TS2CS_CLK3 0x00060000 /* SCC2 Tx Clock Source is CLK3 */
  736. #define CMXSCR_TS2CS_CLK4 0x00070000 /* SCC2 Tx Clock Source is CLK4 */
  737. #define CMXSCR_RS3CS_BRG1 0x00000000 /* SCC3 Rx Clock Source is BRG1 */
  738. #define CMXSCR_RS3CS_BRG2 0x00000800 /* SCC3 Rx Clock Source is BRG2 */
  739. #define CMXSCR_RS3CS_BRG3 0x00001000 /* SCC3 Rx Clock Source is BRG3 */
  740. #define CMXSCR_RS3CS_BRG4 0x00001800 /* SCC3 Rx Clock Source is BRG4 */
  741. #define CMXSCR_RS3CS_CLK5 0x00002000 /* SCC3 Rx Clock Source is CLK5 */
  742. #define CMXSCR_RS3CS_CLK6 0x00002800 /* SCC3 Rx Clock Source is CLK6 */
  743. #define CMXSCR_RS3CS_CLK7 0x00003000 /* SCC3 Rx Clock Source is CLK7 */
  744. #define CMXSCR_RS3CS_CLK8 0x00003800 /* SCC3 Rx Clock Source is CLK8 */
  745. #define CMXSCR_TS3CS_BRG1 0x00000000 /* SCC3 Tx Clock Source is BRG1 */
  746. #define CMXSCR_TS3CS_BRG2 0x00000100 /* SCC3 Tx Clock Source is BRG2 */
  747. #define CMXSCR_TS3CS_BRG3 0x00000200 /* SCC3 Tx Clock Source is BRG3 */
  748. #define CMXSCR_TS3CS_BRG4 0x00000300 /* SCC3 Tx Clock Source is BRG4 */
  749. #define CMXSCR_TS3CS_CLK5 0x00000400 /* SCC3 Tx Clock Source is CLK5 */
  750. #define CMXSCR_TS3CS_CLK6 0x00000500 /* SCC3 Tx Clock Source is CLK6 */
  751. #define CMXSCR_TS3CS_CLK7 0x00000600 /* SCC3 Tx Clock Source is CLK7 */
  752. #define CMXSCR_TS3CS_CLK8 0x00000700 /* SCC3 Tx Clock Source is CLK8 */
  753. #define CMXSCR_RS4CS_BRG1 0x00000000 /* SCC4 Rx Clock Source is BRG1 */
  754. #define CMXSCR_RS4CS_BRG2 0x00000008 /* SCC4 Rx Clock Source is BRG2 */
  755. #define CMXSCR_RS4CS_BRG3 0x00000010 /* SCC4 Rx Clock Source is BRG3 */
  756. #define CMXSCR_RS4CS_BRG4 0x00000018 /* SCC4 Rx Clock Source is BRG4 */
  757. #define CMXSCR_RS4CS_CLK5 0x00000020 /* SCC4 Rx Clock Source is CLK5 */
  758. #define CMXSCR_RS4CS_CLK6 0x00000028 /* SCC4 Rx Clock Source is CLK6 */
  759. #define CMXSCR_RS4CS_CLK7 0x00000030 /* SCC4 Rx Clock Source is CLK7 */
  760. #define CMXSCR_RS4CS_CLK8 0x00000038 /* SCC4 Rx Clock Source is CLK8 */
  761. #define CMXSCR_TS4CS_BRG1 0x00000000 /* SCC4 Tx Clock Source is BRG1 */
  762. #define CMXSCR_TS4CS_BRG2 0x00000001 /* SCC4 Tx Clock Source is BRG2 */
  763. #define CMXSCR_TS4CS_BRG3 0x00000002 /* SCC4 Tx Clock Source is BRG3 */
  764. #define CMXSCR_TS4CS_BRG4 0x00000003 /* SCC4 Tx Clock Source is BRG4 */
  765. #define CMXSCR_TS4CS_CLK5 0x00000004 /* SCC4 Tx Clock Source is CLK5 */
  766. #define CMXSCR_TS4CS_CLK6 0x00000005 /* SCC4 Tx Clock Source is CLK6 */
  767. #define CMXSCR_TS4CS_CLK7 0x00000006 /* SCC4 Tx Clock Source is CLK7 */
  768. #define CMXSCR_TS4CS_CLK8 0x00000007 /* SCC4 Tx Clock Source is CLK8 */
  769. #endif /* __CPM_85XX__ */