IxQueueAssignments.h 16 KB

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  1. /**
  2. * @file IxQueueAssignments.h
  3. *
  4. * @author Intel Corporation
  5. * @date 29-Oct-2004
  6. *
  7. * @brief Central definition for queue assignments
  8. *
  9. * Design Notes:
  10. * This file contains queue assignments used by Ethernet (EthAcc),
  11. * HSS (HssAcc), ATM (atmdAcc) and DMA (dmaAcc) access libraries.
  12. *
  13. * Note: Ethernet QoS traffic class definitions are managed separately
  14. * by EthDB in IxEthDBQoS.h.
  15. *
  16. * @par
  17. * IXP400 SW Release version 2.0
  18. *
  19. * -- Copyright Notice --
  20. *
  21. * @par
  22. * Copyright 2001-2005, Intel Corporation.
  23. * All rights reserved.
  24. *
  25. * @par
  26. * Redistribution and use in source and binary forms, with or without
  27. * modification, are permitted provided that the following conditions
  28. * are met:
  29. * 1. Redistributions of source code must retain the above copyright
  30. * notice, this list of conditions and the following disclaimer.
  31. * 2. Redistributions in binary form must reproduce the above copyright
  32. * notice, this list of conditions and the following disclaimer in the
  33. * documentation and/or other materials provided with the distribution.
  34. * 3. Neither the name of the Intel Corporation nor the names of its contributors
  35. * may be used to endorse or promote products derived from this software
  36. * without specific prior written permission.
  37. *
  38. * @par
  39. * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS ``AS IS''
  40. * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  41. * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  42. * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE
  43. * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
  44. * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
  45. * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
  46. * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
  47. * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
  48. * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
  49. * SUCH DAMAGE.
  50. *
  51. * @par
  52. * -- End of Copyright Notice --
  53. */
  54. #ifndef IxQueueAssignments_H
  55. #define IxQueueAssignments_H
  56. #include "IxQMgr.h"
  57. /***************************************************************************
  58. * Queue assignments for ATM
  59. ***************************************************************************/
  60. /**
  61. * @brief Global compiler switch to select between 3 possible NPE Modes
  62. * Define this macro to enable MPHY mode
  63. *
  64. * Default(No Switch) = MultiPHY Utopia2
  65. * IX_UTOPIAMODE = 1 for single Phy Utopia1
  66. * IX_MPHYSINGLEPORT = 1 for single Phy Utopia2
  67. */
  68. #define IX_NPE_MPHYMULTIPORT 1
  69. #if IX_UTOPIAMODE == 1
  70. #undef IX_NPE_MPHYMULTIPORT
  71. #endif
  72. #if IX_MPHYSINGLEPORT == 1
  73. #undef IX_NPE_MPHYMULTIPORT
  74. #endif
  75. /**
  76. * @def IX_NPE_A_TXDONE_QUEUE_HIGHWATERMARK
  77. *
  78. * @brief The NPE reserves the High Watermark for its operation. But it must be set by the Xscale
  79. */
  80. #define IX_NPE_A_TXDONE_QUEUE_HIGHWATERMARK 2
  81. /**
  82. * @def IX_NPE_A_QMQ_ATM_TX_DONE
  83. *
  84. * @brief Queue ID for ATM Transmit Done queue
  85. */
  86. #define IX_NPE_A_QMQ_ATM_TX_DONE IX_QMGR_QUEUE_1
  87. /**
  88. * @def IX_NPE_A_QMQ_ATM_TX0
  89. *
  90. * @brief Queue ID for ATM transmit Queue in a single phy configuration
  91. */
  92. #define IX_NPE_A_QMQ_ATM_TX0 IX_QMGR_QUEUE_2
  93. /**
  94. * @def IX_NPE_A_QMQ_ATM_TXID_MIN
  95. *
  96. * @brief Queue Manager Queue ID for ATM transmit Queue with minimum number of queue
  97. *
  98. */
  99. /**
  100. * @def IX_NPE_A_QMQ_ATM_TXID_MAX
  101. *
  102. * @brief Queue Manager Queue ID for ATM transmit Queue with maximum number of queue
  103. *
  104. */
  105. /**
  106. * @def IX_NPE_A_QMQ_ATM_RX_HI
  107. *
  108. * @brief Queue Manager Queue ID for ATM Receive high Queue
  109. *
  110. */
  111. /**
  112. * @def IX_NPE_A_QMQ_ATM_RX_LO
  113. *
  114. * @brief Queue Manager Queue ID for ATM Receive low Queue
  115. */
  116. #ifdef IX_NPE_MPHYMULTIPORT
  117. /**
  118. * @def IX_NPE_A_QMQ_ATM_TX1
  119. *
  120. * @brief Queue ID for ATM transmit Queue Multiphy from 1 to 11
  121. */
  122. #define IX_NPE_A_QMQ_ATM_TX1 IX_NPE_A_QMQ_ATM_TX0+1
  123. #define IX_NPE_A_QMQ_ATM_TX2 IX_NPE_A_QMQ_ATM_TX1+1
  124. #define IX_NPE_A_QMQ_ATM_TX3 IX_NPE_A_QMQ_ATM_TX2+1
  125. #define IX_NPE_A_QMQ_ATM_TX4 IX_NPE_A_QMQ_ATM_TX3+1
  126. #define IX_NPE_A_QMQ_ATM_TX5 IX_NPE_A_QMQ_ATM_TX4+1
  127. #define IX_NPE_A_QMQ_ATM_TX6 IX_NPE_A_QMQ_ATM_TX5+1
  128. #define IX_NPE_A_QMQ_ATM_TX7 IX_NPE_A_QMQ_ATM_TX6+1
  129. #define IX_NPE_A_QMQ_ATM_TX8 IX_NPE_A_QMQ_ATM_TX7+1
  130. #define IX_NPE_A_QMQ_ATM_TX9 IX_NPE_A_QMQ_ATM_TX8+1
  131. #define IX_NPE_A_QMQ_ATM_TX10 IX_NPE_A_QMQ_ATM_TX9+1
  132. #define IX_NPE_A_QMQ_ATM_TX11 IX_NPE_A_QMQ_ATM_TX10+1
  133. #define IX_NPE_A_QMQ_ATM_TXID_MIN IX_NPE_A_QMQ_ATM_TX0
  134. #define IX_NPE_A_QMQ_ATM_TXID_MAX IX_NPE_A_QMQ_ATM_TX11
  135. #define IX_NPE_A_QMQ_ATM_RX_HI IX_QMGR_QUEUE_21
  136. #define IX_NPE_A_QMQ_ATM_RX_LO IX_QMGR_QUEUE_22
  137. #else
  138. #define IX_NPE_A_QMQ_ATM_TXID_MIN IX_NPE_A_QMQ_ATM_TX0
  139. #define IX_NPE_A_QMQ_ATM_TXID_MAX IX_NPE_A_QMQ_ATM_TX0
  140. #define IX_NPE_A_QMQ_ATM_RX_HI IX_QMGR_QUEUE_10
  141. #define IX_NPE_A_QMQ_ATM_RX_LO IX_QMGR_QUEUE_11
  142. #endif /* MPHY */
  143. /**
  144. * @def IX_NPE_A_QMQ_ATM_FREE_VC0
  145. *
  146. * @brief Hardware QMgr Queue ID for ATM Free VC Queue.
  147. *
  148. * There are 32 Hardware QMgr Queue ID; from IX_NPE_A_QMQ_ATM_FREE_VC1 to
  149. * IX_NPE_A_QMQ_ATM_FREE_VC30
  150. */
  151. #define IX_NPE_A_QMQ_ATM_FREE_VC0 IX_QMGR_QUEUE_32
  152. #define IX_NPE_A_QMQ_ATM_FREE_VC1 IX_NPE_A_QMQ_ATM_FREE_VC0+1
  153. #define IX_NPE_A_QMQ_ATM_FREE_VC2 IX_NPE_A_QMQ_ATM_FREE_VC1+1
  154. #define IX_NPE_A_QMQ_ATM_FREE_VC3 IX_NPE_A_QMQ_ATM_FREE_VC2+1
  155. #define IX_NPE_A_QMQ_ATM_FREE_VC4 IX_NPE_A_QMQ_ATM_FREE_VC3+1
  156. #define IX_NPE_A_QMQ_ATM_FREE_VC5 IX_NPE_A_QMQ_ATM_FREE_VC4+1
  157. #define IX_NPE_A_QMQ_ATM_FREE_VC6 IX_NPE_A_QMQ_ATM_FREE_VC5+1
  158. #define IX_NPE_A_QMQ_ATM_FREE_VC7 IX_NPE_A_QMQ_ATM_FREE_VC6+1
  159. #define IX_NPE_A_QMQ_ATM_FREE_VC8 IX_NPE_A_QMQ_ATM_FREE_VC7+1
  160. #define IX_NPE_A_QMQ_ATM_FREE_VC9 IX_NPE_A_QMQ_ATM_FREE_VC8+1
  161. #define IX_NPE_A_QMQ_ATM_FREE_VC10 IX_NPE_A_QMQ_ATM_FREE_VC9+1
  162. #define IX_NPE_A_QMQ_ATM_FREE_VC11 IX_NPE_A_QMQ_ATM_FREE_VC10+1
  163. #define IX_NPE_A_QMQ_ATM_FREE_VC12 IX_NPE_A_QMQ_ATM_FREE_VC11+1
  164. #define IX_NPE_A_QMQ_ATM_FREE_VC13 IX_NPE_A_QMQ_ATM_FREE_VC12+1
  165. #define IX_NPE_A_QMQ_ATM_FREE_VC14 IX_NPE_A_QMQ_ATM_FREE_VC13+1
  166. #define IX_NPE_A_QMQ_ATM_FREE_VC15 IX_NPE_A_QMQ_ATM_FREE_VC14+1
  167. #define IX_NPE_A_QMQ_ATM_FREE_VC16 IX_NPE_A_QMQ_ATM_FREE_VC15+1
  168. #define IX_NPE_A_QMQ_ATM_FREE_VC17 IX_NPE_A_QMQ_ATM_FREE_VC16+1
  169. #define IX_NPE_A_QMQ_ATM_FREE_VC18 IX_NPE_A_QMQ_ATM_FREE_VC17+1
  170. #define IX_NPE_A_QMQ_ATM_FREE_VC19 IX_NPE_A_QMQ_ATM_FREE_VC18+1
  171. #define IX_NPE_A_QMQ_ATM_FREE_VC20 IX_NPE_A_QMQ_ATM_FREE_VC19+1
  172. #define IX_NPE_A_QMQ_ATM_FREE_VC21 IX_NPE_A_QMQ_ATM_FREE_VC20+1
  173. #define IX_NPE_A_QMQ_ATM_FREE_VC22 IX_NPE_A_QMQ_ATM_FREE_VC21+1
  174. #define IX_NPE_A_QMQ_ATM_FREE_VC23 IX_NPE_A_QMQ_ATM_FREE_VC22+1
  175. #define IX_NPE_A_QMQ_ATM_FREE_VC24 IX_NPE_A_QMQ_ATM_FREE_VC23+1
  176. #define IX_NPE_A_QMQ_ATM_FREE_VC25 IX_NPE_A_QMQ_ATM_FREE_VC24+1
  177. #define IX_NPE_A_QMQ_ATM_FREE_VC26 IX_NPE_A_QMQ_ATM_FREE_VC25+1
  178. #define IX_NPE_A_QMQ_ATM_FREE_VC27 IX_NPE_A_QMQ_ATM_FREE_VC26+1
  179. #define IX_NPE_A_QMQ_ATM_FREE_VC28 IX_NPE_A_QMQ_ATM_FREE_VC27+1
  180. #define IX_NPE_A_QMQ_ATM_FREE_VC29 IX_NPE_A_QMQ_ATM_FREE_VC28+1
  181. #define IX_NPE_A_QMQ_ATM_FREE_VC30 IX_NPE_A_QMQ_ATM_FREE_VC29+1
  182. #define IX_NPE_A_QMQ_ATM_FREE_VC31 IX_NPE_A_QMQ_ATM_FREE_VC30+1
  183. /**
  184. * @def IX_NPE_A_QMQ_ATM_RXFREE_MIN
  185. *
  186. * @brief The minimum queue ID for FreeVC queue
  187. */
  188. #define IX_NPE_A_QMQ_ATM_RXFREE_MIN IX_NPE_A_QMQ_ATM_FREE_VC0
  189. /**
  190. * @def IX_NPE_A_QMQ_ATM_RXFREE_MAX
  191. *
  192. * @brief The maximum queue ID for FreeVC queue
  193. */
  194. #define IX_NPE_A_QMQ_ATM_RXFREE_MAX IX_NPE_A_QMQ_ATM_FREE_VC31
  195. /**
  196. * @def IX_NPE_A_QMQ_OAM_FREE_VC
  197. * @brief OAM Rx Free queue ID
  198. */
  199. #ifdef IX_NPE_MPHYMULTIPORT
  200. #define IX_NPE_A_QMQ_OAM_FREE_VC IX_QMGR_QUEUE_14
  201. #else
  202. #define IX_NPE_A_QMQ_OAM_FREE_VC IX_QMGR_QUEUE_3
  203. #endif /* MPHY */
  204. /****************************************************************************
  205. * Queue assignments for HSS
  206. ****************************************************************************/
  207. /**** HSS Port 0 ****/
  208. /**
  209. * @def IX_NPE_A_QMQ_HSS0_CHL_RX_TRIG
  210. *
  211. * @brief Hardware QMgr Queue ID for HSS Port 0 Channelized Receive trigger
  212. */
  213. #define IX_NPE_A_QMQ_HSS0_CHL_RX_TRIG IX_QMGR_QUEUE_12
  214. /**
  215. * @def IX_NPE_A_QMQ_HSS0_PKT_RX
  216. *
  217. * @brief Hardware QMgr Queue ID for HSS Port 0 Packetized Receive
  218. */
  219. #define IX_NPE_A_QMQ_HSS0_PKT_RX IX_QMGR_QUEUE_13
  220. /**
  221. * @def IX_NPE_A_QMQ_HSS0_PKT_TX0
  222. *
  223. * @brief Hardware QMgr Queue ID for HSS Port 0 Packetized Transmit queue 0
  224. */
  225. #define IX_NPE_A_QMQ_HSS0_PKT_TX0 IX_QMGR_QUEUE_14
  226. /**
  227. * @def IX_NPE_A_QMQ_HSS0_PKT_TX1
  228. *
  229. * @brief Hardware QMgr Queue ID for HSS Port 0 Packetized Transmit queue 1
  230. */
  231. #define IX_NPE_A_QMQ_HSS0_PKT_TX1 IX_QMGR_QUEUE_15
  232. /**
  233. * @def IX_NPE_A_QMQ_HSS0_PKT_TX2
  234. *
  235. * @brief Hardware QMgr Queue ID for HSS Port 0 Packetized Transmit queue 2
  236. */
  237. #define IX_NPE_A_QMQ_HSS0_PKT_TX2 IX_QMGR_QUEUE_16
  238. /**
  239. * @def IX_NPE_A_QMQ_HSS0_PKT_TX3
  240. *
  241. * @brief Hardware QMgr Queue ID for HSS Port 0 Packetized Transmit queue 3
  242. */
  243. #define IX_NPE_A_QMQ_HSS0_PKT_TX3 IX_QMGR_QUEUE_17
  244. /**
  245. * @def IX_NPE_A_QMQ_HSS0_PKT_RX_FREE0
  246. *
  247. * @brief Hardware QMgr Queue ID for HSS Port 0 Packetized Receive Free queue 0
  248. */
  249. #define IX_NPE_A_QMQ_HSS0_PKT_RX_FREE0 IX_QMGR_QUEUE_18
  250. /**
  251. * @def IX_NPE_A_QMQ_HSS0_PKT_RX_FREE1
  252. *
  253. * @brief Hardware QMgr Queue ID for HSS Port 0 Packetized Receive Free queue 1
  254. */
  255. #define IX_NPE_A_QMQ_HSS0_PKT_RX_FREE1 IX_QMGR_QUEUE_19
  256. /**
  257. * @def IX_NPE_A_QMQ_HSS0_PKT_RX_FREE2
  258. *
  259. * @brief Hardware QMgr Queue ID for HSS Port 0 Packetized Receive Free queue 2
  260. */
  261. #define IX_NPE_A_QMQ_HSS0_PKT_RX_FREE2 IX_QMGR_QUEUE_20
  262. /**
  263. * @def IX_NPE_A_QMQ_HSS0_PKT_RX_FREE3
  264. *
  265. * @brief Hardware QMgr Queue ID for HSS Port 0 Packetized Receive Free queue 3
  266. */
  267. #define IX_NPE_A_QMQ_HSS0_PKT_RX_FREE3 IX_QMGR_QUEUE_21
  268. /**
  269. * @def IX_NPE_A_QMQ_HSS0_PKT_TX_DONE
  270. *
  271. * @brief Hardware QMgr Queue ID for HSS Port 0 Packetized Transmit Done queue
  272. */
  273. #define IX_NPE_A_QMQ_HSS0_PKT_TX_DONE IX_QMGR_QUEUE_22
  274. /**** HSS Port 1 ****/
  275. /**
  276. * @def IX_NPE_A_QMQ_HSS1_CHL_RX_TRIG
  277. *
  278. * @brief Hardware QMgr Queue ID for HSS Port 1 Channelized Receive trigger
  279. */
  280. #define IX_NPE_A_QMQ_HSS1_CHL_RX_TRIG IX_QMGR_QUEUE_10
  281. /**
  282. * @def IX_NPE_A_QMQ_HSS1_PKT_RX
  283. *
  284. * @brief Hardware QMgr Queue ID for HSS Port 1 Packetized Receive
  285. */
  286. #define IX_NPE_A_QMQ_HSS1_PKT_RX IX_QMGR_QUEUE_0
  287. /**
  288. * @def IX_NPE_A_QMQ_HSS1_PKT_TX0
  289. *
  290. * @brief Hardware QMgr Queue ID for HSS Port 1 Packetized Transmit queue 0
  291. */
  292. #define IX_NPE_A_QMQ_HSS1_PKT_TX0 IX_QMGR_QUEUE_5
  293. /**
  294. * @def IX_NPE_A_QMQ_HSS1_PKT_TX1
  295. *
  296. * @brief Hardware QMgr Queue ID for HSS Port 1 Packetized Transmit queue 1
  297. */
  298. #define IX_NPE_A_QMQ_HSS1_PKT_TX1 IX_QMGR_QUEUE_6
  299. /**
  300. * @def IX_NPE_A_QMQ_HSS1_PKT_TX2
  301. *
  302. * @brief Hardware QMgr Queue ID for HSS Port 1 Packetized Transmit queue 2
  303. */
  304. #define IX_NPE_A_QMQ_HSS1_PKT_TX2 IX_QMGR_QUEUE_7
  305. /**
  306. * @def IX_NPE_A_QMQ_HSS1_PKT_TX3
  307. *
  308. * @brief Hardware QMgr Queue ID for HSS Port 1 Packetized Transmit queue 3
  309. */
  310. #define IX_NPE_A_QMQ_HSS1_PKT_TX3 IX_QMGR_QUEUE_8
  311. /**
  312. * @def IX_NPE_A_QMQ_HSS1_PKT_RX_FREE0
  313. *
  314. * @brief Hardware QMgr Queue ID for HSS Port 1 Packetized Receive Free queue 0
  315. */
  316. #define IX_NPE_A_QMQ_HSS1_PKT_RX_FREE0 IX_QMGR_QUEUE_1
  317. /**
  318. * @def IX_NPE_A_QMQ_HSS1_PKT_RX_FREE1
  319. *
  320. * @brief Hardware QMgr Queue ID for HSS Port 1 Packetized Receive Free queue 1
  321. */
  322. #define IX_NPE_A_QMQ_HSS1_PKT_RX_FREE1 IX_QMGR_QUEUE_2
  323. /**
  324. * @def IX_NPE_A_QMQ_HSS1_PKT_RX_FREE2
  325. *
  326. * @brief Hardware QMgr Queue ID for HSS Port 1 Packetized Receive Free queue 2
  327. */
  328. #define IX_NPE_A_QMQ_HSS1_PKT_RX_FREE2 IX_QMGR_QUEUE_3
  329. /**
  330. * @def IX_NPE_A_QMQ_HSS1_PKT_RX_FREE3
  331. *
  332. * @brief Hardware QMgr Queue ID for HSS Port 1 Packetized Receive Free queue 3
  333. */
  334. #define IX_NPE_A_QMQ_HSS1_PKT_RX_FREE3 IX_QMGR_QUEUE_4
  335. /**
  336. * @def IX_NPE_A_QMQ_HSS1_PKT_TX_DONE
  337. *
  338. * @brief Hardware QMgr Queue ID for HSS Port 1 Packetized Transmit Done queue
  339. */
  340. #define IX_NPE_A_QMQ_HSS1_PKT_TX_DONE IX_QMGR_QUEUE_9
  341. /*****************************************************************************************
  342. * Queue assignments for DMA
  343. *****************************************************************************************/
  344. #define IX_DMA_NPE_A_REQUEST_QID IX_QMGR_QUEUE_19 /**< Queue Id for NPE A DMA Request */
  345. #define IX_DMA_NPE_A_DONE_QID IX_QMGR_QUEUE_20 /**< Queue Id for NPE A DMA Done */
  346. #define IX_DMA_NPE_B_REQUEST_QID IX_QMGR_QUEUE_24 /**< Queue Id for NPE B DMA Request */
  347. #define IX_DMA_NPE_B_DONE_QID IX_QMGR_QUEUE_26 /**< Queue Id for NPE B DMA Done */
  348. #define IX_DMA_NPE_C_REQUEST_QID IX_QMGR_QUEUE_25 /**< Queue Id for NPE C DMA Request */
  349. #define IX_DMA_NPE_C_DONE_QID IX_QMGR_QUEUE_27 /**< Queue Id for NPE C DMA Done */
  350. /*****************************************************************************************
  351. * Queue assignments for Ethernet
  352. *
  353. * Note: Rx queue definitions, which include QoS traffic class definitions
  354. * are managed by EthDB and declared in IxEthDBQoS.h
  355. *****************************************************************************************/
  356. /**
  357. *
  358. * @def IX_ETH_ACC_RX_FRAME_ETH_Q
  359. *
  360. * @brief Eth0/Eth1 NPE Frame Receive Q.
  361. *
  362. * @note THIS IS NOT USED - the Rx queues are read from EthDB QoS configuration
  363. *
  364. */
  365. #define IX_ETH_ACC_RX_FRAME_ETH_Q (IX_QMGR_QUEUE_4)
  366. /**
  367. *
  368. * @def IX_ETH_ACC_RX_FREE_BUFF_ENET0_Q
  369. *
  370. * @brief Supply Rx Buffers Ethernet Q for NPEB - Eth 0 - Port 1
  371. *
  372. */
  373. #define IX_ETH_ACC_RX_FREE_BUFF_ENET0_Q (IX_QMGR_QUEUE_27)
  374. /**
  375. *
  376. * @def IX_ETH_ACC_RX_FREE_BUFF_ENET1_Q
  377. *
  378. * @brief Supply Rx Buffers Ethernet Q for NPEC - Eth 1 - Port 2
  379. *
  380. */
  381. #define IX_ETH_ACC_RX_FREE_BUFF_ENET1_Q (IX_QMGR_QUEUE_28)
  382. /**
  383. *
  384. * @def IX_ETH_ACC_RX_FREE_BUFF_ENET2_Q
  385. *
  386. * @brief Supply Rx Buffers Ethernet Q for NPEA - Eth 2 - Port 3
  387. *
  388. */
  389. #define IX_ETH_ACC_RX_FREE_BUFF_ENET2_Q (IX_QMGR_QUEUE_26)
  390. /**
  391. *
  392. * @def IX_ETH_ACC_TX_FRAME_ENET0_Q
  393. *
  394. * @brief Submit frame Q for NPEB Eth 0 - Port 1
  395. *
  396. */
  397. #define IX_ETH_ACC_TX_FRAME_ENET0_Q (IX_QMGR_QUEUE_24)
  398. /**
  399. *
  400. * @def IX_ETH_ACC_TX_FRAME_ENET1_Q
  401. *
  402. * @brief Submit frame Q for NPEC Eth 1 - Port 2
  403. *
  404. */
  405. #define IX_ETH_ACC_TX_FRAME_ENET1_Q (IX_QMGR_QUEUE_25)
  406. /**
  407. *
  408. * @def IX_ETH_ACC_TX_FRAME_ENET2_Q
  409. *
  410. * @brief Submit frame Q for NPEA Eth 2 - Port 3
  411. *
  412. */
  413. #define IX_ETH_ACC_TX_FRAME_ENET2_Q (IX_QMGR_QUEUE_23)
  414. /**
  415. *
  416. * @def IX_ETH_ACC_TX_FRAME_DONE_ETH_Q
  417. *
  418. * @brief Transmit complete Q for NPE Eth 0/1, Port 1&2
  419. *
  420. */
  421. #define IX_ETH_ACC_TX_FRAME_DONE_ETH_Q (IX_QMGR_QUEUE_31)
  422. /*****************************************************************************************
  423. * Queue assignments for Crypto
  424. *****************************************************************************************/
  425. /** Crypto Service Request Queue */
  426. #define IX_CRYPTO_ACC_CRYPTO_REQ_Q (IX_QMGR_QUEUE_29)
  427. /** Crypto Service Done Queue */
  428. #define IX_CRYPTO_ACC_CRYPTO_DONE_Q (IX_QMGR_QUEUE_30)
  429. /** Crypto Req Q CB tag */
  430. #define IX_CRYPTO_ACC_CRYPTO_REQ_Q_CB_TAG (0)
  431. /** Crypto Done Q CB tag */
  432. #define IX_CRYPTO_ACC_CRYPTO_DONE_Q_CB_TAG (1)
  433. /** WEP Service Request Queue */
  434. #define IX_CRYPTO_ACC_WEP_REQ_Q (IX_QMGR_QUEUE_21)
  435. /** WEP Service Done Queue */
  436. #define IX_CRYPTO_ACC_WEP_DONE_Q (IX_QMGR_QUEUE_22)
  437. /** WEP Req Q CB tag */
  438. #define IX_CRYPTO_ACC_WEP_REQ_Q_CB_TAG (2)
  439. /** WEP Done Q CB tag */
  440. #define IX_CRYPTO_ACC_WEP_DONE_Q_CB_TAG (3)
  441. /** Number of queues allocate to crypto hardware accelerator services */
  442. #define IX_CRYPTO_ACC_NUM_OF_CRYPTO_Q (2)
  443. /** Number of queues allocate to WEP NPE services */
  444. #define IX_CRYPTO_ACC_NUM_OF_WEP_NPE_Q (2)
  445. /** Number of queues allocate to CryptoAcc component */
  446. #define IX_CRYPTO_ACC_NUM_OF_Q (IX_CRYPTO_ACC_NUM_OF_CRYPTO_Q + IX_CRYPTO_ACC_NUM_OF_WEP_NPE_Q)
  447. #endif /* IxQueueAssignments_H */