natsemi.c 23 KB

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  1. /*
  2. natsemi.c: A U-Boot driver for the NatSemi DP8381x series.
  3. Author: Mark A. Rakes (mark_rakes@vivato.net)
  4. Adapted from an Etherboot driver written by:
  5. Copyright (C) 2001 Entity Cyber, Inc.
  6. This development of this Etherboot driver was funded by
  7. Sicom Systems: http://www.sicompos.com/
  8. Author: Marty Connor (mdc@thinguin.org)
  9. Adapted from a Linux driver which was written by Donald Becker
  10. This software may be used and distributed according to the terms
  11. of the GNU Public License (GPL), incorporated herein by reference.
  12. Original Copyright Notice:
  13. Written/copyright 1999-2001 by Donald Becker.
  14. This software may be used and distributed according to the terms of
  15. the GNU General Public License (GPL), incorporated herein by reference.
  16. Drivers based on or derived from this code fall under the GPL and must
  17. retain the authorship, copyright and license notice. This file is not
  18. a complete program and may only be used when the entire operating
  19. system is licensed under the GPL. License for under other terms may be
  20. available. Contact the original author for details.
  21. The original author may be reached as becker@scyld.com, or at
  22. Scyld Computing Corporation
  23. 410 Severn Ave., Suite 210
  24. Annapolis MD 21403
  25. Support information and updates available at
  26. http://www.scyld.com/network/netsemi.html
  27. References:
  28. http://www.scyld.com/expert/100mbps.html
  29. http://www.scyld.com/expert/NWay.html
  30. Datasheet is available from:
  31. http://www.national.com/pf/DP/DP83815.html
  32. */
  33. /* Revision History
  34. * October 2002 mar 1.0
  35. * Initial U-Boot Release. Tested with Netgear FA311 board
  36. * and dp83815 chipset on custom board
  37. */
  38. /* Includes */
  39. #include <common.h>
  40. #include <malloc.h>
  41. #include <net.h>
  42. #include <netdev.h>
  43. #include <asm/io.h>
  44. #include <pci.h>
  45. /* defines */
  46. #define EEPROM_SIZE 0xb /*12 16-bit chunks, or 24 bytes*/
  47. #define DSIZE 0x00000FFF
  48. #define ETH_ALEN 6
  49. #define CRC_SIZE 4
  50. #define TOUT_LOOP 500000
  51. #define TX_BUF_SIZE 1536
  52. #define RX_BUF_SIZE 1536
  53. #define NUM_RX_DESC 4 /* Number of Rx descriptor registers. */
  54. /* Offsets to the device registers.
  55. Unlike software-only systems, device drivers interact with complex hardware.
  56. It's not useful to define symbolic names for every register bit in the
  57. device. */
  58. enum register_offsets {
  59. ChipCmd = 0x00,
  60. ChipConfig = 0x04,
  61. EECtrl = 0x08,
  62. IntrMask = 0x14,
  63. IntrEnable = 0x18,
  64. TxRingPtr = 0x20,
  65. TxConfig = 0x24,
  66. RxRingPtr = 0x30,
  67. RxConfig = 0x34,
  68. ClkRun = 0x3C,
  69. RxFilterAddr = 0x48,
  70. RxFilterData = 0x4C,
  71. SiliconRev = 0x58,
  72. PCIPM = 0x44,
  73. BasicControl = 0x80,
  74. BasicStatus = 0x84,
  75. /* These are from the spec, around page 78... on a separate table. */
  76. PGSEL = 0xCC,
  77. PMDCSR = 0xE4,
  78. TSTDAT = 0xFC,
  79. DSPCFG = 0xF4,
  80. SDCFG = 0x8C
  81. };
  82. /* Bit in ChipCmd. */
  83. enum ChipCmdBits {
  84. ChipReset = 0x100,
  85. RxReset = 0x20,
  86. TxReset = 0x10,
  87. RxOff = 0x08,
  88. RxOn = 0x04,
  89. TxOff = 0x02,
  90. TxOn = 0x01
  91. };
  92. enum ChipConfigBits {
  93. LinkSts = 0x80000000,
  94. HundSpeed = 0x40000000,
  95. FullDuplex = 0x20000000,
  96. TenPolarity = 0x10000000,
  97. AnegDone = 0x08000000,
  98. AnegEnBothBoth = 0x0000E000,
  99. AnegDis100Full = 0x0000C000,
  100. AnegEn100Both = 0x0000A000,
  101. AnegDis100Half = 0x00008000,
  102. AnegEnBothHalf = 0x00006000,
  103. AnegDis10Full = 0x00004000,
  104. AnegEn10Both = 0x00002000,
  105. DuplexMask = 0x00008000,
  106. SpeedMask = 0x00004000,
  107. AnegMask = 0x00002000,
  108. AnegDis10Half = 0x00000000,
  109. ExtPhy = 0x00001000,
  110. PhyRst = 0x00000400,
  111. PhyDis = 0x00000200,
  112. BootRomDisable = 0x00000004,
  113. BEMode = 0x00000001,
  114. };
  115. enum TxConfig_bits {
  116. TxDrthMask = 0x3f,
  117. TxFlthMask = 0x3f00,
  118. TxMxdmaMask = 0x700000,
  119. TxMxdma_512 = 0x0,
  120. TxMxdma_4 = 0x100000,
  121. TxMxdma_8 = 0x200000,
  122. TxMxdma_16 = 0x300000,
  123. TxMxdma_32 = 0x400000,
  124. TxMxdma_64 = 0x500000,
  125. TxMxdma_128 = 0x600000,
  126. TxMxdma_256 = 0x700000,
  127. TxCollRetry = 0x800000,
  128. TxAutoPad = 0x10000000,
  129. TxMacLoop = 0x20000000,
  130. TxHeartIgn = 0x40000000,
  131. TxCarrierIgn = 0x80000000
  132. };
  133. enum RxConfig_bits {
  134. RxDrthMask = 0x3e,
  135. RxMxdmaMask = 0x700000,
  136. RxMxdma_512 = 0x0,
  137. RxMxdma_4 = 0x100000,
  138. RxMxdma_8 = 0x200000,
  139. RxMxdma_16 = 0x300000,
  140. RxMxdma_32 = 0x400000,
  141. RxMxdma_64 = 0x500000,
  142. RxMxdma_128 = 0x600000,
  143. RxMxdma_256 = 0x700000,
  144. RxAcceptLong = 0x8000000,
  145. RxAcceptTx = 0x10000000,
  146. RxAcceptRunt = 0x40000000,
  147. RxAcceptErr = 0x80000000
  148. };
  149. /* Bits in the RxMode register. */
  150. enum rx_mode_bits {
  151. AcceptErr = 0x20,
  152. AcceptRunt = 0x10,
  153. AcceptBroadcast = 0xC0000000,
  154. AcceptMulticast = 0x00200000,
  155. AcceptAllMulticast = 0x20000000,
  156. AcceptAllPhys = 0x10000000,
  157. AcceptMyPhys = 0x08000000
  158. };
  159. typedef struct _BufferDesc {
  160. u32 link;
  161. vu_long cmdsts;
  162. u32 bufptr;
  163. u32 software_use;
  164. } BufferDesc;
  165. /* Bits in network_desc.status */
  166. enum desc_status_bits {
  167. DescOwn = 0x80000000, DescMore = 0x40000000, DescIntr = 0x20000000,
  168. DescNoCRC = 0x10000000, DescPktOK = 0x08000000,
  169. DescSizeMask = 0xfff,
  170. DescTxAbort = 0x04000000, DescTxFIFO = 0x02000000,
  171. DescTxCarrier = 0x01000000, DescTxDefer = 0x00800000,
  172. DescTxExcDefer = 0x00400000, DescTxOOWCol = 0x00200000,
  173. DescTxExcColl = 0x00100000, DescTxCollCount = 0x000f0000,
  174. DescRxAbort = 0x04000000, DescRxOver = 0x02000000,
  175. DescRxDest = 0x01800000, DescRxLong = 0x00400000,
  176. DescRxRunt = 0x00200000, DescRxInvalid = 0x00100000,
  177. DescRxCRC = 0x00080000, DescRxAlign = 0x00040000,
  178. DescRxLoop = 0x00020000, DesRxColl = 0x00010000,
  179. };
  180. /* Globals */
  181. #ifdef NATSEMI_DEBUG
  182. static int natsemi_debug = 0; /* 1 verbose debugging, 0 normal */
  183. #endif
  184. static u32 SavedClkRun;
  185. static unsigned int cur_rx;
  186. static unsigned int advertising;
  187. static unsigned int rx_config;
  188. static unsigned int tx_config;
  189. /* Note: transmit and receive buffers and descriptors must be
  190. longword aligned */
  191. static BufferDesc txd __attribute__ ((aligned(4)));
  192. static BufferDesc rxd[NUM_RX_DESC] __attribute__ ((aligned(4)));
  193. static unsigned char txb[TX_BUF_SIZE] __attribute__ ((aligned(4)));
  194. static unsigned char rxb[NUM_RX_DESC * RX_BUF_SIZE]
  195. __attribute__ ((aligned(4)));
  196. /* Function Prototypes */
  197. #if 0
  198. static void write_eeprom(struct eth_device *dev, long addr, int location,
  199. short value);
  200. #endif
  201. static int read_eeprom(struct eth_device *dev, long addr, int location);
  202. static int mdio_read(struct eth_device *dev, int phy_id, int location);
  203. static int natsemi_init(struct eth_device *dev, bd_t * bis);
  204. static void natsemi_reset(struct eth_device *dev);
  205. static void natsemi_init_rxfilter(struct eth_device *dev);
  206. static void natsemi_init_txd(struct eth_device *dev);
  207. static void natsemi_init_rxd(struct eth_device *dev);
  208. static void natsemi_set_rx_mode(struct eth_device *dev);
  209. static void natsemi_check_duplex(struct eth_device *dev);
  210. static int natsemi_send(struct eth_device *dev, volatile void *packet,
  211. int length);
  212. static int natsemi_poll(struct eth_device *dev);
  213. static void natsemi_disable(struct eth_device *dev);
  214. static struct pci_device_id supported[] = {
  215. {PCI_VENDOR_ID_NS, PCI_DEVICE_ID_NS_83815},
  216. {}
  217. };
  218. #define bus_to_phys(a) pci_mem_to_phys((pci_dev_t)dev->priv, a)
  219. #define phys_to_bus(a) pci_phys_to_mem((pci_dev_t)dev->priv, a)
  220. static inline int
  221. INW(struct eth_device *dev, u_long addr)
  222. {
  223. return le16_to_cpu(*(vu_short *) (addr + dev->iobase));
  224. }
  225. static int
  226. INL(struct eth_device *dev, u_long addr)
  227. {
  228. return le32_to_cpu(*(vu_long *) (addr + dev->iobase));
  229. }
  230. static inline void
  231. OUTW(struct eth_device *dev, int command, u_long addr)
  232. {
  233. *(vu_short *) ((addr + dev->iobase)) = cpu_to_le16(command);
  234. }
  235. static inline void
  236. OUTL(struct eth_device *dev, int command, u_long addr)
  237. {
  238. *(vu_long *) ((addr + dev->iobase)) = cpu_to_le32(command);
  239. }
  240. /*
  241. * Function: natsemi_initialize
  242. *
  243. * Description: Retrieves the MAC address of the card, and sets up some
  244. * globals required by other routines, and initializes the NIC, making it
  245. * ready to send and receive packets.
  246. *
  247. * Side effects:
  248. * leaves the natsemi initialized, and ready to receive packets.
  249. *
  250. * Returns: struct eth_device *: pointer to NIC data structure
  251. */
  252. int
  253. natsemi_initialize(bd_t * bis)
  254. {
  255. pci_dev_t devno;
  256. int card_number = 0;
  257. struct eth_device *dev;
  258. u32 iobase, status, chip_config;
  259. int i, idx = 0;
  260. int prev_eedata;
  261. u32 tmp;
  262. while (1) {
  263. /* Find PCI device(s) */
  264. if ((devno = pci_find_devices(supported, idx++)) < 0) {
  265. break;
  266. }
  267. pci_read_config_dword(devno, PCI_BASE_ADDRESS_0, &iobase);
  268. iobase &= ~0x3; /* bit 1: unused and bit 0: I/O Space Indicator */
  269. pci_write_config_dword(devno, PCI_COMMAND,
  270. PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER);
  271. /* Check if I/O accesses and Bus Mastering are enabled. */
  272. pci_read_config_dword(devno, PCI_COMMAND, &status);
  273. if (!(status & PCI_COMMAND_MEMORY)) {
  274. printf("Error: Can not enable MEM access.\n");
  275. continue;
  276. } else if (!(status & PCI_COMMAND_MASTER)) {
  277. printf("Error: Can not enable Bus Mastering.\n");
  278. continue;
  279. }
  280. dev = (struct eth_device *) malloc(sizeof *dev);
  281. if (!dev) {
  282. printf("natsemi: Can not allocate memory\n");
  283. break;
  284. }
  285. memset(dev, 0, sizeof(*dev));
  286. sprintf(dev->name, "dp83815#%d", card_number);
  287. dev->iobase = bus_to_phys(iobase);
  288. #ifdef NATSEMI_DEBUG
  289. printf("natsemi: NatSemi ns8381[56] @ %#x\n", dev->iobase);
  290. #endif
  291. dev->priv = (void *) devno;
  292. dev->init = natsemi_init;
  293. dev->halt = natsemi_disable;
  294. dev->send = natsemi_send;
  295. dev->recv = natsemi_poll;
  296. eth_register(dev);
  297. card_number++;
  298. /* Set the latency timer for value. */
  299. pci_write_config_byte(devno, PCI_LATENCY_TIMER, 0x20);
  300. udelay(10 * 1000);
  301. /* natsemi has a non-standard PM control register
  302. * in PCI config space. Some boards apparently need
  303. * to be brought to D0 in this manner. */
  304. pci_read_config_dword(devno, PCIPM, &tmp);
  305. if (tmp & (0x03 | 0x100)) {
  306. /* D0 state, disable PME assertion */
  307. u32 newtmp = tmp & ~(0x03 | 0x100);
  308. pci_write_config_dword(devno, PCIPM, newtmp);
  309. }
  310. printf("natsemi: EEPROM contents:\n");
  311. for (i = 0; i <= EEPROM_SIZE; i++) {
  312. short eedata = read_eeprom(dev, EECtrl, i);
  313. printf(" %04hx", eedata);
  314. }
  315. printf("\n");
  316. /* get MAC address */
  317. prev_eedata = read_eeprom(dev, EECtrl, 6);
  318. for (i = 0; i < 3; i++) {
  319. int eedata = read_eeprom(dev, EECtrl, i + 7);
  320. dev->enetaddr[i*2] = (eedata << 1) + (prev_eedata >> 15);
  321. dev->enetaddr[i*2+1] = eedata >> 7;
  322. prev_eedata = eedata;
  323. }
  324. /* Reset the chip to erase any previous misconfiguration. */
  325. OUTL(dev, ChipReset, ChipCmd);
  326. advertising = mdio_read(dev, 1, 4);
  327. chip_config = INL(dev, ChipConfig);
  328. #ifdef NATSEMI_DEBUG
  329. printf("%s: Transceiver status %#08X advertising %#08X\n",
  330. dev->name, (int) INL(dev, BasicStatus), advertising);
  331. printf("%s: Transceiver default autoneg. %s 10%s %s duplex.\n",
  332. dev->name, chip_config & AnegMask ? "enabled, advertise" :
  333. "disabled, force", chip_config & SpeedMask ? "0" : "",
  334. chip_config & DuplexMask ? "full" : "half");
  335. #endif
  336. chip_config |= AnegEnBothBoth;
  337. #ifdef NATSEMI_DEBUG
  338. printf("%s: changed to autoneg. %s 10%s %s duplex.\n",
  339. dev->name, chip_config & AnegMask ? "enabled, advertise" :
  340. "disabled, force", chip_config & SpeedMask ? "0" : "",
  341. chip_config & DuplexMask ? "full" : "half");
  342. #endif
  343. /*write new autoneg bits, reset phy*/
  344. OUTL(dev, (chip_config | PhyRst), ChipConfig);
  345. /*un-reset phy*/
  346. OUTL(dev, chip_config, ChipConfig);
  347. /* Disable PME:
  348. * The PME bit is initialized from the EEPROM contents.
  349. * PCI cards probably have PME disabled, but motherboard
  350. * implementations may have PME set to enable WakeOnLan.
  351. * With PME set the chip will scan incoming packets but
  352. * nothing will be written to memory. */
  353. SavedClkRun = INL(dev, ClkRun);
  354. OUTL(dev, SavedClkRun & ~0x100, ClkRun);
  355. }
  356. return card_number;
  357. }
  358. /* Read the EEPROM and MII Management Data I/O (MDIO) interfaces.
  359. The EEPROM code is for common 93c06/46 EEPROMs w/ 6bit addresses. */
  360. /* Delay between EEPROM clock transitions.
  361. No extra delay is needed with 33MHz PCI, but future 66MHz
  362. access may need a delay. */
  363. #define eeprom_delay(ee_addr) INL(dev, ee_addr)
  364. enum EEPROM_Ctrl_Bits {
  365. EE_ShiftClk = 0x04,
  366. EE_DataIn = 0x01,
  367. EE_ChipSelect = 0x08,
  368. EE_DataOut = 0x02
  369. };
  370. #define EE_Write0 (EE_ChipSelect)
  371. #define EE_Write1 (EE_ChipSelect | EE_DataIn)
  372. /* The EEPROM commands include the alway-set leading bit. */
  373. enum EEPROM_Cmds {
  374. EE_WrEnCmd = (4 << 6), EE_WriteCmd = (5 << 6),
  375. EE_ReadCmd = (6 << 6), EE_EraseCmd = (7 << 6),
  376. };
  377. #if 0
  378. static void
  379. write_eeprom(struct eth_device *dev, long addr, int location, short value)
  380. {
  381. int i;
  382. int ee_addr = (typeof(ee_addr))addr;
  383. short wren_cmd = EE_WrEnCmd | 0x30; /*wren is 100 + 11XXXX*/
  384. short write_cmd = location | EE_WriteCmd;
  385. #ifdef NATSEMI_DEBUG
  386. printf("write_eeprom: %08x, %04hx, %04hx\n",
  387. dev->iobase + ee_addr, write_cmd, value);
  388. #endif
  389. /* Shift the write enable command bits out. */
  390. for (i = 9; i >= 0; i--) {
  391. short cmdval = (wren_cmd & (1 << i)) ? EE_Write1 : EE_Write0;
  392. OUTL(dev, cmdval, ee_addr);
  393. eeprom_delay(ee_addr);
  394. OUTL(dev, cmdval | EE_ShiftClk, ee_addr);
  395. eeprom_delay(ee_addr);
  396. }
  397. OUTL(dev, 0, ee_addr); /*bring chip select low*/
  398. OUTL(dev, EE_ShiftClk, ee_addr);
  399. eeprom_delay(ee_addr);
  400. /* Shift the write command bits out. */
  401. for (i = 9; i >= 0; i--) {
  402. short cmdval = (write_cmd & (1 << i)) ? EE_Write1 : EE_Write0;
  403. OUTL(dev, cmdval, ee_addr);
  404. eeprom_delay(ee_addr);
  405. OUTL(dev, cmdval | EE_ShiftClk, ee_addr);
  406. eeprom_delay(ee_addr);
  407. }
  408. for (i = 0; i < 16; i++) {
  409. short cmdval = (value & (1 << i)) ? EE_Write1 : EE_Write0;
  410. OUTL(dev, cmdval, ee_addr);
  411. eeprom_delay(ee_addr);
  412. OUTL(dev, cmdval | EE_ShiftClk, ee_addr);
  413. eeprom_delay(ee_addr);
  414. }
  415. OUTL(dev, 0, ee_addr); /*bring chip select low*/
  416. OUTL(dev, EE_ShiftClk, ee_addr);
  417. for (i = 0; i < 200000; i++) {
  418. OUTL(dev, EE_Write0, ee_addr); /*poll for done*/
  419. if (INL(dev, ee_addr) & EE_DataOut) {
  420. break; /*finished*/
  421. }
  422. }
  423. eeprom_delay(ee_addr);
  424. /* Terminate the EEPROM access. */
  425. OUTL(dev, EE_Write0, ee_addr);
  426. OUTL(dev, 0, ee_addr);
  427. return;
  428. }
  429. #endif
  430. static int
  431. read_eeprom(struct eth_device *dev, long addr, int location)
  432. {
  433. int i;
  434. int retval = 0;
  435. int ee_addr = (typeof(ee_addr))addr;
  436. int read_cmd = location | EE_ReadCmd;
  437. OUTL(dev, EE_Write0, ee_addr);
  438. /* Shift the read command bits out. */
  439. for (i = 10; i >= 0; i--) {
  440. short dataval = (read_cmd & (1 << i)) ? EE_Write1 : EE_Write0;
  441. OUTL(dev, dataval, ee_addr);
  442. eeprom_delay(ee_addr);
  443. OUTL(dev, dataval | EE_ShiftClk, ee_addr);
  444. eeprom_delay(ee_addr);
  445. }
  446. OUTL(dev, EE_ChipSelect, ee_addr);
  447. eeprom_delay(ee_addr);
  448. for (i = 0; i < 16; i++) {
  449. OUTL(dev, EE_ChipSelect | EE_ShiftClk, ee_addr);
  450. eeprom_delay(ee_addr);
  451. retval |= (INL(dev, ee_addr) & EE_DataOut) ? 1 << i : 0;
  452. OUTL(dev, EE_ChipSelect, ee_addr);
  453. eeprom_delay(ee_addr);
  454. }
  455. /* Terminate the EEPROM access. */
  456. OUTL(dev, EE_Write0, ee_addr);
  457. OUTL(dev, 0, ee_addr);
  458. #ifdef NATSEMI_DEBUG
  459. if (natsemi_debug)
  460. printf("read_eeprom: %08x, %08x, retval %08x\n",
  461. dev->iobase + ee_addr, read_cmd, retval);
  462. #endif
  463. return retval;
  464. }
  465. /* MII transceiver control section.
  466. The 83815 series has an internal transceiver, and we present the
  467. management registers as if they were MII connected. */
  468. static int
  469. mdio_read(struct eth_device *dev, int phy_id, int location)
  470. {
  471. if (phy_id == 1 && location < 32)
  472. return INL(dev, BasicControl+(location<<2))&0xffff;
  473. else
  474. return 0xffff;
  475. }
  476. /* Function: natsemi_init
  477. *
  478. * Description: resets the ethernet controller chip and configures
  479. * registers and data structures required for sending and receiving packets.
  480. *
  481. * Arguments: struct eth_device *dev: NIC data structure
  482. *
  483. * returns: int.
  484. */
  485. static int
  486. natsemi_init(struct eth_device *dev, bd_t * bis)
  487. {
  488. natsemi_reset(dev);
  489. /* Disable PME:
  490. * The PME bit is initialized from the EEPROM contents.
  491. * PCI cards probably have PME disabled, but motherboard
  492. * implementations may have PME set to enable WakeOnLan.
  493. * With PME set the chip will scan incoming packets but
  494. * nothing will be written to memory. */
  495. OUTL(dev, SavedClkRun & ~0x100, ClkRun);
  496. natsemi_init_rxfilter(dev);
  497. natsemi_init_txd(dev);
  498. natsemi_init_rxd(dev);
  499. /* Configure the PCI bus bursts and FIFO thresholds. */
  500. tx_config = TxAutoPad | TxCollRetry | TxMxdma_256 | (0x1002);
  501. rx_config = RxMxdma_256 | 0x20;
  502. #ifdef NATSEMI_DEBUG
  503. printf("%s: Setting TxConfig Register %#08X\n", dev->name, tx_config);
  504. printf("%s: Setting RxConfig Register %#08X\n", dev->name, rx_config);
  505. #endif
  506. OUTL(dev, tx_config, TxConfig);
  507. OUTL(dev, rx_config, RxConfig);
  508. natsemi_check_duplex(dev);
  509. natsemi_set_rx_mode(dev);
  510. OUTL(dev, (RxOn | TxOn), ChipCmd);
  511. return 1;
  512. }
  513. /*
  514. * Function: natsemi_reset
  515. *
  516. * Description: soft resets the controller chip
  517. *
  518. * Arguments: struct eth_device *dev: NIC data structure
  519. *
  520. * Returns: void.
  521. */
  522. static void
  523. natsemi_reset(struct eth_device *dev)
  524. {
  525. OUTL(dev, ChipReset, ChipCmd);
  526. /* On page 78 of the spec, they recommend some settings for "optimum
  527. performance" to be done in sequence. These settings optimize some
  528. of the 100Mbit autodetection circuitry. Also, we only want to do
  529. this for rev C of the chip. */
  530. if (INL(dev, SiliconRev) == 0x302) {
  531. OUTW(dev, 0x0001, PGSEL);
  532. OUTW(dev, 0x189C, PMDCSR);
  533. OUTW(dev, 0x0000, TSTDAT);
  534. OUTW(dev, 0x5040, DSPCFG);
  535. OUTW(dev, 0x008C, SDCFG);
  536. }
  537. /* Disable interrupts using the mask. */
  538. OUTL(dev, 0, IntrMask);
  539. OUTL(dev, 0, IntrEnable);
  540. }
  541. /* Function: natsemi_init_rxfilter
  542. *
  543. * Description: sets receive filter address to our MAC address
  544. *
  545. * Arguments: struct eth_device *dev: NIC data structure
  546. *
  547. * returns: void.
  548. */
  549. static void
  550. natsemi_init_rxfilter(struct eth_device *dev)
  551. {
  552. int i;
  553. for (i = 0; i < ETH_ALEN; i += 2) {
  554. OUTL(dev, i, RxFilterAddr);
  555. OUTW(dev, dev->enetaddr[i] + (dev->enetaddr[i + 1] << 8),
  556. RxFilterData);
  557. }
  558. }
  559. /*
  560. * Function: natsemi_init_txd
  561. *
  562. * Description: initializes the Tx descriptor
  563. *
  564. * Arguments: struct eth_device *dev: NIC data structure
  565. *
  566. * returns: void.
  567. */
  568. static void
  569. natsemi_init_txd(struct eth_device *dev)
  570. {
  571. txd.link = (u32) 0;
  572. txd.cmdsts = (u32) 0;
  573. txd.bufptr = (u32) & txb[0];
  574. /* load Transmit Descriptor Register */
  575. OUTL(dev, (u32) & txd, TxRingPtr);
  576. #ifdef NATSEMI_DEBUG
  577. printf("natsemi_init_txd: TX descriptor reg loaded with: %#08X\n",
  578. INL(dev, TxRingPtr));
  579. #endif
  580. }
  581. /* Function: natsemi_init_rxd
  582. *
  583. * Description: initializes the Rx descriptor ring
  584. *
  585. * Arguments: struct eth_device *dev: NIC data structure
  586. *
  587. * Returns: void.
  588. */
  589. static void
  590. natsemi_init_rxd(struct eth_device *dev)
  591. {
  592. int i;
  593. cur_rx = 0;
  594. /* init RX descriptor */
  595. for (i = 0; i < NUM_RX_DESC; i++) {
  596. rxd[i].link =
  597. cpu_to_le32((i + 1 <
  598. NUM_RX_DESC) ? (u32) & rxd[i +
  599. 1] : (u32) &
  600. rxd[0]);
  601. rxd[i].cmdsts = cpu_to_le32((u32) RX_BUF_SIZE);
  602. rxd[i].bufptr = cpu_to_le32((u32) & rxb[i * RX_BUF_SIZE]);
  603. #ifdef NATSEMI_DEBUG
  604. printf
  605. ("natsemi_init_rxd: rxd[%d]=%p link=%X cmdsts=%lX bufptr=%X\n",
  606. i, &rxd[i], le32_to_cpu(rxd[i].link),
  607. rxd[i].cmdsts, rxd[i].bufptr);
  608. #endif
  609. }
  610. /* load Receive Descriptor Register */
  611. OUTL(dev, (u32) & rxd[0], RxRingPtr);
  612. #ifdef NATSEMI_DEBUG
  613. printf("natsemi_init_rxd: RX descriptor register loaded with: %X\n",
  614. INL(dev, RxRingPtr));
  615. #endif
  616. }
  617. /* Function: natsemi_set_rx_mode
  618. *
  619. * Description:
  620. * sets the receive mode to accept all broadcast packets and packets
  621. * with our MAC address, and reject all multicast packets.
  622. *
  623. * Arguments: struct eth_device *dev: NIC data structure
  624. *
  625. * Returns: void.
  626. */
  627. static void
  628. natsemi_set_rx_mode(struct eth_device *dev)
  629. {
  630. u32 rx_mode = AcceptBroadcast | AcceptMyPhys;
  631. OUTL(dev, rx_mode, RxFilterAddr);
  632. }
  633. static void
  634. natsemi_check_duplex(struct eth_device *dev)
  635. {
  636. int duplex = INL(dev, ChipConfig) & FullDuplex ? 1 : 0;
  637. #ifdef NATSEMI_DEBUG
  638. printf("%s: Setting %s-duplex based on negotiated link"
  639. " capability.\n", dev->name, duplex ? "full" : "half");
  640. #endif
  641. if (duplex) {
  642. rx_config |= RxAcceptTx;
  643. tx_config |= (TxCarrierIgn | TxHeartIgn);
  644. } else {
  645. rx_config &= ~RxAcceptTx;
  646. tx_config &= ~(TxCarrierIgn | TxHeartIgn);
  647. }
  648. OUTL(dev, tx_config, TxConfig);
  649. OUTL(dev, rx_config, RxConfig);
  650. }
  651. /* Function: natsemi_send
  652. *
  653. * Description: transmits a packet and waits for completion or timeout.
  654. *
  655. * Returns: void. */
  656. static int
  657. natsemi_send(struct eth_device *dev, volatile void *packet, int length)
  658. {
  659. u32 i, status = 0;
  660. u32 tx_status = 0;
  661. u32 *tx_ptr = &tx_status;
  662. vu_long *res = (vu_long *)tx_ptr;
  663. /* Stop the transmitter */
  664. OUTL(dev, TxOff, ChipCmd);
  665. #ifdef NATSEMI_DEBUG
  666. if (natsemi_debug)
  667. printf("natsemi_send: sending %d bytes\n", (int) length);
  668. #endif
  669. /* set the transmit buffer descriptor and enable Transmit State Machine */
  670. txd.link = cpu_to_le32(0);
  671. txd.bufptr = cpu_to_le32(phys_to_bus((u32) packet));
  672. txd.cmdsts = cpu_to_le32(DescOwn | length);
  673. /* load Transmit Descriptor Register */
  674. OUTL(dev, phys_to_bus((u32) & txd), TxRingPtr);
  675. #ifdef NATSEMI_DEBUG
  676. if (natsemi_debug)
  677. printf("natsemi_send: TX descriptor register loaded with: %#08X\n",
  678. INL(dev, TxRingPtr));
  679. #endif
  680. /* restart the transmitter */
  681. OUTL(dev, TxOn, ChipCmd);
  682. for (i = 0;
  683. (*res = le32_to_cpu(txd.cmdsts)) & DescOwn;
  684. i++) {
  685. if (i >= TOUT_LOOP) {
  686. printf
  687. ("%s: tx error buffer not ready: txd.cmdsts == %#X\n",
  688. dev->name, tx_status);
  689. goto Done;
  690. }
  691. }
  692. if (!(tx_status & DescPktOK)) {
  693. printf("natsemi_send: Transmit error, Tx status %X.\n",
  694. tx_status);
  695. goto Done;
  696. }
  697. status = 1;
  698. Done:
  699. return status;
  700. }
  701. /* Function: natsemi_poll
  702. *
  703. * Description: checks for a received packet and returns it if found.
  704. *
  705. * Arguments: struct eth_device *dev: NIC data structure
  706. *
  707. * Returns: 1 if packet was received.
  708. * 0 if no packet was received.
  709. *
  710. * Side effects:
  711. * Returns (copies) the packet to the array dev->packet.
  712. * Returns the length of the packet.
  713. */
  714. static int
  715. natsemi_poll(struct eth_device *dev)
  716. {
  717. int retstat = 0;
  718. int length = 0;
  719. u32 rx_status = le32_to_cpu(rxd[cur_rx].cmdsts);
  720. if (!(rx_status & (u32) DescOwn))
  721. return retstat;
  722. #ifdef NATSEMI_DEBUG
  723. if (natsemi_debug)
  724. printf("natsemi_poll: got a packet: cur_rx:%d, status:%X\n",
  725. cur_rx, rx_status);
  726. #endif
  727. length = (rx_status & DSIZE) - CRC_SIZE;
  728. if ((rx_status & (DescMore | DescPktOK | DescRxLong)) != DescPktOK) {
  729. printf
  730. ("natsemi_poll: Corrupted packet received, buffer status = %X\n",
  731. rx_status);
  732. retstat = 0;
  733. } else { /* give packet to higher level routine */
  734. NetReceive((rxb + cur_rx * RX_BUF_SIZE), length);
  735. retstat = 1;
  736. }
  737. /* return the descriptor and buffer to receive ring */
  738. rxd[cur_rx].cmdsts = cpu_to_le32(RX_BUF_SIZE);
  739. rxd[cur_rx].bufptr = cpu_to_le32((u32) & rxb[cur_rx * RX_BUF_SIZE]);
  740. if (++cur_rx == NUM_RX_DESC)
  741. cur_rx = 0;
  742. /* re-enable the potentially idle receive state machine */
  743. OUTL(dev, RxOn, ChipCmd);
  744. return retstat;
  745. }
  746. /* Function: natsemi_disable
  747. *
  748. * Description: Turns off interrupts and stops Tx and Rx engines
  749. *
  750. * Arguments: struct eth_device *dev: NIC data structure
  751. *
  752. * Returns: void.
  753. */
  754. static void
  755. natsemi_disable(struct eth_device *dev)
  756. {
  757. /* Disable interrupts using the mask. */
  758. OUTL(dev, 0, IntrMask);
  759. OUTL(dev, 0, IntrEnable);
  760. /* Stop the chip's Tx and Rx processes. */
  761. OUTL(dev, RxOff | TxOff, ChipCmd);
  762. /* Restore PME enable bit */
  763. OUTL(dev, SavedClkRun, ClkRun);
  764. }