mpc8266ads.c 22 KB

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  1. /*
  2. * (C) Copyright 2001
  3. * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
  4. *
  5. * Modified during 2001 by
  6. * Advanced Communications Technologies (Australia) Pty. Ltd.
  7. * Howard Walker, Tuong Vu-Dinh
  8. *
  9. * (C) Copyright 2001, Stuart Hughes, Lineo Inc, stuarth@lineo.com
  10. * Added support for the 16M dram simm on the 8260ads boards
  11. *
  12. * See file CREDITS for list of people who contributed to this
  13. * project.
  14. *
  15. * This program is free software; you can redistribute it and/or
  16. * modify it under the terms of the GNU General Public License as
  17. * published by the Free Software Foundation; either version 2 of
  18. * the License, or (at your option) any later version.
  19. *
  20. * This program is distributed in the hope that it will be useful,
  21. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  22. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  23. * GNU General Public License for more details.
  24. *
  25. * You should have received a copy of the GNU General Public License
  26. * along with this program; if not, write to the Free Software
  27. * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  28. * MA 02111-1307 USA
  29. */
  30. #include <common.h>
  31. #include <ioports.h>
  32. #include <i2c.h>
  33. #include <mpc8260.h>
  34. #include <pci.h>
  35. /*
  36. * PBI Page Based Interleaving
  37. * PSDMR_PBI page based interleaving
  38. * 0 bank based interleaving
  39. * External Address Multiplexing (EAMUX) adds a clock to address cycles
  40. * (this can help with marginal board layouts)
  41. * PSDMR_EAMUX adds a clock
  42. * 0 no extra clock
  43. * Buffer Command (BUFCMD) adds a clock to command cycles.
  44. * PSDMR_BUFCMD adds a clock
  45. * 0 no extra clock
  46. */
  47. #define CONFIG_PBI 0
  48. #define PESSIMISTIC_SDRAM 0
  49. #define EAMUX 0 /* EST requires EAMUX */
  50. #define BUFCMD 0
  51. /*
  52. * I/O Port configuration table
  53. *
  54. * if conf is 1, then that port pin will be configured at boot time
  55. * according to the five values podr/pdir/ppar/psor/pdat for that entry
  56. */
  57. const iop_conf_t iop_conf_tab[4][32] = {
  58. /* Port A configuration */
  59. { /* conf ppar psor pdir podr pdat */
  60. /* PA31 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 TxENB */
  61. /* PA30 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 TxClav */
  62. /* PA29 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 TxSOC */
  63. /* PA28 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 RxENB */
  64. /* PA27 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 RxSOC */
  65. /* PA26 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 RxClav */
  66. /* PA25 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[0] */
  67. /* PA24 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[1] */
  68. /* PA23 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[2] */
  69. /* PA22 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[3] */
  70. /* PA21 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[4] */
  71. /* PA20 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[5] */
  72. /* PA19 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[6] */
  73. /* PA18 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[7] */
  74. /* PA17 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[7] */
  75. /* PA16 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[6] */
  76. /* PA15 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[5] */
  77. /* PA14 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[4] */
  78. /* PA13 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[3] */
  79. /* PA12 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[2] */
  80. /* PA11 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[1] */
  81. /* PA10 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[0] */
  82. /* PA9 */ { 0, 1, 1, 1, 0, 0 }, /* FCC1 L1TXD */
  83. /* PA8 */ { 0, 1, 1, 0, 0, 0 }, /* FCC1 L1RXD */
  84. /* PA7 */ { 0, 0, 0, 1, 0, 0 }, /* PA7 */
  85. /* PA6 */ { 1, 1, 1, 1, 0, 0 }, /* TDM A1 L1RSYNC */
  86. /* PA5 */ { 0, 0, 0, 1, 0, 0 }, /* PA5 */
  87. /* PA4 */ { 0, 0, 0, 1, 0, 0 }, /* PA4 */
  88. /* PA3 */ { 0, 0, 0, 1, 0, 0 }, /* PA3 */
  89. /* PA2 */ { 0, 0, 0, 1, 0, 0 }, /* PA2 */
  90. /* PA1 */ { 1, 0, 0, 0, 0, 0 }, /* FREERUN */
  91. /* PA0 */ { 0, 0, 0, 1, 0, 0 } /* PA0 */
  92. },
  93. /* Port B configuration */
  94. { /* conf ppar psor pdir podr pdat */
  95. /* PB31 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TX_ER */
  96. /* PB30 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RX_DV */
  97. /* PB29 */ { 1, 1, 1, 1, 0, 0 }, /* FCC2 MII TX_EN */
  98. /* PB28 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RX_ER */
  99. /* PB27 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII COL */
  100. /* PB26 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII CRS */
  101. /* PB25 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[3] */
  102. /* PB24 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[2] */
  103. /* PB23 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[1] */
  104. /* PB22 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[0] */
  105. /* PB21 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[0] */
  106. /* PB20 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[1] */
  107. /* PB19 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[2] */
  108. /* PB18 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[3] */
  109. /* PB17 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:RX_DIV */
  110. /* PB16 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:RX_ERR */
  111. /* PB15 */ { 0, 1, 0, 1, 0, 0 }, /* FCC3:TX_ERR */
  112. /* PB14 */ { 0, 1, 0, 1, 0, 0 }, /* FCC3:TX_EN */
  113. /* PB13 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:COL */
  114. /* PB12 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:CRS */
  115. /* PB11 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:RXD */
  116. /* PB10 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:RXD */
  117. /* PB9 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:RXD */
  118. /* PB8 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:RXD */
  119. /* PB7 */ { 0, 1, 0, 1, 0, 0 }, /* FCC3:TXD */
  120. /* PB6 */ { 0, 1, 0, 1, 0, 0 }, /* FCC3:TXD */
  121. /* PB5 */ { 0, 1, 0, 1, 0, 0 }, /* FCC3:TXD */
  122. /* PB4 */ { 0, 1, 0, 1, 0, 0 }, /* FCC3:TXD */
  123. /* PB3 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */
  124. /* PB2 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */
  125. /* PB1 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */
  126. /* PB0 */ { 0, 0, 0, 0, 0, 0 } /* pin doesn't exist */
  127. },
  128. /* Port C */
  129. { /* conf ppar psor pdir podr pdat */
  130. /* PC31 */ { 0, 0, 0, 1, 0, 0 }, /* PC31 */
  131. /* PC30 */ { 0, 0, 0, 1, 0, 0 }, /* PC30 */
  132. /* PC29 */ { 0, 1, 1, 0, 0, 0 }, /* SCC1 EN *CLSN */
  133. /* PC28 */ { 0, 0, 0, 1, 0, 0 }, /* PC28 */
  134. /* PC27 */ { 0, 0, 0, 1, 0, 0 }, /* UART Clock in */
  135. /* PC26 */ { 0, 0, 0, 1, 0, 0 }, /* PC26 */
  136. /* PC25 */ { 0, 0, 0, 1, 0, 0 }, /* PC25 */
  137. /* PC24 */ { 0, 0, 0, 1, 0, 0 }, /* PC24 */
  138. /* PC23 */ { 0, 1, 0, 1, 0, 0 }, /* ATMTFCLK */
  139. /* PC22 */ { 0, 1, 0, 0, 0, 0 }, /* ATMRFCLK */
  140. /* PC21 */ { 0, 1, 0, 0, 0, 0 }, /* SCC1 EN RXCLK */
  141. /* PC20 */ { 0, 1, 0, 0, 0, 0 }, /* SCC1 EN TXCLK */
  142. /* PC19 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RX_CLK CLK13 */
  143. /* PC18 */ { 1, 1, 0, 0, 0, 0 }, /* FCC Tx Clock (CLK14) */
  144. /* PC17 */ { 0, 0, 0, 1, 0, 0 }, /* PC17 */
  145. /* PC16 */ { 0, 1, 0, 0, 0, 0 }, /* FCC Tx Clock (CLK16) */
  146. /* PC15 */ { 0, 0, 0, 1, 0, 0 }, /* PC15 */
  147. /* PC14 */ { 0, 1, 0, 0, 0, 0 }, /* SCC1 EN *CD */
  148. /* PC13 */ { 0, 0, 0, 1, 0, 0 }, /* PC13 */
  149. /* PC12 */ { 0, 1, 0, 1, 0, 0 }, /* PC12 */
  150. /* PC11 */ { 0, 0, 0, 1, 0, 0 }, /* LXT971 transmit control */
  151. /* PC10 */ { 1, 0, 0, 1, 0, 0 }, /* LXT970 FETHMDC */
  152. /* PC9 */ { 1, 0, 0, 0, 0, 0 }, /* LXT970 FETHMDIO */
  153. /* PC8 */ { 0, 0, 0, 1, 0, 0 }, /* PC8 */
  154. /* PC7 */ { 0, 0, 0, 1, 0, 0 }, /* PC7 */
  155. /* PC6 */ { 0, 0, 0, 1, 0, 0 }, /* PC6 */
  156. /* PC5 */ { 0, 0, 0, 1, 0, 0 }, /* PC5 */
  157. /* PC4 */ { 0, 0, 0, 1, 0, 0 }, /* PC4 */
  158. /* PC3 */ { 0, 0, 0, 1, 0, 0 }, /* PC3 */
  159. /* PC2 */ { 0, 0, 0, 1, 0, 1 }, /* ENET FDE */
  160. /* PC1 */ { 0, 0, 0, 1, 0, 0 }, /* ENET DSQE */
  161. /* PC0 */ { 0, 0, 0, 1, 0, 0 }, /* ENET LBK */
  162. },
  163. /* Port D */
  164. { /* conf ppar psor pdir podr pdat */
  165. /* PD31 */ { 1, 1, 0, 0, 0, 0 }, /* SCC1 EN RxD */
  166. /* PD30 */ { 1, 1, 1, 1, 0, 0 }, /* SCC1 EN TxD */
  167. /* PD29 */ { 0, 1, 0, 1, 0, 0 }, /* SCC1 EN TENA */
  168. /* PD28 */ { 0, 1, 0, 0, 0, 0 }, /* PD28 */
  169. /* PD27 */ { 0, 1, 1, 1, 0, 0 }, /* PD27 */
  170. /* PD26 */ { 0, 0, 0, 1, 0, 0 }, /* PD26 */
  171. /* PD25 */ { 0, 0, 0, 1, 0, 0 }, /* PD25 */
  172. /* PD24 */ { 0, 0, 0, 1, 0, 0 }, /* PD24 */
  173. /* PD23 */ { 0, 0, 0, 1, 0, 0 }, /* PD23 */
  174. /* PD22 */ { 0, 0, 0, 1, 0, 0 }, /* PD22 */
  175. /* PD21 */ { 0, 0, 0, 1, 0, 0 }, /* PD21 */
  176. /* PD20 */ { 0, 0, 0, 1, 0, 0 }, /* PD20 */
  177. /* PD19 */ { 0, 0, 0, 1, 0, 0 }, /* PD19 */
  178. /* PD18 */ { 0, 0, 0, 1, 0, 0 }, /* PD18 */
  179. /* PD17 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXPRTY */
  180. /* PD16 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXPRTY */
  181. /* PD15 */ { 1, 1, 1, 0, 1, 0 }, /* I2C SDA */
  182. /* PD14 */ { 1, 1, 1, 0, 1, 0 }, /* I2C SCL */
  183. /* PD13 */ { 0, 0, 0, 0, 0, 0 }, /* PD13 */
  184. /* PD12 */ { 0, 0, 0, 0, 0, 0 }, /* PD12 */
  185. /* PD11 */ { 0, 0, 0, 0, 0, 0 }, /* PD11 */
  186. /* PD10 */ { 0, 0, 0, 0, 0, 0 }, /* PD10 */
  187. /* PD9 */ { 1, 1, 0, 1, 0, 0 }, /* SMC1 TXD */
  188. /* PD8 */ { 1, 1, 0, 0, 0, 0 }, /* SMC1 RXD */
  189. /* PD7 */ { 0, 0, 0, 1, 0, 1 }, /* PD7 */
  190. /* PD6 */ { 0, 0, 0, 1, 0, 1 }, /* PD6 */
  191. /* PD5 */ { 0, 0, 0, 1, 0, 1 }, /* PD5 */
  192. /* PD4 */ { 0, 0, 0, 1, 0, 1 }, /* PD4 */
  193. /* PD3 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */
  194. /* PD2 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */
  195. /* PD1 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */
  196. /* PD0 */ { 0, 0, 0, 0, 0, 0 } /* pin doesn't exist */
  197. }
  198. };
  199. typedef struct bscr_ {
  200. unsigned long bcsr0;
  201. unsigned long bcsr1;
  202. unsigned long bcsr2;
  203. unsigned long bcsr3;
  204. unsigned long bcsr4;
  205. unsigned long bcsr5;
  206. unsigned long bcsr6;
  207. unsigned long bcsr7;
  208. } bcsr_t;
  209. typedef struct pci_ic_s {
  210. unsigned long pci_int_stat;
  211. unsigned long pci_int_mask;
  212. } pci_ic_t;
  213. void reset_phy(void)
  214. {
  215. volatile bcsr_t *bcsr = (bcsr_t *)CONFIG_SYS_BCSR;
  216. /* reset the FEC port */
  217. bcsr->bcsr1 &= ~FETH_RST;
  218. bcsr->bcsr1 |= FETH_RST;
  219. }
  220. int board_early_init_f (void)
  221. {
  222. volatile bcsr_t *bcsr = (bcsr_t *)CONFIG_SYS_BCSR;
  223. volatile pci_ic_t *pci_ic = (pci_ic_t *) CONFIG_SYS_PCI_INT;
  224. bcsr->bcsr1 = ~FETHIEN & ~RS232EN_1 & ~RS232EN_2;
  225. /* mask all PCI interrupts */
  226. pci_ic->pci_int_mask |= 0xfff00000;
  227. return 0;
  228. }
  229. int checkboard(void)
  230. {
  231. puts ("Board: Motorola MPC8266ADS\n");
  232. return 0;
  233. }
  234. phys_size_t initdram(int board_type)
  235. {
  236. /* Autoinit part stolen from board/sacsng/sacsng.c */
  237. volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR;
  238. volatile memctl8260_t *memctl = &immap->im_memctl;
  239. volatile uchar c = 0xff;
  240. volatile uchar *ramaddr = (uchar *)(CONFIG_SYS_SDRAM_BASE + 0x8);
  241. uint psdmr = CONFIG_SYS_PSDMR;
  242. int i;
  243. uint psrt = 0x21; /* for no SPD */
  244. uint chipselects = 1; /* for no SPD */
  245. uint sdram_size = CONFIG_SYS_SDRAM_SIZE * 1024 * 1024; /* for no SPD */
  246. uint or = CONFIG_SYS_OR2_PRELIM; /* for no SPD */
  247. uint data_width;
  248. uint rows;
  249. uint banks;
  250. uint cols;
  251. uint caslatency;
  252. uint width;
  253. uint rowst;
  254. uint sdam;
  255. uint bsma;
  256. uint sda10;
  257. u_char spd_size;
  258. u_char data;
  259. u_char cksum;
  260. int j;
  261. /* Keep the compiler from complaining about potentially uninitialized vars */
  262. data_width = rows = banks = cols = caslatency = 0;
  263. /*
  264. * Read the SDRAM SPD EEPROM via I2C.
  265. */
  266. i2c_init (CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
  267. i2c_read(SDRAM_SPD_ADDR, 0, 1, &data, 1);
  268. spd_size = data;
  269. cksum = data;
  270. for(j = 1; j < 64; j++)
  271. { /* read only the checksummed bytes */
  272. /* note: the I2C address autoincrements when alen == 0 */
  273. i2c_read(SDRAM_SPD_ADDR, 0, 0, &data, 1);
  274. /*printf("addr %d = 0x%02x\n", j, data);*/
  275. if(j == 5) chipselects = data & 0x0F;
  276. else if(j == 6) data_width = data;
  277. else if(j == 7) data_width |= data << 8;
  278. else if(j == 3) rows = data & 0x0F;
  279. else if(j == 4) cols = data & 0x0F;
  280. else if(j == 12)
  281. {
  282. /*
  283. * Refresh rate: this assumes the prescaler is set to
  284. * approximately 0.39uSec per tick and the target refresh period
  285. * is about 85% of maximum.
  286. */
  287. switch(data & 0x7F)
  288. {
  289. default:
  290. case 0: psrt = 0x21; /* 15.625uS */ break;
  291. case 1: psrt = 0x07; /* 3.9uS */ break;
  292. case 2: psrt = 0x0F; /* 7.8uS */ break;
  293. case 3: psrt = 0x43; /* 31.3uS */ break;
  294. case 4: psrt = 0x87; /* 62.5uS */ break;
  295. case 5: psrt = 0xFF; /* 125uS */ break;
  296. }
  297. }
  298. else if(j == 17) banks = data;
  299. else if(j == 18)
  300. {
  301. caslatency = 3; /* default CL */
  302. # if(PESSIMISTIC_SDRAM)
  303. if((data & 0x04) != 0) caslatency = 3;
  304. else if((data & 0x02) != 0) caslatency = 2;
  305. else if((data & 0x01) != 0) caslatency = 1;
  306. # else
  307. if((data & 0x01) != 0) caslatency = 1;
  308. else if((data & 0x02) != 0) caslatency = 2;
  309. else if((data & 0x04) != 0) caslatency = 3;
  310. # endif
  311. else
  312. {
  313. printf ("WARNING: Unknown CAS latency 0x%02X, using 3\n",
  314. data);
  315. }
  316. }
  317. else if(j == 63)
  318. {
  319. if(data != cksum)
  320. {
  321. printf ("WARNING: Configuration data checksum failure:"
  322. " is 0x%02x, calculated 0x%02x\n",
  323. data, cksum);
  324. }
  325. }
  326. cksum += data;
  327. }
  328. /* We don't trust CL less than 2 (only saw it on an old 16MByte DIMM) */
  329. if(caslatency < 2) {
  330. printf("CL was %d, forcing to 2\n", caslatency);
  331. caslatency = 2;
  332. }
  333. if(rows > 14) {
  334. printf("This doesn't look good, rows = %d, should be <= 14\n", rows);
  335. rows = 14;
  336. }
  337. if(cols > 11) {
  338. printf("This doesn't look good, columns = %d, should be <= 11\n", cols);
  339. cols = 11;
  340. }
  341. if((data_width != 64) && (data_width != 72))
  342. {
  343. printf("WARNING: SDRAM width unsupported, is %d, expected 64 or 72.\n",
  344. data_width);
  345. }
  346. width = 3; /* 2^3 = 8 bytes = 64 bits wide */
  347. /*
  348. * Convert banks into log2(banks)
  349. */
  350. if (banks == 2) banks = 1;
  351. else if(banks == 4) banks = 2;
  352. else if(banks == 8) banks = 3;
  353. sdram_size = 1 << (rows + cols + banks + width);
  354. /* hack for high density memory (512MB per CS) */
  355. /* !!!!! Will ONLY work with Page Based Interleave !!!!!
  356. ( PSDMR[PBI] = 1 )
  357. */
  358. /* mamory actually has 11 column addresses, but the memory controller
  359. doesn't really care.
  360. the calculations that follow will however move the rows so that
  361. they are muxed one bit off if you use 11 bit columns.
  362. The solution is to tell the memory controller the correct size of the memory
  363. but change the number of columns to 10 afterwards.
  364. The 11th column addre will still be mucxed correctly onto the bus.
  365. Also be aware that the MPC8266ADS board Rev B has not connected
  366. Row address 13 to anything.
  367. The fix is to connect ADD16 (from U37-47) to SADDR12 (U28-126)
  368. */
  369. if (cols > 10)
  370. cols = 10;
  371. #if(CONFIG_PBI == 0) /* bank-based interleaving */
  372. rowst = ((32 - 6) - (rows + cols + width)) * 2;
  373. #else
  374. rowst = 32 - (rows + banks + cols + width);
  375. #endif
  376. or = ~(sdram_size - 1) | /* SDAM address mask */
  377. ((banks-1) << 13) | /* banks per device */
  378. (rowst << 9) | /* rowst */
  379. ((rows - 9) << 6); /* numr */
  380. /*printf("memctl->memc_or2 = 0x%08x\n", or);*/
  381. /*
  382. * SDAM specifies the number of columns that are multiplexed
  383. * (reference AN2165/D), defined to be (columns - 6) for page
  384. * interleave, (columns - 8) for bank interleave.
  385. *
  386. * BSMA is 14 - max(rows, cols). The bank select lines come
  387. * into play above the highest "address" line going into the
  388. * the SDRAM.
  389. */
  390. #if(CONFIG_PBI == 0) /* bank-based interleaving */
  391. sdam = cols - 8;
  392. bsma = ((31 - width) - 14) - ((rows > cols) ? rows : cols);
  393. sda10 = sdam + 2;
  394. #else
  395. sdam = cols + banks - 8;
  396. bsma = ((31 - width) - 14) - ((rows > cols) ? rows : cols);
  397. sda10 = sdam;
  398. #endif
  399. #if(PESSIMISTIC_SDRAM)
  400. psdmr = (CONFIG_PBI |\
  401. PSDMR_RFEN |\
  402. PSDMR_RFRC_16_CLK |\
  403. PSDMR_PRETOACT_8W |\
  404. PSDMR_ACTTORW_8W |\
  405. PSDMR_WRC_4C |\
  406. PSDMR_EAMUX |\
  407. PSDMR_BUFCMD) |\
  408. caslatency |\
  409. ((caslatency - 1) << 6) | /* LDOTOPRE is CL - 1 */ \
  410. (sdam << 24) |\
  411. (bsma << 21) |\
  412. (sda10 << 18);
  413. #else
  414. psdmr = (CONFIG_PBI |\
  415. PSDMR_RFEN |\
  416. PSDMR_RFRC_7_CLK |\
  417. PSDMR_PRETOACT_3W | /* 1 for 7E parts (fast PC-133) */ \
  418. PSDMR_ACTTORW_2W | /* 1 for 7E parts (fast PC-133) */ \
  419. PSDMR_WRC_1C | /* 1 clock + 7nSec */
  420. EAMUX |\
  421. BUFCMD) |\
  422. caslatency |\
  423. ((caslatency - 1) << 6) | /* LDOTOPRE is CL - 1 */ \
  424. (sdam << 24) |\
  425. (bsma << 21) |\
  426. (sda10 << 18);
  427. #endif
  428. /*printf("psdmr = 0x%08x\n", psdmr);*/
  429. /*
  430. * Quote from 8260 UM (10.4.2 SDRAM Power-On Initialization, 10-35):
  431. *
  432. * "At system reset, initialization software must set up the
  433. * programmable parameters in the memory controller banks registers
  434. * (ORx, BRx, P/LSDMR). After all memory parameters are configured,
  435. * system software should execute the following initialization sequence
  436. * for each SDRAM device.
  437. *
  438. * 1. Issue a PRECHARGE-ALL-BANKS command
  439. * 2. Issue eight CBR REFRESH commands
  440. * 3. Issue a MODE-SET command to initialize the mode register
  441. *
  442. * Quote from Micron MT48LC8M16A2 data sheet:
  443. *
  444. * "...the SDRAM requires a 100uS delay prior to issuing any
  445. * command other than a COMMAND INHIBIT or NOP. Starting at some
  446. * point during this 100uS period and continuing at least through
  447. * the end of this period, COMMAND INHIBIT or NOP commands should
  448. * be applied."
  449. *
  450. * "Once the 100uS delay has been satisfied with at least one COMMAND
  451. * INHIBIT or NOP command having been applied, a /PRECHARGE command/
  452. * should be applied. All banks must then be precharged, thereby
  453. * placing the device in the all banks idle state."
  454. *
  455. * "Once in the idle state, /two/ AUTO REFRESH cycles must be
  456. * performed. After the AUTO REFRESH cycles are complete, the
  457. * SDRAM is ready for mode register programming."
  458. *
  459. * (/emphasis/ mine, gvb)
  460. *
  461. * The way I interpret this, Micron start up sequence is:
  462. * 1. Issue a PRECHARGE-BANK command (initial precharge)
  463. * 2. Issue a PRECHARGE-ALL-BANKS command ("all banks ... precharged")
  464. * 3. Issue two (presumably, doing eight is OK) CBR REFRESH commands
  465. * 4. Issue a MODE-SET command to initialize the mode register
  466. *
  467. * --------
  468. *
  469. * The initial commands are executed by setting P/LSDMR[OP] and
  470. * accessing the SDRAM with a single-byte transaction."
  471. *
  472. * The appropriate BRx/ORx registers have already been set when we
  473. * get here. The SDRAM can be accessed at the address CONFIG_SYS_SDRAM_BASE.
  474. */
  475. memctl->memc_mptpr = CONFIG_SYS_MPTPR;
  476. memctl->memc_psrt = psrt;
  477. memctl->memc_br2 = CONFIG_SYS_BR2_PRELIM;
  478. memctl->memc_or2 = or;
  479. memctl->memc_psdmr = psdmr | PSDMR_OP_PREA;
  480. *ramaddr = c;
  481. memctl->memc_psdmr = psdmr | PSDMR_OP_CBRR;
  482. for (i = 0; i < 8; i++)
  483. *ramaddr = c;
  484. memctl->memc_psdmr = psdmr | PSDMR_OP_MRW;
  485. *ramaddr = c;
  486. memctl->memc_psdmr = psdmr | PSDMR_OP_NORM | PSDMR_RFEN;
  487. *ramaddr = c;
  488. /*
  489. * Do it a second time for the second set of chips if the DIMM has
  490. * two chip selects (double sided).
  491. */
  492. if(chipselects > 1)
  493. {
  494. ramaddr += sdram_size;
  495. memctl->memc_br3 = CONFIG_SYS_BR3_PRELIM + sdram_size;
  496. memctl->memc_or3 = or;
  497. memctl->memc_psdmr = psdmr | PSDMR_OP_PREA;
  498. *ramaddr = c;
  499. memctl->memc_psdmr = psdmr | PSDMR_OP_CBRR;
  500. for (i = 0; i < 8; i++)
  501. *ramaddr = c;
  502. memctl->memc_psdmr = psdmr | PSDMR_OP_MRW;
  503. *ramaddr = c;
  504. memctl->memc_psdmr = psdmr | PSDMR_OP_NORM | PSDMR_RFEN;
  505. *ramaddr = c;
  506. }
  507. /* print info */
  508. printf("SDRAM configuration read from SPD\n");
  509. printf("\tSize per side = %dMB\n", sdram_size >> 20);
  510. printf("\tOrganization: %d sides, %d banks, %d Columns, %d Rows, Data width = %d bits\n", chipselects, 1<<(banks), cols, rows, data_width);
  511. printf("\tRefresh rate = %d, CAS latency = %d", psrt, caslatency);
  512. #if(CONFIG_PBI == 0) /* bank-based interleaving */
  513. printf(", Using Bank Based Interleave\n");
  514. #else
  515. printf(", Using Page Based Interleave\n");
  516. #endif
  517. printf("\tTotal size: ");
  518. /* this delay only needed for original 16MB DIMM...
  519. * Not needed for any other memory configuration */
  520. if ((sdram_size * chipselects) == (16 *1024 *1024))
  521. udelay (250000);
  522. return (sdram_size * chipselects);
  523. /*return (16 * 1024 * 1024);*/
  524. }
  525. #ifdef CONFIG_PCI
  526. struct pci_controller hose;
  527. extern void pci_mpc8250_init(struct pci_controller *);
  528. void pci_init_board(void)
  529. {
  530. pci_mpc8250_init(&hose);
  531. }
  532. #endif