gt64260R.h 45 KB

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  1. /* gt64260R.h - GT64260 Internal registers definition file */
  2. /* Copyright - Galileo technology. */
  3. #ifndef __INCgt64260rh
  4. #define __INCgt64260rh
  5. #ifndef GT64260
  6. #define GT64260
  7. #endif
  8. /* CPU MASTER CONTROL REGISTER */
  9. #define CPU_CONFIGURATION 0x0
  10. #define CPU_MASTER_CONTROL 0x160
  11. /****************************************/
  12. /* Processor Address Space */
  13. /****************************************/
  14. /* Sdram's BAR'S */
  15. #define SCS_0_LOW_DECODE_ADDRESS 0x008
  16. #define SCS_0_HIGH_DECODE_ADDRESS 0x010
  17. #define SCS_1_LOW_DECODE_ADDRESS 0x208
  18. #define SCS_1_HIGH_DECODE_ADDRESS 0x210
  19. #define SCS_2_LOW_DECODE_ADDRESS 0x018
  20. #define SCS_2_HIGH_DECODE_ADDRESS 0x020
  21. #define SCS_3_LOW_DECODE_ADDRESS 0x218
  22. #define SCS_3_HIGH_DECODE_ADDRESS 0x220
  23. /* Devices BAR'S */
  24. #define CS_0_LOW_DECODE_ADDRESS 0x028
  25. #define CS_0_HIGH_DECODE_ADDRESS 0x030
  26. #define CS_1_LOW_DECODE_ADDRESS 0x228
  27. #define CS_1_HIGH_DECODE_ADDRESS 0x230
  28. #define CS_2_LOW_DECODE_ADDRESS 0x248
  29. #define CS_2_HIGH_DECODE_ADDRESS 0x250
  30. #define CS_3_LOW_DECODE_ADDRESS 0x038
  31. #define CS_3_HIGH_DECODE_ADDRESS 0x040
  32. #define BOOTCS_LOW_DECODE_ADDRESS 0x238
  33. #define BOOTCS_HIGH_DECODE_ADDRESS 0x240
  34. #define PCI_0I_O_LOW_DECODE_ADDRESS 0x048
  35. #define PCI_0I_O_HIGH_DECODE_ADDRESS 0x050
  36. #define PCI_0MEMORY0_LOW_DECODE_ADDRESS 0x058
  37. #define PCI_0MEMORY0_HIGH_DECODE_ADDRESS 0x060
  38. #define PCI_0MEMORY1_LOW_DECODE_ADDRESS 0x080
  39. #define PCI_0MEMORY1_HIGH_DECODE_ADDRESS 0x088
  40. #define PCI_0MEMORY2_LOW_DECODE_ADDRESS 0x258
  41. #define PCI_0MEMORY2_HIGH_DECODE_ADDRESS 0x260
  42. #define PCI_0MEMORY3_LOW_DECODE_ADDRESS 0x280
  43. #define PCI_0MEMORY3_HIGH_DECODE_ADDRESS 0x288
  44. #define PCI_1I_O_LOW_DECODE_ADDRESS 0x090
  45. #define PCI_1I_O_HIGH_DECODE_ADDRESS 0x098
  46. #define PCI_1MEMORY0_LOW_DECODE_ADDRESS 0x0a0
  47. #define PCI_1MEMORY0_HIGH_DECODE_ADDRESS 0x0a8
  48. #define PCI_1MEMORY1_LOW_DECODE_ADDRESS 0x0b0
  49. #define PCI_1MEMORY1_HIGH_DECODE_ADDRESS 0x0b8
  50. #define PCI_1MEMORY2_LOW_DECODE_ADDRESS 0x2a0
  51. #define PCI_1MEMORY2_HIGH_DECODE_ADDRESS 0x2a8
  52. #define PCI_1MEMORY3_LOW_DECODE_ADDRESS 0x2b0
  53. #define PCI_1MEMORY3_HIGH_DECODE_ADDRESS 0x2b8
  54. #define INTERNAL_SPACE_DECODE 0x068
  55. #define CPU_0_LOW_DECODE_ADDRESS 0x290
  56. #define CPU_0_HIGH_DECODE_ADDRESS 0x298
  57. #define CPU_1_LOW_DECODE_ADDRESS 0x2c0
  58. #define CPU_1_HIGH_DECODE_ADDRESS 0x2c8
  59. #define PCI_0I_O_ADDRESS_REMAP 0x0f0
  60. #define PCI_0MEMORY0_ADDRESS_REMAP 0x0f8
  61. #define PCI_0MEMORY0_HIGH_ADDRESS_REMAP 0x320
  62. #define PCI_0MEMORY1_ADDRESS_REMAP 0x100
  63. #define PCI_0MEMORY1_HIGH_ADDRESS_REMAP 0x328
  64. #define PCI_0MEMORY2_ADDRESS_REMAP 0x2f8
  65. #define PCI_0MEMORY2_HIGH_ADDRESS_REMAP 0x330
  66. #define PCI_0MEMORY3_ADDRESS_REMAP 0x300
  67. #define PCI_0MEMORY3_HIGH_ADDRESS_REMAP 0x338
  68. #define PCI_1I_O_ADDRESS_REMAP 0x108
  69. #define PCI_1MEMORY0_ADDRESS_REMAP 0x110
  70. #define PCI_1MEMORY0_HIGH_ADDRESS_REMAP 0x340
  71. #define PCI_1MEMORY1_ADDRESS_REMAP 0x118
  72. #define PCI_1MEMORY1_HIGH_ADDRESS_REMAP 0x348
  73. #define PCI_1MEMORY2_ADDRESS_REMAP 0x310
  74. #define PCI_1MEMORY2_HIGH_ADDRESS_REMAP 0x350
  75. #define PCI_1MEMORY3_ADDRESS_REMAP 0x318
  76. #define PCI_1MEMORY3_HIGH_ADDRESS_REMAP 0x358
  77. /****************************************/
  78. /* CPU Sync Barrier */
  79. /****************************************/
  80. #define PCI_0SYNC_BARIER_VIRTUAL_REGISTER 0x0c0
  81. #define PCI_1SYNC_BARIER_VIRTUAL_REGISTER 0x0c8
  82. /****************************************/
  83. /* CPU Access Protect */
  84. /****************************************/
  85. #define CPU_LOW_PROTECT_ADDRESS_0 0x180
  86. #define CPU_HIGH_PROTECT_ADDRESS_0 0x188
  87. #define CPU_LOW_PROTECT_ADDRESS_1 0x190
  88. #define CPU_HIGH_PROTECT_ADDRESS_1 0x198
  89. #define CPU_LOW_PROTECT_ADDRESS_2 0x1a0
  90. #define CPU_HIGH_PROTECT_ADDRESS_2 0x1a8
  91. #define CPU_LOW_PROTECT_ADDRESS_3 0x1b0
  92. #define CPU_HIGH_PROTECT_ADDRESS_3 0x1b8
  93. #define CPU_LOW_PROTECT_ADDRESS_4 0x1c0
  94. #define CPU_HIGH_PROTECT_ADDRESS_4 0x1c8
  95. #define CPU_LOW_PROTECT_ADDRESS_5 0x1d0
  96. #define CPU_HIGH_PROTECT_ADDRESS_5 0x1d8
  97. #define CPU_LOW_PROTECT_ADDRESS_6 0x1e0
  98. #define CPU_HIGH_PROTECT_ADDRESS_6 0x1e8
  99. #define CPU_LOW_PROTECT_ADDRESS_7 0x1f0
  100. #define CPU_HIGH_PROTECT_ADDRESS_7 0x1f8
  101. /****************************************/
  102. /* Snoop Control */
  103. /****************************************/
  104. #define SNOOP_BASE_ADDRESS_0 0x380
  105. #define SNOOP_TOP_ADDRESS_0 0x388
  106. #define SNOOP_BASE_ADDRESS_1 0x390
  107. #define SNOOP_TOP_ADDRESS_1 0x398
  108. #define SNOOP_BASE_ADDRESS_2 0x3a0
  109. #define SNOOP_TOP_ADDRESS_2 0x3a8
  110. #define SNOOP_BASE_ADDRESS_3 0x3b0
  111. #define SNOOP_TOP_ADDRESS_3 0x3b8
  112. /****************************************/
  113. /* CPU Error Report */
  114. /****************************************/
  115. #define CPU_ERROR_ADDRESS_LOW 0x070
  116. #define CPU_ERROR_ADDRESS_HIGH 0x078
  117. #define CPU_ERROR_DATA_LOW 0x128
  118. #define CPU_ERROR_DATA_HIGH 0x130
  119. #define CPU_ERROR_PARITY 0x138
  120. #define CPU_ERROR_CAUSE 0x140
  121. #define CPU_ERROR_MASK 0x148
  122. /****************************************/
  123. /* Pslave Debug */
  124. /****************************************/
  125. #define X_0_ADDRESS 0x360
  126. #define X_0_COMMAND_ID 0x368
  127. #define X_1_ADDRESS 0x370
  128. #define X_1_COMMAND_ID 0x378
  129. #define WRITE_DATA_LOW 0x3c0
  130. #define WRITE_DATA_HIGH 0x3c8
  131. #define WRITE_BYTE_ENABLE 0x3e0
  132. #define READ_DATA_LOW 0x3d0
  133. #define READ_DATA_HIGH 0x3d8
  134. #define READ_ID 0x3e8
  135. /****************************************/
  136. /* SDRAM and Device Address Space */
  137. /****************************************/
  138. /****************************************/
  139. /* SDRAM Configuration */
  140. /****************************************/
  141. #define SDRAM_CONFIGURATION 0x448
  142. #define SDRAM_OPERATION_MODE 0x474
  143. #define SDRAM_ADDRESS_DECODE 0x47c
  144. #define SDRAM_UMA_CONTROL 0x4a4
  145. #define SDRAM_CROSS_BAR_CONTROL_LOW 0x4a8
  146. #define SDRAM_CROSS_BAR_CONTROL_HIGH 0x4ac
  147. #define SDRAM_CROSS_BAR_TIMEOUT 0x4b0
  148. #define SDRAM_TIMING 0x4b4
  149. /****************************************/
  150. /* SDRAM Parameters */
  151. /****************************************/
  152. #define SDRAM_BANK0PARAMETERS 0x44C
  153. #define SDRAM_BANK1PARAMETERS 0x450
  154. #define SDRAM_BANK2PARAMETERS 0x454
  155. #define SDRAM_BANK3PARAMETERS 0x458
  156. /****************************************/
  157. /* SDRAM Error Report */
  158. /****************************************/
  159. #define SDRAM_ERROR_DATA_LOW 0x484
  160. #define SDRAM_ERROR_DATA_HIGH 0x480
  161. #define SDRAM_AND_DEVICE_ERROR_ADDRESS 0x490
  162. #define SDRAM_RECEIVED_ECC 0x488
  163. #define SDRAM_CALCULATED_ECC 0x48c
  164. #define SDRAM_ECC_CONTROL 0x494
  165. #define SDRAM_ECC_ERROR_COUNTER 0x498
  166. /****************************************/
  167. /* SDunit Debug (for internal use) */
  168. /****************************************/
  169. #define X0_ADDRESS 0x500
  170. #define X0_COMMAND_AND_ID 0x504
  171. #define X0_WRITE_DATA_LOW 0x508
  172. #define X0_WRITE_DATA_HIGH 0x50c
  173. #define X0_WRITE_BYTE_ENABLE 0x518
  174. #define X0_READ_DATA_LOW 0x510
  175. #define X0_READ_DATA_HIGH 0x514
  176. #define X0_READ_ID 0x51c
  177. #define X1_ADDRESS 0x520
  178. #define X1_COMMAND_AND_ID 0x524
  179. #define X1_WRITE_DATA_LOW 0x528
  180. #define X1_WRITE_DATA_HIGH 0x52c
  181. #define X1_WRITE_BYTE_ENABLE 0x538
  182. #define X1_READ_DATA_LOW 0x530
  183. #define X1_READ_DATA_HIGH 0x534
  184. #define X1_READ_ID 0x53c
  185. #define X0_SNOOP_ADDRESS 0x540
  186. #define X0_SNOOP_COMMAND 0x544
  187. #define X1_SNOOP_ADDRESS 0x548
  188. #define X1_SNOOP_COMMAND 0x54c
  189. /****************************************/
  190. /* Device Parameters */
  191. /****************************************/
  192. #define DEVICE_BANK0PARAMETERS 0x45c
  193. #define DEVICE_BANK1PARAMETERS 0x460
  194. #define DEVICE_BANK2PARAMETERS 0x464
  195. #define DEVICE_BANK3PARAMETERS 0x468
  196. #define DEVICE_BOOT_BANK_PARAMETERS 0x46c
  197. #define DEVICE_CONTROL 0x4c0
  198. #define DEVICE_CROSS_BAR_CONTROL_LOW 0x4c8
  199. #define DEVICE_CROSS_BAR_CONTROL_HIGH 0x4cc
  200. #define DEVICE_CROSS_BAR_TIMEOUT 0x4c4
  201. /****************************************/
  202. /* Device Interrupt */
  203. /****************************************/
  204. #define DEVICE_INTERRUPT_CAUSE 0x4d0
  205. #define DEVICE_INTERRUPT_MASK 0x4d4
  206. #define DEVICE_ERROR_ADDRESS 0x4d8
  207. /****************************************/
  208. /* DMA Record */
  209. /****************************************/
  210. #define CHANNEL0_DMA_BYTE_COUNT 0x800
  211. #define CHANNEL1_DMA_BYTE_COUNT 0x804
  212. #define CHANNEL2_DMA_BYTE_COUNT 0x808
  213. #define CHANNEL3_DMA_BYTE_COUNT 0x80C
  214. #define CHANNEL4_DMA_BYTE_COUNT 0x900
  215. #define CHANNEL5_DMA_BYTE_COUNT 0x904
  216. #define CHANNEL6_DMA_BYTE_COUNT 0x908
  217. #define CHANNEL7_DMA_BYTE_COUNT 0x90C
  218. #define CHANNEL0_DMA_SOURCE_ADDRESS 0x810
  219. #define CHANNEL1_DMA_SOURCE_ADDRESS 0x814
  220. #define CHANNEL2_DMA_SOURCE_ADDRESS 0x818
  221. #define CHANNEL3_DMA_SOURCE_ADDRESS 0x81C
  222. #define CHANNEL4_DMA_SOURCE_ADDRESS 0x910
  223. #define CHANNEL5_DMA_SOURCE_ADDRESS 0x914
  224. #define CHANNEL6_DMA_SOURCE_ADDRESS 0x918
  225. #define CHANNEL7_DMA_SOURCE_ADDRESS 0x91C
  226. #define CHANNEL0_DMA_DESTINATION_ADDRESS 0x820
  227. #define CHANNEL1_DMA_DESTINATION_ADDRESS 0x824
  228. #define CHANNEL2_DMA_DESTINATION_ADDRESS 0x828
  229. #define CHANNEL3_DMA_DESTINATION_ADDRESS 0x82C
  230. #define CHANNEL4_DMA_DESTINATION_ADDRESS 0x920
  231. #define CHANNEL5_DMA_DESTINATION_ADDRESS 0x924
  232. #define CHANNEL6_DMA_DESTINATION_ADDRESS 0x928
  233. #define CHANNEL7_DMA_DESTINATION_ADDRESS 0x92C
  234. #define CHANNEL0NEXT_RECORD_POINTER 0x830
  235. #define CHANNEL1NEXT_RECORD_POINTER 0x834
  236. #define CHANNEL2NEXT_RECORD_POINTER 0x838
  237. #define CHANNEL3NEXT_RECORD_POINTER 0x83C
  238. #define CHANNEL4NEXT_RECORD_POINTER 0x930
  239. #define CHANNEL5NEXT_RECORD_POINTER 0x934
  240. #define CHANNEL6NEXT_RECORD_POINTER 0x938
  241. #define CHANNEL7NEXT_RECORD_POINTER 0x93C
  242. #define CHANNEL0CURRENT_DESCRIPTOR_POINTER 0x870
  243. #define CHANNEL1CURRENT_DESCRIPTOR_POINTER 0x874
  244. #define CHANNEL2CURRENT_DESCRIPTOR_POINTER 0x878
  245. #define CHANNEL3CURRENT_DESCRIPTOR_POINTER 0x87C
  246. #define CHANNEL4CURRENT_DESCRIPTOR_POINTER 0x970
  247. #define CHANNEL5CURRENT_DESCRIPTOR_POINTER 0x974
  248. #define CHANNEL6CURRENT_DESCRIPTOR_POINTER 0x978
  249. #define CHANNEL7CURRENT_DESCRIPTOR_POINTER 0x97C
  250. #define CHANNEL0_DMA_SOURCE_HIGH_PCI_ADDRESS 0x890
  251. #define CHANNEL1_DMA_SOURCE_HIGH_PCI_ADDRESS 0x894
  252. #define CHANNEL2_DMA_SOURCE_HIGH_PCI_ADDRESS 0x898
  253. #define CHANNEL3_DMA_SOURCE_HIGH_PCI_ADDRESS 0x89c
  254. #define CHANNEL4_DMA_SOURCE_HIGH_PCI_ADDRESS 0x990
  255. #define CHANNEL5_DMA_SOURCE_HIGH_PCI_ADDRESS 0x994
  256. #define CHANNEL6_DMA_SOURCE_HIGH_PCI_ADDRESS 0x998
  257. #define CHANNEL7_DMA_SOURCE_HIGH_PCI_ADDRESS 0x99c
  258. #define CHANNEL0_DMA_DESTINATION_HIGH_PCI_ADDRESS 0x8a0
  259. #define CHANNEL1_DMA_DESTINATION_HIGH_PCI_ADDRESS 0x8a4
  260. #define CHANNEL2_DMA_DESTINATION_HIGH_PCI_ADDRESS 0x8a8
  261. #define CHANNEL3_DMA_DESTINATION_HIGH_PCI_ADDRESS 0x8ac
  262. #define CHANNEL4_DMA_DESTINATION_HIGH_PCI_ADDRESS 0x9a0
  263. #define CHANNEL5_DMA_DESTINATION_HIGH_PCI_ADDRESS 0x9a4
  264. #define CHANNEL6_DMA_DESTINATION_HIGH_PCI_ADDRESS 0x9a8
  265. #define CHANNEL7_DMA_DESTINATION_HIGH_PCI_ADDRESS 0x9ac
  266. #define CHANNEL0_DMA_NEXT_RECORD_POINTER_HIGH_PCI_ADDRESS 0x8b0
  267. #define CHANNEL1_DMA_NEXT_RECORD_POINTER_HIGH_PCI_ADDRESS 0x8b4
  268. #define CHANNEL2_DMA_NEXT_RECORD_POINTER_HIGH_PCI_ADDRESS 0x8b8
  269. #define CHANNEL3_DMA_NEXT_RECORD_POINTER_HIGH_PCI_ADDRESS 0x8bc
  270. #define CHANNEL4_DMA_NEXT_RECORD_POINTER_HIGH_PCI_ADDRESS 0x9b0
  271. #define CHANNEL5_DMA_NEXT_RECORD_POINTER_HIGH_PCI_ADDRESS 0x9b4
  272. #define CHANNEL6_DMA_NEXT_RECORD_POINTER_HIGH_PCI_ADDRESS 0x9b8
  273. #define CHANNEL7_DMA_NEXT_RECORD_POINTER_HIGH_PCI_ADDRESS 0x9bc
  274. /****************************************/
  275. /* DMA Channel Control */
  276. /****************************************/
  277. #define CHANNEL0CONTROL 0x840
  278. #define CHANNEL0CONTROL_HIGH 0x880
  279. #define CHANNEL1CONTROL 0x844
  280. #define CHANNEL1CONTROL_HIGH 0x884
  281. #define CHANNEL2CONTROL 0x848
  282. #define CHANNEL2CONTROL_HIGH 0x888
  283. #define CHANNEL3CONTROL 0x84C
  284. #define CHANNEL3CONTROL_HIGH 0x88C
  285. #define CHANNEL4CONTROL 0x940
  286. #define CHANNEL4CONTROL_HIGH 0x980
  287. #define CHANNEL5CONTROL 0x944
  288. #define CHANNEL5CONTROL_HIGH 0x984
  289. #define CHANNEL6CONTROL 0x948
  290. #define CHANNEL6CONTROL_HIGH 0x988
  291. #define CHANNEL7CONTROL 0x94C
  292. #define CHANNEL7CONTROL_HIGH 0x98C
  293. /****************************************/
  294. /* DMA Arbiter */
  295. /****************************************/
  296. #define ARBITER_CONTROL_0_3 0x860
  297. #define ARBITER_CONTROL_4_7 0x960
  298. /****************************************/
  299. /* DMA Interrupt */
  300. /****************************************/
  301. #define CHANELS0_3_INTERRUPT_CAUSE 0x8c0
  302. #define CHANELS0_3_INTERRUPT_MASK 0x8c4
  303. #define CHANELS0_3_ERROR_ADDRESS 0x8c8
  304. #define CHANELS0_3_ERROR_SELECT 0x8cc
  305. #define CHANELS4_7_INTERRUPT_CAUSE 0x9c0
  306. #define CHANELS4_7_INTERRUPT_MASK 0x9c4
  307. #define CHANELS4_7_ERROR_ADDRESS 0x9c8
  308. #define CHANELS4_7_ERROR_SELECT 0x9cc
  309. /****************************************/
  310. /* DMA Debug (for internal use) */
  311. /****************************************/
  312. #define DMA_X0_ADDRESS 0x8e0
  313. #define DMA_X0_COMMAND_AND_ID 0x8e4
  314. #define DMA_X0_WRITE_DATA_LOW 0x8e8
  315. #define DMA_X0_WRITE_DATA_HIGH 0x8ec
  316. #define DMA_X0_WRITE_BYTE_ENABLE 0x8f8
  317. #define DMA_X0_READ_DATA_LOW 0x8f0
  318. #define DMA_X0_READ_DATA_HIGH 0x8f4
  319. #define DMA_X0_READ_ID 0x8fc
  320. #define DMA_X1_ADDRESS 0x9e0
  321. #define DMA_X1_COMMAND_AND_ID 0x9e4
  322. #define DMA_X1_WRITE_DATA_LOW 0x9e8
  323. #define DMA_X1_WRITE_DATA_HIGH 0x9ec
  324. #define DMA_X1_WRITE_BYTE_ENABLE 0x9f8
  325. #define DMA_X1_READ_DATA_LOW 0x9f0
  326. #define DMA_X1_READ_DATA_HIGH 0x9f4
  327. #define DMA_X1_READ_ID 0x9fc
  328. /****************************************/
  329. /* Timer_Counter */
  330. /****************************************/
  331. #define TIMER_COUNTER0 0x850
  332. #define TIMER_COUNTER1 0x854
  333. #define TIMER_COUNTER2 0x858
  334. #define TIMER_COUNTER3 0x85C
  335. #define TIMER_COUNTER_0_3_CONTROL 0x864
  336. #define TIMER_COUNTER_0_3_INTERRUPT_CAUSE 0x868
  337. #define TIMER_COUNTER_0_3_INTERRUPT_MASK 0x86c
  338. #define TIMER_COUNTER4 0x950
  339. #define TIMER_COUNTER5 0x954
  340. #define TIMER_COUNTER6 0x958
  341. #define TIMER_COUNTER7 0x95C
  342. #define TIMER_COUNTER_4_7_CONTROL 0x964
  343. #define TIMER_COUNTER_4_7_INTERRUPT_CAUSE 0x968
  344. #define TIMER_COUNTER_4_7_INTERRUPT_MASK 0x96c
  345. /****************************************/
  346. /* PCI Slave Address Decoding */
  347. /****************************************/
  348. #define PCI_0SCS_0_BANK_SIZE 0xc08
  349. #define PCI_1SCS_0_BANK_SIZE 0xc88
  350. #define PCI_0SCS_1_BANK_SIZE 0xd08
  351. #define PCI_1SCS_1_BANK_SIZE 0xd88
  352. #define PCI_0SCS_2_BANK_SIZE 0xc0c
  353. #define PCI_1SCS_2_BANK_SIZE 0xc8c
  354. #define PCI_0SCS_3_BANK_SIZE 0xd0c
  355. #define PCI_1SCS_3_BANK_SIZE 0xd8c
  356. #define PCI_0CS_0_BANK_SIZE 0xc10
  357. #define PCI_1CS_0_BANK_SIZE 0xc90
  358. #define PCI_0CS_1_BANK_SIZE 0xd10
  359. #define PCI_1CS_1_BANK_SIZE 0xd90
  360. #define PCI_0CS_2_BANK_SIZE 0xd18
  361. #define PCI_1CS_2_BANK_SIZE 0xd98
  362. #define PCI_0CS_3_BANK_SIZE 0xc14
  363. #define PCI_1CS_3_BANK_SIZE 0xc94
  364. #define PCI_0CS_BOOT_BANK_SIZE 0xd14
  365. #define PCI_1CS_BOOT_BANK_SIZE 0xd94
  366. #define PCI_0P2P_MEM0_BAR_SIZE 0xd1c
  367. #define PCI_1P2P_MEM0_BAR_SIZE 0xd9c
  368. #define PCI_0P2P_MEM1_BAR_SIZE 0xd20
  369. #define PCI_1P2P_MEM1_BAR_SIZE 0xda0
  370. #define PCI_0P2P_I_O_BAR_SIZE 0xd24
  371. #define PCI_1P2P_I_O_BAR_SIZE 0xda4
  372. #define PCI_0CPU_BAR_SIZE 0xd28
  373. #define PCI_1CPU_BAR_SIZE 0xda8
  374. #define PCI_0DAC_SCS_0_BANK_SIZE 0xe00
  375. #define PCI_1DAC_SCS_0_BANK_SIZE 0xe80
  376. #define PCI_0DAC_SCS_1_BANK_SIZE 0xe04
  377. #define PCI_1DAC_SCS_1_BANK_SIZE 0xe84
  378. #define PCI_0DAC_SCS_2_BANK_SIZE 0xe08
  379. #define PCI_1DAC_SCS_2_BANK_SIZE 0xe88
  380. #define PCI_0DAC_SCS_3_BANK_SIZE 0xe0c
  381. #define PCI_1DAC_SCS_3_BANK_SIZE 0xe8c
  382. #define PCI_0DAC_CS_0_BANK_SIZE 0xe10
  383. #define PCI_1DAC_CS_0_BANK_SIZE 0xe90
  384. #define PCI_0DAC_CS_1_BANK_SIZE 0xe14
  385. #define PCI_1DAC_CS_1_BANK_SIZE 0xe94
  386. #define PCI_0DAC_CS_2_BANK_SIZE 0xe18
  387. #define PCI_1DAC_CS_2_BANK_SIZE 0xe98
  388. #define PCI_0DAC_CS_3_BANK_SIZE 0xe1c
  389. #define PCI_1DAC_CS_3_BANK_SIZE 0xe9c
  390. #define PCI_0DAC_BOOTCS_BANK_SIZE 0xe20
  391. #define PCI_1DAC_BOOTCS_BANK_SIZE 0xea0
  392. #define PCI_0DAC_P2P_MEM0_BAR_SIZE 0xe24
  393. #define PCI_1DAC_P2P_MEM0_BAR_SIZE 0xea4
  394. #define PCI_0DAC_P2P_MEM1_BAR_SIZE 0xe28
  395. #define PCI_1DAC_P2P_MEM1_BAR_SIZE 0xea8
  396. #define PCI_0DAC_CPU_BAR_SIZE 0xe2c
  397. #define PCI_1DAC_CPU_BAR_SIZE 0xeac
  398. #define PCI_0EXPANSION_ROM_BAR_SIZE 0xd2c
  399. #define PCI_1EXPANSION_ROM_BAR_SIZE 0xdac
  400. #define PCI_0BASE_ADDRESS_REGISTERS_ENABLE 0xc3c
  401. #define PCI_1BASE_ADDRESS_REGISTERS_ENABLE 0xcbc
  402. #define PCI_0SCS_0_BASE_ADDRESS_REMAP 0xc48
  403. #define PCI_1SCS_0_BASE_ADDRESS_REMAP 0xcc8
  404. #define PCI_0SCS_1_BASE_ADDRESS_REMAP 0xd48
  405. #define PCI_1SCS_1_BASE_ADDRESS_REMAP 0xdc8
  406. #define PCI_0SCS_2_BASE_ADDRESS_REMAP 0xc4c
  407. #define PCI_1SCS_2_BASE_ADDRESS_REMAP 0xccc
  408. #define PCI_0SCS_3_BASE_ADDRESS_REMAP 0xd4c
  409. #define PCI_1SCS_3_BASE_ADDRESS_REMAP 0xdcc
  410. #define PCI_0CS_0_BASE_ADDRESS_REMAP 0xc50
  411. #define PCI_1CS_0_BASE_ADDRESS_REMAP 0xcd0
  412. #define PCI_0CS_1_BASE_ADDRESS_REMAP 0xd50
  413. #define PCI_1CS_1_BASE_ADDRESS_REMAP 0xdd0
  414. #define PCI_0CS_2_BASE_ADDRESS_REMAP 0xd58
  415. #define PCI_1CS_2_BASE_ADDRESS_REMAP 0xdd8
  416. #define PCI_0CS_3_BASE_ADDRESS_REMAP 0xc54
  417. #define PCI_1CS_3_BASE_ADDRESS_REMAP 0xcd4
  418. #define PCI_0CS_BOOTCS_BASE_ADDRESS_REMAP 0xd54
  419. #define PCI_1CS_BOOTCS_BASE_ADDRESS_REMAP 0xdd4
  420. #define PCI_0P2P_MEM0_BASE_ADDRESS_REMAP_LOW 0xd5c
  421. #define PCI_1P2P_MEM0_BASE_ADDRESS_REMAP_LOW 0xddc
  422. #define PCI_0P2P_MEM0_BASE_ADDRESS_REMAP_HIGH 0xd60
  423. #define PCI_1P2P_MEM0_BASE_ADDRESS_REMAP_HIGH 0xde0
  424. #define PCI_0P2P_MEM1_BASE_ADDRESS_REMAP_LOW 0xd64
  425. #define PCI_1P2P_MEM1_BASE_ADDRESS_REMAP_LOW 0xde4
  426. #define PCI_0P2P_MEM1_BASE_ADDRESS_REMAP_HIGH 0xd68
  427. #define PCI_1P2P_MEM1_BASE_ADDRESS_REMAP_HIGH 0xde8
  428. #define PCI_0P2P_I_O_BASE_ADDRESS_REMAP 0xd6c
  429. #define PCI_1P2P_I_O_BASE_ADDRESS_REMAP 0xdec
  430. #define PCI_0CPU_BASE_ADDRESS_REMAP 0xd70
  431. #define PCI_1CPU_BASE_ADDRESS_REMAP 0xdf0
  432. #define PCI_0DAC_SCS_0_BASE_ADDRESS_REMAP 0xf00
  433. #define PCI_1DAC_SCS_0_BASE_ADDRESS_REMAP 0xff0
  434. #define PCI_0DAC_SCS_1_BASE_ADDRESS_REMAP 0xf04
  435. #define PCI_1DAC_SCS_1_BASE_ADDRESS_REMAP 0xf84
  436. #define PCI_0DAC_SCS_2_BASE_ADDRESS_REMAP 0xf08
  437. #define PCI_1DAC_SCS_2_BASE_ADDRESS_REMAP 0xf88
  438. #define PCI_0DAC_SCS_3_BASE_ADDRESS_REMAP 0xf0c
  439. #define PCI_1DAC_SCS_3_BASE_ADDRESS_REMAP 0xf8c
  440. #define PCI_0DAC_CS_0_BASE_ADDRESS_REMAP 0xf10
  441. #define PCI_1DAC_CS_0_BASE_ADDRESS_REMAP 0xf90
  442. #define PCI_0DAC_CS_1_BASE_ADDRESS_REMAP 0xf14
  443. #define PCI_1DAC_CS_1_BASE_ADDRESS_REMAP 0xf94
  444. #define PCI_0DAC_CS_2_BASE_ADDRESS_REMAP 0xf18
  445. #define PCI_1DAC_CS_2_BASE_ADDRESS_REMAP 0xf98
  446. #define PCI_0DAC_CS_3_BASE_ADDRESS_REMAP 0xf1c
  447. #define PCI_1DAC_CS_3_BASE_ADDRESS_REMAP 0xf9c
  448. #define PCI_0DAC_BOOTCS_BASE_ADDRESS_REMAP 0xf20
  449. #define PCI_1DAC_BOOTCS_BASE_ADDRESS_REMAP 0xfa0
  450. #define PCI_0DAC_P2P_MEM0_BASE_ADDRESS_REMAP_LOW 0xf24
  451. #define PCI_1DAC_P2P_MEM0_BASE_ADDRESS_REMAP_LOW 0xfa4
  452. #define PCI_0DAC_P2P_MEM0_BASE_ADDRESS_REMAP_HIGH 0xf28
  453. #define PCI_1DAC_P2P_MEM0_BASE_ADDRESS_REMAP_HIGH 0xfa8
  454. #define PCI_0DAC_P2P_MEM1_BASE_ADDRESS_REMAP_LOW 0xf2c
  455. #define PCI_1DAC_P2P_MEM1_BASE_ADDRESS_REMAP_LOW 0xfac
  456. #define PCI_0DAC_P2P_MEM1_BASE_ADDRESS_REMAP_HIGH 0xf30
  457. #define PCI_1DAC_P2P_MEM1_BASE_ADDRESS_REMAP_HIGH 0xfb0
  458. #define PCI_0DAC_CPU_BASE_ADDRESS_REMAP 0xf34
  459. #define PCI_1DAC_CPU_BASE_ADDRESS_REMAP 0xfb4
  460. #define PCI_0EXPANSION_ROM_BASE_ADDRESS_REMAP 0xf38
  461. #define PCI_1EXPANSION_ROM_BASE_ADDRESS_REMAP 0xfb8
  462. #define PCI_0ADDRESS_DECODE_CONTROL 0xd3c
  463. #define PCI_1ADDRESS_DECODE_CONTROL 0xdbc
  464. /****************************************/
  465. /* PCI Control */
  466. /****************************************/
  467. #define PCI_0COMMAND 0xc00
  468. #define PCI_1COMMAND 0xc80
  469. #define PCI_0MODE 0xd00
  470. #define PCI_1MODE 0xd80
  471. #define PCI_0TIMEOUT_RETRY 0xc04
  472. #define PCI_1TIMEOUT_RETRY 0xc84
  473. #define PCI_0READ_BUFFER_DISCARD_TIMER 0xd04
  474. #define PCI_1READ_BUFFER_DISCARD_TIMER 0xd84
  475. #define MSI_0TRIGGER_TIMER 0xc38
  476. #define MSI_1TRIGGER_TIMER 0xcb8
  477. #define PCI_0ARBITER_CONTROL 0x1d00
  478. #define PCI_1ARBITER_CONTROL 0x1d80
  479. /* changing untill here */
  480. #define PCI_0CROSS_BAR_CONTROL_LOW 0x1d08
  481. #define PCI_0CROSS_BAR_CONTROL_HIGH 0x1d0c
  482. #define PCI_0CROSS_BAR_TIMEOUT 0x1d04
  483. #define PCI_0READ_RESPONSE_CROSS_BAR_CONTROL_LOW 0x1d18
  484. #define PCI_0READ_RESPONSE_CROSS_BAR_CONTROL_HIGH 0x1d1c
  485. #define PCI_0SYNC_BARRIER_VIRTUAL_REGISTER 0x1d10
  486. #define PCI_0P2P_CONFIGURATION 0x1d14
  487. #define PCI_0ACCESS_CONTROL_BASE_0_LOW 0x1e00
  488. #define PCI_0ACCESS_CONTROL_BASE_0_HIGH 0x1e04
  489. #define PCI_0ACCESS_CONTROL_TOP_0 0x1e08
  490. #define PCI_0ACCESS_CONTROL_BASE_1_LOW 0x1e10
  491. #define PCI_0ACCESS_CONTROL_BASE_1_HIGH 0x1e14
  492. #define PCI_0ACCESS_CONTROL_TOP_1 0x1e18
  493. #define PCI_0ACCESS_CONTROL_BASE_2_LOW 0x1e20
  494. #define PCI_0ACCESS_CONTROL_BASE_2_HIGH 0x1e24
  495. #define PCI_0ACCESS_CONTROL_TOP_2 0x1e28
  496. #define PCI_0ACCESS_CONTROL_BASE_3_LOW 0x1e30
  497. #define PCI_0ACCESS_CONTROL_BASE_3_HIGH 0x1e34
  498. #define PCI_0ACCESS_CONTROL_TOP_3 0x1e38
  499. #define PCI_0ACCESS_CONTROL_BASE_4_LOW 0x1e40
  500. #define PCI_0ACCESS_CONTROL_BASE_4_HIGH 0x1e44
  501. #define PCI_0ACCESS_CONTROL_TOP_4 0x1e48
  502. #define PCI_0ACCESS_CONTROL_BASE_5_LOW 0x1e50
  503. #define PCI_0ACCESS_CONTROL_BASE_5_HIGH 0x1e54
  504. #define PCI_0ACCESS_CONTROL_TOP_5 0x1e58
  505. #define PCI_0ACCESS_CONTROL_BASE_6_LOW 0x1e60
  506. #define PCI_0ACCESS_CONTROL_BASE_6_HIGH 0x1e64
  507. #define PCI_0ACCESS_CONTROL_TOP_6 0x1e68
  508. #define PCI_0ACCESS_CONTROL_BASE_7_LOW 0x1e70
  509. #define PCI_0ACCESS_CONTROL_BASE_7_HIGH 0x1e74
  510. #define PCI_0ACCESS_CONTROL_TOP_7 0x1e78
  511. #define PCI_1CROSS_BAR_CONTROL_LOW 0x1d88
  512. #define PCI_1CROSS_BAR_CONTROL_HIGH 0x1d8c
  513. #define PCI_1CROSS_BAR_TIMEOUT 0x1d84
  514. #define PCI_1READ_RESPONSE_CROSS_BAR_CONTROL_LOW 0x1d98
  515. #define PCI_1READ_RESPONSE_CROSS_BAR_CONTROL_HIGH 0x1d9c
  516. #define PCI_1SYNC_BARRIER_VIRTUAL_REGISTER 0x1d90
  517. #define PCI_1P2P_CONFIGURATION 0x1d94
  518. #define PCI_1ACCESS_CONTROL_BASE_0_LOW 0x1e80
  519. #define PCI_1ACCESS_CONTROL_BASE_0_HIGH 0x1e84
  520. #define PCI_1ACCESS_CONTROL_TOP_0 0x1e88
  521. #define PCI_1ACCESS_CONTROL_BASE_1_LOW 0x1e90
  522. #define PCI_1ACCESS_CONTROL_BASE_1_HIGH 0x1e94
  523. #define PCI_1ACCESS_CONTROL_TOP_1 0x1e98
  524. #define PCI_1ACCESS_CONTROL_BASE_2_LOW 0x1ea0
  525. #define PCI_1ACCESS_CONTROL_BASE_2_HIGH 0x1ea4
  526. #define PCI_1ACCESS_CONTROL_TOP_2 0x1ea8
  527. #define PCI_1ACCESS_CONTROL_BASE_3_LOW 0x1eb0
  528. #define PCI_1ACCESS_CONTROL_BASE_3_HIGH 0x1eb4
  529. #define PCI_1ACCESS_CONTROL_TOP_3 0x1eb8
  530. #define PCI_1ACCESS_CONTROL_BASE_4_LOW 0x1ec0
  531. #define PCI_1ACCESS_CONTROL_BASE_4_HIGH 0x1ec4
  532. #define PCI_1ACCESS_CONTROL_TOP_4 0x1ec8
  533. #define PCI_1ACCESS_CONTROL_BASE_5_LOW 0x1ed0
  534. #define PCI_1ACCESS_CONTROL_BASE_5_HIGH 0x1ed4
  535. #define PCI_1ACCESS_CONTROL_TOP_5 0x1ed8
  536. #define PCI_1ACCESS_CONTROL_BASE_6_LOW 0x1ee0
  537. #define PCI_1ACCESS_CONTROL_BASE_6_HIGH 0x1ee4
  538. #define PCI_1ACCESS_CONTROL_TOP_6 0x1ee8
  539. #define PCI_1ACCESS_CONTROL_BASE_7_LOW 0x1ef0
  540. #define PCI_1ACCESS_CONTROL_BASE_7_HIGH 0x1ef4
  541. #define PCI_1ACCESS_CONTROL_TOP_7 0x1ef8
  542. /****************************************/
  543. /* PCI Snoop Control */
  544. /****************************************/
  545. #define PCI_0SNOOP_CONTROL_BASE_0_LOW 0x1f00
  546. #define PCI_0SNOOP_CONTROL_BASE_0_HIGH 0x1f04
  547. #define PCI_0SNOOP_CONTROL_TOP_0 0x1f08
  548. #define PCI_0SNOOP_CONTROL_BASE_1_0_LOW 0x1f10
  549. #define PCI_0SNOOP_CONTROL_BASE_1_0_HIGH 0x1f14
  550. #define PCI_0SNOOP_CONTROL_TOP_1 0x1f18
  551. #define PCI_0SNOOP_CONTROL_BASE_2_0_LOW 0x1f20
  552. #define PCI_0SNOOP_CONTROL_BASE_2_0_HIGH 0x1f24
  553. #define PCI_0SNOOP_CONTROL_TOP_2 0x1f28
  554. #define PCI_0SNOOP_CONTROL_BASE_3_0_LOW 0x1f30
  555. #define PCI_0SNOOP_CONTROL_BASE_3_0_HIGH 0x1f34
  556. #define PCI_0SNOOP_CONTROL_TOP_3 0x1f38
  557. #define PCI_1SNOOP_CONTROL_BASE_0_LOW 0x1f80
  558. #define PCI_1SNOOP_CONTROL_BASE_0_HIGH 0x1f84
  559. #define PCI_1SNOOP_CONTROL_TOP_0 0x1f88
  560. #define PCI_1SNOOP_CONTROL_BASE_1_0_LOW 0x1f90
  561. #define PCI_1SNOOP_CONTROL_BASE_1_0_HIGH 0x1f94
  562. #define PCI_1SNOOP_CONTROL_TOP_1 0x1f98
  563. #define PCI_1SNOOP_CONTROL_BASE_2_0_LOW 0x1fa0
  564. #define PCI_1SNOOP_CONTROL_BASE_2_0_HIGH 0x1fa4
  565. #define PCI_1SNOOP_CONTROL_TOP_2 0x1fa8
  566. #define PCI_1SNOOP_CONTROL_BASE_3_0_LOW 0x1fb0
  567. #define PCI_1SNOOP_CONTROL_BASE_3_0_HIGH 0x1fb4
  568. #define PCI_1SNOOP_CONTROL_TOP_3 0x1fb8
  569. /****************************************/
  570. /* PCI Configuration Address */
  571. /****************************************/
  572. #define PCI_0CONFIGURATION_ADDRESS 0xcf8
  573. #define PCI_0CONFIGURATION_DATA_VIRTUAL_REGISTER 0xcfc
  574. #define PCI_1CONFIGURATION_ADDRESS 0xc78
  575. #define PCI_1CONFIGURATION_DATA_VIRTUAL_REGISTER 0xc7c
  576. #define PCI_0INTERRUPT_ACKNOWLEDGE_VIRTUAL_REGISTER 0xc34
  577. #define PCI_1INTERRUPT_ACKNOWLEDGE_VIRTUAL_REGISTER 0xcb4
  578. /****************************************/
  579. /* PCI Error Report */
  580. /****************************************/
  581. #define PCI_0SERR_MASK 0xc28
  582. #define PCI_0ERROR_ADDRESS_LOW 0x1d40
  583. #define PCI_0ERROR_ADDRESS_HIGH 0x1d44
  584. #define PCI_0ERROR_DATA_LOW 0x1d48
  585. #define PCI_0ERROR_DATA_HIGH 0x1d4c
  586. #define PCI_0ERROR_COMMAND 0x1d50
  587. #define PCI_0ERROR_CAUSE 0x1d58
  588. #define PCI_0ERROR_MASK 0x1d5c
  589. #define PCI_1SERR_MASK 0xca8
  590. #define PCI_1ERROR_ADDRESS_LOW 0x1dc0
  591. #define PCI_1ERROR_ADDRESS_HIGH 0x1dc4
  592. #define PCI_1ERROR_DATA_LOW 0x1dc8
  593. #define PCI_1ERROR_DATA_HIGH 0x1dcc
  594. #define PCI_1ERROR_COMMAND 0x1dd0
  595. #define PCI_1ERROR_CAUSE 0x1dd8
  596. #define PCI_1ERROR_MASK 0x1ddc
  597. /****************************************/
  598. /* Lslave Debug (for internal use) */
  599. /****************************************/
  600. #define L_SLAVE_X0_ADDRESS 0x1d20
  601. #define L_SLAVE_X0_COMMAND_AND_ID 0x1d24
  602. #define L_SLAVE_X1_ADDRESS 0x1d28
  603. #define L_SLAVE_X1_COMMAND_AND_ID 0x1d2c
  604. #define L_SLAVE_WRITE_DATA_LOW 0x1d30
  605. #define L_SLAVE_WRITE_DATA_HIGH 0x1d34
  606. #define L_SLAVE_WRITE_BYTE_ENABLE 0x1d60
  607. #define L_SLAVE_READ_DATA_LOW 0x1d38
  608. #define L_SLAVE_READ_DATA_HIGH 0x1d3c
  609. #define L_SLAVE_READ_ID 0x1d64
  610. /****************************************/
  611. /* PCI Configuration Function 0 */
  612. /****************************************/
  613. #define PCI_DEVICE_AND_VENDOR_ID 0x000
  614. #define PCI_STATUS_AND_COMMAND 0x004
  615. #define PCI_CLASS_CODE_AND_REVISION_ID 0x008
  616. #define PCI_BIST_HEADER_TYPE_LATENCY_TIMER_CACHE_LINE 0x00C
  617. #define PCI_SCS_0_BASE_ADDRESS 0x010
  618. #define PCI_SCS_1_BASE_ADDRESS 0x014
  619. #define PCI_SCS_2_BASE_ADDRESS 0x018
  620. #define PCI_SCS_3_BASE_ADDRESS 0x01C
  621. #define PCI_INTERNAL_REGISTERS_MEMORY_MAPPED_BASE_ADDRESS 0x020
  622. #define PCI_INTERNAL_REGISTERS_I_OMAPPED_BASE_ADDRESS 0x024
  623. #define PCI_SUBSYSTEM_ID_AND_SUBSYSTEM_VENDOR_ID 0x02C
  624. #define PCI_EXPANSION_ROM_BASE_ADDRESS_REGISTER 0x030
  625. #define PCI_CAPABILTY_LIST_POINTER 0x034
  626. #define PCI_INTERRUPT_PIN_AND_LINE 0x03C
  627. #define PCI_POWER_MANAGEMENT_CAPABILITY 0x040
  628. #define PCI_POWER_MANAGEMENT_STATUS_AND_CONTROL 0x044
  629. #define PCI_VPD_ADDRESS 0x048
  630. #define PCI_VPD_DATA 0x04c
  631. #define PCI_MSI_MESSAGE_CONTROL 0x050
  632. #define PCI_MSI_MESSAGE_ADDRESS 0x054
  633. #define PCI_MSI_MESSAGE_UPPER_ADDRESS 0x058
  634. #define PCI_MSI_MESSAGE_DATA 0x05c
  635. #define PCI_COMPACT_PCI_HOT_SWAP_CAPABILITY 0x058
  636. /****************************************/
  637. /* PCI Configuration Function 1 */
  638. /****************************************/
  639. #define PCI_CS_0_BASE_ADDRESS 0x110
  640. #define PCI_CS_1_BASE_ADDRESS 0x114
  641. #define PCI_CS_2_BASE_ADDRESS 0x118
  642. #define PCI_CS_3_BASE_ADDRESS 0x11c
  643. #define PCI_BOOTCS_BASE_ADDRESS 0x120
  644. /****************************************/
  645. /* PCI Configuration Function 2 */
  646. /****************************************/
  647. #define PCI_P2P_MEM0_BASE_ADDRESS 0x210
  648. #define PCI_P2P_MEM1_BASE_ADDRESS 0x214
  649. #define PCI_P2P_I_O_BASE_ADDRESS 0x218
  650. #define PCI_CPU_BASE_ADDRESS 0x21c
  651. /****************************************/
  652. /* PCI Configuration Function 4 */
  653. /****************************************/
  654. #define PCI_DAC_SCS_0_BASE_ADDRESS_LOW 0x410
  655. #define PCI_DAC_SCS_0_BASE_ADDRESS_HIGH 0x414
  656. #define PCI_DAC_SCS_1_BASE_ADDRESS_LOW 0x418
  657. #define PCI_DAC_SCS_1_BASE_ADDRESS_HIGH 0x41c
  658. #define PCI_DAC_P2P_MEM0_BASE_ADDRESS_LOW 0x420
  659. #define PCI_DAC_P2P_MEM0_BASE_ADDRESS_HIGH 0x424
  660. /****************************************/
  661. /* PCI Configuration Function 5 */
  662. /****************************************/
  663. #define PCI_DAC_SCS_2_BASE_ADDRESS_LOW 0x510
  664. #define PCI_DAC_SCS_2_BASE_ADDRESS_HIGH 0x514
  665. #define PCI_DAC_SCS_3_BASE_ADDRESS_LOW 0x518
  666. #define PCI_DAC_SCS_3_BASE_ADDRESS_HIGH 0x51c
  667. #define PCI_DAC_P2P_MEM1_BASE_ADDRESS_LOW 0x520
  668. #define PCI_DAC_P2P_MEM1_BASE_ADDRESS_HIGH 0x524
  669. /****************************************/
  670. /* PCI Configuration Function 6 */
  671. /****************************************/
  672. #define PCI_DAC_CS_0_BASE_ADDRESS_LOW 0x610
  673. #define PCI_DAC_CS_0_BASE_ADDRESS_HIGH 0x614
  674. #define PCI_DAC_CS_1_BASE_ADDRESS_LOW 0x618
  675. #define PCI_DAC_CS_1_BASE_ADDRESS_HIGH 0x61c
  676. #define PCI_DAC_CS_2_BASE_ADDRESS_LOW 0x620
  677. #define PCI_DAC_CS_2_BASE_ADDRESS_HIGH 0x624
  678. /****************************************/
  679. /* PCI Configuration Function 7 */
  680. /****************************************/
  681. #define PCI_DAC_CS_3_BASE_ADDRESS_LOW 0x710
  682. #define PCI_DAC_CS_3_BASE_ADDRESS_HIGH 0x714
  683. #define PCI_DAC_BOOTCS_BASE_ADDRESS_LOW 0x718
  684. #define PCI_DAC_BOOTCS_BASE_ADDRESS_HIGH 0x71c
  685. #define PCI_DAC_CPU_BASE_ADDRESS_LOW 0x720
  686. #define PCI_DAC_CPU_BASE_ADDRESS_HIGH 0x724
  687. /****************************************/
  688. /* Interrupts */
  689. /****************************************/
  690. #define LOW_INTERRUPT_CAUSE_REGISTER 0xc18
  691. #define HIGH_INTERRUPT_CAUSE_REGISTER 0xc68
  692. #define CPU_INTERRUPT_MASK_REGISTER_LOW 0xc1c
  693. #define CPU_INTERRUPT_MASK_REGISTER_HIGH 0xc6c
  694. #define CPU_SELECT_CAUSE_REGISTER 0xc70
  695. #define PCI_0INTERRUPT_CAUSE_MASK_REGISTER_LOW 0xc24
  696. #define PCI_0INTERRUPT_CAUSE_MASK_REGISTER_HIGH 0xc64
  697. #define PCI_0SELECT_CAUSE 0xc74
  698. #define PCI_1INTERRUPT_CAUSE_MASK_REGISTER_LOW 0xca4
  699. #define PCI_1INTERRUPT_CAUSE_MASK_REGISTER_HIGH 0xce4
  700. #define PCI_1SELECT_CAUSE 0xcf4
  701. #define CPU_INT_0_MASK 0xe60
  702. #define CPU_INT_1_MASK 0xe64
  703. #define CPU_INT_2_MASK 0xe68
  704. #define CPU_INT_3_MASK 0xe6c
  705. /****************************************/
  706. /* I20 Support registers */
  707. /****************************************/
  708. #define INBOUND_MESSAGE_REGISTER0_PCI_SIDE 0x010
  709. #define INBOUND_MESSAGE_REGISTER1_PCI_SIDE 0x014
  710. #define OUTBOUND_MESSAGE_REGISTER0_PCI_SIDE 0x018
  711. #define OUTBOUND_MESSAGE_REGISTER1_PCI_SIDE 0x01C
  712. #define INBOUND_DOORBELL_REGISTER_PCI_SIDE 0x020
  713. #define INBOUND_INTERRUPT_CAUSE_REGISTER_PCI_SIDE 0x024
  714. #define INBOUND_INTERRUPT_MASK_REGISTER_PCI_SIDE 0x028
  715. #define OUTBOUND_DOORBELL_REGISTER_PCI_SIDE 0x02C
  716. #define OUTBOUND_INTERRUPT_CAUSE_REGISTER_PCI_SIDE 0x030
  717. #define OUTBOUND_INTERRUPT_MASK_REGISTER_PCI_SIDE 0x034
  718. #define INBOUND_QUEUE_PORT_VIRTUAL_REGISTER_PCI_SIDE 0x040
  719. #define OUTBOUND_QUEUE_PORT_VIRTUAL_REGISTER_PCI_SIDE 0x044
  720. #define QUEUE_CONTROL_REGISTER_PCI_SIDE 0x050
  721. #define QUEUE_BASE_ADDRESS_REGISTER_PCI_SIDE 0x054
  722. #define INBOUND_FREE_HEAD_POINTER_REGISTER_PCI_SIDE 0x060
  723. #define INBOUND_FREE_TAIL_POINTER_REGISTER_PCI_SIDE 0x064
  724. #define INBOUND_POST_HEAD_POINTER_REGISTER_PCI_SIDE 0x068
  725. #define INBOUND_POST_TAIL_POINTER_REGISTER_PCI_SIDE 0x06C
  726. #define OUTBOUND_FREE_HEAD_POINTER_REGISTER_PCI_SIDE 0x070
  727. #define OUTBOUND_FREE_TAIL_POINTER_REGISTER_PCI_SIDE 0x074
  728. #define OUTBOUND_POST_HEAD_POINTER_REGISTER_PCI_SIDE 0x078
  729. #define OUTBOUND_POST_TAIL_POINTER_REGISTER_PCI_SIDE 0x07C
  730. #define INBOUND_MESSAGE_REGISTER0_CPU_SIDE 0x1C10
  731. #define INBOUND_MESSAGE_REGISTER1_CPU_SIDE 0x1C14
  732. #define OUTBOUND_MESSAGE_REGISTER0_CPU_SIDE 0x1C18
  733. #define OUTBOUND_MESSAGE_REGISTER1_CPU_SIDE 0x1C1C
  734. #define INBOUND_DOORBELL_REGISTER_CPU_SIDE 0x1C20
  735. #define INBOUND_INTERRUPT_CAUSE_REGISTER_CPU_SIDE 0x1C24
  736. #define INBOUND_INTERRUPT_MASK_REGISTER_CPU_SIDE 0x1C28
  737. #define OUTBOUND_DOORBELL_REGISTER_CPU_SIDE 0x1C2C
  738. #define OUTBOUND_INTERRUPT_CAUSE_REGISTER_CPU_SIDE 0x1C30
  739. #define OUTBOUND_INTERRUPT_MASK_REGISTER_CPU_SIDE 0x1C34
  740. #define INBOUND_QUEUE_PORT_VIRTUAL_REGISTER_CPU_SIDE 0x1C40
  741. #define OUTBOUND_QUEUE_PORT_VIRTUAL_REGISTER_CPU_SIDE 0x1C44
  742. #define QUEUE_CONTROL_REGISTER_CPU_SIDE 0x1C50
  743. #define QUEUE_BASE_ADDRESS_REGISTER_CPU_SIDE 0x1C54
  744. #define INBOUND_FREE_HEAD_POINTER_REGISTER_CPU_SIDE 0x1C60
  745. #define INBOUND_FREE_TAIL_POINTER_REGISTER_CPU_SIDE 0x1C64
  746. #define INBOUND_POST_HEAD_POINTER_REGISTER_CPU_SIDE 0x1C68
  747. #define INBOUND_POST_TAIL_POINTER_REGISTER_CPU_SIDE 0x1C6C
  748. #define OUTBOUND_FREE_HEAD_POINTER_REGISTER_CPU_SIDE 0x1C70
  749. #define OUTBOUND_FREE_TAIL_POINTER_REGISTER_CPU_SIDE 0x1C74
  750. #define OUTBOUND_POST_HEAD_POINTER_REGISTER_CPU_SIDE 0x1C78
  751. #define OUTBOUND_POST_TAIL_POINTER_REGISTER_CPU_SIDE 0x1C7C
  752. /****************************************/
  753. /* Communication Unit Registers */
  754. /****************************************/
  755. #define ETHERNET_0_ADDRESS_CONTROL_LOW 0xf200
  756. #define ETHERNET_0_ADDRESS_CONTROL_HIGH 0xf204
  757. #define ETHERNET_0_RECEIVE_BUFFER_PCI_HIGH_ADDRESS 0xf208
  758. #define ETHERNET_0_TRANSMIT_BUFFER_PCI_HIGH_ADDRESS 0xf20c
  759. #define ETHERNET_0_RECEIVE_DESCRIPTOR_PCI_HIGH_ADDRESS 0xf210
  760. #define ETHERNET_0_TRANSMIT_DESCRIPTOR_PCI_HIGH_ADDRESS 0xf214
  761. #define ETHERNET_0_HASH_TABLE_PCI_HIGH_ADDRESS 0xf218
  762. #define ETHERNET_1_ADDRESS_CONTROL_LOW 0xf220
  763. #define ETHERNET_1_ADDRESS_CONTROL_HIGH 0xf224
  764. #define ETHERNET_1_RECEIVE_BUFFER_PCI_HIGH_ADDRESS 0xf228
  765. #define ETHERNET_1_TRANSMIT_BUFFER_PCI_HIGH_ADDRESS 0xf22c
  766. #define ETHERNET_1_RECEIVE_DESCRIPTOR_PCI_HIGH_ADDRESS 0xf230
  767. #define ETHERNET_1_TRANSMIT_DESCRIPTOR_PCI_HIGH_ADDRESS 0xf234
  768. #define ETHERNET_1_HASH_TABLE_PCI_HIGH_ADDRESS 0xf238
  769. #define ETHERNET_2_ADDRESS_CONTROL_LOW 0xf240
  770. #define ETHERNET_2_ADDRESS_CONTROL_HIGH 0xf244
  771. #define ETHERNET_2_RECEIVE_BUFFER_PCI_HIGH_ADDRESS 0xf248
  772. #define ETHERNET_2_TRANSMIT_BUFFER_PCI_HIGH_ADDRESS 0xf24c
  773. #define ETHERNET_2_RECEIVE_DESCRIPTOR_PCI_HIGH_ADDRESS 0xf250
  774. #define ETHERNET_2_TRANSMIT_DESCRIPTOR_PCI_HIGH_ADDRESS 0xf254
  775. #define ETHERNET_2_HASH_TABLE_PCI_HIGH_ADDRESS 0xf258
  776. #define MPSC_0_ADDRESS_CONTROL_LOW 0xf280
  777. #define MPSC_0_ADDRESS_CONTROL_HIGH 0xf284
  778. #define MPSC_0_RECEIVE_BUFFER_PCI_HIGH_ADDRESS 0xf288
  779. #define MPSC_0_TRANSMIT_BUFFER_PCI_HIGH_ADDRESS 0xf28c
  780. #define MPSC_0_RECEIVE_DESCRIPTOR_PCI_HIGH_ADDRESS 0xf290
  781. #define MPSC_0_TRANSMIT_DESCRIPTOR_PCI_HIGH_ADDRESS 0xf294
  782. #define MPSC_1_ADDRESS_CONTROL_LOW 0xf2c0
  783. #define MPSC_1_ADDRESS_CONTROL_HIGH 0xf2c4
  784. #define MPSC_1_RECEIVE_BUFFER_PCI_HIGH_ADDRESS 0xf2c8
  785. #define MPSC_1_TRANSMIT_BUFFER_PCI_HIGH_ADDRESS 0xf2cc
  786. #define MPSC_1_RECEIVE_DESCRIPTOR_PCI_HIGH_ADDRESS 0xf2d0
  787. #define MPSC_1_TRANSMIT_DESCRIPTOR_PCI_HIGH_ADDRESS 0xf2d4
  788. #define SERIAL_INIT_PCI_HIGH_ADDRESS 0xf320
  789. #define SERIAL_INIT_LAST_DATA 0xf324
  790. #define SERIAL_INIT_STATUS_AND_CONTROL 0xf328
  791. #define COMM_UNIT_ARBITER_CONTROL 0xf300
  792. #define COMM_UNIT_CROSS_BAR_TIMEOUT 0xf304
  793. #define COMM_UNIT_INTERRUPT_CAUSE 0xf310
  794. #define COMM_UNIT_INTERRUPT_MASK 0xf314
  795. #define COMM_UNIT_ERROR_ADDRESS 0xf314
  796. /****************************************/
  797. /* Cunit Debug (for internal use) */
  798. /****************************************/
  799. #define CUNIT_ADDRESS 0xf340
  800. #define CUNIT_COMMAND_AND_ID 0xf344
  801. #define CUNIT_WRITE_DATA_LOW 0xf348
  802. #define CUNIT_WRITE_DATA_HIGH 0xf34c
  803. #define CUNIT_WRITE_BYTE_ENABLE 0xf358
  804. #define CUNIT_READ_DATA_LOW 0xf350
  805. #define CUNIT_READ_DATA_HIGH 0xf354
  806. #define CUNIT_READ_ID 0xf35c
  807. /****************************************/
  808. /* Fast Ethernet Unit Registers */
  809. /****************************************/
  810. /* Ethernet */
  811. #define ETHERNET_PHY_ADDRESS_REGISTER 0x2000
  812. #define ETHERNET_SMI_REGISTER 0x2010
  813. /* Ethernet 0 */
  814. #define ETHERNET0_PORT_CONFIGURATION_REGISTER 0x2400
  815. #define ETHERNET0_PORT_CONFIGURATION_EXTEND_REGISTER 0x2408
  816. #define ETHERNET0_PORT_COMMAND_REGISTER 0x2410
  817. #define ETHERNET0_PORT_STATUS_REGISTER 0x2418
  818. #define ETHERNET0_SERIAL_PARAMETRS_REGISTER 0x2420
  819. #define ETHERNET0_HASH_TABLE_POINTER_REGISTER 0x2428
  820. #define ETHERNET0_FLOW_CONTROL_SOURCE_ADDRESS_LOW 0x2430
  821. #define ETHERNET0_FLOW_CONTROL_SOURCE_ADDRESS_HIGH 0x2438
  822. #define ETHERNET0_SDMA_CONFIGURATION_REGISTER 0x2440
  823. #define ETHERNET0_SDMA_COMMAND_REGISTER 0x2448
  824. #define ETHERNET0_INTERRUPT_CAUSE_REGISTER 0x2450
  825. #define ETHERNET0_INTERRUPT_MASK_REGISTER 0x2458
  826. #define ETHERNET0_FIRST_RX_DESCRIPTOR_POINTER0 0x2480
  827. #define ETHERNET0_FIRST_RX_DESCRIPTOR_POINTER1 0x2484
  828. #define ETHERNET0_FIRST_RX_DESCRIPTOR_POINTER2 0x2488
  829. #define ETHERNET0_FIRST_RX_DESCRIPTOR_POINTER3 0x248c
  830. #define ETHERNET0_CURRENT_RX_DESCRIPTOR_POINTER0 0x24a0
  831. #define ETHERNET0_CURRENT_RX_DESCRIPTOR_POINTER1 0x24a4
  832. #define ETHERNET0_CURRENT_RX_DESCRIPTOR_POINTER2 0x24a8
  833. #define ETHERNET0_CURRENT_RX_DESCRIPTOR_POINTER3 0x24ac
  834. #define ETHERNET0_CURRENT_TX_DESCRIPTOR_POINTER0 0x24e0
  835. #define ETHERNET0_CURRENT_TX_DESCRIPTOR_POINTER1 0x24e4
  836. #define ETHERNET0_MIB_COUNTER_BASE 0x2500
  837. /* Ethernet 1 */
  838. #define ETHERNET1_PORT_CONFIGURATION_REGISTER 0x2800
  839. #define ETHERNET1_PORT_CONFIGURATION_EXTEND_REGISTER 0x2808
  840. #define ETHERNET1_PORT_COMMAND_REGISTER 0x2810
  841. #define ETHERNET1_PORT_STATUS_REGISTER 0x2818
  842. #define ETHERNET1_SERIAL_PARAMETRS_REGISTER 0x2820
  843. #define ETHERNET1_HASH_TABLE_POINTER_REGISTER 0x2828
  844. #define ETHERNET1_FLOW_CONTROL_SOURCE_ADDRESS_LOW 0x2830
  845. #define ETHERNET1_FLOW_CONTROL_SOURCE_ADDRESS_HIGH 0x2838
  846. #define ETHERNET1_SDMA_CONFIGURATION_REGISTER 0x2840
  847. #define ETHERNET1_SDMA_COMMAND_REGISTER 0x2848
  848. #define ETHERNET1_INTERRUPT_CAUSE_REGISTER 0x2850
  849. #define ETHERNET1_INTERRUPT_MASK_REGISTER 0x2858
  850. #define ETHERNET1_FIRST_RX_DESCRIPTOR_POINTER0 0x2880
  851. #define ETHERNET1_FIRST_RX_DESCRIPTOR_POINTER1 0x2884
  852. #define ETHERNET1_FIRST_RX_DESCRIPTOR_POINTER2 0x2888
  853. #define ETHERNET1_FIRST_RX_DESCRIPTOR_POINTER3 0x288c
  854. #define ETHERNET1_CURRENT_RX_DESCRIPTOR_POINTER0 0x28a0
  855. #define ETHERNET1_CURRENT_RX_DESCRIPTOR_POINTER1 0x28a4
  856. #define ETHERNET1_CURRENT_RX_DESCRIPTOR_POINTER2 0x28a8
  857. #define ETHERNET1_CURRENT_RX_DESCRIPTOR_POINTER3 0x28ac
  858. #define ETHERNET1_CURRENT_TX_DESCRIPTOR_POINTER0 0x28e0
  859. #define ETHERNET1_CURRENT_TX_DESCRIPTOR_POINTER1 0x28e4
  860. #define ETHERNET1_MIB_COUNTER_BASE 0x2900
  861. /* Ethernet 2 */
  862. #define ETHERNET2_PORT_CONFIGURATION_REGISTER 0x2c00
  863. #define ETHERNET2_PORT_CONFIGURATION_EXTEND_REGISTER 0x2c08
  864. #define ETHERNET2_PORT_COMMAND_REGISTER 0x2c10
  865. #define ETHERNET2_PORT_STATUS_REGISTER 0x2c18
  866. #define ETHERNET2_SERIAL_PARAMETRS_REGISTER 0x2c20
  867. #define ETHERNET2_HASH_TABLE_POINTER_REGISTER 0x2c28
  868. #define ETHERNET2_FLOW_CONTROL_SOURCE_ADDRESS_LOW 0x2c30
  869. #define ETHERNET2_FLOW_CONTROL_SOURCE_ADDRESS_HIGH 0x2c38
  870. #define ETHERNET2_SDMA_CONFIGURATION_REGISTER 0x2c40
  871. #define ETHERNET2_SDMA_COMMAND_REGISTER 0x2c48
  872. #define ETHERNET2_INTERRUPT_CAUSE_REGISTER 0x2c50
  873. #define ETHERNET2_INTERRUPT_MASK_REGISTER 0x2c58
  874. #define ETHERNET2_FIRST_RX_DESCRIPTOR_POINTER0 0x2c80
  875. #define ETHERNET2_FIRST_RX_DESCRIPTOR_POINTER1 0x2c84
  876. #define ETHERNET2_FIRST_RX_DESCRIPTOR_POINTER2 0x2c88
  877. #define ETHERNET2_FIRST_RX_DESCRIPTOR_POINTER3 0x2c8c
  878. #define ETHERNET2_CURRENT_RX_DESCRIPTOR_POINTER0 0x2ca0
  879. #define ETHERNET2_CURRENT_RX_DESCRIPTOR_POINTER1 0x2ca4
  880. #define ETHERNET2_CURRENT_RX_DESCRIPTOR_POINTER2 0x2ca8
  881. #define ETHERNET2_CURRENT_RX_DESCRIPTOR_POINTER3 0x2cac
  882. #define ETHERNET2_CURRENT_TX_DESCRIPTOR_POINTER0 0x2ce0
  883. #define ETHERNET2_CURRENT_TX_DESCRIPTOR_POINTER1 0x2ce4
  884. #define ETHERNET2_MIB_COUNTER_BASE 0x2d00
  885. /****************************************/
  886. /* SDMA Registers */
  887. /****************************************/
  888. #define SDMA_GROUP_CONFIGURATION_REGISTER 0xb1f0
  889. #define CHANNEL0_CONFIGURATION_REGISTER 0x4000
  890. #define CHANNEL0_COMMAND_REGISTER 0x4008
  891. #define CHANNEL0_RX_CMD_STATUS 0x4800
  892. #define CHANNEL0_RX_PACKET_AND_BUFFER_SIZES 0x4804
  893. #define CHANNEL0_RX_BUFFER_POINTER 0x4808
  894. #define CHANNEL0_RX_NEXT_POINTER 0x480c
  895. #define CHANNEL0_CURRENT_RX_DESCRIPTOR_POINTER 0x4810
  896. #define CHANNEL0_TX_CMD_STATUS 0x4C00
  897. #define CHANNEL0_TX_PACKET_SIZE 0x4C04
  898. #define CHANNEL0_TX_BUFFER_POINTER 0x4C08
  899. #define CHANNEL0_TX_NEXT_POINTER 0x4C0c
  900. #define CHANNEL0_CURRENT_TX_DESCRIPTOR_POINTER 0x4c10
  901. #define CHANNEL0_FIRST_TX_DESCRIPTOR_POINTER 0x4c14
  902. #define CHANNEL1_CONFIGURATION_REGISTER 0x5000
  903. #define CHANNEL1_COMMAND_REGISTER 0x5008
  904. #define CHANNEL1_RX_CMD_STATUS 0x5800
  905. #define CHANNEL1_RX_PACKET_AND_BUFFER_SIZES 0x5804
  906. #define CHANNEL1_RX_BUFFER_POINTER 0x5808
  907. #define CHANNEL1_RX_NEXT_POINTER 0x580c
  908. #define CHANNEL1_TX_CMD_STATUS 0x5C00
  909. #define CHANNEL1_TX_PACKET_SIZE 0x5C04
  910. #define CHANNEL1_TX_BUFFER_POINTER 0x5C08
  911. #define CHANNEL1_TX_NEXT_POINTER 0x5C0c
  912. #define CHANNEL1_CURRENT_RX_DESCRIPTOR_POINTER 0x5810
  913. #define CHANNEL1_CURRENT_TX_DESCRIPTOR_POINTER 0x5c10
  914. #define CHANNEL1_FIRST_TX_DESCRIPTOR_POINTER 0x5c14
  915. #define CHANNEL2_CONFIGURATION_REGISTER 0x6000
  916. #define CHANNEL2_COMMAND_REGISTER 0x6008
  917. #define CHANNEL2_RX_CMD_STATUS 0x6800
  918. #define CHANNEL2_RX_PACKET_AND_BUFFER_SIZES 0x6804
  919. #define CHANNEL2_RX_BUFFER_POINTER 0x6808
  920. #define CHANNEL2_RX_NEXT_POINTER 0x680c
  921. #define CHANNEL2_CURRENT_RX_DESCRIPTOR_POINTER 0x6810
  922. #define CHANNEL2_TX_CMD_STATUS 0x6C00
  923. #define CHANNEL2_TX_PACKET_SIZE 0x6C04
  924. #define CHANNEL2_TX_BUFFER_POINTER 0x6C08
  925. #define CHANNEL2_TX_NEXT_POINTER 0x6C0c
  926. #define CHANNEL2_CURRENT_RX_DESCRIPTOR_POINTER 0x6810
  927. #define CHANNEL2_CURRENT_TX_DESCRIPTOR_POINTER 0x6c10
  928. #define CHANNEL2_FIRST_TX_DESCRIPTOR_POINTER 0x6c14
  929. /* SDMA Interrupt */
  930. #define SDMA_CAUSE 0xb820
  931. #define SDMA_MASK 0xb8a0
  932. /****************************************/
  933. /* Baude Rate Generators Registers */
  934. /****************************************/
  935. /* BRG 0 */
  936. #define BRG0_CONFIGURATION_REGISTER 0xb200
  937. #define BRG0_BAUDE_TUNING_REGISTER 0xb204
  938. /* BRG 1 */
  939. #define BRG1_CONFIGURATION_REGISTER 0xb208
  940. #define BRG1_BAUDE_TUNING_REGISTER 0xb20c
  941. /* BRG 2 */
  942. #define BRG2_CONFIGURATION_REGISTER 0xb210
  943. #define BRG2_BAUDE_TUNING_REGISTER 0xb214
  944. /* BRG Interrupts */
  945. #define BRG_CAUSE_REGISTER 0xb834
  946. #define BRG_MASK_REGISTER 0xb8b4
  947. /* MISC */
  948. #define MAIN_ROUTING_REGISTER 0xb400
  949. #define RECEIVE_CLOCK_ROUTING_REGISTER 0xb404
  950. #define TRANSMIT_CLOCK_ROUTING_REGISTER 0xb408
  951. #define COMM_UNIT_ARBITER_CONFIGURATION_REGISTER 0xb40c
  952. #define WATCHDOG_CONFIGURATION_REGISTER 0xb410
  953. #define WATCHDOG_VALUE_REGISTER 0xb414
  954. /****************************************/
  955. /* Flex TDM Registers */
  956. /****************************************/
  957. /* FTDM Port */
  958. #define FLEXTDM_TRANSMIT_READ_POINTER 0xa800
  959. #define FLEXTDM_RECEIVE_READ_POINTER 0xa804
  960. #define FLEXTDM_CONFIGURATION_REGISTER 0xa808
  961. #define FLEXTDM_AUX_CHANNELA_TX_REGISTER 0xa80c
  962. #define FLEXTDM_AUX_CHANNELA_RX_REGISTER 0xa810
  963. #define FLEXTDM_AUX_CHANNELB_TX_REGISTER 0xa814
  964. #define FLEXTDM_AUX_CHANNELB_RX_REGISTER 0xa818
  965. /* FTDM Interrupts */
  966. #define FTDM_CAUSE_REGISTER 0xb830
  967. #define FTDM_MASK_REGISTER 0xb8b0
  968. /****************************************/
  969. /* GPP Interface Registers */
  970. /****************************************/
  971. #define GPP_IO_CONTROL 0xf100
  972. #define GPP_LEVEL_CONTROL 0xf110
  973. #define GPP_VALUE 0xf104
  974. #define GPP_INTERRUPT_CAUSE 0xf108
  975. #define GPP_INTERRUPT_MASK 0xf10c
  976. #define MPP_CONTROL0 0xf000
  977. #define MPP_CONTROL1 0xf004
  978. #define MPP_CONTROL2 0xf008
  979. #define MPP_CONTROL3 0xf00c
  980. #define DEBUG_PORT_MULTIPLEX 0xf014
  981. #define SERIAL_PORT_MULTIPLEX 0xf010
  982. /****************************************/
  983. /* I2C Registers */
  984. /****************************************/
  985. #define I2C_SLAVE_ADDRESS 0xc000
  986. #define I2C_EXTENDED_SLAVE_ADDRESS 0xc040
  987. #define I2C_DATA 0xc004
  988. #define I2C_CONTROL 0xc008
  989. #define I2C_STATUS_BAUDE_RATE 0xc00C
  990. #define I2C_SOFT_RESET 0xc01c
  991. /****************************************/
  992. /* MPSC Registers */
  993. /****************************************/
  994. /* MPSC0 */
  995. #define MPSC0_MAIN_CONFIGURATION_LOW 0x8000
  996. #define MPSC0_MAIN_CONFIGURATION_HIGH 0x8004
  997. #define MPSC0_PROTOCOL_CONFIGURATION 0x8008
  998. #define CHANNEL0_REGISTER1 0x800c
  999. #define CHANNEL0_REGISTER2 0x8010
  1000. #define CHANNEL0_REGISTER3 0x8014
  1001. #define CHANNEL0_REGISTER4 0x8018
  1002. #define CHANNEL0_REGISTER5 0x801c
  1003. #define CHANNEL0_REGISTER6 0x8020
  1004. #define CHANNEL0_REGISTER7 0x8024
  1005. #define CHANNEL0_REGISTER8 0x8028
  1006. #define CHANNEL0_REGISTER9 0x802c
  1007. #define CHANNEL0_REGISTER10 0x8030
  1008. #define CHANNEL0_REGISTER11 0x8034
  1009. /* MPSC1 */
  1010. #define MPSC1_MAIN_CONFIGURATION_LOW 0x8840
  1011. #define MPSC1_MAIN_CONFIGURATION_HIGH 0x8844
  1012. #define MPSC1_PROTOCOL_CONFIGURATION 0x8848
  1013. #define CHANNEL1_REGISTER1 0x884c
  1014. #define CHANNEL1_REGISTER2 0x8850
  1015. #define CHANNEL1_REGISTER3 0x8854
  1016. #define CHANNEL1_REGISTER4 0x8858
  1017. #define CHANNEL1_REGISTER5 0x885c
  1018. #define CHANNEL1_REGISTER6 0x8860
  1019. #define CHANNEL1_REGISTER7 0x8864
  1020. #define CHANNEL1_REGISTER8 0x8868
  1021. #define CHANNEL1_REGISTER9 0x886c
  1022. #define CHANNEL1_REGISTER10 0x8870
  1023. #define CHANNEL1_REGISTER11 0x8874
  1024. /* MPSC2 */
  1025. #define MPSC2_MAIN_CONFIGURATION_LOW 0x9040
  1026. #define MPSC2_MAIN_CONFIGURATION_HIGH 0x9044
  1027. #define MPSC2_PROTOCOL_CONFIGURATION 0x9048
  1028. #define CHANNEL2_REGISTER1 0x904c
  1029. #define CHANNEL2_REGISTER2 0x9050
  1030. #define CHANNEL2_REGISTER3 0x9054
  1031. #define CHANNEL2_REGISTER4 0x9058
  1032. #define CHANNEL2_REGISTER5 0x905c
  1033. #define CHANNEL2_REGISTER6 0x9060
  1034. #define CHANNEL2_REGISTER7 0x9064
  1035. #define CHANNEL2_REGISTER8 0x9068
  1036. #define CHANNEL2_REGISTER9 0x906c
  1037. #define CHANNEL2_REGISTER10 0x9070
  1038. #define CHANNEL2_REGISTER11 0x9074
  1039. /* MPSCs Interrupts */
  1040. #define MPSC0_CAUSE 0xb824
  1041. #define MPSC0_MASK 0xb8a4
  1042. #define MPSC1_CAUSE 0xb828
  1043. #define MPSC1_MASK 0xb8a8
  1044. #define MPSC2_CAUSE 0xb82c
  1045. #define MPSC2_MASK 0xb8ac
  1046. #endif /* __INCgt64260rh */