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dubhe: Update GDB to support H and B extension

Added patch files for GDB to support RISC-V H and B extensions.

Signed-off-by: Jun Yuan Tan <junyuan.tan@starfivetech.com>
Jun Yuan Tan пре 2 година
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cb3238aefd
49 измењених фајлова са 59534 додато и 0 уклоњено
  1. 20092 0
      recipes-devtools/gdb/files/0001-Add-simulator-from-riscv-binutils-2.29-branch.patch
  2. 37 0
      recipes-devtools/gdb/files/0002-Make-the-riscv-sim-testsuite-work.patch
  3. 27 0
      recipes-devtools/gdb/files/0003-Fix-riscv-sim-build-on-Mac.-elf-bfd.h-now-requires-s.patch
  4. 1216 0
      recipes-devtools/gdb/files/0004-RISC-V-Minor-cleanup-and-testcases-improvement-for-a.patch
  5. 83 0
      recipes-devtools/gdb/files/0005-RISC-V-Don-t-allow-any-uppercase-letter-in-the-arch-.patch
  6. 195 0
      recipes-devtools/gdb/files/0006-RISC-V-Add-zifencei-and-prefixed-h-class-extensions.patch
  7. 42 0
      recipes-devtools/gdb/files/0007-RISC-V-Remove-the-unimplemented-extensions.patch
  8. 864 0
      recipes-devtools/gdb/files/0008-RISC-V-Improve-the-version-parsing-for-arch-string.patch
  9. 663 0
      recipes-devtools/gdb/files/0009-RISC-V-Support-to-add-implicit-extensions.patch
  10. 173 0
      recipes-devtools/gdb/files/0010-RISC-V-Support-to-add-implicit-extensions-for-G.patch
  11. 34 0
      recipes-devtools/gdb/files/0011-RISC-V-Fix-the-order-checking-for-Z-extension.patch
  12. 12772 0
      recipes-devtools/gdb/files/0012-RISC-V-Support-RVV-according-to-vector-spec-v1.0-dra.patch
  13. 132 0
      recipes-devtools/gdb/files/0013-Extend-the-VL-nf-R-and-VS-nf-R-instruction-when-nf-i.patch
  14. 212 0
      recipes-devtools/gdb/files/0014-Remove-Vector-indexed-instruction-when-EEW-128.patch
  15. 103 0
      recipes-devtools/gdb/files/0015-Add-assembly-pseudo-instructions-vncvt.x.x.v.patch
  16. 26 0
      recipes-devtools/gdb/files/0016-Update-the-vector-spec-version-tag-Version-1.0-draft.patch
  17. 134 0
      recipes-devtools/gdb/files/0017-Added-reciprocal-and-reciprocal-square-root-estimate.patch
  18. 377 0
      recipes-devtools/gdb/files/0018-Added-element-width-hint-to-whole-register-loads-sto.patch
  19. 26 0
      recipes-devtools/gdb/files/0019-Update-the-vector-spec-version-tag-Version-1.0-draft.patch
  20. 127 0
      recipes-devtools/gdb/files/0020-Added-vrgatherei16-instruction.patch
  21. 157 0
      recipes-devtools/gdb/files/0021-Make-vlmul-bits-contiguous-in-vtype.patch
  22. 70 0
      recipes-devtools/gdb/files/0022-RISC-V-Clarify-the-supported-versions-for-the-unrati.patch
  23. 41 0
      recipes-devtools/gdb/files/0023-RISC-V-Convert-CSR-dwarf-numbers-to-gdb-register-num.patch
  24. 7031 0
      recipes-devtools/gdb/files/0024-RISC-V-Update-the-vector-mask-constraints.patch
  25. 233 0
      recipes-devtools/gdb/files/0025-RISC-V-Add-the-missing-constraints-for-VL-nf-R-and-V.patch
  26. 117 0
      recipes-devtools/gdb/files/0026-RISC-V-Fix-the-constraints-for-vector-mask-and-compr.patch
  27. 3257 0
      recipes-devtools/gdb/files/0027-RISC-V-Report-rvv-assembler-constraint-errors-in-det.patch
  28. 550 0
      recipes-devtools/gdb/files/0028-RISC-V-Support-Zfh-standard-extension-for-half-preci.patch
  29. 97 0
      recipes-devtools/gdb/files/0029-RISC-V-Support-.float16-directive-for-assembler.patch
  30. 25 0
      recipes-devtools/gdb/files/0030-Set-default-version-of-ZFH-to-0.1.patch
  31. 166 0
      recipes-devtools/gdb/files/0031-RISC-V-Add-assembly-pseudoinstructions-vneg.v-and-vf.patch
  32. 5057 0
      recipes-devtools/gdb/files/0032-RISC-V-Added-ordered-unordered-vector-indexed-instru.patch
  33. 112 0
      recipes-devtools/gdb/files/0033-RISC-V-Rename-vncvt.x.x.v-to-vncvt.x.x.w.patch
  34. 120 0
      recipes-devtools/gdb/files/0034-SiFive-Support-SiFive-CLIC-CSRs.patch
  35. 105 0
      recipes-devtools/gdb/files/0035-SiFive-Support-SiFive-specific-cache-control-instruc.patch
  36. 995 0
      recipes-devtools/gdb/files/0036-Initial-support-for-RISC-V-Bitmanip-Spec-0.92.patch
  37. 70 0
      recipes-devtools/gdb/files/0037-RISC-V-Support-sub-extensions-of-B-for-march-parser.patch
  38. 130 0
      recipes-devtools/gdb/files/0038-RISC-V-Remove-ld-testcases-which-should-be-better-to.patch
  39. 152 0
      recipes-devtools/gdb/files/0039-RISC-V-Added-Removed-Updated-instructions-to-the-ris.patch
  40. 128 0
      recipes-devtools/gdb/files/0040-RISC-V-Add-missing-zext.-hw-pseudo-instructions.patch
  41. 552 0
      recipes-devtools/gdb/files/0041-RISC-V-Re-define-zba-zbb-zbc-and-zbs-extensions.patch
  42. 792 0
      recipes-devtools/gdb/files/0042-RISC-V-Define-pseudo-rev-orc-zip-unzip-as-alias-inst.patch
  43. 383 0
      recipes-devtools/gdb/files/0043-RISC-V-Add-testcases-for-ZBA-and-ZBB-instructions.patch
  44. 287 0
      recipes-devtools/gdb/files/0044-RISC-V-Add-sext.-bh-and-zext.-bhw-pseudo-instruction.patch
  45. 25 0
      recipes-devtools/gdb/files/0045-Fix-sim-build-since-op-match_func-have-more-argument.patch
  46. 163 0
      recipes-devtools/gdb/files/0046-SiFive-Add-RNMI-CSRs-and-MNRET-instruction.patch
  47. 1292 0
      recipes-devtools/gdb/files/0047-RISC-V-Freeze-ZBA-ZBB-ZBC-to-0.93.patch
  48. 28 0
      recipes-devtools/gdb/files/0048-fix-incorrect-shfli-and-unshfli-opcode.patch
  49. 64 0
      recipes-devtools/gdb/gdb_10.1.bbappend

+ 20092 - 0
recipes-devtools/gdb/files/0001-Add-simulator-from-riscv-binutils-2.29-branch.patch

@@ -0,0 +1,20092 @@
+From 7e15907dafac40b524dfeb566a06eb8290e38de6 Mon Sep 17 00:00:00 2001
+From: Jim Wilson <jimw@sifive.com>
+Date: Tue, 27 Nov 2018 12:22:33 -0800
+Subject: [PATCH 01/48] Add simulator from riscv-binutils-2.29 branch.
+
+---
+ gdb/configure.tgt                     |     1 +
+ include/gdb/sim-riscv.h               |    99 +
+ sim/common/nltvals.def                |    48 +
+ sim/configure                         |    22 +-
+ sim/configure.tgt                     |     3 +
+ sim/riscv/ChangeLog                   |    16 +
+ sim/riscv/Makefile.in                 |    35 +
+ sim/riscv/aclocal.m4                  |   119 +
+ sim/riscv/config.in                   |   248 +
+ sim/riscv/configure                   | 16131 ++++++++++++++++++++++++
+ sim/riscv/configure.ac                |    30 +
+ sim/riscv/interp.c                    |   220 +
+ sim/riscv/machs.c                     |   125 +
+ sim/riscv/machs.h                     |    45 +
+ sim/riscv/model_list.def              |     9 +
+ sim/riscv/sim-main.c                  |  2468 ++++
+ sim/riscv/sim-main.h                  |   100 +
+ sim/testsuite/configure               |    17 +-
+ sim/testsuite/sim/riscv/ChangeLog     |     3 +
+ sim/testsuite/sim/riscv/allinsn.exp   |    15 +
+ sim/testsuite/sim/riscv/pass.s        |     7 +
+ sim/testsuite/sim/riscv/testutils.inc |    50 +
+ 22 files changed, 19809 insertions(+), 2 deletions(-)
+ create mode 100644 include/gdb/sim-riscv.h
+ create mode 100644 sim/riscv/ChangeLog
+ create mode 100644 sim/riscv/Makefile.in
+ create mode 100644 sim/riscv/aclocal.m4
+ create mode 100644 sim/riscv/config.in
+ create mode 100755 sim/riscv/configure
+ create mode 100644 sim/riscv/configure.ac
+ create mode 100644 sim/riscv/interp.c
+ create mode 100644 sim/riscv/machs.c
+ create mode 100644 sim/riscv/machs.h
+ create mode 100644 sim/riscv/model_list.def
+ create mode 100644 sim/riscv/sim-main.c
+ create mode 100644 sim/riscv/sim-main.h
+ create mode 100644 sim/testsuite/sim/riscv/ChangeLog
+ create mode 100644 sim/testsuite/sim/riscv/allinsn.exp
+ create mode 100644 sim/testsuite/sim/riscv/pass.s
+ create mode 100644 sim/testsuite/sim/riscv/testutils.inc
+
+diff --git a/gdb/configure.tgt b/gdb/configure.tgt
+index a3e11c4b9b..2410253e61 100644
+--- a/gdb/configure.tgt
++++ b/gdb/configure.tgt
+@@ -553,6 +553,7 @@ riscv*-*-linux*)
+ riscv*-*-*)
+ 	# Target: RISC-V architecture
+ 	gdb_target_obs=""
++	gdb_sim=../sim/riscv/libsim.a
+ 	;;
+ 
+ rl78-*-elf)
+diff --git a/include/gdb/sim-riscv.h b/include/gdb/sim-riscv.h
+new file mode 100644
+index 0000000000..a554f34450
+--- /dev/null
++++ b/include/gdb/sim-riscv.h
+@@ -0,0 +1,99 @@
++/* This file defines the interface between the RISC-V simulator and GDB.
++
++   Copyright (C) 2005-2015 Free Software Foundation, Inc.
++
++   This file is part of GDB.
++
++   This program is free software; you can redistribute it and/or modify
++   it under the terms of the GNU General Public License as published by
++   the Free Software Foundation; either version 3 of the License, or
++   (at your option) any later version.
++
++   This program is distributed in the hope that it will be useful,
++   but WITHOUT ANY WARRANTY; without even the implied warranty of
++   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
++   GNU General Public License for more details.
++
++   You should have received a copy of the GNU General Public License
++   along with this program.  If not, see <http://www.gnu.org/licenses/>.  */
++
++/* Order has to match gdb riscv-tdep list.  */
++enum sim_riscv_regnum {
++  SIM_RISCV_ZERO_REGNUM = 0,
++  SIM_RISCV_RA_REGNUM,
++  SIM_RISCV_SP_REGNUM,
++  SIM_RISCV_GP_REGNUM,
++  SIM_RISCV_TP_REGNUM,
++  SIM_RISCV_T0_REGNUM,
++  SIM_RISCV_T1_REGNUM,
++  SIM_RISCV_T2_REGNUM,
++  SIM_RISCV_S0_REGNUM,
++#define SIM_RISCV_FP_REGNUM SIM_RISCV_S0_REGNUM
++  SIM_RISCV_S1_REGNUM,
++  SIM_RISCV_A0_REGNUM,
++  SIM_RISCV_A1_REGNUM,
++  SIM_RISCV_A2_REGNUM,
++  SIM_RISCV_A3_REGNUM,
++  SIM_RISCV_A4_REGNUM,
++  SIM_RISCV_A5_REGNUM,
++  SIM_RISCV_A6_REGNUM,
++  SIM_RISCV_A7_REGNUM,
++  SIM_RISCV_S2_REGNUM,
++  SIM_RISCV_S3_REGNUM,
++  SIM_RISCV_S4_REGNUM,
++  SIM_RISCV_S5_REGNUM,
++  SIM_RISCV_S6_REGNUM,
++  SIM_RISCV_S7_REGNUM,
++  SIM_RISCV_S8_REGNUM,
++  SIM_RISCV_S9_REGNUM,
++  SIM_RISCV_S10_REGNUM,
++  SIM_RISCV_S11_REGNUM,
++  SIM_RISCV_T3_REGNUM,
++  SIM_RISCV_T4_REGNUM,
++  SIM_RISCV_T5_REGNUM,
++  SIM_RISCV_T6_REGNUM,
++  SIM_RISCV_PC_REGNUM,
++  SIM_RISCV_FT0_REGNUM,
++#define SIM_RISCV_FIRST_FP_REGNUM SIM_RISCV_FT0_REGNUM
++  SIM_RISCV_FT1_REGNUM,
++  SIM_RISCV_FT2_REGNUM,
++  SIM_RISCV_FT3_REGNUM,
++  SIM_RISCV_FT4_REGNUM,
++  SIM_RISCV_FT5_REGNUM,
++  SIM_RISCV_FT6_REGNUM,
++  SIM_RISCV_FT7_REGNUM,
++  SIM_RISCV_FS0_REGNUM,
++  SIM_RISCV_FS1_REGNUM,
++  SIM_RISCV_FA0_REGNUM,
++  SIM_RISCV_FA1_REGNUM,
++  SIM_RISCV_FA2_REGNUM,
++  SIM_RISCV_FA3_REGNUM,
++  SIM_RISCV_FA4_REGNUM,
++  SIM_RISCV_FA5_REGNUM,
++  SIM_RISCV_FA6_REGNUM,
++  SIM_RISCV_FA7_REGNUM,
++  SIM_RISCV_FS2_REGNUM,
++  SIM_RISCV_FS3_REGNUM,
++  SIM_RISCV_FS4_REGNUM,
++  SIM_RISCV_FS5_REGNUM,
++  SIM_RISCV_FS6_REGNUM,
++  SIM_RISCV_FS7_REGNUM,
++  SIM_RISCV_FS8_REGNUM,
++  SIM_RISCV_FS9_REGNUM,
++  SIM_RISCV_FS10_REGNUM,
++  SIM_RISCV_FS11_REGNUM,
++  SIM_RISCV_FT8_REGNUM,
++  SIM_RISCV_FT9_REGNUM,
++  SIM_RISCV_FT10_REGNUM,
++  SIM_RISCV_FT11_REGNUM,
++#define SIM_RISCV_LAST_FP_REGNUM SIM_RISCV_FT11_REGNUM
++
++#define SIM_RISCV_FIRST_CSR_REGNUM SIM_RISCV_LAST_FP_REGNUM + 1
++#define DECLARE_CSR(name, num, class, def_ver, abort_ver) \
++  SIM_RISCV_ ## num ## _REGNUM,
++#include "opcode/riscv-opc.h"
++#undef DECLARE_CSR
++#define SIM_RISCV_LAST_CSR_REGNUM SIM_RISCV_LAST_REGNUM - 1
++
++  SIM_RISCV_LAST_REGNUM
++};
+diff --git a/sim/common/nltvals.def b/sim/common/nltvals.def
+index 92ccc9aded..60467f343d 100644
+--- a/sim/common/nltvals.def
++++ b/sim/common/nltvals.def
+@@ -605,3 +605,51 @@
+ /* end pru sys target macros */
+ #endif
+ #endif
++#ifdef NL_TARGET_riscv
++#ifdef sys_defs
++/* from syscall.h */
++/* begin riscv sys target macros */
++ { "SYS_access", 1033 },
++ { "SYS_brk", 214 },
++ { "SYS_chdir", 49 },
++ { "SYS_close", 57 },
++ { "SYS_dup", 23 },
++ { "SYS_exit", 93 },
++ { "SYS_exit_group", 94 },
++ { "SYS_faccessat", 48 },
++ { "SYS_fcntl", 25 },
++ { "SYS_fstat", 80 },
++ { "SYS_fstatat", 79 },
++ { "SYS_getcwd", 17 },
++ { "SYS_getdents", 61 },
++ { "SYS_getegid", 177 },
++ { "SYS_geteuid", 175 },
++ { "SYS_getgid", 176 },
++ { "SYS_getmainvars", 2011 },
++ { "SYS_getpid", 172 },
++ { "SYS_gettimeofday", 169 },
++ { "SYS_getuid", 174 },
++ { "SYS_kill", 129 },
++ { "SYS_link", 1025 },
++ { "SYS_lseek", 62 },
++ { "SYS_lstat", 1039 },
++ { "SYS_mkdir", 1030 },
++ { "SYS_mmap", 222 },
++ { "SYS_mremap", 216 },
++ { "SYS_munmap", 215 },
++ { "SYS_open", 1024 },
++ { "SYS_openat", 56 },
++ { "SYS_pread", 67 },
++ { "SYS_pwrite", 68 },
++ { "SYS_read", 63 },
++ { "SYS_rt_sigaction", 134 },
++ { "SYS_stat", 1038 },
++ { "SYS_time", 1062 },
++ { "SYS_times", 153 },
++ { "SYS_uname", 160 },
++ { "SYS_unlink", 1026 },
++ { "SYS_write", 64 },
++ { "SYS_writev", 66 },
++/* end riscv sys target macros */
++#endif
++#endif
+diff --git a/sim/configure b/sim/configure
+index 34f1a15a4c..7ff3b468b1 100755
+--- a/sim/configure
++++ b/sim/configure
+@@ -633,6 +633,7 @@ infodir
+ docdir
+ oldincludedir
+ includedir
++runstatedir
+ localstatedir
+ sharedstatedir
+ sysconfdir
+@@ -688,6 +689,7 @@ moxie
+ msp430
+ or1k
+ pru
++riscv
+ rl78
+ rx
+ sh64
+@@ -735,6 +737,7 @@ datadir='${datarootdir}'
+ sysconfdir='${prefix}/etc'
+ sharedstatedir='${prefix}/com'
+ localstatedir='${prefix}/var'
++runstatedir='${localstatedir}/run'
+ includedir='${prefix}/include'
+ oldincludedir='/usr/include'
+ docdir='${datarootdir}/doc/${PACKAGE}'
+@@ -987,6 +990,15 @@ do
+   | -silent | --silent | --silen | --sile | --sil)
+     silent=yes ;;
+ 
++  -runstatedir | --runstatedir | --runstatedi | --runstated \
++  | --runstate | --runstat | --runsta | --runst | --runs \
++  | --run | --ru | --r)
++    ac_prev=runstatedir ;;
++  -runstatedir=* | --runstatedir=* | --runstatedi=* | --runstated=* \
++  | --runstate=* | --runstat=* | --runsta=* | --runst=* | --runs=* \
++  | --run=* | --ru=* | --r=*)
++    runstatedir=$ac_optarg ;;
++
+   -sbindir | --sbindir | --sbindi | --sbind | --sbin | --sbi | --sb)
+     ac_prev=sbindir ;;
+   -sbindir=* | --sbindir=* | --sbindi=* | --sbind=* | --sbin=* \
+@@ -1124,7 +1136,7 @@ fi
+ for ac_var in	exec_prefix prefix bindir sbindir libexecdir datarootdir \
+ 		datadir sysconfdir sharedstatedir localstatedir includedir \
+ 		oldincludedir docdir infodir htmldir dvidir pdfdir psdir \
+-		libdir localedir mandir
++		libdir localedir mandir runstatedir
+ do
+   eval ac_val=\$$ac_var
+   # Remove trailing slashes.
+@@ -1277,6 +1289,7 @@ Fine tuning of the installation directories:
+   --sysconfdir=DIR        read-only single-machine data [PREFIX/etc]
+   --sharedstatedir=DIR    modifiable architecture-independent data [PREFIX/com]
+   --localstatedir=DIR     modifiable single-machine data [PREFIX/var]
++  --runstatedir=DIR       modifiable per-process data [LOCALSTATEDIR/run]
+   --libdir=DIR            object code libraries [EPREFIX/lib]
+   --includedir=DIR        C header files [PREFIX/include]
+   --oldincludedir=DIR     C header files for non-gcc [/usr/include]
+@@ -3853,6 +3866,13 @@ subdirs="$subdirs aarch64"
+   subdirs="$subdirs pru"
+ 
+ 
++       ;;
++   riscv*-*-*)
++
++  sim_arch=riscv
++  subdirs="$subdirs riscv"
++
++
+        ;;
+    rl78-*-*)
+ 
+diff --git a/sim/configure.tgt b/sim/configure.tgt
+index c115c3c8dd..54a6342733 100644
+--- a/sim/configure.tgt
++++ b/sim/configure.tgt
+@@ -85,6 +85,9 @@ case "${target}" in
+    pru*-*-*)
+        SIM_ARCH(pru)
+        ;;
++   riscv*-*-*)
++       SIM_ARCH(riscv)
++       ;;
+    rl78-*-*)
+        SIM_ARCH(rl78)
+        ;;
+diff --git a/sim/riscv/ChangeLog b/sim/riscv/ChangeLog
+new file mode 100644
+index 0000000000..8ab02a7a06
+--- /dev/null
++++ b/sim/riscv/ChangeLog
+@@ -0,0 +1,16 @@
++2018-11-26  Jim Wilson  <jimw@sifive.com>
++
++	* sim-main.c (execute_a): Check xlen_requirement not subset.
++	(step_once): Likewise.
++	(execute_one): Check xlen_requirement against cpu instead of subset.
++	New local index.  Set to index of last non-zero char in subset.
++	Delete local subset.  Use op->subset[index] instead of subset.
++	Delete '3' and '6' support from switch.
++
++2015-04-27  Mike Frysinger  <vapier@gentoo.org>
++	    Kito Cheng, Kuan-Lin Chen, Monk Chiang, Palmer Dabbelt, Jim Wilson
++
++	* configure.ac, interp.c, Makefile.in, README, README-ISA,
++	sim-main.c, sim-main.h: New files for example simulator.
++	* aclocal.m4, config.in, configure: Regenerated.
++
+diff --git a/sim/riscv/Makefile.in b/sim/riscv/Makefile.in
+new file mode 100644
+index 0000000000..2902cf68c7
+--- /dev/null
++++ b/sim/riscv/Makefile.in
+@@ -0,0 +1,35 @@
++#    Makefile template for Configure for the example basic simulator.
++#    Copyright (C) 2005-2015 Free Software Foundation, Inc.
++#    Written by Mike Frysinger.
++# 
++# This program is free software; you can redistribute it and/or modify
++# it under the terms of the GNU General Public License as published by
++# the Free Software Foundation; either version 3 of the License, or
++# (at your option) any later version.
++# 
++# This program is distributed in the hope that it will be useful,
++# but WITHOUT ANY WARRANTY; without even the implied warranty of
++# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
++# GNU General Public License for more details.
++# 
++# You should have received a copy of the GNU General Public License
++# along with this program.  If not, see <http://www.gnu.org/licenses/>.
++
++# This selects the newlib/libgloss syscall definitions.
++NL_TARGET = -DNL_TARGET_riscv
++
++## COMMON_PRE_CONFIG_FRAG
++
++SIM_OBJS = \
++	$(SIM_NEW_COMMON_OBJS) \
++	sim-hload.o \
++	sim-model.o \
++	sim-reason.o \
++	sim-reg.o \
++	sim-resume.o \
++	sim-stop.o \
++	interp.o \
++	machs.o \
++	sim-main.o
++
++## COMMON_POST_CONFIG_FRAG
+diff --git a/sim/riscv/aclocal.m4 b/sim/riscv/aclocal.m4
+new file mode 100644
+index 0000000000..c81c155ac9
+--- /dev/null
++++ b/sim/riscv/aclocal.m4
+@@ -0,0 +1,119 @@
++# generated automatically by aclocal 1.14.1 -*- Autoconf -*-
++
++# Copyright (C) 1996-2013 Free Software Foundation, Inc.
++
++# This file is free software; the Free Software Foundation
++# gives unlimited permission to copy and/or distribute it,
++# with or without modifications, as long as this notice is preserved.
++
++# This program is distributed in the hope that it will be useful,
++# but WITHOUT ANY WARRANTY, to the extent permitted by law; without
++# even the implied warranty of MERCHANTABILITY or FITNESS FOR A
++# PARTICULAR PURPOSE.
++
++m4_ifndef([AC_CONFIG_MACRO_DIRS], [m4_defun([_AM_CONFIG_MACRO_DIRS], [])m4_defun([AC_CONFIG_MACRO_DIRS], [_AM_CONFIG_MACRO_DIRS($@)])])
++# AM_CONDITIONAL                                            -*- Autoconf -*-
++
++# Copyright (C) 1997-2013 Free Software Foundation, Inc.
++#
++# This file is free software; the Free Software Foundation
++# gives unlimited permission to copy and/or distribute it,
++# with or without modifications, as long as this notice is preserved.
++
++# AM_CONDITIONAL(NAME, SHELL-CONDITION)
++# -------------------------------------
++# Define a conditional.
++AC_DEFUN([AM_CONDITIONAL],
++[AC_PREREQ([2.52])dnl
++ m4_if([$1], [TRUE],  [AC_FATAL([$0: invalid condition: $1])],
++       [$1], [FALSE], [AC_FATAL([$0: invalid condition: $1])])dnl
++AC_SUBST([$1_TRUE])dnl
++AC_SUBST([$1_FALSE])dnl
++_AM_SUBST_NOTMAKE([$1_TRUE])dnl
++_AM_SUBST_NOTMAKE([$1_FALSE])dnl
++m4_define([_AM_COND_VALUE_$1], [$2])dnl
++if $2; then
++  $1_TRUE=
++  $1_FALSE='#'
++else
++  $1_TRUE='#'
++  $1_FALSE=
++fi
++AC_CONFIG_COMMANDS_PRE(
++[if test -z "${$1_TRUE}" && test -z "${$1_FALSE}"; then
++  AC_MSG_ERROR([[conditional "$1" was never defined.
++Usually this means the macro was only invoked conditionally.]])
++fi])])
++
++# Copyright (C) 2003-2013 Free Software Foundation, Inc.
++#
++# This file is free software; the Free Software Foundation
++# gives unlimited permission to copy and/or distribute it,
++# with or without modifications, as long as this notice is preserved.
++
++# Check whether the underlying file-system supports filenames
++# with a leading dot.  For instance MS-DOS doesn't.
++AC_DEFUN([AM_SET_LEADING_DOT],
++[rm -rf .tst 2>/dev/null
++mkdir .tst 2>/dev/null
++if test -d .tst; then
++  am__leading_dot=.
++else
++  am__leading_dot=_
++fi
++rmdir .tst 2>/dev/null
++AC_SUBST([am__leading_dot])])
++
++# Add --enable-maintainer-mode option to configure.         -*- Autoconf -*-
++# From Jim Meyering
++
++# Copyright (C) 1996-2013 Free Software Foundation, Inc.
++#
++# This file is free software; the Free Software Foundation
++# gives unlimited permission to copy and/or distribute it,
++# with or without modifications, as long as this notice is preserved.
++
++# AM_MAINTAINER_MODE([DEFAULT-MODE])
++# ----------------------------------
++# Control maintainer-specific portions of Makefiles.
++# Default is to disable them, unless 'enable' is passed literally.
++# For symmetry, 'disable' may be passed as well.  Anyway, the user
++# can override the default with the --enable/--disable switch.
++AC_DEFUN([AM_MAINTAINER_MODE],
++[m4_case(m4_default([$1], [disable]),
++       [enable], [m4_define([am_maintainer_other], [disable])],
++       [disable], [m4_define([am_maintainer_other], [enable])],
++       [m4_define([am_maintainer_other], [enable])
++        m4_warn([syntax], [unexpected argument to AM@&t@_MAINTAINER_MODE: $1])])
++AC_MSG_CHECKING([whether to enable maintainer-specific portions of Makefiles])
++  dnl maintainer-mode's default is 'disable' unless 'enable' is passed
++  AC_ARG_ENABLE([maintainer-mode],
++    [AS_HELP_STRING([--]am_maintainer_other[-maintainer-mode],
++      am_maintainer_other[ make rules and dependencies not useful
++      (and sometimes confusing) to the casual installer])],
++    [USE_MAINTAINER_MODE=$enableval],
++    [USE_MAINTAINER_MODE=]m4_if(am_maintainer_other, [enable], [no], [yes]))
++  AC_MSG_RESULT([$USE_MAINTAINER_MODE])
++  AM_CONDITIONAL([MAINTAINER_MODE], [test $USE_MAINTAINER_MODE = yes])
++  MAINT=$MAINTAINER_MODE_TRUE
++  AC_SUBST([MAINT])dnl
++]
++)
++
++# Copyright (C) 2006-2013 Free Software Foundation, Inc.
++#
++# This file is free software; the Free Software Foundation
++# gives unlimited permission to copy and/or distribute it,
++# with or without modifications, as long as this notice is preserved.
++
++# _AM_SUBST_NOTMAKE(VARIABLE)
++# ---------------------------
++# Prevent Automake from outputting VARIABLE = @VARIABLE@ in Makefile.in.
++# This macro is traced by Automake.
++AC_DEFUN([_AM_SUBST_NOTMAKE])
++
++# AM_SUBST_NOTMAKE(VARIABLE)
++# --------------------------
++# Public sister of _AM_SUBST_NOTMAKE.
++AC_DEFUN([AM_SUBST_NOTMAKE], [_AM_SUBST_NOTMAKE($@)])
++
+diff --git a/sim/riscv/config.in b/sim/riscv/config.in
+new file mode 100644
+index 0000000000..aa3e45ca4a
+--- /dev/null
++++ b/sim/riscv/config.in
+@@ -0,0 +1,248 @@
++/* config.in.  Generated from configure.ac by autoheader.  */
++
++/* Define if building universal (internal helper macro) */
++#undef AC_APPLE_UNIVERSAL_BUILD
++
++/* Sim debug setting */
++#undef DEBUG
++
++/* Define to 1 if translation of program messages to the user's native
++   language is requested. */
++#undef ENABLE_NLS
++
++/* Define to 1 if you have the <dlfcn.h> header file. */
++#undef HAVE_DLFCN_H
++
++/* Define to 1 if you have the <errno.h> header file. */
++#undef HAVE_ERRNO_H
++
++/* Define to 1 if you have the <fcntl.h> header file. */
++#undef HAVE_FCNTL_H
++
++/* Define to 1 if you have the <fpu_control.h> header file. */
++#undef HAVE_FPU_CONTROL_H
++
++/* Define to 1 if you have the `ftruncate' function. */
++#undef HAVE_FTRUNCATE
++
++/* Define to 1 if you have the `getrusage' function. */
++#undef HAVE_GETRUSAGE
++
++/* Define to 1 if you have the <inttypes.h> header file. */
++#undef HAVE_INTTYPES_H
++
++/* Define to 1 if you have the `nsl' library (-lnsl). */
++#undef HAVE_LIBNSL
++
++/* Define to 1 if you have the `socket' library (-lsocket). */
++#undef HAVE_LIBSOCKET
++
++/* Define to 1 if you have the `lstat' function. */
++#undef HAVE_LSTAT
++
++/* Define to 1 if you have the <memory.h> header file. */
++#undef HAVE_MEMORY_H
++
++/* Define to 1 if you have the `mmap' function. */
++#undef HAVE_MMAP
++
++/* Define to 1 if you have the `munmap' function. */
++#undef HAVE_MUNMAP
++
++/* Define to 1 if you have the `posix_fallocate' function. */
++#undef HAVE_POSIX_FALLOCATE
++
++/* Define to 1 if you have the `sigaction' function. */
++#undef HAVE_SIGACTION
++
++/* Define to 1 if the system has the type `socklen_t'. */
++#undef HAVE_SOCKLEN_T
++
++/* Define to 1 if you have the <stdint.h> header file. */
++#undef HAVE_STDINT_H
++
++/* Define to 1 if you have the <stdlib.h> header file. */
++#undef HAVE_STDLIB_H
++
++/* Define to 1 if you have the <strings.h> header file. */
++#undef HAVE_STRINGS_H
++
++/* Define to 1 if you have the <string.h> header file. */
++#undef HAVE_STRING_H
++
++/* Define to 1 if `struct stat' is a member of `st_atime'. */
++#undef HAVE_STRUCT_STAT_ST_ATIME
++
++/* Define to 1 if `struct stat' is a member of `st_blksize'. */
++#undef HAVE_STRUCT_STAT_ST_BLKSIZE
++
++/* Define to 1 if `struct stat' is a member of `st_blocks'. */
++#undef HAVE_STRUCT_STAT_ST_BLOCKS
++
++/* Define to 1 if `struct stat' is a member of `st_ctime'. */
++#undef HAVE_STRUCT_STAT_ST_CTIME
++
++/* Define to 1 if `struct stat' is a member of `st_dev'. */
++#undef HAVE_STRUCT_STAT_ST_DEV
++
++/* Define to 1 if `struct stat' is a member of `st_gid'. */
++#undef HAVE_STRUCT_STAT_ST_GID
++
++/* Define to 1 if `struct stat' is a member of `st_ino'. */
++#undef HAVE_STRUCT_STAT_ST_INO
++
++/* Define to 1 if `struct stat' is a member of `st_mode'. */
++#undef HAVE_STRUCT_STAT_ST_MODE
++
++/* Define to 1 if `struct stat' is a member of `st_mtime'. */
++#undef HAVE_STRUCT_STAT_ST_MTIME
++
++/* Define to 1 if `struct stat' is a member of `st_nlink'. */
++#undef HAVE_STRUCT_STAT_ST_NLINK
++
++/* Define to 1 if `struct stat' is a member of `st_rdev'. */
++#undef HAVE_STRUCT_STAT_ST_RDEV
++
++/* Define to 1 if `struct stat' is a member of `st_size'. */
++#undef HAVE_STRUCT_STAT_ST_SIZE
++
++/* Define to 1 if `struct stat' is a member of `st_uid'. */
++#undef HAVE_STRUCT_STAT_ST_UID
++
++/* Define to 1 if you have the <sys/mman.h> header file. */
++#undef HAVE_SYS_MMAN_H
++
++/* Define to 1 if you have the <sys/resource.h> header file. */
++#undef HAVE_SYS_RESOURCE_H
++
++/* Define to 1 if you have the <sys/stat.h> header file. */
++#undef HAVE_SYS_STAT_H
++
++/* Define to 1 if you have the <sys/times.h> header file. */
++#undef HAVE_SYS_TIMES_H
++
++/* Define to 1 if you have the <sys/time.h> header file. */
++#undef HAVE_SYS_TIME_H
++
++/* Define to 1 if you have the <sys/types.h> header file. */
++#undef HAVE_SYS_TYPES_H
++
++/* Define to 1 if you have the `time' function. */
++#undef HAVE_TIME
++
++/* Define to 1 if you have the <time.h> header file. */
++#undef HAVE_TIME_H
++
++/* Define to 1 if you have the `truncate' function. */
++#undef HAVE_TRUNCATE
++
++/* Define to 1 if you have the <unistd.h> header file. */
++#undef HAVE_UNISTD_H
++
++/* Define to 1 if you have the <windows.h> header file. */
++#undef HAVE_WINDOWS_H
++
++/* Define to 1 if you have the `__setfpucw' function. */
++#undef HAVE___SETFPUCW
++
++/* Define to the sub-directory in which libtool stores uninstalled libraries.
++   */
++#undef LT_OBJDIR
++
++/* Name of this package. */
++#undef PACKAGE
++
++/* Define to the address where bug reports for this package should be sent. */
++#undef PACKAGE_BUGREPORT
++
++/* Define to the full name of this package. */
++#undef PACKAGE_NAME
++
++/* Define to the full name and version of this package. */
++#undef PACKAGE_STRING
++
++/* Define to the one symbol short name of this package. */
++#undef PACKAGE_TARNAME
++
++/* Define to the home page for this package. */
++#undef PACKAGE_URL
++
++/* Define to the version of this package. */
++#undef PACKAGE_VERSION
++
++/* Additional package description */
++#undef PKGVERSION
++
++/* Sim profile settings */
++#undef PROFILE
++
++/* Bug reporting address */
++#undef REPORT_BUGS_TO
++
++/* Define as the return type of signal handlers (`int' or `void'). */
++#undef RETSIGTYPE
++
++/* Define to 1 if you have the ANSI C header files. */
++#undef STDC_HEADERS
++
++/* Enable extensions on AIX 3, Interix.  */
++#ifndef _ALL_SOURCE
++# undef _ALL_SOURCE
++#endif
++/* Enable GNU extensions on systems that have them.  */
++#ifndef _GNU_SOURCE
++# undef _GNU_SOURCE
++#endif
++/* Enable threading extensions on Solaris.  */
++#ifndef _POSIX_PTHREAD_SEMANTICS
++# undef _POSIX_PTHREAD_SEMANTICS
++#endif
++/* Enable extensions on HP NonStop.  */
++#ifndef _TANDEM_SOURCE
++# undef _TANDEM_SOURCE
++#endif
++/* Enable general extensions on Solaris.  */
++#ifndef __EXTENSIONS__
++# undef __EXTENSIONS__
++#endif
++
++
++/* Sim assert settings */
++#undef WITH_ASSERT
++
++/* Sim debug setting */
++#undef WITH_DEBUG
++
++/* Sim default environment */
++#undef WITH_ENVIRONMENT
++
++/* Sim profile settings */
++#undef WITH_PROFILE
++
++/* How to route I/O */
++#undef WITH_STDIO
++
++/* Sim trace settings */
++#undef WITH_TRACE
++
++/* Define WORDS_BIGENDIAN to 1 if your processor stores words with the most
++   significant byte first (like Motorola and SPARC, unlike Intel). */
++#if defined AC_APPLE_UNIVERSAL_BUILD
++# if defined __BIG_ENDIAN__
++#  define WORDS_BIGENDIAN 1
++# endif
++#else
++# ifndef WORDS_BIGENDIAN
++#  undef WORDS_BIGENDIAN
++# endif
++#endif
++
++/* Define to 1 if on MINIX. */
++#undef _MINIX
++
++/* Define to 2 if the system does not provide POSIX.1 features except with
++   this defined. */
++#undef _POSIX_1_SOURCE
++
++/* Define to 1 if you need to in order for `stat' and other things to work. */
++#undef _POSIX_SOURCE
+diff --git a/sim/riscv/configure b/sim/riscv/configure
+new file mode 100755
+index 0000000000..4c53d6b576
+--- /dev/null
++++ b/sim/riscv/configure
+@@ -0,0 +1,16131 @@
++#! /bin/sh
++# Guess values for system-dependent variables and create Makefiles.
++# Generated by GNU Autoconf 2.69.
++#
++#
++# Copyright (C) 1992-1996, 1998-2012 Free Software Foundation, Inc.
++#
++#
++# This configure script is free software; the Free Software Foundation
++# gives unlimited permission to copy, distribute and modify it.
++## -------------------- ##
++## M4sh Initialization. ##
++## -------------------- ##
++
++# Be more Bourne compatible
++DUALCASE=1; export DUALCASE # for MKS sh
++if test -n "${ZSH_VERSION+set}" && (emulate sh) >/dev/null 2>&1; then :
++  emulate sh
++  NULLCMD=:
++  # Pre-4.2 versions of Zsh do word splitting on ${1+"$@"}, which
++  # is contrary to our usage.  Disable this feature.
++  alias -g '${1+"$@"}'='"$@"'
++  setopt NO_GLOB_SUBST
++else
++  case `(set -o) 2>/dev/null` in #(
++  *posix*) :
++    set -o posix ;; #(
++  *) :
++     ;;
++esac
++fi
++
++
++as_nl='
++'
++export as_nl
++# Printing a long string crashes Solaris 7 /usr/bin/printf.
++as_echo='\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\'
++as_echo=$as_echo$as_echo$as_echo$as_echo$as_echo
++as_echo=$as_echo$as_echo$as_echo$as_echo$as_echo$as_echo
++# Prefer a ksh shell builtin over an external printf program on Solaris,
++# but without wasting forks for bash or zsh.
++if test -z "$BASH_VERSION$ZSH_VERSION" \
++    && (test "X`print -r -- $as_echo`" = "X$as_echo") 2>/dev/null; then
++  as_echo='print -r --'
++  as_echo_n='print -rn --'
++elif (test "X`printf %s $as_echo`" = "X$as_echo") 2>/dev/null; then
++  as_echo='printf %s\n'
++  as_echo_n='printf %s'
++else
++  if test "X`(/usr/ucb/echo -n -n $as_echo) 2>/dev/null`" = "X-n $as_echo"; then
++    as_echo_body='eval /usr/ucb/echo -n "$1$as_nl"'
++    as_echo_n='/usr/ucb/echo -n'
++  else
++    as_echo_body='eval expr "X$1" : "X\\(.*\\)"'
++    as_echo_n_body='eval
++      arg=$1;
++      case $arg in #(
++      *"$as_nl"*)
++	expr "X$arg" : "X\\(.*\\)$as_nl";
++	arg=`expr "X$arg" : ".*$as_nl\\(.*\\)"`;;
++      esac;
++      expr "X$arg" : "X\\(.*\\)" | tr -d "$as_nl"
++    '
++    export as_echo_n_body
++    as_echo_n='sh -c $as_echo_n_body as_echo'
++  fi
++  export as_echo_body
++  as_echo='sh -c $as_echo_body as_echo'
++fi
++
++# The user is always right.
++if test "${PATH_SEPARATOR+set}" != set; then
++  PATH_SEPARATOR=:
++  (PATH='/bin;/bin'; FPATH=$PATH; sh -c :) >/dev/null 2>&1 && {
++    (PATH='/bin:/bin'; FPATH=$PATH; sh -c :) >/dev/null 2>&1 ||
++      PATH_SEPARATOR=';'
++  }
++fi
++
++
++# IFS
++# We need space, tab and new line, in precisely that order.  Quoting is
++# there to prevent editors from complaining about space-tab.
++# (If _AS_PATH_WALK were called with IFS unset, it would disable word
++# splitting by setting IFS to empty value.)
++IFS=" ""	$as_nl"
++
++# Find who we are.  Look in the path if we contain no directory separator.
++as_myself=
++case $0 in #((
++  *[\\/]* ) as_myself=$0 ;;
++  *) as_save_IFS=$IFS; IFS=$PATH_SEPARATOR
++for as_dir in $PATH
++do
++  IFS=$as_save_IFS
++  test -z "$as_dir" && as_dir=.
++    test -r "$as_dir/$0" && as_myself=$as_dir/$0 && break
++  done
++IFS=$as_save_IFS
++
++     ;;
++esac
++# We did not find ourselves, most probably we were run as `sh COMMAND'
++# in which case we are not to be found in the path.
++if test "x$as_myself" = x; then
++  as_myself=$0
++fi
++if test ! -f "$as_myself"; then
++  $as_echo "$as_myself: error: cannot find myself; rerun with an absolute file name" >&2
++  exit 1
++fi
++
++# Unset variables that we do not need and which cause bugs (e.g. in
++# pre-3.0 UWIN ksh).  But do not cause bugs in bash 2.01; the "|| exit 1"
++# suppresses any "Segmentation fault" message there.  '((' could
++# trigger a bug in pdksh 5.2.14.
++for as_var in BASH_ENV ENV MAIL MAILPATH
++do eval test x\${$as_var+set} = xset \
++  && ( (unset $as_var) || exit 1) >/dev/null 2>&1 && unset $as_var || :
++done
++PS1='$ '
++PS2='> '
++PS4='+ '
++
++# NLS nuisances.
++LC_ALL=C
++export LC_ALL
++LANGUAGE=C
++export LANGUAGE
++
++# CDPATH.
++(unset CDPATH) >/dev/null 2>&1 && unset CDPATH
++
++# Use a proper internal environment variable to ensure we don't fall
++  # into an infinite loop, continuously re-executing ourselves.
++  if test x"${_as_can_reexec}" != xno && test "x$CONFIG_SHELL" != x; then
++    _as_can_reexec=no; export _as_can_reexec;
++    # We cannot yet assume a decent shell, so we have to provide a
++# neutralization value for shells without unset; and this also
++# works around shells that cannot unset nonexistent variables.
++# Preserve -v and -x to the replacement shell.
++BASH_ENV=/dev/null
++ENV=/dev/null
++(unset BASH_ENV) >/dev/null 2>&1 && unset BASH_ENV ENV
++case $- in # ((((
++  *v*x* | *x*v* ) as_opts=-vx ;;
++  *v* ) as_opts=-v ;;
++  *x* ) as_opts=-x ;;
++  * ) as_opts= ;;
++esac
++exec $CONFIG_SHELL $as_opts "$as_myself" ${1+"$@"}
++# Admittedly, this is quite paranoid, since all the known shells bail
++# out after a failed `exec'.
++$as_echo "$0: could not re-execute with $CONFIG_SHELL" >&2
++as_fn_exit 255
++  fi
++  # We don't want this to propagate to other subprocesses.
++          { _as_can_reexec=; unset _as_can_reexec;}
++if test "x$CONFIG_SHELL" = x; then
++  as_bourne_compatible="if test -n \"\${ZSH_VERSION+set}\" && (emulate sh) >/dev/null 2>&1; then :
++  emulate sh
++  NULLCMD=:
++  # Pre-4.2 versions of Zsh do word splitting on \${1+\"\$@\"}, which
++  # is contrary to our usage.  Disable this feature.
++  alias -g '\${1+\"\$@\"}'='\"\$@\"'
++  setopt NO_GLOB_SUBST
++else
++  case \`(set -o) 2>/dev/null\` in #(
++  *posix*) :
++    set -o posix ;; #(
++  *) :
++     ;;
++esac
++fi
++"
++  as_required="as_fn_return () { (exit \$1); }
++as_fn_success () { as_fn_return 0; }
++as_fn_failure () { as_fn_return 1; }
++as_fn_ret_success () { return 0; }
++as_fn_ret_failure () { return 1; }
++
++exitcode=0
++as_fn_success || { exitcode=1; echo as_fn_success failed.; }
++as_fn_failure && { exitcode=1; echo as_fn_failure succeeded.; }
++as_fn_ret_success || { exitcode=1; echo as_fn_ret_success failed.; }
++as_fn_ret_failure && { exitcode=1; echo as_fn_ret_failure succeeded.; }
++if ( set x; as_fn_ret_success y && test x = \"\$1\" ); then :
++
++else
++  exitcode=1; echo positional parameters were not saved.
++fi
++test x\$exitcode = x0 || exit 1
++test -x / || exit 1"
++  as_suggested="  as_lineno_1=";as_suggested=$as_suggested$LINENO;as_suggested=$as_suggested" as_lineno_1a=\$LINENO
++  as_lineno_2=";as_suggested=$as_suggested$LINENO;as_suggested=$as_suggested" as_lineno_2a=\$LINENO
++  eval 'test \"x\$as_lineno_1'\$as_run'\" != \"x\$as_lineno_2'\$as_run'\" &&
++  test \"x\`expr \$as_lineno_1'\$as_run' + 1\`\" = \"x\$as_lineno_2'\$as_run'\"' || exit 1
++test \$(( 1 + 1 )) = 2 || exit 1
++
++  test -n \"\${ZSH_VERSION+set}\${BASH_VERSION+set}\" || (
++    ECHO='\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\'
++    ECHO=\$ECHO\$ECHO\$ECHO\$ECHO\$ECHO
++    ECHO=\$ECHO\$ECHO\$ECHO\$ECHO\$ECHO\$ECHO
++    PATH=/empty FPATH=/empty; export PATH FPATH
++    test \"X\`printf %s \$ECHO\`\" = \"X\$ECHO\" \\
++      || test \"X\`print -r -- \$ECHO\`\" = \"X\$ECHO\" ) || exit 1"
++  if (eval "$as_required") 2>/dev/null; then :
++  as_have_required=yes
++else
++  as_have_required=no
++fi
++  if test x$as_have_required = xyes && (eval "$as_suggested") 2>/dev/null; then :
++
++else
++  as_save_IFS=$IFS; IFS=$PATH_SEPARATOR
++as_found=false
++for as_dir in /bin$PATH_SEPARATOR/usr/bin$PATH_SEPARATOR$PATH
++do
++  IFS=$as_save_IFS
++  test -z "$as_dir" && as_dir=.
++  as_found=:
++  case $as_dir in #(
++	 /*)
++	   for as_base in sh bash ksh sh5; do
++	     # Try only shells that exist, to save several forks.
++	     as_shell=$as_dir/$as_base
++	     if { test -f "$as_shell" || test -f "$as_shell.exe"; } &&
++		    { $as_echo "$as_bourne_compatible""$as_required" | as_run=a "$as_shell"; } 2>/dev/null; then :
++  CONFIG_SHELL=$as_shell as_have_required=yes
++		   if { $as_echo "$as_bourne_compatible""$as_suggested" | as_run=a "$as_shell"; } 2>/dev/null; then :
++  break 2
++fi
++fi
++	   done;;
++       esac
++  as_found=false
++done
++$as_found || { if { test -f "$SHELL" || test -f "$SHELL.exe"; } &&
++	      { $as_echo "$as_bourne_compatible""$as_required" | as_run=a "$SHELL"; } 2>/dev/null; then :
++  CONFIG_SHELL=$SHELL as_have_required=yes
++fi; }
++IFS=$as_save_IFS
++
++
++      if test "x$CONFIG_SHELL" != x; then :
++  export CONFIG_SHELL
++             # We cannot yet assume a decent shell, so we have to provide a
++# neutralization value for shells without unset; and this also
++# works around shells that cannot unset nonexistent variables.
++# Preserve -v and -x to the replacement shell.
++BASH_ENV=/dev/null
++ENV=/dev/null
++(unset BASH_ENV) >/dev/null 2>&1 && unset BASH_ENV ENV
++case $- in # ((((
++  *v*x* | *x*v* ) as_opts=-vx ;;
++  *v* ) as_opts=-v ;;
++  *x* ) as_opts=-x ;;
++  * ) as_opts= ;;
++esac
++exec $CONFIG_SHELL $as_opts "$as_myself" ${1+"$@"}
++# Admittedly, this is quite paranoid, since all the known shells bail
++# out after a failed `exec'.
++$as_echo "$0: could not re-execute with $CONFIG_SHELL" >&2
++exit 255
++fi
++
++    if test x$as_have_required = xno; then :
++  $as_echo "$0: This script requires a shell more modern than all"
++  $as_echo "$0: the shells that I found on your system."
++  if test x${ZSH_VERSION+set} = xset ; then
++    $as_echo "$0: In particular, zsh $ZSH_VERSION has bugs and should"
++    $as_echo "$0: be upgraded to zsh 4.3.4 or later."
++  else
++    $as_echo "$0: Please tell bug-autoconf@gnu.org about your system,
++$0: including any error possibly output before this
++$0: message. Then install a modern shell, or manually run
++$0: the script under such a shell if you do have one."
++  fi
++  exit 1
++fi
++fi
++fi
++SHELL=${CONFIG_SHELL-/bin/sh}
++export SHELL
++# Unset more variables known to interfere with behavior of common tools.
++CLICOLOR_FORCE= GREP_OPTIONS=
++unset CLICOLOR_FORCE GREP_OPTIONS
++
++## --------------------- ##
++## M4sh Shell Functions. ##
++## --------------------- ##
++# as_fn_unset VAR
++# ---------------
++# Portably unset VAR.
++as_fn_unset ()
++{
++  { eval $1=; unset $1;}
++}
++as_unset=as_fn_unset
++
++# as_fn_set_status STATUS
++# -----------------------
++# Set $? to STATUS, without forking.
++as_fn_set_status ()
++{
++  return $1
++} # as_fn_set_status
++
++# as_fn_exit STATUS
++# -----------------
++# Exit the shell with STATUS, even in a "trap 0" or "set -e" context.
++as_fn_exit ()
++{
++  set +e
++  as_fn_set_status $1
++  exit $1
++} # as_fn_exit
++
++# as_fn_mkdir_p
++# -------------
++# Create "$as_dir" as a directory, including parents if necessary.
++as_fn_mkdir_p ()
++{
++
++  case $as_dir in #(
++  -*) as_dir=./$as_dir;;
++  esac
++  test -d "$as_dir" || eval $as_mkdir_p || {
++    as_dirs=
++    while :; do
++      case $as_dir in #(
++      *\'*) as_qdir=`$as_echo "$as_dir" | sed "s/'/'\\\\\\\\''/g"`;; #'(
++      *) as_qdir=$as_dir;;
++      esac
++      as_dirs="'$as_qdir' $as_dirs"
++      as_dir=`$as_dirname -- "$as_dir" ||
++$as_expr X"$as_dir" : 'X\(.*[^/]\)//*[^/][^/]*/*$' \| \
++	 X"$as_dir" : 'X\(//\)[^/]' \| \
++	 X"$as_dir" : 'X\(//\)$' \| \
++	 X"$as_dir" : 'X\(/\)' \| . 2>/dev/null ||
++$as_echo X"$as_dir" |
++    sed '/^X\(.*[^/]\)\/\/*[^/][^/]*\/*$/{
++	    s//\1/
++	    q
++	  }
++	  /^X\(\/\/\)[^/].*/{
++	    s//\1/
++	    q
++	  }
++	  /^X\(\/\/\)$/{
++	    s//\1/
++	    q
++	  }
++	  /^X\(\/\).*/{
++	    s//\1/
++	    q
++	  }
++	  s/.*/./; q'`
++      test -d "$as_dir" && break
++    done
++    test -z "$as_dirs" || eval "mkdir $as_dirs"
++  } || test -d "$as_dir" || as_fn_error $? "cannot create directory $as_dir"
++
++
++} # as_fn_mkdir_p
++
++# as_fn_executable_p FILE
++# -----------------------
++# Test if FILE is an executable regular file.
++as_fn_executable_p ()
++{
++  test -f "$1" && test -x "$1"
++} # as_fn_executable_p
++# as_fn_append VAR VALUE
++# ----------------------
++# Append the text in VALUE to the end of the definition contained in VAR. Take
++# advantage of any shell optimizations that allow amortized linear growth over
++# repeated appends, instead of the typical quadratic growth present in naive
++# implementations.
++if (eval "as_var=1; as_var+=2; test x\$as_var = x12") 2>/dev/null; then :
++  eval 'as_fn_append ()
++  {
++    eval $1+=\$2
++  }'
++else
++  as_fn_append ()
++  {
++    eval $1=\$$1\$2
++  }
++fi # as_fn_append
++
++# as_fn_arith ARG...
++# ------------------
++# Perform arithmetic evaluation on the ARGs, and store the result in the
++# global $as_val. Take advantage of shells that can avoid forks. The arguments
++# must be portable across $(()) and expr.
++if (eval "test \$(( 1 + 1 )) = 2") 2>/dev/null; then :
++  eval 'as_fn_arith ()
++  {
++    as_val=$(( $* ))
++  }'
++else
++  as_fn_arith ()
++  {
++    as_val=`expr "$@" || test $? -eq 1`
++  }
++fi # as_fn_arith
++
++
++# as_fn_error STATUS ERROR [LINENO LOG_FD]
++# ----------------------------------------
++# Output "`basename $0`: error: ERROR" to stderr. If LINENO and LOG_FD are
++# provided, also output the error to LOG_FD, referencing LINENO. Then exit the
++# script with STATUS, using 1 if that was 0.
++as_fn_error ()
++{
++  as_status=$1; test $as_status -eq 0 && as_status=1
++  if test "$4"; then
++    as_lineno=${as_lineno-"$3"} as_lineno_stack=as_lineno_stack=$as_lineno_stack
++    $as_echo "$as_me:${as_lineno-$LINENO}: error: $2" >&$4
++  fi
++  $as_echo "$as_me: error: $2" >&2
++  as_fn_exit $as_status
++} # as_fn_error
++
++if expr a : '\(a\)' >/dev/null 2>&1 &&
++   test "X`expr 00001 : '.*\(...\)'`" = X001; then
++  as_expr=expr
++else
++  as_expr=false
++fi
++
++if (basename -- /) >/dev/null 2>&1 && test "X`basename -- / 2>&1`" = "X/"; then
++  as_basename=basename
++else
++  as_basename=false
++fi
++
++if (as_dir=`dirname -- /` && test "X$as_dir" = X/) >/dev/null 2>&1; then
++  as_dirname=dirname
++else
++  as_dirname=false
++fi
++
++as_me=`$as_basename -- "$0" ||
++$as_expr X/"$0" : '.*/\([^/][^/]*\)/*$' \| \
++	 X"$0" : 'X\(//\)$' \| \
++	 X"$0" : 'X\(/\)' \| . 2>/dev/null ||
++$as_echo X/"$0" |
++    sed '/^.*\/\([^/][^/]*\)\/*$/{
++	    s//\1/
++	    q
++	  }
++	  /^X\/\(\/\/\)$/{
++	    s//\1/
++	    q
++	  }
++	  /^X\/\(\/\).*/{
++	    s//\1/
++	    q
++	  }
++	  s/.*/./; q'`
++
++# Avoid depending upon Character Ranges.
++as_cr_letters='abcdefghijklmnopqrstuvwxyz'
++as_cr_LETTERS='ABCDEFGHIJKLMNOPQRSTUVWXYZ'
++as_cr_Letters=$as_cr_letters$as_cr_LETTERS
++as_cr_digits='0123456789'
++as_cr_alnum=$as_cr_Letters$as_cr_digits
++
++
++  as_lineno_1=$LINENO as_lineno_1a=$LINENO
++  as_lineno_2=$LINENO as_lineno_2a=$LINENO
++  eval 'test "x$as_lineno_1'$as_run'" != "x$as_lineno_2'$as_run'" &&
++  test "x`expr $as_lineno_1'$as_run' + 1`" = "x$as_lineno_2'$as_run'"' || {
++  # Blame Lee E. McMahon (1931-1989) for sed's syntax.  :-)
++  sed -n '
++    p
++    /[$]LINENO/=
++  ' <$as_myself |
++    sed '
++      s/[$]LINENO.*/&-/
++      t lineno
++      b
++      :lineno
++      N
++      :loop
++      s/[$]LINENO\([^'$as_cr_alnum'_].*\n\)\(.*\)/\2\1\2/
++      t loop
++      s/-\n.*//
++    ' >$as_me.lineno &&
++  chmod +x "$as_me.lineno" ||
++    { $as_echo "$as_me: error: cannot create $as_me.lineno; rerun with a POSIX shell" >&2; as_fn_exit 1; }
++
++  # If we had to re-execute with $CONFIG_SHELL, we're ensured to have
++  # already done that, so ensure we don't try to do so again and fall
++  # in an infinite loop.  This has already happened in practice.
++  _as_can_reexec=no; export _as_can_reexec
++  # Don't try to exec as it changes $[0], causing all sort of problems
++  # (the dirname of $[0] is not the place where we might find the
++  # original and so on.  Autoconf is especially sensitive to this).
++  . "./$as_me.lineno"
++  # Exit status is that of the last command.
++  exit
++}
++
++ECHO_C= ECHO_N= ECHO_T=
++case `echo -n x` in #(((((
++-n*)
++  case `echo 'xy\c'` in
++  *c*) ECHO_T='	';;	# ECHO_T is single tab character.
++  xy)  ECHO_C='\c';;
++  *)   echo `echo ksh88 bug on AIX 6.1` > /dev/null
++       ECHO_T='	';;
++  esac;;
++*)
++  ECHO_N='-n';;
++esac
++
++rm -f conf$$ conf$$.exe conf$$.file
++if test -d conf$$.dir; then
++  rm -f conf$$.dir/conf$$.file
++else
++  rm -f conf$$.dir
++  mkdir conf$$.dir 2>/dev/null
++fi
++if (echo >conf$$.file) 2>/dev/null; then
++  if ln -s conf$$.file conf$$ 2>/dev/null; then
++    as_ln_s='ln -s'
++    # ... but there are two gotchas:
++    # 1) On MSYS, both `ln -s file dir' and `ln file dir' fail.
++    # 2) DJGPP < 2.04 has no symlinks; `ln -s' creates a wrapper executable.
++    # In both cases, we have to default to `cp -pR'.
++    ln -s conf$$.file conf$$.dir 2>/dev/null && test ! -f conf$$.exe ||
++      as_ln_s='cp -pR'
++  elif ln conf$$.file conf$$ 2>/dev/null; then
++    as_ln_s=ln
++  else
++    as_ln_s='cp -pR'
++  fi
++else
++  as_ln_s='cp -pR'
++fi
++rm -f conf$$ conf$$.exe conf$$.dir/conf$$.file conf$$.file
++rmdir conf$$.dir 2>/dev/null
++
++if mkdir -p . 2>/dev/null; then
++  as_mkdir_p='mkdir -p "$as_dir"'
++else
++  test -d ./-p && rmdir ./-p
++  as_mkdir_p=false
++fi
++
++as_test_x='test -x'
++as_executable_p=as_fn_executable_p
++
++# Sed expression to map a string onto a valid CPP name.
++as_tr_cpp="eval sed 'y%*$as_cr_letters%P$as_cr_LETTERS%;s%[^_$as_cr_alnum]%_%g'"
++
++# Sed expression to map a string onto a valid variable name.
++as_tr_sh="eval sed 'y%*+%pp%;s%[^_$as_cr_alnum]%_%g'"
++
++SHELL=${CONFIG_SHELL-/bin/sh}
++
++
++test -n "$DJDIR" || exec 7<&0 </dev/null
++exec 6>&1
++
++# Name of the host.
++# hostname on some systems (SVR3.2, old GNU/Linux) returns a bogus exit status,
++# so uname gets run too.
++ac_hostname=`(hostname || uname -n) 2>/dev/null | sed 1q`
++
++#
++# Initializations.
++#
++ac_default_prefix=/usr/local
++ac_clean_files=
++ac_config_libobj_dir=.
++LIBOBJS=
++cross_compiling=no
++subdirs=
++MFLAGS=
++MAKEFLAGS=
++
++# Identity of this package.
++PACKAGE_NAME=
++PACKAGE_TARNAME=
++PACKAGE_VERSION=
++PACKAGE_STRING=
++PACKAGE_BUGREPORT=
++PACKAGE_URL=
++
++ac_unique_file="Makefile.in"
++# Factoring default headers for most tests.
++ac_includes_default="\
++#include <stdio.h>
++#ifdef HAVE_SYS_TYPES_H
++# include <sys/types.h>
++#endif
++#ifdef HAVE_SYS_STAT_H
++# include <sys/stat.h>
++#endif
++#ifdef STDC_HEADERS
++# include <stdlib.h>
++# include <stddef.h>
++#else
++# ifdef HAVE_STDLIB_H
++#  include <stdlib.h>
++# endif
++#endif
++#ifdef HAVE_STRING_H
++# if !defined STDC_HEADERS && defined HAVE_MEMORY_H
++#  include <memory.h>
++# endif
++# include <string.h>
++#endif
++#ifdef HAVE_STRINGS_H
++# include <strings.h>
++#endif
++#ifdef HAVE_INTTYPES_H
++# include <inttypes.h>
++#endif
++#ifdef HAVE_STDINT_H
++# include <stdint.h>
++#endif
++#ifdef HAVE_UNISTD_H
++# include <unistd.h>
++#endif"
++
++ac_subst_vars='LTLIBOBJS
++LIBOBJS
++cgen_breaks
++REPORT_BUGS_TEXI
++REPORT_BUGS_TO
++PKGVERSION
++MAINT
++MAINTAINER_MODE_FALSE
++MAINTAINER_MODE_TRUE
++lt_cv_dlopen_libs
++OTOOL64
++OTOOL
++LIPO
++NMEDIT
++DSYMUTIL
++AWK
++STRIP
++OBJDUMP
++LN_S
++NM
++ac_ct_DUMPBIN
++DUMPBIN
++LD
++FGREP
++SED
++LIBTOOL
++PLUGINS_FALSE
++PLUGINS_TRUE
++zlibinc
++zlibdir
++CATOBJEXT
++GENCAT
++INSTOBJEXT
++DATADIRNAME
++CATALOGS
++POSUB
++GMSGFMT
++XGETTEXT
++INCINTL
++LIBINTL_DEP
++LIBINTL
++USE_NLS
++GMAKE_FALSE
++GMAKE_TRUE
++MAKE
++CCDEPMODE
++DEPDIR
++am__leading_dot
++PACKAGE
++RANLIB
++AR
++HDEFINES
++CC_FOR_BUILD
++INSTALL_DATA
++INSTALL_SCRIPT
++INSTALL_PROGRAM
++EGREP
++GREP
++CPP
++target_os
++target_vendor
++target_cpu
++target
++host_os
++host_vendor
++host_cpu
++host
++build_os
++build_vendor
++build_cpu
++build
++OBJEXT
++EXEEXT
++ac_ct_CC
++CPPFLAGS
++LDFLAGS
++CFLAGS
++CC
++WERROR_CFLAGS
++WARN_CFLAGS
++sim_reserved_bits
++sim_inline
++sim_hw
++sim_hw_objs
++sim_hw_cflags
++sim_default_model
++sim_scache
++sim_float
++sim_endian
++sim_bitsize
++sim_alignment
++target_alias
++host_alias
++build_alias
++LIBS
++ECHO_T
++ECHO_N
++ECHO_C
++DEFS
++mandir
++localedir
++libdir
++psdir
++pdfdir
++dvidir
++htmldir
++infodir
++docdir
++oldincludedir
++includedir
++runstatedir
++localstatedir
++sharedstatedir
++sysconfdir
++datadir
++datarootdir
++libexecdir
++sbindir
++bindir
++program_transform_name
++prefix
++exec_prefix
++PACKAGE_URL
++PACKAGE_BUGREPORT
++PACKAGE_STRING
++PACKAGE_VERSION
++PACKAGE_TARNAME
++PACKAGE_NAME
++PATH_SEPARATOR
++SHELL'
++ac_subst_files=''
++ac_user_opts='
++enable_option_checking
++with_system_zlib
++enable_plugins
++enable_shared
++enable_static
++with_pic
++enable_fast_install
++with_gnu_ld
++enable_libtool_lock
++enable_maintainer_mode
++enable_sim_debug
++enable_sim_stdio
++enable_sim_trace
++enable_sim_profile
++enable_sim_assert
++enable_sim_environment
++enable_sim_inline
++with_pkgversion
++with_bugurl
++enable_sim_endian
++enable_sim_alignment
++enable_werror
++enable_build_warnings
++enable_sim_build_warnings
++enable_sim_default_model
++enable_sim_bitsize
++'
++      ac_precious_vars='build_alias
++host_alias
++target_alias
++CC
++CFLAGS
++LDFLAGS
++LIBS
++CPPFLAGS
++CPP'
++
++
++# Initialize some variables set by options.
++ac_init_help=
++ac_init_version=false
++ac_unrecognized_opts=
++ac_unrecognized_sep=
++# The variables have the same names as the options, with
++# dashes changed to underlines.
++cache_file=/dev/null
++exec_prefix=NONE
++no_create=
++no_recursion=
++prefix=NONE
++program_prefix=NONE
++program_suffix=NONE
++program_transform_name=s,x,x,
++silent=
++site=
++srcdir=
++verbose=
++x_includes=NONE
++x_libraries=NONE
++
++# Installation directory options.
++# These are left unexpanded so users can "make install exec_prefix=/foo"
++# and all the variables that are supposed to be based on exec_prefix
++# by default will actually change.
++# Use braces instead of parens because sh, perl, etc. also accept them.
++# (The list follows the same order as the GNU Coding Standards.)
++bindir='${exec_prefix}/bin'
++sbindir='${exec_prefix}/sbin'
++libexecdir='${exec_prefix}/libexec'
++datarootdir='${prefix}/share'
++datadir='${datarootdir}'
++sysconfdir='${prefix}/etc'
++sharedstatedir='${prefix}/com'
++localstatedir='${prefix}/var'
++runstatedir='${localstatedir}/run'
++includedir='${prefix}/include'
++oldincludedir='/usr/include'
++docdir='${datarootdir}/doc/${PACKAGE}'
++infodir='${datarootdir}/info'
++htmldir='${docdir}'
++dvidir='${docdir}'
++pdfdir='${docdir}'
++psdir='${docdir}'
++libdir='${exec_prefix}/lib'
++localedir='${datarootdir}/locale'
++mandir='${datarootdir}/man'
++
++ac_prev=
++ac_dashdash=
++for ac_option
++do
++  # If the previous option needs an argument, assign it.
++  if test -n "$ac_prev"; then
++    eval $ac_prev=\$ac_option
++    ac_prev=
++    continue
++  fi
++
++  case $ac_option in
++  *=?*) ac_optarg=`expr "X$ac_option" : '[^=]*=\(.*\)'` ;;
++  *=)   ac_optarg= ;;
++  *)    ac_optarg=yes ;;
++  esac
++
++  # Accept the important Cygnus configure options, so we can diagnose typos.
++
++  case $ac_dashdash$ac_option in
++  --)
++    ac_dashdash=yes ;;
++
++  -bindir | --bindir | --bindi | --bind | --bin | --bi)
++    ac_prev=bindir ;;
++  -bindir=* | --bindir=* | --bindi=* | --bind=* | --bin=* | --bi=*)
++    bindir=$ac_optarg ;;
++
++  -build | --build | --buil | --bui | --bu)
++    ac_prev=build_alias ;;
++  -build=* | --build=* | --buil=* | --bui=* | --bu=*)
++    build_alias=$ac_optarg ;;
++
++  -cache-file | --cache-file | --cache-fil | --cache-fi \
++  | --cache-f | --cache- | --cache | --cach | --cac | --ca | --c)
++    ac_prev=cache_file ;;
++  -cache-file=* | --cache-file=* | --cache-fil=* | --cache-fi=* \
++  | --cache-f=* | --cache-=* | --cache=* | --cach=* | --cac=* | --ca=* | --c=*)
++    cache_file=$ac_optarg ;;
++
++  --config-cache | -C)
++    cache_file=config.cache ;;
++
++  -datadir | --datadir | --datadi | --datad)
++    ac_prev=datadir ;;
++  -datadir=* | --datadir=* | --datadi=* | --datad=*)
++    datadir=$ac_optarg ;;
++
++  -datarootdir | --datarootdir | --datarootdi | --datarootd | --dataroot \
++  | --dataroo | --dataro | --datar)
++    ac_prev=datarootdir ;;
++  -datarootdir=* | --datarootdir=* | --datarootdi=* | --datarootd=* \
++  | --dataroot=* | --dataroo=* | --dataro=* | --datar=*)
++    datarootdir=$ac_optarg ;;
++
++  -disable-* | --disable-*)
++    ac_useropt=`expr "x$ac_option" : 'x-*disable-\(.*\)'`
++    # Reject names that are not valid shell variable names.
++    expr "x$ac_useropt" : ".*[^-+._$as_cr_alnum]" >/dev/null &&
++      as_fn_error $? "invalid feature name: $ac_useropt"
++    ac_useropt_orig=$ac_useropt
++    ac_useropt=`$as_echo "$ac_useropt" | sed 's/[-+.]/_/g'`
++    case $ac_user_opts in
++      *"
++"enable_$ac_useropt"
++"*) ;;
++      *) ac_unrecognized_opts="$ac_unrecognized_opts$ac_unrecognized_sep--disable-$ac_useropt_orig"
++	 ac_unrecognized_sep=', ';;
++    esac
++    eval enable_$ac_useropt=no ;;
++
++  -docdir | --docdir | --docdi | --doc | --do)
++    ac_prev=docdir ;;
++  -docdir=* | --docdir=* | --docdi=* | --doc=* | --do=*)
++    docdir=$ac_optarg ;;
++
++  -dvidir | --dvidir | --dvidi | --dvid | --dvi | --dv)
++    ac_prev=dvidir ;;
++  -dvidir=* | --dvidir=* | --dvidi=* | --dvid=* | --dvi=* | --dv=*)
++    dvidir=$ac_optarg ;;
++
++  -enable-* | --enable-*)
++    ac_useropt=`expr "x$ac_option" : 'x-*enable-\([^=]*\)'`
++    # Reject names that are not valid shell variable names.
++    expr "x$ac_useropt" : ".*[^-+._$as_cr_alnum]" >/dev/null &&
++      as_fn_error $? "invalid feature name: $ac_useropt"
++    ac_useropt_orig=$ac_useropt
++    ac_useropt=`$as_echo "$ac_useropt" | sed 's/[-+.]/_/g'`
++    case $ac_user_opts in
++      *"
++"enable_$ac_useropt"
++"*) ;;
++      *) ac_unrecognized_opts="$ac_unrecognized_opts$ac_unrecognized_sep--enable-$ac_useropt_orig"
++	 ac_unrecognized_sep=', ';;
++    esac
++    eval enable_$ac_useropt=\$ac_optarg ;;
++
++  -exec-prefix | --exec_prefix | --exec-prefix | --exec-prefi \
++  | --exec-pref | --exec-pre | --exec-pr | --exec-p | --exec- \
++  | --exec | --exe | --ex)
++    ac_prev=exec_prefix ;;
++  -exec-prefix=* | --exec_prefix=* | --exec-prefix=* | --exec-prefi=* \
++  | --exec-pref=* | --exec-pre=* | --exec-pr=* | --exec-p=* | --exec-=* \
++  | --exec=* | --exe=* | --ex=*)
++    exec_prefix=$ac_optarg ;;
++
++  -gas | --gas | --ga | --g)
++    # Obsolete; use --with-gas.
++    with_gas=yes ;;
++
++  -help | --help | --hel | --he | -h)
++    ac_init_help=long ;;
++  -help=r* | --help=r* | --hel=r* | --he=r* | -hr*)
++    ac_init_help=recursive ;;
++  -help=s* | --help=s* | --hel=s* | --he=s* | -hs*)
++    ac_init_help=short ;;
++
++  -host | --host | --hos | --ho)
++    ac_prev=host_alias ;;
++  -host=* | --host=* | --hos=* | --ho=*)
++    host_alias=$ac_optarg ;;
++
++  -htmldir | --htmldir | --htmldi | --htmld | --html | --htm | --ht)
++    ac_prev=htmldir ;;
++  -htmldir=* | --htmldir=* | --htmldi=* | --htmld=* | --html=* | --htm=* \
++  | --ht=*)
++    htmldir=$ac_optarg ;;
++
++  -includedir | --includedir | --includedi | --included | --include \
++  | --includ | --inclu | --incl | --inc)
++    ac_prev=includedir ;;
++  -includedir=* | --includedir=* | --includedi=* | --included=* | --include=* \
++  | --includ=* | --inclu=* | --incl=* | --inc=*)
++    includedir=$ac_optarg ;;
++
++  -infodir | --infodir | --infodi | --infod | --info | --inf)
++    ac_prev=infodir ;;
++  -infodir=* | --infodir=* | --infodi=* | --infod=* | --info=* | --inf=*)
++    infodir=$ac_optarg ;;
++
++  -libdir | --libdir | --libdi | --libd)
++    ac_prev=libdir ;;
++  -libdir=* | --libdir=* | --libdi=* | --libd=*)
++    libdir=$ac_optarg ;;
++
++  -libexecdir | --libexecdir | --libexecdi | --libexecd | --libexec \
++  | --libexe | --libex | --libe)
++    ac_prev=libexecdir ;;
++  -libexecdir=* | --libexecdir=* | --libexecdi=* | --libexecd=* | --libexec=* \
++  | --libexe=* | --libex=* | --libe=*)
++    libexecdir=$ac_optarg ;;
++
++  -localedir | --localedir | --localedi | --localed | --locale)
++    ac_prev=localedir ;;
++  -localedir=* | --localedir=* | --localedi=* | --localed=* | --locale=*)
++    localedir=$ac_optarg ;;
++
++  -localstatedir | --localstatedir | --localstatedi | --localstated \
++  | --localstate | --localstat | --localsta | --localst | --locals)
++    ac_prev=localstatedir ;;
++  -localstatedir=* | --localstatedir=* | --localstatedi=* | --localstated=* \
++  | --localstate=* | --localstat=* | --localsta=* | --localst=* | --locals=*)
++    localstatedir=$ac_optarg ;;
++
++  -mandir | --mandir | --mandi | --mand | --man | --ma | --m)
++    ac_prev=mandir ;;
++  -mandir=* | --mandir=* | --mandi=* | --mand=* | --man=* | --ma=* | --m=*)
++    mandir=$ac_optarg ;;
++
++  -nfp | --nfp | --nf)
++    # Obsolete; use --without-fp.
++    with_fp=no ;;
++
++  -no-create | --no-create | --no-creat | --no-crea | --no-cre \
++  | --no-cr | --no-c | -n)
++    no_create=yes ;;
++
++  -no-recursion | --no-recursion | --no-recursio | --no-recursi \
++  | --no-recurs | --no-recur | --no-recu | --no-rec | --no-re | --no-r)
++    no_recursion=yes ;;
++
++  -oldincludedir | --oldincludedir | --oldincludedi | --oldincluded \
++  | --oldinclude | --oldinclud | --oldinclu | --oldincl | --oldinc \
++  | --oldin | --oldi | --old | --ol | --o)
++    ac_prev=oldincludedir ;;
++  -oldincludedir=* | --oldincludedir=* | --oldincludedi=* | --oldincluded=* \
++  | --oldinclude=* | --oldinclud=* | --oldinclu=* | --oldincl=* | --oldinc=* \
++  | --oldin=* | --oldi=* | --old=* | --ol=* | --o=*)
++    oldincludedir=$ac_optarg ;;
++
++  -prefix | --prefix | --prefi | --pref | --pre | --pr | --p)
++    ac_prev=prefix ;;
++  -prefix=* | --prefix=* | --prefi=* | --pref=* | --pre=* | --pr=* | --p=*)
++    prefix=$ac_optarg ;;
++
++  -program-prefix | --program-prefix | --program-prefi | --program-pref \
++  | --program-pre | --program-pr | --program-p)
++    ac_prev=program_prefix ;;
++  -program-prefix=* | --program-prefix=* | --program-prefi=* \
++  | --program-pref=* | --program-pre=* | --program-pr=* | --program-p=*)
++    program_prefix=$ac_optarg ;;
++
++  -program-suffix | --program-suffix | --program-suffi | --program-suff \
++  | --program-suf | --program-su | --program-s)
++    ac_prev=program_suffix ;;
++  -program-suffix=* | --program-suffix=* | --program-suffi=* \
++  | --program-suff=* | --program-suf=* | --program-su=* | --program-s=*)
++    program_suffix=$ac_optarg ;;
++
++  -program-transform-name | --program-transform-name \
++  | --program-transform-nam | --program-transform-na \
++  | --program-transform-n | --program-transform- \
++  | --program-transform | --program-transfor \
++  | --program-transfo | --program-transf \
++  | --program-trans | --program-tran \
++  | --progr-tra | --program-tr | --program-t)
++    ac_prev=program_transform_name ;;
++  -program-transform-name=* | --program-transform-name=* \
++  | --program-transform-nam=* | --program-transform-na=* \
++  | --program-transform-n=* | --program-transform-=* \
++  | --program-transform=* | --program-transfor=* \
++  | --program-transfo=* | --program-transf=* \
++  | --program-trans=* | --program-tran=* \
++  | --progr-tra=* | --program-tr=* | --program-t=*)
++    program_transform_name=$ac_optarg ;;
++
++  -pdfdir | --pdfdir | --pdfdi | --pdfd | --pdf | --pd)
++    ac_prev=pdfdir ;;
++  -pdfdir=* | --pdfdir=* | --pdfdi=* | --pdfd=* | --pdf=* | --pd=*)
++    pdfdir=$ac_optarg ;;
++
++  -psdir | --psdir | --psdi | --psd | --ps)
++    ac_prev=psdir ;;
++  -psdir=* | --psdir=* | --psdi=* | --psd=* | --ps=*)
++    psdir=$ac_optarg ;;
++
++  -q | -quiet | --quiet | --quie | --qui | --qu | --q \
++  | -silent | --silent | --silen | --sile | --sil)
++    silent=yes ;;
++
++  -runstatedir | --runstatedir | --runstatedi | --runstated \
++  | --runstate | --runstat | --runsta | --runst | --runs \
++  | --run | --ru | --r)
++    ac_prev=runstatedir ;;
++  -runstatedir=* | --runstatedir=* | --runstatedi=* | --runstated=* \
++  | --runstate=* | --runstat=* | --runsta=* | --runst=* | --runs=* \
++  | --run=* | --ru=* | --r=*)
++    runstatedir=$ac_optarg ;;
++
++  -sbindir | --sbindir | --sbindi | --sbind | --sbin | --sbi | --sb)
++    ac_prev=sbindir ;;
++  -sbindir=* | --sbindir=* | --sbindi=* | --sbind=* | --sbin=* \
++  | --sbi=* | --sb=*)
++    sbindir=$ac_optarg ;;
++
++  -sharedstatedir | --sharedstatedir | --sharedstatedi \
++  | --sharedstated | --sharedstate | --sharedstat | --sharedsta \
++  | --sharedst | --shareds | --shared | --share | --shar \
++  | --sha | --sh)
++    ac_prev=sharedstatedir ;;
++  -sharedstatedir=* | --sharedstatedir=* | --sharedstatedi=* \
++  | --sharedstated=* | --sharedstate=* | --sharedstat=* | --sharedsta=* \
++  | --sharedst=* | --shareds=* | --shared=* | --share=* | --shar=* \
++  | --sha=* | --sh=*)
++    sharedstatedir=$ac_optarg ;;
++
++  -site | --site | --sit)
++    ac_prev=site ;;
++  -site=* | --site=* | --sit=*)
++    site=$ac_optarg ;;
++
++  -srcdir | --srcdir | --srcdi | --srcd | --src | --sr)
++    ac_prev=srcdir ;;
++  -srcdir=* | --srcdir=* | --srcdi=* | --srcd=* | --src=* | --sr=*)
++    srcdir=$ac_optarg ;;
++
++  -sysconfdir | --sysconfdir | --sysconfdi | --sysconfd | --sysconf \
++  | --syscon | --sysco | --sysc | --sys | --sy)
++    ac_prev=sysconfdir ;;
++  -sysconfdir=* | --sysconfdir=* | --sysconfdi=* | --sysconfd=* | --sysconf=* \
++  | --syscon=* | --sysco=* | --sysc=* | --sys=* | --sy=*)
++    sysconfdir=$ac_optarg ;;
++
++  -target | --target | --targe | --targ | --tar | --ta | --t)
++    ac_prev=target_alias ;;
++  -target=* | --target=* | --targe=* | --targ=* | --tar=* | --ta=* | --t=*)
++    target_alias=$ac_optarg ;;
++
++  -v | -verbose | --verbose | --verbos | --verbo | --verb)
++    verbose=yes ;;
++
++  -version | --version | --versio | --versi | --vers | -V)
++    ac_init_version=: ;;
++
++  -with-* | --with-*)
++    ac_useropt=`expr "x$ac_option" : 'x-*with-\([^=]*\)'`
++    # Reject names that are not valid shell variable names.
++    expr "x$ac_useropt" : ".*[^-+._$as_cr_alnum]" >/dev/null &&
++      as_fn_error $? "invalid package name: $ac_useropt"
++    ac_useropt_orig=$ac_useropt
++    ac_useropt=`$as_echo "$ac_useropt" | sed 's/[-+.]/_/g'`
++    case $ac_user_opts in
++      *"
++"with_$ac_useropt"
++"*) ;;
++      *) ac_unrecognized_opts="$ac_unrecognized_opts$ac_unrecognized_sep--with-$ac_useropt_orig"
++	 ac_unrecognized_sep=', ';;
++    esac
++    eval with_$ac_useropt=\$ac_optarg ;;
++
++  -without-* | --without-*)
++    ac_useropt=`expr "x$ac_option" : 'x-*without-\(.*\)'`
++    # Reject names that are not valid shell variable names.
++    expr "x$ac_useropt" : ".*[^-+._$as_cr_alnum]" >/dev/null &&
++      as_fn_error $? "invalid package name: $ac_useropt"
++    ac_useropt_orig=$ac_useropt
++    ac_useropt=`$as_echo "$ac_useropt" | sed 's/[-+.]/_/g'`
++    case $ac_user_opts in
++      *"
++"with_$ac_useropt"
++"*) ;;
++      *) ac_unrecognized_opts="$ac_unrecognized_opts$ac_unrecognized_sep--without-$ac_useropt_orig"
++	 ac_unrecognized_sep=', ';;
++    esac
++    eval with_$ac_useropt=no ;;
++
++  --x)
++    # Obsolete; use --with-x.
++    with_x=yes ;;
++
++  -x-includes | --x-includes | --x-include | --x-includ | --x-inclu \
++  | --x-incl | --x-inc | --x-in | --x-i)
++    ac_prev=x_includes ;;
++  -x-includes=* | --x-includes=* | --x-include=* | --x-includ=* | --x-inclu=* \
++  | --x-incl=* | --x-inc=* | --x-in=* | --x-i=*)
++    x_includes=$ac_optarg ;;
++
++  -x-libraries | --x-libraries | --x-librarie | --x-librari \
++  | --x-librar | --x-libra | --x-libr | --x-lib | --x-li | --x-l)
++    ac_prev=x_libraries ;;
++  -x-libraries=* | --x-libraries=* | --x-librarie=* | --x-librari=* \
++  | --x-librar=* | --x-libra=* | --x-libr=* | --x-lib=* | --x-li=* | --x-l=*)
++    x_libraries=$ac_optarg ;;
++
++  -*) as_fn_error $? "unrecognized option: \`$ac_option'
++Try \`$0 --help' for more information"
++    ;;
++
++  *=*)
++    ac_envvar=`expr "x$ac_option" : 'x\([^=]*\)='`
++    # Reject names that are not valid shell variable names.
++    case $ac_envvar in #(
++      '' | [0-9]* | *[!_$as_cr_alnum]* )
++      as_fn_error $? "invalid variable name: \`$ac_envvar'" ;;
++    esac
++    eval $ac_envvar=\$ac_optarg
++    export $ac_envvar ;;
++
++  *)
++    # FIXME: should be removed in autoconf 3.0.
++    $as_echo "$as_me: WARNING: you should use --build, --host, --target" >&2
++    expr "x$ac_option" : ".*[^-._$as_cr_alnum]" >/dev/null &&
++      $as_echo "$as_me: WARNING: invalid host type: $ac_option" >&2
++    : "${build_alias=$ac_option} ${host_alias=$ac_option} ${target_alias=$ac_option}"
++    ;;
++
++  esac
++done
++
++if test -n "$ac_prev"; then
++  ac_option=--`echo $ac_prev | sed 's/_/-/g'`
++  as_fn_error $? "missing argument to $ac_option"
++fi
++
++if test -n "$ac_unrecognized_opts"; then
++  case $enable_option_checking in
++    no) ;;
++    fatal) as_fn_error $? "unrecognized options: $ac_unrecognized_opts" ;;
++    *)     $as_echo "$as_me: WARNING: unrecognized options: $ac_unrecognized_opts" >&2 ;;
++  esac
++fi
++
++# Check all directory arguments for consistency.
++for ac_var in	exec_prefix prefix bindir sbindir libexecdir datarootdir \
++		datadir sysconfdir sharedstatedir localstatedir includedir \
++		oldincludedir docdir infodir htmldir dvidir pdfdir psdir \
++		libdir localedir mandir runstatedir
++do
++  eval ac_val=\$$ac_var
++  # Remove trailing slashes.
++  case $ac_val in
++    */ )
++      ac_val=`expr "X$ac_val" : 'X\(.*[^/]\)' \| "X$ac_val" : 'X\(.*\)'`
++      eval $ac_var=\$ac_val;;
++  esac
++  # Be sure to have absolute directory names.
++  case $ac_val in
++    [\\/$]* | ?:[\\/]* )  continue;;
++    NONE | '' ) case $ac_var in *prefix ) continue;; esac;;
++  esac
++  as_fn_error $? "expected an absolute directory name for --$ac_var: $ac_val"
++done
++
++# There might be people who depend on the old broken behavior: `$host'
++# used to hold the argument of --host etc.
++# FIXME: To remove some day.
++build=$build_alias
++host=$host_alias
++target=$target_alias
++
++# FIXME: To remove some day.
++if test "x$host_alias" != x; then
++  if test "x$build_alias" = x; then
++    cross_compiling=maybe
++  elif test "x$build_alias" != "x$host_alias"; then
++    cross_compiling=yes
++  fi
++fi
++
++ac_tool_prefix=
++test -n "$host_alias" && ac_tool_prefix=$host_alias-
++
++test "$silent" = yes && exec 6>/dev/null
++
++
++ac_pwd=`pwd` && test -n "$ac_pwd" &&
++ac_ls_di=`ls -di .` &&
++ac_pwd_ls_di=`cd "$ac_pwd" && ls -di .` ||
++  as_fn_error $? "working directory cannot be determined"
++test "X$ac_ls_di" = "X$ac_pwd_ls_di" ||
++  as_fn_error $? "pwd does not report name of working directory"
++
++
++# Find the source files, if location was not specified.
++if test -z "$srcdir"; then
++  ac_srcdir_defaulted=yes
++  # Try the directory containing this script, then the parent directory.
++  ac_confdir=`$as_dirname -- "$as_myself" ||
++$as_expr X"$as_myself" : 'X\(.*[^/]\)//*[^/][^/]*/*$' \| \
++	 X"$as_myself" : 'X\(//\)[^/]' \| \
++	 X"$as_myself" : 'X\(//\)$' \| \
++	 X"$as_myself" : 'X\(/\)' \| . 2>/dev/null ||
++$as_echo X"$as_myself" |
++    sed '/^X\(.*[^/]\)\/\/*[^/][^/]*\/*$/{
++	    s//\1/
++	    q
++	  }
++	  /^X\(\/\/\)[^/].*/{
++	    s//\1/
++	    q
++	  }
++	  /^X\(\/\/\)$/{
++	    s//\1/
++	    q
++	  }
++	  /^X\(\/\).*/{
++	    s//\1/
++	    q
++	  }
++	  s/.*/./; q'`
++  srcdir=$ac_confdir
++  if test ! -r "$srcdir/$ac_unique_file"; then
++    srcdir=..
++  fi
++else
++  ac_srcdir_defaulted=no
++fi
++if test ! -r "$srcdir/$ac_unique_file"; then
++  test "$ac_srcdir_defaulted" = yes && srcdir="$ac_confdir or .."
++  as_fn_error $? "cannot find sources ($ac_unique_file) in $srcdir"
++fi
++ac_msg="sources are in $srcdir, but \`cd $srcdir' does not work"
++ac_abs_confdir=`(
++	cd "$srcdir" && test -r "./$ac_unique_file" || as_fn_error $? "$ac_msg"
++	pwd)`
++# When building in place, set srcdir=.
++if test "$ac_abs_confdir" = "$ac_pwd"; then
++  srcdir=.
++fi
++# Remove unnecessary trailing slashes from srcdir.
++# Double slashes in file names in object file debugging info
++# mess up M-x gdb in Emacs.
++case $srcdir in
++*/) srcdir=`expr "X$srcdir" : 'X\(.*[^/]\)' \| "X$srcdir" : 'X\(.*\)'`;;
++esac
++for ac_var in $ac_precious_vars; do
++  eval ac_env_${ac_var}_set=\${${ac_var}+set}
++  eval ac_env_${ac_var}_value=\$${ac_var}
++  eval ac_cv_env_${ac_var}_set=\${${ac_var}+set}
++  eval ac_cv_env_${ac_var}_value=\$${ac_var}
++done
++
++#
++# Report the --help message.
++#
++if test "$ac_init_help" = "long"; then
++  # Omit some internal or obsolete options to make the list less imposing.
++  # This message is too long to be a string in the A/UX 3.1 sh.
++  cat <<_ACEOF
++\`configure' configures this package to adapt to many kinds of systems.
++
++Usage: $0 [OPTION]... [VAR=VALUE]...
++
++To assign environment variables (e.g., CC, CFLAGS...), specify them as
++VAR=VALUE.  See below for descriptions of some of the useful variables.
++
++Defaults for the options are specified in brackets.
++
++Configuration:
++  -h, --help              display this help and exit
++      --help=short        display options specific to this package
++      --help=recursive    display the short help of all the included packages
++  -V, --version           display version information and exit
++  -q, --quiet, --silent   do not print \`checking ...' messages
++      --cache-file=FILE   cache test results in FILE [disabled]
++  -C, --config-cache      alias for \`--cache-file=config.cache'
++  -n, --no-create         do not create output files
++      --srcdir=DIR        find the sources in DIR [configure dir or \`..']
++
++Installation directories:
++  --prefix=PREFIX         install architecture-independent files in PREFIX
++                          [$ac_default_prefix]
++  --exec-prefix=EPREFIX   install architecture-dependent files in EPREFIX
++                          [PREFIX]
++
++By default, \`make install' will install all the files in
++\`$ac_default_prefix/bin', \`$ac_default_prefix/lib' etc.  You can specify
++an installation prefix other than \`$ac_default_prefix' using \`--prefix',
++for instance \`--prefix=\$HOME'.
++
++For better control, use the options below.
++
++Fine tuning of the installation directories:
++  --bindir=DIR            user executables [EPREFIX/bin]
++  --sbindir=DIR           system admin executables [EPREFIX/sbin]
++  --libexecdir=DIR        program executables [EPREFIX/libexec]
++  --sysconfdir=DIR        read-only single-machine data [PREFIX/etc]
++  --sharedstatedir=DIR    modifiable architecture-independent data [PREFIX/com]
++  --localstatedir=DIR     modifiable single-machine data [PREFIX/var]
++  --runstatedir=DIR       modifiable per-process data [LOCALSTATEDIR/run]
++  --libdir=DIR            object code libraries [EPREFIX/lib]
++  --includedir=DIR        C header files [PREFIX/include]
++  --oldincludedir=DIR     C header files for non-gcc [/usr/include]
++  --datarootdir=DIR       read-only arch.-independent data root [PREFIX/share]
++  --datadir=DIR           read-only architecture-independent data [DATAROOTDIR]
++  --infodir=DIR           info documentation [DATAROOTDIR/info]
++  --localedir=DIR         locale-dependent data [DATAROOTDIR/locale]
++  --mandir=DIR            man documentation [DATAROOTDIR/man]
++  --docdir=DIR            documentation root [DATAROOTDIR/doc/PACKAGE]
++  --htmldir=DIR           html documentation [DOCDIR]
++  --dvidir=DIR            dvi documentation [DOCDIR]
++  --pdfdir=DIR            pdf documentation [DOCDIR]
++  --psdir=DIR             ps documentation [DOCDIR]
++_ACEOF
++
++  cat <<\_ACEOF
++
++Program names:
++  --program-prefix=PREFIX            prepend PREFIX to installed program names
++  --program-suffix=SUFFIX            append SUFFIX to installed program names
++  --program-transform-name=PROGRAM   run sed PROGRAM on installed program names
++
++System types:
++  --build=BUILD     configure for building on BUILD [guessed]
++  --host=HOST       cross-compile to build programs to run on HOST [BUILD]
++  --target=TARGET   configure for building compilers for TARGET [HOST]
++_ACEOF
++fi
++
++if test -n "$ac_init_help"; then
++
++  cat <<\_ACEOF
++
++Optional Features:
++  --disable-option-checking  ignore unrecognized --enable/--with options
++  --disable-FEATURE       do not include FEATURE (same as --enable-FEATURE=no)
++  --enable-FEATURE[=ARG]  include FEATURE [ARG=yes]
++  --enable-plugins        Enable support for plugins
++  --enable-shared[=PKGS]  build shared libraries [default=yes]
++  --enable-static[=PKGS]  build static libraries [default=yes]
++  --enable-fast-install[=PKGS]
++                          optimize for fast installation [default=yes]
++  --disable-libtool-lock  avoid locking (might break parallel builds)
++  --enable-maintainer-mode
++                          enable make rules and dependencies not useful (and
++                          sometimes confusing) to the casual installer
++  --enable-sim-debug=opts Enable debugging flags (for developers of the sim
++                          itself)
++  --enable-sim-stdio      Specify whether to use stdio for console
++                          input/output
++  --enable-sim-trace=opts Enable tracing of simulated programs
++  --enable-sim-profile=opts
++                          Enable profiling flags
++  --enable-sim-assert     Specify whether to perform random assertions
++  --enable-sim-environment=environment
++                          Specify mixed, user, virtual or operating
++                          environment
++  --enable-sim-inline=inlines
++                          Specify which functions should be inlined
++  --enable-sim-endian=endian
++                          Specify target byte endian orientation
++  --enable-sim-alignment=align
++                          Specify strict, nonstrict or forced alignment of
++                          memory accesses
++  --enable-werror         treat compile warnings as errors
++  --enable-build-warnings enable build-time compiler warnings if gcc is used
++  --enable-sim-build-warnings
++                          enable SIM specific build-time compiler warnings if
++                          gcc is used
++  --enable-sim-default-model=model
++                          Specify default model to simulate
++  --enable-sim-bitsize=N  Specify target bitsize (32 or 64)
++
++Optional Packages:
++  --with-PACKAGE[=ARG]    use PACKAGE [ARG=yes]
++  --without-PACKAGE       do not use PACKAGE (same as --with-PACKAGE=no)
++  --with-system-zlib      use installed libz
++  --with-pic              try to use only PIC/non-PIC objects [default=use
++                          both]
++  --with-gnu-ld           assume the C compiler uses GNU ld [default=no]
++  --with-pkgversion=PKG   Use PKG in the version string in place of "SIM"
++  --with-bugurl=URL       Direct users to URL to report a bug
++
++Some influential environment variables:
++  CC          C compiler command
++  CFLAGS      C compiler flags
++  LDFLAGS     linker flags, e.g. -L<lib dir> if you have libraries in a
++              nonstandard directory <lib dir>
++  LIBS        libraries to pass to the linker, e.g. -l<library>
++  CPPFLAGS    (Objective) C/C++ preprocessor flags, e.g. -I<include dir> if
++              you have headers in a nonstandard directory <include dir>
++  CPP         C preprocessor
++
++Use these variables to override the choices made by `configure' or to help
++it to find libraries and programs with nonstandard names/locations.
++
++Report bugs to the package provider.
++_ACEOF
++ac_status=$?
++fi
++
++if test "$ac_init_help" = "recursive"; then
++  # If there are subdirs, report their specific --help.
++  for ac_dir in : $ac_subdirs_all; do test "x$ac_dir" = x: && continue
++    test -d "$ac_dir" ||
++      { cd "$srcdir" && ac_pwd=`pwd` && srcdir=. && test -d "$ac_dir"; } ||
++      continue
++    ac_builddir=.
++
++case "$ac_dir" in
++.) ac_dir_suffix= ac_top_builddir_sub=. ac_top_build_prefix= ;;
++*)
++  ac_dir_suffix=/`$as_echo "$ac_dir" | sed 's|^\.[\\/]||'`
++  # A ".." for each directory in $ac_dir_suffix.
++  ac_top_builddir_sub=`$as_echo "$ac_dir_suffix" | sed 's|/[^\\/]*|/..|g;s|/||'`
++  case $ac_top_builddir_sub in
++  "") ac_top_builddir_sub=. ac_top_build_prefix= ;;
++  *)  ac_top_build_prefix=$ac_top_builddir_sub/ ;;
++  esac ;;
++esac
++ac_abs_top_builddir=$ac_pwd
++ac_abs_builddir=$ac_pwd$ac_dir_suffix
++# for backward compatibility:
++ac_top_builddir=$ac_top_build_prefix
++
++case $srcdir in
++  .)  # We are building in place.
++    ac_srcdir=.
++    ac_top_srcdir=$ac_top_builddir_sub
++    ac_abs_top_srcdir=$ac_pwd ;;
++  [\\/]* | ?:[\\/]* )  # Absolute name.
++    ac_srcdir=$srcdir$ac_dir_suffix;
++    ac_top_srcdir=$srcdir
++    ac_abs_top_srcdir=$srcdir ;;
++  *) # Relative name.
++    ac_srcdir=$ac_top_build_prefix$srcdir$ac_dir_suffix
++    ac_top_srcdir=$ac_top_build_prefix$srcdir
++    ac_abs_top_srcdir=$ac_pwd/$srcdir ;;
++esac
++ac_abs_srcdir=$ac_abs_top_srcdir$ac_dir_suffix
++
++    cd "$ac_dir" || { ac_status=$?; continue; }
++    # Check for guested configure.
++    if test -f "$ac_srcdir/configure.gnu"; then
++      echo &&
++      $SHELL "$ac_srcdir/configure.gnu" --help=recursive
++    elif test -f "$ac_srcdir/configure"; then
++      echo &&
++      $SHELL "$ac_srcdir/configure" --help=recursive
++    else
++      $as_echo "$as_me: WARNING: no configuration information is in $ac_dir" >&2
++    fi || ac_status=$?
++    cd "$ac_pwd" || { ac_status=$?; break; }
++  done
++fi
++
++test -n "$ac_init_help" && exit $ac_status
++if $ac_init_version; then
++  cat <<\_ACEOF
++configure
++generated by GNU Autoconf 2.69
++
++Copyright (C) 2012 Free Software Foundation, Inc.
++This configure script is free software; the Free Software Foundation
++gives unlimited permission to copy, distribute and modify it.
++_ACEOF
++  exit
++fi
++
++## ------------------------ ##
++## Autoconf initialization. ##
++## ------------------------ ##
++
++# ac_fn_c_try_compile LINENO
++# --------------------------
++# Try to compile conftest.$ac_ext, and return whether this succeeded.
++ac_fn_c_try_compile ()
++{
++  as_lineno=${as_lineno-"$1"} as_lineno_stack=as_lineno_stack=$as_lineno_stack
++  rm -f conftest.$ac_objext
++  if { { ac_try="$ac_compile"
++case "(($ac_try" in
++  *\"* | *\`* | *\\*) ac_try_echo=\$ac_try;;
++  *) ac_try_echo=$ac_try;;
++esac
++eval ac_try_echo="\"\$as_me:${as_lineno-$LINENO}: $ac_try_echo\""
++$as_echo "$ac_try_echo"; } >&5
++  (eval "$ac_compile") 2>conftest.err
++  ac_status=$?
++  if test -s conftest.err; then
++    grep -v '^ *+' conftest.err >conftest.er1
++    cat conftest.er1 >&5
++    mv -f conftest.er1 conftest.err
++  fi
++  $as_echo "$as_me:${as_lineno-$LINENO}: \$? = $ac_status" >&5
++  test $ac_status = 0; } && {
++	 test -z "$ac_c_werror_flag" ||
++	 test ! -s conftest.err
++       } && test -s conftest.$ac_objext; then :
++  ac_retval=0
++else
++  $as_echo "$as_me: failed program was:" >&5
++sed 's/^/| /' conftest.$ac_ext >&5
++
++	ac_retval=1
++fi
++  eval $as_lineno_stack; ${as_lineno_stack:+:} unset as_lineno
++  as_fn_set_status $ac_retval
++
++} # ac_fn_c_try_compile
++
++# ac_fn_c_try_cpp LINENO
++# ----------------------
++# Try to preprocess conftest.$ac_ext, and return whether this succeeded.
++ac_fn_c_try_cpp ()
++{
++  as_lineno=${as_lineno-"$1"} as_lineno_stack=as_lineno_stack=$as_lineno_stack
++  if { { ac_try="$ac_cpp conftest.$ac_ext"
++case "(($ac_try" in
++  *\"* | *\`* | *\\*) ac_try_echo=\$ac_try;;
++  *) ac_try_echo=$ac_try;;
++esac
++eval ac_try_echo="\"\$as_me:${as_lineno-$LINENO}: $ac_try_echo\""
++$as_echo "$ac_try_echo"; } >&5
++  (eval "$ac_cpp conftest.$ac_ext") 2>conftest.err
++  ac_status=$?
++  if test -s conftest.err; then
++    grep -v '^ *+' conftest.err >conftest.er1
++    cat conftest.er1 >&5
++    mv -f conftest.er1 conftest.err
++  fi
++  $as_echo "$as_me:${as_lineno-$LINENO}: \$? = $ac_status" >&5
++  test $ac_status = 0; } > conftest.i && {
++	 test -z "$ac_c_preproc_warn_flag$ac_c_werror_flag" ||
++	 test ! -s conftest.err
++       }; then :
++  ac_retval=0
++else
++  $as_echo "$as_me: failed program was:" >&5
++sed 's/^/| /' conftest.$ac_ext >&5
++
++    ac_retval=1
++fi
++  eval $as_lineno_stack; ${as_lineno_stack:+:} unset as_lineno
++  as_fn_set_status $ac_retval
++
++} # ac_fn_c_try_cpp
++
++# ac_fn_c_check_header_mongrel LINENO HEADER VAR INCLUDES
++# -------------------------------------------------------
++# Tests whether HEADER exists, giving a warning if it cannot be compiled using
++# the include files in INCLUDES and setting the cache variable VAR
++# accordingly.
++ac_fn_c_check_header_mongrel ()
++{
++  as_lineno=${as_lineno-"$1"} as_lineno_stack=as_lineno_stack=$as_lineno_stack
++  if eval \${$3+:} false; then :
++  { $as_echo "$as_me:${as_lineno-$LINENO}: checking for $2" >&5
++$as_echo_n "checking for $2... " >&6; }
++if eval \${$3+:} false; then :
++  $as_echo_n "(cached) " >&6
++fi
++eval ac_res=\$$3
++	       { $as_echo "$as_me:${as_lineno-$LINENO}: result: $ac_res" >&5
++$as_echo "$ac_res" >&6; }
++else
++  # Is the header compilable?
++{ $as_echo "$as_me:${as_lineno-$LINENO}: checking $2 usability" >&5
++$as_echo_n "checking $2 usability... " >&6; }
++cat confdefs.h - <<_ACEOF >conftest.$ac_ext
++/* end confdefs.h.  */
++$4
++#include <$2>
++_ACEOF
++if ac_fn_c_try_compile "$LINENO"; then :
++  ac_header_compiler=yes
++else
++  ac_header_compiler=no
++fi
++rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext
++{ $as_echo "$as_me:${as_lineno-$LINENO}: result: $ac_header_compiler" >&5
++$as_echo "$ac_header_compiler" >&6; }
++
++# Is the header present?
++{ $as_echo "$as_me:${as_lineno-$LINENO}: checking $2 presence" >&5
++$as_echo_n "checking $2 presence... " >&6; }
++cat confdefs.h - <<_ACEOF >conftest.$ac_ext
++/* end confdefs.h.  */
++#include <$2>
++_ACEOF
++if ac_fn_c_try_cpp "$LINENO"; then :
++  ac_header_preproc=yes
++else
++  ac_header_preproc=no
++fi
++rm -f conftest.err conftest.i conftest.$ac_ext
++{ $as_echo "$as_me:${as_lineno-$LINENO}: result: $ac_header_preproc" >&5
++$as_echo "$ac_header_preproc" >&6; }
++
++# So?  What about this header?
++case $ac_header_compiler:$ac_header_preproc:$ac_c_preproc_warn_flag in #((
++  yes:no: )
++    { $as_echo "$as_me:${as_lineno-$LINENO}: WARNING: $2: accepted by the compiler, rejected by the preprocessor!" >&5
++$as_echo "$as_me: WARNING: $2: accepted by the compiler, rejected by the preprocessor!" >&2;}
++    { $as_echo "$as_me:${as_lineno-$LINENO}: WARNING: $2: proceeding with the compiler's result" >&5
++$as_echo "$as_me: WARNING: $2: proceeding with the compiler's result" >&2;}
++    ;;
++  no:yes:* )
++    { $as_echo "$as_me:${as_lineno-$LINENO}: WARNING: $2: present but cannot be compiled" >&5
++$as_echo "$as_me: WARNING: $2: present but cannot be compiled" >&2;}
++    { $as_echo "$as_me:${as_lineno-$LINENO}: WARNING: $2:     check for missing prerequisite headers?" >&5
++$as_echo "$as_me: WARNING: $2:     check for missing prerequisite headers?" >&2;}
++    { $as_echo "$as_me:${as_lineno-$LINENO}: WARNING: $2: see the Autoconf documentation" >&5
++$as_echo "$as_me: WARNING: $2: see the Autoconf documentation" >&2;}
++    { $as_echo "$as_me:${as_lineno-$LINENO}: WARNING: $2:     section \"Present But Cannot Be Compiled\"" >&5
++$as_echo "$as_me: WARNING: $2:     section \"Present But Cannot Be Compiled\"" >&2;}
++    { $as_echo "$as_me:${as_lineno-$LINENO}: WARNING: $2: proceeding with the compiler's result" >&5
++$as_echo "$as_me: WARNING: $2: proceeding with the compiler's result" >&2;}
++    ;;
++esac
++  { $as_echo "$as_me:${as_lineno-$LINENO}: checking for $2" >&5
++$as_echo_n "checking for $2... " >&6; }
++if eval \${$3+:} false; then :
++  $as_echo_n "(cached) " >&6
++else
++  eval "$3=\$ac_header_compiler"
++fi
++eval ac_res=\$$3
++	       { $as_echo "$as_me:${as_lineno-$LINENO}: result: $ac_res" >&5
++$as_echo "$ac_res" >&6; }
++fi
++  eval $as_lineno_stack; ${as_lineno_stack:+:} unset as_lineno
++
++} # ac_fn_c_check_header_mongrel
++
++# ac_fn_c_try_run LINENO
++# ----------------------
++# Try to link conftest.$ac_ext, and return whether this succeeded. Assumes
++# that executables *can* be run.
++ac_fn_c_try_run ()
++{
++  as_lineno=${as_lineno-"$1"} as_lineno_stack=as_lineno_stack=$as_lineno_stack
++  if { { ac_try="$ac_link"
++case "(($ac_try" in
++  *\"* | *\`* | *\\*) ac_try_echo=\$ac_try;;
++  *) ac_try_echo=$ac_try;;
++esac
++eval ac_try_echo="\"\$as_me:${as_lineno-$LINENO}: $ac_try_echo\""
++$as_echo "$ac_try_echo"; } >&5
++  (eval "$ac_link") 2>&5
++  ac_status=$?
++  $as_echo "$as_me:${as_lineno-$LINENO}: \$? = $ac_status" >&5
++  test $ac_status = 0; } && { ac_try='./conftest$ac_exeext'
++  { { case "(($ac_try" in
++  *\"* | *\`* | *\\*) ac_try_echo=\$ac_try;;
++  *) ac_try_echo=$ac_try;;
++esac
++eval ac_try_echo="\"\$as_me:${as_lineno-$LINENO}: $ac_try_echo\""
++$as_echo "$ac_try_echo"; } >&5
++  (eval "$ac_try") 2>&5
++  ac_status=$?
++  $as_echo "$as_me:${as_lineno-$LINENO}: \$? = $ac_status" >&5
++  test $ac_status = 0; }; }; then :
++  ac_retval=0
++else
++  $as_echo "$as_me: program exited with status $ac_status" >&5
++       $as_echo "$as_me: failed program was:" >&5
++sed 's/^/| /' conftest.$ac_ext >&5
++
++       ac_retval=$ac_status
++fi
++  rm -rf conftest.dSYM conftest_ipa8_conftest.oo
++  eval $as_lineno_stack; ${as_lineno_stack:+:} unset as_lineno
++  as_fn_set_status $ac_retval
++
++} # ac_fn_c_try_run
++
++# ac_fn_c_check_header_compile LINENO HEADER VAR INCLUDES
++# -------------------------------------------------------
++# Tests whether HEADER exists and can be compiled using the include files in
++# INCLUDES, setting the cache variable VAR accordingly.
++ac_fn_c_check_header_compile ()
++{
++  as_lineno=${as_lineno-"$1"} as_lineno_stack=as_lineno_stack=$as_lineno_stack
++  { $as_echo "$as_me:${as_lineno-$LINENO}: checking for $2" >&5
++$as_echo_n "checking for $2... " >&6; }
++if eval \${$3+:} false; then :
++  $as_echo_n "(cached) " >&6
++else
++  cat confdefs.h - <<_ACEOF >conftest.$ac_ext
++/* end confdefs.h.  */
++$4
++#include <$2>
++_ACEOF
++if ac_fn_c_try_compile "$LINENO"; then :
++  eval "$3=yes"
++else
++  eval "$3=no"
++fi
++rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext
++fi
++eval ac_res=\$$3
++	       { $as_echo "$as_me:${as_lineno-$LINENO}: result: $ac_res" >&5
++$as_echo "$ac_res" >&6; }
++  eval $as_lineno_stack; ${as_lineno_stack:+:} unset as_lineno
++
++} # ac_fn_c_check_header_compile
++
++# ac_fn_c_try_link LINENO
++# -----------------------
++# Try to link conftest.$ac_ext, and return whether this succeeded.
++ac_fn_c_try_link ()
++{
++  as_lineno=${as_lineno-"$1"} as_lineno_stack=as_lineno_stack=$as_lineno_stack
++  rm -f conftest.$ac_objext conftest$ac_exeext
++  if { { ac_try="$ac_link"
++case "(($ac_try" in
++  *\"* | *\`* | *\\*) ac_try_echo=\$ac_try;;
++  *) ac_try_echo=$ac_try;;
++esac
++eval ac_try_echo="\"\$as_me:${as_lineno-$LINENO}: $ac_try_echo\""
++$as_echo "$ac_try_echo"; } >&5
++  (eval "$ac_link") 2>conftest.err
++  ac_status=$?
++  if test -s conftest.err; then
++    grep -v '^ *+' conftest.err >conftest.er1
++    cat conftest.er1 >&5
++    mv -f conftest.er1 conftest.err
++  fi
++  $as_echo "$as_me:${as_lineno-$LINENO}: \$? = $ac_status" >&5
++  test $ac_status = 0; } && {
++	 test -z "$ac_c_werror_flag" ||
++	 test ! -s conftest.err
++       } && test -s conftest$ac_exeext && {
++	 test "$cross_compiling" = yes ||
++	 test -x conftest$ac_exeext
++       }; then :
++  ac_retval=0
++else
++  $as_echo "$as_me: failed program was:" >&5
++sed 's/^/| /' conftest.$ac_ext >&5
++
++	ac_retval=1
++fi
++  # Delete the IPA/IPO (Inter Procedural Analysis/Optimization) information
++  # created by the PGI compiler (conftest_ipa8_conftest.oo), as it would
++  # interfere with the next link command; also delete a directory that is
++  # left behind by Apple's compiler.  We do this before executing the actions.
++  rm -rf conftest.dSYM conftest_ipa8_conftest.oo
++  eval $as_lineno_stack; ${as_lineno_stack:+:} unset as_lineno
++  as_fn_set_status $ac_retval
++
++} # ac_fn_c_try_link
++
++# ac_fn_c_check_func LINENO FUNC VAR
++# ----------------------------------
++# Tests whether FUNC exists, setting the cache variable VAR accordingly
++ac_fn_c_check_func ()
++{
++  as_lineno=${as_lineno-"$1"} as_lineno_stack=as_lineno_stack=$as_lineno_stack
++  { $as_echo "$as_me:${as_lineno-$LINENO}: checking for $2" >&5
++$as_echo_n "checking for $2... " >&6; }
++if eval \${$3+:} false; then :
++  $as_echo_n "(cached) " >&6
++else
++  cat confdefs.h - <<_ACEOF >conftest.$ac_ext
++/* end confdefs.h.  */
++/* Define $2 to an innocuous variant, in case <limits.h> declares $2.
++   For example, HP-UX 11i <limits.h> declares gettimeofday.  */
++#define $2 innocuous_$2
++
++/* System header to define __stub macros and hopefully few prototypes,
++    which can conflict with char $2 (); below.
++    Prefer <limits.h> to <assert.h> if __STDC__ is defined, since
++    <limits.h> exists even on freestanding compilers.  */
++
++#ifdef __STDC__
++# include <limits.h>
++#else
++# include <assert.h>
++#endif
++
++#undef $2
++
++/* Override any GCC internal prototype to avoid an error.
++   Use char because int might match the return type of a GCC
++   builtin and then its argument prototype would still apply.  */
++#ifdef __cplusplus
++extern "C"
++#endif
++char $2 ();
++/* The GNU C library defines this for functions which it implements
++    to always fail with ENOSYS.  Some functions are actually named
++    something starting with __ and the normal name is an alias.  */
++#if defined __stub_$2 || defined __stub___$2
++choke me
++#endif
++
++int
++main ()
++{
++return $2 ();
++  ;
++  return 0;
++}
++_ACEOF
++if ac_fn_c_try_link "$LINENO"; then :
++  eval "$3=yes"
++else
++  eval "$3=no"
++fi
++rm -f core conftest.err conftest.$ac_objext \
++    conftest$ac_exeext conftest.$ac_ext
++fi
++eval ac_res=\$$3
++	       { $as_echo "$as_me:${as_lineno-$LINENO}: result: $ac_res" >&5
++$as_echo "$ac_res" >&6; }
++  eval $as_lineno_stack; ${as_lineno_stack:+:} unset as_lineno
++
++} # ac_fn_c_check_func
++
++# ac_fn_c_check_member LINENO AGGR MEMBER VAR INCLUDES
++# ----------------------------------------------------
++# Tries to find if the field MEMBER exists in type AGGR, after including
++# INCLUDES, setting cache variable VAR accordingly.
++ac_fn_c_check_member ()
++{
++  as_lineno=${as_lineno-"$1"} as_lineno_stack=as_lineno_stack=$as_lineno_stack
++  { $as_echo "$as_me:${as_lineno-$LINENO}: checking for $2.$3" >&5
++$as_echo_n "checking for $2.$3... " >&6; }
++if eval \${$4+:} false; then :
++  $as_echo_n "(cached) " >&6
++else
++  cat confdefs.h - <<_ACEOF >conftest.$ac_ext
++/* end confdefs.h.  */
++$5
++int
++main ()
++{
++static $2 ac_aggr;
++if (ac_aggr.$3)
++return 0;
++  ;
++  return 0;
++}
++_ACEOF
++if ac_fn_c_try_compile "$LINENO"; then :
++  eval "$4=yes"
++else
++  cat confdefs.h - <<_ACEOF >conftest.$ac_ext
++/* end confdefs.h.  */
++$5
++int
++main ()
++{
++static $2 ac_aggr;
++if (sizeof ac_aggr.$3)
++return 0;
++  ;
++  return 0;
++}
++_ACEOF
++if ac_fn_c_try_compile "$LINENO"; then :
++  eval "$4=yes"
++else
++  eval "$4=no"
++fi
++rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext
++fi
++rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext
++fi
++eval ac_res=\$$4
++	       { $as_echo "$as_me:${as_lineno-$LINENO}: result: $ac_res" >&5
++$as_echo "$ac_res" >&6; }
++  eval $as_lineno_stack; ${as_lineno_stack:+:} unset as_lineno
++
++} # ac_fn_c_check_member
++
++# ac_fn_c_check_type LINENO TYPE VAR INCLUDES
++# -------------------------------------------
++# Tests whether TYPE exists after having included INCLUDES, setting cache
++# variable VAR accordingly.
++ac_fn_c_check_type ()
++{
++  as_lineno=${as_lineno-"$1"} as_lineno_stack=as_lineno_stack=$as_lineno_stack
++  { $as_echo "$as_me:${as_lineno-$LINENO}: checking for $2" >&5
++$as_echo_n "checking for $2... " >&6; }
++if eval \${$3+:} false; then :
++  $as_echo_n "(cached) " >&6
++else
++  eval "$3=no"
++  cat confdefs.h - <<_ACEOF >conftest.$ac_ext
++/* end confdefs.h.  */
++$4
++int
++main ()
++{
++if (sizeof ($2))
++	 return 0;
++  ;
++  return 0;
++}
++_ACEOF
++if ac_fn_c_try_compile "$LINENO"; then :
++  cat confdefs.h - <<_ACEOF >conftest.$ac_ext
++/* end confdefs.h.  */
++$4
++int
++main ()
++{
++if (sizeof (($2)))
++	    return 0;
++  ;
++  return 0;
++}
++_ACEOF
++if ac_fn_c_try_compile "$LINENO"; then :
++
++else
++  eval "$3=yes"
++fi
++rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext
++fi
++rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext
++fi
++eval ac_res=\$$3
++	       { $as_echo "$as_me:${as_lineno-$LINENO}: result: $ac_res" >&5
++$as_echo "$ac_res" >&6; }
++  eval $as_lineno_stack; ${as_lineno_stack:+:} unset as_lineno
++
++} # ac_fn_c_check_type
++cat >config.log <<_ACEOF
++This file contains any messages produced by compilers while
++running configure, to aid debugging if configure makes a mistake.
++
++It was created by $as_me, which was
++generated by GNU Autoconf 2.69.  Invocation command line was
++
++  $ $0 $@
++
++_ACEOF
++exec 5>>config.log
++{
++cat <<_ASUNAME
++## --------- ##
++## Platform. ##
++## --------- ##
++
++hostname = `(hostname || uname -n) 2>/dev/null | sed 1q`
++uname -m = `(uname -m) 2>/dev/null || echo unknown`
++uname -r = `(uname -r) 2>/dev/null || echo unknown`
++uname -s = `(uname -s) 2>/dev/null || echo unknown`
++uname -v = `(uname -v) 2>/dev/null || echo unknown`
++
++/usr/bin/uname -p = `(/usr/bin/uname -p) 2>/dev/null || echo unknown`
++/bin/uname -X     = `(/bin/uname -X) 2>/dev/null     || echo unknown`
++
++/bin/arch              = `(/bin/arch) 2>/dev/null              || echo unknown`
++/usr/bin/arch -k       = `(/usr/bin/arch -k) 2>/dev/null       || echo unknown`
++/usr/convex/getsysinfo = `(/usr/convex/getsysinfo) 2>/dev/null || echo unknown`
++/usr/bin/hostinfo      = `(/usr/bin/hostinfo) 2>/dev/null      || echo unknown`
++/bin/machine           = `(/bin/machine) 2>/dev/null           || echo unknown`
++/usr/bin/oslevel       = `(/usr/bin/oslevel) 2>/dev/null       || echo unknown`
++/bin/universe          = `(/bin/universe) 2>/dev/null          || echo unknown`
++
++_ASUNAME
++
++as_save_IFS=$IFS; IFS=$PATH_SEPARATOR
++for as_dir in $PATH
++do
++  IFS=$as_save_IFS
++  test -z "$as_dir" && as_dir=.
++    $as_echo "PATH: $as_dir"
++  done
++IFS=$as_save_IFS
++
++} >&5
++
++cat >&5 <<_ACEOF
++
++
++## ----------- ##
++## Core tests. ##
++## ----------- ##
++
++_ACEOF
++
++
++# Keep a trace of the command line.
++# Strip out --no-create and --no-recursion so they do not pile up.
++# Strip out --silent because we don't want to record it for future runs.
++# Also quote any args containing shell meta-characters.
++# Make two passes to allow for proper duplicate-argument suppression.
++ac_configure_args=
++ac_configure_args0=
++ac_configure_args1=
++ac_must_keep_next=false
++for ac_pass in 1 2
++do
++  for ac_arg
++  do
++    case $ac_arg in
++    -no-create | --no-c* | -n | -no-recursion | --no-r*) continue ;;
++    -q | -quiet | --quiet | --quie | --qui | --qu | --q \
++    | -silent | --silent | --silen | --sile | --sil)
++      continue ;;
++    *\'*)
++      ac_arg=`$as_echo "$ac_arg" | sed "s/'/'\\\\\\\\''/g"` ;;
++    esac
++    case $ac_pass in
++    1) as_fn_append ac_configure_args0 " '$ac_arg'" ;;
++    2)
++      as_fn_append ac_configure_args1 " '$ac_arg'"
++      if test $ac_must_keep_next = true; then
++	ac_must_keep_next=false # Got value, back to normal.
++      else
++	case $ac_arg in
++	  *=* | --config-cache | -C | -disable-* | --disable-* \
++	  | -enable-* | --enable-* | -gas | --g* | -nfp | --nf* \
++	  | -q | -quiet | --q* | -silent | --sil* | -v | -verb* \
++	  | -with-* | --with-* | -without-* | --without-* | --x)
++	    case "$ac_configure_args0 " in
++	      "$ac_configure_args1"*" '$ac_arg' "* ) continue ;;
++	    esac
++	    ;;
++	  -* ) ac_must_keep_next=true ;;
++	esac
++      fi
++      as_fn_append ac_configure_args " '$ac_arg'"
++      ;;
++    esac
++  done
++done
++{ ac_configure_args0=; unset ac_configure_args0;}
++{ ac_configure_args1=; unset ac_configure_args1;}
++
++# When interrupted or exit'd, cleanup temporary files, and complete
++# config.log.  We remove comments because anyway the quotes in there
++# would cause problems or look ugly.
++# WARNING: Use '\'' to represent an apostrophe within the trap.
++# WARNING: Do not start the trap code with a newline, due to a FreeBSD 4.0 bug.
++trap 'exit_status=$?
++  # Save into config.log some information that might help in debugging.
++  {
++    echo
++
++    $as_echo "## ---------------- ##
++## Cache variables. ##
++## ---------------- ##"
++    echo
++    # The following way of writing the cache mishandles newlines in values,
++(
++  for ac_var in `(set) 2>&1 | sed -n '\''s/^\([a-zA-Z_][a-zA-Z0-9_]*\)=.*/\1/p'\''`; do
++    eval ac_val=\$$ac_var
++    case $ac_val in #(
++    *${as_nl}*)
++      case $ac_var in #(
++      *_cv_*) { $as_echo "$as_me:${as_lineno-$LINENO}: WARNING: cache variable $ac_var contains a newline" >&5
++$as_echo "$as_me: WARNING: cache variable $ac_var contains a newline" >&2;} ;;
++      esac
++      case $ac_var in #(
++      _ | IFS | as_nl) ;; #(
++      BASH_ARGV | BASH_SOURCE) eval $ac_var= ;; #(
++      *) { eval $ac_var=; unset $ac_var;} ;;
++      esac ;;
++    esac
++  done
++  (set) 2>&1 |
++    case $as_nl`(ac_space='\'' '\''; set) 2>&1` in #(
++    *${as_nl}ac_space=\ *)
++      sed -n \
++	"s/'\''/'\''\\\\'\'''\''/g;
++	  s/^\\([_$as_cr_alnum]*_cv_[_$as_cr_alnum]*\\)=\\(.*\\)/\\1='\''\\2'\''/p"
++      ;; #(
++    *)
++      sed -n "/^[_$as_cr_alnum]*_cv_[_$as_cr_alnum]*=/p"
++      ;;
++    esac |
++    sort
++)
++    echo
++
++    $as_echo "## ----------------- ##
++## Output variables. ##
++## ----------------- ##"
++    echo
++    for ac_var in $ac_subst_vars
++    do
++      eval ac_val=\$$ac_var
++      case $ac_val in
++      *\'\''*) ac_val=`$as_echo "$ac_val" | sed "s/'\''/'\''\\\\\\\\'\'''\''/g"`;;
++      esac
++      $as_echo "$ac_var='\''$ac_val'\''"
++    done | sort
++    echo
++
++    if test -n "$ac_subst_files"; then
++      $as_echo "## ------------------- ##
++## File substitutions. ##
++## ------------------- ##"
++      echo
++      for ac_var in $ac_subst_files
++      do
++	eval ac_val=\$$ac_var
++	case $ac_val in
++	*\'\''*) ac_val=`$as_echo "$ac_val" | sed "s/'\''/'\''\\\\\\\\'\'''\''/g"`;;
++	esac
++	$as_echo "$ac_var='\''$ac_val'\''"
++      done | sort
++      echo
++    fi
++
++    if test -s confdefs.h; then
++      $as_echo "## ----------- ##
++## confdefs.h. ##
++## ----------- ##"
++      echo
++      cat confdefs.h
++      echo
++    fi
++    test "$ac_signal" != 0 &&
++      $as_echo "$as_me: caught signal $ac_signal"
++    $as_echo "$as_me: exit $exit_status"
++  } >&5
++  rm -f core *.core core.conftest.* &&
++    rm -f -r conftest* confdefs* conf$$* $ac_clean_files &&
++    exit $exit_status
++' 0
++for ac_signal in 1 2 13 15; do
++  trap 'ac_signal='$ac_signal'; as_fn_exit 1' $ac_signal
++done
++ac_signal=0
++
++# confdefs.h avoids OS command line length limits that DEFS can exceed.
++rm -f -r conftest* confdefs.h
++
++$as_echo "/* confdefs.h */" > confdefs.h
++
++# Predefined preprocessor variables.
++
++cat >>confdefs.h <<_ACEOF
++#define PACKAGE_NAME "$PACKAGE_NAME"
++_ACEOF
++
++cat >>confdefs.h <<_ACEOF
++#define PACKAGE_TARNAME "$PACKAGE_TARNAME"
++_ACEOF
++
++cat >>confdefs.h <<_ACEOF
++#define PACKAGE_VERSION "$PACKAGE_VERSION"
++_ACEOF
++
++cat >>confdefs.h <<_ACEOF
++#define PACKAGE_STRING "$PACKAGE_STRING"
++_ACEOF
++
++cat >>confdefs.h <<_ACEOF
++#define PACKAGE_BUGREPORT "$PACKAGE_BUGREPORT"
++_ACEOF
++
++cat >>confdefs.h <<_ACEOF
++#define PACKAGE_URL "$PACKAGE_URL"
++_ACEOF
++
++
++# Let the site file select an alternate cache file if it wants to.
++# Prefer an explicitly selected file to automatically selected ones.
++ac_site_file1=NONE
++ac_site_file2=NONE
++if test -n "$CONFIG_SITE"; then
++  # We do not want a PATH search for config.site.
++  case $CONFIG_SITE in #((
++    -*)  ac_site_file1=./$CONFIG_SITE;;
++    */*) ac_site_file1=$CONFIG_SITE;;
++    *)   ac_site_file1=./$CONFIG_SITE;;
++  esac
++elif test "x$prefix" != xNONE; then
++  ac_site_file1=$prefix/share/config.site
++  ac_site_file2=$prefix/etc/config.site
++else
++  ac_site_file1=$ac_default_prefix/share/config.site
++  ac_site_file2=$ac_default_prefix/etc/config.site
++fi
++for ac_site_file in "$ac_site_file1" "$ac_site_file2"
++do
++  test "x$ac_site_file" = xNONE && continue
++  if test /dev/null != "$ac_site_file" && test -r "$ac_site_file"; then
++    { $as_echo "$as_me:${as_lineno-$LINENO}: loading site script $ac_site_file" >&5
++$as_echo "$as_me: loading site script $ac_site_file" >&6;}
++    sed 's/^/| /' "$ac_site_file" >&5
++    . "$ac_site_file" \
++      || { { $as_echo "$as_me:${as_lineno-$LINENO}: error: in \`$ac_pwd':" >&5
++$as_echo "$as_me: error: in \`$ac_pwd':" >&2;}
++as_fn_error $? "failed to load site script $ac_site_file
++See \`config.log' for more details" "$LINENO" 5; }
++  fi
++done
++
++if test -r "$cache_file"; then
++  # Some versions of bash will fail to source /dev/null (special files
++  # actually), so we avoid doing that.  DJGPP emulates it as a regular file.
++  if test /dev/null != "$cache_file" && test -f "$cache_file"; then
++    { $as_echo "$as_me:${as_lineno-$LINENO}: loading cache $cache_file" >&5
++$as_echo "$as_me: loading cache $cache_file" >&6;}
++    case $cache_file in
++      [\\/]* | ?:[\\/]* ) . "$cache_file";;
++      *)                      . "./$cache_file";;
++    esac
++  fi
++else
++  { $as_echo "$as_me:${as_lineno-$LINENO}: creating cache $cache_file" >&5
++$as_echo "$as_me: creating cache $cache_file" >&6;}
++  >$cache_file
++fi
++
++# Check that the precious variables saved in the cache have kept the same
++# value.
++ac_cache_corrupted=false
++for ac_var in $ac_precious_vars; do
++  eval ac_old_set=\$ac_cv_env_${ac_var}_set
++  eval ac_new_set=\$ac_env_${ac_var}_set
++  eval ac_old_val=\$ac_cv_env_${ac_var}_value
++  eval ac_new_val=\$ac_env_${ac_var}_value
++  case $ac_old_set,$ac_new_set in
++    set,)
++      { $as_echo "$as_me:${as_lineno-$LINENO}: error: \`$ac_var' was set to \`$ac_old_val' in the previous run" >&5
++$as_echo "$as_me: error: \`$ac_var' was set to \`$ac_old_val' in the previous run" >&2;}
++      ac_cache_corrupted=: ;;
++    ,set)
++      { $as_echo "$as_me:${as_lineno-$LINENO}: error: \`$ac_var' was not set in the previous run" >&5
++$as_echo "$as_me: error: \`$ac_var' was not set in the previous run" >&2;}
++      ac_cache_corrupted=: ;;
++    ,);;
++    *)
++      if test "x$ac_old_val" != "x$ac_new_val"; then
++	# differences in whitespace do not lead to failure.
++	ac_old_val_w=`echo x $ac_old_val`
++	ac_new_val_w=`echo x $ac_new_val`
++	if test "$ac_old_val_w" != "$ac_new_val_w"; then
++	  { $as_echo "$as_me:${as_lineno-$LINENO}: error: \`$ac_var' has changed since the previous run:" >&5
++$as_echo "$as_me: error: \`$ac_var' has changed since the previous run:" >&2;}
++	  ac_cache_corrupted=:
++	else
++	  { $as_echo "$as_me:${as_lineno-$LINENO}: warning: ignoring whitespace changes in \`$ac_var' since the previous run:" >&5
++$as_echo "$as_me: warning: ignoring whitespace changes in \`$ac_var' since the previous run:" >&2;}
++	  eval $ac_var=\$ac_old_val
++	fi
++	{ $as_echo "$as_me:${as_lineno-$LINENO}:   former value:  \`$ac_old_val'" >&5
++$as_echo "$as_me:   former value:  \`$ac_old_val'" >&2;}
++	{ $as_echo "$as_me:${as_lineno-$LINENO}:   current value: \`$ac_new_val'" >&5
++$as_echo "$as_me:   current value: \`$ac_new_val'" >&2;}
++      fi;;
++  esac
++  # Pass precious variables to config.status.
++  if test "$ac_new_set" = set; then
++    case $ac_new_val in
++    *\'*) ac_arg=$ac_var=`$as_echo "$ac_new_val" | sed "s/'/'\\\\\\\\''/g"` ;;
++    *) ac_arg=$ac_var=$ac_new_val ;;
++    esac
++    case " $ac_configure_args " in
++      *" '$ac_arg' "*) ;; # Avoid dups.  Use of quotes ensures accuracy.
++      *) as_fn_append ac_configure_args " '$ac_arg'" ;;
++    esac
++  fi
++done
++if $ac_cache_corrupted; then
++  { $as_echo "$as_me:${as_lineno-$LINENO}: error: in \`$ac_pwd':" >&5
++$as_echo "$as_me: error: in \`$ac_pwd':" >&2;}
++  { $as_echo "$as_me:${as_lineno-$LINENO}: error: changes in the environment can compromise the build" >&5
++$as_echo "$as_me: error: changes in the environment can compromise the build" >&2;}
++  as_fn_error $? "run \`make distclean' and/or \`rm $cache_file' and start over" "$LINENO" 5
++fi
++## -------------------- ##
++## Main body of script. ##
++## -------------------- ##
++
++ac_ext=c
++ac_cpp='$CPP $CPPFLAGS'
++ac_compile='$CC -c $CFLAGS $CPPFLAGS conftest.$ac_ext >&5'
++ac_link='$CC -o conftest$ac_exeext $CFLAGS $CPPFLAGS $LDFLAGS conftest.$ac_ext $LIBS >&5'
++ac_compiler_gnu=$ac_cv_c_compiler_gnu
++
++
++# This file contains common code used by all simulators.
++#
++# SIM_AC_COMMON invokes AC macros used by all simulators and by the common
++# directory.  It is intended to be invoked before any target specific stuff.
++# SIM_AC_OUTPUT is a cover function to AC_OUTPUT to generate the Makefile.
++# It is intended to be invoked last.
++#
++# The simulator's configure.ac should look like:
++#
++# dnl Process this file with autoconf to produce a configure script.
++# AC_PREREQ(2.64)dnl
++# AC_INIT(Makefile.in)
++# sinclude(../common/aclocal.m4)
++#
++# SIM_AC_COMMON
++#
++# ... target specific stuff ...
++#
++# SIM_AC_OUTPUT
++
++# Include global overrides and fixes for Autoconf.
++
++
++
++
++
++
++
++
++
++
++
++
++
++
++
++
++
++
++
++
++
++
++
++
++
++
++
++
++
++
++
++
++
++
++
++# libtool.m4 - Configure libtool for the host system. -*-Autoconf-*-
++#
++#   Copyright (C) 1996, 1997, 1998, 1999, 2000, 2001, 2003, 2004, 2005,
++#                 2006, 2007, 2008, 2009 Free Software Foundation, Inc.
++#   Written by Gordon Matzigkeit, 1996
++#
++# This file is free software; the Free Software Foundation gives
++# unlimited permission to copy and/or distribute it, with or without
++# modifications, as long as this notice is preserved.
++
++
++
++# serial 56 LT_INIT
++
++
++# LT_PREREQ(VERSION)
++# ------------------
++# Complain and exit if this libtool version is less that VERSION.
++
++
++
++# _LT_CHECK_BUILDDIR
++# ------------------
++# Complain if the absolute build directory name contains unusual characters
++
++
++
++# LT_INIT([OPTIONS])
++# ------------------
++# LT_INIT
++
++# Old names:
++# This is what autoupdate's m4 run will expand.  It fires
++# the warning (with _au_warn_XXX), outputs it into the
++# updated configure.ac (with AC_DIAGNOSE), and then outputs
++# the replacement expansion.
++
++
++# This is an auxiliary macro that is also run when
++# autoupdate runs m4.  It simply calls m4_warning, but
++# we need a wrapper so that each warning is emitted only
++# once.  We break the quoting in m4_warning's argument in
++# order to expand this macro's arguments, not AU_DEFUN's.
++
++
++# Finally, this is the expansion that is picked up by
++# autoconf.  It tells the user to run autoupdate, and
++# then outputs the replacement expansion.  We do not care
++# about autoupdate's warning because that contains
++# information on what to do *after* running autoupdate.
++
++# This is what autoupdate's m4 run will expand.  It fires
++# the warning (with _au_warn_XXX), outputs it into the
++# updated configure.ac (with AC_DIAGNOSE), and then outputs
++# the replacement expansion.
++
++
++# This is an auxiliary macro that is also run when
++# autoupdate runs m4.  It simply calls m4_warning, but
++# we need a wrapper so that each warning is emitted only
++# once.  We break the quoting in m4_warning's argument in
++# order to expand this macro's arguments, not AU_DEFUN's.
++
++
++# Finally, this is the expansion that is picked up by
++# autoconf.  It tells the user to run autoupdate, and
++# then outputs the replacement expansion.  We do not care
++# about autoupdate's warning because that contains
++# information on what to do *after* running autoupdate.
++
++
++
++# _LT_CC_BASENAME(CC)
++# -------------------
++# Calculate cc_basename.  Skip known compiler wrappers and cross-prefix.
++
++
++
++# _LT_FILEUTILS_DEFAULTS
++# ----------------------
++# It is okay to use these file commands and assume they have been set
++# sensibly after `m4_require([_LT_FILEUTILS_DEFAULTS])'.
++# _LT_FILEUTILS_DEFAULTS
++
++
++# _LT_SETUP
++# ---------
++# _LT_SETUP
++
++
++# _LT_PREPARE_SED_QUOTE_VARS
++# --------------------------
++# Define a few sed substitution that help us do robust quoting.
++
++
++# _LT_PROG_LTMAIN
++# ---------------
++# Note that this code is called both from `configure', and `config.status'
++# now that we use AC_CONFIG_COMMANDS to generate libtool.  Notably,
++# `config.status' has no value for ac_aux_dir unless we are using Automake,
++# so we pass a copy along to make sure it has a sensible value anyway.
++# _LT_PROG_LTMAIN
++
++
++## ------------------------------------- ##
++## Accumulate code for creating libtool. ##
++## ------------------------------------- ##
++
++# So that we can recreate a full libtool script including additional
++# tags, we accumulate the chunks of code to send to AC_CONFIG_COMMANDS
++# in macros and then make a single call at the end using the `libtool'
++# label.
++
++
++# _LT_CONFIG_LIBTOOL_INIT([INIT-COMMANDS])
++# ----------------------------------------
++# Register INIT-COMMANDS to be passed to AC_CONFIG_COMMANDS later.
++
++
++# Initialize.
++
++
++
++# _LT_CONFIG_LIBTOOL([COMMANDS])
++# ------------------------------
++# Register COMMANDS to be passed to AC_CONFIG_COMMANDS later.
++
++
++# Initialize.
++
++
++
++# _LT_CONFIG_SAVE_COMMANDS([COMMANDS], [INIT_COMMANDS])
++# -----------------------------------------------------
++
++
++
++# _LT_FORMAT_COMMENT([COMMENT])
++# -----------------------------
++# Add leading comment marks to the start of each line, and a trailing
++# full-stop to the whole comment if one is not present already.
++
++
++
++
++## ------------------------ ##
++## FIXME: Eliminate VARNAME ##
++## ------------------------ ##
++
++
++# _LT_DECL([CONFIGNAME], VARNAME, VALUE, [DESCRIPTION], [IS-TAGGED?])
++# -------------------------------------------------------------------
++# CONFIGNAME is the name given to the value in the libtool script.
++# VARNAME is the (base) name used in the configure script.
++# VALUE may be 0, 1 or 2 for a computed quote escaped value based on
++# VARNAME.  Any other value will be used directly.
++
++
++
++# _LT_TAGDECL([CONFIGNAME], VARNAME, VALUE, [DESCRIPTION])
++# --------------------------------------------------------
++
++
++
++# lt_decl_tag_varnames([SEPARATOR], [VARNAME1...])
++# ------------------------------------------------
++
++
++
++# _lt_decl_filter(SUBKEY, VALUE, [SEPARATOR], [VARNAME1..])
++# ---------------------------------------------------------
++
++
++
++# lt_decl_quote_varnames([SEPARATOR], [VARNAME1...])
++# --------------------------------------------------
++
++
++
++# lt_decl_dquote_varnames([SEPARATOR], [VARNAME1...])
++# ---------------------------------------------------
++
++
++
++# lt_decl_varnames_tagged([SEPARATOR], [VARNAME1...])
++# ---------------------------------------------------
++
++
++
++
++# lt_decl_all_varnames([SEPARATOR], [VARNAME1...])
++# ------------------------------------------------
++
++
++
++
++# _LT_CONFIG_STATUS_DECLARE([VARNAME])
++# ------------------------------------
++# Quote a variable value, and forward it to `config.status' so that its
++# declaration there will have the same value as in `configure'.  VARNAME
++# must have a single quote delimited value for this to work.
++
++
++
++# _LT_CONFIG_STATUS_DECLARATIONS
++# ------------------------------
++# We delimit libtool config variables with single quotes, so when
++# we write them to config.status, we have to be sure to quote all
++# embedded single quotes properly.  In configure, this macro expands
++# each variable declared with _LT_DECL (and _LT_TAGDECL) into:
++#
++#    <var>='`$ECHO "$<var>" | $SED "$delay_single_quote_subst"`'
++
++
++
++# _LT_LIBTOOL_TAGS
++# ----------------
++# Output comment and list of tags supported by the script
++
++
++
++# _LT_LIBTOOL_DECLARE(VARNAME, [TAG])
++# -----------------------------------
++# Extract the dictionary values for VARNAME (optionally with TAG) and
++# expand to a commented shell variable setting:
++#
++#    # Some comment about what VAR is for.
++#    visible_name=$lt_internal_name
++
++
++
++# _LT_LIBTOOL_CONFIG_VARS
++# -----------------------
++# Produce commented declarations of non-tagged libtool config variables
++# suitable for insertion in the LIBTOOL CONFIG section of the `libtool'
++# script.  Tagged libtool config variables (even for the LIBTOOL CONFIG
++# section) are produced by _LT_LIBTOOL_TAG_VARS.
++
++
++
++# _LT_LIBTOOL_TAG_VARS(TAG)
++# -------------------------
++
++
++
++# _LT_TAGVAR(VARNAME, [TAGNAME])
++# ------------------------------
++
++
++
++# _LT_CONFIG_COMMANDS
++# -------------------
++# Send accumulated output to $CONFIG_STATUS.  Thanks to the lists of
++# variables for single and double quote escaping we saved from calls
++# to _LT_DECL, we can put quote escaped variables declarations
++# into `config.status', and then the shell code to quote escape them in
++# for loops in `config.status'.  Finally, any additional code accumulated
++# from calls to _LT_CONFIG_LIBTOOL_INIT is expanded.
++#_LT_CONFIG_COMMANDS
++
++
++# Initialize.
++
++
++# _LT_GENERATED_FILE_INIT(FILE, [COMMENT])
++# ------------------------------------
++# Generate a child script FILE with all initialization necessary to
++# reuse the environment learned by the parent script, and make the
++# file executable.  If COMMENT is supplied, it is inserted after the
++# `#!' sequence but before initialization text begins.  After this
++# macro, additional text can be appended to FILE to form the body of
++# the child script.  The macro ends with non-zero status if the
++# file could not be fully written (such as if the disk is full).
++# _LT_GENERATED_FILE_INIT
++
++# LT_OUTPUT
++# ---------
++# This macro allows early generation of the libtool script (before
++# AC_OUTPUT is called), incase it is used in configure for compilation
++# tests.
++# LT_OUTPUT
++
++
++# _LT_CONFIG(TAG)
++# ---------------
++# If TAG is the built-in tag, create an initial libtool script with a
++# default configuration from the untagged config vars.  Otherwise add code
++# to config.status for appending the configuration named by TAG from the
++# matching tagged config vars.
++# _LT_CONFIG
++
++
++# LT_SUPPORTED_TAG(TAG)
++# ---------------------
++# Trace this macro to discover what tags are supported by the libtool
++# --tag option, using:
++#    autoconf --trace 'LT_SUPPORTED_TAG:$1'
++
++
++
++# C support is built-in for now
++
++
++
++
++# LT_LANG(LANG)
++# -------------
++# Enable libtool support for the given language if not already enabled.
++# LT_LANG
++
++
++# _LT_LANG(LANGNAME)
++# ------------------
++# _LT_LANG
++
++
++# _LT_LANG_DEFAULT_CONFIG
++# -----------------------
++# _LT_LANG_DEFAULT_CONFIG
++
++# Obsolete macros:
++# This is what autoupdate's m4 run will expand.  It fires
++# the warning (with _au_warn_XXX), outputs it into the
++# updated configure.ac (with AC_DIAGNOSE), and then outputs
++# the replacement expansion.
++
++
++# This is an auxiliary macro that is also run when
++# autoupdate runs m4.  It simply calls m4_warning, but
++# we need a wrapper so that each warning is emitted only
++# once.  We break the quoting in m4_warning's argument in
++# order to expand this macro's arguments, not AU_DEFUN's.
++
++
++# Finally, this is the expansion that is picked up by
++# autoconf.  It tells the user to run autoupdate, and
++# then outputs the replacement expansion.  We do not care
++# about autoupdate's warning because that contains
++# information on what to do *after* running autoupdate.
++
++# This is what autoupdate's m4 run will expand.  It fires
++# the warning (with _au_warn_XXX), outputs it into the
++# updated configure.ac (with AC_DIAGNOSE), and then outputs
++# the replacement expansion.
++
++
++# This is an auxiliary macro that is also run when
++# autoupdate runs m4.  It simply calls m4_warning, but
++# we need a wrapper so that each warning is emitted only
++# once.  We break the quoting in m4_warning's argument in
++# order to expand this macro's arguments, not AU_DEFUN's.
++
++
++# Finally, this is the expansion that is picked up by
++# autoconf.  It tells the user to run autoupdate, and
++# then outputs the replacement expansion.  We do not care
++# about autoupdate's warning because that contains
++# information on what to do *after* running autoupdate.
++
++# This is what autoupdate's m4 run will expand.  It fires
++# the warning (with _au_warn_XXX), outputs it into the
++# updated configure.ac (with AC_DIAGNOSE), and then outputs
++# the replacement expansion.
++
++
++# This is an auxiliary macro that is also run when
++# autoupdate runs m4.  It simply calls m4_warning, but
++# we need a wrapper so that each warning is emitted only
++# once.  We break the quoting in m4_warning's argument in
++# order to expand this macro's arguments, not AU_DEFUN's.
++
++
++# Finally, this is the expansion that is picked up by
++# autoconf.  It tells the user to run autoupdate, and
++# then outputs the replacement expansion.  We do not care
++# about autoupdate's warning because that contains
++# information on what to do *after* running autoupdate.
++
++# This is what autoupdate's m4 run will expand.  It fires
++# the warning (with _au_warn_XXX), outputs it into the
++# updated configure.ac (with AC_DIAGNOSE), and then outputs
++# the replacement expansion.
++
++
++# This is an auxiliary macro that is also run when
++# autoupdate runs m4.  It simply calls m4_warning, but
++# we need a wrapper so that each warning is emitted only
++# once.  We break the quoting in m4_warning's argument in
++# order to expand this macro's arguments, not AU_DEFUN's.
++
++
++# Finally, this is the expansion that is picked up by
++# autoconf.  It tells the user to run autoupdate, and
++# then outputs the replacement expansion.  We do not care
++# about autoupdate's warning because that contains
++# information on what to do *after* running autoupdate.
++
++# This is what autoupdate's m4 run will expand.  It fires
++# the warning (with _au_warn_XXX), outputs it into the
++# updated configure.ac (with AC_DIAGNOSE), and then outputs
++# the replacement expansion.
++
++
++# This is an auxiliary macro that is also run when
++# autoupdate runs m4.  It simply calls m4_warning, but
++# we need a wrapper so that each warning is emitted only
++# once.  We break the quoting in m4_warning's argument in
++# order to expand this macro's arguments, not AU_DEFUN's.
++
++
++# Finally, this is the expansion that is picked up by
++# autoconf.  It tells the user to run autoupdate, and
++# then outputs the replacement expansion.  We do not care
++# about autoupdate's warning because that contains
++# information on what to do *after* running autoupdate.
++
++
++
++# _LT_TAG_COMPILER
++# ----------------
++# _LT_TAG_COMPILER
++
++
++# _LT_COMPILER_BOILERPLATE
++# ------------------------
++# Check for compiler boilerplate output or warnings with
++# the simple compiler test code.
++# _LT_COMPILER_BOILERPLATE
++
++
++# _LT_LINKER_BOILERPLATE
++# ----------------------
++# Check for linker boilerplate output or warnings with
++# the simple link test code.
++# _LT_LINKER_BOILERPLATE
++
++# _LT_REQUIRED_DARWIN_CHECKS
++# -------------------------
++
++
++
++# _LT_DARWIN_LINKER_FEATURES
++# --------------------------
++# Checks for linker and compiler features on darwin
++
++
++# _LT_SYS_MODULE_PATH_AIX
++# -----------------------
++# Links a minimal program and checks the executable
++# for the system default hardcoded library path. In most cases,
++# this is /usr/lib:/lib, but when the MPI compilers are used
++# the location of the communication and MPI libs are included too.
++# If we don't find anything, use the default library path according
++# to the aix ld manual.
++# _LT_SYS_MODULE_PATH_AIX
++
++
++# _LT_SHELL_INIT(ARG)
++# -------------------
++# _LT_SHELL_INIT
++
++
++
++# _LT_PROG_ECHO_BACKSLASH
++# -----------------------
++# Find how we can fake an echo command that does not interpret backslash.
++# In particular, with Autoconf 2.60 or later we add some code to the start
++# of the generated configure script which will find a shell with a builtin
++# printf (which we can use as an echo command).
++# _LT_PROG_ECHO_BACKSLASH
++
++
++# _LT_ENABLE_LOCK
++# ---------------
++# _LT_ENABLE_LOCK
++
++
++# _LT_CMD_OLD_ARCHIVE
++# -------------------
++# _LT_CMD_OLD_ARCHIVE
++
++
++# _LT_COMPILER_OPTION(MESSAGE, VARIABLE-NAME, FLAGS,
++#		[OUTPUT-FILE], [ACTION-SUCCESS], [ACTION-FAILURE])
++# ----------------------------------------------------------------
++# Check whether the given compiler option works
++# _LT_COMPILER_OPTION
++
++# Old name:
++# This is what autoupdate's m4 run will expand.  It fires
++# the warning (with _au_warn_XXX), outputs it into the
++# updated configure.ac (with AC_DIAGNOSE), and then outputs
++# the replacement expansion.
++
++
++# This is an auxiliary macro that is also run when
++# autoupdate runs m4.  It simply calls m4_warning, but
++# we need a wrapper so that each warning is emitted only
++# once.  We break the quoting in m4_warning's argument in
++# order to expand this macro's arguments, not AU_DEFUN's.
++
++
++# Finally, this is the expansion that is picked up by
++# autoconf.  It tells the user to run autoupdate, and
++# then outputs the replacement expansion.  We do not care
++# about autoupdate's warning because that contains
++# information on what to do *after* running autoupdate.
++
++
++
++# _LT_LINKER_OPTION(MESSAGE, VARIABLE-NAME, FLAGS,
++#                  [ACTION-SUCCESS], [ACTION-FAILURE])
++# ----------------------------------------------------
++# Check whether the given linker option works
++# _LT_LINKER_OPTION
++
++# Old name:
++# This is what autoupdate's m4 run will expand.  It fires
++# the warning (with _au_warn_XXX), outputs it into the
++# updated configure.ac (with AC_DIAGNOSE), and then outputs
++# the replacement expansion.
++
++
++# This is an auxiliary macro that is also run when
++# autoupdate runs m4.  It simply calls m4_warning, but
++# we need a wrapper so that each warning is emitted only
++# once.  We break the quoting in m4_warning's argument in
++# order to expand this macro's arguments, not AU_DEFUN's.
++
++
++# Finally, this is the expansion that is picked up by
++# autoconf.  It tells the user to run autoupdate, and
++# then outputs the replacement expansion.  We do not care
++# about autoupdate's warning because that contains
++# information on what to do *after* running autoupdate.
++
++
++
++# LT_CMD_MAX_LEN
++#---------------
++# LT_CMD_MAX_LEN
++
++# Old name:
++# This is what autoupdate's m4 run will expand.  It fires
++# the warning (with _au_warn_XXX), outputs it into the
++# updated configure.ac (with AC_DIAGNOSE), and then outputs
++# the replacement expansion.
++
++
++# This is an auxiliary macro that is also run when
++# autoupdate runs m4.  It simply calls m4_warning, but
++# we need a wrapper so that each warning is emitted only
++# once.  We break the quoting in m4_warning's argument in
++# order to expand this macro's arguments, not AU_DEFUN's.
++
++
++# Finally, this is the expansion that is picked up by
++# autoconf.  It tells the user to run autoupdate, and
++# then outputs the replacement expansion.  We do not care
++# about autoupdate's warning because that contains
++# information on what to do *after* running autoupdate.
++
++
++
++# _LT_HEADER_DLFCN
++# ----------------
++# _LT_HEADER_DLFCN
++
++
++# _LT_TRY_DLOPEN_SELF (ACTION-IF-TRUE, ACTION-IF-TRUE-W-USCORE,
++#                      ACTION-IF-FALSE, ACTION-IF-CROSS-COMPILING)
++# ----------------------------------------------------------------
++# _LT_TRY_DLOPEN_SELF
++
++
++# LT_SYS_DLOPEN_SELF
++# ------------------
++# LT_SYS_DLOPEN_SELF
++
++# Old name:
++# This is what autoupdate's m4 run will expand.  It fires
++# the warning (with _au_warn_XXX), outputs it into the
++# updated configure.ac (with AC_DIAGNOSE), and then outputs
++# the replacement expansion.
++
++
++# This is an auxiliary macro that is also run when
++# autoupdate runs m4.  It simply calls m4_warning, but
++# we need a wrapper so that each warning is emitted only
++# once.  We break the quoting in m4_warning's argument in
++# order to expand this macro's arguments, not AU_DEFUN's.
++
++
++# Finally, this is the expansion that is picked up by
++# autoconf.  It tells the user to run autoupdate, and
++# then outputs the replacement expansion.  We do not care
++# about autoupdate's warning because that contains
++# information on what to do *after* running autoupdate.
++
++
++
++# _LT_COMPILER_C_O([TAGNAME])
++# ---------------------------
++# Check to see if options -c and -o are simultaneously supported by compiler.
++# This macro does not hard code the compiler like AC_PROG_CC_C_O.
++# _LT_COMPILER_C_O
++
++
++# _LT_COMPILER_FILE_LOCKS([TAGNAME])
++# ----------------------------------
++# Check to see if we can do hard links to lock some files if needed
++# _LT_COMPILER_FILE_LOCKS
++
++
++# _LT_CHECK_OBJDIR
++# ----------------
++# _LT_CHECK_OBJDIR
++
++
++# _LT_LINKER_HARDCODE_LIBPATH([TAGNAME])
++# --------------------------------------
++# Check hardcoding attributes.
++# _LT_LINKER_HARDCODE_LIBPATH
++
++
++# _LT_CMD_STRIPLIB
++# ----------------
++# _LT_CMD_STRIPLIB
++
++
++# _LT_SYS_DYNAMIC_LINKER([TAG])
++# -----------------------------
++# PORTME Fill in your ld.so characteristics
++# _LT_SYS_DYNAMIC_LINKER
++
++
++# _LT_PATH_TOOL_PREFIX(TOOL)
++# --------------------------
++# find a file program which can recognize shared library
++# _LT_PATH_TOOL_PREFIX
++
++# Old name:
++# This is what autoupdate's m4 run will expand.  It fires
++# the warning (with _au_warn_XXX), outputs it into the
++# updated configure.ac (with AC_DIAGNOSE), and then outputs
++# the replacement expansion.
++
++
++# This is an auxiliary macro that is also run when
++# autoupdate runs m4.  It simply calls m4_warning, but
++# we need a wrapper so that each warning is emitted only
++# once.  We break the quoting in m4_warning's argument in
++# order to expand this macro's arguments, not AU_DEFUN's.
++
++
++# Finally, this is the expansion that is picked up by
++# autoconf.  It tells the user to run autoupdate, and
++# then outputs the replacement expansion.  We do not care
++# about autoupdate's warning because that contains
++# information on what to do *after* running autoupdate.
++
++
++
++# _LT_PATH_MAGIC
++# --------------
++# find a file program which can recognize a shared library
++# _LT_PATH_MAGIC
++
++
++# LT_PATH_LD
++# ----------
++# find the pathname to the GNU or non-GNU linker
++# LT_PATH_LD
++
++# Old names:
++# This is what autoupdate's m4 run will expand.  It fires
++# the warning (with _au_warn_XXX), outputs it into the
++# updated configure.ac (with AC_DIAGNOSE), and then outputs
++# the replacement expansion.
++
++
++# This is an auxiliary macro that is also run when
++# autoupdate runs m4.  It simply calls m4_warning, but
++# we need a wrapper so that each warning is emitted only
++# once.  We break the quoting in m4_warning's argument in
++# order to expand this macro's arguments, not AU_DEFUN's.
++
++
++# Finally, this is the expansion that is picked up by
++# autoconf.  It tells the user to run autoupdate, and
++# then outputs the replacement expansion.  We do not care
++# about autoupdate's warning because that contains
++# information on what to do *after* running autoupdate.
++
++# This is what autoupdate's m4 run will expand.  It fires
++# the warning (with _au_warn_XXX), outputs it into the
++# updated configure.ac (with AC_DIAGNOSE), and then outputs
++# the replacement expansion.
++
++
++# This is an auxiliary macro that is also run when
++# autoupdate runs m4.  It simply calls m4_warning, but
++# we need a wrapper so that each warning is emitted only
++# once.  We break the quoting in m4_warning's argument in
++# order to expand this macro's arguments, not AU_DEFUN's.
++
++
++# Finally, this is the expansion that is picked up by
++# autoconf.  It tells the user to run autoupdate, and
++# then outputs the replacement expansion.  We do not care
++# about autoupdate's warning because that contains
++# information on what to do *after* running autoupdate.
++
++
++
++# _LT_PATH_LD_GNU
++#- --------------
++# _LT_PATH_LD_GNU
++
++
++# _LT_CMD_RELOAD
++# --------------
++# find reload flag for linker
++#   -- PORTME Some linkers may need a different reload flag.
++# _LT_CMD_RELOAD
++
++
++# _LT_CHECK_MAGIC_METHOD
++# ----------------------
++# how to check for library dependencies
++#  -- PORTME fill in with the dynamic library characteristics
++# _LT_CHECK_MAGIC_METHOD
++
++
++# LT_PATH_NM
++# ----------
++# find the pathname to a BSD- or MS-compatible name lister
++# LT_PATH_NM
++
++# Old names:
++# This is what autoupdate's m4 run will expand.  It fires
++# the warning (with _au_warn_XXX), outputs it into the
++# updated configure.ac (with AC_DIAGNOSE), and then outputs
++# the replacement expansion.
++
++
++# This is an auxiliary macro that is also run when
++# autoupdate runs m4.  It simply calls m4_warning, but
++# we need a wrapper so that each warning is emitted only
++# once.  We break the quoting in m4_warning's argument in
++# order to expand this macro's arguments, not AU_DEFUN's.
++
++
++# Finally, this is the expansion that is picked up by
++# autoconf.  It tells the user to run autoupdate, and
++# then outputs the replacement expansion.  We do not care
++# about autoupdate's warning because that contains
++# information on what to do *after* running autoupdate.
++
++# This is what autoupdate's m4 run will expand.  It fires
++# the warning (with _au_warn_XXX), outputs it into the
++# updated configure.ac (with AC_DIAGNOSE), and then outputs
++# the replacement expansion.
++
++
++# This is an auxiliary macro that is also run when
++# autoupdate runs m4.  It simply calls m4_warning, but
++# we need a wrapper so that each warning is emitted only
++# once.  We break the quoting in m4_warning's argument in
++# order to expand this macro's arguments, not AU_DEFUN's.
++
++
++# Finally, this is the expansion that is picked up by
++# autoconf.  It tells the user to run autoupdate, and
++# then outputs the replacement expansion.  We do not care
++# about autoupdate's warning because that contains
++# information on what to do *after* running autoupdate.
++
++
++
++# LT_LIB_M
++# --------
++# check for math library
++# LT_LIB_M
++
++# Old name:
++# This is what autoupdate's m4 run will expand.  It fires
++# the warning (with _au_warn_XXX), outputs it into the
++# updated configure.ac (with AC_DIAGNOSE), and then outputs
++# the replacement expansion.
++
++
++# This is an auxiliary macro that is also run when
++# autoupdate runs m4.  It simply calls m4_warning, but
++# we need a wrapper so that each warning is emitted only
++# once.  We break the quoting in m4_warning's argument in
++# order to expand this macro's arguments, not AU_DEFUN's.
++
++
++# Finally, this is the expansion that is picked up by
++# autoconf.  It tells the user to run autoupdate, and
++# then outputs the replacement expansion.  We do not care
++# about autoupdate's warning because that contains
++# information on what to do *after* running autoupdate.
++
++
++
++# _LT_COMPILER_NO_RTTI([TAGNAME])
++# -------------------------------
++# _LT_COMPILER_NO_RTTI
++
++
++# _LT_CMD_GLOBAL_SYMBOLS
++# ----------------------
++ # _LT_CMD_GLOBAL_SYMBOLS
++
++
++# _LT_COMPILER_PIC([TAGNAME])
++# ---------------------------
++# _LT_COMPILER_PIC
++
++
++# _LT_LINKER_SHLIBS([TAGNAME])
++# ----------------------------
++# See if the linker supports building shared libraries.
++# _LT_LINKER_SHLIBS
++
++
++# _LT_LANG_C_CONFIG([TAG])
++# ------------------------
++# Ensure that the configuration variables for a C compiler are suitably
++# defined.  These variables are subsequently used by _LT_CONFIG to write
++# the compiler configuration to `libtool'.
++# _LT_LANG_C_CONFIG
++
++
++# _LT_LANG_CXX_CONFIG([TAG])
++# --------------------------
++# Ensure that the configuration variables for a C++ compiler are suitably
++# defined.  These variables are subsequently used by _LT_CONFIG to write
++# the compiler configuration to `libtool'.
++# _LT_LANG_CXX_CONFIG
++
++
++# _LT_SYS_HIDDEN_LIBDEPS([TAGNAME])
++# ---------------------------------
++# Figure out "hidden" library dependencies from verbose
++# compiler output when linking a shared library.
++# Parse the compiler output and extract the necessary
++# objects, libraries and library flags.
++# _LT_SYS_HIDDEN_LIBDEPS
++
++
++# _LT_LANG_F77_CONFIG([TAG])
++# --------------------------
++# Ensure that the configuration variables for a Fortran 77 compiler are
++# suitably defined.  These variables are subsequently used by _LT_CONFIG
++# to write the compiler configuration to `libtool'.
++# _LT_LANG_F77_CONFIG
++
++
++# _LT_LANG_FC_CONFIG([TAG])
++# -------------------------
++# Ensure that the configuration variables for a Fortran compiler are
++# suitably defined.  These variables are subsequently used by _LT_CONFIG
++# to write the compiler configuration to `libtool'.
++# _LT_LANG_FC_CONFIG
++
++
++# _LT_LANG_GCJ_CONFIG([TAG])
++# --------------------------
++# Ensure that the configuration variables for the GNU Java Compiler compiler
++# are suitably defined.  These variables are subsequently used by _LT_CONFIG
++# to write the compiler configuration to `libtool'.
++# _LT_LANG_GCJ_CONFIG
++
++
++# _LT_LANG_RC_CONFIG([TAG])
++# -------------------------
++# Ensure that the configuration variables for the Windows resource compiler
++# are suitably defined.  These variables are subsequently used by _LT_CONFIG
++# to write the compiler configuration to `libtool'.
++# _LT_LANG_RC_CONFIG
++
++
++# LT_PROG_GCJ
++# -----------
++
++
++# Old name:
++# This is what autoupdate's m4 run will expand.  It fires
++# the warning (with _au_warn_XXX), outputs it into the
++# updated configure.ac (with AC_DIAGNOSE), and then outputs
++# the replacement expansion.
++
++
++# This is an auxiliary macro that is also run when
++# autoupdate runs m4.  It simply calls m4_warning, but
++# we need a wrapper so that each warning is emitted only
++# once.  We break the quoting in m4_warning's argument in
++# order to expand this macro's arguments, not AU_DEFUN's.
++
++
++# Finally, this is the expansion that is picked up by
++# autoconf.  It tells the user to run autoupdate, and
++# then outputs the replacement expansion.  We do not care
++# about autoupdate's warning because that contains
++# information on what to do *after* running autoupdate.
++
++
++
++# LT_PROG_RC
++# ----------
++
++
++# Old name:
++# This is what autoupdate's m4 run will expand.  It fires
++# the warning (with _au_warn_XXX), outputs it into the
++# updated configure.ac (with AC_DIAGNOSE), and then outputs
++# the replacement expansion.
++
++
++# This is an auxiliary macro that is also run when
++# autoupdate runs m4.  It simply calls m4_warning, but
++# we need a wrapper so that each warning is emitted only
++# once.  We break the quoting in m4_warning's argument in
++# order to expand this macro's arguments, not AU_DEFUN's.
++
++
++# Finally, this is the expansion that is picked up by
++# autoconf.  It tells the user to run autoupdate, and
++# then outputs the replacement expansion.  We do not care
++# about autoupdate's warning because that contains
++# information on what to do *after* running autoupdate.
++
++
++
++# _LT_DECL_EGREP
++# --------------
++# If we don't have a new enough Autoconf to choose the best grep
++# available, choose the one first in the user's PATH.
++
++
++
++# _LT_DECL_OBJDUMP
++# --------------
++# If we don't have a new enough Autoconf to choose the best objdump
++# available, choose the one first in the user's PATH.
++
++
++
++# _LT_DECL_SED
++# ------------
++# Check for a fully-functional sed program, that truncates
++# as few characters as possible.  Prefer GNU sed if found.
++# _LT_DECL_SED
++
++#m4_ifndef
++
++# Old name:
++# This is what autoupdate's m4 run will expand.  It fires
++# the warning (with _au_warn_XXX), outputs it into the
++# updated configure.ac (with AC_DIAGNOSE), and then outputs
++# the replacement expansion.
++
++
++# This is an auxiliary macro that is also run when
++# autoupdate runs m4.  It simply calls m4_warning, but
++# we need a wrapper so that each warning is emitted only
++# once.  We break the quoting in m4_warning's argument in
++# order to expand this macro's arguments, not AU_DEFUN's.
++
++
++# Finally, this is the expansion that is picked up by
++# autoconf.  It tells the user to run autoupdate, and
++# then outputs the replacement expansion.  We do not care
++# about autoupdate's warning because that contains
++# information on what to do *after* running autoupdate.
++
++
++
++# _LT_CHECK_SHELL_FEATURES
++# ------------------------
++# Find out whether the shell is Bourne or XSI compatible,
++# or has some other useful features.
++# _LT_CHECK_SHELL_FEATURES
++
++
++# _LT_PROG_XSI_SHELLFNS
++# ---------------------
++# Bourne and XSI compatible variants of some useful shell functions.
++
++
++# Helper functions for option handling.                    -*- Autoconf -*-
++#
++#   Copyright (C) 2004, 2005, 2007, 2008, 2009 Free Software Foundation,
++#   Inc.
++#   Written by Gary V. Vaughan, 2004
++#
++# This file is free software; the Free Software Foundation gives
++# unlimited permission to copy and/or distribute it, with or without
++# modifications, as long as this notice is preserved.
++
++# serial 6 ltoptions.m4
++
++# This is to help aclocal find these macros, as it can't see m4_define.
++
++
++
++# _LT_MANGLE_OPTION(MACRO-NAME, OPTION-NAME)
++# ------------------------------------------
++
++
++
++# _LT_SET_OPTION(MACRO-NAME, OPTION-NAME)
++# ---------------------------------------
++# Set option OPTION-NAME for macro MACRO-NAME, and if there is a
++# matching handler defined, dispatch to it.  Other OPTION-NAMEs are
++# saved as a flag.
++
++
++
++# _LT_IF_OPTION(MACRO-NAME, OPTION-NAME, IF-SET, [IF-NOT-SET])
++# ------------------------------------------------------------
++# Execute IF-SET if OPTION is set, IF-NOT-SET otherwise.
++
++
++
++# _LT_UNLESS_OPTIONS(MACRO-NAME, OPTION-LIST, IF-NOT-SET)
++# -------------------------------------------------------
++# Execute IF-NOT-SET unless all options in OPTION-LIST for MACRO-NAME
++# are set.
++
++
++
++# _LT_SET_OPTIONS(MACRO-NAME, OPTION-LIST)
++# ----------------------------------------
++# OPTION-LIST is a space-separated list of Libtool options associated
++# with MACRO-NAME.  If any OPTION has a matching handler declared with
++# LT_OPTION_DEFINE, dispatch to that macro; otherwise complain about
++# the unknown option and exit.
++# _LT_SET_OPTIONS
++
++
++## --------------------------------- ##
++## Macros to handle LT_INIT options. ##
++## --------------------------------- ##
++
++# _LT_MANGLE_DEFUN(MACRO-NAME, OPTION-NAME)
++# -----------------------------------------
++
++
++
++# LT_OPTION_DEFINE(MACRO-NAME, OPTION-NAME, CODE)
++# -----------------------------------------------
++# LT_OPTION_DEFINE
++
++
++# dlopen
++# ------
++
++
++# This is what autoupdate's m4 run will expand.  It fires
++# the warning (with _au_warn_XXX), outputs it into the
++# updated configure.ac (with AC_DIAGNOSE), and then outputs
++# the replacement expansion.
++
++
++# This is an auxiliary macro that is also run when
++# autoupdate runs m4.  It simply calls m4_warning, but
++# we need a wrapper so that each warning is emitted only
++# once.  We break the quoting in m4_warning's argument in
++# order to expand this macro's arguments, not AU_DEFUN's.
++
++
++# Finally, this is the expansion that is picked up by
++# autoconf.  It tells the user to run autoupdate, and
++# then outputs the replacement expansion.  We do not care
++# about autoupdate's warning because that contains
++# information on what to do *after* running autoupdate.
++
++
++
++
++# win32-dll
++# ---------
++# Declare package support for building win32 dll's.
++# win32-dll
++
++# This is what autoupdate's m4 run will expand.  It fires
++# the warning (with _au_warn_XXX), outputs it into the
++# updated configure.ac (with AC_DIAGNOSE), and then outputs
++# the replacement expansion.
++
++
++# This is an auxiliary macro that is also run when
++# autoupdate runs m4.  It simply calls m4_warning, but
++# we need a wrapper so that each warning is emitted only
++# once.  We break the quoting in m4_warning's argument in
++# order to expand this macro's arguments, not AU_DEFUN's.
++
++
++# Finally, this is the expansion that is picked up by
++# autoconf.  It tells the user to run autoupdate, and
++# then outputs the replacement expansion.  We do not care
++# about autoupdate's warning because that contains
++# information on what to do *after* running autoupdate.
++
++
++
++
++# _LT_ENABLE_SHARED([DEFAULT])
++# ----------------------------
++# implement the --enable-shared flag, and supports the `shared' and
++# `disable-shared' LT_INIT options.
++# DEFAULT is either `yes' or `no'.  If omitted, it defaults to `yes'.
++# _LT_ENABLE_SHARED
++
++
++
++
++# Old names:
++
++
++
++
++# This is what autoupdate's m4 run will expand.  It fires
++# the warning (with _au_warn_XXX), outputs it into the
++# updated configure.ac (with AC_DIAGNOSE), and then outputs
++# the replacement expansion.
++
++
++# This is an auxiliary macro that is also run when
++# autoupdate runs m4.  It simply calls m4_warning, but
++# we need a wrapper so that each warning is emitted only
++# once.  We break the quoting in m4_warning's argument in
++# order to expand this macro's arguments, not AU_DEFUN's.
++
++
++# Finally, this is the expansion that is picked up by
++# autoconf.  It tells the user to run autoupdate, and
++# then outputs the replacement expansion.  We do not care
++# about autoupdate's warning because that contains
++# information on what to do *after* running autoupdate.
++
++# This is what autoupdate's m4 run will expand.  It fires
++# the warning (with _au_warn_XXX), outputs it into the
++# updated configure.ac (with AC_DIAGNOSE), and then outputs
++# the replacement expansion.
++
++
++# This is an auxiliary macro that is also run when
++# autoupdate runs m4.  It simply calls m4_warning, but
++# we need a wrapper so that each warning is emitted only
++# once.  We break the quoting in m4_warning's argument in
++# order to expand this macro's arguments, not AU_DEFUN's.
++
++
++# Finally, this is the expansion that is picked up by
++# autoconf.  It tells the user to run autoupdate, and
++# then outputs the replacement expansion.  We do not care
++# about autoupdate's warning because that contains
++# information on what to do *after* running autoupdate.
++
++
++
++
++
++# _LT_ENABLE_STATIC([DEFAULT])
++# ----------------------------
++# implement the --enable-static flag, and support the `static' and
++# `disable-static' LT_INIT options.
++# DEFAULT is either `yes' or `no'.  If omitted, it defaults to `yes'.
++# _LT_ENABLE_STATIC
++
++
++
++
++# Old names:
++
++
++
++
++# This is what autoupdate's m4 run will expand.  It fires
++# the warning (with _au_warn_XXX), outputs it into the
++# updated configure.ac (with AC_DIAGNOSE), and then outputs
++# the replacement expansion.
++
++
++# This is an auxiliary macro that is also run when
++# autoupdate runs m4.  It simply calls m4_warning, but
++# we need a wrapper so that each warning is emitted only
++# once.  We break the quoting in m4_warning's argument in
++# order to expand this macro's arguments, not AU_DEFUN's.
++
++
++# Finally, this is the expansion that is picked up by
++# autoconf.  It tells the user to run autoupdate, and
++# then outputs the replacement expansion.  We do not care
++# about autoupdate's warning because that contains
++# information on what to do *after* running autoupdate.
++
++# This is what autoupdate's m4 run will expand.  It fires
++# the warning (with _au_warn_XXX), outputs it into the
++# updated configure.ac (with AC_DIAGNOSE), and then outputs
++# the replacement expansion.
++
++
++# This is an auxiliary macro that is also run when
++# autoupdate runs m4.  It simply calls m4_warning, but
++# we need a wrapper so that each warning is emitted only
++# once.  We break the quoting in m4_warning's argument in
++# order to expand this macro's arguments, not AU_DEFUN's.
++
++
++# Finally, this is the expansion that is picked up by
++# autoconf.  It tells the user to run autoupdate, and
++# then outputs the replacement expansion.  We do not care
++# about autoupdate's warning because that contains
++# information on what to do *after* running autoupdate.
++
++
++
++
++
++# _LT_ENABLE_FAST_INSTALL([DEFAULT])
++# ----------------------------------
++# implement the --enable-fast-install flag, and support the `fast-install'
++# and `disable-fast-install' LT_INIT options.
++# DEFAULT is either `yes' or `no'.  If omitted, it defaults to `yes'.
++# _LT_ENABLE_FAST_INSTALL
++
++
++
++
++# Old names:
++# This is what autoupdate's m4 run will expand.  It fires
++# the warning (with _au_warn_XXX), outputs it into the
++# updated configure.ac (with AC_DIAGNOSE), and then outputs
++# the replacement expansion.
++
++
++# This is an auxiliary macro that is also run when
++# autoupdate runs m4.  It simply calls m4_warning, but
++# we need a wrapper so that each warning is emitted only
++# once.  We break the quoting in m4_warning's argument in
++# order to expand this macro's arguments, not AU_DEFUN's.
++
++
++# Finally, this is the expansion that is picked up by
++# autoconf.  It tells the user to run autoupdate, and
++# then outputs the replacement expansion.  We do not care
++# about autoupdate's warning because that contains
++# information on what to do *after* running autoupdate.
++
++
++# This is what autoupdate's m4 run will expand.  It fires
++# the warning (with _au_warn_XXX), outputs it into the
++# updated configure.ac (with AC_DIAGNOSE), and then outputs
++# the replacement expansion.
++
++
++# This is an auxiliary macro that is also run when
++# autoupdate runs m4.  It simply calls m4_warning, but
++# we need a wrapper so that each warning is emitted only
++# once.  We break the quoting in m4_warning's argument in
++# order to expand this macro's arguments, not AU_DEFUN's.
++
++
++# Finally, this is the expansion that is picked up by
++# autoconf.  It tells the user to run autoupdate, and
++# then outputs the replacement expansion.  We do not care
++# about autoupdate's warning because that contains
++# information on what to do *after* running autoupdate.
++
++
++
++
++# _LT_WITH_PIC([MODE])
++# --------------------
++# implement the --with-pic flag, and support the `pic-only' and `no-pic'
++# LT_INIT options.
++# MODE is either `yes' or `no'.  If omitted, it defaults to `both'.
++# _LT_WITH_PIC
++
++
++
++
++# Old name:
++# This is what autoupdate's m4 run will expand.  It fires
++# the warning (with _au_warn_XXX), outputs it into the
++# updated configure.ac (with AC_DIAGNOSE), and then outputs
++# the replacement expansion.
++
++
++# This is an auxiliary macro that is also run when
++# autoupdate runs m4.  It simply calls m4_warning, but
++# we need a wrapper so that each warning is emitted only
++# once.  We break the quoting in m4_warning's argument in
++# order to expand this macro's arguments, not AU_DEFUN's.
++
++
++# Finally, this is the expansion that is picked up by
++# autoconf.  It tells the user to run autoupdate, and
++# then outputs the replacement expansion.  We do not care
++# about autoupdate's warning because that contains
++# information on what to do *after* running autoupdate.
++
++
++
++## ----------------- ##
++## LTDL_INIT Options ##
++## ----------------- ##
++
++
++
++
++
++
++
++
++
++
++# ltsugar.m4 -- libtool m4 base layer.                         -*-Autoconf-*-
++#
++# Copyright (C) 2004, 2005, 2007, 2008 Free Software Foundation, Inc.
++# Written by Gary V. Vaughan, 2004
++#
++# This file is free software; the Free Software Foundation gives
++# unlimited permission to copy and/or distribute it, with or without
++# modifications, as long as this notice is preserved.
++
++# serial 6 ltsugar.m4
++
++# This is to help aclocal find these macros, as it can't see m4_define.
++
++
++
++# lt_join(SEP, ARG1, [ARG2...])
++# -----------------------------
++# Produce ARG1SEPARG2...SEPARGn, omitting [] arguments and their
++# associated separator.
++# Needed until we can rely on m4_join from Autoconf 2.62, since all earlier
++# versions in m4sugar had bugs.
++
++
++
++
++# lt_car(LIST)
++# lt_cdr(LIST)
++# ------------
++# Manipulate m4 lists.
++# These macros are necessary as long as will still need to support
++# Autoconf-2.59 which quotes differently.
++
++
++
++
++
++# lt_append(MACRO-NAME, STRING, [SEPARATOR])
++# ------------------------------------------
++# Redefine MACRO-NAME to hold its former content plus `SEPARATOR'`STRING'.
++# Note that neither SEPARATOR nor STRING are expanded; they are appended
++# to MACRO-NAME as is (leaving the expansion for when MACRO-NAME is invoked).
++# No SEPARATOR is output if MACRO-NAME was previously undefined (different
++# than defined and empty).
++#
++# This macro is needed until we can rely on Autoconf 2.62, since earlier
++# versions of m4sugar mistakenly expanded SEPARATOR but not STRING.
++
++
++
++
++# lt_combine(SEP, PREFIX-LIST, INFIX, SUFFIX1, [SUFFIX2...])
++# ----------------------------------------------------------
++# Produce a SEP delimited list of all paired combinations of elements of
++# PREFIX-LIST with SUFFIX1 through SUFFIXn.  Each element of the list
++# has the form PREFIXmINFIXSUFFIXn.
++# Needed until we can rely on m4_combine added in Autoconf 2.62.
++
++
++
++# lt_if_append_uniq(MACRO-NAME, VARNAME, [SEPARATOR], [UNIQ], [NOT-UNIQ])
++# -----------------------------------------------------------------------
++# Iff MACRO-NAME does not yet contain VARNAME, then append it (delimited
++# by SEPARATOR if supplied) and expand UNIQ, else NOT-UNIQ.
++
++
++
++# lt_dict_add(DICT, KEY, VALUE)
++# -----------------------------
++
++
++
++# lt_dict_add_subkey(DICT, KEY, SUBKEY, VALUE)
++# --------------------------------------------
++
++
++
++# lt_dict_fetch(DICT, KEY, [SUBKEY])
++# ----------------------------------
++
++
++
++# lt_if_dict_fetch(DICT, KEY, [SUBKEY], VALUE, IF-TRUE, [IF-FALSE])
++# -----------------------------------------------------------------
++
++
++
++# lt_dict_filter(DICT, [SUBKEY], VALUE, [SEPARATOR], KEY, [...])
++# --------------------------------------------------------------
++
++
++# ltversion.m4 -- version numbers			-*- Autoconf -*-
++#
++#   Copyright (C) 2004 Free Software Foundation, Inc.
++#   Written by Scott James Remnant, 2004
++#
++# This file is free software; the Free Software Foundation gives
++# unlimited permission to copy and/or distribute it, with or without
++# modifications, as long as this notice is preserved.
++
++# Generated from ltversion.in.
++
++# serial 3134 ltversion.m4
++# This file is part of GNU Libtool
++
++
++
++
++
++
++# lt~obsolete.m4 -- aclocal satisfying obsolete definitions.    -*-Autoconf-*-
++#
++#   Copyright (C) 2004, 2005, 2007, 2009 Free Software Foundation, Inc.
++#   Written by Scott James Remnant, 2004.
++#
++# This file is free software; the Free Software Foundation gives
++# unlimited permission to copy and/or distribute it, with or without
++# modifications, as long as this notice is preserved.
++
++# serial 4 lt~obsolete.m4
++
++# These exist entirely to fool aclocal when bootstrapping libtool.
++#
++# In the past libtool.m4 has provided macros via AC_DEFUN (or AU_DEFUN)
++# which have later been changed to m4_define as they aren't part of the
++# exported API, or moved to Autoconf or Automake where they belong.
++#
++# The trouble is, aclocal is a bit thick.  It'll see the old AC_DEFUN
++# in /usr/share/aclocal/libtool.m4 and remember it, then when it sees us
++# using a macro with the same name in our local m4/libtool.m4 it'll
++# pull the old libtool.m4 in (it doesn't see our shiny new m4_define
++# and doesn't know about Autoconf macros at all.)
++#
++# So we provide this file, which has a silly filename so it's always
++# included after everything else.  This provides aclocal with the
++# AC_DEFUNs it wants, but when m4 processes it, it doesn't do anything
++# because those macros already exist, or will be overwritten later.
++# We use AC_DEFUN over AU_DEFUN for compatibility with aclocal-1.6.
++#
++# Anytime we withdraw an AC_DEFUN or AU_DEFUN, remember to add it here.
++# Yes, that means every name once taken will need to remain here until
++# we give up compatibility with versions before 1.7, at which point
++# we need to keep only those names which we still refer to.
++
++# This is to help aclocal find these macros, as it can't see m4_define.
++
++
++
++
++
++
++
++
++
++
++
++
++
++
++
++
++
++
++
++
++
++
++
++
++
++
++
++
++
++
++
++
++
++
++
++
++
++
++
++
++
++
++
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++
++
++
++
++
++
++
++
++
++
++
++
++
++
++
++
++
++
++
++
++##                                                          -*- Autoconf -*-
++
++# Copyright (C) 1999, 2000, 2001, 2002, 2003, 2004, 2005, 2007
++# Free Software Foundation, Inc.
++#
++# This file is free software; the Free Software Foundation
++# gives unlimited permission to copy and/or distribute it,
++# with or without modifications, as long as this notice is preserved.
++
++# serial 8
++
++# Based on depend.m4 from automake 1.9, modified for standalone use in
++# an environment where GNU make is required.
++
++# ZW_PROG_COMPILER_DEPENDENCIES
++# -----------------------------
++# Variant of _AM_DEPENDENCIES which just does the dependency probe and
++# sets fooDEPMODE accordingly.  Cache-variable compatible with
++# original; not side-effect compatible.  As the users of this macro
++# may require accurate dependencies for correct builds, it does *not*
++# honor --disable-dependency-checking, and failure to detect a usable
++# method is an error.  depcomp is assumed to be located in
++# $ac_aux_dir.
++#
++# FIXME: Should use the Autoconf 2.5x language-selection mechanism.
++
++
++
++# AM_SET_DEPDIR
++# -------------
++# Choose a directory name for dependency files.
++
++
++# ZW_CREATE_DEPDIR
++# ----------------
++# As AM_SET_DEPDIR, but also create the directory at config.status time.
++
++
++
++
++
++
++
++
++
++
++
++
++
++
++
++
++
++
++
++
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++
++
++
++
++
++
++
++
++
++
++
++
++
++
++
++
++
++
++# intl sister-directory configuration rules.
++#
++
++# The idea behind this macro is that there's no need to repeat all the
++# autoconf probes done by the intl directory - it's already done them
++# for us.  In fact, there's no need even to look at the cache for the
++# answers.  All we need to do is nab a few pieces of information.
++# The intl directory is set up to make this easy, by generating a
++# small file which can be sourced as a shell script; then we produce
++# the necessary substitutions and definitions for this directory.
++
++
++
++# Autoconf M4 include file defining utility macros for complex Canadian
++# cross builds.
++
++
++
++
++
++
++
++
++
++####
++# _NCN_TOOL_PREFIXES:  Some stuff that oughtta be done in AC_CANONICAL_SYSTEM
++# or AC_INIT.
++# These demand that AC_CANONICAL_SYSTEM be called beforehand.
++
++####
++# NCN_STRICT_CHECK_TOOLS(variable, progs-to-check-for,[value-if-not-found],[path])
++# Like plain AC_CHECK_TOOLS, but require prefix if build!=host.
++
++
++####
++# NCN_STRICT_CHECK_TARGET_TOOLS(variable, progs-to-check-for,[value-if-not-found],[path])
++# Like CVS Autoconf AC_CHECK_TARGET_TOOLS, but require prefix if build!=target.
++
++
++
++# Backported from Autoconf 2.5x; can go away when and if
++# we switch.  Put the OS path separator in $PATH_SEPARATOR.
++
++
++
++
++
++
++
++
++# ACX_HAVE_GCC_FOR_TARGET
++# Check if the variable GCC_FOR_TARGET really points to a GCC binary.
++
++
++# ACX_CHECK_INSTALLED_TARGET_TOOL(VAR, PROG)
++# Searching for installed target binutils.  We need to take extra care,
++# else we may find the wrong assembler, linker, etc., and lose.
++#
++# First try --with-build-time-tools, if specified.
++#
++# For build != host, we ask the installed GCC for the name of the tool it
++# uses, and accept it if it is an absolute path.  This is because the
++# only good choice for a compiler is the same GCC version that is being
++# installed (or we couldn't make target libraries), and we assume that
++# on the host system we'll have not only the same GCC version, but also
++# the same binutils version.
++#
++# For build == host, search the same directories that the installed
++# compiler will search.  We used to do this for the assembler, linker,
++# and nm only; for simplicity of configuration, however, we extend this
++# criterion to tools (such as ar and ranlib) that are never invoked by
++# the compiler, to avoid mismatches.
++#
++# Also note we have to check MD_EXEC_PREFIX before checking the user's path
++# if build == target.  This makes the most sense only when bootstrapping,
++# but we also do so when build != host.  In this case, we hope that the
++# build and host systems will have similar contents of MD_EXEC_PREFIX.
++#
++# If we do not find a suitable binary, then try the user's path.
++
++
++###
++# AC_PROG_CPP_WERROR
++# Used for autoconf 2.5x to force AC_PREPROC_IFELSE to reject code which
++# triggers warnings from the preprocessor.  Will be in autoconf 2.58.
++# For now, using this also overrides header checks to use only the
++# preprocessor (matches 2.13 behavior; matching 2.58's behavior is a
++# bit harder from here).
++# Eventually autoconf will default to checking headers with the compiler
++# instead, and we'll have to do this differently.
++
++# AC_PROG_CPP_WERROR
++
++# Test for GNAT.
++# We require the gnatbind & gnatmake programs, as well as a compiler driver
++# that understands Ada.  We use the user's CC setting, already found, and
++# possibly add $1 to the command-line parameters.
++#
++# Sets the shell variable have_gnat to yes or no as appropriate, and
++# substitutes GNATBIND and GNATMAKE.
++
++
++
++
++
++
++
++
++
++
++
++
++
++
++
++
++
++
++
++
++
++
++
++
++
++ac_ext=c
++ac_cpp='$CPP $CPPFLAGS'
++ac_compile='$CC -c $CFLAGS $CPPFLAGS conftest.$ac_ext >&5'
++ac_link='$CC -o conftest$ac_exeext $CFLAGS $CPPFLAGS $LDFLAGS conftest.$ac_ext $LIBS >&5'
++ac_compiler_gnu=$ac_cv_c_compiler_gnu
++if test -n "$ac_tool_prefix"; then
++  # Extract the first word of "${ac_tool_prefix}gcc", so it can be a program name with args.
++set dummy ${ac_tool_prefix}gcc; ac_word=$2
++{ $as_echo "$as_me:${as_lineno-$LINENO}: checking for $ac_word" >&5
++$as_echo_n "checking for $ac_word... " >&6; }
++if ${ac_cv_prog_CC+:} false; then :
++  $as_echo_n "(cached) " >&6
++else
++  if test -n "$CC"; then
++  ac_cv_prog_CC="$CC" # Let the user override the test.
++else
++as_save_IFS=$IFS; IFS=$PATH_SEPARATOR
++for as_dir in $PATH
++do
++  IFS=$as_save_IFS
++  test -z "$as_dir" && as_dir=.
++    for ac_exec_ext in '' $ac_executable_extensions; do
++  if as_fn_executable_p "$as_dir/$ac_word$ac_exec_ext"; then
++    ac_cv_prog_CC="${ac_tool_prefix}gcc"
++    $as_echo "$as_me:${as_lineno-$LINENO}: found $as_dir/$ac_word$ac_exec_ext" >&5
++    break 2
++  fi
++done
++  done
++IFS=$as_save_IFS
++
++fi
++fi
++CC=$ac_cv_prog_CC
++if test -n "$CC"; then
++  { $as_echo "$as_me:${as_lineno-$LINENO}: result: $CC" >&5
++$as_echo "$CC" >&6; }
++else
++  { $as_echo "$as_me:${as_lineno-$LINENO}: result: no" >&5
++$as_echo "no" >&6; }
++fi
++
++
++fi
++if test -z "$ac_cv_prog_CC"; then
++  ac_ct_CC=$CC
++  # Extract the first word of "gcc", so it can be a program name with args.
++set dummy gcc; ac_word=$2
++{ $as_echo "$as_me:${as_lineno-$LINENO}: checking for $ac_word" >&5
++$as_echo_n "checking for $ac_word... " >&6; }
++if ${ac_cv_prog_ac_ct_CC+:} false; then :
++  $as_echo_n "(cached) " >&6
++else
++  if test -n "$ac_ct_CC"; then
++  ac_cv_prog_ac_ct_CC="$ac_ct_CC" # Let the user override the test.
++else
++as_save_IFS=$IFS; IFS=$PATH_SEPARATOR
++for as_dir in $PATH
++do
++  IFS=$as_save_IFS
++  test -z "$as_dir" && as_dir=.
++    for ac_exec_ext in '' $ac_executable_extensions; do
++  if as_fn_executable_p "$as_dir/$ac_word$ac_exec_ext"; then
++    ac_cv_prog_ac_ct_CC="gcc"
++    $as_echo "$as_me:${as_lineno-$LINENO}: found $as_dir/$ac_word$ac_exec_ext" >&5
++    break 2
++  fi
++done
++  done
++IFS=$as_save_IFS
++
++fi
++fi
++ac_ct_CC=$ac_cv_prog_ac_ct_CC
++if test -n "$ac_ct_CC"; then
++  { $as_echo "$as_me:${as_lineno-$LINENO}: result: $ac_ct_CC" >&5
++$as_echo "$ac_ct_CC" >&6; }
++else
++  { $as_echo "$as_me:${as_lineno-$LINENO}: result: no" >&5
++$as_echo "no" >&6; }
++fi
++
++  if test "x$ac_ct_CC" = x; then
++    CC=""
++  else
++    case $cross_compiling:$ac_tool_warned in
++yes:)
++{ $as_echo "$as_me:${as_lineno-$LINENO}: WARNING: using cross tools not prefixed with host triplet" >&5
++$as_echo "$as_me: WARNING: using cross tools not prefixed with host triplet" >&2;}
++ac_tool_warned=yes ;;
++esac
++    CC=$ac_ct_CC
++  fi
++else
++  CC="$ac_cv_prog_CC"
++fi
++
++if test -z "$CC"; then
++          if test -n "$ac_tool_prefix"; then
++    # Extract the first word of "${ac_tool_prefix}cc", so it can be a program name with args.
++set dummy ${ac_tool_prefix}cc; ac_word=$2
++{ $as_echo "$as_me:${as_lineno-$LINENO}: checking for $ac_word" >&5
++$as_echo_n "checking for $ac_word... " >&6; }
++if ${ac_cv_prog_CC+:} false; then :
++  $as_echo_n "(cached) " >&6
++else
++  if test -n "$CC"; then
++  ac_cv_prog_CC="$CC" # Let the user override the test.
++else
++as_save_IFS=$IFS; IFS=$PATH_SEPARATOR
++for as_dir in $PATH
++do
++  IFS=$as_save_IFS
++  test -z "$as_dir" && as_dir=.
++    for ac_exec_ext in '' $ac_executable_extensions; do
++  if as_fn_executable_p "$as_dir/$ac_word$ac_exec_ext"; then
++    ac_cv_prog_CC="${ac_tool_prefix}cc"
++    $as_echo "$as_me:${as_lineno-$LINENO}: found $as_dir/$ac_word$ac_exec_ext" >&5
++    break 2
++  fi
++done
++  done
++IFS=$as_save_IFS
++
++fi
++fi
++CC=$ac_cv_prog_CC
++if test -n "$CC"; then
++  { $as_echo "$as_me:${as_lineno-$LINENO}: result: $CC" >&5
++$as_echo "$CC" >&6; }
++else
++  { $as_echo "$as_me:${as_lineno-$LINENO}: result: no" >&5
++$as_echo "no" >&6; }
++fi
++
++
++  fi
++fi
++if test -z "$CC"; then
++  # Extract the first word of "cc", so it can be a program name with args.
++set dummy cc; ac_word=$2
++{ $as_echo "$as_me:${as_lineno-$LINENO}: checking for $ac_word" >&5
++$as_echo_n "checking for $ac_word... " >&6; }
++if ${ac_cv_prog_CC+:} false; then :
++  $as_echo_n "(cached) " >&6
++else
++  if test -n "$CC"; then
++  ac_cv_prog_CC="$CC" # Let the user override the test.
++else
++  ac_prog_rejected=no
++as_save_IFS=$IFS; IFS=$PATH_SEPARATOR
++for as_dir in $PATH
++do
++  IFS=$as_save_IFS
++  test -z "$as_dir" && as_dir=.
++    for ac_exec_ext in '' $ac_executable_extensions; do
++  if as_fn_executable_p "$as_dir/$ac_word$ac_exec_ext"; then
++    if test "$as_dir/$ac_word$ac_exec_ext" = "/usr/ucb/cc"; then
++       ac_prog_rejected=yes
++       continue
++     fi
++    ac_cv_prog_CC="cc"
++    $as_echo "$as_me:${as_lineno-$LINENO}: found $as_dir/$ac_word$ac_exec_ext" >&5
++    break 2
++  fi
++done
++  done
++IFS=$as_save_IFS
++
++if test $ac_prog_rejected = yes; then
++  # We found a bogon in the path, so make sure we never use it.
++  set dummy $ac_cv_prog_CC
++  shift
++  if test $# != 0; then
++    # We chose a different compiler from the bogus one.
++    # However, it has the same basename, so the bogon will be chosen
++    # first if we set CC to just the basename; use the full file name.
++    shift
++    ac_cv_prog_CC="$as_dir/$ac_word${1+' '}$@"
++  fi
++fi
++fi
++fi
++CC=$ac_cv_prog_CC
++if test -n "$CC"; then
++  { $as_echo "$as_me:${as_lineno-$LINENO}: result: $CC" >&5
++$as_echo "$CC" >&6; }
++else
++  { $as_echo "$as_me:${as_lineno-$LINENO}: result: no" >&5
++$as_echo "no" >&6; }
++fi
++
++
++fi
++if test -z "$CC"; then
++  if test -n "$ac_tool_prefix"; then
++  for ac_prog in cl.exe
++  do
++    # Extract the first word of "$ac_tool_prefix$ac_prog", so it can be a program name with args.
++set dummy $ac_tool_prefix$ac_prog; ac_word=$2
++{ $as_echo "$as_me:${as_lineno-$LINENO}: checking for $ac_word" >&5
++$as_echo_n "checking for $ac_word... " >&6; }
++if ${ac_cv_prog_CC+:} false; then :
++  $as_echo_n "(cached) " >&6
++else
++  if test -n "$CC"; then
++  ac_cv_prog_CC="$CC" # Let the user override the test.
++else
++as_save_IFS=$IFS; IFS=$PATH_SEPARATOR
++for as_dir in $PATH
++do
++  IFS=$as_save_IFS
++  test -z "$as_dir" && as_dir=.
++    for ac_exec_ext in '' $ac_executable_extensions; do
++  if as_fn_executable_p "$as_dir/$ac_word$ac_exec_ext"; then
++    ac_cv_prog_CC="$ac_tool_prefix$ac_prog"
++    $as_echo "$as_me:${as_lineno-$LINENO}: found $as_dir/$ac_word$ac_exec_ext" >&5
++    break 2
++  fi
++done
++  done
++IFS=$as_save_IFS
++
++fi
++fi
++CC=$ac_cv_prog_CC
++if test -n "$CC"; then
++  { $as_echo "$as_me:${as_lineno-$LINENO}: result: $CC" >&5
++$as_echo "$CC" >&6; }
++else
++  { $as_echo "$as_me:${as_lineno-$LINENO}: result: no" >&5
++$as_echo "no" >&6; }
++fi
++
++
++    test -n "$CC" && break
++  done
++fi
++if test -z "$CC"; then
++  ac_ct_CC=$CC
++  for ac_prog in cl.exe
++do
++  # Extract the first word of "$ac_prog", so it can be a program name with args.
++set dummy $ac_prog; ac_word=$2
++{ $as_echo "$as_me:${as_lineno-$LINENO}: checking for $ac_word" >&5
++$as_echo_n "checking for $ac_word... " >&6; }
++if ${ac_cv_prog_ac_ct_CC+:} false; then :
++  $as_echo_n "(cached) " >&6
++else
++  if test -n "$ac_ct_CC"; then
++  ac_cv_prog_ac_ct_CC="$ac_ct_CC" # Let the user override the test.
++else
++as_save_IFS=$IFS; IFS=$PATH_SEPARATOR
++for as_dir in $PATH
++do
++  IFS=$as_save_IFS
++  test -z "$as_dir" && as_dir=.
++    for ac_exec_ext in '' $ac_executable_extensions; do
++  if as_fn_executable_p "$as_dir/$ac_word$ac_exec_ext"; then
++    ac_cv_prog_ac_ct_CC="$ac_prog"
++    $as_echo "$as_me:${as_lineno-$LINENO}: found $as_dir/$ac_word$ac_exec_ext" >&5
++    break 2
++  fi
++done
++  done
++IFS=$as_save_IFS
++
++fi
++fi
++ac_ct_CC=$ac_cv_prog_ac_ct_CC
++if test -n "$ac_ct_CC"; then
++  { $as_echo "$as_me:${as_lineno-$LINENO}: result: $ac_ct_CC" >&5
++$as_echo "$ac_ct_CC" >&6; }
++else
++  { $as_echo "$as_me:${as_lineno-$LINENO}: result: no" >&5
++$as_echo "no" >&6; }
++fi
++
++
++  test -n "$ac_ct_CC" && break
++done
++
++  if test "x$ac_ct_CC" = x; then
++    CC=""
++  else
++    case $cross_compiling:$ac_tool_warned in
++yes:)
++{ $as_echo "$as_me:${as_lineno-$LINENO}: WARNING: using cross tools not prefixed with host triplet" >&5
++$as_echo "$as_me: WARNING: using cross tools not prefixed with host triplet" >&2;}
++ac_tool_warned=yes ;;
++esac
++    CC=$ac_ct_CC
++  fi
++fi
++
++fi
++
++
++test -z "$CC" && { { $as_echo "$as_me:${as_lineno-$LINENO}: error: in \`$ac_pwd':" >&5
++$as_echo "$as_me: error: in \`$ac_pwd':" >&2;}
++as_fn_error $? "no acceptable C compiler found in \$PATH
++See \`config.log' for more details" "$LINENO" 5; }
++
++# Provide some information about the compiler.
++$as_echo "$as_me:${as_lineno-$LINENO}: checking for C compiler version" >&5
++set X $ac_compile
++ac_compiler=$2
++for ac_option in --version -v -V -qversion; do
++  { { ac_try="$ac_compiler $ac_option >&5"
++case "(($ac_try" in
++  *\"* | *\`* | *\\*) ac_try_echo=\$ac_try;;
++  *) ac_try_echo=$ac_try;;
++esac
++eval ac_try_echo="\"\$as_me:${as_lineno-$LINENO}: $ac_try_echo\""
++$as_echo "$ac_try_echo"; } >&5
++  (eval "$ac_compiler $ac_option >&5") 2>conftest.err
++  ac_status=$?
++  if test -s conftest.err; then
++    sed '10a\
++... rest of stderr output deleted ...
++         10q' conftest.err >conftest.er1
++    cat conftest.er1 >&5
++  fi
++  rm -f conftest.er1 conftest.err
++  $as_echo "$as_me:${as_lineno-$LINENO}: \$? = $ac_status" >&5
++  test $ac_status = 0; }
++done
++
++cat confdefs.h - <<_ACEOF >conftest.$ac_ext
++/* end confdefs.h.  */
++
++int
++main ()
++{
++
++  ;
++  return 0;
++}
++_ACEOF
++ac_clean_files_save=$ac_clean_files
++ac_clean_files="$ac_clean_files a.out a.out.dSYM a.exe b.out"
++# Try to create an executable without -o first, disregard a.out.
++# It will help us diagnose broken compilers, and finding out an intuition
++# of exeext.
++{ $as_echo "$as_me:${as_lineno-$LINENO}: checking whether the C compiler works" >&5
++$as_echo_n "checking whether the C compiler works... " >&6; }
++ac_link_default=`$as_echo "$ac_link" | sed 's/ -o *conftest[^ ]*//'`
++
++# The possible output files:
++ac_files="a.out conftest.exe conftest a.exe a_out.exe b.out conftest.*"
++
++ac_rmfiles=
++for ac_file in $ac_files
++do
++  case $ac_file in
++    *.$ac_ext | *.xcoff | *.tds | *.d | *.pdb | *.xSYM | *.bb | *.bbg | *.map | *.inf | *.dSYM | *.o | *.obj ) ;;
++    * ) ac_rmfiles="$ac_rmfiles $ac_file";;
++  esac
++done
++rm -f $ac_rmfiles
++
++if { { ac_try="$ac_link_default"
++case "(($ac_try" in
++  *\"* | *\`* | *\\*) ac_try_echo=\$ac_try;;
++  *) ac_try_echo=$ac_try;;
++esac
++eval ac_try_echo="\"\$as_me:${as_lineno-$LINENO}: $ac_try_echo\""
++$as_echo "$ac_try_echo"; } >&5
++  (eval "$ac_link_default") 2>&5
++  ac_status=$?
++  $as_echo "$as_me:${as_lineno-$LINENO}: \$? = $ac_status" >&5
++  test $ac_status = 0; }; then :
++  # Autoconf-2.13 could set the ac_cv_exeext variable to `no'.
++# So ignore a value of `no', otherwise this would lead to `EXEEXT = no'
++# in a Makefile.  We should not override ac_cv_exeext if it was cached,
++# so that the user can short-circuit this test for compilers unknown to
++# Autoconf.
++for ac_file in $ac_files ''
++do
++  test -f "$ac_file" || continue
++  case $ac_file in
++    *.$ac_ext | *.xcoff | *.tds | *.d | *.pdb | *.xSYM | *.bb | *.bbg | *.map | *.inf | *.dSYM | *.o | *.obj )
++	;;
++    [ab].out )
++	# We found the default executable, but exeext='' is most
++	# certainly right.
++	break;;
++    *.* )
++	if test "${ac_cv_exeext+set}" = set && test "$ac_cv_exeext" != no;
++	then :; else
++	   ac_cv_exeext=`expr "$ac_file" : '[^.]*\(\..*\)'`
++	fi
++	# We set ac_cv_exeext here because the later test for it is not
++	# safe: cross compilers may not add the suffix if given an `-o'
++	# argument, so we may need to know it at that point already.
++	# Even if this section looks crufty: it has the advantage of
++	# actually working.
++	break;;
++    * )
++	break;;
++  esac
++done
++test "$ac_cv_exeext" = no && ac_cv_exeext=
++
++else
++  ac_file=''
++fi
++if test -z "$ac_file"; then :
++  { $as_echo "$as_me:${as_lineno-$LINENO}: result: no" >&5
++$as_echo "no" >&6; }
++$as_echo "$as_me: failed program was:" >&5
++sed 's/^/| /' conftest.$ac_ext >&5
++
++{ { $as_echo "$as_me:${as_lineno-$LINENO}: error: in \`$ac_pwd':" >&5
++$as_echo "$as_me: error: in \`$ac_pwd':" >&2;}
++as_fn_error 77 "C compiler cannot create executables
++See \`config.log' for more details" "$LINENO" 5; }
++else
++  { $as_echo "$as_me:${as_lineno-$LINENO}: result: yes" >&5
++$as_echo "yes" >&6; }
++fi
++{ $as_echo "$as_me:${as_lineno-$LINENO}: checking for C compiler default output file name" >&5
++$as_echo_n "checking for C compiler default output file name... " >&6; }
++{ $as_echo "$as_me:${as_lineno-$LINENO}: result: $ac_file" >&5
++$as_echo "$ac_file" >&6; }
++ac_exeext=$ac_cv_exeext
++
++rm -f -r a.out a.out.dSYM a.exe conftest$ac_cv_exeext b.out
++ac_clean_files=$ac_clean_files_save
++{ $as_echo "$as_me:${as_lineno-$LINENO}: checking for suffix of executables" >&5
++$as_echo_n "checking for suffix of executables... " >&6; }
++if { { ac_try="$ac_link"
++case "(($ac_try" in
++  *\"* | *\`* | *\\*) ac_try_echo=\$ac_try;;
++  *) ac_try_echo=$ac_try;;
++esac
++eval ac_try_echo="\"\$as_me:${as_lineno-$LINENO}: $ac_try_echo\""
++$as_echo "$ac_try_echo"; } >&5
++  (eval "$ac_link") 2>&5
++  ac_status=$?
++  $as_echo "$as_me:${as_lineno-$LINENO}: \$? = $ac_status" >&5
++  test $ac_status = 0; }; then :
++  # If both `conftest.exe' and `conftest' are `present' (well, observable)
++# catch `conftest.exe'.  For instance with Cygwin, `ls conftest' will
++# work properly (i.e., refer to `conftest.exe'), while it won't with
++# `rm'.
++for ac_file in conftest.exe conftest conftest.*; do
++  test -f "$ac_file" || continue
++  case $ac_file in
++    *.$ac_ext | *.xcoff | *.tds | *.d | *.pdb | *.xSYM | *.bb | *.bbg | *.map | *.inf | *.dSYM | *.o | *.obj ) ;;
++    *.* ) ac_cv_exeext=`expr "$ac_file" : '[^.]*\(\..*\)'`
++	  break;;
++    * ) break;;
++  esac
++done
++else
++  { { $as_echo "$as_me:${as_lineno-$LINENO}: error: in \`$ac_pwd':" >&5
++$as_echo "$as_me: error: in \`$ac_pwd':" >&2;}
++as_fn_error $? "cannot compute suffix of executables: cannot compile and link
++See \`config.log' for more details" "$LINENO" 5; }
++fi
++rm -f conftest conftest$ac_cv_exeext
++{ $as_echo "$as_me:${as_lineno-$LINENO}: result: $ac_cv_exeext" >&5
++$as_echo "$ac_cv_exeext" >&6; }
++
++rm -f conftest.$ac_ext
++EXEEXT=$ac_cv_exeext
++ac_exeext=$EXEEXT
++cat confdefs.h - <<_ACEOF >conftest.$ac_ext
++/* end confdefs.h.  */
++#include <stdio.h>
++int
++main ()
++{
++FILE *f = fopen ("conftest.out", "w");
++ return ferror (f) || fclose (f) != 0;
++
++  ;
++  return 0;
++}
++_ACEOF
++ac_clean_files="$ac_clean_files conftest.out"
++# Check that the compiler produces executables we can run.  If not, either
++# the compiler is broken, or we cross compile.
++{ $as_echo "$as_me:${as_lineno-$LINENO}: checking whether we are cross compiling" >&5
++$as_echo_n "checking whether we are cross compiling... " >&6; }
++if test "$cross_compiling" != yes; then
++  { { ac_try="$ac_link"
++case "(($ac_try" in
++  *\"* | *\`* | *\\*) ac_try_echo=\$ac_try;;
++  *) ac_try_echo=$ac_try;;
++esac
++eval ac_try_echo="\"\$as_me:${as_lineno-$LINENO}: $ac_try_echo\""
++$as_echo "$ac_try_echo"; } >&5
++  (eval "$ac_link") 2>&5
++  ac_status=$?
++  $as_echo "$as_me:${as_lineno-$LINENO}: \$? = $ac_status" >&5
++  test $ac_status = 0; }
++  if { ac_try='./conftest$ac_cv_exeext'
++  { { case "(($ac_try" in
++  *\"* | *\`* | *\\*) ac_try_echo=\$ac_try;;
++  *) ac_try_echo=$ac_try;;
++esac
++eval ac_try_echo="\"\$as_me:${as_lineno-$LINENO}: $ac_try_echo\""
++$as_echo "$ac_try_echo"; } >&5
++  (eval "$ac_try") 2>&5
++  ac_status=$?
++  $as_echo "$as_me:${as_lineno-$LINENO}: \$? = $ac_status" >&5
++  test $ac_status = 0; }; }; then
++    cross_compiling=no
++  else
++    if test "$cross_compiling" = maybe; then
++	cross_compiling=yes
++    else
++	{ { $as_echo "$as_me:${as_lineno-$LINENO}: error: in \`$ac_pwd':" >&5
++$as_echo "$as_me: error: in \`$ac_pwd':" >&2;}
++as_fn_error $? "cannot run C compiled programs.
++If you meant to cross compile, use \`--host'.
++See \`config.log' for more details" "$LINENO" 5; }
++    fi
++  fi
++fi
++{ $as_echo "$as_me:${as_lineno-$LINENO}: result: $cross_compiling" >&5
++$as_echo "$cross_compiling" >&6; }
++
++rm -f conftest.$ac_ext conftest$ac_cv_exeext conftest.out
++ac_clean_files=$ac_clean_files_save
++{ $as_echo "$as_me:${as_lineno-$LINENO}: checking for suffix of object files" >&5
++$as_echo_n "checking for suffix of object files... " >&6; }
++if ${ac_cv_objext+:} false; then :
++  $as_echo_n "(cached) " >&6
++else
++  cat confdefs.h - <<_ACEOF >conftest.$ac_ext
++/* end confdefs.h.  */
++
++int
++main ()
++{
++
++  ;
++  return 0;
++}
++_ACEOF
++rm -f conftest.o conftest.obj
++if { { ac_try="$ac_compile"
++case "(($ac_try" in
++  *\"* | *\`* | *\\*) ac_try_echo=\$ac_try;;
++  *) ac_try_echo=$ac_try;;
++esac
++eval ac_try_echo="\"\$as_me:${as_lineno-$LINENO}: $ac_try_echo\""
++$as_echo "$ac_try_echo"; } >&5
++  (eval "$ac_compile") 2>&5
++  ac_status=$?
++  $as_echo "$as_me:${as_lineno-$LINENO}: \$? = $ac_status" >&5
++  test $ac_status = 0; }; then :
++  for ac_file in conftest.o conftest.obj conftest.*; do
++  test -f "$ac_file" || continue;
++  case $ac_file in
++    *.$ac_ext | *.xcoff | *.tds | *.d | *.pdb | *.xSYM | *.bb | *.bbg | *.map | *.inf | *.dSYM ) ;;
++    *) ac_cv_objext=`expr "$ac_file" : '.*\.\(.*\)'`
++       break;;
++  esac
++done
++else
++  $as_echo "$as_me: failed program was:" >&5
++sed 's/^/| /' conftest.$ac_ext >&5
++
++{ { $as_echo "$as_me:${as_lineno-$LINENO}: error: in \`$ac_pwd':" >&5
++$as_echo "$as_me: error: in \`$ac_pwd':" >&2;}
++as_fn_error $? "cannot compute suffix of object files: cannot compile
++See \`config.log' for more details" "$LINENO" 5; }
++fi
++rm -f conftest.$ac_cv_objext conftest.$ac_ext
++fi
++{ $as_echo "$as_me:${as_lineno-$LINENO}: result: $ac_cv_objext" >&5
++$as_echo "$ac_cv_objext" >&6; }
++OBJEXT=$ac_cv_objext
++ac_objext=$OBJEXT
++{ $as_echo "$as_me:${as_lineno-$LINENO}: checking whether we are using the GNU C compiler" >&5
++$as_echo_n "checking whether we are using the GNU C compiler... " >&6; }
++if ${ac_cv_c_compiler_gnu+:} false; then :
++  $as_echo_n "(cached) " >&6
++else
++  cat confdefs.h - <<_ACEOF >conftest.$ac_ext
++/* end confdefs.h.  */
++
++int
++main ()
++{
++#ifndef __GNUC__
++       choke me
++#endif
++
++  ;
++  return 0;
++}
++_ACEOF
++if ac_fn_c_try_compile "$LINENO"; then :
++  ac_compiler_gnu=yes
++else
++  ac_compiler_gnu=no
++fi
++rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext
++ac_cv_c_compiler_gnu=$ac_compiler_gnu
++
++fi
++{ $as_echo "$as_me:${as_lineno-$LINENO}: result: $ac_cv_c_compiler_gnu" >&5
++$as_echo "$ac_cv_c_compiler_gnu" >&6; }
++if test $ac_compiler_gnu = yes; then
++  GCC=yes
++else
++  GCC=
++fi
++ac_test_CFLAGS=${CFLAGS+set}
++ac_save_CFLAGS=$CFLAGS
++{ $as_echo "$as_me:${as_lineno-$LINENO}: checking whether $CC accepts -g" >&5
++$as_echo_n "checking whether $CC accepts -g... " >&6; }
++if ${ac_cv_prog_cc_g+:} false; then :
++  $as_echo_n "(cached) " >&6
++else
++  ac_save_c_werror_flag=$ac_c_werror_flag
++   ac_c_werror_flag=yes
++   ac_cv_prog_cc_g=no
++   CFLAGS="-g"
++   cat confdefs.h - <<_ACEOF >conftest.$ac_ext
++/* end confdefs.h.  */
++
++int
++main ()
++{
++
++  ;
++  return 0;
++}
++_ACEOF
++if ac_fn_c_try_compile "$LINENO"; then :
++  ac_cv_prog_cc_g=yes
++else
++  CFLAGS=""
++      cat confdefs.h - <<_ACEOF >conftest.$ac_ext
++/* end confdefs.h.  */
++
++int
++main ()
++{
++
++  ;
++  return 0;
++}
++_ACEOF
++if ac_fn_c_try_compile "$LINENO"; then :
++
++else
++  ac_c_werror_flag=$ac_save_c_werror_flag
++	 CFLAGS="-g"
++	 cat confdefs.h - <<_ACEOF >conftest.$ac_ext
++/* end confdefs.h.  */
++
++int
++main ()
++{
++
++  ;
++  return 0;
++}
++_ACEOF
++if ac_fn_c_try_compile "$LINENO"; then :
++  ac_cv_prog_cc_g=yes
++fi
++rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext
++fi
++rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext
++fi
++rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext
++   ac_c_werror_flag=$ac_save_c_werror_flag
++fi
++{ $as_echo "$as_me:${as_lineno-$LINENO}: result: $ac_cv_prog_cc_g" >&5
++$as_echo "$ac_cv_prog_cc_g" >&6; }
++if test "$ac_test_CFLAGS" = set; then
++  CFLAGS=$ac_save_CFLAGS
++elif test $ac_cv_prog_cc_g = yes; then
++  if test "$GCC" = yes; then
++    CFLAGS="-g -O2"
++  else
++    CFLAGS="-g"
++  fi
++else
++  if test "$GCC" = yes; then
++    CFLAGS="-O2"
++  else
++    CFLAGS=
++  fi
++fi
++{ $as_echo "$as_me:${as_lineno-$LINENO}: checking for $CC option to accept ISO C89" >&5
++$as_echo_n "checking for $CC option to accept ISO C89... " >&6; }
++if ${ac_cv_prog_cc_c89+:} false; then :
++  $as_echo_n "(cached) " >&6
++else
++  ac_cv_prog_cc_c89=no
++ac_save_CC=$CC
++cat confdefs.h - <<_ACEOF >conftest.$ac_ext
++/* end confdefs.h.  */
++#include <stdarg.h>
++#include <stdio.h>
++struct stat;
++/* Most of the following tests are stolen from RCS 5.7's src/conf.sh.  */
++struct buf { int x; };
++FILE * (*rcsopen) (struct buf *, struct stat *, int);
++static char *e (p, i)
++     char **p;
++     int i;
++{
++  return p[i];
++}
++static char *f (char * (*g) (char **, int), char **p, ...)
++{
++  char *s;
++  va_list v;
++  va_start (v,p);
++  s = g (p, va_arg (v,int));
++  va_end (v);
++  return s;
++}
++
++/* OSF 4.0 Compaq cc is some sort of almost-ANSI by default.  It has
++   function prototypes and stuff, but not '\xHH' hex character constants.
++   These don't provoke an error unfortunately, instead are silently treated
++   as 'x'.  The following induces an error, until -std is added to get
++   proper ANSI mode.  Curiously '\x00'!='x' always comes out true, for an
++   array size at least.  It's necessary to write '\x00'==0 to get something
++   that's true only with -std.  */
++int osf4_cc_array ['\x00' == 0 ? 1 : -1];
++
++/* IBM C 6 for AIX is almost-ANSI by default, but it replaces macro parameters
++   inside strings and character constants.  */
++#define FOO(x) 'x'
++int xlc6_cc_array[FOO(a) == 'x' ? 1 : -1];
++
++int test (int i, double x);
++struct s1 {int (*f) (int a);};
++struct s2 {int (*f) (double a);};
++int pairnames (int, char **, FILE *(*)(struct buf *, struct stat *, int), int, int);
++int argc;
++char **argv;
++int
++main ()
++{
++return f (e, argv, 0) != argv[0]  ||  f (e, argv, 1) != argv[1];
++  ;
++  return 0;
++}
++_ACEOF
++for ac_arg in '' -qlanglvl=extc89 -qlanglvl=ansi -std \
++	-Ae "-Aa -D_HPUX_SOURCE" "-Xc -D__EXTENSIONS__"
++do
++  CC="$ac_save_CC $ac_arg"
++  if ac_fn_c_try_compile "$LINENO"; then :
++  ac_cv_prog_cc_c89=$ac_arg
++fi
++rm -f core conftest.err conftest.$ac_objext
++  test "x$ac_cv_prog_cc_c89" != "xno" && break
++done
++rm -f conftest.$ac_ext
++CC=$ac_save_CC
++
++fi
++# AC_CACHE_VAL
++case "x$ac_cv_prog_cc_c89" in
++  x)
++    { $as_echo "$as_me:${as_lineno-$LINENO}: result: none needed" >&5
++$as_echo "none needed" >&6; } ;;
++  xno)
++    { $as_echo "$as_me:${as_lineno-$LINENO}: result: unsupported" >&5
++$as_echo "unsupported" >&6; } ;;
++  *)
++    CC="$CC $ac_cv_prog_cc_c89"
++    { $as_echo "$as_me:${as_lineno-$LINENO}: result: $ac_cv_prog_cc_c89" >&5
++$as_echo "$ac_cv_prog_cc_c89" >&6; } ;;
++esac
++if test "x$ac_cv_prog_cc_c89" != xno; then :
++
++fi
++
++ac_ext=c
++ac_cpp='$CPP $CPPFLAGS'
++ac_compile='$CC -c $CFLAGS $CPPFLAGS conftest.$ac_ext >&5'
++ac_link='$CC -o conftest$ac_exeext $CFLAGS $CPPFLAGS $LDFLAGS conftest.$ac_ext $LIBS >&5'
++ac_compiler_gnu=$ac_cv_c_compiler_gnu
++
++ac_aux_dir=
++for ac_dir in "$srcdir" "$srcdir/.." "$srcdir/../.."; do
++  if test -f "$ac_dir/install-sh"; then
++    ac_aux_dir=$ac_dir
++    ac_install_sh="$ac_aux_dir/install-sh -c"
++    break
++  elif test -f "$ac_dir/install.sh"; then
++    ac_aux_dir=$ac_dir
++    ac_install_sh="$ac_aux_dir/install.sh -c"
++    break
++  elif test -f "$ac_dir/shtool"; then
++    ac_aux_dir=$ac_dir
++    ac_install_sh="$ac_aux_dir/shtool install -c"
++    break
++  fi
++done
++if test -z "$ac_aux_dir"; then
++  as_fn_error $? "cannot find install-sh, install.sh, or shtool in \"$srcdir\" \"$srcdir/..\" \"$srcdir/../..\"" "$LINENO" 5
++fi
++
++# These three variables are undocumented and unsupported,
++# and are intended to be withdrawn in a future Autoconf release.
++# They can cause serious problems if a builder's source tree is in a directory
++# whose full name contains unusual characters.
++ac_config_guess="$SHELL $ac_aux_dir/config.guess"  # Please don't use this var.
++ac_config_sub="$SHELL $ac_aux_dir/config.sub"  # Please don't use this var.
++ac_configure="$SHELL $ac_aux_dir/configure"  # Please don't use this var.
++
++
++# Make sure we can run config.sub.
++$SHELL "$ac_aux_dir/config.sub" sun4 >/dev/null 2>&1 ||
++  as_fn_error $? "cannot run $SHELL $ac_aux_dir/config.sub" "$LINENO" 5
++
++{ $as_echo "$as_me:${as_lineno-$LINENO}: checking build system type" >&5
++$as_echo_n "checking build system type... " >&6; }
++if ${ac_cv_build+:} false; then :
++  $as_echo_n "(cached) " >&6
++else
++  ac_build_alias=$build_alias
++test "x$ac_build_alias" = x &&
++  ac_build_alias=`$SHELL "$ac_aux_dir/config.guess"`
++test "x$ac_build_alias" = x &&
++  as_fn_error $? "cannot guess build type; you must specify one" "$LINENO" 5
++ac_cv_build=`$SHELL "$ac_aux_dir/config.sub" $ac_build_alias` ||
++  as_fn_error $? "$SHELL $ac_aux_dir/config.sub $ac_build_alias failed" "$LINENO" 5
++
++fi
++{ $as_echo "$as_me:${as_lineno-$LINENO}: result: $ac_cv_build" >&5
++$as_echo "$ac_cv_build" >&6; }
++case $ac_cv_build in
++*-*-*) ;;
++*) as_fn_error $? "invalid value of canonical build" "$LINENO" 5;;
++esac
++build=$ac_cv_build
++ac_save_IFS=$IFS; IFS='-'
++set x $ac_cv_build
++shift
++build_cpu=$1
++build_vendor=$2
++shift; shift
++# Remember, the first character of IFS is used to create $*,
++# except with old shells:
++build_os=$*
++IFS=$ac_save_IFS
++case $build_os in *\ *) build_os=`echo "$build_os" | sed 's/ /-/g'`;; esac
++
++
++{ $as_echo "$as_me:${as_lineno-$LINENO}: checking host system type" >&5
++$as_echo_n "checking host system type... " >&6; }
++if ${ac_cv_host+:} false; then :
++  $as_echo_n "(cached) " >&6
++else
++  if test "x$host_alias" = x; then
++  ac_cv_host=$ac_cv_build
++else
++  ac_cv_host=`$SHELL "$ac_aux_dir/config.sub" $host_alias` ||
++    as_fn_error $? "$SHELL $ac_aux_dir/config.sub $host_alias failed" "$LINENO" 5
++fi
++
++fi
++{ $as_echo "$as_me:${as_lineno-$LINENO}: result: $ac_cv_host" >&5
++$as_echo "$ac_cv_host" >&6; }
++case $ac_cv_host in
++*-*-*) ;;
++*) as_fn_error $? "invalid value of canonical host" "$LINENO" 5;;
++esac
++host=$ac_cv_host
++ac_save_IFS=$IFS; IFS='-'
++set x $ac_cv_host
++shift
++host_cpu=$1
++host_vendor=$2
++shift; shift
++# Remember, the first character of IFS is used to create $*,
++# except with old shells:
++host_os=$*
++IFS=$ac_save_IFS
++case $host_os in *\ *) host_os=`echo "$host_os" | sed 's/ /-/g'`;; esac
++
++
++{ $as_echo "$as_me:${as_lineno-$LINENO}: checking target system type" >&5
++$as_echo_n "checking target system type... " >&6; }
++if ${ac_cv_target+:} false; then :
++  $as_echo_n "(cached) " >&6
++else
++  if test "x$target_alias" = x; then
++  ac_cv_target=$ac_cv_host
++else
++  ac_cv_target=`$SHELL "$ac_aux_dir/config.sub" $target_alias` ||
++    as_fn_error $? "$SHELL $ac_aux_dir/config.sub $target_alias failed" "$LINENO" 5
++fi
++
++fi
++{ $as_echo "$as_me:${as_lineno-$LINENO}: result: $ac_cv_target" >&5
++$as_echo "$ac_cv_target" >&6; }
++case $ac_cv_target in
++*-*-*) ;;
++*) as_fn_error $? "invalid value of canonical target" "$LINENO" 5;;
++esac
++target=$ac_cv_target
++ac_save_IFS=$IFS; IFS='-'
++set x $ac_cv_target
++shift
++target_cpu=$1
++target_vendor=$2
++shift; shift
++# Remember, the first character of IFS is used to create $*,
++# except with old shells:
++target_os=$*
++IFS=$ac_save_IFS
++case $target_os in *\ *) target_os=`echo "$target_os" | sed 's/ /-/g'`;; esac
++
++
++# The aliases save the names the user supplied, while $host etc.
++# will get canonicalized.
++test -n "$target_alias" &&
++  test "$program_prefix$program_suffix$program_transform_name" = \
++    NONENONEs,x,x, &&
++  program_prefix=${target_alias}-
++
++ac_ext=c
++ac_cpp='$CPP $CPPFLAGS'
++ac_compile='$CC -c $CFLAGS $CPPFLAGS conftest.$ac_ext >&5'
++ac_link='$CC -o conftest$ac_exeext $CFLAGS $CPPFLAGS $LDFLAGS conftest.$ac_ext $LIBS >&5'
++ac_compiler_gnu=$ac_cv_c_compiler_gnu
++{ $as_echo "$as_me:${as_lineno-$LINENO}: checking how to run the C preprocessor" >&5
++$as_echo_n "checking how to run the C preprocessor... " >&6; }
++# On Suns, sometimes $CPP names a directory.
++if test -n "$CPP" && test -d "$CPP"; then
++  CPP=
++fi
++if test -z "$CPP"; then
++  if ${ac_cv_prog_CPP+:} false; then :
++  $as_echo_n "(cached) " >&6
++else
++      # Double quotes because CPP needs to be expanded
++    for CPP in "$CC -E" "$CC -E -traditional-cpp" "/lib/cpp"
++    do
++      ac_preproc_ok=false
++for ac_c_preproc_warn_flag in '' yes
++do
++  # Use a header file that comes with gcc, so configuring glibc
++  # with a fresh cross-compiler works.
++  # Prefer <limits.h> to <assert.h> if __STDC__ is defined, since
++  # <limits.h> exists even on freestanding compilers.
++  # On the NeXT, cc -E runs the code through the compiler's parser,
++  # not just through cpp. "Syntax error" is here to catch this case.
++  cat confdefs.h - <<_ACEOF >conftest.$ac_ext
++/* end confdefs.h.  */
++#ifdef __STDC__
++# include <limits.h>
++#else
++# include <assert.h>
++#endif
++		     Syntax error
++_ACEOF
++if ac_fn_c_try_cpp "$LINENO"; then :
++
++else
++  # Broken: fails on valid input.
++continue
++fi
++rm -f conftest.err conftest.i conftest.$ac_ext
++
++  # OK, works on sane cases.  Now check whether nonexistent headers
++  # can be detected and how.
++  cat confdefs.h - <<_ACEOF >conftest.$ac_ext
++/* end confdefs.h.  */
++#include <ac_nonexistent.h>
++_ACEOF
++if ac_fn_c_try_cpp "$LINENO"; then :
++  # Broken: success on invalid input.
++continue
++else
++  # Passes both tests.
++ac_preproc_ok=:
++break
++fi
++rm -f conftest.err conftest.i conftest.$ac_ext
++
++done
++# Because of `break', _AC_PREPROC_IFELSE's cleaning code was skipped.
++rm -f conftest.i conftest.err conftest.$ac_ext
++if $ac_preproc_ok; then :
++  break
++fi
++
++    done
++    ac_cv_prog_CPP=$CPP
++
++fi
++  CPP=$ac_cv_prog_CPP
++else
++  ac_cv_prog_CPP=$CPP
++fi
++{ $as_echo "$as_me:${as_lineno-$LINENO}: result: $CPP" >&5
++$as_echo "$CPP" >&6; }
++ac_preproc_ok=false
++for ac_c_preproc_warn_flag in '' yes
++do
++  # Use a header file that comes with gcc, so configuring glibc
++  # with a fresh cross-compiler works.
++  # Prefer <limits.h> to <assert.h> if __STDC__ is defined, since
++  # <limits.h> exists even on freestanding compilers.
++  # On the NeXT, cc -E runs the code through the compiler's parser,
++  # not just through cpp. "Syntax error" is here to catch this case.
++  cat confdefs.h - <<_ACEOF >conftest.$ac_ext
++/* end confdefs.h.  */
++#ifdef __STDC__
++# include <limits.h>
++#else
++# include <assert.h>
++#endif
++		     Syntax error
++_ACEOF
++if ac_fn_c_try_cpp "$LINENO"; then :
++
++else
++  # Broken: fails on valid input.
++continue
++fi
++rm -f conftest.err conftest.i conftest.$ac_ext
++
++  # OK, works on sane cases.  Now check whether nonexistent headers
++  # can be detected and how.
++  cat confdefs.h - <<_ACEOF >conftest.$ac_ext
++/* end confdefs.h.  */
++#include <ac_nonexistent.h>
++_ACEOF
++if ac_fn_c_try_cpp "$LINENO"; then :
++  # Broken: success on invalid input.
++continue
++else
++  # Passes both tests.
++ac_preproc_ok=:
++break
++fi
++rm -f conftest.err conftest.i conftest.$ac_ext
++
++done
++# Because of `break', _AC_PREPROC_IFELSE's cleaning code was skipped.
++rm -f conftest.i conftest.err conftest.$ac_ext
++if $ac_preproc_ok; then :
++
++else
++  { { $as_echo "$as_me:${as_lineno-$LINENO}: error: in \`$ac_pwd':" >&5
++$as_echo "$as_me: error: in \`$ac_pwd':" >&2;}
++as_fn_error $? "C preprocessor \"$CPP\" fails sanity check
++See \`config.log' for more details" "$LINENO" 5; }
++fi
++
++ac_ext=c
++ac_cpp='$CPP $CPPFLAGS'
++ac_compile='$CC -c $CFLAGS $CPPFLAGS conftest.$ac_ext >&5'
++ac_link='$CC -o conftest$ac_exeext $CFLAGS $CPPFLAGS $LDFLAGS conftest.$ac_ext $LIBS >&5'
++ac_compiler_gnu=$ac_cv_c_compiler_gnu
++
++
++{ $as_echo "$as_me:${as_lineno-$LINENO}: checking for grep that handles long lines and -e" >&5
++$as_echo_n "checking for grep that handles long lines and -e... " >&6; }
++if ${ac_cv_path_GREP+:} false; then :
++  $as_echo_n "(cached) " >&6
++else
++  if test -z "$GREP"; then
++  ac_path_GREP_found=false
++  # Loop through the user's path and test for each of PROGNAME-LIST
++  as_save_IFS=$IFS; IFS=$PATH_SEPARATOR
++for as_dir in $PATH$PATH_SEPARATOR/usr/xpg4/bin
++do
++  IFS=$as_save_IFS
++  test -z "$as_dir" && as_dir=.
++    for ac_prog in grep ggrep; do
++    for ac_exec_ext in '' $ac_executable_extensions; do
++      ac_path_GREP="$as_dir/$ac_prog$ac_exec_ext"
++      as_fn_executable_p "$ac_path_GREP" || continue
++# Check for GNU ac_path_GREP and select it if it is found.
++  # Check for GNU $ac_path_GREP
++case `"$ac_path_GREP" --version 2>&1` in
++*GNU*)
++  ac_cv_path_GREP="$ac_path_GREP" ac_path_GREP_found=:;;
++*)
++  ac_count=0
++  $as_echo_n 0123456789 >"conftest.in"
++  while :
++  do
++    cat "conftest.in" "conftest.in" >"conftest.tmp"
++    mv "conftest.tmp" "conftest.in"
++    cp "conftest.in" "conftest.nl"
++    $as_echo 'GREP' >> "conftest.nl"
++    "$ac_path_GREP" -e 'GREP$' -e '-(cannot match)-' < "conftest.nl" >"conftest.out" 2>/dev/null || break
++    diff "conftest.out" "conftest.nl" >/dev/null 2>&1 || break
++    as_fn_arith $ac_count + 1 && ac_count=$as_val
++    if test $ac_count -gt ${ac_path_GREP_max-0}; then
++      # Best one so far, save it but keep looking for a better one
++      ac_cv_path_GREP="$ac_path_GREP"
++      ac_path_GREP_max=$ac_count
++    fi
++    # 10*(2^10) chars as input seems more than enough
++    test $ac_count -gt 10 && break
++  done
++  rm -f conftest.in conftest.tmp conftest.nl conftest.out;;
++esac
++
++      $ac_path_GREP_found && break 3
++    done
++  done
++  done
++IFS=$as_save_IFS
++  if test -z "$ac_cv_path_GREP"; then
++    as_fn_error $? "no acceptable grep could be found in $PATH$PATH_SEPARATOR/usr/xpg4/bin" "$LINENO" 5
++  fi
++else
++  ac_cv_path_GREP=$GREP
++fi
++
++fi
++{ $as_echo "$as_me:${as_lineno-$LINENO}: result: $ac_cv_path_GREP" >&5
++$as_echo "$ac_cv_path_GREP" >&6; }
++ GREP="$ac_cv_path_GREP"
++
++
++{ $as_echo "$as_me:${as_lineno-$LINENO}: checking for egrep" >&5
++$as_echo_n "checking for egrep... " >&6; }
++if ${ac_cv_path_EGREP+:} false; then :
++  $as_echo_n "(cached) " >&6
++else
++  if echo a | $GREP -E '(a|b)' >/dev/null 2>&1
++   then ac_cv_path_EGREP="$GREP -E"
++   else
++     if test -z "$EGREP"; then
++  ac_path_EGREP_found=false
++  # Loop through the user's path and test for each of PROGNAME-LIST
++  as_save_IFS=$IFS; IFS=$PATH_SEPARATOR
++for as_dir in $PATH$PATH_SEPARATOR/usr/xpg4/bin
++do
++  IFS=$as_save_IFS
++  test -z "$as_dir" && as_dir=.
++    for ac_prog in egrep; do
++    for ac_exec_ext in '' $ac_executable_extensions; do
++      ac_path_EGREP="$as_dir/$ac_prog$ac_exec_ext"
++      as_fn_executable_p "$ac_path_EGREP" || continue
++# Check for GNU ac_path_EGREP and select it if it is found.
++  # Check for GNU $ac_path_EGREP
++case `"$ac_path_EGREP" --version 2>&1` in
++*GNU*)
++  ac_cv_path_EGREP="$ac_path_EGREP" ac_path_EGREP_found=:;;
++*)
++  ac_count=0
++  $as_echo_n 0123456789 >"conftest.in"
++  while :
++  do
++    cat "conftest.in" "conftest.in" >"conftest.tmp"
++    mv "conftest.tmp" "conftest.in"
++    cp "conftest.in" "conftest.nl"
++    $as_echo 'EGREP' >> "conftest.nl"
++    "$ac_path_EGREP" 'EGREP$' < "conftest.nl" >"conftest.out" 2>/dev/null || break
++    diff "conftest.out" "conftest.nl" >/dev/null 2>&1 || break
++    as_fn_arith $ac_count + 1 && ac_count=$as_val
++    if test $ac_count -gt ${ac_path_EGREP_max-0}; then
++      # Best one so far, save it but keep looking for a better one
++      ac_cv_path_EGREP="$ac_path_EGREP"
++      ac_path_EGREP_max=$ac_count
++    fi
++    # 10*(2^10) chars as input seems more than enough
++    test $ac_count -gt 10 && break
++  done
++  rm -f conftest.in conftest.tmp conftest.nl conftest.out;;
++esac
++
++      $ac_path_EGREP_found && break 3
++    done
++  done
++  done
++IFS=$as_save_IFS
++  if test -z "$ac_cv_path_EGREP"; then
++    as_fn_error $? "no acceptable egrep could be found in $PATH$PATH_SEPARATOR/usr/xpg4/bin" "$LINENO" 5
++  fi
++else
++  ac_cv_path_EGREP=$EGREP
++fi
++
++   fi
++fi
++{ $as_echo "$as_me:${as_lineno-$LINENO}: result: $ac_cv_path_EGREP" >&5
++$as_echo "$ac_cv_path_EGREP" >&6; }
++ EGREP="$ac_cv_path_EGREP"
++
++
++{ $as_echo "$as_me:${as_lineno-$LINENO}: checking for ANSI C header files" >&5
++$as_echo_n "checking for ANSI C header files... " >&6; }
++if ${ac_cv_header_stdc+:} false; then :
++  $as_echo_n "(cached) " >&6
++else
++  cat confdefs.h - <<_ACEOF >conftest.$ac_ext
++/* end confdefs.h.  */
++#include <stdlib.h>
++#include <stdarg.h>
++#include <string.h>
++#include <float.h>
++
++int
++main ()
++{
++
++  ;
++  return 0;
++}
++_ACEOF
++if ac_fn_c_try_compile "$LINENO"; then :
++  ac_cv_header_stdc=yes
++else
++  ac_cv_header_stdc=no
++fi
++rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext
++
++if test $ac_cv_header_stdc = yes; then
++  # SunOS 4.x string.h does not declare mem*, contrary to ANSI.
++  cat confdefs.h - <<_ACEOF >conftest.$ac_ext
++/* end confdefs.h.  */
++#include <string.h>
++
++_ACEOF
++if (eval "$ac_cpp conftest.$ac_ext") 2>&5 |
++  $EGREP "memchr" >/dev/null 2>&1; then :
++
++else
++  ac_cv_header_stdc=no
++fi
++rm -f conftest*
++
++fi
++
++if test $ac_cv_header_stdc = yes; then
++  # ISC 2.0.2 stdlib.h does not declare free, contrary to ANSI.
++  cat confdefs.h - <<_ACEOF >conftest.$ac_ext
++/* end confdefs.h.  */
++#include <stdlib.h>
++
++_ACEOF
++if (eval "$ac_cpp conftest.$ac_ext") 2>&5 |
++  $EGREP "free" >/dev/null 2>&1; then :
++
++else
++  ac_cv_header_stdc=no
++fi
++rm -f conftest*
++
++fi
++
++if test $ac_cv_header_stdc = yes; then
++  # /bin/cc in Irix-4.0.5 gets non-ANSI ctype macros unless using -ansi.
++  if test "$cross_compiling" = yes; then :
++  :
++else
++  cat confdefs.h - <<_ACEOF >conftest.$ac_ext
++/* end confdefs.h.  */
++#include <ctype.h>
++#include <stdlib.h>
++#if ((' ' & 0x0FF) == 0x020)
++# define ISLOWER(c) ('a' <= (c) && (c) <= 'z')
++# define TOUPPER(c) (ISLOWER(c) ? 'A' + ((c) - 'a') : (c))
++#else
++# define ISLOWER(c) \
++		   (('a' <= (c) && (c) <= 'i') \
++		     || ('j' <= (c) && (c) <= 'r') \
++		     || ('s' <= (c) && (c) <= 'z'))
++# define TOUPPER(c) (ISLOWER(c) ? ((c) | 0x40) : (c))
++#endif
++
++#define XOR(e, f) (((e) && !(f)) || (!(e) && (f)))
++int
++main ()
++{
++  int i;
++  for (i = 0; i < 256; i++)
++    if (XOR (islower (i), ISLOWER (i))
++	|| toupper (i) != TOUPPER (i))
++      return 2;
++  return 0;
++}
++_ACEOF
++if ac_fn_c_try_run "$LINENO"; then :
++
++else
++  ac_cv_header_stdc=no
++fi
++rm -f core *.core core.conftest.* gmon.out bb.out conftest$ac_exeext \
++  conftest.$ac_objext conftest.beam conftest.$ac_ext
++fi
++
++fi
++fi
++{ $as_echo "$as_me:${as_lineno-$LINENO}: result: $ac_cv_header_stdc" >&5
++$as_echo "$ac_cv_header_stdc" >&6; }
++if test $ac_cv_header_stdc = yes; then
++
++$as_echo "#define STDC_HEADERS 1" >>confdefs.h
++
++fi
++
++# On IRIX 5.3, sys/types and inttypes.h are conflicting.
++for ac_header in sys/types.h sys/stat.h stdlib.h string.h memory.h strings.h \
++		  inttypes.h stdint.h unistd.h
++do :
++  as_ac_Header=`$as_echo "ac_cv_header_$ac_header" | $as_tr_sh`
++ac_fn_c_check_header_compile "$LINENO" "$ac_header" "$as_ac_Header" "$ac_includes_default
++"
++if eval test \"x\$"$as_ac_Header"\" = x"yes"; then :
++  cat >>confdefs.h <<_ACEOF
++#define `$as_echo "HAVE_$ac_header" | $as_tr_cpp` 1
++_ACEOF
++
++fi
++
++done
++
++
++
++  ac_fn_c_check_header_mongrel "$LINENO" "minix/config.h" "ac_cv_header_minix_config_h" "$ac_includes_default"
++if test "x$ac_cv_header_minix_config_h" = xyes; then :
++  MINIX=yes
++else
++  MINIX=
++fi
++
++
++  if test "$MINIX" = yes; then
++
++$as_echo "#define _POSIX_SOURCE 1" >>confdefs.h
++
++
++$as_echo "#define _POSIX_1_SOURCE 2" >>confdefs.h
++
++
++$as_echo "#define _MINIX 1" >>confdefs.h
++
++  fi
++
++
++  { $as_echo "$as_me:${as_lineno-$LINENO}: checking whether it is safe to define __EXTENSIONS__" >&5
++$as_echo_n "checking whether it is safe to define __EXTENSIONS__... " >&6; }
++if ${ac_cv_safe_to_define___extensions__+:} false; then :
++  $as_echo_n "(cached) " >&6
++else
++  cat confdefs.h - <<_ACEOF >conftest.$ac_ext
++/* end confdefs.h.  */
++
++#         define __EXTENSIONS__ 1
++          $ac_includes_default
++int
++main ()
++{
++
++  ;
++  return 0;
++}
++_ACEOF
++if ac_fn_c_try_compile "$LINENO"; then :
++  ac_cv_safe_to_define___extensions__=yes
++else
++  ac_cv_safe_to_define___extensions__=no
++fi
++rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext
++fi
++{ $as_echo "$as_me:${as_lineno-$LINENO}: result: $ac_cv_safe_to_define___extensions__" >&5
++$as_echo "$ac_cv_safe_to_define___extensions__" >&6; }
++  test $ac_cv_safe_to_define___extensions__ = yes &&
++    $as_echo "#define __EXTENSIONS__ 1" >>confdefs.h
++
++  $as_echo "#define _ALL_SOURCE 1" >>confdefs.h
++
++  $as_echo "#define _GNU_SOURCE 1" >>confdefs.h
++
++  $as_echo "#define _POSIX_PTHREAD_SEMANTICS 1" >>confdefs.h
++
++  $as_echo "#define _TANDEM_SOURCE 1" >>confdefs.h
++
++
++test "$program_prefix" != NONE &&
++  program_transform_name="s&^&$program_prefix&;$program_transform_name"
++# Use a double $ so make ignores it.
++test "$program_suffix" != NONE &&
++  program_transform_name="s&\$&$program_suffix&;$program_transform_name"
++# Double any \ or $.
++# By default was `s,x,x', remove it if useless.
++ac_script='s/[\\$]/&&/g;s/;s,x,x,$//'
++program_transform_name=`$as_echo "$program_transform_name" | sed "$ac_script"`
++
++# Find a good install program.  We prefer a C program (faster),
++# so one script is as good as another.  But avoid the broken or
++# incompatible versions:
++# SysV /etc/install, /usr/sbin/install
++# SunOS /usr/etc/install
++# IRIX /sbin/install
++# AIX /bin/install
++# AmigaOS /C/install, which installs bootblocks on floppy discs
++# AIX 4 /usr/bin/installbsd, which doesn't work without a -g flag
++# AFS /usr/afsws/bin/install, which mishandles nonexistent args
++# SVR4 /usr/ucb/install, which tries to use the nonexistent group "staff"
++# OS/2's system install, which has a completely different semantic
++# ./install, which can be erroneously created by make from ./install.sh.
++# Reject install programs that cannot install multiple files.
++{ $as_echo "$as_me:${as_lineno-$LINENO}: checking for a BSD-compatible install" >&5
++$as_echo_n "checking for a BSD-compatible install... " >&6; }
++if test -z "$INSTALL"; then
++if ${ac_cv_path_install+:} false; then :
++  $as_echo_n "(cached) " >&6
++else
++  as_save_IFS=$IFS; IFS=$PATH_SEPARATOR
++for as_dir in $PATH
++do
++  IFS=$as_save_IFS
++  test -z "$as_dir" && as_dir=.
++    # Account for people who put trailing slashes in PATH elements.
++case $as_dir/ in #((
++  ./ | .// | /[cC]/* | \
++  /etc/* | /usr/sbin/* | /usr/etc/* | /sbin/* | /usr/afsws/bin/* | \
++  ?:[\\/]os2[\\/]install[\\/]* | ?:[\\/]OS2[\\/]INSTALL[\\/]* | \
++  /usr/ucb/* ) ;;
++  *)
++    # OSF1 and SCO ODT 3.0 have their own names for install.
++    # Don't use installbsd from OSF since it installs stuff as root
++    # by default.
++    for ac_prog in ginstall scoinst install; do
++      for ac_exec_ext in '' $ac_executable_extensions; do
++	if as_fn_executable_p "$as_dir/$ac_prog$ac_exec_ext"; then
++	  if test $ac_prog = install &&
++	    grep dspmsg "$as_dir/$ac_prog$ac_exec_ext" >/dev/null 2>&1; then
++	    # AIX install.  It has an incompatible calling convention.
++	    :
++	  elif test $ac_prog = install &&
++	    grep pwplus "$as_dir/$ac_prog$ac_exec_ext" >/dev/null 2>&1; then
++	    # program-specific install script used by HP pwplus--don't use.
++	    :
++	  else
++	    rm -rf conftest.one conftest.two conftest.dir
++	    echo one > conftest.one
++	    echo two > conftest.two
++	    mkdir conftest.dir
++	    if "$as_dir/$ac_prog$ac_exec_ext" -c conftest.one conftest.two "`pwd`/conftest.dir" &&
++	      test -s conftest.one && test -s conftest.two &&
++	      test -s conftest.dir/conftest.one &&
++	      test -s conftest.dir/conftest.two
++	    then
++	      ac_cv_path_install="$as_dir/$ac_prog$ac_exec_ext -c"
++	      break 3
++	    fi
++	  fi
++	fi
++      done
++    done
++    ;;
++esac
++
++  done
++IFS=$as_save_IFS
++
++rm -rf conftest.one conftest.two conftest.dir
++
++fi
++  if test "${ac_cv_path_install+set}" = set; then
++    INSTALL=$ac_cv_path_install
++  else
++    # As a last resort, use the slow shell script.  Don't cache a
++    # value for INSTALL within a source directory, because that will
++    # break other packages using the cache if that directory is
++    # removed, or if the value is a relative name.
++    INSTALL=$ac_install_sh
++  fi
++fi
++{ $as_echo "$as_me:${as_lineno-$LINENO}: result: $INSTALL" >&5
++$as_echo "$INSTALL" >&6; }
++
++# Use test -z because SunOS4 sh mishandles braces in ${var-val}.
++# It thinks the first close brace ends the variable substitution.
++test -z "$INSTALL_PROGRAM" && INSTALL_PROGRAM='${INSTALL}'
++
++test -z "$INSTALL_SCRIPT" && INSTALL_SCRIPT='${INSTALL}'
++
++test -z "$INSTALL_DATA" && INSTALL_DATA='${INSTALL} -m 644'
++
++rm -rf .tst 2>/dev/null
++mkdir .tst 2>/dev/null
++if test -d .tst; then
++  am__leading_dot=.
++else
++  am__leading_dot=_
++fi
++rmdir .tst 2>/dev/null
++
++DEPDIR="${am__leading_dot}deps"
++
++case `pwd` in
++  *\ * | *\	*)
++    { $as_echo "$as_me:${as_lineno-$LINENO}: WARNING: Libtool does not cope well with whitespace in \`pwd\`" >&5
++$as_echo "$as_me: WARNING: Libtool does not cope well with whitespace in \`pwd\`" >&2;} ;;
++esac
++
++
++
++macro_version='2.2.7a'
++macro_revision='1.3134'
++
++
++
++
++
++
++
++
++
++
++
++
++
++ltmain="$ac_aux_dir/ltmain.sh"
++
++# Backslashify metacharacters that are still active within
++# double-quoted strings.
++sed_quote_subst='s/\(["`$\\]\)/\\\1/g'
++
++# Same as above, but do not quote variable references.
++double_quote_subst='s/\(["`\\]\)/\\\1/g'
++
++# Sed substitution to delay expansion of an escaped shell variable in a
++# double_quote_subst'ed string.
++delay_variable_subst='s/\\\\\\\\\\\$/\\\\\\$/g'
++
++# Sed substitution to delay expansion of an escaped single quote.
++delay_single_quote_subst='s/'\''/'\'\\\\\\\'\''/g'
++
++# Sed substitution to avoid accidental globbing in evaled expressions
++no_glob_subst='s/\*/\\\*/g'
++
++ECHO='\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\'
++ECHO=$ECHO$ECHO$ECHO$ECHO$ECHO
++ECHO=$ECHO$ECHO$ECHO$ECHO$ECHO$ECHO
++
++{ $as_echo "$as_me:${as_lineno-$LINENO}: checking how to print strings" >&5
++$as_echo_n "checking how to print strings... " >&6; }
++# Test print first, because it will be a builtin if present.
++if test "X`print -r -- -n 2>/dev/null`" = X-n && \
++   test "X`print -r -- $ECHO 2>/dev/null`" = "X$ECHO"; then
++  ECHO='print -r --'
++elif test "X`printf %s $ECHO 2>/dev/null`" = "X$ECHO"; then
++  ECHO='printf %s\n'
++else
++  # Use this function as a fallback that always works.
++  func_fallback_echo ()
++  {
++    eval 'cat <<_LTECHO_EOF
++$1
++_LTECHO_EOF'
++  }
++  ECHO='func_fallback_echo'
++fi
++
++# func_echo_all arg...
++# Invoke $ECHO with all args, space-separated.
++func_echo_all ()
++{
++    $ECHO ""
++}
++
++case "$ECHO" in
++  printf*) { $as_echo "$as_me:${as_lineno-$LINENO}: result: printf" >&5
++$as_echo "printf" >&6; } ;;
++  print*) { $as_echo "$as_me:${as_lineno-$LINENO}: result: print -r" >&5
++$as_echo "print -r" >&6; } ;;
++  *) { $as_echo "$as_me:${as_lineno-$LINENO}: result: cat" >&5
++$as_echo "cat" >&6; } ;;
++esac
++
++
++
++
++
++
++
++
++
++
++
++
++
++
++{ $as_echo "$as_me:${as_lineno-$LINENO}: checking for a sed that does not truncate output" >&5
++$as_echo_n "checking for a sed that does not truncate output... " >&6; }
++if ${ac_cv_path_SED+:} false; then :
++  $as_echo_n "(cached) " >&6
++else
++            ac_script=s/aaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaa/bbbbbbbbbbbbbbbbbbbbbbbbbbbbbbbbb/
++     for ac_i in 1 2 3 4 5 6 7; do
++       ac_script="$ac_script$as_nl$ac_script"
++     done
++     echo "$ac_script" 2>/dev/null | sed 99q >conftest.sed
++     { ac_script=; unset ac_script;}
++     if test -z "$SED"; then
++  ac_path_SED_found=false
++  # Loop through the user's path and test for each of PROGNAME-LIST
++  as_save_IFS=$IFS; IFS=$PATH_SEPARATOR
++for as_dir in $PATH
++do
++  IFS=$as_save_IFS
++  test -z "$as_dir" && as_dir=.
++    for ac_prog in sed gsed; do
++    for ac_exec_ext in '' $ac_executable_extensions; do
++      ac_path_SED="$as_dir/$ac_prog$ac_exec_ext"
++      as_fn_executable_p "$ac_path_SED" || continue
++# Check for GNU ac_path_SED and select it if it is found.
++  # Check for GNU $ac_path_SED
++case `"$ac_path_SED" --version 2>&1` in
++*GNU*)
++  ac_cv_path_SED="$ac_path_SED" ac_path_SED_found=:;;
++*)
++  ac_count=0
++  $as_echo_n 0123456789 >"conftest.in"
++  while :
++  do
++    cat "conftest.in" "conftest.in" >"conftest.tmp"
++    mv "conftest.tmp" "conftest.in"
++    cp "conftest.in" "conftest.nl"
++    $as_echo '' >> "conftest.nl"
++    "$ac_path_SED" -f conftest.sed < "conftest.nl" >"conftest.out" 2>/dev/null || break
++    diff "conftest.out" "conftest.nl" >/dev/null 2>&1 || break
++    as_fn_arith $ac_count + 1 && ac_count=$as_val
++    if test $ac_count -gt ${ac_path_SED_max-0}; then
++      # Best one so far, save it but keep looking for a better one
++      ac_cv_path_SED="$ac_path_SED"
++      ac_path_SED_max=$ac_count
++    fi
++    # 10*(2^10) chars as input seems more than enough
++    test $ac_count -gt 10 && break
++  done
++  rm -f conftest.in conftest.tmp conftest.nl conftest.out;;
++esac
++
++      $ac_path_SED_found && break 3
++    done
++  done
++  done
++IFS=$as_save_IFS
++  if test -z "$ac_cv_path_SED"; then
++    as_fn_error $? "no acceptable sed could be found in \$PATH" "$LINENO" 5
++  fi
++else
++  ac_cv_path_SED=$SED
++fi
++
++fi
++{ $as_echo "$as_me:${as_lineno-$LINENO}: result: $ac_cv_path_SED" >&5
++$as_echo "$ac_cv_path_SED" >&6; }
++ SED="$ac_cv_path_SED"
++  rm -f conftest.sed
++
++test -z "$SED" && SED=sed
++Xsed="$SED -e 1s/^X//"
++
++
++
++
++
++
++
++
++
++
++
++{ $as_echo "$as_me:${as_lineno-$LINENO}: checking for fgrep" >&5
++$as_echo_n "checking for fgrep... " >&6; }
++if ${ac_cv_path_FGREP+:} false; then :
++  $as_echo_n "(cached) " >&6
++else
++  if echo 'ab*c' | $GREP -F 'ab*c' >/dev/null 2>&1
++   then ac_cv_path_FGREP="$GREP -F"
++   else
++     if test -z "$FGREP"; then
++  ac_path_FGREP_found=false
++  # Loop through the user's path and test for each of PROGNAME-LIST
++  as_save_IFS=$IFS; IFS=$PATH_SEPARATOR
++for as_dir in $PATH$PATH_SEPARATOR/usr/xpg4/bin
++do
++  IFS=$as_save_IFS
++  test -z "$as_dir" && as_dir=.
++    for ac_prog in fgrep; do
++    for ac_exec_ext in '' $ac_executable_extensions; do
++      ac_path_FGREP="$as_dir/$ac_prog$ac_exec_ext"
++      as_fn_executable_p "$ac_path_FGREP" || continue
++# Check for GNU ac_path_FGREP and select it if it is found.
++  # Check for GNU $ac_path_FGREP
++case `"$ac_path_FGREP" --version 2>&1` in
++*GNU*)
++  ac_cv_path_FGREP="$ac_path_FGREP" ac_path_FGREP_found=:;;
++*)
++  ac_count=0
++  $as_echo_n 0123456789 >"conftest.in"
++  while :
++  do
++    cat "conftest.in" "conftest.in" >"conftest.tmp"
++    mv "conftest.tmp" "conftest.in"
++    cp "conftest.in" "conftest.nl"
++    $as_echo 'FGREP' >> "conftest.nl"
++    "$ac_path_FGREP" FGREP < "conftest.nl" >"conftest.out" 2>/dev/null || break
++    diff "conftest.out" "conftest.nl" >/dev/null 2>&1 || break
++    as_fn_arith $ac_count + 1 && ac_count=$as_val
++    if test $ac_count -gt ${ac_path_FGREP_max-0}; then
++      # Best one so far, save it but keep looking for a better one
++      ac_cv_path_FGREP="$ac_path_FGREP"
++      ac_path_FGREP_max=$ac_count
++    fi
++    # 10*(2^10) chars as input seems more than enough
++    test $ac_count -gt 10 && break
++  done
++  rm -f conftest.in conftest.tmp conftest.nl conftest.out;;
++esac
++
++      $ac_path_FGREP_found && break 3
++    done
++  done
++  done
++IFS=$as_save_IFS
++  if test -z "$ac_cv_path_FGREP"; then
++    as_fn_error $? "no acceptable fgrep could be found in $PATH$PATH_SEPARATOR/usr/xpg4/bin" "$LINENO" 5
++  fi
++else
++  ac_cv_path_FGREP=$FGREP
++fi
++
++   fi
++fi
++{ $as_echo "$as_me:${as_lineno-$LINENO}: result: $ac_cv_path_FGREP" >&5
++$as_echo "$ac_cv_path_FGREP" >&6; }
++ FGREP="$ac_cv_path_FGREP"
++
++
++test -z "$GREP" && GREP=grep
++
++
++
++
++
++
++
++
++
++
++
++
++
++
++
++
++
++
++
++# Check whether --with-gnu-ld was given.
++if test "${with_gnu_ld+set}" = set; then :
++  withval=$with_gnu_ld; test "$withval" = no || with_gnu_ld=yes
++else
++  with_gnu_ld=no
++fi
++
++ac_prog=ld
++if test "$GCC" = yes; then
++  # Check if gcc -print-prog-name=ld gives a path.
++  { $as_echo "$as_me:${as_lineno-$LINENO}: checking for ld used by $CC" >&5
++$as_echo_n "checking for ld used by $CC... " >&6; }
++  case $host in
++  *-*-mingw*)
++    # gcc leaves a trailing carriage return which upsets mingw
++    ac_prog=`($CC -print-prog-name=ld) 2>&5 | tr -d '\015'` ;;
++  *)
++    ac_prog=`($CC -print-prog-name=ld) 2>&5` ;;
++  esac
++  case $ac_prog in
++    # Accept absolute paths.
++    [\\/]* | ?:[\\/]*)
++      re_direlt='/[^/][^/]*/\.\./'
++      # Canonicalize the pathname of ld
++      ac_prog=`$ECHO "$ac_prog"| $SED 's%\\\\%/%g'`
++      while $ECHO "$ac_prog" | $GREP "$re_direlt" > /dev/null 2>&1; do
++	ac_prog=`$ECHO $ac_prog| $SED "s%$re_direlt%/%"`
++      done
++      test -z "$LD" && LD="$ac_prog"
++      ;;
++  "")
++    # If it fails, then pretend we aren't using GCC.
++    ac_prog=ld
++    ;;
++  *)
++    # If it is relative, then search for the first ld in PATH.
++    with_gnu_ld=unknown
++    ;;
++  esac
++elif test "$with_gnu_ld" = yes; then
++  { $as_echo "$as_me:${as_lineno-$LINENO}: checking for GNU ld" >&5
++$as_echo_n "checking for GNU ld... " >&6; }
++else
++  { $as_echo "$as_me:${as_lineno-$LINENO}: checking for non-GNU ld" >&5
++$as_echo_n "checking for non-GNU ld... " >&6; }
++fi
++if ${lt_cv_path_LD+:} false; then :
++  $as_echo_n "(cached) " >&6
++else
++  if test -z "$LD"; then
++  lt_save_ifs="$IFS"; IFS=$PATH_SEPARATOR
++  for ac_dir in $PATH; do
++    IFS="$lt_save_ifs"
++    test -z "$ac_dir" && ac_dir=.
++    if test -f "$ac_dir/$ac_prog" || test -f "$ac_dir/$ac_prog$ac_exeext"; then
++      lt_cv_path_LD="$ac_dir/$ac_prog"
++      # Check to see if the program is GNU ld.  I'd rather use --version,
++      # but apparently some variants of GNU ld only accept -v.
++      # Break only if it was the GNU/non-GNU ld that we prefer.
++      case `"$lt_cv_path_LD" -v 2>&1 </dev/null` in
++      *GNU* | *'with BFD'*)
++	test "$with_gnu_ld" != no && break
++	;;
++      *)
++	test "$with_gnu_ld" != yes && break
++	;;
++      esac
++    fi
++  done
++  IFS="$lt_save_ifs"
++else
++  lt_cv_path_LD="$LD" # Let the user override the test with a path.
++fi
++fi
++
++LD="$lt_cv_path_LD"
++if test -n "$LD"; then
++  { $as_echo "$as_me:${as_lineno-$LINENO}: result: $LD" >&5
++$as_echo "$LD" >&6; }
++else
++  { $as_echo "$as_me:${as_lineno-$LINENO}: result: no" >&5
++$as_echo "no" >&6; }
++fi
++test -z "$LD" && as_fn_error $? "no acceptable ld found in \$PATH" "$LINENO" 5
++{ $as_echo "$as_me:${as_lineno-$LINENO}: checking if the linker ($LD) is GNU ld" >&5
++$as_echo_n "checking if the linker ($LD) is GNU ld... " >&6; }
++if ${lt_cv_prog_gnu_ld+:} false; then :
++  $as_echo_n "(cached) " >&6
++else
++  # I'd rather use --version here, but apparently some GNU lds only accept -v.
++case `$LD -v 2>&1 </dev/null` in
++*GNU* | *'with BFD'*)
++  lt_cv_prog_gnu_ld=yes
++  ;;
++*)
++  lt_cv_prog_gnu_ld=no
++  ;;
++esac
++fi
++{ $as_echo "$as_me:${as_lineno-$LINENO}: result: $lt_cv_prog_gnu_ld" >&5
++$as_echo "$lt_cv_prog_gnu_ld" >&6; }
++with_gnu_ld=$lt_cv_prog_gnu_ld
++
++
++
++
++
++
++
++
++
++{ $as_echo "$as_me:${as_lineno-$LINENO}: checking for BSD- or MS-compatible name lister (nm)" >&5
++$as_echo_n "checking for BSD- or MS-compatible name lister (nm)... " >&6; }
++if ${lt_cv_path_NM+:} false; then :
++  $as_echo_n "(cached) " >&6
++else
++  if test -n "$NM"; then
++  # Let the user override the test.
++  lt_cv_path_NM="$NM"
++else
++  lt_nm_to_check="${ac_tool_prefix}nm"
++  if test -n "$ac_tool_prefix" && test "$build" = "$host"; then
++    lt_nm_to_check="$lt_nm_to_check nm"
++  fi
++  for lt_tmp_nm in $lt_nm_to_check; do
++    lt_save_ifs="$IFS"; IFS=$PATH_SEPARATOR
++    for ac_dir in $PATH /usr/ccs/bin/elf /usr/ccs/bin /usr/ucb /bin; do
++      IFS="$lt_save_ifs"
++      test -z "$ac_dir" && ac_dir=.
++      tmp_nm="$ac_dir/$lt_tmp_nm"
++      if test -f "$tmp_nm" || test -f "$tmp_nm$ac_exeext" ; then
++	# Check to see if the nm accepts a BSD-compat flag.
++	# Adding the `sed 1q' prevents false positives on HP-UX, which says:
++	#   nm: unknown option "B" ignored
++	# Tru64's nm complains that /dev/null is an invalid object file
++	case `"$tmp_nm" -B /dev/null 2>&1 | sed '1q'` in
++	*/dev/null* | *'Invalid file or object type'*)
++	  lt_cv_path_NM="$tmp_nm -B"
++	  break
++	  ;;
++	*)
++	  case `"$tmp_nm" -p /dev/null 2>&1 | sed '1q'` in
++	  */dev/null*)
++	    lt_cv_path_NM="$tmp_nm -p"
++	    break
++	    ;;
++	  *)
++	    lt_cv_path_NM=${lt_cv_path_NM="$tmp_nm"} # keep the first match, but
++	    continue # so that we can try to find one that supports BSD flags
++	    ;;
++	  esac
++	  ;;
++	esac
++      fi
++    done
++    IFS="$lt_save_ifs"
++  done
++  : ${lt_cv_path_NM=no}
++fi
++fi
++{ $as_echo "$as_me:${as_lineno-$LINENO}: result: $lt_cv_path_NM" >&5
++$as_echo "$lt_cv_path_NM" >&6; }
++if test "$lt_cv_path_NM" != "no"; then
++  NM="$lt_cv_path_NM"
++else
++  # Didn't find any BSD compatible name lister, look for dumpbin.
++  if test -n "$DUMPBIN"; then :
++    # Let the user override the test.
++  else
++    if test -n "$ac_tool_prefix"; then
++  for ac_prog in dumpbin "link -dump"
++  do
++    # Extract the first word of "$ac_tool_prefix$ac_prog", so it can be a program name with args.
++set dummy $ac_tool_prefix$ac_prog; ac_word=$2
++{ $as_echo "$as_me:${as_lineno-$LINENO}: checking for $ac_word" >&5
++$as_echo_n "checking for $ac_word... " >&6; }
++if ${ac_cv_prog_DUMPBIN+:} false; then :
++  $as_echo_n "(cached) " >&6
++else
++  if test -n "$DUMPBIN"; then
++  ac_cv_prog_DUMPBIN="$DUMPBIN" # Let the user override the test.
++else
++as_save_IFS=$IFS; IFS=$PATH_SEPARATOR
++for as_dir in $PATH
++do
++  IFS=$as_save_IFS
++  test -z "$as_dir" && as_dir=.
++    for ac_exec_ext in '' $ac_executable_extensions; do
++  if as_fn_executable_p "$as_dir/$ac_word$ac_exec_ext"; then
++    ac_cv_prog_DUMPBIN="$ac_tool_prefix$ac_prog"
++    $as_echo "$as_me:${as_lineno-$LINENO}: found $as_dir/$ac_word$ac_exec_ext" >&5
++    break 2
++  fi
++done
++  done
++IFS=$as_save_IFS
++
++fi
++fi
++DUMPBIN=$ac_cv_prog_DUMPBIN
++if test -n "$DUMPBIN"; then
++  { $as_echo "$as_me:${as_lineno-$LINENO}: result: $DUMPBIN" >&5
++$as_echo "$DUMPBIN" >&6; }
++else
++  { $as_echo "$as_me:${as_lineno-$LINENO}: result: no" >&5
++$as_echo "no" >&6; }
++fi
++
++
++    test -n "$DUMPBIN" && break
++  done
++fi
++if test -z "$DUMPBIN"; then
++  ac_ct_DUMPBIN=$DUMPBIN
++  for ac_prog in dumpbin "link -dump"
++do
++  # Extract the first word of "$ac_prog", so it can be a program name with args.
++set dummy $ac_prog; ac_word=$2
++{ $as_echo "$as_me:${as_lineno-$LINENO}: checking for $ac_word" >&5
++$as_echo_n "checking for $ac_word... " >&6; }
++if ${ac_cv_prog_ac_ct_DUMPBIN+:} false; then :
++  $as_echo_n "(cached) " >&6
++else
++  if test -n "$ac_ct_DUMPBIN"; then
++  ac_cv_prog_ac_ct_DUMPBIN="$ac_ct_DUMPBIN" # Let the user override the test.
++else
++as_save_IFS=$IFS; IFS=$PATH_SEPARATOR
++for as_dir in $PATH
++do
++  IFS=$as_save_IFS
++  test -z "$as_dir" && as_dir=.
++    for ac_exec_ext in '' $ac_executable_extensions; do
++  if as_fn_executable_p "$as_dir/$ac_word$ac_exec_ext"; then
++    ac_cv_prog_ac_ct_DUMPBIN="$ac_prog"
++    $as_echo "$as_me:${as_lineno-$LINENO}: found $as_dir/$ac_word$ac_exec_ext" >&5
++    break 2
++  fi
++done
++  done
++IFS=$as_save_IFS
++
++fi
++fi
++ac_ct_DUMPBIN=$ac_cv_prog_ac_ct_DUMPBIN
++if test -n "$ac_ct_DUMPBIN"; then
++  { $as_echo "$as_me:${as_lineno-$LINENO}: result: $ac_ct_DUMPBIN" >&5
++$as_echo "$ac_ct_DUMPBIN" >&6; }
++else
++  { $as_echo "$as_me:${as_lineno-$LINENO}: result: no" >&5
++$as_echo "no" >&6; }
++fi
++
++
++  test -n "$ac_ct_DUMPBIN" && break
++done
++
++  if test "x$ac_ct_DUMPBIN" = x; then
++    DUMPBIN=":"
++  else
++    case $cross_compiling:$ac_tool_warned in
++yes:)
++{ $as_echo "$as_me:${as_lineno-$LINENO}: WARNING: using cross tools not prefixed with host triplet" >&5
++$as_echo "$as_me: WARNING: using cross tools not prefixed with host triplet" >&2;}
++ac_tool_warned=yes ;;
++esac
++    DUMPBIN=$ac_ct_DUMPBIN
++  fi
++fi
++
++    case `$DUMPBIN -symbols /dev/null 2>&1 | sed '1q'` in
++    *COFF*)
++      DUMPBIN="$DUMPBIN -symbols"
++      ;;
++    *)
++      DUMPBIN=:
++      ;;
++    esac
++  fi
++
++  if test "$DUMPBIN" != ":"; then
++    NM="$DUMPBIN"
++  fi
++fi
++test -z "$NM" && NM=nm
++
++
++
++
++
++
++{ $as_echo "$as_me:${as_lineno-$LINENO}: checking the name lister ($NM) interface" >&5
++$as_echo_n "checking the name lister ($NM) interface... " >&6; }
++if ${lt_cv_nm_interface+:} false; then :
++  $as_echo_n "(cached) " >&6
++else
++  lt_cv_nm_interface="BSD nm"
++  echo "int some_variable = 0;" > conftest.$ac_ext
++  (eval echo "\"\$as_me:$LINENO: $ac_compile\"" >&5)
++  (eval "$ac_compile" 2>conftest.err)
++  cat conftest.err >&5
++  (eval echo "\"\$as_me:$LINENO: $NM \\\"conftest.$ac_objext\\\"\"" >&5)
++  (eval "$NM \"conftest.$ac_objext\"" 2>conftest.err > conftest.out)
++  cat conftest.err >&5
++  (eval echo "\"\$as_me:$LINENO: output\"" >&5)
++  cat conftest.out >&5
++  if $GREP 'External.*some_variable' conftest.out > /dev/null; then
++    lt_cv_nm_interface="MS dumpbin"
++  fi
++  rm -f conftest*
++fi
++{ $as_echo "$as_me:${as_lineno-$LINENO}: result: $lt_cv_nm_interface" >&5
++$as_echo "$lt_cv_nm_interface" >&6; }
++
++{ $as_echo "$as_me:${as_lineno-$LINENO}: checking whether ln -s works" >&5
++$as_echo_n "checking whether ln -s works... " >&6; }
++LN_S=$as_ln_s
++if test "$LN_S" = "ln -s"; then
++  { $as_echo "$as_me:${as_lineno-$LINENO}: result: yes" >&5
++$as_echo "yes" >&6; }
++else
++  { $as_echo "$as_me:${as_lineno-$LINENO}: result: no, using $LN_S" >&5
++$as_echo "no, using $LN_S" >&6; }
++fi
++
++# find the maximum length of command line arguments
++{ $as_echo "$as_me:${as_lineno-$LINENO}: checking the maximum length of command line arguments" >&5
++$as_echo_n "checking the maximum length of command line arguments... " >&6; }
++if ${lt_cv_sys_max_cmd_len+:} false; then :
++  $as_echo_n "(cached) " >&6
++else
++    i=0
++  teststring="ABCD"
++
++  case $build_os in
++  msdosdjgpp*)
++    # On DJGPP, this test can blow up pretty badly due to problems in libc
++    # (any single argument exceeding 2000 bytes causes a buffer overrun
++    # during glob expansion).  Even if it were fixed, the result of this
++    # check would be larger than it should be.
++    lt_cv_sys_max_cmd_len=12288;    # 12K is about right
++    ;;
++
++  gnu*)
++    # Under GNU Hurd, this test is not required because there is
++    # no limit to the length of command line arguments.
++    # Libtool will interpret -1 as no limit whatsoever
++    lt_cv_sys_max_cmd_len=-1;
++    ;;
++
++  cygwin* | mingw* | cegcc*)
++    # On Win9x/ME, this test blows up -- it succeeds, but takes
++    # about 5 minutes as the teststring grows exponentially.
++    # Worse, since 9x/ME are not pre-emptively multitasking,
++    # you end up with a "frozen" computer, even though with patience
++    # the test eventually succeeds (with a max line length of 256k).
++    # Instead, let's just punt: use the minimum linelength reported by
++    # all of the supported platforms: 8192 (on NT/2K/XP).
++    lt_cv_sys_max_cmd_len=8192;
++    ;;
++
++  mint*)
++    # On MiNT this can take a long time and run out of memory.
++    lt_cv_sys_max_cmd_len=8192;
++    ;;
++
++  amigaos*)
++    # On AmigaOS with pdksh, this test takes hours, literally.
++    # So we just punt and use a minimum line length of 8192.
++    lt_cv_sys_max_cmd_len=8192;
++    ;;
++
++  netbsd* | freebsd* | openbsd* | darwin* | dragonfly*)
++    # This has been around since 386BSD, at least.  Likely further.
++    if test -x /sbin/sysctl; then
++      lt_cv_sys_max_cmd_len=`/sbin/sysctl -n kern.argmax`
++    elif test -x /usr/sbin/sysctl; then
++      lt_cv_sys_max_cmd_len=`/usr/sbin/sysctl -n kern.argmax`
++    else
++      lt_cv_sys_max_cmd_len=65536	# usable default for all BSDs
++    fi
++    # And add a safety zone
++    lt_cv_sys_max_cmd_len=`expr $lt_cv_sys_max_cmd_len \/ 4`
++    lt_cv_sys_max_cmd_len=`expr $lt_cv_sys_max_cmd_len \* 3`
++    ;;
++
++  interix*)
++    # We know the value 262144 and hardcode it with a safety zone (like BSD)
++    lt_cv_sys_max_cmd_len=196608
++    ;;
++
++  osf*)
++    # Dr. Hans Ekkehard Plesser reports seeing a kernel panic running configure
++    # due to this test when exec_disable_arg_limit is 1 on Tru64. It is not
++    # nice to cause kernel panics so lets avoid the loop below.
++    # First set a reasonable default.
++    lt_cv_sys_max_cmd_len=16384
++    #
++    if test -x /sbin/sysconfig; then
++      case `/sbin/sysconfig -q proc exec_disable_arg_limit` in
++        *1*) lt_cv_sys_max_cmd_len=-1 ;;
++      esac
++    fi
++    ;;
++  sco3.2v5*)
++    lt_cv_sys_max_cmd_len=102400
++    ;;
++  sysv5* | sco5v6* | sysv4.2uw2*)
++    kargmax=`grep ARG_MAX /etc/conf/cf.d/stune 2>/dev/null`
++    if test -n "$kargmax"; then
++      lt_cv_sys_max_cmd_len=`echo $kargmax | sed 's/.*[	 ]//'`
++    else
++      lt_cv_sys_max_cmd_len=32768
++    fi
++    ;;
++  *)
++    lt_cv_sys_max_cmd_len=`(getconf ARG_MAX) 2> /dev/null`
++    if test -n "$lt_cv_sys_max_cmd_len"; then
++      lt_cv_sys_max_cmd_len=`expr $lt_cv_sys_max_cmd_len \/ 4`
++      lt_cv_sys_max_cmd_len=`expr $lt_cv_sys_max_cmd_len \* 3`
++    else
++      # Make teststring a little bigger before we do anything with it.
++      # a 1K string should be a reasonable start.
++      for i in 1 2 3 4 5 6 7 8 ; do
++        teststring=$teststring$teststring
++      done
++      SHELL=${SHELL-${CONFIG_SHELL-/bin/sh}}
++      # If test is not a shell built-in, we'll probably end up computing a
++      # maximum length that is only half of the actual maximum length, but
++      # we can't tell.
++      while { test "X"`func_fallback_echo "$teststring$teststring" 2>/dev/null` \
++	         = "X$teststring$teststring"; } >/dev/null 2>&1 &&
++	      test $i != 17 # 1/2 MB should be enough
++      do
++        i=`expr $i + 1`
++        teststring=$teststring$teststring
++      done
++      # Only check the string length outside the loop.
++      lt_cv_sys_max_cmd_len=`expr "X$teststring" : ".*" 2>&1`
++      teststring=
++      # Add a significant safety factor because C++ compilers can tack on
++      # massive amounts of additional arguments before passing them to the
++      # linker.  It appears as though 1/2 is a usable value.
++      lt_cv_sys_max_cmd_len=`expr $lt_cv_sys_max_cmd_len \/ 2`
++    fi
++    ;;
++  esac
++
++fi
++
++if test -n $lt_cv_sys_max_cmd_len ; then
++  { $as_echo "$as_me:${as_lineno-$LINENO}: result: $lt_cv_sys_max_cmd_len" >&5
++$as_echo "$lt_cv_sys_max_cmd_len" >&6; }
++else
++  { $as_echo "$as_me:${as_lineno-$LINENO}: result: none" >&5
++$as_echo "none" >&6; }
++fi
++max_cmd_len=$lt_cv_sys_max_cmd_len
++
++
++
++
++
++
++: ${CP="cp -f"}
++: ${MV="mv -f"}
++: ${RM="rm -f"}
++
++{ $as_echo "$as_me:${as_lineno-$LINENO}: checking whether the shell understands some XSI constructs" >&5
++$as_echo_n "checking whether the shell understands some XSI constructs... " >&6; }
++# Try some XSI features
++xsi_shell=no
++( _lt_dummy="a/b/c"
++  test "${_lt_dummy##*/},${_lt_dummy%/*},"${_lt_dummy%"$_lt_dummy"}, \
++      = c,a/b,, \
++    && eval 'test $(( 1 + 1 )) -eq 2 \
++    && test "${#_lt_dummy}" -eq 5' ) >/dev/null 2>&1 \
++  && xsi_shell=yes
++{ $as_echo "$as_me:${as_lineno-$LINENO}: result: $xsi_shell" >&5
++$as_echo "$xsi_shell" >&6; }
++
++
++{ $as_echo "$as_me:${as_lineno-$LINENO}: checking whether the shell understands \"+=\"" >&5
++$as_echo_n "checking whether the shell understands \"+=\"... " >&6; }
++lt_shell_append=no
++( foo=bar; set foo baz; eval "$1+=\$2" && test "$foo" = barbaz ) \
++    >/dev/null 2>&1 \
++  && lt_shell_append=yes
++{ $as_echo "$as_me:${as_lineno-$LINENO}: result: $lt_shell_append" >&5
++$as_echo "$lt_shell_append" >&6; }
++
++
++if ( (MAIL=60; unset MAIL) || exit) >/dev/null 2>&1; then
++  lt_unset=unset
++else
++  lt_unset=false
++fi
++
++
++
++
++
++# test EBCDIC or ASCII
++case `echo X|tr X '\101'` in
++ A) # ASCII based system
++    # \n is not interpreted correctly by Solaris 8 /usr/ucb/tr
++  lt_SP2NL='tr \040 \012'
++  lt_NL2SP='tr \015\012 \040\040'
++  ;;
++ *) # EBCDIC based system
++  lt_SP2NL='tr \100 \n'
++  lt_NL2SP='tr \r\n \100\100'
++  ;;
++esac
++
++
++
++
++
++
++
++
++
++{ $as_echo "$as_me:${as_lineno-$LINENO}: checking for $LD option to reload object files" >&5
++$as_echo_n "checking for $LD option to reload object files... " >&6; }
++if ${lt_cv_ld_reload_flag+:} false; then :
++  $as_echo_n "(cached) " >&6
++else
++  lt_cv_ld_reload_flag='-r'
++fi
++{ $as_echo "$as_me:${as_lineno-$LINENO}: result: $lt_cv_ld_reload_flag" >&5
++$as_echo "$lt_cv_ld_reload_flag" >&6; }
++reload_flag=$lt_cv_ld_reload_flag
++case $reload_flag in
++"" | " "*) ;;
++*) reload_flag=" $reload_flag" ;;
++esac
++reload_cmds='$LD$reload_flag -o $output$reload_objs'
++case $host_os in
++  darwin*)
++    if test "$GCC" = yes; then
++      reload_cmds='$LTCC $LTCFLAGS -nostdlib ${wl}-r -o $output$reload_objs'
++    else
++      reload_cmds='$LD$reload_flag -o $output$reload_objs'
++    fi
++    ;;
++esac
++
++
++
++
++
++
++
++
++
++if test -n "$ac_tool_prefix"; then
++  # Extract the first word of "${ac_tool_prefix}objdump", so it can be a program name with args.
++set dummy ${ac_tool_prefix}objdump; ac_word=$2
++{ $as_echo "$as_me:${as_lineno-$LINENO}: checking for $ac_word" >&5
++$as_echo_n "checking for $ac_word... " >&6; }
++if ${ac_cv_prog_OBJDUMP+:} false; then :
++  $as_echo_n "(cached) " >&6
++else
++  if test -n "$OBJDUMP"; then
++  ac_cv_prog_OBJDUMP="$OBJDUMP" # Let the user override the test.
++else
++as_save_IFS=$IFS; IFS=$PATH_SEPARATOR
++for as_dir in $PATH
++do
++  IFS=$as_save_IFS
++  test -z "$as_dir" && as_dir=.
++    for ac_exec_ext in '' $ac_executable_extensions; do
++  if as_fn_executable_p "$as_dir/$ac_word$ac_exec_ext"; then
++    ac_cv_prog_OBJDUMP="${ac_tool_prefix}objdump"
++    $as_echo "$as_me:${as_lineno-$LINENO}: found $as_dir/$ac_word$ac_exec_ext" >&5
++    break 2
++  fi
++done
++  done
++IFS=$as_save_IFS
++
++fi
++fi
++OBJDUMP=$ac_cv_prog_OBJDUMP
++if test -n "$OBJDUMP"; then
++  { $as_echo "$as_me:${as_lineno-$LINENO}: result: $OBJDUMP" >&5
++$as_echo "$OBJDUMP" >&6; }
++else
++  { $as_echo "$as_me:${as_lineno-$LINENO}: result: no" >&5
++$as_echo "no" >&6; }
++fi
++
++
++fi
++if test -z "$ac_cv_prog_OBJDUMP"; then
++  ac_ct_OBJDUMP=$OBJDUMP
++  # Extract the first word of "objdump", so it can be a program name with args.
++set dummy objdump; ac_word=$2
++{ $as_echo "$as_me:${as_lineno-$LINENO}: checking for $ac_word" >&5
++$as_echo_n "checking for $ac_word... " >&6; }
++if ${ac_cv_prog_ac_ct_OBJDUMP+:} false; then :
++  $as_echo_n "(cached) " >&6
++else
++  if test -n "$ac_ct_OBJDUMP"; then
++  ac_cv_prog_ac_ct_OBJDUMP="$ac_ct_OBJDUMP" # Let the user override the test.
++else
++as_save_IFS=$IFS; IFS=$PATH_SEPARATOR
++for as_dir in $PATH
++do
++  IFS=$as_save_IFS
++  test -z "$as_dir" && as_dir=.
++    for ac_exec_ext in '' $ac_executable_extensions; do
++  if as_fn_executable_p "$as_dir/$ac_word$ac_exec_ext"; then
++    ac_cv_prog_ac_ct_OBJDUMP="objdump"
++    $as_echo "$as_me:${as_lineno-$LINENO}: found $as_dir/$ac_word$ac_exec_ext" >&5
++    break 2
++  fi
++done
++  done
++IFS=$as_save_IFS
++
++fi
++fi
++ac_ct_OBJDUMP=$ac_cv_prog_ac_ct_OBJDUMP
++if test -n "$ac_ct_OBJDUMP"; then
++  { $as_echo "$as_me:${as_lineno-$LINENO}: result: $ac_ct_OBJDUMP" >&5
++$as_echo "$ac_ct_OBJDUMP" >&6; }
++else
++  { $as_echo "$as_me:${as_lineno-$LINENO}: result: no" >&5
++$as_echo "no" >&6; }
++fi
++
++  if test "x$ac_ct_OBJDUMP" = x; then
++    OBJDUMP="false"
++  else
++    case $cross_compiling:$ac_tool_warned in
++yes:)
++{ $as_echo "$as_me:${as_lineno-$LINENO}: WARNING: using cross tools not prefixed with host triplet" >&5
++$as_echo "$as_me: WARNING: using cross tools not prefixed with host triplet" >&2;}
++ac_tool_warned=yes ;;
++esac
++    OBJDUMP=$ac_ct_OBJDUMP
++  fi
++else
++  OBJDUMP="$ac_cv_prog_OBJDUMP"
++fi
++
++test -z "$OBJDUMP" && OBJDUMP=objdump
++
++
++
++
++
++
++
++
++
++{ $as_echo "$as_me:${as_lineno-$LINENO}: checking how to recognize dependent libraries" >&5
++$as_echo_n "checking how to recognize dependent libraries... " >&6; }
++if ${lt_cv_deplibs_check_method+:} false; then :
++  $as_echo_n "(cached) " >&6
++else
++  lt_cv_file_magic_cmd='$MAGIC_CMD'
++lt_cv_file_magic_test_file=
++lt_cv_deplibs_check_method='unknown'
++# Need to set the preceding variable on all platforms that support
++# interlibrary dependencies.
++# 'none' -- dependencies not supported.
++# `unknown' -- same as none, but documents that we really don't know.
++# 'pass_all' -- all dependencies passed with no checks.
++# 'test_compile' -- check by making test program.
++# 'file_magic [[regex]]' -- check by looking for files in library path
++# which responds to the $file_magic_cmd with a given extended regex.
++# If you have `file' or equivalent on your system and you're not sure
++# whether `pass_all' will *always* work, you probably want this one.
++
++case $host_os in
++aix[4-9]*)
++  lt_cv_deplibs_check_method=pass_all
++  ;;
++
++beos*)
++  lt_cv_deplibs_check_method=pass_all
++  ;;
++
++bsdi[45]*)
++  lt_cv_deplibs_check_method='file_magic ELF [0-9][0-9]*-bit [ML]SB (shared object|dynamic lib)'
++  lt_cv_file_magic_cmd='/usr/bin/file -L'
++  lt_cv_file_magic_test_file=/shlib/libc.so
++  ;;
++
++cygwin*)
++  # func_win32_libid is a shell function defined in ltmain.sh
++  lt_cv_deplibs_check_method='file_magic ^x86 archive import|^x86 DLL'
++  lt_cv_file_magic_cmd='func_win32_libid'
++  ;;
++
++mingw* | pw32*)
++  # Base MSYS/MinGW do not provide the 'file' command needed by
++  # func_win32_libid shell function, so use a weaker test based on 'objdump',
++  # unless we find 'file', for example because we are cross-compiling.
++  # func_win32_libid assumes BSD nm, so disallow it if using MS dumpbin.
++  if ( test "$lt_cv_nm_interface" = "BSD nm" && file / ) >/dev/null 2>&1; then
++    lt_cv_deplibs_check_method='file_magic ^x86 archive import|^x86 DLL'
++    lt_cv_file_magic_cmd='func_win32_libid'
++  else
++    lt_cv_deplibs_check_method='file_magic file format pei*-i386(.*architecture: i386)?'
++    lt_cv_file_magic_cmd='$OBJDUMP -f'
++  fi
++  ;;
++
++cegcc*)
++  # use the weaker test based on 'objdump'. See mingw*.
++  lt_cv_deplibs_check_method='file_magic file format pe-arm-.*little(.*architecture: arm)?'
++  lt_cv_file_magic_cmd='$OBJDUMP -f'
++  ;;
++
++darwin* | rhapsody*)
++  lt_cv_deplibs_check_method=pass_all
++  ;;
++
++freebsd* | dragonfly*)
++  if echo __ELF__ | $CC -E - | $GREP __ELF__ > /dev/null; then
++    case $host_cpu in
++    i*86 )
++      # Not sure whether the presence of OpenBSD here was a mistake.
++      # Let's accept both of them until this is cleared up.
++      lt_cv_deplibs_check_method='file_magic (FreeBSD|OpenBSD|DragonFly)/i[3-9]86 (compact )?demand paged shared library'
++      lt_cv_file_magic_cmd=/usr/bin/file
++      lt_cv_file_magic_test_file=`echo /usr/lib/libc.so.*`
++      ;;
++    esac
++  else
++    lt_cv_deplibs_check_method=pass_all
++  fi
++  ;;
++
++gnu*)
++  lt_cv_deplibs_check_method=pass_all
++  ;;
++
++haiku*)
++  lt_cv_deplibs_check_method=pass_all
++  ;;
++
++hpux10.20* | hpux11*)
++  lt_cv_file_magic_cmd=/usr/bin/file
++  case $host_cpu in
++  ia64*)
++    lt_cv_deplibs_check_method='file_magic (s[0-9][0-9][0-9]|ELF-[0-9][0-9]) shared object file - IA64'
++    lt_cv_file_magic_test_file=/usr/lib/hpux32/libc.so
++    ;;
++  hppa*64*)
++    lt_cv_deplibs_check_method='file_magic (s[0-9][0-9][0-9]|ELF[ -][0-9][0-9])(-bit)?( [LM]SB)? shared object( file)?[, -]* PA-RISC [0-9]\.[0-9]'
++    lt_cv_file_magic_test_file=/usr/lib/pa20_64/libc.sl
++    ;;
++  *)
++    lt_cv_deplibs_check_method='file_magic (s[0-9][0-9][0-9]|PA-RISC[0-9]\.[0-9]) shared library'
++    lt_cv_file_magic_test_file=/usr/lib/libc.sl
++    ;;
++  esac
++  ;;
++
++interix[3-9]*)
++  # PIC code is broken on Interix 3.x, that's why |\.a not |_pic\.a here
++  lt_cv_deplibs_check_method='match_pattern /lib[^/]+(\.so|\.a)$'
++  ;;
++
++irix5* | irix6* | nonstopux*)
++  case $LD in
++  *-32|*"-32 ") libmagic=32-bit;;
++  *-n32|*"-n32 ") libmagic=N32;;
++  *-64|*"-64 ") libmagic=64-bit;;
++  *) libmagic=never-match;;
++  esac
++  lt_cv_deplibs_check_method=pass_all
++  ;;
++
++# This must be Linux ELF.
++linux* | k*bsd*-gnu | kopensolaris*-gnu)
++  lt_cv_deplibs_check_method=pass_all
++  ;;
++
++netbsd*)
++  if echo __ELF__ | $CC -E - | $GREP __ELF__ > /dev/null; then
++    lt_cv_deplibs_check_method='match_pattern /lib[^/]+(\.so\.[0-9]+\.[0-9]+|_pic\.a)$'
++  else
++    lt_cv_deplibs_check_method='match_pattern /lib[^/]+(\.so|_pic\.a)$'
++  fi
++  ;;
++
++newos6*)
++  lt_cv_deplibs_check_method='file_magic ELF [0-9][0-9]*-bit [ML]SB (executable|dynamic lib)'
++  lt_cv_file_magic_cmd=/usr/bin/file
++  lt_cv_file_magic_test_file=/usr/lib/libnls.so
++  ;;
++
++*nto* | *qnx*)
++  lt_cv_deplibs_check_method=pass_all
++  ;;
++
++openbsd*)
++  if test -z "`echo __ELF__ | $CC -E - | $GREP __ELF__`" || test "$host_os-$host_cpu" = "openbsd2.8-powerpc"; then
++    lt_cv_deplibs_check_method='match_pattern /lib[^/]+(\.so\.[0-9]+\.[0-9]+|\.so|_pic\.a)$'
++  else
++    lt_cv_deplibs_check_method='match_pattern /lib[^/]+(\.so\.[0-9]+\.[0-9]+|_pic\.a)$'
++  fi
++  ;;
++
++osf3* | osf4* | osf5*)
++  lt_cv_deplibs_check_method=pass_all
++  ;;
++
++rdos*)
++  lt_cv_deplibs_check_method=pass_all
++  ;;
++
++solaris*)
++  lt_cv_deplibs_check_method=pass_all
++  ;;
++
++sysv5* | sco3.2v5* | sco5v6* | unixware* | OpenUNIX* | sysv4*uw2*)
++  lt_cv_deplibs_check_method=pass_all
++  ;;
++
++sysv4 | sysv4.3*)
++  case $host_vendor in
++  motorola)
++    lt_cv_deplibs_check_method='file_magic ELF [0-9][0-9]*-bit [ML]SB (shared object|dynamic lib) M[0-9][0-9]* Version [0-9]'
++    lt_cv_file_magic_test_file=`echo /usr/lib/libc.so*`
++    ;;
++  ncr)
++    lt_cv_deplibs_check_method=pass_all
++    ;;
++  sequent)
++    lt_cv_file_magic_cmd='/bin/file'
++    lt_cv_deplibs_check_method='file_magic ELF [0-9][0-9]*-bit [LM]SB (shared object|dynamic lib )'
++    ;;
++  sni)
++    lt_cv_file_magic_cmd='/bin/file'
++    lt_cv_deplibs_check_method="file_magic ELF [0-9][0-9]*-bit [LM]SB dynamic lib"
++    lt_cv_file_magic_test_file=/lib/libc.so
++    ;;
++  siemens)
++    lt_cv_deplibs_check_method=pass_all
++    ;;
++  pc)
++    lt_cv_deplibs_check_method=pass_all
++    ;;
++  esac
++  ;;
++
++tpf*)
++  lt_cv_deplibs_check_method=pass_all
++  ;;
++esac
++
++fi
++{ $as_echo "$as_me:${as_lineno-$LINENO}: result: $lt_cv_deplibs_check_method" >&5
++$as_echo "$lt_cv_deplibs_check_method" >&6; }
++file_magic_cmd=$lt_cv_file_magic_cmd
++deplibs_check_method=$lt_cv_deplibs_check_method
++test -z "$deplibs_check_method" && deplibs_check_method=unknown
++
++
++
++
++
++
++
++
++
++
++
++
++if test -n "$ac_tool_prefix"; then
++  # Extract the first word of "${ac_tool_prefix}ar", so it can be a program name with args.
++set dummy ${ac_tool_prefix}ar; ac_word=$2
++{ $as_echo "$as_me:${as_lineno-$LINENO}: checking for $ac_word" >&5
++$as_echo_n "checking for $ac_word... " >&6; }
++if ${ac_cv_prog_AR+:} false; then :
++  $as_echo_n "(cached) " >&6
++else
++  if test -n "$AR"; then
++  ac_cv_prog_AR="$AR" # Let the user override the test.
++else
++as_save_IFS=$IFS; IFS=$PATH_SEPARATOR
++for as_dir in $PATH
++do
++  IFS=$as_save_IFS
++  test -z "$as_dir" && as_dir=.
++    for ac_exec_ext in '' $ac_executable_extensions; do
++  if as_fn_executable_p "$as_dir/$ac_word$ac_exec_ext"; then
++    ac_cv_prog_AR="${ac_tool_prefix}ar"
++    $as_echo "$as_me:${as_lineno-$LINENO}: found $as_dir/$ac_word$ac_exec_ext" >&5
++    break 2
++  fi
++done
++  done
++IFS=$as_save_IFS
++
++fi
++fi
++AR=$ac_cv_prog_AR
++if test -n "$AR"; then
++  { $as_echo "$as_me:${as_lineno-$LINENO}: result: $AR" >&5
++$as_echo "$AR" >&6; }
++else
++  { $as_echo "$as_me:${as_lineno-$LINENO}: result: no" >&5
++$as_echo "no" >&6; }
++fi
++
++
++fi
++if test -z "$ac_cv_prog_AR"; then
++  ac_ct_AR=$AR
++  # Extract the first word of "ar", so it can be a program name with args.
++set dummy ar; ac_word=$2
++{ $as_echo "$as_me:${as_lineno-$LINENO}: checking for $ac_word" >&5
++$as_echo_n "checking for $ac_word... " >&6; }
++if ${ac_cv_prog_ac_ct_AR+:} false; then :
++  $as_echo_n "(cached) " >&6
++else
++  if test -n "$ac_ct_AR"; then
++  ac_cv_prog_ac_ct_AR="$ac_ct_AR" # Let the user override the test.
++else
++as_save_IFS=$IFS; IFS=$PATH_SEPARATOR
++for as_dir in $PATH
++do
++  IFS=$as_save_IFS
++  test -z "$as_dir" && as_dir=.
++    for ac_exec_ext in '' $ac_executable_extensions; do
++  if as_fn_executable_p "$as_dir/$ac_word$ac_exec_ext"; then
++    ac_cv_prog_ac_ct_AR="ar"
++    $as_echo "$as_me:${as_lineno-$LINENO}: found $as_dir/$ac_word$ac_exec_ext" >&5
++    break 2
++  fi
++done
++  done
++IFS=$as_save_IFS
++
++fi
++fi
++ac_ct_AR=$ac_cv_prog_ac_ct_AR
++if test -n "$ac_ct_AR"; then
++  { $as_echo "$as_me:${as_lineno-$LINENO}: result: $ac_ct_AR" >&5
++$as_echo "$ac_ct_AR" >&6; }
++else
++  { $as_echo "$as_me:${as_lineno-$LINENO}: result: no" >&5
++$as_echo "no" >&6; }
++fi
++
++  if test "x$ac_ct_AR" = x; then
++    AR="false"
++  else
++    case $cross_compiling:$ac_tool_warned in
++yes:)
++{ $as_echo "$as_me:${as_lineno-$LINENO}: WARNING: using cross tools not prefixed with host triplet" >&5
++$as_echo "$as_me: WARNING: using cross tools not prefixed with host triplet" >&2;}
++ac_tool_warned=yes ;;
++esac
++    AR=$ac_ct_AR
++  fi
++else
++  AR="$ac_cv_prog_AR"
++fi
++
++test -z "$AR" && AR=ar
++test -z "$AR_FLAGS" && AR_FLAGS=cru
++
++
++
++
++
++
++
++
++
++
++
++if test -n "$ac_tool_prefix"; then
++  # Extract the first word of "${ac_tool_prefix}strip", so it can be a program name with args.
++set dummy ${ac_tool_prefix}strip; ac_word=$2
++{ $as_echo "$as_me:${as_lineno-$LINENO}: checking for $ac_word" >&5
++$as_echo_n "checking for $ac_word... " >&6; }
++if ${ac_cv_prog_STRIP+:} false; then :
++  $as_echo_n "(cached) " >&6
++else
++  if test -n "$STRIP"; then
++  ac_cv_prog_STRIP="$STRIP" # Let the user override the test.
++else
++as_save_IFS=$IFS; IFS=$PATH_SEPARATOR
++for as_dir in $PATH
++do
++  IFS=$as_save_IFS
++  test -z "$as_dir" && as_dir=.
++    for ac_exec_ext in '' $ac_executable_extensions; do
++  if as_fn_executable_p "$as_dir/$ac_word$ac_exec_ext"; then
++    ac_cv_prog_STRIP="${ac_tool_prefix}strip"
++    $as_echo "$as_me:${as_lineno-$LINENO}: found $as_dir/$ac_word$ac_exec_ext" >&5
++    break 2
++  fi
++done
++  done
++IFS=$as_save_IFS
++
++fi
++fi
++STRIP=$ac_cv_prog_STRIP
++if test -n "$STRIP"; then
++  { $as_echo "$as_me:${as_lineno-$LINENO}: result: $STRIP" >&5
++$as_echo "$STRIP" >&6; }
++else
++  { $as_echo "$as_me:${as_lineno-$LINENO}: result: no" >&5
++$as_echo "no" >&6; }
++fi
++
++
++fi
++if test -z "$ac_cv_prog_STRIP"; then
++  ac_ct_STRIP=$STRIP
++  # Extract the first word of "strip", so it can be a program name with args.
++set dummy strip; ac_word=$2
++{ $as_echo "$as_me:${as_lineno-$LINENO}: checking for $ac_word" >&5
++$as_echo_n "checking for $ac_word... " >&6; }
++if ${ac_cv_prog_ac_ct_STRIP+:} false; then :
++  $as_echo_n "(cached) " >&6
++else
++  if test -n "$ac_ct_STRIP"; then
++  ac_cv_prog_ac_ct_STRIP="$ac_ct_STRIP" # Let the user override the test.
++else
++as_save_IFS=$IFS; IFS=$PATH_SEPARATOR
++for as_dir in $PATH
++do
++  IFS=$as_save_IFS
++  test -z "$as_dir" && as_dir=.
++    for ac_exec_ext in '' $ac_executable_extensions; do
++  if as_fn_executable_p "$as_dir/$ac_word$ac_exec_ext"; then
++    ac_cv_prog_ac_ct_STRIP="strip"
++    $as_echo "$as_me:${as_lineno-$LINENO}: found $as_dir/$ac_word$ac_exec_ext" >&5
++    break 2
++  fi
++done
++  done
++IFS=$as_save_IFS
++
++fi
++fi
++ac_ct_STRIP=$ac_cv_prog_ac_ct_STRIP
++if test -n "$ac_ct_STRIP"; then
++  { $as_echo "$as_me:${as_lineno-$LINENO}: result: $ac_ct_STRIP" >&5
++$as_echo "$ac_ct_STRIP" >&6; }
++else
++  { $as_echo "$as_me:${as_lineno-$LINENO}: result: no" >&5
++$as_echo "no" >&6; }
++fi
++
++  if test "x$ac_ct_STRIP" = x; then
++    STRIP=":"
++  else
++    case $cross_compiling:$ac_tool_warned in
++yes:)
++{ $as_echo "$as_me:${as_lineno-$LINENO}: WARNING: using cross tools not prefixed with host triplet" >&5
++$as_echo "$as_me: WARNING: using cross tools not prefixed with host triplet" >&2;}
++ac_tool_warned=yes ;;
++esac
++    STRIP=$ac_ct_STRIP
++  fi
++else
++  STRIP="$ac_cv_prog_STRIP"
++fi
++
++test -z "$STRIP" && STRIP=:
++
++
++
++
++
++
++if test -n "$ac_tool_prefix"; then
++  # Extract the first word of "${ac_tool_prefix}ranlib", so it can be a program name with args.
++set dummy ${ac_tool_prefix}ranlib; ac_word=$2
++{ $as_echo "$as_me:${as_lineno-$LINENO}: checking for $ac_word" >&5
++$as_echo_n "checking for $ac_word... " >&6; }
++if ${ac_cv_prog_RANLIB+:} false; then :
++  $as_echo_n "(cached) " >&6
++else
++  if test -n "$RANLIB"; then
++  ac_cv_prog_RANLIB="$RANLIB" # Let the user override the test.
++else
++as_save_IFS=$IFS; IFS=$PATH_SEPARATOR
++for as_dir in $PATH
++do
++  IFS=$as_save_IFS
++  test -z "$as_dir" && as_dir=.
++    for ac_exec_ext in '' $ac_executable_extensions; do
++  if as_fn_executable_p "$as_dir/$ac_word$ac_exec_ext"; then
++    ac_cv_prog_RANLIB="${ac_tool_prefix}ranlib"
++    $as_echo "$as_me:${as_lineno-$LINENO}: found $as_dir/$ac_word$ac_exec_ext" >&5
++    break 2
++  fi
++done
++  done
++IFS=$as_save_IFS
++
++fi
++fi
++RANLIB=$ac_cv_prog_RANLIB
++if test -n "$RANLIB"; then
++  { $as_echo "$as_me:${as_lineno-$LINENO}: result: $RANLIB" >&5
++$as_echo "$RANLIB" >&6; }
++else
++  { $as_echo "$as_me:${as_lineno-$LINENO}: result: no" >&5
++$as_echo "no" >&6; }
++fi
++
++
++fi
++if test -z "$ac_cv_prog_RANLIB"; then
++  ac_ct_RANLIB=$RANLIB
++  # Extract the first word of "ranlib", so it can be a program name with args.
++set dummy ranlib; ac_word=$2
++{ $as_echo "$as_me:${as_lineno-$LINENO}: checking for $ac_word" >&5
++$as_echo_n "checking for $ac_word... " >&6; }
++if ${ac_cv_prog_ac_ct_RANLIB+:} false; then :
++  $as_echo_n "(cached) " >&6
++else
++  if test -n "$ac_ct_RANLIB"; then
++  ac_cv_prog_ac_ct_RANLIB="$ac_ct_RANLIB" # Let the user override the test.
++else
++as_save_IFS=$IFS; IFS=$PATH_SEPARATOR
++for as_dir in $PATH
++do
++  IFS=$as_save_IFS
++  test -z "$as_dir" && as_dir=.
++    for ac_exec_ext in '' $ac_executable_extensions; do
++  if as_fn_executable_p "$as_dir/$ac_word$ac_exec_ext"; then
++    ac_cv_prog_ac_ct_RANLIB="ranlib"
++    $as_echo "$as_me:${as_lineno-$LINENO}: found $as_dir/$ac_word$ac_exec_ext" >&5
++    break 2
++  fi
++done
++  done
++IFS=$as_save_IFS
++
++fi
++fi
++ac_ct_RANLIB=$ac_cv_prog_ac_ct_RANLIB
++if test -n "$ac_ct_RANLIB"; then
++  { $as_echo "$as_me:${as_lineno-$LINENO}: result: $ac_ct_RANLIB" >&5
++$as_echo "$ac_ct_RANLIB" >&6; }
++else
++  { $as_echo "$as_me:${as_lineno-$LINENO}: result: no" >&5
++$as_echo "no" >&6; }
++fi
++
++  if test "x$ac_ct_RANLIB" = x; then
++    RANLIB=":"
++  else
++    case $cross_compiling:$ac_tool_warned in
++yes:)
++{ $as_echo "$as_me:${as_lineno-$LINENO}: WARNING: using cross tools not prefixed with host triplet" >&5
++$as_echo "$as_me: WARNING: using cross tools not prefixed with host triplet" >&2;}
++ac_tool_warned=yes ;;
++esac
++    RANLIB=$ac_ct_RANLIB
++  fi
++else
++  RANLIB="$ac_cv_prog_RANLIB"
++fi
++
++test -z "$RANLIB" && RANLIB=:
++
++
++
++
++
++
++# Determine commands to create old-style static archives.
++old_archive_cmds='$AR $AR_FLAGS $oldlib$oldobjs'
++old_postinstall_cmds='chmod 644 $oldlib'
++old_postuninstall_cmds=
++
++if test -n "$RANLIB"; then
++  case $host_os in
++  openbsd*)
++    old_postinstall_cmds="$old_postinstall_cmds~\$RANLIB -t \$oldlib"
++    ;;
++  *)
++    old_postinstall_cmds="$old_postinstall_cmds~\$RANLIB \$oldlib"
++    ;;
++  esac
++  old_archive_cmds="$old_archive_cmds~\$RANLIB \$oldlib"
++fi
++
++case $host_os in
++  darwin*)
++    lock_old_archive_extraction=yes ;;
++  *)
++    lock_old_archive_extraction=no ;;
++esac
++
++
++
++
++
++
++
++
++
++
++
++
++
++
++
++
++
++
++
++
++
++for ac_prog in gawk mawk nawk awk
++do
++  # Extract the first word of "$ac_prog", so it can be a program name with args.
++set dummy $ac_prog; ac_word=$2
++{ $as_echo "$as_me:${as_lineno-$LINENO}: checking for $ac_word" >&5
++$as_echo_n "checking for $ac_word... " >&6; }
++if ${ac_cv_prog_AWK+:} false; then :
++  $as_echo_n "(cached) " >&6
++else
++  if test -n "$AWK"; then
++  ac_cv_prog_AWK="$AWK" # Let the user override the test.
++else
++as_save_IFS=$IFS; IFS=$PATH_SEPARATOR
++for as_dir in $PATH
++do
++  IFS=$as_save_IFS
++  test -z "$as_dir" && as_dir=.
++    for ac_exec_ext in '' $ac_executable_extensions; do
++  if as_fn_executable_p "$as_dir/$ac_word$ac_exec_ext"; then
++    ac_cv_prog_AWK="$ac_prog"
++    $as_echo "$as_me:${as_lineno-$LINENO}: found $as_dir/$ac_word$ac_exec_ext" >&5
++    break 2
++  fi
++done
++  done
++IFS=$as_save_IFS
++
++fi
++fi
++AWK=$ac_cv_prog_AWK
++if test -n "$AWK"; then
++  { $as_echo "$as_me:${as_lineno-$LINENO}: result: $AWK" >&5
++$as_echo "$AWK" >&6; }
++else
++  { $as_echo "$as_me:${as_lineno-$LINENO}: result: no" >&5
++$as_echo "no" >&6; }
++fi
++
++
++  test -n "$AWK" && break
++done
++
++
++
++
++
++
++
++
++
++
++
++
++
++
++
++
++
++
++
++# If no C compiler was specified, use CC.
++LTCC=${LTCC-"$CC"}
++
++# If no C compiler flags were specified, use CFLAGS.
++LTCFLAGS=${LTCFLAGS-"$CFLAGS"}
++
++# Allow CC to be a program name with arguments.
++compiler=$CC
++
++
++# Check for command to grab the raw symbol name followed by C symbol from nm.
++{ $as_echo "$as_me:${as_lineno-$LINENO}: checking command to parse $NM output from $compiler object" >&5
++$as_echo_n "checking command to parse $NM output from $compiler object... " >&6; }
++if ${lt_cv_sys_global_symbol_pipe+:} false; then :
++  $as_echo_n "(cached) " >&6
++else
++
++# These are sane defaults that work on at least a few old systems.
++# [They come from Ultrix.  What could be older than Ultrix?!! ;)]
++
++# Character class describing NM global symbol codes.
++symcode='[BCDEGRST]'
++
++# Regexp to match symbols that can be accessed directly from C.
++sympat='\([_A-Za-z][_A-Za-z0-9]*\)'
++
++# Define system-specific variables.
++case $host_os in
++aix*)
++  symcode='[BCDT]'
++  ;;
++cygwin* | mingw* | pw32* | cegcc*)
++  symcode='[ABCDGISTW]'
++  ;;
++hpux*)
++  if test "$host_cpu" = ia64; then
++    symcode='[ABCDEGRST]'
++  fi
++  ;;
++irix* | nonstopux*)
++  symcode='[BCDEGRST]'
++  ;;
++osf*)
++  symcode='[BCDEGQRST]'
++  ;;
++solaris*)
++  symcode='[BDRT]'
++  ;;
++sco3.2v5*)
++  symcode='[DT]'
++  ;;
++sysv4.2uw2*)
++  symcode='[DT]'
++  ;;
++sysv5* | sco5v6* | unixware* | OpenUNIX*)
++  symcode='[ABDT]'
++  ;;
++sysv4)
++  symcode='[DFNSTU]'
++  ;;
++esac
++
++# If we're using GNU nm, then use its standard symbol codes.
++case `$NM -V 2>&1` in
++*GNU* | *'with BFD'*)
++  symcode='[ABCDGIRSTW]' ;;
++esac
++
++# Transform an extracted symbol line into a proper C declaration.
++# Some systems (esp. on ia64) link data and code symbols differently,
++# so use this general approach.
++lt_cv_sys_global_symbol_to_cdecl="sed -n -e 's/^T .* \(.*\)$/extern int \1();/p' -e 's/^$symcode* .* \(.*\)$/extern char \1;/p'"
++
++# Transform an extracted symbol line into symbol name and symbol address
++lt_cv_sys_global_symbol_to_c_name_address="sed -n -e 's/^: \([^ ]*\) $/  {\\\"\1\\\", (void *) 0},/p' -e 's/^$symcode* \([^ ]*\) \([^ ]*\)$/  {\"\2\", (void *) \&\2},/p'"
++lt_cv_sys_global_symbol_to_c_name_address_lib_prefix="sed -n -e 's/^: \([^ ]*\) $/  {\\\"\1\\\", (void *) 0},/p' -e 's/^$symcode* \([^ ]*\) \(lib[^ ]*\)$/  {\"\2\", (void *) \&\2},/p' -e 's/^$symcode* \([^ ]*\) \([^ ]*\)$/  {\"lib\2\", (void *) \&\2},/p'"
++
++# Handle CRLF in mingw tool chain
++opt_cr=
++case $build_os in
++mingw*)
++  opt_cr=`$ECHO 'x\{0,1\}' | tr x '\015'` # option cr in regexp
++  ;;
++esac
++
++# Try without a prefix underscore, then with it.
++for ac_symprfx in "" "_"; do
++
++  # Transform symcode, sympat, and symprfx into a raw symbol and a C symbol.
++  symxfrm="\\1 $ac_symprfx\\2 \\2"
++
++  # Write the raw and C identifiers.
++  if test "$lt_cv_nm_interface" = "MS dumpbin"; then
++    # Fake it for dumpbin and say T for any non-static function
++    # and D for any global variable.
++    # Also find C++ and __fastcall symbols from MSVC++,
++    # which start with @ or ?.
++    lt_cv_sys_global_symbol_pipe="$AWK '"\
++"     {last_section=section; section=\$ 3};"\
++"     /Section length .*#relocs.*(pick any)/{hide[last_section]=1};"\
++"     \$ 0!~/External *\|/{next};"\
++"     / 0+ UNDEF /{next}; / UNDEF \([^|]\)*()/{next};"\
++"     {if(hide[section]) next};"\
++"     {f=0}; \$ 0~/\(\).*\|/{f=1}; {printf f ? \"T \" : \"D \"};"\
++"     {split(\$ 0, a, /\||\r/); split(a[2], s)};"\
++"     s[1]~/^[@?]/{print s[1], s[1]; next};"\
++"     s[1]~prfx {split(s[1],t,\"@\"); print t[1], substr(t[1],length(prfx))}"\
++"     ' prfx=^$ac_symprfx"
++  else
++    lt_cv_sys_global_symbol_pipe="sed -n -e 's/^.*[	 ]\($symcode$symcode*\)[	 ][	 ]*$ac_symprfx$sympat$opt_cr$/$symxfrm/p'"
++  fi
++
++  # Check to see that the pipe works correctly.
++  pipe_works=no
++
++  rm -f conftest*
++  cat > conftest.$ac_ext <<_LT_EOF
++#ifdef __cplusplus
++extern "C" {
++#endif
++char nm_test_var;
++void nm_test_func(void);
++void nm_test_func(void){}
++#ifdef __cplusplus
++}
++#endif
++int main(){nm_test_var='a';nm_test_func();return(0);}
++_LT_EOF
++
++  if { { eval echo "\"\$as_me\":${as_lineno-$LINENO}: \"$ac_compile\""; } >&5
++  (eval $ac_compile) 2>&5
++  ac_status=$?
++  $as_echo "$as_me:${as_lineno-$LINENO}: \$? = $ac_status" >&5
++  test $ac_status = 0; }; then
++    # Now try to grab the symbols.
++    nlist=conftest.nm
++    if { { eval echo "\"\$as_me\":${as_lineno-$LINENO}: \"$NM conftest.$ac_objext \| "$lt_cv_sys_global_symbol_pipe" \> $nlist\""; } >&5
++  (eval $NM conftest.$ac_objext \| "$lt_cv_sys_global_symbol_pipe" \> $nlist) 2>&5
++  ac_status=$?
++  $as_echo "$as_me:${as_lineno-$LINENO}: \$? = $ac_status" >&5
++  test $ac_status = 0; } && test -s "$nlist"; then
++      # Try sorting and uniquifying the output.
++      if sort "$nlist" | uniq > "$nlist"T; then
++	mv -f "$nlist"T "$nlist"
++      else
++	rm -f "$nlist"T
++      fi
++
++      # Make sure that we snagged all the symbols we need.
++      if $GREP ' nm_test_var$' "$nlist" >/dev/null; then
++	if $GREP ' nm_test_func$' "$nlist" >/dev/null; then
++	  cat <<_LT_EOF > conftest.$ac_ext
++#ifdef __cplusplus
++extern "C" {
++#endif
++
++_LT_EOF
++	  # Now generate the symbol file.
++	  eval "$lt_cv_sys_global_symbol_to_cdecl"' < "$nlist" | $GREP -v main >> conftest.$ac_ext'
++
++	  cat <<_LT_EOF >> conftest.$ac_ext
++
++/* The mapping between symbol names and symbols.  */
++const struct {
++  const char *name;
++  void       *address;
++}
++lt__PROGRAM__LTX_preloaded_symbols[] =
++{
++  { "@PROGRAM@", (void *) 0 },
++_LT_EOF
++	  $SED "s/^$symcode$symcode* \(.*\) \(.*\)$/  {\"\2\", (void *) \&\2},/" < "$nlist" | $GREP -v main >> conftest.$ac_ext
++	  cat <<\_LT_EOF >> conftest.$ac_ext
++  {0, (void *) 0}
++};
++
++/* This works around a problem in FreeBSD linker */
++#ifdef FREEBSD_WORKAROUND
++static const void *lt_preloaded_setup() {
++  return lt__PROGRAM__LTX_preloaded_symbols;
++}
++#endif
++
++#ifdef __cplusplus
++}
++#endif
++_LT_EOF
++	  # Now try linking the two files.
++	  mv conftest.$ac_objext conftstm.$ac_objext
++	  lt_save_LIBS="$LIBS"
++	  lt_save_CFLAGS="$CFLAGS"
++	  LIBS="conftstm.$ac_objext"
++	  CFLAGS="$CFLAGS$lt_prog_compiler_no_builtin_flag"
++	  if { { eval echo "\"\$as_me\":${as_lineno-$LINENO}: \"$ac_link\""; } >&5
++  (eval $ac_link) 2>&5
++  ac_status=$?
++  $as_echo "$as_me:${as_lineno-$LINENO}: \$? = $ac_status" >&5
++  test $ac_status = 0; } && test -s conftest${ac_exeext}; then
++	    pipe_works=yes
++	  fi
++	  LIBS="$lt_save_LIBS"
++	  CFLAGS="$lt_save_CFLAGS"
++	else
++	  echo "cannot find nm_test_func in $nlist" >&5
++	fi
++      else
++	echo "cannot find nm_test_var in $nlist" >&5
++      fi
++    else
++      echo "cannot run $lt_cv_sys_global_symbol_pipe" >&5
++    fi
++  else
++    echo "$progname: failed program was:" >&5
++    cat conftest.$ac_ext >&5
++  fi
++  rm -rf conftest* conftst*
++
++  # Do not use the global_symbol_pipe unless it works.
++  if test "$pipe_works" = yes; then
++    break
++  else
++    lt_cv_sys_global_symbol_pipe=
++  fi
++done
++
++fi
++
++if test -z "$lt_cv_sys_global_symbol_pipe"; then
++  lt_cv_sys_global_symbol_to_cdecl=
++fi
++if test -z "$lt_cv_sys_global_symbol_pipe$lt_cv_sys_global_symbol_to_cdecl"; then
++  { $as_echo "$as_me:${as_lineno-$LINENO}: result: failed" >&5
++$as_echo "failed" >&6; }
++else
++  { $as_echo "$as_me:${as_lineno-$LINENO}: result: ok" >&5
++$as_echo "ok" >&6; }
++fi
++
++
++
++
++
++
++
++
++
++
++
++
++
++
++
++
++
++
++
++
++
++
++# Check whether --enable-libtool-lock was given.
++if test "${enable_libtool_lock+set}" = set; then :
++  enableval=$enable_libtool_lock;
++fi
++
++test "x$enable_libtool_lock" != xno && enable_libtool_lock=yes
++
++# Some flags need to be propagated to the compiler or linker for good
++# libtool support.
++case $host in
++ia64-*-hpux*)
++  # Find out which ABI we are using.
++  echo 'int i;' > conftest.$ac_ext
++  if { { eval echo "\"\$as_me\":${as_lineno-$LINENO}: \"$ac_compile\""; } >&5
++  (eval $ac_compile) 2>&5
++  ac_status=$?
++  $as_echo "$as_me:${as_lineno-$LINENO}: \$? = $ac_status" >&5
++  test $ac_status = 0; }; then
++    case `/usr/bin/file conftest.$ac_objext` in
++      *ELF-32*)
++	HPUX_IA64_MODE="32"
++	;;
++      *ELF-64*)
++	HPUX_IA64_MODE="64"
++	;;
++    esac
++  fi
++  rm -rf conftest*
++  ;;
++*-*-irix6*)
++  # Find out which ABI we are using.
++  echo '#line '$LINENO' "configure"' > conftest.$ac_ext
++  if { { eval echo "\"\$as_me\":${as_lineno-$LINENO}: \"$ac_compile\""; } >&5
++  (eval $ac_compile) 2>&5
++  ac_status=$?
++  $as_echo "$as_me:${as_lineno-$LINENO}: \$? = $ac_status" >&5
++  test $ac_status = 0; }; then
++    if test "$lt_cv_prog_gnu_ld" = yes; then
++      case `/usr/bin/file conftest.$ac_objext` in
++	*32-bit*)
++	  LD="${LD-ld} -melf32bsmip"
++	  ;;
++	*N32*)
++	  LD="${LD-ld} -melf32bmipn32"
++	  ;;
++	*64-bit*)
++	  LD="${LD-ld} -melf64bmip"
++	;;
++      esac
++    else
++      case `/usr/bin/file conftest.$ac_objext` in
++	*32-bit*)
++	  LD="${LD-ld} -32"
++	  ;;
++	*N32*)
++	  LD="${LD-ld} -n32"
++	  ;;
++	*64-bit*)
++	  LD="${LD-ld} -64"
++	  ;;
++      esac
++    fi
++  fi
++  rm -rf conftest*
++  ;;
++
++x86_64-*kfreebsd*-gnu|x86_64-*linux*|powerpc*-*linux*| \
++s390*-*linux*|s390*-*tpf*|sparc*-*linux*)
++  # Find out which ABI we are using.
++  echo 'int i;' > conftest.$ac_ext
++  if { { eval echo "\"\$as_me\":${as_lineno-$LINENO}: \"$ac_compile\""; } >&5
++  (eval $ac_compile) 2>&5
++  ac_status=$?
++  $as_echo "$as_me:${as_lineno-$LINENO}: \$? = $ac_status" >&5
++  test $ac_status = 0; }; then
++    case `/usr/bin/file conftest.o` in
++      *32-bit*)
++	case $host in
++	  x86_64-*kfreebsd*-gnu)
++	    LD="${LD-ld} -m elf_i386_fbsd"
++	    ;;
++	  x86_64-*linux*)
++	    case `/usr/bin/file conftest.o` in
++	      *x86-64*)
++		LD="${LD-ld} -m elf32_x86_64"
++		;;
++	      *)
++		LD="${LD-ld} -m elf_i386"
++		;;
++	    esac
++	    ;;
++	  powerpc64le-*linux*)
++	    LD="${LD-ld} -m elf32lppclinux"
++	    ;;
++	  powerpc64-*linux*)
++	    LD="${LD-ld} -m elf32ppclinux"
++	    ;;
++	  s390x-*linux*)
++	    LD="${LD-ld} -m elf_s390"
++	    ;;
++	  sparc64-*linux*)
++	    LD="${LD-ld} -m elf32_sparc"
++	    ;;
++	esac
++	;;
++      *64-bit*)
++	case $host in
++	  x86_64-*kfreebsd*-gnu)
++	    LD="${LD-ld} -m elf_x86_64_fbsd"
++	    ;;
++	  x86_64-*linux*)
++	    LD="${LD-ld} -m elf_x86_64"
++	    ;;
++	  powerpcle-*linux*)
++	    LD="${LD-ld} -m elf64lppc"
++	    ;;
++	  powerpc-*linux*)
++	    LD="${LD-ld} -m elf64ppc"
++	    ;;
++	  s390*-*linux*|s390*-*tpf*)
++	    LD="${LD-ld} -m elf64_s390"
++	    ;;
++	  sparc*-*linux*)
++	    LD="${LD-ld} -m elf64_sparc"
++	    ;;
++	esac
++	;;
++    esac
++  fi
++  rm -rf conftest*
++  ;;
++
++*-*-sco3.2v5*)
++  # On SCO OpenServer 5, we need -belf to get full-featured binaries.
++  SAVE_CFLAGS="$CFLAGS"
++  CFLAGS="$CFLAGS -belf"
++  { $as_echo "$as_me:${as_lineno-$LINENO}: checking whether the C compiler needs -belf" >&5
++$as_echo_n "checking whether the C compiler needs -belf... " >&6; }
++if ${lt_cv_cc_needs_belf+:} false; then :
++  $as_echo_n "(cached) " >&6
++else
++  ac_ext=c
++ac_cpp='$CPP $CPPFLAGS'
++ac_compile='$CC -c $CFLAGS $CPPFLAGS conftest.$ac_ext >&5'
++ac_link='$CC -o conftest$ac_exeext $CFLAGS $CPPFLAGS $LDFLAGS conftest.$ac_ext $LIBS >&5'
++ac_compiler_gnu=$ac_cv_c_compiler_gnu
++
++     cat confdefs.h - <<_ACEOF >conftest.$ac_ext
++/* end confdefs.h.  */
++
++int
++main ()
++{
++
++  ;
++  return 0;
++}
++_ACEOF
++if ac_fn_c_try_link "$LINENO"; then :
++  lt_cv_cc_needs_belf=yes
++else
++  lt_cv_cc_needs_belf=no
++fi
++rm -f core conftest.err conftest.$ac_objext \
++    conftest$ac_exeext conftest.$ac_ext
++     ac_ext=c
++ac_cpp='$CPP $CPPFLAGS'
++ac_compile='$CC -c $CFLAGS $CPPFLAGS conftest.$ac_ext >&5'
++ac_link='$CC -o conftest$ac_exeext $CFLAGS $CPPFLAGS $LDFLAGS conftest.$ac_ext $LIBS >&5'
++ac_compiler_gnu=$ac_cv_c_compiler_gnu
++
++fi
++{ $as_echo "$as_me:${as_lineno-$LINENO}: result: $lt_cv_cc_needs_belf" >&5
++$as_echo "$lt_cv_cc_needs_belf" >&6; }
++  if test x"$lt_cv_cc_needs_belf" != x"yes"; then
++    # this is probably gcc 2.8.0, egcs 1.0 or newer; no need for -belf
++    CFLAGS="$SAVE_CFLAGS"
++  fi
++  ;;
++sparc*-*solaris*)
++  # Find out which ABI we are using.
++  echo 'int i;' > conftest.$ac_ext
++  if { { eval echo "\"\$as_me\":${as_lineno-$LINENO}: \"$ac_compile\""; } >&5
++  (eval $ac_compile) 2>&5
++  ac_status=$?
++  $as_echo "$as_me:${as_lineno-$LINENO}: \$? = $ac_status" >&5
++  test $ac_status = 0; }; then
++    case `/usr/bin/file conftest.o` in
++    *64-bit*)
++      case $lt_cv_prog_gnu_ld in
++      yes*) LD="${LD-ld} -m elf64_sparc" ;;
++      *)
++	if ${LD-ld} -64 -r -o conftest2.o conftest.o >/dev/null 2>&1; then
++	  LD="${LD-ld} -64"
++	fi
++	;;
++      esac
++      ;;
++    esac
++  fi
++  rm -rf conftest*
++  ;;
++esac
++
++need_locks="$enable_libtool_lock"
++
++
++  case $host_os in
++    rhapsody* | darwin*)
++    if test -n "$ac_tool_prefix"; then
++  # Extract the first word of "${ac_tool_prefix}dsymutil", so it can be a program name with args.
++set dummy ${ac_tool_prefix}dsymutil; ac_word=$2
++{ $as_echo "$as_me:${as_lineno-$LINENO}: checking for $ac_word" >&5
++$as_echo_n "checking for $ac_word... " >&6; }
++if ${ac_cv_prog_DSYMUTIL+:} false; then :
++  $as_echo_n "(cached) " >&6
++else
++  if test -n "$DSYMUTIL"; then
++  ac_cv_prog_DSYMUTIL="$DSYMUTIL" # Let the user override the test.
++else
++as_save_IFS=$IFS; IFS=$PATH_SEPARATOR
++for as_dir in $PATH
++do
++  IFS=$as_save_IFS
++  test -z "$as_dir" && as_dir=.
++    for ac_exec_ext in '' $ac_executable_extensions; do
++  if as_fn_executable_p "$as_dir/$ac_word$ac_exec_ext"; then
++    ac_cv_prog_DSYMUTIL="${ac_tool_prefix}dsymutil"
++    $as_echo "$as_me:${as_lineno-$LINENO}: found $as_dir/$ac_word$ac_exec_ext" >&5
++    break 2
++  fi
++done
++  done
++IFS=$as_save_IFS
++
++fi
++fi
++DSYMUTIL=$ac_cv_prog_DSYMUTIL
++if test -n "$DSYMUTIL"; then
++  { $as_echo "$as_me:${as_lineno-$LINENO}: result: $DSYMUTIL" >&5
++$as_echo "$DSYMUTIL" >&6; }
++else
++  { $as_echo "$as_me:${as_lineno-$LINENO}: result: no" >&5
++$as_echo "no" >&6; }
++fi
++
++
++fi
++if test -z "$ac_cv_prog_DSYMUTIL"; then
++  ac_ct_DSYMUTIL=$DSYMUTIL
++  # Extract the first word of "dsymutil", so it can be a program name with args.
++set dummy dsymutil; ac_word=$2
++{ $as_echo "$as_me:${as_lineno-$LINENO}: checking for $ac_word" >&5
++$as_echo_n "checking for $ac_word... " >&6; }
++if ${ac_cv_prog_ac_ct_DSYMUTIL+:} false; then :
++  $as_echo_n "(cached) " >&6
++else
++  if test -n "$ac_ct_DSYMUTIL"; then
++  ac_cv_prog_ac_ct_DSYMUTIL="$ac_ct_DSYMUTIL" # Let the user override the test.
++else
++as_save_IFS=$IFS; IFS=$PATH_SEPARATOR
++for as_dir in $PATH
++do
++  IFS=$as_save_IFS
++  test -z "$as_dir" && as_dir=.
++    for ac_exec_ext in '' $ac_executable_extensions; do
++  if as_fn_executable_p "$as_dir/$ac_word$ac_exec_ext"; then
++    ac_cv_prog_ac_ct_DSYMUTIL="dsymutil"
++    $as_echo "$as_me:${as_lineno-$LINENO}: found $as_dir/$ac_word$ac_exec_ext" >&5
++    break 2
++  fi
++done
++  done
++IFS=$as_save_IFS
++
++fi
++fi
++ac_ct_DSYMUTIL=$ac_cv_prog_ac_ct_DSYMUTIL
++if test -n "$ac_ct_DSYMUTIL"; then
++  { $as_echo "$as_me:${as_lineno-$LINENO}: result: $ac_ct_DSYMUTIL" >&5
++$as_echo "$ac_ct_DSYMUTIL" >&6; }
++else
++  { $as_echo "$as_me:${as_lineno-$LINENO}: result: no" >&5
++$as_echo "no" >&6; }
++fi
++
++  if test "x$ac_ct_DSYMUTIL" = x; then
++    DSYMUTIL=":"
++  else
++    case $cross_compiling:$ac_tool_warned in
++yes:)
++{ $as_echo "$as_me:${as_lineno-$LINENO}: WARNING: using cross tools not prefixed with host triplet" >&5
++$as_echo "$as_me: WARNING: using cross tools not prefixed with host triplet" >&2;}
++ac_tool_warned=yes ;;
++esac
++    DSYMUTIL=$ac_ct_DSYMUTIL
++  fi
++else
++  DSYMUTIL="$ac_cv_prog_DSYMUTIL"
++fi
++
++    if test -n "$ac_tool_prefix"; then
++  # Extract the first word of "${ac_tool_prefix}nmedit", so it can be a program name with args.
++set dummy ${ac_tool_prefix}nmedit; ac_word=$2
++{ $as_echo "$as_me:${as_lineno-$LINENO}: checking for $ac_word" >&5
++$as_echo_n "checking for $ac_word... " >&6; }
++if ${ac_cv_prog_NMEDIT+:} false; then :
++  $as_echo_n "(cached) " >&6
++else
++  if test -n "$NMEDIT"; then
++  ac_cv_prog_NMEDIT="$NMEDIT" # Let the user override the test.
++else
++as_save_IFS=$IFS; IFS=$PATH_SEPARATOR
++for as_dir in $PATH
++do
++  IFS=$as_save_IFS
++  test -z "$as_dir" && as_dir=.
++    for ac_exec_ext in '' $ac_executable_extensions; do
++  if as_fn_executable_p "$as_dir/$ac_word$ac_exec_ext"; then
++    ac_cv_prog_NMEDIT="${ac_tool_prefix}nmedit"
++    $as_echo "$as_me:${as_lineno-$LINENO}: found $as_dir/$ac_word$ac_exec_ext" >&5
++    break 2
++  fi
++done
++  done
++IFS=$as_save_IFS
++
++fi
++fi
++NMEDIT=$ac_cv_prog_NMEDIT
++if test -n "$NMEDIT"; then
++  { $as_echo "$as_me:${as_lineno-$LINENO}: result: $NMEDIT" >&5
++$as_echo "$NMEDIT" >&6; }
++else
++  { $as_echo "$as_me:${as_lineno-$LINENO}: result: no" >&5
++$as_echo "no" >&6; }
++fi
++
++
++fi
++if test -z "$ac_cv_prog_NMEDIT"; then
++  ac_ct_NMEDIT=$NMEDIT
++  # Extract the first word of "nmedit", so it can be a program name with args.
++set dummy nmedit; ac_word=$2
++{ $as_echo "$as_me:${as_lineno-$LINENO}: checking for $ac_word" >&5
++$as_echo_n "checking for $ac_word... " >&6; }
++if ${ac_cv_prog_ac_ct_NMEDIT+:} false; then :
++  $as_echo_n "(cached) " >&6
++else
++  if test -n "$ac_ct_NMEDIT"; then
++  ac_cv_prog_ac_ct_NMEDIT="$ac_ct_NMEDIT" # Let the user override the test.
++else
++as_save_IFS=$IFS; IFS=$PATH_SEPARATOR
++for as_dir in $PATH
++do
++  IFS=$as_save_IFS
++  test -z "$as_dir" && as_dir=.
++    for ac_exec_ext in '' $ac_executable_extensions; do
++  if as_fn_executable_p "$as_dir/$ac_word$ac_exec_ext"; then
++    ac_cv_prog_ac_ct_NMEDIT="nmedit"
++    $as_echo "$as_me:${as_lineno-$LINENO}: found $as_dir/$ac_word$ac_exec_ext" >&5
++    break 2
++  fi
++done
++  done
++IFS=$as_save_IFS
++
++fi
++fi
++ac_ct_NMEDIT=$ac_cv_prog_ac_ct_NMEDIT
++if test -n "$ac_ct_NMEDIT"; then
++  { $as_echo "$as_me:${as_lineno-$LINENO}: result: $ac_ct_NMEDIT" >&5
++$as_echo "$ac_ct_NMEDIT" >&6; }
++else
++  { $as_echo "$as_me:${as_lineno-$LINENO}: result: no" >&5
++$as_echo "no" >&6; }
++fi
++
++  if test "x$ac_ct_NMEDIT" = x; then
++    NMEDIT=":"
++  else
++    case $cross_compiling:$ac_tool_warned in
++yes:)
++{ $as_echo "$as_me:${as_lineno-$LINENO}: WARNING: using cross tools not prefixed with host triplet" >&5
++$as_echo "$as_me: WARNING: using cross tools not prefixed with host triplet" >&2;}
++ac_tool_warned=yes ;;
++esac
++    NMEDIT=$ac_ct_NMEDIT
++  fi
++else
++  NMEDIT="$ac_cv_prog_NMEDIT"
++fi
++
++    if test -n "$ac_tool_prefix"; then
++  # Extract the first word of "${ac_tool_prefix}lipo", so it can be a program name with args.
++set dummy ${ac_tool_prefix}lipo; ac_word=$2
++{ $as_echo "$as_me:${as_lineno-$LINENO}: checking for $ac_word" >&5
++$as_echo_n "checking for $ac_word... " >&6; }
++if ${ac_cv_prog_LIPO+:} false; then :
++  $as_echo_n "(cached) " >&6
++else
++  if test -n "$LIPO"; then
++  ac_cv_prog_LIPO="$LIPO" # Let the user override the test.
++else
++as_save_IFS=$IFS; IFS=$PATH_SEPARATOR
++for as_dir in $PATH
++do
++  IFS=$as_save_IFS
++  test -z "$as_dir" && as_dir=.
++    for ac_exec_ext in '' $ac_executable_extensions; do
++  if as_fn_executable_p "$as_dir/$ac_word$ac_exec_ext"; then
++    ac_cv_prog_LIPO="${ac_tool_prefix}lipo"
++    $as_echo "$as_me:${as_lineno-$LINENO}: found $as_dir/$ac_word$ac_exec_ext" >&5
++    break 2
++  fi
++done
++  done
++IFS=$as_save_IFS
++
++fi
++fi
++LIPO=$ac_cv_prog_LIPO
++if test -n "$LIPO"; then
++  { $as_echo "$as_me:${as_lineno-$LINENO}: result: $LIPO" >&5
++$as_echo "$LIPO" >&6; }
++else
++  { $as_echo "$as_me:${as_lineno-$LINENO}: result: no" >&5
++$as_echo "no" >&6; }
++fi
++
++
++fi
++if test -z "$ac_cv_prog_LIPO"; then
++  ac_ct_LIPO=$LIPO
++  # Extract the first word of "lipo", so it can be a program name with args.
++set dummy lipo; ac_word=$2
++{ $as_echo "$as_me:${as_lineno-$LINENO}: checking for $ac_word" >&5
++$as_echo_n "checking for $ac_word... " >&6; }
++if ${ac_cv_prog_ac_ct_LIPO+:} false; then :
++  $as_echo_n "(cached) " >&6
++else
++  if test -n "$ac_ct_LIPO"; then
++  ac_cv_prog_ac_ct_LIPO="$ac_ct_LIPO" # Let the user override the test.
++else
++as_save_IFS=$IFS; IFS=$PATH_SEPARATOR
++for as_dir in $PATH
++do
++  IFS=$as_save_IFS
++  test -z "$as_dir" && as_dir=.
++    for ac_exec_ext in '' $ac_executable_extensions; do
++  if as_fn_executable_p "$as_dir/$ac_word$ac_exec_ext"; then
++    ac_cv_prog_ac_ct_LIPO="lipo"
++    $as_echo "$as_me:${as_lineno-$LINENO}: found $as_dir/$ac_word$ac_exec_ext" >&5
++    break 2
++  fi
++done
++  done
++IFS=$as_save_IFS
++
++fi
++fi
++ac_ct_LIPO=$ac_cv_prog_ac_ct_LIPO
++if test -n "$ac_ct_LIPO"; then
++  { $as_echo "$as_me:${as_lineno-$LINENO}: result: $ac_ct_LIPO" >&5
++$as_echo "$ac_ct_LIPO" >&6; }
++else
++  { $as_echo "$as_me:${as_lineno-$LINENO}: result: no" >&5
++$as_echo "no" >&6; }
++fi
++
++  if test "x$ac_ct_LIPO" = x; then
++    LIPO=":"
++  else
++    case $cross_compiling:$ac_tool_warned in
++yes:)
++{ $as_echo "$as_me:${as_lineno-$LINENO}: WARNING: using cross tools not prefixed with host triplet" >&5
++$as_echo "$as_me: WARNING: using cross tools not prefixed with host triplet" >&2;}
++ac_tool_warned=yes ;;
++esac
++    LIPO=$ac_ct_LIPO
++  fi
++else
++  LIPO="$ac_cv_prog_LIPO"
++fi
++
++    if test -n "$ac_tool_prefix"; then
++  # Extract the first word of "${ac_tool_prefix}otool", so it can be a program name with args.
++set dummy ${ac_tool_prefix}otool; ac_word=$2
++{ $as_echo "$as_me:${as_lineno-$LINENO}: checking for $ac_word" >&5
++$as_echo_n "checking for $ac_word... " >&6; }
++if ${ac_cv_prog_OTOOL+:} false; then :
++  $as_echo_n "(cached) " >&6
++else
++  if test -n "$OTOOL"; then
++  ac_cv_prog_OTOOL="$OTOOL" # Let the user override the test.
++else
++as_save_IFS=$IFS; IFS=$PATH_SEPARATOR
++for as_dir in $PATH
++do
++  IFS=$as_save_IFS
++  test -z "$as_dir" && as_dir=.
++    for ac_exec_ext in '' $ac_executable_extensions; do
++  if as_fn_executable_p "$as_dir/$ac_word$ac_exec_ext"; then
++    ac_cv_prog_OTOOL="${ac_tool_prefix}otool"
++    $as_echo "$as_me:${as_lineno-$LINENO}: found $as_dir/$ac_word$ac_exec_ext" >&5
++    break 2
++  fi
++done
++  done
++IFS=$as_save_IFS
++
++fi
++fi
++OTOOL=$ac_cv_prog_OTOOL
++if test -n "$OTOOL"; then
++  { $as_echo "$as_me:${as_lineno-$LINENO}: result: $OTOOL" >&5
++$as_echo "$OTOOL" >&6; }
++else
++  { $as_echo "$as_me:${as_lineno-$LINENO}: result: no" >&5
++$as_echo "no" >&6; }
++fi
++
++
++fi
++if test -z "$ac_cv_prog_OTOOL"; then
++  ac_ct_OTOOL=$OTOOL
++  # Extract the first word of "otool", so it can be a program name with args.
++set dummy otool; ac_word=$2
++{ $as_echo "$as_me:${as_lineno-$LINENO}: checking for $ac_word" >&5
++$as_echo_n "checking for $ac_word... " >&6; }
++if ${ac_cv_prog_ac_ct_OTOOL+:} false; then :
++  $as_echo_n "(cached) " >&6
++else
++  if test -n "$ac_ct_OTOOL"; then
++  ac_cv_prog_ac_ct_OTOOL="$ac_ct_OTOOL" # Let the user override the test.
++else
++as_save_IFS=$IFS; IFS=$PATH_SEPARATOR
++for as_dir in $PATH
++do
++  IFS=$as_save_IFS
++  test -z "$as_dir" && as_dir=.
++    for ac_exec_ext in '' $ac_executable_extensions; do
++  if as_fn_executable_p "$as_dir/$ac_word$ac_exec_ext"; then
++    ac_cv_prog_ac_ct_OTOOL="otool"
++    $as_echo "$as_me:${as_lineno-$LINENO}: found $as_dir/$ac_word$ac_exec_ext" >&5
++    break 2
++  fi
++done
++  done
++IFS=$as_save_IFS
++
++fi
++fi
++ac_ct_OTOOL=$ac_cv_prog_ac_ct_OTOOL
++if test -n "$ac_ct_OTOOL"; then
++  { $as_echo "$as_me:${as_lineno-$LINENO}: result: $ac_ct_OTOOL" >&5
++$as_echo "$ac_ct_OTOOL" >&6; }
++else
++  { $as_echo "$as_me:${as_lineno-$LINENO}: result: no" >&5
++$as_echo "no" >&6; }
++fi
++
++  if test "x$ac_ct_OTOOL" = x; then
++    OTOOL=":"
++  else
++    case $cross_compiling:$ac_tool_warned in
++yes:)
++{ $as_echo "$as_me:${as_lineno-$LINENO}: WARNING: using cross tools not prefixed with host triplet" >&5
++$as_echo "$as_me: WARNING: using cross tools not prefixed with host triplet" >&2;}
++ac_tool_warned=yes ;;
++esac
++    OTOOL=$ac_ct_OTOOL
++  fi
++else
++  OTOOL="$ac_cv_prog_OTOOL"
++fi
++
++    if test -n "$ac_tool_prefix"; then
++  # Extract the first word of "${ac_tool_prefix}otool64", so it can be a program name with args.
++set dummy ${ac_tool_prefix}otool64; ac_word=$2
++{ $as_echo "$as_me:${as_lineno-$LINENO}: checking for $ac_word" >&5
++$as_echo_n "checking for $ac_word... " >&6; }
++if ${ac_cv_prog_OTOOL64+:} false; then :
++  $as_echo_n "(cached) " >&6
++else
++  if test -n "$OTOOL64"; then
++  ac_cv_prog_OTOOL64="$OTOOL64" # Let the user override the test.
++else
++as_save_IFS=$IFS; IFS=$PATH_SEPARATOR
++for as_dir in $PATH
++do
++  IFS=$as_save_IFS
++  test -z "$as_dir" && as_dir=.
++    for ac_exec_ext in '' $ac_executable_extensions; do
++  if as_fn_executable_p "$as_dir/$ac_word$ac_exec_ext"; then
++    ac_cv_prog_OTOOL64="${ac_tool_prefix}otool64"
++    $as_echo "$as_me:${as_lineno-$LINENO}: found $as_dir/$ac_word$ac_exec_ext" >&5
++    break 2
++  fi
++done
++  done
++IFS=$as_save_IFS
++
++fi
++fi
++OTOOL64=$ac_cv_prog_OTOOL64
++if test -n "$OTOOL64"; then
++  { $as_echo "$as_me:${as_lineno-$LINENO}: result: $OTOOL64" >&5
++$as_echo "$OTOOL64" >&6; }
++else
++  { $as_echo "$as_me:${as_lineno-$LINENO}: result: no" >&5
++$as_echo "no" >&6; }
++fi
++
++
++fi
++if test -z "$ac_cv_prog_OTOOL64"; then
++  ac_ct_OTOOL64=$OTOOL64
++  # Extract the first word of "otool64", so it can be a program name with args.
++set dummy otool64; ac_word=$2
++{ $as_echo "$as_me:${as_lineno-$LINENO}: checking for $ac_word" >&5
++$as_echo_n "checking for $ac_word... " >&6; }
++if ${ac_cv_prog_ac_ct_OTOOL64+:} false; then :
++  $as_echo_n "(cached) " >&6
++else
++  if test -n "$ac_ct_OTOOL64"; then
++  ac_cv_prog_ac_ct_OTOOL64="$ac_ct_OTOOL64" # Let the user override the test.
++else
++as_save_IFS=$IFS; IFS=$PATH_SEPARATOR
++for as_dir in $PATH
++do
++  IFS=$as_save_IFS
++  test -z "$as_dir" && as_dir=.
++    for ac_exec_ext in '' $ac_executable_extensions; do
++  if as_fn_executable_p "$as_dir/$ac_word$ac_exec_ext"; then
++    ac_cv_prog_ac_ct_OTOOL64="otool64"
++    $as_echo "$as_me:${as_lineno-$LINENO}: found $as_dir/$ac_word$ac_exec_ext" >&5
++    break 2
++  fi
++done
++  done
++IFS=$as_save_IFS
++
++fi
++fi
++ac_ct_OTOOL64=$ac_cv_prog_ac_ct_OTOOL64
++if test -n "$ac_ct_OTOOL64"; then
++  { $as_echo "$as_me:${as_lineno-$LINENO}: result: $ac_ct_OTOOL64" >&5
++$as_echo "$ac_ct_OTOOL64" >&6; }
++else
++  { $as_echo "$as_me:${as_lineno-$LINENO}: result: no" >&5
++$as_echo "no" >&6; }
++fi
++
++  if test "x$ac_ct_OTOOL64" = x; then
++    OTOOL64=":"
++  else
++    case $cross_compiling:$ac_tool_warned in
++yes:)
++{ $as_echo "$as_me:${as_lineno-$LINENO}: WARNING: using cross tools not prefixed with host triplet" >&5
++$as_echo "$as_me: WARNING: using cross tools not prefixed with host triplet" >&2;}
++ac_tool_warned=yes ;;
++esac
++    OTOOL64=$ac_ct_OTOOL64
++  fi
++else
++  OTOOL64="$ac_cv_prog_OTOOL64"
++fi
++
++
++
++
++
++
++
++
++
++
++
++
++
++
++
++
++
++
++
++
++
++
++
++
++
++
++
++    { $as_echo "$as_me:${as_lineno-$LINENO}: checking for -single_module linker flag" >&5
++$as_echo_n "checking for -single_module linker flag... " >&6; }
++if ${lt_cv_apple_cc_single_mod+:} false; then :
++  $as_echo_n "(cached) " >&6
++else
++  lt_cv_apple_cc_single_mod=no
++      if test -z "${LT_MULTI_MODULE}"; then
++	# By default we will add the -single_module flag. You can override
++	# by either setting the environment variable LT_MULTI_MODULE
++	# non-empty at configure time, or by adding -multi_module to the
++	# link flags.
++	rm -rf libconftest.dylib*
++	echo "int foo(void){return 1;}" > conftest.c
++	echo "$LTCC $LTCFLAGS $LDFLAGS -o libconftest.dylib \
++-dynamiclib -Wl,-single_module conftest.c" >&5
++	$LTCC $LTCFLAGS $LDFLAGS -o libconftest.dylib \
++	  -dynamiclib -Wl,-single_module conftest.c 2>conftest.err
++        _lt_result=$?
++	if test -f libconftest.dylib && test ! -s conftest.err && test $_lt_result = 0; then
++	  lt_cv_apple_cc_single_mod=yes
++	else
++	  cat conftest.err >&5
++	fi
++	rm -rf libconftest.dylib*
++	rm -f conftest.*
++      fi
++fi
++{ $as_echo "$as_me:${as_lineno-$LINENO}: result: $lt_cv_apple_cc_single_mod" >&5
++$as_echo "$lt_cv_apple_cc_single_mod" >&6; }
++    { $as_echo "$as_me:${as_lineno-$LINENO}: checking for -exported_symbols_list linker flag" >&5
++$as_echo_n "checking for -exported_symbols_list linker flag... " >&6; }
++if ${lt_cv_ld_exported_symbols_list+:} false; then :
++  $as_echo_n "(cached) " >&6
++else
++  lt_cv_ld_exported_symbols_list=no
++      save_LDFLAGS=$LDFLAGS
++      echo "_main" > conftest.sym
++      LDFLAGS="$LDFLAGS -Wl,-exported_symbols_list,conftest.sym"
++      cat confdefs.h - <<_ACEOF >conftest.$ac_ext
++/* end confdefs.h.  */
++
++int
++main ()
++{
++
++  ;
++  return 0;
++}
++_ACEOF
++if ac_fn_c_try_link "$LINENO"; then :
++  lt_cv_ld_exported_symbols_list=yes
++else
++  lt_cv_ld_exported_symbols_list=no
++fi
++rm -f core conftest.err conftest.$ac_objext \
++    conftest$ac_exeext conftest.$ac_ext
++	LDFLAGS="$save_LDFLAGS"
++
++fi
++{ $as_echo "$as_me:${as_lineno-$LINENO}: result: $lt_cv_ld_exported_symbols_list" >&5
++$as_echo "$lt_cv_ld_exported_symbols_list" >&6; }
++    { $as_echo "$as_me:${as_lineno-$LINENO}: checking for -force_load linker flag" >&5
++$as_echo_n "checking for -force_load linker flag... " >&6; }
++if ${lt_cv_ld_force_load+:} false; then :
++  $as_echo_n "(cached) " >&6
++else
++  lt_cv_ld_force_load=no
++      cat > conftest.c << _LT_EOF
++int forced_loaded() { return 2;}
++_LT_EOF
++      echo "$LTCC $LTCFLAGS -c -o conftest.o conftest.c" >&5
++      $LTCC $LTCFLAGS -c -o conftest.o conftest.c 2>&5
++      echo "$AR cru libconftest.a conftest.o" >&5
++      $AR cru libconftest.a conftest.o 2>&5
++      cat > conftest.c << _LT_EOF
++int main() { return 0;}
++_LT_EOF
++      echo "$LTCC $LTCFLAGS $LDFLAGS -o conftest conftest.c -Wl,-force_load,./libconftest.a" >&5
++      $LTCC $LTCFLAGS $LDFLAGS -o conftest conftest.c -Wl,-force_load,./libconftest.a 2>conftest.err
++      _lt_result=$?
++      if test -f conftest && test ! -s conftest.err && test $_lt_result = 0 && $GREP forced_load conftest 2>&1 >/dev/null; then
++	lt_cv_ld_force_load=yes
++      else
++	cat conftest.err >&5
++      fi
++        rm -f conftest.err libconftest.a conftest conftest.c
++        rm -rf conftest.dSYM
++
++fi
++{ $as_echo "$as_me:${as_lineno-$LINENO}: result: $lt_cv_ld_force_load" >&5
++$as_echo "$lt_cv_ld_force_load" >&6; }
++    case $host_os in
++    rhapsody* | darwin1.[012])
++      _lt_dar_allow_undefined='${wl}-undefined ${wl}suppress' ;;
++    darwin1.*)
++      _lt_dar_allow_undefined='${wl}-flat_namespace ${wl}-undefined ${wl}suppress' ;;
++    darwin*) # darwin 5.x on
++      # if running on 10.5 or later, the deployment target defaults
++      # to the OS version, if on x86, and 10.4, the deployment
++      # target defaults to 10.4. Don't you love it?
++      case ${MACOSX_DEPLOYMENT_TARGET-10.0},$host in
++	10.0,*86*-darwin8*|10.0,*-darwin[91]*)
++	  _lt_dar_allow_undefined='${wl}-undefined ${wl}dynamic_lookup' ;;
++	10.[012][,.]*)
++	  _lt_dar_allow_undefined='${wl}-flat_namespace ${wl}-undefined ${wl}suppress' ;;
++	10.*)
++	  _lt_dar_allow_undefined='${wl}-undefined ${wl}dynamic_lookup' ;;
++      esac
++    ;;
++  esac
++    if test "$lt_cv_apple_cc_single_mod" = "yes"; then
++      _lt_dar_single_mod='$single_module'
++    fi
++    if test "$lt_cv_ld_exported_symbols_list" = "yes"; then
++      _lt_dar_export_syms=' ${wl}-exported_symbols_list,$output_objdir/${libname}-symbols.expsym'
++    else
++      _lt_dar_export_syms='~$NMEDIT -s $output_objdir/${libname}-symbols.expsym ${lib}'
++    fi
++    if test "$DSYMUTIL" != ":" && test "$lt_cv_ld_force_load" = "no"; then
++      _lt_dsymutil='~$DSYMUTIL $lib || :'
++    else
++      _lt_dsymutil=
++    fi
++    ;;
++  esac
++
++for ac_header in dlfcn.h
++do :
++  ac_fn_c_check_header_compile "$LINENO" "dlfcn.h" "ac_cv_header_dlfcn_h" "$ac_includes_default
++"
++if test "x$ac_cv_header_dlfcn_h" = xyes; then :
++  cat >>confdefs.h <<_ACEOF
++#define HAVE_DLFCN_H 1
++_ACEOF
++
++fi
++
++done
++
++
++
++# autoconf.info says this should be called right after AC_INIT.
++ac_config_headers="$ac_config_headers config.h:config.in"
++
++
++
++ { $as_echo "$as_me:${as_lineno-$LINENO}: checking whether byte ordering is bigendian" >&5
++$as_echo_n "checking whether byte ordering is bigendian... " >&6; }
++if ${ac_cv_c_bigendian+:} false; then :
++  $as_echo_n "(cached) " >&6
++else
++  ac_cv_c_bigendian=unknown
++    # See if we're dealing with a universal compiler.
++    cat confdefs.h - <<_ACEOF >conftest.$ac_ext
++/* end confdefs.h.  */
++#ifndef __APPLE_CC__
++	       not a universal capable compiler
++	     #endif
++	     typedef int dummy;
++
++_ACEOF
++if ac_fn_c_try_compile "$LINENO"; then :
++
++	# Check for potential -arch flags.  It is not universal unless
++	# there are at least two -arch flags with different values.
++	ac_arch=
++	ac_prev=
++	for ac_word in $CC $CFLAGS $CPPFLAGS $LDFLAGS; do
++	 if test -n "$ac_prev"; then
++	   case $ac_word in
++	     i?86 | x86_64 | ppc | ppc64)
++	       if test -z "$ac_arch" || test "$ac_arch" = "$ac_word"; then
++		 ac_arch=$ac_word
++	       else
++		 ac_cv_c_bigendian=universal
++		 break
++	       fi
++	       ;;
++	   esac
++	   ac_prev=
++	 elif test "x$ac_word" = "x-arch"; then
++	   ac_prev=arch
++	 fi
++       done
++fi
++rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext
++    if test $ac_cv_c_bigendian = unknown; then
++      # See if sys/param.h defines the BYTE_ORDER macro.
++      cat confdefs.h - <<_ACEOF >conftest.$ac_ext
++/* end confdefs.h.  */
++#include <sys/types.h>
++	     #include <sys/param.h>
++
++int
++main ()
++{
++#if ! (defined BYTE_ORDER && defined BIG_ENDIAN \
++		     && defined LITTLE_ENDIAN && BYTE_ORDER && BIG_ENDIAN \
++		     && LITTLE_ENDIAN)
++	      bogus endian macros
++	     #endif
++
++  ;
++  return 0;
++}
++_ACEOF
++if ac_fn_c_try_compile "$LINENO"; then :
++  # It does; now see whether it defined to BIG_ENDIAN or not.
++	 cat confdefs.h - <<_ACEOF >conftest.$ac_ext
++/* end confdefs.h.  */
++#include <sys/types.h>
++		#include <sys/param.h>
++
++int
++main ()
++{
++#if BYTE_ORDER != BIG_ENDIAN
++		 not big endian
++		#endif
++
++  ;
++  return 0;
++}
++_ACEOF
++if ac_fn_c_try_compile "$LINENO"; then :
++  ac_cv_c_bigendian=yes
++else
++  ac_cv_c_bigendian=no
++fi
++rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext
++fi
++rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext
++    fi
++    if test $ac_cv_c_bigendian = unknown; then
++      # See if <limits.h> defines _LITTLE_ENDIAN or _BIG_ENDIAN (e.g., Solaris).
++      cat confdefs.h - <<_ACEOF >conftest.$ac_ext
++/* end confdefs.h.  */
++#include <limits.h>
++
++int
++main ()
++{
++#if ! (defined _LITTLE_ENDIAN || defined _BIG_ENDIAN)
++	      bogus endian macros
++	     #endif
++
++  ;
++  return 0;
++}
++_ACEOF
++if ac_fn_c_try_compile "$LINENO"; then :
++  # It does; now see whether it defined to _BIG_ENDIAN or not.
++	 cat confdefs.h - <<_ACEOF >conftest.$ac_ext
++/* end confdefs.h.  */
++#include <limits.h>
++
++int
++main ()
++{
++#ifndef _BIG_ENDIAN
++		 not big endian
++		#endif
++
++  ;
++  return 0;
++}
++_ACEOF
++if ac_fn_c_try_compile "$LINENO"; then :
++  ac_cv_c_bigendian=yes
++else
++  ac_cv_c_bigendian=no
++fi
++rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext
++fi
++rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext
++    fi
++    if test $ac_cv_c_bigendian = unknown; then
++      # Compile a test program.
++      if test "$cross_compiling" = yes; then :
++  # Try to guess by grepping values from an object file.
++	 cat confdefs.h - <<_ACEOF >conftest.$ac_ext
++/* end confdefs.h.  */
++short int ascii_mm[] =
++		  { 0x4249, 0x4765, 0x6E44, 0x6961, 0x6E53, 0x7953, 0 };
++		short int ascii_ii[] =
++		  { 0x694C, 0x5454, 0x656C, 0x6E45, 0x6944, 0x6E61, 0 };
++		int use_ascii (int i) {
++		  return ascii_mm[i] + ascii_ii[i];
++		}
++		short int ebcdic_ii[] =
++		  { 0x89D3, 0xE3E3, 0x8593, 0x95C5, 0x89C4, 0x9581, 0 };
++		short int ebcdic_mm[] =
++		  { 0xC2C9, 0xC785, 0x95C4, 0x8981, 0x95E2, 0xA8E2, 0 };
++		int use_ebcdic (int i) {
++		  return ebcdic_mm[i] + ebcdic_ii[i];
++		}
++		extern int foo;
++
++int
++main ()
++{
++return use_ascii (foo) == use_ebcdic (foo);
++  ;
++  return 0;
++}
++_ACEOF
++if ac_fn_c_try_compile "$LINENO"; then :
++  if grep BIGenDianSyS conftest.$ac_objext >/dev/null; then
++	      ac_cv_c_bigendian=yes
++	    fi
++	    if grep LiTTleEnDian conftest.$ac_objext >/dev/null ; then
++	      if test "$ac_cv_c_bigendian" = unknown; then
++		ac_cv_c_bigendian=no
++	      else
++		# finding both strings is unlikely to happen, but who knows?
++		ac_cv_c_bigendian=unknown
++	      fi
++	    fi
++fi
++rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext
++else
++  cat confdefs.h - <<_ACEOF >conftest.$ac_ext
++/* end confdefs.h.  */
++$ac_includes_default
++int
++main ()
++{
++
++	     /* Are we little or big endian?  From Harbison&Steele.  */
++	     union
++	     {
++	       long int l;
++	       char c[sizeof (long int)];
++	     } u;
++	     u.l = 1;
++	     return u.c[sizeof (long int) - 1] == 1;
++
++  ;
++  return 0;
++}
++_ACEOF
++if ac_fn_c_try_run "$LINENO"; then :
++  ac_cv_c_bigendian=no
++else
++  ac_cv_c_bigendian=yes
++fi
++rm -f core *.core core.conftest.* gmon.out bb.out conftest$ac_exeext \
++  conftest.$ac_objext conftest.beam conftest.$ac_ext
++fi
++
++    fi
++fi
++{ $as_echo "$as_me:${as_lineno-$LINENO}: result: $ac_cv_c_bigendian" >&5
++$as_echo "$ac_cv_c_bigendian" >&6; }
++ case $ac_cv_c_bigendian in #(
++   yes)
++     $as_echo "#define WORDS_BIGENDIAN 1" >>confdefs.h
++;; #(
++   no)
++      ;; #(
++   universal)
++
++$as_echo "#define AC_APPLE_UNIVERSAL_BUILD 1" >>confdefs.h
++
++     ;; #(
++   *)
++     as_fn_error $? "unknown endianness
++ presetting ac_cv_c_bigendian=no (or yes) will help" "$LINENO" 5 ;;
++ esac
++
++
++
++
++# Put a plausible default for CC_FOR_BUILD in Makefile.
++if test -z "$CC_FOR_BUILD"; then
++  if test "x$cross_compiling" = "xno"; then
++    CC_FOR_BUILD='$(CC)'
++  else
++    CC_FOR_BUILD=gcc
++  fi
++fi
++
++
++
++
++AR=${AR-ar}
++
++if test -n "$ac_tool_prefix"; then
++  # Extract the first word of "${ac_tool_prefix}ranlib", so it can be a program name with args.
++set dummy ${ac_tool_prefix}ranlib; ac_word=$2
++{ $as_echo "$as_me:${as_lineno-$LINENO}: checking for $ac_word" >&5
++$as_echo_n "checking for $ac_word... " >&6; }
++if ${ac_cv_prog_RANLIB+:} false; then :
++  $as_echo_n "(cached) " >&6
++else
++  if test -n "$RANLIB"; then
++  ac_cv_prog_RANLIB="$RANLIB" # Let the user override the test.
++else
++as_save_IFS=$IFS; IFS=$PATH_SEPARATOR
++for as_dir in $PATH
++do
++  IFS=$as_save_IFS
++  test -z "$as_dir" && as_dir=.
++    for ac_exec_ext in '' $ac_executable_extensions; do
++  if as_fn_executable_p "$as_dir/$ac_word$ac_exec_ext"; then
++    ac_cv_prog_RANLIB="${ac_tool_prefix}ranlib"
++    $as_echo "$as_me:${as_lineno-$LINENO}: found $as_dir/$ac_word$ac_exec_ext" >&5
++    break 2
++  fi
++done
++  done
++IFS=$as_save_IFS
++
++fi
++fi
++RANLIB=$ac_cv_prog_RANLIB
++if test -n "$RANLIB"; then
++  { $as_echo "$as_me:${as_lineno-$LINENO}: result: $RANLIB" >&5
++$as_echo "$RANLIB" >&6; }
++else
++  { $as_echo "$as_me:${as_lineno-$LINENO}: result: no" >&5
++$as_echo "no" >&6; }
++fi
++
++
++fi
++if test -z "$ac_cv_prog_RANLIB"; then
++  ac_ct_RANLIB=$RANLIB
++  # Extract the first word of "ranlib", so it can be a program name with args.
++set dummy ranlib; ac_word=$2
++{ $as_echo "$as_me:${as_lineno-$LINENO}: checking for $ac_word" >&5
++$as_echo_n "checking for $ac_word... " >&6; }
++if ${ac_cv_prog_ac_ct_RANLIB+:} false; then :
++  $as_echo_n "(cached) " >&6
++else
++  if test -n "$ac_ct_RANLIB"; then
++  ac_cv_prog_ac_ct_RANLIB="$ac_ct_RANLIB" # Let the user override the test.
++else
++as_save_IFS=$IFS; IFS=$PATH_SEPARATOR
++for as_dir in $PATH
++do
++  IFS=$as_save_IFS
++  test -z "$as_dir" && as_dir=.
++    for ac_exec_ext in '' $ac_executable_extensions; do
++  if as_fn_executable_p "$as_dir/$ac_word$ac_exec_ext"; then
++    ac_cv_prog_ac_ct_RANLIB="ranlib"
++    $as_echo "$as_me:${as_lineno-$LINENO}: found $as_dir/$ac_word$ac_exec_ext" >&5
++    break 2
++  fi
++done
++  done
++IFS=$as_save_IFS
++
++fi
++fi
++ac_ct_RANLIB=$ac_cv_prog_ac_ct_RANLIB
++if test -n "$ac_ct_RANLIB"; then
++  { $as_echo "$as_me:${as_lineno-$LINENO}: result: $ac_ct_RANLIB" >&5
++$as_echo "$ac_ct_RANLIB" >&6; }
++else
++  { $as_echo "$as_me:${as_lineno-$LINENO}: result: no" >&5
++$as_echo "no" >&6; }
++fi
++
++  if test "x$ac_ct_RANLIB" = x; then
++    RANLIB=":"
++  else
++    case $cross_compiling:$ac_tool_warned in
++yes:)
++{ $as_echo "$as_me:${as_lineno-$LINENO}: WARNING: using cross tools not prefixed with host triplet" >&5
++$as_echo "$as_me: WARNING: using cross tools not prefixed with host triplet" >&2;}
++ac_tool_warned=yes ;;
++esac
++    RANLIB=$ac_ct_RANLIB
++  fi
++else
++  RANLIB="$ac_cv_prog_RANLIB"
++fi
++
++
++# Some of the common include files depend on bfd.h, and bfd.h checks
++# that config.h is included first by testing that the PACKAGE macro
++# is defined.
++PACKAGE=sim
++
++cat >>confdefs.h <<_ACEOF
++#define PACKAGE "$PACKAGE"
++_ACEOF
++
++
++
++# Dependency checking.
++ac_config_commands="$ac_config_commands depdir"
++
++
++depcc="$CC"   am_compiler_list=
++
++am_depcomp=$ac_aux_dir/depcomp
++{ $as_echo "$as_me:${as_lineno-$LINENO}: checking dependency style of $depcc" >&5
++$as_echo_n "checking dependency style of $depcc... " >&6; }
++if ${am_cv_CC_dependencies_compiler_type+:} false; then :
++  $as_echo_n "(cached) " >&6
++else
++  if test -f "$am_depcomp"; then
++  # We make a subdir and do the tests there.  Otherwise we can end up
++  # making bogus files that we don't know about and never remove.  For
++  # instance it was reported that on HP-UX the gcc test will end up
++  # making a dummy file named `D' -- because `-MD' means `put the output
++  # in D'.
++  mkdir conftest.dir
++  # Copy depcomp to subdir because otherwise we won't find it if we're
++  # using a relative directory.
++  cp "$am_depcomp" conftest.dir
++  cd conftest.dir
++  # We will build objects and dependencies in a subdirectory because
++  # it helps to detect inapplicable dependency modes.  For instance
++  # both Tru64's cc and ICC support -MD to output dependencies as a
++  # side effect of compilation, but ICC will put the dependencies in
++  # the current directory while Tru64 will put them in the object
++  # directory.
++  mkdir sub
++
++  am_cv_CC_dependencies_compiler_type=none
++  if test "$am_compiler_list" = ""; then
++     am_compiler_list=`sed -n 's/^\([a-zA-Z0-9]*\))$/\1/p' < ./depcomp`
++  fi
++  for depmode in $am_compiler_list; do
++    if test $depmode = none; then break; fi
++
++    $as_echo "$as_me:$LINENO: trying $depmode" >&5
++    # Setup a source with many dependencies, because some compilers
++    # like to wrap large dependency lists on column 80 (with \), and
++    # we should not choose a depcomp mode which is confused by this.
++    #
++    # We need to recreate these files for each test, as the compiler may
++    # overwrite some of them when testing with obscure command lines.
++    # This happens at least with the AIX C compiler.
++    : > sub/conftest.c
++    for i in 1 2 3 4 5 6; do
++      echo '#include "conftst'$i'.h"' >> sub/conftest.c
++      # Using `: > sub/conftst$i.h' creates only sub/conftst1.h with
++      # Solaris 8's {/usr,}/bin/sh.
++      touch sub/conftst$i.h
++    done
++    echo "include sub/conftest.Po" > confmf
++
++    # We check with `-c' and `-o' for the sake of the "dashmstdout"
++    # mode.  It turns out that the SunPro C++ compiler does not properly
++    # handle `-M -o', and we need to detect this.
++    depcmd="depmode=$depmode \
++       source=sub/conftest.c object=sub/conftest.${OBJEXT-o} \
++       depfile=sub/conftest.Po tmpdepfile=sub/conftest.TPo \
++       $SHELL ./depcomp $depcc -c -o sub/conftest.${OBJEXT-o} sub/conftest.c"
++    echo "| $depcmd" | sed -e 's/  */ /g' >&5
++    if env $depcmd > conftest.err 2>&1 &&
++       grep sub/conftst6.h sub/conftest.Po >>conftest.err 2>&1 &&
++       grep sub/conftest.${OBJEXT-o} sub/conftest.Po >>conftest.err 2>&1 &&
++       ${MAKE-make} -s -f confmf >>conftest.err 2>&1; then
++      # icc doesn't choke on unknown options, it will just issue warnings
++      # or remarks (even with -Werror).  So we grep stderr for any message
++      # that says an option was ignored or not supported.
++      # When given -MP, icc 7.0 and 7.1 complain thusly:
++      #   icc: Command line warning: ignoring option '-M'; no argument required
++      # The diagnosis changed in icc 8.0:
++      #   icc: Command line remark: option '-MP' not supported
++      if (grep 'ignoring option' conftest.err ||
++          grep 'not supported' conftest.err) >/dev/null 2>&1; then :; else
++        am_cv_CC_dependencies_compiler_type=$depmode
++	$as_echo "$as_me:$LINENO: success" >&5
++        break
++      fi
++    fi
++    $as_echo "$as_me:$LINENO: failure, diagnostics are:" >&5
++    sed -e 's/^/| /' < conftest.err >&5
++  done
++
++  cd ..
++  rm -rf conftest.dir
++else
++  am_cv_CC_dependencies_compiler_type=none
++fi
++
++fi
++{ $as_echo "$as_me:${as_lineno-$LINENO}: result: $am_cv_CC_dependencies_compiler_type" >&5
++$as_echo "$am_cv_CC_dependencies_compiler_type" >&6; }
++if test x${am_cv_CC_dependencies_compiler_type-none} = xnone
++then as_fn_error $? "no usable dependency style found" "$LINENO" 5
++else CCDEPMODE=depmode=$am_cv_CC_dependencies_compiler_type
++
++fi
++
++
++# Check for the 'make' the user wants to use.
++for ac_prog in make
++do
++  # Extract the first word of "$ac_prog", so it can be a program name with args.
++set dummy $ac_prog; ac_word=$2
++{ $as_echo "$as_me:${as_lineno-$LINENO}: checking for $ac_word" >&5
++$as_echo_n "checking for $ac_word... " >&6; }
++if ${ac_cv_prog_MAKE+:} false; then :
++  $as_echo_n "(cached) " >&6
++else
++  if test -n "$MAKE"; then
++  ac_cv_prog_MAKE="$MAKE" # Let the user override the test.
++else
++as_save_IFS=$IFS; IFS=$PATH_SEPARATOR
++for as_dir in $PATH
++do
++  IFS=$as_save_IFS
++  test -z "$as_dir" && as_dir=.
++    for ac_exec_ext in '' $ac_executable_extensions; do
++  if as_fn_executable_p "$as_dir/$ac_word$ac_exec_ext"; then
++    ac_cv_prog_MAKE="$ac_prog"
++    $as_echo "$as_me:${as_lineno-$LINENO}: found $as_dir/$ac_word$ac_exec_ext" >&5
++    break 2
++  fi
++done
++  done
++IFS=$as_save_IFS
++
++fi
++fi
++MAKE=$ac_cv_prog_MAKE
++if test -n "$MAKE"; then
++  { $as_echo "$as_me:${as_lineno-$LINENO}: result: $MAKE" >&5
++$as_echo "$MAKE" >&6; }
++else
++  { $as_echo "$as_me:${as_lineno-$LINENO}: result: no" >&5
++$as_echo "no" >&6; }
++fi
++
++
++  test -n "$MAKE" && break
++done
++
++MAKE_IS_GNU=
++case "`$MAKE --version 2>&1 | sed 1q`" in
++  *GNU*)
++    MAKE_IS_GNU=yes
++    ;;
++esac
++ if test "$MAKE_IS_GNU" = yes; then
++  GMAKE_TRUE=
++  GMAKE_FALSE='#'
++else
++  GMAKE_TRUE='#'
++  GMAKE_FALSE=
++fi
++
++
++ALL_LINGUAS=
++# If we haven't got the data from the intl directory,
++# assume NLS is disabled.
++USE_NLS=no
++LIBINTL=
++LIBINTL_DEP=
++INCINTL=
++XGETTEXT=
++GMSGFMT=
++POSUB=
++
++if test -f  ../../intl/config.intl; then
++  .  ../../intl/config.intl
++fi
++{ $as_echo "$as_me:${as_lineno-$LINENO}: checking whether NLS is requested" >&5
++$as_echo_n "checking whether NLS is requested... " >&6; }
++if test x"$USE_NLS" != xyes; then
++  { $as_echo "$as_me:${as_lineno-$LINENO}: result: no" >&5
++$as_echo "no" >&6; }
++else
++  { $as_echo "$as_me:${as_lineno-$LINENO}: result: yes" >&5
++$as_echo "yes" >&6; }
++
++$as_echo "#define ENABLE_NLS 1" >>confdefs.h
++
++
++  { $as_echo "$as_me:${as_lineno-$LINENO}: checking for catalogs to be installed" >&5
++$as_echo_n "checking for catalogs to be installed... " >&6; }
++  # Look for .po and .gmo files in the source directory.
++  CATALOGS=
++  XLINGUAS=
++  for cat in $srcdir/po/*.gmo $srcdir/po/*.po; do
++    # If there aren't any .gmo files the shell will give us the
++    # literal string "../path/to/srcdir/po/*.gmo" which has to be
++    # weeded out.
++    case "$cat" in *\**)
++      continue;;
++    esac
++    # The quadruple backslash is collapsed to a double backslash
++    # by the backticks, then collapsed again by the double quotes,
++    # leaving us with one backslash in the sed expression (right
++    # before the dot that mustn't act as a wildcard).
++    cat=`echo $cat | sed -e "s!$srcdir/po/!!" -e "s!\\\\.po!.gmo!"`
++    lang=`echo $cat | sed -e "s!\\\\.gmo!!"`
++    # The user is allowed to set LINGUAS to a list of languages to
++    # install catalogs for.  If it's empty that means "all of them."
++    if test "x$LINGUAS" = x; then
++      CATALOGS="$CATALOGS $cat"
++      XLINGUAS="$XLINGUAS $lang"
++    else
++      case "$LINGUAS" in *$lang*)
++        CATALOGS="$CATALOGS $cat"
++        XLINGUAS="$XLINGUAS $lang"
++        ;;
++      esac
++    fi
++  done
++  LINGUAS="$XLINGUAS"
++  { $as_echo "$as_me:${as_lineno-$LINENO}: result: $LINGUAS" >&5
++$as_echo "$LINGUAS" >&6; }
++
++
++    DATADIRNAME=share
++
++  INSTOBJEXT=.mo
++
++  GENCAT=gencat
++
++  CATOBJEXT=.gmo
++
++fi
++
++# Check for common headers.
++# FIXME: Seems to me this can cause problems for i386-windows hosts.
++# At one point there were hardcoded AC_DEFINE's if ${host} = i386-*-windows*.
++for ac_header in stdlib.h string.h strings.h unistd.h time.h
++do :
++  as_ac_Header=`$as_echo "ac_cv_header_$ac_header" | $as_tr_sh`
++ac_fn_c_check_header_mongrel "$LINENO" "$ac_header" "$as_ac_Header" "$ac_includes_default"
++if eval test \"x\$"$as_ac_Header"\" = x"yes"; then :
++  cat >>confdefs.h <<_ACEOF
++#define `$as_echo "HAVE_$ac_header" | $as_tr_cpp` 1
++_ACEOF
++
++fi
++
++done
++
++for ac_header in sys/time.h sys/times.h sys/resource.h sys/mman.h
++do :
++  as_ac_Header=`$as_echo "ac_cv_header_$ac_header" | $as_tr_sh`
++ac_fn_c_check_header_mongrel "$LINENO" "$ac_header" "$as_ac_Header" "$ac_includes_default"
++if eval test \"x\$"$as_ac_Header"\" = x"yes"; then :
++  cat >>confdefs.h <<_ACEOF
++#define `$as_echo "HAVE_$ac_header" | $as_tr_cpp` 1
++_ACEOF
++
++fi
++
++done
++
++for ac_header in fcntl.h fpu_control.h
++do :
++  as_ac_Header=`$as_echo "ac_cv_header_$ac_header" | $as_tr_sh`
++ac_fn_c_check_header_mongrel "$LINENO" "$ac_header" "$as_ac_Header" "$ac_includes_default"
++if eval test \"x\$"$as_ac_Header"\" = x"yes"; then :
++  cat >>confdefs.h <<_ACEOF
++#define `$as_echo "HAVE_$ac_header" | $as_tr_cpp` 1
++_ACEOF
++
++fi
++
++done
++
++for ac_header in dlfcn.h errno.h sys/stat.h
++do :
++  as_ac_Header=`$as_echo "ac_cv_header_$ac_header" | $as_tr_sh`
++ac_fn_c_check_header_mongrel "$LINENO" "$ac_header" "$as_ac_Header" "$ac_includes_default"
++if eval test \"x\$"$as_ac_Header"\" = x"yes"; then :
++  cat >>confdefs.h <<_ACEOF
++#define `$as_echo "HAVE_$ac_header" | $as_tr_cpp` 1
++_ACEOF
++
++fi
++
++done
++
++for ac_func in getrusage time sigaction __setfpucw
++do :
++  as_ac_var=`$as_echo "ac_cv_func_$ac_func" | $as_tr_sh`
++ac_fn_c_check_func "$LINENO" "$ac_func" "$as_ac_var"
++if eval test \"x\$"$as_ac_var"\" = x"yes"; then :
++  cat >>confdefs.h <<_ACEOF
++#define `$as_echo "HAVE_$ac_func" | $as_tr_cpp` 1
++_ACEOF
++
++fi
++done
++
++for ac_func in mmap munmap lstat truncate ftruncate posix_fallocate
++do :
++  as_ac_var=`$as_echo "ac_cv_func_$ac_func" | $as_tr_sh`
++ac_fn_c_check_func "$LINENO" "$ac_func" "$as_ac_var"
++if eval test \"x\$"$as_ac_var"\" = x"yes"; then :
++  cat >>confdefs.h <<_ACEOF
++#define `$as_echo "HAVE_$ac_func" | $as_tr_cpp` 1
++_ACEOF
++
++fi
++done
++
++ac_fn_c_check_member "$LINENO" "struct stat" "st_dev" "ac_cv_member_struct_stat_st_dev" "#ifdef HAVE_SYS_TYPES_H
++#include <sys/types.h>
++#endif
++#ifdef HAVE_SYS_STAT_H
++#include <sys/stat.h>
++#endif
++"
++if test "x$ac_cv_member_struct_stat_st_dev" = xyes; then :
++
++cat >>confdefs.h <<_ACEOF
++#define HAVE_STRUCT_STAT_ST_DEV 1
++_ACEOF
++
++
++fi
++ac_fn_c_check_member "$LINENO" "struct stat" "st_ino" "ac_cv_member_struct_stat_st_ino" "#ifdef HAVE_SYS_TYPES_H
++#include <sys/types.h>
++#endif
++#ifdef HAVE_SYS_STAT_H
++#include <sys/stat.h>
++#endif
++"
++if test "x$ac_cv_member_struct_stat_st_ino" = xyes; then :
++
++cat >>confdefs.h <<_ACEOF
++#define HAVE_STRUCT_STAT_ST_INO 1
++_ACEOF
++
++
++fi
++ac_fn_c_check_member "$LINENO" "struct stat" "st_mode" "ac_cv_member_struct_stat_st_mode" "#ifdef HAVE_SYS_TYPES_H
++#include <sys/types.h>
++#endif
++#ifdef HAVE_SYS_STAT_H
++#include <sys/stat.h>
++#endif
++"
++if test "x$ac_cv_member_struct_stat_st_mode" = xyes; then :
++
++cat >>confdefs.h <<_ACEOF
++#define HAVE_STRUCT_STAT_ST_MODE 1
++_ACEOF
++
++
++fi
++ac_fn_c_check_member "$LINENO" "struct stat" "st_nlink" "ac_cv_member_struct_stat_st_nlink" "#ifdef HAVE_SYS_TYPES_H
++#include <sys/types.h>
++#endif
++#ifdef HAVE_SYS_STAT_H
++#include <sys/stat.h>
++#endif
++"
++if test "x$ac_cv_member_struct_stat_st_nlink" = xyes; then :
++
++cat >>confdefs.h <<_ACEOF
++#define HAVE_STRUCT_STAT_ST_NLINK 1
++_ACEOF
++
++
++fi
++ac_fn_c_check_member "$LINENO" "struct stat" "st_uid" "ac_cv_member_struct_stat_st_uid" "#ifdef HAVE_SYS_TYPES_H
++#include <sys/types.h>
++#endif
++#ifdef HAVE_SYS_STAT_H
++#include <sys/stat.h>
++#endif
++"
++if test "x$ac_cv_member_struct_stat_st_uid" = xyes; then :
++
++cat >>confdefs.h <<_ACEOF
++#define HAVE_STRUCT_STAT_ST_UID 1
++_ACEOF
++
++
++fi
++ac_fn_c_check_member "$LINENO" "struct stat" "st_gid" "ac_cv_member_struct_stat_st_gid" "#ifdef HAVE_SYS_TYPES_H
++#include <sys/types.h>
++#endif
++#ifdef HAVE_SYS_STAT_H
++#include <sys/stat.h>
++#endif
++"
++if test "x$ac_cv_member_struct_stat_st_gid" = xyes; then :
++
++cat >>confdefs.h <<_ACEOF
++#define HAVE_STRUCT_STAT_ST_GID 1
++_ACEOF
++
++
++fi
++ac_fn_c_check_member "$LINENO" "struct stat" "st_rdev" "ac_cv_member_struct_stat_st_rdev" "#ifdef HAVE_SYS_TYPES_H
++#include <sys/types.h>
++#endif
++#ifdef HAVE_SYS_STAT_H
++#include <sys/stat.h>
++#endif
++"
++if test "x$ac_cv_member_struct_stat_st_rdev" = xyes; then :
++
++cat >>confdefs.h <<_ACEOF
++#define HAVE_STRUCT_STAT_ST_RDEV 1
++_ACEOF
++
++
++fi
++ac_fn_c_check_member "$LINENO" "struct stat" "st_size" "ac_cv_member_struct_stat_st_size" "#ifdef HAVE_SYS_TYPES_H
++#include <sys/types.h>
++#endif
++#ifdef HAVE_SYS_STAT_H
++#include <sys/stat.h>
++#endif
++"
++if test "x$ac_cv_member_struct_stat_st_size" = xyes; then :
++
++cat >>confdefs.h <<_ACEOF
++#define HAVE_STRUCT_STAT_ST_SIZE 1
++_ACEOF
++
++
++fi
++ac_fn_c_check_member "$LINENO" "struct stat" "st_blksize" "ac_cv_member_struct_stat_st_blksize" "#ifdef HAVE_SYS_TYPES_H
++#include <sys/types.h>
++#endif
++#ifdef HAVE_SYS_STAT_H
++#include <sys/stat.h>
++#endif
++"
++if test "x$ac_cv_member_struct_stat_st_blksize" = xyes; then :
++
++cat >>confdefs.h <<_ACEOF
++#define HAVE_STRUCT_STAT_ST_BLKSIZE 1
++_ACEOF
++
++
++fi
++ac_fn_c_check_member "$LINENO" "struct stat" "st_blocks" "ac_cv_member_struct_stat_st_blocks" "#ifdef HAVE_SYS_TYPES_H
++#include <sys/types.h>
++#endif
++#ifdef HAVE_SYS_STAT_H
++#include <sys/stat.h>
++#endif
++"
++if test "x$ac_cv_member_struct_stat_st_blocks" = xyes; then :
++
++cat >>confdefs.h <<_ACEOF
++#define HAVE_STRUCT_STAT_ST_BLOCKS 1
++_ACEOF
++
++
++fi
++ac_fn_c_check_member "$LINENO" "struct stat" "st_atime" "ac_cv_member_struct_stat_st_atime" "#ifdef HAVE_SYS_TYPES_H
++#include <sys/types.h>
++#endif
++#ifdef HAVE_SYS_STAT_H
++#include <sys/stat.h>
++#endif
++"
++if test "x$ac_cv_member_struct_stat_st_atime" = xyes; then :
++
++cat >>confdefs.h <<_ACEOF
++#define HAVE_STRUCT_STAT_ST_ATIME 1
++_ACEOF
++
++
++fi
++ac_fn_c_check_member "$LINENO" "struct stat" "st_mtime" "ac_cv_member_struct_stat_st_mtime" "#ifdef HAVE_SYS_TYPES_H
++#include <sys/types.h>
++#endif
++#ifdef HAVE_SYS_STAT_H
++#include <sys/stat.h>
++#endif
++"
++if test "x$ac_cv_member_struct_stat_st_mtime" = xyes; then :
++
++cat >>confdefs.h <<_ACEOF
++#define HAVE_STRUCT_STAT_ST_MTIME 1
++_ACEOF
++
++
++fi
++ac_fn_c_check_member "$LINENO" "struct stat" "st_ctime" "ac_cv_member_struct_stat_st_ctime" "#ifdef HAVE_SYS_TYPES_H
++#include <sys/types.h>
++#endif
++#ifdef HAVE_SYS_STAT_H
++#include <sys/stat.h>
++#endif
++"
++if test "x$ac_cv_member_struct_stat_st_ctime" = xyes; then :
++
++cat >>confdefs.h <<_ACEOF
++#define HAVE_STRUCT_STAT_ST_CTIME 1
++_ACEOF
++
++
++fi
++
++ac_fn_c_check_type "$LINENO" "socklen_t" "ac_cv_type_socklen_t" "#include <sys/types.h>
++#include <sys/socket.h>
++
++"
++if test "x$ac_cv_type_socklen_t" = xyes; then :
++
++cat >>confdefs.h <<_ACEOF
++#define HAVE_SOCKLEN_T 1
++_ACEOF
++
++
++fi
++
++
++# Check for socket libraries
++{ $as_echo "$as_me:${as_lineno-$LINENO}: checking for bind in -lsocket" >&5
++$as_echo_n "checking for bind in -lsocket... " >&6; }
++if ${ac_cv_lib_socket_bind+:} false; then :
++  $as_echo_n "(cached) " >&6
++else
++  ac_check_lib_save_LIBS=$LIBS
++LIBS="-lsocket  $LIBS"
++cat confdefs.h - <<_ACEOF >conftest.$ac_ext
++/* end confdefs.h.  */
++
++/* Override any GCC internal prototype to avoid an error.
++   Use char because int might match the return type of a GCC
++   builtin and then its argument prototype would still apply.  */
++#ifdef __cplusplus
++extern "C"
++#endif
++char bind ();
++int
++main ()
++{
++return bind ();
++  ;
++  return 0;
++}
++_ACEOF
++if ac_fn_c_try_link "$LINENO"; then :
++  ac_cv_lib_socket_bind=yes
++else
++  ac_cv_lib_socket_bind=no
++fi
++rm -f core conftest.err conftest.$ac_objext \
++    conftest$ac_exeext conftest.$ac_ext
++LIBS=$ac_check_lib_save_LIBS
++fi
++{ $as_echo "$as_me:${as_lineno-$LINENO}: result: $ac_cv_lib_socket_bind" >&5
++$as_echo "$ac_cv_lib_socket_bind" >&6; }
++if test "x$ac_cv_lib_socket_bind" = xyes; then :
++  cat >>confdefs.h <<_ACEOF
++#define HAVE_LIBSOCKET 1
++_ACEOF
++
++  LIBS="-lsocket $LIBS"
++
++fi
++
++{ $as_echo "$as_me:${as_lineno-$LINENO}: checking for gethostbyname in -lnsl" >&5
++$as_echo_n "checking for gethostbyname in -lnsl... " >&6; }
++if ${ac_cv_lib_nsl_gethostbyname+:} false; then :
++  $as_echo_n "(cached) " >&6
++else
++  ac_check_lib_save_LIBS=$LIBS
++LIBS="-lnsl  $LIBS"
++cat confdefs.h - <<_ACEOF >conftest.$ac_ext
++/* end confdefs.h.  */
++
++/* Override any GCC internal prototype to avoid an error.
++   Use char because int might match the return type of a GCC
++   builtin and then its argument prototype would still apply.  */
++#ifdef __cplusplus
++extern "C"
++#endif
++char gethostbyname ();
++int
++main ()
++{
++return gethostbyname ();
++  ;
++  return 0;
++}
++_ACEOF
++if ac_fn_c_try_link "$LINENO"; then :
++  ac_cv_lib_nsl_gethostbyname=yes
++else
++  ac_cv_lib_nsl_gethostbyname=no
++fi
++rm -f core conftest.err conftest.$ac_objext \
++    conftest$ac_exeext conftest.$ac_ext
++LIBS=$ac_check_lib_save_LIBS
++fi
++{ $as_echo "$as_me:${as_lineno-$LINENO}: result: $ac_cv_lib_nsl_gethostbyname" >&5
++$as_echo "$ac_cv_lib_nsl_gethostbyname" >&6; }
++if test "x$ac_cv_lib_nsl_gethostbyname" = xyes; then :
++  cat >>confdefs.h <<_ACEOF
++#define HAVE_LIBNSL 1
++_ACEOF
++
++  LIBS="-lnsl $LIBS"
++
++fi
++
++
++# BFD conditionally uses zlib, so we must link it in if libbfd does, by
++# using the same condition.
++
++  # Use the system's zlib library.
++  zlibdir="-L\$(top_builddir)/../zlib"
++  zlibinc="-I\$(top_srcdir)/../zlib"
++
++# Check whether --with-system-zlib was given.
++if test "${with_system_zlib+set}" = set; then :
++  withval=$with_system_zlib; if test x$with_system_zlib = xyes ; then
++    zlibdir=
++    zlibinc=
++  fi
++
++fi
++
++
++
++
++
++# BFD uses libdl when when plugins enabled.
++
++  maybe_plugins=no
++  for ac_header in dlfcn.h
++do :
++  ac_fn_c_check_header_compile "$LINENO" "dlfcn.h" "ac_cv_header_dlfcn_h" "$ac_includes_default
++"
++if test "x$ac_cv_header_dlfcn_h" = xyes; then :
++  cat >>confdefs.h <<_ACEOF
++#define HAVE_DLFCN_H 1
++_ACEOF
++ maybe_plugins=yes
++fi
++
++done
++
++  for ac_header in windows.h
++do :
++  ac_fn_c_check_header_compile "$LINENO" "windows.h" "ac_cv_header_windows_h" "$ac_includes_default
++"
++if test "x$ac_cv_header_windows_h" = xyes; then :
++  cat >>confdefs.h <<_ACEOF
++#define HAVE_WINDOWS_H 1
++_ACEOF
++ maybe_plugins=yes
++fi
++
++done
++
++
++  # Check whether --enable-plugins was given.
++if test "${enable_plugins+set}" = set; then :
++  enableval=$enable_plugins; case "${enableval}" in
++      no) plugins=no ;;
++      *) plugins=yes
++         if test "$maybe_plugins" != "yes" ; then
++	   as_fn_error $? "Building with plugin support requires a host that supports dlopen." "$LINENO" 5
++	 fi ;;
++     esac
++else
++  plugins=$maybe_plugins
++
++fi
++
++  if test "$plugins" = "yes"; then
++    { $as_echo "$as_me:${as_lineno-$LINENO}: checking for library containing dlsym" >&5
++$as_echo_n "checking for library containing dlsym... " >&6; }
++if ${ac_cv_search_dlsym+:} false; then :
++  $as_echo_n "(cached) " >&6
++else
++  ac_func_search_save_LIBS=$LIBS
++cat confdefs.h - <<_ACEOF >conftest.$ac_ext
++/* end confdefs.h.  */
++
++/* Override any GCC internal prototype to avoid an error.
++   Use char because int might match the return type of a GCC
++   builtin and then its argument prototype would still apply.  */
++#ifdef __cplusplus
++extern "C"
++#endif
++char dlsym ();
++int
++main ()
++{
++return dlsym ();
++  ;
++  return 0;
++}
++_ACEOF
++for ac_lib in '' dl; do
++  if test -z "$ac_lib"; then
++    ac_res="none required"
++  else
++    ac_res=-l$ac_lib
++    LIBS="-l$ac_lib  $ac_func_search_save_LIBS"
++  fi
++  if ac_fn_c_try_link "$LINENO"; then :
++  ac_cv_search_dlsym=$ac_res
++fi
++rm -f core conftest.err conftest.$ac_objext \
++    conftest$ac_exeext
++  if ${ac_cv_search_dlsym+:} false; then :
++  break
++fi
++done
++if ${ac_cv_search_dlsym+:} false; then :
++
++else
++  ac_cv_search_dlsym=no
++fi
++rm conftest.$ac_ext
++LIBS=$ac_func_search_save_LIBS
++fi
++{ $as_echo "$as_me:${as_lineno-$LINENO}: result: $ac_cv_search_dlsym" >&5
++$as_echo "$ac_cv_search_dlsym" >&6; }
++ac_res=$ac_cv_search_dlsym
++if test "$ac_res" != no; then :
++  test "$ac_res" = "none required" || LIBS="$ac_res $LIBS"
++
++fi
++
++  fi
++
++ if test "$plugins" = yes; then
++  PLUGINS_TRUE=
++  PLUGINS_FALSE='#'
++else
++  PLUGINS_TRUE='#'
++  PLUGINS_FALSE=
++fi
++
++
++
++
++
++# Set options
++enable_dlopen=yes
++
++
++
++
++  enable_win32_dll=no
++
++
++            # Check whether --enable-shared was given.
++if test "${enable_shared+set}" = set; then :
++  enableval=$enable_shared; p=${PACKAGE-default}
++    case $enableval in
++    yes) enable_shared=yes ;;
++    no) enable_shared=no ;;
++    *)
++      enable_shared=no
++      # Look at the argument we got.  We use all the common list separators.
++      lt_save_ifs="$IFS"; IFS="${IFS}$PATH_SEPARATOR,"
++      for pkg in $enableval; do
++	IFS="$lt_save_ifs"
++	if test "X$pkg" = "X$p"; then
++	  enable_shared=yes
++	fi
++      done
++      IFS="$lt_save_ifs"
++      ;;
++    esac
++else
++  enable_shared=yes
++fi
++
++
++
++
++
++
++
++
++
++  # Check whether --enable-static was given.
++if test "${enable_static+set}" = set; then :
++  enableval=$enable_static; p=${PACKAGE-default}
++    case $enableval in
++    yes) enable_static=yes ;;
++    no) enable_static=no ;;
++    *)
++     enable_static=no
++      # Look at the argument we got.  We use all the common list separators.
++      lt_save_ifs="$IFS"; IFS="${IFS}$PATH_SEPARATOR,"
++      for pkg in $enableval; do
++	IFS="$lt_save_ifs"
++	if test "X$pkg" = "X$p"; then
++	  enable_static=yes
++	fi
++      done
++      IFS="$lt_save_ifs"
++      ;;
++    esac
++else
++  enable_static=yes
++fi
++
++
++
++
++
++
++
++
++
++
++# Check whether --with-pic was given.
++if test "${with_pic+set}" = set; then :
++  withval=$with_pic; pic_mode="$withval"
++else
++  pic_mode=default
++fi
++
++
++test -z "$pic_mode" && pic_mode=default
++
++
++
++
++
++
++
++  # Check whether --enable-fast-install was given.
++if test "${enable_fast_install+set}" = set; then :
++  enableval=$enable_fast_install; p=${PACKAGE-default}
++    case $enableval in
++    yes) enable_fast_install=yes ;;
++    no) enable_fast_install=no ;;
++    *)
++      enable_fast_install=no
++      # Look at the argument we got.  We use all the common list separators.
++      lt_save_ifs="$IFS"; IFS="${IFS}$PATH_SEPARATOR,"
++      for pkg in $enableval; do
++	IFS="$lt_save_ifs"
++	if test "X$pkg" = "X$p"; then
++	  enable_fast_install=yes
++	fi
++      done
++      IFS="$lt_save_ifs"
++      ;;
++    esac
++else
++  enable_fast_install=yes
++fi
++
++
++
++
++
++
++
++
++
++
++
++# This can be used to rebuild libtool when needed
++LIBTOOL_DEPS="$ltmain"
++
++# Always use our own libtool.
++LIBTOOL='$(SHELL) $(top_builddir)/libtool'
++
++
++
++
++
++
++
++
++
++
++
++
++
++
++
++
++
++
++
++
++
++
++
++
++
++
++test -z "$LN_S" && LN_S="ln -s"
++
++
++
++
++
++
++
++
++
++
++
++
++
++
++if test -n "${ZSH_VERSION+set}" ; then
++   setopt NO_GLOB_SUBST
++fi
++
++{ $as_echo "$as_me:${as_lineno-$LINENO}: checking for objdir" >&5
++$as_echo_n "checking for objdir... " >&6; }
++if ${lt_cv_objdir+:} false; then :
++  $as_echo_n "(cached) " >&6
++else
++  rm -f .libs 2>/dev/null
++mkdir .libs 2>/dev/null
++if test -d .libs; then
++  lt_cv_objdir=.libs
++else
++  # MS-DOS does not allow filenames that begin with a dot.
++  lt_cv_objdir=_libs
++fi
++rmdir .libs 2>/dev/null
++fi
++{ $as_echo "$as_me:${as_lineno-$LINENO}: result: $lt_cv_objdir" >&5
++$as_echo "$lt_cv_objdir" >&6; }
++objdir=$lt_cv_objdir
++
++
++
++
++
++cat >>confdefs.h <<_ACEOF
++#define LT_OBJDIR "$lt_cv_objdir/"
++_ACEOF
++
++
++
++
++case $host_os in
++aix3*)
++  # AIX sometimes has problems with the GCC collect2 program.  For some
++  # reason, if we set the COLLECT_NAMES environment variable, the problems
++  # vanish in a puff of smoke.
++  if test "X${COLLECT_NAMES+set}" != Xset; then
++    COLLECT_NAMES=
++    export COLLECT_NAMES
++  fi
++  ;;
++esac
++
++# Global variables:
++ofile=libtool
++can_build_shared=yes
++
++# All known linkers require a `.a' archive for static linking (except MSVC,
++# which needs '.lib').
++libext=a
++
++with_gnu_ld="$lt_cv_prog_gnu_ld"
++
++old_CC="$CC"
++old_CFLAGS="$CFLAGS"
++
++# Set sane defaults for various variables
++test -z "$CC" && CC=cc
++test -z "$LTCC" && LTCC=$CC
++test -z "$LTCFLAGS" && LTCFLAGS=$CFLAGS
++test -z "$LD" && LD=ld
++test -z "$ac_objext" && ac_objext=o
++
++for cc_temp in $compiler""; do
++  case $cc_temp in
++    compile | *[\\/]compile | ccache | *[\\/]ccache ) ;;
++    distcc | *[\\/]distcc | purify | *[\\/]purify ) ;;
++    \-*) ;;
++    *) break;;
++  esac
++done
++cc_basename=`$ECHO "$cc_temp" | $SED "s%.*/%%; s%^$host_alias-%%"`
++
++
++# Only perform the check for file, if the check method requires it
++test -z "$MAGIC_CMD" && MAGIC_CMD=file
++case $deplibs_check_method in
++file_magic*)
++  if test "$file_magic_cmd" = '$MAGIC_CMD'; then
++    { $as_echo "$as_me:${as_lineno-$LINENO}: checking for ${ac_tool_prefix}file" >&5
++$as_echo_n "checking for ${ac_tool_prefix}file... " >&6; }
++if ${lt_cv_path_MAGIC_CMD+:} false; then :
++  $as_echo_n "(cached) " >&6
++else
++  case $MAGIC_CMD in
++[\\/*] |  ?:[\\/]*)
++  lt_cv_path_MAGIC_CMD="$MAGIC_CMD" # Let the user override the test with a path.
++  ;;
++*)
++  lt_save_MAGIC_CMD="$MAGIC_CMD"
++  lt_save_ifs="$IFS"; IFS=$PATH_SEPARATOR
++  ac_dummy="/usr/bin$PATH_SEPARATOR$PATH"
++  for ac_dir in $ac_dummy; do
++    IFS="$lt_save_ifs"
++    test -z "$ac_dir" && ac_dir=.
++    if test -f $ac_dir/${ac_tool_prefix}file; then
++      lt_cv_path_MAGIC_CMD="$ac_dir/${ac_tool_prefix}file"
++      if test -n "$file_magic_test_file"; then
++	case $deplibs_check_method in
++	"file_magic "*)
++	  file_magic_regex=`expr "$deplibs_check_method" : "file_magic \(.*\)"`
++	  MAGIC_CMD="$lt_cv_path_MAGIC_CMD"
++	  if eval $file_magic_cmd \$file_magic_test_file 2> /dev/null |
++	    $EGREP "$file_magic_regex" > /dev/null; then
++	    :
++	  else
++	    cat <<_LT_EOF 1>&2
++
++*** Warning: the command libtool uses to detect shared libraries,
++*** $file_magic_cmd, produces output that libtool cannot recognize.
++*** The result is that libtool may fail to recognize shared libraries
++*** as such.  This will affect the creation of libtool libraries that
++*** depend on shared libraries, but programs linked with such libtool
++*** libraries will work regardless of this problem.  Nevertheless, you
++*** may want to report the problem to your system manager and/or to
++*** bug-libtool@gnu.org
++
++_LT_EOF
++	  fi ;;
++	esac
++      fi
++      break
++    fi
++  done
++  IFS="$lt_save_ifs"
++  MAGIC_CMD="$lt_save_MAGIC_CMD"
++  ;;
++esac
++fi
++
++MAGIC_CMD="$lt_cv_path_MAGIC_CMD"
++if test -n "$MAGIC_CMD"; then
++  { $as_echo "$as_me:${as_lineno-$LINENO}: result: $MAGIC_CMD" >&5
++$as_echo "$MAGIC_CMD" >&6; }
++else
++  { $as_echo "$as_me:${as_lineno-$LINENO}: result: no" >&5
++$as_echo "no" >&6; }
++fi
++
++
++
++
++
++if test -z "$lt_cv_path_MAGIC_CMD"; then
++  if test -n "$ac_tool_prefix"; then
++    { $as_echo "$as_me:${as_lineno-$LINENO}: checking for file" >&5
++$as_echo_n "checking for file... " >&6; }
++if ${lt_cv_path_MAGIC_CMD+:} false; then :
++  $as_echo_n "(cached) " >&6
++else
++  case $MAGIC_CMD in
++[\\/*] |  ?:[\\/]*)
++  lt_cv_path_MAGIC_CMD="$MAGIC_CMD" # Let the user override the test with a path.
++  ;;
++*)
++  lt_save_MAGIC_CMD="$MAGIC_CMD"
++  lt_save_ifs="$IFS"; IFS=$PATH_SEPARATOR
++  ac_dummy="/usr/bin$PATH_SEPARATOR$PATH"
++  for ac_dir in $ac_dummy; do
++    IFS="$lt_save_ifs"
++    test -z "$ac_dir" && ac_dir=.
++    if test -f $ac_dir/file; then
++      lt_cv_path_MAGIC_CMD="$ac_dir/file"
++      if test -n "$file_magic_test_file"; then
++	case $deplibs_check_method in
++	"file_magic "*)
++	  file_magic_regex=`expr "$deplibs_check_method" : "file_magic \(.*\)"`
++	  MAGIC_CMD="$lt_cv_path_MAGIC_CMD"
++	  if eval $file_magic_cmd \$file_magic_test_file 2> /dev/null |
++	    $EGREP "$file_magic_regex" > /dev/null; then
++	    :
++	  else
++	    cat <<_LT_EOF 1>&2
++
++*** Warning: the command libtool uses to detect shared libraries,
++*** $file_magic_cmd, produces output that libtool cannot recognize.
++*** The result is that libtool may fail to recognize shared libraries
++*** as such.  This will affect the creation of libtool libraries that
++*** depend on shared libraries, but programs linked with such libtool
++*** libraries will work regardless of this problem.  Nevertheless, you
++*** may want to report the problem to your system manager and/or to
++*** bug-libtool@gnu.org
++
++_LT_EOF
++	  fi ;;
++	esac
++      fi
++      break
++    fi
++  done
++  IFS="$lt_save_ifs"
++  MAGIC_CMD="$lt_save_MAGIC_CMD"
++  ;;
++esac
++fi
++
++MAGIC_CMD="$lt_cv_path_MAGIC_CMD"
++if test -n "$MAGIC_CMD"; then
++  { $as_echo "$as_me:${as_lineno-$LINENO}: result: $MAGIC_CMD" >&5
++$as_echo "$MAGIC_CMD" >&6; }
++else
++  { $as_echo "$as_me:${as_lineno-$LINENO}: result: no" >&5
++$as_echo "no" >&6; }
++fi
++
++
++  else
++    MAGIC_CMD=:
++  fi
++fi
++
++  fi
++  ;;
++esac
++
++# Use C for the default configuration in the libtool script
++
++lt_save_CC="$CC"
++ac_ext=c
++ac_cpp='$CPP $CPPFLAGS'
++ac_compile='$CC -c $CFLAGS $CPPFLAGS conftest.$ac_ext >&5'
++ac_link='$CC -o conftest$ac_exeext $CFLAGS $CPPFLAGS $LDFLAGS conftest.$ac_ext $LIBS >&5'
++ac_compiler_gnu=$ac_cv_c_compiler_gnu
++
++
++# Source file extension for C test sources.
++ac_ext=c
++
++# Object file extension for compiled C test sources.
++objext=o
++objext=$objext
++
++# Code to be used in simple compile tests
++lt_simple_compile_test_code="int some_variable = 0;"
++
++# Code to be used in simple link tests
++lt_simple_link_test_code='int main(){return(0);}'
++
++
++
++
++
++
++
++# If no C compiler was specified, use CC.
++LTCC=${LTCC-"$CC"}
++
++# If no C compiler flags were specified, use CFLAGS.
++LTCFLAGS=${LTCFLAGS-"$CFLAGS"}
++
++# Allow CC to be a program name with arguments.
++compiler=$CC
++
++# Save the default compiler, since it gets overwritten when the other
++# tags are being tested, and _LT_TAGVAR(compiler, []) is a NOP.
++compiler_DEFAULT=$CC
++
++# save warnings/boilerplate of simple test code
++ac_outfile=conftest.$ac_objext
++echo "$lt_simple_compile_test_code" >conftest.$ac_ext
++eval "$ac_compile" 2>&1 >/dev/null | $SED '/^$/d; /^ *+/d' >conftest.err
++_lt_compiler_boilerplate=`cat conftest.err`
++$RM conftest*
++
++ac_outfile=conftest.$ac_objext
++echo "$lt_simple_link_test_code" >conftest.$ac_ext
++eval "$ac_link" 2>&1 >/dev/null | $SED '/^$/d; /^ *+/d' >conftest.err
++_lt_linker_boilerplate=`cat conftest.err`
++$RM -r conftest*
++
++
++## CAVEAT EMPTOR:
++## There is no encapsulation within the following macros, do not change
++## the running order or otherwise move them around unless you know exactly
++## what you are doing...
++if test -n "$compiler"; then
++
++lt_prog_compiler_no_builtin_flag=
++
++if test "$GCC" = yes; then
++  case $cc_basename in
++  nvcc*)
++    lt_prog_compiler_no_builtin_flag=' -Xcompiler -fno-builtin' ;;
++  *)
++    lt_prog_compiler_no_builtin_flag=' -fno-builtin' ;;
++  esac
++
++  { $as_echo "$as_me:${as_lineno-$LINENO}: checking if $compiler supports -fno-rtti -fno-exceptions" >&5
++$as_echo_n "checking if $compiler supports -fno-rtti -fno-exceptions... " >&6; }
++if ${lt_cv_prog_compiler_rtti_exceptions+:} false; then :
++  $as_echo_n "(cached) " >&6
++else
++  lt_cv_prog_compiler_rtti_exceptions=no
++   ac_outfile=conftest.$ac_objext
++   echo "$lt_simple_compile_test_code" > conftest.$ac_ext
++   lt_compiler_flag="-fno-rtti -fno-exceptions"
++   # Insert the option either (1) after the last *FLAGS variable, or
++   # (2) before a word containing "conftest.", or (3) at the end.
++   # Note that $ac_compile itself does not contain backslashes and begins
++   # with a dollar sign (not a hyphen), so the echo should work correctly.
++   # The option is referenced via a variable to avoid confusing sed.
++   lt_compile=`echo "$ac_compile" | $SED \
++   -e 's:.*FLAGS}\{0,1\} :&$lt_compiler_flag :; t' \
++   -e 's: [^ ]*conftest\.: $lt_compiler_flag&:; t' \
++   -e 's:$: $lt_compiler_flag:'`
++   (eval echo "\"\$as_me:$LINENO: $lt_compile\"" >&5)
++   (eval "$lt_compile" 2>conftest.err)
++   ac_status=$?
++   cat conftest.err >&5
++   echo "$as_me:$LINENO: \$? = $ac_status" >&5
++   if (exit $ac_status) && test -s "$ac_outfile"; then
++     # The compiler can only warn and ignore the option if not recognized
++     # So say no if there are warnings other than the usual output.
++     $ECHO "$_lt_compiler_boilerplate" | $SED '/^$/d' >conftest.exp
++     $SED '/^$/d; /^ *+/d' conftest.err >conftest.er2
++     if test ! -s conftest.er2 || diff conftest.exp conftest.er2 >/dev/null; then
++       lt_cv_prog_compiler_rtti_exceptions=yes
++     fi
++   fi
++   $RM conftest*
++
++fi
++{ $as_echo "$as_me:${as_lineno-$LINENO}: result: $lt_cv_prog_compiler_rtti_exceptions" >&5
++$as_echo "$lt_cv_prog_compiler_rtti_exceptions" >&6; }
++
++if test x"$lt_cv_prog_compiler_rtti_exceptions" = xyes; then
++    lt_prog_compiler_no_builtin_flag="$lt_prog_compiler_no_builtin_flag -fno-rtti -fno-exceptions"
++else
++    :
++fi
++
++fi
++
++
++
++
++
++
++  lt_prog_compiler_wl=
++lt_prog_compiler_pic=
++lt_prog_compiler_static=
++
++{ $as_echo "$as_me:${as_lineno-$LINENO}: checking for $compiler option to produce PIC" >&5
++$as_echo_n "checking for $compiler option to produce PIC... " >&6; }
++
++  if test "$GCC" = yes; then
++    lt_prog_compiler_wl='-Wl,'
++    lt_prog_compiler_static='-static'
++
++    case $host_os in
++      aix*)
++      # All AIX code is PIC.
++      if test "$host_cpu" = ia64; then
++	# AIX 5 now supports IA64 processor
++	lt_prog_compiler_static='-Bstatic'
++      fi
++      lt_prog_compiler_pic='-fPIC'
++      ;;
++
++    amigaos*)
++      case $host_cpu in
++      powerpc)
++            # see comment about AmigaOS4 .so support
++            lt_prog_compiler_pic='-fPIC'
++        ;;
++      m68k)
++            # FIXME: we need at least 68020 code to build shared libraries, but
++            # adding the `-m68020' flag to GCC prevents building anything better,
++            # like `-m68040'.
++            lt_prog_compiler_pic='-m68020 -resident32 -malways-restore-a4'
++        ;;
++      esac
++      ;;
++
++    beos* | irix5* | irix6* | nonstopux* | osf3* | osf4* | osf5*)
++      # PIC is the default for these OSes.
++      ;;
++
++    mingw* | cygwin* | pw32* | os2* | cegcc*)
++      # This hack is so that the source file can tell whether it is being
++      # built for inclusion in a dll (and should export symbols for example).
++      # Although the cygwin gcc ignores -fPIC, still need this for old-style
++      # (--disable-auto-import) libraries
++      lt_prog_compiler_pic='-DDLL_EXPORT'
++      ;;
++
++    darwin* | rhapsody*)
++      # PIC is the default on this platform
++      # Common symbols not allowed in MH_DYLIB files
++      lt_prog_compiler_pic='-fno-common'
++      ;;
++
++    haiku*)
++      # PIC is the default for Haiku.
++      # The "-static" flag exists, but is broken.
++      lt_prog_compiler_static=
++      ;;
++
++    hpux*)
++      # PIC is the default for 64-bit PA HP-UX, but not for 32-bit
++      # PA HP-UX.  On IA64 HP-UX, PIC is the default but the pic flag
++      # sets the default TLS model and affects inlining.
++      case $host_cpu in
++      hppa*64*)
++	# +Z the default
++	;;
++      *)
++	lt_prog_compiler_pic='-fPIC'
++	;;
++      esac
++      ;;
++
++    interix[3-9]*)
++      # Interix 3.x gcc -fpic/-fPIC options generate broken code.
++      # Instead, we relocate shared libraries at runtime.
++      ;;
++
++    msdosdjgpp*)
++      # Just because we use GCC doesn't mean we suddenly get shared libraries
++      # on systems that don't support them.
++      lt_prog_compiler_can_build_shared=no
++      enable_shared=no
++      ;;
++
++    *nto* | *qnx*)
++      # QNX uses GNU C++, but need to define -shared option too, otherwise
++      # it will coredump.
++      lt_prog_compiler_pic='-fPIC -shared'
++      ;;
++
++    sysv4*MP*)
++      if test -d /usr/nec; then
++	lt_prog_compiler_pic=-Kconform_pic
++      fi
++      ;;
++
++    *)
++      lt_prog_compiler_pic='-fPIC'
++      ;;
++    esac
++
++    case $cc_basename in
++    nvcc*) # Cuda Compiler Driver 2.2
++      lt_prog_compiler_wl='-Xlinker '
++      lt_prog_compiler_pic='-Xcompiler -fPIC'
++      ;;
++    esac
++  else
++    # PORTME Check for flag to pass linker flags through the system compiler.
++    case $host_os in
++    aix*)
++      lt_prog_compiler_wl='-Wl,'
++      if test "$host_cpu" = ia64; then
++	# AIX 5 now supports IA64 processor
++	lt_prog_compiler_static='-Bstatic'
++      else
++	lt_prog_compiler_static='-bnso -bI:/lib/syscalls.exp'
++      fi
++      ;;
++
++    mingw* | cygwin* | pw32* | os2* | cegcc*)
++      # This hack is so that the source file can tell whether it is being
++      # built for inclusion in a dll (and should export symbols for example).
++      lt_prog_compiler_pic='-DDLL_EXPORT'
++      ;;
++
++    hpux9* | hpux10* | hpux11*)
++      lt_prog_compiler_wl='-Wl,'
++      # PIC is the default for IA64 HP-UX and 64-bit HP-UX, but
++      # not for PA HP-UX.
++      case $host_cpu in
++      hppa*64*|ia64*)
++	# +Z the default
++	;;
++      *)
++	lt_prog_compiler_pic='+Z'
++	;;
++      esac
++      # Is there a better lt_prog_compiler_static that works with the bundled CC?
++      lt_prog_compiler_static='${wl}-a ${wl}archive'
++      ;;
++
++    irix5* | irix6* | nonstopux*)
++      lt_prog_compiler_wl='-Wl,'
++      # PIC (with -KPIC) is the default.
++      lt_prog_compiler_static='-non_shared'
++      ;;
++
++    linux* | k*bsd*-gnu | kopensolaris*-gnu)
++      case $cc_basename in
++      # old Intel for x86_64 which still supported -KPIC.
++      ecc*)
++	lt_prog_compiler_wl='-Wl,'
++	lt_prog_compiler_pic='-KPIC'
++	lt_prog_compiler_static='-static'
++        ;;
++      # icc used to be incompatible with GCC.
++      # ICC 10 doesn't accept -KPIC any more.
++      icc* | ifort*)
++	lt_prog_compiler_wl='-Wl,'
++	lt_prog_compiler_pic='-fPIC'
++	lt_prog_compiler_static='-static'
++        ;;
++      # Lahey Fortran 8.1.
++      lf95*)
++	lt_prog_compiler_wl='-Wl,'
++	lt_prog_compiler_pic='--shared'
++	lt_prog_compiler_static='--static'
++	;;
++      pgcc* | pgf77* | pgf90* | pgf95* | pgfortran*)
++        # Portland Group compilers (*not* the Pentium gcc compiler,
++	# which looks to be a dead project)
++	lt_prog_compiler_wl='-Wl,'
++	lt_prog_compiler_pic='-fpic'
++	lt_prog_compiler_static='-Bstatic'
++        ;;
++      ccc*)
++        lt_prog_compiler_wl='-Wl,'
++        # All Alpha code is PIC.
++        lt_prog_compiler_static='-non_shared'
++        ;;
++      xl* | bgxl* | bgf* | mpixl*)
++	# IBM XL C 8.0/Fortran 10.1, 11.1 on PPC and BlueGene
++	lt_prog_compiler_wl='-Wl,'
++	lt_prog_compiler_pic='-qpic'
++	lt_prog_compiler_static='-qstaticlink'
++	;;
++      *)
++	case `$CC -V 2>&1 | sed 5q` in
++	*Sun\ F* | *Sun*Fortran*)
++	  # Sun Fortran 8.3 passes all unrecognized flags to the linker
++	  lt_prog_compiler_pic='-KPIC'
++	  lt_prog_compiler_static='-Bstatic'
++	  lt_prog_compiler_wl=''
++	  ;;
++	*Sun\ C*)
++	  # Sun C 5.9
++	  lt_prog_compiler_pic='-KPIC'
++	  lt_prog_compiler_static='-Bstatic'
++	  lt_prog_compiler_wl='-Wl,'
++	  ;;
++	esac
++	;;
++      esac
++      ;;
++
++    newsos6)
++      lt_prog_compiler_pic='-KPIC'
++      lt_prog_compiler_static='-Bstatic'
++      ;;
++
++    *nto* | *qnx*)
++      # QNX uses GNU C++, but need to define -shared option too, otherwise
++      # it will coredump.
++      lt_prog_compiler_pic='-fPIC -shared'
++      ;;
++
++    osf3* | osf4* | osf5*)
++      lt_prog_compiler_wl='-Wl,'
++      # All OSF/1 code is PIC.
++      lt_prog_compiler_static='-non_shared'
++      ;;
++
++    rdos*)
++      lt_prog_compiler_static='-non_shared'
++      ;;
++
++    solaris*)
++      lt_prog_compiler_pic='-KPIC'
++      lt_prog_compiler_static='-Bstatic'
++      case $cc_basename in
++      f77* | f90* | f95*)
++	lt_prog_compiler_wl='-Qoption ld ';;
++      *)
++	lt_prog_compiler_wl='-Wl,';;
++      esac
++      ;;
++
++    sunos4*)
++      lt_prog_compiler_wl='-Qoption ld '
++      lt_prog_compiler_pic='-PIC'
++      lt_prog_compiler_static='-Bstatic'
++      ;;
++
++    sysv4 | sysv4.2uw2* | sysv4.3*)
++      lt_prog_compiler_wl='-Wl,'
++      lt_prog_compiler_pic='-KPIC'
++      lt_prog_compiler_static='-Bstatic'
++      ;;
++
++    sysv4*MP*)
++      if test -d /usr/nec ;then
++	lt_prog_compiler_pic='-Kconform_pic'
++	lt_prog_compiler_static='-Bstatic'
++      fi
++      ;;
++
++    sysv5* | unixware* | sco3.2v5* | sco5v6* | OpenUNIX*)
++      lt_prog_compiler_wl='-Wl,'
++      lt_prog_compiler_pic='-KPIC'
++      lt_prog_compiler_static='-Bstatic'
++      ;;
++
++    unicos*)
++      lt_prog_compiler_wl='-Wl,'
++      lt_prog_compiler_can_build_shared=no
++      ;;
++
++    uts4*)
++      lt_prog_compiler_pic='-pic'
++      lt_prog_compiler_static='-Bstatic'
++      ;;
++
++    *)
++      lt_prog_compiler_can_build_shared=no
++      ;;
++    esac
++  fi
++
++case $host_os in
++  # For platforms which do not support PIC, -DPIC is meaningless:
++  *djgpp*)
++    lt_prog_compiler_pic=
++    ;;
++  *)
++    lt_prog_compiler_pic="$lt_prog_compiler_pic -DPIC"
++    ;;
++esac
++{ $as_echo "$as_me:${as_lineno-$LINENO}: result: $lt_prog_compiler_pic" >&5
++$as_echo "$lt_prog_compiler_pic" >&6; }
++
++
++
++
++
++
++#
++# Check to make sure the PIC flag actually works.
++#
++if test -n "$lt_prog_compiler_pic"; then
++  { $as_echo "$as_me:${as_lineno-$LINENO}: checking if $compiler PIC flag $lt_prog_compiler_pic works" >&5
++$as_echo_n "checking if $compiler PIC flag $lt_prog_compiler_pic works... " >&6; }
++if ${lt_cv_prog_compiler_pic_works+:} false; then :
++  $as_echo_n "(cached) " >&6
++else
++  lt_cv_prog_compiler_pic_works=no
++   ac_outfile=conftest.$ac_objext
++   echo "$lt_simple_compile_test_code" > conftest.$ac_ext
++   lt_compiler_flag="$lt_prog_compiler_pic -DPIC"
++   # Insert the option either (1) after the last *FLAGS variable, or
++   # (2) before a word containing "conftest.", or (3) at the end.
++   # Note that $ac_compile itself does not contain backslashes and begins
++   # with a dollar sign (not a hyphen), so the echo should work correctly.
++   # The option is referenced via a variable to avoid confusing sed.
++   lt_compile=`echo "$ac_compile" | $SED \
++   -e 's:.*FLAGS}\{0,1\} :&$lt_compiler_flag :; t' \
++   -e 's: [^ ]*conftest\.: $lt_compiler_flag&:; t' \
++   -e 's:$: $lt_compiler_flag:'`
++   (eval echo "\"\$as_me:$LINENO: $lt_compile\"" >&5)
++   (eval "$lt_compile" 2>conftest.err)
++   ac_status=$?
++   cat conftest.err >&5
++   echo "$as_me:$LINENO: \$? = $ac_status" >&5
++   if (exit $ac_status) && test -s "$ac_outfile"; then
++     # The compiler can only warn and ignore the option if not recognized
++     # So say no if there are warnings other than the usual output.
++     $ECHO "$_lt_compiler_boilerplate" | $SED '/^$/d' >conftest.exp
++     $SED '/^$/d; /^ *+/d' conftest.err >conftest.er2
++     if test ! -s conftest.er2 || diff conftest.exp conftest.er2 >/dev/null; then
++       lt_cv_prog_compiler_pic_works=yes
++     fi
++   fi
++   $RM conftest*
++
++fi
++{ $as_echo "$as_me:${as_lineno-$LINENO}: result: $lt_cv_prog_compiler_pic_works" >&5
++$as_echo "$lt_cv_prog_compiler_pic_works" >&6; }
++
++if test x"$lt_cv_prog_compiler_pic_works" = xyes; then
++    case $lt_prog_compiler_pic in
++     "" | " "*) ;;
++     *) lt_prog_compiler_pic=" $lt_prog_compiler_pic" ;;
++     esac
++else
++    lt_prog_compiler_pic=
++     lt_prog_compiler_can_build_shared=no
++fi
++
++fi
++
++
++
++
++
++
++#
++# Check to make sure the static flag actually works.
++#
++wl=$lt_prog_compiler_wl eval lt_tmp_static_flag=\"$lt_prog_compiler_static\"
++{ $as_echo "$as_me:${as_lineno-$LINENO}: checking if $compiler static flag $lt_tmp_static_flag works" >&5
++$as_echo_n "checking if $compiler static flag $lt_tmp_static_flag works... " >&6; }
++if ${lt_cv_prog_compiler_static_works+:} false; then :
++  $as_echo_n "(cached) " >&6
++else
++  lt_cv_prog_compiler_static_works=no
++   save_LDFLAGS="$LDFLAGS"
++   LDFLAGS="$LDFLAGS $lt_tmp_static_flag"
++   echo "$lt_simple_link_test_code" > conftest.$ac_ext
++   if (eval $ac_link 2>conftest.err) && test -s conftest$ac_exeext; then
++     # The linker can only warn and ignore the option if not recognized
++     # So say no if there are warnings
++     if test -s conftest.err; then
++       # Append any errors to the config.log.
++       cat conftest.err 1>&5
++       $ECHO "$_lt_linker_boilerplate" | $SED '/^$/d' > conftest.exp
++       $SED '/^$/d; /^ *+/d' conftest.err >conftest.er2
++       if diff conftest.exp conftest.er2 >/dev/null; then
++         lt_cv_prog_compiler_static_works=yes
++       fi
++     else
++       lt_cv_prog_compiler_static_works=yes
++     fi
++   fi
++   $RM -r conftest*
++   LDFLAGS="$save_LDFLAGS"
++
++fi
++{ $as_echo "$as_me:${as_lineno-$LINENO}: result: $lt_cv_prog_compiler_static_works" >&5
++$as_echo "$lt_cv_prog_compiler_static_works" >&6; }
++
++if test x"$lt_cv_prog_compiler_static_works" = xyes; then
++    :
++else
++    lt_prog_compiler_static=
++fi
++
++
++
++
++
++
++
++  { $as_echo "$as_me:${as_lineno-$LINENO}: checking if $compiler supports -c -o file.$ac_objext" >&5
++$as_echo_n "checking if $compiler supports -c -o file.$ac_objext... " >&6; }
++if ${lt_cv_prog_compiler_c_o+:} false; then :
++  $as_echo_n "(cached) " >&6
++else
++  lt_cv_prog_compiler_c_o=no
++   $RM -r conftest 2>/dev/null
++   mkdir conftest
++   cd conftest
++   mkdir out
++   echo "$lt_simple_compile_test_code" > conftest.$ac_ext
++
++   lt_compiler_flag="-o out/conftest2.$ac_objext"
++   # Insert the option either (1) after the last *FLAGS variable, or
++   # (2) before a word containing "conftest.", or (3) at the end.
++   # Note that $ac_compile itself does not contain backslashes and begins
++   # with a dollar sign (not a hyphen), so the echo should work correctly.
++   lt_compile=`echo "$ac_compile" | $SED \
++   -e 's:.*FLAGS}\{0,1\} :&$lt_compiler_flag :; t' \
++   -e 's: [^ ]*conftest\.: $lt_compiler_flag&:; t' \
++   -e 's:$: $lt_compiler_flag:'`
++   (eval echo "\"\$as_me:$LINENO: $lt_compile\"" >&5)
++   (eval "$lt_compile" 2>out/conftest.err)
++   ac_status=$?
++   cat out/conftest.err >&5
++   echo "$as_me:$LINENO: \$? = $ac_status" >&5
++   if (exit $ac_status) && test -s out/conftest2.$ac_objext
++   then
++     # The compiler can only warn and ignore the option if not recognized
++     # So say no if there are warnings
++     $ECHO "$_lt_compiler_boilerplate" | $SED '/^$/d' > out/conftest.exp
++     $SED '/^$/d; /^ *+/d' out/conftest.err >out/conftest.er2
++     if test ! -s out/conftest.er2 || diff out/conftest.exp out/conftest.er2 >/dev/null; then
++       lt_cv_prog_compiler_c_o=yes
++     fi
++   fi
++   chmod u+w . 2>&5
++   $RM conftest*
++   # SGI C++ compiler will create directory out/ii_files/ for
++   # template instantiation
++   test -d out/ii_files && $RM out/ii_files/* && rmdir out/ii_files
++   $RM out/* && rmdir out
++   cd ..
++   $RM -r conftest
++   $RM conftest*
++
++fi
++{ $as_echo "$as_me:${as_lineno-$LINENO}: result: $lt_cv_prog_compiler_c_o" >&5
++$as_echo "$lt_cv_prog_compiler_c_o" >&6; }
++
++
++
++
++
++
++  { $as_echo "$as_me:${as_lineno-$LINENO}: checking if $compiler supports -c -o file.$ac_objext" >&5
++$as_echo_n "checking if $compiler supports -c -o file.$ac_objext... " >&6; }
++if ${lt_cv_prog_compiler_c_o+:} false; then :
++  $as_echo_n "(cached) " >&6
++else
++  lt_cv_prog_compiler_c_o=no
++   $RM -r conftest 2>/dev/null
++   mkdir conftest
++   cd conftest
++   mkdir out
++   echo "$lt_simple_compile_test_code" > conftest.$ac_ext
++
++   lt_compiler_flag="-o out/conftest2.$ac_objext"
++   # Insert the option either (1) after the last *FLAGS variable, or
++   # (2) before a word containing "conftest.", or (3) at the end.
++   # Note that $ac_compile itself does not contain backslashes and begins
++   # with a dollar sign (not a hyphen), so the echo should work correctly.
++   lt_compile=`echo "$ac_compile" | $SED \
++   -e 's:.*FLAGS}\{0,1\} :&$lt_compiler_flag :; t' \
++   -e 's: [^ ]*conftest\.: $lt_compiler_flag&:; t' \
++   -e 's:$: $lt_compiler_flag:'`
++   (eval echo "\"\$as_me:$LINENO: $lt_compile\"" >&5)
++   (eval "$lt_compile" 2>out/conftest.err)
++   ac_status=$?
++   cat out/conftest.err >&5
++   echo "$as_me:$LINENO: \$? = $ac_status" >&5
++   if (exit $ac_status) && test -s out/conftest2.$ac_objext
++   then
++     # The compiler can only warn and ignore the option if not recognized
++     # So say no if there are warnings
++     $ECHO "$_lt_compiler_boilerplate" | $SED '/^$/d' > out/conftest.exp
++     $SED '/^$/d; /^ *+/d' out/conftest.err >out/conftest.er2
++     if test ! -s out/conftest.er2 || diff out/conftest.exp out/conftest.er2 >/dev/null; then
++       lt_cv_prog_compiler_c_o=yes
++     fi
++   fi
++   chmod u+w . 2>&5
++   $RM conftest*
++   # SGI C++ compiler will create directory out/ii_files/ for
++   # template instantiation
++   test -d out/ii_files && $RM out/ii_files/* && rmdir out/ii_files
++   $RM out/* && rmdir out
++   cd ..
++   $RM -r conftest
++   $RM conftest*
++
++fi
++{ $as_echo "$as_me:${as_lineno-$LINENO}: result: $lt_cv_prog_compiler_c_o" >&5
++$as_echo "$lt_cv_prog_compiler_c_o" >&6; }
++
++
++
++
++hard_links="nottested"
++if test "$lt_cv_prog_compiler_c_o" = no && test "$need_locks" != no; then
++  # do not overwrite the value of need_locks provided by the user
++  { $as_echo "$as_me:${as_lineno-$LINENO}: checking if we can lock with hard links" >&5
++$as_echo_n "checking if we can lock with hard links... " >&6; }
++  hard_links=yes
++  $RM conftest*
++  ln conftest.a conftest.b 2>/dev/null && hard_links=no
++  touch conftest.a
++  ln conftest.a conftest.b 2>&5 || hard_links=no
++  ln conftest.a conftest.b 2>/dev/null && hard_links=no
++  { $as_echo "$as_me:${as_lineno-$LINENO}: result: $hard_links" >&5
++$as_echo "$hard_links" >&6; }
++  if test "$hard_links" = no; then
++    { $as_echo "$as_me:${as_lineno-$LINENO}: WARNING: \`$CC' does not support \`-c -o', so \`make -j' may be unsafe" >&5
++$as_echo "$as_me: WARNING: \`$CC' does not support \`-c -o', so \`make -j' may be unsafe" >&2;}
++    need_locks=warn
++  fi
++else
++  need_locks=no
++fi
++
++
++
++
++
++
++  { $as_echo "$as_me:${as_lineno-$LINENO}: checking whether the $compiler linker ($LD) supports shared libraries" >&5
++$as_echo_n "checking whether the $compiler linker ($LD) supports shared libraries... " >&6; }
++
++  runpath_var=
++  allow_undefined_flag=
++  always_export_symbols=no
++  archive_cmds=
++  archive_expsym_cmds=
++  compiler_needs_object=no
++  enable_shared_with_static_runtimes=no
++  export_dynamic_flag_spec=
++  export_symbols_cmds='$NM $libobjs $convenience | $global_symbol_pipe | $SED '\''s/.* //'\'' | sort | uniq > $export_symbols'
++  hardcode_automatic=no
++  hardcode_direct=no
++  hardcode_direct_absolute=no
++  hardcode_libdir_flag_spec=
++  hardcode_libdir_flag_spec_ld=
++  hardcode_libdir_separator=
++  hardcode_minus_L=no
++  hardcode_shlibpath_var=unsupported
++  inherit_rpath=no
++  link_all_deplibs=unknown
++  module_cmds=
++  module_expsym_cmds=
++  old_archive_from_new_cmds=
++  old_archive_from_expsyms_cmds=
++  thread_safe_flag_spec=
++  whole_archive_flag_spec=
++  # include_expsyms should be a list of space-separated symbols to be *always*
++  # included in the symbol list
++  include_expsyms=
++  # exclude_expsyms can be an extended regexp of symbols to exclude
++  # it will be wrapped by ` (' and `)$', so one must not match beginning or
++  # end of line.  Example: `a|bc|.*d.*' will exclude the symbols `a' and `bc',
++  # as well as any symbol that contains `d'.
++  exclude_expsyms='_GLOBAL_OFFSET_TABLE_|_GLOBAL__F[ID]_.*'
++  # Although _GLOBAL_OFFSET_TABLE_ is a valid symbol C name, most a.out
++  # platforms (ab)use it in PIC code, but their linkers get confused if
++  # the symbol is explicitly referenced.  Since portable code cannot
++  # rely on this symbol name, it's probably fine to never include it in
++  # preloaded symbol tables.
++  # Exclude shared library initialization/finalization symbols.
++  extract_expsyms_cmds=
++
++  case $host_os in
++  cygwin* | mingw* | pw32* | cegcc*)
++    # FIXME: the MSVC++ port hasn't been tested in a loooong time
++    # When not using gcc, we currently assume that we are using
++    # Microsoft Visual C++.
++    if test "$GCC" != yes; then
++      with_gnu_ld=no
++    fi
++    ;;
++  interix*)
++    # we just hope/assume this is gcc and not c89 (= MSVC++)
++    with_gnu_ld=yes
++    ;;
++  openbsd*)
++    with_gnu_ld=no
++    ;;
++  esac
++
++  ld_shlibs=yes
++
++  # On some targets, GNU ld is compatible enough with the native linker
++  # that we're better off using the native interface for both.
++  lt_use_gnu_ld_interface=no
++  if test "$with_gnu_ld" = yes; then
++    case $host_os in
++      aix*)
++	# The AIX port of GNU ld has always aspired to compatibility
++	# with the native linker.  However, as the warning in the GNU ld
++	# block says, versions before 2.19.5* couldn't really create working
++	# shared libraries, regardless of the interface used.
++	case `$LD -v 2>&1` in
++	  *\ \(GNU\ Binutils\)\ 2.19.5*) ;;
++	  *\ \(GNU\ Binutils\)\ 2.[2-9]*) ;;
++	  *\ \(GNU\ Binutils\)\ [3-9]*) ;;
++	  *)
++	    lt_use_gnu_ld_interface=yes
++	    ;;
++	esac
++	;;
++      *)
++	lt_use_gnu_ld_interface=yes
++	;;
++    esac
++  fi
++
++  if test "$lt_use_gnu_ld_interface" = yes; then
++    # If archive_cmds runs LD, not CC, wlarc should be empty
++    wlarc='${wl}'
++
++    # Set some defaults for GNU ld with shared library support. These
++    # are reset later if shared libraries are not supported. Putting them
++    # here allows them to be overridden if necessary.
++    runpath_var=LD_RUN_PATH
++    hardcode_libdir_flag_spec='${wl}-rpath ${wl}$libdir'
++    export_dynamic_flag_spec='${wl}--export-dynamic'
++    # ancient GNU ld didn't support --whole-archive et. al.
++    if $LD --help 2>&1 | $GREP 'no-whole-archive' > /dev/null; then
++      whole_archive_flag_spec="$wlarc"'--whole-archive$convenience '"$wlarc"'--no-whole-archive'
++    else
++      whole_archive_flag_spec=
++    fi
++    supports_anon_versioning=no
++    case `$LD -v 2>&1` in
++      *GNU\ gold*) supports_anon_versioning=yes ;;
++      *\ [01].* | *\ 2.[0-9].* | *\ 2.10.*) ;; # catch versions < 2.11
++      *\ 2.11.93.0.2\ *) supports_anon_versioning=yes ;; # RH7.3 ...
++      *\ 2.11.92.0.12\ *) supports_anon_versioning=yes ;; # Mandrake 8.2 ...
++      *\ 2.11.*) ;; # other 2.11 versions
++      *) supports_anon_versioning=yes ;;
++    esac
++
++    # See if GNU ld supports shared libraries.
++    case $host_os in
++    aix[3-9]*)
++      # On AIX/PPC, the GNU linker is very broken
++      if test "$host_cpu" != ia64; then
++	ld_shlibs=no
++	cat <<_LT_EOF 1>&2
++
++*** Warning: the GNU linker, at least up to release 2.19, is reported
++*** to be unable to reliably create shared libraries on AIX.
++*** Therefore, libtool is disabling shared libraries support.  If you
++*** really care for shared libraries, you may want to install binutils
++*** 2.20 or above, or modify your PATH so that a non-GNU linker is found.
++*** You will then need to restart the configuration process.
++
++_LT_EOF
++      fi
++      ;;
++
++    amigaos*)
++      case $host_cpu in
++      powerpc)
++            # see comment about AmigaOS4 .so support
++            archive_cmds='$CC -shared $libobjs $deplibs $compiler_flags ${wl}-soname $wl$soname -o $lib'
++            archive_expsym_cmds=''
++        ;;
++      m68k)
++            archive_cmds='$RM $output_objdir/a2ixlibrary.data~$ECHO "#define NAME $libname" > $output_objdir/a2ixlibrary.data~$ECHO "#define LIBRARY_ID 1" >> $output_objdir/a2ixlibrary.data~$ECHO "#define VERSION $major" >> $output_objdir/a2ixlibrary.data~$ECHO "#define REVISION $revision" >> $output_objdir/a2ixlibrary.data~$AR $AR_FLAGS $lib $libobjs~$RANLIB $lib~(cd $output_objdir && a2ixlibrary -32)'
++            hardcode_libdir_flag_spec='-L$libdir'
++            hardcode_minus_L=yes
++        ;;
++      esac
++      ;;
++
++    beos*)
++      if $LD --help 2>&1 | $GREP ': supported targets:.* elf' > /dev/null; then
++	allow_undefined_flag=unsupported
++	# Joseph Beckenbach <jrb3@best.com> says some releases of gcc
++	# support --undefined.  This deserves some investigation.  FIXME
++	archive_cmds='$CC -nostart $libobjs $deplibs $compiler_flags ${wl}-soname $wl$soname -o $lib'
++      else
++	ld_shlibs=no
++      fi
++      ;;
++
++    cygwin* | mingw* | pw32* | cegcc*)
++      # _LT_TAGVAR(hardcode_libdir_flag_spec, ) is actually meaningless,
++      # as there is no search path for DLLs.
++      hardcode_libdir_flag_spec='-L$libdir'
++      export_dynamic_flag_spec='${wl}--export-all-symbols'
++      allow_undefined_flag=unsupported
++      always_export_symbols=no
++      enable_shared_with_static_runtimes=yes
++      export_symbols_cmds='$NM $libobjs $convenience | $global_symbol_pipe | $SED -e '\''/^[BCDGRS][ ]/s/.*[ ]\([^ ]*\)/\1 DATA/'\'' | $SED -e '\''/^[AITW][ ]/s/.*[ ]//'\'' | sort | uniq > $export_symbols'
++
++      if $LD --help 2>&1 | $GREP 'auto-import' > /dev/null; then
++        archive_cmds='$CC -shared $libobjs $deplibs $compiler_flags -o $output_objdir/$soname ${wl}--enable-auto-image-base -Xlinker --out-implib -Xlinker $lib'
++	# If the export-symbols file already is a .def file (1st line
++	# is EXPORTS), use it as is; otherwise, prepend...
++	archive_expsym_cmds='if test "x`$SED 1q $export_symbols`" = xEXPORTS; then
++	  cp $export_symbols $output_objdir/$soname.def;
++	else
++	  echo EXPORTS > $output_objdir/$soname.def;
++	  cat $export_symbols >> $output_objdir/$soname.def;
++	fi~
++	$CC -shared $output_objdir/$soname.def $libobjs $deplibs $compiler_flags -o $output_objdir/$soname ${wl}--enable-auto-image-base -Xlinker --out-implib -Xlinker $lib'
++      else
++	ld_shlibs=no
++      fi
++      ;;
++
++    haiku*)
++      archive_cmds='$CC -shared $libobjs $deplibs $compiler_flags ${wl}-soname $wl$soname -o $lib'
++      link_all_deplibs=yes
++      ;;
++
++    interix[3-9]*)
++      hardcode_direct=no
++      hardcode_shlibpath_var=no
++      hardcode_libdir_flag_spec='${wl}-rpath,$libdir'
++      export_dynamic_flag_spec='${wl}-E'
++      # Hack: On Interix 3.x, we cannot compile PIC because of a broken gcc.
++      # Instead, shared libraries are loaded at an image base (0x10000000 by
++      # default) and relocated if they conflict, which is a slow very memory
++      # consuming and fragmenting process.  To avoid this, we pick a random,
++      # 256 KiB-aligned image base between 0x50000000 and 0x6FFC0000 at link
++      # time.  Moving up from 0x10000000 also allows more sbrk(2) space.
++      archive_cmds='$CC -shared $pic_flag $libobjs $deplibs $compiler_flags ${wl}-h,$soname ${wl}--image-base,`expr ${RANDOM-$$} % 4096 / 2 \* 262144 + 1342177280` -o $lib'
++      archive_expsym_cmds='sed "s,^,_," $export_symbols >$output_objdir/$soname.expsym~$CC -shared $pic_flag $libobjs $deplibs $compiler_flags ${wl}-h,$soname ${wl}--retain-symbols-file,$output_objdir/$soname.expsym ${wl}--image-base,`expr ${RANDOM-$$} % 4096 / 2 \* 262144 + 1342177280` -o $lib'
++      ;;
++
++    gnu* | linux* | tpf* | k*bsd*-gnu | kopensolaris*-gnu)
++      tmp_diet=no
++      if test "$host_os" = linux-dietlibc; then
++	case $cc_basename in
++	  diet\ *) tmp_diet=yes;;	# linux-dietlibc with static linking (!diet-dyn)
++	esac
++      fi
++      if $LD --help 2>&1 | $EGREP ': supported targets:.* elf' > /dev/null \
++	 && test "$tmp_diet" = no
++      then
++	tmp_addflag=' $pic_flag'
++	tmp_sharedflag='-shared'
++	case $cc_basename,$host_cpu in
++        pgcc*)				# Portland Group C compiler
++	  whole_archive_flag_spec='${wl}--whole-archive`for conv in $convenience\"\"; do test  -n \"$conv\" && new_convenience=\"$new_convenience,$conv\"; done; func_echo_all \"$new_convenience\"` ${wl}--no-whole-archive'
++	  tmp_addflag=' $pic_flag'
++	  ;;
++	pgf77* | pgf90* | pgf95* | pgfortran*)
++					# Portland Group f77 and f90 compilers
++	  whole_archive_flag_spec='${wl}--whole-archive`for conv in $convenience\"\"; do test  -n \"$conv\" && new_convenience=\"$new_convenience,$conv\"; done; func_echo_all \"$new_convenience\"` ${wl}--no-whole-archive'
++	  tmp_addflag=' $pic_flag -Mnomain' ;;
++	ecc*,ia64* | icc*,ia64*)	# Intel C compiler on ia64
++	  tmp_addflag=' -i_dynamic' ;;
++	efc*,ia64* | ifort*,ia64*)	# Intel Fortran compiler on ia64
++	  tmp_addflag=' -i_dynamic -nofor_main' ;;
++	ifc* | ifort*)			# Intel Fortran compiler
++	  tmp_addflag=' -nofor_main' ;;
++	lf95*)				# Lahey Fortran 8.1
++	  whole_archive_flag_spec=
++	  tmp_sharedflag='--shared' ;;
++	xl[cC]* | bgxl[cC]* | mpixl[cC]*) # IBM XL C 8.0 on PPC (deal with xlf below)
++	  tmp_sharedflag='-qmkshrobj'
++	  tmp_addflag= ;;
++	nvcc*)	# Cuda Compiler Driver 2.2
++	  whole_archive_flag_spec='${wl}--whole-archive`for conv in $convenience\"\"; do test  -n \"$conv\" && new_convenience=\"$new_convenience,$conv\"; done; func_echo_all \"$new_convenience\"` ${wl}--no-whole-archive'
++	  compiler_needs_object=yes
++	  ;;
++	esac
++	case `$CC -V 2>&1 | sed 5q` in
++	*Sun\ C*)			# Sun C 5.9
++	  whole_archive_flag_spec='${wl}--whole-archive`new_convenience=; for conv in $convenience\"\"; do test -z \"$conv\" || new_convenience=\"$new_convenience,$conv\"; done; func_echo_all \"$new_convenience\"` ${wl}--no-whole-archive'
++	  compiler_needs_object=yes
++	  tmp_sharedflag='-G' ;;
++	*Sun\ F*)			# Sun Fortran 8.3
++	  tmp_sharedflag='-G' ;;
++	esac
++	archive_cmds='$CC '"$tmp_sharedflag""$tmp_addflag"' $libobjs $deplibs $compiler_flags ${wl}-soname $wl$soname -o $lib'
++
++        if test "x$supports_anon_versioning" = xyes; then
++          archive_expsym_cmds='echo "{ global:" > $output_objdir/$libname.ver~
++	    cat $export_symbols | sed -e "s/\(.*\)/\1;/" >> $output_objdir/$libname.ver~
++	    echo "local: *; };" >> $output_objdir/$libname.ver~
++	    $CC '"$tmp_sharedflag""$tmp_addflag"' $libobjs $deplibs $compiler_flags ${wl}-soname $wl$soname ${wl}-version-script ${wl}$output_objdir/$libname.ver -o $lib'
++        fi
++
++	case $cc_basename in
++	xlf* | bgf* | bgxlf* | mpixlf*)
++	  # IBM XL Fortran 10.1 on PPC cannot create shared libs itself
++	  whole_archive_flag_spec='--whole-archive$convenience --no-whole-archive'
++	  hardcode_libdir_flag_spec=
++	  hardcode_libdir_flag_spec_ld='-rpath $libdir'
++	  archive_cmds='$LD -shared $libobjs $deplibs $compiler_flags -soname $soname -o $lib'
++	  if test "x$supports_anon_versioning" = xyes; then
++	    archive_expsym_cmds='echo "{ global:" > $output_objdir/$libname.ver~
++	      cat $export_symbols | sed -e "s/\(.*\)/\1;/" >> $output_objdir/$libname.ver~
++	      echo "local: *; };" >> $output_objdir/$libname.ver~
++	      $LD -shared $libobjs $deplibs $compiler_flags -soname $soname -version-script $output_objdir/$libname.ver -o $lib'
++	  fi
++	  ;;
++	esac
++      else
++        ld_shlibs=no
++      fi
++      ;;
++
++    netbsd*)
++      if echo __ELF__ | $CC -E - | $GREP __ELF__ >/dev/null; then
++	archive_cmds='$LD -Bshareable $libobjs $deplibs $linker_flags -o $lib'
++	wlarc=
++      else
++	archive_cmds='$CC -shared $libobjs $deplibs $compiler_flags ${wl}-soname $wl$soname -o $lib'
++	archive_expsym_cmds='$CC -shared $libobjs $deplibs $compiler_flags ${wl}-soname $wl$soname ${wl}-retain-symbols-file $wl$export_symbols -o $lib'
++      fi
++      ;;
++
++    solaris*)
++      if $LD -v 2>&1 | $GREP 'BFD 2\.8' > /dev/null; then
++	ld_shlibs=no
++	cat <<_LT_EOF 1>&2
++
++*** Warning: The releases 2.8.* of the GNU linker cannot reliably
++*** create shared libraries on Solaris systems.  Therefore, libtool
++*** is disabling shared libraries support.  We urge you to upgrade GNU
++*** binutils to release 2.9.1 or newer.  Another option is to modify
++*** your PATH or compiler configuration so that the native linker is
++*** used, and then restart.
++
++_LT_EOF
++      elif $LD --help 2>&1 | $GREP ': supported targets:.* elf' > /dev/null; then
++	archive_cmds='$CC -shared $libobjs $deplibs $compiler_flags ${wl}-soname $wl$soname -o $lib'
++	archive_expsym_cmds='$CC -shared $libobjs $deplibs $compiler_flags ${wl}-soname $wl$soname ${wl}-retain-symbols-file $wl$export_symbols -o $lib'
++      else
++	ld_shlibs=no
++      fi
++      ;;
++
++    sysv5* | sco3.2v5* | sco5v6* | unixware* | OpenUNIX*)
++      case `$LD -v 2>&1` in
++        *\ [01].* | *\ 2.[0-9].* | *\ 2.1[0-5].*)
++	ld_shlibs=no
++	cat <<_LT_EOF 1>&2
++
++*** Warning: Releases of the GNU linker prior to 2.16.91.0.3 can not
++*** reliably create shared libraries on SCO systems.  Therefore, libtool
++*** is disabling shared libraries support.  We urge you to upgrade GNU
++*** binutils to release 2.16.91.0.3 or newer.  Another option is to modify
++*** your PATH or compiler configuration so that the native linker is
++*** used, and then restart.
++
++_LT_EOF
++	;;
++	*)
++	  # For security reasons, it is highly recommended that you always
++	  # use absolute paths for naming shared libraries, and exclude the
++	  # DT_RUNPATH tag from executables and libraries.  But doing so
++	  # requires that you compile everything twice, which is a pain.
++	  if $LD --help 2>&1 | $GREP ': supported targets:.* elf' > /dev/null; then
++	    hardcode_libdir_flag_spec='${wl}-rpath ${wl}$libdir'
++	    archive_cmds='$CC -shared $libobjs $deplibs $compiler_flags ${wl}-soname $wl$soname -o $lib'
++	    archive_expsym_cmds='$CC -shared $libobjs $deplibs $compiler_flags ${wl}-soname $wl$soname ${wl}-retain-symbols-file $wl$export_symbols -o $lib'
++	  else
++	    ld_shlibs=no
++	  fi
++	;;
++      esac
++      ;;
++
++    sunos4*)
++      archive_cmds='$LD -assert pure-text -Bshareable -o $lib $libobjs $deplibs $linker_flags'
++      wlarc=
++      hardcode_direct=yes
++      hardcode_shlibpath_var=no
++      ;;
++
++    *)
++      if $LD --help 2>&1 | $GREP ': supported targets:.* elf' > /dev/null; then
++	archive_cmds='$CC -shared $libobjs $deplibs $compiler_flags ${wl}-soname $wl$soname -o $lib'
++	archive_expsym_cmds='$CC -shared $libobjs $deplibs $compiler_flags ${wl}-soname $wl$soname ${wl}-retain-symbols-file $wl$export_symbols -o $lib'
++      else
++	ld_shlibs=no
++      fi
++      ;;
++    esac
++
++    if test "$ld_shlibs" = no; then
++      runpath_var=
++      hardcode_libdir_flag_spec=
++      export_dynamic_flag_spec=
++      whole_archive_flag_spec=
++    fi
++  else
++    # PORTME fill in a description of your system's linker (not GNU ld)
++    case $host_os in
++    aix3*)
++      allow_undefined_flag=unsupported
++      always_export_symbols=yes
++      archive_expsym_cmds='$LD -o $output_objdir/$soname $libobjs $deplibs $linker_flags -bE:$export_symbols -T512 -H512 -bM:SRE~$AR $AR_FLAGS $lib $output_objdir/$soname'
++      # Note: this linker hardcodes the directories in LIBPATH if there
++      # are no directories specified by -L.
++      hardcode_minus_L=yes
++      if test "$GCC" = yes && test -z "$lt_prog_compiler_static"; then
++	# Neither direct hardcoding nor static linking is supported with a
++	# broken collect2.
++	hardcode_direct=unsupported
++      fi
++      ;;
++
++    aix[4-9]*)
++      if test "$host_cpu" = ia64; then
++	# On IA64, the linker does run time linking by default, so we don't
++	# have to do anything special.
++	aix_use_runtimelinking=no
++	exp_sym_flag='-Bexport'
++	no_entry_flag=""
++      else
++	# If we're using GNU nm, then we don't want the "-C" option.
++	# -C means demangle to AIX nm, but means don't demangle with GNU nm
++	# Also, AIX nm treats weak defined symbols like other global
++	# defined symbols, whereas GNU nm marks them as "W".
++	if $NM -V 2>&1 | $GREP 'GNU' > /dev/null; then
++	  export_symbols_cmds='$NM -Bpg $libobjs $convenience | awk '\''{ if (((\$ 2 == "T") || (\$ 2 == "D") || (\$ 2 == "B") || (\$ 2 == "W")) && (substr(\$ 3,1,1) != ".")) { print \$ 3 } }'\'' | sort -u > $export_symbols'
++	else
++	  export_symbols_cmds='$NM -BCpg $libobjs $convenience | awk '\''{ if (((\$ 2 == "T") || (\$ 2 == "D") || (\$ 2 == "B") || (\$ 2 == "L")) && (substr(\$ 3,1,1) != ".")) { print \$ 3 } }'\'' | sort -u > $export_symbols'
++	fi
++	aix_use_runtimelinking=no
++
++	# Test if we are trying to use run time linking or normal
++	# AIX style linking. If -brtl is somewhere in LDFLAGS, we
++	# need to do runtime linking.
++	case $host_os in aix4.[23]|aix4.[23].*|aix[5-9]*)
++	  for ld_flag in $LDFLAGS; do
++	  if (test $ld_flag = "-brtl" || test $ld_flag = "-Wl,-brtl"); then
++	    aix_use_runtimelinking=yes
++	    break
++	  fi
++	  done
++	  ;;
++	esac
++
++	exp_sym_flag='-bexport'
++	no_entry_flag='-bnoentry'
++      fi
++
++      # When large executables or shared objects are built, AIX ld can
++      # have problems creating the table of contents.  If linking a library
++      # or program results in "error TOC overflow" add -mminimal-toc to
++      # CXXFLAGS/CFLAGS for g++/gcc.  In the cases where that is not
++      # enough to fix the problem, add -Wl,-bbigtoc to LDFLAGS.
++
++      archive_cmds=''
++      hardcode_direct=yes
++      hardcode_direct_absolute=yes
++      hardcode_libdir_separator=':'
++      link_all_deplibs=yes
++      file_list_spec='${wl}-f,'
++
++      if test "$GCC" = yes; then
++	case $host_os in aix4.[012]|aix4.[012].*)
++	# We only want to do this on AIX 4.2 and lower, the check
++	# below for broken collect2 doesn't work under 4.3+
++	  collect2name=`${CC} -print-prog-name=collect2`
++	  if test -f "$collect2name" &&
++	   strings "$collect2name" | $GREP resolve_lib_name >/dev/null
++	  then
++	  # We have reworked collect2
++	  :
++	  else
++	  # We have old collect2
++	  hardcode_direct=unsupported
++	  # It fails to find uninstalled libraries when the uninstalled
++	  # path is not listed in the libpath.  Setting hardcode_minus_L
++	  # to unsupported forces relinking
++	  hardcode_minus_L=yes
++	  hardcode_libdir_flag_spec='-L$libdir'
++	  hardcode_libdir_separator=
++	  fi
++	  ;;
++	esac
++	shared_flag='-shared'
++	if test "$aix_use_runtimelinking" = yes; then
++	  shared_flag="$shared_flag "'${wl}-G'
++	fi
++      else
++	# not using gcc
++	if test "$host_cpu" = ia64; then
++	# VisualAge C++, Version 5.5 for AIX 5L for IA-64, Beta 3 Release
++	# chokes on -Wl,-G. The following line is correct:
++	  shared_flag='-G'
++	else
++	  if test "$aix_use_runtimelinking" = yes; then
++	    shared_flag='${wl}-G'
++	  else
++	    shared_flag='${wl}-bM:SRE'
++	  fi
++	fi
++      fi
++
++      export_dynamic_flag_spec='${wl}-bexpall'
++      # It seems that -bexpall does not export symbols beginning with
++      # underscore (_), so it is better to generate a list of symbols to export.
++      always_export_symbols=yes
++      if test "$aix_use_runtimelinking" = yes; then
++	# Warning - without using the other runtime loading flags (-brtl),
++	# -berok will link without error, but may produce a broken library.
++	allow_undefined_flag='-berok'
++        # Determine the default libpath from the value encoded in an
++        # empty executable.
++        cat confdefs.h - <<_ACEOF >conftest.$ac_ext
++/* end confdefs.h.  */
++
++int
++main ()
++{
++
++  ;
++  return 0;
++}
++_ACEOF
++if ac_fn_c_try_link "$LINENO"; then :
++
++lt_aix_libpath_sed='
++    /Import File Strings/,/^$/ {
++	/^0/ {
++	    s/^0  *\(.*\)$/\1/
++	    p
++	}
++    }'
++aix_libpath=`dump -H conftest$ac_exeext 2>/dev/null | $SED -n -e "$lt_aix_libpath_sed"`
++# Check for a 64-bit object if we didn't find anything.
++if test -z "$aix_libpath"; then
++  aix_libpath=`dump -HX64 conftest$ac_exeext 2>/dev/null | $SED -n -e "$lt_aix_libpath_sed"`
++fi
++fi
++rm -f core conftest.err conftest.$ac_objext \
++    conftest$ac_exeext conftest.$ac_ext
++if test -z "$aix_libpath"; then aix_libpath="/usr/lib:/lib"; fi
++
++        hardcode_libdir_flag_spec='${wl}-blibpath:$libdir:'"$aix_libpath"
++        archive_expsym_cmds='$CC -o $output_objdir/$soname $libobjs $deplibs '"\${wl}$no_entry_flag"' $compiler_flags `if test "x${allow_undefined_flag}" != "x"; then func_echo_all "${wl}${allow_undefined_flag}"; else :; fi` '"\${wl}$exp_sym_flag:\$export_symbols $shared_flag"
++      else
++	if test "$host_cpu" = ia64; then
++	  hardcode_libdir_flag_spec='${wl}-R $libdir:/usr/lib:/lib'
++	  allow_undefined_flag="-z nodefs"
++	  archive_expsym_cmds="\$CC $shared_flag"' -o $output_objdir/$soname $libobjs $deplibs '"\${wl}$no_entry_flag"' $compiler_flags ${wl}${allow_undefined_flag} '"\${wl}$exp_sym_flag:\$export_symbols"
++	else
++	 # Determine the default libpath from the value encoded in an
++	 # empty executable.
++	 cat confdefs.h - <<_ACEOF >conftest.$ac_ext
++/* end confdefs.h.  */
++
++int
++main ()
++{
++
++  ;
++  return 0;
++}
++_ACEOF
++if ac_fn_c_try_link "$LINENO"; then :
++
++lt_aix_libpath_sed='
++    /Import File Strings/,/^$/ {
++	/^0/ {
++	    s/^0  *\(.*\)$/\1/
++	    p
++	}
++    }'
++aix_libpath=`dump -H conftest$ac_exeext 2>/dev/null | $SED -n -e "$lt_aix_libpath_sed"`
++# Check for a 64-bit object if we didn't find anything.
++if test -z "$aix_libpath"; then
++  aix_libpath=`dump -HX64 conftest$ac_exeext 2>/dev/null | $SED -n -e "$lt_aix_libpath_sed"`
++fi
++fi
++rm -f core conftest.err conftest.$ac_objext \
++    conftest$ac_exeext conftest.$ac_ext
++if test -z "$aix_libpath"; then aix_libpath="/usr/lib:/lib"; fi
++
++	 hardcode_libdir_flag_spec='${wl}-blibpath:$libdir:'"$aix_libpath"
++	  # Warning - without using the other run time loading flags,
++	  # -berok will link without error, but may produce a broken library.
++	  no_undefined_flag=' ${wl}-bernotok'
++	  allow_undefined_flag=' ${wl}-berok'
++	  if test "$with_gnu_ld" = yes; then
++	    # We only use this code for GNU lds that support --whole-archive.
++	    whole_archive_flag_spec='${wl}--whole-archive$convenience ${wl}--no-whole-archive'
++	  else
++	    # Exported symbols can be pulled into shared objects from archives
++	    whole_archive_flag_spec='$convenience'
++	  fi
++	  archive_cmds_need_lc=yes
++	  # This is similar to how AIX traditionally builds its shared libraries.
++	  archive_expsym_cmds="\$CC $shared_flag"' -o $output_objdir/$soname $libobjs $deplibs ${wl}-bnoentry $compiler_flags ${wl}-bE:$export_symbols${allow_undefined_flag}~$AR $AR_FLAGS $output_objdir/$libname$release.a $output_objdir/$soname'
++	fi
++      fi
++      ;;
++
++    amigaos*)
++      case $host_cpu in
++      powerpc)
++            # see comment about AmigaOS4 .so support
++            archive_cmds='$CC -shared $libobjs $deplibs $compiler_flags ${wl}-soname $wl$soname -o $lib'
++            archive_expsym_cmds=''
++        ;;
++      m68k)
++            archive_cmds='$RM $output_objdir/a2ixlibrary.data~$ECHO "#define NAME $libname" > $output_objdir/a2ixlibrary.data~$ECHO "#define LIBRARY_ID 1" >> $output_objdir/a2ixlibrary.data~$ECHO "#define VERSION $major" >> $output_objdir/a2ixlibrary.data~$ECHO "#define REVISION $revision" >> $output_objdir/a2ixlibrary.data~$AR $AR_FLAGS $lib $libobjs~$RANLIB $lib~(cd $output_objdir && a2ixlibrary -32)'
++            hardcode_libdir_flag_spec='-L$libdir'
++            hardcode_minus_L=yes
++        ;;
++      esac
++      ;;
++
++    bsdi[45]*)
++      export_dynamic_flag_spec=-rdynamic
++      ;;
++
++    cygwin* | mingw* | pw32* | cegcc*)
++      # When not using gcc, we currently assume that we are using
++      # Microsoft Visual C++.
++      # hardcode_libdir_flag_spec is actually meaningless, as there is
++      # no search path for DLLs.
++      hardcode_libdir_flag_spec=' '
++      allow_undefined_flag=unsupported
++      # Tell ltmain to make .lib files, not .a files.
++      libext=lib
++      # Tell ltmain to make .dll files, not .so files.
++      shrext_cmds=".dll"
++      # FIXME: Setting linknames here is a bad hack.
++      archive_cmds='$CC -o $lib $libobjs $compiler_flags `func_echo_all "$deplibs" | $SED '\''s/ -lc$//'\''` -link -dll~linknames='
++      # The linker will automatically build a .lib file if we build a DLL.
++      old_archive_from_new_cmds='true'
++      # FIXME: Should let the user specify the lib program.
++      old_archive_cmds='lib -OUT:$oldlib$oldobjs$old_deplibs'
++      fix_srcfile_path='`cygpath -w "$srcfile"`'
++      enable_shared_with_static_runtimes=yes
++      ;;
++
++    darwin* | rhapsody*)
++
++
++  archive_cmds_need_lc=no
++  hardcode_direct=no
++  hardcode_automatic=yes
++  hardcode_shlibpath_var=unsupported
++  if test "$lt_cv_ld_force_load" = "yes"; then
++    whole_archive_flag_spec='`for conv in $convenience\"\"; do test  -n \"$conv\" && new_convenience=\"$new_convenience ${wl}-force_load,$conv\"; done; func_echo_all \"$new_convenience\"`'
++  else
++    whole_archive_flag_spec=''
++  fi
++  link_all_deplibs=yes
++  allow_undefined_flag="$_lt_dar_allow_undefined"
++  case $cc_basename in
++     ifort*) _lt_dar_can_shared=yes ;;
++     *) _lt_dar_can_shared=$GCC ;;
++  esac
++  if test "$_lt_dar_can_shared" = "yes"; then
++    output_verbose_link_cmd=func_echo_all
++    archive_cmds="\$CC -dynamiclib \$allow_undefined_flag -o \$lib \$libobjs \$deplibs \$compiler_flags -install_name \$rpath/\$soname \$verstring $_lt_dar_single_mod${_lt_dsymutil}"
++    module_cmds="\$CC \$allow_undefined_flag -o \$lib -bundle \$libobjs \$deplibs \$compiler_flags${_lt_dsymutil}"
++    archive_expsym_cmds="sed 's,^,_,' < \$export_symbols > \$output_objdir/\${libname}-symbols.expsym~\$CC -dynamiclib \$allow_undefined_flag -o \$lib \$libobjs \$deplibs \$compiler_flags -install_name \$rpath/\$soname \$verstring ${_lt_dar_single_mod}${_lt_dar_export_syms}${_lt_dsymutil}"
++    module_expsym_cmds="sed -e 's,^,_,' < \$export_symbols > \$output_objdir/\${libname}-symbols.expsym~\$CC \$allow_undefined_flag -o \$lib -bundle \$libobjs \$deplibs \$compiler_flags${_lt_dar_export_syms}${_lt_dsymutil}"
++
++  else
++  ld_shlibs=no
++  fi
++
++      ;;
++
++    dgux*)
++      archive_cmds='$LD -G -h $soname -o $lib $libobjs $deplibs $linker_flags'
++      hardcode_libdir_flag_spec='-L$libdir'
++      hardcode_shlibpath_var=no
++      ;;
++
++    # FreeBSD 2.2.[012] allows us to include c++rt0.o to get C++ constructor
++    # support.  Future versions do this automatically, but an explicit c++rt0.o
++    # does not break anything, and helps significantly (at the cost of a little
++    # extra space).
++    freebsd2.2*)
++      archive_cmds='$LD -Bshareable -o $lib $libobjs $deplibs $linker_flags /usr/lib/c++rt0.o'
++      hardcode_libdir_flag_spec='-R$libdir'
++      hardcode_direct=yes
++      hardcode_shlibpath_var=no
++      ;;
++
++    # Unfortunately, older versions of FreeBSD 2 do not have this feature.
++    freebsd2.*)
++      archive_cmds='$LD -Bshareable -o $lib $libobjs $deplibs $linker_flags'
++      hardcode_direct=yes
++      hardcode_minus_L=yes
++      hardcode_shlibpath_var=no
++      ;;
++
++    # FreeBSD 3 and greater uses gcc -shared to do shared libraries.
++    freebsd* | dragonfly*)
++      archive_cmds='$CC -shared -o $lib $libobjs $deplibs $compiler_flags'
++      hardcode_libdir_flag_spec='-R$libdir'
++      hardcode_direct=yes
++      hardcode_shlibpath_var=no
++      ;;
++
++    hpux9*)
++      if test "$GCC" = yes; then
++	archive_cmds='$RM $output_objdir/$soname~$CC -shared -fPIC ${wl}+b ${wl}$install_libdir -o $output_objdir/$soname $libobjs $deplibs $compiler_flags~test $output_objdir/$soname = $lib || mv $output_objdir/$soname $lib'
++      else
++	archive_cmds='$RM $output_objdir/$soname~$LD -b +b $install_libdir -o $output_objdir/$soname $libobjs $deplibs $linker_flags~test $output_objdir/$soname = $lib || mv $output_objdir/$soname $lib'
++      fi
++      hardcode_libdir_flag_spec='${wl}+b ${wl}$libdir'
++      hardcode_libdir_separator=:
++      hardcode_direct=yes
++
++      # hardcode_minus_L: Not really in the search PATH,
++      # but as the default location of the library.
++      hardcode_minus_L=yes
++      export_dynamic_flag_spec='${wl}-E'
++      ;;
++
++    hpux10*)
++      if test "$GCC" = yes && test "$with_gnu_ld" = no; then
++	archive_cmds='$CC -shared -fPIC ${wl}+h ${wl}$soname ${wl}+b ${wl}$install_libdir -o $lib $libobjs $deplibs $compiler_flags'
++      else
++	archive_cmds='$LD -b +h $soname +b $install_libdir -o $lib $libobjs $deplibs $linker_flags'
++      fi
++      if test "$with_gnu_ld" = no; then
++	hardcode_libdir_flag_spec='${wl}+b ${wl}$libdir'
++	hardcode_libdir_flag_spec_ld='+b $libdir'
++	hardcode_libdir_separator=:
++	hardcode_direct=yes
++	hardcode_direct_absolute=yes
++	export_dynamic_flag_spec='${wl}-E'
++	# hardcode_minus_L: Not really in the search PATH,
++	# but as the default location of the library.
++	hardcode_minus_L=yes
++      fi
++      ;;
++
++    hpux11*)
++      if test "$GCC" = yes && test "$with_gnu_ld" = no; then
++	case $host_cpu in
++	hppa*64*)
++	  archive_cmds='$CC -shared ${wl}+h ${wl}$soname -o $lib $libobjs $deplibs $compiler_flags'
++	  ;;
++	ia64*)
++	  archive_cmds='$CC -shared -fPIC ${wl}+h ${wl}$soname ${wl}+nodefaultrpath -o $lib $libobjs $deplibs $compiler_flags'
++	  ;;
++	*)
++	  archive_cmds='$CC -shared -fPIC ${wl}+h ${wl}$soname ${wl}+b ${wl}$install_libdir -o $lib $libobjs $deplibs $compiler_flags'
++	  ;;
++	esac
++      else
++	case $host_cpu in
++	hppa*64*)
++	  archive_cmds='$CC -b ${wl}+h ${wl}$soname -o $lib $libobjs $deplibs $compiler_flags'
++	  ;;
++	ia64*)
++	  archive_cmds='$CC -b ${wl}+h ${wl}$soname ${wl}+nodefaultrpath -o $lib $libobjs $deplibs $compiler_flags'
++	  ;;
++	*)
++
++	  # Older versions of the 11.00 compiler do not understand -b yet
++	  # (HP92453-01 A.11.01.20 doesn't, HP92453-01 B.11.X.35175-35176.GP does)
++	  { $as_echo "$as_me:${as_lineno-$LINENO}: checking if $CC understands -b" >&5
++$as_echo_n "checking if $CC understands -b... " >&6; }
++if ${lt_cv_prog_compiler__b+:} false; then :
++  $as_echo_n "(cached) " >&6
++else
++  lt_cv_prog_compiler__b=no
++   save_LDFLAGS="$LDFLAGS"
++   LDFLAGS="$LDFLAGS -b"
++   echo "$lt_simple_link_test_code" > conftest.$ac_ext
++   if (eval $ac_link 2>conftest.err) && test -s conftest$ac_exeext; then
++     # The linker can only warn and ignore the option if not recognized
++     # So say no if there are warnings
++     if test -s conftest.err; then
++       # Append any errors to the config.log.
++       cat conftest.err 1>&5
++       $ECHO "$_lt_linker_boilerplate" | $SED '/^$/d' > conftest.exp
++       $SED '/^$/d; /^ *+/d' conftest.err >conftest.er2
++       if diff conftest.exp conftest.er2 >/dev/null; then
++         lt_cv_prog_compiler__b=yes
++       fi
++     else
++       lt_cv_prog_compiler__b=yes
++     fi
++   fi
++   $RM -r conftest*
++   LDFLAGS="$save_LDFLAGS"
++
++fi
++{ $as_echo "$as_me:${as_lineno-$LINENO}: result: $lt_cv_prog_compiler__b" >&5
++$as_echo "$lt_cv_prog_compiler__b" >&6; }
++
++if test x"$lt_cv_prog_compiler__b" = xyes; then
++    archive_cmds='$CC -b ${wl}+h ${wl}$soname ${wl}+b ${wl}$install_libdir -o $lib $libobjs $deplibs $compiler_flags'
++else
++    archive_cmds='$LD -b +h $soname +b $install_libdir -o $lib $libobjs $deplibs $linker_flags'
++fi
++
++	  ;;
++	esac
++      fi
++      if test "$with_gnu_ld" = no; then
++	hardcode_libdir_flag_spec='${wl}+b ${wl}$libdir'
++	hardcode_libdir_separator=:
++
++	case $host_cpu in
++	hppa*64*|ia64*)
++	  hardcode_direct=no
++	  hardcode_shlibpath_var=no
++	  ;;
++	*)
++	  hardcode_direct=yes
++	  hardcode_direct_absolute=yes
++	  export_dynamic_flag_spec='${wl}-E'
++
++	  # hardcode_minus_L: Not really in the search PATH,
++	  # but as the default location of the library.
++	  hardcode_minus_L=yes
++	  ;;
++	esac
++      fi
++      ;;
++
++    irix5* | irix6* | nonstopux*)
++      if test "$GCC" = yes; then
++	archive_cmds='$CC -shared $libobjs $deplibs $compiler_flags ${wl}-soname ${wl}$soname `test -n "$verstring" && func_echo_all "${wl}-set_version ${wl}$verstring"` ${wl}-update_registry ${wl}${output_objdir}/so_locations -o $lib'
++	# Try to use the -exported_symbol ld option, if it does not
++	# work, assume that -exports_file does not work either and
++	# implicitly export all symbols.
++        save_LDFLAGS="$LDFLAGS"
++        LDFLAGS="$LDFLAGS -shared ${wl}-exported_symbol ${wl}foo ${wl}-update_registry ${wl}/dev/null"
++        cat confdefs.h - <<_ACEOF >conftest.$ac_ext
++/* end confdefs.h.  */
++int foo(void) {}
++_ACEOF
++if ac_fn_c_try_link "$LINENO"; then :
++  archive_expsym_cmds='$CC -shared $libobjs $deplibs $compiler_flags ${wl}-soname ${wl}$soname `test -n "$verstring" && func_echo_all "${wl}-set_version ${wl}$verstring"` ${wl}-update_registry ${wl}${output_objdir}/so_locations ${wl}-exports_file ${wl}$export_symbols -o $lib'
++
++fi
++rm -f core conftest.err conftest.$ac_objext \
++    conftest$ac_exeext conftest.$ac_ext
++        LDFLAGS="$save_LDFLAGS"
++      else
++	archive_cmds='$CC -shared $libobjs $deplibs $compiler_flags -soname $soname `test -n "$verstring" && func_echo_all "-set_version $verstring"` -update_registry ${output_objdir}/so_locations -o $lib'
++	archive_expsym_cmds='$CC -shared $libobjs $deplibs $compiler_flags -soname $soname `test -n "$verstring" && func_echo_all "-set_version $verstring"` -update_registry ${output_objdir}/so_locations -exports_file $export_symbols -o $lib'
++      fi
++      archive_cmds_need_lc='no'
++      hardcode_libdir_flag_spec='${wl}-rpath ${wl}$libdir'
++      hardcode_libdir_separator=:
++      inherit_rpath=yes
++      link_all_deplibs=yes
++      ;;
++
++    netbsd*)
++      if echo __ELF__ | $CC -E - | $GREP __ELF__ >/dev/null; then
++	archive_cmds='$LD -Bshareable -o $lib $libobjs $deplibs $linker_flags'  # a.out
++      else
++	archive_cmds='$LD -shared -o $lib $libobjs $deplibs $linker_flags'      # ELF
++      fi
++      hardcode_libdir_flag_spec='-R$libdir'
++      hardcode_direct=yes
++      hardcode_shlibpath_var=no
++      ;;
++
++    newsos6)
++      archive_cmds='$LD -G -h $soname -o $lib $libobjs $deplibs $linker_flags'
++      hardcode_direct=yes
++      hardcode_libdir_flag_spec='${wl}-rpath ${wl}$libdir'
++      hardcode_libdir_separator=:
++      hardcode_shlibpath_var=no
++      ;;
++
++    *nto* | *qnx*)
++      ;;
++
++    openbsd*)
++      if test -f /usr/libexec/ld.so; then
++	hardcode_direct=yes
++	hardcode_shlibpath_var=no
++	hardcode_direct_absolute=yes
++	if test -z "`echo __ELF__ | $CC -E - | $GREP __ELF__`" || test "$host_os-$host_cpu" = "openbsd2.8-powerpc"; then
++	  archive_cmds='$CC -shared $pic_flag -o $lib $libobjs $deplibs $compiler_flags'
++	  archive_expsym_cmds='$CC -shared $pic_flag -o $lib $libobjs $deplibs $compiler_flags ${wl}-retain-symbols-file,$export_symbols'
++	  hardcode_libdir_flag_spec='${wl}-rpath,$libdir'
++	  export_dynamic_flag_spec='${wl}-E'
++	else
++	  case $host_os in
++	   openbsd[01].* | openbsd2.[0-7] | openbsd2.[0-7].*)
++	     archive_cmds='$LD -Bshareable -o $lib $libobjs $deplibs $linker_flags'
++	     hardcode_libdir_flag_spec='-R$libdir'
++	     ;;
++	   *)
++	     archive_cmds='$CC -shared $pic_flag -o $lib $libobjs $deplibs $compiler_flags'
++	     hardcode_libdir_flag_spec='${wl}-rpath,$libdir'
++	     ;;
++	  esac
++	fi
++      else
++	ld_shlibs=no
++      fi
++      ;;
++
++    os2*)
++      hardcode_libdir_flag_spec='-L$libdir'
++      hardcode_minus_L=yes
++      allow_undefined_flag=unsupported
++      archive_cmds='$ECHO "LIBRARY $libname INITINSTANCE" > $output_objdir/$libname.def~$ECHO "DESCRIPTION \"$libname\"" >> $output_objdir/$libname.def~echo DATA >> $output_objdir/$libname.def~echo " SINGLE NONSHARED" >> $output_objdir/$libname.def~echo EXPORTS >> $output_objdir/$libname.def~emxexp $libobjs >> $output_objdir/$libname.def~$CC -Zdll -Zcrtdll -o $lib $libobjs $deplibs $compiler_flags $output_objdir/$libname.def'
++      old_archive_from_new_cmds='emximp -o $output_objdir/$libname.a $output_objdir/$libname.def'
++      ;;
++
++    osf3*)
++      if test "$GCC" = yes; then
++	allow_undefined_flag=' ${wl}-expect_unresolved ${wl}\*'
++	archive_cmds='$CC -shared${allow_undefined_flag} $libobjs $deplibs $compiler_flags ${wl}-soname ${wl}$soname `test -n "$verstring" && func_echo_all "${wl}-set_version ${wl}$verstring"` ${wl}-update_registry ${wl}${output_objdir}/so_locations -o $lib'
++      else
++	allow_undefined_flag=' -expect_unresolved \*'
++	archive_cmds='$CC -shared${allow_undefined_flag} $libobjs $deplibs $compiler_flags -soname $soname `test -n "$verstring" && func_echo_all "-set_version $verstring"` -update_registry ${output_objdir}/so_locations -o $lib'
++      fi
++      archive_cmds_need_lc='no'
++      hardcode_libdir_flag_spec='${wl}-rpath ${wl}$libdir'
++      hardcode_libdir_separator=:
++      ;;
++
++    osf4* | osf5*)	# as osf3* with the addition of -msym flag
++      if test "$GCC" = yes; then
++	allow_undefined_flag=' ${wl}-expect_unresolved ${wl}\*'
++	archive_cmds='$CC -shared${allow_undefined_flag} $libobjs $deplibs $compiler_flags ${wl}-msym ${wl}-soname ${wl}$soname `test -n "$verstring" && func_echo_all "${wl}-set_version ${wl}$verstring"` ${wl}-update_registry ${wl}${output_objdir}/so_locations -o $lib'
++	hardcode_libdir_flag_spec='${wl}-rpath ${wl}$libdir'
++      else
++	allow_undefined_flag=' -expect_unresolved \*'
++	archive_cmds='$CC -shared${allow_undefined_flag} $libobjs $deplibs $compiler_flags -msym -soname $soname `test -n "$verstring" && func_echo_all "-set_version $verstring"` -update_registry ${output_objdir}/so_locations -o $lib'
++	archive_expsym_cmds='for i in `cat $export_symbols`; do printf "%s %s\\n" -exported_symbol "\$i" >> $lib.exp; done; printf "%s\\n" "-hidden">> $lib.exp~
++	$CC -shared${allow_undefined_flag} ${wl}-input ${wl}$lib.exp $compiler_flags $libobjs $deplibs -soname $soname `test -n "$verstring" && $ECHO "-set_version $verstring"` -update_registry ${output_objdir}/so_locations -o $lib~$RM $lib.exp'
++
++	# Both c and cxx compiler support -rpath directly
++	hardcode_libdir_flag_spec='-rpath $libdir'
++      fi
++      archive_cmds_need_lc='no'
++      hardcode_libdir_separator=:
++      ;;
++
++    solaris*)
++      no_undefined_flag=' -z defs'
++      if test "$GCC" = yes; then
++	wlarc='${wl}'
++	archive_cmds='$CC -shared ${wl}-z ${wl}text ${wl}-h ${wl}$soname -o $lib $libobjs $deplibs $compiler_flags'
++	archive_expsym_cmds='echo "{ global:" > $lib.exp~cat $export_symbols | $SED -e "s/\(.*\)/\1;/" >> $lib.exp~echo "local: *; };" >> $lib.exp~
++	  $CC -shared ${wl}-z ${wl}text ${wl}-M ${wl}$lib.exp ${wl}-h ${wl}$soname -o $lib $libobjs $deplibs $compiler_flags~$RM $lib.exp'
++      else
++	case `$CC -V 2>&1` in
++	*"Compilers 5.0"*)
++	  wlarc=''
++	  archive_cmds='$LD -G${allow_undefined_flag} -h $soname -o $lib $libobjs $deplibs $linker_flags'
++	  archive_expsym_cmds='echo "{ global:" > $lib.exp~cat $export_symbols | $SED -e "s/\(.*\)/\1;/" >> $lib.exp~echo "local: *; };" >> $lib.exp~
++	  $LD -G${allow_undefined_flag} -M $lib.exp -h $soname -o $lib $libobjs $deplibs $linker_flags~$RM $lib.exp'
++	  ;;
++	*)
++	  wlarc='${wl}'
++	  archive_cmds='$CC -G${allow_undefined_flag} -h $soname -o $lib $libobjs $deplibs $compiler_flags'
++	  archive_expsym_cmds='echo "{ global:" > $lib.exp~cat $export_symbols | $SED -e "s/\(.*\)/\1;/" >> $lib.exp~echo "local: *; };" >> $lib.exp~
++	  $CC -G${allow_undefined_flag} -M $lib.exp -h $soname -o $lib $libobjs $deplibs $compiler_flags~$RM $lib.exp'
++	  ;;
++	esac
++      fi
++      hardcode_libdir_flag_spec='-R$libdir'
++      hardcode_shlibpath_var=no
++      case $host_os in
++      solaris2.[0-5] | solaris2.[0-5].*) ;;
++      *)
++	# The compiler driver will combine and reorder linker options,
++	# but understands `-z linker_flag'.  GCC discards it without `$wl',
++	# but is careful enough not to reorder.
++	# Supported since Solaris 2.6 (maybe 2.5.1?)
++	if test "$GCC" = yes; then
++	  whole_archive_flag_spec='${wl}-z ${wl}allextract$convenience ${wl}-z ${wl}defaultextract'
++	else
++	  whole_archive_flag_spec='-z allextract$convenience -z defaultextract'
++	fi
++	;;
++      esac
++      link_all_deplibs=yes
++      ;;
++
++    sunos4*)
++      if test "x$host_vendor" = xsequent; then
++	# Use $CC to link under sequent, because it throws in some extra .o
++	# files that make .init and .fini sections work.
++	archive_cmds='$CC -G ${wl}-h $soname -o $lib $libobjs $deplibs $compiler_flags'
++      else
++	archive_cmds='$LD -assert pure-text -Bstatic -o $lib $libobjs $deplibs $linker_flags'
++      fi
++      hardcode_libdir_flag_spec='-L$libdir'
++      hardcode_direct=yes
++      hardcode_minus_L=yes
++      hardcode_shlibpath_var=no
++      ;;
++
++    sysv4)
++      case $host_vendor in
++	sni)
++	  archive_cmds='$LD -G -h $soname -o $lib $libobjs $deplibs $linker_flags'
++	  hardcode_direct=yes # is this really true???
++	;;
++	siemens)
++	  ## LD is ld it makes a PLAMLIB
++	  ## CC just makes a GrossModule.
++	  archive_cmds='$LD -G -o $lib $libobjs $deplibs $linker_flags'
++	  reload_cmds='$CC -r -o $output$reload_objs'
++	  hardcode_direct=no
++        ;;
++	motorola)
++	  archive_cmds='$LD -G -h $soname -o $lib $libobjs $deplibs $linker_flags'
++	  hardcode_direct=no #Motorola manual says yes, but my tests say they lie
++	;;
++      esac
++      runpath_var='LD_RUN_PATH'
++      hardcode_shlibpath_var=no
++      ;;
++
++    sysv4.3*)
++      archive_cmds='$LD -G -h $soname -o $lib $libobjs $deplibs $linker_flags'
++      hardcode_shlibpath_var=no
++      export_dynamic_flag_spec='-Bexport'
++      ;;
++
++    sysv4*MP*)
++      if test -d /usr/nec; then
++	archive_cmds='$LD -G -h $soname -o $lib $libobjs $deplibs $linker_flags'
++	hardcode_shlibpath_var=no
++	runpath_var=LD_RUN_PATH
++	hardcode_runpath_var=yes
++	ld_shlibs=yes
++      fi
++      ;;
++
++    sysv4*uw2* | sysv5OpenUNIX* | sysv5UnixWare7.[01].[10]* | unixware7* | sco3.2v5.0.[024]*)
++      no_undefined_flag='${wl}-z,text'
++      archive_cmds_need_lc=no
++      hardcode_shlibpath_var=no
++      runpath_var='LD_RUN_PATH'
++
++      if test "$GCC" = yes; then
++	archive_cmds='$CC -shared ${wl}-h,$soname -o $lib $libobjs $deplibs $compiler_flags'
++	archive_expsym_cmds='$CC -shared ${wl}-Bexport:$export_symbols ${wl}-h,$soname -o $lib $libobjs $deplibs $compiler_flags'
++      else
++	archive_cmds='$CC -G ${wl}-h,$soname -o $lib $libobjs $deplibs $compiler_flags'
++	archive_expsym_cmds='$CC -G ${wl}-Bexport:$export_symbols ${wl}-h,$soname -o $lib $libobjs $deplibs $compiler_flags'
++      fi
++      ;;
++
++    sysv5* | sco3.2v5* | sco5v6*)
++      # Note: We can NOT use -z defs as we might desire, because we do not
++      # link with -lc, and that would cause any symbols used from libc to
++      # always be unresolved, which means just about no library would
++      # ever link correctly.  If we're not using GNU ld we use -z text
++      # though, which does catch some bad symbols but isn't as heavy-handed
++      # as -z defs.
++      no_undefined_flag='${wl}-z,text'
++      allow_undefined_flag='${wl}-z,nodefs'
++      archive_cmds_need_lc=no
++      hardcode_shlibpath_var=no
++      hardcode_libdir_flag_spec='${wl}-R,$libdir'
++      hardcode_libdir_separator=':'
++      link_all_deplibs=yes
++      export_dynamic_flag_spec='${wl}-Bexport'
++      runpath_var='LD_RUN_PATH'
++
++      if test "$GCC" = yes; then
++	archive_cmds='$CC -shared ${wl}-h,$soname -o $lib $libobjs $deplibs $compiler_flags'
++	archive_expsym_cmds='$CC -shared ${wl}-Bexport:$export_symbols ${wl}-h,$soname -o $lib $libobjs $deplibs $compiler_flags'
++      else
++	archive_cmds='$CC -G ${wl}-h,$soname -o $lib $libobjs $deplibs $compiler_flags'
++	archive_expsym_cmds='$CC -G ${wl}-Bexport:$export_symbols ${wl}-h,$soname -o $lib $libobjs $deplibs $compiler_flags'
++      fi
++      ;;
++
++    uts4*)
++      archive_cmds='$LD -G -h $soname -o $lib $libobjs $deplibs $linker_flags'
++      hardcode_libdir_flag_spec='-L$libdir'
++      hardcode_shlibpath_var=no
++      ;;
++
++    *)
++      ld_shlibs=no
++      ;;
++    esac
++
++    if test x$host_vendor = xsni; then
++      case $host in
++      sysv4 | sysv4.2uw2* | sysv4.3* | sysv5*)
++	export_dynamic_flag_spec='${wl}-Blargedynsym'
++	;;
++      esac
++    fi
++  fi
++
++{ $as_echo "$as_me:${as_lineno-$LINENO}: result: $ld_shlibs" >&5
++$as_echo "$ld_shlibs" >&6; }
++test "$ld_shlibs" = no && can_build_shared=no
++
++with_gnu_ld=$with_gnu_ld
++
++
++
++
++
++
++
++
++
++
++
++
++
++
++
++#
++# Do we need to explicitly link libc?
++#
++case "x$archive_cmds_need_lc" in
++x|xyes)
++  # Assume -lc should be added
++  archive_cmds_need_lc=yes
++
++  if test "$enable_shared" = yes && test "$GCC" = yes; then
++    case $archive_cmds in
++    *'~'*)
++      # FIXME: we may have to deal with multi-command sequences.
++      ;;
++    '$CC '*)
++      # Test whether the compiler implicitly links with -lc since on some
++      # systems, -lgcc has to come before -lc. If gcc already passes -lc
++      # to ld, don't add -lc before -lgcc.
++      { $as_echo "$as_me:${as_lineno-$LINENO}: checking whether -lc should be explicitly linked in" >&5
++$as_echo_n "checking whether -lc should be explicitly linked in... " >&6; }
++if ${lt_cv_archive_cmds_need_lc+:} false; then :
++  $as_echo_n "(cached) " >&6
++else
++  $RM conftest*
++	echo "$lt_simple_compile_test_code" > conftest.$ac_ext
++
++	if { { eval echo "\"\$as_me\":${as_lineno-$LINENO}: \"$ac_compile\""; } >&5
++  (eval $ac_compile) 2>&5
++  ac_status=$?
++  $as_echo "$as_me:${as_lineno-$LINENO}: \$? = $ac_status" >&5
++  test $ac_status = 0; } 2>conftest.err; then
++	  soname=conftest
++	  lib=conftest
++	  libobjs=conftest.$ac_objext
++	  deplibs=
++	  wl=$lt_prog_compiler_wl
++	  pic_flag=$lt_prog_compiler_pic
++	  compiler_flags=-v
++	  linker_flags=-v
++	  verstring=
++	  output_objdir=.
++	  libname=conftest
++	  lt_save_allow_undefined_flag=$allow_undefined_flag
++	  allow_undefined_flag=
++	  if { { eval echo "\"\$as_me\":${as_lineno-$LINENO}: \"$archive_cmds 2\>\&1 \| $GREP \" -lc \" \>/dev/null 2\>\&1\""; } >&5
++  (eval $archive_cmds 2\>\&1 \| $GREP \" -lc \" \>/dev/null 2\>\&1) 2>&5
++  ac_status=$?
++  $as_echo "$as_me:${as_lineno-$LINENO}: \$? = $ac_status" >&5
++  test $ac_status = 0; }
++	  then
++	    lt_cv_archive_cmds_need_lc=no
++	  else
++	    lt_cv_archive_cmds_need_lc=yes
++	  fi
++	  allow_undefined_flag=$lt_save_allow_undefined_flag
++	else
++	  cat conftest.err 1>&5
++	fi
++	$RM conftest*
++
++fi
++{ $as_echo "$as_me:${as_lineno-$LINENO}: result: $lt_cv_archive_cmds_need_lc" >&5
++$as_echo "$lt_cv_archive_cmds_need_lc" >&6; }
++      archive_cmds_need_lc=$lt_cv_archive_cmds_need_lc
++      ;;
++    esac
++  fi
++  ;;
++esac
++
++
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++
++
++  { $as_echo "$as_me:${as_lineno-$LINENO}: checking dynamic linker characteristics" >&5
++$as_echo_n "checking dynamic linker characteristics... " >&6; }
++
++if test "$GCC" = yes; then
++  case $host_os in
++    darwin*) lt_awk_arg="/^libraries:/,/LR/" ;;
++    *) lt_awk_arg="/^libraries:/" ;;
++  esac
++  case $host_os in
++    mingw* | cegcc*) lt_sed_strip_eq="s,=\([A-Za-z]:\),\1,g" ;;
++    *) lt_sed_strip_eq="s,=/,/,g" ;;
++  esac
++  lt_search_path_spec=`$CC -print-search-dirs | awk $lt_awk_arg | $SED -e "s/^libraries://" -e $lt_sed_strip_eq`
++  case $lt_search_path_spec in
++  *\;*)
++    # if the path contains ";" then we assume it to be the separator
++    # otherwise default to the standard path separator (i.e. ":") - it is
++    # assumed that no part of a normal pathname contains ";" but that should
++    # okay in the real world where ";" in dirpaths is itself problematic.
++    lt_search_path_spec=`$ECHO "$lt_search_path_spec" | $SED 's/;/ /g'`
++    ;;
++  *)
++    lt_search_path_spec=`$ECHO "$lt_search_path_spec" | $SED "s/$PATH_SEPARATOR/ /g"`
++    ;;
++  esac
++  # Ok, now we have the path, separated by spaces, we can step through it
++  # and add multilib dir if necessary.
++  lt_tmp_lt_search_path_spec=
++  lt_multi_os_dir=`$CC $CPPFLAGS $CFLAGS $LDFLAGS -print-multi-os-directory 2>/dev/null`
++  for lt_sys_path in $lt_search_path_spec; do
++    if test -d "$lt_sys_path/$lt_multi_os_dir"; then
++      lt_tmp_lt_search_path_spec="$lt_tmp_lt_search_path_spec $lt_sys_path/$lt_multi_os_dir"
++    else
++      test -d "$lt_sys_path" && \
++	lt_tmp_lt_search_path_spec="$lt_tmp_lt_search_path_spec $lt_sys_path"
++    fi
++  done
++  lt_search_path_spec=`$ECHO "$lt_tmp_lt_search_path_spec" | awk '
++BEGIN {RS=" "; FS="/|\n";} {
++  lt_foo="";
++  lt_count=0;
++  for (lt_i = NF; lt_i > 0; lt_i--) {
++    if ($lt_i != "" && $lt_i != ".") {
++      if ($lt_i == "..") {
++        lt_count++;
++      } else {
++        if (lt_count == 0) {
++          lt_foo="/" $lt_i lt_foo;
++        } else {
++          lt_count--;
++        }
++      }
++    }
++  }
++  if (lt_foo != "") { lt_freq[lt_foo]++; }
++  if (lt_freq[lt_foo] == 1) { print lt_foo; }
++}'`
++  # AWK program above erroneously prepends '/' to C:/dos/paths
++  # for these hosts.
++  case $host_os in
++    mingw* | cegcc*) lt_search_path_spec=`$ECHO "$lt_search_path_spec" |\
++      $SED 's,/\([A-Za-z]:\),\1,g'` ;;
++  esac
++  sys_lib_search_path_spec=`$ECHO "$lt_search_path_spec" | $lt_NL2SP`
++else
++  sys_lib_search_path_spec="/lib /usr/lib /usr/local/lib"
++fi
++library_names_spec=
++libname_spec='lib$name'
++soname_spec=
++shrext_cmds=".so"
++postinstall_cmds=
++postuninstall_cmds=
++finish_cmds=
++finish_eval=
++shlibpath_var=
++shlibpath_overrides_runpath=unknown
++version_type=none
++dynamic_linker="$host_os ld.so"
++sys_lib_dlsearch_path_spec="/lib /usr/lib"
++need_lib_prefix=unknown
++hardcode_into_libs=no
++
++# when you set need_version to no, make sure it does not cause -set_version
++# flags to be left without arguments
++need_version=unknown
++
++case $host_os in
++aix3*)
++  version_type=linux
++  library_names_spec='${libname}${release}${shared_ext}$versuffix $libname.a'
++  shlibpath_var=LIBPATH
++
++  # AIX 3 has no versioning support, so we append a major version to the name.
++  soname_spec='${libname}${release}${shared_ext}$major'
++  ;;
++
++aix[4-9]*)
++  version_type=linux
++  need_lib_prefix=no
++  need_version=no
++  hardcode_into_libs=yes
++  if test "$host_cpu" = ia64; then
++    # AIX 5 supports IA64
++    library_names_spec='${libname}${release}${shared_ext}$major ${libname}${release}${shared_ext}$versuffix $libname${shared_ext}'
++    shlibpath_var=LD_LIBRARY_PATH
++  else
++    # With GCC up to 2.95.x, collect2 would create an import file
++    # for dependence libraries.  The import file would start with
++    # the line `#! .'.  This would cause the generated library to
++    # depend on `.', always an invalid library.  This was fixed in
++    # development snapshots of GCC prior to 3.0.
++    case $host_os in
++      aix4 | aix4.[01] | aix4.[01].*)
++      if { echo '#if __GNUC__ > 2 || (__GNUC__ == 2 && __GNUC_MINOR__ >= 97)'
++	   echo ' yes '
++	   echo '#endif'; } | ${CC} -E - | $GREP yes > /dev/null; then
++	:
++      else
++	can_build_shared=no
++      fi
++      ;;
++    esac
++    # AIX (on Power*) has no versioning support, so currently we can not hardcode correct
++    # soname into executable. Probably we can add versioning support to
++    # collect2, so additional links can be useful in future.
++    if test "$aix_use_runtimelinking" = yes; then
++      # If using run time linking (on AIX 4.2 or later) use lib<name>.so
++      # instead of lib<name>.a to let people know that these are not
++      # typical AIX shared libraries.
++      library_names_spec='${libname}${release}${shared_ext}$versuffix ${libname}${release}${shared_ext}$major $libname${shared_ext}'
++    else
++      # We preserve .a as extension for shared libraries through AIX4.2
++      # and later when we are not doing run time linking.
++      library_names_spec='${libname}${release}.a $libname.a'
++      soname_spec='${libname}${release}${shared_ext}$major'
++    fi
++    shlibpath_var=LIBPATH
++  fi
++  ;;
++
++amigaos*)
++  case $host_cpu in
++  powerpc)
++    # Since July 2007 AmigaOS4 officially supports .so libraries.
++    # When compiling the executable, add -use-dynld -Lsobjs: to the compileline.
++    library_names_spec='${libname}${release}${shared_ext}$versuffix ${libname}${release}${shared_ext}$major $libname${shared_ext}'
++    ;;
++  m68k)
++    library_names_spec='$libname.ixlibrary $libname.a'
++    # Create ${libname}_ixlibrary.a entries in /sys/libs.
++    finish_eval='for lib in `ls $libdir/*.ixlibrary 2>/dev/null`; do libname=`func_echo_all "$lib" | $SED '\''s%^.*/\([^/]*\)\.ixlibrary$%\1%'\''`; test $RM /sys/libs/${libname}_ixlibrary.a; $show "cd /sys/libs && $LN_S $lib ${libname}_ixlibrary.a"; cd /sys/libs && $LN_S $lib ${libname}_ixlibrary.a || exit 1; done'
++    ;;
++  esac
++  ;;
++
++beos*)
++  library_names_spec='${libname}${shared_ext}'
++  dynamic_linker="$host_os ld.so"
++  shlibpath_var=LIBRARY_PATH
++  ;;
++
++bsdi[45]*)
++  version_type=linux
++  need_version=no
++  library_names_spec='${libname}${release}${shared_ext}$versuffix ${libname}${release}${shared_ext}$major $libname${shared_ext}'
++  soname_spec='${libname}${release}${shared_ext}$major'
++  finish_cmds='PATH="\$PATH:/sbin" ldconfig $libdir'
++  shlibpath_var=LD_LIBRARY_PATH
++  sys_lib_search_path_spec="/shlib /usr/lib /usr/X11/lib /usr/contrib/lib /lib /usr/local/lib"
++  sys_lib_dlsearch_path_spec="/shlib /usr/lib /usr/local/lib"
++  # the default ld.so.conf also contains /usr/contrib/lib and
++  # /usr/X11R6/lib (/usr/X11 is a link to /usr/X11R6), but let us allow
++  # libtool to hard-code these into programs
++  ;;
++
++cygwin* | mingw* | pw32* | cegcc*)
++  version_type=windows
++  shrext_cmds=".dll"
++  need_version=no
++  need_lib_prefix=no
++
++  case $GCC,$host_os in
++  yes,cygwin* | yes,mingw* | yes,pw32* | yes,cegcc*)
++    library_names_spec='$libname.dll.a'
++    # DLL is installed to $(libdir)/../bin by postinstall_cmds
++    postinstall_cmds='base_file=`basename \${file}`~
++      dlpath=`$SHELL 2>&1 -c '\''. $dir/'\''\${base_file}'\''i; echo \$dlname'\''`~
++      dldir=$destdir/`dirname \$dlpath`~
++      test -d \$dldir || mkdir -p \$dldir~
++      $install_prog $dir/$dlname \$dldir/$dlname~
++      chmod a+x \$dldir/$dlname~
++      if test -n '\''$stripme'\'' && test -n '\''$striplib'\''; then
++        eval '\''$striplib \$dldir/$dlname'\'' || exit \$?;
++      fi'
++    postuninstall_cmds='dldll=`$SHELL 2>&1 -c '\''. $file; echo \$dlname'\''`~
++      dlpath=$dir/\$dldll~
++       $RM \$dlpath'
++    shlibpath_overrides_runpath=yes
++
++    case $host_os in
++    cygwin*)
++      # Cygwin DLLs use 'cyg' prefix rather than 'lib'
++      soname_spec='`echo ${libname} | sed -e 's/^lib/cyg/'``echo ${release} | $SED -e 's/[.]/-/g'`${versuffix}${shared_ext}'
++
++      sys_lib_search_path_spec="$sys_lib_search_path_spec /usr/lib/w32api"
++      ;;
++    mingw* | cegcc*)
++      # MinGW DLLs use traditional 'lib' prefix
++      soname_spec='${libname}`echo ${release} | $SED -e 's/[.]/-/g'`${versuffix}${shared_ext}'
++      ;;
++    pw32*)
++      # pw32 DLLs use 'pw' prefix rather than 'lib'
++      library_names_spec='`echo ${libname} | sed -e 's/^lib/pw/'``echo ${release} | $SED -e 's/[.]/-/g'`${versuffix}${shared_ext}'
++      ;;
++    esac
++    ;;
++
++  *)
++    library_names_spec='${libname}`echo ${release} | $SED -e 's/[.]/-/g'`${versuffix}${shared_ext} $libname.lib'
++    ;;
++  esac
++  dynamic_linker='Win32 ld.exe'
++  # FIXME: first we should search . and the directory the executable is in
++  shlibpath_var=PATH
++  ;;
++
++darwin* | rhapsody*)
++  dynamic_linker="$host_os dyld"
++  version_type=darwin
++  need_lib_prefix=no
++  need_version=no
++  library_names_spec='${libname}${release}${major}$shared_ext ${libname}$shared_ext'
++  soname_spec='${libname}${release}${major}$shared_ext'
++  shlibpath_overrides_runpath=yes
++  shlibpath_var=DYLD_LIBRARY_PATH
++  shrext_cmds='`test .$module = .yes && echo .so || echo .dylib`'
++
++  sys_lib_search_path_spec="$sys_lib_search_path_spec /usr/local/lib"
++  sys_lib_dlsearch_path_spec='/usr/local/lib /lib /usr/lib'
++  ;;
++
++dgux*)
++  version_type=linux
++  need_lib_prefix=no
++  need_version=no
++  library_names_spec='${libname}${release}${shared_ext}$versuffix ${libname}${release}${shared_ext}$major $libname$shared_ext'
++  soname_spec='${libname}${release}${shared_ext}$major'
++  shlibpath_var=LD_LIBRARY_PATH
++  ;;
++
++freebsd* | dragonfly*)
++  # DragonFly does not have aout.  When/if they implement a new
++  # versioning mechanism, adjust this.
++  if test -x /usr/bin/objformat; then
++    objformat=`/usr/bin/objformat`
++  else
++    case $host_os in
++    freebsd[23].*) objformat=aout ;;
++    *) objformat=elf ;;
++    esac
++  fi
++  version_type=freebsd-$objformat
++  case $version_type in
++    freebsd-elf*)
++      library_names_spec='${libname}${release}${shared_ext}$versuffix ${libname}${release}${shared_ext} $libname${shared_ext}'
++      need_version=no
++      need_lib_prefix=no
++      ;;
++    freebsd-*)
++      library_names_spec='${libname}${release}${shared_ext}$versuffix $libname${shared_ext}$versuffix'
++      need_version=yes
++      ;;
++  esac
++  shlibpath_var=LD_LIBRARY_PATH
++  case $host_os in
++  freebsd2.*)
++    shlibpath_overrides_runpath=yes
++    ;;
++  freebsd3.[01]* | freebsdelf3.[01]*)
++    shlibpath_overrides_runpath=yes
++    hardcode_into_libs=yes
++    ;;
++  freebsd3.[2-9]* | freebsdelf3.[2-9]* | \
++  freebsd4.[0-5] | freebsdelf4.[0-5] | freebsd4.1.1 | freebsdelf4.1.1)
++    shlibpath_overrides_runpath=no
++    hardcode_into_libs=yes
++    ;;
++  *) # from 4.6 on, and DragonFly
++    shlibpath_overrides_runpath=yes
++    hardcode_into_libs=yes
++    ;;
++  esac
++  ;;
++
++gnu*)
++  version_type=linux
++  need_lib_prefix=no
++  need_version=no
++  library_names_spec='${libname}${release}${shared_ext}$versuffix ${libname}${release}${shared_ext}${major} ${libname}${shared_ext}'
++  soname_spec='${libname}${release}${shared_ext}$major'
++  shlibpath_var=LD_LIBRARY_PATH
++  hardcode_into_libs=yes
++  ;;
++
++haiku*)
++  version_type=linux
++  need_lib_prefix=no
++  need_version=no
++  dynamic_linker="$host_os runtime_loader"
++  library_names_spec='${libname}${release}${shared_ext}$versuffix ${libname}${release}${shared_ext}${major} ${libname}${shared_ext}'
++  soname_spec='${libname}${release}${shared_ext}$major'
++  shlibpath_var=LIBRARY_PATH
++  shlibpath_overrides_runpath=yes
++  sys_lib_dlsearch_path_spec='/boot/home/config/lib /boot/common/lib /boot/beos/system/lib'
++  hardcode_into_libs=yes
++  ;;
++
++hpux9* | hpux10* | hpux11*)
++  # Give a soname corresponding to the major version so that dld.sl refuses to
++  # link against other versions.
++  version_type=sunos
++  need_lib_prefix=no
++  need_version=no
++  case $host_cpu in
++  ia64*)
++    shrext_cmds='.so'
++    hardcode_into_libs=yes
++    dynamic_linker="$host_os dld.so"
++    shlibpath_var=LD_LIBRARY_PATH
++    shlibpath_overrides_runpath=yes # Unless +noenvvar is specified.
++    library_names_spec='${libname}${release}${shared_ext}$versuffix ${libname}${release}${shared_ext}$major $libname${shared_ext}'
++    soname_spec='${libname}${release}${shared_ext}$major'
++    if test "X$HPUX_IA64_MODE" = X32; then
++      sys_lib_search_path_spec="/usr/lib/hpux32 /usr/local/lib/hpux32 /usr/local/lib"
++    else
++      sys_lib_search_path_spec="/usr/lib/hpux64 /usr/local/lib/hpux64"
++    fi
++    sys_lib_dlsearch_path_spec=$sys_lib_search_path_spec
++    ;;
++  hppa*64*)
++    shrext_cmds='.sl'
++    hardcode_into_libs=yes
++    dynamic_linker="$host_os dld.sl"
++    shlibpath_var=LD_LIBRARY_PATH # How should we handle SHLIB_PATH
++    shlibpath_overrides_runpath=yes # Unless +noenvvar is specified.
++    library_names_spec='${libname}${release}${shared_ext}$versuffix ${libname}${release}${shared_ext}$major $libname${shared_ext}'
++    soname_spec='${libname}${release}${shared_ext}$major'
++    sys_lib_search_path_spec="/usr/lib/pa20_64 /usr/ccs/lib/pa20_64"
++    sys_lib_dlsearch_path_spec=$sys_lib_search_path_spec
++    ;;
++  *)
++    shrext_cmds='.sl'
++    dynamic_linker="$host_os dld.sl"
++    shlibpath_var=SHLIB_PATH
++    shlibpath_overrides_runpath=no # +s is required to enable SHLIB_PATH
++    library_names_spec='${libname}${release}${shared_ext}$versuffix ${libname}${release}${shared_ext}$major $libname${shared_ext}'
++    soname_spec='${libname}${release}${shared_ext}$major'
++    ;;
++  esac
++  # HP-UX runs *really* slowly unless shared libraries are mode 555, ...
++  postinstall_cmds='chmod 555 $lib'
++  # or fails outright, so override atomically:
++  install_override_mode=555
++  ;;
++
++interix[3-9]*)
++  version_type=linux
++  need_lib_prefix=no
++  need_version=no
++  library_names_spec='${libname}${release}${shared_ext}$versuffix ${libname}${release}${shared_ext}$major ${libname}${shared_ext}'
++  soname_spec='${libname}${release}${shared_ext}$major'
++  dynamic_linker='Interix 3.x ld.so.1 (PE, like ELF)'
++  shlibpath_var=LD_LIBRARY_PATH
++  shlibpath_overrides_runpath=no
++  hardcode_into_libs=yes
++  ;;
++
++irix5* | irix6* | nonstopux*)
++  case $host_os in
++    nonstopux*) version_type=nonstopux ;;
++    *)
++	if test "$lt_cv_prog_gnu_ld" = yes; then
++		version_type=linux
++	else
++		version_type=irix
++	fi ;;
++  esac
++  need_lib_prefix=no
++  need_version=no
++  soname_spec='${libname}${release}${shared_ext}$major'
++  library_names_spec='${libname}${release}${shared_ext}$versuffix ${libname}${release}${shared_ext}$major ${libname}${release}${shared_ext} $libname${shared_ext}'
++  case $host_os in
++  irix5* | nonstopux*)
++    libsuff= shlibsuff=
++    ;;
++  *)
++    case $LD in # libtool.m4 will add one of these switches to LD
++    *-32|*"-32 "|*-melf32bsmip|*"-melf32bsmip ")
++      libsuff= shlibsuff= libmagic=32-bit;;
++    *-n32|*"-n32 "|*-melf32bmipn32|*"-melf32bmipn32 ")
++      libsuff=32 shlibsuff=N32 libmagic=N32;;
++    *-64|*"-64 "|*-melf64bmip|*"-melf64bmip ")
++      libsuff=64 shlibsuff=64 libmagic=64-bit;;
++    *) libsuff= shlibsuff= libmagic=never-match;;
++    esac
++    ;;
++  esac
++  shlibpath_var=LD_LIBRARY${shlibsuff}_PATH
++  shlibpath_overrides_runpath=no
++  sys_lib_search_path_spec="/usr/lib${libsuff} /lib${libsuff} /usr/local/lib${libsuff}"
++  sys_lib_dlsearch_path_spec="/usr/lib${libsuff} /lib${libsuff}"
++  hardcode_into_libs=yes
++  ;;
++
++# No shared lib support for Linux oldld, aout, or coff.
++linux*oldld* | linux*aout* | linux*coff*)
++  dynamic_linker=no
++  ;;
++
++# This must be Linux ELF.
++linux* | k*bsd*-gnu | kopensolaris*-gnu)
++  version_type=linux
++  need_lib_prefix=no
++  need_version=no
++  library_names_spec='${libname}${release}${shared_ext}$versuffix ${libname}${release}${shared_ext}$major $libname${shared_ext}'
++  soname_spec='${libname}${release}${shared_ext}$major'
++  finish_cmds='PATH="\$PATH:/sbin" ldconfig -n $libdir'
++  shlibpath_var=LD_LIBRARY_PATH
++  shlibpath_overrides_runpath=no
++
++  # Some binutils ld are patched to set DT_RUNPATH
++  if ${lt_cv_shlibpath_overrides_runpath+:} false; then :
++  $as_echo_n "(cached) " >&6
++else
++  lt_cv_shlibpath_overrides_runpath=no
++    save_LDFLAGS=$LDFLAGS
++    save_libdir=$libdir
++    eval "libdir=/foo; wl=\"$lt_prog_compiler_wl\"; \
++	 LDFLAGS=\"\$LDFLAGS $hardcode_libdir_flag_spec\""
++    cat confdefs.h - <<_ACEOF >conftest.$ac_ext
++/* end confdefs.h.  */
++
++int
++main ()
++{
++
++  ;
++  return 0;
++}
++_ACEOF
++if ac_fn_c_try_link "$LINENO"; then :
++  if  ($OBJDUMP -p conftest$ac_exeext) 2>/dev/null | grep "RUNPATH.*$libdir" >/dev/null; then :
++  lt_cv_shlibpath_overrides_runpath=yes
++fi
++fi
++rm -f core conftest.err conftest.$ac_objext \
++    conftest$ac_exeext conftest.$ac_ext
++    LDFLAGS=$save_LDFLAGS
++    libdir=$save_libdir
++
++fi
++
++  shlibpath_overrides_runpath=$lt_cv_shlibpath_overrides_runpath
++
++  # This implies no fast_install, which is unacceptable.
++  # Some rework will be needed to allow for fast_install
++  # before this can be enabled.
++  hardcode_into_libs=yes
++
++  # Append ld.so.conf contents to the search path
++  if test -f /etc/ld.so.conf; then
++    lt_ld_extra=`awk '/^include / { system(sprintf("cd /etc; cat %s 2>/dev/null", \$2)); skip = 1; } { if (!skip) print \$0; skip = 0; }' < /etc/ld.so.conf | $SED -e 's/#.*//;/^[	 ]*hwcap[	 ]/d;s/[:,	]/ /g;s/=[^=]*$//;s/=[^= ]* / /g;s/"//g;/^$/d' | tr '\n' ' '`
++    sys_lib_dlsearch_path_spec="/lib /usr/lib $lt_ld_extra"
++  fi
++
++  # We used to test for /lib/ld.so.1 and disable shared libraries on
++  # powerpc, because MkLinux only supported shared libraries with the
++  # GNU dynamic linker.  Since this was broken with cross compilers,
++  # most powerpc-linux boxes support dynamic linking these days and
++  # people can always --disable-shared, the test was removed, and we
++  # assume the GNU/Linux dynamic linker is in use.
++  dynamic_linker='GNU/Linux ld.so'
++  ;;
++
++netbsd*)
++  version_type=sunos
++  need_lib_prefix=no
++  need_version=no
++  if echo __ELF__ | $CC -E - | $GREP __ELF__ >/dev/null; then
++    library_names_spec='${libname}${release}${shared_ext}$versuffix ${libname}${shared_ext}$versuffix'
++    finish_cmds='PATH="\$PATH:/sbin" ldconfig -m $libdir'
++    dynamic_linker='NetBSD (a.out) ld.so'
++  else
++    library_names_spec='${libname}${release}${shared_ext}$versuffix ${libname}${release}${shared_ext}$major ${libname}${shared_ext}'
++    soname_spec='${libname}${release}${shared_ext}$major'
++    dynamic_linker='NetBSD ld.elf_so'
++  fi
++  shlibpath_var=LD_LIBRARY_PATH
++  shlibpath_overrides_runpath=yes
++  hardcode_into_libs=yes
++  ;;
++
++newsos6)
++  version_type=linux
++  library_names_spec='${libname}${release}${shared_ext}$versuffix ${libname}${release}${shared_ext}$major $libname${shared_ext}'
++  shlibpath_var=LD_LIBRARY_PATH
++  shlibpath_overrides_runpath=yes
++  ;;
++
++*nto* | *qnx*)
++  version_type=qnx
++  need_lib_prefix=no
++  need_version=no
++  library_names_spec='${libname}${release}${shared_ext}$versuffix ${libname}${release}${shared_ext}$major $libname${shared_ext}'
++  soname_spec='${libname}${release}${shared_ext}$major'
++  shlibpath_var=LD_LIBRARY_PATH
++  shlibpath_overrides_runpath=no
++  hardcode_into_libs=yes
++  dynamic_linker='ldqnx.so'
++  ;;
++
++openbsd*)
++  version_type=sunos
++  sys_lib_dlsearch_path_spec="/usr/lib"
++  need_lib_prefix=no
++  # Some older versions of OpenBSD (3.3 at least) *do* need versioned libs.
++  case $host_os in
++    openbsd3.3 | openbsd3.3.*)	need_version=yes ;;
++    *)				need_version=no  ;;
++  esac
++  library_names_spec='${libname}${release}${shared_ext}$versuffix ${libname}${shared_ext}$versuffix'
++  finish_cmds='PATH="\$PATH:/sbin" ldconfig -m $libdir'
++  shlibpath_var=LD_LIBRARY_PATH
++  if test -z "`echo __ELF__ | $CC -E - | $GREP __ELF__`" || test "$host_os-$host_cpu" = "openbsd2.8-powerpc"; then
++    case $host_os in
++      openbsd2.[89] | openbsd2.[89].*)
++	shlibpath_overrides_runpath=no
++	;;
++      *)
++	shlibpath_overrides_runpath=yes
++	;;
++      esac
++  else
++    shlibpath_overrides_runpath=yes
++  fi
++  ;;
++
++os2*)
++  libname_spec='$name'
++  shrext_cmds=".dll"
++  need_lib_prefix=no
++  library_names_spec='$libname${shared_ext} $libname.a'
++  dynamic_linker='OS/2 ld.exe'
++  shlibpath_var=LIBPATH
++  ;;
++
++osf3* | osf4* | osf5*)
++  version_type=osf
++  need_lib_prefix=no
++  need_version=no
++  soname_spec='${libname}${release}${shared_ext}$major'
++  library_names_spec='${libname}${release}${shared_ext}$versuffix ${libname}${release}${shared_ext}$major $libname${shared_ext}'
++  shlibpath_var=LD_LIBRARY_PATH
++  sys_lib_search_path_spec="/usr/shlib /usr/ccs/lib /usr/lib/cmplrs/cc /usr/lib /usr/local/lib /var/shlib"
++  sys_lib_dlsearch_path_spec="$sys_lib_search_path_spec"
++  ;;
++
++rdos*)
++  dynamic_linker=no
++  ;;
++
++solaris*)
++  version_type=linux
++  need_lib_prefix=no
++  need_version=no
++  library_names_spec='${libname}${release}${shared_ext}$versuffix ${libname}${release}${shared_ext}$major $libname${shared_ext}'
++  soname_spec='${libname}${release}${shared_ext}$major'
++  shlibpath_var=LD_LIBRARY_PATH
++  shlibpath_overrides_runpath=yes
++  hardcode_into_libs=yes
++  # ldd complains unless libraries are executable
++  postinstall_cmds='chmod +x $lib'
++  ;;
++
++sunos4*)
++  version_type=sunos
++  library_names_spec='${libname}${release}${shared_ext}$versuffix ${libname}${shared_ext}$versuffix'
++  finish_cmds='PATH="\$PATH:/usr/etc" ldconfig $libdir'
++  shlibpath_var=LD_LIBRARY_PATH
++  shlibpath_overrides_runpath=yes
++  if test "$with_gnu_ld" = yes; then
++    need_lib_prefix=no
++  fi
++  need_version=yes
++  ;;
++
++sysv4 | sysv4.3*)
++  version_type=linux
++  library_names_spec='${libname}${release}${shared_ext}$versuffix ${libname}${release}${shared_ext}$major $libname${shared_ext}'
++  soname_spec='${libname}${release}${shared_ext}$major'
++  shlibpath_var=LD_LIBRARY_PATH
++  case $host_vendor in
++    sni)
++      shlibpath_overrides_runpath=no
++      need_lib_prefix=no
++      runpath_var=LD_RUN_PATH
++      ;;
++    siemens)
++      need_lib_prefix=no
++      ;;
++    motorola)
++      need_lib_prefix=no
++      need_version=no
++      shlibpath_overrides_runpath=no
++      sys_lib_search_path_spec='/lib /usr/lib /usr/ccs/lib'
++      ;;
++  esac
++  ;;
++
++sysv4*MP*)
++  if test -d /usr/nec ;then
++    version_type=linux
++    library_names_spec='$libname${shared_ext}.$versuffix $libname${shared_ext}.$major $libname${shared_ext}'
++    soname_spec='$libname${shared_ext}.$major'
++    shlibpath_var=LD_LIBRARY_PATH
++  fi
++  ;;
++
++sysv5* | sco3.2v5* | sco5v6* | unixware* | OpenUNIX* | sysv4*uw2*)
++  version_type=freebsd-elf
++  need_lib_prefix=no
++  need_version=no
++  library_names_spec='${libname}${release}${shared_ext}$versuffix ${libname}${release}${shared_ext} $libname${shared_ext}'
++  soname_spec='${libname}${release}${shared_ext}$major'
++  shlibpath_var=LD_LIBRARY_PATH
++  shlibpath_overrides_runpath=yes
++  hardcode_into_libs=yes
++  if test "$with_gnu_ld" = yes; then
++    sys_lib_search_path_spec='/usr/local/lib /usr/gnu/lib /usr/ccs/lib /usr/lib /lib'
++  else
++    sys_lib_search_path_spec='/usr/ccs/lib /usr/lib'
++    case $host_os in
++      sco3.2v5*)
++        sys_lib_search_path_spec="$sys_lib_search_path_spec /lib"
++	;;
++    esac
++  fi
++  sys_lib_dlsearch_path_spec='/usr/lib'
++  ;;
++
++tpf*)
++  # TPF is a cross-target only.  Preferred cross-host = GNU/Linux.
++  version_type=linux
++  need_lib_prefix=no
++  need_version=no
++  library_names_spec='${libname}${release}${shared_ext}$versuffix ${libname}${release}${shared_ext}$major $libname${shared_ext}'
++  shlibpath_var=LD_LIBRARY_PATH
++  shlibpath_overrides_runpath=no
++  hardcode_into_libs=yes
++  ;;
++
++uts4*)
++  version_type=linux
++  library_names_spec='${libname}${release}${shared_ext}$versuffix ${libname}${release}${shared_ext}$major $libname${shared_ext}'
++  soname_spec='${libname}${release}${shared_ext}$major'
++  shlibpath_var=LD_LIBRARY_PATH
++  ;;
++
++*)
++  dynamic_linker=no
++  ;;
++esac
++{ $as_echo "$as_me:${as_lineno-$LINENO}: result: $dynamic_linker" >&5
++$as_echo "$dynamic_linker" >&6; }
++test "$dynamic_linker" = no && can_build_shared=no
++
++variables_saved_for_relink="PATH $shlibpath_var $runpath_var"
++if test "$GCC" = yes; then
++  variables_saved_for_relink="$variables_saved_for_relink GCC_EXEC_PREFIX COMPILER_PATH LIBRARY_PATH"
++fi
++
++if test "${lt_cv_sys_lib_search_path_spec+set}" = set; then
++  sys_lib_search_path_spec="$lt_cv_sys_lib_search_path_spec"
++fi
++if test "${lt_cv_sys_lib_dlsearch_path_spec+set}" = set; then
++  sys_lib_dlsearch_path_spec="$lt_cv_sys_lib_dlsearch_path_spec"
++fi
++
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++
++
++
++
++
++
++
++
++
++
++
++
++
++
++
++
++
++
++  { $as_echo "$as_me:${as_lineno-$LINENO}: checking how to hardcode library paths into programs" >&5
++$as_echo_n "checking how to hardcode library paths into programs... " >&6; }
++hardcode_action=
++if test -n "$hardcode_libdir_flag_spec" ||
++   test -n "$runpath_var" ||
++   test "X$hardcode_automatic" = "Xyes" ; then
++
++  # We can hardcode non-existent directories.
++  if test "$hardcode_direct" != no &&
++     # If the only mechanism to avoid hardcoding is shlibpath_var, we
++     # have to relink, otherwise we might link with an installed library
++     # when we should be linking with a yet-to-be-installed one
++     ## test "$_LT_TAGVAR(hardcode_shlibpath_var, )" != no &&
++     test "$hardcode_minus_L" != no; then
++    # Linking always hardcodes the temporary library directory.
++    hardcode_action=relink
++  else
++    # We can link without hardcoding, and we can hardcode nonexisting dirs.
++    hardcode_action=immediate
++  fi
++else
++  # We cannot hardcode anything, or else we can only hardcode existing
++  # directories.
++  hardcode_action=unsupported
++fi
++{ $as_echo "$as_me:${as_lineno-$LINENO}: result: $hardcode_action" >&5
++$as_echo "$hardcode_action" >&6; }
++
++if test "$hardcode_action" = relink ||
++   test "$inherit_rpath" = yes; then
++  # Fast installation is not supported
++  enable_fast_install=no
++elif test "$shlibpath_overrides_runpath" = yes ||
++     test "$enable_shared" = no; then
++  # Fast installation is not necessary
++  enable_fast_install=needless
++fi
++
++
++
++
++
++
++  if test "x$enable_dlopen" != xyes; then
++  enable_dlopen=unknown
++  enable_dlopen_self=unknown
++  enable_dlopen_self_static=unknown
++else
++  lt_cv_dlopen=no
++  lt_cv_dlopen_libs=
++
++  case $host_os in
++  beos*)
++    lt_cv_dlopen="load_add_on"
++    lt_cv_dlopen_libs=
++    lt_cv_dlopen_self=yes
++    ;;
++
++  mingw* | pw32* | cegcc*)
++    lt_cv_dlopen="LoadLibrary"
++    lt_cv_dlopen_libs=
++    ;;
++
++  cygwin*)
++    lt_cv_dlopen="dlopen"
++    lt_cv_dlopen_libs=
++    ;;
++
++  darwin*)
++  # if libdl is installed we need to link against it
++    { $as_echo "$as_me:${as_lineno-$LINENO}: checking for dlopen in -ldl" >&5
++$as_echo_n "checking for dlopen in -ldl... " >&6; }
++if ${ac_cv_lib_dl_dlopen+:} false; then :
++  $as_echo_n "(cached) " >&6
++else
++  ac_check_lib_save_LIBS=$LIBS
++LIBS="-ldl  $LIBS"
++cat confdefs.h - <<_ACEOF >conftest.$ac_ext
++/* end confdefs.h.  */
++
++/* Override any GCC internal prototype to avoid an error.
++   Use char because int might match the return type of a GCC
++   builtin and then its argument prototype would still apply.  */
++#ifdef __cplusplus
++extern "C"
++#endif
++char dlopen ();
++int
++main ()
++{
++return dlopen ();
++  ;
++  return 0;
++}
++_ACEOF
++if ac_fn_c_try_link "$LINENO"; then :
++  ac_cv_lib_dl_dlopen=yes
++else
++  ac_cv_lib_dl_dlopen=no
++fi
++rm -f core conftest.err conftest.$ac_objext \
++    conftest$ac_exeext conftest.$ac_ext
++LIBS=$ac_check_lib_save_LIBS
++fi
++{ $as_echo "$as_me:${as_lineno-$LINENO}: result: $ac_cv_lib_dl_dlopen" >&5
++$as_echo "$ac_cv_lib_dl_dlopen" >&6; }
++if test "x$ac_cv_lib_dl_dlopen" = xyes; then :
++  lt_cv_dlopen="dlopen" lt_cv_dlopen_libs="-ldl"
++else
++
++    lt_cv_dlopen="dyld"
++    lt_cv_dlopen_libs=
++    lt_cv_dlopen_self=yes
++
++fi
++
++    ;;
++
++  *)
++    ac_fn_c_check_func "$LINENO" "shl_load" "ac_cv_func_shl_load"
++if test "x$ac_cv_func_shl_load" = xyes; then :
++  lt_cv_dlopen="shl_load"
++else
++  { $as_echo "$as_me:${as_lineno-$LINENO}: checking for shl_load in -ldld" >&5
++$as_echo_n "checking for shl_load in -ldld... " >&6; }
++if ${ac_cv_lib_dld_shl_load+:} false; then :
++  $as_echo_n "(cached) " >&6
++else
++  ac_check_lib_save_LIBS=$LIBS
++LIBS="-ldld  $LIBS"
++cat confdefs.h - <<_ACEOF >conftest.$ac_ext
++/* end confdefs.h.  */
++
++/* Override any GCC internal prototype to avoid an error.
++   Use char because int might match the return type of a GCC
++   builtin and then its argument prototype would still apply.  */
++#ifdef __cplusplus
++extern "C"
++#endif
++char shl_load ();
++int
++main ()
++{
++return shl_load ();
++  ;
++  return 0;
++}
++_ACEOF
++if ac_fn_c_try_link "$LINENO"; then :
++  ac_cv_lib_dld_shl_load=yes
++else
++  ac_cv_lib_dld_shl_load=no
++fi
++rm -f core conftest.err conftest.$ac_objext \
++    conftest$ac_exeext conftest.$ac_ext
++LIBS=$ac_check_lib_save_LIBS
++fi
++{ $as_echo "$as_me:${as_lineno-$LINENO}: result: $ac_cv_lib_dld_shl_load" >&5
++$as_echo "$ac_cv_lib_dld_shl_load" >&6; }
++if test "x$ac_cv_lib_dld_shl_load" = xyes; then :
++  lt_cv_dlopen="shl_load" lt_cv_dlopen_libs="-ldld"
++else
++  ac_fn_c_check_func "$LINENO" "dlopen" "ac_cv_func_dlopen"
++if test "x$ac_cv_func_dlopen" = xyes; then :
++  lt_cv_dlopen="dlopen"
++else
++  { $as_echo "$as_me:${as_lineno-$LINENO}: checking for dlopen in -ldl" >&5
++$as_echo_n "checking for dlopen in -ldl... " >&6; }
++if ${ac_cv_lib_dl_dlopen+:} false; then :
++  $as_echo_n "(cached) " >&6
++else
++  ac_check_lib_save_LIBS=$LIBS
++LIBS="-ldl  $LIBS"
++cat confdefs.h - <<_ACEOF >conftest.$ac_ext
++/* end confdefs.h.  */
++
++/* Override any GCC internal prototype to avoid an error.
++   Use char because int might match the return type of a GCC
++   builtin and then its argument prototype would still apply.  */
++#ifdef __cplusplus
++extern "C"
++#endif
++char dlopen ();
++int
++main ()
++{
++return dlopen ();
++  ;
++  return 0;
++}
++_ACEOF
++if ac_fn_c_try_link "$LINENO"; then :
++  ac_cv_lib_dl_dlopen=yes
++else
++  ac_cv_lib_dl_dlopen=no
++fi
++rm -f core conftest.err conftest.$ac_objext \
++    conftest$ac_exeext conftest.$ac_ext
++LIBS=$ac_check_lib_save_LIBS
++fi
++{ $as_echo "$as_me:${as_lineno-$LINENO}: result: $ac_cv_lib_dl_dlopen" >&5
++$as_echo "$ac_cv_lib_dl_dlopen" >&6; }
++if test "x$ac_cv_lib_dl_dlopen" = xyes; then :
++  lt_cv_dlopen="dlopen" lt_cv_dlopen_libs="-ldl"
++else
++  { $as_echo "$as_me:${as_lineno-$LINENO}: checking for dlopen in -lsvld" >&5
++$as_echo_n "checking for dlopen in -lsvld... " >&6; }
++if ${ac_cv_lib_svld_dlopen+:} false; then :
++  $as_echo_n "(cached) " >&6
++else
++  ac_check_lib_save_LIBS=$LIBS
++LIBS="-lsvld  $LIBS"
++cat confdefs.h - <<_ACEOF >conftest.$ac_ext
++/* end confdefs.h.  */
++
++/* Override any GCC internal prototype to avoid an error.
++   Use char because int might match the return type of a GCC
++   builtin and then its argument prototype would still apply.  */
++#ifdef __cplusplus
++extern "C"
++#endif
++char dlopen ();
++int
++main ()
++{
++return dlopen ();
++  ;
++  return 0;
++}
++_ACEOF
++if ac_fn_c_try_link "$LINENO"; then :
++  ac_cv_lib_svld_dlopen=yes
++else
++  ac_cv_lib_svld_dlopen=no
++fi
++rm -f core conftest.err conftest.$ac_objext \
++    conftest$ac_exeext conftest.$ac_ext
++LIBS=$ac_check_lib_save_LIBS
++fi
++{ $as_echo "$as_me:${as_lineno-$LINENO}: result: $ac_cv_lib_svld_dlopen" >&5
++$as_echo "$ac_cv_lib_svld_dlopen" >&6; }
++if test "x$ac_cv_lib_svld_dlopen" = xyes; then :
++  lt_cv_dlopen="dlopen" lt_cv_dlopen_libs="-lsvld"
++else
++  { $as_echo "$as_me:${as_lineno-$LINENO}: checking for dld_link in -ldld" >&5
++$as_echo_n "checking for dld_link in -ldld... " >&6; }
++if ${ac_cv_lib_dld_dld_link+:} false; then :
++  $as_echo_n "(cached) " >&6
++else
++  ac_check_lib_save_LIBS=$LIBS
++LIBS="-ldld  $LIBS"
++cat confdefs.h - <<_ACEOF >conftest.$ac_ext
++/* end confdefs.h.  */
++
++/* Override any GCC internal prototype to avoid an error.
++   Use char because int might match the return type of a GCC
++   builtin and then its argument prototype would still apply.  */
++#ifdef __cplusplus
++extern "C"
++#endif
++char dld_link ();
++int
++main ()
++{
++return dld_link ();
++  ;
++  return 0;
++}
++_ACEOF
++if ac_fn_c_try_link "$LINENO"; then :
++  ac_cv_lib_dld_dld_link=yes
++else
++  ac_cv_lib_dld_dld_link=no
++fi
++rm -f core conftest.err conftest.$ac_objext \
++    conftest$ac_exeext conftest.$ac_ext
++LIBS=$ac_check_lib_save_LIBS
++fi
++{ $as_echo "$as_me:${as_lineno-$LINENO}: result: $ac_cv_lib_dld_dld_link" >&5
++$as_echo "$ac_cv_lib_dld_dld_link" >&6; }
++if test "x$ac_cv_lib_dld_dld_link" = xyes; then :
++  lt_cv_dlopen="dld_link" lt_cv_dlopen_libs="-ldld"
++fi
++
++
++fi
++
++
++fi
++
++
++fi
++
++
++fi
++
++
++fi
++
++    ;;
++  esac
++
++  if test "x$lt_cv_dlopen" != xno; then
++    enable_dlopen=yes
++  else
++    enable_dlopen=no
++  fi
++
++  case $lt_cv_dlopen in
++  dlopen)
++    save_CPPFLAGS="$CPPFLAGS"
++    test "x$ac_cv_header_dlfcn_h" = xyes && CPPFLAGS="$CPPFLAGS -DHAVE_DLFCN_H"
++
++    save_LDFLAGS="$LDFLAGS"
++    wl=$lt_prog_compiler_wl eval LDFLAGS=\"\$LDFLAGS $export_dynamic_flag_spec\"
++
++    save_LIBS="$LIBS"
++    LIBS="$lt_cv_dlopen_libs $LIBS"
++
++    { $as_echo "$as_me:${as_lineno-$LINENO}: checking whether a program can dlopen itself" >&5
++$as_echo_n "checking whether a program can dlopen itself... " >&6; }
++if ${lt_cv_dlopen_self+:} false; then :
++  $as_echo_n "(cached) " >&6
++else
++  	  if test "$cross_compiling" = yes; then :
++  lt_cv_dlopen_self=cross
++else
++  lt_dlunknown=0; lt_dlno_uscore=1; lt_dlneed_uscore=2
++  lt_status=$lt_dlunknown
++  cat > conftest.$ac_ext <<_LT_EOF
++#line 12899 "configure"
++#include "confdefs.h"
++
++#if HAVE_DLFCN_H
++#include <dlfcn.h>
++#endif
++
++#include <stdio.h>
++
++#ifdef RTLD_GLOBAL
++#  define LT_DLGLOBAL		RTLD_GLOBAL
++#else
++#  ifdef DL_GLOBAL
++#    define LT_DLGLOBAL		DL_GLOBAL
++#  else
++#    define LT_DLGLOBAL		0
++#  endif
++#endif
++
++/* We may have to define LT_DLLAZY_OR_NOW in the command line if we
++   find out it does not work in some platform. */
++#ifndef LT_DLLAZY_OR_NOW
++#  ifdef RTLD_LAZY
++#    define LT_DLLAZY_OR_NOW		RTLD_LAZY
++#  else
++#    ifdef DL_LAZY
++#      define LT_DLLAZY_OR_NOW		DL_LAZY
++#    else
++#      ifdef RTLD_NOW
++#        define LT_DLLAZY_OR_NOW	RTLD_NOW
++#      else
++#        ifdef DL_NOW
++#          define LT_DLLAZY_OR_NOW	DL_NOW
++#        else
++#          define LT_DLLAZY_OR_NOW	0
++#        endif
++#      endif
++#    endif
++#  endif
++#endif
++
++/* When -fvisbility=hidden is used, assume the code has been annotated
++   correspondingly for the symbols needed.  */
++#if defined(__GNUC__) && (((__GNUC__ == 3) && (__GNUC_MINOR__ >= 3)) || (__GNUC__ > 3))
++void fnord () __attribute__((visibility("default")));
++#endif
++
++void fnord () { int i=42; }
++int main ()
++{
++  void *self = dlopen (0, LT_DLGLOBAL|LT_DLLAZY_OR_NOW);
++  int status = $lt_dlunknown;
++
++  if (self)
++    {
++      if (dlsym (self,"fnord"))       status = $lt_dlno_uscore;
++      else
++        {
++	  if (dlsym( self,"_fnord"))  status = $lt_dlneed_uscore;
++          else puts (dlerror ());
++	}
++      /* dlclose (self); */
++    }
++  else
++    puts (dlerror ());
++
++  return status;
++}
++_LT_EOF
++  if { { eval echo "\"\$as_me\":${as_lineno-$LINENO}: \"$ac_link\""; } >&5
++  (eval $ac_link) 2>&5
++  ac_status=$?
++  $as_echo "$as_me:${as_lineno-$LINENO}: \$? = $ac_status" >&5
++  test $ac_status = 0; } && test -s conftest${ac_exeext} 2>/dev/null; then
++    (./conftest; exit; ) >&5 2>/dev/null
++    lt_status=$?
++    case x$lt_status in
++      x$lt_dlno_uscore) lt_cv_dlopen_self=yes ;;
++      x$lt_dlneed_uscore) lt_cv_dlopen_self=yes ;;
++      x$lt_dlunknown|x*) lt_cv_dlopen_self=no ;;
++    esac
++  else :
++    # compilation failed
++    lt_cv_dlopen_self=no
++  fi
++fi
++rm -fr conftest*
++
++
++fi
++{ $as_echo "$as_me:${as_lineno-$LINENO}: result: $lt_cv_dlopen_self" >&5
++$as_echo "$lt_cv_dlopen_self" >&6; }
++
++    if test "x$lt_cv_dlopen_self" = xyes; then
++      wl=$lt_prog_compiler_wl eval LDFLAGS=\"\$LDFLAGS $lt_prog_compiler_static\"
++      { $as_echo "$as_me:${as_lineno-$LINENO}: checking whether a statically linked program can dlopen itself" >&5
++$as_echo_n "checking whether a statically linked program can dlopen itself... " >&6; }
++if ${lt_cv_dlopen_self_static+:} false; then :
++  $as_echo_n "(cached) " >&6
++else
++  	  if test "$cross_compiling" = yes; then :
++  lt_cv_dlopen_self_static=cross
++else
++  lt_dlunknown=0; lt_dlno_uscore=1; lt_dlneed_uscore=2
++  lt_status=$lt_dlunknown
++  cat > conftest.$ac_ext <<_LT_EOF
++#line 13005 "configure"
++#include "confdefs.h"
++
++#if HAVE_DLFCN_H
++#include <dlfcn.h>
++#endif
++
++#include <stdio.h>
++
++#ifdef RTLD_GLOBAL
++#  define LT_DLGLOBAL		RTLD_GLOBAL
++#else
++#  ifdef DL_GLOBAL
++#    define LT_DLGLOBAL		DL_GLOBAL
++#  else
++#    define LT_DLGLOBAL		0
++#  endif
++#endif
++
++/* We may have to define LT_DLLAZY_OR_NOW in the command line if we
++   find out it does not work in some platform. */
++#ifndef LT_DLLAZY_OR_NOW
++#  ifdef RTLD_LAZY
++#    define LT_DLLAZY_OR_NOW		RTLD_LAZY
++#  else
++#    ifdef DL_LAZY
++#      define LT_DLLAZY_OR_NOW		DL_LAZY
++#    else
++#      ifdef RTLD_NOW
++#        define LT_DLLAZY_OR_NOW	RTLD_NOW
++#      else
++#        ifdef DL_NOW
++#          define LT_DLLAZY_OR_NOW	DL_NOW
++#        else
++#          define LT_DLLAZY_OR_NOW	0
++#        endif
++#      endif
++#    endif
++#  endif
++#endif
++
++/* When -fvisbility=hidden is used, assume the code has been annotated
++   correspondingly for the symbols needed.  */
++#if defined(__GNUC__) && (((__GNUC__ == 3) && (__GNUC_MINOR__ >= 3)) || (__GNUC__ > 3))
++void fnord () __attribute__((visibility("default")));
++#endif
++
++void fnord () { int i=42; }
++int main ()
++{
++  void *self = dlopen (0, LT_DLGLOBAL|LT_DLLAZY_OR_NOW);
++  int status = $lt_dlunknown;
++
++  if (self)
++    {
++      if (dlsym (self,"fnord"))       status = $lt_dlno_uscore;
++      else
++        {
++	  if (dlsym( self,"_fnord"))  status = $lt_dlneed_uscore;
++          else puts (dlerror ());
++	}
++      /* dlclose (self); */
++    }
++  else
++    puts (dlerror ());
++
++  return status;
++}
++_LT_EOF
++  if { { eval echo "\"\$as_me\":${as_lineno-$LINENO}: \"$ac_link\""; } >&5
++  (eval $ac_link) 2>&5
++  ac_status=$?
++  $as_echo "$as_me:${as_lineno-$LINENO}: \$? = $ac_status" >&5
++  test $ac_status = 0; } && test -s conftest${ac_exeext} 2>/dev/null; then
++    (./conftest; exit; ) >&5 2>/dev/null
++    lt_status=$?
++    case x$lt_status in
++      x$lt_dlno_uscore) lt_cv_dlopen_self_static=yes ;;
++      x$lt_dlneed_uscore) lt_cv_dlopen_self_static=yes ;;
++      x$lt_dlunknown|x*) lt_cv_dlopen_self_static=no ;;
++    esac
++  else :
++    # compilation failed
++    lt_cv_dlopen_self_static=no
++  fi
++fi
++rm -fr conftest*
++
++
++fi
++{ $as_echo "$as_me:${as_lineno-$LINENO}: result: $lt_cv_dlopen_self_static" >&5
++$as_echo "$lt_cv_dlopen_self_static" >&6; }
++    fi
++
++    CPPFLAGS="$save_CPPFLAGS"
++    LDFLAGS="$save_LDFLAGS"
++    LIBS="$save_LIBS"
++    ;;
++  esac
++
++  case $lt_cv_dlopen_self in
++  yes|no) enable_dlopen_self=$lt_cv_dlopen_self ;;
++  *) enable_dlopen_self=unknown ;;
++  esac
++
++  case $lt_cv_dlopen_self_static in
++  yes|no) enable_dlopen_self_static=$lt_cv_dlopen_self_static ;;
++  *) enable_dlopen_self_static=unknown ;;
++  esac
++fi
++
++
++
++
++
++
++
++
++
++
++
++
++
++
++
++
++
++striplib=
++old_striplib=
++{ $as_echo "$as_me:${as_lineno-$LINENO}: checking whether stripping libraries is possible" >&5
++$as_echo_n "checking whether stripping libraries is possible... " >&6; }
++if test -n "$STRIP" && $STRIP -V 2>&1 | $GREP "GNU strip" >/dev/null; then
++  test -z "$old_striplib" && old_striplib="$STRIP --strip-debug"
++  test -z "$striplib" && striplib="$STRIP --strip-unneeded"
++  { $as_echo "$as_me:${as_lineno-$LINENO}: result: yes" >&5
++$as_echo "yes" >&6; }
++else
++# FIXME - insert some real tests, host_os isn't really good enough
++  case $host_os in
++  darwin*)
++    if test -n "$STRIP" ; then
++      striplib="$STRIP -x"
++      old_striplib="$STRIP -S"
++      { $as_echo "$as_me:${as_lineno-$LINENO}: result: yes" >&5
++$as_echo "yes" >&6; }
++    else
++      { $as_echo "$as_me:${as_lineno-$LINENO}: result: no" >&5
++$as_echo "no" >&6; }
++    fi
++    ;;
++  *)
++    { $as_echo "$as_me:${as_lineno-$LINENO}: result: no" >&5
++$as_echo "no" >&6; }
++    ;;
++  esac
++fi
++
++
++
++
++
++
++
++
++
++
++
++
++  # Report which library types will actually be built
++  { $as_echo "$as_me:${as_lineno-$LINENO}: checking if libtool supports shared libraries" >&5
++$as_echo_n "checking if libtool supports shared libraries... " >&6; }
++  { $as_echo "$as_me:${as_lineno-$LINENO}: result: $can_build_shared" >&5
++$as_echo "$can_build_shared" >&6; }
++
++  { $as_echo "$as_me:${as_lineno-$LINENO}: checking whether to build shared libraries" >&5
++$as_echo_n "checking whether to build shared libraries... " >&6; }
++  test "$can_build_shared" = "no" && enable_shared=no
++
++  # On AIX, shared libraries and static libraries use the same namespace, and
++  # are all built from PIC.
++  case $host_os in
++  aix3*)
++    test "$enable_shared" = yes && enable_static=no
++    if test -n "$RANLIB"; then
++      archive_cmds="$archive_cmds~\$RANLIB \$lib"
++      postinstall_cmds='$RANLIB $lib'
++    fi
++    ;;
++
++  aix[4-9]*)
++    if test "$host_cpu" != ia64 && test "$aix_use_runtimelinking" = no ; then
++      test "$enable_shared" = yes && enable_static=no
++    fi
++    ;;
++  esac
++  { $as_echo "$as_me:${as_lineno-$LINENO}: result: $enable_shared" >&5
++$as_echo "$enable_shared" >&6; }
++
++  { $as_echo "$as_me:${as_lineno-$LINENO}: checking whether to build static libraries" >&5
++$as_echo_n "checking whether to build static libraries... " >&6; }
++  # Make sure either enable_shared or enable_static is yes.
++  test "$enable_shared" = yes || enable_static=yes
++  { $as_echo "$as_me:${as_lineno-$LINENO}: result: $enable_static" >&5
++$as_echo "$enable_static" >&6; }
++
++
++
++
++fi
++ac_ext=c
++ac_cpp='$CPP $CPPFLAGS'
++ac_compile='$CC -c $CFLAGS $CPPFLAGS conftest.$ac_ext >&5'
++ac_link='$CC -o conftest$ac_exeext $CFLAGS $CPPFLAGS $LDFLAGS conftest.$ac_ext $LIBS >&5'
++ac_compiler_gnu=$ac_cv_c_compiler_gnu
++
++CC="$lt_save_CC"
++
++
++
++
++
++
++
++
++
++
++
++
++
++        ac_config_commands="$ac_config_commands libtool"
++
++
++
++
++# Only expand once:
++
++
++
++
++. ${srcdir}/../../bfd/configure.host
++
++
++
++
++{ $as_echo "$as_me:${as_lineno-$LINENO}: checking whether to enable maintainer-specific portions of Makefiles" >&5
++$as_echo_n "checking whether to enable maintainer-specific portions of Makefiles... " >&6; }
++    # Check whether --enable-maintainer-mode was given.
++if test "${enable_maintainer_mode+set}" = set; then :
++  enableval=$enable_maintainer_mode; USE_MAINTAINER_MODE=$enableval
++else
++  USE_MAINTAINER_MODE=no
++fi
++
++  { $as_echo "$as_me:${as_lineno-$LINENO}: result: $USE_MAINTAINER_MODE" >&5
++$as_echo "$USE_MAINTAINER_MODE" >&6; }
++   if test $USE_MAINTAINER_MODE = yes; then
++  MAINTAINER_MODE_TRUE=
++  MAINTAINER_MODE_FALSE='#'
++else
++  MAINTAINER_MODE_TRUE='#'
++  MAINTAINER_MODE_FALSE=
++fi
++
++  MAINT=$MAINTAINER_MODE_TRUE
++
++
++
++
++{ $as_echo "$as_me:${as_lineno-$LINENO}: checking for sim debug setting" >&5
++$as_echo_n "checking for sim debug setting... " >&6; }
++sim_debug="0"
++# Check whether --enable-sim-debug was given.
++if test "${enable_sim_debug+set}" = set; then :
++  enableval=$enable_sim_debug; case "${enableval}" in
++  yes) sim_debug="7";;
++  no)  sim_debug="0";;
++  *)   sim_debug="($enableval)";;
++esac
++fi
++if test "$sim_debug" != "0"; then
++
++cat >>confdefs.h <<_ACEOF
++#define DEBUG $sim_debug
++_ACEOF
++
++fi
++
++cat >>confdefs.h <<_ACEOF
++#define WITH_DEBUG $sim_debug
++_ACEOF
++
++{ $as_echo "$as_me:${as_lineno-$LINENO}: result: $sim_debug" >&5
++$as_echo "$sim_debug" >&6; }
++
++
++{ $as_echo "$as_me:${as_lineno-$LINENO}: checking for sim stdio debug behavior" >&5
++$as_echo_n "checking for sim stdio debug behavior... " >&6; }
++sim_stdio="0"
++# Check whether --enable-sim-stdio was given.
++if test "${enable_sim_stdio+set}" = set; then :
++  enableval=$enable_sim_stdio; case "${enableval}" in
++  yes)	sim_stdio="DO_USE_STDIO";;
++  no)	sim_stdio="DONT_USE_STDIO";;
++  *)	as_fn_error $? "Unknown value $enableval passed to --enable-sim-stdio" "$LINENO" 5;;
++esac
++fi
++
++cat >>confdefs.h <<_ACEOF
++#define WITH_STDIO $sim_stdio
++_ACEOF
++
++{ $as_echo "$as_me:${as_lineno-$LINENO}: result: $sim_stdio" >&5
++$as_echo "$sim_stdio" >&6; }
++
++
++{ $as_echo "$as_me:${as_lineno-$LINENO}: checking for sim trace settings" >&5
++$as_echo_n "checking for sim trace settings... " >&6; }
++sim_trace="~TRACE_debug"
++# Check whether --enable-sim-trace was given.
++if test "${enable_sim_trace+set}" = set; then :
++  enableval=$enable_sim_trace; case "${enableval}" in
++  yes)	sim_trace="-1";;
++  no)	sim_trace="0";;
++  [-0-9]*)
++	sim_trace="'(${enableval})'";;
++  [[:lower:]]*)
++	sim_trace=""
++	for x in `echo "$enableval" | sed -e "s/,/ /g"`; do
++	  if test x"$sim_trace" = x; then
++	    sim_trace="(TRACE_$x"
++	  else
++	    sim_trace="${sim_trace}|TRACE_$x"
++	  fi
++	done
++	sim_trace="$sim_trace)" ;;
++esac
++fi
++
++cat >>confdefs.h <<_ACEOF
++#define WITH_TRACE $sim_trace
++_ACEOF
++
++{ $as_echo "$as_me:${as_lineno-$LINENO}: result: $sim_trace" >&5
++$as_echo "$sim_trace" >&6; }
++
++
++{ $as_echo "$as_me:${as_lineno-$LINENO}: checking for sim profile settings" >&5
++$as_echo_n "checking for sim profile settings... " >&6; }
++profile="1"
++sim_profile="-1"
++# Check whether --enable-sim-profile was given.
++if test "${enable_sim_profile+set}" = set; then :
++  enableval=$enable_sim_profile; case "${enableval}" in
++  yes)	profile="1" sim_profile="-1";;
++  no)	profile="0" sim_profile="0";;
++  [-0-9]*)
++	profile="(${enableval})" sim_profile="(${enableval})";;
++  [a-z]*)
++    profile="1"
++	sim_profile=""
++	for x in `echo "$enableval" | sed -e "s/,/ /g"`; do
++	  if test x"$sim_profile" = x; then
++	    sim_profile="(PROFILE_$x"
++	  else
++	    sim_profile="${sim_profile}|PROFILE_$x"
++	  fi
++	done
++	sim_profile="$sim_profile)" ;;
++esac
++fi
++
++cat >>confdefs.h <<_ACEOF
++#define PROFILE $profile
++_ACEOF
++
++
++cat >>confdefs.h <<_ACEOF
++#define WITH_PROFILE $sim_profile
++_ACEOF
++
++{ $as_echo "$as_me:${as_lineno-$LINENO}: result: $sim_profile" >&5
++$as_echo "$sim_profile" >&6; }
++
++
++
++{ $as_echo "$as_me:${as_lineno-$LINENO}: checking whether to enable sim asserts" >&5
++$as_echo_n "checking whether to enable sim asserts... " >&6; }
++sim_assert="1"
++# Check whether --enable-sim-assert was given.
++if test "${enable_sim_assert+set}" = set; then :
++  enableval=$enable_sim_assert; case "${enableval}" in
++  yes)	sim_assert="1";;
++  no)	sim_assert="0";;
++  *)	as_fn_error $? "--enable-sim-assert does not take a value" "$LINENO" 5;;
++esac
++fi
++
++cat >>confdefs.h <<_ACEOF
++#define WITH_ASSERT $sim_assert
++_ACEOF
++
++{ $as_echo "$as_me:${as_lineno-$LINENO}: result: $sim_assert" >&5
++$as_echo "$sim_assert" >&6; }
++
++
++{ $as_echo "$as_me:${as_lineno-$LINENO}: checking default sim environment setting" >&5
++$as_echo_n "checking default sim environment setting... " >&6; }
++sim_environment="ALL_ENVIRONMENT"
++# Check whether --enable-sim-environment was given.
++if test "${enable_sim_environment+set}" = set; then :
++  enableval=$enable_sim_environment; case "${enableval}" in
++  all | ALL)             sim_environment="ALL_ENVIRONMENT";;
++  user | USER)           sim_environment="USER_ENVIRONMENT";;
++  virtual | VIRTUAL)     sim_environment="VIRTUAL_ENVIRONMENT";;
++  operating | OPERATING) sim_environment="OPERATING_ENVIRONMENT";;
++  *)   as_fn_error $? "Unknown value $enableval passed to --enable-sim-environment" "$LINENO" 5;;
++esac
++fi
++
++cat >>confdefs.h <<_ACEOF
++#define WITH_ENVIRONMENT $sim_environment
++_ACEOF
++
++{ $as_echo "$as_me:${as_lineno-$LINENO}: result: $sim_environment" >&5
++$as_echo "$sim_environment" >&6; }
++
++
++sim_inline="-DDEFAULT_INLINE=0"
++# Check whether --enable-sim-inline was given.
++if test "${enable_sim_inline+set}" = set; then :
++  enableval=$enable_sim_inline; sim_inline=""
++case "$enableval" in
++  no)		sim_inline="-DDEFAULT_INLINE=0";;
++  0)		sim_inline="-DDEFAULT_INLINE=0";;
++  yes | 2)	sim_inline="-DDEFAULT_INLINE=ALL_C_INLINE";;
++  1)		sim_inline="-DDEFAULT_INLINE=INLINE_LOCALS";;
++  *) for x in `echo "$enableval" | sed -e "s/,/ /g"`; do
++       new_flag=""
++       case "$x" in
++	 *_INLINE=*)	new_flag="-D$x";;
++	 *=*)		new_flag=`echo "$x" | sed -e "s/=/_INLINE=/" -e "s/^/-D/"`;;
++	 *_INLINE)	new_flag="-D$x=ALL_C_INLINE";;
++	 *)		new_flag="-D$x""_INLINE=ALL_C_INLINE";;
++       esac
++       if test x"$sim_inline" = x""; then
++	 sim_inline="$new_flag"
++       else
++	 sim_inline="$sim_inline $new_flag"
++       fi
++     done;;
++esac
++if test x"$silent" != x"yes" && test x"$sim_inline" != x""; then
++  echo "Setting inline flags = $sim_inline" 6>&1
++fi
++fi
++
++
++
++
++# Check whether --with-pkgversion was given.
++if test "${with_pkgversion+set}" = set; then :
++  withval=$with_pkgversion; case "$withval" in
++      yes) as_fn_error $? "package version not specified" "$LINENO" 5 ;;
++      no)  PKGVERSION= ;;
++      *)   PKGVERSION="($withval) " ;;
++     esac
++else
++  PKGVERSION="(SIM) "
++
++fi
++
++
++
++
++
++# Check whether --with-bugurl was given.
++if test "${with_bugurl+set}" = set; then :
++  withval=$with_bugurl; case "$withval" in
++      yes) as_fn_error $? "bug URL not specified" "$LINENO" 5 ;;
++      no)  BUGURL=
++	   ;;
++      *)   BUGURL="$withval"
++	   ;;
++     esac
++else
++  BUGURL="http://www.gnu.org/software/gdb/bugs/"
++
++fi
++
++  case ${BUGURL} in
++  "")
++    REPORT_BUGS_TO=
++    REPORT_BUGS_TEXI=
++    ;;
++  *)
++    REPORT_BUGS_TO="<$BUGURL>"
++    REPORT_BUGS_TEXI=@uref{`echo "$BUGURL" | sed 's/@/@@/g'`}
++    ;;
++  esac;
++
++
++
++
++cat >>confdefs.h <<_ACEOF
++#define PKGVERSION "$PKGVERSION"
++_ACEOF
++
++
++cat >>confdefs.h <<_ACEOF
++#define REPORT_BUGS_TO "$REPORT_BUGS_TO"
++_ACEOF
++
++
++{ $as_echo "$as_me:${as_lineno-$LINENO}: checking return type of signal handlers" >&5
++$as_echo_n "checking return type of signal handlers... " >&6; }
++if ${ac_cv_type_signal+:} false; then :
++  $as_echo_n "(cached) " >&6
++else
++  cat confdefs.h - <<_ACEOF >conftest.$ac_ext
++/* end confdefs.h.  */
++#include <sys/types.h>
++#include <signal.h>
++
++int
++main ()
++{
++return *(signal (0, 0)) (0) == 1;
++  ;
++  return 0;
++}
++_ACEOF
++if ac_fn_c_try_compile "$LINENO"; then :
++  ac_cv_type_signal=int
++else
++  ac_cv_type_signal=void
++fi
++rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext
++fi
++{ $as_echo "$as_me:${as_lineno-$LINENO}: result: $ac_cv_type_signal" >&5
++$as_echo "$ac_cv_type_signal" >&6; }
++
++cat >>confdefs.h <<_ACEOF
++#define RETSIGTYPE $ac_cv_type_signal
++_ACEOF
++
++
++
++
++
++
++
++
++wire_endian="LITTLE"
++default_endian=""
++# Check whether --enable-sim-endian was given.
++if test "${enable_sim_endian+set}" = set; then :
++  enableval=$enable_sim_endian; case "${enableval}" in
++  b*|B*) sim_endian="-DWITH_TARGET_BYTE_ORDER=BFD_ENDIAN_BIG";;
++  l*|L*) sim_endian="-DWITH_TARGET_BYTE_ORDER=BFD_ENDIAN_LITTLE";;
++  yes)	 if test x"$wire_endian" != x; then
++	   sim_endian="-DWITH_TARGET_BYTE_ORDER=BFD_ENDIAN_${wire_endian}"
++	 else
++	  if test x"$default_endian" != x; then
++	     sim_endian="-DWITH_TARGET_BYTE_ORDER=BFD_ENDIAN_${default_endian}"
++	   else
++	     echo "No hard-wired endian for target $target" 1>&6
++	     sim_endian="-DWITH_TARGET_BYTE_ORDER=BFD_ENDIAN_UNKNOWN"
++	   fi
++	 fi;;
++  no)	 if test x"$default_endian" != x; then
++	   sim_endian="-DWITH_DEFAULT_TARGET_BYTE_ORDER=BFD_ENDIAN_${default_endian}"
++	 else
++	   if test x"$wire_endian" != x; then
++	     sim_endian="-DWITH_DEFAULT_TARGET_BYTE_ORDER=BFD_ENDIAN_${wire_endian}"
++	   else
++	     echo "No default endian for target $target" 1>&6
++	     sim_endian="-DWITH_DEFAULT_TARGET_BYTE_ORDER=BFD_ENDIAN_UNKNOWN"
++	   fi
++	 fi;;
++  *)	 as_fn_error $? "\"Unknown value $enableval for --enable-sim-endian\"" "$LINENO" 5; sim_endian="";;
++esac
++if test x"$silent" != x"yes" && test x"$sim_endian" != x""; then
++  echo "Setting endian flags = $sim_endian" 6>&1
++fi
++else
++  if test x"$default_endian" != x; then
++  sim_endian="-DWITH_DEFAULT_TARGET_BYTE_ORDER=BFD_ENDIAN_${default_endian}"
++else
++  if test x"$wire_endian" != x; then
++    sim_endian="-DWITH_TARGET_BYTE_ORDER=BFD_ENDIAN_${wire_endian}"
++  else
++    sim_endian=
++  fi
++fi
++fi
++
++wire_alignment="NONSTRICT_ALIGNMENT"
++default_alignment=""
++
++# Check whether --enable-sim-alignment was given.
++if test "${enable_sim_alignment+set}" = set; then :
++  enableval=$enable_sim_alignment; case "${enableval}" in
++  strict | STRICT)       sim_alignment="-DWITH_ALIGNMENT=STRICT_ALIGNMENT";;
++  nonstrict | NONSTRICT) sim_alignment="-DWITH_ALIGNMENT=NONSTRICT_ALIGNMENT";;
++  forced | FORCED)       sim_alignment="-DWITH_ALIGNMENT=FORCED_ALIGNMENT";;
++  yes) if test x"$wire_alignment" != x; then
++	 sim_alignment="-DWITH_ALIGNMENT=${wire_alignment}"
++       else
++         if test x"$default_alignment" != x; then
++           sim_alignment="-DWITH_ALIGNMENT=${default_alignment}"
++         else
++	   echo "No hard-wired alignment for target $target" 1>&6
++	   sim_alignment="-DWITH_ALIGNMENT=0"
++         fi
++       fi;;
++  no)  if test x"$default_alignment" != x; then
++	 sim_alignment="-DWITH_DEFAULT_ALIGNMENT=${default_alignment}"
++       else
++         if test x"$wire_alignment" != x; then
++	   sim_alignment="-DWITH_DEFAULT_ALIGNMENT=${wire_alignment}"
++         else
++           echo "No default alignment for target $target" 1>&6
++           sim_alignment="-DWITH_DEFAULT_ALIGNMENT=0"
++         fi
++       fi;;
++  *)   as_fn_error $? "\"Unknown value $enableval passed to --enable-sim-alignment\"" "$LINENO" 5; sim_alignment="";;
++esac
++if test x"$silent" != x"yes" && test x"$sim_alignment" != x""; then
++  echo "Setting alignment flags = $sim_alignment" 6>&1
++fi
++else
++  if test x"$default_alignment" != x; then
++  sim_alignment="-DWITH_DEFAULT_ALIGNMENT=${default_alignment}"
++else
++  if test x"$wire_alignment" != x; then
++    sim_alignment="-DWITH_ALIGNMENT=${wire_alignment}"
++  else
++    sim_alignment=
++  fi
++fi
++fi
++
++
++{ $as_echo "$as_me:${as_lineno-$LINENO}: checking default sim environment setting" >&5
++$as_echo_n "checking default sim environment setting... " >&6; }
++sim_environment="ALL_ENVIRONMENT"
++# Check whether --enable-sim-environment was given.
++if test "${enable_sim_environment+set}" = set; then :
++  enableval=$enable_sim_environment; case "${enableval}" in
++  all | ALL)             sim_environment="ALL_ENVIRONMENT";;
++  user | USER)           sim_environment="USER_ENVIRONMENT";;
++  virtual | VIRTUAL)     sim_environment="VIRTUAL_ENVIRONMENT";;
++  operating | OPERATING) sim_environment="OPERATING_ENVIRONMENT";;
++  *)   as_fn_error $? "Unknown value $enableval passed to --enable-sim-environment" "$LINENO" 5;;
++esac
++fi
++
++cat >>confdefs.h <<_ACEOF
++#define WITH_ENVIRONMENT $sim_environment
++_ACEOF
++
++{ $as_echo "$as_me:${as_lineno-$LINENO}: result: $sim_environment" >&5
++$as_echo "$sim_environment" >&6; }
++
++
++sim_inline="-DDEFAULT_INLINE=0"
++# Check whether --enable-sim-inline was given.
++if test "${enable_sim_inline+set}" = set; then :
++  enableval=$enable_sim_inline; sim_inline=""
++case "$enableval" in
++  no)		sim_inline="-DDEFAULT_INLINE=0";;
++  0)		sim_inline="-DDEFAULT_INLINE=0";;
++  yes | 2)	sim_inline="-DDEFAULT_INLINE=ALL_C_INLINE";;
++  1)		sim_inline="-DDEFAULT_INLINE=INLINE_LOCALS";;
++  *) for x in `echo "$enableval" | sed -e "s/,/ /g"`; do
++       new_flag=""
++       case "$x" in
++	 *_INLINE=*)	new_flag="-D$x";;
++	 *=*)		new_flag=`echo "$x" | sed -e "s/=/_INLINE=/" -e "s/^/-D/"`;;
++	 *_INLINE)	new_flag="-D$x=ALL_C_INLINE";;
++	 *)		new_flag="-D$x""_INLINE=ALL_C_INLINE";;
++       esac
++       if test x"$sim_inline" = x""; then
++	 sim_inline="$new_flag"
++       else
++	 sim_inline="$sim_inline $new_flag"
++       fi
++     done;;
++esac
++if test x"$silent" != x"yes" && test x"$sim_inline" != x""; then
++  echo "Setting inline flags = $sim_inline" 6>&1
++fi
++fi
++
++
++# Check whether --enable-werror was given.
++if test "${enable_werror+set}" = set; then :
++  enableval=$enable_werror; case "${enableval}" in
++     yes | y) ERROR_ON_WARNING="yes" ;;
++     no | n)  ERROR_ON_WARNING="no" ;;
++     *) as_fn_error $? "bad value ${enableval} for --enable-werror" "$LINENO" 5 ;;
++   esac
++fi
++
++
++# Enable -Werror by default when using gcc
++if test "${GCC}" = yes -a -z "${ERROR_ON_WARNING}" ; then
++    ERROR_ON_WARNING=yes
++fi
++
++WERROR_CFLAGS=""
++if test "${ERROR_ON_WARNING}" = yes ; then
++# NOTE: Disabled in the sim dir due to most sims generating warnings.
++#    WERROR_CFLAGS="-Werror"
++     true
++fi
++
++build_warnings="-Wall -Wdeclaration-after-statement -Wpointer-arith \
++-Wpointer-sign \
++-Wno-unused -Wunused-value -Wunused-function \
++-Wno-switch -Wno-char-subscripts -Wmissing-prototypes
++-Wdeclaration-after-statement -Wempty-body -Wmissing-parameter-type \
++-Wold-style-declaration -Wold-style-definition"
++
++# Enable -Wno-format by default when using gcc on mingw since many
++# GCC versions complain about %I64.
++case "${host}" in
++  *-*-mingw32*) build_warnings="$build_warnings -Wno-format" ;;
++  *) build_warnings="$build_warnings -Wformat-nonliteral" ;;
++esac
++
++# Check whether --enable-build-warnings was given.
++if test "${enable_build_warnings+set}" = set; then :
++  enableval=$enable_build_warnings; case "${enableval}" in
++  yes)	;;
++  no)	build_warnings="-w";;
++  ,*)   t=`echo "${enableval}" | sed -e "s/,/ /g"`
++        build_warnings="${build_warnings} ${t}";;
++  *,)   t=`echo "${enableval}" | sed -e "s/,/ /g"`
++        build_warnings="${t} ${build_warnings}";;
++  *)    build_warnings=`echo "${enableval}" | sed -e "s/,/ /g"`;;
++esac
++if test x"$silent" != x"yes" && test x"$build_warnings" != x""; then
++  echo "Setting compiler warning flags = $build_warnings" 6>&1
++fi
++fi
++# Check whether --enable-sim-build-warnings was given.
++if test "${enable_sim_build_warnings+set}" = set; then :
++  enableval=$enable_sim_build_warnings; case "${enableval}" in
++  yes)	;;
++  no)	build_warnings="-w";;
++  ,*)   t=`echo "${enableval}" | sed -e "s/,/ /g"`
++        build_warnings="${build_warnings} ${t}";;
++  *,)   t=`echo "${enableval}" | sed -e "s/,/ /g"`
++        build_warnings="${t} ${build_warnings}";;
++  *)    build_warnings=`echo "${enableval}" | sed -e "s/,/ /g"`;;
++esac
++if test x"$silent" != x"yes" && test x"$build_warnings" != x""; then
++  echo "Setting GDB specific compiler warning flags = $build_warnings" 6>&1
++fi
++fi
++WARN_CFLAGS=""
++if test "x${build_warnings}" != x -a "x$GCC" = xyes
++then
++    { $as_echo "$as_me:${as_lineno-$LINENO}: checking compiler warning flags" >&5
++$as_echo_n "checking compiler warning flags... " >&6; }
++    # Separate out the -Werror flag as some files just cannot be
++    # compiled with it enabled.
++    for w in ${build_warnings}; do
++	case $w in
++	-Werr*) WERROR_CFLAGS=-Werror ;;
++	*) # Check that GCC accepts it
++	    saved_CFLAGS="$CFLAGS"
++	    CFLAGS="$CFLAGS $w"
++	    cat confdefs.h - <<_ACEOF >conftest.$ac_ext
++/* end confdefs.h.  */
++
++int
++main ()
++{
++
++  ;
++  return 0;
++}
++_ACEOF
++if ac_fn_c_try_compile "$LINENO"; then :
++  WARN_CFLAGS="${WARN_CFLAGS} $w"
++fi
++rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext
++	    CFLAGS="$saved_CFLAGS"
++	esac
++    done
++    { $as_echo "$as_me:${as_lineno-$LINENO}: result: ${WARN_CFLAGS} ${WERROR_CFLAGS}" >&5
++$as_echo "${WARN_CFLAGS} ${WERROR_CFLAGS}" >&6; }
++fi
++
++
++# Select the default model for the target.
++riscv_model=
++case "${target}" in
++riscv32*) riscv_model="RV32G" ;;
++riscv*) riscv_model="RV64G" ;;
++esac
++
++default_sim_default_model="${riscv_model}"
++# Check whether --enable-sim-default-model was given.
++if test "${enable_sim_default_model+set}" = set; then :
++  enableval=$enable_sim_default_model; case "${enableval}" in
++  yes|no) as_fn_error $? "\"Missing argument to --enable-sim-default-model\"" "$LINENO" 5;;
++  *)	sim_default_model="-DWITH_DEFAULT_MODEL='\"${enableval}\"'";;
++esac
++if test x"$silent" != x"yes" && test x"$sim_default_model" != x""; then
++  echo "Setting default model = $sim_default_model" 6>&1
++fi
++else
++  sim_default_model="-DWITH_DEFAULT_MODEL='\"${default_sim_default_model}\"'"
++fi
++
++
++
++# Select the bitsize of the target.
++riscv_addr_bitsize=
++case "${target}" in
++riscv32*) riscv_addr_bitsize=32 ;;
++riscv*) riscv_addr_bitsize=64 ;;
++esac
++wire_word_bitsize="$riscv_addr_bitsize"
++wire_word_msb=""
++wire_address_bitsize=""
++wire_cell_bitsize=""
++# Check whether --enable-sim-bitsize was given.
++if test "${enable_sim_bitsize+set}" = set; then :
++  enableval=$enable_sim_bitsize; sim_bitsize=
++case "${enableval}" in
++  64,63 | 64,63,* ) sim_bitsize="-DWITH_TARGET_WORD_BITSIZE=64 -DWITH_TARGET_WORD_MSB=63";;
++  32,31 | 32,31,* ) sim_bitsize="-DWITH_TARGET_WORD_BITSIZE=32 -DWITH_TARGET_WORD_MSB=31";;
++  64,0 | 64,0,* ) sim_bitsize="-DWITH_TARGET_WORD_BITSIZE=32 -DWITH_TARGET_WORD_MSB=0";;
++  32,0 | 64,0,* ) sim_bitsize="-DWITH_TARGET_WORD_BITSIZE=32 -DWITH_TARGET_WORD_MSB=0";;
++  32) if test x"$wire_word_msb" != x -a x"$wire_word_msb" != x0; then
++        sim_bitsize="-DWITH_TARGET_WORD_BITSIZE=32 -DWITH_TARGET_WORD_MSB=31"
++      else
++        sim_bitsize="-DWITH_TARGET_WORD_BITSIZE=32 -DWITH_TARGET_WORD_MSB=0"
++      fi ;;
++  64) if test x"$wire_word_msb" != x -a x"$wire_word_msb" != x0; then
++        sim_bitsize="-DWITH_TARGET_WORD_BITSIZE=64 -DWITH_TARGET_WORD_MSB=63"
++      else
++        sim_bitsize="-DWITH_TARGET_WORD_BITSIZE=64 -DWITH_TARGET_WORD_MSB=0"
++      fi ;;
++  *)  as_fn_error $? "\"--enable-sim-bitsize was given $enableval.  Expected 32 or 64\"" "$LINENO" 5 ;;
++esac
++# address bitsize
++tmp=`echo "${enableval}" | sed -e "s/^[0-9]*,*[0-9]*,*//"`
++case x"${tmp}" in
++  x ) ;;
++  x32 | x32,* ) sim_bitsize="${sim_bitsize} -DWITH_TARGET_ADDRESS_BITSIZE=32" ;;
++  x64 | x64,* ) sim_bitsize="${sim_bitsize} -DWITH_TARGET_ADDRESS_BITSIZE=64" ;;
++  * ) as_fn_error $? "\"--enable-sim-bitsize was given address size $enableval.  Expected 32 or 64\"" "$LINENO" 5 ;;
++esac
++# cell bitsize
++tmp=`echo "${enableval}" | sed -e "s/^[0-9]*,*[0-9*]*,*[0-9]*,*//"`
++case x"${tmp}" in
++  x ) ;;
++  x32 | x32,* ) sim_bitsize="${sim_bitsize} -DWITH_TARGET_CELL_BITSIZE=32" ;;
++  x64 | x64,* ) sim_bitsize="${sim_bitsize} -DWITH_TARGET_CELL_BITSIZE=64" ;;
++  * ) as_fn_error $? "\"--enable-sim-bitsize was given cell size $enableval.  Expected 32 or 64\"" "$LINENO" 5 ;;
++esac
++if test x"$silent" != x"yes" && test x"$sim_bitsize" != x""; then
++  echo "Setting bitsize flags = $sim_bitsize" 6>&1
++fi
++else
++  sim_bitsize=""
++if test x"$wire_word_bitsize" != x; then
++  sim_bitsize="$sim_bitsize -DWITH_TARGET_WORD_BITSIZE=$wire_word_bitsize"
++fi
++if test x"$wire_word_msb" != x; then
++  sim_bitsize="$sim_bitsize -DWITH_TARGET_WORD_MSB=$wire_word_msb"
++fi
++if test x"$wire_address_bitsize" != x; then
++  sim_bitsize="$sim_bitsize -DWITH_TARGET_ADDRESS_BITSIZE=$wire_address_bitsize"
++fi
++if test x"$wire_cell_bitsize" != x; then
++  sim_bitsize="$sim_bitsize -DWITH_TARGET_CELL_BITSIZE=$wire_cell_bitsize"
++fi
++fi
++
++
++
++cgen_breaks=""
++if grep CGEN_MAINT $srcdir/Makefile.in >/dev/null; then
++cgen_breaks="break cgen_rtx_error";
++fi
++
++ac_config_files="$ac_config_files Makefile.sim:Makefile.in"
++
++ac_config_files="$ac_config_files Make-common.sim:../common/Make-common.in"
++
++ac_config_files="$ac_config_files .gdbinit:../common/gdbinit.in"
++
++ac_config_commands="$ac_config_commands Makefile"
++
++ac_config_commands="$ac_config_commands stamp-h"
++
++cat >confcache <<\_ACEOF
++# This file is a shell script that caches the results of configure
++# tests run on this system so they can be shared between configure
++# scripts and configure runs, see configure's option --config-cache.
++# It is not useful on other systems.  If it contains results you don't
++# want to keep, you may remove or edit it.
++#
++# config.status only pays attention to the cache file if you give it
++# the --recheck option to rerun configure.
++#
++# `ac_cv_env_foo' variables (set or unset) will be overridden when
++# loading this file, other *unset* `ac_cv_foo' will be assigned the
++# following values.
++
++_ACEOF
++
++# The following way of writing the cache mishandles newlines in values,
++# but we know of no workaround that is simple, portable, and efficient.
++# So, we kill variables containing newlines.
++# Ultrix sh set writes to stderr and can't be redirected directly,
++# and sets the high bit in the cache file unless we assign to the vars.
++(
++  for ac_var in `(set) 2>&1 | sed -n 's/^\([a-zA-Z_][a-zA-Z0-9_]*\)=.*/\1/p'`; do
++    eval ac_val=\$$ac_var
++    case $ac_val in #(
++    *${as_nl}*)
++      case $ac_var in #(
++      *_cv_*) { $as_echo "$as_me:${as_lineno-$LINENO}: WARNING: cache variable $ac_var contains a newline" >&5
++$as_echo "$as_me: WARNING: cache variable $ac_var contains a newline" >&2;} ;;
++      esac
++      case $ac_var in #(
++      _ | IFS | as_nl) ;; #(
++      BASH_ARGV | BASH_SOURCE) eval $ac_var= ;; #(
++      *) { eval $ac_var=; unset $ac_var;} ;;
++      esac ;;
++    esac
++  done
++
++  (set) 2>&1 |
++    case $as_nl`(ac_space=' '; set) 2>&1` in #(
++    *${as_nl}ac_space=\ *)
++      # `set' does not quote correctly, so add quotes: double-quote
++      # substitution turns \\\\ into \\, and sed turns \\ into \.
++      sed -n \
++	"s/'/'\\\\''/g;
++	  s/^\\([_$as_cr_alnum]*_cv_[_$as_cr_alnum]*\\)=\\(.*\\)/\\1='\\2'/p"
++      ;; #(
++    *)
++      # `set' quotes correctly as required by POSIX, so do not add quotes.
++      sed -n "/^[_$as_cr_alnum]*_cv_[_$as_cr_alnum]*=/p"
++      ;;
++    esac |
++    sort
++) |
++  sed '
++     /^ac_cv_env_/b end
++     t clear
++     :clear
++     s/^\([^=]*\)=\(.*[{}].*\)$/test "${\1+set}" = set || &/
++     t end
++     s/^\([^=]*\)=\(.*\)$/\1=${\1=\2}/
++     :end' >>confcache
++if diff "$cache_file" confcache >/dev/null 2>&1; then :; else
++  if test -w "$cache_file"; then
++    if test "x$cache_file" != "x/dev/null"; then
++      { $as_echo "$as_me:${as_lineno-$LINENO}: updating cache $cache_file" >&5
++$as_echo "$as_me: updating cache $cache_file" >&6;}
++      if test ! -f "$cache_file" || test -h "$cache_file"; then
++	cat confcache >"$cache_file"
++      else
++        case $cache_file in #(
++        */* | ?:*)
++	  mv -f confcache "$cache_file"$$ &&
++	  mv -f "$cache_file"$$ "$cache_file" ;; #(
++        *)
++	  mv -f confcache "$cache_file" ;;
++	esac
++      fi
++    fi
++  else
++    { $as_echo "$as_me:${as_lineno-$LINENO}: not updating unwritable cache $cache_file" >&5
++$as_echo "$as_me: not updating unwritable cache $cache_file" >&6;}
++  fi
++fi
++rm -f confcache
++
++test "x$prefix" = xNONE && prefix=$ac_default_prefix
++# Let make expand exec_prefix.
++test "x$exec_prefix" = xNONE && exec_prefix='${prefix}'
++
++DEFS=-DHAVE_CONFIG_H
++
++ac_libobjs=
++ac_ltlibobjs=
++U=
++for ac_i in : $LIBOBJS; do test "x$ac_i" = x: && continue
++  # 1. Remove the extension, and $U if already installed.
++  ac_script='s/\$U\././;s/\.o$//;s/\.obj$//'
++  ac_i=`$as_echo "$ac_i" | sed "$ac_script"`
++  # 2. Prepend LIBOBJDIR.  When used with automake>=1.10 LIBOBJDIR
++  #    will be set to the directory where LIBOBJS objects are built.
++  as_fn_append ac_libobjs " \${LIBOBJDIR}$ac_i\$U.$ac_objext"
++  as_fn_append ac_ltlibobjs " \${LIBOBJDIR}$ac_i"'$U.lo'
++done
++LIBOBJS=$ac_libobjs
++
++LTLIBOBJS=$ac_ltlibobjs
++
++
++
++if test -z "${GMAKE_TRUE}" && test -z "${GMAKE_FALSE}"; then
++  as_fn_error $? "conditional \"GMAKE\" was never defined.
++Usually this means the macro was only invoked conditionally." "$LINENO" 5
++fi
++if test -z "${PLUGINS_TRUE}" && test -z "${PLUGINS_FALSE}"; then
++  as_fn_error $? "conditional \"PLUGINS\" was never defined.
++Usually this means the macro was only invoked conditionally." "$LINENO" 5
++fi
++if test -z "${MAINTAINER_MODE_TRUE}" && test -z "${MAINTAINER_MODE_FALSE}"; then
++  as_fn_error $? "conditional \"MAINTAINER_MODE\" was never defined.
++Usually this means the macro was only invoked conditionally." "$LINENO" 5
++fi
++
++: "${CONFIG_STATUS=./config.status}"
++ac_write_fail=0
++ac_clean_files_save=$ac_clean_files
++ac_clean_files="$ac_clean_files $CONFIG_STATUS"
++{ $as_echo "$as_me:${as_lineno-$LINENO}: creating $CONFIG_STATUS" >&5
++$as_echo "$as_me: creating $CONFIG_STATUS" >&6;}
++as_write_fail=0
++cat >$CONFIG_STATUS <<_ASEOF || as_write_fail=1
++#! $SHELL
++# Generated by $as_me.
++# Run this file to recreate the current configuration.
++# Compiler output produced by configure, useful for debugging
++# configure, is in config.log if it exists.
++
++debug=false
++ac_cs_recheck=false
++ac_cs_silent=false
++
++SHELL=\${CONFIG_SHELL-$SHELL}
++export SHELL
++_ASEOF
++cat >>$CONFIG_STATUS <<\_ASEOF || as_write_fail=1
++## -------------------- ##
++## M4sh Initialization. ##
++## -------------------- ##
++
++# Be more Bourne compatible
++DUALCASE=1; export DUALCASE # for MKS sh
++if test -n "${ZSH_VERSION+set}" && (emulate sh) >/dev/null 2>&1; then :
++  emulate sh
++  NULLCMD=:
++  # Pre-4.2 versions of Zsh do word splitting on ${1+"$@"}, which
++  # is contrary to our usage.  Disable this feature.
++  alias -g '${1+"$@"}'='"$@"'
++  setopt NO_GLOB_SUBST
++else
++  case `(set -o) 2>/dev/null` in #(
++  *posix*) :
++    set -o posix ;; #(
++  *) :
++     ;;
++esac
++fi
++
++
++as_nl='
++'
++export as_nl
++# Printing a long string crashes Solaris 7 /usr/bin/printf.
++as_echo='\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\'
++as_echo=$as_echo$as_echo$as_echo$as_echo$as_echo
++as_echo=$as_echo$as_echo$as_echo$as_echo$as_echo$as_echo
++# Prefer a ksh shell builtin over an external printf program on Solaris,
++# but without wasting forks for bash or zsh.
++if test -z "$BASH_VERSION$ZSH_VERSION" \
++    && (test "X`print -r -- $as_echo`" = "X$as_echo") 2>/dev/null; then
++  as_echo='print -r --'
++  as_echo_n='print -rn --'
++elif (test "X`printf %s $as_echo`" = "X$as_echo") 2>/dev/null; then
++  as_echo='printf %s\n'
++  as_echo_n='printf %s'
++else
++  if test "X`(/usr/ucb/echo -n -n $as_echo) 2>/dev/null`" = "X-n $as_echo"; then
++    as_echo_body='eval /usr/ucb/echo -n "$1$as_nl"'
++    as_echo_n='/usr/ucb/echo -n'
++  else
++    as_echo_body='eval expr "X$1" : "X\\(.*\\)"'
++    as_echo_n_body='eval
++      arg=$1;
++      case $arg in #(
++      *"$as_nl"*)
++	expr "X$arg" : "X\\(.*\\)$as_nl";
++	arg=`expr "X$arg" : ".*$as_nl\\(.*\\)"`;;
++      esac;
++      expr "X$arg" : "X\\(.*\\)" | tr -d "$as_nl"
++    '
++    export as_echo_n_body
++    as_echo_n='sh -c $as_echo_n_body as_echo'
++  fi
++  export as_echo_body
++  as_echo='sh -c $as_echo_body as_echo'
++fi
++
++# The user is always right.
++if test "${PATH_SEPARATOR+set}" != set; then
++  PATH_SEPARATOR=:
++  (PATH='/bin;/bin'; FPATH=$PATH; sh -c :) >/dev/null 2>&1 && {
++    (PATH='/bin:/bin'; FPATH=$PATH; sh -c :) >/dev/null 2>&1 ||
++      PATH_SEPARATOR=';'
++  }
++fi
++
++
++# IFS
++# We need space, tab and new line, in precisely that order.  Quoting is
++# there to prevent editors from complaining about space-tab.
++# (If _AS_PATH_WALK were called with IFS unset, it would disable word
++# splitting by setting IFS to empty value.)
++IFS=" ""	$as_nl"
++
++# Find who we are.  Look in the path if we contain no directory separator.
++as_myself=
++case $0 in #((
++  *[\\/]* ) as_myself=$0 ;;
++  *) as_save_IFS=$IFS; IFS=$PATH_SEPARATOR
++for as_dir in $PATH
++do
++  IFS=$as_save_IFS
++  test -z "$as_dir" && as_dir=.
++    test -r "$as_dir/$0" && as_myself=$as_dir/$0 && break
++  done
++IFS=$as_save_IFS
++
++     ;;
++esac
++# We did not find ourselves, most probably we were run as `sh COMMAND'
++# in which case we are not to be found in the path.
++if test "x$as_myself" = x; then
++  as_myself=$0
++fi
++if test ! -f "$as_myself"; then
++  $as_echo "$as_myself: error: cannot find myself; rerun with an absolute file name" >&2
++  exit 1
++fi
++
++# Unset variables that we do not need and which cause bugs (e.g. in
++# pre-3.0 UWIN ksh).  But do not cause bugs in bash 2.01; the "|| exit 1"
++# suppresses any "Segmentation fault" message there.  '((' could
++# trigger a bug in pdksh 5.2.14.
++for as_var in BASH_ENV ENV MAIL MAILPATH
++do eval test x\${$as_var+set} = xset \
++  && ( (unset $as_var) || exit 1) >/dev/null 2>&1 && unset $as_var || :
++done
++PS1='$ '
++PS2='> '
++PS4='+ '
++
++# NLS nuisances.
++LC_ALL=C
++export LC_ALL
++LANGUAGE=C
++export LANGUAGE
++
++# CDPATH.
++(unset CDPATH) >/dev/null 2>&1 && unset CDPATH
++
++
++# as_fn_error STATUS ERROR [LINENO LOG_FD]
++# ----------------------------------------
++# Output "`basename $0`: error: ERROR" to stderr. If LINENO and LOG_FD are
++# provided, also output the error to LOG_FD, referencing LINENO. Then exit the
++# script with STATUS, using 1 if that was 0.
++as_fn_error ()
++{
++  as_status=$1; test $as_status -eq 0 && as_status=1
++  if test "$4"; then
++    as_lineno=${as_lineno-"$3"} as_lineno_stack=as_lineno_stack=$as_lineno_stack
++    $as_echo "$as_me:${as_lineno-$LINENO}: error: $2" >&$4
++  fi
++  $as_echo "$as_me: error: $2" >&2
++  as_fn_exit $as_status
++} # as_fn_error
++
++
++# as_fn_set_status STATUS
++# -----------------------
++# Set $? to STATUS, without forking.
++as_fn_set_status ()
++{
++  return $1
++} # as_fn_set_status
++
++# as_fn_exit STATUS
++# -----------------
++# Exit the shell with STATUS, even in a "trap 0" or "set -e" context.
++as_fn_exit ()
++{
++  set +e
++  as_fn_set_status $1
++  exit $1
++} # as_fn_exit
++
++# as_fn_unset VAR
++# ---------------
++# Portably unset VAR.
++as_fn_unset ()
++{
++  { eval $1=; unset $1;}
++}
++as_unset=as_fn_unset
++# as_fn_append VAR VALUE
++# ----------------------
++# Append the text in VALUE to the end of the definition contained in VAR. Take
++# advantage of any shell optimizations that allow amortized linear growth over
++# repeated appends, instead of the typical quadratic growth present in naive
++# implementations.
++if (eval "as_var=1; as_var+=2; test x\$as_var = x12") 2>/dev/null; then :
++  eval 'as_fn_append ()
++  {
++    eval $1+=\$2
++  }'
++else
++  as_fn_append ()
++  {
++    eval $1=\$$1\$2
++  }
++fi # as_fn_append
++
++# as_fn_arith ARG...
++# ------------------
++# Perform arithmetic evaluation on the ARGs, and store the result in the
++# global $as_val. Take advantage of shells that can avoid forks. The arguments
++# must be portable across $(()) and expr.
++if (eval "test \$(( 1 + 1 )) = 2") 2>/dev/null; then :
++  eval 'as_fn_arith ()
++  {
++    as_val=$(( $* ))
++  }'
++else
++  as_fn_arith ()
++  {
++    as_val=`expr "$@" || test $? -eq 1`
++  }
++fi # as_fn_arith
++
++
++if expr a : '\(a\)' >/dev/null 2>&1 &&
++   test "X`expr 00001 : '.*\(...\)'`" = X001; then
++  as_expr=expr
++else
++  as_expr=false
++fi
++
++if (basename -- /) >/dev/null 2>&1 && test "X`basename -- / 2>&1`" = "X/"; then
++  as_basename=basename
++else
++  as_basename=false
++fi
++
++if (as_dir=`dirname -- /` && test "X$as_dir" = X/) >/dev/null 2>&1; then
++  as_dirname=dirname
++else
++  as_dirname=false
++fi
++
++as_me=`$as_basename -- "$0" ||
++$as_expr X/"$0" : '.*/\([^/][^/]*\)/*$' \| \
++	 X"$0" : 'X\(//\)$' \| \
++	 X"$0" : 'X\(/\)' \| . 2>/dev/null ||
++$as_echo X/"$0" |
++    sed '/^.*\/\([^/][^/]*\)\/*$/{
++	    s//\1/
++	    q
++	  }
++	  /^X\/\(\/\/\)$/{
++	    s//\1/
++	    q
++	  }
++	  /^X\/\(\/\).*/{
++	    s//\1/
++	    q
++	  }
++	  s/.*/./; q'`
++
++# Avoid depending upon Character Ranges.
++as_cr_letters='abcdefghijklmnopqrstuvwxyz'
++as_cr_LETTERS='ABCDEFGHIJKLMNOPQRSTUVWXYZ'
++as_cr_Letters=$as_cr_letters$as_cr_LETTERS
++as_cr_digits='0123456789'
++as_cr_alnum=$as_cr_Letters$as_cr_digits
++
++ECHO_C= ECHO_N= ECHO_T=
++case `echo -n x` in #(((((
++-n*)
++  case `echo 'xy\c'` in
++  *c*) ECHO_T='	';;	# ECHO_T is single tab character.
++  xy)  ECHO_C='\c';;
++  *)   echo `echo ksh88 bug on AIX 6.1` > /dev/null
++       ECHO_T='	';;
++  esac;;
++*)
++  ECHO_N='-n';;
++esac
++
++rm -f conf$$ conf$$.exe conf$$.file
++if test -d conf$$.dir; then
++  rm -f conf$$.dir/conf$$.file
++else
++  rm -f conf$$.dir
++  mkdir conf$$.dir 2>/dev/null
++fi
++if (echo >conf$$.file) 2>/dev/null; then
++  if ln -s conf$$.file conf$$ 2>/dev/null; then
++    as_ln_s='ln -s'
++    # ... but there are two gotchas:
++    # 1) On MSYS, both `ln -s file dir' and `ln file dir' fail.
++    # 2) DJGPP < 2.04 has no symlinks; `ln -s' creates a wrapper executable.
++    # In both cases, we have to default to `cp -pR'.
++    ln -s conf$$.file conf$$.dir 2>/dev/null && test ! -f conf$$.exe ||
++      as_ln_s='cp -pR'
++  elif ln conf$$.file conf$$ 2>/dev/null; then
++    as_ln_s=ln
++  else
++    as_ln_s='cp -pR'
++  fi
++else
++  as_ln_s='cp -pR'
++fi
++rm -f conf$$ conf$$.exe conf$$.dir/conf$$.file conf$$.file
++rmdir conf$$.dir 2>/dev/null
++
++
++# as_fn_mkdir_p
++# -------------
++# Create "$as_dir" as a directory, including parents if necessary.
++as_fn_mkdir_p ()
++{
++
++  case $as_dir in #(
++  -*) as_dir=./$as_dir;;
++  esac
++  test -d "$as_dir" || eval $as_mkdir_p || {
++    as_dirs=
++    while :; do
++      case $as_dir in #(
++      *\'*) as_qdir=`$as_echo "$as_dir" | sed "s/'/'\\\\\\\\''/g"`;; #'(
++      *) as_qdir=$as_dir;;
++      esac
++      as_dirs="'$as_qdir' $as_dirs"
++      as_dir=`$as_dirname -- "$as_dir" ||
++$as_expr X"$as_dir" : 'X\(.*[^/]\)//*[^/][^/]*/*$' \| \
++	 X"$as_dir" : 'X\(//\)[^/]' \| \
++	 X"$as_dir" : 'X\(//\)$' \| \
++	 X"$as_dir" : 'X\(/\)' \| . 2>/dev/null ||
++$as_echo X"$as_dir" |
++    sed '/^X\(.*[^/]\)\/\/*[^/][^/]*\/*$/{
++	    s//\1/
++	    q
++	  }
++	  /^X\(\/\/\)[^/].*/{
++	    s//\1/
++	    q
++	  }
++	  /^X\(\/\/\)$/{
++	    s//\1/
++	    q
++	  }
++	  /^X\(\/\).*/{
++	    s//\1/
++	    q
++	  }
++	  s/.*/./; q'`
++      test -d "$as_dir" && break
++    done
++    test -z "$as_dirs" || eval "mkdir $as_dirs"
++  } || test -d "$as_dir" || as_fn_error $? "cannot create directory $as_dir"
++
++
++} # as_fn_mkdir_p
++if mkdir -p . 2>/dev/null; then
++  as_mkdir_p='mkdir -p "$as_dir"'
++else
++  test -d ./-p && rmdir ./-p
++  as_mkdir_p=false
++fi
++
++
++# as_fn_executable_p FILE
++# -----------------------
++# Test if FILE is an executable regular file.
++as_fn_executable_p ()
++{
++  test -f "$1" && test -x "$1"
++} # as_fn_executable_p
++as_test_x='test -x'
++as_executable_p=as_fn_executable_p
++
++# Sed expression to map a string onto a valid CPP name.
++as_tr_cpp="eval sed 'y%*$as_cr_letters%P$as_cr_LETTERS%;s%[^_$as_cr_alnum]%_%g'"
++
++# Sed expression to map a string onto a valid variable name.
++as_tr_sh="eval sed 'y%*+%pp%;s%[^_$as_cr_alnum]%_%g'"
++
++
++exec 6>&1
++## ----------------------------------- ##
++## Main body of $CONFIG_STATUS script. ##
++## ----------------------------------- ##
++_ASEOF
++test $as_write_fail = 0 && chmod +x $CONFIG_STATUS || ac_write_fail=1
++
++cat >>$CONFIG_STATUS <<\_ACEOF || ac_write_fail=1
++# Save the log message, to keep $0 and so on meaningful, and to
++# report actual input values of CONFIG_FILES etc. instead of their
++# values after options handling.
++ac_log="
++This file was extended by $as_me, which was
++generated by GNU Autoconf 2.69.  Invocation command line was
++
++  CONFIG_FILES    = $CONFIG_FILES
++  CONFIG_HEADERS  = $CONFIG_HEADERS
++  CONFIG_LINKS    = $CONFIG_LINKS
++  CONFIG_COMMANDS = $CONFIG_COMMANDS
++  $ $0 $@
++
++on `(hostname || uname -n) 2>/dev/null | sed 1q`
++"
++
++_ACEOF
++
++case $ac_config_files in *"
++"*) set x $ac_config_files; shift; ac_config_files=$*;;
++esac
++
++case $ac_config_headers in *"
++"*) set x $ac_config_headers; shift; ac_config_headers=$*;;
++esac
++
++
++cat >>$CONFIG_STATUS <<_ACEOF || ac_write_fail=1
++# Files that config.status was made for.
++config_files="$ac_config_files"
++config_headers="$ac_config_headers"
++config_commands="$ac_config_commands"
++
++_ACEOF
++
++cat >>$CONFIG_STATUS <<\_ACEOF || ac_write_fail=1
++ac_cs_usage="\
++\`$as_me' instantiates files and other configuration actions
++from templates according to the current configuration.  Unless the files
++and actions are specified as TAGs, all are instantiated by default.
++
++Usage: $0 [OPTION]... [TAG]...
++
++  -h, --help       print this help, then exit
++  -V, --version    print version number and configuration settings, then exit
++      --config     print configuration, then exit
++  -q, --quiet, --silent
++                   do not print progress messages
++  -d, --debug      don't remove temporary files
++      --recheck    update $as_me by reconfiguring in the same conditions
++      --file=FILE[:TEMPLATE]
++                   instantiate the configuration file FILE
++      --header=FILE[:TEMPLATE]
++                   instantiate the configuration header FILE
++
++Configuration files:
++$config_files
++
++Configuration headers:
++$config_headers
++
++Configuration commands:
++$config_commands
++
++Report bugs to the package provider."
++
++_ACEOF
++cat >>$CONFIG_STATUS <<_ACEOF || ac_write_fail=1
++ac_cs_config="`$as_echo "$ac_configure_args" | sed 's/^ //; s/[\\""\`\$]/\\\\&/g'`"
++ac_cs_version="\\
++config.status
++configured by $0, generated by GNU Autoconf 2.69,
++  with options \\"\$ac_cs_config\\"
++
++Copyright (C) 2012 Free Software Foundation, Inc.
++This config.status script is free software; the Free Software Foundation
++gives unlimited permission to copy, distribute and modify it."
++
++ac_pwd='$ac_pwd'
++srcdir='$srcdir'
++INSTALL='$INSTALL'
++AWK='$AWK'
++test -n "\$AWK" || AWK=awk
++_ACEOF
++
++cat >>$CONFIG_STATUS <<\_ACEOF || ac_write_fail=1
++# The default lists apply if the user does not specify any file.
++ac_need_defaults=:
++while test $# != 0
++do
++  case $1 in
++  --*=?*)
++    ac_option=`expr "X$1" : 'X\([^=]*\)='`
++    ac_optarg=`expr "X$1" : 'X[^=]*=\(.*\)'`
++    ac_shift=:
++    ;;
++  --*=)
++    ac_option=`expr "X$1" : 'X\([^=]*\)='`
++    ac_optarg=
++    ac_shift=:
++    ;;
++  *)
++    ac_option=$1
++    ac_optarg=$2
++    ac_shift=shift
++    ;;
++  esac
++
++  case $ac_option in
++  # Handling of the options.
++  -recheck | --recheck | --rechec | --reche | --rech | --rec | --re | --r)
++    ac_cs_recheck=: ;;
++  --version | --versio | --versi | --vers | --ver | --ve | --v | -V )
++    $as_echo "$ac_cs_version"; exit ;;
++  --config | --confi | --conf | --con | --co | --c )
++    $as_echo "$ac_cs_config"; exit ;;
++  --debug | --debu | --deb | --de | --d | -d )
++    debug=: ;;
++  --file | --fil | --fi | --f )
++    $ac_shift
++    case $ac_optarg in
++    *\'*) ac_optarg=`$as_echo "$ac_optarg" | sed "s/'/'\\\\\\\\''/g"` ;;
++    '') as_fn_error $? "missing file argument" ;;
++    esac
++    as_fn_append CONFIG_FILES " '$ac_optarg'"
++    ac_need_defaults=false;;
++  --header | --heade | --head | --hea )
++    $ac_shift
++    case $ac_optarg in
++    *\'*) ac_optarg=`$as_echo "$ac_optarg" | sed "s/'/'\\\\\\\\''/g"` ;;
++    esac
++    as_fn_append CONFIG_HEADERS " '$ac_optarg'"
++    ac_need_defaults=false;;
++  --he | --h)
++    # Conflict between --help and --header
++    as_fn_error $? "ambiguous option: \`$1'
++Try \`$0 --help' for more information.";;
++  --help | --hel | -h )
++    $as_echo "$ac_cs_usage"; exit ;;
++  -q | -quiet | --quiet | --quie | --qui | --qu | --q \
++  | -silent | --silent | --silen | --sile | --sil | --si | --s)
++    ac_cs_silent=: ;;
++
++  # This is an error.
++  -*) as_fn_error $? "unrecognized option: \`$1'
++Try \`$0 --help' for more information." ;;
++
++  *) as_fn_append ac_config_targets " $1"
++     ac_need_defaults=false ;;
++
++  esac
++  shift
++done
++
++ac_configure_extra_args=
++
++if $ac_cs_silent; then
++  exec 6>/dev/null
++  ac_configure_extra_args="$ac_configure_extra_args --silent"
++fi
++
++_ACEOF
++cat >>$CONFIG_STATUS <<_ACEOF || ac_write_fail=1
++if \$ac_cs_recheck; then
++  set X $SHELL '$0' $ac_configure_args \$ac_configure_extra_args --no-create --no-recursion
++  shift
++  \$as_echo "running CONFIG_SHELL=$SHELL \$*" >&6
++  CONFIG_SHELL='$SHELL'
++  export CONFIG_SHELL
++  exec "\$@"
++fi
++
++_ACEOF
++cat >>$CONFIG_STATUS <<\_ACEOF || ac_write_fail=1
++exec 5>>config.log
++{
++  echo
++  sed 'h;s/./-/g;s/^.../## /;s/...$/ ##/;p;x;p;x' <<_ASBOX
++## Running $as_me. ##
++_ASBOX
++  $as_echo "$ac_log"
++} >&5
++
++_ACEOF
++cat >>$CONFIG_STATUS <<_ACEOF || ac_write_fail=1
++#
++# INIT-COMMANDS
++#
++ac_aux_dir=$ac_aux_dir DEPDIR=$DEPDIR
++
++
++# The HP-UX ksh and POSIX shell print the target directory to stdout
++# if CDPATH is set.
++(unset CDPATH) >/dev/null 2>&1 && unset CDPATH
++
++sed_quote_subst='$sed_quote_subst'
++double_quote_subst='$double_quote_subst'
++delay_variable_subst='$delay_variable_subst'
++macro_version='`$ECHO "$macro_version" | $SED "$delay_single_quote_subst"`'
++macro_revision='`$ECHO "$macro_revision" | $SED "$delay_single_quote_subst"`'
++enable_shared='`$ECHO "$enable_shared" | $SED "$delay_single_quote_subst"`'
++enable_static='`$ECHO "$enable_static" | $SED "$delay_single_quote_subst"`'
++pic_mode='`$ECHO "$pic_mode" | $SED "$delay_single_quote_subst"`'
++enable_fast_install='`$ECHO "$enable_fast_install" | $SED "$delay_single_quote_subst"`'
++SHELL='`$ECHO "$SHELL" | $SED "$delay_single_quote_subst"`'
++ECHO='`$ECHO "$ECHO" | $SED "$delay_single_quote_subst"`'
++host_alias='`$ECHO "$host_alias" | $SED "$delay_single_quote_subst"`'
++host='`$ECHO "$host" | $SED "$delay_single_quote_subst"`'
++host_os='`$ECHO "$host_os" | $SED "$delay_single_quote_subst"`'
++build_alias='`$ECHO "$build_alias" | $SED "$delay_single_quote_subst"`'
++build='`$ECHO "$build" | $SED "$delay_single_quote_subst"`'
++build_os='`$ECHO "$build_os" | $SED "$delay_single_quote_subst"`'
++SED='`$ECHO "$SED" | $SED "$delay_single_quote_subst"`'
++Xsed='`$ECHO "$Xsed" | $SED "$delay_single_quote_subst"`'
++GREP='`$ECHO "$GREP" | $SED "$delay_single_quote_subst"`'
++EGREP='`$ECHO "$EGREP" | $SED "$delay_single_quote_subst"`'
++FGREP='`$ECHO "$FGREP" | $SED "$delay_single_quote_subst"`'
++LD='`$ECHO "$LD" | $SED "$delay_single_quote_subst"`'
++NM='`$ECHO "$NM" | $SED "$delay_single_quote_subst"`'
++LN_S='`$ECHO "$LN_S" | $SED "$delay_single_quote_subst"`'
++max_cmd_len='`$ECHO "$max_cmd_len" | $SED "$delay_single_quote_subst"`'
++ac_objext='`$ECHO "$ac_objext" | $SED "$delay_single_quote_subst"`'
++exeext='`$ECHO "$exeext" | $SED "$delay_single_quote_subst"`'
++lt_unset='`$ECHO "$lt_unset" | $SED "$delay_single_quote_subst"`'
++lt_SP2NL='`$ECHO "$lt_SP2NL" | $SED "$delay_single_quote_subst"`'
++lt_NL2SP='`$ECHO "$lt_NL2SP" | $SED "$delay_single_quote_subst"`'
++reload_flag='`$ECHO "$reload_flag" | $SED "$delay_single_quote_subst"`'
++reload_cmds='`$ECHO "$reload_cmds" | $SED "$delay_single_quote_subst"`'
++OBJDUMP='`$ECHO "$OBJDUMP" | $SED "$delay_single_quote_subst"`'
++deplibs_check_method='`$ECHO "$deplibs_check_method" | $SED "$delay_single_quote_subst"`'
++file_magic_cmd='`$ECHO "$file_magic_cmd" | $SED "$delay_single_quote_subst"`'
++AR='`$ECHO "$AR" | $SED "$delay_single_quote_subst"`'
++AR_FLAGS='`$ECHO "$AR_FLAGS" | $SED "$delay_single_quote_subst"`'
++STRIP='`$ECHO "$STRIP" | $SED "$delay_single_quote_subst"`'
++RANLIB='`$ECHO "$RANLIB" | $SED "$delay_single_quote_subst"`'
++old_postinstall_cmds='`$ECHO "$old_postinstall_cmds" | $SED "$delay_single_quote_subst"`'
++old_postuninstall_cmds='`$ECHO "$old_postuninstall_cmds" | $SED "$delay_single_quote_subst"`'
++old_archive_cmds='`$ECHO "$old_archive_cmds" | $SED "$delay_single_quote_subst"`'
++lock_old_archive_extraction='`$ECHO "$lock_old_archive_extraction" | $SED "$delay_single_quote_subst"`'
++CC='`$ECHO "$CC" | $SED "$delay_single_quote_subst"`'
++CFLAGS='`$ECHO "$CFLAGS" | $SED "$delay_single_quote_subst"`'
++compiler='`$ECHO "$compiler" | $SED "$delay_single_quote_subst"`'
++GCC='`$ECHO "$GCC" | $SED "$delay_single_quote_subst"`'
++lt_cv_sys_global_symbol_pipe='`$ECHO "$lt_cv_sys_global_symbol_pipe" | $SED "$delay_single_quote_subst"`'
++lt_cv_sys_global_symbol_to_cdecl='`$ECHO "$lt_cv_sys_global_symbol_to_cdecl" | $SED "$delay_single_quote_subst"`'
++lt_cv_sys_global_symbol_to_c_name_address='`$ECHO "$lt_cv_sys_global_symbol_to_c_name_address" | $SED "$delay_single_quote_subst"`'
++lt_cv_sys_global_symbol_to_c_name_address_lib_prefix='`$ECHO "$lt_cv_sys_global_symbol_to_c_name_address_lib_prefix" | $SED "$delay_single_quote_subst"`'
++objdir='`$ECHO "$objdir" | $SED "$delay_single_quote_subst"`'
++MAGIC_CMD='`$ECHO "$MAGIC_CMD" | $SED "$delay_single_quote_subst"`'
++lt_prog_compiler_no_builtin_flag='`$ECHO "$lt_prog_compiler_no_builtin_flag" | $SED "$delay_single_quote_subst"`'
++lt_prog_compiler_wl='`$ECHO "$lt_prog_compiler_wl" | $SED "$delay_single_quote_subst"`'
++lt_prog_compiler_pic='`$ECHO "$lt_prog_compiler_pic" | $SED "$delay_single_quote_subst"`'
++lt_prog_compiler_static='`$ECHO "$lt_prog_compiler_static" | $SED "$delay_single_quote_subst"`'
++lt_cv_prog_compiler_c_o='`$ECHO "$lt_cv_prog_compiler_c_o" | $SED "$delay_single_quote_subst"`'
++need_locks='`$ECHO "$need_locks" | $SED "$delay_single_quote_subst"`'
++DSYMUTIL='`$ECHO "$DSYMUTIL" | $SED "$delay_single_quote_subst"`'
++NMEDIT='`$ECHO "$NMEDIT" | $SED "$delay_single_quote_subst"`'
++LIPO='`$ECHO "$LIPO" | $SED "$delay_single_quote_subst"`'
++OTOOL='`$ECHO "$OTOOL" | $SED "$delay_single_quote_subst"`'
++OTOOL64='`$ECHO "$OTOOL64" | $SED "$delay_single_quote_subst"`'
++libext='`$ECHO "$libext" | $SED "$delay_single_quote_subst"`'
++shrext_cmds='`$ECHO "$shrext_cmds" | $SED "$delay_single_quote_subst"`'
++extract_expsyms_cmds='`$ECHO "$extract_expsyms_cmds" | $SED "$delay_single_quote_subst"`'
++archive_cmds_need_lc='`$ECHO "$archive_cmds_need_lc" | $SED "$delay_single_quote_subst"`'
++enable_shared_with_static_runtimes='`$ECHO "$enable_shared_with_static_runtimes" | $SED "$delay_single_quote_subst"`'
++export_dynamic_flag_spec='`$ECHO "$export_dynamic_flag_spec" | $SED "$delay_single_quote_subst"`'
++whole_archive_flag_spec='`$ECHO "$whole_archive_flag_spec" | $SED "$delay_single_quote_subst"`'
++compiler_needs_object='`$ECHO "$compiler_needs_object" | $SED "$delay_single_quote_subst"`'
++old_archive_from_new_cmds='`$ECHO "$old_archive_from_new_cmds" | $SED "$delay_single_quote_subst"`'
++old_archive_from_expsyms_cmds='`$ECHO "$old_archive_from_expsyms_cmds" | $SED "$delay_single_quote_subst"`'
++archive_cmds='`$ECHO "$archive_cmds" | $SED "$delay_single_quote_subst"`'
++archive_expsym_cmds='`$ECHO "$archive_expsym_cmds" | $SED "$delay_single_quote_subst"`'
++module_cmds='`$ECHO "$module_cmds" | $SED "$delay_single_quote_subst"`'
++module_expsym_cmds='`$ECHO "$module_expsym_cmds" | $SED "$delay_single_quote_subst"`'
++with_gnu_ld='`$ECHO "$with_gnu_ld" | $SED "$delay_single_quote_subst"`'
++allow_undefined_flag='`$ECHO "$allow_undefined_flag" | $SED "$delay_single_quote_subst"`'
++no_undefined_flag='`$ECHO "$no_undefined_flag" | $SED "$delay_single_quote_subst"`'
++hardcode_libdir_flag_spec='`$ECHO "$hardcode_libdir_flag_spec" | $SED "$delay_single_quote_subst"`'
++hardcode_libdir_flag_spec_ld='`$ECHO "$hardcode_libdir_flag_spec_ld" | $SED "$delay_single_quote_subst"`'
++hardcode_libdir_separator='`$ECHO "$hardcode_libdir_separator" | $SED "$delay_single_quote_subst"`'
++hardcode_direct='`$ECHO "$hardcode_direct" | $SED "$delay_single_quote_subst"`'
++hardcode_direct_absolute='`$ECHO "$hardcode_direct_absolute" | $SED "$delay_single_quote_subst"`'
++hardcode_minus_L='`$ECHO "$hardcode_minus_L" | $SED "$delay_single_quote_subst"`'
++hardcode_shlibpath_var='`$ECHO "$hardcode_shlibpath_var" | $SED "$delay_single_quote_subst"`'
++hardcode_automatic='`$ECHO "$hardcode_automatic" | $SED "$delay_single_quote_subst"`'
++inherit_rpath='`$ECHO "$inherit_rpath" | $SED "$delay_single_quote_subst"`'
++link_all_deplibs='`$ECHO "$link_all_deplibs" | $SED "$delay_single_quote_subst"`'
++fix_srcfile_path='`$ECHO "$fix_srcfile_path" | $SED "$delay_single_quote_subst"`'
++always_export_symbols='`$ECHO "$always_export_symbols" | $SED "$delay_single_quote_subst"`'
++export_symbols_cmds='`$ECHO "$export_symbols_cmds" | $SED "$delay_single_quote_subst"`'
++exclude_expsyms='`$ECHO "$exclude_expsyms" | $SED "$delay_single_quote_subst"`'
++include_expsyms='`$ECHO "$include_expsyms" | $SED "$delay_single_quote_subst"`'
++prelink_cmds='`$ECHO "$prelink_cmds" | $SED "$delay_single_quote_subst"`'
++file_list_spec='`$ECHO "$file_list_spec" | $SED "$delay_single_quote_subst"`'
++variables_saved_for_relink='`$ECHO "$variables_saved_for_relink" | $SED "$delay_single_quote_subst"`'
++need_lib_prefix='`$ECHO "$need_lib_prefix" | $SED "$delay_single_quote_subst"`'
++need_version='`$ECHO "$need_version" | $SED "$delay_single_quote_subst"`'
++version_type='`$ECHO "$version_type" | $SED "$delay_single_quote_subst"`'
++runpath_var='`$ECHO "$runpath_var" | $SED "$delay_single_quote_subst"`'
++shlibpath_var='`$ECHO "$shlibpath_var" | $SED "$delay_single_quote_subst"`'
++shlibpath_overrides_runpath='`$ECHO "$shlibpath_overrides_runpath" | $SED "$delay_single_quote_subst"`'
++libname_spec='`$ECHO "$libname_spec" | $SED "$delay_single_quote_subst"`'
++library_names_spec='`$ECHO "$library_names_spec" | $SED "$delay_single_quote_subst"`'
++soname_spec='`$ECHO "$soname_spec" | $SED "$delay_single_quote_subst"`'
++install_override_mode='`$ECHO "$install_override_mode" | $SED "$delay_single_quote_subst"`'
++postinstall_cmds='`$ECHO "$postinstall_cmds" | $SED "$delay_single_quote_subst"`'
++postuninstall_cmds='`$ECHO "$postuninstall_cmds" | $SED "$delay_single_quote_subst"`'
++finish_cmds='`$ECHO "$finish_cmds" | $SED "$delay_single_quote_subst"`'
++finish_eval='`$ECHO "$finish_eval" | $SED "$delay_single_quote_subst"`'
++hardcode_into_libs='`$ECHO "$hardcode_into_libs" | $SED "$delay_single_quote_subst"`'
++sys_lib_search_path_spec='`$ECHO "$sys_lib_search_path_spec" | $SED "$delay_single_quote_subst"`'
++sys_lib_dlsearch_path_spec='`$ECHO "$sys_lib_dlsearch_path_spec" | $SED "$delay_single_quote_subst"`'
++hardcode_action='`$ECHO "$hardcode_action" | $SED "$delay_single_quote_subst"`'
++enable_dlopen='`$ECHO "$enable_dlopen" | $SED "$delay_single_quote_subst"`'
++enable_dlopen_self='`$ECHO "$enable_dlopen_self" | $SED "$delay_single_quote_subst"`'
++enable_dlopen_self_static='`$ECHO "$enable_dlopen_self_static" | $SED "$delay_single_quote_subst"`'
++old_striplib='`$ECHO "$old_striplib" | $SED "$delay_single_quote_subst"`'
++striplib='`$ECHO "$striplib" | $SED "$delay_single_quote_subst"`'
++
++LTCC='$LTCC'
++LTCFLAGS='$LTCFLAGS'
++compiler='$compiler_DEFAULT'
++
++# A function that is used when there is no print builtin or printf.
++func_fallback_echo ()
++{
++  eval 'cat <<_LTECHO_EOF
++\$1
++_LTECHO_EOF'
++}
++
++# Quote evaled strings.
++for var in SHELL \
++ECHO \
++SED \
++GREP \
++EGREP \
++FGREP \
++LD \
++NM \
++LN_S \
++lt_SP2NL \
++lt_NL2SP \
++reload_flag \
++OBJDUMP \
++deplibs_check_method \
++file_magic_cmd \
++AR \
++AR_FLAGS \
++STRIP \
++RANLIB \
++CC \
++CFLAGS \
++compiler \
++lt_cv_sys_global_symbol_pipe \
++lt_cv_sys_global_symbol_to_cdecl \
++lt_cv_sys_global_symbol_to_c_name_address \
++lt_cv_sys_global_symbol_to_c_name_address_lib_prefix \
++lt_prog_compiler_no_builtin_flag \
++lt_prog_compiler_wl \
++lt_prog_compiler_pic \
++lt_prog_compiler_static \
++lt_cv_prog_compiler_c_o \
++need_locks \
++DSYMUTIL \
++NMEDIT \
++LIPO \
++OTOOL \
++OTOOL64 \
++shrext_cmds \
++export_dynamic_flag_spec \
++whole_archive_flag_spec \
++compiler_needs_object \
++with_gnu_ld \
++allow_undefined_flag \
++no_undefined_flag \
++hardcode_libdir_flag_spec \
++hardcode_libdir_flag_spec_ld \
++hardcode_libdir_separator \
++fix_srcfile_path \
++exclude_expsyms \
++include_expsyms \
++file_list_spec \
++variables_saved_for_relink \
++libname_spec \
++library_names_spec \
++soname_spec \
++install_override_mode \
++finish_eval \
++old_striplib \
++striplib; do
++    case \`eval \\\\\$ECHO \\\\""\\\\\$\$var"\\\\"\` in
++    *[\\\\\\\`\\"\\\$]*)
++      eval "lt_\$var=\\\\\\"\\\`\\\$ECHO \\"\\\$\$var\\" | \\\$SED \\"\\\$sed_quote_subst\\"\\\`\\\\\\""
++      ;;
++    *)
++      eval "lt_\$var=\\\\\\"\\\$\$var\\\\\\""
++      ;;
++    esac
++done
++
++# Double-quote double-evaled strings.
++for var in reload_cmds \
++old_postinstall_cmds \
++old_postuninstall_cmds \
++old_archive_cmds \
++extract_expsyms_cmds \
++old_archive_from_new_cmds \
++old_archive_from_expsyms_cmds \
++archive_cmds \
++archive_expsym_cmds \
++module_cmds \
++module_expsym_cmds \
++export_symbols_cmds \
++prelink_cmds \
++postinstall_cmds \
++postuninstall_cmds \
++finish_cmds \
++sys_lib_search_path_spec \
++sys_lib_dlsearch_path_spec; do
++    case \`eval \\\\\$ECHO \\\\""\\\\\$\$var"\\\\"\` in
++    *[\\\\\\\`\\"\\\$]*)
++      eval "lt_\$var=\\\\\\"\\\`\\\$ECHO \\"\\\$\$var\\" | \\\$SED -e \\"\\\$double_quote_subst\\" -e \\"\\\$sed_quote_subst\\" -e \\"\\\$delay_variable_subst\\"\\\`\\\\\\""
++      ;;
++    *)
++      eval "lt_\$var=\\\\\\"\\\$\$var\\\\\\""
++      ;;
++    esac
++done
++
++ac_aux_dir='$ac_aux_dir'
++xsi_shell='$xsi_shell'
++lt_shell_append='$lt_shell_append'
++
++# See if we are running on zsh, and set the options which allow our
++# commands through without removal of \ escapes INIT.
++if test -n "\${ZSH_VERSION+set}" ; then
++   setopt NO_GLOB_SUBST
++fi
++
++
++    PACKAGE='$PACKAGE'
++    VERSION='$VERSION'
++    TIMESTAMP='$TIMESTAMP'
++    RM='$RM'
++    ofile='$ofile'
++
++
++
++
++_ACEOF
++
++cat >>$CONFIG_STATUS <<\_ACEOF || ac_write_fail=1
++
++# Handling of arguments.
++for ac_config_target in $ac_config_targets
++do
++  case $ac_config_target in
++    "config.h") CONFIG_HEADERS="$CONFIG_HEADERS config.h:config.in" ;;
++    "depdir") CONFIG_COMMANDS="$CONFIG_COMMANDS depdir" ;;
++    "libtool") CONFIG_COMMANDS="$CONFIG_COMMANDS libtool" ;;
++    "Makefile.sim") CONFIG_FILES="$CONFIG_FILES Makefile.sim:Makefile.in" ;;
++    "Make-common.sim") CONFIG_FILES="$CONFIG_FILES Make-common.sim:../common/Make-common.in" ;;
++    ".gdbinit") CONFIG_FILES="$CONFIG_FILES .gdbinit:../common/gdbinit.in" ;;
++    "Makefile") CONFIG_COMMANDS="$CONFIG_COMMANDS Makefile" ;;
++    "stamp-h") CONFIG_COMMANDS="$CONFIG_COMMANDS stamp-h" ;;
++
++  *) as_fn_error $? "invalid argument: \`$ac_config_target'" "$LINENO" 5;;
++  esac
++done
++
++
++# If the user did not use the arguments to specify the items to instantiate,
++# then the envvar interface is used.  Set only those that are not.
++# We use the long form for the default assignment because of an extremely
++# bizarre bug on SunOS 4.1.3.
++if $ac_need_defaults; then
++  test "${CONFIG_FILES+set}" = set || CONFIG_FILES=$config_files
++  test "${CONFIG_HEADERS+set}" = set || CONFIG_HEADERS=$config_headers
++  test "${CONFIG_COMMANDS+set}" = set || CONFIG_COMMANDS=$config_commands
++fi
++
++# Have a temporary directory for convenience.  Make it in the build tree
++# simply because there is no reason against having it here, and in addition,
++# creating and moving files from /tmp can sometimes cause problems.
++# Hook for its removal unless debugging.
++# Note that there is a small window in which the directory will not be cleaned:
++# after its creation but before its name has been assigned to `$tmp'.
++$debug ||
++{
++  tmp= ac_tmp=
++  trap 'exit_status=$?
++  : "${ac_tmp:=$tmp}"
++  { test ! -d "$ac_tmp" || rm -fr "$ac_tmp"; } && exit $exit_status
++' 0
++  trap 'as_fn_exit 1' 1 2 13 15
++}
++# Create a (secure) tmp directory for tmp files.
++
++{
++  tmp=`(umask 077 && mktemp -d "./confXXXXXX") 2>/dev/null` &&
++  test -d "$tmp"
++}  ||
++{
++  tmp=./conf$$-$RANDOM
++  (umask 077 && mkdir "$tmp")
++} || as_fn_error $? "cannot create a temporary directory in ." "$LINENO" 5
++ac_tmp=$tmp
++
++# Set up the scripts for CONFIG_FILES section.
++# No need to generate them if there are no CONFIG_FILES.
++# This happens for instance with `./config.status config.h'.
++if test -n "$CONFIG_FILES"; then
++
++
++ac_cr=`echo X | tr X '\015'`
++# On cygwin, bash can eat \r inside `` if the user requested igncr.
++# But we know of no other shell where ac_cr would be empty at this
++# point, so we can use a bashism as a fallback.
++if test "x$ac_cr" = x; then
++  eval ac_cr=\$\'\\r\'
++fi
++ac_cs_awk_cr=`$AWK 'BEGIN { print "a\rb" }' </dev/null 2>/dev/null`
++if test "$ac_cs_awk_cr" = "a${ac_cr}b"; then
++  ac_cs_awk_cr='\\r'
++else
++  ac_cs_awk_cr=$ac_cr
++fi
++
++echo 'BEGIN {' >"$ac_tmp/subs1.awk" &&
++_ACEOF
++
++
++{
++  echo "cat >conf$$subs.awk <<_ACEOF" &&
++  echo "$ac_subst_vars" | sed 's/.*/&!$&$ac_delim/' &&
++  echo "_ACEOF"
++} >conf$$subs.sh ||
++  as_fn_error $? "could not make $CONFIG_STATUS" "$LINENO" 5
++ac_delim_num=`echo "$ac_subst_vars" | grep -c '^'`
++ac_delim='%!_!# '
++for ac_last_try in false false false false false :; do
++  . ./conf$$subs.sh ||
++    as_fn_error $? "could not make $CONFIG_STATUS" "$LINENO" 5
++
++  ac_delim_n=`sed -n "s/.*$ac_delim\$/X/p" conf$$subs.awk | grep -c X`
++  if test $ac_delim_n = $ac_delim_num; then
++    break
++  elif $ac_last_try; then
++    as_fn_error $? "could not make $CONFIG_STATUS" "$LINENO" 5
++  else
++    ac_delim="$ac_delim!$ac_delim _$ac_delim!! "
++  fi
++done
++rm -f conf$$subs.sh
++
++cat >>$CONFIG_STATUS <<_ACEOF || ac_write_fail=1
++cat >>"\$ac_tmp/subs1.awk" <<\\_ACAWK &&
++_ACEOF
++sed -n '
++h
++s/^/S["/; s/!.*/"]=/
++p
++g
++s/^[^!]*!//
++:repl
++t repl
++s/'"$ac_delim"'$//
++t delim
++:nl
++h
++s/\(.\{148\}\)..*/\1/
++t more1
++s/["\\]/\\&/g; s/^/"/; s/$/\\n"\\/
++p
++n
++b repl
++:more1
++s/["\\]/\\&/g; s/^/"/; s/$/"\\/
++p
++g
++s/.\{148\}//
++t nl
++:delim
++h
++s/\(.\{148\}\)..*/\1/
++t more2
++s/["\\]/\\&/g; s/^/"/; s/$/"/
++p
++b
++:more2
++s/["\\]/\\&/g; s/^/"/; s/$/"\\/
++p
++g
++s/.\{148\}//
++t delim
++' <conf$$subs.awk | sed '
++/^[^""]/{
++  N
++  s/\n//
++}
++' >>$CONFIG_STATUS || ac_write_fail=1
++rm -f conf$$subs.awk
++cat >>$CONFIG_STATUS <<_ACEOF || ac_write_fail=1
++_ACAWK
++cat >>"\$ac_tmp/subs1.awk" <<_ACAWK &&
++  for (key in S) S_is_set[key] = 1
++  FS = ""
++
++}
++{
++  line = $ 0
++  nfields = split(line, field, "@")
++  substed = 0
++  len = length(field[1])
++  for (i = 2; i < nfields; i++) {
++    key = field[i]
++    keylen = length(key)
++    if (S_is_set[key]) {
++      value = S[key]
++      line = substr(line, 1, len) "" value "" substr(line, len + keylen + 3)
++      len += length(value) + length(field[++i])
++      substed = 1
++    } else
++      len += 1 + keylen
++  }
++
++  print line
++}
++
++_ACAWK
++_ACEOF
++cat >>$CONFIG_STATUS <<\_ACEOF || ac_write_fail=1
++if sed "s/$ac_cr//" < /dev/null > /dev/null 2>&1; then
++  sed "s/$ac_cr\$//; s/$ac_cr/$ac_cs_awk_cr/g"
++else
++  cat
++fi < "$ac_tmp/subs1.awk" > "$ac_tmp/subs.awk" \
++  || as_fn_error $? "could not setup config files machinery" "$LINENO" 5
++_ACEOF
++
++# VPATH may cause trouble with some makes, so we remove sole $(srcdir),
++# ${srcdir} and @srcdir@ entries from VPATH if srcdir is ".", strip leading and
++# trailing colons and then remove the whole line if VPATH becomes empty
++# (actually we leave an empty line to preserve line numbers).
++if test "x$srcdir" = x.; then
++  ac_vpsub='/^[	 ]*VPATH[	 ]*=[	 ]*/{
++h
++s///
++s/^/:/
++s/[	 ]*$/:/
++s/:\$(srcdir):/:/g
++s/:\${srcdir}:/:/g
++s/:@srcdir@:/:/g
++s/^:*//
++s/:*$//
++x
++s/\(=[	 ]*\).*/\1/
++G
++s/\n//
++s/^[^=]*=[	 ]*$//
++}'
++fi
++
++cat >>$CONFIG_STATUS <<\_ACEOF || ac_write_fail=1
++fi # test -n "$CONFIG_FILES"
++
++# Set up the scripts for CONFIG_HEADERS section.
++# No need to generate them if there are no CONFIG_HEADERS.
++# This happens for instance with `./config.status Makefile'.
++if test -n "$CONFIG_HEADERS"; then
++cat >"$ac_tmp/defines.awk" <<\_ACAWK ||
++BEGIN {
++_ACEOF
++
++# Transform confdefs.h into an awk script `defines.awk', embedded as
++# here-document in config.status, that substitutes the proper values into
++# config.h.in to produce config.h.
++
++# Create a delimiter string that does not exist in confdefs.h, to ease
++# handling of long lines.
++ac_delim='%!_!# '
++for ac_last_try in false false :; do
++  ac_tt=`sed -n "/$ac_delim/p" confdefs.h`
++  if test -z "$ac_tt"; then
++    break
++  elif $ac_last_try; then
++    as_fn_error $? "could not make $CONFIG_HEADERS" "$LINENO" 5
++  else
++    ac_delim="$ac_delim!$ac_delim _$ac_delim!! "
++  fi
++done
++
++# For the awk script, D is an array of macro values keyed by name,
++# likewise P contains macro parameters if any.  Preserve backslash
++# newline sequences.
++
++ac_word_re=[_$as_cr_Letters][_$as_cr_alnum]*
++sed -n '
++s/.\{148\}/&'"$ac_delim"'/g
++t rset
++:rset
++s/^[	 ]*#[	 ]*define[	 ][	 ]*/ /
++t def
++d
++:def
++s/\\$//
++t bsnl
++s/["\\]/\\&/g
++s/^ \('"$ac_word_re"'\)\(([^()]*)\)[	 ]*\(.*\)/P["\1"]="\2"\
++D["\1"]=" \3"/p
++s/^ \('"$ac_word_re"'\)[	 ]*\(.*\)/D["\1"]=" \2"/p
++d
++:bsnl
++s/["\\]/\\&/g
++s/^ \('"$ac_word_re"'\)\(([^()]*)\)[	 ]*\(.*\)/P["\1"]="\2"\
++D["\1"]=" \3\\\\\\n"\\/p
++t cont
++s/^ \('"$ac_word_re"'\)[	 ]*\(.*\)/D["\1"]=" \2\\\\\\n"\\/p
++t cont
++d
++:cont
++n
++s/.\{148\}/&'"$ac_delim"'/g
++t clear
++:clear
++s/\\$//
++t bsnlc
++s/["\\]/\\&/g; s/^/"/; s/$/"/p
++d
++:bsnlc
++s/["\\]/\\&/g; s/^/"/; s/$/\\\\\\n"\\/p
++b cont
++' <confdefs.h | sed '
++s/'"$ac_delim"'/"\\\
++"/g' >>$CONFIG_STATUS || ac_write_fail=1
++
++cat >>$CONFIG_STATUS <<_ACEOF || ac_write_fail=1
++  for (key in D) D_is_set[key] = 1
++  FS = ""
++}
++/^[\t ]*#[\t ]*(define|undef)[\t ]+$ac_word_re([\t (]|\$)/ {
++  line = \$ 0
++  split(line, arg, " ")
++  if (arg[1] == "#") {
++    defundef = arg[2]
++    mac1 = arg[3]
++  } else {
++    defundef = substr(arg[1], 2)
++    mac1 = arg[2]
++  }
++  split(mac1, mac2, "(") #)
++  macro = mac2[1]
++  prefix = substr(line, 1, index(line, defundef) - 1)
++  if (D_is_set[macro]) {
++    # Preserve the white space surrounding the "#".
++    print prefix "define", macro P[macro] D[macro]
++    next
++  } else {
++    # Replace #undef with comments.  This is necessary, for example,
++    # in the case of _POSIX_SOURCE, which is predefined and required
++    # on some systems where configure will not decide to define it.
++    if (defundef == "undef") {
++      print "/*", prefix defundef, macro, "*/"
++      next
++    }
++  }
++}
++{ print }
++_ACAWK
++_ACEOF
++cat >>$CONFIG_STATUS <<\_ACEOF || ac_write_fail=1
++  as_fn_error $? "could not setup config headers machinery" "$LINENO" 5
++fi # test -n "$CONFIG_HEADERS"
++
++
++eval set X "  :F $CONFIG_FILES  :H $CONFIG_HEADERS    :C $CONFIG_COMMANDS"
++shift
++for ac_tag
++do
++  case $ac_tag in
++  :[FHLC]) ac_mode=$ac_tag; continue;;
++  esac
++  case $ac_mode$ac_tag in
++  :[FHL]*:*);;
++  :L* | :C*:*) as_fn_error $? "invalid tag \`$ac_tag'" "$LINENO" 5;;
++  :[FH]-) ac_tag=-:-;;
++  :[FH]*) ac_tag=$ac_tag:$ac_tag.in;;
++  esac
++  ac_save_IFS=$IFS
++  IFS=:
++  set x $ac_tag
++  IFS=$ac_save_IFS
++  shift
++  ac_file=$1
++  shift
++
++  case $ac_mode in
++  :L) ac_source=$1;;
++  :[FH])
++    ac_file_inputs=
++    for ac_f
++    do
++      case $ac_f in
++      -) ac_f="$ac_tmp/stdin";;
++      *) # Look for the file first in the build tree, then in the source tree
++	 # (if the path is not absolute).  The absolute path cannot be DOS-style,
++	 # because $ac_f cannot contain `:'.
++	 test -f "$ac_f" ||
++	   case $ac_f in
++	   [\\/$]*) false;;
++	   *) test -f "$srcdir/$ac_f" && ac_f="$srcdir/$ac_f";;
++	   esac ||
++	   as_fn_error 1 "cannot find input file: \`$ac_f'" "$LINENO" 5;;
++      esac
++      case $ac_f in *\'*) ac_f=`$as_echo "$ac_f" | sed "s/'/'\\\\\\\\''/g"`;; esac
++      as_fn_append ac_file_inputs " '$ac_f'"
++    done
++
++    # Let's still pretend it is `configure' which instantiates (i.e., don't
++    # use $as_me), people would be surprised to read:
++    #    /* config.h.  Generated by config.status.  */
++    configure_input='Generated from '`
++	  $as_echo "$*" | sed 's|^[^:]*/||;s|:[^:]*/|, |g'
++	`' by configure.'
++    if test x"$ac_file" != x-; then
++      configure_input="$ac_file.  $configure_input"
++      { $as_echo "$as_me:${as_lineno-$LINENO}: creating $ac_file" >&5
++$as_echo "$as_me: creating $ac_file" >&6;}
++    fi
++    # Neutralize special characters interpreted by sed in replacement strings.
++    case $configure_input in #(
++    *\&* | *\|* | *\\* )
++       ac_sed_conf_input=`$as_echo "$configure_input" |
++       sed 's/[\\\\&|]/\\\\&/g'`;; #(
++    *) ac_sed_conf_input=$configure_input;;
++    esac
++
++    case $ac_tag in
++    *:-:* | *:-) cat >"$ac_tmp/stdin" \
++      || as_fn_error $? "could not create $ac_file" "$LINENO" 5 ;;
++    esac
++    ;;
++  esac
++
++  ac_dir=`$as_dirname -- "$ac_file" ||
++$as_expr X"$ac_file" : 'X\(.*[^/]\)//*[^/][^/]*/*$' \| \
++	 X"$ac_file" : 'X\(//\)[^/]' \| \
++	 X"$ac_file" : 'X\(//\)$' \| \
++	 X"$ac_file" : 'X\(/\)' \| . 2>/dev/null ||
++$as_echo X"$ac_file" |
++    sed '/^X\(.*[^/]\)\/\/*[^/][^/]*\/*$/{
++	    s//\1/
++	    q
++	  }
++	  /^X\(\/\/\)[^/].*/{
++	    s//\1/
++	    q
++	  }
++	  /^X\(\/\/\)$/{
++	    s//\1/
++	    q
++	  }
++	  /^X\(\/\).*/{
++	    s//\1/
++	    q
++	  }
++	  s/.*/./; q'`
++  as_dir="$ac_dir"; as_fn_mkdir_p
++  ac_builddir=.
++
++case "$ac_dir" in
++.) ac_dir_suffix= ac_top_builddir_sub=. ac_top_build_prefix= ;;
++*)
++  ac_dir_suffix=/`$as_echo "$ac_dir" | sed 's|^\.[\\/]||'`
++  # A ".." for each directory in $ac_dir_suffix.
++  ac_top_builddir_sub=`$as_echo "$ac_dir_suffix" | sed 's|/[^\\/]*|/..|g;s|/||'`
++  case $ac_top_builddir_sub in
++  "") ac_top_builddir_sub=. ac_top_build_prefix= ;;
++  *)  ac_top_build_prefix=$ac_top_builddir_sub/ ;;
++  esac ;;
++esac
++ac_abs_top_builddir=$ac_pwd
++ac_abs_builddir=$ac_pwd$ac_dir_suffix
++# for backward compatibility:
++ac_top_builddir=$ac_top_build_prefix
++
++case $srcdir in
++  .)  # We are building in place.
++    ac_srcdir=.
++    ac_top_srcdir=$ac_top_builddir_sub
++    ac_abs_top_srcdir=$ac_pwd ;;
++  [\\/]* | ?:[\\/]* )  # Absolute name.
++    ac_srcdir=$srcdir$ac_dir_suffix;
++    ac_top_srcdir=$srcdir
++    ac_abs_top_srcdir=$srcdir ;;
++  *) # Relative name.
++    ac_srcdir=$ac_top_build_prefix$srcdir$ac_dir_suffix
++    ac_top_srcdir=$ac_top_build_prefix$srcdir
++    ac_abs_top_srcdir=$ac_pwd/$srcdir ;;
++esac
++ac_abs_srcdir=$ac_abs_top_srcdir$ac_dir_suffix
++
++
++  case $ac_mode in
++  :F)
++  #
++  # CONFIG_FILE
++  #
++
++  case $INSTALL in
++  [\\/$]* | ?:[\\/]* ) ac_INSTALL=$INSTALL ;;
++  *) ac_INSTALL=$ac_top_build_prefix$INSTALL ;;
++  esac
++_ACEOF
++
++cat >>$CONFIG_STATUS <<\_ACEOF || ac_write_fail=1
++# If the template does not know about datarootdir, expand it.
++# FIXME: This hack should be removed a few years after 2.60.
++ac_datarootdir_hack=; ac_datarootdir_seen=
++ac_sed_dataroot='
++/datarootdir/ {
++  p
++  q
++}
++/@datadir@/p
++/@docdir@/p
++/@infodir@/p
++/@localedir@/p
++/@mandir@/p'
++case `eval "sed -n \"\$ac_sed_dataroot\" $ac_file_inputs"` in
++*datarootdir*) ac_datarootdir_seen=yes;;
++*@datadir@*|*@docdir@*|*@infodir@*|*@localedir@*|*@mandir@*)
++  { $as_echo "$as_me:${as_lineno-$LINENO}: WARNING: $ac_file_inputs seems to ignore the --datarootdir setting" >&5
++$as_echo "$as_me: WARNING: $ac_file_inputs seems to ignore the --datarootdir setting" >&2;}
++_ACEOF
++cat >>$CONFIG_STATUS <<_ACEOF || ac_write_fail=1
++  ac_datarootdir_hack='
++  s&@datadir@&$datadir&g
++  s&@docdir@&$docdir&g
++  s&@infodir@&$infodir&g
++  s&@localedir@&$localedir&g
++  s&@mandir@&$mandir&g
++  s&\\\${datarootdir}&$datarootdir&g' ;;
++esac
++_ACEOF
++
++# Neutralize VPATH when `$srcdir' = `.'.
++# Shell code in configure.ac might set extrasub.
++# FIXME: do we really want to maintain this feature?
++cat >>$CONFIG_STATUS <<_ACEOF || ac_write_fail=1
++ac_sed_extra="$ac_vpsub
++$extrasub
++_ACEOF
++cat >>$CONFIG_STATUS <<\_ACEOF || ac_write_fail=1
++:t
++/@[a-zA-Z_][a-zA-Z_0-9]*@/!b
++s|@configure_input@|$ac_sed_conf_input|;t t
++s&@top_builddir@&$ac_top_builddir_sub&;t t
++s&@top_build_prefix@&$ac_top_build_prefix&;t t
++s&@srcdir@&$ac_srcdir&;t t
++s&@abs_srcdir@&$ac_abs_srcdir&;t t
++s&@top_srcdir@&$ac_top_srcdir&;t t
++s&@abs_top_srcdir@&$ac_abs_top_srcdir&;t t
++s&@builddir@&$ac_builddir&;t t
++s&@abs_builddir@&$ac_abs_builddir&;t t
++s&@abs_top_builddir@&$ac_abs_top_builddir&;t t
++s&@INSTALL@&$ac_INSTALL&;t t
++$ac_datarootdir_hack
++"
++eval sed \"\$ac_sed_extra\" "$ac_file_inputs" | $AWK -f "$ac_tmp/subs.awk" \
++  >$ac_tmp/out || as_fn_error $? "could not create $ac_file" "$LINENO" 5
++
++test -z "$ac_datarootdir_hack$ac_datarootdir_seen" &&
++  { ac_out=`sed -n '/\${datarootdir}/p' "$ac_tmp/out"`; test -n "$ac_out"; } &&
++  { ac_out=`sed -n '/^[	 ]*datarootdir[	 ]*:*=/p' \
++      "$ac_tmp/out"`; test -z "$ac_out"; } &&
++  { $as_echo "$as_me:${as_lineno-$LINENO}: WARNING: $ac_file contains a reference to the variable \`datarootdir'
++which seems to be undefined.  Please make sure it is defined" >&5
++$as_echo "$as_me: WARNING: $ac_file contains a reference to the variable \`datarootdir'
++which seems to be undefined.  Please make sure it is defined" >&2;}
++
++  rm -f "$ac_tmp/stdin"
++  case $ac_file in
++  -) cat "$ac_tmp/out" && rm -f "$ac_tmp/out";;
++  *) rm -f "$ac_file" && mv "$ac_tmp/out" "$ac_file";;
++  esac \
++  || as_fn_error $? "could not create $ac_file" "$LINENO" 5
++ ;;
++  :H)
++  #
++  # CONFIG_HEADER
++  #
++  if test x"$ac_file" != x-; then
++    {
++      $as_echo "/* $configure_input  */" \
++      && eval '$AWK -f "$ac_tmp/defines.awk"' "$ac_file_inputs"
++    } >"$ac_tmp/config.h" \
++      || as_fn_error $? "could not create $ac_file" "$LINENO" 5
++    if diff "$ac_file" "$ac_tmp/config.h" >/dev/null 2>&1; then
++      { $as_echo "$as_me:${as_lineno-$LINENO}: $ac_file is unchanged" >&5
++$as_echo "$as_me: $ac_file is unchanged" >&6;}
++    else
++      rm -f "$ac_file"
++      mv "$ac_tmp/config.h" "$ac_file" \
++	|| as_fn_error $? "could not create $ac_file" "$LINENO" 5
++    fi
++  else
++    $as_echo "/* $configure_input  */" \
++      && eval '$AWK -f "$ac_tmp/defines.awk"' "$ac_file_inputs" \
++      || as_fn_error $? "could not create -" "$LINENO" 5
++  fi
++ ;;
++
++  :C)  { $as_echo "$as_me:${as_lineno-$LINENO}: executing $ac_file commands" >&5
++$as_echo "$as_me: executing $ac_file commands" >&6;}
++ ;;
++  esac
++
++
++  case $ac_file$ac_mode in
++    "depdir":C) $SHELL $ac_aux_dir/mkinstalldirs $DEPDIR ;;
++    "libtool":C)
++
++    # See if we are running on zsh, and set the options which allow our
++    # commands through without removal of \ escapes.
++    if test -n "${ZSH_VERSION+set}" ; then
++      setopt NO_GLOB_SUBST
++    fi
++
++    cfgfile="${ofile}T"
++    trap "$RM \"$cfgfile\"; exit 1" 1 2 15
++    $RM "$cfgfile"
++
++    cat <<_LT_EOF >> "$cfgfile"
++#! $SHELL
++
++# `$ECHO "$ofile" | sed 's%^.*/%%'` - Provide generalized library-building support services.
++# Generated automatically by $as_me ($PACKAGE$TIMESTAMP) $VERSION
++# Libtool was configured on host `(hostname || uname -n) 2>/dev/null | sed 1q`:
++# NOTE: Changes made to this file will be lost: look at ltmain.sh.
++#
++#   Copyright (C) 1996, 1997, 1998, 1999, 2000, 2001, 2003, 2004, 2005,
++#                 2006, 2007, 2008, 2009 Free Software Foundation, Inc.
++#   Written by Gordon Matzigkeit, 1996
++#
++#   This file is part of GNU Libtool.
++#
++# GNU Libtool is free software; you can redistribute it and/or
++# modify it under the terms of the GNU General Public License as
++# published by the Free Software Foundation; either version 2 of
++# the License, or (at your option) any later version.
++#
++# As a special exception to the GNU General Public License,
++# if you distribute this file as part of a program or library that
++# is built using GNU Libtool, you may include this file under the
++# same distribution terms that you use for the rest of that program.
++#
++# GNU Libtool is distributed in the hope that it will be useful,
++# but WITHOUT ANY WARRANTY; without even the implied warranty of
++# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
++# GNU General Public License for more details.
++#
++# You should have received a copy of the GNU General Public License
++# along with GNU Libtool; see the file COPYING.  If not, a copy
++# can be downloaded from http://www.gnu.org/licenses/gpl.html, or
++# obtained by writing to the Free Software Foundation, Inc.,
++# 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
++
++
++# The names of the tagged configurations supported by this script.
++available_tags=""
++
++# ### BEGIN LIBTOOL CONFIG
++
++# Which release of libtool.m4 was used?
++macro_version=$macro_version
++macro_revision=$macro_revision
++
++# Whether or not to build shared libraries.
++build_libtool_libs=$enable_shared
++
++# Whether or not to build static libraries.
++build_old_libs=$enable_static
++
++# What type of objects to build.
++pic_mode=$pic_mode
++
++# Whether or not to optimize for fast installation.
++fast_install=$enable_fast_install
++
++# Shell to use when invoking shell scripts.
++SHELL=$lt_SHELL
++
++# An echo program that protects backslashes.
++ECHO=$lt_ECHO
++
++# The host system.
++host_alias=$host_alias
++host=$host
++host_os=$host_os
++
++# The build system.
++build_alias=$build_alias
++build=$build
++build_os=$build_os
++
++# A sed program that does not truncate output.
++SED=$lt_SED
++
++# Sed that helps us avoid accidentally triggering echo(1) options like -n.
++Xsed="\$SED -e 1s/^X//"
++
++# A grep program that handles long lines.
++GREP=$lt_GREP
++
++# An ERE matcher.
++EGREP=$lt_EGREP
++
++# A literal string matcher.
++FGREP=$lt_FGREP
++
++# A BSD- or MS-compatible name lister.
++NM=$lt_NM
++
++# Whether we need soft or hard links.
++LN_S=$lt_LN_S
++
++# What is the maximum length of a command?
++max_cmd_len=$max_cmd_len
++
++# Object file suffix (normally "o").
++objext=$ac_objext
++
++# Executable file suffix (normally "").
++exeext=$exeext
++
++# whether the shell understands "unset".
++lt_unset=$lt_unset
++
++# turn spaces into newlines.
++SP2NL=$lt_lt_SP2NL
++
++# turn newlines into spaces.
++NL2SP=$lt_lt_NL2SP
++
++# An object symbol dumper.
++OBJDUMP=$lt_OBJDUMP
++
++# Method to check whether dependent libraries are shared objects.
++deplibs_check_method=$lt_deplibs_check_method
++
++# Command to use when deplibs_check_method == "file_magic".
++file_magic_cmd=$lt_file_magic_cmd
++
++# The archiver.
++AR=$lt_AR
++AR_FLAGS=$lt_AR_FLAGS
++
++# A symbol stripping program.
++STRIP=$lt_STRIP
++
++# Commands used to install an old-style archive.
++RANLIB=$lt_RANLIB
++old_postinstall_cmds=$lt_old_postinstall_cmds
++old_postuninstall_cmds=$lt_old_postuninstall_cmds
++
++# Whether to use a lock for old archive extraction.
++lock_old_archive_extraction=$lock_old_archive_extraction
++
++# A C compiler.
++LTCC=$lt_CC
++
++# LTCC compiler flags.
++LTCFLAGS=$lt_CFLAGS
++
++# Take the output of nm and produce a listing of raw symbols and C names.
++global_symbol_pipe=$lt_lt_cv_sys_global_symbol_pipe
++
++# Transform the output of nm in a proper C declaration.
++global_symbol_to_cdecl=$lt_lt_cv_sys_global_symbol_to_cdecl
++
++# Transform the output of nm in a C name address pair.
++global_symbol_to_c_name_address=$lt_lt_cv_sys_global_symbol_to_c_name_address
++
++# Transform the output of nm in a C name address pair when lib prefix is needed.
++global_symbol_to_c_name_address_lib_prefix=$lt_lt_cv_sys_global_symbol_to_c_name_address_lib_prefix
++
++# The name of the directory that contains temporary libtool files.
++objdir=$objdir
++
++# Used to examine libraries when file_magic_cmd begins with "file".
++MAGIC_CMD=$MAGIC_CMD
++
++# Must we lock files when doing compilation?
++need_locks=$lt_need_locks
++
++# Tool to manipulate archived DWARF debug symbol files on Mac OS X.
++DSYMUTIL=$lt_DSYMUTIL
++
++# Tool to change global to local symbols on Mac OS X.
++NMEDIT=$lt_NMEDIT
++
++# Tool to manipulate fat objects and archives on Mac OS X.
++LIPO=$lt_LIPO
++
++# ldd/readelf like tool for Mach-O binaries on Mac OS X.
++OTOOL=$lt_OTOOL
++
++# ldd/readelf like tool for 64 bit Mach-O binaries on Mac OS X 10.4.
++OTOOL64=$lt_OTOOL64
++
++# Old archive suffix (normally "a").
++libext=$libext
++
++# Shared library suffix (normally ".so").
++shrext_cmds=$lt_shrext_cmds
++
++# The commands to extract the exported symbol list from a shared archive.
++extract_expsyms_cmds=$lt_extract_expsyms_cmds
++
++# Variables whose values should be saved in libtool wrapper scripts and
++# restored at link time.
++variables_saved_for_relink=$lt_variables_saved_for_relink
++
++# Do we need the "lib" prefix for modules?
++need_lib_prefix=$need_lib_prefix
++
++# Do we need a version for libraries?
++need_version=$need_version
++
++# Library versioning type.
++version_type=$version_type
++
++# Shared library runtime path variable.
++runpath_var=$runpath_var
++
++# Shared library path variable.
++shlibpath_var=$shlibpath_var
++
++# Is shlibpath searched before the hard-coded library search path?
++shlibpath_overrides_runpath=$shlibpath_overrides_runpath
++
++# Format of library name prefix.
++libname_spec=$lt_libname_spec
++
++# List of archive names.  First name is the real one, the rest are links.
++# The last name is the one that the linker finds with -lNAME
++library_names_spec=$lt_library_names_spec
++
++# The coded name of the library, if different from the real name.
++soname_spec=$lt_soname_spec
++
++# Permission mode override for installation of shared libraries.
++install_override_mode=$lt_install_override_mode
++
++# Command to use after installation of a shared archive.
++postinstall_cmds=$lt_postinstall_cmds
++
++# Command to use after uninstallation of a shared archive.
++postuninstall_cmds=$lt_postuninstall_cmds
++
++# Commands used to finish a libtool library installation in a directory.
++finish_cmds=$lt_finish_cmds
++
++# As "finish_cmds", except a single script fragment to be evaled but
++# not shown.
++finish_eval=$lt_finish_eval
++
++# Whether we should hardcode library paths into libraries.
++hardcode_into_libs=$hardcode_into_libs
++
++# Compile-time system search path for libraries.
++sys_lib_search_path_spec=$lt_sys_lib_search_path_spec
++
++# Run-time system search path for libraries.
++sys_lib_dlsearch_path_spec=$lt_sys_lib_dlsearch_path_spec
++
++# Whether dlopen is supported.
++dlopen_support=$enable_dlopen
++
++# Whether dlopen of programs is supported.
++dlopen_self=$enable_dlopen_self
++
++# Whether dlopen of statically linked programs is supported.
++dlopen_self_static=$enable_dlopen_self_static
++
++# Commands to strip libraries.
++old_striplib=$lt_old_striplib
++striplib=$lt_striplib
++
++
++# The linker used to build libraries.
++LD=$lt_LD
++
++# How to create reloadable object files.
++reload_flag=$lt_reload_flag
++reload_cmds=$lt_reload_cmds
++
++# Commands used to build an old-style archive.
++old_archive_cmds=$lt_old_archive_cmds
++
++# A language specific compiler.
++CC=$lt_compiler
++
++# Is the compiler the GNU compiler?
++with_gcc=$GCC
++
++# Compiler flag to turn off builtin functions.
++no_builtin_flag=$lt_lt_prog_compiler_no_builtin_flag
++
++# How to pass a linker flag through the compiler.
++wl=$lt_lt_prog_compiler_wl
++
++# Additional compiler flags for building library objects.
++pic_flag=$lt_lt_prog_compiler_pic
++
++# Compiler flag to prevent dynamic linking.
++link_static_flag=$lt_lt_prog_compiler_static
++
++# Does compiler simultaneously support -c and -o options?
++compiler_c_o=$lt_lt_cv_prog_compiler_c_o
++
++# Whether or not to add -lc for building shared libraries.
++build_libtool_need_lc=$archive_cmds_need_lc
++
++# Whether or not to disallow shared libs when runtime libs are static.
++allow_libtool_libs_with_static_runtimes=$enable_shared_with_static_runtimes
++
++# Compiler flag to allow reflexive dlopens.
++export_dynamic_flag_spec=$lt_export_dynamic_flag_spec
++
++# Compiler flag to generate shared objects directly from archives.
++whole_archive_flag_spec=$lt_whole_archive_flag_spec
++
++# Whether the compiler copes with passing no objects directly.
++compiler_needs_object=$lt_compiler_needs_object
++
++# Create an old-style archive from a shared archive.
++old_archive_from_new_cmds=$lt_old_archive_from_new_cmds
++
++# Create a temporary old-style archive to link instead of a shared archive.
++old_archive_from_expsyms_cmds=$lt_old_archive_from_expsyms_cmds
++
++# Commands used to build a shared archive.
++archive_cmds=$lt_archive_cmds
++archive_expsym_cmds=$lt_archive_expsym_cmds
++
++# Commands used to build a loadable module if different from building
++# a shared archive.
++module_cmds=$lt_module_cmds
++module_expsym_cmds=$lt_module_expsym_cmds
++
++# Whether we are building with GNU ld or not.
++with_gnu_ld=$lt_with_gnu_ld
++
++# Flag that allows shared libraries with undefined symbols to be built.
++allow_undefined_flag=$lt_allow_undefined_flag
++
++# Flag that enforces no undefined symbols.
++no_undefined_flag=$lt_no_undefined_flag
++
++# Flag to hardcode \$libdir into a binary during linking.
++# This must work even if \$libdir does not exist
++hardcode_libdir_flag_spec=$lt_hardcode_libdir_flag_spec
++
++# If ld is used when linking, flag to hardcode \$libdir into a binary
++# during linking.  This must work even if \$libdir does not exist.
++hardcode_libdir_flag_spec_ld=$lt_hardcode_libdir_flag_spec_ld
++
++# Whether we need a single "-rpath" flag with a separated argument.
++hardcode_libdir_separator=$lt_hardcode_libdir_separator
++
++# Set to "yes" if using DIR/libNAME\${shared_ext} during linking hardcodes
++# DIR into the resulting binary.
++hardcode_direct=$hardcode_direct
++
++# Set to "yes" if using DIR/libNAME\${shared_ext} during linking hardcodes
++# DIR into the resulting binary and the resulting library dependency is
++# "absolute",i.e impossible to change by setting \${shlibpath_var} if the
++# library is relocated.
++hardcode_direct_absolute=$hardcode_direct_absolute
++
++# Set to "yes" if using the -LDIR flag during linking hardcodes DIR
++# into the resulting binary.
++hardcode_minus_L=$hardcode_minus_L
++
++# Set to "yes" if using SHLIBPATH_VAR=DIR during linking hardcodes DIR
++# into the resulting binary.
++hardcode_shlibpath_var=$hardcode_shlibpath_var
++
++# Set to "yes" if building a shared library automatically hardcodes DIR
++# into the library and all subsequent libraries and executables linked
++# against it.
++hardcode_automatic=$hardcode_automatic
++
++# Set to yes if linker adds runtime paths of dependent libraries
++# to runtime path list.
++inherit_rpath=$inherit_rpath
++
++# Whether libtool must link a program against all its dependency libraries.
++link_all_deplibs=$link_all_deplibs
++
++# Fix the shell variable \$srcfile for the compiler.
++fix_srcfile_path=$lt_fix_srcfile_path
++
++# Set to "yes" if exported symbols are required.
++always_export_symbols=$always_export_symbols
++
++# The commands to list exported symbols.
++export_symbols_cmds=$lt_export_symbols_cmds
++
++# Symbols that should not be listed in the preloaded symbols.
++exclude_expsyms=$lt_exclude_expsyms
++
++# Symbols that must always be exported.
++include_expsyms=$lt_include_expsyms
++
++# Commands necessary for linking programs (against libraries) with templates.
++prelink_cmds=$lt_prelink_cmds
++
++# Specify filename containing input files.
++file_list_spec=$lt_file_list_spec
++
++# How to hardcode a shared library path into an executable.
++hardcode_action=$hardcode_action
++
++# ### END LIBTOOL CONFIG
++
++_LT_EOF
++
++  case $host_os in
++  aix3*)
++    cat <<\_LT_EOF >> "$cfgfile"
++# AIX sometimes has problems with the GCC collect2 program.  For some
++# reason, if we set the COLLECT_NAMES environment variable, the problems
++# vanish in a puff of smoke.
++if test "X${COLLECT_NAMES+set}" != Xset; then
++  COLLECT_NAMES=
++  export COLLECT_NAMES
++fi
++_LT_EOF
++    ;;
++  esac
++
++
++ltmain="$ac_aux_dir/ltmain.sh"
++
++
++  # We use sed instead of cat because bash on DJGPP gets confused if
++  # if finds mixed CR/LF and LF-only lines.  Since sed operates in
++  # text mode, it properly converts lines to CR/LF.  This bash problem
++  # is reportedly fixed, but why not run on old versions too?
++  sed '/^# Generated shell functions inserted here/q' "$ltmain" >> "$cfgfile" \
++    || (rm -f "$cfgfile"; exit 1)
++
++  case $xsi_shell in
++  yes)
++    cat << \_LT_EOF >> "$cfgfile"
++
++# func_dirname file append nondir_replacement
++# Compute the dirname of FILE.  If nonempty, add APPEND to the result,
++# otherwise set result to NONDIR_REPLACEMENT.
++func_dirname ()
++{
++  case ${1} in
++    */*) func_dirname_result="${1%/*}${2}" ;;
++    *  ) func_dirname_result="${3}" ;;
++  esac
++}
++
++# func_basename file
++func_basename ()
++{
++  func_basename_result="${1##*/}"
++}
++
++# func_dirname_and_basename file append nondir_replacement
++# perform func_basename and func_dirname in a single function
++# call:
++#   dirname:  Compute the dirname of FILE.  If nonempty,
++#             add APPEND to the result, otherwise set result
++#             to NONDIR_REPLACEMENT.
++#             value returned in "$func_dirname_result"
++#   basename: Compute filename of FILE.
++#             value retuned in "$func_basename_result"
++# Implementation must be kept synchronized with func_dirname
++# and func_basename. For efficiency, we do not delegate to
++# those functions but instead duplicate the functionality here.
++func_dirname_and_basename ()
++{
++  case ${1} in
++    */*) func_dirname_result="${1%/*}${2}" ;;
++    *  ) func_dirname_result="${3}" ;;
++  esac
++  func_basename_result="${1##*/}"
++}
++
++# func_stripname prefix suffix name
++# strip PREFIX and SUFFIX off of NAME.
++# PREFIX and SUFFIX must not contain globbing or regex special
++# characters, hashes, percent signs, but SUFFIX may contain a leading
++# dot (in which case that matches only a dot).
++func_stripname ()
++{
++  # pdksh 5.2.14 does not do ${X%$Y} correctly if both X and Y are
++  # positional parameters, so assign one to ordinary parameter first.
++  func_stripname_result=${3}
++  func_stripname_result=${func_stripname_result#"${1}"}
++  func_stripname_result=${func_stripname_result%"${2}"}
++}
++
++# func_opt_split
++func_opt_split ()
++{
++  func_opt_split_opt=${1%%=*}
++  func_opt_split_arg=${1#*=}
++}
++
++# func_lo2o object
++func_lo2o ()
++{
++  case ${1} in
++    *.lo) func_lo2o_result=${1%.lo}.${objext} ;;
++    *)    func_lo2o_result=${1} ;;
++  esac
++}
++
++# func_xform libobj-or-source
++func_xform ()
++{
++  func_xform_result=${1%.*}.lo
++}
++
++# func_arith arithmetic-term...
++func_arith ()
++{
++  func_arith_result=$(( $* ))
++}
++
++# func_len string
++# STRING may not start with a hyphen.
++func_len ()
++{
++  func_len_result=${#1}
++}
++
++_LT_EOF
++    ;;
++  *) # Bourne compatible functions.
++    cat << \_LT_EOF >> "$cfgfile"
++
++# func_dirname file append nondir_replacement
++# Compute the dirname of FILE.  If nonempty, add APPEND to the result,
++# otherwise set result to NONDIR_REPLACEMENT.
++func_dirname ()
++{
++  # Extract subdirectory from the argument.
++  func_dirname_result=`$ECHO "${1}" | $SED "$dirname"`
++  if test "X$func_dirname_result" = "X${1}"; then
++    func_dirname_result="${3}"
++  else
++    func_dirname_result="$func_dirname_result${2}"
++  fi
++}
++
++# func_basename file
++func_basename ()
++{
++  func_basename_result=`$ECHO "${1}" | $SED "$basename"`
++}
++
++
++# func_stripname prefix suffix name
++# strip PREFIX and SUFFIX off of NAME.
++# PREFIX and SUFFIX must not contain globbing or regex special
++# characters, hashes, percent signs, but SUFFIX may contain a leading
++# dot (in which case that matches only a dot).
++# func_strip_suffix prefix name
++func_stripname ()
++{
++  case ${2} in
++    .*) func_stripname_result=`$ECHO "${3}" | $SED "s%^${1}%%; s%\\\\${2}\$%%"`;;
++    *)  func_stripname_result=`$ECHO "${3}" | $SED "s%^${1}%%; s%${2}\$%%"`;;
++  esac
++}
++
++# sed scripts:
++my_sed_long_opt='1s/^\(-[^=]*\)=.*/\1/;q'
++my_sed_long_arg='1s/^-[^=]*=//'
++
++# func_opt_split
++func_opt_split ()
++{
++  func_opt_split_opt=`$ECHO "${1}" | $SED "$my_sed_long_opt"`
++  func_opt_split_arg=`$ECHO "${1}" | $SED "$my_sed_long_arg"`
++}
++
++# func_lo2o object
++func_lo2o ()
++{
++  func_lo2o_result=`$ECHO "${1}" | $SED "$lo2o"`
++}
++
++# func_xform libobj-or-source
++func_xform ()
++{
++  func_xform_result=`$ECHO "${1}" | $SED 's/\.[^.]*$/.lo/'`
++}
++
++# func_arith arithmetic-term...
++func_arith ()
++{
++  func_arith_result=`expr "$@"`
++}
++
++# func_len string
++# STRING may not start with a hyphen.
++func_len ()
++{
++  func_len_result=`expr "$1" : ".*" 2>/dev/null || echo $max_cmd_len`
++}
++
++_LT_EOF
++esac
++
++case $lt_shell_append in
++  yes)
++    cat << \_LT_EOF >> "$cfgfile"
++
++# func_append var value
++# Append VALUE to the end of shell variable VAR.
++func_append ()
++{
++  eval "$1+=\$2"
++}
++_LT_EOF
++    ;;
++  *)
++    cat << \_LT_EOF >> "$cfgfile"
++
++# func_append var value
++# Append VALUE to the end of shell variable VAR.
++func_append ()
++{
++  eval "$1=\$$1\$2"
++}
++
++_LT_EOF
++    ;;
++  esac
++
++
++  sed -n '/^# Generated shell functions inserted here/,$p' "$ltmain" >> "$cfgfile" \
++    || (rm -f "$cfgfile"; exit 1)
++
++  mv -f "$cfgfile" "$ofile" ||
++    (rm -f "$ofile" && cp "$cfgfile" "$ofile" && rm -f "$cfgfile")
++  chmod +x "$ofile"
++
++ ;;
++    "Makefile":C) echo "Merging Makefile.sim+Make-common.sim into Makefile ..."
++ rm -f Makesim1.tmp Makesim2.tmp Makefile
++ sed -n -e '/^## COMMON_PRE_/,/^## End COMMON_PRE_/ p' <Make-common.sim >Makesim1.tmp
++ sed -n -e '/^## COMMON_POST_/,/^## End COMMON_POST_/ p' <Make-common.sim >Makesim2.tmp
++ sed -e '/^## COMMON_PRE_/ r Makesim1.tmp' \
++	-e '/^## COMMON_POST_/ r Makesim2.tmp' \
++	<Makefile.sim >Makefile
++ rm -f Makefile.sim Make-common.sim Makesim1.tmp Makesim2.tmp
++ ;;
++    "stamp-h":C) echo > stamp-h ;;
++
++  esac
++done # for ac_tag
++
++
++as_fn_exit 0
++_ACEOF
++ac_clean_files=$ac_clean_files_save
++
++test $ac_write_fail = 0 ||
++  as_fn_error $? "write failure creating $CONFIG_STATUS" "$LINENO" 5
++
++
++# configure is writing to config.log, and then calls config.status.
++# config.status does its own redirection, appending to config.log.
++# Unfortunately, on DOS this fails, as config.log is still kept open
++# by configure, so config.status won't be able to write to it; its
++# output is simply discarded.  So we exec the FD to /dev/null,
++# effectively closing config.log, so it can be properly (re)opened and
++# appended to by config.status.  When coming back to configure, we
++# need to make the FD available again.
++if test "$no_create" != yes; then
++  ac_cs_success=:
++  ac_config_status_args=
++  test "$silent" = yes &&
++    ac_config_status_args="$ac_config_status_args --quiet"
++  exec 5>/dev/null
++  $SHELL $CONFIG_STATUS $ac_config_status_args || ac_cs_success=false
++  exec 5>>config.log
++  # Use ||, not &&, to avoid exiting from the if with $? = 1, which
++  # would make configure fail if this is the last instruction.
++  $ac_cs_success || as_fn_exit 1
++fi
++if test -n "$ac_unrecognized_opts" && test "$enable_option_checking" != no; then
++  { $as_echo "$as_me:${as_lineno-$LINENO}: WARNING: unrecognized options: $ac_unrecognized_opts" >&5
++$as_echo "$as_me: WARNING: unrecognized options: $ac_unrecognized_opts" >&2;}
++fi
++
++
+diff --git a/sim/riscv/configure.ac b/sim/riscv/configure.ac
+new file mode 100644
+index 0000000000..a53e54c19f
+--- /dev/null
++++ b/sim/riscv/configure.ac
+@@ -0,0 +1,30 @@
++dnl Process this file with autoconf to produce a configure script.
++AC_PREREQ(2.64)dnl
++AC_INIT(Makefile.in)
++sinclude(../common/acinclude.m4)
++
++SIM_AC_COMMON
++
++SIM_AC_OPTION_ENDIAN(LITTLE)
++SIM_AC_OPTION_ALIGNMENT(NONSTRICT_ALIGNMENT)
++SIM_AC_OPTION_ENVIRONMENT
++SIM_AC_OPTION_INLINE
++SIM_AC_OPTION_WARNINGS
++
++# Select the default model for the target.
++riscv_model=
++case "${target}" in
++riscv32*) riscv_model="RV32G" ;;
++riscv*) riscv_model="RV64G" ;;
++esac
++SIM_AC_OPTION_DEFAULT_MODEL(${riscv_model})
++
++# Select the bitsize of the target.
++riscv_addr_bitsize=
++case "${target}" in
++riscv32*) riscv_addr_bitsize=32 ;;
++riscv*) riscv_addr_bitsize=64 ;;
++esac
++SIM_AC_OPTION_BITSIZE($riscv_addr_bitsize)
++
++SIM_AC_OUTPUT
+diff --git a/sim/riscv/interp.c b/sim/riscv/interp.c
+new file mode 100644
+index 0000000000..f28c841cfc
+--- /dev/null
++++ b/sim/riscv/interp.c
+@@ -0,0 +1,220 @@
++/* RISC-V simulator.
++
++   Copyright (C) 2005-2015 Free Software Foundation, Inc.
++   Contributed by Mike Frysinger.
++
++   This file is part of simulators.
++
++   This program is free software; you can redistribute it and/or modify
++   it under the terms of the GNU General Public License as published by
++   the Free Software Foundation; either version 3 of the License, or
++   (at your option) any later version.
++
++   This program is distributed in the hope that it will be useful,
++   but WITHOUT ANY WARRANTY; without even the implied warranty of
++   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
++   GNU General Public License for more details.
++
++   You should have received a copy of the GNU General Public License
++   along with this program.  If not, see <http://www.gnu.org/licenses/>.  */
++
++/* This file contains the main glue logic between the sim core and the target
++   specific simulator.  Normally this file will be kept small and the target
++   details will live in other files.
++
++   For more specific details on these functions, see the gdb/remote-sim.h
++   header file.  */
++
++#include "config.h"
++
++#include "libiberty.h"
++#include "bfd.h"
++#include "elf-bfd.h"
++
++#include "sim-main.h"
++#include "sim-options.h"
++
++/* This function is the main loop.  It should process ticks and decode+execute
++   a single instruction.
++
++   Usually you do not need to change things here.  */
++
++void
++sim_engine_run (SIM_DESC sd,
++		int next_cpu_nr, /* ignore  */
++		int nr_cpus, /* ignore  */
++		int siggnal) /* ignore  */
++{
++  SIM_CPU *cpu;
++
++  SIM_ASSERT (STATE_MAGIC (sd) == SIM_MAGIC_NUMBER);
++
++  cpu = STATE_CPU (sd, 0);
++
++  while (1)
++    {
++      step_once (cpu);
++      if (sim_events_tick (sd))
++	sim_events_process (sd);
++    }
++}
++
++/* Initialize the simulator from scratch.  This is called once per lifetime of
++   the simulation.  Think of it as a processor reset.
++
++   Usually all cpu-specific setup is handled in the initialize_cpu callback.
++   If you want to do cpu-independent stuff, then it should go at the end (see
++   where memory is initialized).  */
++
++static void
++free_state (SIM_DESC sd)
++{
++  if (STATE_MODULES (sd) != NULL)
++    sim_module_uninstall (sd);
++  sim_cpu_free_all (sd);
++  sim_state_free (sd);
++}
++
++SIM_DESC
++sim_open (SIM_OPEN_KIND kind, host_callback *callback,
++	  struct bfd *abfd, char * const *argv)
++{
++  char c;
++  int i;
++  SIM_DESC sd = sim_state_alloc (kind, callback);
++
++  /* The cpu data is kept in a separately allocated chunk of memory.  */
++  if (sim_cpu_alloc_all (sd, 1, /*cgen_cpu_max_extra_bytes ()*/0) != SIM_RC_OK)
++    {
++      free_state (sd);
++      return 0;
++    }
++
++  if (sim_pre_argv_init (sd, argv[0]) != SIM_RC_OK)
++    {
++      free_state (sd);
++      return 0;
++    }
++
++  /* XXX: Default to the Virtual environment.  */
++  if (STATE_ENVIRONMENT (sd) == ALL_ENVIRONMENT)
++    STATE_ENVIRONMENT (sd) = VIRTUAL_ENVIRONMENT;
++
++  /* getopt will print the error message so we just have to exit if this fails.
++     FIXME: Hmmm...  in the case of gdb we need getopt to call
++     print_filtered.  */
++  if (sim_parse_args (sd, argv) != SIM_RC_OK)
++    {
++      free_state (sd);
++      return 0;
++    }
++
++  /* Check for/establish the a reference program image.  */
++  if (sim_analyze_program (sd,
++			   (STATE_PROG_ARGV (sd) != NULL
++			    ? *STATE_PROG_ARGV (sd)
++			    : NULL), abfd) != SIM_RC_OK)
++    {
++      free_state (sd);
++      return 0;
++    }
++
++  /* Establish any remaining configuration options.  */
++  if (sim_config (sd) != SIM_RC_OK)
++    {
++      free_state (sd);
++      return 0;
++    }
++
++  if (sim_post_argv_init (sd) != SIM_RC_OK)
++    {
++      free_state (sd);
++      return 0;
++    }
++
++  /* CPU specific initialization.  */
++  for (i = 0; i < MAX_NR_PROCESSORS; ++i)
++    {
++      SIM_CPU *cpu = STATE_CPU (sd, i);
++
++      initialize_cpu (sd, cpu, i);
++    }
++
++  /* Allocate external memory if none specified by user.
++     Use address 4 here in case the user wanted address 0 unmapped.  */
++  if (sim_core_read_buffer (sd, NULL, read_map, &c, 4, 1) == 0)
++    sim_do_commandf (sd, "memory-size %#x", DEFAULT_MEM_SIZE);
++
++  return sd;
++}
++
++static bfd_vma
++riscv_get_symbol (SIM_DESC sd, const char *sym)
++{
++  long symcount = STATE_PROG_SYMS_COUNT (sd);
++  asymbol **symtab = STATE_PROG_SYMS (sd);
++  int i;
++
++  for (i = 0;i < symcount; ++i)
++    {
++      if (strcmp (sym, bfd_asymbol_name (symtab[i])) == 0)
++	{
++	  bfd_vma sa;
++	  sa = bfd_asymbol_value (symtab[i]);
++	  return sa;
++	}
++    }
++
++  /* Symbol not found.  */
++  return 0;
++}
++
++/* Prepare to run a program that has already been loaded into memory.
++
++   Usually you do not need to change things here.  */
++
++SIM_RC
++sim_create_inferior (SIM_DESC sd, struct bfd *abfd,
++		     char * const *argv, char * const *env)
++{
++  SIM_CPU *cpu = STATE_CPU (sd, 0);
++  sim_cia addr;
++  Elf_Internal_Phdr *phdr;
++  int i, phnum;
++
++  /* Set the PC.  */
++  if (abfd != NULL)
++    addr = bfd_get_start_address (abfd);
++  else
++    addr = 0;
++  sim_pc_set (cpu, addr);
++  phdr = elf_tdata (abfd)->phdr;
++  phnum = elf_elfheader (abfd)->e_phnum;
++
++  /* Try to find _end symbol, and set it to the end of brk.  */
++  trace_load_symbols (sd);
++  cpu->endbrk = riscv_get_symbol (sd, "_end");
++
++  /* If not found, set end of brk to end of all section.  */
++  if (cpu->endbrk == 0)
++    {
++      for (i = 0; i < phnum; i++)
++	{
++	  if (phdr[i].p_paddr + phdr[i].p_memsz > cpu->endbrk)
++	    cpu->endbrk = phdr[i].p_paddr + phdr[i].p_memsz;
++	}
++    }
++
++  /* Standalone mode (i.e. `run`) will take care of the argv for us in
++     sim_open() -> sim_parse_args().  But in debug mode (i.e. 'target sim'
++     with `gdb`), we need to handle it.  */
++  if (STATE_OPEN_KIND (sd) == SIM_OPEN_DEBUG)
++    {
++      freeargv (STATE_PROG_ARGV (sd));
++      STATE_PROG_ARGV (sd) = dupargv (argv);
++    }
++
++  initialize_env (sd, (void *)argv, (void *)env);
++
++  return SIM_RC_OK;
++}
+diff --git a/sim/riscv/machs.c b/sim/riscv/machs.c
+new file mode 100644
+index 0000000000..78ed28d1f0
+--- /dev/null
++++ b/sim/riscv/machs.c
+@@ -0,0 +1,125 @@
++/* RISC-V simulator.
++
++   Copyright (C) 2005-2015 Free Software Foundation, Inc.
++   Contributed by Mike Frysinger.
++
++   This file is part of simulators.
++
++   This program is free software; you can redistribute it and/or modify
++   it under the terms of the GNU General Public License as published by
++   the Free Software Foundation; either version 3 of the License, or
++   (at your option) any later version.
++
++   This program is distributed in the hope that it will be useful,
++   but WITHOUT ANY WARRANTY; without even the implied warranty of
++   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
++   GNU General Public License for more details.
++
++   You should have received a copy of the GNU General Public License
++   along with this program.  If not, see <http://www.gnu.org/licenses/>.  */
++
++#include "config.h"
++
++#include "sim-main.h"
++
++static void
++riscv_model_init (SIM_CPU *cpu)
++{
++}
++
++static void
++riscv_init_cpu (SIM_CPU *cpu)
++{
++}
++
++static void
++riscv_prepare_run (SIM_CPU *cpu)
++{
++}
++
++static const SIM_MACH_IMP_PROPERTIES riscv_imp_properties =
++{
++  sizeof (SIM_CPU),
++  0,
++};
++
++#if WITH_TARGET_WORD_BITSIZE >= 32
++
++static const SIM_MACH rv32i_mach;
++
++static const SIM_MODEL rv32_models[] =
++{
++#define M(ext) { "RV32"#ext, &rv32i_mach, MODEL_RV32##ext, NULL, riscv_model_init },
++#include "model_list.def"
++#undef M
++  { 0, NULL, 0, NULL, NULL, }
++};
++
++static const SIM_MACH rv32i_mach =
++{
++  "rv32i", "riscv:rv32", MACH_RV32I,
++  32, 32, &rv32_models[0], &riscv_imp_properties,
++  riscv_init_cpu,
++  riscv_prepare_run
++};
++
++#endif
++
++#if WITH_TARGET_WORD_BITSIZE >= 64
++
++static const SIM_MACH rv64i_mach;
++
++static const SIM_MODEL rv64_models[] =
++{
++#define M(ext) { "RV64"#ext, &rv64i_mach, MODEL_RV64##ext, NULL, riscv_model_init },
++#include "model_list.def"
++#undef M
++  { 0, NULL, 0, NULL, NULL, }
++};
++
++static const SIM_MACH rv64i_mach =
++{
++  "rv64i", "riscv:rv64", MACH_RV64I,
++  64, 64, &rv64_models[0], &riscv_imp_properties,
++  riscv_init_cpu,
++  riscv_prepare_run
++};
++
++#endif
++
++#if WITH_TARGET_WORD_BITSIZE >= 128
++
++static const SIM_MACH rv128i_mach;
++
++static const SIM_MODEL rv128_models[] =
++{
++#define M(ext) { "RV128"#ext, &rv128i_mach, MODEL_RV128##ext, NULL, riscv_model_init },
++#include "model_list.def"
++#undef M
++  { 0, NULL, 0, NULL, NULL, }
++};
++
++static const SIM_MACH rv128i_mach =
++{
++  "rv128i", "riscv:rv128", MACH_RV128I,
++  128, 128, &rv128_models[0], &riscv_imp_properties,
++  riscv_init_cpu,
++  riscv_prepare_run
++};
++
++#endif
++
++/* Order matters here.  */
++const SIM_MACH *sim_machs[] =
++{
++#if WITH_TARGET_WORD_BITSIZE >= 128
++  &rv128i_mach,
++#endif
++#if WITH_TARGET_WORD_BITSIZE >= 64
++  &rv64i_mach,
++#endif
++#if WITH_TARGET_WORD_BITSIZE >= 32
++  &rv32i_mach,
++#endif
++  NULL
++};
+diff --git a/sim/riscv/machs.h b/sim/riscv/machs.h
+new file mode 100644
+index 0000000000..6c8cd43e93
+--- /dev/null
++++ b/sim/riscv/machs.h
+@@ -0,0 +1,45 @@
++/* RISC-V simulator.
++
++   Copyright (C) 2005-2014 Free Software Foundation, Inc.
++   Contributed by Mike Frysinger.
++
++   This file is part of simulators.
++
++   This program is free software; you can redistribute it and/or modify
++   it under the terms of the GNU General Public License as published by
++   the Free Software Foundation; either version 3 of the License, or
++   (at your option) any later version.
++
++   This program is distributed in the hope that it will be useful,
++   but WITHOUT ANY WARRANTY; without even the implied warranty of
++   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
++   GNU General Public License for more details.
++
++   You should have received a copy of the GNU General Public License
++   along with this program.  If not, see <http://www.gnu.org/licenses/>.  */
++
++#ifndef RISCV_SIM_MACHS_H
++#define RISCV_SIM_MACHS_H
++
++typedef enum model_type {
++#define M(ext) MODEL_RV32##ext,
++#include "model_list.def"
++#undef M
++#define M(ext) MODEL_RV64##ext,
++#include "model_list.def"
++#undef M
++#define M(ext) MODEL_RV128##ext,
++#include "model_list.def"
++#undef M
++  MODEL_MAX
++} MODEL_TYPE;
++
++typedef enum mach_attr {
++  MACH_BASE,
++  MACH_RV32I,
++  MACH_RV64I,
++  MACH_RV128I,
++  MACH_MAX
++} MACH_ATTR;
++
++#endif
+diff --git a/sim/riscv/model_list.def b/sim/riscv/model_list.def
+new file mode 100644
+index 0000000000..5efd85ab28
+--- /dev/null
++++ b/sim/riscv/model_list.def
+@@ -0,0 +1,9 @@
++M(G)
++M(I)
++M(IM)
++M(IMA)
++M(IA)
++M(E)
++M(EM)
++M(EMA)
++M(EA)
+diff --git a/sim/riscv/sim-main.c b/sim/riscv/sim-main.c
+new file mode 100644
+index 0000000000..d773a35cb5
+--- /dev/null
++++ b/sim/riscv/sim-main.c
+@@ -0,0 +1,2468 @@
++/* RISC-V simulator.
++
++   Copyright (C) 2005-2014 Free Software Foundation, Inc.
++   Contributed by Mike Frysinger.
++
++   This file is part of simulators.
++
++   This program is free software; you can redistribute it and/or modify
++   it under the terms of the GNU General Public License as published by
++   the Free Software Foundation; either version 3 of the License, or
++   (at your option) any later version.
++
++   This program is distributed in the hope that it will be useful,
++   but WITHOUT ANY WARRANTY; without even the implied warranty of
++   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
++   GNU General Public License for more details.
++
++   You should have received a copy of the GNU General Public License
++   along with this program.  If not, see <http://www.gnu.org/licenses/>.  */
++
++/* This file contains the main simulator decoding logic.  i.e. everything that
++   is architecture specific.  */
++
++#include "config.h"
++
++#include <inttypes.h>
++#include <time.h>
++#include <ctype.h>
++#include <unistd.h>
++#include <sys/time.h>
++
++#include "sim-main.h"
++#include "sim-fpu.h"
++#include "sim-syscall.h"
++
++#include "opcode/riscv.h"
++
++#include "gdb/sim-riscv.h"
++
++#include "targ-vals.h"
++
++
++#define TRACE_REG(cpu, reg) TRACE_REGISTER (cpu, "wrote %s = %#" PRIxTW, riscv_gpr_names_abi[reg], cpu->regs[reg])
++
++static const struct riscv_opcode *riscv_hash[OP_MASK_OP + 1];
++#define OP_HASH_IDX(i) ((i) & (riscv_insn_length (i) == 2 ? 0x3 : 0x7f))
++
++#define RISCV_ASSERT_RV32(cpu, fmt, args...) \
++  do { \
++    if (RISCV_XLEN (cpu) != 32) \
++      { \
++	SIM_DESC sd = CPU_STATE (cpu); \
++	TRACE_INSN (cpu, "RV32I-only " fmt, ## args); \
++	sim_engine_halt (sd, cpu, NULL, cpu->pc, sim_signalled, SIM_SIGILL); \
++      } \
++  } while (0)
++
++#define RISCV_ASSERT_RV64(cpu, fmt, args...) \
++  do { \
++    if (RISCV_XLEN (cpu) != 64) \
++      { \
++	SIM_DESC sd = CPU_STATE (cpu); \
++	TRACE_INSN (cpu, "RV64I-only " fmt, ## args); \
++	sim_engine_halt (sd, cpu, NULL, cpu->pc, sim_signalled, SIM_SIGILL); \
++      } \
++  } while (0)
++
++static INLINE void
++store_rd (SIM_CPU *cpu, int rd, unsigned_word val)
++{
++  if (rd)
++    {
++      cpu->regs[rd] = val;
++      TRACE_REG (cpu, rd);
++    }
++}
++
++static INLINE void
++store_frd (SIM_CPU *cpu, int rd, unsigned_word val)
++{
++  cpu->fpregs[rd].w[0] = val;
++}
++
++static inline void
++store_frd64 (SIM_CPU *cpu, int rd, uint64_t val)
++{
++  cpu->fpregs[rd].v[0] = val;
++}
++
++static INLINE unsigned_word
++fetch_csr (SIM_CPU *cpu, const char *name, int csr, unsigned_word *reg)
++{
++  /* Handle pseudo registers.  */
++  switch (csr)
++    {
++    /* Allow certain registers only in respective modes.  */
++    case CSR_CYCLEH:
++    case CSR_INSTRETH:
++    case CSR_TIMEH:
++      RISCV_ASSERT_RV32 (cpu, "CSR: %s", name);
++      break;
++    }
++
++  return *reg;
++}
++
++static INLINE void
++store_csr (SIM_CPU *cpu, const char *name, int csr, unsigned_word *reg,
++	   unsigned_word val)
++{
++  switch (csr)
++    {
++    /* These are pseudo registers that modify sub-fields of fcsr.  */
++    case CSR_FRM:
++      val &= 0x7;
++      *reg = val;
++      cpu->csr.fcsr = (cpu->csr.fcsr & ~0xe0) | (val << 5);
++      break;
++    case CSR_FFLAGS:
++      val &= 0x1f;
++      *reg = val;
++      cpu->csr.fcsr = (cpu->csr.fcsr & ~0x1f) | val;
++      break;
++    /* Keep the sub-fields in sync.  */
++    case CSR_FCSR:
++      *reg = val;
++      cpu->csr.frm = (val >> 5) & 0x7;
++      cpu->csr.fflags = val & 0x1f;
++      break;
++
++    /* Allow certain registers only in respective modes.  */
++    case CSR_CYCLEH:
++    case CSR_INSTRETH:
++    case CSR_TIMEH:
++      RISCV_ASSERT_RV32 (cpu, "CSR: %s", name);
++
++    /* All the rest are immutable.  */
++    default:
++      val = *reg;
++      break;
++    }
++
++  TRACE_REGISTER (cpu, "wrote CSR %s = %#" PRIxTW, name, val);
++}
++
++static inline unsigned_word
++ashiftrt (unsigned_word val, unsigned_word shift)
++{
++  unsigned32 sign = (val & 0x80000000) ? ~(0xfffffffful >> shift) : 0;
++  return (val >> shift) | sign;
++}
++
++static inline unsigned_word
++ashiftrt64 (unsigned_word val, unsigned_word shift)
++{
++  unsigned64 sign = (val & 0x8000000000000000ull) ? ~(0xffffffffffffffffull >> shift) : 0;
++  return (val >> shift) | sign;
++}
++
++static sim_cia
++execute_d (SIM_CPU *cpu, unsigned_word iw, const struct riscv_opcode *op)
++{
++  SIM_DESC sd = CPU_STATE (cpu);
++  unsigned int mask_arithmetic = MASK_FADD_D;
++  unsigned int mask_mul_add = MASK_FMADD_S;
++  unsigned int mask_convert = MASK_FCVT_S_W;
++
++  static const int round_modes[] =
++  {
++      sim_fpu_round_near, sim_fpu_round_zero,
++      sim_fpu_round_down, sim_fpu_round_up,
++      sim_fpu_round_default, sim_fpu_round_default,
++      sim_fpu_round_default
++  };
++
++  int rd = (iw >> OP_SH_RD) & OP_MASK_RD;
++  int rs1 = (iw >> OP_SH_RS1) & OP_MASK_RS1;
++  int rs2 = (iw >> OP_SH_RS2) & OP_MASK_RS2;
++  int rs3 = (iw >> OP_SH_RS3) & OP_MASK_RS3;
++  const char *frd_name = riscv_fpr_names_abi[rd];
++  const char *frs1_name = riscv_fpr_names_abi[rs1];
++  const char *frs2_name = riscv_fpr_names_abi[rs2];
++  const char *frs3_name = riscv_fpr_names_abi[rs3];
++  const char *rd_name = riscv_gpr_names_abi[rd];
++  const char *rs1_name = riscv_gpr_names_abi[rs1];
++  unsigned_word i_imm = EXTRACT_ITYPE_IMM (iw);
++  unsigned_word s_imm = EXTRACT_STYPE_IMM (iw);
++  uint32_t u32;
++  int32_t i32;
++  uint64_t u64;
++  int64_t i64;
++  sim_cia pc = cpu->pc + 4;
++
++  /* Rounding mode.  */
++  int rm = (iw >> OP_SH_RM) & OP_MASK_RM;
++  int rounding = round_modes[rm];
++
++  sim_fpu sft, sft2;
++  sim_fpu sfa, sfb, sfc;
++  sim_fpu_64to (&sfa, cpu->fpregs[rs1].v[0]);
++  sim_fpu_64to (&sfb, cpu->fpregs[rs2].v[0]);
++
++  switch (op->match & mask_mul_add)
++    {
++    case MATCH_FMADD_D:
++      TRACE_INSN (cpu, "fmadd.d %s, %s, %s, %s",
++		  frd_name, frs1_name, frs2_name, frs3_name);
++      sim_fpu_64to (&sfc, cpu->fpregs[rs3].v[0]);
++      sim_fpu_mul (&sft2, &sfa, &sfb);
++      sim_fpu_add (&sft, &sfc, &sft2);
++      sim_fpu_round_64 (&sft, rounding, sim_fpu_denorm_default);
++      sim_fpu_to64 (&cpu->fpregs[rd].v[0], &sft);
++      goto done;
++    case MATCH_FMSUB_D:
++      TRACE_INSN (cpu, "fmsub.d %s, %s, %s, %s",
++		  frd_name, frs1_name, frs2_name, frs3_name);
++      sim_fpu_64to (&sfc, cpu->fpregs[rs3].v[0]);
++      sim_fpu_mul (&sft2, &sfa, &sfb);
++      sim_fpu_sub (&sft, &sft2, &sfc);
++      sim_fpu_round_64 (&sft, rounding, sim_fpu_denorm_default);
++      sim_fpu_to64 (&cpu->fpregs[rd].v[0], &sft);
++      goto done;
++    case MATCH_FNMADD_D:
++      TRACE_INSN (cpu, "fnmadd.d %s, %s, %s, %s",
++		  frd_name, frs1_name, frs2_name, frs3_name);
++      sim_fpu_64to (&sfc, cpu->fpregs[rs3].v[0]);
++      sim_fpu_mul (&sft2, &sfa, &sfb);
++      sim_fpu_add (&sft, &sfc, &sft2);
++      sim_fpu_neg (&sft, &sft);
++      sim_fpu_round_64 (&sft, rounding, sim_fpu_denorm_default);
++      sim_fpu_to64 (&cpu->fpregs[rd].v[0], &sft);
++      goto done;
++    case MATCH_FNMSUB_D:
++      TRACE_INSN (cpu, "fnmsub.d %s, %s, %s, %s",
++		  frd_name, frs1_name, frs2_name, frs3_name);
++      sim_fpu_64to (&sfc, cpu->fpregs[rs3].v[0]);
++      sim_fpu_mul (&sft2, &sfa, &sfb);
++      sim_fpu_sub (&sft, &sft2, &sfc);
++      sim_fpu_neg (&sft, &sft);
++      sim_fpu_round_64 (&sft, rounding, sim_fpu_denorm_default);
++      sim_fpu_to64 (&cpu->fpregs[rd].v[0], &sft);
++      goto done;
++    }
++
++  switch (op->match & mask_arithmetic)
++    {
++    case MATCH_FADD_D:
++      TRACE_INSN (cpu, "fadd.d %s, %s, %s",
++		  frd_name, frs1_name, frs2_name);
++      sim_fpu_add (&sft, &sfa, &sfb);
++      sim_fpu_round_64 (&sft, rounding, sim_fpu_denorm_default);
++      sim_fpu_to64 (&cpu->fpregs[rd].v[0], &sft);
++      goto done;
++    case MATCH_FSUB_D:
++      TRACE_INSN (cpu, "fsub.d %s, %s, %s",
++		  frd_name, frs1_name, frs2_name);
++      sim_fpu_sub (&sft, &sfa, &sfb);
++      sim_fpu_round_64 (&sft, rounding, sim_fpu_denorm_default);
++      sim_fpu_to64 (&cpu->fpregs[rd].v[0], &sft);
++      goto done;
++    case MATCH_FMUL_D:
++      TRACE_INSN (cpu, "fmul.d %s, %s, %s",
++		  frd_name, frs1_name, frs2_name);
++      sim_fpu_mul (&sft, &sfa, &sfb);
++      sim_fpu_round_64 (&sft, rounding, sim_fpu_denorm_default);
++      sim_fpu_to64 (&cpu->fpregs[rd].v[0], &sft);
++      goto done;
++    case MATCH_FDIV_D:
++      TRACE_INSN (cpu, "fdiv.d %s, %s, %s",
++		  frd_name, frs1_name, frs2_name);
++      sim_fpu_div (&sft, &sfa, &sfb);
++      sim_fpu_round_64 (&sft, rounding, sim_fpu_denorm_default);
++      sim_fpu_to64 (&cpu->fpregs[rd].v[0], &sft);
++      goto done;
++    case MATCH_FSQRT_D:
++      TRACE_INSN (cpu, "fsqrt.d %s, %s",
++		  frd_name, frs1_name);
++      sim_fpu_sqrt (&sft, &sfa);
++      sim_fpu_round_64 (&sft, rounding, sim_fpu_denorm_default);
++      sim_fpu_to64 (&cpu->fpregs[rd].v[0], &sft);
++      goto done;
++    }
++
++  switch (op->match & mask_convert)
++    {
++    case MATCH_FCVT_W_D:
++      TRACE_INSN (cpu, "fcvt.w.d %s, %s",
++		  rd_name, frs1_name);
++      sim_fpu_to32i (&i32, &sfa, rounding);
++      cpu->regs[rd] = i32;
++      goto done;
++    case MATCH_FCVT_WU_D:
++      TRACE_INSN (cpu, "fcvt.wu.d %s, %s",
++		  rd_name, frs1_name);
++      sim_fpu_to32u (&u32, &sfa, rounding);
++      i32 = u32;
++      cpu->regs[rd] = i32;
++      goto done;
++    case MATCH_FCVT_D_W:
++      TRACE_INSN (cpu, "fcvt.d.w %s, %s",
++		  frd_name, rs1_name);
++      sim_fpu_i32to (&sft, cpu->regs[rs1], rounding);
++      sim_fpu_to64 ((unsigned64 *) (cpu->fpregs + rd), &sft);
++      goto done;
++    case MATCH_FCVT_D_WU:
++      TRACE_INSN (cpu, "fcvt.d.wu %s, %s",
++		  frd_name, rs1_name);
++      sim_fpu_u32to (&sft, cpu->regs[rs1], rounding);
++      sim_fpu_to64 ((unsigned64 *) (cpu->fpregs + rd), &sft);
++      goto done;
++    case MATCH_FCVT_S_D:
++      TRACE_INSN (cpu, "fcvt.s.d %s, %s",
++		  frd_name, frs1_name);
++      sft = sfa;
++      sim_fpu_round_32 (&sft, sim_fpu_round_near, sim_fpu_denorm_default);
++      sim_fpu_to32 ((unsigned32 *) (cpu -> fpregs + rd), &sft);
++      goto done;
++    case MATCH_FCVT_D_S:
++      TRACE_INSN (cpu, "fcvt.d.s %s, %s",
++		  frd_name, frs1_name);
++      sim_fpu_32to (&sft, cpu->fpregs[rs1].w[0]);
++      sim_fpu_to64 (&cpu->fpregs[rd].v[0], &sft);
++      goto done;
++    case MATCH_FCVT_L_D:
++      TRACE_INSN (cpu, "fcvt.l.d %s, %s",
++		  rd_name, frs1_name);
++      cpu->regs[rd] = (int64_t) cpu->fpregs[rs1].D[0];
++      goto done;
++    case MATCH_FCVT_LU_D:
++      TRACE_INSN (cpu, "fcvt.lu.d %s, %s",
++		  rd_name, frs1_name);
++      cpu->regs[rd] = (uint64_t) cpu->fpregs[rs1].D[0];
++      goto done;
++    case MATCH_FCVT_D_L:
++      TRACE_INSN (cpu, "fcvt.d.l %s, %s",
++		  frd_name, rs1_name);
++      cpu->fpregs[rd].D[0] = (double) ((int64_t) cpu->regs[rs1]);
++      goto done;
++    case MATCH_FCVT_D_LU:
++      TRACE_INSN (cpu, "fcvt.d.lu %s, %s",
++		  frd_name, rs1_name);
++      cpu->fpregs[rd].D[0] = (double) cpu->regs[rs1];
++      goto done;
++    }
++
++  switch (op->match)
++    {
++    case MATCH_FLD:
++      TRACE_INSN (cpu, "fld %s, %" PRIiTW "(%s)",
++		  frd_name, i_imm, rs1_name);
++      store_frd64 (cpu, rd,
++	sim_core_read_unaligned_8 (cpu, cpu->pc, read_map,
++				   cpu->regs[rs1] + i_imm));
++      break;
++    case MATCH_FSD:
++      TRACE_INSN (cpu, "fsd %s, %" PRIiTW "(%s)",
++		  frs2_name, s_imm, rs1_name);
++      sim_core_write_unaligned_8 (cpu, cpu->pc, write_map,
++				  cpu->regs[rs1] + s_imm,
++				  cpu->fpregs[rs2].v[0]);
++      break;
++    case MATCH_FSGNJ_D:
++      TRACE_INSN (cpu, "fsgnj.d %s, %s, %s",
++		  frd_name, frs1_name, frs2_name);
++      u32 = cpu->fpregs[rs1].w[1] & 0x7fffffff;
++      u32 |= cpu->fpregs[rs2].w[1] & 0x80000000;
++      cpu->fpregs[rd].w[1] = u32;
++      cpu->fpregs[rd].w[0] = cpu->fpregs[rs1].w[0];
++      break;
++    case MATCH_FSGNJN_D:
++      TRACE_INSN (cpu, "fsgnjn.d %s, %s, %s",
++		  frd_name, frs1_name, frs2_name);
++      u32 = cpu->fpregs[rs1].w[1] & 0x7fffffff;
++      u32 |= (cpu->fpregs[rs2].w[1] & 0x80000000) ^ 0x80000000;
++      cpu->fpregs[rd].w[1] = u32;
++      cpu->fpregs[rd].w[0] = cpu->fpregs[rs1].w[0];
++      break;
++    case MATCH_FSGNJX_D:
++      TRACE_INSN (cpu, "fsgnjx.d %s, %s, %s",
++		  frd_name, frs1_name, frs2_name);
++      u32 = cpu->fpregs[rs1].w[1] & 0x7fffffff;
++      u32 |= (cpu->fpregs[rs1].w[1] & 0x80000000) ^ (cpu->fpregs[rs2].w[1] & 0x80000000);
++      cpu->fpregs[rd].w[1] = u32;
++      cpu->fpregs[rd].w[0] = cpu->fpregs[rs1].w[0];
++      break;
++    case MATCH_FMIN_D:
++      TRACE_INSN (cpu, "fmin.d %s, %s, %s",
++		  frd_name, frs1_name, frs2_name);
++      if (cpu->fpregs[rs1].D[0] < cpu->fpregs[rs2].D[0])
++	cpu->fpregs[rd].D[0] = cpu->fpregs[rs1].D[0];
++      else
++	cpu->fpregs[rd].D[0] = cpu->fpregs[rs2].D[0];
++      break;
++    case MATCH_FMAX_D:
++      TRACE_INSN (cpu, "fmax.d %s, %s, %s",
++		  frd_name, frs1_name, frs2_name);
++      if (cpu->fpregs[rs1].D[0] > cpu->fpregs[rs2].D[0])
++	cpu->fpregs[rd].D[0] = cpu->fpregs[rs1].D[0];
++      else
++	cpu->fpregs[rd].D[0] = cpu->fpregs[rs2].D[0];
++      break;
++    case MATCH_FMV_X_D:
++      TRACE_INSN (cpu, "fmv.x.d %s, %s",
++		  rd_name, frs1_name);
++      cpu->regs[rd] = cpu->fpregs[rs1].v[0];
++      break;
++    case MATCH_FMV_D_X:
++      TRACE_INSN (cpu, "fmv.d.x %s, %s",
++		  frd_name, frs1_name);
++      cpu->fpregs[rd].v[0] = cpu->regs[rs1];
++      break;
++    case MATCH_FEQ_D:
++      TRACE_INSN (cpu, "feq.d %s, %s, %s",
++		  rd_name, frs1_name, frs2_name);
++      cpu->regs[rd] = sim_fpu_is_eq (&sfa, &sfb);
++      break;
++    case MATCH_FLE_D:
++      TRACE_INSN (cpu, "fle.d %s, %s, %s",
++		  rd_name, frs1_name, frs2_name);
++      cpu->regs[rd] = sim_fpu_is_le (&sfa, &sfb);
++      break;
++    case MATCH_FLT_D:
++      TRACE_INSN (cpu, "flt.d %s, %s, %s",
++		  rd_name, frs1_name, frs2_name);
++      cpu->regs[rd] = sim_fpu_is_lt (&sfa, &sfb);
++      break;
++    case MATCH_FCLASS_D:
++      TRACE_INSN (cpu, "fclass.d %s, %s",
++		  rd_name, frs1_name);
++      switch (sim_fpu_is (&sfa))
++	{
++	case SIM_FPU_IS_NINF:
++	  cpu->regs[rd] = 1;
++	  break;
++	case SIM_FPU_IS_NNUMBER:
++	  cpu->regs[rd] = 1 << 1;
++	  break;
++	case SIM_FPU_IS_NDENORM:
++	  cpu->regs[rd] = 1 << 2;
++	  break;
++	case SIM_FPU_IS_NZERO:
++	  cpu->regs[rd] = 1 << 3;
++	  break;
++	case SIM_FPU_IS_PZERO:
++	  cpu->regs[rd] = 1 << 4;
++	  break;
++	case SIM_FPU_IS_PDENORM:
++	  cpu->regs[rd] = 1 << 5;
++	  break;
++	case SIM_FPU_IS_PNUMBER:
++	  cpu->regs[rd] = 1 << 6;
++	  break;
++	case SIM_FPU_IS_PINF:
++	  cpu->regs[rd] = 1 << 7;
++	  break;
++	case SIM_FPU_IS_SNAN:
++	  cpu->regs[rd] = 1 << 8;
++	  break;
++	case SIM_FPU_IS_QNAN:
++	  cpu->regs[rd] = 1 << 9;
++	  break;
++	}
++      break;
++    default:
++      TRACE_INSN (cpu, "UNHANDLED INSN: %s", op->name);
++      sim_engine_halt (sd, cpu, NULL, cpu->pc, sim_signalled, SIM_SIGILL);
++    }
++
++ done:
++  return pc;
++
++}
++
++static sim_cia
++execute_f (SIM_CPU *cpu, unsigned_word iw, const struct riscv_opcode *op)
++{
++  SIM_DESC sd = CPU_STATE (cpu);
++  unsigned int mask_arithmetic = MASK_FADD_S;
++  unsigned int mask_mul_add = MASK_FMADD_S;
++  unsigned int mask_convert = MASK_FCVT_S_W;
++
++  static const int round_modes[] =
++  {
++      sim_fpu_round_near, sim_fpu_round_zero,
++      sim_fpu_round_down, sim_fpu_round_up,
++      sim_fpu_round_default, sim_fpu_round_default,
++      sim_fpu_round_default
++  };
++
++  int rd = (iw >> OP_SH_RD) & OP_MASK_RD;
++  int rs1 = (iw >> OP_SH_RS1) & OP_MASK_RS1;
++  int rs2 = (iw >> OP_SH_RS2) & OP_MASK_RS2;
++  int rs3 = (iw >> OP_SH_RS3) & OP_MASK_RS3;
++  const char *frd_name = riscv_fpr_names_abi[rd];
++  const char *frs1_name = riscv_fpr_names_abi[rs1];
++  const char *frs2_name = riscv_fpr_names_abi[rs2];
++  const char *frs3_name = riscv_fpr_names_abi[rs3];
++  const char *rd_name = riscv_gpr_names_abi[rd];
++  const char *rs1_name = riscv_gpr_names_abi[rs1];
++  unsigned_word i_imm = EXTRACT_ITYPE_IMM (iw);
++  unsigned_word s_imm = EXTRACT_STYPE_IMM (iw);
++  uint32_t u32;
++  int32_t i32;
++  int64_t i64;
++  uint64_t u64;
++  sim_cia pc = cpu->pc + 4;
++
++  /* Rounding mode.  */
++  int rm = (iw >> OP_SH_RM) & OP_MASK_RM;
++  int rounding = round_modes[rm];
++
++  sim_fpu sft, sft2;
++  sim_fpu sfa, sfb, sfc;
++  sim_fpu_32to (&sfa, cpu->fpregs[rs1].w[0]);
++  sim_fpu_32to (&sfb, cpu->fpregs[rs2].w[0]);
++
++  switch (op->match & mask_mul_add)
++    {
++    case MATCH_FMADD_S:
++      TRACE_INSN (cpu, "fmadd.s %s, %s, %s, %s",
++		  frd_name, frs1_name, frs2_name, frs3_name);
++      sim_fpu_32to (&sfc, cpu->fpregs[rs3].w[0]);
++      sim_fpu_mul (&sft2, &sfa, &sfb);
++      sim_fpu_add (&sft, &sfc, &sft2);
++      sim_fpu_round_32 (&sft, rounding, sim_fpu_denorm_default);
++      sim_fpu_to32 (&cpu->fpregs[rd].w[0], &sft);
++      goto done;
++    case MATCH_FMSUB_S:
++      TRACE_INSN (cpu, "fmsub.s %s, %s, %s, %s",
++		  frd_name, frs1_name, frs2_name, frs3_name);
++      sim_fpu_32to (&sfc, cpu->fpregs[rs3].w[0]);
++      sim_fpu_mul (&sft2, &sfa, &sfb);
++      sim_fpu_sub (&sft, &sft2, &sfc);
++      sim_fpu_round_32 (&sft, rounding, sim_fpu_denorm_default);
++      sim_fpu_to32 (&cpu->fpregs[rd].w[0], &sft);
++      goto done;
++    case MATCH_FNMADD_S:
++      TRACE_INSN (cpu, "fnmadd.s %s, %s, %s, %s",
++		  frd_name, frs1_name, frs2_name, frs3_name);
++      sim_fpu_32to (&sfc, cpu->fpregs[rs3].w[0]);
++      sim_fpu_mul (&sft2, &sfa, &sfb);
++      sim_fpu_add (&sft, &sfc, &sft2);
++      sim_fpu_neg (&sft, &sft);
++      sim_fpu_round_32 (&sft, rounding, sim_fpu_denorm_default);
++      sim_fpu_to32 (&cpu->fpregs[rd].w[0], &sft);
++      goto done;
++    case MATCH_FNMSUB_S:
++      TRACE_INSN (cpu, "fnmsub.s %s, %s, %s, %s",
++		  frd_name, frs1_name, frs2_name, frs3_name);
++      sim_fpu_32to (&sfc, cpu->fpregs[rs3].w[0]);
++      sim_fpu_mul (&sft2, &sfa, &sfb);
++      sim_fpu_sub (&sft, &sft2, &sfc);
++      sim_fpu_neg (&sft, &sft);
++      sim_fpu_round_32 (&sft, rounding, sim_fpu_denorm_default);
++      sim_fpu_to32 (&cpu->fpregs[rd].w[0], &sft);
++      goto done;
++    }
++
++  switch (op->match & mask_arithmetic)
++    {
++    case MATCH_FADD_S:
++      TRACE_INSN (cpu, "fadd.s %s, %s, %s",
++		  frd_name, frs1_name, frs2_name);
++      sim_fpu_add (&sft, &sfa, &sfb);
++      sim_fpu_round_32 (&sft, rounding, sim_fpu_denorm_default);
++      sim_fpu_to32 (&cpu->fpregs[rd].w[0], &sft);
++      goto done;
++    case MATCH_FSUB_S:
++      TRACE_INSN (cpu, "fsub.s %s, %s, %s",
++		  frd_name, frs1_name, frs2_name);
++      sim_fpu_sub (&sft, &sfa, &sfb);
++      sim_fpu_round_32 (&sft, rounding, sim_fpu_denorm_default);
++      sim_fpu_to32 (&cpu->fpregs[rd].w[0], &sft);
++      goto done;
++    case MATCH_FMUL_S:
++      TRACE_INSN (cpu, "fmul.s %s, %s, %s",
++		  frd_name, frs1_name, frs2_name);
++      sim_fpu_mul (&sft, &sfa, &sfb);
++      sim_fpu_round_64 (&sft, rounding, sim_fpu_denorm_default);
++      sim_fpu_round_32 (&sft, rounding, sim_fpu_denorm_default);
++      sim_fpu_to32 (&cpu->fpregs[rd].w[0], &sft);
++      goto done;
++    case MATCH_FDIV_S:
++      TRACE_INSN (cpu, "fdiv.s %s, %s, %s",
++		  frd_name, frs1_name, frs2_name);
++      sim_fpu_div (&sft, &sfa, &sfb);
++      sim_fpu_round_32 (&sft, rounding, sim_fpu_denorm_default);
++      sim_fpu_to32 (&cpu->fpregs[rd].w[0], &sft);
++      goto done;
++    case MATCH_FSQRT_S:
++      TRACE_INSN (cpu, "fsqrt.s %s, %s, %s",
++		  frd_name, frs1_name, frs2_name);
++      sim_fpu_sqrt (&sft, &sfa);
++      sim_fpu_to32 (&cpu->fpregs[rd].w[0], &sft);
++      goto done;
++    }
++
++  switch (op->match & mask_convert)
++    {
++    case MATCH_FCVT_W_S:
++      TRACE_INSN (cpu, "fcvt.w.s %s, %s",
++		  rd_name, frs1_name);
++      sim_fpu_to32i (&i32, &sfa, rounding);
++      cpu->regs[rd] = i32;
++      goto done;
++    case MATCH_FCVT_WU_S:
++      TRACE_INSN (cpu, "fcvt.wu.s %s, %s",
++		  rd_name, frs1_name);
++      sim_fpu_to32u (&u32, &sfa, rounding);
++      i32 = u32;
++      cpu->regs[rd] = i32;
++      goto done;
++    case MATCH_FCVT_S_W:
++      TRACE_INSN (cpu, "fcvt.s.w %s, %s",
++		  frd_name, rs1_name);
++      sim_fpu_i32to (&sft, cpu->regs[rs1], rounding);
++      sim_fpu_round_32 (&sft, rounding, sim_fpu_denorm_default);
++      sim_fpu_to32 ((unsigned32 *) (cpu->fpregs + rd), &sft);
++      goto done;
++    case MATCH_FCVT_S_WU:
++      TRACE_INSN (cpu, "fcvt.s.wu %s, %s",
++		  frd_name, rs1_name);
++      sim_fpu_u32to (&sft, cpu->regs[rs1], rounding);
++      sim_fpu_round_32 (&sft, rounding, sim_fpu_denorm_default);
++      sim_fpu_to32 ((unsigned32 *) (cpu->fpregs + rd), &sft);
++      goto done;
++    case MATCH_FCVT_L_S:
++      TRACE_INSN (cpu, "fcvt.l.s %s, %s",
++		  rd_name, frs1_name);
++      cpu->regs[rd] = (int64_t) cpu->fpregs[rs1].S[0];
++      goto done;
++    case MATCH_FCVT_LU_S:
++      TRACE_INSN (cpu, "fcvt.lu.s %s, %s",
++		  rd_name, frs1_name);
++      cpu->regs[rd] = (uint64_t) cpu->fpregs[rs1].S[0];
++      goto done;
++    case MATCH_FCVT_S_L:
++      TRACE_INSN (cpu, "fcvt.s.l %s, %s",
++		  frd_name, rs1_name);
++      cpu->fpregs[rd].S[0] = (float) ((int64_t) cpu->regs[rs1]);
++      goto done;
++    case MATCH_FCVT_S_LU:
++      TRACE_INSN (cpu, "fcvt.s.lu %s, %s",
++		  frd_name, rs1_name);
++      cpu->fpregs[rd].S[0] = (float) cpu->regs[rs1];
++      goto done;
++    }
++
++  switch (op->match)
++    {
++    case MATCH_FLW:
++      TRACE_INSN (cpu, "flw %s, %" PRIiTW "(%s)",
++		  frd_name, i_imm, rs1_name);
++      store_frd (cpu, rd, EXTEND32 (
++	sim_core_read_unaligned_4 (cpu, cpu->pc, read_map,
++				   cpu->regs[rs1] + i_imm)));
++      break;
++    case MATCH_FSW:
++      TRACE_INSN (cpu, "fsw %s, %" PRIiTW "(%s)",
++		  frs2_name, s_imm, rs1_name);
++      sim_core_write_unaligned_4 (cpu, cpu->pc, write_map,
++				  cpu->regs[rs1] + s_imm, cpu->fpregs[rs2].w[0]);
++      break;
++    case MATCH_FSGNJ_S:
++      TRACE_INSN (cpu, "fsgnj.s %s, %s, %s",
++		  frd_name, frs1_name, frs2_name);
++      u32 = cpu->fpregs[rs1].w[0] & 0x7fffffff;
++      u32 |= cpu->fpregs[rs2].w[0] & 0x80000000;
++      cpu->fpregs[rd].w[0] = u32;
++      break;
++    case MATCH_FSGNJN_S:
++      TRACE_INSN (cpu, "fsgnjn.s %s, %s, %s",
++		  frd_name, frs1_name, frs2_name);
++      u32 = cpu->fpregs[rs1].w[0] & 0x7fffffff;
++      u32 |= (cpu->fpregs[rs2].w[0] & 0x80000000) ^ 0x80000000;
++      cpu->fpregs[rd].w[0] = u32;
++      break;
++    case MATCH_FSGNJX_S:
++      TRACE_INSN (cpu, "fsgnx.s %s, %s, %s",
++		  frd_name, frs1_name, frs2_name);
++      u32 = cpu->fpregs[rs1].w[0] & 0x7fffffff;
++      u32 |= (cpu->fpregs[rs1].w[0] & 0x80000000) ^ (cpu->fpregs[rs2].w[0] & 0x80000000);
++      cpu->fpregs[rd].w[0] = u32;
++      break;
++    case MATCH_FMIN_S:
++      TRACE_INSN (cpu, "fmin.s %s, %s, %s",
++		  frd_name, frs1_name, frs2_name);
++      if (cpu->fpregs[rs1].S[0] < cpu->fpregs[rs2].S[0])
++	cpu->fpregs[rd].S[0] = cpu->fpregs[rs1].S[0];
++      else
++	cpu->fpregs[rd].S[0] = cpu->fpregs[rs2].S[0];
++      break;
++    case MATCH_FMAX_S:
++      TRACE_INSN (cpu, "fmax.s %s, %s, %s",
++		  frd_name, frs1_name, frs2_name);
++      if (cpu->fpregs[rs1].S[0] > cpu->fpregs[rs2].S[0])
++	cpu->fpregs[rd].S[0] = cpu->fpregs[rs1].S[0];
++      else
++	cpu->fpregs[rd].S[0] = cpu->fpregs[rs2].S[0];
++      break;
++    case MATCH_FMV_X_S:
++      TRACE_INSN (cpu, "fmv.x.s %s, %s",
++		  rd_name, frs1_name);
++      cpu->regs[rd] = cpu->fpregs[rs1].W[0];
++      break;
++    case MATCH_FMV_S_X:
++      TRACE_INSN (cpu, "fmv.s.x %s, %s",
++		  frd_name, rs1_name);
++      cpu->fpregs[rd].w[0] = cpu->regs[rs1];
++      break;
++    case MATCH_FEQ_S:
++      TRACE_INSN (cpu, "feq.s %s, %s, %s",
++		  rd_name, frs1_name, frs2_name);
++      cpu->regs[rd] = sim_fpu_is_eq (&sfa, &sfb);
++      break;
++    case MATCH_FLE_S:
++      TRACE_INSN (cpu, "fle.s %s, %s, %s",
++		  rd_name, frs1_name, frs2_name);
++      cpu->regs[rd] = sim_fpu_is_le (&sfa, &sfb);
++      break;
++    case MATCH_FLT_S:
++      TRACE_INSN (cpu, "flt.s %s, %s, %s",
++		  rd_name, frs1_name, frs2_name);
++      cpu->regs[rd] = sim_fpu_is_lt (&sfa, &sfb);
++      break;
++    case MATCH_FCLASS_S:
++      TRACE_INSN (cpu, "fclass.s %s, %s",
++		  rd_name, frs1_name);
++      switch (sim_fpu_is (&sfa))
++	{
++	case SIM_FPU_IS_NINF:
++	  cpu->regs[rd] = 1;
++	  break;
++	case SIM_FPU_IS_NNUMBER:
++	  cpu->regs[rd] = 1 << 1;
++	  break;
++	case SIM_FPU_IS_NDENORM:
++	  cpu->regs[rd] = 1 << 2;
++	  break;
++	case SIM_FPU_IS_NZERO:
++	  cpu->regs[rd] = 1 << 3;
++	  break;
++	case SIM_FPU_IS_PZERO:
++	  cpu->regs[rd] = 1 << 4;
++	  break;
++	case SIM_FPU_IS_PDENORM:
++	  cpu->regs[rd] = 1 << 5;
++	  break;
++	case SIM_FPU_IS_PNUMBER:
++	  cpu->regs[rd] = 1 << 6;
++	  break;
++	case SIM_FPU_IS_PINF:
++	  cpu->regs[rd] = 1 << 7;
++	  break;
++	case SIM_FPU_IS_SNAN:
++	  cpu->regs[rd] = 1 << 8;
++	  break;
++	case SIM_FPU_IS_QNAN:
++	  cpu->regs[rd] = 1 << 9;
++	  break;
++	}
++      break;
++    case MATCH_FRCSR:
++      TRACE_INSN (cpu, "frcsr %s",
++		  rd_name);
++      store_rd (cpu, rd, fetch_csr (cpu, "fcsr", CSR_FCSR, &cpu->csr.fcsr));
++      break;
++    case MATCH_FSCSR:
++      TRACE_INSN (cpu, "fscsr %s, %sf",
++		  rd_name, rs1_name);
++      store_rd (cpu, rd, fetch_csr (cpu, "fcsr", CSR_FCSR, &cpu->csr.fcsr));
++      store_csr (cpu, "fcsr", CSR_FCSR, &cpu->csr.fcsr, cpu->regs[rs1]);
++      break;
++    case MATCH_FRRM:
++      TRACE_INSN (cpu, "frrm %s",
++		  rd_name);
++      store_rd (cpu, rd, fetch_csr (cpu, "frm", CSR_FRM, &cpu->csr.frm));
++      break;
++    case MATCH_FSRM:
++      TRACE_INSN (cpu, "fsrm %s, %s",
++		  rd_name, rs1_name);
++      store_rd (cpu, rd, fetch_csr (cpu, "frm", CSR_FCSR, &cpu->csr.frm));
++      store_csr (cpu, "frm", CSR_FCSR, &cpu->csr.frm, cpu->regs[rs1]);
++      break;
++    case MATCH_FRFLAGS:
++      TRACE_INSN (cpu, "frflags %s",
++		  rd_name);
++      store_rd (cpu, rd, fetch_csr (cpu, "fflags", CSR_FFLAGS, &cpu->csr.fflags));
++      break;
++    case MATCH_FSFLAGS:
++      TRACE_INSN (cpu, "fsflags %s, %s",
++		  rd_name, frs1_name);
++      store_rd (cpu, rd, fetch_csr (cpu, "fflags", CSR_FFLAGS, &cpu->csr.fflags));
++      store_csr (cpu, "fflags", CSR_FFLAGS, &cpu->csr.fflags, cpu->regs[rs1]);
++      break;
++    default:
++      TRACE_INSN (cpu, "UNHANDLED INSN: %s", op->name);
++      sim_engine_halt (sd, cpu, NULL, cpu->pc, sim_signalled, SIM_SIGILL);
++    }
++
++ done:
++  return pc;
++}
++
++static sim_cia
++execute_c (SIM_CPU *cpu, unsigned_word iw, const struct riscv_opcode *op)
++{
++  SIM_DESC sd = CPU_STATE (cpu);
++  const int mask_group_op = 0x3;
++  const int mask_mv_jr = 0xf003;
++  const int match_mv_jr = 0x8002;
++  const int mask_ebk_jalr_add = 0xf003;
++  const int match_ebk_jalr_add = 0x9002;
++
++  int rd = (iw >> OP_SH_RD) & OP_MASK_RD;
++  int crs2 = (iw >> OP_SH_CRS2) & OP_MASK_CRS2;
++  int crs1s = ((iw >> OP_SH_CRS1S) & OP_MASK_CRS1S) | 0x8;
++  int crs2s = ((iw >> OP_SH_CRS2S) & OP_MASK_CRS2S) | 0x8;
++  int ciw_rd = crs2s;
++  unsigned_word rvc_imm = EXTRACT_RVC_IMM (iw);
++  unsigned_word tmp;
++  sim_cia pc = cpu->pc + 2;
++
++  const char *rd_name = riscv_gpr_names_abi[rd];
++  const char *crs2_name = riscv_gpr_names_abi[crs2];
++  const char *crs1s_name = riscv_gpr_names_abi[crs1s];
++  const char *crs2s_name = riscv_gpr_names_abi[crs2s];
++  const char *ciw_rd_name = crs2s_name;
++
++  const char *frd_name = riscv_fpr_names_abi[rd];
++  const char *fcrs2_name = riscv_fpr_names_abi[crs2];
++  const char *fcrs1s_name = riscv_fpr_names_abi[crs1s];
++  const char *fcrs2s_name = riscv_fpr_names_abi[crs2s];
++  const char *fciw_rd_name = fcrs2s_name;
++
++  /* Deal with c.mv, c.jr instructons.  */
++  if ((op->match & mask_mv_jr) == match_mv_jr)
++    {
++      if (crs2 != 0)
++	{
++	  /* c.mv */
++	  TRACE_INSN (cpu, "c.mv %s, %s // %s = %s",
++		      rd_name, crs2_name, rd_name, crs2_name);
++	  cpu->regs[rd] = cpu->regs[crs2];
++	}
++      else
++	{
++	  /* c.jr */
++	  TRACE_INSN (cpu, "c.jr %s", rd_name);
++	  pc = cpu->regs[rd];
++	}
++      return pc;
++    }
++
++  /* Deal with c.ebreak, c.jalr, c.add instructions.  */
++  if ((op->match & mask_ebk_jalr_add) == match_ebk_jalr_add)
++    {
++      if (iw == MATCH_C_EBREAK)
++	{
++	  /* c.ebreak */
++	  TRACE_INSN (cpu, "c.break");
++	  sim_engine_halt (sd, cpu, NULL, cpu->pc, sim_stopped, SIM_SIGTRAP);
++	}
++      else if (crs2 == 0)
++	{
++	  /* c.jalr */
++	  TRACE_INSN (cpu, "c.jalr %s", rd_name);
++	  pc = cpu->regs[rd];
++	  store_rd (cpu, X_RA, cpu->pc + 2);
++	}
++      else
++	{
++	  /* c.add */
++	  TRACE_INSN (cpu, "c.add %s, %s // %s += %s",
++		      rd_name, crs2_name, rd_name, crs2_name);
++	  store_rd (cpu, rd, cpu->regs[rd] + cpu->regs[crs2]);
++	}
++      return pc;
++    }
++
++  switch (op->match & mask_group_op)
++    {
++    case 0:
++      switch (op->match)
++	{
++	case MATCH_C_LW:
++	  TRACE_INSN (cpu, "c.lw %s, %" PRIiTW "(%s);"
++			   " // %s = *(%s + %" PRIiTW ")",
++		      crs2s_name, EXTRACT_RVC_LW_IMM (iw), crs1s_name,
++		      crs2s_name, crs1s_name, EXTRACT_RVC_LW_IMM (iw));
++	  store_rd (cpu, crs2s, EXTEND32 (
++	    sim_core_read_unaligned_4 (cpu, cpu->pc, read_map,
++				       cpu->regs[crs1s]
++				       + EXTRACT_RVC_LW_IMM (iw))));
++	  return pc;
++	case MATCH_C_SW:
++	  TRACE_INSN (cpu, "c.sw %s, %" PRIiTW "(%s);"
++			   " // *(%s + %" PRIiTW ") = %s",
++		      crs2s_name, EXTRACT_RVC_LW_IMM (iw), crs1s_name,
++		      crs1s_name, EXTRACT_RVC_LW_IMM (iw), crs2s_name);
++	  sim_core_write_unaligned_4 (cpu, cpu->pc, write_map,
++				      (cpu->regs[crs1s]
++				       + EXTRACT_RVC_LW_IMM (iw)),
++				      cpu->regs[crs2s]);
++	  return pc;
++	case MATCH_C_ADDI4SPN:
++	  TRACE_INSN (cpu, "c.addi4spn %s, %" PRIiTW
++			   " // %s = sp + %" PRIiTW,
++		      ciw_rd_name, EXTRACT_RVC_ADDI4SPN_IMM (iw),
++		      ciw_rd_name, EXTRACT_RVC_ADDI4SPN_IMM (iw));
++	  store_rd (cpu, ciw_rd, cpu->sp + EXTRACT_RVC_ADDI4SPN_IMM (iw));
++	  return pc;
++	case MATCH_C_FLD:
++	  if (RISCV_XLEN (cpu) <= 64)
++	    {
++	      TRACE_INSN (cpu, "c.fld %s, %" PRIiTW "(%s);"
++			       " // %s = *(%s + %" PRIiTW ")",
++			  fcrs2s_name, EXTRACT_RVC_LD_IMM (iw), fcrs1s_name,
++			  fcrs2s_name, fcrs1s_name, EXTRACT_RVC_LD_IMM (iw));
++	      /* rv32/64, c.fld instruction.  */
++	      store_frd64 (cpu, crs2s,
++		sim_core_read_unaligned_8 (cpu, cpu->pc, read_map,
++					   cpu->regs[crs1s]
++					   + EXTRACT_RVC_LD_IMM (iw)));
++	      return pc;
++	    }
++	  else
++	    {
++	      /* rv128, c.lq instruction.  */
++	      TRACE_INSN (cpu, "UNHANDLED RV128 INSN: %s", op->name);
++	      sim_engine_halt (sd, cpu, NULL, cpu->pc,
++			       sim_signalled, SIM_SIGILL);
++	    }
++	case MATCH_C_FLW:
++	  /* rv32: c.flw, rv64: c.ld.  */
++	  if (RISCV_XLEN (cpu) == 32)
++	    {
++	      TRACE_INSN (cpu, "c.flw %s, %" PRIiTW "(%s);"
++			       " // *(%s + %" PRIiTW ") = %s",
++			  fcrs2s_name, EXTRACT_RVC_LW_IMM (iw), crs1s_name,
++			  crs1s_name, EXTRACT_RVC_LW_IMM (iw), fcrs2s_name);
++	      store_frd (cpu, crs2s, EXTEND32 (
++		sim_core_read_unaligned_4 (cpu, cpu->pc, read_map,
++					   cpu->regs[crs1s]
++					   + EXTRACT_RVC_LW_IMM (iw))));
++	    }
++	  else
++	    {
++	      TRACE_INSN (cpu, "c.ld %s, %" PRIiTW "(%s);"
++			       " // *(%s + %" PRIiTW ") = %s",
++			  crs2s_name, EXTRACT_RVC_LD_IMM (iw), crs1s_name,
++			  crs1s_name, EXTRACT_RVC_LD_IMM (iw), crs2s_name);
++	      store_rd (cpu, crs2s,
++		sim_core_read_unaligned_8 (cpu, cpu->pc, read_map,
++					   cpu->regs[crs1s]
++					   + EXTRACT_RVC_LD_IMM (iw)));
++	    }
++	  return pc;
++	case MATCH_C_FSD:
++	  if (RISCV_XLEN (cpu) <= 64)
++	    {
++	      /* rv32/64, c.fsd instruction.  */
++	      TRACE_INSN (cpu, "c.fsd %s, %" PRIiTW "(%s);"
++			       " // *(%s + %" PRIiTW ") = %s",
++			  fcrs2s_name, EXTRACT_RVC_LD_IMM (iw), crs1s_name,
++			  crs1s_name, EXTRACT_RVC_LD_IMM (iw), fcrs2s_name);
++	      sim_core_write_unaligned_8 (cpu, cpu->pc, write_map,
++					  cpu->regs[crs1s]
++					  + EXTRACT_RVC_LD_IMM (iw),
++					  cpu->fpregs[crs2s].v[0]);
++	      return pc;
++	    }
++	  else
++	    {
++	      /* rv128, c.sq instruction.  */
++	      TRACE_INSN (cpu, "UNHANDLED RV128 INSN: %s", op->name);
++	      sim_engine_halt (sd, cpu, NULL, cpu->pc,
++			       sim_signalled, SIM_SIGILL);
++	    }
++	case MATCH_C_FSW:
++	  /* rv32: c.fsw, rv64: c.sd.  */
++	  if (RISCV_XLEN (cpu) == 32)
++	    {
++	      TRACE_INSN (cpu, "c.fsw %s, %" PRIiTW "(%s);"
++			       " // *(%s + %" PRIiTW ") = %s",
++			  fcrs2s_name, EXTRACT_RVC_LW_IMM (iw), crs1s_name,
++			  crs1s_name, EXTRACT_RVC_LW_IMM (iw), fcrs2s_name);
++	      sim_core_write_unaligned_4 (cpu, cpu->pc, write_map,
++					  cpu->regs[crs1s]
++					  + EXTRACT_RVC_LW_IMM (iw),
++					  cpu->fpregs[crs2s].w[0]);
++	    }
++	  else
++	    {
++	      TRACE_INSN (cpu, "c.sd %s, %" PRIiTW "(%s);"
++			       " // *(%s + %" PRIiTW ") = %s",
++			  crs2s_name, EXTRACT_RVC_LD_IMM (iw), crs1s_name,
++			  crs1s_name, EXTRACT_RVC_LD_IMM (iw), crs2s_name);
++	      sim_core_write_unaligned_8 (cpu, cpu->pc, write_map,
++					  cpu->regs[crs1s]
++					  + EXTRACT_RVC_LD_IMM (iw),
++					  cpu->regs[crs2s]);
++	    }
++	  return pc;
++	default:
++	  TRACE_INSN (cpu, "UNHANDLED INSN: %s", op->name);
++	  sim_engine_halt (sd, cpu, NULL, cpu->pc, sim_signalled, SIM_SIGILL);
++	}
++    case 1:
++      switch (op->match)
++	{
++	case MATCH_C_ADDI:
++	  if (rd != 0)
++	    {
++	      /* c.addi */
++	      TRACE_INSN (cpu, "c.addi %s, %" PRIiTW " // %s += %" PRIiTW,
++			  rd_name, rvc_imm, rd_name, rvc_imm);
++	      store_rd (cpu, rd, cpu->regs[rd] + rvc_imm);
++	      return pc;
++	    }
++	  else
++	    {
++	      /* c.nop */
++	      TRACE_INSN (cpu, "c.nop");
++	      return pc;
++	    }
++	case MATCH_C_JAL:
++	  /* In rv32 is c.jal, rv64 c.addiw.  */
++	  if (RISCV_XLEN (cpu) == 32)
++	    {
++	      TRACE_INSN (cpu, "c.jal %" PRIiTW, EXTRACT_RVC_J_IMM (iw));
++	      store_rd (cpu, X_RA, cpu->pc + 2);
++	      pc = cpu->pc + EXTRACT_RVC_J_IMM (iw);
++	    }
++	  else
++	    {
++	      TRACE_INSN (cpu, "c.addiw %s, %" PRIiTW " // %s += %" PRIiTW,
++			  rd_name, rvc_imm, rd_name, rvc_imm);
++	      store_rd (cpu, rd, EXTEND32 (cpu->regs[rd] + rvc_imm));
++	    }
++	  return pc;
++	case MATCH_C_LI:
++	  TRACE_INSN (cpu, "c.li %s, %" PRIiTW " // %s = %" PRIiTW,
++		      rd_name, rvc_imm, rd_name, rvc_imm);
++	  store_rd (cpu, rd, rvc_imm);
++	  return pc;
++	case MATCH_C_ADDI16SP:
++	  TRACE_INSN (cpu, "c.addi16sp %s, %" PRIiTW,
++		      rd_name, rvc_imm);
++	  store_rd (cpu, rd, cpu->sp + EXTRACT_RVC_ADDI16SP_IMM (iw));
++	  return pc;
++	case MATCH_C_SRLI:
++	  /* rv32: c.srli, rv128: c.srli64.  */
++	  TRACE_INSN (cpu, "c.srli %s, %" PRIiTW,
++		      crs1s_name, EXTRACT_RVC_IMM (iw));
++	  if (RISCV_XLEN (cpu) == 32 && EXTRACT_RVC_IMM (iw) > 0x1f)
++	    sim_engine_halt (sd, cpu, NULL, cpu->pc, sim_signalled, SIM_SIGILL);
++	  store_rd (cpu, crs1s, cpu->regs[crs1s] >> EXTRACT_RVC_IMM (iw));
++	  return pc;
++	case MATCH_C_SRAI:
++	  /* rv32: c.srli, rv128: c.srli64.  */
++	  TRACE_INSN (cpu, "c.srai %s, %" PRIiTW,
++		      crs1s_name, EXTRACT_RVC_IMM (iw));
++	  if (RISCV_XLEN (cpu) == 32)
++	    {
++	      if (EXTRACT_RVC_IMM (iw) > 0x1f)
++		sim_engine_halt (sd, cpu, NULL, cpu->pc,
++				 sim_signalled, SIM_SIGILL);
++	      tmp = ashiftrt (cpu->regs[crs1s], EXTRACT_RVC_IMM (iw));
++	    }
++	  else
++	    tmp = ashiftrt64 (cpu->regs[crs1s], EXTRACT_RVC_IMM (iw));
++	  store_rd (cpu, crs1s, tmp);
++	  return pc;
++	case MATCH_C_ANDI:
++	  TRACE_INSN (cpu, "c.andi %s, %" PRIiTW,
++		      crs1s_name, EXTRACT_RVC_IMM (iw));
++	  store_rd (cpu, crs1s, cpu->regs[crs1s] & EXTRACT_RVC_IMM (iw));
++	  return pc;
++	case MATCH_C_SUB:
++	  TRACE_INSN (cpu, "c.sub %s, %s",
++		      crs1s_name, crs2s_name);
++	  store_rd (cpu, crs1s, cpu->regs[crs1s] - cpu->regs[crs2s]);
++	  return pc;
++	case MATCH_C_XOR:
++	  TRACE_INSN (cpu, "c.xor %s, %s",
++		      crs1s_name, crs2s_name);
++	  store_rd (cpu, crs1s, cpu->regs[crs1s] ^ cpu->regs[crs2s]);
++	  return pc;
++	case MATCH_C_OR:
++	  TRACE_INSN (cpu, "c.or %s, %s",
++		      crs1s_name, crs2s_name);
++	  store_rd (cpu, crs1s, cpu->regs[crs1s] | cpu->regs[crs2s]);
++	  return pc;
++	case MATCH_C_AND:
++	  TRACE_INSN (cpu, "c.and %s, %s",
++		      crs1s_name, crs2s_name);
++	  store_rd (cpu, crs1s, cpu->regs[crs1s] & cpu->regs[crs2s]);
++	  return pc;
++	case MATCH_C_SUBW:
++	  TRACE_INSN (cpu, "c.subw %s, %s",
++		      crs1s_name, crs2s_name);
++	  RISCV_ASSERT_RV64 (cpu, "insn: %s", op->name);
++	  store_rd (cpu, crs1s, EXTEND32 (cpu->regs[crs1s] - cpu->regs[crs2s]));
++	  return pc;
++	case MATCH_C_ADDW:
++	  TRACE_INSN (cpu, "c.addw %s, %s",
++		      crs1s_name, crs2s_name);
++	  RISCV_ASSERT_RV64 (cpu, "insn: %s", op->name);
++	  store_rd (cpu, crs1s, EXTEND32 (cpu->regs[crs1s] + cpu->regs[crs2s]));
++	  return pc;
++	case MATCH_C_BEQZ:
++	  TRACE_INSN (cpu, "c.beqz %s, %" PRIiTW,
++		      crs1s_name, cpu->pc + EXTRACT_RVC_B_IMM (iw));
++	  if (cpu->regs[crs1s] == 0)
++	    pc = cpu->pc + EXTRACT_RVC_B_IMM (iw);
++	  return pc;
++	case MATCH_C_BNEZ:
++	  TRACE_INSN (cpu, "c.bnez %s, %" PRIiTW,
++		      crs1s_name, cpu->pc + EXTRACT_RVC_B_IMM (iw));
++	  if (cpu->regs[crs1s] != 0)
++	    pc = cpu->pc + EXTRACT_RVC_B_IMM (iw);
++	  return pc;
++	case MATCH_C_LUI:
++	  TRACE_INSN (cpu, "c.lui %s, %" PRIiTW,
++		      rd_name, EXTRACT_RVC_LUI_IMM (iw));
++	  store_rd (cpu, rd, EXTRACT_RVC_LUI_IMM (iw));
++	  return pc;
++	case MATCH_C_J:
++	  TRACE_INSN (cpu, "c.j %" PRIiTW,
++		      cpu->pc + EXTRACT_RVC_B_IMM (iw));
++	  pc = cpu->pc + EXTRACT_RVC_J_IMM (iw);
++	  return pc;
++	default:
++	  TRACE_INSN (cpu, "UNHANDLED INSN: %s", op->name);
++	  sim_engine_halt (sd, cpu, NULL, cpu->pc, sim_signalled, SIM_SIGILL);
++	}
++    case 2:
++      switch (op->match)
++	{
++	case MATCH_C_SLLI:
++	  TRACE_INSN (cpu, "c.slli %s, %" PRIiTW,
++		      rd_name, rvc_imm);
++	  /* rv32: c.slli, rv128: c.slli64.  */
++	  if (RISCV_XLEN (cpu) == 32 && rvc_imm > 0x1f)
++	    sim_engine_halt (sd, cpu, NULL, cpu->pc, sim_signalled, SIM_SIGILL);
++	  store_rd (cpu, rd, cpu->regs[rd] << rvc_imm);
++	  return pc;
++	case MATCH_C_LWSP:
++	  TRACE_INSN (cpu, "c.lwsp %s, %" PRIiTW "(sp);"
++			   " // %s = *(sp + %" PRIiTW ")",
++		      rd_name, EXTRACT_RVC_LWSP_IMM (iw),
++		      rd_name, EXTRACT_RVC_LWSP_IMM (iw));
++	  store_rd (cpu, rd, EXTEND32 (
++	    sim_core_read_unaligned_4 (cpu, cpu->pc, read_map,
++				       cpu->sp
++				       + EXTRACT_RVC_LWSP_IMM (iw))));
++	  return pc;
++	case MATCH_C_SWSP:
++	  TRACE_INSN (cpu, "c.swsp %s, %" PRIiTW "(sp);"
++			   " // *(sp + %" PRIiTW ") = %s",
++		      rd_name, EXTRACT_RVC_SWSP_IMM (iw),
++		      EXTRACT_RVC_SWSP_IMM (iw), rd_name);
++	  sim_core_write_unaligned_4 (cpu, cpu->pc, write_map,
++				      (cpu->sp + EXTRACT_RVC_SWSP_IMM (iw)),
++				      cpu->regs[crs2]);
++	  return pc;
++	case MATCH_C_ADD:
++	  TRACE_INSN (cpu, "c.add %s, %s // %s += %s",
++		      rd_name, crs2_name,
++		      rd_name, crs2_name);
++	  store_rd (cpu, rd, cpu->regs[rd] + cpu->regs[crs2]);
++	  return pc;
++	case MATCH_C_FLDSP:
++	  /* rv32/64: c.fldsp, rv128: c.flqsp.  */
++	  if (RISCV_XLEN (cpu) <= 64)
++	    {
++	      TRACE_INSN (cpu, "c.fldsp %s, %" PRIiTW "(sp);"
++			       " // %s = *(sp + %" PRIiTW ")",
++			  frd_name, EXTRACT_RVC_LDSP_IMM (iw),
++			  frd_name, EXTRACT_RVC_LDSP_IMM (iw));
++	      store_frd64 (cpu, rd,
++		sim_core_read_unaligned_8 (cpu, cpu->pc, read_map,
++					   cpu->sp
++					   + EXTRACT_RVC_LDSP_IMM (iw)));
++	      return pc;
++	    }
++	  else
++	    {
++	      TRACE_INSN (cpu, "UNHANDLED RV128 INSN: %s", op->name);
++	      sim_engine_halt (sd, cpu, NULL, cpu->pc,
++			       sim_signalled, SIM_SIGILL);
++	    }
++	case MATCH_C_FLWSP:
++	  /* rv32: c.flwsp, rv64: c.ldsp.  */
++	  if (RISCV_XLEN (cpu) == 32)
++	    {
++	      TRACE_INSN (cpu, "c.flwsp %s, %" PRIiTW "(sp);"
++			       " // %s = *(sp + %" PRIiTW ")",
++			  frd_name, EXTRACT_RVC_LWSP_IMM (iw),
++			  frd_name, EXTRACT_RVC_LWSP_IMM (iw));
++	      store_frd (cpu, rd, EXTEND32 (
++		sim_core_read_unaligned_4 (cpu, cpu->pc, read_map,
++					   cpu->sp
++					   + EXTRACT_RVC_LWSP_IMM (iw))));
++	    }
++	  else
++	    {
++	      TRACE_INSN (cpu, "c.ldsp %s, %" PRIiTW "(sp);"
++			       " // %s = *(sp + %" PRIiTW ")",
++			  rd_name, EXTRACT_RVC_LDSP_IMM (iw),
++			  rd_name, EXTRACT_RVC_LDSP_IMM (iw));
++	      store_rd (cpu, rd,
++		sim_core_read_unaligned_8 (cpu, cpu->pc, read_map,
++					   cpu->sp
++					   + EXTRACT_RVC_LDSP_IMM (iw)));
++	    }
++	  return pc;
++	case MATCH_C_FSDSP:
++	  /* rv32/64: c.fsdsp, rv128: c.fsqsp.  */
++	  if (RISCV_XLEN (cpu) <= 64)
++	    {
++	      TRACE_INSN (cpu, "c.fsdsp %s, %" PRIiTW "(sp);"
++			       " // *(sp + %" PRIiTW ") = %s",
++			  fcrs2_name, EXTRACT_RVC_LDSP_IMM (iw),
++			  EXTRACT_RVC_LDSP_IMM (iw), fcrs2_name);
++	      sim_core_write_unaligned_8 (cpu, cpu->pc, write_map,
++					  cpu->sp + EXTRACT_RVC_SDSP_IMM (iw),
++					  cpu->fpregs[crs2].v[0]);
++	      return pc;
++	    }
++	  else
++	    {
++	      TRACE_INSN (cpu, "UNHANDLED RV128 INSN: %s", op->name);
++	      sim_engine_halt (sd, cpu, NULL, cpu->pc,
++			       sim_signalled, SIM_SIGILL);
++	    }
++	case MATCH_C_FSWSP:
++	  /* rv32: c.fswsp, rv64: c.sdsp.  */
++	  if (RISCV_XLEN (cpu) == 32)
++	    {
++	      TRACE_INSN (cpu, "c.fswsp %s, %" PRIiTW "(sp);"
++			       " // *(sp + %" PRIiTW ") = %s",
++			  fcrs2_name, EXTRACT_RVC_SWSP_IMM (iw),
++			  EXTRACT_RVC_SWSP_IMM (iw), fcrs2_name);
++	      sim_core_write_unaligned_4 (cpu, cpu->pc, write_map,
++					  cpu->sp
++					  + EXTRACT_RVC_SWSP_IMM (iw),
++					  cpu->fpregs[crs2].w[0]);
++	    }
++	  else
++	    {
++	      TRACE_INSN (cpu, "c.sdsp %s, %" PRIiTW "(sp);"
++			       " // *(sp + %" PRIiTW ") = %s",
++			  crs2_name, EXTRACT_RVC_SDSP_IMM (iw),
++			  EXTRACT_RVC_SDSP_IMM (iw), crs2_name);
++	      sim_core_write_unaligned_8 (cpu, cpu->pc, write_map,
++					  cpu->sp + EXTRACT_RVC_SDSP_IMM (iw),
++					  cpu->regs[crs2]);
++	    }
++	  return pc;
++	default:
++	  TRACE_INSN (cpu, "UNHANDLED INSN: %s", op->name);
++	  sim_engine_halt (sd, cpu, NULL, cpu->pc, sim_signalled, SIM_SIGILL);
++	}
++    default:
++      TRACE_INSN (cpu, "UNHANDLED INSN: %s", op->name);
++      sim_engine_halt (sd, cpu, NULL, cpu->pc, sim_signalled, SIM_SIGILL);
++    }
++
++  return pc;
++}
++
++static sim_cia
++execute_i (SIM_CPU *cpu, unsigned_word iw, const struct riscv_opcode *op)
++{
++  SIM_DESC sd = CPU_STATE (cpu);
++  int rd = (iw >> OP_SH_RD) & OP_MASK_RD;
++  int rs1 = (iw >> OP_SH_RS1) & OP_MASK_RS1;
++  int rs2 = (iw >> OP_SH_RS2) & OP_MASK_RS2;
++  const char *rd_name = riscv_gpr_names_abi[rd];
++  const char *rs1_name = riscv_gpr_names_abi[rs1];
++  const char *rs2_name = riscv_gpr_names_abi[rs2];
++  unsigned int csr = (iw >> OP_SH_CSR) & OP_MASK_CSR;
++  unsigned_word i_imm = EXTRACT_ITYPE_IMM (iw);
++  unsigned_word u_imm = EXTRACT_UTYPE_IMM ((unsigned64) iw);
++  unsigned_word s_imm = EXTRACT_STYPE_IMM (iw);
++  unsigned_word sb_imm = EXTRACT_SBTYPE_IMM (iw);
++  unsigned_word shamt_imm = ((iw >> OP_SH_SHAMT) & OP_MASK_SHAMT);
++  unsigned_word tmp;
++  sim_cia pc = cpu->pc + 4;
++
++  TRACE_EXTRACT (cpu, "rd:%-2i:%-4s  rs1:%-2i:%-4s %0*"PRIxTW"  rs2:%-2i:%-4s %0*"PRIxTW"  match:%#x mask:%#x",
++		 rd, rd_name,
++		 rs1, rs1_name, (int)sizeof (unsigned_word) * 2, cpu->regs[rs1],
++		 rs2, rs2_name, (int)sizeof (unsigned_word) * 2, cpu->regs[rs2],
++		 (unsigned) op->match, (unsigned) op->mask);
++
++  switch (op->match)
++    {
++    case MATCH_ADD:
++      TRACE_INSN (cpu, "add %s, %s, %s;  // %s = %s + %s",
++		  rd_name, rs1_name, rs2_name, rd_name, rs1_name, rs2_name);
++      store_rd (cpu, rd, cpu->regs[rs1] + cpu->regs[rs2]);
++      break;
++    case MATCH_ADDW:
++      TRACE_INSN (cpu, "addw %s, %s, %s;  // %s = %s + %s",
++		  rd_name, rs1_name, rs2_name, rd_name, rs1_name, rs2_name);
++      RISCV_ASSERT_RV64 (cpu, "insn: %s", op->name);
++      store_rd (cpu, rd, EXTEND32 (cpu->regs[rs1] + cpu->regs[rs2]));
++      break;
++    case MATCH_ADDI:
++      TRACE_INSN (cpu, "addi %s, %s, %#"PRIxTW";  // %s = %s + %#" PRIxTW,
++		  rd_name, rs1_name, i_imm, rd_name, rs1_name, i_imm);
++      store_rd (cpu, rd, cpu->regs[rs1] + i_imm);
++      break;
++    case MATCH_ADDIW:
++      TRACE_INSN (cpu, "addiw %s, %s, %#" PRIxTW ";  // %s = %s + %#" PRIxTW,
++		  rd_name, rs1_name, i_imm, rd_name, rs1_name, i_imm);
++      RISCV_ASSERT_RV64 (cpu, "insn: %s", op->name);
++      store_rd (cpu, rd, EXTEND32 (cpu->regs[rs1] + i_imm));
++      break;
++    case MATCH_AND:
++      TRACE_INSN (cpu, "and %s, %s, %s;  // %s = %s & %s",
++		  rd_name, rs1_name, rs2_name, rd_name, rs1_name, rs2_name);
++      store_rd (cpu, rd, cpu->regs[rs1] & cpu->regs[rs2]);
++      break;
++    case MATCH_ANDI:
++      TRACE_INSN (cpu, "andi %s, %s, %" PRIiTW ";  // %s = %s & %#" PRIxTW,
++		  rd_name, rs1_name, i_imm, rd_name, rs1_name, i_imm);
++      store_rd (cpu, rd, cpu->regs[rs1] & i_imm);
++      break;
++    case MATCH_OR:
++      TRACE_INSN (cpu, "or %s, %s, %s;  // %s = %s | %s",
++		  rd_name, rs1_name, rs2_name, rd_name, rs1_name, rs2_name);
++      store_rd (cpu, rd, cpu->regs[rs1] | cpu->regs[rs2]);
++      break;
++    case MATCH_ORI:
++      TRACE_INSN (cpu, "ori %s, %s, %" PRIiTW ";  // %s = %s | %#" PRIxTW,
++		  rd_name, rs1_name, i_imm, rd_name, rs1_name, i_imm);
++      store_rd (cpu, rd, cpu->regs[rs1] | i_imm);
++      break;
++    case MATCH_XOR:
++      TRACE_INSN (cpu, "xor %s, %s, %s;  // %s = %s ^ %s",
++		  rd_name, rs1_name, rs2_name, rd_name, rs1_name, rs2_name);
++      store_rd (cpu, rd, cpu->regs[rs1] ^ cpu->regs[rs2]);
++      break;
++    case MATCH_XORI:
++      TRACE_INSN (cpu, "xori %s, %s, %" PRIiTW ";  // %s = %s ^ %#" PRIxTW,
++		  rd_name, rs1_name, i_imm, rd_name, rs1_name, i_imm);
++      store_rd (cpu, rd, cpu->regs[rs1] ^ i_imm);
++      break;
++    case MATCH_SUB:
++      TRACE_INSN (cpu, "sub %s, %s, %s;  // %s = %s - %s",
++		  rd_name, rs1_name, rs2_name, rd_name, rs1_name, rs2_name);
++      store_rd (cpu, rd, cpu->regs[rs1] - cpu->regs[rs2]);
++      break;
++    case MATCH_SUBW:
++      TRACE_INSN (cpu, "subw %s, %s, %s;  // %s = %s - %s",
++		  rd_name, rs1_name, rs2_name, rd_name, rs1_name, rs2_name);
++      RISCV_ASSERT_RV64 (cpu, "insn: %s", op->name);
++      store_rd (cpu, rd, EXTEND32 (cpu->regs[rs1] - cpu->regs[rs2]));
++      break;
++    case MATCH_LUI:
++      TRACE_INSN (cpu, "lui %s, %#"PRIxTW";", rd_name, u_imm);
++      store_rd (cpu, rd, u_imm);
++      break;
++    case MATCH_SLL:
++      TRACE_INSN (cpu, "sll %s, %s, %s;  // %s = %s << %s",
++		  rd_name, rs1_name, rs2_name, rd_name, rs1_name, rs2_name);
++      u_imm = RISCV_XLEN (cpu) == 32 ? 0x1f : 0x3f;
++      store_rd (cpu, rd, cpu->regs[rs1] << (cpu->regs[rs2] & u_imm));
++      break;
++    case MATCH_SLLW:
++      TRACE_INSN (cpu, "sllw %s, %s, %s;  // %s = %s << %s",
++		  rd_name, rs1_name, rs2_name, rd_name, rs1_name, rs2_name);
++      RISCV_ASSERT_RV64 (cpu, "insn: %s", op->name);
++      store_rd (cpu, rd, EXTEND32 ((unsigned32)cpu->regs[rs1] << (cpu->regs[rs2] & 0x1f)));
++      break;
++    case MATCH_SLLI:
++      TRACE_INSN (cpu, "slli %s, %s, %" PRIiTW ";  // %s = %s << %#" PRIxTW,
++		  rd_name, rs1_name, shamt_imm, rd_name, rs1_name, shamt_imm);
++      if (RISCV_XLEN (cpu) == 32 && shamt_imm > 0x1f)
++	sim_engine_halt (sd, cpu, NULL, cpu->pc, sim_signalled, SIM_SIGILL);
++      store_rd (cpu, rd, cpu->regs[rs1] << shamt_imm);
++      break;
++    case MATCH_SLLIW:
++      TRACE_INSN (cpu, "slliw %s, %s, %" PRIiTW ";  // %s = %s << %#" PRIxTW,
++		  rd_name, rs1_name, shamt_imm, rd_name, rs1_name, shamt_imm);
++      RISCV_ASSERT_RV64 (cpu, "insn: %s", op->name);
++      store_rd (cpu, rd, EXTEND32 ((unsigned32)cpu->regs[rs1] << shamt_imm));
++      break;
++    case MATCH_SRL:
++      TRACE_INSN (cpu, "srl %s, %s, %s;  // %s = %s >> %s",
++		  rd_name, rs1_name, rs2_name, rd_name, rs1_name, rs2_name);
++      u_imm = RISCV_XLEN (cpu) == 32 ? 0x1f : 0x3f;
++      store_rd (cpu, rd, cpu->regs[rs1] >> (cpu->regs[rs2] & u_imm));
++      break;
++    case MATCH_SRLW:
++      TRACE_INSN (cpu, "srlw %s, %s, %s;  // %s = %s >> %s",
++		  rd_name, rs1_name, rs2_name, rd_name, rs1_name, rs2_name);
++      RISCV_ASSERT_RV64 (cpu, "insn: %s", op->name);
++      store_rd (cpu, rd, EXTEND32 ((unsigned32)cpu->regs[rs1] >> (cpu->regs[rs2] & 0x1f)));
++      break;
++    case MATCH_SRLI:
++      TRACE_INSN (cpu, "srli %s, %s, %" PRIiTW ";  // %s = %s >> %#" PRIxTW,
++		  rd_name, rs1_name, shamt_imm, rd_name, rs1_name, shamt_imm);
++      if (RISCV_XLEN (cpu) == 32 && shamt_imm > 0x1f)
++	sim_engine_halt (sd, cpu, NULL, cpu->pc, sim_signalled, SIM_SIGILL);
++      store_rd (cpu, rd, cpu->regs[rs1] >> shamt_imm);
++      break;
++    case MATCH_SRLIW:
++      TRACE_INSN (cpu, "srliw %s, %s, %" PRIiTW ";  // %s = %s >> %#" PRIxTW,
++		  rd_name, rs1_name, shamt_imm, rd_name, rs1_name, shamt_imm);
++      RISCV_ASSERT_RV64 (cpu, "insn: %s", op->name);
++      store_rd (cpu, rd, EXTEND32 ((unsigned32)cpu->regs[rs1] >> shamt_imm));
++      break;
++    case MATCH_SRA:
++      TRACE_INSN (cpu, "sra %s, %s, %s;  // %s = %s >>> %s",
++		  rd_name, rs1_name, rs2_name, rd_name, rs1_name, rs2_name);
++      if (RISCV_XLEN (cpu) == 32)
++	tmp = ashiftrt (cpu->regs[rs1], cpu->regs[rs2] & 0x1f);
++      else
++	tmp = ashiftrt64 (cpu->regs[rs1], cpu->regs[rs2] & 0x3f);
++      store_rd (cpu, rd, tmp);
++      break;
++    case MATCH_SRAW:
++      TRACE_INSN (cpu, "sraw %s, %s, %s;  // %s = %s >>> %s",
++		  rd_name, rs1_name, rs2_name, rd_name, rs1_name, rs2_name);
++      RISCV_ASSERT_RV64 (cpu, "insn: %s", op->name);
++      store_rd (cpu, rd, EXTEND32 (ashiftrt ((signed32)cpu->regs[rs1], cpu->regs[rs2] & 0x1f)));
++      break;
++    case MATCH_SRAI:
++      TRACE_INSN (cpu, "srai %s, %s, %" PRIiTW ";  // %s = %s >>> %#" PRIxTW,
++		  rd_name, rs1_name, shamt_imm, rd_name, rs1_name, shamt_imm);
++      if (RISCV_XLEN (cpu) == 32)
++	{
++	  if (shamt_imm > 0x1f)
++	    sim_engine_halt (sd, cpu, NULL, cpu->pc, sim_signalled, SIM_SIGILL);
++	  tmp = ashiftrt (cpu->regs[rs1], shamt_imm);
++	}
++      else
++	tmp = ashiftrt64 (cpu->regs[rs1], shamt_imm);
++      store_rd (cpu, rd, tmp);
++      break;
++    case MATCH_SRAIW:
++      TRACE_INSN (cpu, "sraiw %s, %s, %" PRIiTW ";  // %s = %s >>> %#" PRIxTW,
++		  rd_name, rs1_name, shamt_imm, rd_name, rs1_name, shamt_imm);
++      RISCV_ASSERT_RV64 (cpu, "insn: %s", op->name);
++      store_rd (cpu, rd,
++		EXTEND32 (ashiftrt ((signed32)cpu->regs[rs1], shamt_imm)));
++      break;
++    case MATCH_SLT:
++      TRACE_INSN (cpu, "slt %s, %s, %s", rd_name, rs1_name, rs2_name);
++      store_rd (cpu, rd,
++		!!((signed_word)cpu->regs[rs1] < (signed_word)cpu->regs[rs2]));
++      break;
++    case MATCH_SLTU:
++      TRACE_INSN (cpu, "sltu %s, %s, %s", rd_name, rs1_name, rs2_name);
++      store_rd (cpu, rd,
++		!!((unsigned_word)cpu->regs[rs1]
++		   < (unsigned_word)cpu->regs[rs2]));
++      break;
++    case MATCH_SLTI:
++      TRACE_INSN (cpu, "slti %s, %s, %" PRIiTW,
++		  rd_name, rs1_name, i_imm);
++      store_rd (cpu, rd, !!((signed_word)cpu->regs[rs1] < (signed_word)i_imm));
++      break;
++    case MATCH_SLTIU:
++      TRACE_INSN (cpu, "sltiu %s, %s, %" PRIiTW,
++		  rd_name, rs1_name, i_imm);
++      store_rd (cpu, rd,
++		!!((unsigned_word)cpu->regs[rs1] < (unsigned_word)i_imm));
++      break;
++    case MATCH_AUIPC:
++      TRACE_INSN (cpu, "auipc %s, %" PRIiTW ";  // %s = pc + %" PRIiTW,
++		  rd_name, u_imm, rd_name, u_imm);
++      store_rd (cpu, rd, cpu->pc + u_imm);
++      break;
++    case MATCH_BEQ:
++      TRACE_INSN (cpu, "beq %s, %s, %#" PRIxTW ";  // if (%s == %s) goto %#" PRIxTW,
++		  rs1_name, rs2_name, sb_imm, rs1_name, rs2_name, cpu->pc + sb_imm);
++      if (cpu->regs[rs1] == cpu->regs[rs2])
++	{
++	  pc = cpu->pc + sb_imm;
++	  TRACE_BRANCH (cpu, "to %#" PRIxTW, pc);
++	}
++      break;
++    case MATCH_BLT:
++      TRACE_INSN (cpu, "blt %s, %s, %#" PRIxTW ";  // if (%s < %s) goto %#" PRIxTW,
++		  rs1_name, rs2_name, sb_imm, rs1_name, rs2_name, cpu->pc + sb_imm);
++      if ((signed_word)cpu->regs[rs1] < (signed_word)cpu->regs[rs2])
++	{
++	  pc = cpu->pc + sb_imm;
++	  TRACE_BRANCH (cpu, "to %#" PRIxTW, pc);
++	}
++      break;
++    case MATCH_BLTU:
++      TRACE_INSN (cpu, "bltu %s, %s, %#" PRIxTW ";  // if (%s < %s) goto %#" PRIxTW,
++		  rs1_name, rs2_name, sb_imm, rs1_name, rs2_name, cpu->pc + sb_imm);
++      if ((unsigned_word)cpu->regs[rs1] < (unsigned_word)cpu->regs[rs2])
++	{
++	  pc = cpu->pc + sb_imm;
++	  TRACE_BRANCH (cpu, "to %#" PRIxTW, pc);
++	}
++      break;
++    case MATCH_BGE:
++      TRACE_INSN (cpu, "bge %s, %s, %#" PRIxTW ";  // if (%s >= %s) goto %#" PRIxTW,
++		  rs1_name, rs2_name, sb_imm, rs1_name, rs2_name, cpu->pc + sb_imm);
++      if ((signed_word)cpu->regs[rs1] >= (signed_word)cpu->regs[rs2])
++	{
++	  pc = cpu->pc + sb_imm;
++	  TRACE_BRANCH (cpu, "to %#" PRIxTW, pc);
++	}
++      break;
++    case MATCH_BGEU:
++      TRACE_INSN (cpu, "bgeu %s, %s, %#" PRIxTW ";  // if (%s >= %s) goto %#" PRIxTW,
++		  rs1_name, rs2_name, sb_imm, rs1_name, rs2_name, cpu->pc + sb_imm);
++      if ((unsigned_word)cpu->regs[rs1] >= (unsigned_word)cpu->regs[rs2])
++	{
++	  pc = cpu->pc + sb_imm;
++	  TRACE_BRANCH (cpu, "to %#" PRIxTW, pc);
++	}
++      break;
++    case MATCH_BNE:
++      TRACE_INSN (cpu, "bne %s, %s, %#" PRIxTW ";  // if (%s != %s) goto %#" PRIxTW,
++		  rs1_name, rs2_name, sb_imm, rs1_name, rs2_name, cpu->pc + sb_imm);
++      if (cpu->regs[rs1] != cpu->regs[rs2])
++	{
++	  pc = cpu->pc + sb_imm;
++	  TRACE_BRANCH (cpu, "to %#" PRIxTW, pc);
++	}
++      break;
++    case MATCH_JAL:
++      TRACE_INSN (cpu, "jal %s, %" PRIiTW ";", rd_name, EXTRACT_UJTYPE_IMM (iw));
++      pc = cpu->pc + EXTRACT_UJTYPE_IMM (iw);
++      store_rd (cpu, rd, cpu->pc + 4);
++      TRACE_BRANCH (cpu, "to %#" PRIxTW, pc);
++      break;
++    case MATCH_JALR:
++      TRACE_INSN (cpu, "jalr %s, %s, %" PRIiTW ";", rd_name, rs1_name, i_imm);
++      pc = cpu->regs[rs1] + i_imm;
++      store_rd (cpu, rd, cpu->pc + 4);
++      TRACE_BRANCH (cpu, "to %#" PRIxTW, pc);
++      break;
++
++    case MATCH_LD:
++      TRACE_INSN (cpu, "ld %s, %" PRIiTW "(%s); // ",
++		  rd_name, i_imm, rs1_name);
++      RISCV_ASSERT_RV64 (cpu, "insn: %s", op->name);
++      store_rd (cpu, rd,
++	sim_core_read_unaligned_8 (cpu, cpu->pc, read_map,
++				   cpu->regs[rs1] + i_imm));
++      break;
++    case MATCH_LW:
++      TRACE_INSN (cpu, "lw %s, %" PRIiTW "(%s); // ",
++		  rd_name, i_imm, rs1_name);
++      store_rd (cpu, rd, EXTEND32 (
++	sim_core_read_unaligned_4 (cpu, cpu->pc, read_map,
++				   cpu->regs[rs1] + i_imm)));
++      break;
++    case MATCH_LWU:
++      TRACE_INSN (cpu, "lwu %s, %" PRIiTW "(%s); // ",
++		  rd_name, i_imm, rs1_name);
++      store_rd (cpu, rd,
++	sim_core_read_unaligned_4 (cpu, cpu->pc, read_map,
++				   cpu->regs[rs1] + i_imm));
++      break;
++    case MATCH_LH:
++      TRACE_INSN (cpu, "lh %s, %" PRIiTW "(%s); // ",
++		  rd_name, i_imm, rs1_name);
++      store_rd (cpu, rd, EXTEND16 (
++	sim_core_read_unaligned_2 (cpu, cpu->pc, read_map,
++				   cpu->regs[rs1] + i_imm)));
++      break;
++    case MATCH_LHU:
++      TRACE_INSN (cpu, "lhu %s, %" PRIiTW "(%s); // ",
++		  rd_name, i_imm, rs1_name);
++      store_rd (cpu, rd,
++	sim_core_read_unaligned_2 (cpu, cpu->pc, read_map,
++				   cpu->regs[rs1] + i_imm));
++      break;
++    case MATCH_LB:
++      TRACE_INSN (cpu, "lb %s, %" PRIiTW "(%s); // ",
++		  rd_name, i_imm, rs1_name);
++      store_rd (cpu, rd, EXTEND8 (
++	sim_core_read_unaligned_1 (cpu, cpu->pc, read_map,
++				   cpu->regs[rs1] + i_imm)));
++      break;
++    case MATCH_LBU:
++      TRACE_INSN (cpu, "lbu %s, %" PRIiTW "(%s); // ",
++		  rd_name, i_imm, rs1_name);
++      store_rd (cpu, rd,
++	sim_core_read_unaligned_1 (cpu, cpu->pc, read_map,
++				   cpu->regs[rs1] + i_imm));
++      break;
++    case MATCH_SD:
++      TRACE_INSN (cpu, "sd %s, %" PRIiTW "(%s); // ",
++		  rs2_name, s_imm, rs1_name);
++      RISCV_ASSERT_RV64 (cpu, "insn: %s", op->name);
++      sim_core_write_unaligned_8 (cpu, cpu->pc, write_map,
++				  cpu->regs[rs1] + s_imm, cpu->regs[rs2]);
++      break;
++    case MATCH_SW:
++      TRACE_INSN (cpu, "sw %s, %" PRIiTW "(%s); // ",
++		  rs2_name, s_imm, rs1_name);
++      sim_core_write_unaligned_4 (cpu, cpu->pc, write_map,
++				  cpu->regs[rs1] + s_imm, cpu->regs[rs2]);
++      break;
++    case MATCH_SH:
++      TRACE_INSN (cpu, "sh %s, %" PRIiTW "(%s); // ",
++		  rs2_name, s_imm, rs1_name);
++      sim_core_write_unaligned_2 (cpu, cpu->pc, write_map,
++				  cpu->regs[rs1] + s_imm, cpu->regs[rs2]);
++      break;
++    case MATCH_SB:
++      TRACE_INSN (cpu, "sb %s, %" PRIiTW "(%s); // ",
++		  rs2_name, s_imm, rs1_name);
++      sim_core_write_unaligned_1 (cpu, cpu->pc, write_map,
++				  cpu->regs[rs1] + s_imm, cpu->regs[rs2]);
++      break;
++
++    case MATCH_CSRRC:
++      TRACE_INSN (cpu, "csrrc");
++      switch (csr)
++	{
++#define DECLARE_CSR(name, num, class, def_ver, abort_ver)	\
++	case num: \
++	  store_rd (cpu, rd, fetch_csr (cpu, #name, num, &cpu->csr.name)); \
++	  store_csr (cpu, #name, num, &cpu->csr.name, \
++		     cpu->csr.name & !cpu->regs[rs1]); \
++	  break;
++#include "opcode/riscv-opc.h"
++#undef DECLARE_CSR
++	}
++      break;
++    case MATCH_CSRRCI:
++      TRACE_INSN (cpu, "csrrci");
++      switch (csr)
++	{
++#define DECLARE_CSR(name, num, class, def_ver, abort_ver)	\
++	case num: \
++	  store_rd (cpu, rd, fetch_csr (cpu, #name, num, &cpu->csr.name)); \
++	  store_csr (cpu, #name, num, &cpu->csr.name, \
++		     cpu->csr.name & !rs1); \
++	  break;
++#include "opcode/riscv-opc.h"
++#undef DECLARE_CSR
++	}
++      break;
++    case MATCH_CSRRS:
++      TRACE_INSN (cpu, "csrrs");
++      switch (csr)
++	{
++#define DECLARE_CSR(name, num, class, def_ver, abort_ver)	\
++	case num: \
++	  store_rd (cpu, rd, fetch_csr (cpu, #name, num, &cpu->csr.name)); \
++	  store_csr (cpu, #name, num, &cpu->csr.name, \
++		     cpu->csr.name | cpu->regs[rs1]); \
++	  break;
++#include "opcode/riscv-opc.h"
++#undef DECLARE_CSR
++	}
++      break;
++    case MATCH_CSRRSI:
++      TRACE_INSN (cpu, "csrrsi");
++      switch (csr)
++	{
++#define DECLARE_CSR(name, num, class, def_ver, abort_ver)	\
++	case num: \
++	  store_rd (cpu, rd, fetch_csr (cpu, #name, num, &cpu->csr.name)); \
++	  store_csr (cpu, #name, num, &cpu->csr.name, \
++		     cpu->csr.name | rs1); \
++	  break;
++#include "opcode/riscv-opc.h"
++#undef DECLARE_CSR
++	}
++      break;
++    case MATCH_CSRRW:
++      TRACE_INSN (cpu, "csrrw");
++      switch (csr)
++	{
++#define DECLARE_CSR(name, num, class, def_ver, abort_ver)	\
++	case num: \
++	  store_rd (cpu, rd, fetch_csr (cpu, #name, num, &cpu->csr.name)); \
++	  store_csr (cpu, #name, num, &cpu->csr.name, cpu->regs[rs1]); \
++	  break;
++#include "opcode/riscv-opc.h"
++#undef DECLARE_CSR
++	}
++      break;
++    case MATCH_CSRRWI:
++      TRACE_INSN (cpu, "csrrwi");
++      switch (csr)
++	{
++#define DECLARE_CSR(name, num, class, def_ver, abort_ver)	\
++	case num: \
++	  store_rd (cpu, rd, fetch_csr (cpu, #name, num, &cpu->csr.name)); \
++	  store_csr (cpu, #name, num, &cpu->csr.name, rs1); \
++	  break;
++#include "opcode/riscv-opc.h"
++#undef DECLARE_CSR
++	}
++      break;
++
++    case MATCH_RDCYCLE:
++      TRACE_INSN (cpu, "rdcycle %s;", rd_name);
++      store_rd (cpu, rd, fetch_csr (cpu, "cycle", CSR_CYCLE, &cpu->csr.cycle));
++      break;
++    case MATCH_RDCYCLEH:
++      TRACE_INSN (cpu, "rdcycleh %s;", rd_name);
++      RISCV_ASSERT_RV32 (cpu, "insn: %s", op->name);
++      store_rd (cpu, rd, fetch_csr (cpu, "cycleh", CSR_CYCLEH, &cpu->csr.cycleh));
++      break;
++    case MATCH_RDINSTRET:
++      TRACE_INSN (cpu, "rdinstret %s;", rd_name);
++      store_rd (cpu, rd, fetch_csr (cpu, "instret", CSR_INSTRET, &cpu->csr.instret));
++      break;
++    case MATCH_RDINSTRETH:
++      TRACE_INSN (cpu, "rdinstreth %s;", rd_name);
++      RISCV_ASSERT_RV32 (cpu, "insn: %s", op->name);
++      store_rd (cpu, rd, fetch_csr (cpu, "instreth", CSR_INSTRETH, &cpu->csr.instreth));
++      break;
++    case MATCH_RDTIME:
++      TRACE_INSN (cpu, "rdtime %s;", rd_name);
++      store_rd (cpu, rd, fetch_csr (cpu, "time", CSR_TIME, &cpu->csr.cycle));
++      break;
++    case MATCH_RDTIMEH:
++      TRACE_INSN (cpu, "rdtimeh %s;", rd_name);
++      RISCV_ASSERT_RV32 (cpu, "insn: %s", op->name);
++      store_rd (cpu, rd, fetch_csr (cpu, "timeh", CSR_TIMEH, &cpu->csr.cycleh));
++      break;
++
++    case MATCH_FENCE:
++      TRACE_INSN (cpu, "fence;");
++      break;
++    case MATCH_FENCE_I:
++      TRACE_INSN (cpu, "fence.i;");
++      break;
++    case MATCH_SBREAK:
++      TRACE_INSN (cpu, "sbreak;");
++      /* GDB expects us to step over SBREAK.  */
++      sim_engine_halt (sd, cpu, NULL, cpu->pc, sim_stopped, SIM_SIGTRAP);
++      break;
++    case MATCH_ECALL:
++      TRACE_INSN (cpu, "ecall;");
++      if (cb_target_to_host_syscall (STATE_CALLBACK (sd), cpu->a7) == -1)
++	{
++	  host_callback *cb = STATE_CALLBACK (sd);
++	  CB_SYSCALL sc;
++
++	  CB_SYSCALL_INIT (&sc);
++
++	  sc.arg1 = cpu->a0;
++	  sc.arg2 = cpu->a1;
++	  sc.arg3 = cpu->a2;
++	  sc.arg4 = cpu->a3;
++	  sc.func = cpu->a7;
++
++	  sc.p1 = (PTR) sd;
++	  sc.p2 = (PTR) cpu;
++	  sc.read_mem = sim_syscall_read_mem;
++	  sc.write_mem = sim_syscall_write_mem;
++
++	  switch (cpu->a7)
++	    {
++#ifndef __MINGW32__
++	    case TARGET_SYS_link:
++	      {
++		char oldpath[1024], newpath[1024];
++		cb_get_string (cb, &sc, oldpath, sizeof (oldpath), sc.arg1);
++		cb_get_string (cb, &sc, newpath, sizeof (newpath), sc.arg2);
++		cpu->a0 = link (oldpath, newpath);
++		break;
++	      }
++#endif
++	    case TARGET_SYS_brk:
++	      {
++		/* FIXME: Check the invalid access.  */
++		if (cpu->a0 == 0)
++		  cpu->a0 = cpu->endbrk;
++		else
++		  {
++		    if (cpu->a0 >= DEFAULT_MEM_SIZE)
++		      cpu->a0 = -1;
++		    else
++		      cpu->endbrk = cpu->a0;
++		  }
++		break;
++	      }
++	    case TARGET_SYS_gettimeofday:
++	      {
++		int rv;
++		struct timeval tv;
++
++		rv = gettimeofday (&tv, 0);
++		if (RISCV_XLEN (cpu) == 32)
++		  {
++		    sim_core_write_unaligned_4 (cpu, cpu->pc, write_map,
++						cpu->a0, tv.tv_sec);
++		    sim_core_write_unaligned_4 (cpu, cpu->pc, write_map,
++						cpu->a0 + 4,
++						tv.tv_usec);
++		  }
++		else
++		  {
++		    sim_core_write_unaligned_8 (cpu, cpu->pc, write_map,
++						cpu->a0, tv.tv_sec);
++		    sim_core_write_unaligned_8 (cpu, cpu->pc, write_map,
++						cpu->a0 + 8,
++						tv.tv_usec);
++		  }
++
++		cpu->a0 = rv;
++		break;
++	      }
++	    default:
++	      cpu->a0 = sim_syscall (cpu, cpu->a7, cpu->a0,
++				     cpu->a1, cpu->a2, cpu->a3);
++	      break;
++	    }
++	}
++      else
++	cpu->a0 = sim_syscall (cpu, cpu->a7, cpu->a0, cpu->a1, cpu->a2, cpu->a3);
++      break;
++    default:
++      TRACE_INSN (cpu, "UNHANDLED INSN: %s", op->name);
++      sim_engine_halt (sd, cpu, NULL, cpu->pc, sim_signalled, SIM_SIGILL);
++    }
++
++  return pc;
++}
++
++static unsigned64
++mulhu (unsigned64 a, unsigned64 b)
++{
++  uint64_t t;
++  uint32_t y1, y2, y3;
++  uint64_t a0 = (uint32_t)a, a1 = a >> 32;
++  uint64_t b0 = (uint32_t)b, b1 = b >> 32;
++
++  t = a1*b0 + ((a0*b0) >> 32);
++  y1 = t;
++  y2 = t >> 32;
++
++  t = a0*b1 + y1;
++  y1 = t;
++
++  t = a1*b1 + y2 + (t >> 32);
++  y2 = t;
++  y3 = t >> 32;
++
++  return ((uint64_t)y3 << 32) | y2;
++}
++
++static unsigned64
++mulh (signed64 a, signed64 b)
++{
++  int negate = (a < 0) != (b < 0);
++  uint64_t res = mulhu (a < 0 ? -a : a, b < 0 ? -b : b);
++  return negate ? ~res + (a * b == 0) : res;
++}
++
++static unsigned64
++mulhsu (signed64 a, unsigned64 b)
++{
++  int negate = a < 0;
++  uint64_t res = mulhu (a < 0 ? -a : a, b);
++  return negate ? ~res + (a * b == 0) : res;
++}
++
++static sim_cia
++execute_m (SIM_CPU *cpu, unsigned_word iw, const struct riscv_opcode *op)
++{
++  SIM_DESC sd = CPU_STATE (cpu);
++  int rd = (iw >> OP_SH_RD) & OP_MASK_RD;
++  int rs1 = (iw >> OP_SH_RS1) & OP_MASK_RS1;
++  int rs2 = (iw >> OP_SH_RS2) & OP_MASK_RS2;
++  const char *rd_name = riscv_gpr_names_abi[rd];
++  const char *rs1_name = riscv_gpr_names_abi[rs1];
++  const char *rs2_name = riscv_gpr_names_abi[rs2];
++  unsigned_word tmp, dividend_max;
++  signed_word dividend32_max;
++  sim_cia pc = cpu->pc + 4;
++
++  dividend_max = -((unsigned_word)1 << (WITH_TARGET_WORD_BITSIZE - 1));
++  dividend32_max = INT32_MIN;
++
++  switch (op->match)
++    {
++    case MATCH_DIV:
++      TRACE_INSN (cpu, "div %s, %s, %s;  // %s = %s / %s",
++		  rd_name, rs1_name, rs2_name, rd_name, rs1_name, rs2_name);
++      if (cpu->regs[rs1] == dividend_max && cpu->regs[rs2] == -1)
++	tmp = dividend_max;
++      else if (cpu->regs[rs2])
++	tmp = (signed_word)cpu->regs[rs1] / (signed_word)cpu->regs[rs2];
++      else
++	tmp = -1;
++      store_rd (cpu, rd, tmp);
++      break;
++    case MATCH_DIVW:
++      TRACE_INSN (cpu, "divw %s, %s, %s;  // %s = %s / %s",
++		  rd_name, rs1_name, rs2_name, rd_name, rs1_name, rs2_name);
++      RISCV_ASSERT_RV64 (cpu, "insn: %s", op->name);
++      if (EXTEND32 (cpu->regs[rs1]) == dividend32_max
++	  && EXTEND32 (cpu->regs[rs2]) == -1)
++	tmp = 1 << 31;
++      else if (EXTEND32 (cpu->regs[rs2]))
++	tmp = EXTEND32 (cpu->regs[rs1]) / EXTEND32 (cpu->regs[rs2]);
++      else
++	tmp = -1;
++      store_rd (cpu, rd, EXTEND32 (tmp));
++      break;
++    case MATCH_DIVU:
++      TRACE_INSN (cpu, "divu %s, %s, %s;  // %s = %s / %s",
++		  rd_name, rs1_name, rs2_name, rd_name, rs1_name, rs2_name);
++      if (cpu->regs[rs2])
++	store_rd (cpu, rd, (unsigned_word)cpu->regs[rs1]
++			   / (unsigned_word)cpu->regs[rs2]);
++      else
++	store_rd (cpu, rd, -1);
++      break;
++    case MATCH_DIVUW:
++      TRACE_INSN (cpu, "divuw %s, %s, %s;  // %s = %s / %s",
++		  rd_name, rs1_name, rs2_name, rd_name, rs1_name, rs2_name);
++      RISCV_ASSERT_RV64 (cpu, "insn: %s", op->name);
++      if ((unsigned32)cpu->regs[rs2])
++	tmp = (unsigned32)cpu->regs[rs1] / (unsigned32)cpu->regs[rs2];
++      else
++	tmp = -1;
++      store_rd (cpu, rd, EXTEND32 (tmp));
++      break;
++    case MATCH_MUL:
++      TRACE_INSN (cpu, "mul %s, %s, %s;  // %s = %s * %s",
++		  rd_name, rs1_name, rs2_name, rd_name, rs1_name, rs2_name);
++      store_rd (cpu, rd, cpu->regs[rs1] * cpu->regs[rs2]);
++      break;
++    case MATCH_MULW:
++      TRACE_INSN (cpu, "mulw %s, %s, %s;  // %s = %s * %s",
++		  rd_name, rs1_name, rs2_name, rd_name, rs1_name, rs2_name);
++      RISCV_ASSERT_RV64 (cpu, "insn: %s", op->name);
++      store_rd (cpu, rd, EXTEND32 ((signed32)cpu->regs[rs1]
++				   * (signed32)cpu->regs[rs2]));
++      break;
++    case MATCH_MULH:
++      TRACE_INSN (cpu, "mulh %s, %s, %s;  // %s = %s * %s",
++		  rd_name, rs1_name, rs2_name, rd_name, rs1_name, rs2_name);
++      if (RISCV_XLEN (cpu) == 32)
++	store_rd (cpu, rd, ((signed64)(signed_word)cpu->regs[rs1]
++			    * (signed64)(signed_word)cpu->regs[rs2]) >> 32);
++      else
++	store_rd (cpu, rd, mulh (cpu->regs[rs1], cpu->regs[rs2]));
++      break;
++    case MATCH_MULHU:
++      TRACE_INSN (cpu, "mulhu %s, %s, %s;  // %s = %s * %s",
++		  rd_name, rs1_name, rs2_name, rd_name, rs1_name, rs2_name);
++      if (RISCV_XLEN (cpu) == 32)
++	store_rd (cpu, rd, ((unsigned64)cpu->regs[rs1]
++			    * (unsigned64)cpu->regs[rs2]) >> 32);
++      else
++	store_rd (cpu, rd, mulhu (cpu->regs[rs1], cpu->regs[rs2]));
++      break;
++    case MATCH_MULHSU:
++      TRACE_INSN (cpu, "mulhsu %s, %s, %s;  // %s = %s * %s",
++		  rd_name, rs1_name, rs2_name, rd_name, rs1_name, rs2_name);
++      if (RISCV_XLEN (cpu) == 32)
++	store_rd (cpu, rd, ((signed64)(signed_word)cpu->regs[rs1]
++			    * (unsigned64)cpu->regs[rs2]) >> 32);
++      else
++	store_rd (cpu, rd, mulhsu (cpu->regs[rs1], cpu->regs[rs2]));
++      break;
++    case MATCH_REM:
++      TRACE_INSN (cpu, "rem %s, %s, %s;  // %s = %s %% %s",
++		  rd_name, rs1_name, rs2_name, rd_name, rs1_name, rs2_name);
++      if (cpu->regs[rs1] == dividend_max && cpu->regs[rs2] == -1)
++	tmp = 0;
++      else if (cpu->regs[rs2])
++	tmp = (signed_word)cpu->regs[rs1] % (signed_word)cpu->regs[rs2];
++      else
++	tmp = cpu->regs[rs1];
++      store_rd (cpu, rd, tmp);
++      break;
++    case MATCH_REMW:
++      TRACE_INSN (cpu, "remw %s, %s, %s;  // %s = %s %% %s",
++		  rd_name, rs1_name, rs2_name, rd_name, rs1_name, rs2_name);
++      RISCV_ASSERT_RV64 (cpu, "insn: %s", op->name);
++      if (EXTEND32 (cpu->regs[rs1]) == dividend32_max
++	  && EXTEND32 (cpu->regs[rs2]) == -1)
++	tmp = 0;
++      else if (EXTEND32 (cpu->regs[rs2]))
++	tmp = EXTEND32 (cpu->regs[rs1]) % EXTEND32 (cpu->regs[rs2]);
++      else
++	tmp = cpu->regs[rs1];
++      store_rd (cpu, rd, EXTEND32 (tmp));
++      break;
++    case MATCH_REMU:
++      TRACE_INSN (cpu, "remu %s, %s, %s;  // %s = %s %% %s",
++		  rd_name, rs1_name, rs2_name, rd_name, rs1_name, rs2_name);
++      if (cpu->regs[rs2])
++	store_rd (cpu, rd, cpu->regs[rs1] % cpu->regs[rs2]);
++      else
++	store_rd (cpu, rd, cpu->regs[rs1]);
++      break;
++    case MATCH_REMUW:
++      TRACE_INSN (cpu, "remuw %s, %s, %s;  // %s = %s %% %s",
++		  rd_name, rs1_name, rs2_name, rd_name, rs1_name, rs2_name);
++      RISCV_ASSERT_RV64 (cpu, "insn: %s", op->name);
++      if ((unsigned32)cpu->regs[rs2])
++	tmp = (unsigned32)cpu->regs[rs1] % (unsigned32)cpu->regs[rs2];
++      else
++	tmp = cpu->regs[rs1];
++      store_rd (cpu, rd, EXTEND32 (tmp));
++      break;
++    default:
++      TRACE_INSN (cpu, "UNHANDLED INSN: %s", op->name);
++      sim_engine_halt (sd, cpu, NULL, cpu->pc, sim_signalled, SIM_SIGILL);
++    }
++
++  return pc;
++}
++
++#define MAX(a, b) ((a) > (b) ? (a) : (b))
++#define MIN(a, b) ((a) < (b) ? (a) : (b))
++
++static sim_cia
++execute_a (SIM_CPU *cpu, unsigned_word iw, const struct riscv_opcode *op)
++{
++  SIM_DESC sd = CPU_STATE (cpu);
++  int rd = (iw >> OP_SH_RD) & OP_MASK_RD;
++  int rs1 = (iw >> OP_SH_RS1) & OP_MASK_RS1;
++  int rs2 = (iw >> OP_SH_RS2) & OP_MASK_RS2;
++  const char *rd_name = riscv_gpr_names_abi[rd];
++  const char *rs1_name = riscv_gpr_names_abi[rs1];
++  const char *rs2_name = riscv_gpr_names_abi[rs2];
++  struct atomic_mem_reserved_list *amo_prev, *amo_curr;
++  insn_t aqrl_mask = (OP_MASK_AQ << OP_SH_AQ) | (OP_MASK_RL << OP_SH_RL);
++  unsigned_word tmp;
++  unsigned_word rs2_val = cpu->regs[rs2];
++  sim_cia pc = cpu->pc + 4;
++
++  /* Handle these two load/store operations specifically.  */
++  switch (op->match & ~aqrl_mask)
++    {
++    case MATCH_LR_W:
++      TRACE_INSN (cpu, "%s %s, (%s);", op->name, rd_name, rs1_name);
++      store_rd (cpu, rd,
++	sim_core_read_unaligned_4 (cpu, cpu->pc, read_map, cpu->regs[rs1]));
++
++      /* Walk the reservation list to find an existing match.  */
++      amo_curr = sd->amo_reserved_list;
++      while (amo_curr)
++	{
++	  if (amo_curr->addr == cpu->regs[rs1])
++	    goto done;
++	  amo_curr = amo_curr->next;
++	}
++
++      /* No reservation exists, so add one.  */
++      amo_curr = xmalloc (sizeof (*amo_curr));
++      amo_curr->addr = cpu->regs[rs1];
++      amo_curr->next = sd->amo_reserved_list;
++      sd->amo_reserved_list = amo_curr;
++      goto done;
++    case MATCH_SC_W:
++      TRACE_INSN (cpu, "%s %s, %s, (%s);", op->name, rd_name, rs2_name, rs1_name);
++
++      /* Walk the reservation list to find a match.  */
++      amo_curr = amo_prev = sd->amo_reserved_list;
++      while (amo_curr)
++	{
++	  if (amo_curr->addr == cpu->regs[rs1])
++	    {
++	      /* We found a reservation, so operate it.  */
++	      sim_core_write_unaligned_4 (cpu, cpu->pc, write_map,
++					  cpu->regs[rs1], cpu->regs[rs2]);
++	      store_rd (cpu, rd, 0);
++	      if (amo_curr == sd->amo_reserved_list)
++		sd->amo_reserved_list = amo_curr->next;
++	      else
++		amo_prev->next = amo_curr->next;
++	      free (amo_curr);
++	      goto done;
++	    }
++	  amo_prev = amo_curr;
++	  amo_curr = amo_curr->next;
++	}
++
++      /* If we're still here, then no reservation exists, so mark as failed.  */
++      store_rd (cpu, rd, 1);
++      goto done;
++    }
++
++  /* Handle the rest of the atomic insns with common code paths.  */
++  TRACE_INSN (cpu, "%s %s, %s, (%s);",
++	      op->name, rd_name, rs2_name, rs1_name);
++  if (op->xlen_requirement == 64)
++    tmp = sim_core_read_unaligned_8 (cpu, cpu->pc, read_map, cpu->regs[rs1]);
++  else
++    tmp = EXTEND32 (sim_core_read_unaligned_4 (cpu, cpu->pc,
++					       read_map, cpu->regs[rs1]));
++
++  store_rd (cpu, rd, tmp);
++
++  switch (op->match & ~aqrl_mask)
++    {
++    case MATCH_AMOADD_D:
++    case MATCH_AMOADD_W:
++      tmp = tmp + cpu->regs[rs2];
++      break;
++    case MATCH_AMOAND_D:
++    case MATCH_AMOAND_W:
++      tmp = tmp & cpu->regs[rs2];
++      break;
++    case MATCH_AMOMAX_D:
++    case MATCH_AMOMAX_W:
++      tmp = MAX ((signed_word)tmp, (signed_word)cpu->regs[rs2]);
++      break;
++    case MATCH_AMOMAXU_D:
++    case MATCH_AMOMAXU_W:
++      tmp = MAX ((unsigned_word)tmp, (unsigned_word)cpu->regs[rs2]);
++      break;
++    case MATCH_AMOMIN_D:
++    case MATCH_AMOMIN_W:
++      tmp = MIN ((signed_word)tmp, (signed_word)cpu->regs[rs2]);
++      break;
++    case MATCH_AMOMINU_D:
++    case MATCH_AMOMINU_W:
++      tmp = MIN ((unsigned_word)tmp, (unsigned_word)cpu->regs[rs2]);
++      break;
++    case MATCH_AMOOR_D:
++    case MATCH_AMOOR_W:
++      tmp = tmp | cpu->regs[rs2];
++      break;
++    case MATCH_AMOSWAP_D:
++    case MATCH_AMOSWAP_W:
++      tmp = rs2_val;
++      break;
++    case MATCH_AMOXOR_D:
++    case MATCH_AMOXOR_W:
++      tmp = tmp ^ cpu->regs[rs2];
++      break;
++    default:
++      TRACE_INSN (cpu, "UNHANDLED INSN: %s", op->name);
++      sim_engine_halt (sd, cpu, NULL, cpu->pc, sim_signalled, SIM_SIGILL);
++    }
++
++  if (op->xlen_requirement == 64)
++    sim_core_write_unaligned_8 (cpu, cpu->pc, write_map, cpu->regs[rs1], tmp);
++  else
++    sim_core_write_unaligned_4 (cpu, cpu->pc, write_map, cpu->regs[rs1], tmp);
++
++ done:
++  return pc;
++}
++
++static sim_cia
++execute_one (SIM_CPU *cpu, unsigned_word iw, const struct riscv_opcode *op)
++{
++  SIM_DESC sd = CPU_STATE (cpu);
++  int index;
++
++  if (op->xlen_requirement == 32)
++    RISCV_ASSERT_RV32 (cpu, "insn: %s", op->name);
++  else if (op->xlen_requirement == 64)
++    RISCV_ASSERT_RV64 (cpu, "insn: %s", op->name);
++
++  switch (op->insn_class)
++    {
++    case INSN_CLASS_A:
++      return execute_a (cpu, iw, op);
++    case INSN_CLASS_C:
++    case INSN_CLASS_F_AND_C:
++    case INSN_CLASS_D_AND_C:
++      return execute_c (cpu, iw, op);
++    case INSN_CLASS_D:
++      return execute_d (cpu, iw, op);
++    case INSN_CLASS_F:
++      return execute_f (cpu, iw, op);
++    case INSN_CLASS_I:
++      return execute_i (cpu, iw, op);
++    case INSN_CLASS_M:
++      return execute_m (cpu, iw, op);
++    case_default:
++    default:
++      TRACE_INSN (cpu, "UNHANDLED EXTENSION: %d", op->insn_class);
++      sim_engine_halt (sd, cpu, NULL, cpu->pc, sim_signalled, SIM_SIGILL);
++    }
++
++  return cpu->pc + riscv_insn_length (iw);
++}
++
++/* Decode & execute a single instruction.  */
++void step_once (SIM_CPU *cpu)
++{
++  SIM_DESC sd = CPU_STATE (cpu);
++  unsigned_word iw;
++  unsigned int len;
++  sim_cia pc = cpu->pc;
++  const struct riscv_opcode *op;
++  int xlen = RISCV_XLEN (cpu);
++
++  if (TRACE_ANY_P (cpu))
++    trace_prefix (sd, cpu, NULL_CIA, pc, TRACE_LINENUM_P (cpu),
++		  NULL, 0, " "); /* Use a space for gcc warnings.  */
++
++  iw = sim_core_read_aligned_2 (cpu, pc, exec_map, pc);
++
++  len = riscv_insn_length (iw);
++
++  if (len == 4)
++    iw |= ((unsigned_word)sim_core_read_aligned_2 (cpu, pc, exec_map, pc + 2) << 16);
++
++  TRACE_CORE (cpu, "0x%08" PRIxTW, iw);
++
++  op = riscv_hash[OP_HASH_IDX (iw)];
++  if (!op)
++    sim_engine_halt (sd, cpu, NULL, pc, sim_signalled, SIM_SIGILL);
++
++  for (; op->name; op++)
++    {
++      /* Does the opcode match?  */
++      if (!(op->match_func) (op, iw))
++	continue;
++      /* Is this a pseudo-instruction?  */
++      if ((op->pinfo & INSN_ALIAS))
++	continue;
++      /* Is this instruction restricted to a certain value of XLEN?  */
++      if (op->xlen_requirement != 0 && op->xlen_requirement != xlen)
++	continue;
++      /* It's a match.  */
++      pc = execute_one (cpu, iw, op);
++      break;
++    }
++
++  /* TODO: Try to use a common counter and only update on demand (reads).  */
++  if (RISCV_XLEN (cpu) == 32)
++    {
++      unsigned_word old_cycle = cpu->csr.cycle++;
++
++      /* Increase cycleh if cycle is overflowed.  */
++      if (old_cycle > cpu->csr.cycle)
++	cpu->csr.cycleh++;
++    }
++  else
++    ++cpu->csr.cycle;
++
++  cpu->csr.instret = cpu->csr.cycle;
++  cpu->csr.instreth = cpu->csr.cycleh;
++
++  cpu->pc = pc;
++}
++
++/* Return the program counter for this cpu. */
++static sim_cia
++pc_get (sim_cpu *cpu)
++{
++  return cpu->pc;
++}
++
++/* Set the program counter for this cpu to the new pc value. */
++static void
++pc_set (sim_cpu *cpu, sim_cia pc)
++{
++  cpu->pc = pc;
++}
++
++static int
++reg_fetch (sim_cpu *cpu, int rn, unsigned char *buf, int len)
++{
++  if (len <= 0 || len > sizeof (unsigned_word))
++    return -1;
++
++  switch (rn)
++    {
++    case SIM_RISCV_RA_REGNUM ... SIM_RISCV_T6_REGNUM:
++      memcpy (buf, &cpu->regs[rn], len);
++      return len;
++    case SIM_RISCV_FIRST_FP_REGNUM ... SIM_RISCV_LAST_FP_REGNUM:
++      rn -= SIM_RISCV_FIRST_FP_REGNUM;
++      memcpy (buf, &cpu->fpregs[rn], len);
++      return len;
++    case SIM_RISCV_PC_REGNUM:
++      memcpy (buf, &cpu->pc, len);
++      return len;
++
++#define DECLARE_CSR(name, num, class, def_ver, abort_ver) \
++    case SIM_RISCV_ ## num ## _REGNUM: \
++      memcpy (buf, &cpu->csr.name, len); \
++      return len;
++#include "opcode/riscv-opc.h"
++#undef DECLARE_CSR
++
++    default:
++      return -1;
++    }
++}
++
++static int
++reg_store (sim_cpu *cpu, int rn, unsigned char *buf, int len)
++{
++  if (len <= 0 || len > sizeof (unsigned_word))
++    return -1;
++
++  switch (rn)
++    {
++    case SIM_RISCV_ZERO_REGNUM:
++      /* Always return len to avoid warning/error in gdbsim_store_register.  */
++      return len;
++    case SIM_RISCV_RA_REGNUM ... SIM_RISCV_T6_REGNUM:
++      memcpy (&cpu->regs[rn], buf, len);
++      return len;
++    case SIM_RISCV_FIRST_FP_REGNUM ... SIM_RISCV_LAST_FP_REGNUM:
++      rn -= SIM_RISCV_FIRST_FP_REGNUM;
++      memcpy (&cpu->fpregs[rn], buf, len);
++      return len;
++    case SIM_RISCV_PC_REGNUM:
++      memcpy (&cpu->pc, buf, len);
++      return len;
++
++#define DECLARE_CSR(name, num, class, def_ver, abort_ver) \
++    case SIM_RISCV_ ## num ## _REGNUM: \
++      memcpy (&cpu->csr.name, buf, len); \
++      return len;
++#include "opcode/riscv-opc.h"
++#undef DECLARE_CSR
++
++    default:
++      return -1;
++    }
++}
++
++/* Initialize the state for a single cpu.  Usuaully this involves clearing all
++   registers back to their reset state.  Should also hook up the fetch/store
++   helper functions too.  */
++void initialize_cpu (SIM_DESC sd, SIM_CPU *cpu, int mhartid)
++{
++  const char *extensions;
++  int i;
++
++  memset (cpu->regs, 0, sizeof (cpu->regs));
++
++  CPU_PC_FETCH (cpu) = pc_get;
++  CPU_PC_STORE (cpu) = pc_set;
++  CPU_REG_FETCH (cpu) = reg_fetch;
++  CPU_REG_STORE (cpu) = reg_store;
++
++  if (!riscv_hash[0])
++    {
++      const struct riscv_opcode *op;
++
++      for (op = riscv_opcodes; op->name; op++)
++	if (!riscv_hash[OP_HASH_IDX (op->match)])
++	  riscv_hash[OP_HASH_IDX (op->match)] = op;
++    }
++
++  cpu->csr.misa = 0;
++  /* RV32 sets this field to 0, and we don't really support RV128 yet.  */
++  if (RISCV_XLEN (cpu) == 64)
++    cpu->csr.misa |= (unsigned64)2 << 62;
++
++  /* Skip the leading "rv" prefix and the two numbers.  */
++  extensions = MODEL_NAME (CPU_MODEL (cpu)) + 4;
++  for (i = 0; i < 26; ++i)
++    {
++      char ext = 'A' + i;
++
++      if (ext == 'X')
++	continue;
++      else if (strchr (extensions, ext) != NULL)
++	{
++	  if (ext == 'G')
++	    cpu->csr.misa |= 0x1129;  /* G = IMAFD.  */
++	  else
++	    cpu->csr.misa |= (1 << i);
++	}
++    }
++
++  cpu->csr.mimpid = 0x8000;
++  cpu->csr.mhartid = mhartid;
++  cpu->csr.cycle = 0;
++  cpu->csr.cycleh = 0;
++  cpu->csr.instret = 0;
++  cpu->csr.instreth = 0;
++}
++
++/* Some utils don't like having a NULL environ.  */
++static const char * const simple_env[] = { "HOME=/", "PATH=/bin", NULL };
++
++/* Count the number of arguments in an argv.  */
++static int
++count_argv (const char * const *argv)
++{
++  int i;
++
++  if (!argv)
++    return -1;
++
++  for (i = 0; argv[i] != NULL; ++i)
++    continue;
++  return i;
++}
++
++void initialize_env (SIM_DESC sd, const char * const *argv,
++		     const char * const *env)
++{
++  SIM_CPU *cpu = STATE_CPU (sd, 0);
++  int i;
++  int argc, argv_flat;
++  int envc, env_flat;
++  address_word sp, sp_flat;
++  unsigned char null[8] = { 0, 0, 0, 0, 0, 0, 0, 0, };
++
++  /* Figure out how many bytes the argv strings take up.  */
++  argc = count_argv (argv);
++  if (argc == -1)
++    argc = 0;
++  argv_flat = argc; /* NUL bytes.  */
++  for (i = 0; i < argc; ++i)
++    argv_flat += strlen (argv[i]);
++
++  /* Figure out how many bytes the environ strings take up.  */
++  if (!env)
++    env = simple_env;
++  envc = count_argv (env);
++  env_flat = envc; /* NUL bytes.  */
++  for (i = 0; i < envc; ++i)
++    env_flat += strlen (env[i]);
++
++  /* Make space for the strings themselves.  */
++  sp_flat = (DEFAULT_MEM_SIZE - argv_flat - env_flat) & -sizeof (address_word);
++  /* Then the pointers to the strings.  */
++  sp = sp_flat - ((argc + 1 + envc + 1) * sizeof (address_word));
++  /* Then the argc.  */
++  sp -= sizeof (unsigned_word);
++  /* Synchronize sp alignment with GCC's STACK_BOUNDARY.  */
++  sp = ALIGN_16 (sp - 15);
++
++  /* Set up the regs the libgloss crt0 expects.  */
++  cpu->a0 = argc;
++  cpu->sp = sp;
++
++  /* First push the argc value.  */
++  sim_write (sd, sp, (void *)&argc, sizeof (unsigned_word));
++  sp += sizeof (unsigned_word);
++
++  /* Then the actual argv strings so we know where to point argv[].  */
++  for (i = 0; i < argc; ++i)
++    {
++      unsigned len = strlen (argv[i]) + 1;
++      sim_write (sd, sp_flat, (void *)argv[i], len);
++      sim_write (sd, sp, (void *)&sp_flat, sizeof (address_word));
++      sp_flat += len;
++      sp += sizeof (address_word);
++    }
++  sim_write (sd, sp, null, sizeof (address_word));
++  sp += sizeof (address_word);
++
++  /* Then the actual env strings so we know where to point env[].  */
++  for (i = 0; i < envc; ++i)
++    {
++      unsigned len = strlen (env[i]) + 1;
++      sim_write (sd, sp_flat, (void *)env[i], len);
++      sim_write (sd, sp, (void *)&sp_flat, sizeof (address_word));
++      sp_flat += len;
++      sp += sizeof (address_word);
++    }
++}
+diff --git a/sim/riscv/sim-main.h b/sim/riscv/sim-main.h
+new file mode 100644
+index 0000000000..94b3b08047
+--- /dev/null
++++ b/sim/riscv/sim-main.h
+@@ -0,0 +1,100 @@
++/* RISC-V simulator.
++
++   Copyright (C) 2005-2014 Free Software Foundation, Inc.
++   Contributed by Mike Frysinger.
++
++   This file is part of simulators.
++
++   This program is free software; you can redistribute it and/or modify
++   it under the terms of the GNU General Public License as published by
++   the Free Software Foundation; either version 3 of the License, or
++   (at your option) any later version.
++
++   This program is distributed in the hope that it will be useful,
++   but WITHOUT ANY WARRANTY; without even the implied warranty of
++   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
++   GNU General Public License for more details.
++
++   You should have received a copy of the GNU General Public License
++   along with this program.  If not, see <http://www.gnu.org/licenses/>.  */
++
++#ifndef SIM_MAIN_H
++#define SIM_MAIN_H
++
++#include "sim-basics.h"
++#include "machs.h"
++#include "sim-base.h"
++
++typedef union FRegisterValue
++{
++  uint64_t     v[2];
++  uint32_t     w[4];
++
++  int64_t      V[2];
++  int32_t      W[4];
++
++  float        S[4];
++  double       D[2];
++
++} FRegister;
++
++struct _sim_cpu {
++  union {
++    unsigned_word regs[32];
++    struct {
++      /* These are the ABI names.  */
++      unsigned_word zero, ra, sp, gp, tp;
++      unsigned_word t0, t1, t2;
++      unsigned_word s0, s1;
++      unsigned_word a0, a1, a2, a3, a4, a5, a6, a7;
++      unsigned_word s2, s3, s4, s5, s6, s7, s8, s9, s10, s11;
++      unsigned_word t3, t4, t5, t6;
++    };
++  };
++  union {
++    FRegister fpregs[32];
++    struct {
++      /* These are the ABI names.  */
++      unsigned_word ft0, ft1, ft2, ft3, ft4, ft5, ft6, ft7;
++      unsigned_word fs0, fs1;
++      unsigned_word fa0, fa1, fa2, fa3, fa4, fa5, fa6, fa7;
++      unsigned_word fs2, fs3, fs4, fs5, fs6, fs7, fs8, fs9, fs10, fs11;
++      unsigned_word ft8, ft9, ft10, ft11;
++    };
++  };
++  sim_cia pc;
++  sim_cia endbrk;
++
++  struct {
++#define DECLARE_CSR(name, num, class, def_ver, abort_ver) unsigned_word name;
++#include "opcode/riscv-opc.h"
++#undef DECLARE_CSR
++  } csr;
++
++  sim_cpu_base base;
++};
++
++struct atomic_mem_reserved_list;
++struct atomic_mem_reserved_list {
++  struct atomic_mem_reserved_list *next;
++  address_word addr;
++};
++
++struct sim_state {
++  sim_cpu *cpu[MAX_NR_PROCESSORS];
++  struct atomic_mem_reserved_list *amo_reserved_list;
++
++  /* ... simulator specific members ... */
++  sim_state_base base;
++};
++
++extern void step_once (SIM_CPU *);
++extern void initialize_cpu (SIM_DESC, SIM_CPU *, int);
++extern void initialize_env (SIM_DESC, const char * const *argv,
++			    const char * const *env);
++
++#define DEFAULT_MEM_SIZE (64 * 1024 * 1024)
++
++#define RISCV_XLEN(cpu) MACH_WORD_BITSIZE (CPU_MACH (cpu))
++
++#endif
+diff --git a/sim/testsuite/configure b/sim/testsuite/configure
+index c3674c2fa0..a52f7c2663 100755
+--- a/sim/testsuite/configure
++++ b/sim/testsuite/configure
+@@ -619,6 +619,7 @@ infodir
+ docdir
+ oldincludedir
+ includedir
++runstatedir
+ localstatedir
+ sharedstatedir
+ sysconfdir
+@@ -686,6 +687,7 @@ datadir='${datarootdir}'
+ sysconfdir='${prefix}/etc'
+ sharedstatedir='${prefix}/com'
+ localstatedir='${prefix}/var'
++runstatedir='${localstatedir}/run'
+ includedir='${prefix}/include'
+ oldincludedir='/usr/include'
+ docdir='${datarootdir}/doc/${PACKAGE}'
+@@ -938,6 +940,15 @@ do
+   | -silent | --silent | --silen | --sile | --sil)
+     silent=yes ;;
+ 
++  -runstatedir | --runstatedir | --runstatedi | --runstated \
++  | --runstate | --runstat | --runsta | --runst | --runs \
++  | --run | --ru | --r)
++    ac_prev=runstatedir ;;
++  -runstatedir=* | --runstatedir=* | --runstatedi=* | --runstated=* \
++  | --runstate=* | --runstat=* | --runsta=* | --runst=* | --runs=* \
++  | --run=* | --ru=* | --r=*)
++    runstatedir=$ac_optarg ;;
++
+   -sbindir | --sbindir | --sbindi | --sbind | --sbin | --sbi | --sb)
+     ac_prev=sbindir ;;
+   -sbindir=* | --sbindir=* | --sbindi=* | --sbind=* | --sbin=* \
+@@ -1075,7 +1086,7 @@ fi
+ for ac_var in	exec_prefix prefix bindir sbindir libexecdir datarootdir \
+ 		datadir sysconfdir sharedstatedir localstatedir includedir \
+ 		oldincludedir docdir infodir htmldir dvidir pdfdir psdir \
+-		libdir localedir mandir
++		libdir localedir mandir runstatedir
+ do
+   eval ac_val=\$$ac_var
+   # Remove trailing slashes.
+@@ -1228,6 +1239,7 @@ Fine tuning of the installation directories:
+   --sysconfdir=DIR        read-only single-machine data [PREFIX/etc]
+   --sharedstatedir=DIR    modifiable architecture-independent data [PREFIX/com]
+   --localstatedir=DIR     modifiable single-machine data [PREFIX/var]
++  --runstatedir=DIR       modifiable per-process data [LOCALSTATEDIR/run]
+   --libdir=DIR            object code libraries [EPREFIX/lib]
+   --includedir=DIR        C header files [PREFIX/include]
+   --oldincludedir=DIR     C header files for non-gcc [/usr/include]
+@@ -1934,6 +1946,9 @@ case "${target}" in
+    pru*-*-*)
+        sim_arch=pru
+        ;;
++   riscv*-*-*)
++       sim_arch=riscv
++       ;;
+    rl78-*-*)
+        sim_arch=rl78
+        ;;
+diff --git a/sim/testsuite/sim/riscv/ChangeLog b/sim/testsuite/sim/riscv/ChangeLog
+new file mode 100644
+index 0000000000..72dd0c36da
+--- /dev/null
++++ b/sim/testsuite/sim/riscv/ChangeLog
+@@ -0,0 +1,3 @@
++2015-03-29  Mike Frysinger  <vapier@gentoo.org>
++
++	* allinsn.exp, exit-0.s, exit-7.s, isa.inc, testutils.inc: New files.
+diff --git a/sim/testsuite/sim/riscv/allinsn.exp b/sim/testsuite/sim/riscv/allinsn.exp
+new file mode 100644
+index 0000000000..4ed7cff5d2
+--- /dev/null
++++ b/sim/testsuite/sim/riscv/allinsn.exp
+@@ -0,0 +1,15 @@
++# mcore simulator testsuite
++
++if [istarget riscv-*] {
++    # all machines
++    set all_machs "riscv"
++
++    foreach src [lsort [glob -nocomplain $srcdir/$subdir/*.s]] {
++	# If we're only testing specific files and this isn't one of them,
++	# skip it.
++	if ![runtest_file_p $runtests $src] {
++	    continue
++	}
++	run_sim_test $src $all_machs
++    }
++}
+diff --git a/sim/testsuite/sim/riscv/pass.s b/sim/testsuite/sim/riscv/pass.s
+new file mode 100644
+index 0000000000..bd428ca167
+--- /dev/null
++++ b/sim/testsuite/sim/riscv/pass.s
+@@ -0,0 +1,7 @@
++# check that the sim doesn't die immediately.
++# mach: riscv
++
++.include "testutils.inc"
++
++	start
++	pass
+diff --git a/sim/testsuite/sim/riscv/testutils.inc b/sim/testsuite/sim/riscv/testutils.inc
+new file mode 100644
+index 0000000000..bb92ac0f4d
+--- /dev/null
++++ b/sim/testsuite/sim/riscv/testutils.inc
+@@ -0,0 +1,50 @@
++# MACRO: exit
++	.macro exit nr
++	li a0, \nr
++	# The exit utility function.
++	li a7, 93;
++	.endm
++
++# MACRO: pass
++# Write 'pass' to stdout and quit
++	.macro pass
++	# syscall write().
++	li a7, 64;
++	# Use stdout.
++	li a0, 1;
++	# Point to the string.
++	lla a1, 1f;
++	# Number of bytes to write.
++	li a2, 5;
++	# Trigger OS trap.
++	ecall;
++	exit 0;
++	.data
++	1: .asciz "pass\n"
++	.endm
++
++# MACRO: fail
++# Write 'fail' to stdout and quit
++	.macro fail
++	# syscall write();
++	li a7, 64;
++	# Use stdout.
++	li a0, 1;
++	# Point to the string.
++	lla a1, 1f;
++	# Number of bytes to write.
++	li a2, 5;
++	# Trigger OS trap.
++	ecall;
++	exit 0;
++	.data
++	1: .asciz "fail\n"
++	.endm
++
++# MACRO: start
++# All assembler tests should start with a call to "start"
++	.macro start
++	.text
++.global _start
++_start:
++	.endm
+-- 
+2.33.0
+

+ 37 - 0
recipes-devtools/gdb/files/0002-Make-the-riscv-sim-testsuite-work.patch

@@ -0,0 +1,37 @@
+From f9922f1710db5d7a4e456c1a910c79b48d284c7c Mon Sep 17 00:00:00 2001
+From: Jim Wilson <jimw@sifive.com>
+Date: Tue, 17 Nov 2020 16:51:22 -0800
+Subject: [PATCH 02/48] Make the riscv sim testsuite work.
+
+---
+ sim/testsuite/sim/riscv/allinsn.exp   | 2 +-
+ sim/testsuite/sim/riscv/testutils.inc | 1 +
+ 2 files changed, 2 insertions(+), 1 deletion(-)
+
+diff --git a/sim/testsuite/sim/riscv/allinsn.exp b/sim/testsuite/sim/riscv/allinsn.exp
+index 4ed7cff5d2..8553a795a5 100644
+--- a/sim/testsuite/sim/riscv/allinsn.exp
++++ b/sim/testsuite/sim/riscv/allinsn.exp
+@@ -1,6 +1,6 @@
+ # mcore simulator testsuite
+ 
+-if [istarget riscv-*] {
++if [istarget riscv*-*] {
+     # all machines
+     set all_machs "riscv"
+ 
+diff --git a/sim/testsuite/sim/riscv/testutils.inc b/sim/testsuite/sim/riscv/testutils.inc
+index bb92ac0f4d..b5467ebeab 100644
+--- a/sim/testsuite/sim/riscv/testutils.inc
++++ b/sim/testsuite/sim/riscv/testutils.inc
+@@ -3,6 +3,7 @@
+ 	li a0, \nr
+ 	# The exit utility function.
+ 	li a7, 93;
++	ecall
+ 	.endm
+ 
+ # MACRO: pass
+-- 
+2.33.0
+

+ 27 - 0
recipes-devtools/gdb/files/0003-Fix-riscv-sim-build-on-Mac.-elf-bfd.h-now-requires-s.patch

@@ -0,0 +1,27 @@
+From 63a44e5923c859e99d3a8799fa8132b49a135241 Mon Sep 17 00:00:00 2001
+From: Jim Wilson <jimw@sifive.com>
+Date: Tue, 17 Nov 2020 19:30:08 -0800
+Subject: [PATCH 03/48] Fix riscv sim build on Mac.  elf-bfd.h now requires
+ string.h for strncmp.
+
+---
+ sim/riscv/interp.c | 3 +++
+ 1 file changed, 3 insertions(+)
+
+diff --git a/sim/riscv/interp.c b/sim/riscv/interp.c
+index f28c841cfc..5557d5bb81 100644
+--- a/sim/riscv/interp.c
++++ b/sim/riscv/interp.c
+@@ -27,6 +27,9 @@
+ 
+ #include "config.h"
+ 
++/* elf-bfd.h requires string.h for strncmp.  */
++#include <string.h>
++
+ #include "libiberty.h"
+ #include "bfd.h"
+ #include "elf-bfd.h"
+-- 
+2.33.0
+

+ 1216 - 0
recipes-devtools/gdb/files/0004-RISC-V-Minor-cleanup-and-testcases-improvement-for-a.patch

@@ -0,0 +1,1216 @@
+From c7e8eb17c274e33dd718871f15ee05f1f77341c2 Mon Sep 17 00:00:00 2001
+From: Nelson Chu <nelson.chu@sifive.com>
+Date: Fri, 20 Nov 2020 14:45:32 +0800
+Subject: [PATCH 04/48] RISC-V: Minor cleanup and testcases improvement for
+ arch string parser.
+
+Re-indent the related codes, unify and improve the related error messages
+and comments.  Besies, also re-write the testcases to cover more cases.
+
+	bfd/
+	* elfxx-riscv.c: Re-indent codes, unify and improve the error
+	messages and comments.
+	(riscv_parse_prefixed_ext): Stop parsing the prefixed class
+	extensions if the class is RV_ISA_CLASS_UNKNOWN, I get internal
+	errors before adding this check for march-fail-porder* testcases.
+	(riscv_parse_subset): Move the rv32 with q checking in front.
+	* elfxx-riscv.h: Likewise.
+
+	gas/
+	(These are new testcases that cover more cases)
+	* testsuite/gas/riscv/march-fail-base-01.d: The first extension must
+	be e, i or g.
+	* testsuite/gas/riscv/march-fail-base-01.l: Likewise.
+	* testsuite/gas/riscv/march-fail-base-02.d: rv64e is an invalid base ISA.
+	* testsuite/gas/riscv/march-fail-base-02.l: Likewise.
+	* testsuite/gas/riscv/march-fail-order-std.d: Check orders of standard
+	extensions.
+	* testsuite/gas/riscv/march-fail-order-std.l: Likewise.
+	* testsuite/gas/riscv/march-fail-order-x.d: Check orders of prefixed
+	x extensions.
+	* testsuite/gas/riscv/march-fail-order-x.l: Likewise.
+	* testsuite/gas/riscv/march-fail-porder-x-std.d: Check orders when
+	standard and prefixed extensions are set at the same time.
+	* testsuite/gas/riscv/march-fail-porder-x-z.d: Likewise.
+	* testsuite/gas/riscv/march-fail-porder-z-std.d: Likewise.
+	* testsuite/gas/riscv/march-fail-porder.l: Likewise.
+	* testsuite/gas/riscv/march-fail-single-char-s.d: Only standard
+	extensions can use single char.
+	* testsuite/gas/riscv/march-fail-single-char-x.d: Likewise.
+	* testsuite/gas/riscv/march-fail-single-char-z.d: Likewise.
+	* testsuite/gas/riscv/march-fail-single-char.l: Likewise.
+	* testsuite/gas/riscv/march-fail-unknown-s.d: All extensions
+	should be known, except the non-standard x extensions.
+	* testsuite/gas/riscv/march-fail-unknown-std.d: Likewise.
+	* testsuite/gas/riscv/march-fail-unknown-std.l: Likewise.
+	* testsuite/gas/riscv/march-fail-unknown-z.d: Likewise.
+	* testsuite/gas/riscv/march-fail-unknown.l: Likewise.
+	* testsuite/gas/riscv/march-fail-uppercase-base.d: Do not
+	allow any uppercase in the arch string.
+	* testsuite/gas/riscv/march-fail-uppercase-std.d: Likewise.
+	* testsuite/gas/riscv/march-fail-uppercase-z.d: Likewise.
+	* testsuite/gas/riscv/march-fail-uppercase.l: Likewise.
+	* testsuite/gas/riscv/march-fail-version-x.d: Failed to set versions.
+	* testsuite/gas/riscv/march-fail-version-z.d: Likewise.
+	* testsuite/gas/riscv/march-fail-version.l: Likewise.
+	* testsuite/gas/riscv/march-fail-rv32ef.l: Updated.
+	* testsuite/gas/riscv/march-fail-rv32id.d: Need f-ext.
+	* testsuite/gas/riscv/march-fail-rv32iq.d: Should be rv64.
+	* testsuite/gas/riscv/march-fail-rv32iq.l: Likewise.
+	* testsuite/gas/riscv/march-fail-rv64iq.d: Need d-ext and f-ext.
+	* testsuite/gas/riscv/march-fail-rv64iq.l: Likewise.
+
+	(The following testcases are removed and covered by new testcases)
+	* testsuite/gas/riscv/march-fail-rv32i.d: march-fail-uppercase-base.
+	* testsuite/gas/riscv/march-fail-rv32i.l: Likewise.
+	* testsuite/gas/riscv/march-fail-rv32iam.d: march-fail-order-std.
+	* testsuite/gas/riscv/march-fail-rv32iam.l: Likewise.
+	* testsuite/gas/riscv/march-fail-rv32ic.d: march-fail-uppercase-std.
+	* testsuite/gas/riscv/march-fail-rv32ic.l: Likewise.
+	* testsuite/gas/riscv/march-fail-rv32icx2p.d: march-fail-version-x.
+	* testsuite/gas/riscv/march-fail-rv32icx2p.l: Likewise.
+	* testsuite/gas/riscv/march-fail-rv32imc.d: march-fail-order-std.
+	* testsuite/gas/riscv/march-fail-rv32imc.l: Likewise.
+	* testsuite/gas/riscv/march-fail-rv64I.d: march-fail-uppercase-std.
+	* testsuite/gas/riscv/march-fail-rv64I.l: Likewise.
+	* testsuite/gas/riscv/march-fail-rv64e.d: march-fail-base-02.
+	* testsuite/gas/riscv/march-fail-rv64e.l: Likewise.
+	* testsuite/gas/riscv/march-fail-s-with-version.d: march-fail-unknown-s.
+	* testsuite/gas/riscv/march-fail-s-with-version.l: Likewise.
+	* testsuite/gas/riscv/march-fail-s.d: march-fail-unknown-s.
+	* testsuite/gas/riscv/march-fail-s.l: Likewise.
+	* testsuite/gas/riscv/march-fail-sx.d: march-fail-unknown-s.
+	* testsuite/gas/riscv/march-fail-sx.l: Likewise.
+---
+ bfd/elfxx-riscv.c                             | 214 +++++++++---------
+ bfd/elfxx-riscv.h                             |  27 ++-
+ gas/testsuite/gas/riscv/march-fail-base-01.d  |   3 +
+ gas/testsuite/gas/riscv/march-fail-base-01.l  |   2 +
+ gas/testsuite/gas/riscv/march-fail-base-02.d  |   3 +
+ gas/testsuite/gas/riscv/march-fail-base-02.l  |   2 +
+ ...-fail-rv32imc.d => march-fail-order-std.d} |   2 +-
+ .../gas/riscv/march-fail-order-std.l          |   2 +
+ gas/testsuite/gas/riscv/march-fail-order-x.d  |   3 +
+ gas/testsuite/gas/riscv/march-fail-order-x.l  |   2 +
+ .../gas/riscv/march-fail-porder-x-std.d       |   3 +
+ .../gas/riscv/march-fail-porder-x-z.d         |   3 +
+ .../gas/riscv/march-fail-porder-z-std.d       |   3 +
+ gas/testsuite/gas/riscv/march-fail-porder.l   |   2 +
+ gas/testsuite/gas/riscv/march-fail-rv32ef.l   |   4 +-
+ gas/testsuite/gas/riscv/march-fail-rv32i.d    |   3 -
+ gas/testsuite/gas/riscv/march-fail-rv32i.l    |   2 -
+ gas/testsuite/gas/riscv/march-fail-rv32iam.d  |   3 -
+ gas/testsuite/gas/riscv/march-fail-rv32iam.l  |   2 -
+ gas/testsuite/gas/riscv/march-fail-rv32ic.d   |   3 -
+ gas/testsuite/gas/riscv/march-fail-rv32ic.l   |   2 -
+ .../gas/riscv/march-fail-rv32icx2p.d          |   3 -
+ .../gas/riscv/march-fail-rv32icx2p.l          |   2 -
+ gas/testsuite/gas/riscv/march-fail-rv32id.d   |   3 +
+ gas/testsuite/gas/riscv/march-fail-rv32id.l   |   2 +
+ gas/testsuite/gas/riscv/march-fail-rv32imc.l  |   2 -
+ gas/testsuite/gas/riscv/march-fail-rv32iq.d   |   3 +
+ gas/testsuite/gas/riscv/march-fail-rv32iq.l   |   2 +
+ gas/testsuite/gas/riscv/march-fail-rv64I.d    |   3 -
+ gas/testsuite/gas/riscv/march-fail-rv64I.l    |   2 -
+ gas/testsuite/gas/riscv/march-fail-rv64e.d    |   3 -
+ gas/testsuite/gas/riscv/march-fail-rv64e.l    |   2 -
+ gas/testsuite/gas/riscv/march-fail-rv64iq.d   |   3 +
+ gas/testsuite/gas/riscv/march-fail-rv64iq.l   |   2 +
+ .../gas/riscv/march-fail-s-with-version.d     |   6 -
+ .../gas/riscv/march-fail-s-with-version.l     |   2 -
+ gas/testsuite/gas/riscv/march-fail-s.d        |   6 -
+ gas/testsuite/gas/riscv/march-fail-s.l        |   2 -
+ .../gas/riscv/march-fail-single-char-s.d      |   3 +
+ .../gas/riscv/march-fail-single-char-x.d      |   3 +
+ .../gas/riscv/march-fail-single-char-z.d      |   3 +
+ .../gas/riscv/march-fail-single-char.l        |   2 +
+ gas/testsuite/gas/riscv/march-fail-sx.d       |   6 -
+ gas/testsuite/gas/riscv/march-fail-sx.l       |   2 -
+ .../gas/riscv/march-fail-unknown-s.d          |   3 +
+ .../gas/riscv/march-fail-unknown-std.d        |   3 +
+ .../gas/riscv/march-fail-unknown-std.l        |   2 +
+ .../gas/riscv/march-fail-unknown-z.d          |   3 +
+ gas/testsuite/gas/riscv/march-fail-unknown.l  |   2 +
+ .../gas/riscv/march-fail-uppercase-base.d     |   3 +
+ .../gas/riscv/march-fail-uppercase-std.d      |   3 +
+ .../gas/riscv/march-fail-uppercase-z.d        |   3 +
+ .../gas/riscv/march-fail-uppercase.l          |   2 +
+ .../gas/riscv/march-fail-version-x.d          |   3 +
+ .../gas/riscv/march-fail-version-z.d          |   3 +
+ gas/testsuite/gas/riscv/march-fail-version.l  |   2 +
+ 56 files changed, 206 insertions(+), 183 deletions(-)
+ create mode 100644 gas/testsuite/gas/riscv/march-fail-base-01.d
+ create mode 100644 gas/testsuite/gas/riscv/march-fail-base-01.l
+ create mode 100644 gas/testsuite/gas/riscv/march-fail-base-02.d
+ create mode 100644 gas/testsuite/gas/riscv/march-fail-base-02.l
+ rename gas/testsuite/gas/riscv/{march-fail-rv32imc.d => march-fail-order-std.d} (50%)
+ create mode 100644 gas/testsuite/gas/riscv/march-fail-order-std.l
+ create mode 100644 gas/testsuite/gas/riscv/march-fail-order-x.d
+ create mode 100644 gas/testsuite/gas/riscv/march-fail-order-x.l
+ create mode 100644 gas/testsuite/gas/riscv/march-fail-porder-x-std.d
+ create mode 100644 gas/testsuite/gas/riscv/march-fail-porder-x-z.d
+ create mode 100644 gas/testsuite/gas/riscv/march-fail-porder-z-std.d
+ create mode 100644 gas/testsuite/gas/riscv/march-fail-porder.l
+ delete mode 100644 gas/testsuite/gas/riscv/march-fail-rv32i.d
+ delete mode 100644 gas/testsuite/gas/riscv/march-fail-rv32i.l
+ delete mode 100644 gas/testsuite/gas/riscv/march-fail-rv32iam.d
+ delete mode 100644 gas/testsuite/gas/riscv/march-fail-rv32iam.l
+ delete mode 100644 gas/testsuite/gas/riscv/march-fail-rv32ic.d
+ delete mode 100644 gas/testsuite/gas/riscv/march-fail-rv32ic.l
+ delete mode 100644 gas/testsuite/gas/riscv/march-fail-rv32icx2p.d
+ delete mode 100644 gas/testsuite/gas/riscv/march-fail-rv32icx2p.l
+ create mode 100644 gas/testsuite/gas/riscv/march-fail-rv32id.d
+ create mode 100644 gas/testsuite/gas/riscv/march-fail-rv32id.l
+ delete mode 100644 gas/testsuite/gas/riscv/march-fail-rv32imc.l
+ create mode 100644 gas/testsuite/gas/riscv/march-fail-rv32iq.d
+ create mode 100644 gas/testsuite/gas/riscv/march-fail-rv32iq.l
+ delete mode 100644 gas/testsuite/gas/riscv/march-fail-rv64I.d
+ delete mode 100644 gas/testsuite/gas/riscv/march-fail-rv64I.l
+ delete mode 100644 gas/testsuite/gas/riscv/march-fail-rv64e.d
+ delete mode 100644 gas/testsuite/gas/riscv/march-fail-rv64e.l
+ create mode 100644 gas/testsuite/gas/riscv/march-fail-rv64iq.d
+ create mode 100644 gas/testsuite/gas/riscv/march-fail-rv64iq.l
+ delete mode 100644 gas/testsuite/gas/riscv/march-fail-s-with-version.d
+ delete mode 100644 gas/testsuite/gas/riscv/march-fail-s-with-version.l
+ delete mode 100644 gas/testsuite/gas/riscv/march-fail-s.d
+ delete mode 100644 gas/testsuite/gas/riscv/march-fail-s.l
+ create mode 100644 gas/testsuite/gas/riscv/march-fail-single-char-s.d
+ create mode 100644 gas/testsuite/gas/riscv/march-fail-single-char-x.d
+ create mode 100644 gas/testsuite/gas/riscv/march-fail-single-char-z.d
+ create mode 100644 gas/testsuite/gas/riscv/march-fail-single-char.l
+ delete mode 100644 gas/testsuite/gas/riscv/march-fail-sx.d
+ delete mode 100644 gas/testsuite/gas/riscv/march-fail-sx.l
+ create mode 100644 gas/testsuite/gas/riscv/march-fail-unknown-s.d
+ create mode 100644 gas/testsuite/gas/riscv/march-fail-unknown-std.d
+ create mode 100644 gas/testsuite/gas/riscv/march-fail-unknown-std.l
+ create mode 100644 gas/testsuite/gas/riscv/march-fail-unknown-z.d
+ create mode 100644 gas/testsuite/gas/riscv/march-fail-unknown.l
+ create mode 100644 gas/testsuite/gas/riscv/march-fail-uppercase-base.d
+ create mode 100644 gas/testsuite/gas/riscv/march-fail-uppercase-std.d
+ create mode 100644 gas/testsuite/gas/riscv/march-fail-uppercase-z.d
+ create mode 100644 gas/testsuite/gas/riscv/march-fail-uppercase.l
+ create mode 100644 gas/testsuite/gas/riscv/march-fail-version-x.d
+ create mode 100644 gas/testsuite/gas/riscv/march-fail-version-z.d
+ create mode 100644 gas/testsuite/gas/riscv/march-fail-version.l
+
+diff --git a/bfd/elfxx-riscv.c b/bfd/elfxx-riscv.c
+index cfdd867e0d..dc196e0e12 100644
+--- a/bfd/elfxx-riscv.c
++++ b/bfd/elfxx-riscv.c
+@@ -1010,13 +1010,13 @@ riscv_elf_add_sub_reloc (bfd *abfd,
+   return bfd_reloc_ok;
+ }
+ 
+-/* Parsing subset version.
++/* Parsing extension version.
+ 
+    Return Value:
+      Points to the end of version
+ 
+    Arguments:
+-     `rps`: Hooks and status for parsing subset.
++     `rps`: Hooks and status for parsing extensions.
+      `march`: Full arch string.
+      `p`: Curent parsing position.
+      `major_version`: Parsing result of major version, using
+@@ -1060,7 +1060,7 @@ riscv_parsing_subset_version (riscv_parse_subset_t *rps,
+ 	      else
+ 		{
+ 		  rps->error_handler
+-		    (_("-march=%s: Expect number after `%dp'."),
++		    (_("-march=%s: expect number after `%dp'"),
+ 		     march, version);
+ 		  return NULL;
+ 		}
+@@ -1104,7 +1104,7 @@ riscv_supported_std_ext (void)
+      Points to the end of extensions.
+ 
+    Arguments:
+-     `rps`: Hooks and status for parsing subset.
++     `rps`: Hooks and status for parsing extensions.
+      `march`: Full arch string.
+      `p`: Curent parsing position.  */
+ 
+@@ -1117,21 +1117,17 @@ riscv_parse_std_ext (riscv_parse_subset_t *rps,
+   const char *std_exts = all_std_exts;
+   unsigned major_version = 0;
+   unsigned minor_version = 0;
+-  char std_ext = '\0';
+   bfd_boolean use_default_version = FALSE;
++  char subset[2] = {0, 0};
+ 
+   /* First letter must start with i, e or g.  */
+   switch (*p)
+     {
+       case 'i':
+-	p = riscv_parsing_subset_version (rps,
+-					  march,
+-					  ++p,
++	p = riscv_parsing_subset_version (rps, march, ++p,
+ 					  &major_version,
+-					  &minor_version,
+-					  /* std_ext_p= */TRUE,
++					  &minor_version, TRUE,
+ 					  &use_default_version);
+-
+ 	/* Find the default version if needed.  */
+ 	if (use_default_version
+ 	    && rps->get_default_version != NULL)
+@@ -1139,18 +1135,15 @@ riscv_parse_std_ext (riscv_parse_subset_t *rps,
+ 				    &major_version,
+ 				    &minor_version);
+ 	riscv_add_subset (rps->subset_list, "i",
+-			  major_version, minor_version);
++			  major_version,
++			  minor_version);
+ 	break;
+ 
+       case 'e':
+-	p = riscv_parsing_subset_version (rps,
+-					  march,
+-					  ++p,
++	p = riscv_parsing_subset_version (rps, march, ++p,
+ 					  &major_version,
+-					  &minor_version,
+-					  /* std_ext_p= */TRUE,
++					  &minor_version, TRUE,
+ 					  &use_default_version);
+-
+ 	/* Find the default version if needed.  */
+ 	if (use_default_version
+ 	    && rps->get_default_version != NULL)
+@@ -1158,7 +1151,8 @@ riscv_parse_std_ext (riscv_parse_subset_t *rps,
+ 				    &major_version,
+ 				    &minor_version);
+ 	riscv_add_subset (rps->subset_list, "e",
+-			  major_version, minor_version);
++			  major_version,
++			  minor_version);
+ 
+ 	/* i-ext must be enabled.  */
+ 	if (rps->get_default_version != NULL)
+@@ -1166,7 +1160,8 @@ riscv_parse_std_ext (riscv_parse_subset_t *rps,
+ 				    &major_version,
+ 				    &minor_version);
+ 	riscv_add_subset (rps->subset_list, "i",
+-			  major_version, minor_version);
++			  major_version,
++			  minor_version);
+ 
+ 	if (*rps->xlen > 32)
+ 	  {
+@@ -1180,47 +1175,41 @@ riscv_parse_std_ext (riscv_parse_subset_t *rps,
+       case 'g':
+ 	/* The g-ext shouldn't has the version, so we just
+ 	   skip the setting if user set a version to it.  */
+-	p = riscv_parsing_subset_version (rps,
+-					  march,
+-					  ++p,
++	p = riscv_parsing_subset_version (rps, march, ++p,
+ 					  &major_version,
+-					  &minor_version,
+-					  TRUE,
++					  &minor_version, TRUE,
+ 					  &use_default_version);
+-
+ 	/* i-ext must be enabled.  */
+ 	if (rps->get_default_version != NULL)
+ 	  rps->get_default_version ("i",
+ 				    &major_version,
+ 				    &minor_version);
+ 	riscv_add_subset (rps->subset_list, "i",
+-			  major_version, minor_version);
++			  major_version,
++			  minor_version);
+ 
+ 	for ( ; *std_exts != 'q'; std_exts++)
+ 	  {
+-	    const char subset[] = {*std_exts, '\0'};
+-
++	    subset[0] = *std_exts;
+ 	    if (rps->get_default_version != NULL)
+ 	      rps->get_default_version (subset,
+ 					&major_version,
+ 					&minor_version);
+ 	    riscv_add_subset (rps->subset_list, subset,
+-			      major_version, minor_version);
++			      major_version,
++			      minor_version);
+ 	  }
+ 	break;
+ 
+       default:
+ 	rps->error_handler
+-	  (_("-march=%s: first ISA subset must be `e', `i' or `g'"), march);
++	  (_("-march=%s: first ISA extension must be `e', `i' or `g'"),
++	   march);
+ 	return NULL;
+     }
+ 
+-  /* The riscv_parsing_subset_version may set `p` to NULL, so I think we should
+-     skip parsing the string if `p` is NULL or value of `p` is `\0`.  */
+   while (p != NULL && *p != '\0')
+     {
+-      char subset[2] = {0, 0};
+-
+       if (*p == 'x' || *p == 's' || *p == 'z')
+ 	break;
+ 
+@@ -1230,35 +1219,31 @@ riscv_parse_std_ext (riscv_parse_subset_t *rps,
+ 	  continue;
+ 	}
+ 
+-      std_ext = *p;
+-
+       /* Checking canonical order.  */
+-      while (*std_exts && std_ext != *std_exts) std_exts++;
++      char std_ext = *p;
++      while (*std_exts && std_ext != *std_exts)
++	std_exts++;
+ 
+       if (std_ext != *std_exts)
+ 	{
+ 	  if (strchr (all_std_exts, std_ext) == NULL)
+ 	    rps->error_handler
+-	      (_("-march=%s: unsupported ISA subset `%c'"), march, *p);
++	      (_("-march=%s: unknown standard ISA extension `%c'"),
++	       march, std_ext);
+ 	  else
+ 	    rps->error_handler
+-	      (_("-march=%s: ISA string is not in canonical order. `%c'"),
+-	       march, *p);
++	      (_("-march=%s: standard ISA extension `%c' is not "
++		 "in canonical order"), march, std_ext);
+ 	  return NULL;
+ 	}
+ 
+       std_exts++;
+-
+       use_default_version = FALSE;
+       subset[0] = std_ext;
+-      p = riscv_parsing_subset_version (rps,
+-					march,
+-					++p,
++      p = riscv_parsing_subset_version (rps, march, ++p,
+ 					&major_version,
+-					&minor_version,
+-					TRUE,
++					&minor_version, TRUE,
+ 					&use_default_version);
+-
+       /* Find the default version if needed.  */
+       if (use_default_version
+ 	  && rps->get_default_version != NULL)
+@@ -1266,8 +1251,10 @@ riscv_parse_std_ext (riscv_parse_subset_t *rps,
+ 				  &major_version,
+ 				  &minor_version);
+       riscv_add_subset (rps->subset_list, subset,
+-			major_version, minor_version);
++			major_version,
++			minor_version);
+     }
++
+   return p;
+ }
+ 
+@@ -1294,23 +1281,26 @@ typedef struct riscv_parse_config
+   /* Class of the extension. */
+   riscv_isa_ext_class_t class;
+ 
+-  /* Lower-case prefix string for error printing
+-     and internal parser usage, e.g. "z", "x".  */
++  /* Prefix string for error printing and internal parser usage.  */
+   const char *prefix;
+ 
+-  /* Predicate which is used for checking whether
+-     this is a "known" extension. For 'x',
+-     it always returns true (since they are by
++  /* Predicate which is used for checking whether this is a "known"
++     extension. For 'x', it always returns true since they are by
+      definition non-standard and cannot be known.  */
+   bfd_boolean (*ext_valid_p) (const char *);
+ } riscv_parse_config_t;
+ 
+-/* Parse a generic prefixed extension.
+-   `rps`: Hooks and status for parsing subset.
+-   `march`: The full architecture string as passed in by "-march=...".
+-   `p`: Point from which to start parsing the -march string.
+-   `config`: What class of extensions to parse, predicate funcs,
+-   and strings to use in error reporting.  */
++/* Parsing function for prefixed extensions.
++
++   Return Value:
++     Points to the end of extension.
++
++   Arguments:
++     `rps`: Hooks and status for parsing extensions.
++     `march`: Full architecture string.
++     `p`: Curent parsing position.
++     `config`: What class and predicate function to use for the
++     extension.  */
+ 
+ static const char *
+ riscv_parse_prefixed_ext (riscv_parse_subset_t *rps,
+@@ -1335,7 +1325,8 @@ riscv_parse_prefixed_ext (riscv_parse_subset_t *rps,
+       /* Assert that the current extension specifier matches our parsing
+ 	 class.  */
+       class = riscv_get_prefix_class (p);
+-      if (class != config->class)
++      if (class != config->class
++	  || class == RV_ISA_CLASS_UNKNOWN)
+ 	break;
+ 
+       char *subset = xstrdup (p);
+@@ -1347,12 +1338,13 @@ riscv_parse_prefixed_ext (riscv_parse_subset_t *rps,
+ 
+       use_default_version = FALSE;
+       end_of_version =
+-	riscv_parsing_subset_version (rps, march, q, &major_version,
++	riscv_parsing_subset_version (rps, march, q,
++				      &major_version,
+ 				      &minor_version, FALSE,
+ 				      &use_default_version);
+       *q = '\0';
+ 
+-      /* Check that the name is valid.
++      /* Check that the prefix extension is known.
+ 	 For 'x', anything goes but it cannot simply be 'x'.
+ 	 For 's', it must be known from a list and cannot simply be 's'.
+ 	 For 'z', it must be known from a list and cannot simply be 'z'.  */
+@@ -1361,30 +1353,30 @@ riscv_parse_prefixed_ext (riscv_parse_subset_t *rps,
+       if (!config->ext_valid_p (subset))
+ 	{
+ 	  rps->error_handler
+-	    (_("-march=%s: Invalid or unknown %s ISA extension: '%s'"),
++	    (_("-march=%s: unknown %s ISA extension `%s'"),
+ 	     march, config->prefix, subset);
+ 	  free (subset);
+ 	  return NULL;
+ 	}
+ 
+-      /* Check that the last item is not the same as this.  */
++      /* Check that the extension isn't duplicate.  */
+       last_name = rps->subset_list->tail->name;
+       if (!strcasecmp (last_name, subset))
+ 	{
+ 	  rps->error_handler
+-	    (_("-march=%s: Duplicate %s ISA extension: \'%s\'"),
++	    (_("-march=%s: duplicate %s ISA extension `%s'"),
+ 	     march, config->prefix, subset);
+ 	  free (subset);
+ 	  return NULL;
+ 	}
+ 
+-      /* Check that we are in alphabetical order within the subset.  */
++      /* Check that the extension is in alphabetical order.  */
+       if (!strncasecmp (last_name, config->prefix, 1)
+ 	  && strcasecmp (last_name, subset) > 0)
+ 	{
+ 	  rps->error_handler
+-	    (_("\
+--march=%s: %s ISA extension not in alphabetical order: \'%s\' must come before \'%s\'."),
++	    (_("-march=%s: %s ISA extension `%s' is not in alphabetical "
++	       "order.  It must come before `%s'"),
+ 	     march, config->prefix, subset, last_name);
+ 	  free (subset);
+ 	  return NULL;
+@@ -1397,15 +1389,17 @@ riscv_parse_prefixed_ext (riscv_parse_subset_t *rps,
+                                  &major_version,
+                                  &minor_version);
+       riscv_add_subset (rps->subset_list, subset,
+-                       major_version, minor_version);
++			major_version,
++			minor_version);
+ 
+       free (subset);
+       p += end_of_version - subset;
+ 
+       if (*p != '\0' && *p != '_')
+ 	{
+-	  rps->error_handler (_("-march=%s: %s must separate with _"),
+-			      march, config->prefix);
++	  rps->error_handler
++	    (_("-march=%s: %s ISA extension must separate with _"),
++	     march, config->prefix);
+ 	  return NULL;
+ 	}
+     }
+@@ -1413,30 +1407,26 @@ riscv_parse_prefixed_ext (riscv_parse_subset_t *rps,
+   return p;
+ }
+ 
+-/* List of Z-class extensions that binutils should know about.
+-   Whether or not a particular entry is in this list will
+-   dictate if gas/ld will accept its presence in the -march
+-   string.
++/* Lists of prefixed class extensions that binutils should know about.
++   Whether or not a particular entry is in these lists will dictate if
++   gas/ld will accept its presence in the architecture string.
+ 
+-   Example: To add an extension called "Zbb" (bitmanip base extension),
+-   add "zbb" string to the list (all lowercase).
+-
+-   Keep this list alphabetically ordered.  */
++   Please add the extensions to the lists in lower case.  However, keep
++   these subsets in alphabetical order in these tables is recommended,
++   although there is no impact on the current implementation.  */
+ 
+ static const char * const riscv_std_z_ext_strtab[] =
+-  {
+-    "zicsr", NULL
+-  };
+-
+-/* Same as `riscv_std_z_ext_strtab', but for S-class extensions.  */
++{
++  "zicsr", NULL
++};
+ 
+ static const char * const riscv_std_s_ext_strtab[] =
+-  {
+-    NULL
+-  };
++{
++  NULL
++};
+ 
+-/* For the extension EXT, search through the list of known extensions
+-   KNOWN_EXTS for a match, and return TRUE if found.  */
++/* For the extension `ext`, search through the list of known extensions
++   `known_exts` for a match, and return TRUE if found.  */
+ 
+ static bfd_boolean
+ riscv_multi_letter_ext_valid_p (const char *ext,
+@@ -1473,7 +1463,7 @@ riscv_ext_z_valid_p (const char *arg)
+ }
+ 
+ /* Predicator function for 's' prefixed extensions.
+-   Must be either literal 's', or a known s-prefixed extension.  */
++   Only known s-extensions are permitted.  */
+ 
+ static bfd_boolean
+ riscv_ext_s_valid_p (const char *arg)
+@@ -1481,14 +1471,15 @@ riscv_ext_s_valid_p (const char *arg)
+   return riscv_multi_letter_ext_valid_p (arg, riscv_std_s_ext_strtab);
+ }
+ 
+-/* Parsing order that is specified by the ISA manual.  */
++/* Parsing order of the prefixed extensions that is specified by
++   the ISA spec.  */
+ 
+ static const riscv_parse_config_t parse_config[] =
+ {
+-   {RV_ISA_CLASS_S, "s", riscv_ext_s_valid_p},
+-   {RV_ISA_CLASS_Z, "z", riscv_ext_z_valid_p},
+-   {RV_ISA_CLASS_X, "x", riscv_ext_x_valid_p},
+-   {RV_ISA_CLASS_UNKNOWN, NULL, NULL}
++  {RV_ISA_CLASS_S, "s", riscv_ext_s_valid_p},
++  {RV_ISA_CLASS_Z, "z", riscv_ext_z_valid_p},
++  {RV_ISA_CLASS_X, "x", riscv_ext_x_valid_p},
++  {RV_ISA_CLASS_UNKNOWN, NULL, NULL}
+ };
+ 
+ /* Function for parsing arch string.
+@@ -1497,8 +1488,8 @@ static const riscv_parse_config_t parse_config[] =
+      Return TRUE on success.
+ 
+    Arguments:
+-     `rps`: Hooks and status for parsing subset.
+-     `arch`: Arch string.  */
++     `rps`: Hooks and status for parsing extensions.
++     `arch`: Full arch string.  */
+ 
+ bfd_boolean
+ riscv_parse_subset (riscv_parse_subset_t *rps,
+@@ -1538,12 +1529,13 @@ riscv_parse_subset (riscv_parse_subset_t *rps,
+     return FALSE;
+ 
+   /* Parse the different classes of extensions in the specified order.  */
+-  for (i = 0; i < ARRAY_SIZE (parse_config); ++i) {
+-    p = riscv_parse_prefixed_ext (rps, arch, p, &parse_config[i]);
++  for (i = 0; i < ARRAY_SIZE (parse_config); ++i)
++    {
++      p = riscv_parse_prefixed_ext (rps, arch, p, &parse_config[i]);
+ 
+-    if (p == NULL)
+-      return FALSE;
+-  }
++      if (p == NULL)
++	return FALSE;
++    }
+ 
+   if (*p != '\0')
+     {
+@@ -1552,6 +1544,7 @@ riscv_parse_subset (riscv_parse_subset_t *rps,
+       return FALSE;
+     }
+ 
++  /* Check the conflicts.  */
+   if (riscv_lookup_subset (rps->subset_list, "e")
+       && riscv_lookup_subset (rps->subset_list, "f"))
+     {
+@@ -1561,6 +1554,14 @@ riscv_parse_subset (riscv_parse_subset_t *rps,
+       return FALSE;
+     }
+ 
++  if (riscv_lookup_subset (rps->subset_list, "q") && *rps->xlen < 64)
++    {
++      rps->error_handler
++	(_("-march=%s: rv32 does not support the `q' extension"),
++	 arch);
++      return FALSE;
++    }
++
+   if (riscv_lookup_subset (rps->subset_list, "d")
+       && !riscv_lookup_subset (rps->subset_list, "f"))
+     {
+@@ -1579,13 +1580,6 @@ riscv_parse_subset (riscv_parse_subset_t *rps,
+       return FALSE;
+     }
+ 
+-  if (riscv_lookup_subset (rps->subset_list, "q") && *rps->xlen < 64)
+-    {
+-      rps->error_handler
+-	(_("-march=%s: rv32 does not support the `q' extension"),
+-	 arch);
+-      return FALSE;
+-    }
+   return TRUE;
+ }
+ 
+diff --git a/bfd/elfxx-riscv.h b/bfd/elfxx-riscv.h
+index c91b169e99..b5b17d1687 100644
+--- a/bfd/elfxx-riscv.h
++++ b/bfd/elfxx-riscv.h
+@@ -46,7 +46,8 @@ struct riscv_subset_t
+ 
+ typedef struct riscv_subset_t riscv_subset_t;
+ 
+-typedef struct {
++typedef struct
++{
+   riscv_subset_t *head;
+   riscv_subset_t *tail;
+ } riscv_subset_list_t;
+@@ -68,14 +69,15 @@ riscv_lookup_subset_version (const riscv_subset_list_t *,
+ 			     const char *,
+ 			     int, int);
+ 
+-typedef struct {
++typedef struct
++{
+   riscv_subset_list_t *subset_list;
+   void (*error_handler) (const char *,
+ 			 ...) ATTRIBUTE_PRINTF_1;
+   unsigned *xlen;
+   void (*get_default_version) (const char *,
+-                              unsigned int *,
+-                              unsigned int *);
++			       unsigned int *,
++			       unsigned int *);
+ } riscv_parse_subset_t;
+ 
+ extern bfd_boolean
+@@ -95,18 +97,15 @@ extern size_t
+ riscv_estimate_digit (unsigned);
+ 
+ /* ISA extension name class. E.g. "zbb" corresponds to RV_ISA_CLASS_Z,
+-   "xargs" corresponds to RV_ISA_CLASS_X, etc.  Order is important
+-   here.  */
++   "xargs" corresponds to RV_ISA_CLASS_X, etc.  */
+ 
+ typedef enum riscv_isa_ext_class
+-  {
+-   RV_ISA_CLASS_S,
+-   RV_ISA_CLASS_Z,
+-   RV_ISA_CLASS_X,
+-   RV_ISA_CLASS_UNKNOWN
+-  } riscv_isa_ext_class_t;
+-
+-/* Classify the argument 'ext' into one of riscv_isa_ext_class_t.  */
++{
++  RV_ISA_CLASS_S,
++  RV_ISA_CLASS_Z,
++  RV_ISA_CLASS_X,
++  RV_ISA_CLASS_UNKNOWN
++} riscv_isa_ext_class_t;
+ 
+ riscv_isa_ext_class_t
+ riscv_get_prefix_class (const char *);
+diff --git a/gas/testsuite/gas/riscv/march-fail-base-01.d b/gas/testsuite/gas/riscv/march-fail-base-01.d
+new file mode 100644
+index 0000000000..68cd453111
+--- /dev/null
++++ b/gas/testsuite/gas/riscv/march-fail-base-01.d
+@@ -0,0 +1,3 @@
++#as: -march=rv32m
++#source: empty.s
++#error_output: march-fail-base-01.l
+diff --git a/gas/testsuite/gas/riscv/march-fail-base-01.l b/gas/testsuite/gas/riscv/march-fail-base-01.l
+new file mode 100644
+index 0000000000..9fa071f5b0
+--- /dev/null
++++ b/gas/testsuite/gas/riscv/march-fail-base-01.l
+@@ -0,0 +1,2 @@
++.*Assembler messages:
++.*Fatal error: .*first ISA extension must be `e', `i' or `g'
+diff --git a/gas/testsuite/gas/riscv/march-fail-base-02.d b/gas/testsuite/gas/riscv/march-fail-base-02.d
+new file mode 100644
+index 0000000000..cfe085ab21
+--- /dev/null
++++ b/gas/testsuite/gas/riscv/march-fail-base-02.d
+@@ -0,0 +1,3 @@
++#as: -march=rv64e
++#source: empty.s
++#error_output: march-fail-base-02.l
+diff --git a/gas/testsuite/gas/riscv/march-fail-base-02.l b/gas/testsuite/gas/riscv/march-fail-base-02.l
+new file mode 100644
+index 0000000000..6fc4dfa7ba
+--- /dev/null
++++ b/gas/testsuite/gas/riscv/march-fail-base-02.l
+@@ -0,0 +1,2 @@
++.*Assembler messages:
++.*Fatal error: .*rv64e is not a valid base ISA
+diff --git a/gas/testsuite/gas/riscv/march-fail-rv32imc.d b/gas/testsuite/gas/riscv/march-fail-order-std.d
+similarity index 50%
+rename from gas/testsuite/gas/riscv/march-fail-rv32imc.d
+rename to gas/testsuite/gas/riscv/march-fail-order-std.d
+index 1cb4d9ef0b..b9c7e09de1 100644
+--- a/gas/testsuite/gas/riscv/march-fail-rv32imc.d
++++ b/gas/testsuite/gas/riscv/march-fail-order-std.d
+@@ -1,3 +1,3 @@
+ #as: -march=rv32iamfd
+ #source: empty.s
+-#error_output: march-fail-rv32imc.l
++#error_output: march-fail-order-std.l
+diff --git a/gas/testsuite/gas/riscv/march-fail-order-std.l b/gas/testsuite/gas/riscv/march-fail-order-std.l
+new file mode 100644
+index 0000000000..666a8c0d2c
+--- /dev/null
++++ b/gas/testsuite/gas/riscv/march-fail-order-std.l
+@@ -0,0 +1,2 @@
++.*Assembler messages:
++.*Fatal error: .*standard ISA extension `m' is not in canonical order
+diff --git a/gas/testsuite/gas/riscv/march-fail-order-x.d b/gas/testsuite/gas/riscv/march-fail-order-x.d
+new file mode 100644
+index 0000000000..72a821ef8e
+--- /dev/null
++++ b/gas/testsuite/gas/riscv/march-fail-order-x.d
+@@ -0,0 +1,3 @@
++#as: -march=rv32i_xbargle2p0_xargle2p0
++#source: empty.s
++#error_output: march-fail-order-x.l
+diff --git a/gas/testsuite/gas/riscv/march-fail-order-x.l b/gas/testsuite/gas/riscv/march-fail-order-x.l
+new file mode 100644
+index 0000000000..f7b383d855
+--- /dev/null
++++ b/gas/testsuite/gas/riscv/march-fail-order-x.l
+@@ -0,0 +1,2 @@
++.*Assembler messages:
++.*Fatal error: .*x ISA extension `xargle' is not in alphabetical order.  It must come before `xbargle'
+diff --git a/gas/testsuite/gas/riscv/march-fail-porder-x-std.d b/gas/testsuite/gas/riscv/march-fail-porder-x-std.d
+new file mode 100644
+index 0000000000..2bef073464
+--- /dev/null
++++ b/gas/testsuite/gas/riscv/march-fail-porder-x-std.d
+@@ -0,0 +1,3 @@
++#as: -march=rv32i_xargle2p0_mafd
++#source: empty.s
++#error_output: march-fail-porder.l
+diff --git a/gas/testsuite/gas/riscv/march-fail-porder-x-z.d b/gas/testsuite/gas/riscv/march-fail-porder-x-z.d
+new file mode 100644
+index 0000000000..094180ddd0
+--- /dev/null
++++ b/gas/testsuite/gas/riscv/march-fail-porder-x-z.d
+@@ -0,0 +1,3 @@
++#as: -march=rv32i_xargle2p0_zicsr2p0
++#source: empty.s
++#error_output: march-fail-porder.l
+diff --git a/gas/testsuite/gas/riscv/march-fail-porder-z-std.d b/gas/testsuite/gas/riscv/march-fail-porder-z-std.d
+new file mode 100644
+index 0000000000..1fa1a159f3
+--- /dev/null
++++ b/gas/testsuite/gas/riscv/march-fail-porder-z-std.d
+@@ -0,0 +1,3 @@
++#as: -march=rv32i_zicsr2p0_mafd
++#source: empty.s
++#error_output: march-fail-porder.l
+diff --git a/gas/testsuite/gas/riscv/march-fail-porder.l b/gas/testsuite/gas/riscv/march-fail-porder.l
+new file mode 100644
+index 0000000000..a06d586580
+--- /dev/null
++++ b/gas/testsuite/gas/riscv/march-fail-porder.l
+@@ -0,0 +1,2 @@
++.*Assembler messages:
++.*Fatal error: .*unexpected ISA string at end:.*
+diff --git a/gas/testsuite/gas/riscv/march-fail-rv32ef.l b/gas/testsuite/gas/riscv/march-fail-rv32ef.l
+index 15e56c8bdc..d2d915d872 100644
+--- a/gas/testsuite/gas/riscv/march-fail-rv32ef.l
++++ b/gas/testsuite/gas/riscv/march-fail-rv32ef.l
+@@ -1,2 +1,2 @@
+-Assembler messages:
+-Fatal error: -march=rv32ef: rv32e does not support the `f' extension
++.*Assembler messages:
++.*Fatal error: .*rv32e does not support the `f' extension
+diff --git a/gas/testsuite/gas/riscv/march-fail-rv32i.d b/gas/testsuite/gas/riscv/march-fail-rv32i.d
+deleted file mode 100644
+index 1e6e9e0868..0000000000
+--- a/gas/testsuite/gas/riscv/march-fail-rv32i.d
++++ /dev/null
+@@ -1,3 +0,0 @@
+-#as: -march=rv32I
+-#source: empty.s
+-#error_output: march-fail-rv32i.l
+diff --git a/gas/testsuite/gas/riscv/march-fail-rv32i.l b/gas/testsuite/gas/riscv/march-fail-rv32i.l
+deleted file mode 100644
+index 1977aede3b..0000000000
+--- a/gas/testsuite/gas/riscv/march-fail-rv32i.l
++++ /dev/null
+@@ -1,2 +0,0 @@
+-Assembler messages:
+-Fatal error: -march=rv32I: first ISA subset must be `e', `i' or `g'
+diff --git a/gas/testsuite/gas/riscv/march-fail-rv32iam.d b/gas/testsuite/gas/riscv/march-fail-rv32iam.d
+deleted file mode 100644
+index 054cf4d28b..0000000000
+--- a/gas/testsuite/gas/riscv/march-fail-rv32iam.d
++++ /dev/null
+@@ -1,3 +0,0 @@
+-#as: -march=rv32iam
+-#source: empty.s
+-#error_output: march-fail-rv32iam.l
+diff --git a/gas/testsuite/gas/riscv/march-fail-rv32iam.l b/gas/testsuite/gas/riscv/march-fail-rv32iam.l
+deleted file mode 100644
+index c7786f82ea..0000000000
+--- a/gas/testsuite/gas/riscv/march-fail-rv32iam.l
++++ /dev/null
+@@ -1,2 +0,0 @@
+-Assembler messages:
+-Fatal error: -march=rv32iam: ISA string is not in canonical order. `m'
+diff --git a/gas/testsuite/gas/riscv/march-fail-rv32ic.d b/gas/testsuite/gas/riscv/march-fail-rv32ic.d
+deleted file mode 100644
+index b419a654bd..0000000000
+--- a/gas/testsuite/gas/riscv/march-fail-rv32ic.d
++++ /dev/null
+@@ -1,3 +0,0 @@
+-#as: -march=rv32iC
+-#source: empty.s
+-#error_output: march-fail-rv32ic.l
+diff --git a/gas/testsuite/gas/riscv/march-fail-rv32ic.l b/gas/testsuite/gas/riscv/march-fail-rv32ic.l
+deleted file mode 100644
+index d24ea2fd03..0000000000
+--- a/gas/testsuite/gas/riscv/march-fail-rv32ic.l
++++ /dev/null
+@@ -1,2 +0,0 @@
+-Assembler messages:
+-Fatal error: -march=rv32iC: unsupported ISA subset `C'
+diff --git a/gas/testsuite/gas/riscv/march-fail-rv32icx2p.d b/gas/testsuite/gas/riscv/march-fail-rv32icx2p.d
+deleted file mode 100644
+index 51980906cd..0000000000
+--- a/gas/testsuite/gas/riscv/march-fail-rv32icx2p.d
++++ /dev/null
+@@ -1,3 +0,0 @@
+-#as: -march=rv32icx2p
+-#source: empty.s
+-#error_output: march-fail-rv32icx2p.l
+diff --git a/gas/testsuite/gas/riscv/march-fail-rv32icx2p.l b/gas/testsuite/gas/riscv/march-fail-rv32icx2p.l
+deleted file mode 100644
+index 25627d4054..0000000000
+--- a/gas/testsuite/gas/riscv/march-fail-rv32icx2p.l
++++ /dev/null
+@@ -1,2 +0,0 @@
+-Assembler messages:
+-Fatal error: -march=rv32icx2p: Expect number after `2p'.
+diff --git a/gas/testsuite/gas/riscv/march-fail-rv32id.d b/gas/testsuite/gas/riscv/march-fail-rv32id.d
+new file mode 100644
+index 0000000000..de741cbc81
+--- /dev/null
++++ b/gas/testsuite/gas/riscv/march-fail-rv32id.d
+@@ -0,0 +1,3 @@
++#as: -march=rv32id
++#source: empty.s
++#error_output: march-fail-rv32id.l
+diff --git a/gas/testsuite/gas/riscv/march-fail-rv32id.l b/gas/testsuite/gas/riscv/march-fail-rv32id.l
+new file mode 100644
+index 0000000000..29b2717ef7
+--- /dev/null
++++ b/gas/testsuite/gas/riscv/march-fail-rv32id.l
+@@ -0,0 +1,2 @@
++.*Assembler messages:
++.*Fatal error: .*`d' extension requires `f' extension
+diff --git a/gas/testsuite/gas/riscv/march-fail-rv32imc.l b/gas/testsuite/gas/riscv/march-fail-rv32imc.l
+deleted file mode 100644
+index d922e9d348..0000000000
+--- a/gas/testsuite/gas/riscv/march-fail-rv32imc.l
++++ /dev/null
+@@ -1,2 +0,0 @@
+-Assembler messages:
+-Fatal error: -march=rv32iamfd: ISA string is not in canonical order. `m'
+diff --git a/gas/testsuite/gas/riscv/march-fail-rv32iq.d b/gas/testsuite/gas/riscv/march-fail-rv32iq.d
+new file mode 100644
+index 0000000000..c289c695ca
+--- /dev/null
++++ b/gas/testsuite/gas/riscv/march-fail-rv32iq.d
+@@ -0,0 +1,3 @@
++#as: -march=rv32iq
++#source: empty.s
++#error_output: march-fail-rv32iq.l
+diff --git a/gas/testsuite/gas/riscv/march-fail-rv32iq.l b/gas/testsuite/gas/riscv/march-fail-rv32iq.l
+new file mode 100644
+index 0000000000..361c381b86
+--- /dev/null
++++ b/gas/testsuite/gas/riscv/march-fail-rv32iq.l
+@@ -0,0 +1,2 @@
++.*Assembler messages:
++.*Fatal error: .*rv32 does not support the `q' extension
+diff --git a/gas/testsuite/gas/riscv/march-fail-rv64I.d b/gas/testsuite/gas/riscv/march-fail-rv64I.d
+deleted file mode 100644
+index e00a6f86eb..0000000000
+--- a/gas/testsuite/gas/riscv/march-fail-rv64I.d
++++ /dev/null
+@@ -1,3 +0,0 @@
+-#as: -march=rv64I
+-#source: empty.s
+-#error_output: march-fail-rv64I.l
+diff --git a/gas/testsuite/gas/riscv/march-fail-rv64I.l b/gas/testsuite/gas/riscv/march-fail-rv64I.l
+deleted file mode 100644
+index 5b46e77d4b..0000000000
+--- a/gas/testsuite/gas/riscv/march-fail-rv64I.l
++++ /dev/null
+@@ -1,2 +0,0 @@
+-Assembler messages:
+-Fatal error: -march=rv64I: first ISA subset must be `e', `i' or `g'
+diff --git a/gas/testsuite/gas/riscv/march-fail-rv64e.d b/gas/testsuite/gas/riscv/march-fail-rv64e.d
+deleted file mode 100644
+index 38d73db474..0000000000
+--- a/gas/testsuite/gas/riscv/march-fail-rv64e.d
++++ /dev/null
+@@ -1,3 +0,0 @@
+-#as: -march=rv64e
+-#source: empty.s
+-#error_output: march-fail-rv64e.l
+diff --git a/gas/testsuite/gas/riscv/march-fail-rv64e.l b/gas/testsuite/gas/riscv/march-fail-rv64e.l
+deleted file mode 100644
+index 85f755462f..0000000000
+--- a/gas/testsuite/gas/riscv/march-fail-rv64e.l
++++ /dev/null
+@@ -1,2 +0,0 @@
+-Assembler messages:
+-Fatal error: -march=rv64e: rv64e is not a valid base ISA
+diff --git a/gas/testsuite/gas/riscv/march-fail-rv64iq.d b/gas/testsuite/gas/riscv/march-fail-rv64iq.d
+new file mode 100644
+index 0000000000..c97a812cb3
+--- /dev/null
++++ b/gas/testsuite/gas/riscv/march-fail-rv64iq.d
+@@ -0,0 +1,3 @@
++#as: -march=rv64iq
++#source: empty.s
++#error_output: march-fail-rv64iq.l
+diff --git a/gas/testsuite/gas/riscv/march-fail-rv64iq.l b/gas/testsuite/gas/riscv/march-fail-rv64iq.l
+new file mode 100644
+index 0000000000..76a41043e3
+--- /dev/null
++++ b/gas/testsuite/gas/riscv/march-fail-rv64iq.l
+@@ -0,0 +1,2 @@
++.*Assembler messages:
++.*Fatal error: .*`q' extension requires `d' extension
+diff --git a/gas/testsuite/gas/riscv/march-fail-s-with-version.d b/gas/testsuite/gas/riscv/march-fail-s-with-version.d
+deleted file mode 100644
+index 9881c2a0e0..0000000000
+--- a/gas/testsuite/gas/riscv/march-fail-s-with-version.d
++++ /dev/null
+@@ -1,6 +0,0 @@
+-#as: -march=rv32isfoo3p4
+-#objdump: -dr
+-#source: empty.s
+-#error_output: march-fail-s-with-version.l
+-
+-.*:     file format elf32-littleriscv
+diff --git a/gas/testsuite/gas/riscv/march-fail-s-with-version.l b/gas/testsuite/gas/riscv/march-fail-s-with-version.l
+deleted file mode 100644
+index 6b1f957276..0000000000
+--- a/gas/testsuite/gas/riscv/march-fail-s-with-version.l
++++ /dev/null
+@@ -1,2 +0,0 @@
+-Assembler messages:
+-.*: Invalid or unknown s ISA extension: 'sfoo'
+diff --git a/gas/testsuite/gas/riscv/march-fail-s.d b/gas/testsuite/gas/riscv/march-fail-s.d
+deleted file mode 100644
+index ebc8377aaf..0000000000
+--- a/gas/testsuite/gas/riscv/march-fail-s.d
++++ /dev/null
+@@ -1,6 +0,0 @@
+-#as: -march=rv32isfoo
+-#objdump: -dr
+-#source: empty.s
+-#error_output: march-fail-s.l
+-
+-.*:     file format elf32-littleriscv
+diff --git a/gas/testsuite/gas/riscv/march-fail-s.l b/gas/testsuite/gas/riscv/march-fail-s.l
+deleted file mode 100644
+index 6b1f957276..0000000000
+--- a/gas/testsuite/gas/riscv/march-fail-s.l
++++ /dev/null
+@@ -1,2 +0,0 @@
+-Assembler messages:
+-.*: Invalid or unknown s ISA extension: 'sfoo'
+diff --git a/gas/testsuite/gas/riscv/march-fail-single-char-s.d b/gas/testsuite/gas/riscv/march-fail-single-char-s.d
+new file mode 100644
+index 0000000000..b3aace9122
+--- /dev/null
++++ b/gas/testsuite/gas/riscv/march-fail-single-char-s.d
+@@ -0,0 +1,3 @@
++#as: -march=rv32is
++#source: empty.s
++#error_output: march-fail-single-char.l
+diff --git a/gas/testsuite/gas/riscv/march-fail-single-char-x.d b/gas/testsuite/gas/riscv/march-fail-single-char-x.d
+new file mode 100644
+index 0000000000..585608cb82
+--- /dev/null
++++ b/gas/testsuite/gas/riscv/march-fail-single-char-x.d
+@@ -0,0 +1,3 @@
++#as: -march=rv32ix
++#source: empty.s
++#error_output: march-fail-single-char.l
+diff --git a/gas/testsuite/gas/riscv/march-fail-single-char-z.d b/gas/testsuite/gas/riscv/march-fail-single-char-z.d
+new file mode 100644
+index 0000000000..daf96d2124
+--- /dev/null
++++ b/gas/testsuite/gas/riscv/march-fail-single-char-z.d
+@@ -0,0 +1,3 @@
++#as: -march=rv32iz
++#source: empty.s
++#error_output: march-fail-single-char.l
+diff --git a/gas/testsuite/gas/riscv/march-fail-single-char.l b/gas/testsuite/gas/riscv/march-fail-single-char.l
+new file mode 100644
+index 0000000000..aa87a8db1a
+--- /dev/null
++++ b/gas/testsuite/gas/riscv/march-fail-single-char.l
+@@ -0,0 +1,2 @@
++.*Assembler messages:
++.*Fatal error: .*unknown (s|z|x) ISA extension `(s|z|x)'
+diff --git a/gas/testsuite/gas/riscv/march-fail-sx.d b/gas/testsuite/gas/riscv/march-fail-sx.d
+deleted file mode 100644
+index 144a85c2fb..0000000000
+--- a/gas/testsuite/gas/riscv/march-fail-sx.d
++++ /dev/null
+@@ -1,6 +0,0 @@
+-#as: -march=rv32i_sxbar
+-#objdump: -dr
+-#source: empty.s
+-#error_output: march-fail-sx.l
+-
+-.*:     file format elf32-littleriscv
+diff --git a/gas/testsuite/gas/riscv/march-fail-sx.l b/gas/testsuite/gas/riscv/march-fail-sx.l
+deleted file mode 100644
+index b8ead71a3b..0000000000
+--- a/gas/testsuite/gas/riscv/march-fail-sx.l
++++ /dev/null
+@@ -1,2 +0,0 @@
+-Assembler messages:
+-.*: Invalid or unknown s ISA extension: 'sxbar'
+diff --git a/gas/testsuite/gas/riscv/march-fail-unknown-s.d b/gas/testsuite/gas/riscv/march-fail-unknown-s.d
+new file mode 100644
+index 0000000000..93be528db8
+--- /dev/null
++++ b/gas/testsuite/gas/riscv/march-fail-unknown-s.d
+@@ -0,0 +1,3 @@
++#as: -march=rv32isfoo2p0
++#source: empty.s
++#error_output: march-fail-unknown.l
+diff --git a/gas/testsuite/gas/riscv/march-fail-unknown-std.d b/gas/testsuite/gas/riscv/march-fail-unknown-std.d
+new file mode 100644
+index 0000000000..709c8f0971
+--- /dev/null
++++ b/gas/testsuite/gas/riscv/march-fail-unknown-std.d
+@@ -0,0 +1,3 @@
++#as: -march=rv32iy
++#source: empty.s
++#error_output: march-fail-unknown-std.l
+diff --git a/gas/testsuite/gas/riscv/march-fail-unknown-std.l b/gas/testsuite/gas/riscv/march-fail-unknown-std.l
+new file mode 100644
+index 0000000000..cb856377b3
+--- /dev/null
++++ b/gas/testsuite/gas/riscv/march-fail-unknown-std.l
+@@ -0,0 +1,2 @@
++.*Assembler messages:
++.*Fatal error: .*unknown standard ISA extension `[^eimafdqiglcbjtpvn]'
+diff --git a/gas/testsuite/gas/riscv/march-fail-unknown-z.d b/gas/testsuite/gas/riscv/march-fail-unknown-z.d
+new file mode 100644
+index 0000000000..6ea7c48c39
+--- /dev/null
++++ b/gas/testsuite/gas/riscv/march-fail-unknown-z.d
+@@ -0,0 +1,3 @@
++#as: -march=rv32izfoo2p0
++#source: empty.s
++#error_output: march-fail-unknown.l
+diff --git a/gas/testsuite/gas/riscv/march-fail-unknown.l b/gas/testsuite/gas/riscv/march-fail-unknown.l
+new file mode 100644
+index 0000000000..ac22fe60eb
+--- /dev/null
++++ b/gas/testsuite/gas/riscv/march-fail-unknown.l
+@@ -0,0 +1,2 @@
++.*Assembler messages:
++.*Fatal error: .*unknown (s|z) ISA extension `(s|z)foo'
+diff --git a/gas/testsuite/gas/riscv/march-fail-uppercase-base.d b/gas/testsuite/gas/riscv/march-fail-uppercase-base.d
+new file mode 100644
+index 0000000000..74b55ea165
+--- /dev/null
++++ b/gas/testsuite/gas/riscv/march-fail-uppercase-base.d
+@@ -0,0 +1,3 @@
++#as: -march=rv32I
++#source: empty.s
++#error_output: march-fail-base-01.l
+diff --git a/gas/testsuite/gas/riscv/march-fail-uppercase-std.d b/gas/testsuite/gas/riscv/march-fail-uppercase-std.d
+new file mode 100644
+index 0000000000..8bad1f9c3a
+--- /dev/null
++++ b/gas/testsuite/gas/riscv/march-fail-uppercase-std.d
+@@ -0,0 +1,3 @@
++#as: -march=rv32iC
++#source: empty.s
++#error_output: march-fail-uppercase.l
+diff --git a/gas/testsuite/gas/riscv/march-fail-uppercase-z.d b/gas/testsuite/gas/riscv/march-fail-uppercase-z.d
+new file mode 100644
+index 0000000000..951cc59a94
+--- /dev/null
++++ b/gas/testsuite/gas/riscv/march-fail-uppercase-z.d
+@@ -0,0 +1,3 @@
++#as: -march=rv32ic_ziCSR
++#source: empty.s
++#error_output: march-fail-uppercase.l
+diff --git a/gas/testsuite/gas/riscv/march-fail-uppercase.l b/gas/testsuite/gas/riscv/march-fail-uppercase.l
+new file mode 100644
+index 0000000000..2053135922
+--- /dev/null
++++ b/gas/testsuite/gas/riscv/march-fail-uppercase.l
+@@ -0,0 +1,2 @@
++.*Assembler messages:
++.*Fatal error: .*unknown (standard|z) ISA extension.*
+diff --git a/gas/testsuite/gas/riscv/march-fail-version-x.d b/gas/testsuite/gas/riscv/march-fail-version-x.d
+new file mode 100644
+index 0000000000..8e140e3d5f
+--- /dev/null
++++ b/gas/testsuite/gas/riscv/march-fail-version-x.d
+@@ -0,0 +1,3 @@
++#as: -march=rv32i2p_zicsr2p0_xargle2p
++#source: empty.s
++#error_output: march-fail-version.l
+diff --git a/gas/testsuite/gas/riscv/march-fail-version-z.d b/gas/testsuite/gas/riscv/march-fail-version-z.d
+new file mode 100644
+index 0000000000..73ca5794bf
+--- /dev/null
++++ b/gas/testsuite/gas/riscv/march-fail-version-z.d
+@@ -0,0 +1,3 @@
++#as: -march=rv32i2p_zicsr2p
++#source: empty.s
++#error_output: march-fail-version.l
+diff --git a/gas/testsuite/gas/riscv/march-fail-version.l b/gas/testsuite/gas/riscv/march-fail-version.l
+new file mode 100644
+index 0000000000..b5d0b91350
+--- /dev/null
++++ b/gas/testsuite/gas/riscv/march-fail-version.l
+@@ -0,0 +1,2 @@
++.*Assembler messages:
++.*Fatal error: .*expect number after `2p'
+-- 
+2.33.0
+

+ 83 - 0
recipes-devtools/gdb/files/0005-RISC-V-Don-t-allow-any-uppercase-letter-in-the-arch-.patch

@@ -0,0 +1,83 @@
+From 537d1469b43f7c60cbdd196727afd186951a1286 Mon Sep 17 00:00:00 2001
+From: Nelson Chu <nelson.chu@sifive.com>
+Date: Sat, 21 Nov 2020 11:19:58 +0800
+Subject: [PATCH 05/48] RISC-V: Don't allow any uppercase letter in the arch
+ string.
+
+Although I cannot find any RISC-V specs said that uppercases are not
+allowed in the arhc string, but seems like it is an established fact
+both for GNU and LLVM.  Therefore, we shouldn't allow the uppercases
+for the non-standard x extensions, too.
+
+	bfd/
+	* elfxx-riscv.c (riscv_parse_subset): ISA string cannot contain
+	any uppercase letter.
+
+	gas/
+	* testsuite/gas/riscv/march-fail-uppercase-base.d: Updated.
+	* testsuite/gas/riscv/march-fail-uppercase.l: Updated.
+	* testsuite/gas/riscv/march-fail-uppercase-x.d: New testcase.
+---
+ bfd/elfxx-riscv.c                                  | 14 +++++++++++++-
+ .../gas/riscv/march-fail-uppercase-base.d          |  2 +-
+ gas/testsuite/gas/riscv/march-fail-uppercase-x.d   |  3 +++
+ gas/testsuite/gas/riscv/march-fail-uppercase.l     |  2 +-
+ 4 files changed, 18 insertions(+), 3 deletions(-)
+ create mode 100644 gas/testsuite/gas/riscv/march-fail-uppercase-x.d
+
+diff --git a/bfd/elfxx-riscv.c b/bfd/elfxx-riscv.c
+index dc196e0e12..d29bb0375e 100644
+--- a/bfd/elfxx-riscv.c
++++ b/bfd/elfxx-riscv.c
+@@ -1495,9 +1495,21 @@ bfd_boolean
+ riscv_parse_subset (riscv_parse_subset_t *rps,
+ 		    const char *arch)
+ {
+-  const char *p = arch;
++  const char *p;
+   size_t i;
+ 
++  for (p = arch; *p != '\0'; p++)
++    {
++      if (ISUPPER (*p))
++	{
++	  rps->error_handler
++	    (_("-march=%s: ISA string cannot contain uppercase letters"),
++	     arch);
++	  return FALSE;
++	}
++    }
++
++  p = arch;
+   if (strncmp (p, "rv32", 4) == 0)
+     {
+       *rps->xlen = 32;
+diff --git a/gas/testsuite/gas/riscv/march-fail-uppercase-base.d b/gas/testsuite/gas/riscv/march-fail-uppercase-base.d
+index 74b55ea165..8b595856b4 100644
+--- a/gas/testsuite/gas/riscv/march-fail-uppercase-base.d
++++ b/gas/testsuite/gas/riscv/march-fail-uppercase-base.d
+@@ -1,3 +1,3 @@
+ #as: -march=rv32I
+ #source: empty.s
+-#error_output: march-fail-base-01.l
++#error_output: march-fail-uppercase.l
+diff --git a/gas/testsuite/gas/riscv/march-fail-uppercase-x.d b/gas/testsuite/gas/riscv/march-fail-uppercase-x.d
+new file mode 100644
+index 0000000000..316351fce8
+--- /dev/null
++++ b/gas/testsuite/gas/riscv/march-fail-uppercase-x.d
+@@ -0,0 +1,3 @@
++#as: -march=rv32ic_zicsr_xARGLE
++#source: empty.s
++#error_output: march-fail-uppercase.l
+diff --git a/gas/testsuite/gas/riscv/march-fail-uppercase.l b/gas/testsuite/gas/riscv/march-fail-uppercase.l
+index 2053135922..292c18adcc 100644
+--- a/gas/testsuite/gas/riscv/march-fail-uppercase.l
++++ b/gas/testsuite/gas/riscv/march-fail-uppercase.l
+@@ -1,2 +1,2 @@
+ .*Assembler messages:
+-.*Fatal error: .*unknown (standard|z) ISA extension.*
++.*Fatal error: .*ISA string cannot contain uppercase letters
+-- 
+2.33.0
+

+ 195 - 0
recipes-devtools/gdb/files/0006-RISC-V-Add-zifencei-and-prefixed-h-class-extensions.patch

@@ -0,0 +1,195 @@
+From a091f66f69e2f7b4c029c73edd2a031045a106d8 Mon Sep 17 00:00:00 2001
+From: Nelson Chu <nelson.chu@sifive.com>
+Date: Fri, 20 Nov 2020 15:35:17 +0800
+Subject: [PATCH 06/48] RISC-V: Add zifencei and prefixed h class extensions.
+
+	bfd/
+	* elfxx-riscv.c (riscv_parse_std_ext): Stop parsing standard
+	extensions when parsed h keyword.
+	(riscv_get_prefix_class): Support prefixed h class.
+	(riscv_std_h_ext_strtab): Likewise.
+	(riscv_ext_h_valid_p): Likewise.
+	(parse_config): Likewise.
+	(riscv_std_z_ext_strtab): Add zifencei.
+	* elfxx-riscv.h (riscv_isa_ext_class): Add RV_ISA_CLASS_H.
+
+	gas/
+	* testsuite/gas/riscv/march-fail-order-z.d: New testcase, check
+	orders of prefixed z extensions.
+	* testsuite/gas/riscv/march-fail-order-z.l: Likewise.
+	* testsuite/gas/riscv/march-fail-single-char-h.d: New testcase.
+	* testsuite/gas/riscv/march-fail-single-char.l: Updated.
+	* testsuite/gas/riscv/march-fail-unknown-h.d: New testcase.
+	* testsuite/gas/riscv/march-fail-unknown.l: Updated.
+
+	opcodes/
+	* riscv-opc.c (riscv_ext_version_table): Add zifencei.
+---
+ bfd/elfxx-riscv.c                             | 21 +++++++++++++++++--
+ bfd/elfxx-riscv.h                             |  1 +
+ gas/testsuite/gas/riscv/march-fail-order-z.d  |  3 +++
+ gas/testsuite/gas/riscv/march-fail-order-z.l  |  2 ++
+ .../gas/riscv/march-fail-single-char-h.d      |  3 +++
+ .../gas/riscv/march-fail-single-char.l        |  2 +-
+ .../gas/riscv/march-fail-unknown-h.d          |  3 +++
+ gas/testsuite/gas/riscv/march-fail-unknown.l  |  2 +-
+ opcodes/riscv-opc.c                           |  3 +++
+ 9 files changed, 36 insertions(+), 4 deletions(-)
+ create mode 100644 gas/testsuite/gas/riscv/march-fail-order-z.d
+ create mode 100644 gas/testsuite/gas/riscv/march-fail-order-z.l
+ create mode 100644 gas/testsuite/gas/riscv/march-fail-single-char-h.d
+ create mode 100644 gas/testsuite/gas/riscv/march-fail-unknown-h.d
+
+diff --git a/bfd/elfxx-riscv.c b/bfd/elfxx-riscv.c
+index d29bb0375e..5a95c5cb6c 100644
+--- a/bfd/elfxx-riscv.c
++++ b/bfd/elfxx-riscv.c
+@@ -1210,7 +1210,7 @@ riscv_parse_std_ext (riscv_parse_subset_t *rps,
+ 
+   while (p != NULL && *p != '\0')
+     {
+-      if (*p == 'x' || *p == 's' || *p == 'z')
++      if (*p == 'x' || *p == 's' || *p == 'h' || *p == 'z')
+ 	break;
+ 
+       if (*p == '_')
+@@ -1266,6 +1266,7 @@ riscv_get_prefix_class (const char *arch)
+   switch (*arch)
+     {
+     case 's': return RV_ISA_CLASS_S;
++    case 'h': return RV_ISA_CLASS_H;
+     case 'x': return RV_ISA_CLASS_X;
+     case 'z': return RV_ISA_CLASS_Z;
+     default: return RV_ISA_CLASS_UNKNOWN;
+@@ -1347,6 +1348,7 @@ riscv_parse_prefixed_ext (riscv_parse_subset_t *rps,
+       /* Check that the prefix extension is known.
+ 	 For 'x', anything goes but it cannot simply be 'x'.
+ 	 For 's', it must be known from a list and cannot simply be 's'.
++	 For 'h', it must be known from a list and cannot simply be 'h'.
+ 	 For 'z', it must be known from a list and cannot simply be 'z'.  */
+ 
+       /* Check that the extension name is well-formed.  */
+@@ -1417,7 +1419,7 @@ riscv_parse_prefixed_ext (riscv_parse_subset_t *rps,
+ 
+ static const char * const riscv_std_z_ext_strtab[] =
+ {
+-  "zicsr", NULL
++  "zicsr", "zifencei", NULL
+ };
+ 
+ static const char * const riscv_std_s_ext_strtab[] =
+@@ -1425,6 +1427,11 @@ static const char * const riscv_std_s_ext_strtab[] =
+   NULL
+ };
+ 
++static const char * const riscv_std_h_ext_strtab[] =
++{
++  NULL
++};
++
+ /* For the extension `ext`, search through the list of known extensions
+    `known_exts` for a match, and return TRUE if found.  */
+ 
+@@ -1471,12 +1478,22 @@ riscv_ext_s_valid_p (const char *arg)
+   return riscv_multi_letter_ext_valid_p (arg, riscv_std_s_ext_strtab);
+ }
+ 
++/* Predicator function for 'h' prefixed extensions.
++   Only known h-extensions are permitted.  */
++
++static bfd_boolean
++riscv_ext_h_valid_p (const char *arg)
++{
++  return riscv_multi_letter_ext_valid_p (arg, riscv_std_h_ext_strtab);
++}
++
+ /* Parsing order of the prefixed extensions that is specified by
+    the ISA spec.  */
+ 
+ static const riscv_parse_config_t parse_config[] =
+ {
+   {RV_ISA_CLASS_S, "s", riscv_ext_s_valid_p},
++  {RV_ISA_CLASS_H, "h", riscv_ext_h_valid_p},
+   {RV_ISA_CLASS_Z, "z", riscv_ext_z_valid_p},
+   {RV_ISA_CLASS_X, "x", riscv_ext_x_valid_p},
+   {RV_ISA_CLASS_UNKNOWN, NULL, NULL}
+diff --git a/bfd/elfxx-riscv.h b/bfd/elfxx-riscv.h
+index b5b17d1687..6b7cc5b0bf 100644
+--- a/bfd/elfxx-riscv.h
++++ b/bfd/elfxx-riscv.h
+@@ -102,6 +102,7 @@ riscv_estimate_digit (unsigned);
+ typedef enum riscv_isa_ext_class
+ {
+   RV_ISA_CLASS_S,
++  RV_ISA_CLASS_H,
+   RV_ISA_CLASS_Z,
+   RV_ISA_CLASS_X,
+   RV_ISA_CLASS_UNKNOWN
+diff --git a/gas/testsuite/gas/riscv/march-fail-order-z.d b/gas/testsuite/gas/riscv/march-fail-order-z.d
+new file mode 100644
+index 0000000000..dd076c6d35
+--- /dev/null
++++ b/gas/testsuite/gas/riscv/march-fail-order-z.d
+@@ -0,0 +1,3 @@
++#as: -march=rv32i_zifencei2p0_zicsr2p0
++#source: empty.s
++#error_output: march-fail-order-z.l
+diff --git a/gas/testsuite/gas/riscv/march-fail-order-z.l b/gas/testsuite/gas/riscv/march-fail-order-z.l
+new file mode 100644
+index 0000000000..1129219f2b
+--- /dev/null
++++ b/gas/testsuite/gas/riscv/march-fail-order-z.l
+@@ -0,0 +1,2 @@
++.*Assembler messages:
++.*Fatal error: .*z ISA extension `zicsr' is not in alphabetical order.  It must come before `zifencei'
+diff --git a/gas/testsuite/gas/riscv/march-fail-single-char-h.d b/gas/testsuite/gas/riscv/march-fail-single-char-h.d
+new file mode 100644
+index 0000000000..7fca9576bf
+--- /dev/null
++++ b/gas/testsuite/gas/riscv/march-fail-single-char-h.d
+@@ -0,0 +1,3 @@
++#as: -march=rv32ih
++#source: empty.s
++#error_output: march-fail-single-char.l
+diff --git a/gas/testsuite/gas/riscv/march-fail-single-char.l b/gas/testsuite/gas/riscv/march-fail-single-char.l
+index aa87a8db1a..6466e164ff 100644
+--- a/gas/testsuite/gas/riscv/march-fail-single-char.l
++++ b/gas/testsuite/gas/riscv/march-fail-single-char.l
+@@ -1,2 +1,2 @@
+ .*Assembler messages:
+-.*Fatal error: .*unknown (s|z|x) ISA extension `(s|z|x)'
++.*Fatal error: .*unknown (s|h|z|x) ISA extension `(s|h|z|x)'
+diff --git a/gas/testsuite/gas/riscv/march-fail-unknown-h.d b/gas/testsuite/gas/riscv/march-fail-unknown-h.d
+new file mode 100644
+index 0000000000..b0b83231aa
+--- /dev/null
++++ b/gas/testsuite/gas/riscv/march-fail-unknown-h.d
+@@ -0,0 +1,3 @@
++#as: -march=rv32ihfoo2p0
++#source: empty.s
++#error_output: march-fail-unknown.l
+diff --git a/gas/testsuite/gas/riscv/march-fail-unknown.l b/gas/testsuite/gas/riscv/march-fail-unknown.l
+index ac22fe60eb..28a864dbb7 100644
+--- a/gas/testsuite/gas/riscv/march-fail-unknown.l
++++ b/gas/testsuite/gas/riscv/march-fail-unknown.l
+@@ -1,2 +1,2 @@
+ .*Assembler messages:
+-.*Fatal error: .*unknown (s|z) ISA extension `(s|z)foo'
++.*Fatal error: .*unknown (s|h|z) ISA extension `(s|h|z)foo'
+diff --git a/opcodes/riscv-opc.c b/opcodes/riscv-opc.c
+index 03e3bd7c05..121f3fee41 100644
+--- a/opcodes/riscv-opc.c
++++ b/opcodes/riscv-opc.c
+@@ -935,6 +935,9 @@ const struct riscv_ext_version riscv_ext_version_table[] =
+ {"zicsr", ISA_SPEC_CLASS_20191213, 2, 0},
+ {"zicsr", ISA_SPEC_CLASS_20190608, 2, 0},
+ 
++{"zifencei", ISA_SPEC_CLASS_20191213, 2, 0},
++{"zifencei", ISA_SPEC_CLASS_20190608, 2, 0},
++
+ /* Terminate the list.  */
+ {NULL, 0, 0, 0}
+ };
+-- 
+2.33.0
+

+ 42 - 0
recipes-devtools/gdb/files/0007-RISC-V-Remove-the-unimplemented-extensions.patch

@@ -0,0 +1,42 @@
+From 5b9cc689d4ba988a2540ea7047f9b285eda3da5a Mon Sep 17 00:00:00 2001
+From: Nelson Chu <nelson.chu@sifive.com>
+Date: Fri, 20 Nov 2020 16:52:35 +0800
+Subject: [PATCH 07/48] RISC-V: Remove the unimplemented extensions.
+
+Although spec had defined and ratified p, v and n extensions,
+but we don't have any related implementaitons so far, so keep
+them in the supported extension table looks weird.  Remove them
+until we have the related implementations.
+
+	opcodes/
+	* riscv-opc.c (riscv_ext_version_table): Remove the p, v, n
+	and their versions.
+---
+ opcodes/riscv-opc.c | 11 -----------
+ 1 file changed, 11 deletions(-)
+
+diff --git a/opcodes/riscv-opc.c b/opcodes/riscv-opc.c
+index 121f3fee41..7ca44dc5b8 100644
+--- a/opcodes/riscv-opc.c
++++ b/opcodes/riscv-opc.c
+@@ -921,17 +921,6 @@ const struct riscv_ext_version riscv_ext_version_table[] =
+ {"c", ISA_SPEC_CLASS_20190608, 2, 0},
+ {"c", ISA_SPEC_CLASS_2P2,      2, 0},
+ 
+-{"p", ISA_SPEC_CLASS_20191213, 0, 2},
+-{"p", ISA_SPEC_CLASS_20190608, 0, 2},
+-{"p", ISA_SPEC_CLASS_2P2,      0, 1},
+-
+-{"v", ISA_SPEC_CLASS_20191213, 0, 7},
+-{"v", ISA_SPEC_CLASS_20190608, 0, 7},
+-{"v", ISA_SPEC_CLASS_2P2,      0, 7},
+-
+-{"n", ISA_SPEC_CLASS_20190608, 1, 1},
+-{"n", ISA_SPEC_CLASS_2P2,      1, 1},
+-
+ {"zicsr", ISA_SPEC_CLASS_20191213, 2, 0},
+ {"zicsr", ISA_SPEC_CLASS_20190608, 2, 0},
+ 
+-- 
+2.33.0
+

+ 864 - 0
recipes-devtools/gdb/files/0008-RISC-V-Improve-the-version-parsing-for-arch-string.patch

@@ -0,0 +1,864 @@
+From 5b427d5371e8b33f4cdbfae6d16f339ed94c521e Mon Sep 17 00:00:00 2001
+From: Nelson Chu <nelson.chu@sifive.com>
+Date: Fri, 20 Nov 2020 17:26:04 +0800
+Subject: [PATCH 08/48] RISC-V: Improve the version parsing for arch string.
+
+Keep the riscv_add_subset to do the same thing, and use a new
+function, riscv_parse_add_subset, to cover most of the things
+when parsing, including find the default versions for extensions,
+and check whether the versions are valid.  The version 0p0 should
+be an invalid version, that is the mistake I made before.  This
+patch clarify the version rules as follows,
+
+* We accept any version of extensions set by users, except 0p0.
+* The non-standard x extensions must be set with versions in arch string.
+* If user don't set the versions, or set 0p0 for the extensions, then try
+  to find the supported versions according to the chosen ISA spec.
+  Otherwise, report errors rather than output 0p0 for them.
+
+Besides, we use as_bad rather than as_fatal to report more errors
+for assembler.
+
+	bfd/
+	* elfxx-riscv.c (riscv_lookup_subset): Moved to front.
+	(riscv_add_subset): Likewise.
+	(riscv_release_subset_list): Likewise.
+	(riscv_parse_add_subset): New function.  Find and check the
+	versions before adding them by riscv_add_subset.
+	(riscv_parsing_subset_version): Remove use_default_version
+	and change the version type from unsigned to int.  Set the
+	versions to RISCV_UNKNOWN_VERSION if we can not find them
+	in the arch string.
+	(riscv_parse_std_ext): Updated.
+	(riscv_parse_prefixed_ext): Updated.  Since we use as_bad
+	rather than as_fatal to report more errors, return NULL
+	string if the parsed end_of_version is NULL, too.
+	(riscv_parse_subset): Use a new boolean, no_conflict, to
+	report more errors when we have more than one ISA conflicts.
+
+	* elfxx-riscv.h (RISCV_DONT_CARE_VERSION): Changed to
+	RISCV_UNKNOWN_VERSION.
+	(riscv_lookup_subset_version): Removed.
+	(riscv_parse_subset_t): Updated.
+
+	gas/
+	* config/tc-riscv.c (riscv_get_default_ext_version):
+	Change the version type from unsigned to int.
+	(riscv_set_arch): Use as_bad rather than as_fatal to
+	report more errors.
+
+	* testsuite/gas/riscv/attribute-02.d: Updated since x must be
+	set with versions.
+	* testsuite/gas/riscv/attribute-03.d: Likewise.
+	* testsuite/gas/riscv/march-ok-two-nse.d: Likewise.
+	* testsuite/gas/riscv/attribute-09.d: zicsr wasn't supported
+	in the spec 2.2, so choose the newer spec.
+	* testsuite/gas/riscv/march-fail-base-01.l: Updated since as_bad.
+	* testsuite/gas/riscv/march-fail-base-02.l: Likewise.
+	* testsuite/gas/riscv/march-fail-order-std.l: Likewise.
+	* testsuite/gas/riscv/march-fail-order-x.l: Likewise.
+	* testsuite/gas/riscv/march-fail-order-z.l: Likewise.
+	* testsuite/gas/riscv/march-fail-porder.l: Likewise.
+	* testsuite/gas/riscv/march-fail-rv32ef.l: Likewise.
+	* testsuite/gas/riscv/march-fail-rv32id.l: Likewise.
+	* testsuite/gas/riscv/march-fail-rv32iq.l: Likewise.
+	* testsuite/gas/riscv/march-fail-rv64iq.l: Likewise.
+	* testsuite/gas/riscv/march-fail-single-char.l: Likewise.
+	* testsuite/gas/riscv/march-fail-unknown-std.l: Likewise.
+	* testsuite/gas/riscv/march-fail-unknown.l: Likewise.
+	* testsuite/gas/riscv/march-fail-uppercase.l: Likewise.
+	* testsuite/gas/riscv/march-fail-version.l: Likewise.
+	* testsuite/gas/riscv/march-fail-isa-spec.d: Likewise.
+	* testsuite/gas/riscv/march-fail-isa-spec.l: Likewise.
+
+	include/
+	* opcode/riscv.h (riscv_ext_version):
+	Change the version type from unsigned to int.
+---
+ bfd/elfxx-riscv.c                             | 324 ++++++++----------
+ bfd/elfxx-riscv.h                             |  11 +-
+ gas/config/tc-riscv.c                         |  23 +-
+ gas/testsuite/gas/riscv/attribute-02.d        |   4 +-
+ gas/testsuite/gas/riscv/attribute-03.d        |   4 +-
+ gas/testsuite/gas/riscv/attribute-09.d        |   4 +-
+ gas/testsuite/gas/riscv/march-fail-base-01.l  |   2 +-
+ gas/testsuite/gas/riscv/march-fail-base-02.l  |   2 +-
+ gas/testsuite/gas/riscv/march-fail-isa-spec.d |   3 +
+ gas/testsuite/gas/riscv/march-fail-isa-spec.l |   5 +
+ .../gas/riscv/march-fail-order-std.l          |   2 +-
+ gas/testsuite/gas/riscv/march-fail-order-x.l  |   2 +-
+ gas/testsuite/gas/riscv/march-fail-order-z.l  |   2 +-
+ gas/testsuite/gas/riscv/march-fail-porder.l   |   2 +-
+ gas/testsuite/gas/riscv/march-fail-rv32ef.l   |   2 +-
+ gas/testsuite/gas/riscv/march-fail-rv32id.l   |   2 +-
+ gas/testsuite/gas/riscv/march-fail-rv32iq.l   |   3 +-
+ gas/testsuite/gas/riscv/march-fail-rv64iq.l   |   2 +-
+ .../gas/riscv/march-fail-single-char.l        |   2 +-
+ .../gas/riscv/march-fail-unknown-std.l        |   2 +-
+ gas/testsuite/gas/riscv/march-fail-unknown.l  |   2 +-
+ .../gas/riscv/march-fail-uppercase.l          |   2 +-
+ gas/testsuite/gas/riscv/march-fail-version.l  |   3 +-
+ gas/testsuite/gas/riscv/march-ok-two-nse.d    |   2 +-
+ include/opcode/riscv.h                        |   4 +-
+ 25 files changed, 193 insertions(+), 223 deletions(-)
+ create mode 100644 gas/testsuite/gas/riscv/march-fail-isa-spec.d
+ create mode 100644 gas/testsuite/gas/riscv/march-fail-isa-spec.l
+
+diff --git a/bfd/elfxx-riscv.c b/bfd/elfxx-riscv.c
+index 5a95c5cb6c..233f4e20d6 100644
+--- a/bfd/elfxx-riscv.c
++++ b/bfd/elfxx-riscv.c
+@@ -1010,6 +1010,96 @@ riscv_elf_add_sub_reloc (bfd *abfd,
+   return bfd_reloc_ok;
+ }
+ 
++/* Find subset in list, return NULL if not found.  */
++
++riscv_subset_t *
++riscv_lookup_subset (const riscv_subset_list_t *subset_list,
++		     const char *subset)
++{
++  riscv_subset_t *s;
++
++  for (s = subset_list->head; s != NULL; s = s->next)
++    if (strcasecmp (s->name, subset) == 0)
++      return s;
++
++  return NULL;
++}
++
++/* Add extension to the subset list.  */
++
++void
++riscv_add_subset (riscv_subset_list_t *subset_list,
++		  const char *subset,
++		  int major,
++		  int minor)
++{
++  riscv_subset_t *s = xmalloc (sizeof *s);
++
++  if (subset_list->head == NULL)
++    subset_list->head = s;
++
++  s->name = xstrdup (subset);
++  s->major_version = major;
++  s->minor_version = minor;
++  s->next = NULL;
++
++  if (subset_list->tail != NULL)
++    subset_list->tail->next = s;
++  subset_list->tail = s;
++}
++
++/* Find the default versions for the extension before adding them to
++   the subset list, if their versions are RISCV_UNKNOWN_VERSION.
++   Afterwards, report errors if we can not find their default versions.  */
++
++static void
++riscv_parse_add_subset (riscv_parse_subset_t *rps,
++			const char *subset,
++			int major,
++			int minor)
++{
++  int major_version = major;
++  int minor_version = minor;
++
++  if ((major_version == RISCV_UNKNOWN_VERSION
++       || minor_version == RISCV_UNKNOWN_VERSION)
++      && rps->get_default_version != NULL)
++    rps->get_default_version (subset, &major_version, &minor_version);
++
++  if (major_version == RISCV_UNKNOWN_VERSION
++      || minor_version == RISCV_UNKNOWN_VERSION)
++    {
++      if (subset[0] == 'x')
++	rps->error_handler
++	  (_("x ISA extension `%s' must be set with the versions"),
++	   subset);
++      else
++	rps->error_handler
++	  (_("cannot find default versions of the ISA extension `%s'"),
++	   subset);
++      return;
++    }
++
++  riscv_add_subset (rps->subset_list, subset,
++		    major_version, minor_version);
++}
++
++/* Release subset list.  */
++
++void
++riscv_release_subset_list (riscv_subset_list_t *subset_list)
++{
++   while (subset_list->head != NULL)
++    {
++      riscv_subset_t *next = subset_list->head->next;
++      free ((void *)subset_list->head->name);
++      free (subset_list->head);
++      subset_list->head = next;
++    }
++
++  subset_list->tail = NULL;
++}
++
+ /* Parsing extension version.
+ 
+    Return Value:
+@@ -1019,25 +1109,20 @@ riscv_elf_add_sub_reloc (bfd *abfd,
+      `rps`: Hooks and status for parsing extensions.
+      `march`: Full arch string.
+      `p`: Curent parsing position.
+-     `major_version`: Parsing result of major version, using
+-      default_major_version if version is not present in arch string.
+-     `minor_version`: Parsing result of minor version, set to 0 if version is
+-     not present in arch string, but set to `default_minor_version` if
+-     `major_version` using default_major_version.
+-     `std_ext_p`: True if parsing std extension.
+-     `use_default_version`: Set it to True if we need the default version.  */
++     `major_version`: Parsed major version.
++     `minor_version`: Parsed minor version.
++     `std_ext_p`: True if parsing standard extension.  */
+ 
+ static const char *
+ riscv_parsing_subset_version (riscv_parse_subset_t *rps,
+ 			      const char *march,
+ 			      const char *p,
+-			      unsigned *major_version,
+-			      unsigned *minor_version,
+-			      bfd_boolean std_ext_p,
+-			      bfd_boolean *use_default_version)
++			      int *major_version,
++			      int *minor_version,
++			      bfd_boolean std_ext_p)
+ {
+   bfd_boolean major_p = TRUE;
+-  unsigned version = 0;
++  int version = 0;
+   char np;
+ 
+   *major_version = 0;
+@@ -1081,11 +1166,13 @@ riscv_parsing_subset_version (riscv_parse_subset_t *rps,
+   else
+     *minor_version = version;
+ 
+-  /* We can not find any version in string, need to parse default version.  */
+-  if (use_default_version != NULL
+-      && *major_version == 0
+-      && *minor_version == 0)
+-    *use_default_version = TRUE;
++  /* We can not find any version in string.  */
++  if (*major_version == 0 && *minor_version == 0)
++    {
++      *major_version = RISCV_UNKNOWN_VERSION;
++      *minor_version = RISCV_UNKNOWN_VERSION;
++    }
++
+   return p;
+ }
+ 
+@@ -1115,9 +1202,8 @@ riscv_parse_std_ext (riscv_parse_subset_t *rps,
+ {
+   const char *all_std_exts = riscv_supported_std_ext ();
+   const char *std_exts = all_std_exts;
+-  unsigned major_version = 0;
+-  unsigned minor_version = 0;
+-  bfd_boolean use_default_version = FALSE;
++  int major_version;
++  int minor_version;
+   char subset[2] = {0, 0};
+ 
+   /* First letter must start with i, e or g.  */
+@@ -1126,42 +1212,23 @@ riscv_parse_std_ext (riscv_parse_subset_t *rps,
+       case 'i':
+ 	p = riscv_parsing_subset_version (rps, march, ++p,
+ 					  &major_version,
+-					  &minor_version, TRUE,
+-					  &use_default_version);
+-	/* Find the default version if needed.  */
+-	if (use_default_version
+-	    && rps->get_default_version != NULL)
+-	  rps->get_default_version ("i",
+-				    &major_version,
+-				    &minor_version);
+-	riscv_add_subset (rps->subset_list, "i",
+-			  major_version,
+-			  minor_version);
++					  &minor_version, TRUE);
++	riscv_parse_add_subset (rps, "i",
++				major_version,
++				minor_version);
+ 	break;
+ 
+       case 'e':
+ 	p = riscv_parsing_subset_version (rps, march, ++p,
+ 					  &major_version,
+-					  &minor_version, TRUE,
+-					  &use_default_version);
+-	/* Find the default version if needed.  */
+-	if (use_default_version
+-	    && rps->get_default_version != NULL)
+-	  rps->get_default_version ("e",
+-				    &major_version,
+-				    &minor_version);
+-	riscv_add_subset (rps->subset_list, "e",
+-			  major_version,
+-			  minor_version);
+-
++					  &minor_version, TRUE);
++	riscv_parse_add_subset (rps, "e",
++				major_version,
++				minor_version);
+ 	/* i-ext must be enabled.  */
+-	if (rps->get_default_version != NULL)
+-	  rps->get_default_version ("i",
+-				    &major_version,
+-				    &minor_version);
+-	riscv_add_subset (rps->subset_list, "i",
+-			  major_version,
+-			  minor_version);
++	riscv_parse_add_subset (rps, "i",
++				RISCV_UNKNOWN_VERSION,
++				RISCV_UNKNOWN_VERSION);
+ 
+ 	if (*rps->xlen > 32)
+ 	  {
+@@ -1177,27 +1244,17 @@ riscv_parse_std_ext (riscv_parse_subset_t *rps,
+ 	   skip the setting if user set a version to it.  */
+ 	p = riscv_parsing_subset_version (rps, march, ++p,
+ 					  &major_version,
+-					  &minor_version, TRUE,
+-					  &use_default_version);
++					  &minor_version, TRUE);
+ 	/* i-ext must be enabled.  */
+-	if (rps->get_default_version != NULL)
+-	  rps->get_default_version ("i",
+-				    &major_version,
+-				    &minor_version);
+-	riscv_add_subset (rps->subset_list, "i",
+-			  major_version,
+-			  minor_version);
+-
++	riscv_parse_add_subset (rps, "i",
++				RISCV_UNKNOWN_VERSION,
++				RISCV_UNKNOWN_VERSION);
+ 	for ( ; *std_exts != 'q'; std_exts++)
+ 	  {
+ 	    subset[0] = *std_exts;
+-	    if (rps->get_default_version != NULL)
+-	      rps->get_default_version (subset,
+-					&major_version,
+-					&minor_version);
+-	    riscv_add_subset (rps->subset_list, subset,
+-			      major_version,
+-			      minor_version);
++	    riscv_parse_add_subset (rps, subset,
++				    RISCV_UNKNOWN_VERSION,
++				    RISCV_UNKNOWN_VERSION);
+ 	  }
+ 	break;
+ 
+@@ -1238,21 +1295,13 @@ riscv_parse_std_ext (riscv_parse_subset_t *rps,
+ 	}
+ 
+       std_exts++;
+-      use_default_version = FALSE;
+       subset[0] = std_ext;
+       p = riscv_parsing_subset_version (rps, march, ++p,
+ 					&major_version,
+-					&minor_version, TRUE,
+-					&use_default_version);
+-      /* Find the default version if needed.  */
+-      if (use_default_version
+-	  && rps->get_default_version != NULL)
+-	rps->get_default_version (subset,
+-				  &major_version,
+-				  &minor_version);
+-      riscv_add_subset (rps->subset_list, subset,
+-			major_version,
+-			minor_version);
++					&minor_version, TRUE);
++      riscv_parse_add_subset (rps, subset,
++			      major_version,
++			      minor_version);
+     }
+ 
+   return p;
+@@ -1309,11 +1358,10 @@ riscv_parse_prefixed_ext (riscv_parse_subset_t *rps,
+ 			  const char *p,
+ 			  const riscv_parse_config_t *config)
+ {
+-  unsigned major_version = 0;
+-  unsigned minor_version = 0;
++  int major_version;
++  int minor_version;
+   const char *last_name;
+   riscv_isa_ext_class_t class;
+-  bfd_boolean use_default_version;
+ 
+   while (*p)
+     {
+@@ -1337,14 +1385,18 @@ riscv_parse_prefixed_ext (riscv_parse_subset_t *rps,
+       while (*++q != '\0' && *q != '_' && !ISDIGIT (*q))
+ 	;
+ 
+-      use_default_version = FALSE;
+       end_of_version =
+ 	riscv_parsing_subset_version (rps, march, q,
+ 				      &major_version,
+-				      &minor_version, FALSE,
+-				      &use_default_version);
++				      &minor_version, FALSE);
+       *q = '\0';
+ 
++      if (end_of_version == NULL)
++	{
++	  free (subset);
++	  return NULL;
++	}
++
+       /* Check that the prefix extension is known.
+ 	 For 'x', anything goes but it cannot simply be 'x'.
+ 	 For 's', it must be known from a list and cannot simply be 's'.
+@@ -1384,16 +1436,9 @@ riscv_parse_prefixed_ext (riscv_parse_subset_t *rps,
+ 	  return NULL;
+ 	}
+ 
+-      /* Find the default version if needed.  */
+-      if (use_default_version
+-         && rps->get_default_version != NULL)
+-       rps->get_default_version (subset,
+-                                 &major_version,
+-                                 &minor_version);
+-      riscv_add_subset (rps->subset_list, subset,
+-			major_version,
+-			minor_version);
+-
++      riscv_parse_add_subset (rps, subset,
++			      major_version,
++			      minor_version);
+       free (subset);
+       p += end_of_version - subset;
+ 
+@@ -1514,6 +1559,7 @@ riscv_parse_subset (riscv_parse_subset_t *rps,
+ {
+   const char *p;
+   size_t i;
++  bfd_boolean no_conflict = TRUE;
+ 
+   for (p = arch; *p != '\0'; p++)
+     {
+@@ -1580,7 +1626,7 @@ riscv_parse_subset (riscv_parse_subset_t *rps,
+       rps->error_handler
+ 	(_("-march=%s: rv32e does not support the `f' extension"),
+ 	 arch);
+-      return FALSE;
++      no_conflict = FALSE;
+     }
+ 
+   if (riscv_lookup_subset (rps->subset_list, "q") && *rps->xlen < 64)
+@@ -1588,7 +1634,7 @@ riscv_parse_subset (riscv_parse_subset_t *rps,
+       rps->error_handler
+ 	(_("-march=%s: rv32 does not support the `q' extension"),
+ 	 arch);
+-      return FALSE;
++      no_conflict = FALSE;
+     }
+ 
+   if (riscv_lookup_subset (rps->subset_list, "d")
+@@ -1597,7 +1643,7 @@ riscv_parse_subset (riscv_parse_subset_t *rps,
+       rps->error_handler
+ 	(_("-march=%s: `d' extension requires `f' extension"),
+ 	 arch);
+-      return FALSE;
++      no_conflict = FALSE;
+     }
+ 
+   if (riscv_lookup_subset (rps->subset_list, "q")
+@@ -1606,88 +1652,10 @@ riscv_parse_subset (riscv_parse_subset_t *rps,
+       rps->error_handler
+ 	(_("-march=%s: `q' extension requires `d' extension"),
+ 	 arch);
+-      return FALSE;
+-    }
+-
+-  return TRUE;
+-}
+-
+-/* Add new subset to list.  */
+-
+-void
+-riscv_add_subset (riscv_subset_list_t *subset_list,
+-		  const char *subset,
+-		  int major,
+-		  int minor)
+-{
+-  riscv_subset_t *s = xmalloc (sizeof *s);
+-
+-  if (subset_list->head == NULL)
+-    subset_list->head = s;
+-
+-  s->name = xstrdup (subset);
+-  s->major_version = major;
+-  s->minor_version = minor;
+-  s->next = NULL;
+-
+-  if (subset_list->tail != NULL)
+-    subset_list->tail->next = s;
+-
+-  subset_list->tail = s;
+-}
+-
+-/* Find subset in list without version checking, return NULL if not found.  */
+-
+-riscv_subset_t *
+-riscv_lookup_subset (const riscv_subset_list_t *subset_list,
+-		     const char *subset)
+-{
+-  return riscv_lookup_subset_version
+-    (subset_list, subset,
+-     RISCV_DONT_CARE_VERSION,
+-     RISCV_DONT_CARE_VERSION);
+-}
+-
+-/* Find subset in list with version checking, return NULL if not found.  */
+-
+-riscv_subset_t *
+-riscv_lookup_subset_version (const riscv_subset_list_t *subset_list,
+-			     const char *subset,
+-			     int major, int minor)
+-{
+-  riscv_subset_t *s;
+-
+-  for (s = subset_list->head; s != NULL; s = s->next)
+-    if (strcasecmp (s->name, subset) == 0)
+-      {
+-	if ((major != RISCV_DONT_CARE_VERSION)
+-	    && (s->major_version != major))
+-	  return NULL;
+-
+-	if ((minor != RISCV_DONT_CARE_VERSION)
+-	    && (s->minor_version != minor))
+-	  return NULL;
+-
+-	return s;
+-      }
+-
+-  return NULL;
+-}
+-
+-/* Release subset list.  */
+-
+-void
+-riscv_release_subset_list (riscv_subset_list_t *subset_list)
+-{
+-   while (subset_list->head != NULL)
+-    {
+-      riscv_subset_t *next = subset_list->head->next;
+-      free ((void *)subset_list->head->name);
+-      free (subset_list->head);
+-      subset_list->head = next;
++      no_conflict = FALSE;
+     }
+ 
+-  subset_list->tail = NULL;
++  return no_conflict;
+ }
+ 
+ /* Return the number of digits for the input.  */
+diff --git a/bfd/elfxx-riscv.h b/bfd/elfxx-riscv.h
+index 6b7cc5b0bf..45705ce31c 100644
+--- a/bfd/elfxx-riscv.h
++++ b/bfd/elfxx-riscv.h
+@@ -33,7 +33,7 @@ riscv_reloc_type_lookup (bfd *, bfd_reloc_code_real_type);
+ extern reloc_howto_type *
+ riscv_elf_rtype_to_howto (bfd *, unsigned int r_type);
+ 
+-#define RISCV_DONT_CARE_VERSION -1
++#define RISCV_UNKNOWN_VERSION -1
+ 
+ /* The information of architecture attribute.  */
+ struct riscv_subset_t
+@@ -64,11 +64,6 @@ extern riscv_subset_t *
+ riscv_lookup_subset (const riscv_subset_list_t *,
+ 		     const char *);
+ 
+-extern riscv_subset_t *
+-riscv_lookup_subset_version (const riscv_subset_list_t *,
+-			     const char *,
+-			     int, int);
+-
+ typedef struct
+ {
+   riscv_subset_list_t *subset_list;
+@@ -76,8 +71,8 @@ typedef struct
+ 			 ...) ATTRIBUTE_PRINTF_1;
+   unsigned *xlen;
+   void (*get_default_version) (const char *,
+-			       unsigned int *,
+-			       unsigned int *);
++			       int *,
++			       int *);
+ } riscv_parse_subset_t;
+ 
+ extern bfd_boolean
+diff --git a/gas/config/tc-riscv.c b/gas/config/tc-riscv.c
+index 9df6d3f415..24771b0a0b 100644
+--- a/gas/config/tc-riscv.c
++++ b/gas/config/tc-riscv.c
+@@ -267,28 +267,25 @@ init_ext_version_hash (const struct riscv_ext_version *table)
+ 
+ static void
+ riscv_get_default_ext_version (const char *name,
+-                              unsigned int *major_version,
+-                              unsigned int *minor_version)
++			       int *major_version,
++			       int *minor_version)
+ {
+   struct riscv_ext_version *ext;
+ 
+-  *major_version = 0;
+-  *minor_version = 0;
+-
+   if (name == NULL || default_isa_spec == ISA_SPEC_CLASS_NONE)
+     return;
+ 
+   ext = (struct riscv_ext_version *) str_hash_find (ext_version_hash, name);
+   while (ext
+-        && ext->name
+-        && strcmp (ext->name, name) == 0)
++	 && ext->name
++	 && strcmp (ext->name, name) == 0)
+     {
+       if (ext->isa_spec_class == default_isa_spec)
+-       {
+-         *major_version = ext->major_version;
+-         *minor_version = ext->minor_version;
+-         return;
+-       }
++	{
++	  *major_version = ext->major_version;
++	  *minor_version = ext->minor_version;
++	  return;
++	}
+       ext++;
+     }
+ }
+@@ -300,7 +297,7 @@ riscv_set_arch (const char *s)
+ {
+   riscv_parse_subset_t rps;
+   rps.subset_list = &riscv_subsets;
+-  rps.error_handler = as_fatal;
++  rps.error_handler = as_bad;
+   rps.xlen = &xlen;
+   rps.get_default_version = riscv_get_default_ext_version;
+ 
+diff --git a/gas/testsuite/gas/riscv/attribute-02.d b/gas/testsuite/gas/riscv/attribute-02.d
+index ae0195e9a2..45b89f2d62 100644
+--- a/gas/testsuite/gas/riscv/attribute-02.d
++++ b/gas/testsuite/gas/riscv/attribute-02.d
+@@ -1,6 +1,6 @@
+-#as: -march=rv32gxargle -march-attr -misa-spec=2.2
++#as: -march=rv32gxargle2p0 -march-attr -misa-spec=2.2
+ #readelf: -A
+ #source: empty.s
+ Attribute Section: riscv
+ File Attributes
+-  Tag_RISCV_arch: "rv32i2p0_m2p0_a2p0_f2p0_d2p0_xargle0p0"
++  Tag_RISCV_arch: "rv32i2p0_m2p0_a2p0_f2p0_d2p0_xargle2p0"
+diff --git a/gas/testsuite/gas/riscv/attribute-03.d b/gas/testsuite/gas/riscv/attribute-03.d
+index 9916ff6e92..11416d63d2 100644
+--- a/gas/testsuite/gas/riscv/attribute-03.d
++++ b/gas/testsuite/gas/riscv/attribute-03.d
+@@ -1,6 +1,6 @@
+-#as: -march=rv32gxargle_xfoo -march-attr -misa-spec=2.2
++#as: -march=rv32gxargle2p0_xfoo3p0 -march-attr -misa-spec=2.2
+ #readelf: -A
+ #source: empty.s
+ Attribute Section: riscv
+ File Attributes
+-  Tag_RISCV_arch: "rv32i2p0_m2p0_a2p0_f2p0_d2p0_xargle0p0_xfoo0p0"
++  Tag_RISCV_arch: "rv32i2p0_m2p0_a2p0_f2p0_d2p0_xargle2p0_xfoo3p0"
+diff --git a/gas/testsuite/gas/riscv/attribute-09.d b/gas/testsuite/gas/riscv/attribute-09.d
+index cad1713b0a..fc87f82c55 100644
+--- a/gas/testsuite/gas/riscv/attribute-09.d
++++ b/gas/testsuite/gas/riscv/attribute-09.d
+@@ -1,6 +1,6 @@
+-#as: -march-attr -march=rv32i2p1m_zicsr -misa-spec=2.2
++#as: -march-attr -march=rv32i2p2m_zicsr -misa-spec=20191213
+ #readelf: -A
+ #source: empty.s
+ Attribute Section: riscv
+ File Attributes
+-  Tag_RISCV_arch: "rv32i2p1_m2p0_zicsr0p0"
++  Tag_RISCV_arch: "rv32i2p2_m2p0_zicsr2p0"
+diff --git a/gas/testsuite/gas/riscv/march-fail-base-01.l b/gas/testsuite/gas/riscv/march-fail-base-01.l
+index 9fa071f5b0..45d5c9ad98 100644
+--- a/gas/testsuite/gas/riscv/march-fail-base-01.l
++++ b/gas/testsuite/gas/riscv/march-fail-base-01.l
+@@ -1,2 +1,2 @@
+ .*Assembler messages:
+-.*Fatal error: .*first ISA extension must be `e', `i' or `g'
++.*Error: .*first ISA extension must be `e', `i' or `g'
+diff --git a/gas/testsuite/gas/riscv/march-fail-base-02.l b/gas/testsuite/gas/riscv/march-fail-base-02.l
+index 6fc4dfa7ba..f6a3c1dc51 100644
+--- a/gas/testsuite/gas/riscv/march-fail-base-02.l
++++ b/gas/testsuite/gas/riscv/march-fail-base-02.l
+@@ -1,2 +1,2 @@
+ .*Assembler messages:
+-.*Fatal error: .*rv64e is not a valid base ISA
++.*Error: .*rv64e is not a valid base ISA
+diff --git a/gas/testsuite/gas/riscv/march-fail-isa-spec.d b/gas/testsuite/gas/riscv/march-fail-isa-spec.d
+new file mode 100644
+index 0000000000..af707e232e
+--- /dev/null
++++ b/gas/testsuite/gas/riscv/march-fail-isa-spec.d
+@@ -0,0 +1,3 @@
++#as: -march=rv32iln_zicsr_xargle_xbargle -misa-spec=20191213
++#source: empty.s
++#error_output: march-fail-isa-spec.l
+diff --git a/gas/testsuite/gas/riscv/march-fail-isa-spec.l b/gas/testsuite/gas/riscv/march-fail-isa-spec.l
+new file mode 100644
+index 0000000000..e714ddf7ba
+--- /dev/null
++++ b/gas/testsuite/gas/riscv/march-fail-isa-spec.l
+@@ -0,0 +1,5 @@
++.*Assembler messages:
++.*Error: cannot find default versions of the ISA extension `l'
++.*Error: cannot find default versions of the ISA extension `n'
++.*Error: x ISA extension `xargle' must be set with the versions
++.*Error: x ISA extension `xbargle' must be set with the versions
+diff --git a/gas/testsuite/gas/riscv/march-fail-order-std.l b/gas/testsuite/gas/riscv/march-fail-order-std.l
+index 666a8c0d2c..9e3ce5e8d9 100644
+--- a/gas/testsuite/gas/riscv/march-fail-order-std.l
++++ b/gas/testsuite/gas/riscv/march-fail-order-std.l
+@@ -1,2 +1,2 @@
+ .*Assembler messages:
+-.*Fatal error: .*standard ISA extension `m' is not in canonical order
++.*Error: .*standard ISA extension `m' is not in canonical order
+diff --git a/gas/testsuite/gas/riscv/march-fail-order-x.l b/gas/testsuite/gas/riscv/march-fail-order-x.l
+index f7b383d855..025db14686 100644
+--- a/gas/testsuite/gas/riscv/march-fail-order-x.l
++++ b/gas/testsuite/gas/riscv/march-fail-order-x.l
+@@ -1,2 +1,2 @@
+ .*Assembler messages:
+-.*Fatal error: .*x ISA extension `xargle' is not in alphabetical order.  It must come before `xbargle'
++.*Error: .*x ISA extension `xargle' is not in alphabetical order.  It must come before `xbargle'
+diff --git a/gas/testsuite/gas/riscv/march-fail-order-z.l b/gas/testsuite/gas/riscv/march-fail-order-z.l
+index 1129219f2b..a98c53a279 100644
+--- a/gas/testsuite/gas/riscv/march-fail-order-z.l
++++ b/gas/testsuite/gas/riscv/march-fail-order-z.l
+@@ -1,2 +1,2 @@
+ .*Assembler messages:
+-.*Fatal error: .*z ISA extension `zicsr' is not in alphabetical order.  It must come before `zifencei'
++.*Error: .*z ISA extension `zicsr' is not in alphabetical order.  It must come before `zifencei'
+diff --git a/gas/testsuite/gas/riscv/march-fail-porder.l b/gas/testsuite/gas/riscv/march-fail-porder.l
+index a06d586580..c5496eab49 100644
+--- a/gas/testsuite/gas/riscv/march-fail-porder.l
++++ b/gas/testsuite/gas/riscv/march-fail-porder.l
+@@ -1,2 +1,2 @@
+ .*Assembler messages:
+-.*Fatal error: .*unexpected ISA string at end:.*
++.*Error: .*unexpected ISA string at end:.*
+diff --git a/gas/testsuite/gas/riscv/march-fail-rv32ef.l b/gas/testsuite/gas/riscv/march-fail-rv32ef.l
+index d2d915d872..e6d93f28fa 100644
+--- a/gas/testsuite/gas/riscv/march-fail-rv32ef.l
++++ b/gas/testsuite/gas/riscv/march-fail-rv32ef.l
+@@ -1,2 +1,2 @@
+ .*Assembler messages:
+-.*Fatal error: .*rv32e does not support the `f' extension
++.*Error: .*rv32e does not support the `f' extension
+diff --git a/gas/testsuite/gas/riscv/march-fail-rv32id.l b/gas/testsuite/gas/riscv/march-fail-rv32id.l
+index 29b2717ef7..c5f990cd73 100644
+--- a/gas/testsuite/gas/riscv/march-fail-rv32id.l
++++ b/gas/testsuite/gas/riscv/march-fail-rv32id.l
+@@ -1,2 +1,2 @@
+ .*Assembler messages:
+-.*Fatal error: .*`d' extension requires `f' extension
++.*Error: .*`d' extension requires `f' extension
+diff --git a/gas/testsuite/gas/riscv/march-fail-rv32iq.l b/gas/testsuite/gas/riscv/march-fail-rv32iq.l
+index 361c381b86..8143dd441d 100644
+--- a/gas/testsuite/gas/riscv/march-fail-rv32iq.l
++++ b/gas/testsuite/gas/riscv/march-fail-rv32iq.l
+@@ -1,2 +1,3 @@
+ .*Assembler messages:
+-.*Fatal error: .*rv32 does not support the `q' extension
++.*Error: .*rv32 does not support the `q' extension
++.*Error: .*`q' extension requires `d' extension
+diff --git a/gas/testsuite/gas/riscv/march-fail-rv64iq.l b/gas/testsuite/gas/riscv/march-fail-rv64iq.l
+index 76a41043e3..787f46d1ed 100644
+--- a/gas/testsuite/gas/riscv/march-fail-rv64iq.l
++++ b/gas/testsuite/gas/riscv/march-fail-rv64iq.l
+@@ -1,2 +1,2 @@
+ .*Assembler messages:
+-.*Fatal error: .*`q' extension requires `d' extension
++.*Error: .*`q' extension requires `d' extension
+diff --git a/gas/testsuite/gas/riscv/march-fail-single-char.l b/gas/testsuite/gas/riscv/march-fail-single-char.l
+index 6466e164ff..435d0b23a4 100644
+--- a/gas/testsuite/gas/riscv/march-fail-single-char.l
++++ b/gas/testsuite/gas/riscv/march-fail-single-char.l
+@@ -1,2 +1,2 @@
+ .*Assembler messages:
+-.*Fatal error: .*unknown (s|h|z|x) ISA extension `(s|h|z|x)'
++.*Error: .*unknown (s|h|z|x) ISA extension `(s|h|z|x)'
+diff --git a/gas/testsuite/gas/riscv/march-fail-unknown-std.l b/gas/testsuite/gas/riscv/march-fail-unknown-std.l
+index cb856377b3..75cdda3894 100644
+--- a/gas/testsuite/gas/riscv/march-fail-unknown-std.l
++++ b/gas/testsuite/gas/riscv/march-fail-unknown-std.l
+@@ -1,2 +1,2 @@
+ .*Assembler messages:
+-.*Fatal error: .*unknown standard ISA extension `[^eimafdqiglcbjtpvn]'
++.*Error: .*unknown standard ISA extension `[^eimafdqiglcbjtpvn]'
+diff --git a/gas/testsuite/gas/riscv/march-fail-unknown.l b/gas/testsuite/gas/riscv/march-fail-unknown.l
+index 28a864dbb7..874b8d461b 100644
+--- a/gas/testsuite/gas/riscv/march-fail-unknown.l
++++ b/gas/testsuite/gas/riscv/march-fail-unknown.l
+@@ -1,2 +1,2 @@
+ .*Assembler messages:
+-.*Fatal error: .*unknown (s|h|z) ISA extension `(s|h|z)foo'
++.*Error: .*unknown (s|h|z) ISA extension `(s|h|z)foo'
+diff --git a/gas/testsuite/gas/riscv/march-fail-uppercase.l b/gas/testsuite/gas/riscv/march-fail-uppercase.l
+index 292c18adcc..14f03d6954 100644
+--- a/gas/testsuite/gas/riscv/march-fail-uppercase.l
++++ b/gas/testsuite/gas/riscv/march-fail-uppercase.l
+@@ -1,2 +1,2 @@
+ .*Assembler messages:
+-.*Fatal error: .*ISA string cannot contain uppercase letters
++.*Error: .*ISA string cannot contain uppercase letters
+diff --git a/gas/testsuite/gas/riscv/march-fail-version.l b/gas/testsuite/gas/riscv/march-fail-version.l
+index b5d0b91350..c7f8a4d548 100644
+--- a/gas/testsuite/gas/riscv/march-fail-version.l
++++ b/gas/testsuite/gas/riscv/march-fail-version.l
+@@ -1,2 +1,3 @@
+ .*Assembler messages:
+-.*Fatal error: .*expect number after `2p'
++.*Error: cannot find default versions of the ISA extension `p'
++.*Error: .*expect number after `2p'
+diff --git a/gas/testsuite/gas/riscv/march-ok-two-nse.d b/gas/testsuite/gas/riscv/march-ok-two-nse.d
+index 0fe503793b..e78cf9dd09 100644
+--- a/gas/testsuite/gas/riscv/march-ok-two-nse.d
++++ b/gas/testsuite/gas/riscv/march-ok-two-nse.d
+@@ -1,4 +1,4 @@
+-#as: -march=rv32imafd_xargle_xbargle
++#as: -march=rv32imafd_xargle2p0_xbargle3p0
+ #objdump: -dr
+ #source: empty.s
+ 
+diff --git a/include/opcode/riscv.h b/include/opcode/riscv.h
+index 2f1bc793e5..94a13803d9 100644
+--- a/include/opcode/riscv.h
++++ b/include/opcode/riscv.h
+@@ -360,8 +360,8 @@ struct riscv_ext_version
+ {
+   const char *name;
+   enum riscv_isa_spec_class isa_spec_class;
+-  unsigned int major_version;
+-  unsigned int minor_version;
++  int major_version;
++  int minor_version;
+ };
+ 
+ /* All RISC-V CSR belong to one of these classes.  */
+-- 
+2.33.0
+

+ 663 - 0
recipes-devtools/gdb/files/0009-RISC-V-Support-to-add-implicit-extensions.patch

@@ -0,0 +1,663 @@
+From 0249aa42c5267cdaeeaf5a26dbc2e7e54dd71b96 Mon Sep 17 00:00:00 2001
+From: Nelson Chu <nelson.chu@sifive.com>
+Date: Fri, 20 Nov 2020 18:05:05 +0800
+Subject: [PATCH 09/48] RISC-V: Support to add implicit extensions.
+
+We have to parse and add all arch string extensions at first, and then
+start to add their implicit extensions.  That means we can always add
+arch string extensions at the end of the subset list, but we need to
+search the right place to add their implicit extensions.  For now we
+follow the following rules to add the implicit extensions,
+
+* Add zicsr and zifencei only when the i's version less than 2.1.
+* Add d, f and zicsr when q is found.
+* Add f and zicsr when d is found.
+* Add zicsr when f is found.
+
+Besides, we do not add the implicit extensions if they are already added
+in the subset list, or we cannot find their default versions according to
+the chosen ISA spec.
+
+	bfd/
+	* elfnn-riscv.c (riscv_merge_std_ext): Updated since
+	riscv_lookup_subset is changed.
+	* elfxx-riscv.c (riscv_ext_order): New Array used to compare the
+	extensions' order quickly.
+	(riscv_init_ext_order): New function.  Init the riscv_ext_order
+	according to the riscv_supported_std_ext and parse_config[i].class
+	automatically.
+	(riscv_compare_subsets): New function.  Similar to the strcmp, but
+	compare the subsets with the specific order.
+	(riscv_lookup_subset): Return TRUE and set `current` to the subset
+	if it is found.  Otherwise, return FALSE and set `current` to the
+	place where we should insert the subset.
+	(riscv_add_implicit_subset): New function.  Search the list first,
+	and then find the right place to add the implicit_subset.
+	(riscv_parse_add_subset): Since We have to add all arch string
+	extensions first, and then start to add their implicit extensions.
+	We can add arch string extensions in order by the original
+	riscv_add_subset, and then add the implicit subsets by the
+	riscv_add_implicit_subset.  Besides, do not add the implicit
+	extensions if we failed to find their default versions.
+	(riscv_parse_std_ext): Updated.
+	(riscv_parse_add_implicit_subsets): New function.  Add all implicit
+	extensions according to the arch string extensions.
+	(riscv_parse_subset): Call riscv_init_ext_order and
+	riscv_parse_add_implicit_subsets, before and after parsing the
+	arch string.  Remove parts of the ISA conflict checking since
+	the implicit extensions are added.
+	* elfxx-riscv.h (riscv_lookup_subset): Updated.
+
+	gas/
+	* config/tc-riscv.c (riscv_subset_supports): Updated.
+	* testsuite/gas/riscv/march-imply-i2p0.d: New testcase.  Need to
+	add the implicit zicsr and zifencei when i's version less than 2.1.
+	* testsuite/gas/riscv/march-imply-i2p1.d: New testcase.
+	* testsuite/gas/riscv/march-imply-d.d: Likewise.
+	* testsuite/gas/riscv/march-imply-f.d: Likewise.
+	* testsuite/gas/riscv/march-imply-q.d: Likewise.
+	* testsuite/gas/riscv/march-fail-rv32iq.l: Updated.
+	* testsuite/gas/riscv/march-fail-rv32id.d: Removed.
+	* testsuite/gas/riscv/march-fail-rv32id.l: Likewise.
+	* testsuite/gas/riscv/march-fail-rv64iq.d: Likewise.
+	* testsuite/gas/riscv/march-fail-rv64iq.l: Likewise.
+---
+ bfd/elfnn-riscv.c                           |  21 +-
+ bfd/elfxx-riscv.c                           | 267 ++++++++++++++++----
+ bfd/elfxx-riscv.h                           |   5 +-
+ gas/config/tc-riscv.c                       |   4 +-
+ gas/testsuite/gas/riscv/march-fail-rv32id.d |   3 -
+ gas/testsuite/gas/riscv/march-fail-rv32id.l |   2 -
+ gas/testsuite/gas/riscv/march-fail-rv32iq.l |   1 -
+ gas/testsuite/gas/riscv/march-fail-rv64iq.d |   3 -
+ gas/testsuite/gas/riscv/march-fail-rv64iq.l |   2 -
+ gas/testsuite/gas/riscv/march-imply-d.d     |   6 +
+ gas/testsuite/gas/riscv/march-imply-f.d     |   6 +
+ gas/testsuite/gas/riscv/march-imply-i2p0.d  |   6 +
+ gas/testsuite/gas/riscv/march-imply-i2p1.d  |   6 +
+ gas/testsuite/gas/riscv/march-imply-q.d     |   6 +
+ 14 files changed, 269 insertions(+), 69 deletions(-)
+ delete mode 100644 gas/testsuite/gas/riscv/march-fail-rv32id.d
+ delete mode 100644 gas/testsuite/gas/riscv/march-fail-rv32id.l
+ delete mode 100644 gas/testsuite/gas/riscv/march-fail-rv64iq.d
+ delete mode 100644 gas/testsuite/gas/riscv/march-fail-rv64iq.l
+ create mode 100644 gas/testsuite/gas/riscv/march-imply-d.d
+ create mode 100644 gas/testsuite/gas/riscv/march-imply-f.d
+ create mode 100644 gas/testsuite/gas/riscv/march-imply-i2p0.d
+ create mode 100644 gas/testsuite/gas/riscv/march-imply-i2p1.d
+ create mode 100644 gas/testsuite/gas/riscv/march-imply-q.d
+
+diff --git a/bfd/elfnn-riscv.c b/bfd/elfnn-riscv.c
+index c08827873c..8524e689ef 100644
+--- a/bfd/elfnn-riscv.c
++++ b/bfd/elfnn-riscv.c
+@@ -2727,21 +2727,24 @@ riscv_merge_std_ext (bfd *ibfd,
+   /* Handle standard extension first.  */
+   for (p = standard_exts; *p; ++p)
+     {
++      struct riscv_subset_t *ext_in, *ext_out, *ext_merged;
+       char find_ext[2] = {*p, '\0'};
+-      struct riscv_subset_t *find_in =
+-	riscv_lookup_subset (&in_subsets, find_ext);
+-      struct riscv_subset_t *find_out =
+-	riscv_lookup_subset (&out_subsets, find_ext);
++      bfd_boolean find_in, find_out;
+ 
+-      if (find_in == NULL && find_out == NULL)
++      find_in = riscv_lookup_subset (&in_subsets, find_ext, &ext_in);
++      find_out = riscv_lookup_subset (&out_subsets, find_ext, &ext_out);
++
++      if (!find_in && !find_out)
+ 	continue;
+ 
+-      if (!riscv_version_mismatch (ibfd, find_in, find_out))
++      if (find_in
++	  && find_out
++	  && !riscv_version_mismatch (ibfd, ext_in, ext_out))
+ 	return FALSE;
+ 
+-      struct riscv_subset_t *merged = find_out ? find_out : find_in;
+-      riscv_add_subset (&merged_subsets, merged->name,
+-			merged->major_version, merged->minor_version);
++      ext_merged = find_out ? ext_out : ext_in;
++      riscv_add_subset (&merged_subsets, ext_merged->name,
++			ext_merged->major_version, ext_merged->minor_version);
+     }
+ 
+   /* Skip all standard extensions.  */
+diff --git a/bfd/elfxx-riscv.c b/bfd/elfxx-riscv.c
+index 233f4e20d6..38c4de19bd 100644
+--- a/bfd/elfxx-riscv.c
++++ b/bfd/elfxx-riscv.c
+@@ -1010,22 +1010,75 @@ riscv_elf_add_sub_reloc (bfd *abfd,
+   return bfd_reloc_ok;
+ }
+ 
+-/* Find subset in list, return NULL if not found.  */
++/* Array is used to compare the all extensions' order quickly.
+ 
+-riscv_subset_t *
+-riscv_lookup_subset (const riscv_subset_list_t *subset_list,
+-		     const char *subset)
++   Zero     number means it is a preserved keyword.
++   Negative number means it is a prefix keyword (s, h, x, z).
++   Positive number means it is a standard extension.  */
++
++static int riscv_ext_order[26] = {0};
++
++/* Similar to the strcmp.  It returns an integer less than, equal to,
++   or greater than zero if `subset2` is found, respectively, to be less
++   than, to match, or be greater than `subset1`.  */
++
++static int
++riscv_compare_subsets (const char *subset1, const char *subset2)
+ {
+-  riscv_subset_t *s;
++  int order1 = riscv_ext_order[(*subset1 - 'a')];
++  int order2 = riscv_ext_order[(*subset2 - 'a')];
+ 
+-  for (s = subset_list->head; s != NULL; s = s->next)
+-    if (strcasecmp (s->name, subset) == 0)
+-      return s;
++  /* Compare the standard extension first.  */
++  if (order1 > 0 && order2 > 0)
++    return order1 - order2;
+ 
+-  return NULL;
++  if (order1 == order2 && order1 < 0)
++    {
++      /* Compare the standard addition z extensions.  */
++      if (*subset1 == 'z')
++	{
++	  order1 = riscv_ext_order[(*++subset1 - 'a')];
++	  order2 = riscv_ext_order[(*++subset2 - 'a')];
++	  if (order1 != order2)
++	    return order1 - order2;
++	}
++      return strcasecmp (++subset1, ++subset2);
++    }
++
++  return order2 - order1;
+ }
+ 
+-/* Add extension to the subset list.  */
++/* Find subset in the list.  Return TRUE and set `current` to the subset
++   if it is found.  Otherwise, return FALSE and set `current` to the place
++   where we should insert the subset.  However, return FALSE with the NULL
++   `current` means we should insert the subset at the head of subset list,
++   if needed.  */
++
++bfd_boolean
++riscv_lookup_subset (const riscv_subset_list_t *subset_list,
++		     const char *subset,
++		     riscv_subset_t **current)
++{
++  riscv_subset_t *s, *pre_s = NULL;
++
++  for (s = subset_list->head;
++       s != NULL;
++       pre_s = s, s = s->next)
++    {
++      int cmp = riscv_compare_subsets (s->name, subset);
++      if (cmp == 0)
++	{
++	  *current = s;
++	  return TRUE;
++	}
++      else if (cmp > 0)
++	break;
++    }
++  *current = pre_s;
++  return FALSE;
++}
++
++/* Add arch string extension to the last of the subset list.  */
+ 
+ void
+ riscv_add_subset (riscv_subset_list_t *subset_list,
+@@ -1048,7 +1101,44 @@ riscv_add_subset (riscv_subset_list_t *subset_list,
+   subset_list->tail = s;
+ }
+ 
+-/* Find the default versions for the extension before adding them to
++/* Add the implicit extension to the subset list.  Search the
++   list first, and then find the right place to add.  */
++
++static void
++riscv_add_implicit_subset (riscv_subset_list_t *subset_list,
++			   const char *subset,
++			   int major,
++			   int minor)
++{
++  riscv_subset_t *current, *new;
++
++  if (riscv_lookup_subset (subset_list, subset, &current))
++    return;
++
++  new = xmalloc (sizeof *new);
++  new->name = xstrdup (subset);
++  new->major_version = major;
++  new->minor_version = minor;
++  new->next = NULL;
++
++  if (current != NULL)
++    {
++      new->next = current->next;
++      current->next = new;
++    }
++  else
++    {
++      new->next = subset_list->head;
++      subset_list->head = new;
++    }
++}
++
++/* We have to add all arch string extensions first, and then start to
++   add their implicit extensions.  The arch string extensions must be
++   set in order, so we can add them to the last of the subset list
++   directly, without searching.
++
++   Find the default versions for the extension before adding them to
+    the subset list, if their versions are RISCV_UNKNOWN_VERSION.
+    Afterwards, report errors if we can not find their default versions.  */
+ 
+@@ -1056,7 +1146,8 @@ static void
+ riscv_parse_add_subset (riscv_parse_subset_t *rps,
+ 			const char *subset,
+ 			int major,
+-			int minor)
++			int minor,
++			bfd_boolean implicit)
+ {
+   int major_version = major;
+   int minor_version = minor;
+@@ -1066,8 +1157,9 @@ riscv_parse_add_subset (riscv_parse_subset_t *rps,
+       && rps->get_default_version != NULL)
+     rps->get_default_version (subset, &major_version, &minor_version);
+ 
+-  if (major_version == RISCV_UNKNOWN_VERSION
+-      || minor_version == RISCV_UNKNOWN_VERSION)
++  if (!implicit
++      && (major_version == RISCV_UNKNOWN_VERSION
++	  || minor_version == RISCV_UNKNOWN_VERSION))
+     {
+       if (subset[0] == 'x')
+ 	rps->error_handler
+@@ -1080,8 +1172,15 @@ riscv_parse_add_subset (riscv_parse_subset_t *rps,
+       return;
+     }
+ 
+-  riscv_add_subset (rps->subset_list, subset,
+-		    major_version, minor_version);
++  if (!implicit)
++    riscv_add_subset (rps->subset_list, subset,
++		      major_version, minor_version);
++  else if (major_version != RISCV_UNKNOWN_VERSION
++	   && minor_version != RISCV_UNKNOWN_VERSION)
++    /* We only add the implicit extension if it is supported in the
++       chosen ISA spec.  */
++    riscv_add_implicit_subset (rps->subset_list, subset,
++			       major_version, minor_version);
+ }
+ 
+ /* Release subset list.  */
+@@ -1215,7 +1314,7 @@ riscv_parse_std_ext (riscv_parse_subset_t *rps,
+ 					  &minor_version, TRUE);
+ 	riscv_parse_add_subset (rps, "i",
+ 				major_version,
+-				minor_version);
++				minor_version, FALSE);
+ 	break;
+ 
+       case 'e':
+@@ -1224,11 +1323,11 @@ riscv_parse_std_ext (riscv_parse_subset_t *rps,
+ 					  &minor_version, TRUE);
+ 	riscv_parse_add_subset (rps, "e",
+ 				major_version,
+-				minor_version);
++				minor_version, FALSE);
+ 	/* i-ext must be enabled.  */
+ 	riscv_parse_add_subset (rps, "i",
+ 				RISCV_UNKNOWN_VERSION,
+-				RISCV_UNKNOWN_VERSION);
++				RISCV_UNKNOWN_VERSION, FALSE);
+ 
+ 	if (*rps->xlen > 32)
+ 	  {
+@@ -1248,13 +1347,13 @@ riscv_parse_std_ext (riscv_parse_subset_t *rps,
+ 	/* i-ext must be enabled.  */
+ 	riscv_parse_add_subset (rps, "i",
+ 				RISCV_UNKNOWN_VERSION,
+-				RISCV_UNKNOWN_VERSION);
++				RISCV_UNKNOWN_VERSION, FALSE);
+ 	for ( ; *std_exts != 'q'; std_exts++)
+ 	  {
+ 	    subset[0] = *std_exts;
+ 	    riscv_parse_add_subset (rps, subset,
+ 				    RISCV_UNKNOWN_VERSION,
+-				    RISCV_UNKNOWN_VERSION);
++				    RISCV_UNKNOWN_VERSION, FALSE);
+ 	  }
+ 	break;
+ 
+@@ -1301,7 +1400,7 @@ riscv_parse_std_ext (riscv_parse_subset_t *rps,
+ 					&minor_version, TRUE);
+       riscv_parse_add_subset (rps, subset,
+ 			      major_version,
+-			      minor_version);
++			      minor_version, FALSE);
+     }
+ 
+   return p;
+@@ -1438,7 +1537,7 @@ riscv_parse_prefixed_ext (riscv_parse_subset_t *rps,
+ 
+       riscv_parse_add_subset (rps, subset,
+ 			      major_version,
+-			      minor_version);
++			      minor_version, FALSE);
+       free (subset);
+       p += end_of_version - subset;
+ 
+@@ -1544,6 +1643,92 @@ static const riscv_parse_config_t parse_config[] =
+   {RV_ISA_CLASS_UNKNOWN, NULL, NULL}
+ };
+ 
++/* Init the riscv_ext_order array.  */
++
++static void
++riscv_init_ext_order (void)
++{
++  static bfd_boolean inited = FALSE;
++  const char *std_base_exts = "eig";
++  const char *std_remain_exts = riscv_supported_std_ext ();
++  const char *ext;
++  unsigned int i;
++  int order;
++
++  if (inited)
++    return;
++
++  /* All standard extensions' orders are positive numbers.  */
++  order = 1;
++
++  /* Init the standard base extensions first.  */
++  for (ext = std_base_exts; *ext; ext++)
++    riscv_ext_order[(*ext - 'a')] = order++;
++
++  /* Init the standard remaining extensions.  */
++  for (ext = std_remain_exts; *ext; ext++)
++    riscv_ext_order[(*ext - 'a')] = order++;
++
++  /* Init the order for prefixed keywords.  The orders are
++     negative numbers.  */
++  order = -1;
++  for (i = 0; parse_config[i].class != RV_ISA_CLASS_UNKNOWN; i++)
++    {
++      ext = parse_config[i].prefix;
++      riscv_ext_order[(*ext - 'a')] = order--;
++    }
++
++  inited = TRUE;
++}
++
++/* Add the implicit extensions according to the arch string extensions.  */
++
++static void
++riscv_parse_add_implicit_subsets (riscv_parse_subset_t *rps)
++{
++  riscv_subset_t *subset = NULL;
++
++  /* Add the zicsr and zifencei only when the i's version less than 2.1.  */
++  if ((riscv_lookup_subset (rps->subset_list, "i", &subset))
++      && (subset->major_version < 2
++	  || (subset->major_version == 2
++	      && subset->minor_version < 1)))
++    {
++      riscv_parse_add_subset (rps, "zicsr",
++			      RISCV_UNKNOWN_VERSION,
++			      RISCV_UNKNOWN_VERSION, TRUE);
++      riscv_parse_add_subset (rps, "zifencei",
++			      RISCV_UNKNOWN_VERSION,
++			      RISCV_UNKNOWN_VERSION, TRUE);
++    }
++
++  if ((riscv_lookup_subset (rps->subset_list, "q", &subset)))
++    {
++      riscv_parse_add_subset (rps, "d",
++			      RISCV_UNKNOWN_VERSION,
++			      RISCV_UNKNOWN_VERSION, TRUE);
++      riscv_parse_add_subset (rps, "f",
++			      RISCV_UNKNOWN_VERSION,
++			      RISCV_UNKNOWN_VERSION, TRUE);
++      riscv_parse_add_subset (rps, "zicsr",
++			      RISCV_UNKNOWN_VERSION,
++			      RISCV_UNKNOWN_VERSION, TRUE);
++    }
++  else if ((riscv_lookup_subset (rps->subset_list, "d", &subset)))
++    {
++      riscv_parse_add_subset (rps, "f",
++			      RISCV_UNKNOWN_VERSION,
++			      RISCV_UNKNOWN_VERSION, TRUE);
++      riscv_parse_add_subset (rps, "zicsr",
++			      RISCV_UNKNOWN_VERSION,
++			      RISCV_UNKNOWN_VERSION, TRUE);
++    }
++  else if ((riscv_lookup_subset (rps->subset_list, "f", &subset)))
++    riscv_parse_add_subset (rps, "zicsr",
++			    RISCV_UNKNOWN_VERSION,
++			    RISCV_UNKNOWN_VERSION, TRUE);
++}
++
+ /* Function for parsing arch string.
+ 
+    Return Value:
+@@ -1557,6 +1742,7 @@ bfd_boolean
+ riscv_parse_subset (riscv_parse_subset_t *rps,
+ 		    const char *arch)
+ {
++  riscv_subset_t *subset = NULL;
+   const char *p;
+   size_t i;
+   bfd_boolean no_conflict = TRUE;
+@@ -1597,6 +1783,10 @@ riscv_parse_subset (riscv_parse_subset_t *rps,
+       return FALSE;
+     }
+ 
++  /* Init the riscv_ext_order array to compare the order of extensions
++     quickly.  */
++  riscv_init_ext_order ();
++
+   /* Parsing standard extension.  */
+   p = riscv_parse_std_ext (rps, arch, p);
+ 
+@@ -1619,42 +1809,27 @@ riscv_parse_subset (riscv_parse_subset_t *rps,
+       return FALSE;
+     }
+ 
++  /* Finally add implicit extensions according to the current
++     extensions.  */
++  riscv_parse_add_implicit_subsets (rps);
++
+   /* Check the conflicts.  */
+-  if (riscv_lookup_subset (rps->subset_list, "e")
+-      && riscv_lookup_subset (rps->subset_list, "f"))
++  if (riscv_lookup_subset (rps->subset_list, "e", &subset)
++      && riscv_lookup_subset (rps->subset_list, "f", &subset))
+     {
+       rps->error_handler
+ 	(_("-march=%s: rv32e does not support the `f' extension"),
+ 	 arch);
+       no_conflict = FALSE;
+     }
+-
+-  if (riscv_lookup_subset (rps->subset_list, "q") && *rps->xlen < 64)
++  if (riscv_lookup_subset (rps->subset_list, "q", &subset)
++      && *rps->xlen < 64)
+     {
+       rps->error_handler
+ 	(_("-march=%s: rv32 does not support the `q' extension"),
+ 	 arch);
+       no_conflict = FALSE;
+     }
+-
+-  if (riscv_lookup_subset (rps->subset_list, "d")
+-      && !riscv_lookup_subset (rps->subset_list, "f"))
+-    {
+-      rps->error_handler
+-	(_("-march=%s: `d' extension requires `f' extension"),
+-	 arch);
+-      no_conflict = FALSE;
+-    }
+-
+-  if (riscv_lookup_subset (rps->subset_list, "q")
+-      && !riscv_lookup_subset (rps->subset_list, "d"))
+-    {
+-      rps->error_handler
+-	(_("-march=%s: `q' extension requires `d' extension"),
+-	 arch);
+-      no_conflict = FALSE;
+-    }
+-
+   return no_conflict;
+ }
+ 
+diff --git a/bfd/elfxx-riscv.h b/bfd/elfxx-riscv.h
+index 45705ce31c..89d4abb86e 100644
+--- a/bfd/elfxx-riscv.h
++++ b/bfd/elfxx-riscv.h
+@@ -60,9 +60,10 @@ riscv_add_subset (riscv_subset_list_t *,
+ 		  const char *,
+ 		  int, int);
+ 
+-extern riscv_subset_t *
++extern bfd_boolean
+ riscv_lookup_subset (const riscv_subset_list_t *,
+-		     const char *);
++		     const char *,
++		     riscv_subset_t **);
+ 
+ typedef struct
+ {
+diff --git a/gas/config/tc-riscv.c b/gas/config/tc-riscv.c
+index 24771b0a0b..c21bb719d8 100644
+--- a/gas/config/tc-riscv.c
++++ b/gas/config/tc-riscv.c
+@@ -210,10 +210,12 @@ static riscv_subset_list_t riscv_subsets;
+ static bfd_boolean
+ riscv_subset_supports (const char *feature)
+ {
++  struct riscv_subset_t *subset;
++
+   if (riscv_opts.rvc && (strcasecmp (feature, "c") == 0))
+     return TRUE;
+ 
+-  return riscv_lookup_subset (&riscv_subsets, feature) != NULL;
++  return riscv_lookup_subset (&riscv_subsets, feature, &subset);
+ }
+ 
+ static bfd_boolean
+diff --git a/gas/testsuite/gas/riscv/march-fail-rv32id.d b/gas/testsuite/gas/riscv/march-fail-rv32id.d
+deleted file mode 100644
+index de741cbc81..0000000000
+--- a/gas/testsuite/gas/riscv/march-fail-rv32id.d
++++ /dev/null
+@@ -1,3 +0,0 @@
+-#as: -march=rv32id
+-#source: empty.s
+-#error_output: march-fail-rv32id.l
+diff --git a/gas/testsuite/gas/riscv/march-fail-rv32id.l b/gas/testsuite/gas/riscv/march-fail-rv32id.l
+deleted file mode 100644
+index c5f990cd73..0000000000
+--- a/gas/testsuite/gas/riscv/march-fail-rv32id.l
++++ /dev/null
+@@ -1,2 +0,0 @@
+-.*Assembler messages:
+-.*Error: .*`d' extension requires `f' extension
+diff --git a/gas/testsuite/gas/riscv/march-fail-rv32iq.l b/gas/testsuite/gas/riscv/march-fail-rv32iq.l
+index 8143dd441d..dc201b3d7b 100644
+--- a/gas/testsuite/gas/riscv/march-fail-rv32iq.l
++++ b/gas/testsuite/gas/riscv/march-fail-rv32iq.l
+@@ -1,3 +1,2 @@
+ .*Assembler messages:
+ .*Error: .*rv32 does not support the `q' extension
+-.*Error: .*`q' extension requires `d' extension
+diff --git a/gas/testsuite/gas/riscv/march-fail-rv64iq.d b/gas/testsuite/gas/riscv/march-fail-rv64iq.d
+deleted file mode 100644
+index c97a812cb3..0000000000
+--- a/gas/testsuite/gas/riscv/march-fail-rv64iq.d
++++ /dev/null
+@@ -1,3 +0,0 @@
+-#as: -march=rv64iq
+-#source: empty.s
+-#error_output: march-fail-rv64iq.l
+diff --git a/gas/testsuite/gas/riscv/march-fail-rv64iq.l b/gas/testsuite/gas/riscv/march-fail-rv64iq.l
+deleted file mode 100644
+index 787f46d1ed..0000000000
+--- a/gas/testsuite/gas/riscv/march-fail-rv64iq.l
++++ /dev/null
+@@ -1,2 +0,0 @@
+-.*Assembler messages:
+-.*Error: .*`q' extension requires `d' extension
+diff --git a/gas/testsuite/gas/riscv/march-imply-d.d b/gas/testsuite/gas/riscv/march-imply-d.d
+new file mode 100644
+index 0000000000..ce2b47929f
+--- /dev/null
++++ b/gas/testsuite/gas/riscv/march-imply-d.d
+@@ -0,0 +1,6 @@
++#as: -march=rv32id -march-attr -misa-spec=20191213
++#readelf: -A
++#source: empty.s
++Attribute Section: riscv
++File Attributes
++  Tag_RISCV_arch: "rv32i2p1_f2p2_d2p2_zicsr2p0"
+diff --git a/gas/testsuite/gas/riscv/march-imply-f.d b/gas/testsuite/gas/riscv/march-imply-f.d
+new file mode 100644
+index 0000000000..bc372aed0e
+--- /dev/null
++++ b/gas/testsuite/gas/riscv/march-imply-f.d
+@@ -0,0 +1,6 @@
++#as: -march=rv32if -march-attr -misa-spec=20191213
++#readelf: -A
++#source: empty.s
++Attribute Section: riscv
++File Attributes
++  Tag_RISCV_arch: "rv32i2p1_f2p2_zicsr2p0"
+diff --git a/gas/testsuite/gas/riscv/march-imply-i2p0.d b/gas/testsuite/gas/riscv/march-imply-i2p0.d
+new file mode 100644
+index 0000000000..17fcc7aa90
+--- /dev/null
++++ b/gas/testsuite/gas/riscv/march-imply-i2p0.d
+@@ -0,0 +1,6 @@
++#as: -march=rv32i2p0 -march-attr -misa-spec=20191213
++#readelf: -A
++#source: empty.s
++Attribute Section: riscv
++File Attributes
++  Tag_RISCV_arch: "rv32i2p0_zicsr2p0_zifencei2p0"
+diff --git a/gas/testsuite/gas/riscv/march-imply-i2p1.d b/gas/testsuite/gas/riscv/march-imply-i2p1.d
+new file mode 100644
+index 0000000000..0e9a464d61
+--- /dev/null
++++ b/gas/testsuite/gas/riscv/march-imply-i2p1.d
+@@ -0,0 +1,6 @@
++#as: -march=rv32i -march-attr -misa-spec=20191213
++#readelf: -A
++#source: empty.s
++Attribute Section: riscv
++File Attributes
++  Tag_RISCV_arch: "rv32i2p1"
+diff --git a/gas/testsuite/gas/riscv/march-imply-q.d b/gas/testsuite/gas/riscv/march-imply-q.d
+new file mode 100644
+index 0000000000..d631d6f321
+--- /dev/null
++++ b/gas/testsuite/gas/riscv/march-imply-q.d
+@@ -0,0 +1,6 @@
++#as: -march=rv64iq -march-attr -misa-spec=20191213
++#readelf: -A
++#source: empty.s
++Attribute Section: riscv
++File Attributes
++  Tag_RISCV_arch: "rv64i2p1_f2p2_d2p2_q2p2_zicsr2p0"
+-- 
+2.33.0
+

+ 173 - 0
recipes-devtools/gdb/files/0010-RISC-V-Support-to-add-implicit-extensions-for-G.patch

@@ -0,0 +1,173 @@
+From fc4fc5e8d08978e94212af98282b3123e4313390 Mon Sep 17 00:00:00 2001
+From: Nelson Chu <nelson.chu@sifive.com>
+Date: Fri, 20 Nov 2020 22:33:11 +0800
+Subject: [PATCH 10/48] RISC-V: Support to add implicit extensions for G.
+
+G is a special case, consider the ISA spec github issue as follows,
+https://github.com/riscv/riscv-isa-manual/issues/575
+
+My understand is that - i, m, a, f and d extensions are not g's implicit
+extensions, they are g's expansions.  The zifencei is the implicit extension
+of g, and so is zicsr, since it is implicited by f (or i2p1).  However,
+we add the g with the RISCV_UNKNOWN_VERSION to the subset list, and it
+will not output to the arch string, it is only used to check what implicit
+extensions are need to be added.
+
+	bfd/
+	* elfxx-riscv.c (riscv_parse_add_subset): Allow to add g with
+	RISCV_UNKNOWN_VERSION versions.
+	(riscv_parse_std_ext): Add g to the subset list, we only use it
+	to add the implicit extensions, but won't output it to arch string.
+	(riscv_parse_add_implicit_subsets): Add implicit zicsr and zifencei
+	for g extension.
+	(riscv_arch_str1): Do not output g to the arch string.
+	* elfxx-riscv.h (RISCV_UNKNOWN_VERSION): Moved to include/opcode/riscv.h.
+
+	gas/
+	* testsuite/gas/riscv/attribute-10.d: Updated.
+	* testsuite/gas/riscv/march-imply-g.d: New testcase for g.
+	* testsuite/gas/riscv/march-imply-unsupported.d: The zicsr and zifencei
+	are not supported in the ISA spec v2.2, so don't add and output them.
+
+	include/
+	* opcode/riscv.h (RISCV_UNKNOWN_VERSION): added.
+---
+ bfd/elfxx-riscv.c                             | 27 ++++++++++++++-----
+ bfd/elfxx-riscv.h                             |  2 --
+ gas/testsuite/gas/riscv/attribute-10.d        |  2 +-
+ gas/testsuite/gas/riscv/march-imply-g.d       |  6 +++++
+ .../gas/riscv/march-imply-unsupported.d       |  6 +++++
+ include/opcode/riscv.h                        |  2 ++
+ 6 files changed, 36 insertions(+), 9 deletions(-)
+ create mode 100644 gas/testsuite/gas/riscv/march-imply-g.d
+ create mode 100644 gas/testsuite/gas/riscv/march-imply-unsupported.d
+
+diff --git a/bfd/elfxx-riscv.c b/bfd/elfxx-riscv.c
+index 38c4de19bd..7ff8c52620 100644
+--- a/bfd/elfxx-riscv.c
++++ b/bfd/elfxx-riscv.c
+@@ -1158,6 +1158,7 @@ riscv_parse_add_subset (riscv_parse_subset_t *rps,
+     rps->get_default_version (subset, &major_version, &minor_version);
+ 
+   if (!implicit
++      && strcmp (subset, "g") != 0
+       && (major_version == RISCV_UNKNOWN_VERSION
+ 	  || minor_version == RISCV_UNKNOWN_VERSION))
+     {
+@@ -1339,8 +1340,6 @@ riscv_parse_std_ext (riscv_parse_subset_t *rps,
+ 	break;
+ 
+       case 'g':
+-	/* The g-ext shouldn't has the version, so we just
+-	   skip the setting if user set a version to it.  */
+ 	p = riscv_parsing_subset_version (rps, march, ++p,
+ 					  &major_version,
+ 					  &minor_version, TRUE);
+@@ -1348,6 +1347,11 @@ riscv_parse_std_ext (riscv_parse_subset_t *rps,
+ 	riscv_parse_add_subset (rps, "i",
+ 				RISCV_UNKNOWN_VERSION,
+ 				RISCV_UNKNOWN_VERSION, FALSE);
++	/* g-ext is used to add the implicit extensions, but will
++	   not be output to the arch string.  */
++	riscv_parse_add_subset (rps, "g",
++				major_version,
++				minor_version, FALSE);
+ 	for ( ; *std_exts != 'q'; std_exts++)
+ 	  {
+ 	    subset[0] = *std_exts;
+@@ -1727,6 +1731,16 @@ riscv_parse_add_implicit_subsets (riscv_parse_subset_t *rps)
+     riscv_parse_add_subset (rps, "zicsr",
+ 			    RISCV_UNKNOWN_VERSION,
+ 			    RISCV_UNKNOWN_VERSION, TRUE);
++
++  if ((riscv_lookup_subset (rps->subset_list, "g", &subset)))
++    {
++      riscv_parse_add_subset (rps, "zicsr",
++			      RISCV_UNKNOWN_VERSION,
++			      RISCV_UNKNOWN_VERSION, TRUE);
++      riscv_parse_add_subset (rps, "zifencei",
++			      RISCV_UNKNOWN_VERSION,
++			      RISCV_UNKNOWN_VERSION, TRUE);
++    }
+ }
+ 
+ /* Function for parsing arch string.
+@@ -1896,10 +1910,11 @@ riscv_arch_str1 (riscv_subset_t *subset,
+ 
+   strncat (attr_str, buf, bufsz);
+ 
+-  /* Skip 'i' extension after 'e'.  */
+-  if ((strcasecmp (subset->name, "e") == 0)
+-      && subset->next
+-      && (strcasecmp (subset->next->name, "i") == 0))
++  /* Skip 'i' extension after 'e', and skip 'g' extension.  */
++  if (subset->next
++      && ((strcmp (subset->name, "e") == 0
++	   && strcmp (subset->next->name, "i") == 0)
++	  || strcmp (subset->next->name, "g") == 0))
+     riscv_arch_str1 (subset->next->next, attr_str, buf, bufsz);
+   else
+     riscv_arch_str1 (subset->next, attr_str, buf, bufsz);
+diff --git a/bfd/elfxx-riscv.h b/bfd/elfxx-riscv.h
+index 89d4abb86e..4e03ce1e86 100644
+--- a/bfd/elfxx-riscv.h
++++ b/bfd/elfxx-riscv.h
+@@ -33,8 +33,6 @@ riscv_reloc_type_lookup (bfd *, bfd_reloc_code_real_type);
+ extern reloc_howto_type *
+ riscv_elf_rtype_to_howto (bfd *, unsigned int r_type);
+ 
+-#define RISCV_UNKNOWN_VERSION -1
+-
+ /* The information of architecture attribute.  */
+ struct riscv_subset_t
+ {
+diff --git a/gas/testsuite/gas/riscv/attribute-10.d b/gas/testsuite/gas/riscv/attribute-10.d
+index ba903d1727..30b82d7207 100644
+--- a/gas/testsuite/gas/riscv/attribute-10.d
++++ b/gas/testsuite/gas/riscv/attribute-10.d
+@@ -3,4 +3,4 @@
+ #source: empty.s
+ Attribute Section: riscv
+ File Attributes
+-  Tag_RISCV_arch: "rv32i2p1_m2p0_a2p1_f2p2_d2p2_c2p0_zicsr2p0"
++  Tag_RISCV_arch: "rv32i2p1_m2p0_a2p1_f2p2_d2p2_c2p0_zicsr2p0_zifencei2p0"
+diff --git a/gas/testsuite/gas/riscv/march-imply-g.d b/gas/testsuite/gas/riscv/march-imply-g.d
+new file mode 100644
+index 0000000000..33a243d78d
+--- /dev/null
++++ b/gas/testsuite/gas/riscv/march-imply-g.d
+@@ -0,0 +1,6 @@
++#as: -march=rv32g -march-attr -misa-spec=20191213
++#readelf: -A
++#source: empty.s
++Attribute Section: riscv
++File Attributes
++  Tag_RISCV_arch: "rv32i2p1_m2p0_a2p1_f2p2_d2p2_zicsr2p0_zifencei2p0"
+diff --git a/gas/testsuite/gas/riscv/march-imply-unsupported.d b/gas/testsuite/gas/riscv/march-imply-unsupported.d
+new file mode 100644
+index 0000000000..2e19e09abf
+--- /dev/null
++++ b/gas/testsuite/gas/riscv/march-imply-unsupported.d
+@@ -0,0 +1,6 @@
++#as: -march=rv32g -march-attr -misa-spec=2.2
++#readelf: -A
++#source: empty.s
++Attribute Section: riscv
++File Attributes
++  Tag_RISCV_arch: "rv32i2p0_m2p0_a2p0_f2p0_d2p0"
+diff --git a/include/opcode/riscv.h b/include/opcode/riscv.h
+index 94a13803d9..680780a664 100644
+--- a/include/opcode/riscv.h
++++ b/include/opcode/riscv.h
+@@ -354,6 +354,8 @@ enum riscv_isa_spec_class
+   ISA_SPEC_CLASS_20191213
+ };
+ 
++#define RISCV_UNKNOWN_VERSION -1
++
+ /* This structure holds version information for specific ISA.  */
+ 
+ struct riscv_ext_version
+-- 
+2.33.0
+

+ 34 - 0
recipes-devtools/gdb/files/0011-RISC-V-Fix-the-order-checking-for-Z-extension.patch

@@ -0,0 +1,34 @@
+From 6424f98467fbdd6d7ad8fad1c9ba4fd6a517f846 Mon Sep 17 00:00:00 2001
+From: Nelson Chu <nelson.chu@sifive.com>
+Date: Fri, 20 Nov 2020 23:42:28 +0800
+Subject: [PATCH 11/48] RISC-V: Fix the order checking for Z* extension.
+
+We have to check the first char of the Z* extensions, to make sure that
+they follow the order of the standard extensions.  But we can not have
+the testcases for this patch, since we only support the zicsr and zifencei
+so far, both of them are the sub extensions of i.
+
+	bfd/
+	* elfxx-riscv.c (riscv_parse_prefixed_ext): Use riscv_compare_subsets
+	to check the Z* extensions' order.
+---
+ bfd/elfxx-riscv.c | 3 +--
+ 1 file changed, 1 insertion(+), 2 deletions(-)
+
+diff --git a/bfd/elfxx-riscv.c b/bfd/elfxx-riscv.c
+index 7ff8c52620..86c0d94d0e 100644
+--- a/bfd/elfxx-riscv.c
++++ b/bfd/elfxx-riscv.c
+@@ -1528,8 +1528,7 @@ riscv_parse_prefixed_ext (riscv_parse_subset_t *rps,
+ 	}
+ 
+       /* Check that the extension is in alphabetical order.  */
+-      if (!strncasecmp (last_name, config->prefix, 1)
+-	  && strcasecmp (last_name, subset) > 0)
++      if (riscv_compare_subsets (last_name, subset) > 0)
+ 	{
+ 	  rps->error_handler
+ 	    (_("-march=%s: %s ISA extension `%s' is not in alphabetical "
+-- 
+2.33.0
+

+ 12772 - 0
recipes-devtools/gdb/files/0012-RISC-V-Support-RVV-according-to-vector-spec-v1.0-dra.patch

@@ -0,0 +1,12772 @@
+From 9fc7114a93d01d5c4e656331ba38fcd0b0d458f9 Mon Sep 17 00:00:00 2001
+From: Nelson Chu <nelson.chu@sifive.com>
+Date: Wed, 8 Jul 2020 14:50:08 +0800
+Subject: [PATCH 12/48] RISC-V: Support RVV according to vector spec
+ v1.0-draft-20200516.
+
+	2020-05-16  Jim Wilson  <jimw@sifive.com>
+		    Kito Cheng  <kito.cheng@sifive.com>
+		    Nelson Chu  <nelson.chu@sifive.com>
+---
+ bfd/elfxx-riscv.c                             |    4 +-
+ gas/config/tc-riscv.c                         |  438 ++-
+ gas/testsuite/gas/riscv/csr-dw-regnums.d      |    9 +-
+ gas/testsuite/gas/riscv/csr-dw-regnums.s      |    7 +
+ gas/testsuite/gas/riscv/insn.d                |   69 +-
+ gas/testsuite/gas/riscv/insn.s                |   84 +
+ .../gas/riscv/march-fail-s-with-version       |    2 +
+ .../gas/riscv/priv-reg-fail-version-1p10.d    |    2 +-
+ .../gas/riscv/priv-reg-fail-version-1p11.d    |    2 +-
+ .../gas/riscv/priv-reg-fail-version-1p9p1.d   |    2 +-
+ gas/testsuite/gas/riscv/priv-reg-fail-vext.d  |    3 +
+ gas/testsuite/gas/riscv/priv-reg-fail-vext.l  |    9 +
+ .../gas/riscv/priv-reg-version-1p10.d         |    9 +-
+ .../gas/riscv/priv-reg-version-1p11.d         |    9 +-
+ .../gas/riscv/priv-reg-version-1p9p1.d        |    9 +-
+ gas/testsuite/gas/riscv/priv-reg.s            |    9 +
+ gas/testsuite/gas/riscv/v-zero-imm.d          |   17 +
+ gas/testsuite/gas/riscv/v-zero-imm.s          |    8 +
+ .../gas/riscv/vector-insns-fail-01.d          |    3 +
+ .../gas/riscv/vector-insns-fail-01.l          |  393 +++
+ .../gas/riscv/vector-insns-fail-01.s          | 1037 +++++++
+ .../gas/riscv/vector-insns-fail-02.d          |    3 +
+ .../gas/riscv/vector-insns-fail-02.l          |  121 +
+ .../gas/riscv/vector-insns-fail-02.s          |  162 +
+ .../gas/riscv/vector-insns-fail-03.d          |    3 +
+ .../gas/riscv/vector-insns-fail-03.l          |  125 +
+ .../gas/riscv/vector-insns-fail-03.s          |  187 ++
+ .../gas/riscv/vector-insns-fail-04.d          |    3 +
+ .../gas/riscv/vector-insns-fail-04.l          |   49 +
+ .../gas/riscv/vector-insns-fail-04.s          |   85 +
+ .../gas/riscv/vector-insns-fail-05.d          |    3 +
+ .../gas/riscv/vector-insns-fail-05.l          |   61 +
+ .../gas/riscv/vector-insns-fail-05.s          |  133 +
+ .../gas/riscv/vector-insns-fail-06.d          |    3 +
+ .../gas/riscv/vector-insns-fail-06.l          |   22 +
+ .../gas/riscv/vector-insns-fail-06.s          |   67 +
+ .../gas/riscv/vector-insns-fail-zvediv.d      |   20 +
+ .../gas/riscv/vector-insns-fail-zvediv.l      |    6 +
+ .../gas/riscv/vector-insns-fail-zvediv.s      |    9 +
+ .../gas/riscv/vector-insns-vmsgtvx.d          |   29 +
+ .../gas/riscv/vector-insns-vmsgtvx.s          |    9 +
+ gas/testsuite/gas/riscv/vector-insns.d        | 2384 +++++++++++++++
+ gas/testsuite/gas/riscv/vector-insns.s        | 2718 +++++++++++++++++
+ include/opcode/riscv-opc.h                    | 2138 +++++++++++++
+ include/opcode/riscv.h                        |   99 +-
+ opcodes/riscv-dis.c                           |   86 +-
+ opcodes/riscv-opc.c                           | 1306 +++++++-
+ 47 files changed, 11910 insertions(+), 46 deletions(-)
+ create mode 100644 gas/testsuite/gas/riscv/march-fail-s-with-version
+ create mode 100644 gas/testsuite/gas/riscv/priv-reg-fail-vext.d
+ create mode 100644 gas/testsuite/gas/riscv/priv-reg-fail-vext.l
+ create mode 100644 gas/testsuite/gas/riscv/v-zero-imm.d
+ create mode 100644 gas/testsuite/gas/riscv/v-zero-imm.s
+ create mode 100644 gas/testsuite/gas/riscv/vector-insns-fail-01.d
+ create mode 100644 gas/testsuite/gas/riscv/vector-insns-fail-01.l
+ create mode 100644 gas/testsuite/gas/riscv/vector-insns-fail-01.s
+ create mode 100644 gas/testsuite/gas/riscv/vector-insns-fail-02.d
+ create mode 100644 gas/testsuite/gas/riscv/vector-insns-fail-02.l
+ create mode 100644 gas/testsuite/gas/riscv/vector-insns-fail-02.s
+ create mode 100644 gas/testsuite/gas/riscv/vector-insns-fail-03.d
+ create mode 100644 gas/testsuite/gas/riscv/vector-insns-fail-03.l
+ create mode 100644 gas/testsuite/gas/riscv/vector-insns-fail-03.s
+ create mode 100644 gas/testsuite/gas/riscv/vector-insns-fail-04.d
+ create mode 100644 gas/testsuite/gas/riscv/vector-insns-fail-04.l
+ create mode 100644 gas/testsuite/gas/riscv/vector-insns-fail-04.s
+ create mode 100644 gas/testsuite/gas/riscv/vector-insns-fail-05.d
+ create mode 100644 gas/testsuite/gas/riscv/vector-insns-fail-05.l
+ create mode 100644 gas/testsuite/gas/riscv/vector-insns-fail-05.s
+ create mode 100644 gas/testsuite/gas/riscv/vector-insns-fail-06.d
+ create mode 100644 gas/testsuite/gas/riscv/vector-insns-fail-06.l
+ create mode 100644 gas/testsuite/gas/riscv/vector-insns-fail-06.s
+ create mode 100644 gas/testsuite/gas/riscv/vector-insns-fail-zvediv.d
+ create mode 100644 gas/testsuite/gas/riscv/vector-insns-fail-zvediv.l
+ create mode 100644 gas/testsuite/gas/riscv/vector-insns-fail-zvediv.s
+ create mode 100644 gas/testsuite/gas/riscv/vector-insns-vmsgtvx.d
+ create mode 100644 gas/testsuite/gas/riscv/vector-insns-vmsgtvx.s
+ create mode 100644 gas/testsuite/gas/riscv/vector-insns.d
+ create mode 100644 gas/testsuite/gas/riscv/vector-insns.s
+
+diff --git a/bfd/elfxx-riscv.c b/bfd/elfxx-riscv.c
+index 86c0d94d0e..f797d28f59 100644
+--- a/bfd/elfxx-riscv.c
++++ b/bfd/elfxx-riscv.c
+@@ -1566,7 +1566,9 @@ riscv_parse_prefixed_ext (riscv_parse_subset_t *rps,
+ 
+ static const char * const riscv_std_z_ext_strtab[] =
+ {
+-  "zicsr", "zifencei", NULL
++  "zicsr", "zifencei",
++  "zvamo", "zvediv", "zvlsseg", "zvqmac",
++  NULL
+ };
+ 
+ static const char * const riscv_std_s_ext_strtab[] =
+diff --git a/gas/config/tc-riscv.c b/gas/config/tc-riscv.c
+index c21bb719d8..222214d7e4 100644
+--- a/gas/config/tc-riscv.c
++++ b/gas/config/tc-riscv.c
+@@ -178,6 +178,7 @@ struct riscv_set_options
+   int relax; /* Emit relocs the linker is allowed to relax.  */
+   int arch_attr; /* Emit arch attribute.  */
+   int csr_check; /* Enable the CSR checking.  */
++  int check_constraints; /* Enable/disable the match_func checking.  */
+ };
+ 
+ static struct riscv_set_options riscv_opts =
+@@ -187,7 +188,8 @@ static struct riscv_set_options riscv_opts =
+   0,	/* rve */
+   1,	/* relax */
+   DEFAULT_RISCV_ATTR, /* arch_attr */
+-  0.	/* csr_check */
++  0,	/* csr_check */
++  0,	/* check_constraints */
+ };
+ 
+ static void
+@@ -237,6 +239,20 @@ riscv_multi_subset_supports (enum riscv_insn_class insn_class)
+ 
+     case INSN_CLASS_Q: return riscv_subset_supports ("q");
+ 
++    case INSN_CLASS_V: return riscv_subset_supports ("v");
++    case INSN_CLASS_V_AND_F:
++      return riscv_subset_supports ("v") && riscv_subset_supports ("f");
++    case INSN_CLASS_V_OR_ZVAMO:
++      return (riscv_subset_supports ("a")
++	      && (riscv_subset_supports ("v")
++		  || riscv_subset_supports ("zvamo")));
++    case INSN_CLASS_V_AND_ZVEDIV:
++      return riscv_subset_supports ("v") && riscv_subset_supports ("zvediv");
++    case INSN_CLASS_V_OR_ZVLSSEG:
++      return riscv_subset_supports ("v") || riscv_subset_supports ("zvlsseg");
++    case INSN_CLASS_V_AND_ZVQMAC:
++      return riscv_subset_supports ("v") && riscv_subset_supports ("zvqmac");
++
+     default:
+       as_fatal ("Unreachable");
+       return FALSE;
+@@ -598,6 +614,8 @@ enum reg_class
+ {
+   RCLASS_GPR,
+   RCLASS_FPR,
++  RCLASS_VECR,
++  RCLASS_VECM,
+   RCLASS_MAX,
+ 
+   RCLASS_CSR
+@@ -696,6 +714,12 @@ riscv_csr_address (const char *csr_name,
+       result = riscv_subset_supports ("f");
+       need_check_version = FALSE;
+       break;
++    case CSR_CLASS_V:
++      result = (riscv_subset_supports ("v")
++		|| riscv_subset_supports ("zvamo")
++		|| riscv_subset_supports ("zvlsseg"));
++      need_check_version = FALSE;
++      break;
+     case CSR_CLASS_DEBUG:
+       need_check_version = FALSE;
+       break;
+@@ -735,10 +759,8 @@ riscv_csr_address (const char *csr_name,
+   return saved_entry->address;
+ }
+ 
+-/* Once the CSR is defined, including the old privilege spec, then we call
+-   riscv_csr_class_check and riscv_csr_version_check to do the further checking
+-   and get the corresponding address.  Return -1 if the CSR is never been
+-   defined.  Otherwise, return the address.  */
++/* Return -1 if the CSR is never been defined.  Otherwise, return the
++   address.  */
+ 
+ static unsigned int
+ reg_csr_lookup_internal (const char *s)
+@@ -773,6 +795,11 @@ reg_lookup_internal (const char *s, enum reg_class class)
+   if (riscv_opts.rve && class == RCLASS_GPR && DECODE_REG_NUM (r) > 15)
+     return -1;
+ 
++  if (class == RCLASS_CSR
++      && riscv_opts.csr_check
++      && !reg_csr_lookup_internal (s))
++    return -1;
++
+   return DECODE_REG_NUM (r);
+ }
+ 
+@@ -965,6 +992,32 @@ validate_riscv_insn (const struct riscv_opcode *opc, int length)
+ 	     return FALSE;
+ 	  }
+ 	break;
++
++      case 'V': /* RVV */
++	switch (c = *p++)
++	  {
++	  case 'd':
++	  case 'f': USE_BITS (OP_MASK_VD, OP_SH_VD); break;
++	  case 'e': USE_BITS (OP_MASK_VWD, OP_SH_VWD); break;
++	  case 's': USE_BITS (OP_MASK_VS1, OP_SH_VS1); break;
++	  case 't': USE_BITS (OP_MASK_VS2, OP_SH_VS2); break;
++	  case 'u': USE_BITS (OP_MASK_VS1, OP_SH_VS1);
++		    USE_BITS (OP_MASK_VS2, OP_SH_VS2); break;
++	  case 'v': USE_BITS (OP_MASK_VD, OP_SH_VD);
++		    USE_BITS (OP_MASK_VS1, OP_SH_VS1);
++		    USE_BITS (OP_MASK_VS2, OP_SH_VS2); break;
++	  case '0': break;
++	  case 'c': used_bits |= ENCODE_RVV_VC_IMM (-1U); break;
++	  case 'i':
++	  case 'j':
++	  case 'k': USE_BITS (OP_MASK_VIMM, OP_SH_VIMM); break;
++	  case 'm': USE_BITS (OP_MASK_VMASK, OP_SH_VMASK); break;
++	  default:
++	    as_bad (_("internal: bad RISC-V opcode (unknown operand type `V%c'): %s %s"),
++		    c, opc->name, opc->args);
++	  }
++	break;
++
+       default:
+ 	as_bad (_("internal: bad RISC-V opcode "
+ 		  "(unknown operand type `%c'): %s %s"),
+@@ -1043,6 +1096,8 @@ md_begin (void)
+   hash_reg_names (RCLASS_GPR, riscv_gpr_names_abi, NGPR);
+   hash_reg_names (RCLASS_FPR, riscv_fpr_names_numeric, NFPR);
+   hash_reg_names (RCLASS_FPR, riscv_fpr_names_abi, NFPR);
++  hash_reg_names (RCLASS_VECR, riscv_vecr_names_numeric, NVECR);
++  hash_reg_names (RCLASS_VECM, riscv_vecm_names_numeric, NVECM);
+   /* Add "fp" as an alias for "s0".  */
+   hash_reg_name (RCLASS_GPR, "fp", 8);
+ 
+@@ -1201,6 +1256,42 @@ macro_build (expressionS *ep, const char *name, const char *fmt, ...)
+ 	  break;
+ 	case ',':
+ 	  continue;
++
++	case 'V': /* RVV */
++	  {
++	    switch (*fmt++)
++	      {
++	      case 'd':
++		INSERT_OPERAND (VD, insn, va_arg (args, int));
++		continue;
++
++	      case 's':
++		INSERT_OPERAND (VS1, insn, va_arg (args, int));
++		continue;
++
++	      case 't':
++		INSERT_OPERAND (VS2, insn, va_arg (args, int));
++		continue;
++
++	      case 'm':
++		{
++		  int reg = va_arg (args, int);
++		  if (reg == -1)
++		    {
++		      INSERT_OPERAND (VMASK, insn, 1);
++		      continue;
++		    }
++		  else if (reg == 0)
++		    {
++		      INSERT_OPERAND (VMASK, insn, 0);
++		      continue;
++		    }
++		}
++		/* fallthru */
++	      }
++	  }
++	  /* fallthru */
++
+ 	default:
+ 	  as_fatal (_("internal error: invalid macro"));
+ 	}
+@@ -1365,6 +1456,96 @@ load_const (int reg, expressionS *ep)
+     }
+ }
+ 
++/* Expand RISC-V Vector macros into one of more instructions.  */
++
++static void
++vector_macro (struct riscv_cl_insn *ip)
++{
++  int vd = (ip->insn_opcode >> OP_SH_VD) & OP_MASK_VD;
++  int vs1 = (ip->insn_opcode >> OP_SH_VS1) & OP_MASK_VS1;
++  int vs2 = (ip->insn_opcode >> OP_SH_VS2) & OP_MASK_VS2;
++  int vm = (ip->insn_opcode >> OP_SH_VMASK) & OP_MASK_VMASK;
++  int vtemp = (ip->insn_opcode >> OP_SH_VFUNCT6) & OP_MASK_VFUNCT6;
++  int mask = ip->insn_mo->mask;
++
++  switch (mask)
++    {
++    case M_VMSGE:
++      if (vm)
++	{
++	  /* Unmasked.  */
++	  macro_build (NULL, "vmslt.vx", "Vd,Vt,sVm", vd, vs2, vs1, -1);
++	  macro_build (NULL, "vmnand.mm", "Vd,Vt,Vs", vd, vd, vd);
++	  break;
++	}
++      if (vtemp != 0)
++	{
++	  /* Masked.  Have vtemp to avoid overlap constraints.  */
++	  if (vd == vm)
++	    {
++	      macro_build (NULL, "vmslt.vx", "Vd,Vt,s", vtemp, vs2, vs1);
++	      macro_build (NULL, "vmandnot.mm", "Vd,Vt,Vs", vd, vm, vtemp);
++	    }
++	  else
++	    {
++	      /* Preserve the value of vd if not updating by vm.  */
++	      macro_build (NULL, "vmslt.vx", "Vd,Vt,s", vtemp, vs2, vs1);
++	      macro_build (NULL, "vmandnot.mm", "Vd,Vt,Vs", vtemp, vm, vtemp);
++	      macro_build (NULL, "vmandnot.mm", "Vd,Vt,Vs", vd, vd, vm);
++	      macro_build (NULL, "vmor.mm", "Vd,Vt,Vs", vd, vtemp, vd);
++	    }
++	}
++      else if (vd != vm)
++	{
++	  /* Masked.  This may cause the vd overlaps vs2, when LMUL > 1.  */
++	  macro_build (NULL, "vmslt.vx", "Vd,Vt,sVm", vd, vs2, vs1, vm);
++	  macro_build (NULL, "vmxor.mm", "Vd,Vt,Vs", vd, vd, vm);
++	}
++      else
++	as_bad (_("must provide temp if destination overlaps mask"));
++      break;
++
++    case M_VMSGEU:
++      if (vm)
++	{
++	  /* Unmasked.  */
++	  macro_build (NULL, "vmsltu.vx", "Vd,Vt,sVm", vd, vs2, vs1, -1);
++	  macro_build (NULL, "vmnand.mm", "Vd,Vt,Vs", vd, vd, vd);
++	  break;
++	}
++      if (vtemp != 0)
++	{
++	  /* Masked.  Have vtemp to avoid overlap constraints.  */
++	  if (vd == vm)
++	    {
++	      macro_build (NULL, "vmsltu.vx", "Vd,Vt,s", vtemp, vs2, vs1);
++	      macro_build (NULL, "vmandnot.mm", "Vd,Vt,Vs", vd, vm, vtemp);
++	    }
++	  else
++	    {
++	      /* Preserve the value of vd if not updating by vm.  */
++	      macro_build (NULL, "vmsltu.vx", "Vd,Vt,s", vtemp, vs2, vs1);
++	      macro_build (NULL, "vmandnot.mm", "Vd,Vt,Vs", vtemp, vm, vtemp);
++	      macro_build (NULL, "vmandnot.mm", "Vd,Vt,Vs", vd, vd, vm);
++	      macro_build (NULL, "vmor.mm", "Vd,Vt,Vs", vd, vtemp, vd);
++	    }
++	}
++      else if (vd != vm)
++	{
++	  /* Masked.  This may cause the vd overlaps vs2, when LMUL > 1.  */
++	  macro_build (NULL, "vmsltu.vx", "Vd,Vt,sVm", vd, vs2, vs1, vm);
++	  macro_build (NULL, "vmxor.mm", "Vd,Vt,Vs", vd, vd, vm);
++	}
++      else
++	as_bad (_("must provide temp if destination overlaps mask"));
++      break;
++
++    default:
++      as_bad (_("Macro %s not implemented"), ip->insn_mo->name);
++      break;
++    }
++}
++
+ /* Expand RISC-V assembly macros into one or more instructions.  */
+ static void
+ macro (struct riscv_cl_insn *ip, expressionS *imm_expr,
+@@ -1486,6 +1667,11 @@ macro (struct riscv_cl_insn *ip, expressionS *imm_expr,
+       riscv_call (rd, rs1, imm_expr, *imm_reloc);
+       break;
+ 
++    case M_VMSGE:
++    case M_VMSGEU:
++      vector_macro (ip);
++      break;
++
+     default:
+       as_bad (_("Macro %s not implemented"), ip->insn_mo->name);
+       break;
+@@ -1639,6 +1825,81 @@ my_getSmallExpression (expressionS *ep, bfd_reloc_code_real_type *reloc,
+   return reloc_index;
+ }
+ 
++/* Parse string STR as a vsetvli operand.  Store the expression in *EP.
++   On exit, EXPR_END points to the first character after the expression.  */
++
++static void
++my_getVsetvliExpression (expressionS *ep, char *str)
++{
++  unsigned int vsew_value = 0, vlmul_value = 0, vediv_value = 0;
++  unsigned int vta_value = 0, vma_value = 0;
++  bfd_boolean vsew_found = FALSE, vlmul_found = FALSE, vediv_found = FALSE;
++  bfd_boolean vta_found = FALSE, vma_found = FALSE;
++
++  if (arg_lookup (&str, riscv_vsew, ARRAY_SIZE (riscv_vsew), &vsew_value))
++    {
++      if (*str == ',')
++	++str;
++      if (vsew_found)
++	as_bad (_("multiple vsew constants"));
++      vsew_found = TRUE;
++    }
++  if (arg_lookup (&str, riscv_vlmul, ARRAY_SIZE (riscv_vlmul), &vlmul_value))
++    {
++      if (*str == ',')
++	++str;
++      if (vlmul_found)
++	as_bad (_("multiple vlmul constants"));
++      vlmul_found = TRUE;
++    }
++  if (arg_lookup (&str, riscv_vta, ARRAY_SIZE (riscv_vta), &vta_value))
++    {
++      if (*str == ',')
++	++str;
++      if (vta_found)
++	as_bad (_("multiple vta constants"));
++      vta_found = TRUE;
++    }
++  if (arg_lookup (&str, riscv_vma, ARRAY_SIZE (riscv_vma), &vma_value))
++    {
++      if (*str == ',')
++	++str;
++      if (vma_found)
++	as_bad (_("multiple vma constants"));
++      vma_found = TRUE;
++    }
++  if (arg_lookup (&str, riscv_vediv, ARRAY_SIZE (riscv_vediv), &vediv_value))
++    {
++      if (*str == ',')
++	++str;
++      if (vediv_found)
++	as_bad (_("multiple vediv constants"));
++      vediv_found = TRUE;
++    }
++
++  if (vsew_found || vlmul_found || vediv_found || vta_found || vma_found)
++    {
++      ep->X_op = O_constant;
++      ep->X_add_number = (vediv_value << OP_SH_VEDIV)
++			 | (vsew_value << OP_SH_VSEW)
++			 | (vta_value << OP_SH_VTA)
++			 | (vma_value << OP_SH_VMA) ;
++      INSERT_VLMUL (ep->X_add_number, vlmul_value);
++      expr_end = str;
++    }
++  else
++    {
++      my_getExpression (ep, str);
++      str = expr_end;
++    }
++
++  /* Report warning message if the vediv field is set, but the Zvediv
++     extension isn't enabled.  */
++  if (!riscv_multi_subset_supports (INSN_CLASS_V_AND_ZVEDIV)
++      && (ep->X_add_number & (OP_MASK_VEDIV << OP_SH_VEDIV)))
++    as_warn ("vediv is set but Zvediv extension isn't enabled");
++}
++
+ /* Parse opcode name, could be an mnemonics or number.  */
+ static size_t
+ my_getOpcodeExpression (expressionS *ep, bfd_reloc_code_real_type *reloc,
+@@ -1811,7 +2072,8 @@ riscv_ip (char *str, struct riscv_cl_insn *ip, expressionS *imm_expr,
+ 	    case '\0': 	/* End of args.  */
+ 	      if (insn->pinfo != INSN_MACRO)
+ 		{
+-		  if (!insn->match_func (insn, ip->insn_opcode))
++		  if (!insn->match_func (insn, ip->insn_opcode,
++					 riscv_opts.check_constraints))
+ 		    break;
+ 
+ 		  /* For .insn, insn->match and insn->mask are 0.  */
+@@ -2502,6 +2764,154 @@ riscv_ip (char *str, struct riscv_cl_insn *ip, expressionS *imm_expr,
+ 	      imm_expr->X_op = O_absent;
+ 	      continue;
+ 
++	    case 'V': /* RVV */
++	      switch (*++args)
++		{
++		case 'd': /* VD */
++		  if (!reg_lookup (&s, RCLASS_VECR, &regno))
++		    break;
++		  INSERT_OPERAND (VD, *ip, regno);
++		  continue;
++
++		case 'e': /* AMO VD */
++		  if (reg_lookup (&s, RCLASS_GPR, &regno) && regno == 0)
++		    INSERT_OPERAND (VWD, *ip, 0);
++		  else if (reg_lookup (&s, RCLASS_VECR, &regno))
++		    {
++		      INSERT_OPERAND (VWD, *ip, 1);
++		      INSERT_OPERAND (VD, *ip, regno);
++		    }
++		  else
++		    break;
++		  continue;
++
++		case 'f': /* AMO VS3 */
++		  if (!reg_lookup (&s, RCLASS_VECR, &regno))
++		    break;
++		  if (!EXTRACT_OPERAND (VWD, ip->insn_opcode))
++		    INSERT_OPERAND (VD, *ip, regno);
++		  else
++		    {
++		      /* VS3 must match VD.  */
++		      if (EXTRACT_OPERAND (VD, ip->insn_opcode) != regno)
++			break;
++		    }
++		  continue;
++
++		case 's': /* VS1 */
++		  if (!reg_lookup (&s, RCLASS_VECR, &regno))
++		    break;
++		  INSERT_OPERAND (VS1, *ip, regno);
++		  continue;
++
++		case 't': /* VS2 */
++		  if (!reg_lookup (&s, RCLASS_VECR, &regno))
++		    break;
++		  INSERT_OPERAND (VS2, *ip, regno);
++		  continue;
++
++		case 'u': /* VS1 == VS2 */
++		  if (!reg_lookup (&s, RCLASS_VECR, &regno))
++		    break;
++		  INSERT_OPERAND (VS1, *ip, regno);
++		  INSERT_OPERAND (VS2, *ip, regno);
++		  continue;
++
++		case 'v': /* VD == VS1 == VS2 */
++		  if (!reg_lookup (&s, RCLASS_VECR, &regno))
++		    break;
++		  INSERT_OPERAND (VD, *ip, regno);
++		  INSERT_OPERAND (VS1, *ip, regno);
++		  INSERT_OPERAND (VS2, *ip, regno);
++		  continue;
++
++		case '0': /* required vector mask register without .t */
++		  if (reg_lookup (&s, RCLASS_VECR, &regno) && regno == 0)
++		    continue;
++		  break;
++
++		case 'c': /* vtypei for vsetvli */
++		  my_getVsetvliExpression (imm_expr, s);
++		  check_absolute_expr (ip, imm_expr, FALSE);
++		  if (!VALID_RVV_VC_IMM (imm_expr->X_add_number))
++		    as_bad (_("bad value for vsetvli immediate field, "
++			      "value must be 0..2047"));
++		  ip->insn_opcode
++		    |= ENCODE_RVV_VC_IMM (imm_expr->X_add_number);
++		  imm_expr->X_op = O_absent;
++		  s = expr_end;
++		  continue;
++
++		case 'i': /* vector arith signed immediate */
++		  my_getExpression (imm_expr, s);
++		  check_absolute_expr (ip, imm_expr, FALSE);
++		  if (imm_expr->X_add_number > 15
++		      || imm_expr->X_add_number < -16)
++		    as_bad (_("bad value for vector immediate field, "
++			      "value must be -16...15"));
++		  INSERT_OPERAND (VIMM, *ip, imm_expr->X_add_number);
++		  imm_expr->X_op = O_absent;
++		  s = expr_end;
++		  continue;
++
++		case 'j': /* vector arith unsigned immediate */
++		  my_getExpression (imm_expr, s);
++		  check_absolute_expr (ip, imm_expr, FALSE);
++		  if (imm_expr->X_add_number < 0
++		      || imm_expr->X_add_number >= 32)
++		    as_bad (_("bad value for vector immediate field, "
++			      "value must be 0...31"));
++		  INSERT_OPERAND (VIMM, *ip, imm_expr->X_add_number);
++		  imm_expr->X_op = O_absent;
++		  s = expr_end;
++		  continue;
++
++		case 'k': /* vector arith signed immediate, minus 1 */
++		  my_getExpression (imm_expr, s);
++		  check_absolute_expr (ip, imm_expr, FALSE);
++		  if (imm_expr->X_add_number > 16
++		      || imm_expr->X_add_number < -15)
++		    as_bad (_("bad value for vector immediate field, "
++			      "value must be -15...16"));
++		  INSERT_OPERAND (VIMM, *ip, imm_expr->X_add_number - 1);
++		  imm_expr->X_op = O_absent;
++		  s = expr_end;
++		  continue;
++
++		case 'm': /* optional vector mask */
++		  if (*s == '\0')
++		    {
++		      INSERT_OPERAND (VMASK, *ip, 1);
++		      continue;
++		    }
++		  else if (*s == ',' && s++
++			   && reg_lookup (&s, RCLASS_VECM, &regno)
++			   && regno == 0)
++		    {
++		      INSERT_OPERAND (VMASK, *ip, 0);
++		      continue;
++		    }
++		  break;
++
++		  /* The following ones are only used in macros.  */
++		case 'M': /* required vector mask */
++		  if (reg_lookup (&s, RCLASS_VECM, &regno) && regno == 0)
++		    {
++		      INSERT_OPERAND (VMASK, *ip, 0);
++		      continue;
++		    }
++		  break;
++
++		case 'T': /* vector macro temporary register */
++		  if (!reg_lookup (&s, RCLASS_VECR, &regno) || regno == 0)
++		    break;
++		  /* Store it in the FUNCT6 field as we don't have anyplace
++		     else to store it.  */
++		  INSERT_OPERAND (VFUNCT6, *ip, regno);
++		  continue;
++		}
++	      break;
++
+ 	    default:
+ 	      as_fatal (_("internal error: bad argument type %c"), *args);
+ 	    }
+@@ -2579,6 +2989,8 @@ enum options
+   OPTION_NO_CSR_CHECK,
+   OPTION_MISA_SPEC,
+   OPTION_MPRIV_SPEC,
++  OPTION_CHECK_CONSTRAINTS,
++  OPTION_NO_CHECK_CONSTRAINTS,
+   OPTION_END_OF_ENUM
+ };
+ 
+@@ -2597,6 +3009,8 @@ struct option md_longopts[] =
+   {"mno-csr-check", no_argument, NULL, OPTION_NO_CSR_CHECK},
+   {"misa-spec", required_argument, NULL, OPTION_MISA_SPEC},
+   {"mpriv-spec", required_argument, NULL, OPTION_MPRIV_SPEC},
++  {"mcheck-constraints", no_argument, NULL, OPTION_CHECK_CONSTRAINTS},
++  {"mno-check-constraints", no_argument, NULL, OPTION_NO_CHECK_CONSTRAINTS},
+ 
+   {NULL, no_argument, NULL, 0}
+ };
+@@ -2691,6 +3105,14 @@ md_parse_option (int c, const char *arg)
+     case OPTION_MPRIV_SPEC:
+       return riscv_set_default_priv_spec (arg);
+ 
++    case OPTION_CHECK_CONSTRAINTS:
++      riscv_opts.check_constraints = TRUE;
++      break;
++
++    case OPTION_NO_CHECK_CONSTRAINTS:
++      riscv_opts.check_constraints = FALSE;
++      break;
++
+     default:
+       return 0;
+     }
+@@ -3117,6 +3539,10 @@ s_riscv_option (int x ATTRIBUTE_UNUSED)
+     riscv_opts.csr_check = TRUE;
+   else if (strcmp (name, "no-csr-check") == 0)
+     riscv_opts.csr_check = FALSE;
++  else if (strcmp (name, "checkconstraints") == 0)
++    riscv_opts.check_constraints = TRUE;
++  else if (strcmp (name, "nocheckconstraints") == 0)
++    riscv_opts.check_constraints = FALSE;
+   else if (strcmp (name, "push") == 0)
+     {
+       struct riscv_option_stack *s;
+diff --git a/gas/testsuite/gas/riscv/csr-dw-regnums.d b/gas/testsuite/gas/riscv/csr-dw-regnums.d
+index de17ad81fb..06b62fd808 100644
+--- a/gas/testsuite/gas/riscv/csr-dw-regnums.d
++++ b/gas/testsuite/gas/riscv/csr-dw-regnums.d
+@@ -1,4 +1,4 @@
+-#as: -march=rv32if -mpriv-spec=1.11
++#as: -march=rv32ifv -mpriv-spec=1.11
+ #objdump: --dwarf=frames
+ 
+ 
+@@ -250,6 +250,13 @@ Contents of the .* section:
+   DW_CFA_offset_extended_sf: r4097 \(fflags\) at cfa\+4
+   DW_CFA_offset_extended_sf: r4098 \(frm\) at cfa\+8
+   DW_CFA_offset_extended_sf: r4099 \(fcsr\) at cfa\+12
++  DW_CFA_offset_extended_sf: r4104 \(vstart\) at cfa\+32
++  DW_CFA_offset_extended_sf: r4105 \(vxsat\) at cfa\+36
++  DW_CFA_offset_extended_sf: r4106 \(vxrm\) at cfa\+40
++  DW_CFA_offset_extended_sf: r4111 \(vcsr\) at cfa\+60
++  DW_CFA_offset_extended_sf: r7200 \(vl\) at cfa\+12416
++  DW_CFA_offset_extended_sf: r7201 \(vtype\) at cfa\+12420
++  DW_CFA_offset_extended_sf: r7202 \(vlenb\) at cfa\+12424
+   DW_CFA_offset_extended_sf: r6064 \(dcsr\) at cfa\+7872
+   DW_CFA_offset_extended_sf: r6065 \(dpc\) at cfa\+7876
+   DW_CFA_offset_extended_sf: r6066 \(dscratch0\) at cfa\+7880
+diff --git a/gas/testsuite/gas/riscv/csr-dw-regnums.s b/gas/testsuite/gas/riscv/csr-dw-regnums.s
+index ecc8014697..399e786440 100644
+--- a/gas/testsuite/gas/riscv/csr-dw-regnums.s
++++ b/gas/testsuite/gas/riscv/csr-dw-regnums.s
+@@ -242,6 +242,13 @@ _start:
+ 	.cfi_offset fflags, 4
+ 	.cfi_offset frm, 8
+ 	.cfi_offset fcsr, 12
++	.cfi_offset vstart, 32
++	.cfi_offset vxsat, 36
++	.cfi_offset vxrm, 40
++	.cfi_offset vcsr, 60
++	.cfi_offset vl, 12416
++	.cfi_offset vtype, 12420
++	.cfi_offset vlenb, 12424
+ 	.cfi_offset dcsr, 7872
+ 	.cfi_offset dpc, 7876
+ 	.cfi_offset dscratch0, 7880
+diff --git a/gas/testsuite/gas/riscv/insn.d b/gas/testsuite/gas/riscv/insn.d
+index 8f0badfce1..9d417b0794 100644
+--- a/gas/testsuite/gas/riscv/insn.d
++++ b/gas/testsuite/gas/riscv/insn.d
+@@ -1,4 +1,4 @@
+-#as: -march=rv32ifc
++#as: -march=rv32ifcv
+ #objdump: -dr
+ 
+ .*:[ 	]+file format .*
+@@ -63,3 +63,70 @@ Disassembly of section .text:
+ [^:]+:[ 	]+00c58533[ 	]+add[ 	]+a0,a1,a2
+ [^:]+:[ 	]+00c58533[ 	]+add[ 	]+a0,a1,a2
+ [^:]+:[ 	]+00c58533[ 	]+add[ 	]+a0,a1,a2
++[^:]+:[ 	]+00d675af[ 	]+vamoaddei64.v[ 	]+zero,\(a2\),v13,v11,v0.t
++[^:]+:[ 	]+00d675af[ 	]+vamoaddei64.v[ 	]+zero,\(a2\),v13,v11,v0.t
++[^:]+:[ 	]+00d675af[ 	]+vamoaddei64.v[ 	]+zero,\(a2\),v13,v11,v0.t
++[^:]+:[ 	]+00d675af[ 	]+vamoaddei64.v[ 	]+zero,\(a2\),v13,v11,v0.t
++[^:]+:[ 	]+00d675af[ 	]+vamoaddei64.v[ 	]+zero,\(a2\),v13,v11,v0.t
++[^:]+:[ 	]+00d675af[ 	]+vamoaddei64.v[ 	]+zero,\(a2\),v13,v11,v0.t
++[^:]+:[ 	]+00d675af[ 	]+vamoaddei64.v[ 	]+zero,\(a2\),v13,v11,v0.t
++[^:]+:[ 	]+00d675af[ 	]+vamoaddei64.v[ 	]+zero,\(a2\),v13,v11,v0.t
++[^:]+:[ 	]+00d675af[ 	]+vamoaddei64.v[ 	]+zero,\(a2\),v13,v11,v0.t
++[^:]+:[ 	]+00d675af[ 	]+vamoaddei64.v[ 	]+zero,\(a2\),v13,v11,v0.t
++[^:]+:[ 	]+00d675af[ 	]+vamoaddei64.v[ 	]+zero,\(a2\),v13,v11,v0.t
++[^:]+:[ 	]+00d675af[ 	]+vamoaddei64.v[ 	]+zero,\(a2\),v13,v11,v0.t
++[^:]+:[ 	]+00d675af[ 	]+vamoaddei64.v[ 	]+zero,\(a2\),v13,v11,v0.t
++[^:]+:[ 	]+00d675af[ 	]+vamoaddei64.v[ 	]+zero,\(a2\),v13,v11,v0.t
++[^:]+:[ 	]+00d675af[ 	]+vamoaddei64.v[ 	]+zero,\(a2\),v13,v11,v0.t
++[^:]+:[ 	]+00d675af[ 	]+vamoaddei64.v[ 	]+zero,\(a2\),v13,v11,v0.t
++[^:]+:[ 	]+00d675af[ 	]+vamoaddei64.v[ 	]+zero,\(a2\),v13,v11,v0.t
++[^:]+:[ 	]+00d675af[ 	]+vamoaddei64.v[ 	]+zero,\(a2\),v13,v11,v0.t
++[^:]+:[ 	]+00d675af[ 	]+vamoaddei64.v[ 	]+zero,\(a2\),v13,v11,v0.t
++[^:]+:[ 	]+08d67587[ 	]+vlse64.v[ 	]+v11,\(a2\),a3,v0.t
++[^:]+:[ 	]+08d67587[ 	]+vlse64.v[ 	]+v11,\(a2\),a3,v0.t
++[^:]+:[ 	]+08d67587[ 	]+vlse64.v[ 	]+v11,\(a2\),a3,v0.t
++[^:]+:[ 	]+08d67587[ 	]+vlse64.v[ 	]+v11,\(a2\),a3,v0.t
++[^:]+:[ 	]+08d67587[ 	]+vlse64.v[ 	]+v11,\(a2\),a3,v0.t
++[^:]+:[ 	]+0ad67587[ 	]+vlse64.v[ 	]+v11,\(a2\),a3
++[^:]+:[ 	]+0ad67587[ 	]+vlse64.v[ 	]+v11,\(a2\),a3
++[^:]+:[ 	]+0ad67587[ 	]+vlse64.v[ 	]+v11,\(a2\),a3
++[^:]+:[ 	]+0ad67587[ 	]+vlse64.v[ 	]+v11,\(a2\),a3
++[^:]+:[ 	]+0ad67587[ 	]+vlse64.v[ 	]+v11,\(a2\),a3
++[^:]+:[ 	]+08d675a7[ 	]+vsse64.v[ 	]+v11,\(a2\),a3,v0.t
++[^:]+:[ 	]+08d675a7[ 	]+vsse64.v[ 	]+v11,\(a2\),a3,v0.t
++[^:]+:[ 	]+08d675a7[ 	]+vsse64.v[ 	]+v11,\(a2\),a3,v0.t
++[^:]+:[ 	]+08d675a7[ 	]+vsse64.v[ 	]+v11,\(a2\),a3,v0.t
++[^:]+:[ 	]+08d675a7[ 	]+vsse64.v[ 	]+v11,\(a2\),a3,v0.t
++[^:]+:[ 	]+0ad675a7[ 	]+vsse64.v[ 	]+v11,\(a2\),a3
++[^:]+:[ 	]+0ad675a7[ 	]+vsse64.v[ 	]+v11,\(a2\),a3
++[^:]+:[ 	]+0ad675a7[ 	]+vsse64.v[ 	]+v11,\(a2\),a3
++[^:]+:[ 	]+0ad675a7[ 	]+vsse64.v[ 	]+v11,\(a2\),a3
++[^:]+:[ 	]+0ad675a7[ 	]+vsse64.v[ 	]+v11,\(a2\),a3
++[^:]+:[ 	]+00067587[ 	]+vle64.v[ 	]+v11,\(a2\),v0.t
++[^:]+:[ 	]+03067587[ 	]+vle64ff.v[ 	]+v11,\(a2\)
++[^:]+:[ 	]+000675a7[ 	]+vse64.v[ 	]+v11,\(a2\),v0.t
++[^:]+:[ 	]+00d605d7[ 	]+vadd.vv[ 	]+v11,v13,v12,v0.t
++[^:]+:[ 	]+00d605d7[ 	]+vadd.vv[ 	]+v11,v13,v12,v0.t
++[^:]+:[ 	]+00d605d7[ 	]+vadd.vv[ 	]+v11,v13,v12,v0.t
++[^:]+:[ 	]+00d605d7[ 	]+vadd.vv[ 	]+v11,v13,v12,v0.t
++[^:]+:[ 	]+00d605d7[ 	]+vadd.vv[ 	]+v11,v13,v12,v0.t
++[^:]+:[ 	]+00d605d7[ 	]+vadd.vv[ 	]+v11,v13,v12,v0.t
++[^:]+:[ 	]+00d605d7[ 	]+vadd.vv[ 	]+v11,v13,v12,v0.t
++[^:]+:[ 	]+00d615d7[ 	]+vfadd.vv[ 	]+v11,v13,v12,v0.t
++[^:]+:[ 	]+00d615d7[ 	]+vfadd.vv[ 	]+v11,v13,v12,v0.t
++[^:]+:[ 	]+00d625d7[ 	]+vredsum.vs[ 	]+v11,v13,v12,v0.t
++[^:]+:[ 	]+00d625d7[ 	]+vredsum.vs[ 	]+v11,v13,v12,v0.t
++[^:]+:[ 	]+00d645d7[ 	]+vadd.vx[ 	]+v11,v13,a2,v0.t
++[^:]+:[ 	]+00d645d7[ 	]+vadd.vx[ 	]+v11,v13,a2,v0.t
++[^:]+:[ 	]+00d655d7[ 	]+vfadd.vf[ 	]+v11,v13,fa2,v0.t
++[^:]+:[ 	]+00d655d7[ 	]+vfadd.vf[ 	]+v11,v13,fa2,v0.t
++[^:]+:[ 	]+38d665d7[ 	]+vslide1up.vx[ 	]+v11,v13,a2,v0.t
++[^:]+:[ 	]+3cd665d7[ 	]+vslide1down.vx[ 	]+v11,v13,a2,v0.t
++[^:]+:[ 	]+00d675d7[ 	]+vsetvli[ 	]+a1,a2,e64,m2,tu,mu,d1
++[^:]+:[ 	]+00d675d7[ 	]+vsetvli[ 	]+a1,a2,e64,m2,tu,mu,d1
++[^:]+:[ 	]+00d035d7[ 	]+vadd.vi[ 	]+v11,v13,0,v0.t
++[^:]+:[ 	]+00d0b5d7[ 	]+vadd.vi[ 	]+v11,v13,1,v0.t
++[^:]+:[ 	]+00d7b5d7[ 	]+vadd.vi[ 	]+v11,v13,15,v0.t
++[^:]+:[ 	]+00d835d7[ 	]+vadd.vi[ 	]+v11,v13,-16,v0.t
++[^:]+:[ 	]+00df35d7[ 	]+vadd.vi[ 	]+v11,v13,-2,v0.t
++[^:]+:[ 	]+00dfb5d7[ 	]+vadd.vi[ 	]+v11,v13,-1,v0.t
+diff --git a/gas/testsuite/gas/riscv/insn.s b/gas/testsuite/gas/riscv/insn.s
+index 6c08f49d43..b7cd92e96d 100644
+--- a/gas/testsuite/gas/riscv/insn.s
++++ b/gas/testsuite/gas/riscv/insn.s
+@@ -47,3 +47,87 @@ target:
+ 	.insn r  0x33,  0,  0, fa0, a1, fa2
+ 	.insn r  0x33,  0,  0, a0, fa1, fa2
+ 	.insn r  0x33,  0,  0, fa0, fa1, fa2
++
++# vamo
++# F3: width[14:12]
++# F7: amoop[31:27] + wd[26] + vm[25]
++
++	.insn r AMO, 0x7, 0x0, v11, a2, a3
++	.insn r AMO, 0x7, 0x0, v11, fa2, a3
++	.insn r AMO, 0x7, 0x0, v11, a2, fa3
++	.insn r AMO, 0x7, 0x0, v11, fa2, fa3
++	.insn r AMO, 0x7, 0x0, a1, v12, a3
++	.insn r AMO, 0x7, 0x0, fa1, v12, a3
++	.insn r AMO, 0x7, 0x0, a1, v12, fa3
++	.insn r AMO, 0x7, 0x0, fa1, v12, fa3
++	.insn r AMO, 0x7, 0x0, a1, a2, v13
++	.insn r AMO, 0x7, 0x0, fa1, a2, v13
++	.insn r 0x2f, 0x7, 0x0, a1, fa2, v13
++	.insn r 0x2f, 0x7, 0x0, fa1, fa2, v13
++	.insn r 0x2f, 0x7, 0x0, a1, v12, v13
++	.insn r 0x2f, 0x7, 0x0, fa1, v12, v13
++	.insn r 0x2f, 0x7, 0x0, v11, a2, v13
++	.insn r 0x2f, 0x7, 0x0, v11, fa2, v13
++	.insn r 0x2f, 0x7, 0x0, v11, v12, a3
++	.insn r 0x2f, 0x7, 0x0, v11, v12, fa3
++	.insn r 0x2f, 0x7, 0x0, v11, v12, v13
++
++# vmem
++# F3: width[14:12]
++# F7: nf[31:29] + mop[28:26] + vm[25]
++
++	.insn r LOAD_FP, 0x7, 0x4, v11, a2, a3
++	.insn r LOAD_FP, 0x7, 0x4, v11, a2, a3
++	.insn r LOAD_FP, 0x7, 0x4, v11, fa2, a3
++	.insn r LOAD_FP, 0x7, 0x4, v11, a2, fa3
++	.insn r LOAD_FP, 0x7, 0x4, v11, fa2, fa3
++	.insn r 0x7, 0x7, 0x5, a1, v12, a3
++	.insn r 0x7, 0x7, 0x5, fa1, v12, a3
++	.insn r 0x7, 0x7, 0x5, a1, v12, fa3
++	.insn r 0x7, 0x7, 0x5, fa1, v12, fa3
++	.insn r 0x7, 0x7, 0x5, a1, a2, v13
++	.insn r STORE_FP, 0x7, 0x4, fa1, a2, v13
++	.insn r STORE_FP, 0x7, 0x4, a1, fa2, v13
++	.insn r STORE_FP, 0x7, 0x4, fa1, fa2, v13
++	.insn r STORE_FP, 0x7, 0x4, a1, v12, v13
++	.insn r STORE_FP, 0x7, 0x4, fa1, v12, v13
++	.insn r 0x27, 0x7, 0x5, v11, a2, v13
++	.insn r 0x27, 0x7, 0x5, v11, fa2, v13
++	.insn r 0x27, 0x7, 0x5, v11, v12, a3
++	.insn r 0x27, 0x7, 0x5, v11, v12, fa3
++	.insn r 0x27, 0x7, 0x5, v11, v12, v13
++	# unit-stride
++	.insn r LOAD_FP, 0x7, 0x0, v11, a2, x0
++	.insn r LOAD_FP, 0x7, 0x1, v11, a2, x16
++	.insn r STORE_FP, 0x7, 0x0, v11, a2, x0
++
++# valu and vcfg
++# F3: funct3[14:12]
++# F7: F6[31:26] + vm[25]
++
++	.insn r 0x57, 0x0, 0x0, v11, a2, a3
++	.insn r 0x57, 0x0, 0x0, v11, fa2, a3
++	.insn r 0x57, 0x0, 0x0, v11, a2, fa3
++	.insn r 0x57, 0x0, 0x0, v11, fa2, fa3
++	.insn r 0x57, 0x0, 0x0, a1, v12, a3
++	.insn r 0x57, 0x0, 0x0, fa1, v12, a3
++	.insn r 0x57, 0x0, 0x0, a1, v12, fa3
++	.insn r 0x57, 0x1, 0x0, fa1, v12, fa3
++	.insn r 0x57, 0x1, 0x0, a1, a2, v13
++	.insn r 0x57, 0x2, 0x0, fa1, a2, v13
++	.insn r 0x57, 0x2, 0x0, a1, fa2, v13
++	.insn r 0x57, 0x4, 0x0, fa1, fa2, v13
++	.insn r 0x57, 0x4, 0x0, a1, v12, v13
++	.insn r 0x57, 0x5, 0x0, fa1, v12, v13
++	.insn r 0x57, 0x5, 0x0, v11, a2, v13
++	.insn r 0x57, 0x6, 0x1c, v11, fa2, v13
++	.insn r 0x57, 0x6, 0x1e, v11, v12, a3
++	.insn r 0x57, 0x7, 0x0, v11, v12, fa3
++	.insn r 0x57, 0x7, 0x0, v11, v12, v13
++	# OPIVI
++	.insn r 0x57, 0x3, 0x0, v11, x0, a3
++	.insn r 0x57, 0x3, 0x0, v11, x1, a3
++	.insn r 0x57, 0x3, 0x0, v11, x15, a3
++	.insn r 0x57, 0x3, 0x0, v11, x16, a3
++	.insn r 0x57, 0x3, 0x0, v11, x30, a3
++	.insn r 0x57, 0x3, 0x0, v11, x31, a3
+diff --git a/gas/testsuite/gas/riscv/march-fail-s-with-version b/gas/testsuite/gas/riscv/march-fail-s-with-version
+new file mode 100644
+index 0000000000..a514d4aec7
+--- /dev/null
++++ b/gas/testsuite/gas/riscv/march-fail-s-with-version
+@@ -0,0 +1,2 @@
++Assembler messages:
++.*: Invalid or unknown s ISA extension: 'sfoo'
+\ No newline at end of file
+diff --git a/gas/testsuite/gas/riscv/priv-reg-fail-version-1p10.d b/gas/testsuite/gas/riscv/priv-reg-fail-version-1p10.d
+index 07cf05a9c2..4fa2b18911 100644
+--- a/gas/testsuite/gas/riscv/priv-reg-fail-version-1p10.d
++++ b/gas/testsuite/gas/riscv/priv-reg-fail-version-1p10.d
+@@ -1,4 +1,4 @@
+-#as: -march=rv32if -mcsr-check -mpriv-spec=1.10 -march-attr
++#as: -march=rv32ifv -mcsr-check -mpriv-spec=1.10 -march-attr
+ #source: priv-reg.s
+ #warning_output: priv-reg-fail-version-1p10.l
+ #readelf: -A
+diff --git a/gas/testsuite/gas/riscv/priv-reg-fail-version-1p11.d b/gas/testsuite/gas/riscv/priv-reg-fail-version-1p11.d
+index bf4b1db3ed..852ce8bf64 100644
+--- a/gas/testsuite/gas/riscv/priv-reg-fail-version-1p11.d
++++ b/gas/testsuite/gas/riscv/priv-reg-fail-version-1p11.d
+@@ -1,4 +1,4 @@
+-#as: -march=rv32if -mcsr-check -mpriv-spec=1.11 -march-attr
++#as: -march=rv32ifv -mcsr-check -mpriv-spec=1.11 -march-attr
+ #source: priv-reg.s
+ #warning_output: priv-reg-fail-version-1p11.l
+ #readelf: -A
+diff --git a/gas/testsuite/gas/riscv/priv-reg-fail-version-1p9p1.d b/gas/testsuite/gas/riscv/priv-reg-fail-version-1p9p1.d
+index e2c33d81dc..e6f9fc9500 100644
+--- a/gas/testsuite/gas/riscv/priv-reg-fail-version-1p9p1.d
++++ b/gas/testsuite/gas/riscv/priv-reg-fail-version-1p9p1.d
+@@ -1,4 +1,4 @@
+-#as: -march=rv32if -mcsr-check -mpriv-spec=1.9.1 -march-attr
++#as: -march=rv32ifv -mcsr-check -mpriv-spec=1.9.1 -march-attr
+ #source: priv-reg.s
+ #warning_output: priv-reg-fail-version-1p9p1.l
+ #readelf: -A
+diff --git a/gas/testsuite/gas/riscv/priv-reg-fail-vext.d b/gas/testsuite/gas/riscv/priv-reg-fail-vext.d
+new file mode 100644
+index 0000000000..13e731c2e7
+--- /dev/null
++++ b/gas/testsuite/gas/riscv/priv-reg-fail-vext.d
+@@ -0,0 +1,3 @@
++#as: -march=rv32if -mcsr-check
++#source: priv-reg.s
++#warning_output: priv-reg-fail-vext.l
+diff --git a/gas/testsuite/gas/riscv/priv-reg-fail-vext.l b/gas/testsuite/gas/riscv/priv-reg-fail-vext.l
+new file mode 100644
+index 0000000000..1243fc7c12
+--- /dev/null
++++ b/gas/testsuite/gas/riscv/priv-reg-fail-vext.l
+@@ -0,0 +1,9 @@
++.*Assembler messages:
++#...
++.*Warning: Invalid CSR `vstart' for the current ISA
++.*Warning: Invalid CSR `vxsat' for the current ISA
++.*Warning: Invalid CSR `vxrm' for the current ISA
++.*Warning: Invalid CSR `vcsr' for the current ISA
++.*Warning: Invalid CSR `vl' for the current ISA
++.*Warning: Invalid CSR `vtype' for the current ISA
++#...
+diff --git a/gas/testsuite/gas/riscv/priv-reg-version-1p10.d b/gas/testsuite/gas/riscv/priv-reg-version-1p10.d
+index 3ad8eebe85..0a023ea5a2 100644
+--- a/gas/testsuite/gas/riscv/priv-reg-version-1p10.d
++++ b/gas/testsuite/gas/riscv/priv-reg-version-1p10.d
+@@ -1,4 +1,4 @@
+-#as: -march=rv32if -mpriv-spec=1.10
++#as: -march=rv32ifv -mpriv-spec=1.10
+ #source: priv-reg.s
+ #objdump: -dr -Mpriv-spec=1.10
+ 
+@@ -246,6 +246,13 @@ Disassembly of section .text:
+ [     	]+[0-9a-f]+:[  	]+00102573[    	]+frflags[     	]+a0
+ [     	]+[0-9a-f]+:[  	]+00202573[    	]+frrm[        	]+a0
+ [     	]+[0-9a-f]+:[  	]+00302573[    	]+frcsr[       	]+a0
++[     	]+[0-9a-f]+:[  	]+00802573[    	]+csrr[     	]+a0,vstart
++[     	]+[0-9a-f]+:[  	]+00902573[    	]+csrr[        	]+a0,vxsat
++[     	]+[0-9a-f]+:[  	]+00a02573[    	]+csrr[       	]+a0,vxrm
++[     	]+[0-9a-f]+:[  	]+00f02573[    	]+csrr[     	]+a0,vcsr
++[     	]+[0-9a-f]+:[  	]+c2002573[    	]+csrr[        	]+a0,vl
++[     	]+[0-9a-f]+:[  	]+c2102573[    	]+csrr[       	]+a0,vtype
++[     	]+[0-9a-f]+:[  	]+c2202573[    	]+csrr[       	]+a0,vlenb
+ [     	]+[0-9a-f]+:[  	]+7b002573[    	]+csrr[        	]+a0,dcsr
+ [     	]+[0-9a-f]+:[  	]+7b102573[    	]+csrr[        	]+a0,dpc
+ [     	]+[0-9a-f]+:[  	]+7b202573[    	]+csrr[        	]+a0,dscratch0
+diff --git a/gas/testsuite/gas/riscv/priv-reg-version-1p11.d b/gas/testsuite/gas/riscv/priv-reg-version-1p11.d
+index 5824bc5e1f..5956b0d9fd 100644
+--- a/gas/testsuite/gas/riscv/priv-reg-version-1p11.d
++++ b/gas/testsuite/gas/riscv/priv-reg-version-1p11.d
+@@ -1,4 +1,4 @@
+-#as: -march=rv32if -mpriv-spec=1.11
++#as: -march=rv32ifv -mpriv-spec=1.11
+ #source: priv-reg.s
+ #objdump: -dr -Mpriv-spec=1.11
+ 
+@@ -246,6 +246,13 @@ Disassembly of section .text:
+ [     	]+[0-9a-f]+:[  	]+00102573[    	]+frflags[     	]+a0
+ [     	]+[0-9a-f]+:[  	]+00202573[    	]+frrm[        	]+a0
+ [     	]+[0-9a-f]+:[  	]+00302573[    	]+frcsr[       	]+a0
++[     	]+[0-9a-f]+:[  	]+00802573[    	]+csrr[     	]+a0,vstart
++[     	]+[0-9a-f]+:[  	]+00902573[    	]+csrr[        	]+a0,vxsat
++[     	]+[0-9a-f]+:[  	]+00a02573[    	]+csrr[       	]+a0,vxrm
++[     	]+[0-9a-f]+:[  	]+00f02573[    	]+csrr[     	]+a0,vcsr
++[     	]+[0-9a-f]+:[  	]+c2002573[    	]+csrr[        	]+a0,vl
++[     	]+[0-9a-f]+:[  	]+c2102573[    	]+csrr[       	]+a0,vtype
++[     	]+[0-9a-f]+:[  	]+c2202573[    	]+csrr[       	]+a0,vlenb
+ [     	]+[0-9a-f]+:[  	]+7b002573[    	]+csrr[        	]+a0,dcsr
+ [     	]+[0-9a-f]+:[  	]+7b102573[    	]+csrr[        	]+a0,dpc
+ [     	]+[0-9a-f]+:[  	]+7b202573[    	]+csrr[        	]+a0,dscratch0
+diff --git a/gas/testsuite/gas/riscv/priv-reg-version-1p9p1.d b/gas/testsuite/gas/riscv/priv-reg-version-1p9p1.d
+index 569b9587e2..3fea56d947 100644
+--- a/gas/testsuite/gas/riscv/priv-reg-version-1p9p1.d
++++ b/gas/testsuite/gas/riscv/priv-reg-version-1p9p1.d
+@@ -1,4 +1,4 @@
+-#as: -march=rv32if -mpriv-spec=1.9.1
++#as: -march=rv32ifv -mpriv-spec=1.9.1
+ #source: priv-reg.s
+ #objdump: -dr -Mpriv-spec=1.9.1
+ 
+@@ -246,6 +246,13 @@ Disassembly of section .text:
+ [     	]+[0-9a-f]+:[  	]+00102573[    	]+frflags[     	]+a0
+ [     	]+[0-9a-f]+:[  	]+00202573[    	]+frrm[        	]+a0
+ [     	]+[0-9a-f]+:[  	]+00302573[    	]+frcsr[       	]+a0
++[     	]+[0-9a-f]+:[  	]+00802573[    	]+csrr[     	]+a0,vstart
++[     	]+[0-9a-f]+:[  	]+00902573[    	]+csrr[        	]+a0,vxsat
++[     	]+[0-9a-f]+:[  	]+00a02573[    	]+csrr[       	]+a0,vxrm
++[     	]+[0-9a-f]+:[  	]+00f02573[    	]+csrr[     	]+a0,vcsr
++[     	]+[0-9a-f]+:[  	]+c2002573[    	]+csrr[        	]+a0,vl
++[     	]+[0-9a-f]+:[  	]+c2102573[    	]+csrr[       	]+a0,vtype
++[     	]+[0-9a-f]+:[  	]+c2202573[    	]+csrr[       	]+a0,vlenb
+ [     	]+[0-9a-f]+:[  	]+7b002573[    	]+csrr[        	]+a0,dcsr
+ [     	]+[0-9a-f]+:[  	]+7b102573[    	]+csrr[        	]+a0,dpc
+ [     	]+[0-9a-f]+:[  	]+7b202573[    	]+csrr[        	]+a0,dscratch0
+diff --git a/gas/testsuite/gas/riscv/priv-reg.s b/gas/testsuite/gas/riscv/priv-reg.s
+index c40d28862b..8f625054c1 100644
+--- a/gas/testsuite/gas/riscv/priv-reg.s
++++ b/gas/testsuite/gas/riscv/priv-reg.s
+@@ -260,6 +260,15 @@
+ 	csr frm
+ 	csr fcsr
+ 
++	# Vector
++	csr vstart
++	csr vxsat
++	csr vxrm
++	csr vcsr
++	csr vl
++	csr vtype
++	csr vlenb
++
+ 	# Core debug
+ 	csr dcsr
+ 	csr dpc
+diff --git a/gas/testsuite/gas/riscv/v-zero-imm.d b/gas/testsuite/gas/riscv/v-zero-imm.d
+new file mode 100644
+index 0000000000..f6fe2ffaa8
+--- /dev/null
++++ b/gas/testsuite/gas/riscv/v-zero-imm.d
+@@ -0,0 +1,17 @@
++#as: -march=rv32ifv
++#objdump: -dr
++
++.*:[ 	]+file format .*
++
++
++Disassembly of section .text:
++
++0+000 <.text>:
++[ 	]+[0-9a-f]+:[ 	]+768fb257[ 	]+vmsle.vi[ 	]+v4,v8,-1
++[ 	]+[0-9a-f]+:[ 	]+748fb257[ 	]+vmsle.vi[ 	]+v4,v8,-1,v0.t
++[ 	]+[0-9a-f]+:[ 	]+66840257[ 	]+vmsne.vv[ 	]+v4,v8,v8
++[ 	]+[0-9a-f]+:[ 	]+64840257[ 	]+vmsne.vv[ 	]+v4,v8,v8,v0.t
++[ 	]+[0-9a-f]+:[ 	]+7e8fb257[ 	]+vmsgt.vi[ 	]+v4,v8,-1
++[ 	]+[0-9a-f]+:[ 	]+7c8fb257[ 	]+vmsgt.vi[ 	]+v4,v8,-1,v0.t
++[ 	]+[0-9a-f]+:[ 	]+62840257[ 	]+vmseq.vv[ 	]+v4,v8,v8
++[ 	]+[0-9a-f]+:[ 	]+60840257[ 	]+vmseq.vv[ 	]+v4,v8,v8,v0.t
+diff --git a/gas/testsuite/gas/riscv/v-zero-imm.s b/gas/testsuite/gas/riscv/v-zero-imm.s
+new file mode 100644
+index 0000000000..98b7063880
+--- /dev/null
++++ b/gas/testsuite/gas/riscv/v-zero-imm.s
+@@ -0,0 +1,8 @@
++	vmslt.vi v4, v8, 0
++	vmslt.vi v4, v8, 0, v0.t
++	vmsltu.vi v4, v8, 0
++	vmsltu.vi v4, v8, 0, v0.t
++	vmsge.vi v4, v8, 0
++	vmsge.vi v4, v8, 0, v0.t
++	vmsgeu.vi v4, v8, 0
++	vmsgeu.vi v4, v8, 0, v0.t
+diff --git a/gas/testsuite/gas/riscv/vector-insns-fail-01.d b/gas/testsuite/gas/riscv/vector-insns-fail-01.d
+new file mode 100644
+index 0000000000..ade7888937
+--- /dev/null
++++ b/gas/testsuite/gas/riscv/vector-insns-fail-01.d
+@@ -0,0 +1,3 @@
++#as: -march=rv32ifv -mcheck-constraints
++#source: vector-insns-fail-01.s
++#error_output: vector-insns-fail-01.l
+diff --git a/gas/testsuite/gas/riscv/vector-insns-fail-01.l b/gas/testsuite/gas/riscv/vector-insns-fail-01.l
+new file mode 100644
+index 0000000000..61687938c9
+--- /dev/null
++++ b/gas/testsuite/gas/riscv/vector-insns-fail-01.l
+@@ -0,0 +1,393 @@
++.*: Assembler messages:
++.*Error: illegal operands `vlseg2e8.v v0,\(a0\),v0.t'
++.*Error: illegal operands `vlseg2e8ff.v v0,\(a0\),v0.t'
++.*Error: illegal operands `vlseg3e8.v v0,\(a0\),v0.t'
++.*Error: illegal operands `vlseg3e8ff.v v0,\(a0\),v0.t'
++.*Error: illegal operands `vlseg4e8.v v0,\(a0\),v0.t'
++.*Error: illegal operands `vlseg4e8ff.v v0,\(a0\),v0.t'
++.*Error: illegal operands `vlseg5e8.v v0,\(a0\),v0.t'
++.*Error: illegal operands `vlseg5e8ff.v v0,\(a0\),v0.t'
++.*Error: illegal operands `vlseg6e8.v v0,\(a0\),v0.t'
++.*Error: illegal operands `vlseg6e8ff.v v0,\(a0\),v0.t'
++.*Error: illegal operands `vlseg7e8.v v0,\(a0\),v0.t'
++.*Error: illegal operands `vlseg7e8ff.v v0,\(a0\),v0.t'
++.*Error: illegal operands `vlseg8e8.v v0,\(a0\),v0.t'
++.*Error: illegal operands `vlseg8e8ff.v v0,\(a0\),v0.t'
++.*Error: illegal operands `vlseg2e16.v v0,\(a0\),v0.t'
++.*Error: illegal operands `vlseg2e16ff.v v0,\(a0\),v0.t'
++.*Error: illegal operands `vlseg3e16.v v0,\(a0\),v0.t'
++.*Error: illegal operands `vlseg3e16ff.v v0,\(a0\),v0.t'
++.*Error: illegal operands `vlseg4e16.v v0,\(a0\),v0.t'
++.*Error: illegal operands `vlseg4e16ff.v v0,\(a0\),v0.t'
++.*Error: illegal operands `vlseg5e16.v v0,\(a0\),v0.t'
++.*Error: illegal operands `vlseg5e16ff.v v0,\(a0\),v0.t'
++.*Error: illegal operands `vlseg6e16.v v0,\(a0\),v0.t'
++.*Error: illegal operands `vlseg6e16ff.v v0,\(a0\),v0.t'
++.*Error: illegal operands `vlseg7e16.v v0,\(a0\),v0.t'
++.*Error: illegal operands `vlseg7e16ff.v v0,\(a0\),v0.t'
++.*Error: illegal operands `vlseg8e16.v v0,\(a0\),v0.t'
++.*Error: illegal operands `vlseg8e16ff.v v0,\(a0\),v0.t'
++.*Error: illegal operands `vlseg2e32.v v0,\(a0\),v0.t'
++.*Error: illegal operands `vlseg2e32ff.v v0,\(a0\),v0.t'
++.*Error: illegal operands `vlseg3e32.v v0,\(a0\),v0.t'
++.*Error: illegal operands `vlseg3e32ff.v v0,\(a0\),v0.t'
++.*Error: illegal operands `vlseg4e32.v v0,\(a0\),v0.t'
++.*Error: illegal operands `vlseg4e32ff.v v0,\(a0\),v0.t'
++.*Error: illegal operands `vlseg5e32.v v0,\(a0\),v0.t'
++.*Error: illegal operands `vlseg5e32ff.v v0,\(a0\),v0.t'
++.*Error: illegal operands `vlseg6e32.v v0,\(a0\),v0.t'
++.*Error: illegal operands `vlseg6e32ff.v v0,\(a0\),v0.t'
++.*Error: illegal operands `vlseg7e32.v v0,\(a0\),v0.t'
++.*Error: illegal operands `vlseg7e32ff.v v0,\(a0\),v0.t'
++.*Error: illegal operands `vlseg8e32.v v0,\(a0\),v0.t'
++.*Error: illegal operands `vlseg8e32ff.v v0,\(a0\),v0.t'
++.*Error: illegal operands `vlseg2e64.v v0,\(a0\),v0.t'
++.*Error: illegal operands `vlseg2e64ff.v v0,\(a0\),v0.t'
++.*Error: illegal operands `vlseg3e64.v v0,\(a0\),v0.t'
++.*Error: illegal operands `vlseg3e64ff.v v0,\(a0\),v0.t'
++.*Error: illegal operands `vlseg4e64.v v0,\(a0\),v0.t'
++.*Error: illegal operands `vlseg4e64ff.v v0,\(a0\),v0.t'
++.*Error: illegal operands `vlseg5e64.v v0,\(a0\),v0.t'
++.*Error: illegal operands `vlseg5e64ff.v v0,\(a0\),v0.t'
++.*Error: illegal operands `vlseg6e64.v v0,\(a0\),v0.t'
++.*Error: illegal operands `vlseg6e64ff.v v0,\(a0\),v0.t'
++.*Error: illegal operands `vlseg7e64.v v0,\(a0\),v0.t'
++.*Error: illegal operands `vlseg7e64ff.v v0,\(a0\),v0.t'
++.*Error: illegal operands `vlseg8e64.v v0,\(a0\),v0.t'
++.*Error: illegal operands `vlseg8e64ff.v v0,\(a0\),v0.t'
++.*Error: illegal operands `vlseg2e128.v v0,\(a0\),v0.t'
++.*Error: illegal operands `vlseg2e128ff.v v0,\(a0\),v0.t'
++.*Error: illegal operands `vlseg3e128.v v0,\(a0\),v0.t'
++.*Error: illegal operands `vlseg3e128ff.v v0,\(a0\),v0.t'
++.*Error: illegal operands `vlseg4e128.v v0,\(a0\),v0.t'
++.*Error: illegal operands `vlseg4e128ff.v v0,\(a0\),v0.t'
++.*Error: illegal operands `vlseg5e128.v v0,\(a0\),v0.t'
++.*Error: illegal operands `vlseg5e128ff.v v0,\(a0\),v0.t'
++.*Error: illegal operands `vlseg6e128.v v0,\(a0\),v0.t'
++.*Error: illegal operands `vlseg6e128ff.v v0,\(a0\),v0.t'
++.*Error: illegal operands `vlseg7e128.v v0,\(a0\),v0.t'
++.*Error: illegal operands `vlseg7e128ff.v v0,\(a0\),v0.t'
++.*Error: illegal operands `vlseg8e128.v v0,\(a0\),v0.t'
++.*Error: illegal operands `vlseg8e128ff.v v0,\(a0\),v0.t'
++.*Error: illegal operands `vlseg2e256.v v0,\(a0\),v0.t'
++.*Error: illegal operands `vlseg2e256ff.v v0,\(a0\),v0.t'
++.*Error: illegal operands `vlseg3e256.v v0,\(a0\),v0.t'
++.*Error: illegal operands `vlseg3e256ff.v v0,\(a0\),v0.t'
++.*Error: illegal operands `vlseg4e256.v v0,\(a0\),v0.t'
++.*Error: illegal operands `vlseg4e256ff.v v0,\(a0\),v0.t'
++.*Error: illegal operands `vlseg5e256.v v0,\(a0\),v0.t'
++.*Error: illegal operands `vlseg5e256ff.v v0,\(a0\),v0.t'
++.*Error: illegal operands `vlseg6e256.v v0,\(a0\),v0.t'
++.*Error: illegal operands `vlseg6e256ff.v v0,\(a0\),v0.t'
++.*Error: illegal operands `vlseg7e256.v v0,\(a0\),v0.t'
++.*Error: illegal operands `vlseg7e256ff.v v0,\(a0\),v0.t'
++.*Error: illegal operands `vlseg8e256.v v0,\(a0\),v0.t'
++.*Error: illegal operands `vlseg8e256ff.v v0,\(a0\),v0.t'
++.*Error: illegal operands `vlseg2e512.v v0,\(a0\),v0.t'
++.*Error: illegal operands `vlseg2e512ff.v v0,\(a0\),v0.t'
++.*Error: illegal operands `vlseg3e512.v v0,\(a0\),v0.t'
++.*Error: illegal operands `vlseg3e512ff.v v0,\(a0\),v0.t'
++.*Error: illegal operands `vlseg4e512.v v0,\(a0\),v0.t'
++.*Error: illegal operands `vlseg4e512ff.v v0,\(a0\),v0.t'
++.*Error: illegal operands `vlseg5e512.v v0,\(a0\),v0.t'
++.*Error: illegal operands `vlseg5e512ff.v v0,\(a0\),v0.t'
++.*Error: illegal operands `vlseg6e512.v v0,\(a0\),v0.t'
++.*Error: illegal operands `vlseg6e512ff.v v0,\(a0\),v0.t'
++.*Error: illegal operands `vlseg7e512.v v0,\(a0\),v0.t'
++.*Error: illegal operands `vlseg7e512ff.v v0,\(a0\),v0.t'
++.*Error: illegal operands `vlseg8e512.v v0,\(a0\),v0.t'
++.*Error: illegal operands `vlseg8e512ff.v v0,\(a0\),v0.t'
++.*Error: illegal operands `vlseg2e1024.v v0,\(a0\),v0.t'
++.*Error: illegal operands `vlseg2e1024ff.v v0,\(a0\),v0.t'
++.*Error: illegal operands `vlseg3e1024.v v0,\(a0\),v0.t'
++.*Error: illegal operands `vlseg3e1024ff.v v0,\(a0\),v0.t'
++.*Error: illegal operands `vlseg4e1024.v v0,\(a0\),v0.t'
++.*Error: illegal operands `vlseg4e1024ff.v v0,\(a0\),v0.t'
++.*Error: illegal operands `vlseg5e1024.v v0,\(a0\),v0.t'
++.*Error: illegal operands `vlseg5e1024ff.v v0,\(a0\),v0.t'
++.*Error: illegal operands `vlseg6e1024.v v0,\(a0\),v0.t'
++.*Error: illegal operands `vlseg6e1024ff.v v0,\(a0\),v0.t'
++.*Error: illegal operands `vlseg7e1024.v v0,\(a0\),v0.t'
++.*Error: illegal operands `vlseg7e1024ff.v v0,\(a0\),v0.t'
++.*Error: illegal operands `vlseg8e1024.v v0,\(a0\),v0.t'
++.*Error: illegal operands `vlseg8e1024ff.v v0,\(a0\),v0.t'
++.*Error: illegal operands `vlsseg2e8.v v0,\(a0\),a1,v0.t'
++.*Error: illegal operands `vlsseg3e8.v v0,\(a0\),a1,v0.t'
++.*Error: illegal operands `vlsseg4e8.v v0,\(a0\),a1,v0.t'
++.*Error: illegal operands `vlsseg5e8.v v0,\(a0\),a1,v0.t'
++.*Error: illegal operands `vlsseg6e8.v v0,\(a0\),a1,v0.t'
++.*Error: illegal operands `vlsseg7e8.v v0,\(a0\),a1,v0.t'
++.*Error: illegal operands `vlsseg8e8.v v0,\(a0\),a1,v0.t'
++.*Error: illegal operands `vlsseg2e16.v v0,\(a0\),a1,v0.t'
++.*Error: illegal operands `vlsseg3e16.v v0,\(a0\),a1,v0.t'
++.*Error: illegal operands `vlsseg4e16.v v0,\(a0\),a1,v0.t'
++.*Error: illegal operands `vlsseg5e16.v v0,\(a0\),a1,v0.t'
++.*Error: illegal operands `vlsseg6e16.v v0,\(a0\),a1,v0.t'
++.*Error: illegal operands `vlsseg7e16.v v0,\(a0\),a1,v0.t'
++.*Error: illegal operands `vlsseg8e16.v v0,\(a0\),a1,v0.t'
++.*Error: illegal operands `vlsseg2e32.v v0,\(a0\),a1,v0.t'
++.*Error: illegal operands `vlsseg3e32.v v0,\(a0\),a1,v0.t'
++.*Error: illegal operands `vlsseg4e32.v v0,\(a0\),a1,v0.t'
++.*Error: illegal operands `vlsseg5e32.v v0,\(a0\),a1,v0.t'
++.*Error: illegal operands `vlsseg6e32.v v0,\(a0\),a1,v0.t'
++.*Error: illegal operands `vlsseg7e32.v v0,\(a0\),a1,v0.t'
++.*Error: illegal operands `vlsseg8e32.v v0,\(a0\),a1,v0.t'
++.*Error: illegal operands `vlsseg2e64.v v0,\(a0\),a1,v0.t'
++.*Error: illegal operands `vlsseg3e64.v v0,\(a0\),a1,v0.t'
++.*Error: illegal operands `vlsseg4e64.v v0,\(a0\),a1,v0.t'
++.*Error: illegal operands `vlsseg5e64.v v0,\(a0\),a1,v0.t'
++.*Error: illegal operands `vlsseg6e64.v v0,\(a0\),a1,v0.t'
++.*Error: illegal operands `vlsseg7e64.v v0,\(a0\),a1,v0.t'
++.*Error: illegal operands `vlsseg8e64.v v0,\(a0\),a1,v0.t'
++.*Error: illegal operands `vlsseg2e128.v v0,\(a0\),a1,v0.t'
++.*Error: illegal operands `vlsseg3e128.v v0,\(a0\),a1,v0.t'
++.*Error: illegal operands `vlsseg4e128.v v0,\(a0\),a1,v0.t'
++.*Error: illegal operands `vlsseg5e128.v v0,\(a0\),a1,v0.t'
++.*Error: illegal operands `vlsseg6e128.v v0,\(a0\),a1,v0.t'
++.*Error: illegal operands `vlsseg7e128.v v0,\(a0\),a1,v0.t'
++.*Error: illegal operands `vlsseg8e128.v v0,\(a0\),a1,v0.t'
++.*Error: illegal operands `vlsseg2e256.v v0,\(a0\),a1,v0.t'
++.*Error: illegal operands `vlsseg3e256.v v0,\(a0\),a1,v0.t'
++.*Error: illegal operands `vlsseg4e256.v v0,\(a0\),a1,v0.t'
++.*Error: illegal operands `vlsseg5e256.v v0,\(a0\),a1,v0.t'
++.*Error: illegal operands `vlsseg6e256.v v0,\(a0\),a1,v0.t'
++.*Error: illegal operands `vlsseg7e256.v v0,\(a0\),a1,v0.t'
++.*Error: illegal operands `vlsseg8e256.v v0,\(a0\),a1,v0.t'
++.*Error: illegal operands `vlsseg2e512.v v0,\(a0\),a1,v0.t'
++.*Error: illegal operands `vlsseg3e512.v v0,\(a0\),a1,v0.t'
++.*Error: illegal operands `vlsseg4e512.v v0,\(a0\),a1,v0.t'
++.*Error: illegal operands `vlsseg5e512.v v0,\(a0\),a1,v0.t'
++.*Error: illegal operands `vlsseg6e512.v v0,\(a0\),a1,v0.t'
++.*Error: illegal operands `vlsseg7e512.v v0,\(a0\),a1,v0.t'
++.*Error: illegal operands `vlsseg8e512.v v0,\(a0\),a1,v0.t'
++.*Error: illegal operands `vlsseg2e1024.v v0,\(a0\),a1,v0.t'
++.*Error: illegal operands `vlsseg3e1024.v v0,\(a0\),a1,v0.t'
++.*Error: illegal operands `vlsseg4e1024.v v0,\(a0\),a1,v0.t'
++.*Error: illegal operands `vlsseg5e1024.v v0,\(a0\),a1,v0.t'
++.*Error: illegal operands `vlsseg6e1024.v v0,\(a0\),a1,v0.t'
++.*Error: illegal operands `vlsseg7e1024.v v0,\(a0\),a1,v0.t'
++.*Error: illegal operands `vlsseg8e1024.v v0,\(a0\),a1,v0.t'
++.*Error: illegal operands `vlxseg2ei8.v v2,\(a0\),v2'
++.*Error: illegal operands `vlxseg2ei8.v v0,\(a0\),v2,v0.t'
++.*Error: illegal operands `vsxseg2ei8.v v2,\(a0\),v2'
++.*Error: illegal operands `vsxseg2ei8.v v0,\(a0\),v2,v0.t'
++.*Error: illegal operands `vlxseg3ei8.v v2,\(a0\),v2'
++.*Error: illegal operands `vlxseg3ei8.v v0,\(a0\),v2,v0.t'
++.*Error: illegal operands `vsxseg3ei8.v v2,\(a0\),v2'
++.*Error: illegal operands `vsxseg3ei8.v v0,\(a0\),v2,v0.t'
++.*Error: illegal operands `vlxseg4ei8.v v2,\(a0\),v2'
++.*Error: illegal operands `vlxseg4ei8.v v0,\(a0\),v2,v0.t'
++.*Error: illegal operands `vsxseg4ei8.v v2,\(a0\),v2'
++.*Error: illegal operands `vsxseg4ei8.v v0,\(a0\),v2,v0.t'
++.*Error: illegal operands `vlxseg5ei8.v v2,\(a0\),v2'
++.*Error: illegal operands `vlxseg5ei8.v v0,\(a0\),v2,v0.t'
++.*Error: illegal operands `vsxseg5ei8.v v2,\(a0\),v2'
++.*Error: illegal operands `vsxseg5ei8.v v0,\(a0\),v2,v0.t'
++.*Error: illegal operands `vlxseg6ei8.v v2,\(a0\),v2'
++.*Error: illegal operands `vlxseg6ei8.v v0,\(a0\),v2,v0.t'
++.*Error: illegal operands `vsxseg6ei8.v v2,\(a0\),v2'
++.*Error: illegal operands `vsxseg6ei8.v v0,\(a0\),v2,v0.t'
++.*Error: illegal operands `vlxseg7ei8.v v2,\(a0\),v2'
++.*Error: illegal operands `vlxseg7ei8.v v0,\(a0\),v2,v0.t'
++.*Error: illegal operands `vsxseg7ei8.v v2,\(a0\),v2'
++.*Error: illegal operands `vsxseg7ei8.v v0,\(a0\),v2,v0.t'
++.*Error: illegal operands `vlxseg8ei8.v v2,\(a0\),v2'
++.*Error: illegal operands `vlxseg8ei8.v v0,\(a0\),v2,v0.t'
++.*Error: illegal operands `vsxseg8ei8.v v2,\(a0\),v2'
++.*Error: illegal operands `vsxseg8ei8.v v0,\(a0\),v2,v0.t'
++.*Error: illegal operands `vlxseg2ei16.v v2,\(a0\),v2'
++.*Error: illegal operands `vlxseg2ei16.v v0,\(a0\),v2,v0.t'
++.*Error: illegal operands `vsxseg2ei16.v v2,\(a0\),v2'
++.*Error: illegal operands `vsxseg2ei16.v v0,\(a0\),v2,v0.t'
++.*Error: illegal operands `vlxseg3ei16.v v2,\(a0\),v2'
++.*Error: illegal operands `vlxseg3ei16.v v0,\(a0\),v2,v0.t'
++.*Error: illegal operands `vsxseg3ei16.v v2,\(a0\),v2'
++.*Error: illegal operands `vsxseg3ei16.v v0,\(a0\),v2,v0.t'
++.*Error: illegal operands `vlxseg4ei16.v v2,\(a0\),v2'
++.*Error: illegal operands `vlxseg4ei16.v v0,\(a0\),v2,v0.t'
++.*Error: illegal operands `vsxseg4ei16.v v2,\(a0\),v2'
++.*Error: illegal operands `vsxseg4ei16.v v0,\(a0\),v2,v0.t'
++.*Error: illegal operands `vlxseg5ei16.v v2,\(a0\),v2'
++.*Error: illegal operands `vlxseg5ei16.v v0,\(a0\),v2,v0.t'
++.*Error: illegal operands `vsxseg5ei16.v v2,\(a0\),v2'
++.*Error: illegal operands `vsxseg5ei16.v v0,\(a0\),v2,v0.t'
++.*Error: illegal operands `vlxseg6ei16.v v2,\(a0\),v2'
++.*Error: illegal operands `vlxseg6ei16.v v0,\(a0\),v2,v0.t'
++.*Error: illegal operands `vsxseg6ei16.v v2,\(a0\),v2'
++.*Error: illegal operands `vsxseg6ei16.v v0,\(a0\),v2,v0.t'
++.*Error: illegal operands `vlxseg7ei16.v v2,\(a0\),v2'
++.*Error: illegal operands `vlxseg7ei16.v v0,\(a0\),v2,v0.t'
++.*Error: illegal operands `vsxseg7ei16.v v2,\(a0\),v2'
++.*Error: illegal operands `vsxseg7ei16.v v0,\(a0\),v2,v0.t'
++.*Error: illegal operands `vlxseg8ei16.v v2,\(a0\),v2'
++.*Error: illegal operands `vlxseg8ei16.v v0,\(a0\),v2,v0.t'
++.*Error: illegal operands `vsxseg8ei16.v v2,\(a0\),v2'
++.*Error: illegal operands `vsxseg8ei16.v v0,\(a0\),v2,v0.t'
++.*Error: illegal operands `vlxseg2ei32.v v2,\(a0\),v2'
++.*Error: illegal operands `vlxseg2ei32.v v0,\(a0\),v2,v0.t'
++.*Error: illegal operands `vsxseg2ei32.v v2,\(a0\),v2'
++.*Error: illegal operands `vsxseg2ei32.v v0,\(a0\),v2,v0.t'
++.*Error: illegal operands `vlxseg3ei32.v v2,\(a0\),v2'
++.*Error: illegal operands `vlxseg3ei32.v v0,\(a0\),v2,v0.t'
++.*Error: illegal operands `vsxseg3ei32.v v2,\(a0\),v2'
++.*Error: illegal operands `vsxseg3ei32.v v0,\(a0\),v2,v0.t'
++.*Error: illegal operands `vlxseg4ei32.v v2,\(a0\),v2'
++.*Error: illegal operands `vlxseg4ei32.v v0,\(a0\),v2,v0.t'
++.*Error: illegal operands `vsxseg4ei32.v v2,\(a0\),v2'
++.*Error: illegal operands `vsxseg4ei32.v v0,\(a0\),v2,v0.t'
++.*Error: illegal operands `vlxseg5ei32.v v2,\(a0\),v2'
++.*Error: illegal operands `vlxseg5ei32.v v0,\(a0\),v2,v0.t'
++.*Error: illegal operands `vsxseg5ei32.v v2,\(a0\),v2'
++.*Error: illegal operands `vsxseg5ei32.v v0,\(a0\),v2,v0.t'
++.*Error: illegal operands `vlxseg6ei32.v v2,\(a0\),v2'
++.*Error: illegal operands `vlxseg6ei32.v v0,\(a0\),v2,v0.t'
++.*Error: illegal operands `vsxseg6ei32.v v2,\(a0\),v2'
++.*Error: illegal operands `vsxseg6ei32.v v0,\(a0\),v2,v0.t'
++.*Error: illegal operands `vlxseg7ei32.v v2,\(a0\),v2'
++.*Error: illegal operands `vlxseg7ei32.v v0,\(a0\),v2,v0.t'
++.*Error: illegal operands `vsxseg7ei32.v v2,\(a0\),v2'
++.*Error: illegal operands `vsxseg7ei32.v v0,\(a0\),v2,v0.t'
++.*Error: illegal operands `vlxseg8ei32.v v2,\(a0\),v2'
++.*Error: illegal operands `vlxseg8ei32.v v0,\(a0\),v2,v0.t'
++.*Error: illegal operands `vsxseg8ei32.v v2,\(a0\),v2'
++.*Error: illegal operands `vsxseg8ei32.v v0,\(a0\),v2,v0.t'
++.*Error: illegal operands `vlxseg2ei64.v v2,\(a0\),v2'
++.*Error: illegal operands `vlxseg2ei64.v v0,\(a0\),v2,v0.t'
++.*Error: illegal operands `vsxseg2ei64.v v2,\(a0\),v2'
++.*Error: illegal operands `vsxseg2ei64.v v0,\(a0\),v2,v0.t'
++.*Error: illegal operands `vlxseg3ei64.v v2,\(a0\),v2'
++.*Error: illegal operands `vlxseg3ei64.v v0,\(a0\),v2,v0.t'
++.*Error: illegal operands `vsxseg3ei64.v v2,\(a0\),v2'
++.*Error: illegal operands `vsxseg3ei64.v v0,\(a0\),v2,v0.t'
++.*Error: illegal operands `vlxseg4ei64.v v2,\(a0\),v2'
++.*Error: illegal operands `vlxseg4ei64.v v0,\(a0\),v2,v0.t'
++.*Error: illegal operands `vsxseg4ei64.v v2,\(a0\),v2'
++.*Error: illegal operands `vsxseg4ei64.v v0,\(a0\),v2,v0.t'
++.*Error: illegal operands `vlxseg5ei64.v v2,\(a0\),v2'
++.*Error: illegal operands `vlxseg5ei64.v v0,\(a0\),v2,v0.t'
++.*Error: illegal operands `vsxseg5ei64.v v2,\(a0\),v2'
++.*Error: illegal operands `vsxseg5ei64.v v0,\(a0\),v2,v0.t'
++.*Error: illegal operands `vlxseg6ei64.v v2,\(a0\),v2'
++.*Error: illegal operands `vlxseg6ei64.v v0,\(a0\),v2,v0.t'
++.*Error: illegal operands `vsxseg6ei64.v v2,\(a0\),v2'
++.*Error: illegal operands `vsxseg6ei64.v v0,\(a0\),v2,v0.t'
++.*Error: illegal operands `vlxseg7ei64.v v2,\(a0\),v2'
++.*Error: illegal operands `vlxseg7ei64.v v0,\(a0\),v2,v0.t'
++.*Error: illegal operands `vsxseg7ei64.v v2,\(a0\),v2'
++.*Error: illegal operands `vsxseg7ei64.v v0,\(a0\),v2,v0.t'
++.*Error: illegal operands `vlxseg8ei64.v v2,\(a0\),v2'
++.*Error: illegal operands `vlxseg8ei64.v v0,\(a0\),v2,v0.t'
++.*Error: illegal operands `vsxseg8ei64.v v2,\(a0\),v2'
++.*Error: illegal operands `vsxseg8ei64.v v0,\(a0\),v2,v0.t'
++.*Error: illegal operands `vlxseg2ei128.v v2,\(a0\),v2'
++.*Error: illegal operands `vlxseg2ei128.v v0,\(a0\),v2,v0.t'
++.*Error: illegal operands `vsxseg2ei128.v v2,\(a0\),v2'
++.*Error: illegal operands `vsxseg2ei128.v v0,\(a0\),v2,v0.t'
++.*Error: illegal operands `vlxseg3ei128.v v2,\(a0\),v2'
++.*Error: illegal operands `vlxseg3ei128.v v0,\(a0\),v2,v0.t'
++.*Error: illegal operands `vsxseg3ei128.v v2,\(a0\),v2'
++.*Error: illegal operands `vsxseg3ei128.v v0,\(a0\),v2,v0.t'
++.*Error: illegal operands `vlxseg4ei128.v v2,\(a0\),v2'
++.*Error: illegal operands `vlxseg4ei128.v v0,\(a0\),v2,v0.t'
++.*Error: illegal operands `vsxseg4ei128.v v2,\(a0\),v2'
++.*Error: illegal operands `vsxseg4ei128.v v0,\(a0\),v2,v0.t'
++.*Error: illegal operands `vlxseg5ei128.v v2,\(a0\),v2'
++.*Error: illegal operands `vlxseg5ei128.v v0,\(a0\),v2,v0.t'
++.*Error: illegal operands `vsxseg5ei128.v v2,\(a0\),v2'
++.*Error: illegal operands `vsxseg5ei128.v v0,\(a0\),v2,v0.t'
++.*Error: illegal operands `vlxseg6ei128.v v2,\(a0\),v2'
++.*Error: illegal operands `vlxseg6ei128.v v0,\(a0\),v2,v0.t'
++.*Error: illegal operands `vsxseg6ei128.v v2,\(a0\),v2'
++.*Error: illegal operands `vsxseg6ei128.v v0,\(a0\),v2,v0.t'
++.*Error: illegal operands `vlxseg7ei128.v v2,\(a0\),v2'
++.*Error: illegal operands `vlxseg7ei128.v v0,\(a0\),v2,v0.t'
++.*Error: illegal operands `vsxseg7ei128.v v2,\(a0\),v2'
++.*Error: illegal operands `vsxseg7ei128.v v0,\(a0\),v2,v0.t'
++.*Error: illegal operands `vlxseg8ei128.v v2,\(a0\),v2'
++.*Error: illegal operands `vlxseg8ei128.v v0,\(a0\),v2,v0.t'
++.*Error: illegal operands `vsxseg8ei128.v v2,\(a0\),v2'
++.*Error: illegal operands `vsxseg8ei128.v v0,\(a0\),v2,v0.t'
++.*Error: illegal operands `vlxseg2ei256.v v2,\(a0\),v2'
++.*Error: illegal operands `vlxseg2ei256.v v0,\(a0\),v2,v0.t'
++.*Error: illegal operands `vsxseg2ei256.v v2,\(a0\),v2'
++.*Error: illegal operands `vsxseg2ei256.v v0,\(a0\),v2,v0.t'
++.*Error: illegal operands `vlxseg3ei256.v v2,\(a0\),v2'
++.*Error: illegal operands `vlxseg3ei256.v v0,\(a0\),v2,v0.t'
++.*Error: illegal operands `vsxseg3ei256.v v2,\(a0\),v2'
++.*Error: illegal operands `vsxseg3ei256.v v0,\(a0\),v2,v0.t'
++.*Error: illegal operands `vlxseg4ei256.v v2,\(a0\),v2'
++.*Error: illegal operands `vlxseg4ei256.v v0,\(a0\),v2,v0.t'
++.*Error: illegal operands `vsxseg4ei256.v v2,\(a0\),v2'
++.*Error: illegal operands `vsxseg4ei256.v v0,\(a0\),v2,v0.t'
++.*Error: illegal operands `vlxseg5ei256.v v2,\(a0\),v2'
++.*Error: illegal operands `vlxseg5ei256.v v0,\(a0\),v2,v0.t'
++.*Error: illegal operands `vsxseg5ei256.v v2,\(a0\),v2'
++.*Error: illegal operands `vsxseg5ei256.v v0,\(a0\),v2,v0.t'
++.*Error: illegal operands `vlxseg6ei256.v v2,\(a0\),v2'
++.*Error: illegal operands `vlxseg6ei256.v v0,\(a0\),v2,v0.t'
++.*Error: illegal operands `vsxseg6ei256.v v2,\(a0\),v2'
++.*Error: illegal operands `vsxseg6ei256.v v0,\(a0\),v2,v0.t'
++.*Error: illegal operands `vlxseg7ei256.v v2,\(a0\),v2'
++.*Error: illegal operands `vlxseg7ei256.v v0,\(a0\),v2,v0.t'
++.*Error: illegal operands `vsxseg7ei256.v v2,\(a0\),v2'
++.*Error: illegal operands `vsxseg7ei256.v v0,\(a0\),v2,v0.t'
++.*Error: illegal operands `vlxseg8ei256.v v2,\(a0\),v2'
++.*Error: illegal operands `vlxseg8ei256.v v0,\(a0\),v2,v0.t'
++.*Error: illegal operands `vsxseg8ei256.v v2,\(a0\),v2'
++.*Error: illegal operands `vsxseg8ei256.v v0,\(a0\),v2,v0.t'
++.*Error: illegal operands `vlxseg2ei512.v v2,\(a0\),v2'
++.*Error: illegal operands `vlxseg2ei512.v v0,\(a0\),v2,v0.t'
++.*Error: illegal operands `vsxseg2ei512.v v2,\(a0\),v2'
++.*Error: illegal operands `vsxseg2ei512.v v0,\(a0\),v2,v0.t'
++.*Error: illegal operands `vlxseg3ei512.v v2,\(a0\),v2'
++.*Error: illegal operands `vlxseg3ei512.v v0,\(a0\),v2,v0.t'
++.*Error: illegal operands `vsxseg3ei512.v v2,\(a0\),v2'
++.*Error: illegal operands `vsxseg3ei512.v v0,\(a0\),v2,v0.t'
++.*Error: illegal operands `vlxseg4ei512.v v2,\(a0\),v2'
++.*Error: illegal operands `vlxseg4ei512.v v0,\(a0\),v2,v0.t'
++.*Error: illegal operands `vsxseg4ei512.v v2,\(a0\),v2'
++.*Error: illegal operands `vsxseg4ei512.v v0,\(a0\),v2,v0.t'
++.*Error: illegal operands `vlxseg5ei512.v v2,\(a0\),v2'
++.*Error: illegal operands `vlxseg5ei512.v v0,\(a0\),v2,v0.t'
++.*Error: illegal operands `vsxseg5ei512.v v2,\(a0\),v2'
++.*Error: illegal operands `vsxseg5ei512.v v0,\(a0\),v2,v0.t'
++.*Error: illegal operands `vlxseg6ei512.v v2,\(a0\),v2'
++.*Error: illegal operands `vlxseg6ei512.v v0,\(a0\),v2,v0.t'
++.*Error: illegal operands `vsxseg6ei512.v v2,\(a0\),v2'
++.*Error: illegal operands `vsxseg6ei512.v v0,\(a0\),v2,v0.t'
++.*Error: illegal operands `vlxseg7ei512.v v2,\(a0\),v2'
++.*Error: illegal operands `vlxseg7ei512.v v0,\(a0\),v2,v0.t'
++.*Error: illegal operands `vsxseg7ei512.v v2,\(a0\),v2'
++.*Error: illegal operands `vsxseg7ei512.v v0,\(a0\),v2,v0.t'
++.*Error: illegal operands `vlxseg8ei512.v v2,\(a0\),v2'
++.*Error: illegal operands `vlxseg8ei512.v v0,\(a0\),v2,v0.t'
++.*Error: illegal operands `vsxseg8ei512.v v2,\(a0\),v2'
++.*Error: illegal operands `vsxseg8ei512.v v0,\(a0\),v2,v0.t'
++.*Error: illegal operands `vlxseg2ei1024.v v2,\(a0\),v2'
++.*Error: illegal operands `vlxseg2ei1024.v v0,\(a0\),v2,v0.t'
++.*Error: illegal operands `vsxseg2ei1024.v v2,\(a0\),v2'
++.*Error: illegal operands `vsxseg2ei1024.v v0,\(a0\),v2,v0.t'
++.*Error: illegal operands `vlxseg3ei1024.v v2,\(a0\),v2'
++.*Error: illegal operands `vlxseg3ei1024.v v0,\(a0\),v2,v0.t'
++.*Error: illegal operands `vsxseg3ei1024.v v2,\(a0\),v2'
++.*Error: illegal operands `vsxseg3ei1024.v v0,\(a0\),v2,v0.t'
++.*Error: illegal operands `vlxseg4ei1024.v v2,\(a0\),v2'
++.*Error: illegal operands `vlxseg4ei1024.v v0,\(a0\),v2,v0.t'
++.*Error: illegal operands `vsxseg4ei1024.v v2,\(a0\),v2'
++.*Error: illegal operands `vsxseg4ei1024.v v0,\(a0\),v2,v0.t'
++.*Error: illegal operands `vlxseg5ei1024.v v2,\(a0\),v2'
++.*Error: illegal operands `vlxseg5ei1024.v v0,\(a0\),v2,v0.t'
++.*Error: illegal operands `vsxseg5ei1024.v v2,\(a0\),v2'
++.*Error: illegal operands `vsxseg5ei1024.v v0,\(a0\),v2,v0.t'
++.*Error: illegal operands `vlxseg6ei1024.v v2,\(a0\),v2'
++.*Error: illegal operands `vlxseg6ei1024.v v0,\(a0\),v2,v0.t'
++.*Error: illegal operands `vsxseg6ei1024.v v2,\(a0\),v2'
++.*Error: illegal operands `vsxseg6ei1024.v v0,\(a0\),v2,v0.t'
++.*Error: illegal operands `vlxseg7ei1024.v v2,\(a0\),v2'
++.*Error: illegal operands `vlxseg7ei1024.v v0,\(a0\),v2,v0.t'
++.*Error: illegal operands `vsxseg7ei1024.v v2,\(a0\),v2'
++.*Error: illegal operands `vsxseg7ei1024.v v0,\(a0\),v2,v0.t'
++.*Error: illegal operands `vlxseg8ei1024.v v2,\(a0\),v2'
++.*Error: illegal operands `vlxseg8ei1024.v v0,\(a0\),v2,v0.t'
++.*Error: illegal operands `vsxseg8ei1024.v v2,\(a0\),v2'
++.*Error: illegal operands `vsxseg8ei1024.v v0,\(a0\),v2,v0.t'
+diff --git a/gas/testsuite/gas/riscv/vector-insns-fail-01.s b/gas/testsuite/gas/riscv/vector-insns-fail-01.s
+new file mode 100644
+index 0000000000..4c1a913f2d
+--- /dev/null
++++ b/gas/testsuite/gas/riscv/vector-insns-fail-01.s
+@@ -0,0 +1,1037 @@
++# Vector Unit-Stride Segment Loads and Stores
++
++	vlseg2e8.v v0, (a0), v0.t	# vd overlap vm
++	vlseg2e8.v v4, (a0), v0.t	# OK
++	vsseg2e8.v v0, (a0), v0.t	# OK
++	vsseg2e8.v v4, (a0), v0.t	# OK
++	vlseg2e8ff.v v0, (a0), v0.t	# vd overlap vm
++	vlseg2e8ff.v v4, (a0), v0.t	# OK
++	vlseg3e8.v v0, (a0), v0.t	# vd overlap vm
++	vlseg3e8.v v4, (a0), v0.t	# OK
++	vsseg3e8.v v0, (a0), v0.t	# OK
++	vsseg3e8.v v4, (a0), v0.t	# OK
++	vlseg3e8ff.v v0, (a0), v0.t	# vd overlap vm
++	vlseg3e8ff.v v4, (a0), v0.t	# OK
++	vlseg4e8.v v0, (a0), v0.t	# vd overlap vm
++	vlseg4e8.v v4, (a0), v0.t	# OK
++	vsseg4e8.v v0, (a0), v0.t	# OK
++	vsseg4e8.v v4, (a0), v0.t	# OK
++	vlseg4e8ff.v v0, (a0), v0.t	# vd overlap vm
++	vlseg4e8ff.v v4, (a0), v0.t	# OK
++	vlseg5e8.v v0, (a0), v0.t	# vd overlap vm
++	vlseg5e8.v v4, (a0), v0.t	# OK
++	vsseg5e8.v v0, (a0), v0.t	# OK
++	vsseg5e8.v v4, (a0), v0.t	# OK
++	vlseg5e8ff.v v0, (a0), v0.t	# vd overlap vm
++	vlseg5e8ff.v v4, (a0), v0.t	# OK
++	vlseg6e8.v v0, (a0), v0.t	# vd overlap vm
++	vlseg6e8.v v4, (a0), v0.t	# OK
++	vsseg6e8.v v0, (a0), v0.t	# OK
++	vsseg6e8.v v4, (a0), v0.t	# OK
++	vlseg6e8ff.v v0, (a0), v0.t	# vd overlap vm
++	vlseg6e8ff.v v4, (a0), v0.t	# OK
++	vlseg7e8.v v0, (a0), v0.t	# vd overlap vm
++	vlseg7e8.v v4, (a0), v0.t	# OK
++	vsseg7e8.v v0, (a0), v0.t	# OK
++	vsseg7e8.v v4, (a0), v0.t	# OK
++	vlseg7e8ff.v v0, (a0), v0.t	# vd overlap vm
++	vlseg7e8ff.v v4, (a0), v0.t	# OK
++	vlseg8e8.v v0, (a0), v0.t	# vd overlap vm
++	vlseg8e8.v v4, (a0), v0.t	# OK
++	vsseg8e8.v v0, (a0), v0.t	# OK
++	vsseg8e8.v v4, (a0), v0.t	# OK
++	vlseg8e8ff.v v0, (a0), v0.t	# vd overlap vm
++	vlseg8e8ff.v v4, (a0), v0.t	# OK
++
++	vlseg2e16.v v0, (a0), v0.t	# vd overlap vm
++	vlseg2e16.v v4, (a0), v0.t	# OK
++	vsseg2e16.v v0, (a0), v0.t	# OK
++	vsseg2e16.v v4, (a0), v0.t	# OK
++	vlseg2e16ff.v v0, (a0), v0.t	# vd overlap vm
++	vlseg2e16ff.v v4, (a0), v0.t	# OK
++	vlseg3e16.v v0, (a0), v0.t	# vd overlap vm
++	vlseg3e16.v v4, (a0), v0.t	# OK
++	vsseg3e16.v v0, (a0), v0.t	# OK
++	vsseg3e16.v v4, (a0), v0.t	# OK
++	vlseg3e16ff.v v0, (a0), v0.t	# vd overlap vm
++	vlseg3e16ff.v v4, (a0), v0.t	# OK
++	vlseg4e16.v v0, (a0), v0.t	# vd overlap vm
++	vlseg4e16.v v4, (a0), v0.t	# OK
++	vsseg4e16.v v0, (a0), v0.t	# OK
++	vsseg4e16.v v4, (a0), v0.t	# OK
++	vlseg4e16ff.v v0, (a0), v0.t	# vd overlap vm
++	vlseg4e16ff.v v4, (a0), v0.t	# OK
++	vlseg5e16.v v0, (a0), v0.t	# vd overlap vm
++	vlseg5e16.v v4, (a0), v0.t	# OK
++	vsseg5e16.v v0, (a0), v0.t	# OK
++	vsseg5e16.v v4, (a0), v0.t	# OK
++	vlseg5e16ff.v v0, (a0), v0.t	# vd overlap vm
++	vlseg5e16ff.v v4, (a0), v0.t	# OK
++	vlseg6e16.v v0, (a0), v0.t	# vd overlap vm
++	vlseg6e16.v v4, (a0), v0.t	# OK
++	vsseg6e16.v v0, (a0), v0.t	# OK
++	vsseg6e16.v v4, (a0), v0.t	# OK
++	vlseg6e16ff.v v0, (a0), v0.t	# vd overlap vm
++	vlseg6e16ff.v v4, (a0), v0.t	# OK
++	vlseg7e16.v v0, (a0), v0.t	# vd overlap vm
++	vlseg7e16.v v4, (a0), v0.t	# OK
++	vsseg7e16.v v0, (a0), v0.t	# OK
++	vsseg7e16.v v4, (a0), v0.t	# OK
++	vlseg7e16ff.v v0, (a0), v0.t	# vd overlap vm
++	vlseg7e16ff.v v4, (a0), v0.t	# OK
++	vlseg8e16.v v0, (a0), v0.t	# vd overlap vm
++	vlseg8e16.v v4, (a0), v0.t	# OK
++	vsseg8e16.v v0, (a0), v0.t	# OK
++	vsseg8e16.v v4, (a0), v0.t	# OK
++	vlseg8e16ff.v v0, (a0), v0.t	# vd overlap vm
++	vlseg8e16ff.v v4, (a0), v0.t	# OK
++
++	vlseg2e32.v v0, (a0), v0.t	# vd overlap vm
++	vlseg2e32.v v4, (a0), v0.t	# OK
++	vsseg2e32.v v0, (a0), v0.t	# OK
++	vsseg2e32.v v4, (a0), v0.t	# OK
++	vlseg2e32ff.v v0, (a0), v0.t	# vd overlap vm
++	vlseg2e32ff.v v4, (a0), v0.t	# OK
++	vlseg3e32.v v0, (a0), v0.t	# vd overlap vm
++	vlseg3e32.v v4, (a0), v0.t	# OK
++	vsseg3e32.v v0, (a0), v0.t	# OK
++	vsseg3e32.v v4, (a0), v0.t	# OK
++	vlseg3e32ff.v v0, (a0), v0.t	# vd overlap vm
++	vlseg3e32ff.v v4, (a0), v0.t	# OK
++	vlseg4e32.v v0, (a0), v0.t	# vd overlap vm
++	vlseg4e32.v v4, (a0), v0.t	# OK
++	vsseg4e32.v v0, (a0), v0.t	# OK
++	vsseg4e32.v v4, (a0), v0.t	# OK
++	vlseg4e32ff.v v0, (a0), v0.t	# vd overlap vm
++	vlseg4e32ff.v v4, (a0), v0.t	# OK
++	vlseg5e32.v v0, (a0), v0.t	# vd overlap vm
++	vlseg5e32.v v4, (a0), v0.t	# OK
++	vsseg5e32.v v0, (a0), v0.t	# OK
++	vsseg5e32.v v4, (a0), v0.t	# OK
++	vlseg5e32ff.v v0, (a0), v0.t	# vd overlap vm
++	vlseg5e32ff.v v4, (a0), v0.t	# OK
++	vlseg6e32.v v0, (a0), v0.t	# vd overlap vm
++	vlseg6e32.v v4, (a0), v0.t	# OK
++	vsseg6e32.v v0, (a0), v0.t	# OK
++	vsseg6e32.v v4, (a0), v0.t	# OK
++	vlseg6e32ff.v v0, (a0), v0.t	# vd overlap vm
++	vlseg6e32ff.v v4, (a0), v0.t	# OK
++	vlseg7e32.v v0, (a0), v0.t	# vd overlap vm
++	vlseg7e32.v v4, (a0), v0.t	# OK
++	vsseg7e32.v v0, (a0), v0.t	# OK
++	vsseg7e32.v v4, (a0), v0.t	# OK
++	vlseg7e32ff.v v0, (a0), v0.t	# vd overlap vm
++	vlseg7e32ff.v v4, (a0), v0.t	# OK
++	vlseg8e32.v v0, (a0), v0.t	# vd overlap vm
++	vlseg8e32.v v4, (a0), v0.t	# OK
++	vsseg8e32.v v0, (a0), v0.t	# OK
++	vsseg8e32.v v4, (a0), v0.t	# OK
++	vlseg8e32ff.v v0, (a0), v0.t	# vd overlap vm
++	vlseg8e32ff.v v4, (a0), v0.t	# OK
++
++	vlseg2e64.v v0, (a0), v0.t	# vd overlap vm
++	vlseg2e64.v v4, (a0), v0.t	# OK
++	vsseg2e64.v v0, (a0), v0.t	# OK
++	vsseg2e64.v v4, (a0), v0.t	# OK
++	vlseg2e64ff.v v0, (a0), v0.t	# vd overlap vm
++	vlseg2e64ff.v v4, (a0), v0.t	# OK
++	vlseg3e64.v v0, (a0), v0.t	# vd overlap vm
++	vlseg3e64.v v4, (a0), v0.t	# OK
++	vsseg3e64.v v0, (a0), v0.t	# OK
++	vsseg3e64.v v4, (a0), v0.t	# OK
++	vlseg3e64ff.v v0, (a0), v0.t	# vd overlap vm
++	vlseg3e64ff.v v4, (a0), v0.t	# OK
++	vlseg4e64.v v0, (a0), v0.t	# vd overlap vm
++	vlseg4e64.v v4, (a0), v0.t	# OK
++	vsseg4e64.v v0, (a0), v0.t	# OK
++	vsseg4e64.v v4, (a0), v0.t	# OK
++	vlseg4e64ff.v v0, (a0), v0.t	# vd overlap vm
++	vlseg4e64ff.v v4, (a0), v0.t	# OK
++	vlseg5e64.v v0, (a0), v0.t	# vd overlap vm
++	vlseg5e64.v v4, (a0), v0.t	# OK
++	vsseg5e64.v v0, (a0), v0.t	# OK
++	vsseg5e64.v v4, (a0), v0.t	# OK
++	vlseg5e64ff.v v0, (a0), v0.t	# vd overlap vm
++	vlseg5e64ff.v v4, (a0), v0.t	# OK
++	vlseg6e64.v v0, (a0), v0.t	# vd overlap vm
++	vlseg6e64.v v4, (a0), v0.t	# OK
++	vsseg6e64.v v0, (a0), v0.t	# OK
++	vsseg6e64.v v4, (a0), v0.t	# OK
++	vlseg6e64ff.v v0, (a0), v0.t	# vd overlap vm
++	vlseg6e64ff.v v4, (a0), v0.t	# OK
++	vlseg7e64.v v0, (a0), v0.t	# vd overlap vm
++	vlseg7e64.v v4, (a0), v0.t	# OK
++	vsseg7e64.v v0, (a0), v0.t	# OK
++	vsseg7e64.v v4, (a0), v0.t	# OK
++	vlseg7e64ff.v v0, (a0), v0.t	# vd overlap vm
++	vlseg7e64ff.v v4, (a0), v0.t	# OK
++	vlseg8e64.v v0, (a0), v0.t	# vd overlap vm
++	vlseg8e64.v v4, (a0), v0.t	# OK
++	vsseg8e64.v v0, (a0), v0.t	# OK
++	vsseg8e64.v v4, (a0), v0.t	# OK
++	vlseg8e64ff.v v0, (a0), v0.t	# vd overlap vm
++	vlseg8e64ff.v v4, (a0), v0.t	# OK
++
++	vlseg2e128.v v0, (a0), v0.t	# vd overlap vm
++	vlseg2e128.v v4, (a0), v0.t	# OK
++	vsseg2e128.v v0, (a0), v0.t	# OK
++	vsseg2e128.v v4, (a0), v0.t	# OK
++	vlseg2e128ff.v v0, (a0), v0.t	# vd overlap vm
++	vlseg2e128ff.v v4, (a0), v0.t	# OK
++	vlseg3e128.v v0, (a0), v0.t	# vd overlap vm
++	vlseg3e128.v v4, (a0), v0.t	# OK
++	vsseg3e128.v v0, (a0), v0.t	# OK
++	vsseg3e128.v v4, (a0), v0.t	# OK
++	vlseg3e128ff.v v0, (a0), v0.t	# vd overlap vm
++	vlseg3e128ff.v v4, (a0), v0.t	# OK
++	vlseg4e128.v v0, (a0), v0.t	# vd overlap vm
++	vlseg4e128.v v4, (a0), v0.t	# OK
++	vsseg4e128.v v0, (a0), v0.t	# OK
++	vsseg4e128.v v4, (a0), v0.t	# OK
++	vlseg4e128ff.v v0, (a0), v0.t	# vd overlap vm
++	vlseg4e128ff.v v4, (a0), v0.t	# OK
++	vlseg5e128.v v0, (a0), v0.t	# vd overlap vm
++	vlseg5e128.v v4, (a0), v0.t	# OK
++	vsseg5e128.v v0, (a0), v0.t	# OK
++	vsseg5e128.v v4, (a0), v0.t	# OK
++	vlseg5e128ff.v v0, (a0), v0.t	# vd overlap vm
++	vlseg5e128ff.v v4, (a0), v0.t	# OK
++	vlseg6e128.v v0, (a0), v0.t	# vd overlap vm
++	vlseg6e128.v v4, (a0), v0.t	# OK
++	vsseg6e128.v v0, (a0), v0.t	# OK
++	vsseg6e128.v v4, (a0), v0.t	# OK
++	vlseg6e128ff.v v0, (a0), v0.t	# vd overlap vm
++	vlseg6e128ff.v v4, (a0), v0.t	# OK
++	vlseg7e128.v v0, (a0), v0.t	# vd overlap vm
++	vlseg7e128.v v4, (a0), v0.t	# OK
++	vsseg7e128.v v0, (a0), v0.t	# OK
++	vsseg7e128.v v4, (a0), v0.t	# OK
++	vlseg7e128ff.v v0, (a0), v0.t	# vd overlap vm
++	vlseg7e128ff.v v4, (a0), v0.t	# OK
++	vlseg8e128.v v0, (a0), v0.t	# vd overlap vm
++	vlseg8e128.v v4, (a0), v0.t	# OK
++	vsseg8e128.v v0, (a0), v0.t	# OK
++	vsseg8e128.v v4, (a0), v0.t	# OK
++	vlseg8e128ff.v v0, (a0), v0.t	# vd overlap vm
++	vlseg8e128ff.v v4, (a0), v0.t	# OK
++
++	vlseg2e256.v v0, (a0), v0.t	# vd overlap vm
++	vlseg2e256.v v4, (a0), v0.t	# OK
++	vsseg2e256.v v0, (a0), v0.t	# OK
++	vsseg2e256.v v4, (a0), v0.t	# OK
++	vlseg2e256ff.v v0, (a0), v0.t	# vd overlap vm
++	vlseg2e256ff.v v4, (a0), v0.t	# OK
++	vlseg3e256.v v0, (a0), v0.t	# vd overlap vm
++	vlseg3e256.v v4, (a0), v0.t	# OK
++	vsseg3e256.v v0, (a0), v0.t	# OK
++	vsseg3e256.v v4, (a0), v0.t	# OK
++	vlseg3e256ff.v v0, (a0), v0.t	# vd overlap vm
++	vlseg3e256ff.v v4, (a0), v0.t	# OK
++	vlseg4e256.v v0, (a0), v0.t	# vd overlap vm
++	vlseg4e256.v v4, (a0), v0.t	# OK
++	vsseg4e256.v v0, (a0), v0.t	# OK
++	vsseg4e256.v v4, (a0), v0.t	# OK
++	vlseg4e256ff.v v0, (a0), v0.t	# vd overlap vm
++	vlseg4e256ff.v v4, (a0), v0.t	# OK
++	vlseg5e256.v v0, (a0), v0.t	# vd overlap vm
++	vlseg5e256.v v4, (a0), v0.t	# OK
++	vsseg5e256.v v0, (a0), v0.t	# OK
++	vsseg5e256.v v4, (a0), v0.t	# OK
++	vlseg5e256ff.v v0, (a0), v0.t	# vd overlap vm
++	vlseg5e256ff.v v4, (a0), v0.t	# OK
++	vlseg6e256.v v0, (a0), v0.t	# vd overlap vm
++	vlseg6e256.v v4, (a0), v0.t	# OK
++	vsseg6e256.v v0, (a0), v0.t	# OK
++	vsseg6e256.v v4, (a0), v0.t	# OK
++	vlseg6e256ff.v v0, (a0), v0.t	# vd overlap vm
++	vlseg6e256ff.v v4, (a0), v0.t	# OK
++	vlseg7e256.v v0, (a0), v0.t	# vd overlap vm
++	vlseg7e256.v v4, (a0), v0.t	# OK
++	vsseg7e256.v v0, (a0), v0.t	# OK
++	vsseg7e256.v v4, (a0), v0.t	# OK
++	vlseg7e256ff.v v0, (a0), v0.t	# vd overlap vm
++	vlseg7e256ff.v v4, (a0), v0.t	# OK
++	vlseg8e256.v v0, (a0), v0.t	# vd overlap vm
++	vlseg8e256.v v4, (a0), v0.t	# OK
++	vsseg8e256.v v0, (a0), v0.t	# OK
++	vsseg8e256.v v4, (a0), v0.t	# OK
++	vlseg8e256ff.v v0, (a0), v0.t	# vd overlap vm
++	vlseg8e256ff.v v4, (a0), v0.t	# OK
++
++	vlseg2e512.v v0, (a0), v0.t	# vd overlap vm
++	vlseg2e512.v v4, (a0), v0.t	# OK
++	vsseg2e512.v v0, (a0), v0.t	# OK
++	vsseg2e512.v v4, (a0), v0.t	# OK
++	vlseg2e512ff.v v0, (a0), v0.t	# vd overlap vm
++	vlseg2e512ff.v v4, (a0), v0.t	# OK
++	vlseg3e512.v v0, (a0), v0.t	# vd overlap vm
++	vlseg3e512.v v4, (a0), v0.t	# OK
++	vsseg3e512.v v0, (a0), v0.t	# OK
++	vsseg3e512.v v4, (a0), v0.t	# OK
++	vlseg3e512ff.v v0, (a0), v0.t	# vd overlap vm
++	vlseg3e512ff.v v4, (a0), v0.t	# OK
++	vlseg4e512.v v0, (a0), v0.t	# vd overlap vm
++	vlseg4e512.v v4, (a0), v0.t	# OK
++	vsseg4e512.v v0, (a0), v0.t	# OK
++	vsseg4e512.v v4, (a0), v0.t	# OK
++	vlseg4e512ff.v v0, (a0), v0.t	# vd overlap vm
++	vlseg4e512ff.v v4, (a0), v0.t	# OK
++	vlseg5e512.v v0, (a0), v0.t	# vd overlap vm
++	vlseg5e512.v v4, (a0), v0.t	# OK
++	vsseg5e512.v v0, (a0), v0.t	# OK
++	vsseg5e512.v v4, (a0), v0.t	# OK
++	vlseg5e512ff.v v0, (a0), v0.t	# vd overlap vm
++	vlseg5e512ff.v v4, (a0), v0.t	# OK
++	vlseg6e512.v v0, (a0), v0.t	# vd overlap vm
++	vlseg6e512.v v4, (a0), v0.t	# OK
++	vsseg6e512.v v0, (a0), v0.t	# OK
++	vsseg6e512.v v4, (a0), v0.t	# OK
++	vlseg6e512ff.v v0, (a0), v0.t	# vd overlap vm
++	vlseg6e512ff.v v4, (a0), v0.t	# OK
++	vlseg7e512.v v0, (a0), v0.t	# vd overlap vm
++	vlseg7e512.v v4, (a0), v0.t	# OK
++	vsseg7e512.v v0, (a0), v0.t	# OK
++	vsseg7e512.v v4, (a0), v0.t	# OK
++	vlseg7e512ff.v v0, (a0), v0.t	# vd overlap vm
++	vlseg7e512ff.v v4, (a0), v0.t	# OK
++	vlseg8e512.v v0, (a0), v0.t	# vd overlap vm
++	vlseg8e512.v v4, (a0), v0.t	# OK
++	vsseg8e512.v v0, (a0), v0.t	# OK
++	vsseg8e512.v v4, (a0), v0.t	# OK
++	vlseg8e512ff.v v0, (a0), v0.t	# vd overlap vm
++	vlseg8e512ff.v v4, (a0), v0.t	# OK
++
++	vlseg2e1024.v v0, (a0), v0.t	# vd overlap vm
++	vlseg2e1024.v v4, (a0), v0.t	# OK
++	vsseg2e1024.v v0, (a0), v0.t	# OK
++	vsseg2e1024.v v4, (a0), v0.t	# OK
++	vlseg2e1024ff.v v0, (a0), v0.t	# vd overlap vm
++	vlseg2e1024ff.v v4, (a0), v0.t	# OK
++	vlseg3e1024.v v0, (a0), v0.t	# vd overlap vm
++	vlseg3e1024.v v4, (a0), v0.t	# OK
++	vsseg3e1024.v v0, (a0), v0.t	# OK
++	vsseg3e1024.v v4, (a0), v0.t	# OK
++	vlseg3e1024ff.v v0, (a0), v0.t	# vd overlap vm
++	vlseg3e1024ff.v v4, (a0), v0.t	# OK
++	vlseg4e1024.v v0, (a0), v0.t	# vd overlap vm
++	vlseg4e1024.v v4, (a0), v0.t	# OK
++	vsseg4e1024.v v0, (a0), v0.t	# OK
++	vsseg4e1024.v v4, (a0), v0.t	# OK
++	vlseg4e1024ff.v v0, (a0), v0.t	# vd overlap vm
++	vlseg4e1024ff.v v4, (a0), v0.t	# OK
++	vlseg5e1024.v v0, (a0), v0.t	# vd overlap vm
++	vlseg5e1024.v v4, (a0), v0.t	# OK
++	vsseg5e1024.v v0, (a0), v0.t	# OK
++	vsseg5e1024.v v4, (a0), v0.t	# OK
++	vlseg5e1024ff.v v0, (a0), v0.t	# vd overlap vm
++	vlseg5e1024ff.v v4, (a0), v0.t	# OK
++	vlseg6e1024.v v0, (a0), v0.t	# vd overlap vm
++	vlseg6e1024.v v4, (a0), v0.t	# OK
++	vsseg6e1024.v v0, (a0), v0.t	# OK
++	vsseg6e1024.v v4, (a0), v0.t	# OK
++	vlseg6e1024ff.v v0, (a0), v0.t	# vd overlap vm
++	vlseg6e1024ff.v v4, (a0), v0.t	# OK
++	vlseg7e1024.v v0, (a0), v0.t	# vd overlap vm
++	vlseg7e1024.v v4, (a0), v0.t	# OK
++	vsseg7e1024.v v0, (a0), v0.t	# OK
++	vsseg7e1024.v v4, (a0), v0.t	# OK
++	vlseg7e1024ff.v v0, (a0), v0.t	# vd overlap vm
++	vlseg7e1024ff.v v4, (a0), v0.t	# OK
++	vlseg8e1024.v v0, (a0), v0.t	# vd overlap vm
++	vlseg8e1024.v v4, (a0), v0.t	# OK
++	vsseg8e1024.v v0, (a0), v0.t	# OK
++	vsseg8e1024.v v4, (a0), v0.t	# OK
++	vlseg8e1024ff.v v0, (a0), v0.t	# vd overlap vm
++	vlseg8e1024ff.v v4, (a0), v0.t	# OK
++
++# Vector Strided Segment Loads and Stores
++
++	vlsseg2e8.v v0, (a0), a1, v0.t	# vd overlap vm
++	vlsseg2e8.v v4, (a0), a1, v0.t	# OK
++	vssseg2e8.v v0, (a0), a1, v0.t	# vd overlap vm
++	vssseg2e8.v v4, (a0), a1, v0.t	# OK
++	vlsseg3e8.v v0, (a0), a1, v0.t	# vd overlap vm
++	vlsseg3e8.v v4, (a0), a1, v0.t	# OK
++	vssseg3e8.v v0, (a0), a1, v0.t	# vd overlap vm
++	vssseg3e8.v v4, (a0), a1, v0.t	# OK
++	vlsseg4e8.v v0, (a0), a1, v0.t	# vd overlap vm
++	vlsseg4e8.v v4, (a0), a1, v0.t	# OK
++	vssseg4e8.v v0, (a0), a1, v0.t	# vd overlap vm
++	vssseg4e8.v v4, (a0), a1, v0.t	# OK
++	vlsseg5e8.v v0, (a0), a1, v0.t	# vd overlap vm
++	vlsseg5e8.v v4, (a0), a1, v0.t	# OK
++	vssseg5e8.v v0, (a0), a1, v0.t	# vd overlap vm
++	vssseg5e8.v v4, (a0), a1, v0.t	# OK
++	vlsseg6e8.v v0, (a0), a1, v0.t	# vd overlap vm
++	vlsseg6e8.v v4, (a0), a1, v0.t	# OK
++	vssseg6e8.v v0, (a0), a1, v0.t	# vd overlap vm
++	vssseg6e8.v v4, (a0), a1, v0.t	# OK
++	vlsseg7e8.v v0, (a0), a1, v0.t	# vd overlap vm
++	vlsseg7e8.v v4, (a0), a1, v0.t	# OK
++	vssseg7e8.v v0, (a0), a1, v0.t	# vd overlap vm
++	vssseg7e8.v v4, (a0), a1, v0.t	# OK
++	vlsseg8e8.v v0, (a0), a1, v0.t	# vd overlap vm
++	vlsseg8e8.v v4, (a0), a1, v0.t	# OK
++	vssseg8e8.v v0, (a0), a1, v0.t	# vd overlap vm
++	vssseg8e8.v v4, (a0), a1, v0.t	# OK
++
++	vlsseg2e16.v v0, (a0), a1, v0.t	# vd overlap vm
++	vlsseg2e16.v v4, (a0), a1, v0.t	# OK
++	vssseg2e16.v v0, (a0), a1, v0.t	# vd overlap vm
++	vssseg2e16.v v4, (a0), a1, v0.t	# OK
++	vlsseg3e16.v v0, (a0), a1, v0.t	# vd overlap vm
++	vlsseg3e16.v v4, (a0), a1, v0.t	# OK
++	vssseg3e16.v v0, (a0), a1, v0.t	# vd overlap vm
++	vssseg3e16.v v4, (a0), a1, v0.t	# OK
++	vlsseg4e16.v v0, (a0), a1, v0.t	# vd overlap vm
++	vlsseg4e16.v v4, (a0), a1, v0.t	# OK
++	vssseg4e16.v v0, (a0), a1, v0.t	# vd overlap vm
++	vssseg4e16.v v4, (a0), a1, v0.t	# OK
++	vlsseg5e16.v v0, (a0), a1, v0.t	# vd overlap vm
++	vlsseg5e16.v v4, (a0), a1, v0.t	# OK
++	vssseg5e16.v v0, (a0), a1, v0.t	# vd overlap vm
++	vssseg5e16.v v4, (a0), a1, v0.t	# OK
++	vlsseg6e16.v v0, (a0), a1, v0.t	# vd overlap vm
++	vlsseg6e16.v v4, (a0), a1, v0.t	# OK
++	vssseg6e16.v v0, (a0), a1, v0.t	# vd overlap vm
++	vssseg6e16.v v4, (a0), a1, v0.t	# OK
++	vlsseg7e16.v v0, (a0), a1, v0.t	# vd overlap vm
++	vlsseg7e16.v v4, (a0), a1, v0.t	# OK
++	vssseg7e16.v v0, (a0), a1, v0.t	# vd overlap vm
++	vssseg7e16.v v4, (a0), a1, v0.t	# OK
++	vlsseg8e16.v v0, (a0), a1, v0.t	# vd overlap vm
++	vlsseg8e16.v v4, (a0), a1, v0.t	# OK
++	vssseg8e16.v v0, (a0), a1, v0.t	# vd overlap vm
++	vssseg8e16.v v4, (a0), a1, v0.t	# OK
++
++	vlsseg2e32.v v0, (a0), a1, v0.t	# vd overlap vm
++	vlsseg2e32.v v4, (a0), a1, v0.t	# OK
++	vssseg2e32.v v0, (a0), a1, v0.t	# vd overlap vm
++	vssseg2e32.v v4, (a0), a1, v0.t	# OK
++	vlsseg3e32.v v0, (a0), a1, v0.t	# vd overlap vm
++	vlsseg3e32.v v4, (a0), a1, v0.t	# OK
++	vssseg3e32.v v0, (a0), a1, v0.t	# vd overlap vm
++	vssseg3e32.v v4, (a0), a1, v0.t	# OK
++	vlsseg4e32.v v0, (a0), a1, v0.t	# vd overlap vm
++	vlsseg4e32.v v4, (a0), a1, v0.t	# OK
++	vssseg4e32.v v0, (a0), a1, v0.t	# vd overlap vm
++	vssseg4e32.v v4, (a0), a1, v0.t	# OK
++	vlsseg5e32.v v0, (a0), a1, v0.t	# vd overlap vm
++	vlsseg5e32.v v4, (a0), a1, v0.t	# OK
++	vssseg5e32.v v0, (a0), a1, v0.t	# vd overlap vm
++	vssseg5e32.v v4, (a0), a1, v0.t	# OK
++	vlsseg6e32.v v0, (a0), a1, v0.t	# vd overlap vm
++	vlsseg6e32.v v4, (a0), a1, v0.t	# OK
++	vssseg6e32.v v0, (a0), a1, v0.t	# vd overlap vm
++	vssseg6e32.v v4, (a0), a1, v0.t	# OK
++	vlsseg7e32.v v0, (a0), a1, v0.t	# vd overlap vm
++	vlsseg7e32.v v4, (a0), a1, v0.t	# OK
++	vssseg7e32.v v0, (a0), a1, v0.t	# vd overlap vm
++	vssseg7e32.v v4, (a0), a1, v0.t	# OK
++	vlsseg8e32.v v0, (a0), a1, v0.t	# vd overlap vm
++	vlsseg8e32.v v4, (a0), a1, v0.t	# OK
++	vssseg8e32.v v0, (a0), a1, v0.t	# vd overlap vm
++	vssseg8e32.v v4, (a0), a1, v0.t	# OK
++
++	vlsseg2e64.v v0, (a0), a1, v0.t	# vd overlap vm
++	vlsseg2e64.v v4, (a0), a1, v0.t	# OK
++	vssseg2e64.v v0, (a0), a1, v0.t	# vd overlap vm
++	vssseg2e64.v v4, (a0), a1, v0.t	# OK
++	vlsseg3e64.v v0, (a0), a1, v0.t	# vd overlap vm
++	vlsseg3e64.v v4, (a0), a1, v0.t	# OK
++	vssseg3e64.v v0, (a0), a1, v0.t	# vd overlap vm
++	vssseg3e64.v v4, (a0), a1, v0.t	# OK
++	vlsseg4e64.v v0, (a0), a1, v0.t	# vd overlap vm
++	vlsseg4e64.v v4, (a0), a1, v0.t	# OK
++	vssseg4e64.v v0, (a0), a1, v0.t	# vd overlap vm
++	vssseg4e64.v v4, (a0), a1, v0.t	# OK
++	vlsseg5e64.v v0, (a0), a1, v0.t	# vd overlap vm
++	vlsseg5e64.v v4, (a0), a1, v0.t	# OK
++	vssseg5e64.v v0, (a0), a1, v0.t	# vd overlap vm
++	vssseg5e64.v v4, (a0), a1, v0.t	# OK
++	vlsseg6e64.v v0, (a0), a1, v0.t	# vd overlap vm
++	vlsseg6e64.v v4, (a0), a1, v0.t	# OK
++	vssseg6e64.v v0, (a0), a1, v0.t	# vd overlap vm
++	vssseg6e64.v v4, (a0), a1, v0.t	# OK
++	vlsseg7e64.v v0, (a0), a1, v0.t	# vd overlap vm
++	vlsseg7e64.v v4, (a0), a1, v0.t	# OK
++	vssseg7e64.v v0, (a0), a1, v0.t	# vd overlap vm
++	vssseg7e64.v v4, (a0), a1, v0.t	# OK
++	vlsseg8e64.v v0, (a0), a1, v0.t	# vd overlap vm
++	vlsseg8e64.v v4, (a0), a1, v0.t	# OK
++	vssseg8e64.v v0, (a0), a1, v0.t	# vd overlap vm
++	vssseg8e64.v v4, (a0), a1, v0.t	# OK
++
++	vlsseg2e128.v v0, (a0), a1, v0.t	# vd overlap vm
++	vlsseg2e128.v v4, (a0), a1, v0.t	# OK
++	vssseg2e128.v v0, (a0), a1, v0.t	# vd overlap vm
++	vssseg2e128.v v4, (a0), a1, v0.t	# OK
++	vlsseg3e128.v v0, (a0), a1, v0.t	# vd overlap vm
++	vlsseg3e128.v v4, (a0), a1, v0.t	# OK
++	vssseg3e128.v v0, (a0), a1, v0.t	# vd overlap vm
++	vssseg3e128.v v4, (a0), a1, v0.t	# OK
++	vlsseg4e128.v v0, (a0), a1, v0.t	# vd overlap vm
++	vlsseg4e128.v v4, (a0), a1, v0.t	# OK
++	vssseg4e128.v v0, (a0), a1, v0.t	# vd overlap vm
++	vssseg4e128.v v4, (a0), a1, v0.t	# OK
++	vlsseg5e128.v v0, (a0), a1, v0.t	# vd overlap vm
++	vlsseg5e128.v v4, (a0), a1, v0.t	# OK
++	vssseg5e128.v v0, (a0), a1, v0.t	# vd overlap vm
++	vssseg5e128.v v4, (a0), a1, v0.t	# OK
++	vlsseg6e128.v v0, (a0), a1, v0.t	# vd overlap vm
++	vlsseg6e128.v v4, (a0), a1, v0.t	# OK
++	vssseg6e128.v v0, (a0), a1, v0.t	# vd overlap vm
++	vssseg6e128.v v4, (a0), a1, v0.t	# OK
++	vlsseg7e128.v v0, (a0), a1, v0.t	# vd overlap vm
++	vlsseg7e128.v v4, (a0), a1, v0.t	# OK
++	vssseg7e128.v v0, (a0), a1, v0.t	# vd overlap vm
++	vssseg7e128.v v4, (a0), a1, v0.t	# OK
++	vlsseg8e128.v v0, (a0), a1, v0.t	# vd overlap vm
++	vlsseg8e128.v v4, (a0), a1, v0.t	# OK
++	vssseg8e128.v v0, (a0), a1, v0.t	# vd overlap vm
++	vssseg8e128.v v4, (a0), a1, v0.t	# OK
++
++	vlsseg2e256.v v0, (a0), a1, v0.t	# vd overlap vm
++	vlsseg2e256.v v4, (a0), a1, v0.t	# OK
++	vssseg2e256.v v0, (a0), a1, v0.t	# vd overlap vm
++	vssseg2e256.v v4, (a0), a1, v0.t	# OK
++	vlsseg3e256.v v0, (a0), a1, v0.t	# vd overlap vm
++	vlsseg3e256.v v4, (a0), a1, v0.t	# OK
++	vssseg3e256.v v0, (a0), a1, v0.t	# vd overlap vm
++	vssseg3e256.v v4, (a0), a1, v0.t	# OK
++	vlsseg4e256.v v0, (a0), a1, v0.t	# vd overlap vm
++	vlsseg4e256.v v4, (a0), a1, v0.t	# OK
++	vssseg4e256.v v0, (a0), a1, v0.t	# vd overlap vm
++	vssseg4e256.v v4, (a0), a1, v0.t	# OK
++	vlsseg5e256.v v0, (a0), a1, v0.t	# vd overlap vm
++	vlsseg5e256.v v4, (a0), a1, v0.t	# OK
++	vssseg5e256.v v0, (a0), a1, v0.t	# vd overlap vm
++	vssseg5e256.v v4, (a0), a1, v0.t	# OK
++	vlsseg6e256.v v0, (a0), a1, v0.t	# vd overlap vm
++	vlsseg6e256.v v4, (a0), a1, v0.t	# OK
++	vssseg6e256.v v0, (a0), a1, v0.t	# vd overlap vm
++	vssseg6e256.v v4, (a0), a1, v0.t	# OK
++	vlsseg7e256.v v0, (a0), a1, v0.t	# vd overlap vm
++	vlsseg7e256.v v4, (a0), a1, v0.t	# OK
++	vssseg7e256.v v0, (a0), a1, v0.t	# vd overlap vm
++	vssseg7e256.v v4, (a0), a1, v0.t	# OK
++	vlsseg8e256.v v0, (a0), a1, v0.t	# vd overlap vm
++	vlsseg8e256.v v4, (a0), a1, v0.t	# OK
++	vssseg8e256.v v0, (a0), a1, v0.t	# vd overlap vm
++	vssseg8e256.v v4, (a0), a1, v0.t	# OK
++
++	vlsseg2e512.v v0, (a0), a1, v0.t	# vd overlap vm
++	vlsseg2e512.v v4, (a0), a1, v0.t	# OK
++	vssseg2e512.v v0, (a0), a1, v0.t	# vd overlap vm
++	vssseg2e512.v v4, (a0), a1, v0.t	# OK
++	vlsseg3e512.v v0, (a0), a1, v0.t	# vd overlap vm
++	vlsseg3e512.v v4, (a0), a1, v0.t	# OK
++	vssseg3e512.v v0, (a0), a1, v0.t	# vd overlap vm
++	vssseg3e512.v v4, (a0), a1, v0.t	# OK
++	vlsseg4e512.v v0, (a0), a1, v0.t	# vd overlap vm
++	vlsseg4e512.v v4, (a0), a1, v0.t	# OK
++	vssseg4e512.v v0, (a0), a1, v0.t	# vd overlap vm
++	vssseg4e512.v v4, (a0), a1, v0.t	# OK
++	vlsseg5e512.v v0, (a0), a1, v0.t	# vd overlap vm
++	vlsseg5e512.v v4, (a0), a1, v0.t	# OK
++	vssseg5e512.v v0, (a0), a1, v0.t	# vd overlap vm
++	vssseg5e512.v v4, (a0), a1, v0.t	# OK
++	vlsseg6e512.v v0, (a0), a1, v0.t	# vd overlap vm
++	vlsseg6e512.v v4, (a0), a1, v0.t	# OK
++	vssseg6e512.v v0, (a0), a1, v0.t	# vd overlap vm
++	vssseg6e512.v v4, (a0), a1, v0.t	# OK
++	vlsseg7e512.v v0, (a0), a1, v0.t	# vd overlap vm
++	vlsseg7e512.v v4, (a0), a1, v0.t	# OK
++	vssseg7e512.v v0, (a0), a1, v0.t	# vd overlap vm
++	vssseg7e512.v v4, (a0), a1, v0.t	# OK
++	vlsseg8e512.v v0, (a0), a1, v0.t	# vd overlap vm
++	vlsseg8e512.v v4, (a0), a1, v0.t	# OK
++	vssseg8e512.v v0, (a0), a1, v0.t	# vd overlap vm
++	vssseg8e512.v v4, (a0), a1, v0.t	# OK
++
++	vlsseg2e1024.v v0, (a0), a1, v0.t	# vd overlap vm
++	vlsseg2e1024.v v4, (a0), a1, v0.t	# OK
++	vssseg2e1024.v v0, (a0), a1, v0.t	# vd overlap vm
++	vssseg2e1024.v v4, (a0), a1, v0.t	# OK
++	vlsseg3e1024.v v0, (a0), a1, v0.t	# vd overlap vm
++	vlsseg3e1024.v v4, (a0), a1, v0.t	# OK
++	vssseg3e1024.v v0, (a0), a1, v0.t	# vd overlap vm
++	vssseg3e1024.v v4, (a0), a1, v0.t	# OK
++	vlsseg4e1024.v v0, (a0), a1, v0.t	# vd overlap vm
++	vlsseg4e1024.v v4, (a0), a1, v0.t	# OK
++	vssseg4e1024.v v0, (a0), a1, v0.t	# vd overlap vm
++	vssseg4e1024.v v4, (a0), a1, v0.t	# OK
++	vlsseg5e1024.v v0, (a0), a1, v0.t	# vd overlap vm
++	vlsseg5e1024.v v4, (a0), a1, v0.t	# OK
++	vssseg5e1024.v v0, (a0), a1, v0.t	# vd overlap vm
++	vssseg5e1024.v v4, (a0), a1, v0.t	# OK
++	vlsseg6e1024.v v0, (a0), a1, v0.t	# vd overlap vm
++	vlsseg6e1024.v v4, (a0), a1, v0.t	# OK
++	vssseg6e1024.v v0, (a0), a1, v0.t	# vd overlap vm
++	vssseg6e1024.v v4, (a0), a1, v0.t	# OK
++	vlsseg7e1024.v v0, (a0), a1, v0.t	# vd overlap vm
++	vlsseg7e1024.v v4, (a0), a1, v0.t	# OK
++	vssseg7e1024.v v0, (a0), a1, v0.t	# vd overlap vm
++	vssseg7e1024.v v4, (a0), a1, v0.t	# OK
++	vlsseg8e1024.v v0, (a0), a1, v0.t	# vd overlap vm
++	vlsseg8e1024.v v4, (a0), a1, v0.t	# OK
++	vssseg8e1024.v v0, (a0), a1, v0.t	# vd overlap vm
++	vssseg8e1024.v v4, (a0), a1, v0.t	# OK
++
++# Vector Indexed Segment Loads and Stores
++
++	vlxseg2ei8.v v0, (a0), v2		# OK
++	vlxseg2ei8.v v1, (a0), v2		# OK
++	vlxseg2ei8.v v2, (a0), v2		# vd overlap vs2
++	vlxseg2ei8.v v0, (a0), v2, v0.t		# vd overlap vm
++	vsxseg2ei8.v v0, (a0), v2
++	vsxseg2ei8.v v1, (a0), v2
++	vsxseg2ei8.v v2, (a0), v2
++	vsxseg2ei8.v v0, (a0), v2, v0.t
++	vlxseg3ei8.v v0, (a0), v2
++	vlxseg3ei8.v v1, (a0), v2
++	vlxseg3ei8.v v2, (a0), v2
++	vlxseg3ei8.v v0, (a0), v2, v0.t
++	vsxseg3ei8.v v0, (a0), v2
++	vsxseg3ei8.v v1, (a0), v2
++	vsxseg3ei8.v v2, (a0), v2
++	vsxseg3ei8.v v0, (a0), v2, v0.t
++	vlxseg4ei8.v v0, (a0), v2
++	vlxseg4ei8.v v1, (a0), v2
++	vlxseg4ei8.v v2, (a0), v2
++	vlxseg4ei8.v v0, (a0), v2, v0.t
++	vsxseg4ei8.v v0, (a0), v2
++	vsxseg4ei8.v v1, (a0), v2
++	vsxseg4ei8.v v2, (a0), v2
++	vsxseg4ei8.v v0, (a0), v2, v0.t
++	vlxseg5ei8.v v0, (a0), v2
++	vlxseg5ei8.v v1, (a0), v2
++	vlxseg5ei8.v v2, (a0), v2
++	vlxseg5ei8.v v0, (a0), v2, v0.t
++	vsxseg5ei8.v v0, (a0), v2
++	vsxseg5ei8.v v1, (a0), v2
++	vsxseg5ei8.v v2, (a0), v2
++	vsxseg5ei8.v v0, (a0), v2, v0.t
++	vlxseg6ei8.v v0, (a0), v2
++	vlxseg6ei8.v v1, (a0), v2
++	vlxseg6ei8.v v2, (a0), v2
++	vlxseg6ei8.v v0, (a0), v2, v0.t
++	vsxseg6ei8.v v0, (a0), v2
++	vsxseg6ei8.v v1, (a0), v2
++	vsxseg6ei8.v v2, (a0), v2
++	vsxseg6ei8.v v0, (a0), v2, v0.t
++	vlxseg7ei8.v v0, (a0), v2
++	vlxseg7ei8.v v1, (a0), v2
++	vlxseg7ei8.v v2, (a0), v2
++	vlxseg7ei8.v v0, (a0), v2, v0.t
++	vsxseg7ei8.v v0, (a0), v2
++	vsxseg7ei8.v v1, (a0), v2
++	vsxseg7ei8.v v2, (a0), v2
++	vsxseg7ei8.v v0, (a0), v2, v0.t
++	vlxseg8ei8.v v0, (a0), v2
++	vlxseg8ei8.v v1, (a0), v2
++	vlxseg8ei8.v v2, (a0), v2
++	vlxseg8ei8.v v0, (a0), v2, v0.t
++	vsxseg8ei8.v v0, (a0), v2
++	vsxseg8ei8.v v1, (a0), v2
++	vsxseg8ei8.v v2, (a0), v2
++	vsxseg8ei8.v v0, (a0), v2, v0.t
++
++	vlxseg2ei16.v v0, (a0), v2		# OK
++	vlxseg2ei16.v v1, (a0), v2		# OK
++	vlxseg2ei16.v v2, (a0), v2		# vd overlap vs2
++	vlxseg2ei16.v v0, (a0), v2, v0.t	# vd overlap vm
++	vsxseg2ei16.v v0, (a0), v2
++	vsxseg2ei16.v v1, (a0), v2
++	vsxseg2ei16.v v2, (a0), v2
++	vsxseg2ei16.v v0, (a0), v2, v0.t
++	vlxseg3ei16.v v0, (a0), v2
++	vlxseg3ei16.v v1, (a0), v2
++	vlxseg3ei16.v v2, (a0), v2
++	vlxseg3ei16.v v0, (a0), v2, v0.t
++	vsxseg3ei16.v v0, (a0), v2
++	vsxseg3ei16.v v1, (a0), v2
++	vsxseg3ei16.v v2, (a0), v2
++	vsxseg3ei16.v v0, (a0), v2, v0.t
++	vlxseg4ei16.v v0, (a0), v2
++	vlxseg4ei16.v v1, (a0), v2
++	vlxseg4ei16.v v2, (a0), v2
++	vlxseg4ei16.v v0, (a0), v2, v0.t
++	vsxseg4ei16.v v0, (a0), v2
++	vsxseg4ei16.v v1, (a0), v2
++	vsxseg4ei16.v v2, (a0), v2
++	vsxseg4ei16.v v0, (a0), v2, v0.t
++	vlxseg5ei16.v v0, (a0), v2
++	vlxseg5ei16.v v1, (a0), v2
++	vlxseg5ei16.v v2, (a0), v2
++	vlxseg5ei16.v v0, (a0), v2, v0.t
++	vsxseg5ei16.v v0, (a0), v2
++	vsxseg5ei16.v v1, (a0), v2
++	vsxseg5ei16.v v2, (a0), v2
++	vsxseg5ei16.v v0, (a0), v2, v0.t
++	vlxseg6ei16.v v0, (a0), v2
++	vlxseg6ei16.v v1, (a0), v2
++	vlxseg6ei16.v v2, (a0), v2
++	vlxseg6ei16.v v0, (a0), v2, v0.t
++	vsxseg6ei16.v v0, (a0), v2
++	vsxseg6ei16.v v1, (a0), v2
++	vsxseg6ei16.v v2, (a0), v2
++	vsxseg6ei16.v v0, (a0), v2, v0.t
++	vlxseg7ei16.v v0, (a0), v2
++	vlxseg7ei16.v v1, (a0), v2
++	vlxseg7ei16.v v2, (a0), v2
++	vlxseg7ei16.v v0, (a0), v2, v0.t
++	vsxseg7ei16.v v0, (a0), v2
++	vsxseg7ei16.v v1, (a0), v2
++	vsxseg7ei16.v v2, (a0), v2
++	vsxseg7ei16.v v0, (a0), v2, v0.t
++	vlxseg8ei16.v v0, (a0), v2
++	vlxseg8ei16.v v1, (a0), v2
++	vlxseg8ei16.v v2, (a0), v2
++	vlxseg8ei16.v v0, (a0), v2, v0.t
++	vsxseg8ei16.v v0, (a0), v2
++	vsxseg8ei16.v v1, (a0), v2
++	vsxseg8ei16.v v2, (a0), v2
++	vsxseg8ei16.v v0, (a0), v2, v0.t
++
++	vlxseg2ei32.v v0, (a0), v2		# OK
++	vlxseg2ei32.v v1, (a0), v2		# OK
++	vlxseg2ei32.v v2, (a0), v2		# vd overlap vs2
++	vlxseg2ei32.v v0, (a0), v2, v0.t	# vd overlap vm
++	vsxseg2ei32.v v0, (a0), v2
++	vsxseg2ei32.v v1, (a0), v2
++	vsxseg2ei32.v v2, (a0), v2
++	vsxseg2ei32.v v0, (a0), v2, v0.t
++	vlxseg3ei32.v v0, (a0), v2
++	vlxseg3ei32.v v1, (a0), v2
++	vlxseg3ei32.v v2, (a0), v2
++	vlxseg3ei32.v v0, (a0), v2, v0.t
++	vsxseg3ei32.v v0, (a0), v2
++	vsxseg3ei32.v v1, (a0), v2
++	vsxseg3ei32.v v2, (a0), v2
++	vsxseg3ei32.v v0, (a0), v2, v0.t
++	vlxseg4ei32.v v0, (a0), v2
++	vlxseg4ei32.v v1, (a0), v2
++	vlxseg4ei32.v v2, (a0), v2
++	vlxseg4ei32.v v0, (a0), v2, v0.t
++	vsxseg4ei32.v v0, (a0), v2
++	vsxseg4ei32.v v1, (a0), v2
++	vsxseg4ei32.v v2, (a0), v2
++	vsxseg4ei32.v v0, (a0), v2, v0.t
++	vlxseg5ei32.v v0, (a0), v2
++	vlxseg5ei32.v v1, (a0), v2
++	vlxseg5ei32.v v2, (a0), v2
++	vlxseg5ei32.v v0, (a0), v2, v0.t
++	vsxseg5ei32.v v0, (a0), v2
++	vsxseg5ei32.v v1, (a0), v2
++	vsxseg5ei32.v v2, (a0), v2
++	vsxseg5ei32.v v0, (a0), v2, v0.t
++	vlxseg6ei32.v v0, (a0), v2
++	vlxseg6ei32.v v1, (a0), v2
++	vlxseg6ei32.v v2, (a0), v2
++	vlxseg6ei32.v v0, (a0), v2, v0.t
++	vsxseg6ei32.v v0, (a0), v2
++	vsxseg6ei32.v v1, (a0), v2
++	vsxseg6ei32.v v2, (a0), v2
++	vsxseg6ei32.v v0, (a0), v2, v0.t
++	vlxseg7ei32.v v0, (a0), v2
++	vlxseg7ei32.v v1, (a0), v2
++	vlxseg7ei32.v v2, (a0), v2
++	vlxseg7ei32.v v0, (a0), v2, v0.t
++	vsxseg7ei32.v v0, (a0), v2
++	vsxseg7ei32.v v1, (a0), v2
++	vsxseg7ei32.v v2, (a0), v2
++	vsxseg7ei32.v v0, (a0), v2, v0.t
++	vlxseg8ei32.v v0, (a0), v2
++	vlxseg8ei32.v v1, (a0), v2
++	vlxseg8ei32.v v2, (a0), v2
++	vlxseg8ei32.v v0, (a0), v2, v0.t
++	vsxseg8ei32.v v0, (a0), v2
++	vsxseg8ei32.v v1, (a0), v2
++	vsxseg8ei32.v v2, (a0), v2
++	vsxseg8ei32.v v0, (a0), v2, v0.t
++
++	vlxseg2ei64.v v0, (a0), v2		# OK
++	vlxseg2ei64.v v1, (a0), v2		# OK
++	vlxseg2ei64.v v2, (a0), v2		# vd overlap vs2
++	vlxseg2ei64.v v0, (a0), v2, v0.t	# vd overlap vm
++	vsxseg2ei64.v v0, (a0), v2
++	vsxseg2ei64.v v1, (a0), v2
++	vsxseg2ei64.v v2, (a0), v2
++	vsxseg2ei64.v v0, (a0), v2, v0.t
++	vlxseg3ei64.v v0, (a0), v2
++	vlxseg3ei64.v v1, (a0), v2
++	vlxseg3ei64.v v2, (a0), v2
++	vlxseg3ei64.v v0, (a0), v2, v0.t
++	vsxseg3ei64.v v0, (a0), v2
++	vsxseg3ei64.v v1, (a0), v2
++	vsxseg3ei64.v v2, (a0), v2
++	vsxseg3ei64.v v0, (a0), v2, v0.t
++	vlxseg4ei64.v v0, (a0), v2
++	vlxseg4ei64.v v1, (a0), v2
++	vlxseg4ei64.v v2, (a0), v2
++	vlxseg4ei64.v v0, (a0), v2, v0.t
++	vsxseg4ei64.v v0, (a0), v2
++	vsxseg4ei64.v v1, (a0), v2
++	vsxseg4ei64.v v2, (a0), v2
++	vsxseg4ei64.v v0, (a0), v2, v0.t
++	vlxseg5ei64.v v0, (a0), v2
++	vlxseg5ei64.v v1, (a0), v2
++	vlxseg5ei64.v v2, (a0), v2
++	vlxseg5ei64.v v0, (a0), v2, v0.t
++	vsxseg5ei64.v v0, (a0), v2
++	vsxseg5ei64.v v1, (a0), v2
++	vsxseg5ei64.v v2, (a0), v2
++	vsxseg5ei64.v v0, (a0), v2, v0.t
++	vlxseg6ei64.v v0, (a0), v2
++	vlxseg6ei64.v v1, (a0), v2
++	vlxseg6ei64.v v2, (a0), v2
++	vlxseg6ei64.v v0, (a0), v2, v0.t
++	vsxseg6ei64.v v0, (a0), v2
++	vsxseg6ei64.v v1, (a0), v2
++	vsxseg6ei64.v v2, (a0), v2
++	vsxseg6ei64.v v0, (a0), v2, v0.t
++	vlxseg7ei64.v v0, (a0), v2
++	vlxseg7ei64.v v1, (a0), v2
++	vlxseg7ei64.v v2, (a0), v2
++	vlxseg7ei64.v v0, (a0), v2, v0.t
++	vsxseg7ei64.v v0, (a0), v2
++	vsxseg7ei64.v v1, (a0), v2
++	vsxseg7ei64.v v2, (a0), v2
++	vsxseg7ei64.v v0, (a0), v2, v0.t
++	vlxseg8ei64.v v0, (a0), v2
++	vlxseg8ei64.v v1, (a0), v2
++	vlxseg8ei64.v v2, (a0), v2
++	vlxseg8ei64.v v0, (a0), v2, v0.t
++	vsxseg8ei64.v v0, (a0), v2
++	vsxseg8ei64.v v1, (a0), v2
++	vsxseg8ei64.v v2, (a0), v2
++	vsxseg8ei64.v v0, (a0), v2, v0.t
++
++	vlxseg2ei128.v v0, (a0), v2		# OK
++	vlxseg2ei128.v v1, (a0), v2		# OK
++	vlxseg2ei128.v v2, (a0), v2		# vd overlap vs2
++	vlxseg2ei128.v v0, (a0), v2, v0.t	# vd overlap vm
++	vsxseg2ei128.v v0, (a0), v2
++	vsxseg2ei128.v v1, (a0), v2
++	vsxseg2ei128.v v2, (a0), v2
++	vsxseg2ei128.v v0, (a0), v2, v0.t
++	vlxseg3ei128.v v0, (a0), v2
++	vlxseg3ei128.v v1, (a0), v2
++	vlxseg3ei128.v v2, (a0), v2
++	vlxseg3ei128.v v0, (a0), v2, v0.t
++	vsxseg3ei128.v v0, (a0), v2
++	vsxseg3ei128.v v1, (a0), v2
++	vsxseg3ei128.v v2, (a0), v2
++	vsxseg3ei128.v v0, (a0), v2, v0.t
++	vlxseg4ei128.v v0, (a0), v2
++	vlxseg4ei128.v v1, (a0), v2
++	vlxseg4ei128.v v2, (a0), v2
++	vlxseg4ei128.v v0, (a0), v2, v0.t
++	vsxseg4ei128.v v0, (a0), v2
++	vsxseg4ei128.v v1, (a0), v2
++	vsxseg4ei128.v v2, (a0), v2
++	vsxseg4ei128.v v0, (a0), v2, v0.t
++	vlxseg5ei128.v v0, (a0), v2
++	vlxseg5ei128.v v1, (a0), v2
++	vlxseg5ei128.v v2, (a0), v2
++	vlxseg5ei128.v v0, (a0), v2, v0.t
++	vsxseg5ei128.v v0, (a0), v2
++	vsxseg5ei128.v v1, (a0), v2
++	vsxseg5ei128.v v2, (a0), v2
++	vsxseg5ei128.v v0, (a0), v2, v0.t
++	vlxseg6ei128.v v0, (a0), v2
++	vlxseg6ei128.v v1, (a0), v2
++	vlxseg6ei128.v v2, (a0), v2
++	vlxseg6ei128.v v0, (a0), v2, v0.t
++	vsxseg6ei128.v v0, (a0), v2
++	vsxseg6ei128.v v1, (a0), v2
++	vsxseg6ei128.v v2, (a0), v2
++	vsxseg6ei128.v v0, (a0), v2, v0.t
++	vlxseg7ei128.v v0, (a0), v2
++	vlxseg7ei128.v v1, (a0), v2
++	vlxseg7ei128.v v2, (a0), v2
++	vlxseg7ei128.v v0, (a0), v2, v0.t
++	vsxseg7ei128.v v0, (a0), v2
++	vsxseg7ei128.v v1, (a0), v2
++	vsxseg7ei128.v v2, (a0), v2
++	vsxseg7ei128.v v0, (a0), v2, v0.t
++	vlxseg8ei128.v v0, (a0), v2
++	vlxseg8ei128.v v1, (a0), v2
++	vlxseg8ei128.v v2, (a0), v2
++	vlxseg8ei128.v v0, (a0), v2, v0.t
++	vsxseg8ei128.v v0, (a0), v2
++	vsxseg8ei128.v v1, (a0), v2
++	vsxseg8ei128.v v2, (a0), v2
++	vsxseg8ei128.v v0, (a0), v2, v0.t
++
++	vlxseg2ei256.v v0, (a0), v2		# OK
++	vlxseg2ei256.v v1, (a0), v2		# OK
++	vlxseg2ei256.v v2, (a0), v2		# vd overlap vs2
++	vlxseg2ei256.v v0, (a0), v2, v0.t	# vd overlap vm
++	vsxseg2ei256.v v0, (a0), v2
++	vsxseg2ei256.v v1, (a0), v2
++	vsxseg2ei256.v v2, (a0), v2
++	vsxseg2ei256.v v0, (a0), v2, v0.t
++	vlxseg3ei256.v v0, (a0), v2
++	vlxseg3ei256.v v1, (a0), v2
++	vlxseg3ei256.v v2, (a0), v2
++	vlxseg3ei256.v v0, (a0), v2, v0.t
++	vsxseg3ei256.v v0, (a0), v2
++	vsxseg3ei256.v v1, (a0), v2
++	vsxseg3ei256.v v2, (a0), v2
++	vsxseg3ei256.v v0, (a0), v2, v0.t
++	vlxseg4ei256.v v0, (a0), v2
++	vlxseg4ei256.v v1, (a0), v2
++	vlxseg4ei256.v v2, (a0), v2
++	vlxseg4ei256.v v0, (a0), v2, v0.t
++	vsxseg4ei256.v v0, (a0), v2
++	vsxseg4ei256.v v1, (a0), v2
++	vsxseg4ei256.v v2, (a0), v2
++	vsxseg4ei256.v v0, (a0), v2, v0.t
++	vlxseg5ei256.v v0, (a0), v2
++	vlxseg5ei256.v v1, (a0), v2
++	vlxseg5ei256.v v2, (a0), v2
++	vlxseg5ei256.v v0, (a0), v2, v0.t
++	vsxseg5ei256.v v0, (a0), v2
++	vsxseg5ei256.v v1, (a0), v2
++	vsxseg5ei256.v v2, (a0), v2
++	vsxseg5ei256.v v0, (a0), v2, v0.t
++	vlxseg6ei256.v v0, (a0), v2
++	vlxseg6ei256.v v1, (a0), v2
++	vlxseg6ei256.v v2, (a0), v2
++	vlxseg6ei256.v v0, (a0), v2, v0.t
++	vsxseg6ei256.v v0, (a0), v2
++	vsxseg6ei256.v v1, (a0), v2
++	vsxseg6ei256.v v2, (a0), v2
++	vsxseg6ei256.v v0, (a0), v2, v0.t
++	vlxseg7ei256.v v0, (a0), v2
++	vlxseg7ei256.v v1, (a0), v2
++	vlxseg7ei256.v v2, (a0), v2
++	vlxseg7ei256.v v0, (a0), v2, v0.t
++	vsxseg7ei256.v v0, (a0), v2
++	vsxseg7ei256.v v1, (a0), v2
++	vsxseg7ei256.v v2, (a0), v2
++	vsxseg7ei256.v v0, (a0), v2, v0.t
++	vlxseg8ei256.v v0, (a0), v2
++	vlxseg8ei256.v v1, (a0), v2
++	vlxseg8ei256.v v2, (a0), v2
++	vlxseg8ei256.v v0, (a0), v2, v0.t
++	vsxseg8ei256.v v0, (a0), v2
++	vsxseg8ei256.v v1, (a0), v2
++	vsxseg8ei256.v v2, (a0), v2
++	vsxseg8ei256.v v0, (a0), v2, v0.t
++
++	vlxseg2ei512.v v0, (a0), v2		# OK
++	vlxseg2ei512.v v1, (a0), v2		# OK
++	vlxseg2ei512.v v2, (a0), v2		# vd overlap vs2
++	vlxseg2ei512.v v0, (a0), v2, v0.t	# vd overlap vm
++	vsxseg2ei512.v v0, (a0), v2
++	vsxseg2ei512.v v1, (a0), v2
++	vsxseg2ei512.v v2, (a0), v2
++	vsxseg2ei512.v v0, (a0), v2, v0.t
++	vlxseg3ei512.v v0, (a0), v2
++	vlxseg3ei512.v v1, (a0), v2
++	vlxseg3ei512.v v2, (a0), v2
++	vlxseg3ei512.v v0, (a0), v2, v0.t
++	vsxseg3ei512.v v0, (a0), v2
++	vsxseg3ei512.v v1, (a0), v2
++	vsxseg3ei512.v v2, (a0), v2
++	vsxseg3ei512.v v0, (a0), v2, v0.t
++	vlxseg4ei512.v v0, (a0), v2
++	vlxseg4ei512.v v1, (a0), v2
++	vlxseg4ei512.v v2, (a0), v2
++	vlxseg4ei512.v v0, (a0), v2, v0.t
++	vsxseg4ei512.v v0, (a0), v2
++	vsxseg4ei512.v v1, (a0), v2
++	vsxseg4ei512.v v2, (a0), v2
++	vsxseg4ei512.v v0, (a0), v2, v0.t
++	vlxseg5ei512.v v0, (a0), v2
++	vlxseg5ei512.v v1, (a0), v2
++	vlxseg5ei512.v v2, (a0), v2
++	vlxseg5ei512.v v0, (a0), v2, v0.t
++	vsxseg5ei512.v v0, (a0), v2
++	vsxseg5ei512.v v1, (a0), v2
++	vsxseg5ei512.v v2, (a0), v2
++	vsxseg5ei512.v v0, (a0), v2, v0.t
++	vlxseg6ei512.v v0, (a0), v2
++	vlxseg6ei512.v v1, (a0), v2
++	vlxseg6ei512.v v2, (a0), v2
++	vlxseg6ei512.v v0, (a0), v2, v0.t
++	vsxseg6ei512.v v0, (a0), v2
++	vsxseg6ei512.v v1, (a0), v2
++	vsxseg6ei512.v v2, (a0), v2
++	vsxseg6ei512.v v0, (a0), v2, v0.t
++	vlxseg7ei512.v v0, (a0), v2
++	vlxseg7ei512.v v1, (a0), v2
++	vlxseg7ei512.v v2, (a0), v2
++	vlxseg7ei512.v v0, (a0), v2, v0.t
++	vsxseg7ei512.v v0, (a0), v2
++	vsxseg7ei512.v v1, (a0), v2
++	vsxseg7ei512.v v2, (a0), v2
++	vsxseg7ei512.v v0, (a0), v2, v0.t
++	vlxseg8ei512.v v0, (a0), v2
++	vlxseg8ei512.v v1, (a0), v2
++	vlxseg8ei512.v v2, (a0), v2
++	vlxseg8ei512.v v0, (a0), v2, v0.t
++	vsxseg8ei512.v v0, (a0), v2
++	vsxseg8ei512.v v1, (a0), v2
++	vsxseg8ei512.v v2, (a0), v2
++	vsxseg8ei512.v v0, (a0), v2, v0.t
++
++	vlxseg2ei1024.v v0, (a0), v2		# OK
++	vlxseg2ei1024.v v1, (a0), v2		# OK
++	vlxseg2ei1024.v v2, (a0), v2		# vd overlap vs2
++	vlxseg2ei1024.v v0, (a0), v2, v0.t	# vd overlap vm
++	vsxseg2ei1024.v v0, (a0), v2
++	vsxseg2ei1024.v v1, (a0), v2
++	vsxseg2ei1024.v v2, (a0), v2
++	vsxseg2ei1024.v v0, (a0), v2, v0.t
++	vlxseg3ei1024.v v0, (a0), v2
++	vlxseg3ei1024.v v1, (a0), v2
++	vlxseg3ei1024.v v2, (a0), v2
++	vlxseg3ei1024.v v0, (a0), v2, v0.t
++	vsxseg3ei1024.v v0, (a0), v2
++	vsxseg3ei1024.v v1, (a0), v2
++	vsxseg3ei1024.v v2, (a0), v2
++	vsxseg3ei1024.v v0, (a0), v2, v0.t
++	vlxseg4ei1024.v v0, (a0), v2
++	vlxseg4ei1024.v v1, (a0), v2
++	vlxseg4ei1024.v v2, (a0), v2
++	vlxseg4ei1024.v v0, (a0), v2, v0.t
++	vsxseg4ei1024.v v0, (a0), v2
++	vsxseg4ei1024.v v1, (a0), v2
++	vsxseg4ei1024.v v2, (a0), v2
++	vsxseg4ei1024.v v0, (a0), v2, v0.t
++	vlxseg5ei1024.v v0, (a0), v2
++	vlxseg5ei1024.v v1, (a0), v2
++	vlxseg5ei1024.v v2, (a0), v2
++	vlxseg5ei1024.v v0, (a0), v2, v0.t
++	vsxseg5ei1024.v v0, (a0), v2
++	vsxseg5ei1024.v v1, (a0), v2
++	vsxseg5ei1024.v v2, (a0), v2
++	vsxseg5ei1024.v v0, (a0), v2, v0.t
++	vlxseg6ei1024.v v0, (a0), v2
++	vlxseg6ei1024.v v1, (a0), v2
++	vlxseg6ei1024.v v2, (a0), v2
++	vlxseg6ei1024.v v0, (a0), v2, v0.t
++	vsxseg6ei1024.v v0, (a0), v2
++	vsxseg6ei1024.v v1, (a0), v2
++	vsxseg6ei1024.v v2, (a0), v2
++	vsxseg6ei1024.v v0, (a0), v2, v0.t
++	vlxseg7ei1024.v v0, (a0), v2
++	vlxseg7ei1024.v v1, (a0), v2
++	vlxseg7ei1024.v v2, (a0), v2
++	vlxseg7ei1024.v v0, (a0), v2, v0.t
++	vsxseg7ei1024.v v0, (a0), v2
++	vsxseg7ei1024.v v1, (a0), v2
++	vsxseg7ei1024.v v2, (a0), v2
++	vsxseg7ei1024.v v0, (a0), v2, v0.t
++	vlxseg8ei1024.v v0, (a0), v2
++	vlxseg8ei1024.v v1, (a0), v2
++	vlxseg8ei1024.v v2, (a0), v2
++	vlxseg8ei1024.v v0, (a0), v2, v0.t
++	vsxseg8ei1024.v v0, (a0), v2
++	vsxseg8ei1024.v v1, (a0), v2
++	vsxseg8ei1024.v v2, (a0), v2
++	vsxseg8ei1024.v v0, (a0), v2, v0.t
+diff --git a/gas/testsuite/gas/riscv/vector-insns-fail-02.d b/gas/testsuite/gas/riscv/vector-insns-fail-02.d
+new file mode 100644
+index 0000000000..6780b8553d
+--- /dev/null
++++ b/gas/testsuite/gas/riscv/vector-insns-fail-02.d
+@@ -0,0 +1,3 @@
++#as: -march=rv32ifv_zvqmac -mcheck-constraints
++#source: vector-insns-fail-02.s
++#error_output: vector-insns-fail-02.l
+diff --git a/gas/testsuite/gas/riscv/vector-insns-fail-02.l b/gas/testsuite/gas/riscv/vector-insns-fail-02.l
+new file mode 100644
+index 0000000000..c015fd75fc
+--- /dev/null
++++ b/gas/testsuite/gas/riscv/vector-insns-fail-02.l
+@@ -0,0 +1,121 @@
++.*: Assembler messages:
++.*Error: illegal operands `vwaddu.vv v1,v2,v4'
++.*Error: illegal operands `vwaddu.vv v2,v2,v4'
++.*Error: illegal operands `vwaddu.vv v2,v3,v4'
++.*Error: illegal operands `vwaddu.vv v4,v2,v4'
++.*Error: illegal operands `vwaddu.vv v4,v2,v5'
++.*Error: illegal operands `vwaddu.vv v0,v2,v4,v0.t'
++.*Error: illegal operands `vwsubu.vv v1,v2,v4'
++.*Error: illegal operands `vwsubu.vv v2,v2,v4'
++.*Error: illegal operands `vwsubu.vv v2,v3,v4'
++.*Error: illegal operands `vwsubu.vv v4,v2,v4'
++.*Error: illegal operands `vwsubu.vv v4,v2,v5'
++.*Error: illegal operands `vwsubu.vv v0,v2,v4,v0.t'
++.*Error: illegal operands `vwadd.vv v1,v2,v4'
++.*Error: illegal operands `vwadd.vv v2,v2,v4'
++.*Error: illegal operands `vwadd.vv v2,v3,v4'
++.*Error: illegal operands `vwadd.vv v4,v2,v4'
++.*Error: illegal operands `vwadd.vv v4,v2,v5'
++.*Error: illegal operands `vwadd.vv v0,v2,v4,v0.t'
++.*Error: illegal operands `vwsub.vv v1,v2,v4'
++.*Error: illegal operands `vwsub.vv v2,v2,v4'
++.*Error: illegal operands `vwsub.vv v2,v3,v4'
++.*Error: illegal operands `vwsub.vv v4,v2,v4'
++.*Error: illegal operands `vwsub.vv v4,v2,v5'
++.*Error: illegal operands `vwsub.vv v0,v2,v4,v0.t'
++.*Error: illegal operands `vwmul.vv v1,v2,v4'
++.*Error: illegal operands `vwmul.vv v2,v2,v4'
++.*Error: illegal operands `vwmul.vv v2,v3,v4'
++.*Error: illegal operands `vwmul.vv v4,v2,v4'
++.*Error: illegal operands `vwmul.vv v4,v2,v5'
++.*Error: illegal operands `vwmul.vv v0,v2,v4,v0.t'
++.*Error: illegal operands `vwmulu.vv v1,v2,v4'
++.*Error: illegal operands `vwmulu.vv v2,v2,v4'
++.*Error: illegal operands `vwmulu.vv v2,v3,v4'
++.*Error: illegal operands `vwmulu.vv v4,v2,v4'
++.*Error: illegal operands `vwmulu.vv v4,v2,v5'
++.*Error: illegal operands `vwmulu.vv v0,v2,v4,v0.t'
++.*Error: illegal operands `vwmulsu.vv v1,v2,v4'
++.*Error: illegal operands `vwmulsu.vv v2,v2,v4'
++.*Error: illegal operands `vwmulsu.vv v2,v3,v4'
++.*Error: illegal operands `vwmulsu.vv v4,v2,v4'
++.*Error: illegal operands `vwmulsu.vv v4,v2,v5'
++.*Error: illegal operands `vwmulsu.vv v0,v2,v4,v0.t'
++.*Error: illegal operands `vwmaccu.vv v1,v2,v4'
++.*Error: illegal operands `vwmaccu.vv v2,v2,v4'
++.*Error: illegal operands `vwmaccu.vv v2,v3,v4'
++.*Error: illegal operands `vwmaccu.vv v4,v2,v4'
++.*Error: illegal operands `vwmaccu.vv v4,v2,v5'
++.*Error: illegal operands `vwmaccu.vv v0,v2,v4,v0.t'
++.*Error: illegal operands `vwmacc.vv v1,v2,v4'
++.*Error: illegal operands `vwmacc.vv v2,v2,v4'
++.*Error: illegal operands `vwmacc.vv v2,v3,v4'
++.*Error: illegal operands `vwmacc.vv v4,v2,v4'
++.*Error: illegal operands `vwmacc.vv v4,v2,v5'
++.*Error: illegal operands `vwmacc.vv v0,v2,v4,v0.t'
++.*Error: illegal operands `vwmaccsu.vv v1,v2,v4'
++.*Error: illegal operands `vwmaccsu.vv v2,v2,v4'
++.*Error: illegal operands `vwmaccsu.vv v2,v3,v4'
++.*Error: illegal operands `vwmaccsu.vv v4,v2,v4'
++.*Error: illegal operands `vwmaccsu.vv v4,v2,v5'
++.*Error: illegal operands `vwmaccsu.vv v0,v2,v4,v0.t'
++.*Error: illegal operands `vqmaccu.vv v2,v4,v8'
++.*Error: illegal operands `vqmaccu.vv v4,v4,v8'
++.*Error: illegal operands `vqmaccu.vv v4,v6,v8'
++.*Error: illegal operands `vqmaccu.vv v8,v4,v8'
++.*Error: illegal operands `vqmaccu.vv v8,v4,v10'
++.*Error: illegal operands `vqmaccu.vv v0,v4,v8,v0.t'
++.*Error: illegal operands `vqmacc.vv v2,v4,v8'
++.*Error: illegal operands `vqmacc.vv v4,v4,v8'
++.*Error: illegal operands `vqmacc.vv v4,v6,v8'
++.*Error: illegal operands `vqmacc.vv v8,v4,v8'
++.*Error: illegal operands `vqmacc.vv v8,v4,v10'
++.*Error: illegal operands `vqmacc.vv v0,v4,v8,v0.t'
++.*Error: illegal operands `vqmaccsu.vv v2,v4,v8'
++.*Error: illegal operands `vqmaccsu.vv v4,v4,v8'
++.*Error: illegal operands `vqmaccsu.vv v4,v6,v8'
++.*Error: illegal operands `vqmaccsu.vv v8,v4,v8'
++.*Error: illegal operands `vqmaccsu.vv v8,v4,v10'
++.*Error: illegal operands `vqmaccsu.vv v0,v4,v8,v0.t'
++.*Error: illegal operands `vfwadd.vv v1,v2,v4'
++.*Error: illegal operands `vfwadd.vv v2,v2,v4'
++.*Error: illegal operands `vfwadd.vv v2,v3,v4'
++.*Error: illegal operands `vfwadd.vv v4,v2,v4'
++.*Error: illegal operands `vfwadd.vv v4,v2,v5'
++.*Error: illegal operands `vfwadd.vv v0,v2,v4,v0.t'
++.*Error: illegal operands `vfwsub.vv v1,v2,v4'
++.*Error: illegal operands `vfwsub.vv v2,v2,v4'
++.*Error: illegal operands `vfwsub.vv v2,v3,v4'
++.*Error: illegal operands `vfwsub.vv v4,v2,v4'
++.*Error: illegal operands `vfwsub.vv v4,v2,v5'
++.*Error: illegal operands `vfwsub.vv v0,v2,v4,v0.t'
++.*Error: illegal operands `vfwmul.vv v1,v2,v4'
++.*Error: illegal operands `vfwmul.vv v2,v2,v4'
++.*Error: illegal operands `vfwmul.vv v2,v3,v4'
++.*Error: illegal operands `vfwmul.vv v4,v2,v4'
++.*Error: illegal operands `vfwmul.vv v4,v2,v5'
++.*Error: illegal operands `vfwmul.vv v0,v2,v4,v0.t'
++.*Error: illegal operands `vfwmacc.vv v1,v2,v4'
++.*Error: illegal operands `vfwmacc.vv v2,v2,v4'
++.*Error: illegal operands `vfwmacc.vv v2,v3,v4'
++.*Error: illegal operands `vfwmacc.vv v4,v2,v4'
++.*Error: illegal operands `vfwmacc.vv v4,v2,v5'
++.*Error: illegal operands `vfwmacc.vv v0,v2,v4,v0.t'
++.*Error: illegal operands `vfwnmacc.vv v1,v2,v4'
++.*Error: illegal operands `vfwnmacc.vv v2,v2,v4'
++.*Error: illegal operands `vfwnmacc.vv v2,v3,v4'
++.*Error: illegal operands `vfwnmacc.vv v4,v2,v4'
++.*Error: illegal operands `vfwnmacc.vv v4,v2,v5'
++.*Error: illegal operands `vfwnmacc.vv v0,v2,v4,v0.t'
++.*Error: illegal operands `vfwmsac.vv v1,v2,v4'
++.*Error: illegal operands `vfwmsac.vv v2,v2,v4'
++.*Error: illegal operands `vfwmsac.vv v2,v3,v4'
++.*Error: illegal operands `vfwmsac.vv v4,v2,v4'
++.*Error: illegal operands `vfwmsac.vv v4,v2,v5'
++.*Error: illegal operands `vfwmsac.vv v0,v2,v4,v0.t'
++.*Error: illegal operands `vfwnmsac.vv v1,v2,v4'
++.*Error: illegal operands `vfwnmsac.vv v2,v2,v4'
++.*Error: illegal operands `vfwnmsac.vv v2,v3,v4'
++.*Error: illegal operands `vfwnmsac.vv v4,v2,v4'
++.*Error: illegal operands `vfwnmsac.vv v4,v2,v5'
++.*Error: illegal operands `vfwnmsac.vv v0,v2,v4,v0.t'
+diff --git a/gas/testsuite/gas/riscv/vector-insns-fail-02.s b/gas/testsuite/gas/riscv/vector-insns-fail-02.s
+new file mode 100644
+index 0000000000..bf493c8ddb
+--- /dev/null
++++ b/gas/testsuite/gas/riscv/vector-insns-fail-02.s
+@@ -0,0 +1,162 @@
++# Widening Vector Arithmetic Instructions (VV)
++# Quad-Widening Vector Arithmetic Instructions (VV)
++
++	vwaddu.vv v0, v2, v4		# OK
++	vwaddu.vv v1, v2, v4		# vd should be multiple of 2
++	vwaddu.vv v2, v2, v4		# vd overlap vs2
++	vwaddu.vv v2, v3, v4		# vd overlap vs2
++	vwaddu.vv v4, v2, v4		# vd overlap vs1
++	vwaddu.vv v4, v2, v5		# vd overlap vs1
++	vwaddu.vv v0, v2, v4, v0.t	# vd overlap vm
++
++	vwsubu.vv v0, v2, v4		# OK
++	vwsubu.vv v1, v2, v4		# vd should be multiple of 2
++	vwsubu.vv v2, v2, v4		# vd overlap vs2
++	vwsubu.vv v2, v3, v4		# vd overlap vs2
++	vwsubu.vv v4, v2, v4		# vd overlap vs1
++	vwsubu.vv v4, v2, v5		# vd overlap vs1
++	vwsubu.vv v0, v2, v4, v0.t	# vd overlap vm
++
++	vwadd.vv v0, v2, v4		# OK
++	vwadd.vv v1, v2, v4		# vd should be multiple of 2
++	vwadd.vv v2, v2, v4		# vd overlap vs2
++	vwadd.vv v2, v3, v4		# vd overlap vs2
++	vwadd.vv v4, v2, v4		# vd overlap vs1
++	vwadd.vv v4, v2, v5		# vd overlap vs1
++	vwadd.vv v0, v2, v4, v0.t	# vd overlap vm
++
++	vwsub.vv v0, v2, v4		# OK
++	vwsub.vv v1, v2, v4		# vd should be multiple of 2
++	vwsub.vv v2, v2, v4		# vd overlap vs2
++	vwsub.vv v2, v3, v4		# vd overlap vs2
++	vwsub.vv v4, v2, v4		# vd overlap vs1
++	vwsub.vv v4, v2, v5		# vd overlap vs1
++	vwsub.vv v0, v2, v4, v0.t	# vd overlap vm
++
++	vwmul.vv v0, v2, v4		# OK
++	vwmul.vv v1, v2, v4		# vd should be multiple of 2
++	vwmul.vv v2, v2, v4		# vd overlap vs2
++	vwmul.vv v2, v3, v4		# vd overlap vs2
++	vwmul.vv v4, v2, v4		# vd overlap vs1
++	vwmul.vv v4, v2, v5		# vd overlap vs1
++	vwmul.vv v0, v2, v4, v0.t	# vd overlap vm
++
++	vwmulu.vv v0, v2, v4		# OK
++	vwmulu.vv v1, v2, v4		# vd should be multiple of 2
++	vwmulu.vv v2, v2, v4		# vd overlap vs2
++	vwmulu.vv v2, v3, v4		# vd overlap vs2
++	vwmulu.vv v4, v2, v4		# vd overlap vs1
++	vwmulu.vv v4, v2, v5		# vd overlap vs1
++	vwmulu.vv v0, v2, v4, v0.t	# vd overlap vm
++
++	vwmulsu.vv v0, v2, v4		# OK
++	vwmulsu.vv v1, v2, v4		# vd should be multiple of 2
++	vwmulsu.vv v2, v2, v4		# vd overlap vs2
++	vwmulsu.vv v2, v3, v4		# vd overlap vs2
++	vwmulsu.vv v4, v2, v4		# vd overlap vs1
++	vwmulsu.vv v4, v2, v5		# vd overlap vs1
++	vwmulsu.vv v0, v2, v4, v0.t	# vd overlap vm
++
++	vwmaccu.vv v0, v2, v4		# OK
++	vwmaccu.vv v1, v2, v4		# vd should be multiple of 2
++	vwmaccu.vv v2, v2, v4		# vd overlap vs1
++	vwmaccu.vv v2, v3, v4		# vd overlap vs1
++	vwmaccu.vv v4, v2, v4		# vd overlap vs2
++	vwmaccu.vv v4, v2, v5		# vd overlap vs2
++	vwmaccu.vv v0, v2, v4, v0.t	# vd overlap vm
++
++	vwmacc.vv v0, v2, v4		# OK
++	vwmacc.vv v1, v2, v4		# vd should be multiple of 2
++	vwmacc.vv v2, v2, v4		# vd overlap vs1
++	vwmacc.vv v2, v3, v4		# vd overlap vs1
++	vwmacc.vv v4, v2, v4		# vd overlap vs2
++	vwmacc.vv v4, v2, v5		# vd overlap vs2
++	vwmacc.vv v0, v2, v4, v0.t	# vd overlap vm
++
++	vwmaccsu.vv v0, v2, v4		# OK
++	vwmaccsu.vv v1, v2, v4		# vd should be multiple of 2
++	vwmaccsu.vv v2, v2, v4		# vd overlap vs1
++	vwmaccsu.vv v2, v3, v4		# vd overlap vs1
++	vwmaccsu.vv v4, v2, v4		# vd overlap vs2
++	vwmaccsu.vv v4, v2, v5		# vd overlap vs2
++	vwmaccsu.vv v0, v2, v4, v0.t	# vd overlap vm
++
++	vqmaccu.vv v0, v4, v8		# OK
++	vqmaccu.vv v2, v4, v8		# vd should be multiple of 4
++	vqmaccu.vv v4, v4, v8		# vd overlap vs1
++	vqmaccu.vv v4, v6, v8		# vd overlap vs1
++	vqmaccu.vv v8, v4, v8		# vd overlap vs2
++	vqmaccu.vv v8, v4, v10		# vd overlap vs2
++	vqmaccu.vv v0, v4, v8, v0.t	# vd overlap vm
++
++	vqmacc.vv v0, v4, v8		# OK
++	vqmacc.vv v2, v4, v8		# vd should be multiple of 4
++	vqmacc.vv v4, v4, v8		# vd overlap vs1
++	vqmacc.vv v4, v6, v8		# vd overlap vs1
++	vqmacc.vv v8, v4, v8		# vd overlap vs2
++	vqmacc.vv v8, v4, v10		# vd overlap vs2
++	vqmacc.vv v0, v4, v8, v0.t	# vd overlap vm
++
++	vqmaccsu.vv v0, v4, v8		# OK
++	vqmaccsu.vv v2, v4, v8		# vd should be multiple of 4
++	vqmaccsu.vv v4, v4, v8		# vd overlap vs1
++	vqmaccsu.vv v4, v6, v8		# vd overlap vs1
++	vqmaccsu.vv v8, v4, v8		# vd overlap vs2
++	vqmaccsu.vv v8, v4, v10		# vd overlap vs2
++	vqmaccsu.vv v0, v4, v8, v0.t	# vd overlap vm
++
++	vfwadd.vv v0, v2, v4		# OK
++	vfwadd.vv v1, v2, v4		# vd should be multiple of 2
++	vfwadd.vv v2, v2, v4		# vd overlap vs2
++	vfwadd.vv v2, v3, v4		# vd overlap vs2
++	vfwadd.vv v4, v2, v4		# vd overlap vs1
++	vfwadd.vv v4, v2, v5		# vd overlap vs1
++	vfwadd.vv v0, v2, v4, v0.t	# vd overlap vm
++
++	vfwsub.vv v0, v2, v4		# OK
++	vfwsub.vv v1, v2, v4		# vd should be multiple of 2
++	vfwsub.vv v2, v2, v4		# vd overlap vs2
++	vfwsub.vv v2, v3, v4		# vd overlap vs2
++	vfwsub.vv v4, v2, v4		# vd overlap vs1
++	vfwsub.vv v4, v2, v5		# vd overlap vs1
++	vfwsub.vv v0, v2, v4, v0.t	# vd overlap vm
++
++	vfwmul.vv v0, v2, v4		# OK
++	vfwmul.vv v1, v2, v4		# vd should be multiple of 2
++	vfwmul.vv v2, v2, v4		# vd overlap vs2
++	vfwmul.vv v2, v3, v4		# vd overlap vs2
++	vfwmul.vv v4, v2, v4		# vd overlap vs1
++	vfwmul.vv v4, v2, v5		# vd overlap vs1
++	vfwmul.vv v0, v2, v4, v0.t	# vd overlap vm
++
++	vfwmacc.vv v0, v2, v4		# OK
++	vfwmacc.vv v1, v2, v4		# vd should be multiple of 2
++	vfwmacc.vv v2, v2, v4		# vd overlap vs1
++	vfwmacc.vv v2, v3, v4		# vd overlap vs1
++	vfwmacc.vv v4, v2, v4		# vd overlap vs2
++	vfwmacc.vv v4, v2, v5		# vd overlap vs2
++	vfwmacc.vv v0, v2, v4, v0.t	# vd overlap vm
++
++	vfwnmacc.vv v0, v2, v4		# OK
++	vfwnmacc.vv v1, v2, v4		# vd should be multiple of 2
++	vfwnmacc.vv v2, v2, v4		# vd overlap vs1
++	vfwnmacc.vv v2, v3, v4		# vd overlap vs1
++	vfwnmacc.vv v4, v2, v4		# vd overlap vs2
++	vfwnmacc.vv v4, v2, v5		# vd overlap vs2
++	vfwnmacc.vv v0, v2, v4, v0.t	# vd overlap vm
++
++	vfwmsac.vv v0, v2, v4		# OK
++	vfwmsac.vv v1, v2, v4		# vd should be multiple of 2
++	vfwmsac.vv v2, v2, v4		# vd overlap vs1
++	vfwmsac.vv v2, v3, v4		# vd overlap vs1
++	vfwmsac.vv v4, v2, v4		# vd overlap vs2
++	vfwmsac.vv v4, v2, v5		# vd overlap vs2
++	vfwmsac.vv v0, v2, v4, v0.t	# vd overlap vm
++
++	vfwnmsac.vv v0, v2, v4		# OK
++	vfwnmsac.vv v1, v2, v4		# vd should be multiple of 2
++	vfwnmsac.vv v2, v2, v4		# vd overlap vs1
++	vfwnmsac.vv v2, v3, v4		# vd overlap vs1
++	vfwnmsac.vv v4, v2, v4		# vd overlap vs2
++	vfwnmsac.vv v4, v2, v5		# vd overlap vs2
++	vfwnmsac.vv v0, v2, v4, v0.t	# vd overlap vm
+diff --git a/gas/testsuite/gas/riscv/vector-insns-fail-03.d b/gas/testsuite/gas/riscv/vector-insns-fail-03.d
+new file mode 100644
+index 0000000000..1bfe441872
+--- /dev/null
++++ b/gas/testsuite/gas/riscv/vector-insns-fail-03.d
+@@ -0,0 +1,3 @@
++#as: -march=rv32ifv_zvqmac -mcheck-constraints
++#source: vector-insns-fail-03.s
++#error_output: vector-insns-fail-03.l
+diff --git a/gas/testsuite/gas/riscv/vector-insns-fail-03.l b/gas/testsuite/gas/riscv/vector-insns-fail-03.l
+new file mode 100644
+index 0000000000..128e22726d
+--- /dev/null
++++ b/gas/testsuite/gas/riscv/vector-insns-fail-03.l
+@@ -0,0 +1,125 @@
++.*: Assembler messages:
++.*Error: illegal operands `vwcvt.x.x.v v1,v2'
++.*Error: illegal operands `vwcvt.x.x.v v2,v2'
++.*Error: illegal operands `vwcvt.x.x.v v2,v3'
++.*Error: illegal operands `vwcvt.x.x.v v0,v2,v0.t'
++.*Error: illegal operands `vwcvtu.x.x.v v1,v2'
++.*Error: illegal operands `vwcvtu.x.x.v v2,v2'
++.*Error: illegal operands `vwcvtu.x.x.v v2,v3'
++.*Error: illegal operands `vwcvtu.x.x.v v0,v2,v0.t'
++.*Error: illegal operands `vwaddu.vx v1,v2,a1'
++.*Error: illegal operands `vwaddu.vx v2,v2,a1'
++.*Error: illegal operands `vwaddu.vx v2,v3,a1'
++.*Error: illegal operands `vwaddu.vx v0,v2,a1,v0.t'
++.*Error: illegal operands `vwsubu.vx v1,v2,a1'
++.*Error: illegal operands `vwsubu.vx v2,v2,a1'
++.*Error: illegal operands `vwsubu.vx v2,v3,a1'
++.*Error: illegal operands `vwsubu.vx v0,v2,a1,v0.t'
++.*Error: illegal operands `vwadd.vx v1,v2,a1'
++.*Error: illegal operands `vwadd.vx v2,v2,a1'
++.*Error: illegal operands `vwadd.vx v2,v3,a1'
++.*Error: illegal operands `vwadd.vx v0,v2,a1,v0.t'
++.*Error: illegal operands `vwsub.vx v1,v2,a1'
++.*Error: illegal operands `vwsub.vx v2,v2,a1'
++.*Error: illegal operands `vwsub.vx v2,v3,a1'
++.*Error: illegal operands `vwsub.vx v0,v2,a1,v0.t'
++.*Error: illegal operands `vwmul.vx v1,v2,a1'
++.*Error: illegal operands `vwmul.vx v2,v2,a1'
++.*Error: illegal operands `vwmul.vx v2,v3,a1'
++.*Error: illegal operands `vwmul.vx v0,v2,a1,v0.t'
++.*Error: illegal operands `vwmulu.vx v1,v2,a1'
++.*Error: illegal operands `vwmulu.vx v2,v2,a1'
++.*Error: illegal operands `vwmulu.vx v2,v3,a1'
++.*Error: illegal operands `vwmulu.vx v0,v2,a1,v0.t'
++.*Error: illegal operands `vwmulsu.vx v1,v2,a1'
++.*Error: illegal operands `vwmulsu.vx v2,v2,a1'
++.*Error: illegal operands `vwmulsu.vx v2,v3,a1'
++.*Error: illegal operands `vwmulsu.vx v0,v2,a1,v0.t'
++.*Error: illegal operands `vwmaccu.vx v1,a1,v4'
++.*Error: illegal operands `vwmaccu.vx v4,a1,v4'
++.*Error: illegal operands `vwmaccu.vx v4,a1,v5'
++.*Error: illegal operands `vwmaccu.vx v0,a1,v4,v0.t'
++.*Error: illegal operands `vwmacc.vx v1,a1,v4'
++.*Error: illegal operands `vwmacc.vx v4,a1,v4'
++.*Error: illegal operands `vwmacc.vx v4,a1,v5'
++.*Error: illegal operands `vwmacc.vx v0,a1,v4,v0.t'
++.*Error: illegal operands `vwmaccsu.vx v1,a1,v4'
++.*Error: illegal operands `vwmaccsu.vx v4,a1,v4'
++.*Error: illegal operands `vwmaccsu.vx v4,a1,v5'
++.*Error: illegal operands `vwmaccsu.vx v0,a1,v4,v0.t'
++.*Error: illegal operands `vwmaccus.vx v1,a1,v4'
++.*Error: illegal operands `vwmaccus.vx v4,a1,v4'
++.*Error: illegal operands `vwmaccus.vx v4,a1,v5'
++.*Error: illegal operands `vwmaccus.vx v0,a1,v4,v0.t'
++.*Error: illegal operands `vqmaccu.vx v2,a1,v4'
++.*Error: illegal operands `vqmaccu.vx v4,a1,v4'
++.*Error: illegal operands `vqmaccu.vx v4,a1,v6'
++.*Error: illegal operands `vqmaccu.vx v0,a1,v4,v0.t'
++.*Error: illegal operands `vqmacc.vx v2,a1,v4'
++.*Error: illegal operands `vqmacc.vx v4,a1,v4'
++.*Error: illegal operands `vqmacc.vx v4,a1,v6'
++.*Error: illegal operands `vqmacc.vx v0,a1,v4,v0.t'
++.*Error: illegal operands `vqmaccsu.vx v2,a1,v4'
++.*Error: illegal operands `vqmaccsu.vx v4,a1,v4'
++.*Error: illegal operands `vqmaccsu.vx v4,a1,v6'
++.*Error: illegal operands `vqmaccsu.vx v0,a1,v4,v0.t'
++.*Error: illegal operands `vqmaccus.vx v2,a1,v4'
++.*Error: illegal operands `vqmaccus.vx v4,a1,v4'
++.*Error: illegal operands `vqmaccus.vx v4,a1,v6'
++.*Error: illegal operands `vqmaccus.vx v0,a1,v4,v0.t'
++.*Error: illegal operands `vfwadd.vf v1,v2,fa1'
++.*Error: illegal operands `vfwadd.vf v2,v2,fa1'
++.*Error: illegal operands `vfwadd.vf v2,v3,fa1'
++.*Error: illegal operands `vfwadd.vf v0,v2,fa1,v0.t'
++.*Error: illegal operands `vfwsub.vf v1,v2,fa1'
++.*Error: illegal operands `vfwsub.vf v2,v2,fa1'
++.*Error: illegal operands `vfwsub.vf v2,v3,fa1'
++.*Error: illegal operands `vfwsub.vf v0,v2,fa1,v0.t'
++.*Error: illegal operands `vfwmul.vf v1,v2,fa1'
++.*Error: illegal operands `vfwmul.vf v2,v2,fa1'
++.*Error: illegal operands `vfwmul.vf v2,v3,fa1'
++.*Error: illegal operands `vfwmul.vf v0,v2,fa1,v0.t'
++.*Error: illegal operands `vfwmacc.vf v1,fa1,v4'
++.*Error: illegal operands `vfwmacc.vf v4,fa1,v4'
++.*Error: illegal operands `vfwmacc.vf v4,fa1,v5'
++.*Error: illegal operands `vfwmacc.vf v0,fa1,v4,v0.t'
++.*Error: illegal operands `vfwnmacc.vf v1,fa1,v4'
++.*Error: illegal operands `vfwnmacc.vf v4,fa1,v4'
++.*Error: illegal operands `vfwnmacc.vf v4,fa1,v5'
++.*Error: illegal operands `vfwnmacc.vf v0,fa1,v4,v0.t'
++.*Error: illegal operands `vfwmsac.vf v1,fa1,v4'
++.*Error: illegal operands `vfwmsac.vf v4,fa1,v4'
++.*Error: illegal operands `vfwmsac.vf v4,fa1,v5'
++.*Error: illegal operands `vfwmsac.vf v0,fa1,v4,v0.t'
++.*Error: illegal operands `vfwnmsac.vf v1,fa1,v4'
++.*Error: illegal operands `vfwnmsac.vf v4,fa1,v4'
++.*Error: illegal operands `vfwnmsac.vf v4,fa1,v5'
++.*Error: illegal operands `vfwnmsac.vf v0,fa1,v4,v0.t'
++.*Error: illegal operands `vfwcvt.xu.f.v v1,v2'
++.*Error: illegal operands `vfwcvt.xu.f.v v2,v2'
++.*Error: illegal operands `vfwcvt.xu.f.v v2,v3'
++.*Error: illegal operands `vfwcvt.xu.f.v v0,v2,v0.t'
++.*Error: illegal operands `vfwcvt.x.f.v v1,v2'
++.*Error: illegal operands `vfwcvt.x.f.v v2,v2'
++.*Error: illegal operands `vfwcvt.x.f.v v2,v3'
++.*Error: illegal operands `vfwcvt.x.f.v v0,v2,v0.t'
++.*Error: illegal operands `vfwcvt.rtz.xu.f.v v1,v2'
++.*Error: illegal operands `vfwcvt.rtz.xu.f.v v2,v2'
++.*Error: illegal operands `vfwcvt.rtz.xu.f.v v2,v3'
++.*Error: illegal operands `vfwcvt.rtz.xu.f.v v0,v2,v0.t'
++.*Error: illegal operands `vfwcvt.rtz.x.f.v v1,v2'
++.*Error: illegal operands `vfwcvt.rtz.x.f.v v2,v2'
++.*Error: illegal operands `vfwcvt.rtz.x.f.v v2,v3'
++.*Error: illegal operands `vfwcvt.rtz.x.f.v v0,v2,v0.t'
++.*Error: illegal operands `vfwcvt.f.xu.v v1,v2'
++.*Error: illegal operands `vfwcvt.f.xu.v v2,v2'
++.*Error: illegal operands `vfwcvt.f.xu.v v2,v3'
++.*Error: illegal operands `vfwcvt.f.xu.v v0,v2,v0.t'
++.*Error: illegal operands `vfwcvt.f.x.v v1,v2'
++.*Error: illegal operands `vfwcvt.f.x.v v2,v2'
++.*Error: illegal operands `vfwcvt.f.x.v v2,v3'
++.*Error: illegal operands `vfwcvt.f.x.v v0,v2,v0.t'
++.*Error: illegal operands `vfwcvt.f.f.v v1,v2'
++.*Error: illegal operands `vfwcvt.f.f.v v2,v2'
++.*Error: illegal operands `vfwcvt.f.f.v v2,v3'
++.*Error: illegal operands `vfwcvt.f.f.v v0,v2,v0.t'
+diff --git a/gas/testsuite/gas/riscv/vector-insns-fail-03.s b/gas/testsuite/gas/riscv/vector-insns-fail-03.s
+new file mode 100644
+index 0000000000..9450b9ceb0
+--- /dev/null
++++ b/gas/testsuite/gas/riscv/vector-insns-fail-03.s
+@@ -0,0 +1,187 @@
++# Widening Vector Arithmetic Instructions (V[X|F])
++
++	vwcvt.x.x.v v0, v2		# OK
++	vwcvt.x.x.v v1, v2		# vd should be multiple of 2
++	vwcvt.x.x.v v2, v2		# vd overlap vs2
++	vwcvt.x.x.v v2, v3		# vd overlap vs2
++	vwcvt.x.x.v v0, v2, v0.t	# vd overlap vm
++
++	vwcvtu.x.x.v v0, v2		# OK
++	vwcvtu.x.x.v v1, v2		# vd should be multiple of 2
++	vwcvtu.x.x.v v2, v2		# vd overlap vs2
++	vwcvtu.x.x.v v2, v3		# vd overlap vs2
++	vwcvtu.x.x.v v0, v2, v0.t	# vd overlap vm
++
++	vwaddu.vx v0, v2, a1		# OK
++	vwaddu.vx v1, v2, a1		# vd should be multiple of 2
++	vwaddu.vx v2, v2, a1		# vd overlap vs2
++	vwaddu.vx v2, v3, a1		# vd overlap vs2
++	vwaddu.vx v0, v2, a1, v0.t	# vd overlap vm
++
++	vwsubu.vx v0, v2, a1		# OK
++	vwsubu.vx v1, v2, a1		# vd should be multiple of 2
++	vwsubu.vx v2, v2, a1		# vd overlap vs2
++	vwsubu.vx v2, v3, a1		# vd overlap vs2
++	vwsubu.vx v0, v2, a1, v0.t	# vd overlap vm
++
++	vwadd.vx v0, v2, a1		# OK
++	vwadd.vx v1, v2, a1		# vd should be multiple of 2
++	vwadd.vx v2, v2, a1		# vd overlap vs2
++	vwadd.vx v2, v3, a1		# vd overlap vs2
++	vwadd.vx v0, v2, a1, v0.t	# vd overlap vm
++
++	vwsub.vx v0, v2, a1		# OK
++	vwsub.vx v1, v2, a1		# vd should be multiple of 2
++	vwsub.vx v2, v2, a1		# vd overlap vs2
++	vwsub.vx v2, v3, a1		# vd overlap vs2
++	vwsub.vx v0, v2, a1, v0.t	# vd overlap vm
++
++	vwmul.vx v0, v2, a1		# OK
++	vwmul.vx v1, v2, a1		# vd should be multiple of 2
++	vwmul.vx v2, v2, a1		# vd overlap vs2
++	vwmul.vx v2, v3, a1		# vd overlap vs2
++	vwmul.vx v0, v2, a1, v0.t	# vd overlap vm
++
++	vwmulu.vx v0, v2, a1		# OK
++	vwmulu.vx v1, v2, a1		# vd should be multiple of 2
++	vwmulu.vx v2, v2, a1		# vd overlap vs2
++	vwmulu.vx v2, v3, a1		# vd overlap vs2
++	vwmulu.vx v0, v2, a1, v0.t	# vd overlap vm
++
++	vwmulsu.vx v0, v2, a1		# OK
++	vwmulsu.vx v1, v2, a1		# vd should be multiple of 2
++	vwmulsu.vx v2, v2, a1		# vd overlap vs2
++	vwmulsu.vx v2, v3, a1		# vd overlap vs2
++	vwmulsu.vx v0, v2, a1, v0.t	# vd overlap vm
++
++	vwmaccu.vx v0, a1, v4		# OK
++	vwmaccu.vx v1, a1, v4		# vd should be multiple of 2
++	vwmaccu.vx v4, a1, v4		# vd overlap vs2
++	vwmaccu.vx v4, a1, v5		# vd overlap vs2
++	vwmaccu.vx v0, a1, v4, v0.t	# vd overlap vm
++
++	vwmacc.vx v0, a1, v4		# OK
++	vwmacc.vx v1, a1, v4		# vd should be multiple of 2
++	vwmacc.vx v4, a1, v4		# vd overlap vs2
++	vwmacc.vx v4, a1, v5		# vd overlap vs2
++	vwmacc.vx v0, a1, v4, v0.t	# vd overlap vm
++
++	vwmaccsu.vx v0, a1, v4		# OK
++	vwmaccsu.vx v1, a1, v4		# vd should be multiple of 2
++	vwmaccsu.vx v4, a1, v4		# vd overlap vs2
++	vwmaccsu.vx v4, a1, v5		# vd overlap vs2
++	vwmaccsu.vx v0, a1, v4, v0.t	# vd overlap vm
++
++	vwmaccus.vx v0, a1, v4		# OK
++	vwmaccus.vx v1, a1, v4		# vd should be multiple of 2
++	vwmaccus.vx v4, a1, v4		# vd overlap vs2
++	vwmaccus.vx v4, a1, v5		# vd overlap vs2
++	vwmaccus.vx v0, a1, v4, v0.t	# vd overlap vm
++
++	vqmaccu.vx v0, a1, v4		# OK
++	vqmaccu.vx v2, a1, v4		# vd should be multiple of 4
++	vqmaccu.vx v4, a1, v4		# vd overlap vs2
++	vqmaccu.vx v4, a1, v6		# vd overlap vs2
++	vqmaccu.vx v0, a1, v4, v0.t	# vd overlap vm
++
++	vqmacc.vx v0, a1, v4		# OK
++	vqmacc.vx v2, a1, v4		# vd should be multiple of 4
++	vqmacc.vx v4, a1, v4		# vd overlap vs2
++	vqmacc.vx v4, a1, v6		# vd overlap vs2
++	vqmacc.vx v0, a1, v4, v0.t	# vd overlap vm
++
++	vqmaccsu.vx v0, a1, v4		# OK
++	vqmaccsu.vx v2, a1, v4		# vd should be multiple of 4
++	vqmaccsu.vx v4, a1, v4		# vd overlap vs2
++	vqmaccsu.vx v4, a1, v6		# vd overlap vs2
++	vqmaccsu.vx v0, a1, v4, v0.t	# vd overlap vm
++
++	vqmaccus.vx v0, a1, v4		# OK
++	vqmaccus.vx v2, a1, v4		# vd should be multiple of 4
++	vqmaccus.vx v4, a1, v4		# vd overlap vs2
++	vqmaccus.vx v4, a1, v6		# vd overlap vs2
++	vqmaccus.vx v0, a1, v4, v0.t	# vd overlap vm
++
++	vfwadd.vf v0, v2, fa1		# OK
++	vfwadd.vf v1, v2, fa1		# vd should be multiple of 2
++	vfwadd.vf v2, v2, fa1		# vd overlap vs2
++	vfwadd.vf v2, v3, fa1		# vd overlap vs2
++	vfwadd.vf v0, v2, fa1, v0.t	# vd overlap vm
++
++	vfwsub.vf v0, v2, fa1		# OK
++	vfwsub.vf v1, v2, fa1		# vd should be multiple of 2
++	vfwsub.vf v2, v2, fa1		# vd overlap vs2
++	vfwsub.vf v2, v3, fa1		# vd overlap vs2
++	vfwsub.vf v0, v2, fa1, v0.t	# vd overlap vm
++
++	vfwmul.vf v0, v2, fa1		# OK
++	vfwmul.vf v1, v2, fa1		# vd should be multiple of 2
++	vfwmul.vf v2, v2, fa1		# vd overlap vs2
++	vfwmul.vf v2, v3, fa1		# vd overlap vs2
++	vfwmul.vf v0, v2, fa1, v0.t	# vd overlap vm
++
++	vfwmacc.vf v0, fa1, v4		# OK
++	vfwmacc.vf v1, fa1, v4		# vd should be multiple of 2
++	vfwmacc.vf v4, fa1, v4		# vd overlap vs2
++	vfwmacc.vf v4, fa1, v5		# vd overlap vs2
++	vfwmacc.vf v0, fa1, v4, v0.t	# vd overlap vm
++
++	vfwnmacc.vf v0, fa1, v4		# OK
++	vfwnmacc.vf v1, fa1, v4		# vd should be multiple of 2
++	vfwnmacc.vf v4, fa1, v4		# vd overlap vs2
++	vfwnmacc.vf v4, fa1, v5		# vd overlap vs2
++	vfwnmacc.vf v0, fa1, v4, v0.t	# vd overlap vm
++
++	vfwmsac.vf v0, fa1, v4		# OK
++	vfwmsac.vf v1, fa1, v4		# vd should be multiple of 2
++	vfwmsac.vf v4, fa1, v4		# vd overlap vs2
++	vfwmsac.vf v4, fa1, v5		# vd overlap vs2
++	vfwmsac.vf v0, fa1, v4, v0.t	# vd overlap vm
++
++	vfwnmsac.vf v0, fa1, v4		# OK
++	vfwnmsac.vf v1, fa1, v4		# vd should be multiple of 2
++	vfwnmsac.vf v4, fa1, v4		# vd overlap vs2
++	vfwnmsac.vf v4, fa1, v5		# vd overlap vs2
++	vfwnmsac.vf v0, fa1, v4, v0.t	# vd overlap vm
++
++	vfwcvt.xu.f.v v0, v2		# OK
++	vfwcvt.xu.f.v v1, v2		# vd should be multiple of 2
++	vfwcvt.xu.f.v v2, v2		# vd overlap vs2
++	vfwcvt.xu.f.v v2, v3		# vd overlap vs2
++	vfwcvt.xu.f.v v0, v2, v0.t	# vd overlap vm
++
++	vfwcvt.x.f.v v0, v2		# OK
++	vfwcvt.x.f.v v1, v2		# vd should be multiple of 2
++	vfwcvt.x.f.v v2, v2		# vd overlap vs2
++	vfwcvt.x.f.v v2, v3		# vd overlap vs2
++	vfwcvt.x.f.v v0, v2, v0.t	# vd overlap vm
++
++	vfwcvt.rtz.xu.f.v v0, v2	# OK
++	vfwcvt.rtz.xu.f.v v1, v2	# vd should be multiple of 2
++	vfwcvt.rtz.xu.f.v v2, v2	# vd overlap vs2
++	vfwcvt.rtz.xu.f.v v2, v3	# vd overlap vs2
++	vfwcvt.rtz.xu.f.v v0, v2, v0.t	# vd overlap vm
++
++	vfwcvt.rtz.x.f.v v0, v2		# OK
++	vfwcvt.rtz.x.f.v v1, v2		# vd should be multiple of 2
++	vfwcvt.rtz.x.f.v v2, v2		# vd overlap vs2
++	vfwcvt.rtz.x.f.v v2, v3		# vd overlap vs2
++	vfwcvt.rtz.x.f.v v0, v2, v0.t	# vd overlap vm
++
++	vfwcvt.f.xu.v v0, v2		# OK
++	vfwcvt.f.xu.v v1, v2		# vd should be multiple of 2
++	vfwcvt.f.xu.v v2, v2		# vd overlap vs2
++	vfwcvt.f.xu.v v2, v3		# vd overlap vs2
++	vfwcvt.f.xu.v v0, v2, v0.t	# vd overlap vm
++
++	vfwcvt.f.x.v v0, v2		# OK
++	vfwcvt.f.x.v v1, v2		# vd should be multiple of 2
++	vfwcvt.f.x.v v2, v2		# vd overlap vs2
++	vfwcvt.f.x.v v2, v3		# vd overlap vs2
++	vfwcvt.f.x.v v0, v2, v0.t	# vd overlap vm
++
++	vfwcvt.f.f.v v0, v2		# OK
++	vfwcvt.f.f.v v1, v2		# vd should be multiple of 2
++	vfwcvt.f.f.v v2, v2		# vd overlap vs2
++	vfwcvt.f.f.v v2, v3		# vd overlap vs2
++	vfwcvt.f.f.v v0, v2, v0.t	# vd overlap vm
+diff --git a/gas/testsuite/gas/riscv/vector-insns-fail-04.d b/gas/testsuite/gas/riscv/vector-insns-fail-04.d
+new file mode 100644
+index 0000000000..d483884544
+--- /dev/null
++++ b/gas/testsuite/gas/riscv/vector-insns-fail-04.d
+@@ -0,0 +1,3 @@
++#as: -march=rv32ifv -mcheck-constraints
++#source: vector-insns-fail-04.s
++#error_output: vector-insns-fail-04.l
+diff --git a/gas/testsuite/gas/riscv/vector-insns-fail-04.l b/gas/testsuite/gas/riscv/vector-insns-fail-04.l
+new file mode 100644
+index 0000000000..9a9c76c19d
+--- /dev/null
++++ b/gas/testsuite/gas/riscv/vector-insns-fail-04.l
+@@ -0,0 +1,49 @@
++.*: Assembler messages:
++.*Error: illegal operands `vwaddu.wv v1,v2,v4'
++.*Error: illegal operands `vwaddu.wv v2,v3,v4'
++.*Error: illegal operands `vwaddu.wv v4,v2,v4'
++.*Error: illegal operands `vwaddu.wv v4,v2,v5'
++.*Error: illegal operands `vwaddu.wv v0,v2,v4,v0.t'
++.*Error: illegal operands `vwsubu.wv v1,v2,v4'
++.*Error: illegal operands `vwsubu.wv v2,v3,v4'
++.*Error: illegal operands `vwsubu.wv v4,v2,v4'
++.*Error: illegal operands `vwsubu.wv v4,v2,v5'
++.*Error: illegal operands `vwsubu.wv v0,v2,v4,v0.t'
++.*Error: illegal operands `vwadd.wv v1,v2,v4'
++.*Error: illegal operands `vwadd.wv v2,v3,v4'
++.*Error: illegal operands `vwadd.wv v4,v2,v4'
++.*Error: illegal operands `vwadd.wv v4,v2,v5'
++.*Error: illegal operands `vwadd.wv v0,v2,v4,v0.t'
++.*Error: illegal operands `vwsub.wv v1,v2,v4'
++.*Error: illegal operands `vwsub.wv v2,v3,v4'
++.*Error: illegal operands `vwsub.wv v4,v2,v4'
++.*Error: illegal operands `vwsub.wv v4,v2,v5'
++.*Error: illegal operands `vwsub.wv v0,v2,v4,v0.t'
++.*Error: illegal operands `vfwadd.wv v1,v2,v4'
++.*Error: illegal operands `vfwadd.wv v2,v3,v4'
++.*Error: illegal operands `vfwadd.wv v4,v2,v4'
++.*Error: illegal operands `vfwadd.wv v4,v2,v5'
++.*Error: illegal operands `vfwadd.wv v0,v2,v4,v0.t'
++.*Error: illegal operands `vfwsub.wv v1,v2,v4'
++.*Error: illegal operands `vfwsub.wv v2,v3,v4'
++.*Error: illegal operands `vfwsub.wv v4,v2,v4'
++.*Error: illegal operands `vfwsub.wv v4,v2,v5'
++.*Error: illegal operands `vfwsub.wv v0,v2,v4,v0.t'
++.*Error: illegal operands `vwaddu.wx v1,v2,a1'
++.*Error: illegal operands `vwaddu.wx v2,v3,a1'
++.*Error: illegal operands `vwaddu.wx v0,v2,a1,v0.t'
++.*Error: illegal operands `vwsubu.wx v1,v2,a1'
++.*Error: illegal operands `vwsubu.wx v2,v3,a1'
++.*Error: illegal operands `vwsubu.wx v0,v2,a1,v0.t'
++.*Error: illegal operands `vwadd.wx v1,v2,a1'
++.*Error: illegal operands `vwadd.wx v2,v3,a1'
++.*Error: illegal operands `vwadd.wx v0,v2,a1,v0.t'
++.*Error: illegal operands `vwsub.wx v1,v2,a1'
++.*Error: illegal operands `vwsub.wx v2,v3,a1'
++.*Error: illegal operands `vwsub.wx v0,v2,a1,v0.t'
++.*Error: illegal operands `vfwadd.wf v1,v2,fa1'
++.*Error: illegal operands `vfwadd.wf v2,v3,fa1'
++.*Error: illegal operands `vfwadd.wf v0,v2,fa1,v0.t'
++.*Error: illegal operands `vfwsub.wf v1,v2,fa1'
++.*Error: illegal operands `vfwsub.wf v2,v3,fa1'
++.*Error: illegal operands `vfwsub.wf v0,v2,fa1,v0.t'
+diff --git a/gas/testsuite/gas/riscv/vector-insns-fail-04.s b/gas/testsuite/gas/riscv/vector-insns-fail-04.s
+new file mode 100644
+index 0000000000..e1db16d53b
+--- /dev/null
++++ b/gas/testsuite/gas/riscv/vector-insns-fail-04.s
+@@ -0,0 +1,85 @@
++# Widening Vector Arithmetic Instructions (W[V|X])
++
++	vwaddu.wv v0, v2, v4		# OK
++	vwaddu.wv v1, v2, v4		# vd should be multiple of 2
++	vwaddu.wv v2, v2, v4		# OK
++	vwaddu.wv v2, v3, v4		# vs2 should be multiple of 2
++	vwaddu.wv v4, v2, v4		# vd overlap vs1
++	vwaddu.wv v4, v2, v5		# vd overlap vs1
++	vwaddu.wv v0, v2, v4, v0.t	# vd overlap vm
++
++	vwsubu.wv v0, v2, v4		# OK
++	vwsubu.wv v1, v2, v4		# vd should be multiple of 2
++	vwsubu.wv v2, v2, v4		# OK
++	vwsubu.wv v2, v3, v4		# vs2 should be multiple of 2
++	vwsubu.wv v4, v2, v4		# vd overlap vs1
++	vwsubu.wv v4, v2, v5		# vd overlap vs1
++	vwsubu.wv v0, v2, v4, v0.t	# vd overlap vm
++
++	vwadd.wv v0, v2, v4		# OK
++	vwadd.wv v1, v2, v4		# vd should be multiple of 2
++	vwadd.wv v2, v2, v4		# OK
++	vwadd.wv v2, v3, v4		# vs2 should be multiple of 2
++	vwadd.wv v4, v2, v4		# vd overlap vs1
++	vwadd.wv v4, v2, v5		# vd overlap vs1
++	vwadd.wv v0, v2, v4, v0.t	# vd overlap vm
++
++	vwsub.wv v0, v2, v4		# OK
++	vwsub.wv v1, v2, v4		# vd should be multiple of 2
++	vwsub.wv v2, v2, v4		# OK
++	vwsub.wv v2, v3, v4		# vs2 should be multiple of 2
++	vwsub.wv v4, v2, v4		# vd overlap vs1
++	vwsub.wv v4, v2, v5		# vd overlap vs1
++	vwsub.wv v0, v2, v4, v0.t	# vd overlap vm
++
++	vfwadd.wv v0, v2, v4		# OK
++	vfwadd.wv v1, v2, v4		# vd should be multiple of 2
++	vfwadd.wv v2, v2, v4		# OK
++	vfwadd.wv v2, v3, v4		# vs2 should be multiple of 2
++	vfwadd.wv v4, v2, v4		# vd overlap vs1
++	vfwadd.wv v4, v2, v5		# vd overlap vs1
++	vfwadd.wv v0, v2, v4, v0.t	# vd overlap vm
++
++	vfwsub.wv v0, v2, v4		# OK
++	vfwsub.wv v1, v2, v4		# vd should be multiple of 2
++	vfwsub.wv v2, v2, v4		# OK
++	vfwsub.wv v2, v3, v4		# vs2 should be multiple of 2
++	vfwsub.wv v4, v2, v4		# vd overlap vs1
++	vfwsub.wv v4, v2, v5		# vd overlap vs1
++	vfwsub.wv v0, v2, v4, v0.t	# vd overlap vm
++
++	vwaddu.wx v0, v2, a1		# OK
++	vwaddu.wx v1, v2, a1		# vd should be multiple of 2
++	vwaddu.wx v2, v2, a1		# OK
++	vwaddu.wx v2, v3, a1		# vs2 should be multiple of 2
++	vwaddu.wx v0, v2, a1, v0.t	# vd overlap vm
++
++	vwsubu.wx v0, v2, a1		# OK
++	vwsubu.wx v1, v2, a1		# vd should be multiple of 2
++	vwsubu.wx v2, v2, a1		# OK
++	vwsubu.wx v2, v3, a1		# vs2 should be multiple of 2
++	vwsubu.wx v0, v2, a1, v0.t	# vd overlap vm
++
++	vwadd.wx v0, v2, a1		# OK
++	vwadd.wx v1, v2, a1		# vd should be multiple of 2
++	vwadd.wx v2, v2, a1		# OK
++	vwadd.wx v2, v3, a1		# vs2 should be multiple of 2
++	vwadd.wx v0, v2, a1, v0.t	# vd overlap vm
++
++	vwsub.wx v0, v2, a1		# OK
++	vwsub.wx v1, v2, a1		# vd should be multiple of 2
++	vwsub.wx v2, v2, a1		# OK
++	vwsub.wx v2, v3, a1		# vs2 should be multiple of 2
++	vwsub.wx v0, v2, a1, v0.t	# vd overlap vm
++
++	vfwadd.wf v0, v2, fa1		# OK
++	vfwadd.wf v1, v2, fa1		# vd should be multiple of 2
++	vfwadd.wf v2, v2, fa1		# OK
++	vfwadd.wf v2, v3, fa1		# vs2 should be multiple of 2
++	vfwadd.wf v0, v2, fa1, v0.t	# vd overlap vm
++
++	vfwsub.wf v0, v2, fa1		# OK
++	vfwsub.wf v1, v2, fa1		# vd should be multiple of 2
++	vfwsub.wf v2, v2, fa1		# OK
++	vfwsub.wf v2, v3, fa1		# vs2 should be multiple of 2
++	vfwsub.wf v0, v2, fa1, v0.t	# vd overlap vm
+diff --git a/gas/testsuite/gas/riscv/vector-insns-fail-05.d b/gas/testsuite/gas/riscv/vector-insns-fail-05.d
+new file mode 100644
+index 0000000000..b13053ab06
+--- /dev/null
++++ b/gas/testsuite/gas/riscv/vector-insns-fail-05.d
+@@ -0,0 +1,3 @@
++#as: -march=rv32ifv -mcheck-constraints
++#source: vector-insns-fail-05.s
++#error_output: vector-insns-fail-05.l
+diff --git a/gas/testsuite/gas/riscv/vector-insns-fail-05.l b/gas/testsuite/gas/riscv/vector-insns-fail-05.l
+new file mode 100644
+index 0000000000..fa519ffcf9
+--- /dev/null
++++ b/gas/testsuite/gas/riscv/vector-insns-fail-05.l
+@@ -0,0 +1,61 @@
++.*: Assembler messages:
++.*Error: illegal operands `vnsrl.wv v2,v2,v4'
++.*Error: illegal operands `vnsrl.wv v2,v3,v4'
++.*Error: illegal operands `vnsrl.wv v3,v2,v4'
++.*Error: illegal operands `vnsrl.wx v2,v2,a1'
++.*Error: illegal operands `vnsrl.wx v2,v3,a1'
++.*Error: illegal operands `vnsrl.wx v3,v2,a1'
++.*Error: illegal operands `vnsrl.wi v2,v2,1'
++.*Error: illegal operands `vnsrl.wi v2,v3,1'
++.*Error: illegal operands `vnsrl.wi v3,v2,1'
++.*Error: illegal operands `vnsra.wv v2,v2,v4'
++.*Error: illegal operands `vnsra.wv v2,v3,v4'
++.*Error: illegal operands `vnsra.wv v3,v2,v4'
++.*Error: illegal operands `vnsra.wx v2,v2,a1'
++.*Error: illegal operands `vnsra.wx v2,v3,a1'
++.*Error: illegal operands `vnsra.wx v3,v2,a1'
++.*Error: illegal operands `vnsra.wi v2,v2,1'
++.*Error: illegal operands `vnsra.wi v2,v3,1'
++.*Error: illegal operands `vnsra.wi v3,v2,1'
++.*Error: illegal operands `vnclipu.wv v2,v2,v4'
++.*Error: illegal operands `vnclipu.wv v2,v3,v4'
++.*Error: illegal operands `vnclipu.wv v3,v2,v4'
++.*Error: illegal operands `vnclipu.wx v2,v2,a1'
++.*Error: illegal operands `vnclipu.wx v2,v3,a1'
++.*Error: illegal operands `vnclipu.wx v3,v2,a1'
++.*Error: illegal operands `vnclipu.wi v2,v2,1'
++.*Error: illegal operands `vnclipu.wi v2,v3,1'
++.*Error: illegal operands `vnclipu.wi v3,v2,1'
++.*Error: illegal operands `vnclip.wv v2,v2,v4'
++.*Error: illegal operands `vnclip.wv v2,v3,v4'
++.*Error: illegal operands `vnclip.wv v3,v2,v4'
++.*Error: illegal operands `vnclip.wx v2,v2,a1'
++.*Error: illegal operands `vnclip.wx v2,v3,a1'
++.*Error: illegal operands `vnclip.wx v3,v2,a1'
++.*Error: illegal operands `vnclip.wi v2,v2,1'
++.*Error: illegal operands `vnclip.wi v2,v3,1'
++.*Error: illegal operands `vnclip.wi v3,v2,1'
++.*Error: illegal operands `vfncvt.xu.f.w v2,v2'
++.*Error: illegal operands `vfncvt.xu.f.w v2,v3'
++.*Error: illegal operands `vfncvt.xu.f.w v3,v2'
++.*Error: illegal operands `vfncvt.x.f.w v2,v2'
++.*Error: illegal operands `vfncvt.x.f.w v2,v3'
++.*Error: illegal operands `vfncvt.x.f.w v3,v2'
++.*Error: illegal operands `vfncvt.rtz.xu.f.w v2,v2'
++.*Error: illegal operands `vfncvt.rtz.xu.f.w v2,v3'
++.*Error: illegal operands `vfncvt.rtz.xu.f.w v3,v2'
++.*Error: illegal operands `vfncvt.rtz.x.f.w v2,v2'
++.*Error: illegal operands `vfncvt.rtz.x.f.w v2,v3'
++.*Error: illegal operands `vfncvt.rtz.x.f.w v3,v2'
++.*Error: illegal operands `vfncvt.f.xu.w v2,v2'
++.*Error: illegal operands `vfncvt.f.xu.w v2,v3'
++.*Error: illegal operands `vfncvt.f.xu.w v3,v2'
++.*Error: illegal operands `vfncvt.f.x.w v2,v2'
++.*Error: illegal operands `vfncvt.f.x.w v2,v3'
++.*Error: illegal operands `vfncvt.f.x.w v3,v2'
++.*Error: illegal operands `vfncvt.f.f.w v2,v2'
++.*Error: illegal operands `vfncvt.f.f.w v2,v3'
++.*Error: illegal operands `vfncvt.f.f.w v3,v2'
++.*Error: illegal operands `vfncvt.rod.f.f.w v2,v2'
++.*Error: illegal operands `vfncvt.rod.f.f.w v2,v3'
++.*Error: illegal operands `vfncvt.rod.f.f.w v3,v2'
+diff --git a/gas/testsuite/gas/riscv/vector-insns-fail-05.s b/gas/testsuite/gas/riscv/vector-insns-fail-05.s
+new file mode 100644
+index 0000000000..2ec027299c
+--- /dev/null
++++ b/gas/testsuite/gas/riscv/vector-insns-fail-05.s
+@@ -0,0 +1,133 @@
++# Narrowing Vector Arithmetic Instructions
++
++	vnsrl.wv v0, v2, v4		# OK
++	vnsrl.wv v2, v2, v4		# vd overlap vs2
++	vnsrl.wv v2, v3, v4		# vs2 should be multiple of 2
++	vnsrl.wv v3, v2, v4		# vd overlap vs2
++	vnsrl.wv v4, v2, v4		# OK
++	vnsrl.wv v0, v2, v4, v0.t	# We can't know the LMUL, so skip the vm checking
++
++	vnsrl.wx v0, v2, a1		# OK
++	vnsrl.wx v2, v2, a1		# vd overlap vs2
++	vnsrl.wx v2, v3, a1		# vs2 should be multiple of 2
++	vnsrl.wx v3, v2, a1		# vd overlap vs2
++	vnsrl.wx v0, v2, a1, v0.t	# We can't know the LMUL, so skip the vm checking
++
++	vnsrl.wi v0, v2, 1		# OK
++	vnsrl.wi v2, v2, 1		# vd overlap vs2
++	vnsrl.wi v2, v3, 1		# vs2 should be multiple of 2
++	vnsrl.wi v3, v2, 1		# vd overlap vs2
++	vnsrl.wi v0, v2, 1, v0.t	# We can't know the LMUL, so skip the vm checking
++
++	vnsra.wv v0, v2, v4		# OK
++	vnsra.wv v2, v2, v4		# vd overlap vs2
++	vnsra.wv v2, v3, v4		# vs2 should be multiple of 2
++	vnsra.wv v3, v2, v4		# vd overlap vs2
++	vnsra.wv v4, v2, v4		# OK
++	vnsra.wv v0, v2, v4, v0.t	# We can't know the LMUL, so skip the vm checking
++
++	vnsra.wx v0, v2, a1		# OK
++	vnsra.wx v2, v2, a1		# vd overlap vs2
++	vnsra.wx v2, v3, a1		# vs2 should be multiple of 2
++	vnsra.wx v3, v2, a1		# vd overlap vs2
++	vnsra.wx v0, v2, a1, v0.t	# We can't know the LMUL, so skip the vm checking
++
++	vnsra.wi v0, v2, 1		# OK
++	vnsra.wi v2, v2, 1		# vd overlap vs2
++	vnsra.wi v2, v3, 1		# vs2 should be multiple of 2
++	vnsra.wi v3, v2, 1		# vd overlap vs2
++	vnsra.wi v0, v2, 1, v0.t	# We can't know the LMUL, so skip the vm checking
++
++	vnclipu.wv v0, v2, v4		# OK
++	vnclipu.wv v2, v2, v4		# vd overlap vs2
++	vnclipu.wv v2, v3, v4		# vs2 should be multiple of 2
++	vnclipu.wv v3, v2, v4		# vd overlap vs2
++	vnclipu.wv v4, v2, v4		# OK
++	vnclipu.wv v0, v2, v4, v0.t	# We can't know the LMUL, so skip the vm checking
++
++	vnclipu.wx v0, v2, a1		# OK
++	vnclipu.wx v2, v2, a1		# vd overlap vs2
++	vnclipu.wx v2, v3, a1		# vs2 should be multiple of 2
++	vnclipu.wx v3, v2, a1		# vd overlap vs2
++	vnclipu.wx v0, v2, a1, v0.t	# We can't know the LMUL, so skip the vm checking
++
++	vnclipu.wi v0, v2, 1		# OK
++	vnclipu.wi v2, v2, 1		# vd overlap vs2
++	vnclipu.wi v2, v3, 1		# vs2 should be multiple of 2
++	vnclipu.wi v3, v2, 1		# vd overlap vs2
++	vnclipu.wi v0, v2, 1, v0.t	# We can't know the LMUL, so skip the vm checking
++
++	vnclip.wv v0, v2, v4		# OK
++	vnclip.wv v2, v2, v4		# vd overlap vs2
++	vnclip.wv v2, v3, v4		# vs2 should be multiple of 2
++	vnclip.wv v3, v2, v4		# vd overlap vs2
++	vnclip.wv v4, v2, v4		# OK
++	vnclip.wv v0, v2, v4, v0.t	# We can't know the LMUL, so skip the vm checking
++
++	vnclip.wx v0, v2, a1		# OK
++	vnclip.wx v2, v2, a1		# vd overlap vs2
++	vnclip.wx v2, v3, a1		# vs2 should be multiple of 2
++	vnclip.wx v3, v2, a1		# vd overlap vs2
++	vnclip.wx v0, v2, a1, v0.t	# We can't know the LMUL, so skip the vm checking
++
++	vnclip.wi v0, v2, 1		# OK
++	vnclip.wi v2, v2, 1		# vd overlap vs2
++	vnclip.wi v2, v3, 1		# vs2 should be multiple of 2
++	vnclip.wi v3, v2, 1		# vd overlap vs2
++	vnclip.wi v0, v2, 1, v0.t	# We can't know the LMUL, so skip the vm checking
++
++	vfncvt.xu.f.w v0, v2		# OK
++	vfncvt.xu.f.w v2, v2		# vd overlap vs2
++	vfncvt.xu.f.w v2, v3		# vs2 should be multiple of 2
++	vfncvt.xu.f.w v3, v2		# vd overlap vs2
++	vfncvt.xu.f.w v4, v2		# OK
++	vfncvt.xu.f.w v0, v2, v0.t	# We can't know the LMUL, so skip the vm checking
++
++	vfncvt.x.f.w v0, v2		# OK
++	vfncvt.x.f.w v2, v2		# vd overlap vs2
++	vfncvt.x.f.w v2, v3		# vs2 should be multiple of 2
++	vfncvt.x.f.w v3, v2		# vd overlap vs2
++	vfncvt.x.f.w v4, v2		# OK
++	vfncvt.x.f.w v0, v2, v0.t	# We can't know the LMUL, so skip the vm checking
++
++	vfncvt.rtz.xu.f.w v0, v2	# OK
++	vfncvt.rtz.xu.f.w v2, v2	# vd overlap vs2
++	vfncvt.rtz.xu.f.w v2, v3	# vs2 should be multiple of 2
++	vfncvt.rtz.xu.f.w v3, v2	# vd overlap vs2
++	vfncvt.rtz.xu.f.w v4, v2	# OK
++	vfncvt.rtz.xu.f.w v0, v2, v0.t	# We can't know the LMUL, so skip the vm checking
++
++	vfncvt.rtz.x.f.w v0, v2		# OK
++	vfncvt.rtz.x.f.w v2, v2		# vd overlap vs2
++	vfncvt.rtz.x.f.w v2, v3		# vs2 should be multiple of 2
++	vfncvt.rtz.x.f.w v3, v2		# vd overlap vs2
++	vfncvt.rtz.x.f.w v4, v2		# OK
++	vfncvt.rtz.x.f.w v0, v2, v0.t	# We can't know the LMUL, so skip the vm checking
++
++	vfncvt.f.xu.w v0, v2		# OK
++	vfncvt.f.xu.w v2, v2		# vd overlap vs2
++	vfncvt.f.xu.w v2, v3		# vs2 should be multiple of 2
++	vfncvt.f.xu.w v3, v2		# vd overlap vs2
++	vfncvt.f.xu.w v4, v2		# OK
++	vfncvt.f.xu.w v0, v2, v0.t	# We can't know the LMUL, so skip the vm checking
++
++	vfncvt.f.x.w v0, v2		# OK
++	vfncvt.f.x.w v2, v2		# vd overlap vs2
++	vfncvt.f.x.w v2, v3		# vs2 should be multiple of 2
++	vfncvt.f.x.w v3, v2		# vd overlap vs2
++	vfncvt.f.x.w v4, v2		# OK
++	vfncvt.f.x.w v0, v2, v0.t	# We can't know the LMUL, so skip the vm checking
++
++	vfncvt.f.f.w v0, v2		# OK
++	vfncvt.f.f.w v2, v2		# vd overlap vs2
++	vfncvt.f.f.w v2, v3		# vs2 should be multiple of 2
++	vfncvt.f.f.w v3, v2		# vd overlap vs2
++	vfncvt.f.f.w v4, v2		# OK
++	vfncvt.f.f.w v0, v2, v0.t	# We can't know the LMUL, so skip the vm checking
++
++	vfncvt.rod.f.f.w v0, v2		# OK
++	vfncvt.rod.f.f.w v2, v2		# vd overlap vs2
++	vfncvt.rod.f.f.w v2, v3		# vs2 should be multiple of 2
++	vfncvt.rod.f.f.w v3, v2		# vd overlap vs2
++	vfncvt.rod.f.f.w v4, v2		# OK
++	vfncvt.rod.f.f.w v0, v2, v0.t	# We can't know the LMUL, so skip the vm checking
+diff --git a/gas/testsuite/gas/riscv/vector-insns-fail-06.d b/gas/testsuite/gas/riscv/vector-insns-fail-06.d
+new file mode 100644
+index 0000000000..a2a2220d68
+--- /dev/null
++++ b/gas/testsuite/gas/riscv/vector-insns-fail-06.d
+@@ -0,0 +1,3 @@
++#as: -march=rv32ifv -mcheck-constraints
++#source: vector-insns-fail-06.s
++#error_output: vector-insns-fail-06.l
+diff --git a/gas/testsuite/gas/riscv/vector-insns-fail-06.l b/gas/testsuite/gas/riscv/vector-insns-fail-06.l
+new file mode 100644
+index 0000000000..9a86dd37b5
+--- /dev/null
++++ b/gas/testsuite/gas/riscv/vector-insns-fail-06.l
+@@ -0,0 +1,22 @@
++.*: Assembler messages:
++.*Error: illegal operands `viota.m v2,v2'
++.*Error: illegal operands `viota.m v0,v2,v0.t'
++.*Error: illegal operands `vslideup.vx v2,v2,a4'
++.*Error: illegal operands `vslideup.vi v2,v2,1'
++.*Error: illegal operands `vslide1up.vx v2,v2,a4'
++.*Error: illegal operands `vfslide1up.vf v2,v2,fa4'
++.*Error: illegal operands `vrgather.vv v2,v2,v4'
++.*Error: illegal operands `vrgather.vv v4,v2,v4'
++.*Error: illegal operands `vrgather.vv v0,v2,v4,v0.t'
++.*Error: illegal operands `vrgather.vx v2,v2,a4'
++.*Error: illegal operands `vrgather.vx v0,v2,a4,v0.t'
++.*Error: illegal operands `vrgather.vi v2,v2,1'
++.*Error: illegal operands `vrgather.vi v0,v2,1,v0.t'
++.*Error: illegal operands `vcompress.vm v2,v2,v4'
++.*Error: illegal operands `vcompress.vm v4,v2,v4'
++.*Error: illegal operands `vmv2r.v v1,v2'
++.*Error: illegal operands `vmv2r.v v2,v3'
++.*Error: illegal operands `vmv4r.v v2,v4'
++.*Error: illegal operands `vmv4r.v v4,v7'
++.*Error: illegal operands `vmv8r.v v6,v8'
++.*Error: illegal operands `vmv8r.v v8,v12'
+diff --git a/gas/testsuite/gas/riscv/vector-insns-fail-06.s b/gas/testsuite/gas/riscv/vector-insns-fail-06.s
+new file mode 100644
+index 0000000000..df0edd44c9
+--- /dev/null
++++ b/gas/testsuite/gas/riscv/vector-insns-fail-06.s
+@@ -0,0 +1,67 @@
++# Vector Iota Instruction
++# Vector Slideup Instructions
++# Vector Slide1up
++# Vector Register Gather Instruction
++# Vector Compress Instruction
++# Vector Load/Store Whole Register Instructions
++# Whole Vector Register Move
++
++	viota.m v0, v2		# OK
++	viota.m v2, v2		# vd overlap vs2
++	viota.m v0, v2, v0.t	# vd overlap vm
++
++	vslideup.vx v0, v2, a4		# OK
++	vslideup.vx v1, v2, a4		# OK
++	vslideup.vx v2, v2, a4		# vd overlap vs2
++	vslideup.vx v0, v2, a4, v0.t	# vd overlap vm
++
++	vslideup.vi v0, v2, 1		# OK
++	vslideup.vi v1, v2, 1		# OK
++	vslideup.vi v2, v2, 1		# vd overlap vs2
++	vslideup.vi v0, v2, 1, v0.t	# vd overlap vm
++
++	vslide1up.vx v0, v2, a4		# OK
++	vslide1up.vx v1, v2, a4		# OK
++	vslide1up.vx v2, v2, a4		# vd overlap vs2
++	vslide1up.vx v0, v2, a4, v0.t	# vd overlap vm
++
++	vfslide1up.vf v0, v2, fa4	# OK
++	vfslide1up.vf v1, v2, fa4	# OK
++	vfslide1up.vf v2, v2, fa4	# vd overlap vs2
++	vfslide1up.vf v0, v2, fa4, v0.t	# vd overlap vm
++
++	vrgather.vv v0, v2, v4		# OK
++	vrgather.vv v1, v2, v4		# OK
++	vrgather.vv v2, v2, v4		# vd overlap vs2
++	vrgather.vv v4, v2, v4		# vd overlap vs1
++	vrgather.vv v0, v2, v4, v0.t	# vd overlap vm
++
++	vrgather.vx v0, v2, a4		# OK
++	vrgather.vx v1, v2, a4		# OK
++	vrgather.vx v2, v2, a4		# vd overlap vs2
++	vrgather.vx v0, v2, a4, v0.t	# vd overlap vm
++
++	vrgather.vi v0, v2, 1		# OK
++	vrgather.vi v1, v2, 1		# OK
++	vrgather.vi v2, v2, 1		# vd overlap vs2
++	vrgather.vi v0, v2, 1, v0.t	# vd overlap vm
++
++	vcompress.vm v0, v2, v4		# OK
++	vcompress.vm v1, v2, v4		# OK
++	vcompress.vm v2, v2, v4		# vd overlap vs2
++	vcompress.vm v4, v2, v4		# vd overlap vs1
++
++	vmv1r.v v0, v1		# OK
++	vmv1r.v v2, v3		# OK
++
++	vmv2r.v v0, v2		# OK
++	vmv2r.v v1, v2		# vd must be aligned to 2
++	vmv2r.v v2, v3		# vs2 must be aligned to 2
++
++	vmv4r.v v0, v4		# OK
++	vmv4r.v v2, v4		# vd must be aligned to 4
++	vmv4r.v v4, v7		# vs2 must be aligned to 4
++
++	vmv8r.v v0, v8		# OK
++	vmv8r.v v6, v8		# vd must be aligned to 8
++	vmv8r.v v8, v12		# vs2 must be aligned to 8
+diff --git a/gas/testsuite/gas/riscv/vector-insns-fail-zvediv.d b/gas/testsuite/gas/riscv/vector-insns-fail-zvediv.d
+new file mode 100644
+index 0000000000..a730a2e941
+--- /dev/null
++++ b/gas/testsuite/gas/riscv/vector-insns-fail-zvediv.d
+@@ -0,0 +1,20 @@
++#as: -march=rv32iv
++#source: vector-insns-fail-zvediv.s
++#warning_output: vector-insns-fail-zvediv.l
++#objdump: -dr
++
++.*:[ 	]+file format .*
++
++
++Disassembly of section .text:
++
++0+000 <.text>:
++[ 	]+[0-9a-f]+:[ 	]+0005f557[ 	]+vsetvli[ 	]+a0,a1,e8,m1,tu,mu,d1
++[ 	]+[0-9a-f]+:[ 	]+7ff5f557[ 	]+vsetvli[ 	]+a0,a1,2047
++[ 	]+[0-9a-f]+:[ 	]+3005f557[ 	]+vsetvli[ 	]+a0,a1,e8,m1,tu,mu,d8
++[ 	]+[0-9a-f]+:[ 	]+4ff5f557[ 	]+vsetvli[ 	]+a0,a1,1279
++[ 	]+[0-9a-f]+:[ 	]+0005f557[ 	]+vsetvli[ 	]+a0,a1,e8,m1,tu,mu,d1
++[ 	]+[0-9a-f]+:[ 	]+0005f557[ 	]+vsetvli[ 	]+a0,a1,e8,m1,tu,mu,d1
++[ 	]+[0-9a-f]+:[ 	]+1005f557[ 	]+vsetvli[ 	]+a0,a1,e8,m1,tu,mu,d2
++[ 	]+[0-9a-f]+:[ 	]+2005f557[ 	]+vsetvli[ 	]+a0,a1,e8,m1,tu,mu,d4
++[ 	]+[0-9a-f]+:[ 	]+3005f557[ 	]+vsetvli[ 	]+a0,a1,e8,m1,tu,mu,d8
+diff --git a/gas/testsuite/gas/riscv/vector-insns-fail-zvediv.l b/gas/testsuite/gas/riscv/vector-insns-fail-zvediv.l
+new file mode 100644
+index 0000000000..2b0b73bc64
+--- /dev/null
++++ b/gas/testsuite/gas/riscv/vector-insns-fail-zvediv.l
+@@ -0,0 +1,6 @@
++.*Assembler messages:
++.*2: Warning: vediv is set but Zvediv extension isn't enabled
++.*3: Warning: vediv is set but Zvediv extension isn't enabled
++.*7: Warning: vediv is set but Zvediv extension isn't enabled
++.*8: Warning: vediv is set but Zvediv extension isn't enabled
++.*9: Warning: vediv is set but Zvediv extension isn't enabled
+diff --git a/gas/testsuite/gas/riscv/vector-insns-fail-zvediv.s b/gas/testsuite/gas/riscv/vector-insns-fail-zvediv.s
+new file mode 100644
+index 0000000000..834cc17c4a
+--- /dev/null
++++ b/gas/testsuite/gas/riscv/vector-insns-fail-zvediv.s
+@@ -0,0 +1,9 @@
++	vsetvli a0, a1, 0
++	vsetvli a0, a1, 0x7ff
++	vsetvli a0, a1, 0x300
++	vsetvli a0, a1, 0x4ff
++	vsetvli a0, a1, e8, m1
++	vsetvli a0, a1, e8, m1, d1
++	vsetvli a0, a1, e8, m1, d2
++	vsetvli a0, a1, e8, m1, d4
++	vsetvli a0, a1, e8, m1, d8
+diff --git a/gas/testsuite/gas/riscv/vector-insns-vmsgtvx.d b/gas/testsuite/gas/riscv/vector-insns-vmsgtvx.d
+new file mode 100644
+index 0000000000..4d33fe7d59
+--- /dev/null
++++ b/gas/testsuite/gas/riscv/vector-insns-vmsgtvx.d
+@@ -0,0 +1,29 @@
++#as: -march=rv32iv
++#objdump: -dr
++
++.*:[ 	]+file format .*
++
++
++Disassembly of section .text:
++
++0+000 <.text>:
++[ 	]+[0-9a-f]+:[ 	]+6e85c257[ 	]+vmslt.vx[ 	]+v4,v8,a1
++[ 	]+[0-9a-f]+:[ 	]+76422257[ 	]+vmnot.m[ 	]+v4,v4
++[ 	]+[0-9a-f]+:[ 	]+6cc64457[ 	]+vmslt.vx[ 	]+v8,v12,a2,v0.t
++[ 	]+[0-9a-f]+:[ 	]+6e802457[ 	]+vmxor.mm[ 	]+v8,v8,v0
++[ 	]+[0-9a-f]+:[ 	]+6c85c657[ 	]+vmslt.vx[ 	]+v12,v8,a1,v0.t
++[ 	]+[0-9a-f]+:[ 	]+62062057[ 	]+vmandnot.mm[ 	]+v0,v0,v12
++[ 	]+[0-9a-f]+:[ 	]+6c85c657[ 	]+vmslt.vx[ 	]+v12,v8,a1,v0.t
++[ 	]+[0-9a-f]+:[ 	]+62062657[ 	]+vmandnot.mm[ 	]+v12,v0,v12
++[ 	]+[0-9a-f]+:[ 	]+62402257[ 	]+vmandnot.mm[ 	]+v4,v4,v0
++[ 	]+[0-9a-f]+:[ 	]+6ac22257[ 	]+vmor.mm[ 	]+v4,v12,v4
++[ 	]+[0-9a-f]+:[ 	]+6a85c257[ 	]+vmsltu.vx[ 	]+v4,v8,a1
++[ 	]+[0-9a-f]+:[ 	]+76422257[ 	]+vmnot.m[ 	]+v4,v4
++[ 	]+[0-9a-f]+:[ 	]+68c64457[ 	]+vmsltu.vx[ 	]+v8,v12,a2,v0.t
++[ 	]+[0-9a-f]+:[ 	]+6e802457[ 	]+vmxor.mm[ 	]+v8,v8,v0
++[ 	]+[0-9a-f]+:[ 	]+6885c657[ 	]+vmsltu.vx[ 	]+v12,v8,a1,v0.t
++[ 	]+[0-9a-f]+:[ 	]+62062057[ 	]+vmandnot.mm[ 	]+v0,v0,v12
++[ 	]+[0-9a-f]+:[ 	]+6885c657[ 	]+vmsltu.vx[ 	]+v12,v8,a1,v0.t
++[ 	]+[0-9a-f]+:[ 	]+62062657[ 	]+vmandnot.mm[ 	]+v12,v0,v12
++[ 	]+[0-9a-f]+:[ 	]+62402257[ 	]+vmandnot.mm[ 	]+v4,v4,v0
++[ 	]+[0-9a-f]+:[ 	]+6ac22257[ 	]+vmor.mm[ 	]+v4,v12,v4
+diff --git a/gas/testsuite/gas/riscv/vector-insns-vmsgtvx.s b/gas/testsuite/gas/riscv/vector-insns-vmsgtvx.s
+new file mode 100644
+index 0000000000..afbb7ccb36
+--- /dev/null
++++ b/gas/testsuite/gas/riscv/vector-insns-vmsgtvx.s
+@@ -0,0 +1,9 @@
++	vmsge.vx v4, v8, a1		# unmasked va >= x
++	vmsge.vx v8, v12, a2, v0.t	# masked va >= x, vd != v0
++	vmsge.vx v0, v8, a1, v0.t, v12	# masked va >= x, vd == v0
++	vmsge.vx v4, v8, a1, v0.t, v12	# masked va >= x, any vd
++
++	vmsgeu.vx v4, v8, a1		# unmasked va >= x
++	vmsgeu.vx v8, v12, a2, v0.t	# masked va >= x, vd != v0
++	vmsgeu.vx v0, v8, a1, v0.t, v12	# masked va >= x, vd == v0
++	vmsgeu.vx v4, v8, a1, v0.t, v12	# masked va >= x, any vd
+diff --git a/gas/testsuite/gas/riscv/vector-insns.d b/gas/testsuite/gas/riscv/vector-insns.d
+new file mode 100644
+index 0000000000..5e7267c3f8
+--- /dev/null
++++ b/gas/testsuite/gas/riscv/vector-insns.d
+@@ -0,0 +1,2384 @@
++#as: -march=rv32iafv_zvediv_zvqmac
++#objdump: -dr
++
++.*:[ 	]+file format .*
++
++
++Disassembly of section .text:
++
++0+000 <.text>:
++[ 	]+[0-9a-f]+:[ 	]+80c5f557[ 	]+vsetvl[ 	]+a0,a1,a2
++[ 	]+[0-9a-f]+:[ 	]+0005f557[ 	]+vsetvli[ 	]+a0,a1,e8,m1,tu,mu,d1
++[ 	]+[0-9a-f]+:[ 	]+7ff5f557[ 	]+vsetvli[ 	]+a0,a1,2047
++[ 	]+[0-9a-f]+:[ 	]+2055f557[ 	]+vsetvli[ 	]+a0,a1,e16,m2,tu,mu,d4
++[ 	]+[0-9a-f]+:[ 	]+3175f557[ 	]+vsetvli[ 	]+a0,a1,e256,m8,tu,mu,d8
++[ 	]+[0-9a-f]+:[ 	]+31b5f557[ 	]+vsetvli[ 	]+a0,a1,e512,m8,tu,mu,d8
++[ 	]+[0-9a-f]+:[ 	]+31f5f557[ 	]+vsetvli[ 	]+a0,a1,e1024,m8,tu,mu,d8
++[ 	]+[0-9a-f]+:[ 	]+31c5f557[ 	]+vsetvli[ 	]+a0,a1,e1024,m1,tu,mu,d8
++[ 	]+[0-9a-f]+:[ 	]+33f5f557[ 	]+vsetvli[ 	]+a0,a1,e1024,mf2,tu,mu,d8
++[ 	]+[0-9a-f]+:[ 	]+13a5f557[ 	]+vsetvli[ 	]+a0,a1,e512,mf4,tu,mu,d2
++[ 	]+[0-9a-f]+:[ 	]+2355f557[ 	]+vsetvli[ 	]+a0,a1,e256,mf8,tu,mu,d4
++[ 	]+[0-9a-f]+:[ 	]+2555f557[ 	]+vsetvli[ 	]+a0,a1,e256,m2,ta,mu,d4
++[ 	]+[0-9a-f]+:[ 	]+2955f557[ 	]+vsetvli[ 	]+a0,a1,e256,m2,tu,ma,d4
++[ 	]+[0-9a-f]+:[ 	]+2155f557[ 	]+vsetvli[ 	]+a0,a1,e256,m2,tu,mu,d4
++[ 	]+[0-9a-f]+:[ 	]+2155f557[ 	]+vsetvli[ 	]+a0,a1,e256,m2,tu,mu,d4
++[ 	]+[0-9a-f]+:[ 	]+2d55f557[ 	]+vsetvli[ 	]+a0,a1,e256,m2,ta,ma,d4
++[ 	]+[0-9a-f]+:[ 	]+2955f557[ 	]+vsetvli[ 	]+a0,a1,e256,m2,tu,ma,d4
++[ 	]+[0-9a-f]+:[ 	]+2555f557[ 	]+vsetvli[ 	]+a0,a1,e256,m2,ta,mu,d4
++[ 	]+[0-9a-f]+:[ 	]+2155f557[ 	]+vsetvli[ 	]+a0,a1,e256,m2,tu,mu,d4
++[ 	]+[0-9a-f]+:[ 	]+02050207[ 	]+vle8.v[ 	]+v4,\(a0\)
++[ 	]+[0-9a-f]+:[ 	]+02050207[ 	]+vle8.v[ 	]+v4,\(a0\)
++[ 	]+[0-9a-f]+:[ 	]+00050207[ 	]+vle8.v[ 	]+v4,\(a0\),v0.t
++[ 	]+[0-9a-f]+:[ 	]+02050227[ 	]+vse8.v[ 	]+v4,\(a0\)
++[ 	]+[0-9a-f]+:[ 	]+02050227[ 	]+vse8.v[ 	]+v4,\(a0\)
++[ 	]+[0-9a-f]+:[ 	]+00050227[ 	]+vse8.v[ 	]+v4,\(a0\),v0.t
++[ 	]+[0-9a-f]+:[ 	]+02055207[ 	]+vle16.v[ 	]+v4,\(a0\)
++[ 	]+[0-9a-f]+:[ 	]+02055207[ 	]+vle16.v[ 	]+v4,\(a0\)
++[ 	]+[0-9a-f]+:[ 	]+00055207[ 	]+vle16.v[ 	]+v4,\(a0\),v0.t
++[ 	]+[0-9a-f]+:[ 	]+02055227[ 	]+vse16.v[ 	]+v4,\(a0\)
++[ 	]+[0-9a-f]+:[ 	]+02055227[ 	]+vse16.v[ 	]+v4,\(a0\)
++[ 	]+[0-9a-f]+:[ 	]+00055227[ 	]+vse16.v[ 	]+v4,\(a0\),v0.t
++[ 	]+[0-9a-f]+:[ 	]+02056207[ 	]+vle32.v[ 	]+v4,\(a0\)
++[ 	]+[0-9a-f]+:[ 	]+02056207[ 	]+vle32.v[ 	]+v4,\(a0\)
++[ 	]+[0-9a-f]+:[ 	]+00056207[ 	]+vle32.v[ 	]+v4,\(a0\),v0.t
++[ 	]+[0-9a-f]+:[ 	]+02056227[ 	]+vse32.v[ 	]+v4,\(a0\)
++[ 	]+[0-9a-f]+:[ 	]+02056227[ 	]+vse32.v[ 	]+v4,\(a0\)
++[ 	]+[0-9a-f]+:[ 	]+00056227[ 	]+vse32.v[ 	]+v4,\(a0\),v0.t
++[ 	]+[0-9a-f]+:[ 	]+02057207[ 	]+vle64.v[ 	]+v4,\(a0\)
++[ 	]+[0-9a-f]+:[ 	]+02057207[ 	]+vle64.v[ 	]+v4,\(a0\)
++[ 	]+[0-9a-f]+:[ 	]+00057207[ 	]+vle64.v[ 	]+v4,\(a0\),v0.t
++[ 	]+[0-9a-f]+:[ 	]+02057227[ 	]+vse64.v[ 	]+v4,\(a0\)
++[ 	]+[0-9a-f]+:[ 	]+02057227[ 	]+vse64.v[ 	]+v4,\(a0\)
++[ 	]+[0-9a-f]+:[ 	]+00057227[ 	]+vse64.v[ 	]+v4,\(a0\),v0.t
++[ 	]+[0-9a-f]+:[ 	]+12050207[ 	]+vle128.v[ 	]+v4,\(a0\)
++[ 	]+[0-9a-f]+:[ 	]+12050207[ 	]+vle128.v[ 	]+v4,\(a0\)
++[ 	]+[0-9a-f]+:[ 	]+10050207[ 	]+vle128.v[ 	]+v4,\(a0\),v0.t
++[ 	]+[0-9a-f]+:[ 	]+12050227[ 	]+vse128.v[ 	]+v4,\(a0\)
++[ 	]+[0-9a-f]+:[ 	]+12050227[ 	]+vse128.v[ 	]+v4,\(a0\)
++[ 	]+[0-9a-f]+:[ 	]+10050227[ 	]+vse128.v[ 	]+v4,\(a0\),v0.t
++[ 	]+[0-9a-f]+:[ 	]+12055207[ 	]+vle256.v[ 	]+v4,\(a0\)
++[ 	]+[0-9a-f]+:[ 	]+12055207[ 	]+vle256.v[ 	]+v4,\(a0\)
++[ 	]+[0-9a-f]+:[ 	]+10055207[ 	]+vle256.v[ 	]+v4,\(a0\),v0.t
++[ 	]+[0-9a-f]+:[ 	]+12055227[ 	]+vse256.v[ 	]+v4,\(a0\)
++[ 	]+[0-9a-f]+:[ 	]+12055227[ 	]+vse256.v[ 	]+v4,\(a0\)
++[ 	]+[0-9a-f]+:[ 	]+10055227[ 	]+vse256.v[ 	]+v4,\(a0\),v0.t
++[ 	]+[0-9a-f]+:[ 	]+12056207[ 	]+vle512.v[ 	]+v4,\(a0\)
++[ 	]+[0-9a-f]+:[ 	]+12056207[ 	]+vle512.v[ 	]+v4,\(a0\)
++[ 	]+[0-9a-f]+:[ 	]+10056207[ 	]+vle512.v[ 	]+v4,\(a0\),v0.t
++[ 	]+[0-9a-f]+:[ 	]+12056227[ 	]+vse512.v[ 	]+v4,\(a0\)
++[ 	]+[0-9a-f]+:[ 	]+12056227[ 	]+vse512.v[ 	]+v4,\(a0\)
++[ 	]+[0-9a-f]+:[ 	]+10056227[ 	]+vse512.v[ 	]+v4,\(a0\),v0.t
++[ 	]+[0-9a-f]+:[ 	]+12057207[ 	]+vle1024.v[ 	]+v4,\(a0\)
++[ 	]+[0-9a-f]+:[ 	]+12057207[ 	]+vle1024.v[ 	]+v4,\(a0\)
++[ 	]+[0-9a-f]+:[ 	]+10057207[ 	]+vle1024.v[ 	]+v4,\(a0\),v0.t
++[ 	]+[0-9a-f]+:[ 	]+12057227[ 	]+vse1024.v[ 	]+v4,\(a0\)
++[ 	]+[0-9a-f]+:[ 	]+12057227[ 	]+vse1024.v[ 	]+v4,\(a0\)
++[ 	]+[0-9a-f]+:[ 	]+10057227[ 	]+vse1024.v[ 	]+v4,\(a0\),v0.t
++[ 	]+[0-9a-f]+:[ 	]+0ab50207[ 	]+vlse8.v[ 	]+v4,\(a0\),a1
++[ 	]+[0-9a-f]+:[ 	]+0ab50207[ 	]+vlse8.v[ 	]+v4,\(a0\),a1
++[ 	]+[0-9a-f]+:[ 	]+08b50207[ 	]+vlse8.v[ 	]+v4,\(a0\),a1,v0.t
++[ 	]+[0-9a-f]+:[ 	]+0ab50227[ 	]+vsse8.v[ 	]+v4,\(a0\),a1
++[ 	]+[0-9a-f]+:[ 	]+0ab50227[ 	]+vsse8.v[ 	]+v4,\(a0\),a1
++[ 	]+[0-9a-f]+:[ 	]+08b50227[ 	]+vsse8.v[ 	]+v4,\(a0\),a1,v0.t
++[ 	]+[0-9a-f]+:[ 	]+0ab55207[ 	]+vlse16.v[ 	]+v4,\(a0\),a1
++[ 	]+[0-9a-f]+:[ 	]+0ab55207[ 	]+vlse16.v[ 	]+v4,\(a0\),a1
++[ 	]+[0-9a-f]+:[ 	]+08b55207[ 	]+vlse16.v[ 	]+v4,\(a0\),a1,v0.t
++[ 	]+[0-9a-f]+:[ 	]+0ab55227[ 	]+vsse16.v[ 	]+v4,\(a0\),a1
++[ 	]+[0-9a-f]+:[ 	]+0ab55227[ 	]+vsse16.v[ 	]+v4,\(a0\),a1
++[ 	]+[0-9a-f]+:[ 	]+08b55227[ 	]+vsse16.v[ 	]+v4,\(a0\),a1,v0.t
++[ 	]+[0-9a-f]+:[ 	]+0ab56207[ 	]+vlse32.v[ 	]+v4,\(a0\),a1
++[ 	]+[0-9a-f]+:[ 	]+0ab56207[ 	]+vlse32.v[ 	]+v4,\(a0\),a1
++[ 	]+[0-9a-f]+:[ 	]+08b56207[ 	]+vlse32.v[ 	]+v4,\(a0\),a1,v0.t
++[ 	]+[0-9a-f]+:[ 	]+0ab56227[ 	]+vsse32.v[ 	]+v4,\(a0\),a1
++[ 	]+[0-9a-f]+:[ 	]+0ab56227[ 	]+vsse32.v[ 	]+v4,\(a0\),a1
++[ 	]+[0-9a-f]+:[ 	]+08b56227[ 	]+vsse32.v[ 	]+v4,\(a0\),a1,v0.t
++[ 	]+[0-9a-f]+:[ 	]+0ab57207[ 	]+vlse64.v[ 	]+v4,\(a0\),a1
++[ 	]+[0-9a-f]+:[ 	]+0ab57207[ 	]+vlse64.v[ 	]+v4,\(a0\),a1
++[ 	]+[0-9a-f]+:[ 	]+08b57207[ 	]+vlse64.v[ 	]+v4,\(a0\),a1,v0.t
++[ 	]+[0-9a-f]+:[ 	]+0ab57227[ 	]+vsse64.v[ 	]+v4,\(a0\),a1
++[ 	]+[0-9a-f]+:[ 	]+0ab57227[ 	]+vsse64.v[ 	]+v4,\(a0\),a1
++[ 	]+[0-9a-f]+:[ 	]+08b57227[ 	]+vsse64.v[ 	]+v4,\(a0\),a1,v0.t
++[ 	]+[0-9a-f]+:[ 	]+1ab50207[ 	]+vlse128.v[ 	]+v4,\(a0\),a1
++[ 	]+[0-9a-f]+:[ 	]+1ab50207[ 	]+vlse128.v[ 	]+v4,\(a0\),a1
++[ 	]+[0-9a-f]+:[ 	]+18b50207[ 	]+vlse128.v[ 	]+v4,\(a0\),a1,v0.t
++[ 	]+[0-9a-f]+:[ 	]+1ab50227[ 	]+vsse128.v[ 	]+v4,\(a0\),a1
++[ 	]+[0-9a-f]+:[ 	]+1ab50227[ 	]+vsse128.v[ 	]+v4,\(a0\),a1
++[ 	]+[0-9a-f]+:[ 	]+18b50227[ 	]+vsse128.v[ 	]+v4,\(a0\),a1,v0.t
++[ 	]+[0-9a-f]+:[ 	]+1ab55207[ 	]+vlse256.v[ 	]+v4,\(a0\),a1
++[ 	]+[0-9a-f]+:[ 	]+1ab55207[ 	]+vlse256.v[ 	]+v4,\(a0\),a1
++[ 	]+[0-9a-f]+:[ 	]+18b55207[ 	]+vlse256.v[ 	]+v4,\(a0\),a1,v0.t
++[ 	]+[0-9a-f]+:[ 	]+1ab55227[ 	]+vsse256.v[ 	]+v4,\(a0\),a1
++[ 	]+[0-9a-f]+:[ 	]+1ab55227[ 	]+vsse256.v[ 	]+v4,\(a0\),a1
++[ 	]+[0-9a-f]+:[ 	]+18b55227[ 	]+vsse256.v[ 	]+v4,\(a0\),a1,v0.t
++[ 	]+[0-9a-f]+:[ 	]+1ab56207[ 	]+vlse512.v[ 	]+v4,\(a0\),a1
++[ 	]+[0-9a-f]+:[ 	]+1ab56207[ 	]+vlse512.v[ 	]+v4,\(a0\),a1
++[ 	]+[0-9a-f]+:[ 	]+18b56207[ 	]+vlse512.v[ 	]+v4,\(a0\),a1,v0.t
++[ 	]+[0-9a-f]+:[ 	]+1ab56227[ 	]+vsse512.v[ 	]+v4,\(a0\),a1
++[ 	]+[0-9a-f]+:[ 	]+1ab56227[ 	]+vsse512.v[ 	]+v4,\(a0\),a1
++[ 	]+[0-9a-f]+:[ 	]+18b56227[ 	]+vsse512.v[ 	]+v4,\(a0\),a1,v0.t
++[ 	]+[0-9a-f]+:[ 	]+1ab57207[ 	]+vlse1024.v[ 	]+v4,\(a0\),a1
++[ 	]+[0-9a-f]+:[ 	]+1ab57207[ 	]+vlse1024.v[ 	]+v4,\(a0\),a1
++[ 	]+[0-9a-f]+:[ 	]+18b57207[ 	]+vlse1024.v[ 	]+v4,\(a0\),a1,v0.t
++[ 	]+[0-9a-f]+:[ 	]+1ab57227[ 	]+vsse1024.v[ 	]+v4,\(a0\),a1
++[ 	]+[0-9a-f]+:[ 	]+1ab57227[ 	]+vsse1024.v[ 	]+v4,\(a0\),a1
++[ 	]+[0-9a-f]+:[ 	]+18b57227[ 	]+vsse1024.v[ 	]+v4,\(a0\),a1,v0.t
++[ 	]+[0-9a-f]+:[ 	]+0ec50207[ 	]+vlxei8.v[ 	]+v4,\(a0\),v12
++[ 	]+[0-9a-f]+:[ 	]+0ec50207[ 	]+vlxei8.v[ 	]+v4,\(a0\),v12
++[ 	]+[0-9a-f]+:[ 	]+0cc50207[ 	]+vlxei8.v[ 	]+v4,\(a0\),v12,v0.t
++[ 	]+[0-9a-f]+:[ 	]+0ec50227[ 	]+vsxei8.v[ 	]+v4,\(a0\),v12
++[ 	]+[0-9a-f]+:[ 	]+0ec50227[ 	]+vsxei8.v[ 	]+v4,\(a0\),v12
++[ 	]+[0-9a-f]+:[ 	]+0cc50227[ 	]+vsxei8.v[ 	]+v4,\(a0\),v12,v0.t
++[ 	]+[0-9a-f]+:[ 	]+06c50227[ 	]+vsuxei8.v[ 	]+v4,\(a0\),v12
++[ 	]+[0-9a-f]+:[ 	]+06c50227[ 	]+vsuxei8.v[ 	]+v4,\(a0\),v12
++[ 	]+[0-9a-f]+:[ 	]+04c50227[ 	]+vsuxei8.v[ 	]+v4,\(a0\),v12,v0.t
++[ 	]+[0-9a-f]+:[ 	]+0ec55207[ 	]+vlxei16.v[ 	]+v4,\(a0\),v12
++[ 	]+[0-9a-f]+:[ 	]+0ec55207[ 	]+vlxei16.v[ 	]+v4,\(a0\),v12
++[ 	]+[0-9a-f]+:[ 	]+0cc55207[ 	]+vlxei16.v[ 	]+v4,\(a0\),v12,v0.t
++[ 	]+[0-9a-f]+:[ 	]+0ec55227[ 	]+vsxei16.v[ 	]+v4,\(a0\),v12
++[ 	]+[0-9a-f]+:[ 	]+0ec55227[ 	]+vsxei16.v[ 	]+v4,\(a0\),v12
++[ 	]+[0-9a-f]+:[ 	]+0cc55227[ 	]+vsxei16.v[ 	]+v4,\(a0\),v12,v0.t
++[ 	]+[0-9a-f]+:[ 	]+06c55227[ 	]+vsuxei16.v[ 	]+v4,\(a0\),v12
++[ 	]+[0-9a-f]+:[ 	]+06c55227[ 	]+vsuxei16.v[ 	]+v4,\(a0\),v12
++[ 	]+[0-9a-f]+:[ 	]+04c55227[ 	]+vsuxei16.v[ 	]+v4,\(a0\),v12,v0.t
++[ 	]+[0-9a-f]+:[ 	]+0ec56207[ 	]+vlxei32.v[ 	]+v4,\(a0\),v12
++[ 	]+[0-9a-f]+:[ 	]+0ec56207[ 	]+vlxei32.v[ 	]+v4,\(a0\),v12
++[ 	]+[0-9a-f]+:[ 	]+0cc56207[ 	]+vlxei32.v[ 	]+v4,\(a0\),v12,v0.t
++[ 	]+[0-9a-f]+:[ 	]+0ec56227[ 	]+vsxei32.v[ 	]+v4,\(a0\),v12
++[ 	]+[0-9a-f]+:[ 	]+0ec56227[ 	]+vsxei32.v[ 	]+v4,\(a0\),v12
++[ 	]+[0-9a-f]+:[ 	]+0cc56227[ 	]+vsxei32.v[ 	]+v4,\(a0\),v12,v0.t
++[ 	]+[0-9a-f]+:[ 	]+06c56227[ 	]+vsuxei32.v[ 	]+v4,\(a0\),v12
++[ 	]+[0-9a-f]+:[ 	]+06c56227[ 	]+vsuxei32.v[ 	]+v4,\(a0\),v12
++[ 	]+[0-9a-f]+:[ 	]+04c56227[ 	]+vsuxei32.v[ 	]+v4,\(a0\),v12,v0.t
++[ 	]+[0-9a-f]+:[ 	]+0ec57207[ 	]+vlxei64.v[ 	]+v4,\(a0\),v12
++[ 	]+[0-9a-f]+:[ 	]+0ec57207[ 	]+vlxei64.v[ 	]+v4,\(a0\),v12
++[ 	]+[0-9a-f]+:[ 	]+0cc57207[ 	]+vlxei64.v[ 	]+v4,\(a0\),v12,v0.t
++[ 	]+[0-9a-f]+:[ 	]+0ec57227[ 	]+vsxei64.v[ 	]+v4,\(a0\),v12
++[ 	]+[0-9a-f]+:[ 	]+0ec57227[ 	]+vsxei64.v[ 	]+v4,\(a0\),v12
++[ 	]+[0-9a-f]+:[ 	]+0cc57227[ 	]+vsxei64.v[ 	]+v4,\(a0\),v12,v0.t
++[ 	]+[0-9a-f]+:[ 	]+06c57227[ 	]+vsuxei64.v[ 	]+v4,\(a0\),v12
++[ 	]+[0-9a-f]+:[ 	]+06c57227[ 	]+vsuxei64.v[ 	]+v4,\(a0\),v12
++[ 	]+[0-9a-f]+:[ 	]+04c57227[ 	]+vsuxei64.v[ 	]+v4,\(a0\),v12,v0.t
++[ 	]+[0-9a-f]+:[ 	]+1ec50207[ 	]+vlxei128.v[ 	]+v4,\(a0\),v12
++[ 	]+[0-9a-f]+:[ 	]+1ec50207[ 	]+vlxei128.v[ 	]+v4,\(a0\),v12
++[ 	]+[0-9a-f]+:[ 	]+1cc50207[ 	]+vlxei128.v[ 	]+v4,\(a0\),v12,v0.t
++[ 	]+[0-9a-f]+:[ 	]+1ec50227[ 	]+vsxei128.v[ 	]+v4,\(a0\),v12
++[ 	]+[0-9a-f]+:[ 	]+1ec50227[ 	]+vsxei128.v[ 	]+v4,\(a0\),v12
++[ 	]+[0-9a-f]+:[ 	]+1cc50227[ 	]+vsxei128.v[ 	]+v4,\(a0\),v12,v0.t
++[ 	]+[0-9a-f]+:[ 	]+16c50227[ 	]+vsuxei128.v[ 	]+v4,\(a0\),v12
++[ 	]+[0-9a-f]+:[ 	]+16c50227[ 	]+vsuxei128.v[ 	]+v4,\(a0\),v12
++[ 	]+[0-9a-f]+:[ 	]+14c50227[ 	]+vsuxei128.v[ 	]+v4,\(a0\),v12,v0.t
++[ 	]+[0-9a-f]+:[ 	]+1ec55207[ 	]+vlxei256.v[ 	]+v4,\(a0\),v12
++[ 	]+[0-9a-f]+:[ 	]+1ec55207[ 	]+vlxei256.v[ 	]+v4,\(a0\),v12
++[ 	]+[0-9a-f]+:[ 	]+1cc55207[ 	]+vlxei256.v[ 	]+v4,\(a0\),v12,v0.t
++[ 	]+[0-9a-f]+:[ 	]+1ec55227[ 	]+vsxei256.v[ 	]+v4,\(a0\),v12
++[ 	]+[0-9a-f]+:[ 	]+1ec55227[ 	]+vsxei256.v[ 	]+v4,\(a0\),v12
++[ 	]+[0-9a-f]+:[ 	]+1cc55227[ 	]+vsxei256.v[ 	]+v4,\(a0\),v12,v0.t
++[ 	]+[0-9a-f]+:[ 	]+16c55227[ 	]+vsuxei256.v[ 	]+v4,\(a0\),v12
++[ 	]+[0-9a-f]+:[ 	]+16c55227[ 	]+vsuxei256.v[ 	]+v4,\(a0\),v12
++[ 	]+[0-9a-f]+:[ 	]+14c55227[ 	]+vsuxei256.v[ 	]+v4,\(a0\),v12,v0.t
++[ 	]+[0-9a-f]+:[ 	]+1ec56207[ 	]+vlxei512.v[ 	]+v4,\(a0\),v12
++[ 	]+[0-9a-f]+:[ 	]+1ec56207[ 	]+vlxei512.v[ 	]+v4,\(a0\),v12
++[ 	]+[0-9a-f]+:[ 	]+1cc56207[ 	]+vlxei512.v[ 	]+v4,\(a0\),v12,v0.t
++[ 	]+[0-9a-f]+:[ 	]+1ec56227[ 	]+vsxei512.v[ 	]+v4,\(a0\),v12
++[ 	]+[0-9a-f]+:[ 	]+1ec56227[ 	]+vsxei512.v[ 	]+v4,\(a0\),v12
++[ 	]+[0-9a-f]+:[ 	]+1cc56227[ 	]+vsxei512.v[ 	]+v4,\(a0\),v12,v0.t
++[ 	]+[0-9a-f]+:[ 	]+16c56227[ 	]+vsuxei512.v[ 	]+v4,\(a0\),v12
++[ 	]+[0-9a-f]+:[ 	]+16c56227[ 	]+vsuxei512.v[ 	]+v4,\(a0\),v12
++[ 	]+[0-9a-f]+:[ 	]+14c56227[ 	]+vsuxei512.v[ 	]+v4,\(a0\),v12,v0.t
++[ 	]+[0-9a-f]+:[ 	]+1ec57207[ 	]+vlxei1024.v[ 	]+v4,\(a0\),v12
++[ 	]+[0-9a-f]+:[ 	]+1ec57207[ 	]+vlxei1024.v[ 	]+v4,\(a0\),v12
++[ 	]+[0-9a-f]+:[ 	]+1cc57207[ 	]+vlxei1024.v[ 	]+v4,\(a0\),v12,v0.t
++[ 	]+[0-9a-f]+:[ 	]+1ec57227[ 	]+vsxei1024.v[ 	]+v4,\(a0\),v12
++[ 	]+[0-9a-f]+:[ 	]+1ec57227[ 	]+vsxei1024.v[ 	]+v4,\(a0\),v12
++[ 	]+[0-9a-f]+:[ 	]+1cc57227[ 	]+vsxei1024.v[ 	]+v4,\(a0\),v12,v0.t
++[ 	]+[0-9a-f]+:[ 	]+16c57227[ 	]+vsuxei1024.v[ 	]+v4,\(a0\),v12
++[ 	]+[0-9a-f]+:[ 	]+16c57227[ 	]+vsuxei1024.v[ 	]+v4,\(a0\),v12
++[ 	]+[0-9a-f]+:[ 	]+14c57227[ 	]+vsuxei1024.v[ 	]+v4,\(a0\),v12,v0.t
++[ 	]+[0-9a-f]+:[ 	]+03050207[ 	]+vle8ff.v[ 	]+v4,\(a0\)
++[ 	]+[0-9a-f]+:[ 	]+03050207[ 	]+vle8ff.v[ 	]+v4,\(a0\)
++[ 	]+[0-9a-f]+:[ 	]+01050207[ 	]+vle8ff.v[ 	]+v4,\(a0\),v0.t
++[ 	]+[0-9a-f]+:[ 	]+03055207[ 	]+vle16ff.v[ 	]+v4,\(a0\)
++[ 	]+[0-9a-f]+:[ 	]+03055207[ 	]+vle16ff.v[ 	]+v4,\(a0\)
++[ 	]+[0-9a-f]+:[ 	]+01055207[ 	]+vle16ff.v[ 	]+v4,\(a0\),v0.t
++[ 	]+[0-9a-f]+:[ 	]+03056207[ 	]+vle32ff.v[ 	]+v4,\(a0\)
++[ 	]+[0-9a-f]+:[ 	]+03056207[ 	]+vle32ff.v[ 	]+v4,\(a0\)
++[ 	]+[0-9a-f]+:[ 	]+01056207[ 	]+vle32ff.v[ 	]+v4,\(a0\),v0.t
++[ 	]+[0-9a-f]+:[ 	]+03057207[ 	]+vle64ff.v[ 	]+v4,\(a0\)
++[ 	]+[0-9a-f]+:[ 	]+03057207[ 	]+vle64ff.v[ 	]+v4,\(a0\)
++[ 	]+[0-9a-f]+:[ 	]+01057207[ 	]+vle64ff.v[ 	]+v4,\(a0\),v0.t
++[ 	]+[0-9a-f]+:[ 	]+13050207[ 	]+vle128ff.v[ 	]+v4,\(a0\)
++[ 	]+[0-9a-f]+:[ 	]+13050207[ 	]+vle128ff.v[ 	]+v4,\(a0\)
++[ 	]+[0-9a-f]+:[ 	]+11050207[ 	]+vle128ff.v[ 	]+v4,\(a0\),v0.t
++[ 	]+[0-9a-f]+:[ 	]+13055207[ 	]+vle256ff.v[ 	]+v4,\(a0\)
++[ 	]+[0-9a-f]+:[ 	]+13055207[ 	]+vle256ff.v[ 	]+v4,\(a0\)
++[ 	]+[0-9a-f]+:[ 	]+11055207[ 	]+vle256ff.v[ 	]+v4,\(a0\),v0.t
++[ 	]+[0-9a-f]+:[ 	]+13056207[ 	]+vle512ff.v[ 	]+v4,\(a0\)
++[ 	]+[0-9a-f]+:[ 	]+13056207[ 	]+vle512ff.v[ 	]+v4,\(a0\)
++[ 	]+[0-9a-f]+:[ 	]+11056207[ 	]+vle512ff.v[ 	]+v4,\(a0\),v0.t
++[ 	]+[0-9a-f]+:[ 	]+13057207[ 	]+vle1024ff.v[ 	]+v4,\(a0\)
++[ 	]+[0-9a-f]+:[ 	]+13057207[ 	]+vle1024ff.v[ 	]+v4,\(a0\)
++[ 	]+[0-9a-f]+:[ 	]+11057207[ 	]+vle1024ff.v[ 	]+v4,\(a0\),v0.t
++[ 	]+[0-9a-f]+:[ 	]+22050207[ 	]+vlseg2e8.v[ 	]+v4,\(a0\)
++[ 	]+[0-9a-f]+:[ 	]+22050207[ 	]+vlseg2e8.v[ 	]+v4,\(a0\)
++[ 	]+[0-9a-f]+:[ 	]+20050207[ 	]+vlseg2e8.v[ 	]+v4,\(a0\),v0.t
++[ 	]+[0-9a-f]+:[ 	]+22050227[ 	]+vsseg2e8.v[ 	]+v4,\(a0\)
++[ 	]+[0-9a-f]+:[ 	]+22050227[ 	]+vsseg2e8.v[ 	]+v4,\(a0\)
++[ 	]+[0-9a-f]+:[ 	]+20050227[ 	]+vsseg2e8.v[ 	]+v4,\(a0\),v0.t
++[ 	]+[0-9a-f]+:[ 	]+42050207[ 	]+vlseg3e8.v[ 	]+v4,\(a0\)
++[ 	]+[0-9a-f]+:[ 	]+42050207[ 	]+vlseg3e8.v[ 	]+v4,\(a0\)
++[ 	]+[0-9a-f]+:[ 	]+40050207[ 	]+vlseg3e8.v[ 	]+v4,\(a0\),v0.t
++[ 	]+[0-9a-f]+:[ 	]+42050227[ 	]+vsseg3e8.v[ 	]+v4,\(a0\)
++[ 	]+[0-9a-f]+:[ 	]+42050227[ 	]+vsseg3e8.v[ 	]+v4,\(a0\)
++[ 	]+[0-9a-f]+:[ 	]+40050227[ 	]+vsseg3e8.v[ 	]+v4,\(a0\),v0.t
++[ 	]+[0-9a-f]+:[ 	]+62050207[ 	]+vlseg4e8.v[ 	]+v4,\(a0\)
++[ 	]+[0-9a-f]+:[ 	]+62050207[ 	]+vlseg4e8.v[ 	]+v4,\(a0\)
++[ 	]+[0-9a-f]+:[ 	]+60050207[ 	]+vlseg4e8.v[ 	]+v4,\(a0\),v0.t
++[ 	]+[0-9a-f]+:[ 	]+62050227[ 	]+vsseg4e8.v[ 	]+v4,\(a0\)
++[ 	]+[0-9a-f]+:[ 	]+62050227[ 	]+vsseg4e8.v[ 	]+v4,\(a0\)
++[ 	]+[0-9a-f]+:[ 	]+60050227[ 	]+vsseg4e8.v[ 	]+v4,\(a0\),v0.t
++[ 	]+[0-9a-f]+:[ 	]+82050207[ 	]+vlseg5e8.v[ 	]+v4,\(a0\)
++[ 	]+[0-9a-f]+:[ 	]+82050207[ 	]+vlseg5e8.v[ 	]+v4,\(a0\)
++[ 	]+[0-9a-f]+:[ 	]+80050207[ 	]+vlseg5e8.v[ 	]+v4,\(a0\),v0.t
++[ 	]+[0-9a-f]+:[ 	]+82050227[ 	]+vsseg5e8.v[ 	]+v4,\(a0\)
++[ 	]+[0-9a-f]+:[ 	]+82050227[ 	]+vsseg5e8.v[ 	]+v4,\(a0\)
++[ 	]+[0-9a-f]+:[ 	]+80050227[ 	]+vsseg5e8.v[ 	]+v4,\(a0\),v0.t
++[ 	]+[0-9a-f]+:[ 	]+a2050207[ 	]+vlseg6e8.v[ 	]+v4,\(a0\)
++[ 	]+[0-9a-f]+:[ 	]+a2050207[ 	]+vlseg6e8.v[ 	]+v4,\(a0\)
++[ 	]+[0-9a-f]+:[ 	]+a0050207[ 	]+vlseg6e8.v[ 	]+v4,\(a0\),v0.t
++[ 	]+[0-9a-f]+:[ 	]+a2050227[ 	]+vsseg6e8.v[ 	]+v4,\(a0\)
++[ 	]+[0-9a-f]+:[ 	]+a2050227[ 	]+vsseg6e8.v[ 	]+v4,\(a0\)
++[ 	]+[0-9a-f]+:[ 	]+a0050227[ 	]+vsseg6e8.v[ 	]+v4,\(a0\),v0.t
++[ 	]+[0-9a-f]+:[ 	]+c2050207[ 	]+vlseg7e8.v[ 	]+v4,\(a0\)
++[ 	]+[0-9a-f]+:[ 	]+c2050207[ 	]+vlseg7e8.v[ 	]+v4,\(a0\)
++[ 	]+[0-9a-f]+:[ 	]+c0050207[ 	]+vlseg7e8.v[ 	]+v4,\(a0\),v0.t
++[ 	]+[0-9a-f]+:[ 	]+c2050227[ 	]+vsseg7e8.v[ 	]+v4,\(a0\)
++[ 	]+[0-9a-f]+:[ 	]+c2050227[ 	]+vsseg7e8.v[ 	]+v4,\(a0\)
++[ 	]+[0-9a-f]+:[ 	]+c0050227[ 	]+vsseg7e8.v[ 	]+v4,\(a0\),v0.t
++[ 	]+[0-9a-f]+:[ 	]+e2050207[ 	]+vlseg8e8.v[ 	]+v4,\(a0\)
++[ 	]+[0-9a-f]+:[ 	]+e2050207[ 	]+vlseg8e8.v[ 	]+v4,\(a0\)
++[ 	]+[0-9a-f]+:[ 	]+e0050207[ 	]+vlseg8e8.v[ 	]+v4,\(a0\),v0.t
++[ 	]+[0-9a-f]+:[ 	]+e2050227[ 	]+vsseg8e8.v[ 	]+v4,\(a0\)
++[ 	]+[0-9a-f]+:[ 	]+e2050227[ 	]+vsseg8e8.v[ 	]+v4,\(a0\)
++[ 	]+[0-9a-f]+:[ 	]+e0050227[ 	]+vsseg8e8.v[ 	]+v4,\(a0\),v0.t
++[ 	]+[0-9a-f]+:[ 	]+22055207[ 	]+vlseg2e16.v[ 	]+v4,\(a0\)
++[ 	]+[0-9a-f]+:[ 	]+22055207[ 	]+vlseg2e16.v[ 	]+v4,\(a0\)
++[ 	]+[0-9a-f]+:[ 	]+20055207[ 	]+vlseg2e16.v[ 	]+v4,\(a0\),v0.t
++[ 	]+[0-9a-f]+:[ 	]+22055227[ 	]+vsseg2e16.v[ 	]+v4,\(a0\)
++[ 	]+[0-9a-f]+:[ 	]+22055227[ 	]+vsseg2e16.v[ 	]+v4,\(a0\)
++[ 	]+[0-9a-f]+:[ 	]+20055227[ 	]+vsseg2e16.v[ 	]+v4,\(a0\),v0.t
++[ 	]+[0-9a-f]+:[ 	]+42055207[ 	]+vlseg3e16.v[ 	]+v4,\(a0\)
++[ 	]+[0-9a-f]+:[ 	]+42055207[ 	]+vlseg3e16.v[ 	]+v4,\(a0\)
++[ 	]+[0-9a-f]+:[ 	]+40055207[ 	]+vlseg3e16.v[ 	]+v4,\(a0\),v0.t
++[ 	]+[0-9a-f]+:[ 	]+42055227[ 	]+vsseg3e16.v[ 	]+v4,\(a0\)
++[ 	]+[0-9a-f]+:[ 	]+42055227[ 	]+vsseg3e16.v[ 	]+v4,\(a0\)
++[ 	]+[0-9a-f]+:[ 	]+40055227[ 	]+vsseg3e16.v[ 	]+v4,\(a0\),v0.t
++[ 	]+[0-9a-f]+:[ 	]+62055207[ 	]+vlseg4e16.v[ 	]+v4,\(a0\)
++[ 	]+[0-9a-f]+:[ 	]+62055207[ 	]+vlseg4e16.v[ 	]+v4,\(a0\)
++[ 	]+[0-9a-f]+:[ 	]+60055207[ 	]+vlseg4e16.v[ 	]+v4,\(a0\),v0.t
++[ 	]+[0-9a-f]+:[ 	]+62055227[ 	]+vsseg4e16.v[ 	]+v4,\(a0\)
++[ 	]+[0-9a-f]+:[ 	]+62055227[ 	]+vsseg4e16.v[ 	]+v4,\(a0\)
++[ 	]+[0-9a-f]+:[ 	]+60055227[ 	]+vsseg4e16.v[ 	]+v4,\(a0\),v0.t
++[ 	]+[0-9a-f]+:[ 	]+82055207[ 	]+vlseg5e16.v[ 	]+v4,\(a0\)
++[ 	]+[0-9a-f]+:[ 	]+82055207[ 	]+vlseg5e16.v[ 	]+v4,\(a0\)
++[ 	]+[0-9a-f]+:[ 	]+80055207[ 	]+vlseg5e16.v[ 	]+v4,\(a0\),v0.t
++[ 	]+[0-9a-f]+:[ 	]+82055227[ 	]+vsseg5e16.v[ 	]+v4,\(a0\)
++[ 	]+[0-9a-f]+:[ 	]+82055227[ 	]+vsseg5e16.v[ 	]+v4,\(a0\)
++[ 	]+[0-9a-f]+:[ 	]+80055227[ 	]+vsseg5e16.v[ 	]+v4,\(a0\),v0.t
++[ 	]+[0-9a-f]+:[ 	]+a2055207[ 	]+vlseg6e16.v[ 	]+v4,\(a0\)
++[ 	]+[0-9a-f]+:[ 	]+a2055207[ 	]+vlseg6e16.v[ 	]+v4,\(a0\)
++[ 	]+[0-9a-f]+:[ 	]+a0055207[ 	]+vlseg6e16.v[ 	]+v4,\(a0\),v0.t
++[ 	]+[0-9a-f]+:[ 	]+a2055227[ 	]+vsseg6e16.v[ 	]+v4,\(a0\)
++[ 	]+[0-9a-f]+:[ 	]+a2055227[ 	]+vsseg6e16.v[ 	]+v4,\(a0\)
++[ 	]+[0-9a-f]+:[ 	]+a0055227[ 	]+vsseg6e16.v[ 	]+v4,\(a0\),v0.t
++[ 	]+[0-9a-f]+:[ 	]+c2055207[ 	]+vlseg7e16.v[ 	]+v4,\(a0\)
++[ 	]+[0-9a-f]+:[ 	]+c2055207[ 	]+vlseg7e16.v[ 	]+v4,\(a0\)
++[ 	]+[0-9a-f]+:[ 	]+c0055207[ 	]+vlseg7e16.v[ 	]+v4,\(a0\),v0.t
++[ 	]+[0-9a-f]+:[ 	]+c2055227[ 	]+vsseg7e16.v[ 	]+v4,\(a0\)
++[ 	]+[0-9a-f]+:[ 	]+c2055227[ 	]+vsseg7e16.v[ 	]+v4,\(a0\)
++[ 	]+[0-9a-f]+:[ 	]+c0055227[ 	]+vsseg7e16.v[ 	]+v4,\(a0\),v0.t
++[ 	]+[0-9a-f]+:[ 	]+e2055207[ 	]+vlseg8e16.v[ 	]+v4,\(a0\)
++[ 	]+[0-9a-f]+:[ 	]+e2055207[ 	]+vlseg8e16.v[ 	]+v4,\(a0\)
++[ 	]+[0-9a-f]+:[ 	]+e0055207[ 	]+vlseg8e16.v[ 	]+v4,\(a0\),v0.t
++[ 	]+[0-9a-f]+:[ 	]+e2055227[ 	]+vsseg8e16.v[ 	]+v4,\(a0\)
++[ 	]+[0-9a-f]+:[ 	]+e2055227[ 	]+vsseg8e16.v[ 	]+v4,\(a0\)
++[ 	]+[0-9a-f]+:[ 	]+e0055227[ 	]+vsseg8e16.v[ 	]+v4,\(a0\),v0.t
++[ 	]+[0-9a-f]+:[ 	]+22056207[ 	]+vlseg2e32.v[ 	]+v4,\(a0\)
++[ 	]+[0-9a-f]+:[ 	]+22056207[ 	]+vlseg2e32.v[ 	]+v4,\(a0\)
++[ 	]+[0-9a-f]+:[ 	]+20056207[ 	]+vlseg2e32.v[ 	]+v4,\(a0\),v0.t
++[ 	]+[0-9a-f]+:[ 	]+22056227[ 	]+vsseg2e32.v[ 	]+v4,\(a0\)
++[ 	]+[0-9a-f]+:[ 	]+22056227[ 	]+vsseg2e32.v[ 	]+v4,\(a0\)
++[ 	]+[0-9a-f]+:[ 	]+20056227[ 	]+vsseg2e32.v[ 	]+v4,\(a0\),v0.t
++[ 	]+[0-9a-f]+:[ 	]+42056207[ 	]+vlseg3e32.v[ 	]+v4,\(a0\)
++[ 	]+[0-9a-f]+:[ 	]+42056207[ 	]+vlseg3e32.v[ 	]+v4,\(a0\)
++[ 	]+[0-9a-f]+:[ 	]+40056207[ 	]+vlseg3e32.v[ 	]+v4,\(a0\),v0.t
++[ 	]+[0-9a-f]+:[ 	]+42056227[ 	]+vsseg3e32.v[ 	]+v4,\(a0\)
++[ 	]+[0-9a-f]+:[ 	]+42056227[ 	]+vsseg3e32.v[ 	]+v4,\(a0\)
++[ 	]+[0-9a-f]+:[ 	]+40056227[ 	]+vsseg3e32.v[ 	]+v4,\(a0\),v0.t
++[ 	]+[0-9a-f]+:[ 	]+62056207[ 	]+vlseg4e32.v[ 	]+v4,\(a0\)
++[ 	]+[0-9a-f]+:[ 	]+62056207[ 	]+vlseg4e32.v[ 	]+v4,\(a0\)
++[ 	]+[0-9a-f]+:[ 	]+60056207[ 	]+vlseg4e32.v[ 	]+v4,\(a0\),v0.t
++[ 	]+[0-9a-f]+:[ 	]+62056227[ 	]+vsseg4e32.v[ 	]+v4,\(a0\)
++[ 	]+[0-9a-f]+:[ 	]+62056227[ 	]+vsseg4e32.v[ 	]+v4,\(a0\)
++[ 	]+[0-9a-f]+:[ 	]+60056227[ 	]+vsseg4e32.v[ 	]+v4,\(a0\),v0.t
++[ 	]+[0-9a-f]+:[ 	]+82056207[ 	]+vlseg5e32.v[ 	]+v4,\(a0\)
++[ 	]+[0-9a-f]+:[ 	]+82056207[ 	]+vlseg5e32.v[ 	]+v4,\(a0\)
++[ 	]+[0-9a-f]+:[ 	]+80056207[ 	]+vlseg5e32.v[ 	]+v4,\(a0\),v0.t
++[ 	]+[0-9a-f]+:[ 	]+82056227[ 	]+vsseg5e32.v[ 	]+v4,\(a0\)
++[ 	]+[0-9a-f]+:[ 	]+82056227[ 	]+vsseg5e32.v[ 	]+v4,\(a0\)
++[ 	]+[0-9a-f]+:[ 	]+80056227[ 	]+vsseg5e32.v[ 	]+v4,\(a0\),v0.t
++[ 	]+[0-9a-f]+:[ 	]+a2056207[ 	]+vlseg6e32.v[ 	]+v4,\(a0\)
++[ 	]+[0-9a-f]+:[ 	]+a2056207[ 	]+vlseg6e32.v[ 	]+v4,\(a0\)
++[ 	]+[0-9a-f]+:[ 	]+a0056207[ 	]+vlseg6e32.v[ 	]+v4,\(a0\),v0.t
++[ 	]+[0-9a-f]+:[ 	]+a2056227[ 	]+vsseg6e32.v[ 	]+v4,\(a0\)
++[ 	]+[0-9a-f]+:[ 	]+a2056227[ 	]+vsseg6e32.v[ 	]+v4,\(a0\)
++[ 	]+[0-9a-f]+:[ 	]+a0056227[ 	]+vsseg6e32.v[ 	]+v4,\(a0\),v0.t
++[ 	]+[0-9a-f]+:[ 	]+c2056207[ 	]+vlseg7e32.v[ 	]+v4,\(a0\)
++[ 	]+[0-9a-f]+:[ 	]+c2056207[ 	]+vlseg7e32.v[ 	]+v4,\(a0\)
++[ 	]+[0-9a-f]+:[ 	]+c0056207[ 	]+vlseg7e32.v[ 	]+v4,\(a0\),v0.t
++[ 	]+[0-9a-f]+:[ 	]+c2056227[ 	]+vsseg7e32.v[ 	]+v4,\(a0\)
++[ 	]+[0-9a-f]+:[ 	]+c2056227[ 	]+vsseg7e32.v[ 	]+v4,\(a0\)
++[ 	]+[0-9a-f]+:[ 	]+c0056227[ 	]+vsseg7e32.v[ 	]+v4,\(a0\),v0.t
++[ 	]+[0-9a-f]+:[ 	]+e2056207[ 	]+vlseg8e32.v[ 	]+v4,\(a0\)
++[ 	]+[0-9a-f]+:[ 	]+e2056207[ 	]+vlseg8e32.v[ 	]+v4,\(a0\)
++[ 	]+[0-9a-f]+:[ 	]+e0056207[ 	]+vlseg8e32.v[ 	]+v4,\(a0\),v0.t
++[ 	]+[0-9a-f]+:[ 	]+e2056227[ 	]+vsseg8e32.v[ 	]+v4,\(a0\)
++[ 	]+[0-9a-f]+:[ 	]+e2056227[ 	]+vsseg8e32.v[ 	]+v4,\(a0\)
++[ 	]+[0-9a-f]+:[ 	]+e0056227[ 	]+vsseg8e32.v[ 	]+v4,\(a0\),v0.t
++[ 	]+[0-9a-f]+:[ 	]+22057207[ 	]+vlseg2e64.v[ 	]+v4,\(a0\)
++[ 	]+[0-9a-f]+:[ 	]+22057207[ 	]+vlseg2e64.v[ 	]+v4,\(a0\)
++[ 	]+[0-9a-f]+:[ 	]+20057207[ 	]+vlseg2e64.v[ 	]+v4,\(a0\),v0.t
++[ 	]+[0-9a-f]+:[ 	]+22057227[ 	]+vsseg2e64.v[ 	]+v4,\(a0\)
++[ 	]+[0-9a-f]+:[ 	]+22057227[ 	]+vsseg2e64.v[ 	]+v4,\(a0\)
++[ 	]+[0-9a-f]+:[ 	]+20057227[ 	]+vsseg2e64.v[ 	]+v4,\(a0\),v0.t
++[ 	]+[0-9a-f]+:[ 	]+42057207[ 	]+vlseg3e64.v[ 	]+v4,\(a0\)
++[ 	]+[0-9a-f]+:[ 	]+42057207[ 	]+vlseg3e64.v[ 	]+v4,\(a0\)
++[ 	]+[0-9a-f]+:[ 	]+40057207[ 	]+vlseg3e64.v[ 	]+v4,\(a0\),v0.t
++[ 	]+[0-9a-f]+:[ 	]+42057227[ 	]+vsseg3e64.v[ 	]+v4,\(a0\)
++[ 	]+[0-9a-f]+:[ 	]+42057227[ 	]+vsseg3e64.v[ 	]+v4,\(a0\)
++[ 	]+[0-9a-f]+:[ 	]+40057227[ 	]+vsseg3e64.v[ 	]+v4,\(a0\),v0.t
++[ 	]+[0-9a-f]+:[ 	]+62057207[ 	]+vlseg4e64.v[ 	]+v4,\(a0\)
++[ 	]+[0-9a-f]+:[ 	]+62057207[ 	]+vlseg4e64.v[ 	]+v4,\(a0\)
++[ 	]+[0-9a-f]+:[ 	]+60057207[ 	]+vlseg4e64.v[ 	]+v4,\(a0\),v0.t
++[ 	]+[0-9a-f]+:[ 	]+62057227[ 	]+vsseg4e64.v[ 	]+v4,\(a0\)
++[ 	]+[0-9a-f]+:[ 	]+62057227[ 	]+vsseg4e64.v[ 	]+v4,\(a0\)
++[ 	]+[0-9a-f]+:[ 	]+60057227[ 	]+vsseg4e64.v[ 	]+v4,\(a0\),v0.t
++[ 	]+[0-9a-f]+:[ 	]+82057207[ 	]+vlseg5e64.v[ 	]+v4,\(a0\)
++[ 	]+[0-9a-f]+:[ 	]+82057207[ 	]+vlseg5e64.v[ 	]+v4,\(a0\)
++[ 	]+[0-9a-f]+:[ 	]+80057207[ 	]+vlseg5e64.v[ 	]+v4,\(a0\),v0.t
++[ 	]+[0-9a-f]+:[ 	]+82057227[ 	]+vsseg5e64.v[ 	]+v4,\(a0\)
++[ 	]+[0-9a-f]+:[ 	]+82057227[ 	]+vsseg5e64.v[ 	]+v4,\(a0\)
++[ 	]+[0-9a-f]+:[ 	]+80057227[ 	]+vsseg5e64.v[ 	]+v4,\(a0\),v0.t
++[ 	]+[0-9a-f]+:[ 	]+a2057207[ 	]+vlseg6e64.v[ 	]+v4,\(a0\)
++[ 	]+[0-9a-f]+:[ 	]+a2057207[ 	]+vlseg6e64.v[ 	]+v4,\(a0\)
++[ 	]+[0-9a-f]+:[ 	]+a0057207[ 	]+vlseg6e64.v[ 	]+v4,\(a0\),v0.t
++[ 	]+[0-9a-f]+:[ 	]+a2057227[ 	]+vsseg6e64.v[ 	]+v4,\(a0\)
++[ 	]+[0-9a-f]+:[ 	]+a2057227[ 	]+vsseg6e64.v[ 	]+v4,\(a0\)
++[ 	]+[0-9a-f]+:[ 	]+a0057227[ 	]+vsseg6e64.v[ 	]+v4,\(a0\),v0.t
++[ 	]+[0-9a-f]+:[ 	]+c2057207[ 	]+vlseg7e64.v[ 	]+v4,\(a0\)
++[ 	]+[0-9a-f]+:[ 	]+c2057207[ 	]+vlseg7e64.v[ 	]+v4,\(a0\)
++[ 	]+[0-9a-f]+:[ 	]+c0057207[ 	]+vlseg7e64.v[ 	]+v4,\(a0\),v0.t
++[ 	]+[0-9a-f]+:[ 	]+c2057227[ 	]+vsseg7e64.v[ 	]+v4,\(a0\)
++[ 	]+[0-9a-f]+:[ 	]+c2057227[ 	]+vsseg7e64.v[ 	]+v4,\(a0\)
++[ 	]+[0-9a-f]+:[ 	]+c0057227[ 	]+vsseg7e64.v[ 	]+v4,\(a0\),v0.t
++[ 	]+[0-9a-f]+:[ 	]+e2057207[ 	]+vlseg8e64.v[ 	]+v4,\(a0\)
++[ 	]+[0-9a-f]+:[ 	]+e2057207[ 	]+vlseg8e64.v[ 	]+v4,\(a0\)
++[ 	]+[0-9a-f]+:[ 	]+e0057207[ 	]+vlseg8e64.v[ 	]+v4,\(a0\),v0.t
++[ 	]+[0-9a-f]+:[ 	]+e2057227[ 	]+vsseg8e64.v[ 	]+v4,\(a0\)
++[ 	]+[0-9a-f]+:[ 	]+e2057227[ 	]+vsseg8e64.v[ 	]+v4,\(a0\)
++[ 	]+[0-9a-f]+:[ 	]+e0057227[ 	]+vsseg8e64.v[ 	]+v4,\(a0\),v0.t
++[ 	]+[0-9a-f]+:[ 	]+32050207[ 	]+vlseg2e128.v[ 	]+v4,\(a0\)
++[ 	]+[0-9a-f]+:[ 	]+32050207[ 	]+vlseg2e128.v[ 	]+v4,\(a0\)
++[ 	]+[0-9a-f]+:[ 	]+30050207[ 	]+vlseg2e128.v[ 	]+v4,\(a0\),v0.t
++[ 	]+[0-9a-f]+:[ 	]+32050227[ 	]+vsseg2e128.v[ 	]+v4,\(a0\)
++[ 	]+[0-9a-f]+:[ 	]+32050227[ 	]+vsseg2e128.v[ 	]+v4,\(a0\)
++[ 	]+[0-9a-f]+:[ 	]+30050227[ 	]+vsseg2e128.v[ 	]+v4,\(a0\),v0.t
++[ 	]+[0-9a-f]+:[ 	]+52050207[ 	]+vlseg3e128.v[ 	]+v4,\(a0\)
++[ 	]+[0-9a-f]+:[ 	]+52050207[ 	]+vlseg3e128.v[ 	]+v4,\(a0\)
++[ 	]+[0-9a-f]+:[ 	]+50050207[ 	]+vlseg3e128.v[ 	]+v4,\(a0\),v0.t
++[ 	]+[0-9a-f]+:[ 	]+52050227[ 	]+vsseg3e128.v[ 	]+v4,\(a0\)
++[ 	]+[0-9a-f]+:[ 	]+52050227[ 	]+vsseg3e128.v[ 	]+v4,\(a0\)
++[ 	]+[0-9a-f]+:[ 	]+50050227[ 	]+vsseg3e128.v[ 	]+v4,\(a0\),v0.t
++[ 	]+[0-9a-f]+:[ 	]+72050207[ 	]+vlseg4e128.v[ 	]+v4,\(a0\)
++[ 	]+[0-9a-f]+:[ 	]+72050207[ 	]+vlseg4e128.v[ 	]+v4,\(a0\)
++[ 	]+[0-9a-f]+:[ 	]+70050207[ 	]+vlseg4e128.v[ 	]+v4,\(a0\),v0.t
++[ 	]+[0-9a-f]+:[ 	]+72050227[ 	]+vsseg4e128.v[ 	]+v4,\(a0\)
++[ 	]+[0-9a-f]+:[ 	]+72050227[ 	]+vsseg4e128.v[ 	]+v4,\(a0\)
++[ 	]+[0-9a-f]+:[ 	]+70050227[ 	]+vsseg4e128.v[ 	]+v4,\(a0\),v0.t
++[ 	]+[0-9a-f]+:[ 	]+92050207[ 	]+vlseg5e128.v[ 	]+v4,\(a0\)
++[ 	]+[0-9a-f]+:[ 	]+92050207[ 	]+vlseg5e128.v[ 	]+v4,\(a0\)
++[ 	]+[0-9a-f]+:[ 	]+90050207[ 	]+vlseg5e128.v[ 	]+v4,\(a0\),v0.t
++[ 	]+[0-9a-f]+:[ 	]+92050227[ 	]+vsseg5e128.v[ 	]+v4,\(a0\)
++[ 	]+[0-9a-f]+:[ 	]+92050227[ 	]+vsseg5e128.v[ 	]+v4,\(a0\)
++[ 	]+[0-9a-f]+:[ 	]+90050227[ 	]+vsseg5e128.v[ 	]+v4,\(a0\),v0.t
++[ 	]+[0-9a-f]+:[ 	]+b2050207[ 	]+vlseg6e128.v[ 	]+v4,\(a0\)
++[ 	]+[0-9a-f]+:[ 	]+b2050207[ 	]+vlseg6e128.v[ 	]+v4,\(a0\)
++[ 	]+[0-9a-f]+:[ 	]+b0050207[ 	]+vlseg6e128.v[ 	]+v4,\(a0\),v0.t
++[ 	]+[0-9a-f]+:[ 	]+b2050227[ 	]+vsseg6e128.v[ 	]+v4,\(a0\)
++[ 	]+[0-9a-f]+:[ 	]+b2050227[ 	]+vsseg6e128.v[ 	]+v4,\(a0\)
++[ 	]+[0-9a-f]+:[ 	]+b0050227[ 	]+vsseg6e128.v[ 	]+v4,\(a0\),v0.t
++[ 	]+[0-9a-f]+:[ 	]+d2050207[ 	]+vlseg7e128.v[ 	]+v4,\(a0\)
++[ 	]+[0-9a-f]+:[ 	]+d2050207[ 	]+vlseg7e128.v[ 	]+v4,\(a0\)
++[ 	]+[0-9a-f]+:[ 	]+d0050207[ 	]+vlseg7e128.v[ 	]+v4,\(a0\),v0.t
++[ 	]+[0-9a-f]+:[ 	]+d2050227[ 	]+vsseg7e128.v[ 	]+v4,\(a0\)
++[ 	]+[0-9a-f]+:[ 	]+d2050227[ 	]+vsseg7e128.v[ 	]+v4,\(a0\)
++[ 	]+[0-9a-f]+:[ 	]+d0050227[ 	]+vsseg7e128.v[ 	]+v4,\(a0\),v0.t
++[ 	]+[0-9a-f]+:[ 	]+f2050207[ 	]+vlseg8e128.v[ 	]+v4,\(a0\)
++[ 	]+[0-9a-f]+:[ 	]+f2050207[ 	]+vlseg8e128.v[ 	]+v4,\(a0\)
++[ 	]+[0-9a-f]+:[ 	]+f0050207[ 	]+vlseg8e128.v[ 	]+v4,\(a0\),v0.t
++[ 	]+[0-9a-f]+:[ 	]+f2050227[ 	]+vsseg8e128.v[ 	]+v4,\(a0\)
++[ 	]+[0-9a-f]+:[ 	]+f2050227[ 	]+vsseg8e128.v[ 	]+v4,\(a0\)
++[ 	]+[0-9a-f]+:[ 	]+f0050227[ 	]+vsseg8e128.v[ 	]+v4,\(a0\),v0.t
++[ 	]+[0-9a-f]+:[ 	]+32055207[ 	]+vlseg2e256.v[ 	]+v4,\(a0\)
++[ 	]+[0-9a-f]+:[ 	]+32055207[ 	]+vlseg2e256.v[ 	]+v4,\(a0\)
++[ 	]+[0-9a-f]+:[ 	]+30055207[ 	]+vlseg2e256.v[ 	]+v4,\(a0\),v0.t
++[ 	]+[0-9a-f]+:[ 	]+32055227[ 	]+vsseg2e256.v[ 	]+v4,\(a0\)
++[ 	]+[0-9a-f]+:[ 	]+32055227[ 	]+vsseg2e256.v[ 	]+v4,\(a0\)
++[ 	]+[0-9a-f]+:[ 	]+30055227[ 	]+vsseg2e256.v[ 	]+v4,\(a0\),v0.t
++[ 	]+[0-9a-f]+:[ 	]+52055207[ 	]+vlseg3e256.v[ 	]+v4,\(a0\)
++[ 	]+[0-9a-f]+:[ 	]+52055207[ 	]+vlseg3e256.v[ 	]+v4,\(a0\)
++[ 	]+[0-9a-f]+:[ 	]+50055207[ 	]+vlseg3e256.v[ 	]+v4,\(a0\),v0.t
++[ 	]+[0-9a-f]+:[ 	]+52055227[ 	]+vsseg3e256.v[ 	]+v4,\(a0\)
++[ 	]+[0-9a-f]+:[ 	]+52055227[ 	]+vsseg3e256.v[ 	]+v4,\(a0\)
++[ 	]+[0-9a-f]+:[ 	]+50055227[ 	]+vsseg3e256.v[ 	]+v4,\(a0\),v0.t
++[ 	]+[0-9a-f]+:[ 	]+72055207[ 	]+vlseg4e256.v[ 	]+v4,\(a0\)
++[ 	]+[0-9a-f]+:[ 	]+72055207[ 	]+vlseg4e256.v[ 	]+v4,\(a0\)
++[ 	]+[0-9a-f]+:[ 	]+70055207[ 	]+vlseg4e256.v[ 	]+v4,\(a0\),v0.t
++[ 	]+[0-9a-f]+:[ 	]+72055227[ 	]+vsseg4e256.v[ 	]+v4,\(a0\)
++[ 	]+[0-9a-f]+:[ 	]+72055227[ 	]+vsseg4e256.v[ 	]+v4,\(a0\)
++[ 	]+[0-9a-f]+:[ 	]+70055227[ 	]+vsseg4e256.v[ 	]+v4,\(a0\),v0.t
++[ 	]+[0-9a-f]+:[ 	]+92055207[ 	]+vlseg5e256.v[ 	]+v4,\(a0\)
++[ 	]+[0-9a-f]+:[ 	]+92055207[ 	]+vlseg5e256.v[ 	]+v4,\(a0\)
++[ 	]+[0-9a-f]+:[ 	]+90055207[ 	]+vlseg5e256.v[ 	]+v4,\(a0\),v0.t
++[ 	]+[0-9a-f]+:[ 	]+92055227[ 	]+vsseg5e256.v[ 	]+v4,\(a0\)
++[ 	]+[0-9a-f]+:[ 	]+92055227[ 	]+vsseg5e256.v[ 	]+v4,\(a0\)
++[ 	]+[0-9a-f]+:[ 	]+90055227[ 	]+vsseg5e256.v[ 	]+v4,\(a0\),v0.t
++[ 	]+[0-9a-f]+:[ 	]+b2055207[ 	]+vlseg6e256.v[ 	]+v4,\(a0\)
++[ 	]+[0-9a-f]+:[ 	]+b2055207[ 	]+vlseg6e256.v[ 	]+v4,\(a0\)
++[ 	]+[0-9a-f]+:[ 	]+b0055207[ 	]+vlseg6e256.v[ 	]+v4,\(a0\),v0.t
++[ 	]+[0-9a-f]+:[ 	]+b2055227[ 	]+vsseg6e256.v[ 	]+v4,\(a0\)
++[ 	]+[0-9a-f]+:[ 	]+b2055227[ 	]+vsseg6e256.v[ 	]+v4,\(a0\)
++[ 	]+[0-9a-f]+:[ 	]+b0055227[ 	]+vsseg6e256.v[ 	]+v4,\(a0\),v0.t
++[ 	]+[0-9a-f]+:[ 	]+d2055207[ 	]+vlseg7e256.v[ 	]+v4,\(a0\)
++[ 	]+[0-9a-f]+:[ 	]+d2055207[ 	]+vlseg7e256.v[ 	]+v4,\(a0\)
++[ 	]+[0-9a-f]+:[ 	]+d0055207[ 	]+vlseg7e256.v[ 	]+v4,\(a0\),v0.t
++[ 	]+[0-9a-f]+:[ 	]+d2055227[ 	]+vsseg7e256.v[ 	]+v4,\(a0\)
++[ 	]+[0-9a-f]+:[ 	]+d2055227[ 	]+vsseg7e256.v[ 	]+v4,\(a0\)
++[ 	]+[0-9a-f]+:[ 	]+d0055227[ 	]+vsseg7e256.v[ 	]+v4,\(a0\),v0.t
++[ 	]+[0-9a-f]+:[ 	]+f2055207[ 	]+vlseg8e256.v[ 	]+v4,\(a0\)
++[ 	]+[0-9a-f]+:[ 	]+f2055207[ 	]+vlseg8e256.v[ 	]+v4,\(a0\)
++[ 	]+[0-9a-f]+:[ 	]+f0055207[ 	]+vlseg8e256.v[ 	]+v4,\(a0\),v0.t
++[ 	]+[0-9a-f]+:[ 	]+f2055227[ 	]+vsseg8e256.v[ 	]+v4,\(a0\)
++[ 	]+[0-9a-f]+:[ 	]+f2055227[ 	]+vsseg8e256.v[ 	]+v4,\(a0\)
++[ 	]+[0-9a-f]+:[ 	]+f0055227[ 	]+vsseg8e256.v[ 	]+v4,\(a0\),v0.t
++[ 	]+[0-9a-f]+:[ 	]+32056207[ 	]+vlseg2e512.v[ 	]+v4,\(a0\)
++[ 	]+[0-9a-f]+:[ 	]+32056207[ 	]+vlseg2e512.v[ 	]+v4,\(a0\)
++[ 	]+[0-9a-f]+:[ 	]+30056207[ 	]+vlseg2e512.v[ 	]+v4,\(a0\),v0.t
++[ 	]+[0-9a-f]+:[ 	]+32056227[ 	]+vsseg2e512.v[ 	]+v4,\(a0\)
++[ 	]+[0-9a-f]+:[ 	]+32056227[ 	]+vsseg2e512.v[ 	]+v4,\(a0\)
++[ 	]+[0-9a-f]+:[ 	]+30056227[ 	]+vsseg2e512.v[ 	]+v4,\(a0\),v0.t
++[ 	]+[0-9a-f]+:[ 	]+52056207[ 	]+vlseg3e512.v[ 	]+v4,\(a0\)
++[ 	]+[0-9a-f]+:[ 	]+52056207[ 	]+vlseg3e512.v[ 	]+v4,\(a0\)
++[ 	]+[0-9a-f]+:[ 	]+50056207[ 	]+vlseg3e512.v[ 	]+v4,\(a0\),v0.t
++[ 	]+[0-9a-f]+:[ 	]+52056227[ 	]+vsseg3e512.v[ 	]+v4,\(a0\)
++[ 	]+[0-9a-f]+:[ 	]+52056227[ 	]+vsseg3e512.v[ 	]+v4,\(a0\)
++[ 	]+[0-9a-f]+:[ 	]+50056227[ 	]+vsseg3e512.v[ 	]+v4,\(a0\),v0.t
++[ 	]+[0-9a-f]+:[ 	]+72056207[ 	]+vlseg4e512.v[ 	]+v4,\(a0\)
++[ 	]+[0-9a-f]+:[ 	]+72056207[ 	]+vlseg4e512.v[ 	]+v4,\(a0\)
++[ 	]+[0-9a-f]+:[ 	]+70056207[ 	]+vlseg4e512.v[ 	]+v4,\(a0\),v0.t
++[ 	]+[0-9a-f]+:[ 	]+72056227[ 	]+vsseg4e512.v[ 	]+v4,\(a0\)
++[ 	]+[0-9a-f]+:[ 	]+72056227[ 	]+vsseg4e512.v[ 	]+v4,\(a0\)
++[ 	]+[0-9a-f]+:[ 	]+70056227[ 	]+vsseg4e512.v[ 	]+v4,\(a0\),v0.t
++[ 	]+[0-9a-f]+:[ 	]+92056207[ 	]+vlseg5e512.v[ 	]+v4,\(a0\)
++[ 	]+[0-9a-f]+:[ 	]+92056207[ 	]+vlseg5e512.v[ 	]+v4,\(a0\)
++[ 	]+[0-9a-f]+:[ 	]+90056207[ 	]+vlseg5e512.v[ 	]+v4,\(a0\),v0.t
++[ 	]+[0-9a-f]+:[ 	]+92056227[ 	]+vsseg5e512.v[ 	]+v4,\(a0\)
++[ 	]+[0-9a-f]+:[ 	]+92056227[ 	]+vsseg5e512.v[ 	]+v4,\(a0\)
++[ 	]+[0-9a-f]+:[ 	]+90056227[ 	]+vsseg5e512.v[ 	]+v4,\(a0\),v0.t
++[ 	]+[0-9a-f]+:[ 	]+b2056207[ 	]+vlseg6e512.v[ 	]+v4,\(a0\)
++[ 	]+[0-9a-f]+:[ 	]+b2056207[ 	]+vlseg6e512.v[ 	]+v4,\(a0\)
++[ 	]+[0-9a-f]+:[ 	]+b0056207[ 	]+vlseg6e512.v[ 	]+v4,\(a0\),v0.t
++[ 	]+[0-9a-f]+:[ 	]+b2056227[ 	]+vsseg6e512.v[ 	]+v4,\(a0\)
++[ 	]+[0-9a-f]+:[ 	]+b2056227[ 	]+vsseg6e512.v[ 	]+v4,\(a0\)
++[ 	]+[0-9a-f]+:[ 	]+b0056227[ 	]+vsseg6e512.v[ 	]+v4,\(a0\),v0.t
++[ 	]+[0-9a-f]+:[ 	]+d2056207[ 	]+vlseg7e512.v[ 	]+v4,\(a0\)
++[ 	]+[0-9a-f]+:[ 	]+d2056207[ 	]+vlseg7e512.v[ 	]+v4,\(a0\)
++[ 	]+[0-9a-f]+:[ 	]+d0056207[ 	]+vlseg7e512.v[ 	]+v4,\(a0\),v0.t
++[ 	]+[0-9a-f]+:[ 	]+d2056227[ 	]+vsseg7e512.v[ 	]+v4,\(a0\)
++[ 	]+[0-9a-f]+:[ 	]+d2056227[ 	]+vsseg7e512.v[ 	]+v4,\(a0\)
++[ 	]+[0-9a-f]+:[ 	]+d0056227[ 	]+vsseg7e512.v[ 	]+v4,\(a0\),v0.t
++[ 	]+[0-9a-f]+:[ 	]+f2056207[ 	]+vlseg8e512.v[ 	]+v4,\(a0\)
++[ 	]+[0-9a-f]+:[ 	]+f2056207[ 	]+vlseg8e512.v[ 	]+v4,\(a0\)
++[ 	]+[0-9a-f]+:[ 	]+f0056207[ 	]+vlseg8e512.v[ 	]+v4,\(a0\),v0.t
++[ 	]+[0-9a-f]+:[ 	]+f2056227[ 	]+vsseg8e512.v[ 	]+v4,\(a0\)
++[ 	]+[0-9a-f]+:[ 	]+f2056227[ 	]+vsseg8e512.v[ 	]+v4,\(a0\)
++[ 	]+[0-9a-f]+:[ 	]+f0056227[ 	]+vsseg8e512.v[ 	]+v4,\(a0\),v0.t
++[ 	]+[0-9a-f]+:[ 	]+32057207[ 	]+vlseg2e1024.v[ 	]+v4,\(a0\)
++[ 	]+[0-9a-f]+:[ 	]+32057207[ 	]+vlseg2e1024.v[ 	]+v4,\(a0\)
++[ 	]+[0-9a-f]+:[ 	]+30057207[ 	]+vlseg2e1024.v[ 	]+v4,\(a0\),v0.t
++[ 	]+[0-9a-f]+:[ 	]+32057227[ 	]+vsseg2e1024.v[ 	]+v4,\(a0\)
++[ 	]+[0-9a-f]+:[ 	]+32057227[ 	]+vsseg2e1024.v[ 	]+v4,\(a0\)
++[ 	]+[0-9a-f]+:[ 	]+30057227[ 	]+vsseg2e1024.v[ 	]+v4,\(a0\),v0.t
++[ 	]+[0-9a-f]+:[ 	]+52057207[ 	]+vlseg3e1024.v[ 	]+v4,\(a0\)
++[ 	]+[0-9a-f]+:[ 	]+52057207[ 	]+vlseg3e1024.v[ 	]+v4,\(a0\)
++[ 	]+[0-9a-f]+:[ 	]+50057207[ 	]+vlseg3e1024.v[ 	]+v4,\(a0\),v0.t
++[ 	]+[0-9a-f]+:[ 	]+52057227[ 	]+vsseg3e1024.v[ 	]+v4,\(a0\)
++[ 	]+[0-9a-f]+:[ 	]+52057227[ 	]+vsseg3e1024.v[ 	]+v4,\(a0\)
++[ 	]+[0-9a-f]+:[ 	]+50057227[ 	]+vsseg3e1024.v[ 	]+v4,\(a0\),v0.t
++[ 	]+[0-9a-f]+:[ 	]+72057207[ 	]+vlseg4e1024.v[ 	]+v4,\(a0\)
++[ 	]+[0-9a-f]+:[ 	]+72057207[ 	]+vlseg4e1024.v[ 	]+v4,\(a0\)
++[ 	]+[0-9a-f]+:[ 	]+70057207[ 	]+vlseg4e1024.v[ 	]+v4,\(a0\),v0.t
++[ 	]+[0-9a-f]+:[ 	]+72057227[ 	]+vsseg4e1024.v[ 	]+v4,\(a0\)
++[ 	]+[0-9a-f]+:[ 	]+72057227[ 	]+vsseg4e1024.v[ 	]+v4,\(a0\)
++[ 	]+[0-9a-f]+:[ 	]+70057227[ 	]+vsseg4e1024.v[ 	]+v4,\(a0\),v0.t
++[ 	]+[0-9a-f]+:[ 	]+92057207[ 	]+vlseg5e1024.v[ 	]+v4,\(a0\)
++[ 	]+[0-9a-f]+:[ 	]+92057207[ 	]+vlseg5e1024.v[ 	]+v4,\(a0\)
++[ 	]+[0-9a-f]+:[ 	]+90057207[ 	]+vlseg5e1024.v[ 	]+v4,\(a0\),v0.t
++[ 	]+[0-9a-f]+:[ 	]+92057227[ 	]+vsseg5e1024.v[ 	]+v4,\(a0\)
++[ 	]+[0-9a-f]+:[ 	]+92057227[ 	]+vsseg5e1024.v[ 	]+v4,\(a0\)
++[ 	]+[0-9a-f]+:[ 	]+90057227[ 	]+vsseg5e1024.v[ 	]+v4,\(a0\),v0.t
++[ 	]+[0-9a-f]+:[ 	]+b2057207[ 	]+vlseg6e1024.v[ 	]+v4,\(a0\)
++[ 	]+[0-9a-f]+:[ 	]+b2057207[ 	]+vlseg6e1024.v[ 	]+v4,\(a0\)
++[ 	]+[0-9a-f]+:[ 	]+b0057207[ 	]+vlseg6e1024.v[ 	]+v4,\(a0\),v0.t
++[ 	]+[0-9a-f]+:[ 	]+b2057227[ 	]+vsseg6e1024.v[ 	]+v4,\(a0\)
++[ 	]+[0-9a-f]+:[ 	]+b2057227[ 	]+vsseg6e1024.v[ 	]+v4,\(a0\)
++[ 	]+[0-9a-f]+:[ 	]+b0057227[ 	]+vsseg6e1024.v[ 	]+v4,\(a0\),v0.t
++[ 	]+[0-9a-f]+:[ 	]+d2057207[ 	]+vlseg7e1024.v[ 	]+v4,\(a0\)
++[ 	]+[0-9a-f]+:[ 	]+d2057207[ 	]+vlseg7e1024.v[ 	]+v4,\(a0\)
++[ 	]+[0-9a-f]+:[ 	]+d0057207[ 	]+vlseg7e1024.v[ 	]+v4,\(a0\),v0.t
++[ 	]+[0-9a-f]+:[ 	]+d2057227[ 	]+vsseg7e1024.v[ 	]+v4,\(a0\)
++[ 	]+[0-9a-f]+:[ 	]+d2057227[ 	]+vsseg7e1024.v[ 	]+v4,\(a0\)
++[ 	]+[0-9a-f]+:[ 	]+d0057227[ 	]+vsseg7e1024.v[ 	]+v4,\(a0\),v0.t
++[ 	]+[0-9a-f]+:[ 	]+f2057207[ 	]+vlseg8e1024.v[ 	]+v4,\(a0\)
++[ 	]+[0-9a-f]+:[ 	]+f2057207[ 	]+vlseg8e1024.v[ 	]+v4,\(a0\)
++[ 	]+[0-9a-f]+:[ 	]+f0057207[ 	]+vlseg8e1024.v[ 	]+v4,\(a0\),v0.t
++[ 	]+[0-9a-f]+:[ 	]+f2057227[ 	]+vsseg8e1024.v[ 	]+v4,\(a0\)
++[ 	]+[0-9a-f]+:[ 	]+f2057227[ 	]+vsseg8e1024.v[ 	]+v4,\(a0\)
++[ 	]+[0-9a-f]+:[ 	]+f0057227[ 	]+vsseg8e1024.v[ 	]+v4,\(a0\),v0.t
++[ 	]+[0-9a-f]+:[ 	]+2ab50207[ 	]+vlsseg2e8.v[ 	]+v4,\(a0\),a1
++[ 	]+[0-9a-f]+:[ 	]+2ab50207[ 	]+vlsseg2e8.v[ 	]+v4,\(a0\),a1
++[ 	]+[0-9a-f]+:[ 	]+28b50207[ 	]+vlsseg2e8.v[ 	]+v4,\(a0\),a1,v0.t
++[ 	]+[0-9a-f]+:[ 	]+2ab50227[ 	]+vssseg2e8.v[ 	]+v4,\(a0\),a1
++[ 	]+[0-9a-f]+:[ 	]+2ab50227[ 	]+vssseg2e8.v[ 	]+v4,\(a0\),a1
++[ 	]+[0-9a-f]+:[ 	]+28b50227[ 	]+vssseg2e8.v[ 	]+v4,\(a0\),a1,v0.t
++[ 	]+[0-9a-f]+:[ 	]+4ab50207[ 	]+vlsseg3e8.v[ 	]+v4,\(a0\),a1
++[ 	]+[0-9a-f]+:[ 	]+4ab50207[ 	]+vlsseg3e8.v[ 	]+v4,\(a0\),a1
++[ 	]+[0-9a-f]+:[ 	]+48b50207[ 	]+vlsseg3e8.v[ 	]+v4,\(a0\),a1,v0.t
++[ 	]+[0-9a-f]+:[ 	]+4ab50227[ 	]+vssseg3e8.v[ 	]+v4,\(a0\),a1
++[ 	]+[0-9a-f]+:[ 	]+4ab50227[ 	]+vssseg3e8.v[ 	]+v4,\(a0\),a1
++[ 	]+[0-9a-f]+:[ 	]+48b50227[ 	]+vssseg3e8.v[ 	]+v4,\(a0\),a1,v0.t
++[ 	]+[0-9a-f]+:[ 	]+6ab50207[ 	]+vlsseg4e8.v[ 	]+v4,\(a0\),a1
++[ 	]+[0-9a-f]+:[ 	]+6ab50207[ 	]+vlsseg4e8.v[ 	]+v4,\(a0\),a1
++[ 	]+[0-9a-f]+:[ 	]+68b50207[ 	]+vlsseg4e8.v[ 	]+v4,\(a0\),a1,v0.t
++[ 	]+[0-9a-f]+:[ 	]+6ab50227[ 	]+vssseg4e8.v[ 	]+v4,\(a0\),a1
++[ 	]+[0-9a-f]+:[ 	]+6ab50227[ 	]+vssseg4e8.v[ 	]+v4,\(a0\),a1
++[ 	]+[0-9a-f]+:[ 	]+68b50227[ 	]+vssseg4e8.v[ 	]+v4,\(a0\),a1,v0.t
++[ 	]+[0-9a-f]+:[ 	]+8ab50207[ 	]+vlsseg5e8.v[ 	]+v4,\(a0\),a1
++[ 	]+[0-9a-f]+:[ 	]+8ab50207[ 	]+vlsseg5e8.v[ 	]+v4,\(a0\),a1
++[ 	]+[0-9a-f]+:[ 	]+88b50207[ 	]+vlsseg5e8.v[ 	]+v4,\(a0\),a1,v0.t
++[ 	]+[0-9a-f]+:[ 	]+8ab50227[ 	]+vssseg5e8.v[ 	]+v4,\(a0\),a1
++[ 	]+[0-9a-f]+:[ 	]+8ab50227[ 	]+vssseg5e8.v[ 	]+v4,\(a0\),a1
++[ 	]+[0-9a-f]+:[ 	]+88b50227[ 	]+vssseg5e8.v[ 	]+v4,\(a0\),a1,v0.t
++[ 	]+[0-9a-f]+:[ 	]+aab50207[ 	]+vlsseg6e8.v[ 	]+v4,\(a0\),a1
++[ 	]+[0-9a-f]+:[ 	]+aab50207[ 	]+vlsseg6e8.v[ 	]+v4,\(a0\),a1
++[ 	]+[0-9a-f]+:[ 	]+a8b50207[ 	]+vlsseg6e8.v[ 	]+v4,\(a0\),a1,v0.t
++[ 	]+[0-9a-f]+:[ 	]+aab50227[ 	]+vssseg6e8.v[ 	]+v4,\(a0\),a1
++[ 	]+[0-9a-f]+:[ 	]+aab50227[ 	]+vssseg6e8.v[ 	]+v4,\(a0\),a1
++[ 	]+[0-9a-f]+:[ 	]+a8b50227[ 	]+vssseg6e8.v[ 	]+v4,\(a0\),a1,v0.t
++[ 	]+[0-9a-f]+:[ 	]+cab50207[ 	]+vlsseg7e8.v[ 	]+v4,\(a0\),a1
++[ 	]+[0-9a-f]+:[ 	]+cab50207[ 	]+vlsseg7e8.v[ 	]+v4,\(a0\),a1
++[ 	]+[0-9a-f]+:[ 	]+c8b50207[ 	]+vlsseg7e8.v[ 	]+v4,\(a0\),a1,v0.t
++[ 	]+[0-9a-f]+:[ 	]+cab50227[ 	]+vssseg7e8.v[ 	]+v4,\(a0\),a1
++[ 	]+[0-9a-f]+:[ 	]+cab50227[ 	]+vssseg7e8.v[ 	]+v4,\(a0\),a1
++[ 	]+[0-9a-f]+:[ 	]+c8b50227[ 	]+vssseg7e8.v[ 	]+v4,\(a0\),a1,v0.t
++[ 	]+[0-9a-f]+:[ 	]+eab50207[ 	]+vlsseg8e8.v[ 	]+v4,\(a0\),a1
++[ 	]+[0-9a-f]+:[ 	]+eab50207[ 	]+vlsseg8e8.v[ 	]+v4,\(a0\),a1
++[ 	]+[0-9a-f]+:[ 	]+e8b50207[ 	]+vlsseg8e8.v[ 	]+v4,\(a0\),a1,v0.t
++[ 	]+[0-9a-f]+:[ 	]+eab50227[ 	]+vssseg8e8.v[ 	]+v4,\(a0\),a1
++[ 	]+[0-9a-f]+:[ 	]+eab50227[ 	]+vssseg8e8.v[ 	]+v4,\(a0\),a1
++[ 	]+[0-9a-f]+:[ 	]+e8b50227[ 	]+vssseg8e8.v[ 	]+v4,\(a0\),a1,v0.t
++[ 	]+[0-9a-f]+:[ 	]+2ab55207[ 	]+vlsseg2e16.v[ 	]+v4,\(a0\),a1
++[ 	]+[0-9a-f]+:[ 	]+2ab55207[ 	]+vlsseg2e16.v[ 	]+v4,\(a0\),a1
++[ 	]+[0-9a-f]+:[ 	]+28b55207[ 	]+vlsseg2e16.v[ 	]+v4,\(a0\),a1,v0.t
++[ 	]+[0-9a-f]+:[ 	]+2ab55227[ 	]+vssseg2e16.v[ 	]+v4,\(a0\),a1
++[ 	]+[0-9a-f]+:[ 	]+2ab55227[ 	]+vssseg2e16.v[ 	]+v4,\(a0\),a1
++[ 	]+[0-9a-f]+:[ 	]+28b55227[ 	]+vssseg2e16.v[ 	]+v4,\(a0\),a1,v0.t
++[ 	]+[0-9a-f]+:[ 	]+4ab55207[ 	]+vlsseg3e16.v[ 	]+v4,\(a0\),a1
++[ 	]+[0-9a-f]+:[ 	]+4ab55207[ 	]+vlsseg3e16.v[ 	]+v4,\(a0\),a1
++[ 	]+[0-9a-f]+:[ 	]+48b55207[ 	]+vlsseg3e16.v[ 	]+v4,\(a0\),a1,v0.t
++[ 	]+[0-9a-f]+:[ 	]+4ab55227[ 	]+vssseg3e16.v[ 	]+v4,\(a0\),a1
++[ 	]+[0-9a-f]+:[ 	]+4ab55227[ 	]+vssseg3e16.v[ 	]+v4,\(a0\),a1
++[ 	]+[0-9a-f]+:[ 	]+48b55227[ 	]+vssseg3e16.v[ 	]+v4,\(a0\),a1,v0.t
++[ 	]+[0-9a-f]+:[ 	]+6ab55207[ 	]+vlsseg4e16.v[ 	]+v4,\(a0\),a1
++[ 	]+[0-9a-f]+:[ 	]+6ab55207[ 	]+vlsseg4e16.v[ 	]+v4,\(a0\),a1
++[ 	]+[0-9a-f]+:[ 	]+68b55207[ 	]+vlsseg4e16.v[ 	]+v4,\(a0\),a1,v0.t
++[ 	]+[0-9a-f]+:[ 	]+6ab55227[ 	]+vssseg4e16.v[ 	]+v4,\(a0\),a1
++[ 	]+[0-9a-f]+:[ 	]+6ab55227[ 	]+vssseg4e16.v[ 	]+v4,\(a0\),a1
++[ 	]+[0-9a-f]+:[ 	]+68b55227[ 	]+vssseg4e16.v[ 	]+v4,\(a0\),a1,v0.t
++[ 	]+[0-9a-f]+:[ 	]+8ab55207[ 	]+vlsseg5e16.v[ 	]+v4,\(a0\),a1
++[ 	]+[0-9a-f]+:[ 	]+8ab55207[ 	]+vlsseg5e16.v[ 	]+v4,\(a0\),a1
++[ 	]+[0-9a-f]+:[ 	]+88b55207[ 	]+vlsseg5e16.v[ 	]+v4,\(a0\),a1,v0.t
++[ 	]+[0-9a-f]+:[ 	]+8ab55227[ 	]+vssseg5e16.v[ 	]+v4,\(a0\),a1
++[ 	]+[0-9a-f]+:[ 	]+8ab55227[ 	]+vssseg5e16.v[ 	]+v4,\(a0\),a1
++[ 	]+[0-9a-f]+:[ 	]+88b55227[ 	]+vssseg5e16.v[ 	]+v4,\(a0\),a1,v0.t
++[ 	]+[0-9a-f]+:[ 	]+aab55207[ 	]+vlsseg6e16.v[ 	]+v4,\(a0\),a1
++[ 	]+[0-9a-f]+:[ 	]+aab55207[ 	]+vlsseg6e16.v[ 	]+v4,\(a0\),a1
++[ 	]+[0-9a-f]+:[ 	]+a8b55207[ 	]+vlsseg6e16.v[ 	]+v4,\(a0\),a1,v0.t
++[ 	]+[0-9a-f]+:[ 	]+aab55227[ 	]+vssseg6e16.v[ 	]+v4,\(a0\),a1
++[ 	]+[0-9a-f]+:[ 	]+aab55227[ 	]+vssseg6e16.v[ 	]+v4,\(a0\),a1
++[ 	]+[0-9a-f]+:[ 	]+a8b55227[ 	]+vssseg6e16.v[ 	]+v4,\(a0\),a1,v0.t
++[ 	]+[0-9a-f]+:[ 	]+cab55207[ 	]+vlsseg7e16.v[ 	]+v4,\(a0\),a1
++[ 	]+[0-9a-f]+:[ 	]+cab55207[ 	]+vlsseg7e16.v[ 	]+v4,\(a0\),a1
++[ 	]+[0-9a-f]+:[ 	]+c8b55207[ 	]+vlsseg7e16.v[ 	]+v4,\(a0\),a1,v0.t
++[ 	]+[0-9a-f]+:[ 	]+cab55227[ 	]+vssseg7e16.v[ 	]+v4,\(a0\),a1
++[ 	]+[0-9a-f]+:[ 	]+cab55227[ 	]+vssseg7e16.v[ 	]+v4,\(a0\),a1
++[ 	]+[0-9a-f]+:[ 	]+c8b55227[ 	]+vssseg7e16.v[ 	]+v4,\(a0\),a1,v0.t
++[ 	]+[0-9a-f]+:[ 	]+eab55207[ 	]+vlsseg8e16.v[ 	]+v4,\(a0\),a1
++[ 	]+[0-9a-f]+:[ 	]+eab55207[ 	]+vlsseg8e16.v[ 	]+v4,\(a0\),a1
++[ 	]+[0-9a-f]+:[ 	]+e8b55207[ 	]+vlsseg8e16.v[ 	]+v4,\(a0\),a1,v0.t
++[ 	]+[0-9a-f]+:[ 	]+eab55227[ 	]+vssseg8e16.v[ 	]+v4,\(a0\),a1
++[ 	]+[0-9a-f]+:[ 	]+eab55227[ 	]+vssseg8e16.v[ 	]+v4,\(a0\),a1
++[ 	]+[0-9a-f]+:[ 	]+e8b55227[ 	]+vssseg8e16.v[ 	]+v4,\(a0\),a1,v0.t
++[ 	]+[0-9a-f]+:[ 	]+2ab56207[ 	]+vlsseg2e32.v[ 	]+v4,\(a0\),a1
++[ 	]+[0-9a-f]+:[ 	]+2ab56207[ 	]+vlsseg2e32.v[ 	]+v4,\(a0\),a1
++[ 	]+[0-9a-f]+:[ 	]+28b56207[ 	]+vlsseg2e32.v[ 	]+v4,\(a0\),a1,v0.t
++[ 	]+[0-9a-f]+:[ 	]+2ab56227[ 	]+vssseg2e32.v[ 	]+v4,\(a0\),a1
++[ 	]+[0-9a-f]+:[ 	]+2ab56227[ 	]+vssseg2e32.v[ 	]+v4,\(a0\),a1
++[ 	]+[0-9a-f]+:[ 	]+28b56227[ 	]+vssseg2e32.v[ 	]+v4,\(a0\),a1,v0.t
++[ 	]+[0-9a-f]+:[ 	]+4ab56207[ 	]+vlsseg3e32.v[ 	]+v4,\(a0\),a1
++[ 	]+[0-9a-f]+:[ 	]+4ab56207[ 	]+vlsseg3e32.v[ 	]+v4,\(a0\),a1
++[ 	]+[0-9a-f]+:[ 	]+48b56207[ 	]+vlsseg3e32.v[ 	]+v4,\(a0\),a1,v0.t
++[ 	]+[0-9a-f]+:[ 	]+4ab56227[ 	]+vssseg3e32.v[ 	]+v4,\(a0\),a1
++[ 	]+[0-9a-f]+:[ 	]+4ab56227[ 	]+vssseg3e32.v[ 	]+v4,\(a0\),a1
++[ 	]+[0-9a-f]+:[ 	]+48b56227[ 	]+vssseg3e32.v[ 	]+v4,\(a0\),a1,v0.t
++[ 	]+[0-9a-f]+:[ 	]+6ab56207[ 	]+vlsseg4e32.v[ 	]+v4,\(a0\),a1
++[ 	]+[0-9a-f]+:[ 	]+6ab56207[ 	]+vlsseg4e32.v[ 	]+v4,\(a0\),a1
++[ 	]+[0-9a-f]+:[ 	]+68b56207[ 	]+vlsseg4e32.v[ 	]+v4,\(a0\),a1,v0.t
++[ 	]+[0-9a-f]+:[ 	]+6ab56227[ 	]+vssseg4e32.v[ 	]+v4,\(a0\),a1
++[ 	]+[0-9a-f]+:[ 	]+6ab56227[ 	]+vssseg4e32.v[ 	]+v4,\(a0\),a1
++[ 	]+[0-9a-f]+:[ 	]+68b56227[ 	]+vssseg4e32.v[ 	]+v4,\(a0\),a1,v0.t
++[ 	]+[0-9a-f]+:[ 	]+8ab56207[ 	]+vlsseg5e32.v[ 	]+v4,\(a0\),a1
++[ 	]+[0-9a-f]+:[ 	]+8ab56207[ 	]+vlsseg5e32.v[ 	]+v4,\(a0\),a1
++[ 	]+[0-9a-f]+:[ 	]+88b56207[ 	]+vlsseg5e32.v[ 	]+v4,\(a0\),a1,v0.t
++[ 	]+[0-9a-f]+:[ 	]+8ab56227[ 	]+vssseg5e32.v[ 	]+v4,\(a0\),a1
++[ 	]+[0-9a-f]+:[ 	]+8ab56227[ 	]+vssseg5e32.v[ 	]+v4,\(a0\),a1
++[ 	]+[0-9a-f]+:[ 	]+88b56227[ 	]+vssseg5e32.v[ 	]+v4,\(a0\),a1,v0.t
++[ 	]+[0-9a-f]+:[ 	]+aab56207[ 	]+vlsseg6e32.v[ 	]+v4,\(a0\),a1
++[ 	]+[0-9a-f]+:[ 	]+aab56207[ 	]+vlsseg6e32.v[ 	]+v4,\(a0\),a1
++[ 	]+[0-9a-f]+:[ 	]+a8b56207[ 	]+vlsseg6e32.v[ 	]+v4,\(a0\),a1,v0.t
++[ 	]+[0-9a-f]+:[ 	]+aab56227[ 	]+vssseg6e32.v[ 	]+v4,\(a0\),a1
++[ 	]+[0-9a-f]+:[ 	]+aab56227[ 	]+vssseg6e32.v[ 	]+v4,\(a0\),a1
++[ 	]+[0-9a-f]+:[ 	]+a8b56227[ 	]+vssseg6e32.v[ 	]+v4,\(a0\),a1,v0.t
++[ 	]+[0-9a-f]+:[ 	]+cab56207[ 	]+vlsseg7e32.v[ 	]+v4,\(a0\),a1
++[ 	]+[0-9a-f]+:[ 	]+cab56207[ 	]+vlsseg7e32.v[ 	]+v4,\(a0\),a1
++[ 	]+[0-9a-f]+:[ 	]+c8b56207[ 	]+vlsseg7e32.v[ 	]+v4,\(a0\),a1,v0.t
++[ 	]+[0-9a-f]+:[ 	]+cab56227[ 	]+vssseg7e32.v[ 	]+v4,\(a0\),a1
++[ 	]+[0-9a-f]+:[ 	]+cab56227[ 	]+vssseg7e32.v[ 	]+v4,\(a0\),a1
++[ 	]+[0-9a-f]+:[ 	]+c8b56227[ 	]+vssseg7e32.v[ 	]+v4,\(a0\),a1,v0.t
++[ 	]+[0-9a-f]+:[ 	]+eab56207[ 	]+vlsseg8e32.v[ 	]+v4,\(a0\),a1
++[ 	]+[0-9a-f]+:[ 	]+eab56207[ 	]+vlsseg8e32.v[ 	]+v4,\(a0\),a1
++[ 	]+[0-9a-f]+:[ 	]+e8b56207[ 	]+vlsseg8e32.v[ 	]+v4,\(a0\),a1,v0.t
++[ 	]+[0-9a-f]+:[ 	]+eab56227[ 	]+vssseg8e32.v[ 	]+v4,\(a0\),a1
++[ 	]+[0-9a-f]+:[ 	]+eab56227[ 	]+vssseg8e32.v[ 	]+v4,\(a0\),a1
++[ 	]+[0-9a-f]+:[ 	]+e8b56227[ 	]+vssseg8e32.v[ 	]+v4,\(a0\),a1,v0.t
++[ 	]+[0-9a-f]+:[ 	]+2ab57207[ 	]+vlsseg2e64.v[ 	]+v4,\(a0\),a1
++[ 	]+[0-9a-f]+:[ 	]+2ab57207[ 	]+vlsseg2e64.v[ 	]+v4,\(a0\),a1
++[ 	]+[0-9a-f]+:[ 	]+28b57207[ 	]+vlsseg2e64.v[ 	]+v4,\(a0\),a1,v0.t
++[ 	]+[0-9a-f]+:[ 	]+2ab57227[ 	]+vssseg2e64.v[ 	]+v4,\(a0\),a1
++[ 	]+[0-9a-f]+:[ 	]+2ab57227[ 	]+vssseg2e64.v[ 	]+v4,\(a0\),a1
++[ 	]+[0-9a-f]+:[ 	]+28b57227[ 	]+vssseg2e64.v[ 	]+v4,\(a0\),a1,v0.t
++[ 	]+[0-9a-f]+:[ 	]+4ab57207[ 	]+vlsseg3e64.v[ 	]+v4,\(a0\),a1
++[ 	]+[0-9a-f]+:[ 	]+4ab57207[ 	]+vlsseg3e64.v[ 	]+v4,\(a0\),a1
++[ 	]+[0-9a-f]+:[ 	]+48b57207[ 	]+vlsseg3e64.v[ 	]+v4,\(a0\),a1,v0.t
++[ 	]+[0-9a-f]+:[ 	]+4ab57227[ 	]+vssseg3e64.v[ 	]+v4,\(a0\),a1
++[ 	]+[0-9a-f]+:[ 	]+4ab57227[ 	]+vssseg3e64.v[ 	]+v4,\(a0\),a1
++[ 	]+[0-9a-f]+:[ 	]+48b57227[ 	]+vssseg3e64.v[ 	]+v4,\(a0\),a1,v0.t
++[ 	]+[0-9a-f]+:[ 	]+6ab57207[ 	]+vlsseg4e64.v[ 	]+v4,\(a0\),a1
++[ 	]+[0-9a-f]+:[ 	]+6ab57207[ 	]+vlsseg4e64.v[ 	]+v4,\(a0\),a1
++[ 	]+[0-9a-f]+:[ 	]+68b57207[ 	]+vlsseg4e64.v[ 	]+v4,\(a0\),a1,v0.t
++[ 	]+[0-9a-f]+:[ 	]+6ab57227[ 	]+vssseg4e64.v[ 	]+v4,\(a0\),a1
++[ 	]+[0-9a-f]+:[ 	]+6ab57227[ 	]+vssseg4e64.v[ 	]+v4,\(a0\),a1
++[ 	]+[0-9a-f]+:[ 	]+68b57227[ 	]+vssseg4e64.v[ 	]+v4,\(a0\),a1,v0.t
++[ 	]+[0-9a-f]+:[ 	]+8ab57207[ 	]+vlsseg5e64.v[ 	]+v4,\(a0\),a1
++[ 	]+[0-9a-f]+:[ 	]+8ab57207[ 	]+vlsseg5e64.v[ 	]+v4,\(a0\),a1
++[ 	]+[0-9a-f]+:[ 	]+88b57207[ 	]+vlsseg5e64.v[ 	]+v4,\(a0\),a1,v0.t
++[ 	]+[0-9a-f]+:[ 	]+8ab57227[ 	]+vssseg5e64.v[ 	]+v4,\(a0\),a1
++[ 	]+[0-9a-f]+:[ 	]+8ab57227[ 	]+vssseg5e64.v[ 	]+v4,\(a0\),a1
++[ 	]+[0-9a-f]+:[ 	]+88b57227[ 	]+vssseg5e64.v[ 	]+v4,\(a0\),a1,v0.t
++[ 	]+[0-9a-f]+:[ 	]+aab57207[ 	]+vlsseg6e64.v[ 	]+v4,\(a0\),a1
++[ 	]+[0-9a-f]+:[ 	]+aab57207[ 	]+vlsseg6e64.v[ 	]+v4,\(a0\),a1
++[ 	]+[0-9a-f]+:[ 	]+a8b57207[ 	]+vlsseg6e64.v[ 	]+v4,\(a0\),a1,v0.t
++[ 	]+[0-9a-f]+:[ 	]+aab57227[ 	]+vssseg6e64.v[ 	]+v4,\(a0\),a1
++[ 	]+[0-9a-f]+:[ 	]+aab57227[ 	]+vssseg6e64.v[ 	]+v4,\(a0\),a1
++[ 	]+[0-9a-f]+:[ 	]+a8b57227[ 	]+vssseg6e64.v[ 	]+v4,\(a0\),a1,v0.t
++[ 	]+[0-9a-f]+:[ 	]+cab57207[ 	]+vlsseg7e64.v[ 	]+v4,\(a0\),a1
++[ 	]+[0-9a-f]+:[ 	]+cab57207[ 	]+vlsseg7e64.v[ 	]+v4,\(a0\),a1
++[ 	]+[0-9a-f]+:[ 	]+c8b57207[ 	]+vlsseg7e64.v[ 	]+v4,\(a0\),a1,v0.t
++[ 	]+[0-9a-f]+:[ 	]+cab57227[ 	]+vssseg7e64.v[ 	]+v4,\(a0\),a1
++[ 	]+[0-9a-f]+:[ 	]+cab57227[ 	]+vssseg7e64.v[ 	]+v4,\(a0\),a1
++[ 	]+[0-9a-f]+:[ 	]+c8b57227[ 	]+vssseg7e64.v[ 	]+v4,\(a0\),a1,v0.t
++[ 	]+[0-9a-f]+:[ 	]+eab57207[ 	]+vlsseg8e64.v[ 	]+v4,\(a0\),a1
++[ 	]+[0-9a-f]+:[ 	]+eab57207[ 	]+vlsseg8e64.v[ 	]+v4,\(a0\),a1
++[ 	]+[0-9a-f]+:[ 	]+e8b57207[ 	]+vlsseg8e64.v[ 	]+v4,\(a0\),a1,v0.t
++[ 	]+[0-9a-f]+:[ 	]+eab57227[ 	]+vssseg8e64.v[ 	]+v4,\(a0\),a1
++[ 	]+[0-9a-f]+:[ 	]+eab57227[ 	]+vssseg8e64.v[ 	]+v4,\(a0\),a1
++[ 	]+[0-9a-f]+:[ 	]+e8b57227[ 	]+vssseg8e64.v[ 	]+v4,\(a0\),a1,v0.t
++[ 	]+[0-9a-f]+:[ 	]+3ab50207[ 	]+vlsseg2e128.v[ 	]+v4,\(a0\),a1
++[ 	]+[0-9a-f]+:[ 	]+3ab50207[ 	]+vlsseg2e128.v[ 	]+v4,\(a0\),a1
++[ 	]+[0-9a-f]+:[ 	]+38b50207[ 	]+vlsseg2e128.v[ 	]+v4,\(a0\),a1,v0.t
++[ 	]+[0-9a-f]+:[ 	]+3ab50227[ 	]+vssseg2e128.v[ 	]+v4,\(a0\),a1
++[ 	]+[0-9a-f]+:[ 	]+3ab50227[ 	]+vssseg2e128.v[ 	]+v4,\(a0\),a1
++[ 	]+[0-9a-f]+:[ 	]+38b50227[ 	]+vssseg2e128.v[ 	]+v4,\(a0\),a1,v0.t
++[ 	]+[0-9a-f]+:[ 	]+5ab50207[ 	]+vlsseg3e128.v[ 	]+v4,\(a0\),a1
++[ 	]+[0-9a-f]+:[ 	]+5ab50207[ 	]+vlsseg3e128.v[ 	]+v4,\(a0\),a1
++[ 	]+[0-9a-f]+:[ 	]+58b50207[ 	]+vlsseg3e128.v[ 	]+v4,\(a0\),a1,v0.t
++[ 	]+[0-9a-f]+:[ 	]+5ab50227[ 	]+vssseg3e128.v[ 	]+v4,\(a0\),a1
++[ 	]+[0-9a-f]+:[ 	]+5ab50227[ 	]+vssseg3e128.v[ 	]+v4,\(a0\),a1
++[ 	]+[0-9a-f]+:[ 	]+58b50227[ 	]+vssseg3e128.v[ 	]+v4,\(a0\),a1,v0.t
++[ 	]+[0-9a-f]+:[ 	]+7ab50207[ 	]+vlsseg4e128.v[ 	]+v4,\(a0\),a1
++[ 	]+[0-9a-f]+:[ 	]+7ab50207[ 	]+vlsseg4e128.v[ 	]+v4,\(a0\),a1
++[ 	]+[0-9a-f]+:[ 	]+78b50207[ 	]+vlsseg4e128.v[ 	]+v4,\(a0\),a1,v0.t
++[ 	]+[0-9a-f]+:[ 	]+7ab50227[ 	]+vssseg4e128.v[ 	]+v4,\(a0\),a1
++[ 	]+[0-9a-f]+:[ 	]+7ab50227[ 	]+vssseg4e128.v[ 	]+v4,\(a0\),a1
++[ 	]+[0-9a-f]+:[ 	]+78b50227[ 	]+vssseg4e128.v[ 	]+v4,\(a0\),a1,v0.t
++[ 	]+[0-9a-f]+:[ 	]+9ab50207[ 	]+vlsseg5e128.v[ 	]+v4,\(a0\),a1
++[ 	]+[0-9a-f]+:[ 	]+9ab50207[ 	]+vlsseg5e128.v[ 	]+v4,\(a0\),a1
++[ 	]+[0-9a-f]+:[ 	]+98b50207[ 	]+vlsseg5e128.v[ 	]+v4,\(a0\),a1,v0.t
++[ 	]+[0-9a-f]+:[ 	]+9ab50227[ 	]+vssseg5e128.v[ 	]+v4,\(a0\),a1
++[ 	]+[0-9a-f]+:[ 	]+9ab50227[ 	]+vssseg5e128.v[ 	]+v4,\(a0\),a1
++[ 	]+[0-9a-f]+:[ 	]+98b50227[ 	]+vssseg5e128.v[ 	]+v4,\(a0\),a1,v0.t
++[ 	]+[0-9a-f]+:[ 	]+bab50207[ 	]+vlsseg6e128.v[ 	]+v4,\(a0\),a1
++[ 	]+[0-9a-f]+:[ 	]+bab50207[ 	]+vlsseg6e128.v[ 	]+v4,\(a0\),a1
++[ 	]+[0-9a-f]+:[ 	]+b8b50207[ 	]+vlsseg6e128.v[ 	]+v4,\(a0\),a1,v0.t
++[ 	]+[0-9a-f]+:[ 	]+bab50227[ 	]+vssseg6e128.v[ 	]+v4,\(a0\),a1
++[ 	]+[0-9a-f]+:[ 	]+bab50227[ 	]+vssseg6e128.v[ 	]+v4,\(a0\),a1
++[ 	]+[0-9a-f]+:[ 	]+b8b50227[ 	]+vssseg6e128.v[ 	]+v4,\(a0\),a1,v0.t
++[ 	]+[0-9a-f]+:[ 	]+dab50207[ 	]+vlsseg7e128.v[ 	]+v4,\(a0\),a1
++[ 	]+[0-9a-f]+:[ 	]+dab50207[ 	]+vlsseg7e128.v[ 	]+v4,\(a0\),a1
++[ 	]+[0-9a-f]+:[ 	]+d8b50207[ 	]+vlsseg7e128.v[ 	]+v4,\(a0\),a1,v0.t
++[ 	]+[0-9a-f]+:[ 	]+dab50227[ 	]+vssseg7e128.v[ 	]+v4,\(a0\),a1
++[ 	]+[0-9a-f]+:[ 	]+dab50227[ 	]+vssseg7e128.v[ 	]+v4,\(a0\),a1
++[ 	]+[0-9a-f]+:[ 	]+d8b50227[ 	]+vssseg7e128.v[ 	]+v4,\(a0\),a1,v0.t
++[ 	]+[0-9a-f]+:[ 	]+fab50207[ 	]+vlsseg8e128.v[ 	]+v4,\(a0\),a1
++[ 	]+[0-9a-f]+:[ 	]+fab50207[ 	]+vlsseg8e128.v[ 	]+v4,\(a0\),a1
++[ 	]+[0-9a-f]+:[ 	]+f8b50207[ 	]+vlsseg8e128.v[ 	]+v4,\(a0\),a1,v0.t
++[ 	]+[0-9a-f]+:[ 	]+fab50227[ 	]+vssseg8e128.v[ 	]+v4,\(a0\),a1
++[ 	]+[0-9a-f]+:[ 	]+fab50227[ 	]+vssseg8e128.v[ 	]+v4,\(a0\),a1
++[ 	]+[0-9a-f]+:[ 	]+f8b50227[ 	]+vssseg8e128.v[ 	]+v4,\(a0\),a1,v0.t
++[ 	]+[0-9a-f]+:[ 	]+3ab55207[ 	]+vlsseg2e256.v[ 	]+v4,\(a0\),a1
++[ 	]+[0-9a-f]+:[ 	]+3ab55207[ 	]+vlsseg2e256.v[ 	]+v4,\(a0\),a1
++[ 	]+[0-9a-f]+:[ 	]+38b55207[ 	]+vlsseg2e256.v[ 	]+v4,\(a0\),a1,v0.t
++[ 	]+[0-9a-f]+:[ 	]+3ab55227[ 	]+vssseg2e256.v[ 	]+v4,\(a0\),a1
++[ 	]+[0-9a-f]+:[ 	]+3ab55227[ 	]+vssseg2e256.v[ 	]+v4,\(a0\),a1
++[ 	]+[0-9a-f]+:[ 	]+38b55227[ 	]+vssseg2e256.v[ 	]+v4,\(a0\),a1,v0.t
++[ 	]+[0-9a-f]+:[ 	]+5ab55207[ 	]+vlsseg3e256.v[ 	]+v4,\(a0\),a1
++[ 	]+[0-9a-f]+:[ 	]+5ab55207[ 	]+vlsseg3e256.v[ 	]+v4,\(a0\),a1
++[ 	]+[0-9a-f]+:[ 	]+58b55207[ 	]+vlsseg3e256.v[ 	]+v4,\(a0\),a1,v0.t
++[ 	]+[0-9a-f]+:[ 	]+5ab55227[ 	]+vssseg3e256.v[ 	]+v4,\(a0\),a1
++[ 	]+[0-9a-f]+:[ 	]+5ab55227[ 	]+vssseg3e256.v[ 	]+v4,\(a0\),a1
++[ 	]+[0-9a-f]+:[ 	]+58b55227[ 	]+vssseg3e256.v[ 	]+v4,\(a0\),a1,v0.t
++[ 	]+[0-9a-f]+:[ 	]+7ab55207[ 	]+vlsseg4e256.v[ 	]+v4,\(a0\),a1
++[ 	]+[0-9a-f]+:[ 	]+7ab55207[ 	]+vlsseg4e256.v[ 	]+v4,\(a0\),a1
++[ 	]+[0-9a-f]+:[ 	]+78b55207[ 	]+vlsseg4e256.v[ 	]+v4,\(a0\),a1,v0.t
++[ 	]+[0-9a-f]+:[ 	]+7ab55227[ 	]+vssseg4e256.v[ 	]+v4,\(a0\),a1
++[ 	]+[0-9a-f]+:[ 	]+7ab55227[ 	]+vssseg4e256.v[ 	]+v4,\(a0\),a1
++[ 	]+[0-9a-f]+:[ 	]+78b55227[ 	]+vssseg4e256.v[ 	]+v4,\(a0\),a1,v0.t
++[ 	]+[0-9a-f]+:[ 	]+9ab55207[ 	]+vlsseg5e256.v[ 	]+v4,\(a0\),a1
++[ 	]+[0-9a-f]+:[ 	]+9ab55207[ 	]+vlsseg5e256.v[ 	]+v4,\(a0\),a1
++[ 	]+[0-9a-f]+:[ 	]+98b55207[ 	]+vlsseg5e256.v[ 	]+v4,\(a0\),a1,v0.t
++[ 	]+[0-9a-f]+:[ 	]+9ab55227[ 	]+vssseg5e256.v[ 	]+v4,\(a0\),a1
++[ 	]+[0-9a-f]+:[ 	]+9ab55227[ 	]+vssseg5e256.v[ 	]+v4,\(a0\),a1
++[ 	]+[0-9a-f]+:[ 	]+98b55227[ 	]+vssseg5e256.v[ 	]+v4,\(a0\),a1,v0.t
++[ 	]+[0-9a-f]+:[ 	]+bab55207[ 	]+vlsseg6e256.v[ 	]+v4,\(a0\),a1
++[ 	]+[0-9a-f]+:[ 	]+bab55207[ 	]+vlsseg6e256.v[ 	]+v4,\(a0\),a1
++[ 	]+[0-9a-f]+:[ 	]+b8b55207[ 	]+vlsseg6e256.v[ 	]+v4,\(a0\),a1,v0.t
++[ 	]+[0-9a-f]+:[ 	]+bab55227[ 	]+vssseg6e256.v[ 	]+v4,\(a0\),a1
++[ 	]+[0-9a-f]+:[ 	]+bab55227[ 	]+vssseg6e256.v[ 	]+v4,\(a0\),a1
++[ 	]+[0-9a-f]+:[ 	]+b8b55227[ 	]+vssseg6e256.v[ 	]+v4,\(a0\),a1,v0.t
++[ 	]+[0-9a-f]+:[ 	]+dab55207[ 	]+vlsseg7e256.v[ 	]+v4,\(a0\),a1
++[ 	]+[0-9a-f]+:[ 	]+dab55207[ 	]+vlsseg7e256.v[ 	]+v4,\(a0\),a1
++[ 	]+[0-9a-f]+:[ 	]+d8b55207[ 	]+vlsseg7e256.v[ 	]+v4,\(a0\),a1,v0.t
++[ 	]+[0-9a-f]+:[ 	]+dab55227[ 	]+vssseg7e256.v[ 	]+v4,\(a0\),a1
++[ 	]+[0-9a-f]+:[ 	]+dab55227[ 	]+vssseg7e256.v[ 	]+v4,\(a0\),a1
++[ 	]+[0-9a-f]+:[ 	]+d8b55227[ 	]+vssseg7e256.v[ 	]+v4,\(a0\),a1,v0.t
++[ 	]+[0-9a-f]+:[ 	]+fab55207[ 	]+vlsseg8e256.v[ 	]+v4,\(a0\),a1
++[ 	]+[0-9a-f]+:[ 	]+fab55207[ 	]+vlsseg8e256.v[ 	]+v4,\(a0\),a1
++[ 	]+[0-9a-f]+:[ 	]+f8b55207[ 	]+vlsseg8e256.v[ 	]+v4,\(a0\),a1,v0.t
++[ 	]+[0-9a-f]+:[ 	]+fab55227[ 	]+vssseg8e256.v[ 	]+v4,\(a0\),a1
++[ 	]+[0-9a-f]+:[ 	]+fab55227[ 	]+vssseg8e256.v[ 	]+v4,\(a0\),a1
++[ 	]+[0-9a-f]+:[ 	]+f8b55227[ 	]+vssseg8e256.v[ 	]+v4,\(a0\),a1,v0.t
++[ 	]+[0-9a-f]+:[ 	]+3ab56207[ 	]+vlsseg2e512.v[ 	]+v4,\(a0\),a1
++[ 	]+[0-9a-f]+:[ 	]+3ab56207[ 	]+vlsseg2e512.v[ 	]+v4,\(a0\),a1
++[ 	]+[0-9a-f]+:[ 	]+38b56207[ 	]+vlsseg2e512.v[ 	]+v4,\(a0\),a1,v0.t
++[ 	]+[0-9a-f]+:[ 	]+3ab56227[ 	]+vssseg2e512.v[ 	]+v4,\(a0\),a1
++[ 	]+[0-9a-f]+:[ 	]+3ab56227[ 	]+vssseg2e512.v[ 	]+v4,\(a0\),a1
++[ 	]+[0-9a-f]+:[ 	]+38b56227[ 	]+vssseg2e512.v[ 	]+v4,\(a0\),a1,v0.t
++[ 	]+[0-9a-f]+:[ 	]+5ab56207[ 	]+vlsseg3e512.v[ 	]+v4,\(a0\),a1
++[ 	]+[0-9a-f]+:[ 	]+5ab56207[ 	]+vlsseg3e512.v[ 	]+v4,\(a0\),a1
++[ 	]+[0-9a-f]+:[ 	]+58b56207[ 	]+vlsseg3e512.v[ 	]+v4,\(a0\),a1,v0.t
++[ 	]+[0-9a-f]+:[ 	]+5ab56227[ 	]+vssseg3e512.v[ 	]+v4,\(a0\),a1
++[ 	]+[0-9a-f]+:[ 	]+5ab56227[ 	]+vssseg3e512.v[ 	]+v4,\(a0\),a1
++[ 	]+[0-9a-f]+:[ 	]+58b56227[ 	]+vssseg3e512.v[ 	]+v4,\(a0\),a1,v0.t
++[ 	]+[0-9a-f]+:[ 	]+7ab56207[ 	]+vlsseg4e512.v[ 	]+v4,\(a0\),a1
++[ 	]+[0-9a-f]+:[ 	]+7ab56207[ 	]+vlsseg4e512.v[ 	]+v4,\(a0\),a1
++[ 	]+[0-9a-f]+:[ 	]+78b56207[ 	]+vlsseg4e512.v[ 	]+v4,\(a0\),a1,v0.t
++[ 	]+[0-9a-f]+:[ 	]+7ab56227[ 	]+vssseg4e512.v[ 	]+v4,\(a0\),a1
++[ 	]+[0-9a-f]+:[ 	]+7ab56227[ 	]+vssseg4e512.v[ 	]+v4,\(a0\),a1
++[ 	]+[0-9a-f]+:[ 	]+78b56227[ 	]+vssseg4e512.v[ 	]+v4,\(a0\),a1,v0.t
++[ 	]+[0-9a-f]+:[ 	]+9ab56207[ 	]+vlsseg5e512.v[ 	]+v4,\(a0\),a1
++[ 	]+[0-9a-f]+:[ 	]+9ab56207[ 	]+vlsseg5e512.v[ 	]+v4,\(a0\),a1
++[ 	]+[0-9a-f]+:[ 	]+98b56207[ 	]+vlsseg5e512.v[ 	]+v4,\(a0\),a1,v0.t
++[ 	]+[0-9a-f]+:[ 	]+9ab56227[ 	]+vssseg5e512.v[ 	]+v4,\(a0\),a1
++[ 	]+[0-9a-f]+:[ 	]+9ab56227[ 	]+vssseg5e512.v[ 	]+v4,\(a0\),a1
++[ 	]+[0-9a-f]+:[ 	]+98b56227[ 	]+vssseg5e512.v[ 	]+v4,\(a0\),a1,v0.t
++[ 	]+[0-9a-f]+:[ 	]+bab56207[ 	]+vlsseg6e512.v[ 	]+v4,\(a0\),a1
++[ 	]+[0-9a-f]+:[ 	]+bab56207[ 	]+vlsseg6e512.v[ 	]+v4,\(a0\),a1
++[ 	]+[0-9a-f]+:[ 	]+b8b56207[ 	]+vlsseg6e512.v[ 	]+v4,\(a0\),a1,v0.t
++[ 	]+[0-9a-f]+:[ 	]+bab56227[ 	]+vssseg6e512.v[ 	]+v4,\(a0\),a1
++[ 	]+[0-9a-f]+:[ 	]+bab56227[ 	]+vssseg6e512.v[ 	]+v4,\(a0\),a1
++[ 	]+[0-9a-f]+:[ 	]+b8b56227[ 	]+vssseg6e512.v[ 	]+v4,\(a0\),a1,v0.t
++[ 	]+[0-9a-f]+:[ 	]+dab56207[ 	]+vlsseg7e512.v[ 	]+v4,\(a0\),a1
++[ 	]+[0-9a-f]+:[ 	]+dab56207[ 	]+vlsseg7e512.v[ 	]+v4,\(a0\),a1
++[ 	]+[0-9a-f]+:[ 	]+d8b56207[ 	]+vlsseg7e512.v[ 	]+v4,\(a0\),a1,v0.t
++[ 	]+[0-9a-f]+:[ 	]+dab56227[ 	]+vssseg7e512.v[ 	]+v4,\(a0\),a1
++[ 	]+[0-9a-f]+:[ 	]+dab56227[ 	]+vssseg7e512.v[ 	]+v4,\(a0\),a1
++[ 	]+[0-9a-f]+:[ 	]+d8b56227[ 	]+vssseg7e512.v[ 	]+v4,\(a0\),a1,v0.t
++[ 	]+[0-9a-f]+:[ 	]+fab56207[ 	]+vlsseg8e512.v[ 	]+v4,\(a0\),a1
++[ 	]+[0-9a-f]+:[ 	]+fab56207[ 	]+vlsseg8e512.v[ 	]+v4,\(a0\),a1
++[ 	]+[0-9a-f]+:[ 	]+f8b56207[ 	]+vlsseg8e512.v[ 	]+v4,\(a0\),a1,v0.t
++[ 	]+[0-9a-f]+:[ 	]+fab56227[ 	]+vssseg8e512.v[ 	]+v4,\(a0\),a1
++[ 	]+[0-9a-f]+:[ 	]+fab56227[ 	]+vssseg8e512.v[ 	]+v4,\(a0\),a1
++[ 	]+[0-9a-f]+:[ 	]+f8b56227[ 	]+vssseg8e512.v[ 	]+v4,\(a0\),a1,v0.t
++[ 	]+[0-9a-f]+:[ 	]+3ab57207[ 	]+vlsseg2e1024.v[ 	]+v4,\(a0\),a1
++[ 	]+[0-9a-f]+:[ 	]+3ab57207[ 	]+vlsseg2e1024.v[ 	]+v4,\(a0\),a1
++[ 	]+[0-9a-f]+:[ 	]+38b57207[ 	]+vlsseg2e1024.v[ 	]+v4,\(a0\),a1,v0.t
++[ 	]+[0-9a-f]+:[ 	]+3ab57227[ 	]+vssseg2e1024.v[ 	]+v4,\(a0\),a1
++[ 	]+[0-9a-f]+:[ 	]+3ab57227[ 	]+vssseg2e1024.v[ 	]+v4,\(a0\),a1
++[ 	]+[0-9a-f]+:[ 	]+38b57227[ 	]+vssseg2e1024.v[ 	]+v4,\(a0\),a1,v0.t
++[ 	]+[0-9a-f]+:[ 	]+5ab57207[ 	]+vlsseg3e1024.v[ 	]+v4,\(a0\),a1
++[ 	]+[0-9a-f]+:[ 	]+5ab57207[ 	]+vlsseg3e1024.v[ 	]+v4,\(a0\),a1
++[ 	]+[0-9a-f]+:[ 	]+58b57207[ 	]+vlsseg3e1024.v[ 	]+v4,\(a0\),a1,v0.t
++[ 	]+[0-9a-f]+:[ 	]+5ab57227[ 	]+vssseg3e1024.v[ 	]+v4,\(a0\),a1
++[ 	]+[0-9a-f]+:[ 	]+5ab57227[ 	]+vssseg3e1024.v[ 	]+v4,\(a0\),a1
++[ 	]+[0-9a-f]+:[ 	]+58b57227[ 	]+vssseg3e1024.v[ 	]+v4,\(a0\),a1,v0.t
++[ 	]+[0-9a-f]+:[ 	]+7ab57207[ 	]+vlsseg4e1024.v[ 	]+v4,\(a0\),a1
++[ 	]+[0-9a-f]+:[ 	]+7ab57207[ 	]+vlsseg4e1024.v[ 	]+v4,\(a0\),a1
++[ 	]+[0-9a-f]+:[ 	]+78b57207[ 	]+vlsseg4e1024.v[ 	]+v4,\(a0\),a1,v0.t
++[ 	]+[0-9a-f]+:[ 	]+7ab57227[ 	]+vssseg4e1024.v[ 	]+v4,\(a0\),a1
++[ 	]+[0-9a-f]+:[ 	]+7ab57227[ 	]+vssseg4e1024.v[ 	]+v4,\(a0\),a1
++[ 	]+[0-9a-f]+:[ 	]+78b57227[ 	]+vssseg4e1024.v[ 	]+v4,\(a0\),a1,v0.t
++[ 	]+[0-9a-f]+:[ 	]+9ab57207[ 	]+vlsseg5e1024.v[ 	]+v4,\(a0\),a1
++[ 	]+[0-9a-f]+:[ 	]+9ab57207[ 	]+vlsseg5e1024.v[ 	]+v4,\(a0\),a1
++[ 	]+[0-9a-f]+:[ 	]+98b57207[ 	]+vlsseg5e1024.v[ 	]+v4,\(a0\),a1,v0.t
++[ 	]+[0-9a-f]+:[ 	]+9ab57227[ 	]+vssseg5e1024.v[ 	]+v4,\(a0\),a1
++[ 	]+[0-9a-f]+:[ 	]+9ab57227[ 	]+vssseg5e1024.v[ 	]+v4,\(a0\),a1
++[ 	]+[0-9a-f]+:[ 	]+98b57227[ 	]+vssseg5e1024.v[ 	]+v4,\(a0\),a1,v0.t
++[ 	]+[0-9a-f]+:[ 	]+bab57207[ 	]+vlsseg6e1024.v[ 	]+v4,\(a0\),a1
++[ 	]+[0-9a-f]+:[ 	]+bab57207[ 	]+vlsseg6e1024.v[ 	]+v4,\(a0\),a1
++[ 	]+[0-9a-f]+:[ 	]+b8b57207[ 	]+vlsseg6e1024.v[ 	]+v4,\(a0\),a1,v0.t
++[ 	]+[0-9a-f]+:[ 	]+bab57227[ 	]+vssseg6e1024.v[ 	]+v4,\(a0\),a1
++[ 	]+[0-9a-f]+:[ 	]+bab57227[ 	]+vssseg6e1024.v[ 	]+v4,\(a0\),a1
++[ 	]+[0-9a-f]+:[ 	]+b8b57227[ 	]+vssseg6e1024.v[ 	]+v4,\(a0\),a1,v0.t
++[ 	]+[0-9a-f]+:[ 	]+dab57207[ 	]+vlsseg7e1024.v[ 	]+v4,\(a0\),a1
++[ 	]+[0-9a-f]+:[ 	]+dab57207[ 	]+vlsseg7e1024.v[ 	]+v4,\(a0\),a1
++[ 	]+[0-9a-f]+:[ 	]+d8b57207[ 	]+vlsseg7e1024.v[ 	]+v4,\(a0\),a1,v0.t
++[ 	]+[0-9a-f]+:[ 	]+dab57227[ 	]+vssseg7e1024.v[ 	]+v4,\(a0\),a1
++[ 	]+[0-9a-f]+:[ 	]+dab57227[ 	]+vssseg7e1024.v[ 	]+v4,\(a0\),a1
++[ 	]+[0-9a-f]+:[ 	]+d8b57227[ 	]+vssseg7e1024.v[ 	]+v4,\(a0\),a1,v0.t
++[ 	]+[0-9a-f]+:[ 	]+fab57207[ 	]+vlsseg8e1024.v[ 	]+v4,\(a0\),a1
++[ 	]+[0-9a-f]+:[ 	]+fab57207[ 	]+vlsseg8e1024.v[ 	]+v4,\(a0\),a1
++[ 	]+[0-9a-f]+:[ 	]+f8b57207[ 	]+vlsseg8e1024.v[ 	]+v4,\(a0\),a1,v0.t
++[ 	]+[0-9a-f]+:[ 	]+fab57227[ 	]+vssseg8e1024.v[ 	]+v4,\(a0\),a1
++[ 	]+[0-9a-f]+:[ 	]+fab57227[ 	]+vssseg8e1024.v[ 	]+v4,\(a0\),a1
++[ 	]+[0-9a-f]+:[ 	]+f8b57227[ 	]+vssseg8e1024.v[ 	]+v4,\(a0\),a1,v0.t
++[ 	]+[0-9a-f]+:[ 	]+2ec50207[ 	]+vlxseg2ei8.v[ 	]+v4,\(a0\),v12
++[ 	]+[0-9a-f]+:[ 	]+2ec50207[ 	]+vlxseg2ei8.v[ 	]+v4,\(a0\),v12
++[ 	]+[0-9a-f]+:[ 	]+2cc50207[ 	]+vlxseg2ei8.v[ 	]+v4,\(a0\),v12,v0.t
++[ 	]+[0-9a-f]+:[ 	]+2ec50227[ 	]+vsxseg2ei8.v[ 	]+v4,\(a0\),v12
++[ 	]+[0-9a-f]+:[ 	]+2ec50227[ 	]+vsxseg2ei8.v[ 	]+v4,\(a0\),v12
++[ 	]+[0-9a-f]+:[ 	]+2cc50227[ 	]+vsxseg2ei8.v[ 	]+v4,\(a0\),v12,v0.t
++[ 	]+[0-9a-f]+:[ 	]+4ec50207[ 	]+vlxseg3ei8.v[ 	]+v4,\(a0\),v12
++[ 	]+[0-9a-f]+:[ 	]+4ec50207[ 	]+vlxseg3ei8.v[ 	]+v4,\(a0\),v12
++[ 	]+[0-9a-f]+:[ 	]+4cc50207[ 	]+vlxseg3ei8.v[ 	]+v4,\(a0\),v12,v0.t
++[ 	]+[0-9a-f]+:[ 	]+4ec50227[ 	]+vsxseg3ei8.v[ 	]+v4,\(a0\),v12
++[ 	]+[0-9a-f]+:[ 	]+4ec50227[ 	]+vsxseg3ei8.v[ 	]+v4,\(a0\),v12
++[ 	]+[0-9a-f]+:[ 	]+4cc50227[ 	]+vsxseg3ei8.v[ 	]+v4,\(a0\),v12,v0.t
++[ 	]+[0-9a-f]+:[ 	]+6ec50207[ 	]+vlxseg4ei8.v[ 	]+v4,\(a0\),v12
++[ 	]+[0-9a-f]+:[ 	]+6ec50207[ 	]+vlxseg4ei8.v[ 	]+v4,\(a0\),v12
++[ 	]+[0-9a-f]+:[ 	]+6cc50207[ 	]+vlxseg4ei8.v[ 	]+v4,\(a0\),v12,v0.t
++[ 	]+[0-9a-f]+:[ 	]+6ec50227[ 	]+vsxseg4ei8.v[ 	]+v4,\(a0\),v12
++[ 	]+[0-9a-f]+:[ 	]+6ec50227[ 	]+vsxseg4ei8.v[ 	]+v4,\(a0\),v12
++[ 	]+[0-9a-f]+:[ 	]+6cc50227[ 	]+vsxseg4ei8.v[ 	]+v4,\(a0\),v12,v0.t
++[ 	]+[0-9a-f]+:[ 	]+8ec50207[ 	]+vlxseg5ei8.v[ 	]+v4,\(a0\),v12
++[ 	]+[0-9a-f]+:[ 	]+8ec50207[ 	]+vlxseg5ei8.v[ 	]+v4,\(a0\),v12
++[ 	]+[0-9a-f]+:[ 	]+8cc50207[ 	]+vlxseg5ei8.v[ 	]+v4,\(a0\),v12,v0.t
++[ 	]+[0-9a-f]+:[ 	]+8ec50227[ 	]+vsxseg5ei8.v[ 	]+v4,\(a0\),v12
++[ 	]+[0-9a-f]+:[ 	]+8ec50227[ 	]+vsxseg5ei8.v[ 	]+v4,\(a0\),v12
++[ 	]+[0-9a-f]+:[ 	]+8cc50227[ 	]+vsxseg5ei8.v[ 	]+v4,\(a0\),v12,v0.t
++[ 	]+[0-9a-f]+:[ 	]+aec50207[ 	]+vlxseg6ei8.v[ 	]+v4,\(a0\),v12
++[ 	]+[0-9a-f]+:[ 	]+aec50207[ 	]+vlxseg6ei8.v[ 	]+v4,\(a0\),v12
++[ 	]+[0-9a-f]+:[ 	]+acc50207[ 	]+vlxseg6ei8.v[ 	]+v4,\(a0\),v12,v0.t
++[ 	]+[0-9a-f]+:[ 	]+aec50227[ 	]+vsxseg6ei8.v[ 	]+v4,\(a0\),v12
++[ 	]+[0-9a-f]+:[ 	]+aec50227[ 	]+vsxseg6ei8.v[ 	]+v4,\(a0\),v12
++[ 	]+[0-9a-f]+:[ 	]+acc50227[ 	]+vsxseg6ei8.v[ 	]+v4,\(a0\),v12,v0.t
++[ 	]+[0-9a-f]+:[ 	]+cec50207[ 	]+vlxseg7ei8.v[ 	]+v4,\(a0\),v12
++[ 	]+[0-9a-f]+:[ 	]+cec50207[ 	]+vlxseg7ei8.v[ 	]+v4,\(a0\),v12
++[ 	]+[0-9a-f]+:[ 	]+ccc50207[ 	]+vlxseg7ei8.v[ 	]+v4,\(a0\),v12,v0.t
++[ 	]+[0-9a-f]+:[ 	]+cec50227[ 	]+vsxseg7ei8.v[ 	]+v4,\(a0\),v12
++[ 	]+[0-9a-f]+:[ 	]+cec50227[ 	]+vsxseg7ei8.v[ 	]+v4,\(a0\),v12
++[ 	]+[0-9a-f]+:[ 	]+ccc50227[ 	]+vsxseg7ei8.v[ 	]+v4,\(a0\),v12,v0.t
++[ 	]+[0-9a-f]+:[ 	]+eec50207[ 	]+vlxseg8ei8.v[ 	]+v4,\(a0\),v12
++[ 	]+[0-9a-f]+:[ 	]+eec50207[ 	]+vlxseg8ei8.v[ 	]+v4,\(a0\),v12
++[ 	]+[0-9a-f]+:[ 	]+ecc50207[ 	]+vlxseg8ei8.v[ 	]+v4,\(a0\),v12,v0.t
++[ 	]+[0-9a-f]+:[ 	]+eec50227[ 	]+vsxseg8ei8.v[ 	]+v4,\(a0\),v12
++[ 	]+[0-9a-f]+:[ 	]+eec50227[ 	]+vsxseg8ei8.v[ 	]+v4,\(a0\),v12
++[ 	]+[0-9a-f]+:[ 	]+ecc50227[ 	]+vsxseg8ei8.v[ 	]+v4,\(a0\),v12,v0.t
++[ 	]+[0-9a-f]+:[ 	]+2ec55207[ 	]+vlxseg2ei16.v[ 	]+v4,\(a0\),v12
++[ 	]+[0-9a-f]+:[ 	]+2ec55207[ 	]+vlxseg2ei16.v[ 	]+v4,\(a0\),v12
++[ 	]+[0-9a-f]+:[ 	]+2cc55207[ 	]+vlxseg2ei16.v[ 	]+v4,\(a0\),v12,v0.t
++[ 	]+[0-9a-f]+:[ 	]+2ec55227[ 	]+vsxseg2ei16.v[ 	]+v4,\(a0\),v12
++[ 	]+[0-9a-f]+:[ 	]+2ec55227[ 	]+vsxseg2ei16.v[ 	]+v4,\(a0\),v12
++[ 	]+[0-9a-f]+:[ 	]+2cc55227[ 	]+vsxseg2ei16.v[ 	]+v4,\(a0\),v12,v0.t
++[ 	]+[0-9a-f]+:[ 	]+4ec55207[ 	]+vlxseg3ei16.v[ 	]+v4,\(a0\),v12
++[ 	]+[0-9a-f]+:[ 	]+4ec55207[ 	]+vlxseg3ei16.v[ 	]+v4,\(a0\),v12
++[ 	]+[0-9a-f]+:[ 	]+4cc55207[ 	]+vlxseg3ei16.v[ 	]+v4,\(a0\),v12,v0.t
++[ 	]+[0-9a-f]+:[ 	]+4ec55227[ 	]+vsxseg3ei16.v[ 	]+v4,\(a0\),v12
++[ 	]+[0-9a-f]+:[ 	]+4ec55227[ 	]+vsxseg3ei16.v[ 	]+v4,\(a0\),v12
++[ 	]+[0-9a-f]+:[ 	]+4cc55227[ 	]+vsxseg3ei16.v[ 	]+v4,\(a0\),v12,v0.t
++[ 	]+[0-9a-f]+:[ 	]+6ec55207[ 	]+vlxseg4ei16.v[ 	]+v4,\(a0\),v12
++[ 	]+[0-9a-f]+:[ 	]+6ec55207[ 	]+vlxseg4ei16.v[ 	]+v4,\(a0\),v12
++[ 	]+[0-9a-f]+:[ 	]+6cc55207[ 	]+vlxseg4ei16.v[ 	]+v4,\(a0\),v12,v0.t
++[ 	]+[0-9a-f]+:[ 	]+6ec55227[ 	]+vsxseg4ei16.v[ 	]+v4,\(a0\),v12
++[ 	]+[0-9a-f]+:[ 	]+6ec55227[ 	]+vsxseg4ei16.v[ 	]+v4,\(a0\),v12
++[ 	]+[0-9a-f]+:[ 	]+6cc55227[ 	]+vsxseg4ei16.v[ 	]+v4,\(a0\),v12,v0.t
++[ 	]+[0-9a-f]+:[ 	]+8ec55207[ 	]+vlxseg5ei16.v[ 	]+v4,\(a0\),v12
++[ 	]+[0-9a-f]+:[ 	]+8ec55207[ 	]+vlxseg5ei16.v[ 	]+v4,\(a0\),v12
++[ 	]+[0-9a-f]+:[ 	]+8cc55207[ 	]+vlxseg5ei16.v[ 	]+v4,\(a0\),v12,v0.t
++[ 	]+[0-9a-f]+:[ 	]+8ec55227[ 	]+vsxseg5ei16.v[ 	]+v4,\(a0\),v12
++[ 	]+[0-9a-f]+:[ 	]+8ec55227[ 	]+vsxseg5ei16.v[ 	]+v4,\(a0\),v12
++[ 	]+[0-9a-f]+:[ 	]+8cc55227[ 	]+vsxseg5ei16.v[ 	]+v4,\(a0\),v12,v0.t
++[ 	]+[0-9a-f]+:[ 	]+aec55207[ 	]+vlxseg6ei16.v[ 	]+v4,\(a0\),v12
++[ 	]+[0-9a-f]+:[ 	]+aec55207[ 	]+vlxseg6ei16.v[ 	]+v4,\(a0\),v12
++[ 	]+[0-9a-f]+:[ 	]+acc55207[ 	]+vlxseg6ei16.v[ 	]+v4,\(a0\),v12,v0.t
++[ 	]+[0-9a-f]+:[ 	]+aec55227[ 	]+vsxseg6ei16.v[ 	]+v4,\(a0\),v12
++[ 	]+[0-9a-f]+:[ 	]+aec55227[ 	]+vsxseg6ei16.v[ 	]+v4,\(a0\),v12
++[ 	]+[0-9a-f]+:[ 	]+acc55227[ 	]+vsxseg6ei16.v[ 	]+v4,\(a0\),v12,v0.t
++[ 	]+[0-9a-f]+:[ 	]+cec55207[ 	]+vlxseg7ei16.v[ 	]+v4,\(a0\),v12
++[ 	]+[0-9a-f]+:[ 	]+cec55207[ 	]+vlxseg7ei16.v[ 	]+v4,\(a0\),v12
++[ 	]+[0-9a-f]+:[ 	]+ccc55207[ 	]+vlxseg7ei16.v[ 	]+v4,\(a0\),v12,v0.t
++[ 	]+[0-9a-f]+:[ 	]+cec55227[ 	]+vsxseg7ei16.v[ 	]+v4,\(a0\),v12
++[ 	]+[0-9a-f]+:[ 	]+cec55227[ 	]+vsxseg7ei16.v[ 	]+v4,\(a0\),v12
++[ 	]+[0-9a-f]+:[ 	]+ccc55227[ 	]+vsxseg7ei16.v[ 	]+v4,\(a0\),v12,v0.t
++[ 	]+[0-9a-f]+:[ 	]+eec55207[ 	]+vlxseg8ei16.v[ 	]+v4,\(a0\),v12
++[ 	]+[0-9a-f]+:[ 	]+eec55207[ 	]+vlxseg8ei16.v[ 	]+v4,\(a0\),v12
++[ 	]+[0-9a-f]+:[ 	]+ecc55207[ 	]+vlxseg8ei16.v[ 	]+v4,\(a0\),v12,v0.t
++[ 	]+[0-9a-f]+:[ 	]+eec55227[ 	]+vsxseg8ei16.v[ 	]+v4,\(a0\),v12
++[ 	]+[0-9a-f]+:[ 	]+eec55227[ 	]+vsxseg8ei16.v[ 	]+v4,\(a0\),v12
++[ 	]+[0-9a-f]+:[ 	]+ecc55227[ 	]+vsxseg8ei16.v[ 	]+v4,\(a0\),v12,v0.t
++[ 	]+[0-9a-f]+:[ 	]+2ec56207[ 	]+vlxseg2ei32.v[ 	]+v4,\(a0\),v12
++[ 	]+[0-9a-f]+:[ 	]+2ec56207[ 	]+vlxseg2ei32.v[ 	]+v4,\(a0\),v12
++[ 	]+[0-9a-f]+:[ 	]+2cc56207[ 	]+vlxseg2ei32.v[ 	]+v4,\(a0\),v12,v0.t
++[ 	]+[0-9a-f]+:[ 	]+2ec56227[ 	]+vsxseg2ei32.v[ 	]+v4,\(a0\),v12
++[ 	]+[0-9a-f]+:[ 	]+2ec56227[ 	]+vsxseg2ei32.v[ 	]+v4,\(a0\),v12
++[ 	]+[0-9a-f]+:[ 	]+2cc56227[ 	]+vsxseg2ei32.v[ 	]+v4,\(a0\),v12,v0.t
++[ 	]+[0-9a-f]+:[ 	]+4ec56207[ 	]+vlxseg3ei32.v[ 	]+v4,\(a0\),v12
++[ 	]+[0-9a-f]+:[ 	]+4ec56207[ 	]+vlxseg3ei32.v[ 	]+v4,\(a0\),v12
++[ 	]+[0-9a-f]+:[ 	]+4cc56207[ 	]+vlxseg3ei32.v[ 	]+v4,\(a0\),v12,v0.t
++[ 	]+[0-9a-f]+:[ 	]+4ec56227[ 	]+vsxseg3ei32.v[ 	]+v4,\(a0\),v12
++[ 	]+[0-9a-f]+:[ 	]+4ec56227[ 	]+vsxseg3ei32.v[ 	]+v4,\(a0\),v12
++[ 	]+[0-9a-f]+:[ 	]+4cc56227[ 	]+vsxseg3ei32.v[ 	]+v4,\(a0\),v12,v0.t
++[ 	]+[0-9a-f]+:[ 	]+6ec56207[ 	]+vlxseg4ei32.v[ 	]+v4,\(a0\),v12
++[ 	]+[0-9a-f]+:[ 	]+6ec56207[ 	]+vlxseg4ei32.v[ 	]+v4,\(a0\),v12
++[ 	]+[0-9a-f]+:[ 	]+6cc56207[ 	]+vlxseg4ei32.v[ 	]+v4,\(a0\),v12,v0.t
++[ 	]+[0-9a-f]+:[ 	]+6ec56227[ 	]+vsxseg4ei32.v[ 	]+v4,\(a0\),v12
++[ 	]+[0-9a-f]+:[ 	]+6ec56227[ 	]+vsxseg4ei32.v[ 	]+v4,\(a0\),v12
++[ 	]+[0-9a-f]+:[ 	]+6cc56227[ 	]+vsxseg4ei32.v[ 	]+v4,\(a0\),v12,v0.t
++[ 	]+[0-9a-f]+:[ 	]+8ec56207[ 	]+vlxseg5ei32.v[ 	]+v4,\(a0\),v12
++[ 	]+[0-9a-f]+:[ 	]+8ec56207[ 	]+vlxseg5ei32.v[ 	]+v4,\(a0\),v12
++[ 	]+[0-9a-f]+:[ 	]+8cc56207[ 	]+vlxseg5ei32.v[ 	]+v4,\(a0\),v12,v0.t
++[ 	]+[0-9a-f]+:[ 	]+8ec56227[ 	]+vsxseg5ei32.v[ 	]+v4,\(a0\),v12
++[ 	]+[0-9a-f]+:[ 	]+8ec56227[ 	]+vsxseg5ei32.v[ 	]+v4,\(a0\),v12
++[ 	]+[0-9a-f]+:[ 	]+8cc56227[ 	]+vsxseg5ei32.v[ 	]+v4,\(a0\),v12,v0.t
++[ 	]+[0-9a-f]+:[ 	]+aec56207[ 	]+vlxseg6ei32.v[ 	]+v4,\(a0\),v12
++[ 	]+[0-9a-f]+:[ 	]+aec56207[ 	]+vlxseg6ei32.v[ 	]+v4,\(a0\),v12
++[ 	]+[0-9a-f]+:[ 	]+acc56207[ 	]+vlxseg6ei32.v[ 	]+v4,\(a0\),v12,v0.t
++[ 	]+[0-9a-f]+:[ 	]+aec56227[ 	]+vsxseg6ei32.v[ 	]+v4,\(a0\),v12
++[ 	]+[0-9a-f]+:[ 	]+aec56227[ 	]+vsxseg6ei32.v[ 	]+v4,\(a0\),v12
++[ 	]+[0-9a-f]+:[ 	]+acc56227[ 	]+vsxseg6ei32.v[ 	]+v4,\(a0\),v12,v0.t
++[ 	]+[0-9a-f]+:[ 	]+cec56207[ 	]+vlxseg7ei32.v[ 	]+v4,\(a0\),v12
++[ 	]+[0-9a-f]+:[ 	]+cec56207[ 	]+vlxseg7ei32.v[ 	]+v4,\(a0\),v12
++[ 	]+[0-9a-f]+:[ 	]+ccc56207[ 	]+vlxseg7ei32.v[ 	]+v4,\(a0\),v12,v0.t
++[ 	]+[0-9a-f]+:[ 	]+cec56227[ 	]+vsxseg7ei32.v[ 	]+v4,\(a0\),v12
++[ 	]+[0-9a-f]+:[ 	]+cec56227[ 	]+vsxseg7ei32.v[ 	]+v4,\(a0\),v12
++[ 	]+[0-9a-f]+:[ 	]+ccc56227[ 	]+vsxseg7ei32.v[ 	]+v4,\(a0\),v12,v0.t
++[ 	]+[0-9a-f]+:[ 	]+eec56207[ 	]+vlxseg8ei32.v[ 	]+v4,\(a0\),v12
++[ 	]+[0-9a-f]+:[ 	]+eec56207[ 	]+vlxseg8ei32.v[ 	]+v4,\(a0\),v12
++[ 	]+[0-9a-f]+:[ 	]+ecc56207[ 	]+vlxseg8ei32.v[ 	]+v4,\(a0\),v12,v0.t
++[ 	]+[0-9a-f]+:[ 	]+eec56227[ 	]+vsxseg8ei32.v[ 	]+v4,\(a0\),v12
++[ 	]+[0-9a-f]+:[ 	]+eec56227[ 	]+vsxseg8ei32.v[ 	]+v4,\(a0\),v12
++[ 	]+[0-9a-f]+:[ 	]+ecc56227[ 	]+vsxseg8ei32.v[ 	]+v4,\(a0\),v12,v0.t
++[ 	]+[0-9a-f]+:[ 	]+2ec57207[ 	]+vlxseg2ei64.v[ 	]+v4,\(a0\),v12
++[ 	]+[0-9a-f]+:[ 	]+2ec57207[ 	]+vlxseg2ei64.v[ 	]+v4,\(a0\),v12
++[ 	]+[0-9a-f]+:[ 	]+2cc57207[ 	]+vlxseg2ei64.v[ 	]+v4,\(a0\),v12,v0.t
++[ 	]+[0-9a-f]+:[ 	]+2ec57227[ 	]+vsxseg2ei64.v[ 	]+v4,\(a0\),v12
++[ 	]+[0-9a-f]+:[ 	]+2ec57227[ 	]+vsxseg2ei64.v[ 	]+v4,\(a0\),v12
++[ 	]+[0-9a-f]+:[ 	]+2cc57227[ 	]+vsxseg2ei64.v[ 	]+v4,\(a0\),v12,v0.t
++[ 	]+[0-9a-f]+:[ 	]+4ec57207[ 	]+vlxseg3ei64.v[ 	]+v4,\(a0\),v12
++[ 	]+[0-9a-f]+:[ 	]+4ec57207[ 	]+vlxseg3ei64.v[ 	]+v4,\(a0\),v12
++[ 	]+[0-9a-f]+:[ 	]+4cc57207[ 	]+vlxseg3ei64.v[ 	]+v4,\(a0\),v12,v0.t
++[ 	]+[0-9a-f]+:[ 	]+4ec57227[ 	]+vsxseg3ei64.v[ 	]+v4,\(a0\),v12
++[ 	]+[0-9a-f]+:[ 	]+4ec57227[ 	]+vsxseg3ei64.v[ 	]+v4,\(a0\),v12
++[ 	]+[0-9a-f]+:[ 	]+4cc57227[ 	]+vsxseg3ei64.v[ 	]+v4,\(a0\),v12,v0.t
++[ 	]+[0-9a-f]+:[ 	]+6ec57207[ 	]+vlxseg4ei64.v[ 	]+v4,\(a0\),v12
++[ 	]+[0-9a-f]+:[ 	]+6ec57207[ 	]+vlxseg4ei64.v[ 	]+v4,\(a0\),v12
++[ 	]+[0-9a-f]+:[ 	]+6cc57207[ 	]+vlxseg4ei64.v[ 	]+v4,\(a0\),v12,v0.t
++[ 	]+[0-9a-f]+:[ 	]+6ec57227[ 	]+vsxseg4ei64.v[ 	]+v4,\(a0\),v12
++[ 	]+[0-9a-f]+:[ 	]+6ec57227[ 	]+vsxseg4ei64.v[ 	]+v4,\(a0\),v12
++[ 	]+[0-9a-f]+:[ 	]+6cc57227[ 	]+vsxseg4ei64.v[ 	]+v4,\(a0\),v12,v0.t
++[ 	]+[0-9a-f]+:[ 	]+8ec57207[ 	]+vlxseg5ei64.v[ 	]+v4,\(a0\),v12
++[ 	]+[0-9a-f]+:[ 	]+8ec57207[ 	]+vlxseg5ei64.v[ 	]+v4,\(a0\),v12
++[ 	]+[0-9a-f]+:[ 	]+8cc57207[ 	]+vlxseg5ei64.v[ 	]+v4,\(a0\),v12,v0.t
++[ 	]+[0-9a-f]+:[ 	]+8ec57227[ 	]+vsxseg5ei64.v[ 	]+v4,\(a0\),v12
++[ 	]+[0-9a-f]+:[ 	]+8ec57227[ 	]+vsxseg5ei64.v[ 	]+v4,\(a0\),v12
++[ 	]+[0-9a-f]+:[ 	]+8cc57227[ 	]+vsxseg5ei64.v[ 	]+v4,\(a0\),v12,v0.t
++[ 	]+[0-9a-f]+:[ 	]+aec57207[ 	]+vlxseg6ei64.v[ 	]+v4,\(a0\),v12
++[ 	]+[0-9a-f]+:[ 	]+aec57207[ 	]+vlxseg6ei64.v[ 	]+v4,\(a0\),v12
++[ 	]+[0-9a-f]+:[ 	]+acc57207[ 	]+vlxseg6ei64.v[ 	]+v4,\(a0\),v12,v0.t
++[ 	]+[0-9a-f]+:[ 	]+aec57227[ 	]+vsxseg6ei64.v[ 	]+v4,\(a0\),v12
++[ 	]+[0-9a-f]+:[ 	]+aec57227[ 	]+vsxseg6ei64.v[ 	]+v4,\(a0\),v12
++[ 	]+[0-9a-f]+:[ 	]+acc57227[ 	]+vsxseg6ei64.v[ 	]+v4,\(a0\),v12,v0.t
++[ 	]+[0-9a-f]+:[ 	]+cec57207[ 	]+vlxseg7ei64.v[ 	]+v4,\(a0\),v12
++[ 	]+[0-9a-f]+:[ 	]+cec57207[ 	]+vlxseg7ei64.v[ 	]+v4,\(a0\),v12
++[ 	]+[0-9a-f]+:[ 	]+ccc57207[ 	]+vlxseg7ei64.v[ 	]+v4,\(a0\),v12,v0.t
++[ 	]+[0-9a-f]+:[ 	]+cec57227[ 	]+vsxseg7ei64.v[ 	]+v4,\(a0\),v12
++[ 	]+[0-9a-f]+:[ 	]+cec57227[ 	]+vsxseg7ei64.v[ 	]+v4,\(a0\),v12
++[ 	]+[0-9a-f]+:[ 	]+ccc57227[ 	]+vsxseg7ei64.v[ 	]+v4,\(a0\),v12,v0.t
++[ 	]+[0-9a-f]+:[ 	]+eec57207[ 	]+vlxseg8ei64.v[ 	]+v4,\(a0\),v12
++[ 	]+[0-9a-f]+:[ 	]+eec57207[ 	]+vlxseg8ei64.v[ 	]+v4,\(a0\),v12
++[ 	]+[0-9a-f]+:[ 	]+ecc57207[ 	]+vlxseg8ei64.v[ 	]+v4,\(a0\),v12,v0.t
++[ 	]+[0-9a-f]+:[ 	]+eec57227[ 	]+vsxseg8ei64.v[ 	]+v4,\(a0\),v12
++[ 	]+[0-9a-f]+:[ 	]+eec57227[ 	]+vsxseg8ei64.v[ 	]+v4,\(a0\),v12
++[ 	]+[0-9a-f]+:[ 	]+ecc57227[ 	]+vsxseg8ei64.v[ 	]+v4,\(a0\),v12,v0.t
++[ 	]+[0-9a-f]+:[ 	]+3ec50207[ 	]+vlxseg2ei128.v[ 	]+v4,\(a0\),v12
++[ 	]+[0-9a-f]+:[ 	]+3ec50207[ 	]+vlxseg2ei128.v[ 	]+v4,\(a0\),v12
++[ 	]+[0-9a-f]+:[ 	]+3cc50207[ 	]+vlxseg2ei128.v[ 	]+v4,\(a0\),v12,v0.t
++[ 	]+[0-9a-f]+:[ 	]+3ec50227[ 	]+vsxseg2ei128.v[ 	]+v4,\(a0\),v12
++[ 	]+[0-9a-f]+:[ 	]+3ec50227[ 	]+vsxseg2ei128.v[ 	]+v4,\(a0\),v12
++[ 	]+[0-9a-f]+:[ 	]+3cc50227[ 	]+vsxseg2ei128.v[ 	]+v4,\(a0\),v12,v0.t
++[ 	]+[0-9a-f]+:[ 	]+5ec50207[ 	]+vlxseg3ei128.v[ 	]+v4,\(a0\),v12
++[ 	]+[0-9a-f]+:[ 	]+5ec50207[ 	]+vlxseg3ei128.v[ 	]+v4,\(a0\),v12
++[ 	]+[0-9a-f]+:[ 	]+5cc50207[ 	]+vlxseg3ei128.v[ 	]+v4,\(a0\),v12,v0.t
++[ 	]+[0-9a-f]+:[ 	]+5ec50227[ 	]+vsxseg3ei128.v[ 	]+v4,\(a0\),v12
++[ 	]+[0-9a-f]+:[ 	]+5ec50227[ 	]+vsxseg3ei128.v[ 	]+v4,\(a0\),v12
++[ 	]+[0-9a-f]+:[ 	]+5cc50227[ 	]+vsxseg3ei128.v[ 	]+v4,\(a0\),v12,v0.t
++[ 	]+[0-9a-f]+:[ 	]+7ec50207[ 	]+vlxseg4ei128.v[ 	]+v4,\(a0\),v12
++[ 	]+[0-9a-f]+:[ 	]+7ec50207[ 	]+vlxseg4ei128.v[ 	]+v4,\(a0\),v12
++[ 	]+[0-9a-f]+:[ 	]+7cc50207[ 	]+vlxseg4ei128.v[ 	]+v4,\(a0\),v12,v0.t
++[ 	]+[0-9a-f]+:[ 	]+7ec50227[ 	]+vsxseg4ei128.v[ 	]+v4,\(a0\),v12
++[ 	]+[0-9a-f]+:[ 	]+7ec50227[ 	]+vsxseg4ei128.v[ 	]+v4,\(a0\),v12
++[ 	]+[0-9a-f]+:[ 	]+7cc50227[ 	]+vsxseg4ei128.v[ 	]+v4,\(a0\),v12,v0.t
++[ 	]+[0-9a-f]+:[ 	]+9ec50207[ 	]+vlxseg5ei128.v[ 	]+v4,\(a0\),v12
++[ 	]+[0-9a-f]+:[ 	]+9ec50207[ 	]+vlxseg5ei128.v[ 	]+v4,\(a0\),v12
++[ 	]+[0-9a-f]+:[ 	]+9cc50207[ 	]+vlxseg5ei128.v[ 	]+v4,\(a0\),v12,v0.t
++[ 	]+[0-9a-f]+:[ 	]+9ec50227[ 	]+vsxseg5ei128.v[ 	]+v4,\(a0\),v12
++[ 	]+[0-9a-f]+:[ 	]+9ec50227[ 	]+vsxseg5ei128.v[ 	]+v4,\(a0\),v12
++[ 	]+[0-9a-f]+:[ 	]+9cc50227[ 	]+vsxseg5ei128.v[ 	]+v4,\(a0\),v12,v0.t
++[ 	]+[0-9a-f]+:[ 	]+bec50207[ 	]+vlxseg6ei128.v[ 	]+v4,\(a0\),v12
++[ 	]+[0-9a-f]+:[ 	]+bec50207[ 	]+vlxseg6ei128.v[ 	]+v4,\(a0\),v12
++[ 	]+[0-9a-f]+:[ 	]+bcc50207[ 	]+vlxseg6ei128.v[ 	]+v4,\(a0\),v12,v0.t
++[ 	]+[0-9a-f]+:[ 	]+bec50227[ 	]+vsxseg6ei128.v[ 	]+v4,\(a0\),v12
++[ 	]+[0-9a-f]+:[ 	]+bec50227[ 	]+vsxseg6ei128.v[ 	]+v4,\(a0\),v12
++[ 	]+[0-9a-f]+:[ 	]+bcc50227[ 	]+vsxseg6ei128.v[ 	]+v4,\(a0\),v12,v0.t
++[ 	]+[0-9a-f]+:[ 	]+dec50207[ 	]+vlxseg7ei128.v[ 	]+v4,\(a0\),v12
++[ 	]+[0-9a-f]+:[ 	]+dec50207[ 	]+vlxseg7ei128.v[ 	]+v4,\(a0\),v12
++[ 	]+[0-9a-f]+:[ 	]+dcc50207[ 	]+vlxseg7ei128.v[ 	]+v4,\(a0\),v12,v0.t
++[ 	]+[0-9a-f]+:[ 	]+dec50227[ 	]+vsxseg7ei128.v[ 	]+v4,\(a0\),v12
++[ 	]+[0-9a-f]+:[ 	]+dec50227[ 	]+vsxseg7ei128.v[ 	]+v4,\(a0\),v12
++[ 	]+[0-9a-f]+:[ 	]+dcc50227[ 	]+vsxseg7ei128.v[ 	]+v4,\(a0\),v12,v0.t
++[ 	]+[0-9a-f]+:[ 	]+fec50207[ 	]+vlxseg8ei128.v[ 	]+v4,\(a0\),v12
++[ 	]+[0-9a-f]+:[ 	]+fec50207[ 	]+vlxseg8ei128.v[ 	]+v4,\(a0\),v12
++[ 	]+[0-9a-f]+:[ 	]+fcc50207[ 	]+vlxseg8ei128.v[ 	]+v4,\(a0\),v12,v0.t
++[ 	]+[0-9a-f]+:[ 	]+fec50227[ 	]+vsxseg8ei128.v[ 	]+v4,\(a0\),v12
++[ 	]+[0-9a-f]+:[ 	]+fec50227[ 	]+vsxseg8ei128.v[ 	]+v4,\(a0\),v12
++[ 	]+[0-9a-f]+:[ 	]+fcc50227[ 	]+vsxseg8ei128.v[ 	]+v4,\(a0\),v12,v0.t
++[ 	]+[0-9a-f]+:[ 	]+3ec55207[ 	]+vlxseg2ei256.v[ 	]+v4,\(a0\),v12
++[ 	]+[0-9a-f]+:[ 	]+3ec55207[ 	]+vlxseg2ei256.v[ 	]+v4,\(a0\),v12
++[ 	]+[0-9a-f]+:[ 	]+3cc55207[ 	]+vlxseg2ei256.v[ 	]+v4,\(a0\),v12,v0.t
++[ 	]+[0-9a-f]+:[ 	]+3ec55227[ 	]+vsxseg2ei256.v[ 	]+v4,\(a0\),v12
++[ 	]+[0-9a-f]+:[ 	]+3ec55227[ 	]+vsxseg2ei256.v[ 	]+v4,\(a0\),v12
++[ 	]+[0-9a-f]+:[ 	]+3cc55227[ 	]+vsxseg2ei256.v[ 	]+v4,\(a0\),v12,v0.t
++[ 	]+[0-9a-f]+:[ 	]+5ec55207[ 	]+vlxseg3ei256.v[ 	]+v4,\(a0\),v12
++[ 	]+[0-9a-f]+:[ 	]+5ec55207[ 	]+vlxseg3ei256.v[ 	]+v4,\(a0\),v12
++[ 	]+[0-9a-f]+:[ 	]+5cc55207[ 	]+vlxseg3ei256.v[ 	]+v4,\(a0\),v12,v0.t
++[ 	]+[0-9a-f]+:[ 	]+5ec55227[ 	]+vsxseg3ei256.v[ 	]+v4,\(a0\),v12
++[ 	]+[0-9a-f]+:[ 	]+5ec55227[ 	]+vsxseg3ei256.v[ 	]+v4,\(a0\),v12
++[ 	]+[0-9a-f]+:[ 	]+5cc55227[ 	]+vsxseg3ei256.v[ 	]+v4,\(a0\),v12,v0.t
++[ 	]+[0-9a-f]+:[ 	]+7ec55207[ 	]+vlxseg4ei256.v[ 	]+v4,\(a0\),v12
++[ 	]+[0-9a-f]+:[ 	]+7ec55207[ 	]+vlxseg4ei256.v[ 	]+v4,\(a0\),v12
++[ 	]+[0-9a-f]+:[ 	]+7cc55207[ 	]+vlxseg4ei256.v[ 	]+v4,\(a0\),v12,v0.t
++[ 	]+[0-9a-f]+:[ 	]+7ec55227[ 	]+vsxseg4ei256.v[ 	]+v4,\(a0\),v12
++[ 	]+[0-9a-f]+:[ 	]+7ec55227[ 	]+vsxseg4ei256.v[ 	]+v4,\(a0\),v12
++[ 	]+[0-9a-f]+:[ 	]+7cc55227[ 	]+vsxseg4ei256.v[ 	]+v4,\(a0\),v12,v0.t
++[ 	]+[0-9a-f]+:[ 	]+9ec55207[ 	]+vlxseg5ei256.v[ 	]+v4,\(a0\),v12
++[ 	]+[0-9a-f]+:[ 	]+9ec55207[ 	]+vlxseg5ei256.v[ 	]+v4,\(a0\),v12
++[ 	]+[0-9a-f]+:[ 	]+9cc55207[ 	]+vlxseg5ei256.v[ 	]+v4,\(a0\),v12,v0.t
++[ 	]+[0-9a-f]+:[ 	]+9ec55227[ 	]+vsxseg5ei256.v[ 	]+v4,\(a0\),v12
++[ 	]+[0-9a-f]+:[ 	]+9ec55227[ 	]+vsxseg5ei256.v[ 	]+v4,\(a0\),v12
++[ 	]+[0-9a-f]+:[ 	]+9cc55227[ 	]+vsxseg5ei256.v[ 	]+v4,\(a0\),v12,v0.t
++[ 	]+[0-9a-f]+:[ 	]+bec55207[ 	]+vlxseg6ei256.v[ 	]+v4,\(a0\),v12
++[ 	]+[0-9a-f]+:[ 	]+bec55207[ 	]+vlxseg6ei256.v[ 	]+v4,\(a0\),v12
++[ 	]+[0-9a-f]+:[ 	]+bcc55207[ 	]+vlxseg6ei256.v[ 	]+v4,\(a0\),v12,v0.t
++[ 	]+[0-9a-f]+:[ 	]+bec55227[ 	]+vsxseg6ei256.v[ 	]+v4,\(a0\),v12
++[ 	]+[0-9a-f]+:[ 	]+bec55227[ 	]+vsxseg6ei256.v[ 	]+v4,\(a0\),v12
++[ 	]+[0-9a-f]+:[ 	]+bcc55227[ 	]+vsxseg6ei256.v[ 	]+v4,\(a0\),v12,v0.t
++[ 	]+[0-9a-f]+:[ 	]+dec55207[ 	]+vlxseg7ei256.v[ 	]+v4,\(a0\),v12
++[ 	]+[0-9a-f]+:[ 	]+dec55207[ 	]+vlxseg7ei256.v[ 	]+v4,\(a0\),v12
++[ 	]+[0-9a-f]+:[ 	]+dcc55207[ 	]+vlxseg7ei256.v[ 	]+v4,\(a0\),v12,v0.t
++[ 	]+[0-9a-f]+:[ 	]+dec55227[ 	]+vsxseg7ei256.v[ 	]+v4,\(a0\),v12
++[ 	]+[0-9a-f]+:[ 	]+dec55227[ 	]+vsxseg7ei256.v[ 	]+v4,\(a0\),v12
++[ 	]+[0-9a-f]+:[ 	]+dcc55227[ 	]+vsxseg7ei256.v[ 	]+v4,\(a0\),v12,v0.t
++[ 	]+[0-9a-f]+:[ 	]+fec55207[ 	]+vlxseg8ei256.v[ 	]+v4,\(a0\),v12
++[ 	]+[0-9a-f]+:[ 	]+fec55207[ 	]+vlxseg8ei256.v[ 	]+v4,\(a0\),v12
++[ 	]+[0-9a-f]+:[ 	]+fcc55207[ 	]+vlxseg8ei256.v[ 	]+v4,\(a0\),v12,v0.t
++[ 	]+[0-9a-f]+:[ 	]+fec55227[ 	]+vsxseg8ei256.v[ 	]+v4,\(a0\),v12
++[ 	]+[0-9a-f]+:[ 	]+fec55227[ 	]+vsxseg8ei256.v[ 	]+v4,\(a0\),v12
++[ 	]+[0-9a-f]+:[ 	]+fcc55227[ 	]+vsxseg8ei256.v[ 	]+v4,\(a0\),v12,v0.t
++[ 	]+[0-9a-f]+:[ 	]+3ec56207[ 	]+vlxseg2ei512.v[ 	]+v4,\(a0\),v12
++[ 	]+[0-9a-f]+:[ 	]+3ec56207[ 	]+vlxseg2ei512.v[ 	]+v4,\(a0\),v12
++[ 	]+[0-9a-f]+:[ 	]+3cc56207[ 	]+vlxseg2ei512.v[ 	]+v4,\(a0\),v12,v0.t
++[ 	]+[0-9a-f]+:[ 	]+3ec56227[ 	]+vsxseg2ei512.v[ 	]+v4,\(a0\),v12
++[ 	]+[0-9a-f]+:[ 	]+3ec56227[ 	]+vsxseg2ei512.v[ 	]+v4,\(a0\),v12
++[ 	]+[0-9a-f]+:[ 	]+3cc56227[ 	]+vsxseg2ei512.v[ 	]+v4,\(a0\),v12,v0.t
++[ 	]+[0-9a-f]+:[ 	]+5ec56207[ 	]+vlxseg3ei512.v[ 	]+v4,\(a0\),v12
++[ 	]+[0-9a-f]+:[ 	]+5ec56207[ 	]+vlxseg3ei512.v[ 	]+v4,\(a0\),v12
++[ 	]+[0-9a-f]+:[ 	]+5cc56207[ 	]+vlxseg3ei512.v[ 	]+v4,\(a0\),v12,v0.t
++[ 	]+[0-9a-f]+:[ 	]+5ec56227[ 	]+vsxseg3ei512.v[ 	]+v4,\(a0\),v12
++[ 	]+[0-9a-f]+:[ 	]+5ec56227[ 	]+vsxseg3ei512.v[ 	]+v4,\(a0\),v12
++[ 	]+[0-9a-f]+:[ 	]+5cc56227[ 	]+vsxseg3ei512.v[ 	]+v4,\(a0\),v12,v0.t
++[ 	]+[0-9a-f]+:[ 	]+7ec56207[ 	]+vlxseg4ei512.v[ 	]+v4,\(a0\),v12
++[ 	]+[0-9a-f]+:[ 	]+7ec56207[ 	]+vlxseg4ei512.v[ 	]+v4,\(a0\),v12
++[ 	]+[0-9a-f]+:[ 	]+7cc56207[ 	]+vlxseg4ei512.v[ 	]+v4,\(a0\),v12,v0.t
++[ 	]+[0-9a-f]+:[ 	]+7ec56227[ 	]+vsxseg4ei512.v[ 	]+v4,\(a0\),v12
++[ 	]+[0-9a-f]+:[ 	]+7ec56227[ 	]+vsxseg4ei512.v[ 	]+v4,\(a0\),v12
++[ 	]+[0-9a-f]+:[ 	]+7cc56227[ 	]+vsxseg4ei512.v[ 	]+v4,\(a0\),v12,v0.t
++[ 	]+[0-9a-f]+:[ 	]+9ec56207[ 	]+vlxseg5ei512.v[ 	]+v4,\(a0\),v12
++[ 	]+[0-9a-f]+:[ 	]+9ec56207[ 	]+vlxseg5ei512.v[ 	]+v4,\(a0\),v12
++[ 	]+[0-9a-f]+:[ 	]+9cc56207[ 	]+vlxseg5ei512.v[ 	]+v4,\(a0\),v12,v0.t
++[ 	]+[0-9a-f]+:[ 	]+9ec56227[ 	]+vsxseg5ei512.v[ 	]+v4,\(a0\),v12
++[ 	]+[0-9a-f]+:[ 	]+9ec56227[ 	]+vsxseg5ei512.v[ 	]+v4,\(a0\),v12
++[ 	]+[0-9a-f]+:[ 	]+9cc56227[ 	]+vsxseg5ei512.v[ 	]+v4,\(a0\),v12,v0.t
++[ 	]+[0-9a-f]+:[ 	]+bec56207[ 	]+vlxseg6ei512.v[ 	]+v4,\(a0\),v12
++[ 	]+[0-9a-f]+:[ 	]+bec56207[ 	]+vlxseg6ei512.v[ 	]+v4,\(a0\),v12
++[ 	]+[0-9a-f]+:[ 	]+bcc56207[ 	]+vlxseg6ei512.v[ 	]+v4,\(a0\),v12,v0.t
++[ 	]+[0-9a-f]+:[ 	]+bec56227[ 	]+vsxseg6ei512.v[ 	]+v4,\(a0\),v12
++[ 	]+[0-9a-f]+:[ 	]+bec56227[ 	]+vsxseg6ei512.v[ 	]+v4,\(a0\),v12
++[ 	]+[0-9a-f]+:[ 	]+bcc56227[ 	]+vsxseg6ei512.v[ 	]+v4,\(a0\),v12,v0.t
++[ 	]+[0-9a-f]+:[ 	]+dec56207[ 	]+vlxseg7ei512.v[ 	]+v4,\(a0\),v12
++[ 	]+[0-9a-f]+:[ 	]+dec56207[ 	]+vlxseg7ei512.v[ 	]+v4,\(a0\),v12
++[ 	]+[0-9a-f]+:[ 	]+dcc56207[ 	]+vlxseg7ei512.v[ 	]+v4,\(a0\),v12,v0.t
++[ 	]+[0-9a-f]+:[ 	]+dec56227[ 	]+vsxseg7ei512.v[ 	]+v4,\(a0\),v12
++[ 	]+[0-9a-f]+:[ 	]+dec56227[ 	]+vsxseg7ei512.v[ 	]+v4,\(a0\),v12
++[ 	]+[0-9a-f]+:[ 	]+dcc56227[ 	]+vsxseg7ei512.v[ 	]+v4,\(a0\),v12,v0.t
++[ 	]+[0-9a-f]+:[ 	]+fec56207[ 	]+vlxseg8ei512.v[ 	]+v4,\(a0\),v12
++[ 	]+[0-9a-f]+:[ 	]+fec56207[ 	]+vlxseg8ei512.v[ 	]+v4,\(a0\),v12
++[ 	]+[0-9a-f]+:[ 	]+fcc56207[ 	]+vlxseg8ei512.v[ 	]+v4,\(a0\),v12,v0.t
++[ 	]+[0-9a-f]+:[ 	]+fec56227[ 	]+vsxseg8ei512.v[ 	]+v4,\(a0\),v12
++[ 	]+[0-9a-f]+:[ 	]+fec56227[ 	]+vsxseg8ei512.v[ 	]+v4,\(a0\),v12
++[ 	]+[0-9a-f]+:[ 	]+fcc56227[ 	]+vsxseg8ei512.v[ 	]+v4,\(a0\),v12,v0.t
++[ 	]+[0-9a-f]+:[ 	]+3ec57207[ 	]+vlxseg2ei1024.v[ 	]+v4,\(a0\),v12
++[ 	]+[0-9a-f]+:[ 	]+3ec57207[ 	]+vlxseg2ei1024.v[ 	]+v4,\(a0\),v12
++[ 	]+[0-9a-f]+:[ 	]+3cc57207[ 	]+vlxseg2ei1024.v[ 	]+v4,\(a0\),v12,v0.t
++[ 	]+[0-9a-f]+:[ 	]+3ec57227[ 	]+vsxseg2ei1024.v[ 	]+v4,\(a0\),v12
++[ 	]+[0-9a-f]+:[ 	]+3ec57227[ 	]+vsxseg2ei1024.v[ 	]+v4,\(a0\),v12
++[ 	]+[0-9a-f]+:[ 	]+3cc57227[ 	]+vsxseg2ei1024.v[ 	]+v4,\(a0\),v12,v0.t
++[ 	]+[0-9a-f]+:[ 	]+5ec57207[ 	]+vlxseg3ei1024.v[ 	]+v4,\(a0\),v12
++[ 	]+[0-9a-f]+:[ 	]+5ec57207[ 	]+vlxseg3ei1024.v[ 	]+v4,\(a0\),v12
++[ 	]+[0-9a-f]+:[ 	]+5cc57207[ 	]+vlxseg3ei1024.v[ 	]+v4,\(a0\),v12,v0.t
++[ 	]+[0-9a-f]+:[ 	]+5ec57227[ 	]+vsxseg3ei1024.v[ 	]+v4,\(a0\),v12
++[ 	]+[0-9a-f]+:[ 	]+5ec57227[ 	]+vsxseg3ei1024.v[ 	]+v4,\(a0\),v12
++[ 	]+[0-9a-f]+:[ 	]+5cc57227[ 	]+vsxseg3ei1024.v[ 	]+v4,\(a0\),v12,v0.t
++[ 	]+[0-9a-f]+:[ 	]+7ec57207[ 	]+vlxseg4ei1024.v[ 	]+v4,\(a0\),v12
++[ 	]+[0-9a-f]+:[ 	]+7ec57207[ 	]+vlxseg4ei1024.v[ 	]+v4,\(a0\),v12
++[ 	]+[0-9a-f]+:[ 	]+7cc57207[ 	]+vlxseg4ei1024.v[ 	]+v4,\(a0\),v12,v0.t
++[ 	]+[0-9a-f]+:[ 	]+7ec57227[ 	]+vsxseg4ei1024.v[ 	]+v4,\(a0\),v12
++[ 	]+[0-9a-f]+:[ 	]+7ec57227[ 	]+vsxseg4ei1024.v[ 	]+v4,\(a0\),v12
++[ 	]+[0-9a-f]+:[ 	]+7cc57227[ 	]+vsxseg4ei1024.v[ 	]+v4,\(a0\),v12,v0.t
++[ 	]+[0-9a-f]+:[ 	]+9ec57207[ 	]+vlxseg5ei1024.v[ 	]+v4,\(a0\),v12
++[ 	]+[0-9a-f]+:[ 	]+9ec57207[ 	]+vlxseg5ei1024.v[ 	]+v4,\(a0\),v12
++[ 	]+[0-9a-f]+:[ 	]+9cc57207[ 	]+vlxseg5ei1024.v[ 	]+v4,\(a0\),v12,v0.t
++[ 	]+[0-9a-f]+:[ 	]+9ec57227[ 	]+vsxseg5ei1024.v[ 	]+v4,\(a0\),v12
++[ 	]+[0-9a-f]+:[ 	]+9ec57227[ 	]+vsxseg5ei1024.v[ 	]+v4,\(a0\),v12
++[ 	]+[0-9a-f]+:[ 	]+9cc57227[ 	]+vsxseg5ei1024.v[ 	]+v4,\(a0\),v12,v0.t
++[ 	]+[0-9a-f]+:[ 	]+bec57207[ 	]+vlxseg6ei1024.v[ 	]+v4,\(a0\),v12
++[ 	]+[0-9a-f]+:[ 	]+bec57207[ 	]+vlxseg6ei1024.v[ 	]+v4,\(a0\),v12
++[ 	]+[0-9a-f]+:[ 	]+bcc57207[ 	]+vlxseg6ei1024.v[ 	]+v4,\(a0\),v12,v0.t
++[ 	]+[0-9a-f]+:[ 	]+bec57227[ 	]+vsxseg6ei1024.v[ 	]+v4,\(a0\),v12
++[ 	]+[0-9a-f]+:[ 	]+bec57227[ 	]+vsxseg6ei1024.v[ 	]+v4,\(a0\),v12
++[ 	]+[0-9a-f]+:[ 	]+bcc57227[ 	]+vsxseg6ei1024.v[ 	]+v4,\(a0\),v12,v0.t
++[ 	]+[0-9a-f]+:[ 	]+dec57207[ 	]+vlxseg7ei1024.v[ 	]+v4,\(a0\),v12
++[ 	]+[0-9a-f]+:[ 	]+dec57207[ 	]+vlxseg7ei1024.v[ 	]+v4,\(a0\),v12
++[ 	]+[0-9a-f]+:[ 	]+dcc57207[ 	]+vlxseg7ei1024.v[ 	]+v4,\(a0\),v12,v0.t
++[ 	]+[0-9a-f]+:[ 	]+dec57227[ 	]+vsxseg7ei1024.v[ 	]+v4,\(a0\),v12
++[ 	]+[0-9a-f]+:[ 	]+dec57227[ 	]+vsxseg7ei1024.v[ 	]+v4,\(a0\),v12
++[ 	]+[0-9a-f]+:[ 	]+dcc57227[ 	]+vsxseg7ei1024.v[ 	]+v4,\(a0\),v12,v0.t
++[ 	]+[0-9a-f]+:[ 	]+fec57207[ 	]+vlxseg8ei1024.v[ 	]+v4,\(a0\),v12
++[ 	]+[0-9a-f]+:[ 	]+fec57207[ 	]+vlxseg8ei1024.v[ 	]+v4,\(a0\),v12
++[ 	]+[0-9a-f]+:[ 	]+fcc57207[ 	]+vlxseg8ei1024.v[ 	]+v4,\(a0\),v12,v0.t
++[ 	]+[0-9a-f]+:[ 	]+fec57227[ 	]+vsxseg8ei1024.v[ 	]+v4,\(a0\),v12
++[ 	]+[0-9a-f]+:[ 	]+fec57227[ 	]+vsxseg8ei1024.v[ 	]+v4,\(a0\),v12
++[ 	]+[0-9a-f]+:[ 	]+fcc57227[ 	]+vsxseg8ei1024.v[ 	]+v4,\(a0\),v12,v0.t
++[ 	]+[0-9a-f]+:[ 	]+23050207[ 	]+vlseg2e8ff.v[ 	]+v4,\(a0\)
++[ 	]+[0-9a-f]+:[ 	]+23050207[ 	]+vlseg2e8ff.v[ 	]+v4,\(a0\)
++[ 	]+[0-9a-f]+:[ 	]+21050207[ 	]+vlseg2e8ff.v[ 	]+v4,\(a0\),v0.t
++[ 	]+[0-9a-f]+:[ 	]+43050207[ 	]+vlseg3e8ff.v[ 	]+v4,\(a0\)
++[ 	]+[0-9a-f]+:[ 	]+43050207[ 	]+vlseg3e8ff.v[ 	]+v4,\(a0\)
++[ 	]+[0-9a-f]+:[ 	]+41050207[ 	]+vlseg3e8ff.v[ 	]+v4,\(a0\),v0.t
++[ 	]+[0-9a-f]+:[ 	]+63050207[ 	]+vlseg4e8ff.v[ 	]+v4,\(a0\)
++[ 	]+[0-9a-f]+:[ 	]+63050207[ 	]+vlseg4e8ff.v[ 	]+v4,\(a0\)
++[ 	]+[0-9a-f]+:[ 	]+61050207[ 	]+vlseg4e8ff.v[ 	]+v4,\(a0\),v0.t
++[ 	]+[0-9a-f]+:[ 	]+83050207[ 	]+vlseg5e8ff.v[ 	]+v4,\(a0\)
++[ 	]+[0-9a-f]+:[ 	]+83050207[ 	]+vlseg5e8ff.v[ 	]+v4,\(a0\)
++[ 	]+[0-9a-f]+:[ 	]+81050207[ 	]+vlseg5e8ff.v[ 	]+v4,\(a0\),v0.t
++[ 	]+[0-9a-f]+:[ 	]+a3050207[ 	]+vlseg6e8ff.v[ 	]+v4,\(a0\)
++[ 	]+[0-9a-f]+:[ 	]+a3050207[ 	]+vlseg6e8ff.v[ 	]+v4,\(a0\)
++[ 	]+[0-9a-f]+:[ 	]+a1050207[ 	]+vlseg6e8ff.v[ 	]+v4,\(a0\),v0.t
++[ 	]+[0-9a-f]+:[ 	]+c3050207[ 	]+vlseg7e8ff.v[ 	]+v4,\(a0\)
++[ 	]+[0-9a-f]+:[ 	]+c3050207[ 	]+vlseg7e8ff.v[ 	]+v4,\(a0\)
++[ 	]+[0-9a-f]+:[ 	]+c1050207[ 	]+vlseg7e8ff.v[ 	]+v4,\(a0\),v0.t
++[ 	]+[0-9a-f]+:[ 	]+e3050207[ 	]+vlseg8e8ff.v[ 	]+v4,\(a0\)
++[ 	]+[0-9a-f]+:[ 	]+e3050207[ 	]+vlseg8e8ff.v[ 	]+v4,\(a0\)
++[ 	]+[0-9a-f]+:[ 	]+e1050207[ 	]+vlseg8e8ff.v[ 	]+v4,\(a0\),v0.t
++[ 	]+[0-9a-f]+:[ 	]+23055207[ 	]+vlseg2e16ff.v[ 	]+v4,\(a0\)
++[ 	]+[0-9a-f]+:[ 	]+23055207[ 	]+vlseg2e16ff.v[ 	]+v4,\(a0\)
++[ 	]+[0-9a-f]+:[ 	]+21055207[ 	]+vlseg2e16ff.v[ 	]+v4,\(a0\),v0.t
++[ 	]+[0-9a-f]+:[ 	]+43055207[ 	]+vlseg3e16ff.v[ 	]+v4,\(a0\)
++[ 	]+[0-9a-f]+:[ 	]+43055207[ 	]+vlseg3e16ff.v[ 	]+v4,\(a0\)
++[ 	]+[0-9a-f]+:[ 	]+41055207[ 	]+vlseg3e16ff.v[ 	]+v4,\(a0\),v0.t
++[ 	]+[0-9a-f]+:[ 	]+63055207[ 	]+vlseg4e16ff.v[ 	]+v4,\(a0\)
++[ 	]+[0-9a-f]+:[ 	]+63055207[ 	]+vlseg4e16ff.v[ 	]+v4,\(a0\)
++[ 	]+[0-9a-f]+:[ 	]+61055207[ 	]+vlseg4e16ff.v[ 	]+v4,\(a0\),v0.t
++[ 	]+[0-9a-f]+:[ 	]+83055207[ 	]+vlseg5e16ff.v[ 	]+v4,\(a0\)
++[ 	]+[0-9a-f]+:[ 	]+83055207[ 	]+vlseg5e16ff.v[ 	]+v4,\(a0\)
++[ 	]+[0-9a-f]+:[ 	]+81055207[ 	]+vlseg5e16ff.v[ 	]+v4,\(a0\),v0.t
++[ 	]+[0-9a-f]+:[ 	]+a3055207[ 	]+vlseg6e16ff.v[ 	]+v4,\(a0\)
++[ 	]+[0-9a-f]+:[ 	]+a3055207[ 	]+vlseg6e16ff.v[ 	]+v4,\(a0\)
++[ 	]+[0-9a-f]+:[ 	]+a1055207[ 	]+vlseg6e16ff.v[ 	]+v4,\(a0\),v0.t
++[ 	]+[0-9a-f]+:[ 	]+c3055207[ 	]+vlseg7e16ff.v[ 	]+v4,\(a0\)
++[ 	]+[0-9a-f]+:[ 	]+c3055207[ 	]+vlseg7e16ff.v[ 	]+v4,\(a0\)
++[ 	]+[0-9a-f]+:[ 	]+c1055207[ 	]+vlseg7e16ff.v[ 	]+v4,\(a0\),v0.t
++[ 	]+[0-9a-f]+:[ 	]+e3055207[ 	]+vlseg8e16ff.v[ 	]+v4,\(a0\)
++[ 	]+[0-9a-f]+:[ 	]+e3055207[ 	]+vlseg8e16ff.v[ 	]+v4,\(a0\)
++[ 	]+[0-9a-f]+:[ 	]+e1055207[ 	]+vlseg8e16ff.v[ 	]+v4,\(a0\),v0.t
++[ 	]+[0-9a-f]+:[ 	]+23056207[ 	]+vlseg2e32ff.v[ 	]+v4,\(a0\)
++[ 	]+[0-9a-f]+:[ 	]+23056207[ 	]+vlseg2e32ff.v[ 	]+v4,\(a0\)
++[ 	]+[0-9a-f]+:[ 	]+21056207[ 	]+vlseg2e32ff.v[ 	]+v4,\(a0\),v0.t
++[ 	]+[0-9a-f]+:[ 	]+43056207[ 	]+vlseg3e32ff.v[ 	]+v4,\(a0\)
++[ 	]+[0-9a-f]+:[ 	]+43056207[ 	]+vlseg3e32ff.v[ 	]+v4,\(a0\)
++[ 	]+[0-9a-f]+:[ 	]+41056207[ 	]+vlseg3e32ff.v[ 	]+v4,\(a0\),v0.t
++[ 	]+[0-9a-f]+:[ 	]+63056207[ 	]+vlseg4e32ff.v[ 	]+v4,\(a0\)
++[ 	]+[0-9a-f]+:[ 	]+63056207[ 	]+vlseg4e32ff.v[ 	]+v4,\(a0\)
++[ 	]+[0-9a-f]+:[ 	]+61056207[ 	]+vlseg4e32ff.v[ 	]+v4,\(a0\),v0.t
++[ 	]+[0-9a-f]+:[ 	]+83056207[ 	]+vlseg5e32ff.v[ 	]+v4,\(a0\)
++[ 	]+[0-9a-f]+:[ 	]+83056207[ 	]+vlseg5e32ff.v[ 	]+v4,\(a0\)
++[ 	]+[0-9a-f]+:[ 	]+81056207[ 	]+vlseg5e32ff.v[ 	]+v4,\(a0\),v0.t
++[ 	]+[0-9a-f]+:[ 	]+a3056207[ 	]+vlseg6e32ff.v[ 	]+v4,\(a0\)
++[ 	]+[0-9a-f]+:[ 	]+a3056207[ 	]+vlseg6e32ff.v[ 	]+v4,\(a0\)
++[ 	]+[0-9a-f]+:[ 	]+a1056207[ 	]+vlseg6e32ff.v[ 	]+v4,\(a0\),v0.t
++[ 	]+[0-9a-f]+:[ 	]+c3056207[ 	]+vlseg7e32ff.v[ 	]+v4,\(a0\)
++[ 	]+[0-9a-f]+:[ 	]+c3056207[ 	]+vlseg7e32ff.v[ 	]+v4,\(a0\)
++[ 	]+[0-9a-f]+:[ 	]+c1056207[ 	]+vlseg7e32ff.v[ 	]+v4,\(a0\),v0.t
++[ 	]+[0-9a-f]+:[ 	]+e3056207[ 	]+vlseg8e32ff.v[ 	]+v4,\(a0\)
++[ 	]+[0-9a-f]+:[ 	]+e3056207[ 	]+vlseg8e32ff.v[ 	]+v4,\(a0\)
++[ 	]+[0-9a-f]+:[ 	]+e1056207[ 	]+vlseg8e32ff.v[ 	]+v4,\(a0\),v0.t
++[ 	]+[0-9a-f]+:[ 	]+23057207[ 	]+vlseg2e64ff.v[ 	]+v4,\(a0\)
++[ 	]+[0-9a-f]+:[ 	]+23057207[ 	]+vlseg2e64ff.v[ 	]+v4,\(a0\)
++[ 	]+[0-9a-f]+:[ 	]+21057207[ 	]+vlseg2e64ff.v[ 	]+v4,\(a0\),v0.t
++[ 	]+[0-9a-f]+:[ 	]+43057207[ 	]+vlseg3e64ff.v[ 	]+v4,\(a0\)
++[ 	]+[0-9a-f]+:[ 	]+43057207[ 	]+vlseg3e64ff.v[ 	]+v4,\(a0\)
++[ 	]+[0-9a-f]+:[ 	]+41057207[ 	]+vlseg3e64ff.v[ 	]+v4,\(a0\),v0.t
++[ 	]+[0-9a-f]+:[ 	]+63057207[ 	]+vlseg4e64ff.v[ 	]+v4,\(a0\)
++[ 	]+[0-9a-f]+:[ 	]+63057207[ 	]+vlseg4e64ff.v[ 	]+v4,\(a0\)
++[ 	]+[0-9a-f]+:[ 	]+61057207[ 	]+vlseg4e64ff.v[ 	]+v4,\(a0\),v0.t
++[ 	]+[0-9a-f]+:[ 	]+83057207[ 	]+vlseg5e64ff.v[ 	]+v4,\(a0\)
++[ 	]+[0-9a-f]+:[ 	]+83057207[ 	]+vlseg5e64ff.v[ 	]+v4,\(a0\)
++[ 	]+[0-9a-f]+:[ 	]+81057207[ 	]+vlseg5e64ff.v[ 	]+v4,\(a0\),v0.t
++[ 	]+[0-9a-f]+:[ 	]+a3057207[ 	]+vlseg6e64ff.v[ 	]+v4,\(a0\)
++[ 	]+[0-9a-f]+:[ 	]+a3057207[ 	]+vlseg6e64ff.v[ 	]+v4,\(a0\)
++[ 	]+[0-9a-f]+:[ 	]+a1057207[ 	]+vlseg6e64ff.v[ 	]+v4,\(a0\),v0.t
++[ 	]+[0-9a-f]+:[ 	]+c3057207[ 	]+vlseg7e64ff.v[ 	]+v4,\(a0\)
++[ 	]+[0-9a-f]+:[ 	]+c3057207[ 	]+vlseg7e64ff.v[ 	]+v4,\(a0\)
++[ 	]+[0-9a-f]+:[ 	]+c1057207[ 	]+vlseg7e64ff.v[ 	]+v4,\(a0\),v0.t
++[ 	]+[0-9a-f]+:[ 	]+e3057207[ 	]+vlseg8e64ff.v[ 	]+v4,\(a0\)
++[ 	]+[0-9a-f]+:[ 	]+e3057207[ 	]+vlseg8e64ff.v[ 	]+v4,\(a0\)
++[ 	]+[0-9a-f]+:[ 	]+e1057207[ 	]+vlseg8e64ff.v[ 	]+v4,\(a0\),v0.t
++[ 	]+[0-9a-f]+:[ 	]+33050207[ 	]+vlseg2e128ff.v[ 	]+v4,\(a0\)
++[ 	]+[0-9a-f]+:[ 	]+33050207[ 	]+vlseg2e128ff.v[ 	]+v4,\(a0\)
++[ 	]+[0-9a-f]+:[ 	]+31050207[ 	]+vlseg2e128ff.v[ 	]+v4,\(a0\),v0.t
++[ 	]+[0-9a-f]+:[ 	]+53050207[ 	]+vlseg3e128ff.v[ 	]+v4,\(a0\)
++[ 	]+[0-9a-f]+:[ 	]+53050207[ 	]+vlseg3e128ff.v[ 	]+v4,\(a0\)
++[ 	]+[0-9a-f]+:[ 	]+51050207[ 	]+vlseg3e128ff.v[ 	]+v4,\(a0\),v0.t
++[ 	]+[0-9a-f]+:[ 	]+73050207[ 	]+vlseg4e128ff.v[ 	]+v4,\(a0\)
++[ 	]+[0-9a-f]+:[ 	]+73050207[ 	]+vlseg4e128ff.v[ 	]+v4,\(a0\)
++[ 	]+[0-9a-f]+:[ 	]+71050207[ 	]+vlseg4e128ff.v[ 	]+v4,\(a0\),v0.t
++[ 	]+[0-9a-f]+:[ 	]+93050207[ 	]+vlseg5e128ff.v[ 	]+v4,\(a0\)
++[ 	]+[0-9a-f]+:[ 	]+93050207[ 	]+vlseg5e128ff.v[ 	]+v4,\(a0\)
++[ 	]+[0-9a-f]+:[ 	]+91050207[ 	]+vlseg5e128ff.v[ 	]+v4,\(a0\),v0.t
++[ 	]+[0-9a-f]+:[ 	]+b3050207[ 	]+vlseg6e128ff.v[ 	]+v4,\(a0\)
++[ 	]+[0-9a-f]+:[ 	]+b3050207[ 	]+vlseg6e128ff.v[ 	]+v4,\(a0\)
++[ 	]+[0-9a-f]+:[ 	]+b1050207[ 	]+vlseg6e128ff.v[ 	]+v4,\(a0\),v0.t
++[ 	]+[0-9a-f]+:[ 	]+d3050207[ 	]+vlseg7e128ff.v[ 	]+v4,\(a0\)
++[ 	]+[0-9a-f]+:[ 	]+d3050207[ 	]+vlseg7e128ff.v[ 	]+v4,\(a0\)
++[ 	]+[0-9a-f]+:[ 	]+d1050207[ 	]+vlseg7e128ff.v[ 	]+v4,\(a0\),v0.t
++[ 	]+[0-9a-f]+:[ 	]+f3050207[ 	]+vlseg8e128ff.v[ 	]+v4,\(a0\)
++[ 	]+[0-9a-f]+:[ 	]+f3050207[ 	]+vlseg8e128ff.v[ 	]+v4,\(a0\)
++[ 	]+[0-9a-f]+:[ 	]+f1050207[ 	]+vlseg8e128ff.v[ 	]+v4,\(a0\),v0.t
++[ 	]+[0-9a-f]+:[ 	]+33055207[ 	]+vlseg2e256ff.v[ 	]+v4,\(a0\)
++[ 	]+[0-9a-f]+:[ 	]+33055207[ 	]+vlseg2e256ff.v[ 	]+v4,\(a0\)
++[ 	]+[0-9a-f]+:[ 	]+31055207[ 	]+vlseg2e256ff.v[ 	]+v4,\(a0\),v0.t
++[ 	]+[0-9a-f]+:[ 	]+53055207[ 	]+vlseg3e256ff.v[ 	]+v4,\(a0\)
++[ 	]+[0-9a-f]+:[ 	]+53055207[ 	]+vlseg3e256ff.v[ 	]+v4,\(a0\)
++[ 	]+[0-9a-f]+:[ 	]+51055207[ 	]+vlseg3e256ff.v[ 	]+v4,\(a0\),v0.t
++[ 	]+[0-9a-f]+:[ 	]+73055207[ 	]+vlseg4e256ff.v[ 	]+v4,\(a0\)
++[ 	]+[0-9a-f]+:[ 	]+73055207[ 	]+vlseg4e256ff.v[ 	]+v4,\(a0\)
++[ 	]+[0-9a-f]+:[ 	]+71055207[ 	]+vlseg4e256ff.v[ 	]+v4,\(a0\),v0.t
++[ 	]+[0-9a-f]+:[ 	]+93055207[ 	]+vlseg5e256ff.v[ 	]+v4,\(a0\)
++[ 	]+[0-9a-f]+:[ 	]+93055207[ 	]+vlseg5e256ff.v[ 	]+v4,\(a0\)
++[ 	]+[0-9a-f]+:[ 	]+91055207[ 	]+vlseg5e256ff.v[ 	]+v4,\(a0\),v0.t
++[ 	]+[0-9a-f]+:[ 	]+b3055207[ 	]+vlseg6e256ff.v[ 	]+v4,\(a0\)
++[ 	]+[0-9a-f]+:[ 	]+b3055207[ 	]+vlseg6e256ff.v[ 	]+v4,\(a0\)
++[ 	]+[0-9a-f]+:[ 	]+b1055207[ 	]+vlseg6e256ff.v[ 	]+v4,\(a0\),v0.t
++[ 	]+[0-9a-f]+:[ 	]+d3055207[ 	]+vlseg7e256ff.v[ 	]+v4,\(a0\)
++[ 	]+[0-9a-f]+:[ 	]+d3055207[ 	]+vlseg7e256ff.v[ 	]+v4,\(a0\)
++[ 	]+[0-9a-f]+:[ 	]+d1055207[ 	]+vlseg7e256ff.v[ 	]+v4,\(a0\),v0.t
++[ 	]+[0-9a-f]+:[ 	]+f3055207[ 	]+vlseg8e256ff.v[ 	]+v4,\(a0\)
++[ 	]+[0-9a-f]+:[ 	]+f3055207[ 	]+vlseg8e256ff.v[ 	]+v4,\(a0\)
++[ 	]+[0-9a-f]+:[ 	]+f1055207[ 	]+vlseg8e256ff.v[ 	]+v4,\(a0\),v0.t
++[ 	]+[0-9a-f]+:[ 	]+33056207[ 	]+vlseg2e512ff.v[ 	]+v4,\(a0\)
++[ 	]+[0-9a-f]+:[ 	]+33056207[ 	]+vlseg2e512ff.v[ 	]+v4,\(a0\)
++[ 	]+[0-9a-f]+:[ 	]+31056207[ 	]+vlseg2e512ff.v[ 	]+v4,\(a0\),v0.t
++[ 	]+[0-9a-f]+:[ 	]+53056207[ 	]+vlseg3e512ff.v[ 	]+v4,\(a0\)
++[ 	]+[0-9a-f]+:[ 	]+53056207[ 	]+vlseg3e512ff.v[ 	]+v4,\(a0\)
++[ 	]+[0-9a-f]+:[ 	]+51056207[ 	]+vlseg3e512ff.v[ 	]+v4,\(a0\),v0.t
++[ 	]+[0-9a-f]+:[ 	]+73056207[ 	]+vlseg4e512ff.v[ 	]+v4,\(a0\)
++[ 	]+[0-9a-f]+:[ 	]+73056207[ 	]+vlseg4e512ff.v[ 	]+v4,\(a0\)
++[ 	]+[0-9a-f]+:[ 	]+71056207[ 	]+vlseg4e512ff.v[ 	]+v4,\(a0\),v0.t
++[ 	]+[0-9a-f]+:[ 	]+93056207[ 	]+vlseg5e512ff.v[ 	]+v4,\(a0\)
++[ 	]+[0-9a-f]+:[ 	]+93056207[ 	]+vlseg5e512ff.v[ 	]+v4,\(a0\)
++[ 	]+[0-9a-f]+:[ 	]+91056207[ 	]+vlseg5e512ff.v[ 	]+v4,\(a0\),v0.t
++[ 	]+[0-9a-f]+:[ 	]+b3056207[ 	]+vlseg6e512ff.v[ 	]+v4,\(a0\)
++[ 	]+[0-9a-f]+:[ 	]+b3056207[ 	]+vlseg6e512ff.v[ 	]+v4,\(a0\)
++[ 	]+[0-9a-f]+:[ 	]+b1056207[ 	]+vlseg6e512ff.v[ 	]+v4,\(a0\),v0.t
++[ 	]+[0-9a-f]+:[ 	]+d3056207[ 	]+vlseg7e512ff.v[ 	]+v4,\(a0\)
++[ 	]+[0-9a-f]+:[ 	]+d3056207[ 	]+vlseg7e512ff.v[ 	]+v4,\(a0\)
++[ 	]+[0-9a-f]+:[ 	]+d1056207[ 	]+vlseg7e512ff.v[ 	]+v4,\(a0\),v0.t
++[ 	]+[0-9a-f]+:[ 	]+f3056207[ 	]+vlseg8e512ff.v[ 	]+v4,\(a0\)
++[ 	]+[0-9a-f]+:[ 	]+f3056207[ 	]+vlseg8e512ff.v[ 	]+v4,\(a0\)
++[ 	]+[0-9a-f]+:[ 	]+f1056207[ 	]+vlseg8e512ff.v[ 	]+v4,\(a0\),v0.t
++[ 	]+[0-9a-f]+:[ 	]+33057207[ 	]+vlseg2e1024ff.v[ 	]+v4,\(a0\)
++[ 	]+[0-9a-f]+:[ 	]+33057207[ 	]+vlseg2e1024ff.v[ 	]+v4,\(a0\)
++[ 	]+[0-9a-f]+:[ 	]+31057207[ 	]+vlseg2e1024ff.v[ 	]+v4,\(a0\),v0.t
++[ 	]+[0-9a-f]+:[ 	]+53057207[ 	]+vlseg3e1024ff.v[ 	]+v4,\(a0\)
++[ 	]+[0-9a-f]+:[ 	]+53057207[ 	]+vlseg3e1024ff.v[ 	]+v4,\(a0\)
++[ 	]+[0-9a-f]+:[ 	]+51057207[ 	]+vlseg3e1024ff.v[ 	]+v4,\(a0\),v0.t
++[ 	]+[0-9a-f]+:[ 	]+73057207[ 	]+vlseg4e1024ff.v[ 	]+v4,\(a0\)
++[ 	]+[0-9a-f]+:[ 	]+73057207[ 	]+vlseg4e1024ff.v[ 	]+v4,\(a0\)
++[ 	]+[0-9a-f]+:[ 	]+71057207[ 	]+vlseg4e1024ff.v[ 	]+v4,\(a0\),v0.t
++[ 	]+[0-9a-f]+:[ 	]+93057207[ 	]+vlseg5e1024ff.v[ 	]+v4,\(a0\)
++[ 	]+[0-9a-f]+:[ 	]+93057207[ 	]+vlseg5e1024ff.v[ 	]+v4,\(a0\)
++[ 	]+[0-9a-f]+:[ 	]+91057207[ 	]+vlseg5e1024ff.v[ 	]+v4,\(a0\),v0.t
++[ 	]+[0-9a-f]+:[ 	]+b3057207[ 	]+vlseg6e1024ff.v[ 	]+v4,\(a0\)
++[ 	]+[0-9a-f]+:[ 	]+b3057207[ 	]+vlseg6e1024ff.v[ 	]+v4,\(a0\)
++[ 	]+[0-9a-f]+:[ 	]+b1057207[ 	]+vlseg6e1024ff.v[ 	]+v4,\(a0\),v0.t
++[ 	]+[0-9a-f]+:[ 	]+d3057207[ 	]+vlseg7e1024ff.v[ 	]+v4,\(a0\)
++[ 	]+[0-9a-f]+:[ 	]+d3057207[ 	]+vlseg7e1024ff.v[ 	]+v4,\(a0\)
++[ 	]+[0-9a-f]+:[ 	]+d1057207[ 	]+vlseg7e1024ff.v[ 	]+v4,\(a0\),v0.t
++[ 	]+[0-9a-f]+:[ 	]+f3057207[ 	]+vlseg8e1024ff.v[ 	]+v4,\(a0\)
++[ 	]+[0-9a-f]+:[ 	]+f3057207[ 	]+vlseg8e1024ff.v[ 	]+v4,\(a0\)
++[ 	]+[0-9a-f]+:[ 	]+f1057207[ 	]+vlseg8e1024ff.v[ 	]+v4,\(a0\),v0.t
++[ 	]+[0-9a-f]+:[ 	]+02850187[ 	]+vl1r.v[ 	]+v3,\(a0\)
++[ 	]+[0-9a-f]+:[ 	]+02850187[ 	]+vl1r.v[ 	]+v3,\(a0\)
++[ 	]+[0-9a-f]+:[ 	]+028581a7[ 	]+vs1r.v[ 	]+v3,\(a1\)
++[ 	]+[0-9a-f]+:[ 	]+028581a7[ 	]+vs1r.v[ 	]+v3,\(a1\)
++[ 	]+[0-9a-f]+:[ 	]+0685822f[ 	]+vamoaddei8.v[ 	]+v4,\(a1\),v8,v4
++[ 	]+[0-9a-f]+:[ 	]+0285822f[ 	]+vamoaddei8.v[ 	]+zero,\(a1\),v8,v4
++[ 	]+[0-9a-f]+:[ 	]+0485822f[ 	]+vamoaddei8.v[ 	]+v4,\(a1\),v8,v4,v0.t
++[ 	]+[0-9a-f]+:[ 	]+0085822f[ 	]+vamoaddei8.v[ 	]+zero,\(a1\),v8,v4,v0.t
++[ 	]+[0-9a-f]+:[ 	]+0e85822f[ 	]+vamoswapei8.v[ 	]+v4,\(a1\),v8,v4
++[ 	]+[0-9a-f]+:[ 	]+0a85822f[ 	]+vamoswapei8.v[ 	]+zero,\(a1\),v8,v4
++[ 	]+[0-9a-f]+:[ 	]+0c85822f[ 	]+vamoswapei8.v[ 	]+v4,\(a1\),v8,v4,v0.t
++[ 	]+[0-9a-f]+:[ 	]+0885822f[ 	]+vamoswapei8.v[ 	]+zero,\(a1\),v8,v4,v0.t
++[ 	]+[0-9a-f]+:[ 	]+2685822f[ 	]+vamoxorei8.v[ 	]+v4,\(a1\),v8,v4
++[ 	]+[0-9a-f]+:[ 	]+2285822f[ 	]+vamoxorei8.v[ 	]+zero,\(a1\),v8,v4
++[ 	]+[0-9a-f]+:[ 	]+2485822f[ 	]+vamoxorei8.v[ 	]+v4,\(a1\),v8,v4,v0.t
++[ 	]+[0-9a-f]+:[ 	]+2085822f[ 	]+vamoxorei8.v[ 	]+zero,\(a1\),v8,v4,v0.t
++[ 	]+[0-9a-f]+:[ 	]+6685822f[ 	]+vamoandei8.v[ 	]+v4,\(a1\),v8,v4
++[ 	]+[0-9a-f]+:[ 	]+6285822f[ 	]+vamoandei8.v[ 	]+zero,\(a1\),v8,v4
++[ 	]+[0-9a-f]+:[ 	]+6485822f[ 	]+vamoandei8.v[ 	]+v4,\(a1\),v8,v4,v0.t
++[ 	]+[0-9a-f]+:[ 	]+6085822f[ 	]+vamoandei8.v[ 	]+zero,\(a1\),v8,v4,v0.t
++[ 	]+[0-9a-f]+:[ 	]+4685822f[ 	]+vamoorei8.v[ 	]+v4,\(a1\),v8,v4
++[ 	]+[0-9a-f]+:[ 	]+4285822f[ 	]+vamoorei8.v[ 	]+zero,\(a1\),v8,v4
++[ 	]+[0-9a-f]+:[ 	]+4485822f[ 	]+vamoorei8.v[ 	]+v4,\(a1\),v8,v4,v0.t
++[ 	]+[0-9a-f]+:[ 	]+4085822f[ 	]+vamoorei8.v[ 	]+zero,\(a1\),v8,v4,v0.t
++[ 	]+[0-9a-f]+:[ 	]+8685822f[ 	]+vamominei8.v[ 	]+v4,\(a1\),v8,v4
++[ 	]+[0-9a-f]+:[ 	]+8285822f[ 	]+vamominei8.v[ 	]+zero,\(a1\),v8,v4
++[ 	]+[0-9a-f]+:[ 	]+8485822f[ 	]+vamominei8.v[ 	]+v4,\(a1\),v8,v4,v0.t
++[ 	]+[0-9a-f]+:[ 	]+8085822f[ 	]+vamominei8.v[ 	]+zero,\(a1\),v8,v4,v0.t
++[ 	]+[0-9a-f]+:[ 	]+a685822f[ 	]+vamomaxei8.v[ 	]+v4,\(a1\),v8,v4
++[ 	]+[0-9a-f]+:[ 	]+a285822f[ 	]+vamomaxei8.v[ 	]+zero,\(a1\),v8,v4
++[ 	]+[0-9a-f]+:[ 	]+a485822f[ 	]+vamomaxei8.v[ 	]+v4,\(a1\),v8,v4,v0.t
++[ 	]+[0-9a-f]+:[ 	]+a085822f[ 	]+vamomaxei8.v[ 	]+zero,\(a1\),v8,v4,v0.t
++[ 	]+[0-9a-f]+:[ 	]+c685822f[ 	]+vamominuei8.v[ 	]+v4,\(a1\),v8,v4
++[ 	]+[0-9a-f]+:[ 	]+c285822f[ 	]+vamominuei8.v[ 	]+zero,\(a1\),v8,v4
++[ 	]+[0-9a-f]+:[ 	]+c485822f[ 	]+vamominuei8.v[ 	]+v4,\(a1\),v8,v4,v0.t
++[ 	]+[0-9a-f]+:[ 	]+c085822f[ 	]+vamominuei8.v[ 	]+zero,\(a1\),v8,v4,v0.t
++[ 	]+[0-9a-f]+:[ 	]+e685822f[ 	]+vamomaxuei8.v[ 	]+v4,\(a1\),v8,v4
++[ 	]+[0-9a-f]+:[ 	]+e285822f[ 	]+vamomaxuei8.v[ 	]+zero,\(a1\),v8,v4
++[ 	]+[0-9a-f]+:[ 	]+e485822f[ 	]+vamomaxuei8.v[ 	]+v4,\(a1\),v8,v4,v0.t
++[ 	]+[0-9a-f]+:[ 	]+e085822f[ 	]+vamomaxuei8.v[ 	]+zero,\(a1\),v8,v4,v0.t
++[ 	]+[0-9a-f]+:[ 	]+0685822f[ 	]+vamoaddei8.v[ 	]+v4,\(a1\),v8,v4
++[ 	]+[0-9a-f]+:[ 	]+0285822f[ 	]+vamoaddei8.v[ 	]+zero,\(a1\),v8,v4
++[ 	]+[0-9a-f]+:[ 	]+0485822f[ 	]+vamoaddei8.v[ 	]+v4,\(a1\),v8,v4,v0.t
++[ 	]+[0-9a-f]+:[ 	]+0085822f[ 	]+vamoaddei8.v[ 	]+zero,\(a1\),v8,v4,v0.t
++[ 	]+[0-9a-f]+:[ 	]+0e85822f[ 	]+vamoswapei8.v[ 	]+v4,\(a1\),v8,v4
++[ 	]+[0-9a-f]+:[ 	]+0a85822f[ 	]+vamoswapei8.v[ 	]+zero,\(a1\),v8,v4
++[ 	]+[0-9a-f]+:[ 	]+0c85822f[ 	]+vamoswapei8.v[ 	]+v4,\(a1\),v8,v4,v0.t
++[ 	]+[0-9a-f]+:[ 	]+0885822f[ 	]+vamoswapei8.v[ 	]+zero,\(a1\),v8,v4,v0.t
++[ 	]+[0-9a-f]+:[ 	]+2685822f[ 	]+vamoxorei8.v[ 	]+v4,\(a1\),v8,v4
++[ 	]+[0-9a-f]+:[ 	]+2285822f[ 	]+vamoxorei8.v[ 	]+zero,\(a1\),v8,v4
++[ 	]+[0-9a-f]+:[ 	]+2485822f[ 	]+vamoxorei8.v[ 	]+v4,\(a1\),v8,v4,v0.t
++[ 	]+[0-9a-f]+:[ 	]+2085822f[ 	]+vamoxorei8.v[ 	]+zero,\(a1\),v8,v4,v0.t
++[ 	]+[0-9a-f]+:[ 	]+6685822f[ 	]+vamoandei8.v[ 	]+v4,\(a1\),v8,v4
++[ 	]+[0-9a-f]+:[ 	]+6285822f[ 	]+vamoandei8.v[ 	]+zero,\(a1\),v8,v4
++[ 	]+[0-9a-f]+:[ 	]+6485822f[ 	]+vamoandei8.v[ 	]+v4,\(a1\),v8,v4,v0.t
++[ 	]+[0-9a-f]+:[ 	]+6085822f[ 	]+vamoandei8.v[ 	]+zero,\(a1\),v8,v4,v0.t
++[ 	]+[0-9a-f]+:[ 	]+4685822f[ 	]+vamoorei8.v[ 	]+v4,\(a1\),v8,v4
++[ 	]+[0-9a-f]+:[ 	]+4285822f[ 	]+vamoorei8.v[ 	]+zero,\(a1\),v8,v4
++[ 	]+[0-9a-f]+:[ 	]+4485822f[ 	]+vamoorei8.v[ 	]+v4,\(a1\),v8,v4,v0.t
++[ 	]+[0-9a-f]+:[ 	]+4085822f[ 	]+vamoorei8.v[ 	]+zero,\(a1\),v8,v4,v0.t
++[ 	]+[0-9a-f]+:[ 	]+8685822f[ 	]+vamominei8.v[ 	]+v4,\(a1\),v8,v4
++[ 	]+[0-9a-f]+:[ 	]+8285822f[ 	]+vamominei8.v[ 	]+zero,\(a1\),v8,v4
++[ 	]+[0-9a-f]+:[ 	]+8485822f[ 	]+vamominei8.v[ 	]+v4,\(a1\),v8,v4,v0.t
++[ 	]+[0-9a-f]+:[ 	]+8085822f[ 	]+vamominei8.v[ 	]+zero,\(a1\),v8,v4,v0.t
++[ 	]+[0-9a-f]+:[ 	]+a685822f[ 	]+vamomaxei8.v[ 	]+v4,\(a1\),v8,v4
++[ 	]+[0-9a-f]+:[ 	]+a285822f[ 	]+vamomaxei8.v[ 	]+zero,\(a1\),v8,v4
++[ 	]+[0-9a-f]+:[ 	]+a485822f[ 	]+vamomaxei8.v[ 	]+v4,\(a1\),v8,v4,v0.t
++[ 	]+[0-9a-f]+:[ 	]+a085822f[ 	]+vamomaxei8.v[ 	]+zero,\(a1\),v8,v4,v0.t
++[ 	]+[0-9a-f]+:[ 	]+c685822f[ 	]+vamominuei8.v[ 	]+v4,\(a1\),v8,v4
++[ 	]+[0-9a-f]+:[ 	]+c285822f[ 	]+vamominuei8.v[ 	]+zero,\(a1\),v8,v4
++[ 	]+[0-9a-f]+:[ 	]+c485822f[ 	]+vamominuei8.v[ 	]+v4,\(a1\),v8,v4,v0.t
++[ 	]+[0-9a-f]+:[ 	]+c085822f[ 	]+vamominuei8.v[ 	]+zero,\(a1\),v8,v4,v0.t
++[ 	]+[0-9a-f]+:[ 	]+e685822f[ 	]+vamomaxuei8.v[ 	]+v4,\(a1\),v8,v4
++[ 	]+[0-9a-f]+:[ 	]+e285822f[ 	]+vamomaxuei8.v[ 	]+zero,\(a1\),v8,v4
++[ 	]+[0-9a-f]+:[ 	]+e485822f[ 	]+vamomaxuei8.v[ 	]+v4,\(a1\),v8,v4,v0.t
++[ 	]+[0-9a-f]+:[ 	]+e085822f[ 	]+vamomaxuei8.v[ 	]+zero,\(a1\),v8,v4,v0.t
++[ 	]+[0-9a-f]+:[ 	]+0685d22f[ 	]+vamoaddei16.v[ 	]+v4,\(a1\),v8,v4
++[ 	]+[0-9a-f]+:[ 	]+0285d22f[ 	]+vamoaddei16.v[ 	]+zero,\(a1\),v8,v4
++[ 	]+[0-9a-f]+:[ 	]+0485d22f[ 	]+vamoaddei16.v[ 	]+v4,\(a1\),v8,v4,v0.t
++[ 	]+[0-9a-f]+:[ 	]+0085d22f[ 	]+vamoaddei16.v[ 	]+zero,\(a1\),v8,v4,v0.t
++[ 	]+[0-9a-f]+:[ 	]+0e85d22f[ 	]+vamoswapei16.v[ 	]+v4,\(a1\),v8,v4
++[ 	]+[0-9a-f]+:[ 	]+0a85d22f[ 	]+vamoswapei16.v[ 	]+zero,\(a1\),v8,v4
++[ 	]+[0-9a-f]+:[ 	]+0c85d22f[ 	]+vamoswapei16.v[ 	]+v4,\(a1\),v8,v4,v0.t
++[ 	]+[0-9a-f]+:[ 	]+0885d22f[ 	]+vamoswapei16.v[ 	]+zero,\(a1\),v8,v4,v0.t
++[ 	]+[0-9a-f]+:[ 	]+2685d22f[ 	]+vamoxorei16.v[ 	]+v4,\(a1\),v8,v4
++[ 	]+[0-9a-f]+:[ 	]+2285d22f[ 	]+vamoxorei16.v[ 	]+zero,\(a1\),v8,v4
++[ 	]+[0-9a-f]+:[ 	]+2485d22f[ 	]+vamoxorei16.v[ 	]+v4,\(a1\),v8,v4,v0.t
++[ 	]+[0-9a-f]+:[ 	]+2085d22f[ 	]+vamoxorei16.v[ 	]+zero,\(a1\),v8,v4,v0.t
++[ 	]+[0-9a-f]+:[ 	]+6685d22f[ 	]+vamoandei16.v[ 	]+v4,\(a1\),v8,v4
++[ 	]+[0-9a-f]+:[ 	]+6285d22f[ 	]+vamoandei16.v[ 	]+zero,\(a1\),v8,v4
++[ 	]+[0-9a-f]+:[ 	]+6485d22f[ 	]+vamoandei16.v[ 	]+v4,\(a1\),v8,v4,v0.t
++[ 	]+[0-9a-f]+:[ 	]+6085d22f[ 	]+vamoandei16.v[ 	]+zero,\(a1\),v8,v4,v0.t
++[ 	]+[0-9a-f]+:[ 	]+4685d22f[ 	]+vamoorei16.v[ 	]+v4,\(a1\),v8,v4
++[ 	]+[0-9a-f]+:[ 	]+4285d22f[ 	]+vamoorei16.v[ 	]+zero,\(a1\),v8,v4
++[ 	]+[0-9a-f]+:[ 	]+4485d22f[ 	]+vamoorei16.v[ 	]+v4,\(a1\),v8,v4,v0.t
++[ 	]+[0-9a-f]+:[ 	]+4085d22f[ 	]+vamoorei16.v[ 	]+zero,\(a1\),v8,v4,v0.t
++[ 	]+[0-9a-f]+:[ 	]+8685d22f[ 	]+vamominei16.v[ 	]+v4,\(a1\),v8,v4
++[ 	]+[0-9a-f]+:[ 	]+8285d22f[ 	]+vamominei16.v[ 	]+zero,\(a1\),v8,v4
++[ 	]+[0-9a-f]+:[ 	]+8485d22f[ 	]+vamominei16.v[ 	]+v4,\(a1\),v8,v4,v0.t
++[ 	]+[0-9a-f]+:[ 	]+8085d22f[ 	]+vamominei16.v[ 	]+zero,\(a1\),v8,v4,v0.t
++[ 	]+[0-9a-f]+:[ 	]+a685d22f[ 	]+vamomaxei16.v[ 	]+v4,\(a1\),v8,v4
++[ 	]+[0-9a-f]+:[ 	]+a285d22f[ 	]+vamomaxei16.v[ 	]+zero,\(a1\),v8,v4
++[ 	]+[0-9a-f]+:[ 	]+a485d22f[ 	]+vamomaxei16.v[ 	]+v4,\(a1\),v8,v4,v0.t
++[ 	]+[0-9a-f]+:[ 	]+a085d22f[ 	]+vamomaxei16.v[ 	]+zero,\(a1\),v8,v4,v0.t
++[ 	]+[0-9a-f]+:[ 	]+c685d22f[ 	]+vamominuei16.v[ 	]+v4,\(a1\),v8,v4
++[ 	]+[0-9a-f]+:[ 	]+c285d22f[ 	]+vamominuei16.v[ 	]+zero,\(a1\),v8,v4
++[ 	]+[0-9a-f]+:[ 	]+c485d22f[ 	]+vamominuei16.v[ 	]+v4,\(a1\),v8,v4,v0.t
++[ 	]+[0-9a-f]+:[ 	]+c085d22f[ 	]+vamominuei16.v[ 	]+zero,\(a1\),v8,v4,v0.t
++[ 	]+[0-9a-f]+:[ 	]+e685d22f[ 	]+vamomaxuei16.v[ 	]+v4,\(a1\),v8,v4
++[ 	]+[0-9a-f]+:[ 	]+e285d22f[ 	]+vamomaxuei16.v[ 	]+zero,\(a1\),v8,v4
++[ 	]+[0-9a-f]+:[ 	]+e485d22f[ 	]+vamomaxuei16.v[ 	]+v4,\(a1\),v8,v4,v0.t
++[ 	]+[0-9a-f]+:[ 	]+e085d22f[ 	]+vamomaxuei16.v[ 	]+zero,\(a1\),v8,v4,v0.t
++[ 	]+[0-9a-f]+:[ 	]+0685d22f[ 	]+vamoaddei16.v[ 	]+v4,\(a1\),v8,v4
++[ 	]+[0-9a-f]+:[ 	]+0285d22f[ 	]+vamoaddei16.v[ 	]+zero,\(a1\),v8,v4
++[ 	]+[0-9a-f]+:[ 	]+0485d22f[ 	]+vamoaddei16.v[ 	]+v4,\(a1\),v8,v4,v0.t
++[ 	]+[0-9a-f]+:[ 	]+0085d22f[ 	]+vamoaddei16.v[ 	]+zero,\(a1\),v8,v4,v0.t
++[ 	]+[0-9a-f]+:[ 	]+0e85d22f[ 	]+vamoswapei16.v[ 	]+v4,\(a1\),v8,v4
++[ 	]+[0-9a-f]+:[ 	]+0a85d22f[ 	]+vamoswapei16.v[ 	]+zero,\(a1\),v8,v4
++[ 	]+[0-9a-f]+:[ 	]+0c85d22f[ 	]+vamoswapei16.v[ 	]+v4,\(a1\),v8,v4,v0.t
++[ 	]+[0-9a-f]+:[ 	]+0885d22f[ 	]+vamoswapei16.v[ 	]+zero,\(a1\),v8,v4,v0.t
++[ 	]+[0-9a-f]+:[ 	]+2685d22f[ 	]+vamoxorei16.v[ 	]+v4,\(a1\),v8,v4
++[ 	]+[0-9a-f]+:[ 	]+2285d22f[ 	]+vamoxorei16.v[ 	]+zero,\(a1\),v8,v4
++[ 	]+[0-9a-f]+:[ 	]+2485d22f[ 	]+vamoxorei16.v[ 	]+v4,\(a1\),v8,v4,v0.t
++[ 	]+[0-9a-f]+:[ 	]+2085d22f[ 	]+vamoxorei16.v[ 	]+zero,\(a1\),v8,v4,v0.t
++[ 	]+[0-9a-f]+:[ 	]+6685d22f[ 	]+vamoandei16.v[ 	]+v4,\(a1\),v8,v4
++[ 	]+[0-9a-f]+:[ 	]+6285d22f[ 	]+vamoandei16.v[ 	]+zero,\(a1\),v8,v4
++[ 	]+[0-9a-f]+:[ 	]+6485d22f[ 	]+vamoandei16.v[ 	]+v4,\(a1\),v8,v4,v0.t
++[ 	]+[0-9a-f]+:[ 	]+6085d22f[ 	]+vamoandei16.v[ 	]+zero,\(a1\),v8,v4,v0.t
++[ 	]+[0-9a-f]+:[ 	]+4685d22f[ 	]+vamoorei16.v[ 	]+v4,\(a1\),v8,v4
++[ 	]+[0-9a-f]+:[ 	]+4285d22f[ 	]+vamoorei16.v[ 	]+zero,\(a1\),v8,v4
++[ 	]+[0-9a-f]+:[ 	]+4485d22f[ 	]+vamoorei16.v[ 	]+v4,\(a1\),v8,v4,v0.t
++[ 	]+[0-9a-f]+:[ 	]+4085d22f[ 	]+vamoorei16.v[ 	]+zero,\(a1\),v8,v4,v0.t
++[ 	]+[0-9a-f]+:[ 	]+8685d22f[ 	]+vamominei16.v[ 	]+v4,\(a1\),v8,v4
++[ 	]+[0-9a-f]+:[ 	]+8285d22f[ 	]+vamominei16.v[ 	]+zero,\(a1\),v8,v4
++[ 	]+[0-9a-f]+:[ 	]+8485d22f[ 	]+vamominei16.v[ 	]+v4,\(a1\),v8,v4,v0.t
++[ 	]+[0-9a-f]+:[ 	]+8085d22f[ 	]+vamominei16.v[ 	]+zero,\(a1\),v8,v4,v0.t
++[ 	]+[0-9a-f]+:[ 	]+a685d22f[ 	]+vamomaxei16.v[ 	]+v4,\(a1\),v8,v4
++[ 	]+[0-9a-f]+:[ 	]+a285d22f[ 	]+vamomaxei16.v[ 	]+zero,\(a1\),v8,v4
++[ 	]+[0-9a-f]+:[ 	]+a485d22f[ 	]+vamomaxei16.v[ 	]+v4,\(a1\),v8,v4,v0.t
++[ 	]+[0-9a-f]+:[ 	]+a085d22f[ 	]+vamomaxei16.v[ 	]+zero,\(a1\),v8,v4,v0.t
++[ 	]+[0-9a-f]+:[ 	]+c685d22f[ 	]+vamominuei16.v[ 	]+v4,\(a1\),v8,v4
++[ 	]+[0-9a-f]+:[ 	]+c285d22f[ 	]+vamominuei16.v[ 	]+zero,\(a1\),v8,v4
++[ 	]+[0-9a-f]+:[ 	]+c485d22f[ 	]+vamominuei16.v[ 	]+v4,\(a1\),v8,v4,v0.t
++[ 	]+[0-9a-f]+:[ 	]+c085d22f[ 	]+vamominuei16.v[ 	]+zero,\(a1\),v8,v4,v0.t
++[ 	]+[0-9a-f]+:[ 	]+e685d22f[ 	]+vamomaxuei16.v[ 	]+v4,\(a1\),v8,v4
++[ 	]+[0-9a-f]+:[ 	]+e285d22f[ 	]+vamomaxuei16.v[ 	]+zero,\(a1\),v8,v4
++[ 	]+[0-9a-f]+:[ 	]+e485d22f[ 	]+vamomaxuei16.v[ 	]+v4,\(a1\),v8,v4,v0.t
++[ 	]+[0-9a-f]+:[ 	]+e085d22f[ 	]+vamomaxuei16.v[ 	]+zero,\(a1\),v8,v4,v0.t
++[ 	]+[0-9a-f]+:[ 	]+0685e22f[ 	]+vamoaddei32.v[ 	]+v4,\(a1\),v8,v4
++[ 	]+[0-9a-f]+:[ 	]+0285e22f[ 	]+vamoaddei32.v[ 	]+zero,\(a1\),v8,v4
++[ 	]+[0-9a-f]+:[ 	]+0485e22f[ 	]+vamoaddei32.v[ 	]+v4,\(a1\),v8,v4,v0.t
++[ 	]+[0-9a-f]+:[ 	]+0085e22f[ 	]+vamoaddei32.v[ 	]+zero,\(a1\),v8,v4,v0.t
++[ 	]+[0-9a-f]+:[ 	]+0e85e22f[ 	]+vamoswapei32.v[ 	]+v4,\(a1\),v8,v4
++[ 	]+[0-9a-f]+:[ 	]+0a85e22f[ 	]+vamoswapei32.v[ 	]+zero,\(a1\),v8,v4
++[ 	]+[0-9a-f]+:[ 	]+0c85e22f[ 	]+vamoswapei32.v[ 	]+v4,\(a1\),v8,v4,v0.t
++[ 	]+[0-9a-f]+:[ 	]+0885e22f[ 	]+vamoswapei32.v[ 	]+zero,\(a1\),v8,v4,v0.t
++[ 	]+[0-9a-f]+:[ 	]+2685e22f[ 	]+vamoxorei32.v[ 	]+v4,\(a1\),v8,v4
++[ 	]+[0-9a-f]+:[ 	]+2285e22f[ 	]+vamoxorei32.v[ 	]+zero,\(a1\),v8,v4
++[ 	]+[0-9a-f]+:[ 	]+2485e22f[ 	]+vamoxorei32.v[ 	]+v4,\(a1\),v8,v4,v0.t
++[ 	]+[0-9a-f]+:[ 	]+2085e22f[ 	]+vamoxorei32.v[ 	]+zero,\(a1\),v8,v4,v0.t
++[ 	]+[0-9a-f]+:[ 	]+6685e22f[ 	]+vamoandei32.v[ 	]+v4,\(a1\),v8,v4
++[ 	]+[0-9a-f]+:[ 	]+6285e22f[ 	]+vamoandei32.v[ 	]+zero,\(a1\),v8,v4
++[ 	]+[0-9a-f]+:[ 	]+6485e22f[ 	]+vamoandei32.v[ 	]+v4,\(a1\),v8,v4,v0.t
++[ 	]+[0-9a-f]+:[ 	]+6085e22f[ 	]+vamoandei32.v[ 	]+zero,\(a1\),v8,v4,v0.t
++[ 	]+[0-9a-f]+:[ 	]+4685e22f[ 	]+vamoorei32.v[ 	]+v4,\(a1\),v8,v4
++[ 	]+[0-9a-f]+:[ 	]+4285e22f[ 	]+vamoorei32.v[ 	]+zero,\(a1\),v8,v4
++[ 	]+[0-9a-f]+:[ 	]+4485e22f[ 	]+vamoorei32.v[ 	]+v4,\(a1\),v8,v4,v0.t
++[ 	]+[0-9a-f]+:[ 	]+4085e22f[ 	]+vamoorei32.v[ 	]+zero,\(a1\),v8,v4,v0.t
++[ 	]+[0-9a-f]+:[ 	]+8685e22f[ 	]+vamominei32.v[ 	]+v4,\(a1\),v8,v4
++[ 	]+[0-9a-f]+:[ 	]+8285e22f[ 	]+vamominei32.v[ 	]+zero,\(a1\),v8,v4
++[ 	]+[0-9a-f]+:[ 	]+8485e22f[ 	]+vamominei32.v[ 	]+v4,\(a1\),v8,v4,v0.t
++[ 	]+[0-9a-f]+:[ 	]+8085e22f[ 	]+vamominei32.v[ 	]+zero,\(a1\),v8,v4,v0.t
++[ 	]+[0-9a-f]+:[ 	]+a685e22f[ 	]+vamomaxei32.v[ 	]+v4,\(a1\),v8,v4
++[ 	]+[0-9a-f]+:[ 	]+a285e22f[ 	]+vamomaxei32.v[ 	]+zero,\(a1\),v8,v4
++[ 	]+[0-9a-f]+:[ 	]+a485e22f[ 	]+vamomaxei32.v[ 	]+v4,\(a1\),v8,v4,v0.t
++[ 	]+[0-9a-f]+:[ 	]+a085e22f[ 	]+vamomaxei32.v[ 	]+zero,\(a1\),v8,v4,v0.t
++[ 	]+[0-9a-f]+:[ 	]+c685e22f[ 	]+vamominuei32.v[ 	]+v4,\(a1\),v8,v4
++[ 	]+[0-9a-f]+:[ 	]+c285e22f[ 	]+vamominuei32.v[ 	]+zero,\(a1\),v8,v4
++[ 	]+[0-9a-f]+:[ 	]+c485e22f[ 	]+vamominuei32.v[ 	]+v4,\(a1\),v8,v4,v0.t
++[ 	]+[0-9a-f]+:[ 	]+c085e22f[ 	]+vamominuei32.v[ 	]+zero,\(a1\),v8,v4,v0.t
++[ 	]+[0-9a-f]+:[ 	]+e685e22f[ 	]+vamomaxuei32.v[ 	]+v4,\(a1\),v8,v4
++[ 	]+[0-9a-f]+:[ 	]+e285e22f[ 	]+vamomaxuei32.v[ 	]+zero,\(a1\),v8,v4
++[ 	]+[0-9a-f]+:[ 	]+e485e22f[ 	]+vamomaxuei32.v[ 	]+v4,\(a1\),v8,v4,v0.t
++[ 	]+[0-9a-f]+:[ 	]+e085e22f[ 	]+vamomaxuei32.v[ 	]+zero,\(a1\),v8,v4,v0.t
++[ 	]+[0-9a-f]+:[ 	]+0685e22f[ 	]+vamoaddei32.v[ 	]+v4,\(a1\),v8,v4
++[ 	]+[0-9a-f]+:[ 	]+0285e22f[ 	]+vamoaddei32.v[ 	]+zero,\(a1\),v8,v4
++[ 	]+[0-9a-f]+:[ 	]+0485e22f[ 	]+vamoaddei32.v[ 	]+v4,\(a1\),v8,v4,v0.t
++[ 	]+[0-9a-f]+:[ 	]+0085e22f[ 	]+vamoaddei32.v[ 	]+zero,\(a1\),v8,v4,v0.t
++[ 	]+[0-9a-f]+:[ 	]+0e85e22f[ 	]+vamoswapei32.v[ 	]+v4,\(a1\),v8,v4
++[ 	]+[0-9a-f]+:[ 	]+0a85e22f[ 	]+vamoswapei32.v[ 	]+zero,\(a1\),v8,v4
++[ 	]+[0-9a-f]+:[ 	]+0c85e22f[ 	]+vamoswapei32.v[ 	]+v4,\(a1\),v8,v4,v0.t
++[ 	]+[0-9a-f]+:[ 	]+0885e22f[ 	]+vamoswapei32.v[ 	]+zero,\(a1\),v8,v4,v0.t
++[ 	]+[0-9a-f]+:[ 	]+2685e22f[ 	]+vamoxorei32.v[ 	]+v4,\(a1\),v8,v4
++[ 	]+[0-9a-f]+:[ 	]+2285e22f[ 	]+vamoxorei32.v[ 	]+zero,\(a1\),v8,v4
++[ 	]+[0-9a-f]+:[ 	]+2485e22f[ 	]+vamoxorei32.v[ 	]+v4,\(a1\),v8,v4,v0.t
++[ 	]+[0-9a-f]+:[ 	]+2085e22f[ 	]+vamoxorei32.v[ 	]+zero,\(a1\),v8,v4,v0.t
++[ 	]+[0-9a-f]+:[ 	]+6685e22f[ 	]+vamoandei32.v[ 	]+v4,\(a1\),v8,v4
++[ 	]+[0-9a-f]+:[ 	]+6285e22f[ 	]+vamoandei32.v[ 	]+zero,\(a1\),v8,v4
++[ 	]+[0-9a-f]+:[ 	]+6485e22f[ 	]+vamoandei32.v[ 	]+v4,\(a1\),v8,v4,v0.t
++[ 	]+[0-9a-f]+:[ 	]+6085e22f[ 	]+vamoandei32.v[ 	]+zero,\(a1\),v8,v4,v0.t
++[ 	]+[0-9a-f]+:[ 	]+4685e22f[ 	]+vamoorei32.v[ 	]+v4,\(a1\),v8,v4
++[ 	]+[0-9a-f]+:[ 	]+4285e22f[ 	]+vamoorei32.v[ 	]+zero,\(a1\),v8,v4
++[ 	]+[0-9a-f]+:[ 	]+4485e22f[ 	]+vamoorei32.v[ 	]+v4,\(a1\),v8,v4,v0.t
++[ 	]+[0-9a-f]+:[ 	]+4085e22f[ 	]+vamoorei32.v[ 	]+zero,\(a1\),v8,v4,v0.t
++[ 	]+[0-9a-f]+:[ 	]+8685e22f[ 	]+vamominei32.v[ 	]+v4,\(a1\),v8,v4
++[ 	]+[0-9a-f]+:[ 	]+8285e22f[ 	]+vamominei32.v[ 	]+zero,\(a1\),v8,v4
++[ 	]+[0-9a-f]+:[ 	]+8485e22f[ 	]+vamominei32.v[ 	]+v4,\(a1\),v8,v4,v0.t
++[ 	]+[0-9a-f]+:[ 	]+8085e22f[ 	]+vamominei32.v[ 	]+zero,\(a1\),v8,v4,v0.t
++[ 	]+[0-9a-f]+:[ 	]+a685e22f[ 	]+vamomaxei32.v[ 	]+v4,\(a1\),v8,v4
++[ 	]+[0-9a-f]+:[ 	]+a285e22f[ 	]+vamomaxei32.v[ 	]+zero,\(a1\),v8,v4
++[ 	]+[0-9a-f]+:[ 	]+a485e22f[ 	]+vamomaxei32.v[ 	]+v4,\(a1\),v8,v4,v0.t
++[ 	]+[0-9a-f]+:[ 	]+a085e22f[ 	]+vamomaxei32.v[ 	]+zero,\(a1\),v8,v4,v0.t
++[ 	]+[0-9a-f]+:[ 	]+c685e22f[ 	]+vamominuei32.v[ 	]+v4,\(a1\),v8,v4
++[ 	]+[0-9a-f]+:[ 	]+c285e22f[ 	]+vamominuei32.v[ 	]+zero,\(a1\),v8,v4
++[ 	]+[0-9a-f]+:[ 	]+c485e22f[ 	]+vamominuei32.v[ 	]+v4,\(a1\),v8,v4,v0.t
++[ 	]+[0-9a-f]+:[ 	]+c085e22f[ 	]+vamominuei32.v[ 	]+zero,\(a1\),v8,v4,v0.t
++[ 	]+[0-9a-f]+:[ 	]+e685e22f[ 	]+vamomaxuei32.v[ 	]+v4,\(a1\),v8,v4
++[ 	]+[0-9a-f]+:[ 	]+e285e22f[ 	]+vamomaxuei32.v[ 	]+zero,\(a1\),v8,v4
++[ 	]+[0-9a-f]+:[ 	]+e485e22f[ 	]+vamomaxuei32.v[ 	]+v4,\(a1\),v8,v4,v0.t
++[ 	]+[0-9a-f]+:[ 	]+e085e22f[ 	]+vamomaxuei32.v[ 	]+zero,\(a1\),v8,v4,v0.t
++[ 	]+[0-9a-f]+:[ 	]+0685f22f[ 	]+vamoaddei64.v[ 	]+v4,\(a1\),v8,v4
++[ 	]+[0-9a-f]+:[ 	]+0285f22f[ 	]+vamoaddei64.v[ 	]+zero,\(a1\),v8,v4
++[ 	]+[0-9a-f]+:[ 	]+0485f22f[ 	]+vamoaddei64.v[ 	]+v4,\(a1\),v8,v4,v0.t
++[ 	]+[0-9a-f]+:[ 	]+0085f22f[ 	]+vamoaddei64.v[ 	]+zero,\(a1\),v8,v4,v0.t
++[ 	]+[0-9a-f]+:[ 	]+0e85f22f[ 	]+vamoswapei64.v[ 	]+v4,\(a1\),v8,v4
++[ 	]+[0-9a-f]+:[ 	]+0a85f22f[ 	]+vamoswapei64.v[ 	]+zero,\(a1\),v8,v4
++[ 	]+[0-9a-f]+:[ 	]+0c85f22f[ 	]+vamoswapei64.v[ 	]+v4,\(a1\),v8,v4,v0.t
++[ 	]+[0-9a-f]+:[ 	]+0885f22f[ 	]+vamoswapei64.v[ 	]+zero,\(a1\),v8,v4,v0.t
++[ 	]+[0-9a-f]+:[ 	]+2685f22f[ 	]+vamoxorei64.v[ 	]+v4,\(a1\),v8,v4
++[ 	]+[0-9a-f]+:[ 	]+2285f22f[ 	]+vamoxorei64.v[ 	]+zero,\(a1\),v8,v4
++[ 	]+[0-9a-f]+:[ 	]+2485f22f[ 	]+vamoxorei64.v[ 	]+v4,\(a1\),v8,v4,v0.t
++[ 	]+[0-9a-f]+:[ 	]+2085f22f[ 	]+vamoxorei64.v[ 	]+zero,\(a1\),v8,v4,v0.t
++[ 	]+[0-9a-f]+:[ 	]+6685f22f[ 	]+vamoandei64.v[ 	]+v4,\(a1\),v8,v4
++[ 	]+[0-9a-f]+:[ 	]+6285f22f[ 	]+vamoandei64.v[ 	]+zero,\(a1\),v8,v4
++[ 	]+[0-9a-f]+:[ 	]+6485f22f[ 	]+vamoandei64.v[ 	]+v4,\(a1\),v8,v4,v0.t
++[ 	]+[0-9a-f]+:[ 	]+6085f22f[ 	]+vamoandei64.v[ 	]+zero,\(a1\),v8,v4,v0.t
++[ 	]+[0-9a-f]+:[ 	]+4685f22f[ 	]+vamoorei64.v[ 	]+v4,\(a1\),v8,v4
++[ 	]+[0-9a-f]+:[ 	]+4285f22f[ 	]+vamoorei64.v[ 	]+zero,\(a1\),v8,v4
++[ 	]+[0-9a-f]+:[ 	]+4485f22f[ 	]+vamoorei64.v[ 	]+v4,\(a1\),v8,v4,v0.t
++[ 	]+[0-9a-f]+:[ 	]+4085f22f[ 	]+vamoorei64.v[ 	]+zero,\(a1\),v8,v4,v0.t
++[ 	]+[0-9a-f]+:[ 	]+8685f22f[ 	]+vamominei64.v[ 	]+v4,\(a1\),v8,v4
++[ 	]+[0-9a-f]+:[ 	]+8285f22f[ 	]+vamominei64.v[ 	]+zero,\(a1\),v8,v4
++[ 	]+[0-9a-f]+:[ 	]+8485f22f[ 	]+vamominei64.v[ 	]+v4,\(a1\),v8,v4,v0.t
++[ 	]+[0-9a-f]+:[ 	]+8085f22f[ 	]+vamominei64.v[ 	]+zero,\(a1\),v8,v4,v0.t
++[ 	]+[0-9a-f]+:[ 	]+a685f22f[ 	]+vamomaxei64.v[ 	]+v4,\(a1\),v8,v4
++[ 	]+[0-9a-f]+:[ 	]+a285f22f[ 	]+vamomaxei64.v[ 	]+zero,\(a1\),v8,v4
++[ 	]+[0-9a-f]+:[ 	]+a485f22f[ 	]+vamomaxei64.v[ 	]+v4,\(a1\),v8,v4,v0.t
++[ 	]+[0-9a-f]+:[ 	]+a085f22f[ 	]+vamomaxei64.v[ 	]+zero,\(a1\),v8,v4,v0.t
++[ 	]+[0-9a-f]+:[ 	]+c685f22f[ 	]+vamominuei64.v[ 	]+v4,\(a1\),v8,v4
++[ 	]+[0-9a-f]+:[ 	]+c285f22f[ 	]+vamominuei64.v[ 	]+zero,\(a1\),v8,v4
++[ 	]+[0-9a-f]+:[ 	]+c485f22f[ 	]+vamominuei64.v[ 	]+v4,\(a1\),v8,v4,v0.t
++[ 	]+[0-9a-f]+:[ 	]+c085f22f[ 	]+vamominuei64.v[ 	]+zero,\(a1\),v8,v4,v0.t
++[ 	]+[0-9a-f]+:[ 	]+e685f22f[ 	]+vamomaxuei64.v[ 	]+v4,\(a1\),v8,v4
++[ 	]+[0-9a-f]+:[ 	]+e285f22f[ 	]+vamomaxuei64.v[ 	]+zero,\(a1\),v8,v4
++[ 	]+[0-9a-f]+:[ 	]+e485f22f[ 	]+vamomaxuei64.v[ 	]+v4,\(a1\),v8,v4,v0.t
++[ 	]+[0-9a-f]+:[ 	]+e085f22f[ 	]+vamomaxuei64.v[ 	]+zero,\(a1\),v8,v4,v0.t
++[ 	]+[0-9a-f]+:[ 	]+0685f22f[ 	]+vamoaddei64.v[ 	]+v4,\(a1\),v8,v4
++[ 	]+[0-9a-f]+:[ 	]+0285f22f[ 	]+vamoaddei64.v[ 	]+zero,\(a1\),v8,v4
++[ 	]+[0-9a-f]+:[ 	]+0485f22f[ 	]+vamoaddei64.v[ 	]+v4,\(a1\),v8,v4,v0.t
++[ 	]+[0-9a-f]+:[ 	]+0085f22f[ 	]+vamoaddei64.v[ 	]+zero,\(a1\),v8,v4,v0.t
++[ 	]+[0-9a-f]+:[ 	]+0e85f22f[ 	]+vamoswapei64.v[ 	]+v4,\(a1\),v8,v4
++[ 	]+[0-9a-f]+:[ 	]+0a85f22f[ 	]+vamoswapei64.v[ 	]+zero,\(a1\),v8,v4
++[ 	]+[0-9a-f]+:[ 	]+0c85f22f[ 	]+vamoswapei64.v[ 	]+v4,\(a1\),v8,v4,v0.t
++[ 	]+[0-9a-f]+:[ 	]+0885f22f[ 	]+vamoswapei64.v[ 	]+zero,\(a1\),v8,v4,v0.t
++[ 	]+[0-9a-f]+:[ 	]+2685f22f[ 	]+vamoxorei64.v[ 	]+v4,\(a1\),v8,v4
++[ 	]+[0-9a-f]+:[ 	]+2285f22f[ 	]+vamoxorei64.v[ 	]+zero,\(a1\),v8,v4
++[ 	]+[0-9a-f]+:[ 	]+2485f22f[ 	]+vamoxorei64.v[ 	]+v4,\(a1\),v8,v4,v0.t
++[ 	]+[0-9a-f]+:[ 	]+2085f22f[ 	]+vamoxorei64.v[ 	]+zero,\(a1\),v8,v4,v0.t
++[ 	]+[0-9a-f]+:[ 	]+6685f22f[ 	]+vamoandei64.v[ 	]+v4,\(a1\),v8,v4
++[ 	]+[0-9a-f]+:[ 	]+6285f22f[ 	]+vamoandei64.v[ 	]+zero,\(a1\),v8,v4
++[ 	]+[0-9a-f]+:[ 	]+6485f22f[ 	]+vamoandei64.v[ 	]+v4,\(a1\),v8,v4,v0.t
++[ 	]+[0-9a-f]+:[ 	]+6085f22f[ 	]+vamoandei64.v[ 	]+zero,\(a1\),v8,v4,v0.t
++[ 	]+[0-9a-f]+:[ 	]+4685f22f[ 	]+vamoorei64.v[ 	]+v4,\(a1\),v8,v4
++[ 	]+[0-9a-f]+:[ 	]+4285f22f[ 	]+vamoorei64.v[ 	]+zero,\(a1\),v8,v4
++[ 	]+[0-9a-f]+:[ 	]+4485f22f[ 	]+vamoorei64.v[ 	]+v4,\(a1\),v8,v4,v0.t
++[ 	]+[0-9a-f]+:[ 	]+4085f22f[ 	]+vamoorei64.v[ 	]+zero,\(a1\),v8,v4,v0.t
++[ 	]+[0-9a-f]+:[ 	]+8685f22f[ 	]+vamominei64.v[ 	]+v4,\(a1\),v8,v4
++[ 	]+[0-9a-f]+:[ 	]+8285f22f[ 	]+vamominei64.v[ 	]+zero,\(a1\),v8,v4
++[ 	]+[0-9a-f]+:[ 	]+8485f22f[ 	]+vamominei64.v[ 	]+v4,\(a1\),v8,v4,v0.t
++[ 	]+[0-9a-f]+:[ 	]+8085f22f[ 	]+vamominei64.v[ 	]+zero,\(a1\),v8,v4,v0.t
++[ 	]+[0-9a-f]+:[ 	]+a685f22f[ 	]+vamomaxei64.v[ 	]+v4,\(a1\),v8,v4
++[ 	]+[0-9a-f]+:[ 	]+a285f22f[ 	]+vamomaxei64.v[ 	]+zero,\(a1\),v8,v4
++[ 	]+[0-9a-f]+:[ 	]+a485f22f[ 	]+vamomaxei64.v[ 	]+v4,\(a1\),v8,v4,v0.t
++[ 	]+[0-9a-f]+:[ 	]+a085f22f[ 	]+vamomaxei64.v[ 	]+zero,\(a1\),v8,v4,v0.t
++[ 	]+[0-9a-f]+:[ 	]+c685f22f[ 	]+vamominuei64.v[ 	]+v4,\(a1\),v8,v4
++[ 	]+[0-9a-f]+:[ 	]+c285f22f[ 	]+vamominuei64.v[ 	]+zero,\(a1\),v8,v4
++[ 	]+[0-9a-f]+:[ 	]+c485f22f[ 	]+vamominuei64.v[ 	]+v4,\(a1\),v8,v4,v0.t
++[ 	]+[0-9a-f]+:[ 	]+c085f22f[ 	]+vamominuei64.v[ 	]+zero,\(a1\),v8,v4,v0.t
++[ 	]+[0-9a-f]+:[ 	]+e685f22f[ 	]+vamomaxuei64.v[ 	]+v4,\(a1\),v8,v4
++[ 	]+[0-9a-f]+:[ 	]+e285f22f[ 	]+vamomaxuei64.v[ 	]+zero,\(a1\),v8,v4
++[ 	]+[0-9a-f]+:[ 	]+e485f22f[ 	]+vamomaxuei64.v[ 	]+v4,\(a1\),v8,v4,v0.t
++[ 	]+[0-9a-f]+:[ 	]+e085f22f[ 	]+vamomaxuei64.v[ 	]+zero,\(a1\),v8,v4,v0.t
++[ 	]+[0-9a-f]+:[ 	]+02860257[ 	]+vadd.vv[ 	]+v4,v8,v12
++[ 	]+[0-9a-f]+:[ 	]+0285c257[ 	]+vadd.vx[ 	]+v4,v8,a1
++[ 	]+[0-9a-f]+:[ 	]+0287b257[ 	]+vadd.vi[ 	]+v4,v8,15
++[ 	]+[0-9a-f]+:[ 	]+02883257[ 	]+vadd.vi[ 	]+v4,v8,-16
++[ 	]+[0-9a-f]+:[ 	]+00860257[ 	]+vadd.vv[ 	]+v4,v8,v12,v0.t
++[ 	]+[0-9a-f]+:[ 	]+0085c257[ 	]+vadd.vx[ 	]+v4,v8,a1,v0.t
++[ 	]+[0-9a-f]+:[ 	]+0087b257[ 	]+vadd.vi[ 	]+v4,v8,15,v0.t
++[ 	]+[0-9a-f]+:[ 	]+00883257[ 	]+vadd.vi[ 	]+v4,v8,-16,v0.t
++[ 	]+[0-9a-f]+:[ 	]+0a860257[ 	]+vsub.vv[ 	]+v4,v8,v12
++[ 	]+[0-9a-f]+:[ 	]+0a85c257[ 	]+vsub.vx[ 	]+v4,v8,a1
++[ 	]+[0-9a-f]+:[ 	]+0e85c257[ 	]+vrsub.vx[ 	]+v4,v8,a1
++[ 	]+[0-9a-f]+:[ 	]+0e87b257[ 	]+vrsub.vi[ 	]+v4,v8,15
++[ 	]+[0-9a-f]+:[ 	]+0e883257[ 	]+vrsub.vi[ 	]+v4,v8,-16
++[ 	]+[0-9a-f]+:[ 	]+08860257[ 	]+vsub.vv[ 	]+v4,v8,v12,v0.t
++[ 	]+[0-9a-f]+:[ 	]+0885c257[ 	]+vsub.vx[ 	]+v4,v8,a1,v0.t
++[ 	]+[0-9a-f]+:[ 	]+0c85c257[ 	]+vrsub.vx[ 	]+v4,v8,a1,v0.t
++[ 	]+[0-9a-f]+:[ 	]+0c87b257[ 	]+vrsub.vi[ 	]+v4,v8,15,v0.t
++[ 	]+[0-9a-f]+:[ 	]+0c883257[ 	]+vrsub.vi[ 	]+v4,v8,-16,v0.t
++[ 	]+[0-9a-f]+:[ 	]+c6806257[ 	]+vwcvt.x.x.v[ 	]+v4,v8
++[ 	]+[0-9a-f]+:[ 	]+c2806257[ 	]+vwcvtu.x.x.v[ 	]+v4,v8
++[ 	]+[0-9a-f]+:[ 	]+c4806257[ 	]+vwcvt.x.x.v[ 	]+v4,v8,v0.t
++[ 	]+[0-9a-f]+:[ 	]+c0806257[ 	]+vwcvtu.x.x.v[ 	]+v4,v8,v0.t
++[ 	]+[0-9a-f]+:[ 	]+c2862257[ 	]+vwaddu.vv[ 	]+v4,v8,v12
++[ 	]+[0-9a-f]+:[ 	]+c285e257[ 	]+vwaddu.vx[ 	]+v4,v8,a1
++[ 	]+[0-9a-f]+:[ 	]+c0862257[ 	]+vwaddu.vv[ 	]+v4,v8,v12,v0.t
++[ 	]+[0-9a-f]+:[ 	]+c085e257[ 	]+vwaddu.vx[ 	]+v4,v8,a1,v0.t
++[ 	]+[0-9a-f]+:[ 	]+ca862257[ 	]+vwsubu.vv[ 	]+v4,v8,v12
++[ 	]+[0-9a-f]+:[ 	]+ca85e257[ 	]+vwsubu.vx[ 	]+v4,v8,a1
++[ 	]+[0-9a-f]+:[ 	]+c8862257[ 	]+vwsubu.vv[ 	]+v4,v8,v12,v0.t
++[ 	]+[0-9a-f]+:[ 	]+c885e257[ 	]+vwsubu.vx[ 	]+v4,v8,a1,v0.t
++[ 	]+[0-9a-f]+:[ 	]+c6862257[ 	]+vwadd.vv[ 	]+v4,v8,v12
++[ 	]+[0-9a-f]+:[ 	]+c685e257[ 	]+vwadd.vx[ 	]+v4,v8,a1
++[ 	]+[0-9a-f]+:[ 	]+c4862257[ 	]+vwadd.vv[ 	]+v4,v8,v12,v0.t
++[ 	]+[0-9a-f]+:[ 	]+c485e257[ 	]+vwadd.vx[ 	]+v4,v8,a1,v0.t
++[ 	]+[0-9a-f]+:[ 	]+ce862257[ 	]+vwsub.vv[ 	]+v4,v8,v12
++[ 	]+[0-9a-f]+:[ 	]+ce85e257[ 	]+vwsub.vx[ 	]+v4,v8,a1
++[ 	]+[0-9a-f]+:[ 	]+cc862257[ 	]+vwsub.vv[ 	]+v4,v8,v12,v0.t
++[ 	]+[0-9a-f]+:[ 	]+cc85e257[ 	]+vwsub.vx[ 	]+v4,v8,a1,v0.t
++[ 	]+[0-9a-f]+:[ 	]+d2862257[ 	]+vwaddu.wv[ 	]+v4,v8,v12
++[ 	]+[0-9a-f]+:[ 	]+d285e257[ 	]+vwaddu.wx[ 	]+v4,v8,a1
++[ 	]+[0-9a-f]+:[ 	]+d0862257[ 	]+vwaddu.wv[ 	]+v4,v8,v12,v0.t
++[ 	]+[0-9a-f]+:[ 	]+d085e257[ 	]+vwaddu.wx[ 	]+v4,v8,a1,v0.t
++[ 	]+[0-9a-f]+:[ 	]+da862257[ 	]+vwsubu.wv[ 	]+v4,v8,v12
++[ 	]+[0-9a-f]+:[ 	]+da85e257[ 	]+vwsubu.wx[ 	]+v4,v8,a1
++[ 	]+[0-9a-f]+:[ 	]+d8862257[ 	]+vwsubu.wv[ 	]+v4,v8,v12,v0.t
++[ 	]+[0-9a-f]+:[ 	]+d885e257[ 	]+vwsubu.wx[ 	]+v4,v8,a1,v0.t
++[ 	]+[0-9a-f]+:[ 	]+d6862257[ 	]+vwadd.wv[ 	]+v4,v8,v12
++[ 	]+[0-9a-f]+:[ 	]+d685e257[ 	]+vwadd.wx[ 	]+v4,v8,a1
++[ 	]+[0-9a-f]+:[ 	]+d4862257[ 	]+vwadd.wv[ 	]+v4,v8,v12,v0.t
++[ 	]+[0-9a-f]+:[ 	]+d485e257[ 	]+vwadd.wx[ 	]+v4,v8,a1,v0.t
++[ 	]+[0-9a-f]+:[ 	]+de862257[ 	]+vwsub.wv[ 	]+v4,v8,v12
++[ 	]+[0-9a-f]+:[ 	]+de85e257[ 	]+vwsub.wx[ 	]+v4,v8,a1
++[ 	]+[0-9a-f]+:[ 	]+dc862257[ 	]+vwsub.wv[ 	]+v4,v8,v12,v0.t
++[ 	]+[0-9a-f]+:[ 	]+dc85e257[ 	]+vwsub.wx[ 	]+v4,v8,a1,v0.t
++[ 	]+[0-9a-f]+:[ 	]+4a832257[ 	]+vzext.vf2[ 	]+v4,v8
++[ 	]+[0-9a-f]+:[ 	]+48832257[ 	]+vzext.vf2[ 	]+v4,v8,v0.t
++[ 	]+[0-9a-f]+:[ 	]+4a83a257[ 	]+vsext.vf2[ 	]+v4,v8
++[ 	]+[0-9a-f]+:[ 	]+4883a257[ 	]+vsext.vf2[ 	]+v4,v8,v0.t
++[ 	]+[0-9a-f]+:[ 	]+4a822257[ 	]+vzext.vf4[ 	]+v4,v8
++[ 	]+[0-9a-f]+:[ 	]+48822257[ 	]+vzext.vf4[ 	]+v4,v8,v0.t
++[ 	]+[0-9a-f]+:[ 	]+4a82a257[ 	]+vsext.vf4[ 	]+v4,v8
++[ 	]+[0-9a-f]+:[ 	]+4882a257[ 	]+vsext.vf4[ 	]+v4,v8,v0.t
++[ 	]+[0-9a-f]+:[ 	]+4a812257[ 	]+vzext.vf8[ 	]+v4,v8
++[ 	]+[0-9a-f]+:[ 	]+48812257[ 	]+vzext.vf8[ 	]+v4,v8,v0.t
++[ 	]+[0-9a-f]+:[ 	]+4a81a257[ 	]+vsext.vf8[ 	]+v4,v8
++[ 	]+[0-9a-f]+:[ 	]+4881a257[ 	]+vsext.vf8[ 	]+v4,v8,v0.t
++[ 	]+[0-9a-f]+:[ 	]+40860257[ 	]+vadc.vvm[ 	]+v4,v8,v12,v0
++[ 	]+[0-9a-f]+:[ 	]+4085c257[ 	]+vadc.vxm[ 	]+v4,v8,a1,v0
++[ 	]+[0-9a-f]+:[ 	]+4087b257[ 	]+vadc.vim[ 	]+v4,v8,15,v0
++[ 	]+[0-9a-f]+:[ 	]+40883257[ 	]+vadc.vim[ 	]+v4,v8,-16,v0
++[ 	]+[0-9a-f]+:[ 	]+44860257[ 	]+vmadc.vvm[ 	]+v4,v8,v12,v0
++[ 	]+[0-9a-f]+:[ 	]+4485c257[ 	]+vmadc.vxm[ 	]+v4,v8,a1,v0
++[ 	]+[0-9a-f]+:[ 	]+4487b257[ 	]+vmadc.vim[ 	]+v4,v8,15,v0
++[ 	]+[0-9a-f]+:[ 	]+44883257[ 	]+vmadc.vim[ 	]+v4,v8,-16,v0
++[ 	]+[0-9a-f]+:[ 	]+46860257[ 	]+vmadc.vv[ 	]+v4,v8,v12
++[ 	]+[0-9a-f]+:[ 	]+4685c257[ 	]+vmadc.vx[ 	]+v4,v8,a1
++[ 	]+[0-9a-f]+:[ 	]+4687b257[ 	]+vmadc.vi[ 	]+v4,v8,15
++[ 	]+[0-9a-f]+:[ 	]+46883257[ 	]+vmadc.vi[ 	]+v4,v8,-16
++[ 	]+[0-9a-f]+:[ 	]+48860257[ 	]+vsbc.vvm[ 	]+v4,v8,v12,v0
++[ 	]+[0-9a-f]+:[ 	]+4885c257[ 	]+vsbc.vxm[ 	]+v4,v8,a1,v0
++[ 	]+[0-9a-f]+:[ 	]+4c860257[ 	]+vmsbc.vvm[ 	]+v4,v8,v12,v0
++[ 	]+[0-9a-f]+:[ 	]+4c85c257[ 	]+vmsbc.vxm[ 	]+v4,v8,a1,v0
++[ 	]+[0-9a-f]+:[ 	]+4e860257[ 	]+vmsbc.vv[ 	]+v4,v8,v12
++[ 	]+[0-9a-f]+:[ 	]+4e85c257[ 	]+vmsbc.vx[ 	]+v4,v8,a1
++[ 	]+[0-9a-f]+:[ 	]+2e8fb257[ 	]+vnot.v[ 	]+v4,v8
++[ 	]+[0-9a-f]+:[ 	]+2c8fb257[ 	]+vnot.v[ 	]+v4,v8,v0.t
++[ 	]+[0-9a-f]+:[ 	]+26860257[ 	]+vand.vv[ 	]+v4,v8,v12
++[ 	]+[0-9a-f]+:[ 	]+2685c257[ 	]+vand.vx[ 	]+v4,v8,a1
++[ 	]+[0-9a-f]+:[ 	]+2687b257[ 	]+vand.vi[ 	]+v4,v8,15
++[ 	]+[0-9a-f]+:[ 	]+26883257[ 	]+vand.vi[ 	]+v4,v8,-16
++[ 	]+[0-9a-f]+:[ 	]+24860257[ 	]+vand.vv[ 	]+v4,v8,v12,v0.t
++[ 	]+[0-9a-f]+:[ 	]+2485c257[ 	]+vand.vx[ 	]+v4,v8,a1,v0.t
++[ 	]+[0-9a-f]+:[ 	]+2487b257[ 	]+vand.vi[ 	]+v4,v8,15,v0.t
++[ 	]+[0-9a-f]+:[ 	]+24883257[ 	]+vand.vi[ 	]+v4,v8,-16,v0.t
++[ 	]+[0-9a-f]+:[ 	]+2a860257[ 	]+vor.vv[ 	]+v4,v8,v12
++[ 	]+[0-9a-f]+:[ 	]+2a85c257[ 	]+vor.vx[ 	]+v4,v8,a1
++[ 	]+[0-9a-f]+:[ 	]+2a87b257[ 	]+vor.vi[ 	]+v4,v8,15
++[ 	]+[0-9a-f]+:[ 	]+2a883257[ 	]+vor.vi[ 	]+v4,v8,-16
++[ 	]+[0-9a-f]+:[ 	]+28860257[ 	]+vor.vv[ 	]+v4,v8,v12,v0.t
++[ 	]+[0-9a-f]+:[ 	]+2885c257[ 	]+vor.vx[ 	]+v4,v8,a1,v0.t
++[ 	]+[0-9a-f]+:[ 	]+2887b257[ 	]+vor.vi[ 	]+v4,v8,15,v0.t
++[ 	]+[0-9a-f]+:[ 	]+28883257[ 	]+vor.vi[ 	]+v4,v8,-16,v0.t
++[ 	]+[0-9a-f]+:[ 	]+2e860257[ 	]+vxor.vv[ 	]+v4,v8,v12
++[ 	]+[0-9a-f]+:[ 	]+2e85c257[ 	]+vxor.vx[ 	]+v4,v8,a1
++[ 	]+[0-9a-f]+:[ 	]+2e87b257[ 	]+vxor.vi[ 	]+v4,v8,15
++[ 	]+[0-9a-f]+:[ 	]+2e883257[ 	]+vxor.vi[ 	]+v4,v8,-16
++[ 	]+[0-9a-f]+:[ 	]+2c860257[ 	]+vxor.vv[ 	]+v4,v8,v12,v0.t
++[ 	]+[0-9a-f]+:[ 	]+2c85c257[ 	]+vxor.vx[ 	]+v4,v8,a1,v0.t
++[ 	]+[0-9a-f]+:[ 	]+2c87b257[ 	]+vxor.vi[ 	]+v4,v8,15,v0.t
++[ 	]+[0-9a-f]+:[ 	]+2c883257[ 	]+vxor.vi[ 	]+v4,v8,-16,v0.t
++[ 	]+[0-9a-f]+:[ 	]+96860257[ 	]+vsll.vv[ 	]+v4,v8,v12
++[ 	]+[0-9a-f]+:[ 	]+9685c257[ 	]+vsll.vx[ 	]+v4,v8,a1
++[ 	]+[0-9a-f]+:[ 	]+9680b257[ 	]+vsll.vi[ 	]+v4,v8,1
++[ 	]+[0-9a-f]+:[ 	]+968fb257[ 	]+vsll.vi[ 	]+v4,v8,31
++[ 	]+[0-9a-f]+:[ 	]+94860257[ 	]+vsll.vv[ 	]+v4,v8,v12,v0.t
++[ 	]+[0-9a-f]+:[ 	]+9485c257[ 	]+vsll.vx[ 	]+v4,v8,a1,v0.t
++[ 	]+[0-9a-f]+:[ 	]+9480b257[ 	]+vsll.vi[ 	]+v4,v8,1,v0.t
++[ 	]+[0-9a-f]+:[ 	]+948fb257[ 	]+vsll.vi[ 	]+v4,v8,31,v0.t
++[ 	]+[0-9a-f]+:[ 	]+a2860257[ 	]+vsrl.vv[ 	]+v4,v8,v12
++[ 	]+[0-9a-f]+:[ 	]+a285c257[ 	]+vsrl.vx[ 	]+v4,v8,a1
++[ 	]+[0-9a-f]+:[ 	]+a280b257[ 	]+vsrl.vi[ 	]+v4,v8,1
++[ 	]+[0-9a-f]+:[ 	]+a28fb257[ 	]+vsrl.vi[ 	]+v4,v8,31
++[ 	]+[0-9a-f]+:[ 	]+a0860257[ 	]+vsrl.vv[ 	]+v4,v8,v12,v0.t
++[ 	]+[0-9a-f]+:[ 	]+a085c257[ 	]+vsrl.vx[ 	]+v4,v8,a1,v0.t
++[ 	]+[0-9a-f]+:[ 	]+a080b257[ 	]+vsrl.vi[ 	]+v4,v8,1,v0.t
++[ 	]+[0-9a-f]+:[ 	]+a08fb257[ 	]+vsrl.vi[ 	]+v4,v8,31,v0.t
++[ 	]+[0-9a-f]+:[ 	]+a6860257[ 	]+vsra.vv[ 	]+v4,v8,v12
++[ 	]+[0-9a-f]+:[ 	]+a685c257[ 	]+vsra.vx[ 	]+v4,v8,a1
++[ 	]+[0-9a-f]+:[ 	]+a680b257[ 	]+vsra.vi[ 	]+v4,v8,1
++[ 	]+[0-9a-f]+:[ 	]+a68fb257[ 	]+vsra.vi[ 	]+v4,v8,31
++[ 	]+[0-9a-f]+:[ 	]+a4860257[ 	]+vsra.vv[ 	]+v4,v8,v12,v0.t
++[ 	]+[0-9a-f]+:[ 	]+a485c257[ 	]+vsra.vx[ 	]+v4,v8,a1,v0.t
++[ 	]+[0-9a-f]+:[ 	]+a480b257[ 	]+vsra.vi[ 	]+v4,v8,1,v0.t
++[ 	]+[0-9a-f]+:[ 	]+a48fb257[ 	]+vsra.vi[ 	]+v4,v8,31,v0.t
++[ 	]+[0-9a-f]+:[ 	]+b2860257[ 	]+vnsrl.wv[ 	]+v4,v8,v12
++[ 	]+[0-9a-f]+:[ 	]+b285c257[ 	]+vnsrl.wx[ 	]+v4,v8,a1
++[ 	]+[0-9a-f]+:[ 	]+b280b257[ 	]+vnsrl.wi[ 	]+v4,v8,1
++[ 	]+[0-9a-f]+:[ 	]+b28fb257[ 	]+vnsrl.wi[ 	]+v4,v8,31
++[ 	]+[0-9a-f]+:[ 	]+b0860257[ 	]+vnsrl.wv[ 	]+v4,v8,v12,v0.t
++[ 	]+[0-9a-f]+:[ 	]+b085c257[ 	]+vnsrl.wx[ 	]+v4,v8,a1,v0.t
++[ 	]+[0-9a-f]+:[ 	]+b080b257[ 	]+vnsrl.wi[ 	]+v4,v8,1,v0.t
++[ 	]+[0-9a-f]+:[ 	]+b08fb257[ 	]+vnsrl.wi[ 	]+v4,v8,31,v0.t
++[ 	]+[0-9a-f]+:[ 	]+b6860257[ 	]+vnsra.wv[ 	]+v4,v8,v12
++[ 	]+[0-9a-f]+:[ 	]+b685c257[ 	]+vnsra.wx[ 	]+v4,v8,a1
++[ 	]+[0-9a-f]+:[ 	]+b680b257[ 	]+vnsra.wi[ 	]+v4,v8,1
++[ 	]+[0-9a-f]+:[ 	]+b68fb257[ 	]+vnsra.wi[ 	]+v4,v8,31
++[ 	]+[0-9a-f]+:[ 	]+b4860257[ 	]+vnsra.wv[ 	]+v4,v8,v12,v0.t
++[ 	]+[0-9a-f]+:[ 	]+b485c257[ 	]+vnsra.wx[ 	]+v4,v8,a1,v0.t
++[ 	]+[0-9a-f]+:[ 	]+b480b257[ 	]+vnsra.wi[ 	]+v4,v8,1,v0.t
++[ 	]+[0-9a-f]+:[ 	]+b48fb257[ 	]+vnsra.wi[ 	]+v4,v8,31,v0.t
++[ 	]+[0-9a-f]+:[ 	]+6ec40257[ 	]+vmslt.vv[ 	]+v4,v12,v8
++[ 	]+[0-9a-f]+:[ 	]+6ac40257[ 	]+vmsltu.vv[ 	]+v4,v12,v8
++[ 	]+[0-9a-f]+:[ 	]+76c40257[ 	]+vmsle.vv[ 	]+v4,v12,v8
++[ 	]+[0-9a-f]+:[ 	]+72c40257[ 	]+vmsleu.vv[ 	]+v4,v12,v8
++[ 	]+[0-9a-f]+:[ 	]+6cc40257[ 	]+vmslt.vv[ 	]+v4,v12,v8,v0.t
++[ 	]+[0-9a-f]+:[ 	]+68c40257[ 	]+vmsltu.vv[ 	]+v4,v12,v8,v0.t
++[ 	]+[0-9a-f]+:[ 	]+74c40257[ 	]+vmsle.vv[ 	]+v4,v12,v8,v0.t
++[ 	]+[0-9a-f]+:[ 	]+70c40257[ 	]+vmsleu.vv[ 	]+v4,v12,v8,v0.t
++[ 	]+[0-9a-f]+:[ 	]+7687b257[ 	]+vmsle.vi[ 	]+v4,v8,15
++[ 	]+[0-9a-f]+:[ 	]+76883257[ 	]+vmsle.vi[ 	]+v4,v8,-16
++[ 	]+[0-9a-f]+:[ 	]+7287b257[ 	]+vmsleu.vi[ 	]+v4,v8,15
++[ 	]+[0-9a-f]+:[ 	]+72883257[ 	]+vmsleu.vi[ 	]+v4,v8,-16
++[ 	]+[0-9a-f]+:[ 	]+7e87b257[ 	]+vmsgt.vi[ 	]+v4,v8,15
++[ 	]+[0-9a-f]+:[ 	]+7e883257[ 	]+vmsgt.vi[ 	]+v4,v8,-16
++[ 	]+[0-9a-f]+:[ 	]+7a87b257[ 	]+vmsgtu.vi[ 	]+v4,v8,15
++[ 	]+[0-9a-f]+:[ 	]+7a883257[ 	]+vmsgtu.vi[ 	]+v4,v8,-16
++[ 	]+[0-9a-f]+:[ 	]+7487b257[ 	]+vmsle.vi[ 	]+v4,v8,15,v0.t
++[ 	]+[0-9a-f]+:[ 	]+74883257[ 	]+vmsle.vi[ 	]+v4,v8,-16,v0.t
++[ 	]+[0-9a-f]+:[ 	]+7087b257[ 	]+vmsleu.vi[ 	]+v4,v8,15,v0.t
++[ 	]+[0-9a-f]+:[ 	]+70883257[ 	]+vmsleu.vi[ 	]+v4,v8,-16,v0.t
++[ 	]+[0-9a-f]+:[ 	]+7c87b257[ 	]+vmsgt.vi[ 	]+v4,v8,15,v0.t
++[ 	]+[0-9a-f]+:[ 	]+7c883257[ 	]+vmsgt.vi[ 	]+v4,v8,-16,v0.t
++[ 	]+[0-9a-f]+:[ 	]+7887b257[ 	]+vmsgtu.vi[ 	]+v4,v8,15,v0.t
++[ 	]+[0-9a-f]+:[ 	]+78883257[ 	]+vmsgtu.vi[ 	]+v4,v8,-16,v0.t
++[ 	]+[0-9a-f]+:[ 	]+62860257[ 	]+vmseq.vv[ 	]+v4,v8,v12
++[ 	]+[0-9a-f]+:[ 	]+6285c257[ 	]+vmseq.vx[ 	]+v4,v8,a1
++[ 	]+[0-9a-f]+:[ 	]+6287b257[ 	]+vmseq.vi[ 	]+v4,v8,15
++[ 	]+[0-9a-f]+:[ 	]+62883257[ 	]+vmseq.vi[ 	]+v4,v8,-16
++[ 	]+[0-9a-f]+:[ 	]+60860257[ 	]+vmseq.vv[ 	]+v4,v8,v12,v0.t
++[ 	]+[0-9a-f]+:[ 	]+6085c257[ 	]+vmseq.vx[ 	]+v4,v8,a1,v0.t
++[ 	]+[0-9a-f]+:[ 	]+6087b257[ 	]+vmseq.vi[ 	]+v4,v8,15,v0.t
++[ 	]+[0-9a-f]+:[ 	]+60883257[ 	]+vmseq.vi[ 	]+v4,v8,-16,v0.t
++[ 	]+[0-9a-f]+:[ 	]+66860257[ 	]+vmsne.vv[ 	]+v4,v8,v12
++[ 	]+[0-9a-f]+:[ 	]+6685c257[ 	]+vmsne.vx[ 	]+v4,v8,a1
++[ 	]+[0-9a-f]+:[ 	]+6687b257[ 	]+vmsne.vi[ 	]+v4,v8,15
++[ 	]+[0-9a-f]+:[ 	]+66883257[ 	]+vmsne.vi[ 	]+v4,v8,-16
++[ 	]+[0-9a-f]+:[ 	]+64860257[ 	]+vmsne.vv[ 	]+v4,v8,v12,v0.t
++[ 	]+[0-9a-f]+:[ 	]+6485c257[ 	]+vmsne.vx[ 	]+v4,v8,a1,v0.t
++[ 	]+[0-9a-f]+:[ 	]+6487b257[ 	]+vmsne.vi[ 	]+v4,v8,15,v0.t
++[ 	]+[0-9a-f]+:[ 	]+64883257[ 	]+vmsne.vi[ 	]+v4,v8,-16,v0.t
++[ 	]+[0-9a-f]+:[ 	]+6a860257[ 	]+vmsltu.vv[ 	]+v4,v8,v12
++[ 	]+[0-9a-f]+:[ 	]+6a85c257[ 	]+vmsltu.vx[ 	]+v4,v8,a1
++[ 	]+[0-9a-f]+:[ 	]+68860257[ 	]+vmsltu.vv[ 	]+v4,v8,v12,v0.t
++[ 	]+[0-9a-f]+:[ 	]+6885c257[ 	]+vmsltu.vx[ 	]+v4,v8,a1,v0.t
++[ 	]+[0-9a-f]+:[ 	]+6e860257[ 	]+vmslt.vv[ 	]+v4,v8,v12
++[ 	]+[0-9a-f]+:[ 	]+6e85c257[ 	]+vmslt.vx[ 	]+v4,v8,a1
++[ 	]+[0-9a-f]+:[ 	]+6c860257[ 	]+vmslt.vv[ 	]+v4,v8,v12,v0.t
++[ 	]+[0-9a-f]+:[ 	]+6c85c257[ 	]+vmslt.vx[ 	]+v4,v8,a1,v0.t
++[ 	]+[0-9a-f]+:[ 	]+72860257[ 	]+vmsleu.vv[ 	]+v4,v8,v12
++[ 	]+[0-9a-f]+:[ 	]+7285c257[ 	]+vmsleu.vx[ 	]+v4,v8,a1
++[ 	]+[0-9a-f]+:[ 	]+7287b257[ 	]+vmsleu.vi[ 	]+v4,v8,15
++[ 	]+[0-9a-f]+:[ 	]+72883257[ 	]+vmsleu.vi[ 	]+v4,v8,-16
++[ 	]+[0-9a-f]+:[ 	]+70860257[ 	]+vmsleu.vv[ 	]+v4,v8,v12,v0.t
++[ 	]+[0-9a-f]+:[ 	]+7085c257[ 	]+vmsleu.vx[ 	]+v4,v8,a1,v0.t
++[ 	]+[0-9a-f]+:[ 	]+7087b257[ 	]+vmsleu.vi[ 	]+v4,v8,15,v0.t
++[ 	]+[0-9a-f]+:[ 	]+70883257[ 	]+vmsleu.vi[ 	]+v4,v8,-16,v0.t
++[ 	]+[0-9a-f]+:[ 	]+76860257[ 	]+vmsle.vv[ 	]+v4,v8,v12
++[ 	]+[0-9a-f]+:[ 	]+7685c257[ 	]+vmsle.vx[ 	]+v4,v8,a1
++[ 	]+[0-9a-f]+:[ 	]+7687b257[ 	]+vmsle.vi[ 	]+v4,v8,15
++[ 	]+[0-9a-f]+:[ 	]+76883257[ 	]+vmsle.vi[ 	]+v4,v8,-16
++[ 	]+[0-9a-f]+:[ 	]+74860257[ 	]+vmsle.vv[ 	]+v4,v8,v12,v0.t
++[ 	]+[0-9a-f]+:[ 	]+7485c257[ 	]+vmsle.vx[ 	]+v4,v8,a1,v0.t
++[ 	]+[0-9a-f]+:[ 	]+7487b257[ 	]+vmsle.vi[ 	]+v4,v8,15,v0.t
++[ 	]+[0-9a-f]+:[ 	]+74883257[ 	]+vmsle.vi[ 	]+v4,v8,-16,v0.t
++[ 	]+[0-9a-f]+:[ 	]+7a85c257[ 	]+vmsgtu.vx[ 	]+v4,v8,a1
++[ 	]+[0-9a-f]+:[ 	]+7a87b257[ 	]+vmsgtu.vi[ 	]+v4,v8,15
++[ 	]+[0-9a-f]+:[ 	]+7a883257[ 	]+vmsgtu.vi[ 	]+v4,v8,-16
++[ 	]+[0-9a-f]+:[ 	]+7885c257[ 	]+vmsgtu.vx[ 	]+v4,v8,a1,v0.t
++[ 	]+[0-9a-f]+:[ 	]+7887b257[ 	]+vmsgtu.vi[ 	]+v4,v8,15,v0.t
++[ 	]+[0-9a-f]+:[ 	]+78883257[ 	]+vmsgtu.vi[ 	]+v4,v8,-16,v0.t
++[ 	]+[0-9a-f]+:[ 	]+7e85c257[ 	]+vmsgt.vx[ 	]+v4,v8,a1
++[ 	]+[0-9a-f]+:[ 	]+7e87b257[ 	]+vmsgt.vi[ 	]+v4,v8,15
++[ 	]+[0-9a-f]+:[ 	]+7e883257[ 	]+vmsgt.vi[ 	]+v4,v8,-16
++[ 	]+[0-9a-f]+:[ 	]+7c85c257[ 	]+vmsgt.vx[ 	]+v4,v8,a1,v0.t
++[ 	]+[0-9a-f]+:[ 	]+7c87b257[ 	]+vmsgt.vi[ 	]+v4,v8,15,v0.t
++[ 	]+[0-9a-f]+:[ 	]+7c883257[ 	]+vmsgt.vi[ 	]+v4,v8,-16,v0.t
++[ 	]+[0-9a-f]+:[ 	]+12860257[ 	]+vminu.vv[ 	]+v4,v8,v12
++[ 	]+[0-9a-f]+:[ 	]+1285c257[ 	]+vminu.vx[ 	]+v4,v8,a1
++[ 	]+[0-9a-f]+:[ 	]+10860257[ 	]+vminu.vv[ 	]+v4,v8,v12,v0.t
++[ 	]+[0-9a-f]+:[ 	]+1085c257[ 	]+vminu.vx[ 	]+v4,v8,a1,v0.t
++[ 	]+[0-9a-f]+:[ 	]+16860257[ 	]+vmin.vv[ 	]+v4,v8,v12
++[ 	]+[0-9a-f]+:[ 	]+1685c257[ 	]+vmin.vx[ 	]+v4,v8,a1
++[ 	]+[0-9a-f]+:[ 	]+14860257[ 	]+vmin.vv[ 	]+v4,v8,v12,v0.t
++[ 	]+[0-9a-f]+:[ 	]+1485c257[ 	]+vmin.vx[ 	]+v4,v8,a1,v0.t
++[ 	]+[0-9a-f]+:[ 	]+1a860257[ 	]+vmaxu.vv[ 	]+v4,v8,v12
++[ 	]+[0-9a-f]+:[ 	]+1a85c257[ 	]+vmaxu.vx[ 	]+v4,v8,a1
++[ 	]+[0-9a-f]+:[ 	]+18860257[ 	]+vmaxu.vv[ 	]+v4,v8,v12,v0.t
++[ 	]+[0-9a-f]+:[ 	]+1885c257[ 	]+vmaxu.vx[ 	]+v4,v8,a1,v0.t
++[ 	]+[0-9a-f]+:[ 	]+1e860257[ 	]+vmax.vv[ 	]+v4,v8,v12
++[ 	]+[0-9a-f]+:[ 	]+1e85c257[ 	]+vmax.vx[ 	]+v4,v8,a1
++[ 	]+[0-9a-f]+:[ 	]+1c860257[ 	]+vmax.vv[ 	]+v4,v8,v12,v0.t
++[ 	]+[0-9a-f]+:[ 	]+1c85c257[ 	]+vmax.vx[ 	]+v4,v8,a1,v0.t
++[ 	]+[0-9a-f]+:[ 	]+96862257[ 	]+vmul.vv[ 	]+v4,v8,v12
++[ 	]+[0-9a-f]+:[ 	]+9685e257[ 	]+vmul.vx[ 	]+v4,v8,a1
++[ 	]+[0-9a-f]+:[ 	]+94862257[ 	]+vmul.vv[ 	]+v4,v8,v12,v0.t
++[ 	]+[0-9a-f]+:[ 	]+9485e257[ 	]+vmul.vx[ 	]+v4,v8,a1,v0.t
++[ 	]+[0-9a-f]+:[ 	]+9e862257[ 	]+vmulh.vv[ 	]+v4,v8,v12
++[ 	]+[0-9a-f]+:[ 	]+9e85e257[ 	]+vmulh.vx[ 	]+v4,v8,a1
++[ 	]+[0-9a-f]+:[ 	]+9c862257[ 	]+vmulh.vv[ 	]+v4,v8,v12,v0.t
++[ 	]+[0-9a-f]+:[ 	]+9c85e257[ 	]+vmulh.vx[ 	]+v4,v8,a1,v0.t
++[ 	]+[0-9a-f]+:[ 	]+92862257[ 	]+vmulhu.vv[ 	]+v4,v8,v12
++[ 	]+[0-9a-f]+:[ 	]+9285e257[ 	]+vmulhu.vx[ 	]+v4,v8,a1
++[ 	]+[0-9a-f]+:[ 	]+90862257[ 	]+vmulhu.vv[ 	]+v4,v8,v12,v0.t
++[ 	]+[0-9a-f]+:[ 	]+9085e257[ 	]+vmulhu.vx[ 	]+v4,v8,a1,v0.t
++[ 	]+[0-9a-f]+:[ 	]+9a862257[ 	]+vmulhsu.vv[ 	]+v4,v8,v12
++[ 	]+[0-9a-f]+:[ 	]+9a85e257[ 	]+vmulhsu.vx[ 	]+v4,v8,a1
++[ 	]+[0-9a-f]+:[ 	]+98862257[ 	]+vmulhsu.vv[ 	]+v4,v8,v12,v0.t
++[ 	]+[0-9a-f]+:[ 	]+9885e257[ 	]+vmulhsu.vx[ 	]+v4,v8,a1,v0.t
++[ 	]+[0-9a-f]+:[ 	]+ee862257[ 	]+vwmul.vv[ 	]+v4,v8,v12
++[ 	]+[0-9a-f]+:[ 	]+ee85e257[ 	]+vwmul.vx[ 	]+v4,v8,a1
++[ 	]+[0-9a-f]+:[ 	]+ec862257[ 	]+vwmul.vv[ 	]+v4,v8,v12,v0.t
++[ 	]+[0-9a-f]+:[ 	]+ec85e257[ 	]+vwmul.vx[ 	]+v4,v8,a1,v0.t
++[ 	]+[0-9a-f]+:[ 	]+e2862257[ 	]+vwmulu.vv[ 	]+v4,v8,v12
++[ 	]+[0-9a-f]+:[ 	]+e285e257[ 	]+vwmulu.vx[ 	]+v4,v8,a1
++[ 	]+[0-9a-f]+:[ 	]+e0862257[ 	]+vwmulu.vv[ 	]+v4,v8,v12,v0.t
++[ 	]+[0-9a-f]+:[ 	]+e085e257[ 	]+vwmulu.vx[ 	]+v4,v8,a1,v0.t
++[ 	]+[0-9a-f]+:[ 	]+ea862257[ 	]+vwmulsu.vv[ 	]+v4,v8,v12
++[ 	]+[0-9a-f]+:[ 	]+ea85e257[ 	]+vwmulsu.vx[ 	]+v4,v8,a1
++[ 	]+[0-9a-f]+:[ 	]+e8862257[ 	]+vwmulsu.vv[ 	]+v4,v8,v12,v0.t
++[ 	]+[0-9a-f]+:[ 	]+e885e257[ 	]+vwmulsu.vx[ 	]+v4,v8,a1,v0.t
++[ 	]+[0-9a-f]+:[ 	]+b6862257[ 	]+vmacc.vv[ 	]+v4,v12,v8
++[ 	]+[0-9a-f]+:[ 	]+b685e257[ 	]+vmacc.vx[ 	]+v4,a1,v8
++[ 	]+[0-9a-f]+:[ 	]+b4862257[ 	]+vmacc.vv[ 	]+v4,v12,v8,v0.t
++[ 	]+[0-9a-f]+:[ 	]+b485e257[ 	]+vmacc.vx[ 	]+v4,a1,v8,v0.t
++[ 	]+[0-9a-f]+:[ 	]+be862257[ 	]+vnmsac.vv[ 	]+v4,v12,v8
++[ 	]+[0-9a-f]+:[ 	]+be85e257[ 	]+vnmsac.vx[ 	]+v4,a1,v8
++[ 	]+[0-9a-f]+:[ 	]+bc862257[ 	]+vnmsac.vv[ 	]+v4,v12,v8,v0.t
++[ 	]+[0-9a-f]+:[ 	]+bc85e257[ 	]+vnmsac.vx[ 	]+v4,a1,v8,v0.t
++[ 	]+[0-9a-f]+:[ 	]+a6862257[ 	]+vmadd.vv[ 	]+v4,v12,v8
++[ 	]+[0-9a-f]+:[ 	]+a685e257[ 	]+vmadd.vx[ 	]+v4,a1,v8
++[ 	]+[0-9a-f]+:[ 	]+a4862257[ 	]+vmadd.vv[ 	]+v4,v12,v8,v0.t
++[ 	]+[0-9a-f]+:[ 	]+a485e257[ 	]+vmadd.vx[ 	]+v4,a1,v8,v0.t
++[ 	]+[0-9a-f]+:[ 	]+ae862257[ 	]+vnmsub.vv[ 	]+v4,v12,v8
++[ 	]+[0-9a-f]+:[ 	]+ae85e257[ 	]+vnmsub.vx[ 	]+v4,a1,v8
++[ 	]+[0-9a-f]+:[ 	]+ac862257[ 	]+vnmsub.vv[ 	]+v4,v12,v8,v0.t
++[ 	]+[0-9a-f]+:[ 	]+ac85e257[ 	]+vnmsub.vx[ 	]+v4,a1,v8,v0.t
++[ 	]+[0-9a-f]+:[ 	]+f2862257[ 	]+vwmaccu.vv[ 	]+v4,v12,v8
++[ 	]+[0-9a-f]+:[ 	]+f285e257[ 	]+vwmaccu.vx[ 	]+v4,a1,v8
++[ 	]+[0-9a-f]+:[ 	]+f0862257[ 	]+vwmaccu.vv[ 	]+v4,v12,v8,v0.t
++[ 	]+[0-9a-f]+:[ 	]+f085e257[ 	]+vwmaccu.vx[ 	]+v4,a1,v8,v0.t
++[ 	]+[0-9a-f]+:[ 	]+f6862257[ 	]+vwmacc.vv[ 	]+v4,v12,v8
++[ 	]+[0-9a-f]+:[ 	]+f685e257[ 	]+vwmacc.vx[ 	]+v4,a1,v8
++[ 	]+[0-9a-f]+:[ 	]+f4862257[ 	]+vwmacc.vv[ 	]+v4,v12,v8,v0.t
++[ 	]+[0-9a-f]+:[ 	]+f485e257[ 	]+vwmacc.vx[ 	]+v4,a1,v8,v0.t
++[ 	]+[0-9a-f]+:[ 	]+fe862257[ 	]+vwmaccsu.vv[ 	]+v4,v12,v8
++[ 	]+[0-9a-f]+:[ 	]+fe85e257[ 	]+vwmaccsu.vx[ 	]+v4,a1,v8
++[ 	]+[0-9a-f]+:[ 	]+fc862257[ 	]+vwmaccsu.vv[ 	]+v4,v12,v8,v0.t
++[ 	]+[0-9a-f]+:[ 	]+fc85e257[ 	]+vwmaccsu.vx[ 	]+v4,a1,v8,v0.t
++[ 	]+[0-9a-f]+:[ 	]+fa85e257[ 	]+vwmaccus.vx[ 	]+v4,a1,v8
++[ 	]+[0-9a-f]+:[ 	]+f885e257[ 	]+vwmaccus.vx[ 	]+v4,a1,v8,v0.t
++[ 	]+[0-9a-f]+:[ 	]+f2860257[ 	]+vqmaccu.vv[ 	]+v4,v12,v8
++[ 	]+[0-9a-f]+:[ 	]+f285c257[ 	]+vqmaccu.vx[ 	]+v4,a1,v8
++[ 	]+[0-9a-f]+:[ 	]+f0860257[ 	]+vqmaccu.vv[ 	]+v4,v12,v8,v0.t
++[ 	]+[0-9a-f]+:[ 	]+f085c257[ 	]+vqmaccu.vx[ 	]+v4,a1,v8,v0.t
++[ 	]+[0-9a-f]+:[ 	]+f6860257[ 	]+vqmacc.vv[ 	]+v4,v12,v8
++[ 	]+[0-9a-f]+:[ 	]+f685c257[ 	]+vqmacc.vx[ 	]+v4,a1,v8
++[ 	]+[0-9a-f]+:[ 	]+f4860257[ 	]+vqmacc.vv[ 	]+v4,v12,v8,v0.t
++[ 	]+[0-9a-f]+:[ 	]+f485c257[ 	]+vqmacc.vx[ 	]+v4,a1,v8,v0.t
++[ 	]+[0-9a-f]+:[ 	]+fe860257[ 	]+vqmaccsu.vv[ 	]+v4,v12,v8
++[ 	]+[0-9a-f]+:[ 	]+fe85c257[ 	]+vqmaccsu.vx[ 	]+v4,a1,v8
++[ 	]+[0-9a-f]+:[ 	]+fc860257[ 	]+vqmaccsu.vv[ 	]+v4,v12,v8,v0.t
++[ 	]+[0-9a-f]+:[ 	]+fc85c257[ 	]+vqmaccsu.vx[ 	]+v4,a1,v8,v0.t
++[ 	]+[0-9a-f]+:[ 	]+fa85c257[ 	]+vqmaccus.vx[ 	]+v4,a1,v8
++[ 	]+[0-9a-f]+:[ 	]+f885c257[ 	]+vqmaccus.vx[ 	]+v4,a1,v8,v0.t
++[ 	]+[0-9a-f]+:[ 	]+82862257[ 	]+vdivu.vv[ 	]+v4,v8,v12
++[ 	]+[0-9a-f]+:[ 	]+8285e257[ 	]+vdivu.vx[ 	]+v4,v8,a1
++[ 	]+[0-9a-f]+:[ 	]+80862257[ 	]+vdivu.vv[ 	]+v4,v8,v12,v0.t
++[ 	]+[0-9a-f]+:[ 	]+8085e257[ 	]+vdivu.vx[ 	]+v4,v8,a1,v0.t
++[ 	]+[0-9a-f]+:[ 	]+86862257[ 	]+vdiv.vv[ 	]+v4,v8,v12
++[ 	]+[0-9a-f]+:[ 	]+8685e257[ 	]+vdiv.vx[ 	]+v4,v8,a1
++[ 	]+[0-9a-f]+:[ 	]+84862257[ 	]+vdiv.vv[ 	]+v4,v8,v12,v0.t
++[ 	]+[0-9a-f]+:[ 	]+8485e257[ 	]+vdiv.vx[ 	]+v4,v8,a1,v0.t
++[ 	]+[0-9a-f]+:[ 	]+8a862257[ 	]+vremu.vv[ 	]+v4,v8,v12
++[ 	]+[0-9a-f]+:[ 	]+8a85e257[ 	]+vremu.vx[ 	]+v4,v8,a1
++[ 	]+[0-9a-f]+:[ 	]+88862257[ 	]+vremu.vv[ 	]+v4,v8,v12,v0.t
++[ 	]+[0-9a-f]+:[ 	]+8885e257[ 	]+vremu.vx[ 	]+v4,v8,a1,v0.t
++[ 	]+[0-9a-f]+:[ 	]+8e862257[ 	]+vrem.vv[ 	]+v4,v8,v12
++[ 	]+[0-9a-f]+:[ 	]+8e85e257[ 	]+vrem.vx[ 	]+v4,v8,a1
++[ 	]+[0-9a-f]+:[ 	]+8c862257[ 	]+vrem.vv[ 	]+v4,v8,v12,v0.t
++[ 	]+[0-9a-f]+:[ 	]+8c85e257[ 	]+vrem.vx[ 	]+v4,v8,a1,v0.t
++[ 	]+[0-9a-f]+:[ 	]+5c860257[ 	]+vmerge.vvm[ 	]+v4,v8,v12,v0
++[ 	]+[0-9a-f]+:[ 	]+5c85c257[ 	]+vmerge.vxm[ 	]+v4,v8,a1,v0
++[ 	]+[0-9a-f]+:[ 	]+5c87b257[ 	]+vmerge.vim[ 	]+v4,v8,15,v0
++[ 	]+[0-9a-f]+:[ 	]+5c883257[ 	]+vmerge.vim[ 	]+v4,v8,-16,v0
++[ 	]+[0-9a-f]+:[ 	]+5e060457[ 	]+vmv.v.v[ 	]+v8,v12
++[ 	]+[0-9a-f]+:[ 	]+5e05c457[ 	]+vmv.v.x[ 	]+v8,a1
++[ 	]+[0-9a-f]+:[ 	]+5e07b457[ 	]+vmv.v.i[ 	]+v8,15
++[ 	]+[0-9a-f]+:[ 	]+5e083457[ 	]+vmv.v.i[ 	]+v8,-16
++[ 	]+[0-9a-f]+:[ 	]+82860257[ 	]+vsaddu.vv[ 	]+v4,v8,v12
++[ 	]+[0-9a-f]+:[ 	]+8285c257[ 	]+vsaddu.vx[ 	]+v4,v8,a1
++[ 	]+[0-9a-f]+:[ 	]+8287b257[ 	]+vsaddu.vi[ 	]+v4,v8,15
++[ 	]+[0-9a-f]+:[ 	]+82883257[ 	]+vsaddu.vi[ 	]+v4,v8,-16
++[ 	]+[0-9a-f]+:[ 	]+80860257[ 	]+vsaddu.vv[ 	]+v4,v8,v12,v0.t
++[ 	]+[0-9a-f]+:[ 	]+8085c257[ 	]+vsaddu.vx[ 	]+v4,v8,a1,v0.t
++[ 	]+[0-9a-f]+:[ 	]+8087b257[ 	]+vsaddu.vi[ 	]+v4,v8,15,v0.t
++[ 	]+[0-9a-f]+:[ 	]+80883257[ 	]+vsaddu.vi[ 	]+v4,v8,-16,v0.t
++[ 	]+[0-9a-f]+:[ 	]+86860257[ 	]+vsadd.vv[ 	]+v4,v8,v12
++[ 	]+[0-9a-f]+:[ 	]+8685c257[ 	]+vsadd.vx[ 	]+v4,v8,a1
++[ 	]+[0-9a-f]+:[ 	]+8687b257[ 	]+vsadd.vi[ 	]+v4,v8,15
++[ 	]+[0-9a-f]+:[ 	]+86883257[ 	]+vsadd.vi[ 	]+v4,v8,-16
++[ 	]+[0-9a-f]+:[ 	]+84860257[ 	]+vsadd.vv[ 	]+v4,v8,v12,v0.t
++[ 	]+[0-9a-f]+:[ 	]+8485c257[ 	]+vsadd.vx[ 	]+v4,v8,a1,v0.t
++[ 	]+[0-9a-f]+:[ 	]+8487b257[ 	]+vsadd.vi[ 	]+v4,v8,15,v0.t
++[ 	]+[0-9a-f]+:[ 	]+84883257[ 	]+vsadd.vi[ 	]+v4,v8,-16,v0.t
++[ 	]+[0-9a-f]+:[ 	]+8a860257[ 	]+vssubu.vv[ 	]+v4,v8,v12
++[ 	]+[0-9a-f]+:[ 	]+8a85c257[ 	]+vssubu.vx[ 	]+v4,v8,a1
++[ 	]+[0-9a-f]+:[ 	]+88860257[ 	]+vssubu.vv[ 	]+v4,v8,v12,v0.t
++[ 	]+[0-9a-f]+:[ 	]+8885c257[ 	]+vssubu.vx[ 	]+v4,v8,a1,v0.t
++[ 	]+[0-9a-f]+:[ 	]+8e860257[ 	]+vssub.vv[ 	]+v4,v8,v12
++[ 	]+[0-9a-f]+:[ 	]+8e85c257[ 	]+vssub.vx[ 	]+v4,v8,a1
++[ 	]+[0-9a-f]+:[ 	]+8c860257[ 	]+vssub.vv[ 	]+v4,v8,v12,v0.t
++[ 	]+[0-9a-f]+:[ 	]+8c85c257[ 	]+vssub.vx[ 	]+v4,v8,a1,v0.t
++[ 	]+[0-9a-f]+:[ 	]+22862257[ 	]+vaaddu.vv[ 	]+v4,v8,v12
++[ 	]+[0-9a-f]+:[ 	]+2285e257[ 	]+vaaddu.vx[ 	]+v4,v8,a1
++[ 	]+[0-9a-f]+:[ 	]+20862257[ 	]+vaaddu.vv[ 	]+v4,v8,v12,v0.t
++[ 	]+[0-9a-f]+:[ 	]+2085e257[ 	]+vaaddu.vx[ 	]+v4,v8,a1,v0.t
++[ 	]+[0-9a-f]+:[ 	]+26862257[ 	]+vaadd.vv[ 	]+v4,v8,v12
++[ 	]+[0-9a-f]+:[ 	]+2685e257[ 	]+vaadd.vx[ 	]+v4,v8,a1
++[ 	]+[0-9a-f]+:[ 	]+24862257[ 	]+vaadd.vv[ 	]+v4,v8,v12,v0.t
++[ 	]+[0-9a-f]+:[ 	]+2485e257[ 	]+vaadd.vx[ 	]+v4,v8,a1,v0.t
++[ 	]+[0-9a-f]+:[ 	]+2a862257[ 	]+vasubu.vv[ 	]+v4,v8,v12
++[ 	]+[0-9a-f]+:[ 	]+2a85e257[ 	]+vasubu.vx[ 	]+v4,v8,a1
++[ 	]+[0-9a-f]+:[ 	]+28862257[ 	]+vasubu.vv[ 	]+v4,v8,v12,v0.t
++[ 	]+[0-9a-f]+:[ 	]+2885e257[ 	]+vasubu.vx[ 	]+v4,v8,a1,v0.t
++[ 	]+[0-9a-f]+:[ 	]+2e862257[ 	]+vasub.vv[ 	]+v4,v8,v12
++[ 	]+[0-9a-f]+:[ 	]+2e85e257[ 	]+vasub.vx[ 	]+v4,v8,a1
++[ 	]+[0-9a-f]+:[ 	]+2c862257[ 	]+vasub.vv[ 	]+v4,v8,v12,v0.t
++[ 	]+[0-9a-f]+:[ 	]+2c85e257[ 	]+vasub.vx[ 	]+v4,v8,a1,v0.t
++[ 	]+[0-9a-f]+:[ 	]+9e860257[ 	]+vsmul.vv[ 	]+v4,v8,v12
++[ 	]+[0-9a-f]+:[ 	]+9e85c257[ 	]+vsmul.vx[ 	]+v4,v8,a1
++[ 	]+[0-9a-f]+:[ 	]+9c860257[ 	]+vsmul.vv[ 	]+v4,v8,v12,v0.t
++[ 	]+[0-9a-f]+:[ 	]+9c85c257[ 	]+vsmul.vx[ 	]+v4,v8,a1,v0.t
++[ 	]+[0-9a-f]+:[ 	]+aa860257[ 	]+vssrl.vv[ 	]+v4,v8,v12
++[ 	]+[0-9a-f]+:[ 	]+aa85c257[ 	]+vssrl.vx[ 	]+v4,v8,a1
++[ 	]+[0-9a-f]+:[ 	]+aa80b257[ 	]+vssrl.vi[ 	]+v4,v8,1
++[ 	]+[0-9a-f]+:[ 	]+aa8fb257[ 	]+vssrl.vi[ 	]+v4,v8,31
++[ 	]+[0-9a-f]+:[ 	]+a8860257[ 	]+vssrl.vv[ 	]+v4,v8,v12,v0.t
++[ 	]+[0-9a-f]+:[ 	]+a885c257[ 	]+vssrl.vx[ 	]+v4,v8,a1,v0.t
++[ 	]+[0-9a-f]+:[ 	]+a880b257[ 	]+vssrl.vi[ 	]+v4,v8,1,v0.t
++[ 	]+[0-9a-f]+:[ 	]+a88fb257[ 	]+vssrl.vi[ 	]+v4,v8,31,v0.t
++[ 	]+[0-9a-f]+:[ 	]+ae860257[ 	]+vssra.vv[ 	]+v4,v8,v12
++[ 	]+[0-9a-f]+:[ 	]+ae85c257[ 	]+vssra.vx[ 	]+v4,v8,a1
++[ 	]+[0-9a-f]+:[ 	]+ae80b257[ 	]+vssra.vi[ 	]+v4,v8,1
++[ 	]+[0-9a-f]+:[ 	]+ae8fb257[ 	]+vssra.vi[ 	]+v4,v8,31
++[ 	]+[0-9a-f]+:[ 	]+ac860257[ 	]+vssra.vv[ 	]+v4,v8,v12,v0.t
++[ 	]+[0-9a-f]+:[ 	]+ac85c257[ 	]+vssra.vx[ 	]+v4,v8,a1,v0.t
++[ 	]+[0-9a-f]+:[ 	]+ac80b257[ 	]+vssra.vi[ 	]+v4,v8,1,v0.t
++[ 	]+[0-9a-f]+:[ 	]+ac8fb257[ 	]+vssra.vi[ 	]+v4,v8,31,v0.t
++[ 	]+[0-9a-f]+:[ 	]+ba860257[ 	]+vnclipu.wv[ 	]+v4,v8,v12
++[ 	]+[0-9a-f]+:[ 	]+ba85c257[ 	]+vnclipu.wx[ 	]+v4,v8,a1
++[ 	]+[0-9a-f]+:[ 	]+ba80b257[ 	]+vnclipu.wi[ 	]+v4,v8,1
++[ 	]+[0-9a-f]+:[ 	]+ba8fb257[ 	]+vnclipu.wi[ 	]+v4,v8,31
++[ 	]+[0-9a-f]+:[ 	]+b8860257[ 	]+vnclipu.wv[ 	]+v4,v8,v12,v0.t
++[ 	]+[0-9a-f]+:[ 	]+b885c257[ 	]+vnclipu.wx[ 	]+v4,v8,a1,v0.t
++[ 	]+[0-9a-f]+:[ 	]+b880b257[ 	]+vnclipu.wi[ 	]+v4,v8,1,v0.t
++[ 	]+[0-9a-f]+:[ 	]+b88fb257[ 	]+vnclipu.wi[ 	]+v4,v8,31,v0.t
++[ 	]+[0-9a-f]+:[ 	]+be860257[ 	]+vnclip.wv[ 	]+v4,v8,v12
++[ 	]+[0-9a-f]+:[ 	]+be85c257[ 	]+vnclip.wx[ 	]+v4,v8,a1
++[ 	]+[0-9a-f]+:[ 	]+be80b257[ 	]+vnclip.wi[ 	]+v4,v8,1
++[ 	]+[0-9a-f]+:[ 	]+be8fb257[ 	]+vnclip.wi[ 	]+v4,v8,31
++[ 	]+[0-9a-f]+:[ 	]+bc860257[ 	]+vnclip.wv[ 	]+v4,v8,v12,v0.t
++[ 	]+[0-9a-f]+:[ 	]+bc85c257[ 	]+vnclip.wx[ 	]+v4,v8,a1,v0.t
++[ 	]+[0-9a-f]+:[ 	]+bc80b257[ 	]+vnclip.wi[ 	]+v4,v8,1,v0.t
++[ 	]+[0-9a-f]+:[ 	]+bc8fb257[ 	]+vnclip.wi[ 	]+v4,v8,31,v0.t
++[ 	]+[0-9a-f]+:[ 	]+02861257[ 	]+vfadd.vv[ 	]+v4,v8,v12
++[ 	]+[0-9a-f]+:[ 	]+02865257[ 	]+vfadd.vf[ 	]+v4,v8,fa2
++[ 	]+[0-9a-f]+:[ 	]+00861257[ 	]+vfadd.vv[ 	]+v4,v8,v12,v0.t
++[ 	]+[0-9a-f]+:[ 	]+00865257[ 	]+vfadd.vf[ 	]+v4,v8,fa2,v0.t
++[ 	]+[0-9a-f]+:[ 	]+0a861257[ 	]+vfsub.vv[ 	]+v4,v8,v12
++[ 	]+[0-9a-f]+:[ 	]+0a865257[ 	]+vfsub.vf[ 	]+v4,v8,fa2
++[ 	]+[0-9a-f]+:[ 	]+08861257[ 	]+vfsub.vv[ 	]+v4,v8,v12,v0.t
++[ 	]+[0-9a-f]+:[ 	]+08865257[ 	]+vfsub.vf[ 	]+v4,v8,fa2,v0.t
++[ 	]+[0-9a-f]+:[ 	]+9e865257[ 	]+vfrsub.vf[ 	]+v4,v8,fa2
++[ 	]+[0-9a-f]+:[ 	]+9c865257[ 	]+vfrsub.vf[ 	]+v4,v8,fa2,v0.t
++[ 	]+[0-9a-f]+:[ 	]+c2861257[ 	]+vfwadd.vv[ 	]+v4,v8,v12
++[ 	]+[0-9a-f]+:[ 	]+c2865257[ 	]+vfwadd.vf[ 	]+v4,v8,fa2
++[ 	]+[0-9a-f]+:[ 	]+c0861257[ 	]+vfwadd.vv[ 	]+v4,v8,v12,v0.t
++[ 	]+[0-9a-f]+:[ 	]+c0865257[ 	]+vfwadd.vf[ 	]+v4,v8,fa2,v0.t
++[ 	]+[0-9a-f]+:[ 	]+ca861257[ 	]+vfwsub.vv[ 	]+v4,v8,v12
++[ 	]+[0-9a-f]+:[ 	]+ca865257[ 	]+vfwsub.vf[ 	]+v4,v8,fa2
++[ 	]+[0-9a-f]+:[ 	]+c8861257[ 	]+vfwsub.vv[ 	]+v4,v8,v12,v0.t
++[ 	]+[0-9a-f]+:[ 	]+c8865257[ 	]+vfwsub.vf[ 	]+v4,v8,fa2,v0.t
++[ 	]+[0-9a-f]+:[ 	]+d2861257[ 	]+vfwadd.wv[ 	]+v4,v8,v12
++[ 	]+[0-9a-f]+:[ 	]+d2865257[ 	]+vfwadd.wf[ 	]+v4,v8,fa2
++[ 	]+[0-9a-f]+:[ 	]+d0861257[ 	]+vfwadd.wv[ 	]+v4,v8,v12,v0.t
++[ 	]+[0-9a-f]+:[ 	]+d0865257[ 	]+vfwadd.wf[ 	]+v4,v8,fa2,v0.t
++[ 	]+[0-9a-f]+:[ 	]+da861257[ 	]+vfwsub.wv[ 	]+v4,v8,v12
++[ 	]+[0-9a-f]+:[ 	]+da865257[ 	]+vfwsub.wf[ 	]+v4,v8,fa2
++[ 	]+[0-9a-f]+:[ 	]+d8861257[ 	]+vfwsub.wv[ 	]+v4,v8,v12,v0.t
++[ 	]+[0-9a-f]+:[ 	]+d8865257[ 	]+vfwsub.wf[ 	]+v4,v8,fa2,v0.t
++[ 	]+[0-9a-f]+:[ 	]+92861257[ 	]+vfmul.vv[ 	]+v4,v8,v12
++[ 	]+[0-9a-f]+:[ 	]+92865257[ 	]+vfmul.vf[ 	]+v4,v8,fa2
++[ 	]+[0-9a-f]+:[ 	]+90861257[ 	]+vfmul.vv[ 	]+v4,v8,v12,v0.t
++[ 	]+[0-9a-f]+:[ 	]+90865257[ 	]+vfmul.vf[ 	]+v4,v8,fa2,v0.t
++[ 	]+[0-9a-f]+:[ 	]+82861257[ 	]+vfdiv.vv[ 	]+v4,v8,v12
++[ 	]+[0-9a-f]+:[ 	]+82865257[ 	]+vfdiv.vf[ 	]+v4,v8,fa2
++[ 	]+[0-9a-f]+:[ 	]+80861257[ 	]+vfdiv.vv[ 	]+v4,v8,v12,v0.t
++[ 	]+[0-9a-f]+:[ 	]+80865257[ 	]+vfdiv.vf[ 	]+v4,v8,fa2,v0.t
++[ 	]+[0-9a-f]+:[ 	]+86865257[ 	]+vfrdiv.vf[ 	]+v4,v8,fa2
++[ 	]+[0-9a-f]+:[ 	]+84865257[ 	]+vfrdiv.vf[ 	]+v4,v8,fa2,v0.t
++[ 	]+[0-9a-f]+:[ 	]+e2861257[ 	]+vfwmul.vv[ 	]+v4,v8,v12
++[ 	]+[0-9a-f]+:[ 	]+e2865257[ 	]+vfwmul.vf[ 	]+v4,v8,fa2
++[ 	]+[0-9a-f]+:[ 	]+e0861257[ 	]+vfwmul.vv[ 	]+v4,v8,v12,v0.t
++[ 	]+[0-9a-f]+:[ 	]+e0865257[ 	]+vfwmul.vf[ 	]+v4,v8,fa2,v0.t
++[ 	]+[0-9a-f]+:[ 	]+a2861257[ 	]+vfmadd.vv[ 	]+v4,v12,v8
++[ 	]+[0-9a-f]+:[ 	]+a2865257[ 	]+vfmadd.vf[ 	]+v4,fa2,v8
++[ 	]+[0-9a-f]+:[ 	]+a6861257[ 	]+vfnmadd.vv[ 	]+v4,v12,v8
++[ 	]+[0-9a-f]+:[ 	]+a6865257[ 	]+vfnmadd.vf[ 	]+v4,fa2,v8
++[ 	]+[0-9a-f]+:[ 	]+aa861257[ 	]+vfmsub.vv[ 	]+v4,v12,v8
++[ 	]+[0-9a-f]+:[ 	]+aa865257[ 	]+vfmsub.vf[ 	]+v4,fa2,v8
++[ 	]+[0-9a-f]+:[ 	]+ae861257[ 	]+vfnmsub.vv[ 	]+v4,v12,v8
++[ 	]+[0-9a-f]+:[ 	]+ae865257[ 	]+vfnmsub.vf[ 	]+v4,fa2,v8
++[ 	]+[0-9a-f]+:[ 	]+a0861257[ 	]+vfmadd.vv[ 	]+v4,v12,v8,v0.t
++[ 	]+[0-9a-f]+:[ 	]+a0865257[ 	]+vfmadd.vf[ 	]+v4,fa2,v8,v0.t
++[ 	]+[0-9a-f]+:[ 	]+a4861257[ 	]+vfnmadd.vv[ 	]+v4,v12,v8,v0.t
++[ 	]+[0-9a-f]+:[ 	]+a4865257[ 	]+vfnmadd.vf[ 	]+v4,fa2,v8,v0.t
++[ 	]+[0-9a-f]+:[ 	]+a8861257[ 	]+vfmsub.vv[ 	]+v4,v12,v8,v0.t
++[ 	]+[0-9a-f]+:[ 	]+a8865257[ 	]+vfmsub.vf[ 	]+v4,fa2,v8,v0.t
++[ 	]+[0-9a-f]+:[ 	]+ac861257[ 	]+vfnmsub.vv[ 	]+v4,v12,v8,v0.t
++[ 	]+[0-9a-f]+:[ 	]+ac865257[ 	]+vfnmsub.vf[ 	]+v4,fa2,v8,v0.t
++[ 	]+[0-9a-f]+:[ 	]+b2861257[ 	]+vfmacc.vv[ 	]+v4,v12,v8
++[ 	]+[0-9a-f]+:[ 	]+b2865257[ 	]+vfmacc.vf[ 	]+v4,fa2,v8
++[ 	]+[0-9a-f]+:[ 	]+b6861257[ 	]+vfnmacc.vv[ 	]+v4,v12,v8
++[ 	]+[0-9a-f]+:[ 	]+b6865257[ 	]+vfnmacc.vf[ 	]+v4,fa2,v8
++[ 	]+[0-9a-f]+:[ 	]+ba861257[ 	]+vfmsac.vv[ 	]+v4,v12,v8
++[ 	]+[0-9a-f]+:[ 	]+ba865257[ 	]+vfmsac.vf[ 	]+v4,fa2,v8
++[ 	]+[0-9a-f]+:[ 	]+be861257[ 	]+vfnmsac.vv[ 	]+v4,v12,v8
++[ 	]+[0-9a-f]+:[ 	]+be865257[ 	]+vfnmsac.vf[ 	]+v4,fa2,v8
++[ 	]+[0-9a-f]+:[ 	]+b0861257[ 	]+vfmacc.vv[ 	]+v4,v12,v8,v0.t
++[ 	]+[0-9a-f]+:[ 	]+b0865257[ 	]+vfmacc.vf[ 	]+v4,fa2,v8,v0.t
++[ 	]+[0-9a-f]+:[ 	]+b4861257[ 	]+vfnmacc.vv[ 	]+v4,v12,v8,v0.t
++[ 	]+[0-9a-f]+:[ 	]+b4865257[ 	]+vfnmacc.vf[ 	]+v4,fa2,v8,v0.t
++[ 	]+[0-9a-f]+:[ 	]+b8861257[ 	]+vfmsac.vv[ 	]+v4,v12,v8,v0.t
++[ 	]+[0-9a-f]+:[ 	]+b8865257[ 	]+vfmsac.vf[ 	]+v4,fa2,v8,v0.t
++[ 	]+[0-9a-f]+:[ 	]+bc861257[ 	]+vfnmsac.vv[ 	]+v4,v12,v8,v0.t
++[ 	]+[0-9a-f]+:[ 	]+bc865257[ 	]+vfnmsac.vf[ 	]+v4,fa2,v8,v0.t
++[ 	]+[0-9a-f]+:[ 	]+f2861257[ 	]+vfwmacc.vv[ 	]+v4,v12,v8
++[ 	]+[0-9a-f]+:[ 	]+f2865257[ 	]+vfwmacc.vf[ 	]+v4,fa2,v8
++[ 	]+[0-9a-f]+:[ 	]+f6861257[ 	]+vfwnmacc.vv[ 	]+v4,v12,v8
++[ 	]+[0-9a-f]+:[ 	]+f6865257[ 	]+vfwnmacc.vf[ 	]+v4,fa2,v8
++[ 	]+[0-9a-f]+:[ 	]+fa861257[ 	]+vfwmsac.vv[ 	]+v4,v12,v8
++[ 	]+[0-9a-f]+:[ 	]+fa865257[ 	]+vfwmsac.vf[ 	]+v4,fa2,v8
++[ 	]+[0-9a-f]+:[ 	]+fe861257[ 	]+vfwnmsac.vv[ 	]+v4,v12,v8
++[ 	]+[0-9a-f]+:[ 	]+fe865257[ 	]+vfwnmsac.vf[ 	]+v4,fa2,v8
++[ 	]+[0-9a-f]+:[ 	]+f0861257[ 	]+vfwmacc.vv[ 	]+v4,v12,v8,v0.t
++[ 	]+[0-9a-f]+:[ 	]+f0865257[ 	]+vfwmacc.vf[ 	]+v4,fa2,v8,v0.t
++[ 	]+[0-9a-f]+:[ 	]+f4861257[ 	]+vfwnmacc.vv[ 	]+v4,v12,v8,v0.t
++[ 	]+[0-9a-f]+:[ 	]+f4865257[ 	]+vfwnmacc.vf[ 	]+v4,fa2,v8,v0.t
++[ 	]+[0-9a-f]+:[ 	]+f8861257[ 	]+vfwmsac.vv[ 	]+v4,v12,v8,v0.t
++[ 	]+[0-9a-f]+:[ 	]+f8865257[ 	]+vfwmsac.vf[ 	]+v4,fa2,v8,v0.t
++[ 	]+[0-9a-f]+:[ 	]+fc861257[ 	]+vfwnmsac.vv[ 	]+v4,v12,v8,v0.t
++[ 	]+[0-9a-f]+:[ 	]+fc865257[ 	]+vfwnmsac.vf[ 	]+v4,fa2,v8,v0.t
++[ 	]+[0-9a-f]+:[ 	]+4e801257[ 	]+vfsqrt.v[ 	]+v4,v8
++[ 	]+[0-9a-f]+:[ 	]+4c801257[ 	]+vfsqrt.v[ 	]+v4,v8,v0.t
++[ 	]+[0-9a-f]+:[ 	]+12861257[ 	]+vfmin.vv[ 	]+v4,v8,v12
++[ 	]+[0-9a-f]+:[ 	]+12865257[ 	]+vfmin.vf[ 	]+v4,v8,fa2
++[ 	]+[0-9a-f]+:[ 	]+1a861257[ 	]+vfmax.vv[ 	]+v4,v8,v12
++[ 	]+[0-9a-f]+:[ 	]+1a865257[ 	]+vfmax.vf[ 	]+v4,v8,fa2
++[ 	]+[0-9a-f]+:[ 	]+10861257[ 	]+vfmin.vv[ 	]+v4,v8,v12,v0.t
++[ 	]+[0-9a-f]+:[ 	]+10865257[ 	]+vfmin.vf[ 	]+v4,v8,fa2,v0.t
++[ 	]+[0-9a-f]+:[ 	]+18861257[ 	]+vfmax.vv[ 	]+v4,v8,v12,v0.t
++[ 	]+[0-9a-f]+:[ 	]+18865257[ 	]+vfmax.vf[ 	]+v4,v8,fa2,v0.t
++[ 	]+[0-9a-f]+:[ 	]+22861257[ 	]+vfsgnj.vv[ 	]+v4,v8,v12
++[ 	]+[0-9a-f]+:[ 	]+22865257[ 	]+vfsgnj.vf[ 	]+v4,v8,fa2
++[ 	]+[0-9a-f]+:[ 	]+26861257[ 	]+vfsgnjn.vv[ 	]+v4,v8,v12
++[ 	]+[0-9a-f]+:[ 	]+26865257[ 	]+vfsgnjn.vf[ 	]+v4,v8,fa2
++[ 	]+[0-9a-f]+:[ 	]+2a861257[ 	]+vfsgnjx.vv[ 	]+v4,v8,v12
++[ 	]+[0-9a-f]+:[ 	]+2a865257[ 	]+vfsgnjx.vf[ 	]+v4,v8,fa2
++[ 	]+[0-9a-f]+:[ 	]+20861257[ 	]+vfsgnj.vv[ 	]+v4,v8,v12,v0.t
++[ 	]+[0-9a-f]+:[ 	]+20865257[ 	]+vfsgnj.vf[ 	]+v4,v8,fa2,v0.t
++[ 	]+[0-9a-f]+:[ 	]+24861257[ 	]+vfsgnjn.vv[ 	]+v4,v8,v12,v0.t
++[ 	]+[0-9a-f]+:[ 	]+24865257[ 	]+vfsgnjn.vf[ 	]+v4,v8,fa2,v0.t
++[ 	]+[0-9a-f]+:[ 	]+28861257[ 	]+vfsgnjx.vv[ 	]+v4,v8,v12,v0.t
++[ 	]+[0-9a-f]+:[ 	]+28865257[ 	]+vfsgnjx.vf[ 	]+v4,v8,fa2,v0.t
++[ 	]+[0-9a-f]+:[ 	]+6ec41257[ 	]+vmflt.vv[ 	]+v4,v12,v8
++[ 	]+[0-9a-f]+:[ 	]+66c41257[ 	]+vmfle.vv[ 	]+v4,v12,v8
++[ 	]+[0-9a-f]+:[ 	]+6cc41257[ 	]+vmflt.vv[ 	]+v4,v12,v8,v0.t
++[ 	]+[0-9a-f]+:[ 	]+64c41257[ 	]+vmfle.vv[ 	]+v4,v12,v8,v0.t
++[ 	]+[0-9a-f]+:[ 	]+62861257[ 	]+vmfeq.vv[ 	]+v4,v8,v12
++[ 	]+[0-9a-f]+:[ 	]+62865257[ 	]+vmfeq.vf[ 	]+v4,v8,fa2
++[ 	]+[0-9a-f]+:[ 	]+72861257[ 	]+vmfne.vv[ 	]+v4,v8,v12
++[ 	]+[0-9a-f]+:[ 	]+72865257[ 	]+vmfne.vf[ 	]+v4,v8,fa2
++[ 	]+[0-9a-f]+:[ 	]+6e861257[ 	]+vmflt.vv[ 	]+v4,v8,v12
++[ 	]+[0-9a-f]+:[ 	]+6e865257[ 	]+vmflt.vf[ 	]+v4,v8,fa2
++[ 	]+[0-9a-f]+:[ 	]+66861257[ 	]+vmfle.vv[ 	]+v4,v8,v12
++[ 	]+[0-9a-f]+:[ 	]+66865257[ 	]+vmfle.vf[ 	]+v4,v8,fa2
++[ 	]+[0-9a-f]+:[ 	]+76865257[ 	]+vmfgt.vf[ 	]+v4,v8,fa2
++[ 	]+[0-9a-f]+:[ 	]+7e865257[ 	]+vmfge.vf[ 	]+v4,v8,fa2
++[ 	]+[0-9a-f]+:[ 	]+60861257[ 	]+vmfeq.vv[ 	]+v4,v8,v12,v0.t
++[ 	]+[0-9a-f]+:[ 	]+60865257[ 	]+vmfeq.vf[ 	]+v4,v8,fa2,v0.t
++[ 	]+[0-9a-f]+:[ 	]+70861257[ 	]+vmfne.vv[ 	]+v4,v8,v12,v0.t
++[ 	]+[0-9a-f]+:[ 	]+70865257[ 	]+vmfne.vf[ 	]+v4,v8,fa2,v0.t
++[ 	]+[0-9a-f]+:[ 	]+6c861257[ 	]+vmflt.vv[ 	]+v4,v8,v12,v0.t
++[ 	]+[0-9a-f]+:[ 	]+6c865257[ 	]+vmflt.vf[ 	]+v4,v8,fa2,v0.t
++[ 	]+[0-9a-f]+:[ 	]+64861257[ 	]+vmfle.vv[ 	]+v4,v8,v12,v0.t
++[ 	]+[0-9a-f]+:[ 	]+64865257[ 	]+vmfle.vf[ 	]+v4,v8,fa2,v0.t
++[ 	]+[0-9a-f]+:[ 	]+74865257[ 	]+vmfgt.vf[ 	]+v4,v8,fa2,v0.t
++[ 	]+[0-9a-f]+:[ 	]+7c865257[ 	]+vmfge.vf[ 	]+v4,v8,fa2,v0.t
++[ 	]+[0-9a-f]+:[ 	]+4e881257[ 	]+vfclass.v[ 	]+v4,v8
++[ 	]+[0-9a-f]+:[ 	]+4c881257[ 	]+vfclass.v[ 	]+v4,v8,v0.t
++[ 	]+[0-9a-f]+:[ 	]+5c865257[ 	]+vfmerge.vfm[ 	]+v4,v8,fa2,v0
++[ 	]+[0-9a-f]+:[ 	]+5e05d257[ 	]+vfmv.v.f[ 	]+v4,fa1
++[ 	]+[0-9a-f]+:[ 	]+4a801257[ 	]+vfcvt.xu.f.v[ 	]+v4,v8
++[ 	]+[0-9a-f]+:[ 	]+4a809257[ 	]+vfcvt.x.f.v[ 	]+v4,v8
++[ 	]+[0-9a-f]+:[ 	]+4a831257[ 	]+vfcvt.rtz.xu.f.v[ 	]+v4,v8
++[ 	]+[0-9a-f]+:[ 	]+4a839257[ 	]+vfcvt.rtz.x.f.v[ 	]+v4,v8
++[ 	]+[0-9a-f]+:[ 	]+4a811257[ 	]+vfcvt.f.xu.v[ 	]+v4,v8
++[ 	]+[0-9a-f]+:[ 	]+4a819257[ 	]+vfcvt.f.x.v[ 	]+v4,v8
++[ 	]+[0-9a-f]+:[ 	]+48801257[ 	]+vfcvt.xu.f.v[ 	]+v4,v8,v0.t
++[ 	]+[0-9a-f]+:[ 	]+48809257[ 	]+vfcvt.x.f.v[ 	]+v4,v8,v0.t
++[ 	]+[0-9a-f]+:[ 	]+48831257[ 	]+vfcvt.rtz.xu.f.v[ 	]+v4,v8,v0.t
++[ 	]+[0-9a-f]+:[ 	]+48839257[ 	]+vfcvt.rtz.x.f.v[ 	]+v4,v8,v0.t
++[ 	]+[0-9a-f]+:[ 	]+48811257[ 	]+vfcvt.f.xu.v[ 	]+v4,v8,v0.t
++[ 	]+[0-9a-f]+:[ 	]+48819257[ 	]+vfcvt.f.x.v[ 	]+v4,v8,v0.t
++[ 	]+[0-9a-f]+:[ 	]+4a841257[ 	]+vfwcvt.xu.f.v[ 	]+v4,v8
++[ 	]+[0-9a-f]+:[ 	]+4a849257[ 	]+vfwcvt.x.f.v[ 	]+v4,v8
++[ 	]+[0-9a-f]+:[ 	]+4a871257[ 	]+vfwcvt.rtz.xu.f.v[ 	]+v4,v8
++[ 	]+[0-9a-f]+:[ 	]+4a879257[ 	]+vfwcvt.rtz.x.f.v[ 	]+v4,v8
++[ 	]+[0-9a-f]+:[ 	]+4a851257[ 	]+vfwcvt.f.xu.v[ 	]+v4,v8
++[ 	]+[0-9a-f]+:[ 	]+4a859257[ 	]+vfwcvt.f.x.v[ 	]+v4,v8
++[ 	]+[0-9a-f]+:[ 	]+4a861257[ 	]+vfwcvt.f.f.v[ 	]+v4,v8
++[ 	]+[0-9a-f]+:[ 	]+48841257[ 	]+vfwcvt.xu.f.v[ 	]+v4,v8,v0.t
++[ 	]+[0-9a-f]+:[ 	]+48849257[ 	]+vfwcvt.x.f.v[ 	]+v4,v8,v0.t
++[ 	]+[0-9a-f]+:[ 	]+48871257[ 	]+vfwcvt.rtz.xu.f.v[ 	]+v4,v8,v0.t
++[ 	]+[0-9a-f]+:[ 	]+48879257[ 	]+vfwcvt.rtz.x.f.v[ 	]+v4,v8,v0.t
++[ 	]+[0-9a-f]+:[ 	]+48851257[ 	]+vfwcvt.f.xu.v[ 	]+v4,v8,v0.t
++[ 	]+[0-9a-f]+:[ 	]+48859257[ 	]+vfwcvt.f.x.v[ 	]+v4,v8,v0.t
++[ 	]+[0-9a-f]+:[ 	]+48861257[ 	]+vfwcvt.f.f.v[ 	]+v4,v8,v0.t
++[ 	]+[0-9a-f]+:[ 	]+4a881257[ 	]+vfncvt.xu.f.w[ 	]+v4,v8
++[ 	]+[0-9a-f]+:[ 	]+4a889257[ 	]+vfncvt.x.f.w[ 	]+v4,v8
++[ 	]+[0-9a-f]+:[ 	]+4a8b1257[ 	]+vfncvt.rtz.xu.f.w[ 	]+v4,v8
++[ 	]+[0-9a-f]+:[ 	]+4a8b9257[ 	]+vfncvt.rtz.x.f.w[ 	]+v4,v8
++[ 	]+[0-9a-f]+:[ 	]+4a891257[ 	]+vfncvt.f.xu.w[ 	]+v4,v8
++[ 	]+[0-9a-f]+:[ 	]+4a899257[ 	]+vfncvt.f.x.w[ 	]+v4,v8
++[ 	]+[0-9a-f]+:[ 	]+4a8a1257[ 	]+vfncvt.f.f.w[ 	]+v4,v8
++[ 	]+[0-9a-f]+:[ 	]+4a8a9257[ 	]+vfncvt.rod.f.f.w[ 	]+v4,v8
++[ 	]+[0-9a-f]+:[ 	]+48881257[ 	]+vfncvt.xu.f.w[ 	]+v4,v8,v0.t
++[ 	]+[0-9a-f]+:[ 	]+48889257[ 	]+vfncvt.x.f.w[ 	]+v4,v8,v0.t
++[ 	]+[0-9a-f]+:[ 	]+488b1257[ 	]+vfncvt.rtz.xu.f.w[ 	]+v4,v8,v0.t
++[ 	]+[0-9a-f]+:[ 	]+488b9257[ 	]+vfncvt.rtz.x.f.w[ 	]+v4,v8,v0.t
++[ 	]+[0-9a-f]+:[ 	]+48891257[ 	]+vfncvt.f.xu.w[ 	]+v4,v8,v0.t
++[ 	]+[0-9a-f]+:[ 	]+48899257[ 	]+vfncvt.f.x.w[ 	]+v4,v8,v0.t
++[ 	]+[0-9a-f]+:[ 	]+488a1257[ 	]+vfncvt.f.f.w[ 	]+v4,v8,v0.t
++[ 	]+[0-9a-f]+:[ 	]+488a9257[ 	]+vfncvt.rod.f.f.w[ 	]+v4,v8,v0.t
++[ 	]+[0-9a-f]+:[ 	]+02862257[ 	]+vredsum.vs[ 	]+v4,v8,v12
++[ 	]+[0-9a-f]+:[ 	]+1a842257[ 	]+vredmaxu.vs[ 	]+v4,v8,v8
++[ 	]+[0-9a-f]+:[ 	]+1e842257[ 	]+vredmax.vs[ 	]+v4,v8,v8
++[ 	]+[0-9a-f]+:[ 	]+12842257[ 	]+vredminu.vs[ 	]+v4,v8,v8
++[ 	]+[0-9a-f]+:[ 	]+16842257[ 	]+vredmin.vs[ 	]+v4,v8,v8
++[ 	]+[0-9a-f]+:[ 	]+06862257[ 	]+vredand.vs[ 	]+v4,v8,v12
++[ 	]+[0-9a-f]+:[ 	]+0a862257[ 	]+vredor.vs[ 	]+v4,v8,v12
++[ 	]+[0-9a-f]+:[ 	]+0e862257[ 	]+vredxor.vs[ 	]+v4,v8,v12
++[ 	]+[0-9a-f]+:[ 	]+00862257[ 	]+vredsum.vs[ 	]+v4,v8,v12,v0.t
++[ 	]+[0-9a-f]+:[ 	]+18842257[ 	]+vredmaxu.vs[ 	]+v4,v8,v8,v0.t
++[ 	]+[0-9a-f]+:[ 	]+1c842257[ 	]+vredmax.vs[ 	]+v4,v8,v8,v0.t
++[ 	]+[0-9a-f]+:[ 	]+10842257[ 	]+vredminu.vs[ 	]+v4,v8,v8,v0.t
++[ 	]+[0-9a-f]+:[ 	]+14842257[ 	]+vredmin.vs[ 	]+v4,v8,v8,v0.t
++[ 	]+[0-9a-f]+:[ 	]+04862257[ 	]+vredand.vs[ 	]+v4,v8,v12,v0.t
++[ 	]+[0-9a-f]+:[ 	]+08862257[ 	]+vredor.vs[ 	]+v4,v8,v12,v0.t
++[ 	]+[0-9a-f]+:[ 	]+0c862257[ 	]+vredxor.vs[ 	]+v4,v8,v12,v0.t
++[ 	]+[0-9a-f]+:[ 	]+c2860257[ 	]+vwredsumu.vs[ 	]+v4,v8,v12
++[ 	]+[0-9a-f]+:[ 	]+c6860257[ 	]+vwredsum.vs[ 	]+v4,v8,v12
++[ 	]+[0-9a-f]+:[ 	]+c0860257[ 	]+vwredsumu.vs[ 	]+v4,v8,v12,v0.t
++[ 	]+[0-9a-f]+:[ 	]+c4860257[ 	]+vwredsum.vs[ 	]+v4,v8,v12,v0.t
++[ 	]+[0-9a-f]+:[ 	]+0e861257[ 	]+vfredosum.vs[ 	]+v4,v8,v12
++[ 	]+[0-9a-f]+:[ 	]+06861257[ 	]+vfredsum.vs[ 	]+v4,v8,v12
++[ 	]+[0-9a-f]+:[ 	]+1e861257[ 	]+vfredmax.vs[ 	]+v4,v8,v12
++[ 	]+[0-9a-f]+:[ 	]+16861257[ 	]+vfredmin.vs[ 	]+v4,v8,v12
++[ 	]+[0-9a-f]+:[ 	]+0c861257[ 	]+vfredosum.vs[ 	]+v4,v8,v12,v0.t
++[ 	]+[0-9a-f]+:[ 	]+04861257[ 	]+vfredsum.vs[ 	]+v4,v8,v12,v0.t
++[ 	]+[0-9a-f]+:[ 	]+1c861257[ 	]+vfredmax.vs[ 	]+v4,v8,v12,v0.t
++[ 	]+[0-9a-f]+:[ 	]+14861257[ 	]+vfredmin.vs[ 	]+v4,v8,v12,v0.t
++[ 	]+[0-9a-f]+:[ 	]+ce861257[ 	]+vfwredosum.vs[ 	]+v4,v8,v12
++[ 	]+[0-9a-f]+:[ 	]+c6861257[ 	]+vfwredsum.vs[ 	]+v4,v8,v12
++[ 	]+[0-9a-f]+:[ 	]+cc861257[ 	]+vfwredosum.vs[ 	]+v4,v8,v12,v0.t
++[ 	]+[0-9a-f]+:[ 	]+c4861257[ 	]+vfwredsum.vs[ 	]+v4,v8,v12,v0.t
++[ 	]+[0-9a-f]+:[ 	]+66842257[ 	]+vmmv.m[ 	]+v4,v8
++[ 	]+[0-9a-f]+:[ 	]+66842257[ 	]+vmmv.m[ 	]+v4,v8
++[ 	]+[0-9a-f]+:[ 	]+6e422257[ 	]+vmclr.m[ 	]+v4
++[ 	]+[0-9a-f]+:[ 	]+7e422257[ 	]+vmset.m[ 	]+v4
++[ 	]+[0-9a-f]+:[ 	]+76842257[ 	]+vmnot.m[ 	]+v4,v8
++[ 	]+[0-9a-f]+:[ 	]+66862257[ 	]+vmand.mm[ 	]+v4,v8,v12
++[ 	]+[0-9a-f]+:[ 	]+76862257[ 	]+vmnand.mm[ 	]+v4,v8,v12
++[ 	]+[0-9a-f]+:[ 	]+62862257[ 	]+vmandnot.mm[ 	]+v4,v8,v12
++[ 	]+[0-9a-f]+:[ 	]+6e862257[ 	]+vmxor.mm[ 	]+v4,v8,v12
++[ 	]+[0-9a-f]+:[ 	]+6a862257[ 	]+vmor.mm[ 	]+v4,v8,v12
++[ 	]+[0-9a-f]+:[ 	]+7a862257[ 	]+vmnor.mm[ 	]+v4,v8,v12
++[ 	]+[0-9a-f]+:[ 	]+72862257[ 	]+vmornot.mm[ 	]+v4,v8,v12
++[ 	]+[0-9a-f]+:[ 	]+7e862257[ 	]+vmxnor.mm[ 	]+v4,v8,v12
++[ 	]+[0-9a-f]+:[ 	]+42c82557[ 	]+vpopc.m[ 	]+a0,v12
++[ 	]+[0-9a-f]+:[ 	]+42c8a557[ 	]+vfirst.m[ 	]+a0,v12
++[ 	]+[0-9a-f]+:[ 	]+5280a257[ 	]+vmsbf.m[ 	]+v4,v8
++[ 	]+[0-9a-f]+:[ 	]+5281a257[ 	]+vmsif.m[ 	]+v4,v8
++[ 	]+[0-9a-f]+:[ 	]+52812257[ 	]+vmsof.m[ 	]+v4,v8
++[ 	]+[0-9a-f]+:[ 	]+52882257[ 	]+viota.m[ 	]+v4,v8
++[ 	]+[0-9a-f]+:[ 	]+5208a257[ 	]+vid.v[ 	]+v4
++[ 	]+[0-9a-f]+:[ 	]+40c82557[ 	]+vpopc.m[ 	]+a0,v12,v0.t
++[ 	]+[0-9a-f]+:[ 	]+40c8a557[ 	]+vfirst.m[ 	]+a0,v12,v0.t
++[ 	]+[0-9a-f]+:[ 	]+5080a257[ 	]+vmsbf.m[ 	]+v4,v8,v0.t
++[ 	]+[0-9a-f]+:[ 	]+5081a257[ 	]+vmsif.m[ 	]+v4,v8,v0.t
++[ 	]+[0-9a-f]+:[ 	]+50812257[ 	]+vmsof.m[ 	]+v4,v8,v0.t
++[ 	]+[0-9a-f]+:[ 	]+50882257[ 	]+viota.m[ 	]+v4,v8,v0.t
++[ 	]+[0-9a-f]+:[ 	]+5008a257[ 	]+vid.v[ 	]+v4,v0.t
++[ 	]+[0-9a-f]+:[ 	]+42c02557[ 	]+vmv.x.s[ 	]+a0,v12
++[ 	]+[0-9a-f]+:[ 	]+42056257[ 	]+vmv.s.x[ 	]+v4,a0
++[ 	]+[0-9a-f]+:[ 	]+42801557[ 	]+vfmv.f.s[ 	]+fa0,v8
++[ 	]+[0-9a-f]+:[ 	]+4205d257[ 	]+vfmv.s.f[ 	]+v4,fa1
++[ 	]+[0-9a-f]+:[ 	]+3a85c257[ 	]+vslideup.vx[ 	]+v4,v8,a1
++[ 	]+[0-9a-f]+:[ 	]+3a803257[ 	]+vslideup.vi[ 	]+v4,v8,0
++[ 	]+[0-9a-f]+:[ 	]+3a8fb257[ 	]+vslideup.vi[ 	]+v4,v8,31
++[ 	]+[0-9a-f]+:[ 	]+3e85c257[ 	]+vslidedown.vx[ 	]+v4,v8,a1
++[ 	]+[0-9a-f]+:[ 	]+3e803257[ 	]+vslidedown.vi[ 	]+v4,v8,0
++[ 	]+[0-9a-f]+:[ 	]+3e8fb257[ 	]+vslidedown.vi[ 	]+v4,v8,31
++[ 	]+[0-9a-f]+:[ 	]+3885c257[ 	]+vslideup.vx[ 	]+v4,v8,a1,v0.t
++[ 	]+[0-9a-f]+:[ 	]+38803257[ 	]+vslideup.vi[ 	]+v4,v8,0,v0.t
++[ 	]+[0-9a-f]+:[ 	]+388fb257[ 	]+vslideup.vi[ 	]+v4,v8,31,v0.t
++[ 	]+[0-9a-f]+:[ 	]+3c85c257[ 	]+vslidedown.vx[ 	]+v4,v8,a1,v0.t
++[ 	]+[0-9a-f]+:[ 	]+3c803257[ 	]+vslidedown.vi[ 	]+v4,v8,0,v0.t
++[ 	]+[0-9a-f]+:[ 	]+3c8fb257[ 	]+vslidedown.vi[ 	]+v4,v8,31,v0.t
++[ 	]+[0-9a-f]+:[ 	]+3a85e257[ 	]+vslide1up.vx[ 	]+v4,v8,a1
++[ 	]+[0-9a-f]+:[ 	]+3e85e257[ 	]+vslide1down.vx[ 	]+v4,v8,a1
++[ 	]+[0-9a-f]+:[ 	]+3885e257[ 	]+vslide1up.vx[ 	]+v4,v8,a1,v0.t
++[ 	]+[0-9a-f]+:[ 	]+3c85e257[ 	]+vslide1down.vx[ 	]+v4,v8,a1,v0.t
++[ 	]+[0-9a-f]+:[ 	]+3a85d257[ 	]+vfslide1up.vf[ 	]+v4,v8,fa1
++[ 	]+[0-9a-f]+:[ 	]+3e85d257[ 	]+vfslide1down.vf[ 	]+v4,v8,fa1
++[ 	]+[0-9a-f]+:[ 	]+3885d257[ 	]+vfslide1up.vf[ 	]+v4,v8,fa1,v0.t
++[ 	]+[0-9a-f]+:[ 	]+3c85d257[ 	]+vfslide1down.vf[ 	]+v4,v8,fa1,v0.t
++[ 	]+[0-9a-f]+:[ 	]+32860257[ 	]+vrgather.vv[ 	]+v4,v8,v12
++[ 	]+[0-9a-f]+:[ 	]+3285c257[ 	]+vrgather.vx[ 	]+v4,v8,a1
++[ 	]+[0-9a-f]+:[ 	]+32803257[ 	]+vrgather.vi[ 	]+v4,v8,0
++[ 	]+[0-9a-f]+:[ 	]+328fb257[ 	]+vrgather.vi[ 	]+v4,v8,31
++[ 	]+[0-9a-f]+:[ 	]+30860257[ 	]+vrgather.vv[ 	]+v4,v8,v12,v0.t
++[ 	]+[0-9a-f]+:[ 	]+3085c257[ 	]+vrgather.vx[ 	]+v4,v8,a1,v0.t
++[ 	]+[0-9a-f]+:[ 	]+30803257[ 	]+vrgather.vi[ 	]+v4,v8,0,v0.t
++[ 	]+[0-9a-f]+:[ 	]+308fb257[ 	]+vrgather.vi[ 	]+v4,v8,31,v0.t
++[ 	]+[0-9a-f]+:[ 	]+5e862257[ 	]+vcompress.vm[ 	]+v4,v8,v12
++[ 	]+[0-9a-f]+:[ 	]+9e2030d7[ 	]+vmv1r.v[ 	]+v1,v2
++[ 	]+[0-9a-f]+:[ 	]+9e40b157[ 	]+vmv2r.v[ 	]+v2,v4
++[ 	]+[0-9a-f]+:[ 	]+9e81b257[ 	]+vmv4r.v[ 	]+v4,v8
++[ 	]+[0-9a-f]+:[ 	]+9e83b057[ 	]+vmv8r.v[ 	]+v0,v8
++[ 	]+[0-9a-f]+:[ 	]+e6860257[ 	]+vdot.vv[ 	]+v4,v8,v12
++[ 	]+[0-9a-f]+:[ 	]+e2860257[ 	]+vdotu.vv[ 	]+v4,v8,v12
++[ 	]+[0-9a-f]+:[ 	]+e6861257[ 	]+vfdot.vv[ 	]+v4,v8,v12
++[ 	]+[0-9a-f]+:[ 	]+e4860257[ 	]+vdot.vv[ 	]+v4,v8,v12,v0.t
++[ 	]+[0-9a-f]+:[ 	]+e0860257[ 	]+vdotu.vv[ 	]+v4,v8,v12,v0.t
++[ 	]+[0-9a-f]+:[ 	]+e4861257[ 	]+vfdot.vv[ 	]+v4,v8,v12,v0.t
+diff --git a/gas/testsuite/gas/riscv/vector-insns.s b/gas/testsuite/gas/riscv/vector-insns.s
+new file mode 100644
+index 0000000000..8b9a894418
+--- /dev/null
++++ b/gas/testsuite/gas/riscv/vector-insns.s
+@@ -0,0 +1,2718 @@
++	vsetvl a0, a1, a2
++	vsetvli a0, a1, 0
++	vsetvli a0, a1, 0x7ff
++	vsetvli a0, a1, e16,m2,d4
++	vsetvli a0, a1, e256, m8, d8
++	vsetvli a0, a1, e512, m8, d8
++	vsetvli a0, a1, e1024, m8, d8
++	vsetvli a0, a1, e1024, m1, d8
++	vsetvli a0, a1, e1024, mf2, d8
++	vsetvli a0, a1, e512, mf4, d2
++	vsetvli a0, a1, e256, mf8, d4
++	vsetvli a0, a1, e256, m2, ta, d4
++	vsetvli a0, a1, e256, m2, ma, d4
++	vsetvli a0, a1, e256, m2, tu, d4
++	vsetvli a0, a1, e256, m2, mu, d4
++	vsetvli a0, a1, e256, m2, ta,ma, d4
++	vsetvli a0, a1, e256, m2, tu,ma, d4
++	vsetvli a0, a1, e256, m2, ta,mu, d4
++	vsetvli a0, a1, e256, m2, tu,mu, d4
++
++	vle8.v v4, (a0)
++	vle8.v v4, 0(a0)
++	vle8.v v4, (a0), v0.t
++	vse8.v v4, (a0)
++	vse8.v v4, 0(a0)
++	vse8.v v4, (a0), v0.t
++
++	vle16.v v4, (a0)
++	vle16.v v4, 0(a0)
++	vle16.v v4, (a0), v0.t
++	vse16.v v4, (a0)
++	vse16.v v4, 0(a0)
++	vse16.v v4, (a0), v0.t
++
++	vle32.v v4, (a0)
++	vle32.v v4, 0(a0)
++	vle32.v v4, (a0), v0.t
++	vse32.v v4, (a0)
++	vse32.v v4, 0(a0)
++	vse32.v v4, (a0), v0.t
++
++	vle64.v v4, (a0)
++	vle64.v v4, 0(a0)
++	vle64.v v4, (a0), v0.t
++	vse64.v v4, (a0)
++	vse64.v v4, 0(a0)
++	vse64.v v4, (a0), v0.t
++
++	vle128.v v4, (a0)
++	vle128.v v4, 0(a0)
++	vle128.v v4, (a0), v0.t
++	vse128.v v4, (a0)
++	vse128.v v4, 0(a0)
++	vse128.v v4, (a0), v0.t
++
++	vle256.v v4, (a0)
++	vle256.v v4, 0(a0)
++	vle256.v v4, (a0), v0.t
++	vse256.v v4, (a0)
++	vse256.v v4, 0(a0)
++	vse256.v v4, (a0), v0.t
++
++	vle512.v v4, (a0)
++	vle512.v v4, 0(a0)
++	vle512.v v4, (a0), v0.t
++	vse512.v v4, (a0)
++	vse512.v v4, 0(a0)
++	vse512.v v4, (a0), v0.t
++
++	vle1024.v v4, (a0)
++	vle1024.v v4, 0(a0)
++	vle1024.v v4, (a0), v0.t
++	vse1024.v v4, (a0)
++	vse1024.v v4, 0(a0)
++	vse1024.v v4, (a0), v0.t
++
++	vlse8.v v4, (a0), a1
++	vlse8.v v4, 0(a0), a1
++	vlse8.v v4, (a0), a1, v0.t
++	vsse8.v v4, (a0), a1
++	vsse8.v v4, 0(a0), a1
++	vsse8.v v4, (a0), a1, v0.t
++
++	vlse16.v v4, (a0), a1
++	vlse16.v v4, 0(a0), a1
++	vlse16.v v4, (a0), a1, v0.t
++	vsse16.v v4, (a0), a1
++	vsse16.v v4, 0(a0), a1
++	vsse16.v v4, (a0), a1, v0.t
++
++	vlse32.v v4, (a0), a1
++	vlse32.v v4, 0(a0), a1
++	vlse32.v v4, (a0), a1, v0.t
++	vsse32.v v4, (a0), a1
++	vsse32.v v4, 0(a0), a1
++	vsse32.v v4, (a0), a1, v0.t
++
++	vlse64.v v4, (a0), a1
++	vlse64.v v4, 0(a0), a1
++	vlse64.v v4, (a0), a1, v0.t
++	vsse64.v v4, (a0), a1
++	vsse64.v v4, 0(a0), a1
++	vsse64.v v4, (a0), a1, v0.t
++
++	vlse128.v v4, (a0), a1
++	vlse128.v v4, 0(a0), a1
++	vlse128.v v4, (a0), a1, v0.t
++	vsse128.v v4, (a0), a1
++	vsse128.v v4, 0(a0), a1
++	vsse128.v v4, (a0), a1, v0.t
++
++	vlse256.v v4, (a0), a1
++	vlse256.v v4, 0(a0), a1
++	vlse256.v v4, (a0), a1, v0.t
++	vsse256.v v4, (a0), a1
++	vsse256.v v4, 0(a0), a1
++	vsse256.v v4, (a0), a1, v0.t
++
++	vlse512.v v4, (a0), a1
++	vlse512.v v4, 0(a0), a1
++	vlse512.v v4, (a0), a1, v0.t
++	vsse512.v v4, (a0), a1
++	vsse512.v v4, 0(a0), a1
++	vsse512.v v4, (a0), a1, v0.t
++
++	vlse1024.v v4, (a0), a1
++	vlse1024.v v4, 0(a0), a1
++	vlse1024.v v4, (a0), a1, v0.t
++	vsse1024.v v4, (a0), a1
++	vsse1024.v v4, 0(a0), a1
++	vsse1024.v v4, (a0), a1, v0.t
++
++	vlxei8.v v4, (a0), v12
++	vlxei8.v v4, 0(a0), v12
++	vlxei8.v v4, (a0), v12, v0.t
++	vsxei8.v v4, (a0), v12
++	vsxei8.v v4, 0(a0), v12
++	vsxei8.v v4, (a0), v12, v0.t
++	vsuxei8.v v4, (a0), v12
++	vsuxei8.v v4, 0(a0), v12
++	vsuxei8.v v4, (a0), v12, v0.t
++
++	vlxei16.v v4, (a0), v12
++	vlxei16.v v4, 0(a0), v12
++	vlxei16.v v4, (a0), v12, v0.t
++	vsxei16.v v4, (a0), v12
++	vsxei16.v v4, 0(a0), v12
++	vsxei16.v v4, (a0), v12, v0.t
++	vsuxei16.v v4, (a0), v12
++	vsuxei16.v v4, 0(a0), v12
++	vsuxei16.v v4, (a0), v12, v0.t
++
++	vlxei32.v v4, (a0), v12
++	vlxei32.v v4, 0(a0), v12
++	vlxei32.v v4, (a0), v12, v0.t
++	vsxei32.v v4, (a0), v12
++	vsxei32.v v4, 0(a0), v12
++	vsxei32.v v4, (a0), v12, v0.t
++	vsuxei32.v v4, (a0), v12
++	vsuxei32.v v4, 0(a0), v12
++	vsuxei32.v v4, (a0), v12, v0.t
++
++	vlxei64.v v4, (a0), v12
++	vlxei64.v v4, 0(a0), v12
++	vlxei64.v v4, (a0), v12, v0.t
++	vsxei64.v v4, (a0), v12
++	vsxei64.v v4, 0(a0), v12
++	vsxei64.v v4, (a0), v12, v0.t
++	vsuxei64.v v4, (a0), v12
++	vsuxei64.v v4, 0(a0), v12
++	vsuxei64.v v4, (a0), v12, v0.t
++
++	vlxei128.v v4, (a0), v12
++	vlxei128.v v4, 0(a0), v12
++	vlxei128.v v4, (a0), v12, v0.t
++	vsxei128.v v4, (a0), v12
++	vsxei128.v v4, 0(a0), v12
++	vsxei128.v v4, (a0), v12, v0.t
++	vsuxei128.v v4, (a0), v12
++	vsuxei128.v v4, 0(a0), v12
++	vsuxei128.v v4, (a0), v12, v0.t
++
++	vlxei256.v v4, (a0), v12
++	vlxei256.v v4, 0(a0), v12
++	vlxei256.v v4, (a0), v12, v0.t
++	vsxei256.v v4, (a0), v12
++	vsxei256.v v4, 0(a0), v12
++	vsxei256.v v4, (a0), v12, v0.t
++	vsuxei256.v v4, (a0), v12
++	vsuxei256.v v4, 0(a0), v12
++	vsuxei256.v v4, (a0), v12, v0.t
++
++	vlxei512.v v4, (a0), v12
++	vlxei512.v v4, 0(a0), v12
++	vlxei512.v v4, (a0), v12, v0.t
++	vsxei512.v v4, (a0), v12
++	vsxei512.v v4, 0(a0), v12
++	vsxei512.v v4, (a0), v12, v0.t
++	vsuxei512.v v4, (a0), v12
++	vsuxei512.v v4, 0(a0), v12
++	vsuxei512.v v4, (a0), v12, v0.t
++
++	vlxei1024.v v4, (a0), v12
++	vlxei1024.v v4, 0(a0), v12
++	vlxei1024.v v4, (a0), v12, v0.t
++	vsxei1024.v v4, (a0), v12
++	vsxei1024.v v4, 0(a0), v12
++	vsxei1024.v v4, (a0), v12, v0.t
++	vsuxei1024.v v4, (a0), v12
++	vsuxei1024.v v4, 0(a0), v12
++	vsuxei1024.v v4, (a0), v12, v0.t
++
++	vle8ff.v v4, (a0)
++	vle8ff.v v4, 0(a0)
++	vle8ff.v v4, (a0), v0.t
++
++	vle16ff.v v4, (a0)
++	vle16ff.v v4, 0(a0)
++	vle16ff.v v4, (a0), v0.t
++
++	vle32ff.v v4, (a0)
++	vle32ff.v v4, 0(a0)
++	vle32ff.v v4, (a0), v0.t
++
++	vle64ff.v v4, (a0)
++	vle64ff.v v4, 0(a0)
++	vle64ff.v v4, (a0), v0.t
++
++	vle128ff.v v4, (a0)
++	vle128ff.v v4, 0(a0)
++	vle128ff.v v4, (a0), v0.t
++
++	vle256ff.v v4, (a0)
++	vle256ff.v v4, 0(a0)
++	vle256ff.v v4, (a0), v0.t
++
++	vle512ff.v v4, (a0)
++	vle512ff.v v4, 0(a0)
++	vle512ff.v v4, (a0), v0.t
++
++	vle1024ff.v v4, (a0)
++	vle1024ff.v v4, 0(a0)
++	vle1024ff.v v4, (a0), v0.t
++
++	vlseg2e8.v v4, (a0)
++	vlseg2e8.v v4, 0(a0)
++	vlseg2e8.v v4, (a0), v0.t
++	vsseg2e8.v v4, (a0)
++	vsseg2e8.v v4, 0(a0)
++	vsseg2e8.v v4, (a0), v0.t
++
++	vlseg3e8.v v4, (a0)
++	vlseg3e8.v v4, 0(a0)
++	vlseg3e8.v v4, (a0), v0.t
++	vsseg3e8.v v4, (a0)
++	vsseg3e8.v v4, 0(a0)
++	vsseg3e8.v v4, (a0), v0.t
++
++	vlseg4e8.v v4, (a0)
++	vlseg4e8.v v4, 0(a0)
++	vlseg4e8.v v4, (a0), v0.t
++	vsseg4e8.v v4, (a0)
++	vsseg4e8.v v4, 0(a0)
++	vsseg4e8.v v4, (a0), v0.t
++
++	vlseg5e8.v v4, (a0)
++	vlseg5e8.v v4, 0(a0)
++	vlseg5e8.v v4, (a0), v0.t
++	vsseg5e8.v v4, (a0)
++	vsseg5e8.v v4, 0(a0)
++	vsseg5e8.v v4, (a0), v0.t
++
++	vlseg6e8.v v4, (a0)
++	vlseg6e8.v v4, 0(a0)
++	vlseg6e8.v v4, (a0), v0.t
++	vsseg6e8.v v4, (a0)
++	vsseg6e8.v v4, 0(a0)
++	vsseg6e8.v v4, (a0), v0.t
++
++	vlseg7e8.v v4, (a0)
++	vlseg7e8.v v4, 0(a0)
++	vlseg7e8.v v4, (a0), v0.t
++	vsseg7e8.v v4, (a0)
++	vsseg7e8.v v4, 0(a0)
++	vsseg7e8.v v4, (a0), v0.t
++
++	vlseg8e8.v v4, (a0)
++	vlseg8e8.v v4, 0(a0)
++	vlseg8e8.v v4, (a0), v0.t
++	vsseg8e8.v v4, (a0)
++	vsseg8e8.v v4, 0(a0)
++	vsseg8e8.v v4, (a0), v0.t
++
++	vlseg2e16.v v4, (a0)
++	vlseg2e16.v v4, 0(a0)
++	vlseg2e16.v v4, (a0), v0.t
++	vsseg2e16.v v4, (a0)
++	vsseg2e16.v v4, 0(a0)
++	vsseg2e16.v v4, (a0), v0.t
++
++	vlseg3e16.v v4, (a0)
++	vlseg3e16.v v4, 0(a0)
++	vlseg3e16.v v4, (a0), v0.t
++	vsseg3e16.v v4, (a0)
++	vsseg3e16.v v4, 0(a0)
++	vsseg3e16.v v4, (a0), v0.t
++
++	vlseg4e16.v v4, (a0)
++	vlseg4e16.v v4, 0(a0)
++	vlseg4e16.v v4, (a0), v0.t
++	vsseg4e16.v v4, (a0)
++	vsseg4e16.v v4, 0(a0)
++	vsseg4e16.v v4, (a0), v0.t
++
++	vlseg5e16.v v4, (a0)
++	vlseg5e16.v v4, 0(a0)
++	vlseg5e16.v v4, (a0), v0.t
++	vsseg5e16.v v4, (a0)
++	vsseg5e16.v v4, 0(a0)
++	vsseg5e16.v v4, (a0), v0.t
++
++	vlseg6e16.v v4, (a0)
++	vlseg6e16.v v4, 0(a0)
++	vlseg6e16.v v4, (a0), v0.t
++	vsseg6e16.v v4, (a0)
++	vsseg6e16.v v4, 0(a0)
++	vsseg6e16.v v4, (a0), v0.t
++
++	vlseg7e16.v v4, (a0)
++	vlseg7e16.v v4, 0(a0)
++	vlseg7e16.v v4, (a0), v0.t
++	vsseg7e16.v v4, (a0)
++	vsseg7e16.v v4, 0(a0)
++	vsseg7e16.v v4, (a0), v0.t
++
++	vlseg8e16.v v4, (a0)
++	vlseg8e16.v v4, 0(a0)
++	vlseg8e16.v v4, (a0), v0.t
++	vsseg8e16.v v4, (a0)
++	vsseg8e16.v v4, 0(a0)
++	vsseg8e16.v v4, (a0), v0.t
++
++	vlseg2e32.v v4, (a0)
++	vlseg2e32.v v4, 0(a0)
++	vlseg2e32.v v4, (a0), v0.t
++	vsseg2e32.v v4, (a0)
++	vsseg2e32.v v4, 0(a0)
++	vsseg2e32.v v4, (a0), v0.t
++
++	vlseg3e32.v v4, (a0)
++	vlseg3e32.v v4, 0(a0)
++	vlseg3e32.v v4, (a0), v0.t
++	vsseg3e32.v v4, (a0)
++	vsseg3e32.v v4, 0(a0)
++	vsseg3e32.v v4, (a0), v0.t
++
++	vlseg4e32.v v4, (a0)
++	vlseg4e32.v v4, 0(a0)
++	vlseg4e32.v v4, (a0), v0.t
++	vsseg4e32.v v4, (a0)
++	vsseg4e32.v v4, 0(a0)
++	vsseg4e32.v v4, (a0), v0.t
++
++	vlseg5e32.v v4, (a0)
++	vlseg5e32.v v4, 0(a0)
++	vlseg5e32.v v4, (a0), v0.t
++	vsseg5e32.v v4, (a0)
++	vsseg5e32.v v4, 0(a0)
++	vsseg5e32.v v4, (a0), v0.t
++
++	vlseg6e32.v v4, (a0)
++	vlseg6e32.v v4, 0(a0)
++	vlseg6e32.v v4, (a0), v0.t
++	vsseg6e32.v v4, (a0)
++	vsseg6e32.v v4, 0(a0)
++	vsseg6e32.v v4, (a0), v0.t
++
++	vlseg7e32.v v4, (a0)
++	vlseg7e32.v v4, 0(a0)
++	vlseg7e32.v v4, (a0), v0.t
++	vsseg7e32.v v4, (a0)
++	vsseg7e32.v v4, 0(a0)
++	vsseg7e32.v v4, (a0), v0.t
++
++	vlseg8e32.v v4, (a0)
++	vlseg8e32.v v4, 0(a0)
++	vlseg8e32.v v4, (a0), v0.t
++	vsseg8e32.v v4, (a0)
++	vsseg8e32.v v4, 0(a0)
++	vsseg8e32.v v4, (a0), v0.t
++
++	vlseg2e64.v v4, (a0)
++	vlseg2e64.v v4, 0(a0)
++	vlseg2e64.v v4, (a0), v0.t
++	vsseg2e64.v v4, (a0)
++	vsseg2e64.v v4, 0(a0)
++	vsseg2e64.v v4, (a0), v0.t
++
++	vlseg3e64.v v4, (a0)
++	vlseg3e64.v v4, 0(a0)
++	vlseg3e64.v v4, (a0), v0.t
++	vsseg3e64.v v4, (a0)
++	vsseg3e64.v v4, 0(a0)
++	vsseg3e64.v v4, (a0), v0.t
++
++	vlseg4e64.v v4, (a0)
++	vlseg4e64.v v4, 0(a0)
++	vlseg4e64.v v4, (a0), v0.t
++	vsseg4e64.v v4, (a0)
++	vsseg4e64.v v4, 0(a0)
++	vsseg4e64.v v4, (a0), v0.t
++
++	vlseg5e64.v v4, (a0)
++	vlseg5e64.v v4, 0(a0)
++	vlseg5e64.v v4, (a0), v0.t
++	vsseg5e64.v v4, (a0)
++	vsseg5e64.v v4, 0(a0)
++	vsseg5e64.v v4, (a0), v0.t
++
++	vlseg6e64.v v4, (a0)
++	vlseg6e64.v v4, 0(a0)
++	vlseg6e64.v v4, (a0), v0.t
++	vsseg6e64.v v4, (a0)
++	vsseg6e64.v v4, 0(a0)
++	vsseg6e64.v v4, (a0), v0.t
++
++	vlseg7e64.v v4, (a0)
++	vlseg7e64.v v4, 0(a0)
++	vlseg7e64.v v4, (a0), v0.t
++	vsseg7e64.v v4, (a0)
++	vsseg7e64.v v4, 0(a0)
++	vsseg7e64.v v4, (a0), v0.t
++
++	vlseg8e64.v v4, (a0)
++	vlseg8e64.v v4, 0(a0)
++	vlseg8e64.v v4, (a0), v0.t
++	vsseg8e64.v v4, (a0)
++	vsseg8e64.v v4, 0(a0)
++	vsseg8e64.v v4, (a0), v0.t
++
++	vlseg2e128.v v4, (a0)
++	vlseg2e128.v v4, 0(a0)
++	vlseg2e128.v v4, (a0), v0.t
++	vsseg2e128.v v4, (a0)
++	vsseg2e128.v v4, 0(a0)
++	vsseg2e128.v v4, (a0), v0.t
++
++	vlseg3e128.v v4, (a0)
++	vlseg3e128.v v4, 0(a0)
++	vlseg3e128.v v4, (a0), v0.t
++	vsseg3e128.v v4, (a0)
++	vsseg3e128.v v4, 0(a0)
++	vsseg3e128.v v4, (a0), v0.t
++
++	vlseg4e128.v v4, (a0)
++	vlseg4e128.v v4, 0(a0)
++	vlseg4e128.v v4, (a0), v0.t
++	vsseg4e128.v v4, (a0)
++	vsseg4e128.v v4, 0(a0)
++	vsseg4e128.v v4, (a0), v0.t
++
++	vlseg5e128.v v4, (a0)
++	vlseg5e128.v v4, 0(a0)
++	vlseg5e128.v v4, (a0), v0.t
++	vsseg5e128.v v4, (a0)
++	vsseg5e128.v v4, 0(a0)
++	vsseg5e128.v v4, (a0), v0.t
++
++	vlseg6e128.v v4, (a0)
++	vlseg6e128.v v4, 0(a0)
++	vlseg6e128.v v4, (a0), v0.t
++	vsseg6e128.v v4, (a0)
++	vsseg6e128.v v4, 0(a0)
++	vsseg6e128.v v4, (a0), v0.t
++
++	vlseg7e128.v v4, (a0)
++	vlseg7e128.v v4, 0(a0)
++	vlseg7e128.v v4, (a0), v0.t
++	vsseg7e128.v v4, (a0)
++	vsseg7e128.v v4, 0(a0)
++	vsseg7e128.v v4, (a0), v0.t
++
++	vlseg8e128.v v4, (a0)
++	vlseg8e128.v v4, 0(a0)
++	vlseg8e128.v v4, (a0), v0.t
++	vsseg8e128.v v4, (a0)
++	vsseg8e128.v v4, 0(a0)
++	vsseg8e128.v v4, (a0), v0.t
++
++	vlseg2e256.v v4, (a0)
++	vlseg2e256.v v4, 0(a0)
++	vlseg2e256.v v4, (a0), v0.t
++	vsseg2e256.v v4, (a0)
++	vsseg2e256.v v4, 0(a0)
++	vsseg2e256.v v4, (a0), v0.t
++
++	vlseg3e256.v v4, (a0)
++	vlseg3e256.v v4, 0(a0)
++	vlseg3e256.v v4, (a0), v0.t
++	vsseg3e256.v v4, (a0)
++	vsseg3e256.v v4, 0(a0)
++	vsseg3e256.v v4, (a0), v0.t
++
++	vlseg4e256.v v4, (a0)
++	vlseg4e256.v v4, 0(a0)
++	vlseg4e256.v v4, (a0), v0.t
++	vsseg4e256.v v4, (a0)
++	vsseg4e256.v v4, 0(a0)
++	vsseg4e256.v v4, (a0), v0.t
++
++	vlseg5e256.v v4, (a0)
++	vlseg5e256.v v4, 0(a0)
++	vlseg5e256.v v4, (a0), v0.t
++	vsseg5e256.v v4, (a0)
++	vsseg5e256.v v4, 0(a0)
++	vsseg5e256.v v4, (a0), v0.t
++
++	vlseg6e256.v v4, (a0)
++	vlseg6e256.v v4, 0(a0)
++	vlseg6e256.v v4, (a0), v0.t
++	vsseg6e256.v v4, (a0)
++	vsseg6e256.v v4, 0(a0)
++	vsseg6e256.v v4, (a0), v0.t
++
++	vlseg7e256.v v4, (a0)
++	vlseg7e256.v v4, 0(a0)
++	vlseg7e256.v v4, (a0), v0.t
++	vsseg7e256.v v4, (a0)
++	vsseg7e256.v v4, 0(a0)
++	vsseg7e256.v v4, (a0), v0.t
++
++	vlseg8e256.v v4, (a0)
++	vlseg8e256.v v4, 0(a0)
++	vlseg8e256.v v4, (a0), v0.t
++	vsseg8e256.v v4, (a0)
++	vsseg8e256.v v4, 0(a0)
++	vsseg8e256.v v4, (a0), v0.t
++
++	vlseg2e512.v v4, (a0)
++	vlseg2e512.v v4, 0(a0)
++	vlseg2e512.v v4, (a0), v0.t
++	vsseg2e512.v v4, (a0)
++	vsseg2e512.v v4, 0(a0)
++	vsseg2e512.v v4, (a0), v0.t
++
++	vlseg3e512.v v4, (a0)
++	vlseg3e512.v v4, 0(a0)
++	vlseg3e512.v v4, (a0), v0.t
++	vsseg3e512.v v4, (a0)
++	vsseg3e512.v v4, 0(a0)
++	vsseg3e512.v v4, (a0), v0.t
++
++	vlseg4e512.v v4, (a0)
++	vlseg4e512.v v4, 0(a0)
++	vlseg4e512.v v4, (a0), v0.t
++	vsseg4e512.v v4, (a0)
++	vsseg4e512.v v4, 0(a0)
++	vsseg4e512.v v4, (a0), v0.t
++
++	vlseg5e512.v v4, (a0)
++	vlseg5e512.v v4, 0(a0)
++	vlseg5e512.v v4, (a0), v0.t
++	vsseg5e512.v v4, (a0)
++	vsseg5e512.v v4, 0(a0)
++	vsseg5e512.v v4, (a0), v0.t
++
++	vlseg6e512.v v4, (a0)
++	vlseg6e512.v v4, 0(a0)
++	vlseg6e512.v v4, (a0), v0.t
++	vsseg6e512.v v4, (a0)
++	vsseg6e512.v v4, 0(a0)
++	vsseg6e512.v v4, (a0), v0.t
++
++	vlseg7e512.v v4, (a0)
++	vlseg7e512.v v4, 0(a0)
++	vlseg7e512.v v4, (a0), v0.t
++	vsseg7e512.v v4, (a0)
++	vsseg7e512.v v4, 0(a0)
++	vsseg7e512.v v4, (a0), v0.t
++
++	vlseg8e512.v v4, (a0)
++	vlseg8e512.v v4, 0(a0)
++	vlseg8e512.v v4, (a0), v0.t
++	vsseg8e512.v v4, (a0)
++	vsseg8e512.v v4, 0(a0)
++	vsseg8e512.v v4, (a0), v0.t
++
++	vlseg2e1024.v v4, (a0)
++	vlseg2e1024.v v4, 0(a0)
++	vlseg2e1024.v v4, (a0), v0.t
++	vsseg2e1024.v v4, (a0)
++	vsseg2e1024.v v4, 0(a0)
++	vsseg2e1024.v v4, (a0), v0.t
++
++	vlseg3e1024.v v4, (a0)
++	vlseg3e1024.v v4, 0(a0)
++	vlseg3e1024.v v4, (a0), v0.t
++	vsseg3e1024.v v4, (a0)
++	vsseg3e1024.v v4, 0(a0)
++	vsseg3e1024.v v4, (a0), v0.t
++
++	vlseg4e1024.v v4, (a0)
++	vlseg4e1024.v v4, 0(a0)
++	vlseg4e1024.v v4, (a0), v0.t
++	vsseg4e1024.v v4, (a0)
++	vsseg4e1024.v v4, 0(a0)
++	vsseg4e1024.v v4, (a0), v0.t
++
++	vlseg5e1024.v v4, (a0)
++	vlseg5e1024.v v4, 0(a0)
++	vlseg5e1024.v v4, (a0), v0.t
++	vsseg5e1024.v v4, (a0)
++	vsseg5e1024.v v4, 0(a0)
++	vsseg5e1024.v v4, (a0), v0.t
++
++	vlseg6e1024.v v4, (a0)
++	vlseg6e1024.v v4, 0(a0)
++	vlseg6e1024.v v4, (a0), v0.t
++	vsseg6e1024.v v4, (a0)
++	vsseg6e1024.v v4, 0(a0)
++	vsseg6e1024.v v4, (a0), v0.t
++
++	vlseg7e1024.v v4, (a0)
++	vlseg7e1024.v v4, 0(a0)
++	vlseg7e1024.v v4, (a0), v0.t
++	vsseg7e1024.v v4, (a0)
++	vsseg7e1024.v v4, 0(a0)
++	vsseg7e1024.v v4, (a0), v0.t
++
++	vlseg8e1024.v v4, (a0)
++	vlseg8e1024.v v4, 0(a0)
++	vlseg8e1024.v v4, (a0), v0.t
++	vsseg8e1024.v v4, (a0)
++	vsseg8e1024.v v4, 0(a0)
++	vsseg8e1024.v v4, (a0), v0.t
++
++	vlsseg2e8.v v4, (a0), a1
++	vlsseg2e8.v v4, 0(a0), a1
++	vlsseg2e8.v v4, (a0), a1, v0.t
++	vssseg2e8.v v4, (a0), a1
++	vssseg2e8.v v4, 0(a0), a1
++	vssseg2e8.v v4, (a0), a1, v0.t
++
++	vlsseg3e8.v v4, (a0), a1
++	vlsseg3e8.v v4, 0(a0), a1
++	vlsseg3e8.v v4, (a0), a1, v0.t
++	vssseg3e8.v v4, (a0), a1
++	vssseg3e8.v v4, 0(a0), a1
++	vssseg3e8.v v4, (a0), a1, v0.t
++
++	vlsseg4e8.v v4, (a0), a1
++	vlsseg4e8.v v4, 0(a0), a1
++	vlsseg4e8.v v4, (a0), a1, v0.t
++	vssseg4e8.v v4, (a0), a1
++	vssseg4e8.v v4, 0(a0), a1
++	vssseg4e8.v v4, (a0), a1, v0.t
++
++	vlsseg5e8.v v4, (a0), a1
++	vlsseg5e8.v v4, 0(a0), a1
++	vlsseg5e8.v v4, (a0), a1, v0.t
++	vssseg5e8.v v4, (a0), a1
++	vssseg5e8.v v4, 0(a0), a1
++	vssseg5e8.v v4, (a0), a1, v0.t
++
++	vlsseg6e8.v v4, (a0), a1
++	vlsseg6e8.v v4, 0(a0), a1
++	vlsseg6e8.v v4, (a0), a1, v0.t
++	vssseg6e8.v v4, (a0), a1
++	vssseg6e8.v v4, 0(a0), a1
++	vssseg6e8.v v4, (a0), a1, v0.t
++
++	vlsseg7e8.v v4, (a0), a1
++	vlsseg7e8.v v4, 0(a0), a1
++	vlsseg7e8.v v4, (a0), a1, v0.t
++	vssseg7e8.v v4, (a0), a1
++	vssseg7e8.v v4, 0(a0), a1
++	vssseg7e8.v v4, (a0), a1, v0.t
++
++	vlsseg8e8.v v4, (a0), a1
++	vlsseg8e8.v v4, 0(a0), a1
++	vlsseg8e8.v v4, (a0), a1, v0.t
++	vssseg8e8.v v4, (a0), a1
++	vssseg8e8.v v4, 0(a0), a1
++	vssseg8e8.v v4, (a0), a1, v0.t
++
++	vlsseg2e16.v v4, (a0), a1
++	vlsseg2e16.v v4, 0(a0), a1
++	vlsseg2e16.v v4, (a0), a1, v0.t
++	vssseg2e16.v v4, (a0), a1
++	vssseg2e16.v v4, 0(a0), a1
++	vssseg2e16.v v4, (a0), a1, v0.t
++
++	vlsseg3e16.v v4, (a0), a1
++	vlsseg3e16.v v4, 0(a0), a1
++	vlsseg3e16.v v4, (a0), a1, v0.t
++	vssseg3e16.v v4, (a0), a1
++	vssseg3e16.v v4, 0(a0), a1
++	vssseg3e16.v v4, (a0), a1, v0.t
++
++	vlsseg4e16.v v4, (a0), a1
++	vlsseg4e16.v v4, 0(a0), a1
++	vlsseg4e16.v v4, (a0), a1, v0.t
++	vssseg4e16.v v4, (a0), a1
++	vssseg4e16.v v4, 0(a0), a1
++	vssseg4e16.v v4, (a0), a1, v0.t
++
++	vlsseg5e16.v v4, (a0), a1
++	vlsseg5e16.v v4, 0(a0), a1
++	vlsseg5e16.v v4, (a0), a1, v0.t
++	vssseg5e16.v v4, (a0), a1
++	vssseg5e16.v v4, 0(a0), a1
++	vssseg5e16.v v4, (a0), a1, v0.t
++
++	vlsseg6e16.v v4, (a0), a1
++	vlsseg6e16.v v4, 0(a0), a1
++	vlsseg6e16.v v4, (a0), a1, v0.t
++	vssseg6e16.v v4, (a0), a1
++	vssseg6e16.v v4, 0(a0), a1
++	vssseg6e16.v v4, (a0), a1, v0.t
++
++	vlsseg7e16.v v4, (a0), a1
++	vlsseg7e16.v v4, 0(a0), a1
++	vlsseg7e16.v v4, (a0), a1, v0.t
++	vssseg7e16.v v4, (a0), a1
++	vssseg7e16.v v4, 0(a0), a1
++	vssseg7e16.v v4, (a0), a1, v0.t
++
++	vlsseg8e16.v v4, (a0), a1
++	vlsseg8e16.v v4, 0(a0), a1
++	vlsseg8e16.v v4, (a0), a1, v0.t
++	vssseg8e16.v v4, (a0), a1
++	vssseg8e16.v v4, 0(a0), a1
++	vssseg8e16.v v4, (a0), a1, v0.t
++
++	vlsseg2e32.v v4, (a0), a1
++	vlsseg2e32.v v4, 0(a0), a1
++	vlsseg2e32.v v4, (a0), a1, v0.t
++	vssseg2e32.v v4, (a0), a1
++	vssseg2e32.v v4, 0(a0), a1
++	vssseg2e32.v v4, (a0), a1, v0.t
++
++	vlsseg3e32.v v4, (a0), a1
++	vlsseg3e32.v v4, 0(a0), a1
++	vlsseg3e32.v v4, (a0), a1, v0.t
++	vssseg3e32.v v4, (a0), a1
++	vssseg3e32.v v4, 0(a0), a1
++	vssseg3e32.v v4, (a0), a1, v0.t
++
++	vlsseg4e32.v v4, (a0), a1
++	vlsseg4e32.v v4, 0(a0), a1
++	vlsseg4e32.v v4, (a0), a1, v0.t
++	vssseg4e32.v v4, (a0), a1
++	vssseg4e32.v v4, 0(a0), a1
++	vssseg4e32.v v4, (a0), a1, v0.t
++
++	vlsseg5e32.v v4, (a0), a1
++	vlsseg5e32.v v4, 0(a0), a1
++	vlsseg5e32.v v4, (a0), a1, v0.t
++	vssseg5e32.v v4, (a0), a1
++	vssseg5e32.v v4, 0(a0), a1
++	vssseg5e32.v v4, (a0), a1, v0.t
++
++	vlsseg6e32.v v4, (a0), a1
++	vlsseg6e32.v v4, 0(a0), a1
++	vlsseg6e32.v v4, (a0), a1, v0.t
++	vssseg6e32.v v4, (a0), a1
++	vssseg6e32.v v4, 0(a0), a1
++	vssseg6e32.v v4, (a0), a1, v0.t
++
++	vlsseg7e32.v v4, (a0), a1
++	vlsseg7e32.v v4, 0(a0), a1
++	vlsseg7e32.v v4, (a0), a1, v0.t
++	vssseg7e32.v v4, (a0), a1
++	vssseg7e32.v v4, 0(a0), a1
++	vssseg7e32.v v4, (a0), a1, v0.t
++
++	vlsseg8e32.v v4, (a0), a1
++	vlsseg8e32.v v4, 0(a0), a1
++	vlsseg8e32.v v4, (a0), a1, v0.t
++	vssseg8e32.v v4, (a0), a1
++	vssseg8e32.v v4, 0(a0), a1
++	vssseg8e32.v v4, (a0), a1, v0.t
++
++	vlsseg2e64.v v4, (a0), a1
++	vlsseg2e64.v v4, 0(a0), a1
++	vlsseg2e64.v v4, (a0), a1, v0.t
++	vssseg2e64.v v4, (a0), a1
++	vssseg2e64.v v4, 0(a0), a1
++	vssseg2e64.v v4, (a0), a1, v0.t
++
++	vlsseg3e64.v v4, (a0), a1
++	vlsseg3e64.v v4, 0(a0), a1
++	vlsseg3e64.v v4, (a0), a1, v0.t
++	vssseg3e64.v v4, (a0), a1
++	vssseg3e64.v v4, 0(a0), a1
++	vssseg3e64.v v4, (a0), a1, v0.t
++
++	vlsseg4e64.v v4, (a0), a1
++	vlsseg4e64.v v4, 0(a0), a1
++	vlsseg4e64.v v4, (a0), a1, v0.t
++	vssseg4e64.v v4, (a0), a1
++	vssseg4e64.v v4, 0(a0), a1
++	vssseg4e64.v v4, (a0), a1, v0.t
++
++	vlsseg5e64.v v4, (a0), a1
++	vlsseg5e64.v v4, 0(a0), a1
++	vlsseg5e64.v v4, (a0), a1, v0.t
++	vssseg5e64.v v4, (a0), a1
++	vssseg5e64.v v4, 0(a0), a1
++	vssseg5e64.v v4, (a0), a1, v0.t
++
++	vlsseg6e64.v v4, (a0), a1
++	vlsseg6e64.v v4, 0(a0), a1
++	vlsseg6e64.v v4, (a0), a1, v0.t
++	vssseg6e64.v v4, (a0), a1
++	vssseg6e64.v v4, 0(a0), a1
++	vssseg6e64.v v4, (a0), a1, v0.t
++
++	vlsseg7e64.v v4, (a0), a1
++	vlsseg7e64.v v4, 0(a0), a1
++	vlsseg7e64.v v4, (a0), a1, v0.t
++	vssseg7e64.v v4, (a0), a1
++	vssseg7e64.v v4, 0(a0), a1
++	vssseg7e64.v v4, (a0), a1, v0.t
++
++	vlsseg8e64.v v4, (a0), a1
++	vlsseg8e64.v v4, 0(a0), a1
++	vlsseg8e64.v v4, (a0), a1, v0.t
++	vssseg8e64.v v4, (a0), a1
++	vssseg8e64.v v4, 0(a0), a1
++	vssseg8e64.v v4, (a0), a1, v0.t
++
++	vlsseg2e128.v v4, (a0), a1
++	vlsseg2e128.v v4, 0(a0), a1
++	vlsseg2e128.v v4, (a0), a1, v0.t
++	vssseg2e128.v v4, (a0), a1
++	vssseg2e128.v v4, 0(a0), a1
++	vssseg2e128.v v4, (a0), a1, v0.t
++
++	vlsseg3e128.v v4, (a0), a1
++	vlsseg3e128.v v4, 0(a0), a1
++	vlsseg3e128.v v4, (a0), a1, v0.t
++	vssseg3e128.v v4, (a0), a1
++	vssseg3e128.v v4, 0(a0), a1
++	vssseg3e128.v v4, (a0), a1, v0.t
++
++	vlsseg4e128.v v4, (a0), a1
++	vlsseg4e128.v v4, 0(a0), a1
++	vlsseg4e128.v v4, (a0), a1, v0.t
++	vssseg4e128.v v4, (a0), a1
++	vssseg4e128.v v4, 0(a0), a1
++	vssseg4e128.v v4, (a0), a1, v0.t
++
++	vlsseg5e128.v v4, (a0), a1
++	vlsseg5e128.v v4, 0(a0), a1
++	vlsseg5e128.v v4, (a0), a1, v0.t
++	vssseg5e128.v v4, (a0), a1
++	vssseg5e128.v v4, 0(a0), a1
++	vssseg5e128.v v4, (a0), a1, v0.t
++
++	vlsseg6e128.v v4, (a0), a1
++	vlsseg6e128.v v4, 0(a0), a1
++	vlsseg6e128.v v4, (a0), a1, v0.t
++	vssseg6e128.v v4, (a0), a1
++	vssseg6e128.v v4, 0(a0), a1
++	vssseg6e128.v v4, (a0), a1, v0.t
++
++	vlsseg7e128.v v4, (a0), a1
++	vlsseg7e128.v v4, 0(a0), a1
++	vlsseg7e128.v v4, (a0), a1, v0.t
++	vssseg7e128.v v4, (a0), a1
++	vssseg7e128.v v4, 0(a0), a1
++	vssseg7e128.v v4, (a0), a1, v0.t
++
++	vlsseg8e128.v v4, (a0), a1
++	vlsseg8e128.v v4, 0(a0), a1
++	vlsseg8e128.v v4, (a0), a1, v0.t
++	vssseg8e128.v v4, (a0), a1
++	vssseg8e128.v v4, 0(a0), a1
++	vssseg8e128.v v4, (a0), a1, v0.t
++
++	vlsseg2e256.v v4, (a0), a1
++	vlsseg2e256.v v4, 0(a0), a1
++	vlsseg2e256.v v4, (a0), a1, v0.t
++	vssseg2e256.v v4, (a0), a1
++	vssseg2e256.v v4, 0(a0), a1
++	vssseg2e256.v v4, (a0), a1, v0.t
++
++	vlsseg3e256.v v4, (a0), a1
++	vlsseg3e256.v v4, 0(a0), a1
++	vlsseg3e256.v v4, (a0), a1, v0.t
++	vssseg3e256.v v4, (a0), a1
++	vssseg3e256.v v4, 0(a0), a1
++	vssseg3e256.v v4, (a0), a1, v0.t
++
++	vlsseg4e256.v v4, (a0), a1
++	vlsseg4e256.v v4, 0(a0), a1
++	vlsseg4e256.v v4, (a0), a1, v0.t
++	vssseg4e256.v v4, (a0), a1
++	vssseg4e256.v v4, 0(a0), a1
++	vssseg4e256.v v4, (a0), a1, v0.t
++
++	vlsseg5e256.v v4, (a0), a1
++	vlsseg5e256.v v4, 0(a0), a1
++	vlsseg5e256.v v4, (a0), a1, v0.t
++	vssseg5e256.v v4, (a0), a1
++	vssseg5e256.v v4, 0(a0), a1
++	vssseg5e256.v v4, (a0), a1, v0.t
++
++	vlsseg6e256.v v4, (a0), a1
++	vlsseg6e256.v v4, 0(a0), a1
++	vlsseg6e256.v v4, (a0), a1, v0.t
++	vssseg6e256.v v4, (a0), a1
++	vssseg6e256.v v4, 0(a0), a1
++	vssseg6e256.v v4, (a0), a1, v0.t
++
++	vlsseg7e256.v v4, (a0), a1
++	vlsseg7e256.v v4, 0(a0), a1
++	vlsseg7e256.v v4, (a0), a1, v0.t
++	vssseg7e256.v v4, (a0), a1
++	vssseg7e256.v v4, 0(a0), a1
++	vssseg7e256.v v4, (a0), a1, v0.t
++
++	vlsseg8e256.v v4, (a0), a1
++	vlsseg8e256.v v4, 0(a0), a1
++	vlsseg8e256.v v4, (a0), a1, v0.t
++	vssseg8e256.v v4, (a0), a1
++	vssseg8e256.v v4, 0(a0), a1
++	vssseg8e256.v v4, (a0), a1, v0.t
++
++	vlsseg2e512.v v4, (a0), a1
++	vlsseg2e512.v v4, 0(a0), a1
++	vlsseg2e512.v v4, (a0), a1, v0.t
++	vssseg2e512.v v4, (a0), a1
++	vssseg2e512.v v4, 0(a0), a1
++	vssseg2e512.v v4, (a0), a1, v0.t
++
++	vlsseg3e512.v v4, (a0), a1
++	vlsseg3e512.v v4, 0(a0), a1
++	vlsseg3e512.v v4, (a0), a1, v0.t
++	vssseg3e512.v v4, (a0), a1
++	vssseg3e512.v v4, 0(a0), a1
++	vssseg3e512.v v4, (a0), a1, v0.t
++
++	vlsseg4e512.v v4, (a0), a1
++	vlsseg4e512.v v4, 0(a0), a1
++	vlsseg4e512.v v4, (a0), a1, v0.t
++	vssseg4e512.v v4, (a0), a1
++	vssseg4e512.v v4, 0(a0), a1
++	vssseg4e512.v v4, (a0), a1, v0.t
++
++	vlsseg5e512.v v4, (a0), a1
++	vlsseg5e512.v v4, 0(a0), a1
++	vlsseg5e512.v v4, (a0), a1, v0.t
++	vssseg5e512.v v4, (a0), a1
++	vssseg5e512.v v4, 0(a0), a1
++	vssseg5e512.v v4, (a0), a1, v0.t
++
++	vlsseg6e512.v v4, (a0), a1
++	vlsseg6e512.v v4, 0(a0), a1
++	vlsseg6e512.v v4, (a0), a1, v0.t
++	vssseg6e512.v v4, (a0), a1
++	vssseg6e512.v v4, 0(a0), a1
++	vssseg6e512.v v4, (a0), a1, v0.t
++
++	vlsseg7e512.v v4, (a0), a1
++	vlsseg7e512.v v4, 0(a0), a1
++	vlsseg7e512.v v4, (a0), a1, v0.t
++	vssseg7e512.v v4, (a0), a1
++	vssseg7e512.v v4, 0(a0), a1
++	vssseg7e512.v v4, (a0), a1, v0.t
++
++	vlsseg8e512.v v4, (a0), a1
++	vlsseg8e512.v v4, 0(a0), a1
++	vlsseg8e512.v v4, (a0), a1, v0.t
++	vssseg8e512.v v4, (a0), a1
++	vssseg8e512.v v4, 0(a0), a1
++	vssseg8e512.v v4, (a0), a1, v0.t
++
++	vlsseg2e1024.v v4, (a0), a1
++	vlsseg2e1024.v v4, 0(a0), a1
++	vlsseg2e1024.v v4, (a0), a1, v0.t
++	vssseg2e1024.v v4, (a0), a1
++	vssseg2e1024.v v4, 0(a0), a1
++	vssseg2e1024.v v4, (a0), a1, v0.t
++
++	vlsseg3e1024.v v4, (a0), a1
++	vlsseg3e1024.v v4, 0(a0), a1
++	vlsseg3e1024.v v4, (a0), a1, v0.t
++	vssseg3e1024.v v4, (a0), a1
++	vssseg3e1024.v v4, 0(a0), a1
++	vssseg3e1024.v v4, (a0), a1, v0.t
++
++	vlsseg4e1024.v v4, (a0), a1
++	vlsseg4e1024.v v4, 0(a0), a1
++	vlsseg4e1024.v v4, (a0), a1, v0.t
++	vssseg4e1024.v v4, (a0), a1
++	vssseg4e1024.v v4, 0(a0), a1
++	vssseg4e1024.v v4, (a0), a1, v0.t
++
++	vlsseg5e1024.v v4, (a0), a1
++	vlsseg5e1024.v v4, 0(a0), a1
++	vlsseg5e1024.v v4, (a0), a1, v0.t
++	vssseg5e1024.v v4, (a0), a1
++	vssseg5e1024.v v4, 0(a0), a1
++	vssseg5e1024.v v4, (a0), a1, v0.t
++
++	vlsseg6e1024.v v4, (a0), a1
++	vlsseg6e1024.v v4, 0(a0), a1
++	vlsseg6e1024.v v4, (a0), a1, v0.t
++	vssseg6e1024.v v4, (a0), a1
++	vssseg6e1024.v v4, 0(a0), a1
++	vssseg6e1024.v v4, (a0), a1, v0.t
++
++	vlsseg7e1024.v v4, (a0), a1
++	vlsseg7e1024.v v4, 0(a0), a1
++	vlsseg7e1024.v v4, (a0), a1, v0.t
++	vssseg7e1024.v v4, (a0), a1
++	vssseg7e1024.v v4, 0(a0), a1
++	vssseg7e1024.v v4, (a0), a1, v0.t
++
++	vlsseg8e1024.v v4, (a0), a1
++	vlsseg8e1024.v v4, 0(a0), a1
++	vlsseg8e1024.v v4, (a0), a1, v0.t
++	vssseg8e1024.v v4, (a0), a1
++	vssseg8e1024.v v4, 0(a0), a1
++	vssseg8e1024.v v4, (a0), a1, v0.t
++
++	vlxseg2ei8.v v4, (a0), v12
++	vlxseg2ei8.v v4, 0(a0), v12
++	vlxseg2ei8.v v4, (a0), v12, v0.t
++	vsxseg2ei8.v v4, (a0), v12
++	vsxseg2ei8.v v4, 0(a0), v12
++	vsxseg2ei8.v v4, (a0), v12, v0.t
++
++	vlxseg3ei8.v v4, (a0), v12
++	vlxseg3ei8.v v4, 0(a0), v12
++	vlxseg3ei8.v v4, (a0), v12, v0.t
++	vsxseg3ei8.v v4, (a0), v12
++	vsxseg3ei8.v v4, 0(a0), v12
++	vsxseg3ei8.v v4, (a0), v12, v0.t
++
++	vlxseg4ei8.v v4, (a0), v12
++	vlxseg4ei8.v v4, 0(a0), v12
++	vlxseg4ei8.v v4, (a0), v12, v0.t
++	vsxseg4ei8.v v4, (a0), v12
++	vsxseg4ei8.v v4, 0(a0), v12
++	vsxseg4ei8.v v4, (a0), v12, v0.t
++
++	vlxseg5ei8.v v4, (a0), v12
++	vlxseg5ei8.v v4, 0(a0), v12
++	vlxseg5ei8.v v4, (a0), v12, v0.t
++	vsxseg5ei8.v v4, (a0), v12
++	vsxseg5ei8.v v4, 0(a0), v12
++	vsxseg5ei8.v v4, (a0), v12, v0.t
++
++	vlxseg6ei8.v v4, (a0), v12
++	vlxseg6ei8.v v4, 0(a0), v12
++	vlxseg6ei8.v v4, (a0), v12, v0.t
++	vsxseg6ei8.v v4, (a0), v12
++	vsxseg6ei8.v v4, 0(a0), v12
++	vsxseg6ei8.v v4, (a0), v12, v0.t
++
++	vlxseg7ei8.v v4, (a0), v12
++	vlxseg7ei8.v v4, 0(a0), v12
++	vlxseg7ei8.v v4, (a0), v12, v0.t
++	vsxseg7ei8.v v4, (a0), v12
++	vsxseg7ei8.v v4, 0(a0), v12
++	vsxseg7ei8.v v4, (a0), v12, v0.t
++
++	vlxseg8ei8.v v4, (a0), v12
++	vlxseg8ei8.v v4, 0(a0), v12
++	vlxseg8ei8.v v4, (a0), v12, v0.t
++	vsxseg8ei8.v v4, (a0), v12
++	vsxseg8ei8.v v4, 0(a0), v12
++	vsxseg8ei8.v v4, (a0), v12, v0.t
++
++	vlxseg2ei16.v v4, (a0), v12
++	vlxseg2ei16.v v4, 0(a0), v12
++	vlxseg2ei16.v v4, (a0), v12, v0.t
++	vsxseg2ei16.v v4, (a0), v12
++	vsxseg2ei16.v v4, 0(a0), v12
++	vsxseg2ei16.v v4, (a0), v12, v0.t
++
++	vlxseg3ei16.v v4, (a0), v12
++	vlxseg3ei16.v v4, 0(a0), v12
++	vlxseg3ei16.v v4, (a0), v12, v0.t
++	vsxseg3ei16.v v4, (a0), v12
++	vsxseg3ei16.v v4, 0(a0), v12
++	vsxseg3ei16.v v4, (a0), v12, v0.t
++
++	vlxseg4ei16.v v4, (a0), v12
++	vlxseg4ei16.v v4, 0(a0), v12
++	vlxseg4ei16.v v4, (a0), v12, v0.t
++	vsxseg4ei16.v v4, (a0), v12
++	vsxseg4ei16.v v4, 0(a0), v12
++	vsxseg4ei16.v v4, (a0), v12, v0.t
++
++	vlxseg5ei16.v v4, (a0), v12
++	vlxseg5ei16.v v4, 0(a0), v12
++	vlxseg5ei16.v v4, (a0), v12, v0.t
++	vsxseg5ei16.v v4, (a0), v12
++	vsxseg5ei16.v v4, 0(a0), v12
++	vsxseg5ei16.v v4, (a0), v12, v0.t
++
++	vlxseg6ei16.v v4, (a0), v12
++	vlxseg6ei16.v v4, 0(a0), v12
++	vlxseg6ei16.v v4, (a0), v12, v0.t
++	vsxseg6ei16.v v4, (a0), v12
++	vsxseg6ei16.v v4, 0(a0), v12
++	vsxseg6ei16.v v4, (a0), v12, v0.t
++
++	vlxseg7ei16.v v4, (a0), v12
++	vlxseg7ei16.v v4, 0(a0), v12
++	vlxseg7ei16.v v4, (a0), v12, v0.t
++	vsxseg7ei16.v v4, (a0), v12
++	vsxseg7ei16.v v4, 0(a0), v12
++	vsxseg7ei16.v v4, (a0), v12, v0.t
++
++	vlxseg8ei16.v v4, (a0), v12
++	vlxseg8ei16.v v4, 0(a0), v12
++	vlxseg8ei16.v v4, (a0), v12, v0.t
++	vsxseg8ei16.v v4, (a0), v12
++	vsxseg8ei16.v v4, 0(a0), v12
++	vsxseg8ei16.v v4, (a0), v12, v0.t
++
++	vlxseg2ei32.v v4, (a0), v12
++	vlxseg2ei32.v v4, 0(a0), v12
++	vlxseg2ei32.v v4, (a0), v12, v0.t
++	vsxseg2ei32.v v4, (a0), v12
++	vsxseg2ei32.v v4, 0(a0), v12
++	vsxseg2ei32.v v4, (a0), v12, v0.t
++
++	vlxseg3ei32.v v4, (a0), v12
++	vlxseg3ei32.v v4, 0(a0), v12
++	vlxseg3ei32.v v4, (a0), v12, v0.t
++	vsxseg3ei32.v v4, (a0), v12
++	vsxseg3ei32.v v4, 0(a0), v12
++	vsxseg3ei32.v v4, (a0), v12, v0.t
++
++	vlxseg4ei32.v v4, (a0), v12
++	vlxseg4ei32.v v4, 0(a0), v12
++	vlxseg4ei32.v v4, (a0), v12, v0.t
++	vsxseg4ei32.v v4, (a0), v12
++	vsxseg4ei32.v v4, 0(a0), v12
++	vsxseg4ei32.v v4, (a0), v12, v0.t
++
++	vlxseg5ei32.v v4, (a0), v12
++	vlxseg5ei32.v v4, 0(a0), v12
++	vlxseg5ei32.v v4, (a0), v12, v0.t
++	vsxseg5ei32.v v4, (a0), v12
++	vsxseg5ei32.v v4, 0(a0), v12
++	vsxseg5ei32.v v4, (a0), v12, v0.t
++
++	vlxseg6ei32.v v4, (a0), v12
++	vlxseg6ei32.v v4, 0(a0), v12
++	vlxseg6ei32.v v4, (a0), v12, v0.t
++	vsxseg6ei32.v v4, (a0), v12
++	vsxseg6ei32.v v4, 0(a0), v12
++	vsxseg6ei32.v v4, (a0), v12, v0.t
++
++	vlxseg7ei32.v v4, (a0), v12
++	vlxseg7ei32.v v4, 0(a0), v12
++	vlxseg7ei32.v v4, (a0), v12, v0.t
++	vsxseg7ei32.v v4, (a0), v12
++	vsxseg7ei32.v v4, 0(a0), v12
++	vsxseg7ei32.v v4, (a0), v12, v0.t
++
++	vlxseg8ei32.v v4, (a0), v12
++	vlxseg8ei32.v v4, 0(a0), v12
++	vlxseg8ei32.v v4, (a0), v12, v0.t
++	vsxseg8ei32.v v4, (a0), v12
++	vsxseg8ei32.v v4, 0(a0), v12
++	vsxseg8ei32.v v4, (a0), v12, v0.t
++
++	vlxseg2ei64.v v4, (a0), v12
++	vlxseg2ei64.v v4, 0(a0), v12
++	vlxseg2ei64.v v4, (a0), v12, v0.t
++	vsxseg2ei64.v v4, (a0), v12
++	vsxseg2ei64.v v4, 0(a0), v12
++	vsxseg2ei64.v v4, (a0), v12, v0.t
++
++	vlxseg3ei64.v v4, (a0), v12
++	vlxseg3ei64.v v4, 0(a0), v12
++	vlxseg3ei64.v v4, (a0), v12, v0.t
++	vsxseg3ei64.v v4, (a0), v12
++	vsxseg3ei64.v v4, 0(a0), v12
++	vsxseg3ei64.v v4, (a0), v12, v0.t
++
++	vlxseg4ei64.v v4, (a0), v12
++	vlxseg4ei64.v v4, 0(a0), v12
++	vlxseg4ei64.v v4, (a0), v12, v0.t
++	vsxseg4ei64.v v4, (a0), v12
++	vsxseg4ei64.v v4, 0(a0), v12
++	vsxseg4ei64.v v4, (a0), v12, v0.t
++
++	vlxseg5ei64.v v4, (a0), v12
++	vlxseg5ei64.v v4, 0(a0), v12
++	vlxseg5ei64.v v4, (a0), v12, v0.t
++	vsxseg5ei64.v v4, (a0), v12
++	vsxseg5ei64.v v4, 0(a0), v12
++	vsxseg5ei64.v v4, (a0), v12, v0.t
++
++	vlxseg6ei64.v v4, (a0), v12
++	vlxseg6ei64.v v4, 0(a0), v12
++	vlxseg6ei64.v v4, (a0), v12, v0.t
++	vsxseg6ei64.v v4, (a0), v12
++	vsxseg6ei64.v v4, 0(a0), v12
++	vsxseg6ei64.v v4, (a0), v12, v0.t
++
++	vlxseg7ei64.v v4, (a0), v12
++	vlxseg7ei64.v v4, 0(a0), v12
++	vlxseg7ei64.v v4, (a0), v12, v0.t
++	vsxseg7ei64.v v4, (a0), v12
++	vsxseg7ei64.v v4, 0(a0), v12
++	vsxseg7ei64.v v4, (a0), v12, v0.t
++
++	vlxseg8ei64.v v4, (a0), v12
++	vlxseg8ei64.v v4, 0(a0), v12
++	vlxseg8ei64.v v4, (a0), v12, v0.t
++	vsxseg8ei64.v v4, (a0), v12
++	vsxseg8ei64.v v4, 0(a0), v12
++	vsxseg8ei64.v v4, (a0), v12, v0.t
++
++	vlxseg2ei128.v v4, (a0), v12
++	vlxseg2ei128.v v4, 0(a0), v12
++	vlxseg2ei128.v v4, (a0), v12, v0.t
++	vsxseg2ei128.v v4, (a0), v12
++	vsxseg2ei128.v v4, 0(a0), v12
++	vsxseg2ei128.v v4, (a0), v12, v0.t
++
++	vlxseg3ei128.v v4, (a0), v12
++	vlxseg3ei128.v v4, 0(a0), v12
++	vlxseg3ei128.v v4, (a0), v12, v0.t
++	vsxseg3ei128.v v4, (a0), v12
++	vsxseg3ei128.v v4, 0(a0), v12
++	vsxseg3ei128.v v4, (a0), v12, v0.t
++
++	vlxseg4ei128.v v4, (a0), v12
++	vlxseg4ei128.v v4, 0(a0), v12
++	vlxseg4ei128.v v4, (a0), v12, v0.t
++	vsxseg4ei128.v v4, (a0), v12
++	vsxseg4ei128.v v4, 0(a0), v12
++	vsxseg4ei128.v v4, (a0), v12, v0.t
++
++	vlxseg5ei128.v v4, (a0), v12
++	vlxseg5ei128.v v4, 0(a0), v12
++	vlxseg5ei128.v v4, (a0), v12, v0.t
++	vsxseg5ei128.v v4, (a0), v12
++	vsxseg5ei128.v v4, 0(a0), v12
++	vsxseg5ei128.v v4, (a0), v12, v0.t
++
++	vlxseg6ei128.v v4, (a0), v12
++	vlxseg6ei128.v v4, 0(a0), v12
++	vlxseg6ei128.v v4, (a0), v12, v0.t
++	vsxseg6ei128.v v4, (a0), v12
++	vsxseg6ei128.v v4, 0(a0), v12
++	vsxseg6ei128.v v4, (a0), v12, v0.t
++
++	vlxseg7ei128.v v4, (a0), v12
++	vlxseg7ei128.v v4, 0(a0), v12
++	vlxseg7ei128.v v4, (a0), v12, v0.t
++	vsxseg7ei128.v v4, (a0), v12
++	vsxseg7ei128.v v4, 0(a0), v12
++	vsxseg7ei128.v v4, (a0), v12, v0.t
++
++	vlxseg8ei128.v v4, (a0), v12
++	vlxseg8ei128.v v4, 0(a0), v12
++	vlxseg8ei128.v v4, (a0), v12, v0.t
++	vsxseg8ei128.v v4, (a0), v12
++	vsxseg8ei128.v v4, 0(a0), v12
++	vsxseg8ei128.v v4, (a0), v12, v0.t
++
++	vlxseg2ei256.v v4, (a0), v12
++	vlxseg2ei256.v v4, 0(a0), v12
++	vlxseg2ei256.v v4, (a0), v12, v0.t
++	vsxseg2ei256.v v4, (a0), v12
++	vsxseg2ei256.v v4, 0(a0), v12
++	vsxseg2ei256.v v4, (a0), v12, v0.t
++
++	vlxseg3ei256.v v4, (a0), v12
++	vlxseg3ei256.v v4, 0(a0), v12
++	vlxseg3ei256.v v4, (a0), v12, v0.t
++	vsxseg3ei256.v v4, (a0), v12
++	vsxseg3ei256.v v4, 0(a0), v12
++	vsxseg3ei256.v v4, (a0), v12, v0.t
++
++	vlxseg4ei256.v v4, (a0), v12
++	vlxseg4ei256.v v4, 0(a0), v12
++	vlxseg4ei256.v v4, (a0), v12, v0.t
++	vsxseg4ei256.v v4, (a0), v12
++	vsxseg4ei256.v v4, 0(a0), v12
++	vsxseg4ei256.v v4, (a0), v12, v0.t
++
++	vlxseg5ei256.v v4, (a0), v12
++	vlxseg5ei256.v v4, 0(a0), v12
++	vlxseg5ei256.v v4, (a0), v12, v0.t
++	vsxseg5ei256.v v4, (a0), v12
++	vsxseg5ei256.v v4, 0(a0), v12
++	vsxseg5ei256.v v4, (a0), v12, v0.t
++
++	vlxseg6ei256.v v4, (a0), v12
++	vlxseg6ei256.v v4, 0(a0), v12
++	vlxseg6ei256.v v4, (a0), v12, v0.t
++	vsxseg6ei256.v v4, (a0), v12
++	vsxseg6ei256.v v4, 0(a0), v12
++	vsxseg6ei256.v v4, (a0), v12, v0.t
++
++	vlxseg7ei256.v v4, (a0), v12
++	vlxseg7ei256.v v4, 0(a0), v12
++	vlxseg7ei256.v v4, (a0), v12, v0.t
++	vsxseg7ei256.v v4, (a0), v12
++	vsxseg7ei256.v v4, 0(a0), v12
++	vsxseg7ei256.v v4, (a0), v12, v0.t
++
++	vlxseg8ei256.v v4, (a0), v12
++	vlxseg8ei256.v v4, 0(a0), v12
++	vlxseg8ei256.v v4, (a0), v12, v0.t
++	vsxseg8ei256.v v4, (a0), v12
++	vsxseg8ei256.v v4, 0(a0), v12
++	vsxseg8ei256.v v4, (a0), v12, v0.t
++
++	vlxseg2ei512.v v4, (a0), v12
++	vlxseg2ei512.v v4, 0(a0), v12
++	vlxseg2ei512.v v4, (a0), v12, v0.t
++	vsxseg2ei512.v v4, (a0), v12
++	vsxseg2ei512.v v4, 0(a0), v12
++	vsxseg2ei512.v v4, (a0), v12, v0.t
++
++	vlxseg3ei512.v v4, (a0), v12
++	vlxseg3ei512.v v4, 0(a0), v12
++	vlxseg3ei512.v v4, (a0), v12, v0.t
++	vsxseg3ei512.v v4, (a0), v12
++	vsxseg3ei512.v v4, 0(a0), v12
++	vsxseg3ei512.v v4, (a0), v12, v0.t
++
++	vlxseg4ei512.v v4, (a0), v12
++	vlxseg4ei512.v v4, 0(a0), v12
++	vlxseg4ei512.v v4, (a0), v12, v0.t
++	vsxseg4ei512.v v4, (a0), v12
++	vsxseg4ei512.v v4, 0(a0), v12
++	vsxseg4ei512.v v4, (a0), v12, v0.t
++
++	vlxseg5ei512.v v4, (a0), v12
++	vlxseg5ei512.v v4, 0(a0), v12
++	vlxseg5ei512.v v4, (a0), v12, v0.t
++	vsxseg5ei512.v v4, (a0), v12
++	vsxseg5ei512.v v4, 0(a0), v12
++	vsxseg5ei512.v v4, (a0), v12, v0.t
++
++	vlxseg6ei512.v v4, (a0), v12
++	vlxseg6ei512.v v4, 0(a0), v12
++	vlxseg6ei512.v v4, (a0), v12, v0.t
++	vsxseg6ei512.v v4, (a0), v12
++	vsxseg6ei512.v v4, 0(a0), v12
++	vsxseg6ei512.v v4, (a0), v12, v0.t
++
++	vlxseg7ei512.v v4, (a0), v12
++	vlxseg7ei512.v v4, 0(a0), v12
++	vlxseg7ei512.v v4, (a0), v12, v0.t
++	vsxseg7ei512.v v4, (a0), v12
++	vsxseg7ei512.v v4, 0(a0), v12
++	vsxseg7ei512.v v4, (a0), v12, v0.t
++
++	vlxseg8ei512.v v4, (a0), v12
++	vlxseg8ei512.v v4, 0(a0), v12
++	vlxseg8ei512.v v4, (a0), v12, v0.t
++	vsxseg8ei512.v v4, (a0), v12
++	vsxseg8ei512.v v4, 0(a0), v12
++	vsxseg8ei512.v v4, (a0), v12, v0.t
++
++	vlxseg2ei1024.v v4, (a0), v12
++	vlxseg2ei1024.v v4, 0(a0), v12
++	vlxseg2ei1024.v v4, (a0), v12, v0.t
++	vsxseg2ei1024.v v4, (a0), v12
++	vsxseg2ei1024.v v4, 0(a0), v12
++	vsxseg2ei1024.v v4, (a0), v12, v0.t
++
++	vlxseg3ei1024.v v4, (a0), v12
++	vlxseg3ei1024.v v4, 0(a0), v12
++	vlxseg3ei1024.v v4, (a0), v12, v0.t
++	vsxseg3ei1024.v v4, (a0), v12
++	vsxseg3ei1024.v v4, 0(a0), v12
++	vsxseg3ei1024.v v4, (a0), v12, v0.t
++
++	vlxseg4ei1024.v v4, (a0), v12
++	vlxseg4ei1024.v v4, 0(a0), v12
++	vlxseg4ei1024.v v4, (a0), v12, v0.t
++	vsxseg4ei1024.v v4, (a0), v12
++	vsxseg4ei1024.v v4, 0(a0), v12
++	vsxseg4ei1024.v v4, (a0), v12, v0.t
++
++	vlxseg5ei1024.v v4, (a0), v12
++	vlxseg5ei1024.v v4, 0(a0), v12
++	vlxseg5ei1024.v v4, (a0), v12, v0.t
++	vsxseg5ei1024.v v4, (a0), v12
++	vsxseg5ei1024.v v4, 0(a0), v12
++	vsxseg5ei1024.v v4, (a0), v12, v0.t
++
++	vlxseg6ei1024.v v4, (a0), v12
++	vlxseg6ei1024.v v4, 0(a0), v12
++	vlxseg6ei1024.v v4, (a0), v12, v0.t
++	vsxseg6ei1024.v v4, (a0), v12
++	vsxseg6ei1024.v v4, 0(a0), v12
++	vsxseg6ei1024.v v4, (a0), v12, v0.t
++
++	vlxseg7ei1024.v v4, (a0), v12
++	vlxseg7ei1024.v v4, 0(a0), v12
++	vlxseg7ei1024.v v4, (a0), v12, v0.t
++	vsxseg7ei1024.v v4, (a0), v12
++	vsxseg7ei1024.v v4, 0(a0), v12
++	vsxseg7ei1024.v v4, (a0), v12, v0.t
++
++	vlxseg8ei1024.v v4, (a0), v12
++	vlxseg8ei1024.v v4, 0(a0), v12
++	vlxseg8ei1024.v v4, (a0), v12, v0.t
++	vsxseg8ei1024.v v4, (a0), v12
++	vsxseg8ei1024.v v4, 0(a0), v12
++	vsxseg8ei1024.v v4, (a0), v12, v0.t
++
++	vlseg2e8ff.v v4, (a0)
++	vlseg2e8ff.v v4, 0(a0)
++	vlseg2e8ff.v v4, (a0), v0.t
++
++	vlseg3e8ff.v v4, (a0)
++	vlseg3e8ff.v v4, 0(a0)
++	vlseg3e8ff.v v4, (a0), v0.t
++
++	vlseg4e8ff.v v4, (a0)
++	vlseg4e8ff.v v4, 0(a0)
++	vlseg4e8ff.v v4, (a0), v0.t
++
++	vlseg5e8ff.v v4, (a0)
++	vlseg5e8ff.v v4, 0(a0)
++	vlseg5e8ff.v v4, (a0), v0.t
++
++	vlseg6e8ff.v v4, (a0)
++	vlseg6e8ff.v v4, 0(a0)
++	vlseg6e8ff.v v4, (a0), v0.t
++
++	vlseg7e8ff.v v4, (a0)
++	vlseg7e8ff.v v4, 0(a0)
++	vlseg7e8ff.v v4, (a0), v0.t
++
++	vlseg8e8ff.v v4, (a0)
++	vlseg8e8ff.v v4, 0(a0)
++	vlseg8e8ff.v v4, (a0), v0.t
++
++	vlseg2e16ff.v v4, (a0)
++	vlseg2e16ff.v v4, 0(a0)
++	vlseg2e16ff.v v4, (a0), v0.t
++
++	vlseg3e16ff.v v4, (a0)
++	vlseg3e16ff.v v4, 0(a0)
++	vlseg3e16ff.v v4, (a0), v0.t
++
++	vlseg4e16ff.v v4, (a0)
++	vlseg4e16ff.v v4, 0(a0)
++	vlseg4e16ff.v v4, (a0), v0.t
++
++	vlseg5e16ff.v v4, (a0)
++	vlseg5e16ff.v v4, 0(a0)
++	vlseg5e16ff.v v4, (a0), v0.t
++
++	vlseg6e16ff.v v4, (a0)
++	vlseg6e16ff.v v4, 0(a0)
++	vlseg6e16ff.v v4, (a0), v0.t
++
++	vlseg7e16ff.v v4, (a0)
++	vlseg7e16ff.v v4, 0(a0)
++	vlseg7e16ff.v v4, (a0), v0.t
++
++	vlseg8e16ff.v v4, (a0)
++	vlseg8e16ff.v v4, 0(a0)
++	vlseg8e16ff.v v4, (a0), v0.t
++
++	vlseg2e32ff.v v4, (a0)
++	vlseg2e32ff.v v4, 0(a0)
++	vlseg2e32ff.v v4, (a0), v0.t
++
++	vlseg3e32ff.v v4, (a0)
++	vlseg3e32ff.v v4, 0(a0)
++	vlseg3e32ff.v v4, (a0), v0.t
++
++	vlseg4e32ff.v v4, (a0)
++	vlseg4e32ff.v v4, 0(a0)
++	vlseg4e32ff.v v4, (a0), v0.t
++
++	vlseg5e32ff.v v4, (a0)
++	vlseg5e32ff.v v4, 0(a0)
++	vlseg5e32ff.v v4, (a0), v0.t
++
++	vlseg6e32ff.v v4, (a0)
++	vlseg6e32ff.v v4, 0(a0)
++	vlseg6e32ff.v v4, (a0), v0.t
++
++	vlseg7e32ff.v v4, (a0)
++	vlseg7e32ff.v v4, 0(a0)
++	vlseg7e32ff.v v4, (a0), v0.t
++
++	vlseg8e32ff.v v4, (a0)
++	vlseg8e32ff.v v4, 0(a0)
++	vlseg8e32ff.v v4, (a0), v0.t
++
++	vlseg2e64ff.v v4, (a0)
++	vlseg2e64ff.v v4, 0(a0)
++	vlseg2e64ff.v v4, (a0), v0.t
++
++	vlseg3e64ff.v v4, (a0)
++	vlseg3e64ff.v v4, 0(a0)
++	vlseg3e64ff.v v4, (a0), v0.t
++
++	vlseg4e64ff.v v4, (a0)
++	vlseg4e64ff.v v4, 0(a0)
++	vlseg4e64ff.v v4, (a0), v0.t
++
++	vlseg5e64ff.v v4, (a0)
++	vlseg5e64ff.v v4, 0(a0)
++	vlseg5e64ff.v v4, (a0), v0.t
++
++	vlseg6e64ff.v v4, (a0)
++	vlseg6e64ff.v v4, 0(a0)
++	vlseg6e64ff.v v4, (a0), v0.t
++
++	vlseg7e64ff.v v4, (a0)
++	vlseg7e64ff.v v4, 0(a0)
++	vlseg7e64ff.v v4, (a0), v0.t
++
++	vlseg8e64ff.v v4, (a0)
++	vlseg8e64ff.v v4, 0(a0)
++	vlseg8e64ff.v v4, (a0), v0.t
++
++	vlseg2e128ff.v v4, (a0)
++	vlseg2e128ff.v v4, 0(a0)
++	vlseg2e128ff.v v4, (a0), v0.t
++
++	vlseg3e128ff.v v4, (a0)
++	vlseg3e128ff.v v4, 0(a0)
++	vlseg3e128ff.v v4, (a0), v0.t
++
++	vlseg4e128ff.v v4, (a0)
++	vlseg4e128ff.v v4, 0(a0)
++	vlseg4e128ff.v v4, (a0), v0.t
++
++	vlseg5e128ff.v v4, (a0)
++	vlseg5e128ff.v v4, 0(a0)
++	vlseg5e128ff.v v4, (a0), v0.t
++
++	vlseg6e128ff.v v4, (a0)
++	vlseg6e128ff.v v4, 0(a0)
++	vlseg6e128ff.v v4, (a0), v0.t
++
++	vlseg7e128ff.v v4, (a0)
++	vlseg7e128ff.v v4, 0(a0)
++	vlseg7e128ff.v v4, (a0), v0.t
++
++	vlseg8e128ff.v v4, (a0)
++	vlseg8e128ff.v v4, 0(a0)
++	vlseg8e128ff.v v4, (a0), v0.t
++
++	vlseg2e256ff.v v4, (a0)
++	vlseg2e256ff.v v4, 0(a0)
++	vlseg2e256ff.v v4, (a0), v0.t
++
++	vlseg3e256ff.v v4, (a0)
++	vlseg3e256ff.v v4, 0(a0)
++	vlseg3e256ff.v v4, (a0), v0.t
++
++	vlseg4e256ff.v v4, (a0)
++	vlseg4e256ff.v v4, 0(a0)
++	vlseg4e256ff.v v4, (a0), v0.t
++
++	vlseg5e256ff.v v4, (a0)
++	vlseg5e256ff.v v4, 0(a0)
++	vlseg5e256ff.v v4, (a0), v0.t
++
++	vlseg6e256ff.v v4, (a0)
++	vlseg6e256ff.v v4, 0(a0)
++	vlseg6e256ff.v v4, (a0), v0.t
++
++	vlseg7e256ff.v v4, (a0)
++	vlseg7e256ff.v v4, 0(a0)
++	vlseg7e256ff.v v4, (a0), v0.t
++
++	vlseg8e256ff.v v4, (a0)
++	vlseg8e256ff.v v4, 0(a0)
++	vlseg8e256ff.v v4, (a0), v0.t
++
++	vlseg2e512ff.v v4, (a0)
++	vlseg2e512ff.v v4, 0(a0)
++	vlseg2e512ff.v v4, (a0), v0.t
++
++	vlseg3e512ff.v v4, (a0)
++	vlseg3e512ff.v v4, 0(a0)
++	vlseg3e512ff.v v4, (a0), v0.t
++
++	vlseg4e512ff.v v4, (a0)
++	vlseg4e512ff.v v4, 0(a0)
++	vlseg4e512ff.v v4, (a0), v0.t
++
++	vlseg5e512ff.v v4, (a0)
++	vlseg5e512ff.v v4, 0(a0)
++	vlseg5e512ff.v v4, (a0), v0.t
++
++	vlseg6e512ff.v v4, (a0)
++	vlseg6e512ff.v v4, 0(a0)
++	vlseg6e512ff.v v4, (a0), v0.t
++
++	vlseg7e512ff.v v4, (a0)
++	vlseg7e512ff.v v4, 0(a0)
++	vlseg7e512ff.v v4, (a0), v0.t
++
++	vlseg8e512ff.v v4, (a0)
++	vlseg8e512ff.v v4, 0(a0)
++	vlseg8e512ff.v v4, (a0), v0.t
++
++	vlseg2e1024ff.v v4, (a0)
++	vlseg2e1024ff.v v4, 0(a0)
++	vlseg2e1024ff.v v4, (a0), v0.t
++
++	vlseg3e1024ff.v v4, (a0)
++	vlseg3e1024ff.v v4, 0(a0)
++	vlseg3e1024ff.v v4, (a0), v0.t
++
++	vlseg4e1024ff.v v4, (a0)
++	vlseg4e1024ff.v v4, 0(a0)
++	vlseg4e1024ff.v v4, (a0), v0.t
++
++	vlseg5e1024ff.v v4, (a0)
++	vlseg5e1024ff.v v4, 0(a0)
++	vlseg5e1024ff.v v4, (a0), v0.t
++
++	vlseg6e1024ff.v v4, (a0)
++	vlseg6e1024ff.v v4, 0(a0)
++	vlseg6e1024ff.v v4, (a0), v0.t
++
++	vlseg7e1024ff.v v4, (a0)
++	vlseg7e1024ff.v v4, 0(a0)
++	vlseg7e1024ff.v v4, (a0), v0.t
++
++	vlseg8e1024ff.v v4, (a0)
++	vlseg8e1024ff.v v4, 0(a0)
++	vlseg8e1024ff.v v4, (a0), v0.t
++
++	vl1r.v v3, (a0)
++	vl1r.v v3, 0(a0)
++	vs1r.v v3, (a1)
++	vs1r.v v3, 0(a1)
++
++	vamoaddei8.v v4, (a1), v8, v4
++	vamoaddei8.v x0, (a1), v8, v4
++	vamoaddei8.v v4, (a1), v8, v4, v0.t
++	vamoaddei8.v x0, (a1), v8, v4, v0.t
++	vamoswapei8.v v4, (a1), v8, v4
++	vamoswapei8.v x0, (a1), v8, v4
++	vamoswapei8.v v4, (a1), v8, v4, v0.t
++	vamoswapei8.v x0, (a1), v8, v4, v0.t
++
++	vamoxorei8.v v4, (a1), v8, v4
++	vamoxorei8.v x0, (a1), v8, v4
++	vamoxorei8.v v4, (a1), v8, v4, v0.t
++	vamoxorei8.v x0, (a1), v8, v4, v0.t
++	vamoandei8.v v4, (a1), v8, v4
++	vamoandei8.v x0, (a1), v8, v4
++	vamoandei8.v v4, (a1), v8, v4, v0.t
++	vamoandei8.v x0, (a1), v8, v4, v0.t
++	vamoorei8.v v4, (a1), v8, v4
++	vamoorei8.v x0, (a1), v8, v4
++	vamoorei8.v v4, (a1), v8, v4, v0.t
++	vamoorei8.v x0, (a1), v8, v4, v0.t
++
++	vamominei8.v v4, (a1), v8, v4
++	vamominei8.v x0, (a1), v8, v4
++	vamominei8.v v4, (a1), v8, v4, v0.t
++	vamominei8.v x0, (a1), v8, v4, v0.t
++	vamomaxei8.v v4, (a1), v8, v4
++	vamomaxei8.v x0, (a1), v8, v4
++	vamomaxei8.v v4, (a1), v8, v4, v0.t
++	vamomaxei8.v x0, (a1), v8, v4, v0.t
++	vamominuei8.v v4, (a1), v8, v4
++	vamominuei8.v x0, (a1), v8, v4
++	vamominuei8.v v4, (a1), v8, v4, v0.t
++	vamominuei8.v x0, (a1), v8, v4, v0.t
++	vamomaxuei8.v v4, (a1), v8, v4
++	vamomaxuei8.v x0, (a1), v8, v4
++	vamomaxuei8.v v4, (a1), v8, v4, v0.t
++	vamomaxuei8.v x0, (a1), v8, v4, v0.t
++
++	vamoaddei8.v v4, 0(a1), v8, v4
++	vamoaddei8.v x0, 0(a1), v8, v4
++	vamoaddei8.v v4, 0(a1), v8, v4, v0.t
++	vamoaddei8.v x0, 0(a1), v8, v4, v0.t
++	vamoswapei8.v v4, 0(a1), v8, v4
++	vamoswapei8.v x0, 0(a1), v8, v4
++	vamoswapei8.v v4, 0(a1), v8, v4, v0.t
++	vamoswapei8.v x0, 0(a1), v8, v4, v0.t
++
++	vamoxorei8.v v4, 0(a1), v8, v4
++	vamoxorei8.v x0, 0(a1), v8, v4
++	vamoxorei8.v v4, 0(a1), v8, v4, v0.t
++	vamoxorei8.v x0, 0(a1), v8, v4, v0.t
++	vamoandei8.v v4, 0(a1), v8, v4
++	vamoandei8.v x0, 0(a1), v8, v4
++	vamoandei8.v v4, 0(a1), v8, v4, v0.t
++	vamoandei8.v x0, 0(a1), v8, v4, v0.t
++	vamoorei8.v v4, 0(a1), v8, v4
++	vamoorei8.v x0, 0(a1), v8, v4
++	vamoorei8.v v4, 0(a1), v8, v4, v0.t
++	vamoorei8.v x0, 0(a1), v8, v4, v0.t
++
++	vamominei8.v v4, 0(a1), v8, v4
++	vamominei8.v x0, 0(a1), v8, v4
++	vamominei8.v v4, 0(a1), v8, v4, v0.t
++	vamominei8.v x0, 0(a1), v8, v4, v0.t
++	vamomaxei8.v v4, 0(a1), v8, v4
++	vamomaxei8.v x0, 0(a1), v8, v4
++	vamomaxei8.v v4, 0(a1), v8, v4, v0.t
++	vamomaxei8.v x0, 0(a1), v8, v4, v0.t
++	vamominuei8.v v4, 0(a1), v8, v4
++	vamominuei8.v x0, 0(a1), v8, v4
++	vamominuei8.v v4, 0(a1), v8, v4, v0.t
++	vamominuei8.v x0, 0(a1), v8, v4, v0.t
++	vamomaxuei8.v v4, 0(a1), v8, v4
++	vamomaxuei8.v x0, 0(a1), v8, v4
++	vamomaxuei8.v v4, 0(a1), v8, v4, v0.t
++	vamomaxuei8.v x0, 0(a1), v8, v4, v0.t
++
++	vamoaddei16.v v4, (a1), v8, v4
++	vamoaddei16.v x0, (a1), v8, v4
++	vamoaddei16.v v4, (a1), v8, v4, v0.t
++	vamoaddei16.v x0, (a1), v8, v4, v0.t
++	vamoswapei16.v v4, (a1), v8, v4
++	vamoswapei16.v x0, (a1), v8, v4
++	vamoswapei16.v v4, (a1), v8, v4, v0.t
++	vamoswapei16.v x0, (a1), v8, v4, v0.t
++
++	vamoxorei16.v v4, (a1), v8, v4
++	vamoxorei16.v x0, (a1), v8, v4
++	vamoxorei16.v v4, (a1), v8, v4, v0.t
++	vamoxorei16.v x0, (a1), v8, v4, v0.t
++	vamoandei16.v v4, (a1), v8, v4
++	vamoandei16.v x0, (a1), v8, v4
++	vamoandei16.v v4, (a1), v8, v4, v0.t
++	vamoandei16.v x0, (a1), v8, v4, v0.t
++	vamoorei16.v v4, (a1), v8, v4
++	vamoorei16.v x0, (a1), v8, v4
++	vamoorei16.v v4, (a1), v8, v4, v0.t
++	vamoorei16.v x0, (a1), v8, v4, v0.t
++
++	vamominei16.v v4, (a1), v8, v4
++	vamominei16.v x0, (a1), v8, v4
++	vamominei16.v v4, (a1), v8, v4, v0.t
++	vamominei16.v x0, (a1), v8, v4, v0.t
++	vamomaxei16.v v4, (a1), v8, v4
++	vamomaxei16.v x0, (a1), v8, v4
++	vamomaxei16.v v4, (a1), v8, v4, v0.t
++	vamomaxei16.v x0, (a1), v8, v4, v0.t
++	vamominuei16.v v4, (a1), v8, v4
++	vamominuei16.v x0, (a1), v8, v4
++	vamominuei16.v v4, (a1), v8, v4, v0.t
++	vamominuei16.v x0, (a1), v8, v4, v0.t
++	vamomaxuei16.v v4, (a1), v8, v4
++	vamomaxuei16.v x0, (a1), v8, v4
++	vamomaxuei16.v v4, (a1), v8, v4, v0.t
++	vamomaxuei16.v x0, (a1), v8, v4, v0.t
++
++	vamoaddei16.v v4, 0(a1), v8, v4
++	vamoaddei16.v x0, 0(a1), v8, v4
++	vamoaddei16.v v4, 0(a1), v8, v4, v0.t
++	vamoaddei16.v x0, 0(a1), v8, v4, v0.t
++	vamoswapei16.v v4, 0(a1), v8, v4
++	vamoswapei16.v x0, 0(a1), v8, v4
++	vamoswapei16.v v4, 0(a1), v8, v4, v0.t
++	vamoswapei16.v x0, 0(a1), v8, v4, v0.t
++
++	vamoxorei16.v v4, 0(a1), v8, v4
++	vamoxorei16.v x0, 0(a1), v8, v4
++	vamoxorei16.v v4, 0(a1), v8, v4, v0.t
++	vamoxorei16.v x0, 0(a1), v8, v4, v0.t
++	vamoandei16.v v4, 0(a1), v8, v4
++	vamoandei16.v x0, 0(a1), v8, v4
++	vamoandei16.v v4, 0(a1), v8, v4, v0.t
++	vamoandei16.v x0, 0(a1), v8, v4, v0.t
++	vamoorei16.v v4, 0(a1), v8, v4
++	vamoorei16.v x0, 0(a1), v8, v4
++	vamoorei16.v v4, 0(a1), v8, v4, v0.t
++	vamoorei16.v x0, 0(a1), v8, v4, v0.t
++
++	vamominei16.v v4, 0(a1), v8, v4
++	vamominei16.v x0, 0(a1), v8, v4
++	vamominei16.v v4, 0(a1), v8, v4, v0.t
++	vamominei16.v x0, 0(a1), v8, v4, v0.t
++	vamomaxei16.v v4, 0(a1), v8, v4
++	vamomaxei16.v x0, 0(a1), v8, v4
++	vamomaxei16.v v4, 0(a1), v8, v4, v0.t
++	vamomaxei16.v x0, 0(a1), v8, v4, v0.t
++	vamominuei16.v v4, 0(a1), v8, v4
++	vamominuei16.v x0, 0(a1), v8, v4
++	vamominuei16.v v4, 0(a1), v8, v4, v0.t
++	vamominuei16.v x0, 0(a1), v8, v4, v0.t
++	vamomaxuei16.v v4, 0(a1), v8, v4
++	vamomaxuei16.v x0, 0(a1), v8, v4
++	vamomaxuei16.v v4, 0(a1), v8, v4, v0.t
++	vamomaxuei16.v x0, 0(a1), v8, v4, v0.t
++
++	vamoaddei32.v v4, (a1), v8, v4
++	vamoaddei32.v x0, (a1), v8, v4
++	vamoaddei32.v v4, (a1), v8, v4, v0.t
++	vamoaddei32.v x0, (a1), v8, v4, v0.t
++	vamoswapei32.v v4, (a1), v8, v4
++	vamoswapei32.v x0, (a1), v8, v4
++	vamoswapei32.v v4, (a1), v8, v4, v0.t
++	vamoswapei32.v x0, (a1), v8, v4, v0.t
++
++	vamoxorei32.v v4, (a1), v8, v4
++	vamoxorei32.v x0, (a1), v8, v4
++	vamoxorei32.v v4, (a1), v8, v4, v0.t
++	vamoxorei32.v x0, (a1), v8, v4, v0.t
++	vamoandei32.v v4, (a1), v8, v4
++	vamoandei32.v x0, (a1), v8, v4
++	vamoandei32.v v4, (a1), v8, v4, v0.t
++	vamoandei32.v x0, (a1), v8, v4, v0.t
++	vamoorei32.v v4, (a1), v8, v4
++	vamoorei32.v x0, (a1), v8, v4
++	vamoorei32.v v4, (a1), v8, v4, v0.t
++	vamoorei32.v x0, (a1), v8, v4, v0.t
++
++	vamominei32.v v4, (a1), v8, v4
++	vamominei32.v x0, (a1), v8, v4
++	vamominei32.v v4, (a1), v8, v4, v0.t
++	vamominei32.v x0, (a1), v8, v4, v0.t
++	vamomaxei32.v v4, (a1), v8, v4
++	vamomaxei32.v x0, (a1), v8, v4
++	vamomaxei32.v v4, (a1), v8, v4, v0.t
++	vamomaxei32.v x0, (a1), v8, v4, v0.t
++	vamominuei32.v v4, (a1), v8, v4
++	vamominuei32.v x0, (a1), v8, v4
++	vamominuei32.v v4, (a1), v8, v4, v0.t
++	vamominuei32.v x0, (a1), v8, v4, v0.t
++	vamomaxuei32.v v4, (a1), v8, v4
++	vamomaxuei32.v x0, (a1), v8, v4
++	vamomaxuei32.v v4, (a1), v8, v4, v0.t
++	vamomaxuei32.v x0, (a1), v8, v4, v0.t
++
++	vamoaddei32.v v4, 0(a1), v8, v4
++	vamoaddei32.v x0, 0(a1), v8, v4
++	vamoaddei32.v v4, 0(a1), v8, v4, v0.t
++	vamoaddei32.v x0, 0(a1), v8, v4, v0.t
++	vamoswapei32.v v4, 0(a1), v8, v4
++	vamoswapei32.v x0, 0(a1), v8, v4
++	vamoswapei32.v v4, 0(a1), v8, v4, v0.t
++	vamoswapei32.v x0, 0(a1), v8, v4, v0.t
++
++	vamoxorei32.v v4, 0(a1), v8, v4
++	vamoxorei32.v x0, 0(a1), v8, v4
++	vamoxorei32.v v4, 0(a1), v8, v4, v0.t
++	vamoxorei32.v x0, 0(a1), v8, v4, v0.t
++	vamoandei32.v v4, 0(a1), v8, v4
++	vamoandei32.v x0, 0(a1), v8, v4
++	vamoandei32.v v4, 0(a1), v8, v4, v0.t
++	vamoandei32.v x0, 0(a1), v8, v4, v0.t
++	vamoorei32.v v4, 0(a1), v8, v4
++	vamoorei32.v x0, 0(a1), v8, v4
++	vamoorei32.v v4, 0(a1), v8, v4, v0.t
++	vamoorei32.v x0, 0(a1), v8, v4, v0.t
++
++	vamominei32.v v4, 0(a1), v8, v4
++	vamominei32.v x0, 0(a1), v8, v4
++	vamominei32.v v4, 0(a1), v8, v4, v0.t
++	vamominei32.v x0, 0(a1), v8, v4, v0.t
++	vamomaxei32.v v4, 0(a1), v8, v4
++	vamomaxei32.v x0, 0(a1), v8, v4
++	vamomaxei32.v v4, 0(a1), v8, v4, v0.t
++	vamomaxei32.v x0, 0(a1), v8, v4, v0.t
++	vamominuei32.v v4, 0(a1), v8, v4
++	vamominuei32.v x0, 0(a1), v8, v4
++	vamominuei32.v v4, 0(a1), v8, v4, v0.t
++	vamominuei32.v x0, 0(a1), v8, v4, v0.t
++	vamomaxuei32.v v4, 0(a1), v8, v4
++	vamomaxuei32.v x0, 0(a1), v8, v4
++	vamomaxuei32.v v4, 0(a1), v8, v4, v0.t
++	vamomaxuei32.v x0, 0(a1), v8, v4, v0.t
++
++	vamoaddei64.v v4, (a1), v8, v4
++	vamoaddei64.v x0, (a1), v8, v4
++	vamoaddei64.v v4, (a1), v8, v4, v0.t
++	vamoaddei64.v x0, (a1), v8, v4, v0.t
++	vamoswapei64.v v4, (a1), v8, v4
++	vamoswapei64.v x0, (a1), v8, v4
++	vamoswapei64.v v4, (a1), v8, v4, v0.t
++	vamoswapei64.v x0, (a1), v8, v4, v0.t
++
++	vamoxorei64.v v4, (a1), v8, v4
++	vamoxorei64.v x0, (a1), v8, v4
++	vamoxorei64.v v4, (a1), v8, v4, v0.t
++	vamoxorei64.v x0, (a1), v8, v4, v0.t
++	vamoandei64.v v4, (a1), v8, v4
++	vamoandei64.v x0, (a1), v8, v4
++	vamoandei64.v v4, (a1), v8, v4, v0.t
++	vamoandei64.v x0, (a1), v8, v4, v0.t
++	vamoorei64.v v4, (a1), v8, v4
++	vamoorei64.v x0, (a1), v8, v4
++	vamoorei64.v v4, (a1), v8, v4, v0.t
++	vamoorei64.v x0, (a1), v8, v4, v0.t
++
++	vamominei64.v v4, (a1), v8, v4
++	vamominei64.v x0, (a1), v8, v4
++	vamominei64.v v4, (a1), v8, v4, v0.t
++	vamominei64.v x0, (a1), v8, v4, v0.t
++	vamomaxei64.v v4, (a1), v8, v4
++	vamomaxei64.v x0, (a1), v8, v4
++	vamomaxei64.v v4, (a1), v8, v4, v0.t
++	vamomaxei64.v x0, (a1), v8, v4, v0.t
++	vamominuei64.v v4, (a1), v8, v4
++	vamominuei64.v x0, (a1), v8, v4
++	vamominuei64.v v4, (a1), v8, v4, v0.t
++	vamominuei64.v x0, (a1), v8, v4, v0.t
++	vamomaxuei64.v v4, (a1), v8, v4
++	vamomaxuei64.v x0, (a1), v8, v4
++	vamomaxuei64.v v4, (a1), v8, v4, v0.t
++	vamomaxuei64.v x0, (a1), v8, v4, v0.t
++
++	vamoaddei64.v v4, 0(a1), v8, v4
++	vamoaddei64.v x0, 0(a1), v8, v4
++	vamoaddei64.v v4, 0(a1), v8, v4, v0.t
++	vamoaddei64.v x0, 0(a1), v8, v4, v0.t
++	vamoswapei64.v v4, 0(a1), v8, v4
++	vamoswapei64.v x0, 0(a1), v8, v4
++	vamoswapei64.v v4, 0(a1), v8, v4, v0.t
++	vamoswapei64.v x0, 0(a1), v8, v4, v0.t
++
++	vamoxorei64.v v4, 0(a1), v8, v4
++	vamoxorei64.v x0, 0(a1), v8, v4
++	vamoxorei64.v v4, 0(a1), v8, v4, v0.t
++	vamoxorei64.v x0, 0(a1), v8, v4, v0.t
++	vamoandei64.v v4, 0(a1), v8, v4
++	vamoandei64.v x0, 0(a1), v8, v4
++	vamoandei64.v v4, 0(a1), v8, v4, v0.t
++	vamoandei64.v x0, 0(a1), v8, v4, v0.t
++	vamoorei64.v v4, 0(a1), v8, v4
++	vamoorei64.v x0, 0(a1), v8, v4
++	vamoorei64.v v4, 0(a1), v8, v4, v0.t
++	vamoorei64.v x0, 0(a1), v8, v4, v0.t
++
++	vamominei64.v v4, 0(a1), v8, v4
++	vamominei64.v x0, 0(a1), v8, v4
++	vamominei64.v v4, 0(a1), v8, v4, v0.t
++	vamominei64.v x0, 0(a1), v8, v4, v0.t
++	vamomaxei64.v v4, 0(a1), v8, v4
++	vamomaxei64.v x0, 0(a1), v8, v4
++	vamomaxei64.v v4, 0(a1), v8, v4, v0.t
++	vamomaxei64.v x0, 0(a1), v8, v4, v0.t
++	vamominuei64.v v4, 0(a1), v8, v4
++	vamominuei64.v x0, 0(a1), v8, v4
++	vamominuei64.v v4, 0(a1), v8, v4, v0.t
++	vamominuei64.v x0, 0(a1), v8, v4, v0.t
++	vamomaxuei64.v v4, 0(a1), v8, v4
++	vamomaxuei64.v x0, 0(a1), v8, v4
++	vamomaxuei64.v v4, 0(a1), v8, v4, v0.t
++	vamomaxuei64.v x0, 0(a1), v8, v4, v0.t
++
++	vadd.vv v4, v8, v12
++	vadd.vx v4, v8, a1
++	vadd.vi v4, v8, 15
++	vadd.vi v4, v8, -16
++	vadd.vv v4, v8, v12, v0.t
++	vadd.vx v4, v8, a1, v0.t
++	vadd.vi v4, v8, 15, v0.t
++	vadd.vi v4, v8, -16, v0.t
++	vsub.vv v4, v8, v12
++	vsub.vx v4, v8, a1
++	vrsub.vx v4, v8, a1
++	vrsub.vi v4, v8, 15
++	vrsub.vi v4, v8, -16
++	vsub.vv v4, v8, v12, v0.t
++	vsub.vx v4, v8, a1, v0.t
++	vrsub.vx v4, v8, a1, v0.t
++	vrsub.vi v4, v8, 15, v0.t
++	vrsub.vi v4, v8, -16, v0.t
++
++	# Aliases
++	vwcvt.x.x.v v4, v8
++	vwcvtu.x.x.v v4, v8
++	vwcvt.x.x.v v4, v8, v0.t
++	vwcvtu.x.x.v v4, v8, v0.t
++
++	vwaddu.vv v4, v8, v12
++	vwaddu.vx v4, v8, a1
++	vwaddu.vv v4, v8, v12, v0.t
++	vwaddu.vx v4, v8, a1, v0.t
++	vwsubu.vv v4, v8, v12
++	vwsubu.vx v4, v8, a1
++	vwsubu.vv v4, v8, v12, v0.t
++	vwsubu.vx v4, v8, a1, v0.t
++	vwadd.vv v4, v8, v12
++	vwadd.vx v4, v8, a1
++	vwadd.vv v4, v8, v12, v0.t
++	vwadd.vx v4, v8, a1, v0.t
++	vwsub.vv v4, v8, v12
++	vwsub.vx v4, v8, a1
++	vwsub.vv v4, v8, v12, v0.t
++	vwsub.vx v4, v8, a1, v0.t
++	vwaddu.wv v4, v8, v12
++	vwaddu.wx v4, v8, a1
++	vwaddu.wv v4, v8, v12, v0.t
++	vwaddu.wx v4, v8, a1, v0.t
++	vwsubu.wv v4, v8, v12
++	vwsubu.wx v4, v8, a1
++	vwsubu.wv v4, v8, v12, v0.t
++	vwsubu.wx v4, v8, a1, v0.t
++	vwadd.wv v4, v8, v12
++	vwadd.wx v4, v8, a1
++	vwadd.wv v4, v8, v12, v0.t
++	vwadd.wx v4, v8, a1, v0.t
++	vwsub.wv v4, v8, v12
++	vwsub.wx v4, v8, a1
++	vwsub.wv v4, v8, v12, v0.t
++	vwsub.wx v4, v8, a1, v0.t
++
++	vzext.vf2 v4, v8
++	vzext.vf2 v4, v8, v0.t
++	vsext.vf2 v4, v8
++	vsext.vf2 v4, v8, v0.t
++	vzext.vf4 v4, v8
++	vzext.vf4 v4, v8, v0.t
++	vsext.vf4 v4, v8
++	vsext.vf4 v4, v8, v0.t
++	vzext.vf8 v4, v8
++	vzext.vf8 v4, v8, v0.t
++	vsext.vf8 v4, v8
++	vsext.vf8 v4, v8, v0.t
++
++	vadc.vvm v4, v8, v12, v0
++	vadc.vxm v4, v8, a1, v0
++	vadc.vim v4, v8, 15, v0
++	vadc.vim v4, v8, -16, v0
++	vmadc.vvm v4, v8, v12, v0
++	vmadc.vxm v4, v8, a1, v0
++	vmadc.vim v4, v8, 15, v0
++	vmadc.vim v4, v8, -16, v0
++	vmadc.vv v4, v8, v12
++	vmadc.vx v4, v8, a1
++	vmadc.vi v4, v8, 15
++	vmadc.vi v4, v8, -16
++	vsbc.vvm v4, v8, v12, v0
++	vsbc.vxm v4, v8, a1, v0
++	vmsbc.vvm v4, v8, v12, v0
++	vmsbc.vxm v4, v8, a1, v0
++	vmsbc.vv v4, v8, v12
++	vmsbc.vx v4, v8, a1
++
++	# Aliases
++	vnot.v v4, v8
++	vnot.v v4, v8, v0.t
++
++	vand.vv v4, v8, v12
++	vand.vx v4, v8, a1
++	vand.vi v4, v8, 15
++	vand.vi v4, v8, -16
++	vand.vv v4, v8, v12, v0.t
++	vand.vx v4, v8, a1, v0.t
++	vand.vi v4, v8, 15, v0.t
++	vand.vi v4, v8, -16, v0.t
++	vor.vv v4, v8, v12
++	vor.vx v4, v8, a1
++	vor.vi v4, v8, 15
++	vor.vi v4, v8, -16
++	vor.vv v4, v8, v12, v0.t
++	vor.vx v4, v8, a1, v0.t
++	vor.vi v4, v8, 15, v0.t
++	vor.vi v4, v8, -16, v0.t
++	vxor.vv v4, v8, v12
++	vxor.vx v4, v8, a1
++	vxor.vi v4, v8, 15
++	vxor.vi v4, v8, -16
++	vxor.vv v4, v8, v12, v0.t
++	vxor.vx v4, v8, a1, v0.t
++	vxor.vi v4, v8, 15, v0.t
++	vxor.vi v4, v8, -16, v0.t
++
++	vsll.vv v4, v8, v12
++	vsll.vx v4, v8, a1
++	vsll.vi v4, v8, 1
++	vsll.vi v4, v8, 31
++	vsll.vv v4, v8, v12, v0.t
++	vsll.vx v4, v8, a1, v0.t
++	vsll.vi v4, v8, 1, v0.t
++	vsll.vi v4, v8, 31, v0.t
++	vsrl.vv v4, v8, v12
++	vsrl.vx v4, v8, a1
++	vsrl.vi v4, v8, 1
++	vsrl.vi v4, v8, 31
++	vsrl.vv v4, v8, v12, v0.t
++	vsrl.vx v4, v8, a1, v0.t
++	vsrl.vi v4, v8, 1, v0.t
++	vsrl.vi v4, v8, 31, v0.t
++	vsra.vv v4, v8, v12
++	vsra.vx v4, v8, a1
++	vsra.vi v4, v8, 1
++	vsra.vi v4, v8, 31
++	vsra.vv v4, v8, v12, v0.t
++	vsra.vx v4, v8, a1, v0.t
++	vsra.vi v4, v8, 1, v0.t
++	vsra.vi v4, v8, 31, v0.t
++
++	vnsrl.wv v4, v8, v12
++	vnsrl.wx v4, v8, a1
++	vnsrl.wi v4, v8, 1
++	vnsrl.wi v4, v8, 31
++	vnsrl.wv v4, v8, v12, v0.t
++	vnsrl.wx v4, v8, a1, v0.t
++	vnsrl.wi v4, v8, 1, v0.t
++	vnsrl.wi v4, v8, 31, v0.t
++	vnsra.wv v4, v8, v12
++	vnsra.wx v4, v8, a1
++	vnsra.wi v4, v8, 1
++	vnsra.wi v4, v8, 31
++	vnsra.wv v4, v8, v12, v0.t
++	vnsra.wx v4, v8, a1, v0.t
++	vnsra.wi v4, v8, 1, v0.t
++	vnsra.wi v4, v8, 31, v0.t
++
++	# Aliases
++	vmsgt.vv v4, v8, v12
++	vmsgtu.vv v4, v8, v12
++	vmsge.vv v4, v8, v12
++	vmsgeu.vv v4, v8, v12
++	vmsgt.vv v4, v8, v12, v0.t
++	vmsgtu.vv v4, v8, v12, v0.t
++	vmsge.vv v4, v8, v12, v0.t
++	vmsgeu.vv v4, v8, v12, v0.t
++	vmslt.vi v4, v8, 16
++	vmslt.vi v4, v8, -15
++	vmsltu.vi v4, v8, 16
++	vmsltu.vi v4, v8, -15
++	vmsge.vi v4, v8, 16
++	vmsge.vi v4, v8, -15
++	vmsgeu.vi v4, v8, 16
++	vmsgeu.vi v4, v8, -15
++	vmslt.vi v4, v8, 16, v0.t
++	vmslt.vi v4, v8, -15, v0.t
++	vmsltu.vi v4, v8, 16, v0.t
++	vmsltu.vi v4, v8, -15, v0.t
++	vmsge.vi v4, v8, 16, v0.t
++	vmsge.vi v4, v8, -15, v0.t
++	vmsgeu.vi v4, v8, 16, v0.t
++	vmsgeu.vi v4, v8, -15, v0.t
++
++	vmseq.vv v4, v8, v12
++	vmseq.vx v4, v8, a1
++	vmseq.vi v4, v8, 15
++	vmseq.vi v4, v8, -16
++	vmseq.vv v4, v8, v12, v0.t
++	vmseq.vx v4, v8, a1, v0.t
++	vmseq.vi v4, v8, 15, v0.t
++	vmseq.vi v4, v8, -16, v0.t
++	vmsne.vv v4, v8, v12
++	vmsne.vx v4, v8, a1
++	vmsne.vi v4, v8, 15
++	vmsne.vi v4, v8, -16
++	vmsne.vv v4, v8, v12, v0.t
++	vmsne.vx v4, v8, a1, v0.t
++	vmsne.vi v4, v8, 15, v0.t
++	vmsne.vi v4, v8, -16, v0.t
++	vmsltu.vv v4, v8, v12
++	vmsltu.vx v4, v8, a1
++	vmsltu.vv v4, v8, v12, v0.t
++	vmsltu.vx v4, v8, a1, v0.t
++	vmslt.vv v4, v8, v12
++	vmslt.vx v4, v8, a1
++	vmslt.vv v4, v8, v12, v0.t
++	vmslt.vx v4, v8, a1, v0.t
++	vmsleu.vv v4, v8, v12
++	vmsleu.vx v4, v8, a1
++	vmsleu.vi v4, v8, 15
++	vmsleu.vi v4, v8, -16
++	vmsleu.vv v4, v8, v12, v0.t
++	vmsleu.vx v4, v8, a1, v0.t
++	vmsleu.vi v4, v8, 15, v0.t
++	vmsleu.vi v4, v8, -16, v0.t
++	vmsle.vv v4, v8, v12
++	vmsle.vx v4, v8, a1
++	vmsle.vi v4, v8, 15
++	vmsle.vi v4, v8, -16
++	vmsle.vv v4, v8, v12, v0.t
++	vmsle.vx v4, v8, a1, v0.t
++	vmsle.vi v4, v8, 15, v0.t
++	vmsle.vi v4, v8, -16, v0.t
++	vmsgtu.vx v4, v8, a1
++	vmsgtu.vi v4, v8, 15
++	vmsgtu.vi v4, v8, -16
++	vmsgtu.vx v4, v8, a1, v0.t
++	vmsgtu.vi v4, v8, 15, v0.t
++	vmsgtu.vi v4, v8, -16, v0.t
++	vmsgt.vx v4, v8, a1
++	vmsgt.vi v4, v8, 15
++	vmsgt.vi v4, v8, -16
++	vmsgt.vx v4, v8, a1, v0.t
++	vmsgt.vi v4, v8, 15, v0.t
++	vmsgt.vi v4, v8, -16, v0.t
++
++	vminu.vv v4, v8, v12
++	vminu.vx v4, v8, a1
++	vminu.vv v4, v8, v12, v0.t
++	vminu.vx v4, v8, a1, v0.t
++	vmin.vv v4, v8, v12
++	vmin.vx v4, v8, a1
++	vmin.vv v4, v8, v12, v0.t
++	vmin.vx v4, v8, a1, v0.t
++	vmaxu.vv v4, v8, v12
++	vmaxu.vx v4, v8, a1
++	vmaxu.vv v4, v8, v12, v0.t
++	vmaxu.vx v4, v8, a1, v0.t
++	vmax.vv v4, v8, v12
++	vmax.vx v4, v8, a1
++	vmax.vv v4, v8, v12, v0.t
++	vmax.vx v4, v8, a1, v0.t
++
++	vmul.vv v4, v8, v12
++	vmul.vx v4, v8, a1
++	vmul.vv v4, v8, v12, v0.t
++	vmul.vx v4, v8, a1, v0.t
++	vmulh.vv v4, v8, v12
++	vmulh.vx v4, v8, a1
++	vmulh.vv v4, v8, v12, v0.t
++	vmulh.vx v4, v8, a1, v0.t
++	vmulhu.vv v4, v8, v12
++	vmulhu.vx v4, v8, a1
++	vmulhu.vv v4, v8, v12, v0.t
++	vmulhu.vx v4, v8, a1, v0.t
++	vmulhsu.vv v4, v8, v12
++	vmulhsu.vx v4, v8, a1
++	vmulhsu.vv v4, v8, v12, v0.t
++	vmulhsu.vx v4, v8, a1, v0.t
++
++	vwmul.vv v4, v8, v12
++	vwmul.vx v4, v8, a1
++	vwmul.vv v4, v8, v12, v0.t
++	vwmul.vx v4, v8, a1, v0.t
++	vwmulu.vv v4, v8, v12
++	vwmulu.vx v4, v8, a1
++	vwmulu.vv v4, v8, v12, v0.t
++	vwmulu.vx v4, v8, a1, v0.t
++	vwmulsu.vv v4, v8, v12
++	vwmulsu.vx v4, v8, a1
++	vwmulsu.vv v4, v8, v12, v0.t
++	vwmulsu.vx v4, v8, a1, v0.t
++
++	vmacc.vv v4, v12, v8
++	vmacc.vx v4, a1, v8
++	vmacc.vv v4, v12, v8, v0.t
++	vmacc.vx v4, a1, v8, v0.t
++	vnmsac.vv v4, v12, v8
++	vnmsac.vx v4, a1, v8
++	vnmsac.vv v4, v12, v8, v0.t
++	vnmsac.vx v4, a1, v8, v0.t
++	vmadd.vv v4, v12, v8
++	vmadd.vx v4, a1, v8
++	vmadd.vv v4, v12, v8, v0.t
++	vmadd.vx v4, a1, v8, v0.t
++	vnmsub.vv v4, v12, v8
++	vnmsub.vx v4, a1, v8
++	vnmsub.vv v4, v12, v8, v0.t
++	vnmsub.vx v4, a1, v8, v0.t
++
++	vwmaccu.vv v4, v12, v8
++	vwmaccu.vx v4, a1, v8
++	vwmaccu.vv v4, v12, v8, v0.t
++	vwmaccu.vx v4, a1, v8, v0.t
++	vwmacc.vv v4, v12, v8
++	vwmacc.vx v4, a1, v8
++	vwmacc.vv v4, v12, v8, v0.t
++	vwmacc.vx v4, a1, v8, v0.t
++	vwmaccsu.vv v4, v12, v8
++	vwmaccsu.vx v4, a1, v8
++	vwmaccsu.vv v4, v12, v8, v0.t
++	vwmaccsu.vx v4, a1, v8, v0.t
++	vwmaccus.vx v4, a1, v8
++	vwmaccus.vx v4, a1, v8, v0.t
++
++	vqmaccu.vv v4, v12, v8
++	vqmaccu.vx v4, a1, v8
++	vqmaccu.vv v4, v12, v8, v0.t
++	vqmaccu.vx v4, a1, v8, v0.t
++	vqmacc.vv v4, v12, v8
++	vqmacc.vx v4, a1, v8
++	vqmacc.vv v4, v12, v8, v0.t
++	vqmacc.vx v4, a1, v8, v0.t
++	vqmaccsu.vv v4, v12, v8
++	vqmaccsu.vx v4, a1, v8
++	vqmaccsu.vv v4, v12, v8, v0.t
++	vqmaccsu.vx v4, a1, v8, v0.t
++	vqmaccus.vx v4, a1, v8
++	vqmaccus.vx v4, a1, v8, v0.t
++
++	vdivu.vv v4, v8, v12
++	vdivu.vx v4, v8, a1
++	vdivu.vv v4, v8, v12, v0.t
++	vdivu.vx v4, v8, a1, v0.t
++	vdiv.vv v4, v8, v12
++	vdiv.vx v4, v8, a1
++	vdiv.vv v4, v8, v12, v0.t
++	vdiv.vx v4, v8, a1, v0.t
++	vremu.vv v4, v8, v12
++	vremu.vx v4, v8, a1
++	vremu.vv v4, v8, v12, v0.t
++	vremu.vx v4, v8, a1, v0.t
++	vrem.vv v4, v8, v12
++	vrem.vx v4, v8, a1
++	vrem.vv v4, v8, v12, v0.t
++	vrem.vx v4, v8, a1, v0.t
++
++	vmerge.vvm v4, v8, v12, v0
++	vmerge.vxm v4, v8, a1, v0
++	vmerge.vim v4, v8, 15, v0
++	vmerge.vim v4, v8, -16, v0
++
++	vmv.v.v v8, v12
++	vmv.v.x v8, a1
++	vmv.v.i v8, 15
++	vmv.v.i v8, -16
++
++	vsaddu.vv v4, v8, v12
++	vsaddu.vx v4, v8, a1
++	vsaddu.vi v4, v8, 15
++	vsaddu.vi v4, v8, -16
++	vsaddu.vv v4, v8, v12, v0.t
++	vsaddu.vx v4, v8, a1, v0.t
++	vsaddu.vi v4, v8, 15, v0.t
++	vsaddu.vi v4, v8, -16, v0.t
++	vsadd.vv v4, v8, v12
++	vsadd.vx v4, v8, a1
++	vsadd.vi v4, v8, 15
++	vsadd.vi v4, v8, -16
++	vsadd.vv v4, v8, v12, v0.t
++	vsadd.vx v4, v8, a1, v0.t
++	vsadd.vi v4, v8, 15, v0.t
++	vsadd.vi v4, v8, -16, v0.t
++	vssubu.vv v4, v8, v12
++	vssubu.vx v4, v8, a1
++	vssubu.vv v4, v8, v12, v0.t
++	vssubu.vx v4, v8, a1, v0.t
++	vssub.vv v4, v8, v12
++	vssub.vx v4, v8, a1
++	vssub.vv v4, v8, v12, v0.t
++	vssub.vx v4, v8, a1, v0.t
++
++	vaaddu.vv v4, v8, v12
++	vaaddu.vx v4, v8, a1
++	vaaddu.vv v4, v8, v12, v0.t
++	vaaddu.vx v4, v8, a1, v0.t
++	vaadd.vv v4, v8, v12
++	vaadd.vx v4, v8, a1
++	vaadd.vv v4, v8, v12, v0.t
++	vaadd.vx v4, v8, a1, v0.t
++	vasubu.vv v4, v8, v12
++	vasubu.vx v4, v8, a1
++	vasubu.vv v4, v8, v12, v0.t
++	vasubu.vx v4, v8, a1, v0.t
++	vasub.vv v4, v8, v12
++	vasub.vx v4, v8, a1
++	vasub.vv v4, v8, v12, v0.t
++	vasub.vx v4, v8, a1, v0.t
++
++	vsmul.vv v4, v8, v12
++	vsmul.vx v4, v8, a1
++	vsmul.vv v4, v8, v12, v0.t
++	vsmul.vx v4, v8, a1, v0.t
++
++	vssrl.vv v4, v8, v12
++	vssrl.vx v4, v8, a1
++	vssrl.vi v4, v8, 1
++	vssrl.vi v4, v8, 31
++	vssrl.vv v4, v8, v12, v0.t
++	vssrl.vx v4, v8, a1, v0.t
++	vssrl.vi v4, v8, 1, v0.t
++	vssrl.vi v4, v8, 31, v0.t
++	vssra.vv v4, v8, v12
++	vssra.vx v4, v8, a1
++	vssra.vi v4, v8, 1
++	vssra.vi v4, v8, 31
++	vssra.vv v4, v8, v12, v0.t
++	vssra.vx v4, v8, a1, v0.t
++	vssra.vi v4, v8, 1, v0.t
++	vssra.vi v4, v8, 31, v0.t
++
++	vnclipu.wv v4, v8, v12
++	vnclipu.wx v4, v8, a1
++	vnclipu.wi v4, v8, 1
++	vnclipu.wi v4, v8, 31
++	vnclipu.wv v4, v8, v12, v0.t
++	vnclipu.wx v4, v8, a1, v0.t
++	vnclipu.wi v4, v8, 1, v0.t
++	vnclipu.wi v4, v8, 31, v0.t
++	vnclip.wv v4, v8, v12
++	vnclip.wx v4, v8, a1
++	vnclip.wi v4, v8, 1
++	vnclip.wi v4, v8, 31
++	vnclip.wv v4, v8, v12, v0.t
++	vnclip.wx v4, v8, a1, v0.t
++	vnclip.wi v4, v8, 1, v0.t
++	vnclip.wi v4, v8, 31, v0.t
++
++	vfadd.vv v4, v8, v12
++	vfadd.vf v4, v8, fa2
++	vfadd.vv v4, v8, v12, v0.t
++	vfadd.vf v4, v8, fa2, v0.t
++	vfsub.vv v4, v8, v12
++	vfsub.vf v4, v8, fa2
++	vfsub.vv v4, v8, v12, v0.t
++	vfsub.vf v4, v8, fa2, v0.t
++	vfrsub.vf v4, v8, fa2
++	vfrsub.vf v4, v8, fa2, v0.t
++
++	vfwadd.vv v4, v8, v12
++	vfwadd.vf v4, v8, fa2
++	vfwadd.vv v4, v8, v12, v0.t
++	vfwadd.vf v4, v8, fa2, v0.t
++	vfwsub.vv v4, v8, v12
++	vfwsub.vf v4, v8, fa2
++	vfwsub.vv v4, v8, v12, v0.t
++	vfwsub.vf v4, v8, fa2, v0.t
++	vfwadd.wv v4, v8, v12
++	vfwadd.wf v4, v8, fa2
++	vfwadd.wv v4, v8, v12, v0.t
++	vfwadd.wf v4, v8, fa2, v0.t
++	vfwsub.wv v4, v8, v12
++	vfwsub.wf v4, v8, fa2
++	vfwsub.wv v4, v8, v12, v0.t
++	vfwsub.wf v4, v8, fa2, v0.t
++
++	vfmul.vv v4, v8, v12
++	vfmul.vf v4, v8, fa2
++	vfmul.vv v4, v8, v12, v0.t
++	vfmul.vf v4, v8, fa2, v0.t
++	vfdiv.vv v4, v8, v12
++	vfdiv.vf v4, v8, fa2
++	vfdiv.vv v4, v8, v12, v0.t
++	vfdiv.vf v4, v8, fa2, v0.t
++	vfrdiv.vf v4, v8, fa2
++	vfrdiv.vf v4, v8, fa2, v0.t
++
++	vfwmul.vv v4, v8, v12
++	vfwmul.vf v4, v8, fa2
++	vfwmul.vv v4, v8, v12, v0.t
++	vfwmul.vf v4, v8, fa2, v0.t
++
++	vfmadd.vv v4, v12, v8
++	vfmadd.vf v4, fa2, v8
++	vfnmadd.vv v4, v12, v8
++	vfnmadd.vf v4, fa2, v8
++	vfmsub.vv v4, v12, v8
++	vfmsub.vf v4, fa2, v8
++	vfnmsub.vv v4, v12, v8
++	vfnmsub.vf v4, fa2, v8
++	vfmadd.vv v4, v12, v8, v0.t
++	vfmadd.vf v4, fa2, v8, v0.t
++	vfnmadd.vv v4, v12, v8, v0.t
++	vfnmadd.vf v4, fa2, v8, v0.t
++	vfmsub.vv v4, v12, v8, v0.t
++	vfmsub.vf v4, fa2, v8, v0.t
++	vfnmsub.vv v4, v12, v8, v0.t
++	vfnmsub.vf v4, fa2, v8, v0.t
++	vfmacc.vv v4, v12, v8
++	vfmacc.vf v4, fa2, v8
++	vfnmacc.vv v4, v12, v8
++	vfnmacc.vf v4, fa2, v8
++	vfmsac.vv v4, v12, v8
++	vfmsac.vf v4, fa2, v8
++	vfnmsac.vv v4, v12, v8
++	vfnmsac.vf v4, fa2, v8
++	vfmacc.vv v4, v12, v8, v0.t
++	vfmacc.vf v4, fa2, v8, v0.t
++	vfnmacc.vv v4, v12, v8, v0.t
++	vfnmacc.vf v4, fa2, v8, v0.t
++	vfmsac.vv v4, v12, v8, v0.t
++	vfmsac.vf v4, fa2, v8, v0.t
++	vfnmsac.vv v4, v12, v8, v0.t
++	vfnmsac.vf v4, fa2, v8, v0.t
++
++	vfwmacc.vv v4, v12, v8
++	vfwmacc.vf v4, fa2, v8
++	vfwnmacc.vv v4, v12, v8
++	vfwnmacc.vf v4, fa2, v8
++	vfwmsac.vv v4, v12, v8
++	vfwmsac.vf v4, fa2, v8
++	vfwnmsac.vv v4, v12, v8
++	vfwnmsac.vf v4, fa2, v8
++	vfwmacc.vv v4, v12, v8, v0.t
++	vfwmacc.vf v4, fa2, v8, v0.t
++	vfwnmacc.vv v4, v12, v8, v0.t
++	vfwnmacc.vf v4, fa2, v8, v0.t
++	vfwmsac.vv v4, v12, v8, v0.t
++	vfwmsac.vf v4, fa2, v8, v0.t
++	vfwnmsac.vv v4, v12, v8, v0.t
++	vfwnmsac.vf v4, fa2, v8, v0.t
++
++	vfsqrt.v v4, v8
++	vfsqrt.v v4, v8, v0.t
++
++	vfmin.vv v4, v8, v12
++	vfmin.vf v4, v8, fa2
++	vfmax.vv v4, v8, v12
++	vfmax.vf v4, v8, fa2
++	vfmin.vv v4, v8, v12, v0.t
++	vfmin.vf v4, v8, fa2, v0.t
++	vfmax.vv v4, v8, v12, v0.t
++	vfmax.vf v4, v8, fa2, v0.t
++
++	vfsgnj.vv v4, v8, v12
++	vfsgnj.vf v4, v8, fa2
++	vfsgnjn.vv v4, v8, v12
++	vfsgnjn.vf v4, v8, fa2
++	vfsgnjx.vv v4, v8, v12
++	vfsgnjx.vf v4, v8, fa2
++	vfsgnj.vv v4, v8, v12, v0.t
++	vfsgnj.vf v4, v8, fa2, v0.t
++	vfsgnjn.vv v4, v8, v12, v0.t
++	vfsgnjn.vf v4, v8, fa2, v0.t
++	vfsgnjx.vv v4, v8, v12, v0.t
++	vfsgnjx.vf v4, v8, fa2, v0.t
++
++	# Aliases
++	vmfgt.vv v4, v8, v12
++	vmfge.vv v4, v8, v12
++	vmfgt.vv v4, v8, v12, v0.t
++	vmfge.vv v4, v8, v12, v0.t
++
++	vmfeq.vv v4, v8, v12
++	vmfeq.vf v4, v8, fa2
++	vmfne.vv v4, v8, v12
++	vmfne.vf v4, v8, fa2
++	vmflt.vv v4, v8, v12
++	vmflt.vf v4, v8, fa2
++	vmfle.vv v4, v8, v12
++	vmfle.vf v4, v8, fa2
++	vmfgt.vf v4, v8, fa2
++	vmfge.vf v4, v8, fa2
++	vmfeq.vv v4, v8, v12, v0.t
++	vmfeq.vf v4, v8, fa2, v0.t
++	vmfne.vv v4, v8, v12, v0.t
++	vmfne.vf v4, v8, fa2, v0.t
++	vmflt.vv v4, v8, v12, v0.t
++	vmflt.vf v4, v8, fa2, v0.t
++	vmfle.vv v4, v8, v12, v0.t
++	vmfle.vf v4, v8, fa2, v0.t
++	vmfgt.vf v4, v8, fa2, v0.t
++	vmfge.vf v4, v8, fa2, v0.t
++
++	vfclass.v v4, v8
++	vfclass.v v4, v8, v0.t
++
++	vfmerge.vfm v4, v8, fa2, v0
++	vfmv.v.f v4, fa1
++
++	vfcvt.xu.f.v v4, v8
++	vfcvt.x.f.v v4, v8
++	vfcvt.rtz.xu.f.v v4, v8
++	vfcvt.rtz.x.f.v v4, v8
++	vfcvt.f.xu.v v4, v8
++	vfcvt.f.x.v v4, v8
++	vfcvt.xu.f.v v4, v8, v0.t
++	vfcvt.x.f.v v4, v8, v0.t
++	vfcvt.rtz.xu.f.v v4, v8, v0.t
++	vfcvt.rtz.x.f.v v4, v8, v0.t
++	vfcvt.f.xu.v v4, v8, v0.t
++	vfcvt.f.x.v v4, v8, v0.t
++
++	vfwcvt.xu.f.v v4, v8
++	vfwcvt.x.f.v v4, v8
++	vfwcvt.rtz.xu.f.v v4, v8
++	vfwcvt.rtz.x.f.v v4, v8
++	vfwcvt.f.xu.v v4, v8
++	vfwcvt.f.x.v v4, v8
++	vfwcvt.f.f.v v4, v8
++	vfwcvt.xu.f.v v4, v8, v0.t
++	vfwcvt.x.f.v v4, v8, v0.t
++	vfwcvt.rtz.xu.f.v v4, v8, v0.t
++	vfwcvt.rtz.x.f.v v4, v8, v0.t
++	vfwcvt.f.xu.v v4, v8, v0.t
++	vfwcvt.f.x.v v4, v8, v0.t
++	vfwcvt.f.f.v v4, v8, v0.t
++
++	vfncvt.xu.f.w v4, v8
++	vfncvt.x.f.w v4, v8
++	vfncvt.rtz.xu.f.w v4, v8
++	vfncvt.rtz.x.f.w v4, v8
++	vfncvt.f.xu.w v4, v8
++	vfncvt.f.x.w v4, v8
++	vfncvt.f.f.w v4, v8
++	vfncvt.rod.f.f.w v4, v8
++	vfncvt.xu.f.w v4, v8, v0.t
++	vfncvt.x.f.w v4, v8, v0.t
++	vfncvt.rtz.xu.f.w v4, v8, v0.t
++	vfncvt.rtz.x.f.w v4, v8, v0.t
++	vfncvt.f.xu.w v4, v8, v0.t
++	vfncvt.f.x.w v4, v8, v0.t
++	vfncvt.f.f.w v4, v8, v0.t
++	vfncvt.rod.f.f.w v4, v8, v0.t
++
++	vredsum.vs v4, v8, v12
++	vredmaxu.vs v4, v8, v8
++	vredmax.vs v4, v8, v8
++	vredminu.vs v4, v8, v8
++	vredmin.vs v4, v8, v8
++	vredand.vs v4, v8, v12
++	vredor.vs v4, v8, v12
++	vredxor.vs v4, v8, v12
++	vredsum.vs v4, v8, v12, v0.t
++	vredmaxu.vs v4, v8, v8, v0.t
++	vredmax.vs v4, v8, v8, v0.t
++	vredminu.vs v4, v8, v8, v0.t
++	vredmin.vs v4, v8, v8, v0.t
++	vredand.vs v4, v8, v12, v0.t
++	vredor.vs v4, v8, v12, v0.t
++	vredxor.vs v4, v8, v12, v0.t
++
++	vwredsumu.vs v4, v8, v12
++	vwredsum.vs v4, v8, v12
++	vwredsumu.vs v4, v8, v12, v0.t
++	vwredsum.vs v4, v8, v12, v0.t
++
++	vfredosum.vs v4, v8, v12
++	vfredsum.vs v4, v8, v12
++	vfredmax.vs v4, v8, v12
++	vfredmin.vs v4, v8, v12
++	vfredosum.vs v4, v8, v12, v0.t
++	vfredsum.vs v4, v8, v12, v0.t
++	vfredmax.vs v4, v8, v12, v0.t
++	vfredmin.vs v4, v8, v12, v0.t
++
++	vfwredosum.vs v4, v8, v12
++	vfwredsum.vs v4, v8, v12
++	vfwredosum.vs v4, v8, v12, v0.t
++	vfwredsum.vs v4, v8, v12, v0.t
++
++	# Aliases
++	vmcpy.m v4, v8
++	vmmv.m v4, v8
++	vmclr.m v4
++	vmset.m v4
++	vmnot.m v4, v8
++
++	vmand.mm v4, v8, v12
++	vmnand.mm v4, v8, v12
++	vmandnot.mm v4, v8, v12
++	vmxor.mm v4, v8, v12
++	vmor.mm v4, v8, v12
++	vmnor.mm v4, v8, v12
++	vmornot.mm v4, v8, v12
++	vmxnor.mm v4, v8, v12
++
++	vpopc.m a0, v12
++	vfirst.m a0, v12
++	vmsbf.m v4, v8
++	vmsif.m v4, v8
++	vmsof.m v4, v8
++	viota.m v4, v8
++	vid.v v4
++	vpopc.m a0, v12, v0.t
++	vfirst.m a0, v12, v0.t
++	vmsbf.m v4, v8, v0.t
++	vmsif.m v4, v8, v0.t
++	vmsof.m v4, v8, v0.t
++	viota.m v4, v8, v0.t
++	vid.v v4, v0.t
++
++	vmv.x.s a0, v12
++	vmv.s.x v4, a0
++
++	vfmv.f.s fa0, v8
++	vfmv.s.f v4, fa1
++
++	vslideup.vx v4, v8, a1
++	vslideup.vi v4, v8, 0
++	vslideup.vi v4, v8, 31
++	vslidedown.vx v4, v8, a1
++	vslidedown.vi v4, v8, 0
++	vslidedown.vi v4, v8, 31
++	vslideup.vx v4, v8, a1, v0.t
++	vslideup.vi v4, v8, 0, v0.t
++	vslideup.vi v4, v8, 31, v0.t
++	vslidedown.vx v4, v8, a1, v0.t
++	vslidedown.vi v4, v8, 0, v0.t
++	vslidedown.vi v4, v8, 31, v0.t
++
++	vslide1up.vx v4, v8, a1
++	vslide1down.vx v4, v8, a1
++	vslide1up.vx v4, v8, a1, v0.t
++	vslide1down.vx v4, v8, a1, v0.t
++
++	vfslide1up.vf v4, v8, fa1
++	vfslide1down.vf v4, v8, fa1
++	vfslide1up.vf v4, v8, fa1, v0.t
++	vfslide1down.vf v4, v8, fa1, v0.t
++
++	vrgather.vv v4, v8, v12
++	vrgather.vx v4, v8, a1
++	vrgather.vi v4, v8, 0
++	vrgather.vi v4, v8, 31
++	vrgather.vv v4, v8, v12, v0.t
++	vrgather.vx v4, v8, a1, v0.t
++	vrgather.vi v4, v8, 0, v0.t
++	vrgather.vi v4, v8, 31, v0.t
++
++	vcompress.vm v4, v8, v12
++
++	vmv1r.v v1, v2
++	vmv2r.v v2, v4
++	vmv4r.v v4, v8
++	vmv8r.v v0, v8
++
++	vdot.vv v4, v8, v12
++	vdotu.vv v4, v8, v12
++	vfdot.vv v4, v8, v12
++	vdot.vv v4, v8, v12, v0.t
++	vdotu.vv v4, v8, v12, v0.t
++	vfdot.vv v4, v8, v12, v0.t
+diff --git a/include/opcode/riscv-opc.h b/include/opcode/riscv-opc.h
+index 158de32485..6ec4c2a33a 100644
+--- a/include/opcode/riscv-opc.h
++++ b/include/opcode/riscv-opc.h
+@@ -547,6 +547,2130 @@
+ #define MASK_C_LDSP  0xe003
+ #define MATCH_C_SDSP 0xe002
+ #define MASK_C_SDSP  0xe003
++
++/* RVV */
++/* Version 1.0-draft-20200516.  */
++
++#define MATCH_VSETVL  0x80007057
++#define MASK_VSETVL   0xfe00707f
++#define MATCH_VSETVLI 0x00007057
++#define MASK_VSETVLI  0x8000707f
++
++/* Temporary Load/store encoding info
++MOP load
++00 unit-stride	VLE<EEW>, VLE<EEW>FF, VL<nf>RV (nf = 1)
++01 reserved
++10 strided	VLSE<EEW>
++11 indexed	VLXEI<EEW>
++
++MOP store
++00 unit-stride		VSE<EEW>, VS<nf>RV (nf = 1)
++01 indexed-unordered	VSUXEI<EEW>
++10 strided		VSSE<EEW>
++11 indexed-ordered	VSXEI<EEW>
++
++VM 0 masked
++VM 1 unmasked
++
++LUMOP
++00000 unit-stride
++00xxx reserved, x!=0
++01000 unit-stride, whole registers
++01xxx reserved, x!=0
++10000 unit-stride first-fault
++1xxxx reserved, x!=0
++
++SUMOP
++00000 unit-stride
++00xxx reserved, x!=0
++01000 unit-stride, whole registers
++01xxx reserved, x!=0
++1xxxx reserved
++
++MEW WIDTH
++- ---
++x 001	FLH/FSH
++x 010	FLW/FSW
++x 011	FLD/FSW
++x 100	FLQ/FSQ
++0 000	VLxE8/VSxE8
++0 101	VLxE16/VSxE16
++0 110	VLxE32/VSxE32
++0 111	VLxE64/VSxE64
++1 000	VLxE128/VSxE128
++1 101	VLxE256/VSxE256
++1 110	VLxE512/VSxE512
++1 111	VLxE1024/VSxE1024
++
++NF MEW MOP VM LUMOP/RS2 RS1 WIDTH VD opcode
++000 - 00 x 00000 xxxxx --- xxxxx 0000111 VLE<EEW>
++000 - 00 x 00000 xxxxx --- xxxxx 0100111 VSE<EEW>
++000 - 10 x xxxxx xxxxx --- xxxxx 0000111 VLSE<EEW>
++000 - 10 x xxxxx xxxxx --- xxxxx 0100111 VSSE<EEW>
++000 - 11 x xxxxx xxxxx --- xxxxx 0000111 VLXE<EEW>I
++000 - 11 x xxxxx xxxxx --- xxxxx 0100111 VSXE<EEW>I
++000 - 01 x xxxxx xxxxx --- xxxxx 0100111 VSUXE<EEW>I
++000 - 00 x 10000 xxxxx --- xxxxx 0000111 VLE<EEW>FF
++000 0 00 1 01000 xxxxx 000 xxxxx 0000111 VL<nf>R, nf = 1
++000 0 00 1 01000 xxxxx 000 xxxxx 0100111 VS<nf>R, nf = 1
++
++xxx - 00 x 00000 xxxxx --- xxxxx 0000111 VLSEG<nf>E<EEW>
++xxx - 00 x 00000 xxxxx --- xxxxx 0100111 VSSEG<nf>E<EEW>
++xxx - 10 x 00000 xxxxx --- xxxxx 0000111 VLSSEG<nf>E<EEW>
++xxx - 10 x 00000 xxxxx --- xxxxx 0100111 VSSSEG<nf>E<EEW>
++xxx - 11 x 00000 xxxxx --- xxxxx 0000111 VLXSEG<nf>E<EEW>I
++xxx - 11 x 00000 xxxxx --- xxxxx 0100111 VSXSEG<nf>E<EEW>I
++xxx - 00 x 10000 xxxxx --- xxxxx 0000111 VLSEG<nf>E<EEW>FF
++*/
++
++#define MATCH_VLE8V    0x00000007
++#define MASK_VLE8V     0xfdf0707f
++#define MATCH_VLE16V   0x00005007
++#define MASK_VLE16V    0xfdf0707f
++#define MATCH_VLE32V   0x00006007
++#define MASK_VLE32V    0xfdf0707f
++#define MATCH_VLE64V   0x00007007
++#define MASK_VLE64V    0xfdf0707f
++#define MATCH_VLE128V  0x10000007
++#define MASK_VLE128V   0xfdf0707f
++#define MATCH_VLE256V  0x10005007
++#define MASK_VLE256V   0xfdf0707f
++#define MATCH_VLE512V  0x10006007
++#define MASK_VLE512V   0xfdf0707f
++#define MATCH_VLE1024V 0x10007007
++#define MASK_VLE1024V  0xfdf0707f
++
++#define MATCH_VSE8V    0x00000027
++#define MASK_VSE8V     0xfdf0707f
++#define MATCH_VSE16V   0x00005027
++#define MASK_VSE16V    0xfdf0707f
++#define MATCH_VSE32V   0x00006027
++#define MASK_VSE32V    0xfdf0707f
++#define MATCH_VSE64V   0x00007027
++#define MASK_VSE64V    0xfdf0707f
++#define MATCH_VSE128V  0x10000027
++#define MASK_VSE128V   0xfdf0707f
++#define MATCH_VSE256V  0x10005027
++#define MASK_VSE256V   0xfdf0707f
++#define MATCH_VSE512V  0x10006027
++#define MASK_VSE512V   0xfdf0707f
++#define MATCH_VSE1024V 0x10007027
++#define MASK_VSE1024V  0xfdf0707f
++
++#define MATCH_VLSE8V    0x08000007
++#define MASK_VLSE8V     0xfc00707f
++#define MATCH_VLSE16V   0x08005007
++#define MASK_VLSE16V    0xfc00707f
++#define MATCH_VLSE32V   0x08006007
++#define MASK_VLSE32V    0xfc00707f
++#define MATCH_VLSE64V   0x08007007
++#define MASK_VLSE64V    0xfc00707f
++#define MATCH_VLSE128V  0x18000007
++#define MASK_VLSE128V   0xfc00707f
++#define MATCH_VLSE256V  0x18005007
++#define MASK_VLSE256V   0xfc00707f
++#define MATCH_VLSE512V  0x18006007
++#define MASK_VLSE512V   0xfc00707f
++#define MATCH_VLSE1024V 0x18007007
++#define MASK_VLSE1024V  0xfc00707f
++
++#define MATCH_VSSE8V    0x08000027
++#define MASK_VSSE8V     0xfc00707f
++#define MATCH_VSSE16V   0x08005027
++#define MASK_VSSE16V    0xfc00707f
++#define MATCH_VSSE32V   0x08006027
++#define MASK_VSSE32V    0xfc00707f
++#define MATCH_VSSE64V   0x08007027
++#define MASK_VSSE64V    0xfc00707f
++#define MATCH_VSSE128V  0x18000027
++#define MASK_VSSE128V   0xfc00707f
++#define MATCH_VSSE256V  0x18005027
++#define MASK_VSSE256V   0xfc00707f
++#define MATCH_VSSE512V  0x18006027
++#define MASK_VSSE512V   0xfc00707f
++#define MATCH_VSSE1024V 0x18007027
++#define MASK_VSSE1024V  0xfc00707f
++
++#define MATCH_VLXEI8V    0x0c000007
++#define MASK_VLXEI8V     0xfc00707f
++#define MATCH_VLXEI16V   0x0c005007
++#define MASK_VLXEI16V    0xfc00707f
++#define MATCH_VLXEI32V   0x0c006007
++#define MASK_VLXEI32V    0xfc00707f
++#define MATCH_VLXEI64V   0x0c007007
++#define MASK_VLXEI64V    0xfc00707f
++#define MATCH_VLXEI128V  0x1c000007
++#define MASK_VLXEI128V   0xfc00707f
++#define MATCH_VLXEI256V  0x1c005007
++#define MASK_VLXEI256V   0xfc00707f
++#define MATCH_VLXEI512V  0x1c006007
++#define MASK_VLXEI512V   0xfc00707f
++#define MATCH_VLXEI1024V 0x1c007007
++#define MASK_VLXEI1024V  0xfc00707f
++
++#define MATCH_VSXEI8V    0x0c000027
++#define MASK_VSXEI8V     0xfc00707f
++#define MATCH_VSXEI16V   0x0c005027
++#define MASK_VSXEI16V    0xfc00707f
++#define MATCH_VSXEI32V   0x0c006027
++#define MASK_VSXEI32V    0xfc00707f
++#define MATCH_VSXEI64V   0x0c007027
++#define MASK_VSXEI64V    0xfc00707f
++#define MATCH_VSXEI128V  0x1c000027
++#define MASK_VSXEI128V   0xfc00707f
++#define MATCH_VSXEI256V  0x1c005027
++#define MASK_VSXEI256V   0xfc00707f
++#define MATCH_VSXEI512V  0x1c006027
++#define MASK_VSXEI512V   0xfc00707f
++#define MATCH_VSXEI1024V 0x1c007027
++#define MASK_VSXEI1024V  0xfc00707f
++
++#define MATCH_VSUXEI8V    0x04000027
++#define MASK_VSUXEI8V     0xfc00707f
++#define MATCH_VSUXEI16V   0x04005027
++#define MASK_VSUXEI16V    0xfc00707f
++#define MATCH_VSUXEI32V   0x04006027
++#define MASK_VSUXEI32V    0xfc00707f
++#define MATCH_VSUXEI64V   0x04007027
++#define MASK_VSUXEI64V    0xfc00707f
++#define MATCH_VSUXEI128V  0x14000027
++#define MASK_VSUXEI128V   0xfc00707f
++#define MATCH_VSUXEI256V  0x14005027
++#define MASK_VSUXEI256V   0xfc00707f
++#define MATCH_VSUXEI512V  0x14006027
++#define MASK_VSUXEI512V   0xfc00707f
++#define MATCH_VSUXEI1024V 0x14007027
++#define MASK_VSUXEI1024V  0xfc00707f
++
++#define MATCH_VLE8FFV    0x01000007
++#define MASK_VLE8FFV     0xfdf0707f
++#define MATCH_VLE16FFV   0x01005007
++#define MASK_VLE16FFV    0xfdf0707f
++#define MATCH_VLE32FFV   0x01006007
++#define MASK_VLE32FFV    0xfdf0707f
++#define MATCH_VLE64FFV   0x01007007
++#define MASK_VLE64FFV    0xfdf0707f
++#define MATCH_VLE128FFV  0x11000007
++#define MASK_VLE128FFV   0xfdf0707f
++#define MATCH_VLE256FFV  0x11005007
++#define MASK_VLE256FFV   0xfdf0707f
++#define MATCH_VLE512FFV  0x11006007
++#define MASK_VLE512FFV   0xfdf0707f
++#define MATCH_VLE1024FFV 0x11007007
++#define MASK_VLE1024FFV  0xfdf0707f
++
++#define MATCH_VLSEG2E8V  0x20000007
++#define MASK_VLSEG2E8V   0xfdf0707f
++#define MATCH_VSSEG2E8V  0x20000027
++#define MASK_VSSEG2E8V   0xfdf0707f
++#define MATCH_VLSEG3E8V  0x40000007
++#define MASK_VLSEG3E8V   0xfdf0707f
++#define MATCH_VSSEG3E8V  0x40000027
++#define MASK_VSSEG3E8V   0xfdf0707f
++#define MATCH_VLSEG4E8V  0x60000007
++#define MASK_VLSEG4E8V   0xfdf0707f
++#define MATCH_VSSEG4E8V  0x60000027
++#define MASK_VSSEG4E8V   0xfdf0707f
++#define MATCH_VLSEG5E8V  0x80000007
++#define MASK_VLSEG5E8V   0xfdf0707f
++#define MATCH_VSSEG5E8V  0x80000027
++#define MASK_VSSEG5E8V   0xfdf0707f
++#define MATCH_VLSEG6E8V  0xa0000007
++#define MASK_VLSEG6E8V   0xfdf0707f
++#define MATCH_VSSEG6E8V  0xa0000027
++#define MASK_VSSEG6E8V   0xfdf0707f
++#define MATCH_VLSEG7E8V  0xc0000007
++#define MASK_VLSEG7E8V   0xfdf0707f
++#define MATCH_VSSEG7E8V  0xc0000027
++#define MASK_VSSEG7E8V   0xfdf0707f
++#define MATCH_VLSEG8E8V  0xe0000007
++#define MASK_VLSEG8E8V   0xfdf0707f
++#define MATCH_VSSEG8E8V  0xe0000027
++#define MASK_VSSEG8E8V   0xfdf0707f
++
++#define MATCH_VLSEG2E16V  0x20005007
++#define MASK_VLSEG2E16V   0xfdf0707f
++#define MATCH_VSSEG2E16V  0x20005027
++#define MASK_VSSEG2E16V   0xfdf0707f
++#define MATCH_VLSEG3E16V  0x40005007
++#define MASK_VLSEG3E16V   0xfdf0707f
++#define MATCH_VSSEG3E16V  0x40005027
++#define MASK_VSSEG3E16V   0xfdf0707f
++#define MATCH_VLSEG4E16V  0x60005007
++#define MASK_VLSEG4E16V   0xfdf0707f
++#define MATCH_VSSEG4E16V  0x60005027
++#define MASK_VSSEG4E16V   0xfdf0707f
++#define MATCH_VLSEG5E16V  0x80005007
++#define MASK_VLSEG5E16V   0xfdf0707f
++#define MATCH_VSSEG5E16V  0x80005027
++#define MASK_VSSEG5E16V   0xfdf0707f
++#define MATCH_VLSEG6E16V  0xa0005007
++#define MASK_VLSEG6E16V   0xfdf0707f
++#define MATCH_VSSEG6E16V  0xa0005027
++#define MASK_VSSEG6E16V   0xfdf0707f
++#define MATCH_VLSEG7E16V  0xc0005007
++#define MASK_VLSEG7E16V   0xfdf0707f
++#define MATCH_VSSEG7E16V  0xc0005027
++#define MASK_VSSEG7E16V   0xfdf0707f
++#define MATCH_VLSEG8E16V  0xe0005007
++#define MASK_VLSEG8E16V   0xfdf0707f
++#define MATCH_VSSEG8E16V  0xe0005027
++#define MASK_VSSEG8E16V   0xfdf0707f
++
++#define MATCH_VLSEG2E32V  0x20006007
++#define MASK_VLSEG2E32V   0xfdf0707f
++#define MATCH_VSSEG2E32V  0x20006027
++#define MASK_VSSEG2E32V   0xfdf0707f
++#define MATCH_VLSEG3E32V  0x40006007
++#define MASK_VLSEG3E32V   0xfdf0707f
++#define MATCH_VSSEG3E32V  0x40006027
++#define MASK_VSSEG3E32V   0xfdf0707f
++#define MATCH_VLSEG4E32V  0x60006007
++#define MASK_VLSEG4E32V   0xfdf0707f
++#define MATCH_VSSEG4E32V  0x60006027
++#define MASK_VSSEG4E32V   0xfdf0707f
++#define MATCH_VLSEG5E32V  0x80006007
++#define MASK_VLSEG5E32V   0xfdf0707f
++#define MATCH_VSSEG5E32V  0x80006027
++#define MASK_VSSEG5E32V   0xfdf0707f
++#define MATCH_VLSEG6E32V  0xa0006007
++#define MASK_VLSEG6E32V   0xfdf0707f
++#define MATCH_VSSEG6E32V  0xa0006027
++#define MASK_VSSEG6E32V   0xfdf0707f
++#define MATCH_VLSEG7E32V  0xc0006007
++#define MASK_VLSEG7E32V   0xfdf0707f
++#define MATCH_VSSEG7E32V  0xc0006027
++#define MASK_VSSEG7E32V   0xfdf0707f
++#define MATCH_VLSEG8E32V  0xe0006007
++#define MASK_VLSEG8E32V   0xfdf0707f
++#define MATCH_VSSEG8E32V  0xe0006027
++#define MASK_VSSEG8E32V   0xfdf0707f
++
++#define MATCH_VLSEG2E64V  0x20007007
++#define MASK_VLSEG2E64V   0xfdf0707f
++#define MATCH_VSSEG2E64V  0x20007027
++#define MASK_VSSEG2E64V   0xfdf0707f
++#define MATCH_VLSEG3E64V  0x40007007
++#define MASK_VLSEG3E64V   0xfdf0707f
++#define MATCH_VSSEG3E64V  0x40007027
++#define MASK_VSSEG3E64V   0xfdf0707f
++#define MATCH_VLSEG4E64V  0x60007007
++#define MASK_VLSEG4E64V   0xfdf0707f
++#define MATCH_VSSEG4E64V  0x60007027
++#define MASK_VSSEG4E64V   0xfdf0707f
++#define MATCH_VLSEG5E64V  0x80007007
++#define MASK_VLSEG5E64V   0xfdf0707f
++#define MATCH_VSSEG5E64V  0x80007027
++#define MASK_VSSEG5E64V   0xfdf0707f
++#define MATCH_VLSEG6E64V  0xa0007007
++#define MASK_VLSEG6E64V   0xfdf0707f
++#define MATCH_VSSEG6E64V  0xa0007027
++#define MASK_VSSEG6E64V   0xfdf0707f
++#define MATCH_VLSEG7E64V  0xc0007007
++#define MASK_VLSEG7E64V   0xfdf0707f
++#define MATCH_VSSEG7E64V  0xc0007027
++#define MASK_VSSEG7E64V   0xfdf0707f
++#define MATCH_VLSEG8E64V  0xe0007007
++#define MASK_VLSEG8E64V   0xfdf0707f
++#define MATCH_VSSEG8E64V  0xe0007027
++#define MASK_VSSEG8E64V   0xfdf0707f
++
++#define MATCH_VLSEG2E128V  0x30000007
++#define MASK_VLSEG2E128V   0xfdf0707f
++#define MATCH_VSSEG2E128V  0x30000027
++#define MASK_VSSEG2E128V   0xfdf0707f
++#define MATCH_VLSEG3E128V  0x50000007
++#define MASK_VLSEG3E128V   0xfdf0707f
++#define MATCH_VSSEG3E128V  0x50000027
++#define MASK_VSSEG3E128V   0xfdf0707f
++#define MATCH_VLSEG4E128V  0x70000007
++#define MASK_VLSEG4E128V   0xfdf0707f
++#define MATCH_VSSEG4E128V  0x70000027
++#define MASK_VSSEG4E128V   0xfdf0707f
++#define MATCH_VLSEG5E128V  0x90000007
++#define MASK_VLSEG5E128V   0xfdf0707f
++#define MATCH_VSSEG5E128V  0x90000027
++#define MASK_VSSEG5E128V   0xfdf0707f
++#define MATCH_VLSEG6E128V  0xb0000007
++#define MASK_VLSEG6E128V   0xfdf0707f
++#define MATCH_VSSEG6E128V  0xb0000027
++#define MASK_VSSEG6E128V   0xfdf0707f
++#define MATCH_VLSEG7E128V  0xd0000007
++#define MASK_VLSEG7E128V   0xfdf0707f
++#define MATCH_VSSEG7E128V  0xd0000027
++#define MASK_VSSEG7E128V   0xfdf0707f
++#define MATCH_VLSEG8E128V  0xf0000007
++#define MASK_VLSEG8E128V   0xfdf0707f
++#define MATCH_VSSEG8E128V  0xf0000027
++#define MASK_VSSEG8E128V   0xfdf0707f
++
++#define MATCH_VLSEG2E256V  0x30005007
++#define MASK_VLSEG2E256V   0xfdf0707f
++#define MATCH_VSSEG2E256V  0x30005027
++#define MASK_VSSEG2E256V   0xfdf0707f
++#define MATCH_VLSEG3E256V  0x50005007
++#define MASK_VLSEG3E256V   0xfdf0707f
++#define MATCH_VSSEG3E256V  0x50005027
++#define MASK_VSSEG3E256V   0xfdf0707f
++#define MATCH_VLSEG4E256V  0x70005007
++#define MASK_VLSEG4E256V   0xfdf0707f
++#define MATCH_VSSEG4E256V  0x70005027
++#define MASK_VSSEG4E256V   0xfdf0707f
++#define MATCH_VLSEG5E256V  0x90005007
++#define MASK_VLSEG5E256V   0xfdf0707f
++#define MATCH_VSSEG5E256V  0x90005027
++#define MASK_VSSEG5E256V   0xfdf0707f
++#define MATCH_VLSEG6E256V  0xb0005007
++#define MASK_VLSEG6E256V   0xfdf0707f
++#define MATCH_VSSEG6E256V  0xb0005027
++#define MASK_VSSEG6E256V   0xfdf0707f
++#define MATCH_VLSEG7E256V  0xd0005007
++#define MASK_VLSEG7E256V   0xfdf0707f
++#define MATCH_VSSEG7E256V  0xd0005027
++#define MASK_VSSEG7E256V   0xfdf0707f
++#define MATCH_VLSEG8E256V  0xf0005007
++#define MASK_VLSEG8E256V   0xfdf0707f
++#define MATCH_VSSEG8E256V  0xf0005027
++#define MASK_VSSEG8E256V   0xfdf0707f
++
++#define MATCH_VLSEG2E512V  0x30006007
++#define MASK_VLSEG2E512V   0xfdf0707f
++#define MATCH_VSSEG2E512V  0x30006027
++#define MASK_VSSEG2E512V   0xfdf0707f
++#define MATCH_VLSEG3E512V  0x50006007
++#define MASK_VLSEG3E512V   0xfdf0707f
++#define MATCH_VSSEG3E512V  0x50006027
++#define MASK_VSSEG3E512V   0xfdf0707f
++#define MATCH_VLSEG4E512V  0x70006007
++#define MASK_VLSEG4E512V   0xfdf0707f
++#define MATCH_VSSEG4E512V  0x70006027
++#define MASK_VSSEG4E512V   0xfdf0707f
++#define MATCH_VLSEG5E512V  0x90006007
++#define MASK_VLSEG5E512V   0xfdf0707f
++#define MATCH_VSSEG5E512V  0x90006027
++#define MASK_VSSEG5E512V   0xfdf0707f
++#define MATCH_VLSEG6E512V  0xb0006007
++#define MASK_VLSEG6E512V   0xfdf0707f
++#define MATCH_VSSEG6E512V  0xb0006027
++#define MASK_VSSEG6E512V   0xfdf0707f
++#define MATCH_VLSEG7E512V  0xd0006007
++#define MASK_VLSEG7E512V   0xfdf0707f
++#define MATCH_VSSEG7E512V  0xd0006027
++#define MASK_VSSEG7E512V   0xfdf0707f
++#define MATCH_VLSEG8E512V  0xf0006007
++#define MASK_VLSEG8E512V   0xfdf0707f
++#define MATCH_VSSEG8E512V  0xf0006027
++#define MASK_VSSEG8E512V   0xfdf0707f
++
++#define MATCH_VLSEG2E1024V  0x30007007
++#define MASK_VLSEG2E1024V   0xfdf0707f
++#define MATCH_VSSEG2E1024V  0x30007027
++#define MASK_VSSEG2E1024V   0xfdf0707f
++#define MATCH_VLSEG3E1024V  0x50007007
++#define MASK_VLSEG3E1024V   0xfdf0707f
++#define MATCH_VSSEG3E1024V  0x50007027
++#define MASK_VSSEG3E1024V   0xfdf0707f
++#define MATCH_VLSEG4E1024V  0x70007007
++#define MASK_VLSEG4E1024V   0xfdf0707f
++#define MATCH_VSSEG4E1024V  0x70007027
++#define MASK_VSSEG4E1024V   0xfdf0707f
++#define MATCH_VLSEG5E1024V  0x90007007
++#define MASK_VLSEG5E1024V   0xfdf0707f
++#define MATCH_VSSEG5E1024V  0x90007027
++#define MASK_VSSEG5E1024V   0xfdf0707f
++#define MATCH_VLSEG6E1024V  0xb0007007
++#define MASK_VLSEG6E1024V   0xfdf0707f
++#define MATCH_VSSEG6E1024V  0xb0007027
++#define MASK_VSSEG6E1024V   0xfdf0707f
++#define MATCH_VLSEG7E1024V  0xd0007007
++#define MASK_VLSEG7E1024V   0xfdf0707f
++#define MATCH_VSSEG7E1024V  0xd0007027
++#define MASK_VSSEG7E1024V   0xfdf0707f
++#define MATCH_VLSEG8E1024V  0xf0007007
++#define MASK_VLSEG8E1024V   0xfdf0707f
++#define MATCH_VSSEG8E1024V  0xf0007027
++#define MASK_VSSEG8E1024V   0xfdf0707f
++
++#define MATCH_VLSSEG2E8V  0x28000007
++#define MASK_VLSSEG2E8V   0xfc00707f
++#define MATCH_VSSSEG2E8V  0x28000027
++#define MASK_VSSSEG2E8V   0xfc00707f
++#define MATCH_VLSSEG3E8V  0x48000007
++#define MASK_VLSSEG3E8V   0xfc00707f
++#define MATCH_VSSSEG3E8V  0x48000027
++#define MASK_VSSSEG3E8V   0xfc00707f
++#define MATCH_VLSSEG4E8V  0x68000007
++#define MASK_VLSSEG4E8V   0xfc00707f
++#define MATCH_VSSSEG4E8V  0x68000027
++#define MASK_VSSSEG4E8V   0xfc00707f
++#define MATCH_VLSSEG5E8V  0x88000007
++#define MASK_VLSSEG5E8V   0xfc00707f
++#define MATCH_VSSSEG5E8V  0x88000027
++#define MASK_VSSSEG5E8V   0xfc00707f
++#define MATCH_VLSSEG6E8V  0xa8000007
++#define MASK_VLSSEG6E8V   0xfc00707f
++#define MATCH_VSSSEG6E8V  0xa8000027
++#define MASK_VSSSEG6E8V   0xfc00707f
++#define MATCH_VLSSEG7E8V  0xc8000007
++#define MASK_VLSSEG7E8V   0xfc00707f
++#define MATCH_VSSSEG7E8V  0xc8000027
++#define MASK_VSSSEG7E8V   0xfc00707f
++#define MATCH_VLSSEG8E8V  0xe8000007
++#define MASK_VLSSEG8E8V   0xfc00707f
++#define MATCH_VSSSEG8E8V  0xe8000027
++#define MASK_VSSSEG8E8V   0xfc00707f
++
++#define MATCH_VLSSEG2E16V  0x28005007
++#define MASK_VLSSEG2E16V   0xfc00707f
++#define MATCH_VSSSEG2E16V  0x28005027
++#define MASK_VSSSEG2E16V   0xfc00707f
++#define MATCH_VLSSEG3E16V  0x48005007
++#define MASK_VLSSEG3E16V   0xfc00707f
++#define MATCH_VSSSEG3E16V  0x48005027
++#define MASK_VSSSEG3E16V   0xfc00707f
++#define MATCH_VLSSEG4E16V  0x68005007
++#define MASK_VLSSEG4E16V   0xfc00707f
++#define MATCH_VSSSEG4E16V  0x68005027
++#define MASK_VSSSEG4E16V   0xfc00707f
++#define MATCH_VLSSEG5E16V  0x88005007
++#define MASK_VLSSEG5E16V   0xfc00707f
++#define MATCH_VSSSEG5E16V  0x88005027
++#define MASK_VSSSEG5E16V   0xfc00707f
++#define MATCH_VLSSEG6E16V  0xa8005007
++#define MASK_VLSSEG6E16V   0xfc00707f
++#define MATCH_VSSSEG6E16V  0xa8005027
++#define MASK_VSSSEG6E16V   0xfc00707f
++#define MATCH_VLSSEG7E16V  0xc8005007
++#define MASK_VLSSEG7E16V   0xfc00707f
++#define MATCH_VSSSEG7E16V  0xc8005027
++#define MASK_VSSSEG7E16V   0xfc00707f
++#define MATCH_VLSSEG8E16V  0xe8005007
++#define MASK_VLSSEG8E16V   0xfc00707f
++#define MATCH_VSSSEG8E16V  0xe8005027
++#define MASK_VSSSEG8E16V   0xfc00707f
++
++#define MATCH_VLSSEG2E32V  0x28006007
++#define MASK_VLSSEG2E32V   0xfc00707f
++#define MATCH_VSSSEG2E32V  0x28006027
++#define MASK_VSSSEG2E32V   0xfc00707f
++#define MATCH_VLSSEG3E32V  0x48006007
++#define MASK_VLSSEG3E32V   0xfc00707f
++#define MATCH_VSSSEG3E32V  0x48006027
++#define MASK_VSSSEG3E32V   0xfc00707f
++#define MATCH_VLSSEG4E32V  0x68006007
++#define MASK_VLSSEG4E32V   0xfc00707f
++#define MATCH_VSSSEG4E32V  0x68006027
++#define MASK_VSSSEG4E32V   0xfc00707f
++#define MATCH_VLSSEG5E32V  0x88006007
++#define MASK_VLSSEG5E32V   0xfc00707f
++#define MATCH_VSSSEG5E32V  0x88006027
++#define MASK_VSSSEG5E32V   0xfc00707f
++#define MATCH_VLSSEG6E32V  0xa8006007
++#define MASK_VLSSEG6E32V   0xfc00707f
++#define MATCH_VSSSEG6E32V  0xa8006027
++#define MASK_VSSSEG6E32V   0xfc00707f
++#define MATCH_VLSSEG7E32V  0xc8006007
++#define MASK_VLSSEG7E32V   0xfc00707f
++#define MATCH_VSSSEG7E32V  0xc8006027
++#define MASK_VSSSEG7E32V   0xfc00707f
++#define MATCH_VLSSEG8E32V  0xe8006007
++#define MASK_VLSSEG8E32V   0xfc00707f
++#define MATCH_VSSSEG8E32V  0xe8006027
++#define MASK_VSSSEG8E32V   0xfc00707f
++
++#define MATCH_VLSSEG2E64V  0x28007007
++#define MASK_VLSSEG2E64V   0xfc00707f
++#define MATCH_VSSSEG2E64V  0x28007027
++#define MASK_VSSSEG2E64V   0xfc00707f
++#define MATCH_VLSSEG3E64V  0x48007007
++#define MASK_VLSSEG3E64V   0xfc00707f
++#define MATCH_VSSSEG3E64V  0x48007027
++#define MASK_VSSSEG3E64V   0xfc00707f
++#define MATCH_VLSSEG4E64V  0x68007007
++#define MASK_VLSSEG4E64V   0xfc00707f
++#define MATCH_VSSSEG4E64V  0x68007027
++#define MASK_VSSSEG4E64V   0xfc00707f
++#define MATCH_VLSSEG5E64V  0x88007007
++#define MASK_VLSSEG5E64V   0xfc00707f
++#define MATCH_VSSSEG5E64V  0x88007027
++#define MASK_VSSSEG5E64V   0xfc00707f
++#define MATCH_VLSSEG6E64V  0xa8007007
++#define MASK_VLSSEG6E64V   0xfc00707f
++#define MATCH_VSSSEG6E64V  0xa8007027
++#define MASK_VSSSEG6E64V   0xfc00707f
++#define MATCH_VLSSEG7E64V  0xc8007007
++#define MASK_VLSSEG7E64V   0xfc00707f
++#define MATCH_VSSSEG7E64V  0xc8007027
++#define MASK_VSSSEG7E64V   0xfc00707f
++#define MATCH_VLSSEG8E64V  0xe8007007
++#define MASK_VLSSEG8E64V   0xfc00707f
++#define MATCH_VSSSEG8E64V  0xe8007027
++#define MASK_VSSSEG8E64V   0xfc00707f
++
++#define MATCH_VLSSEG2E128V  0x38000007
++#define MASK_VLSSEG2E128V   0xfc00707f
++#define MATCH_VSSSEG2E128V  0x38000027
++#define MASK_VSSSEG2E128V   0xfc00707f
++#define MATCH_VLSSEG3E128V  0x58000007
++#define MASK_VLSSEG3E128V   0xfc00707f
++#define MATCH_VSSSEG3E128V  0x58000027
++#define MASK_VSSSEG3E128V   0xfc00707f
++#define MATCH_VLSSEG4E128V  0x78000007
++#define MASK_VLSSEG4E128V   0xfc00707f
++#define MATCH_VSSSEG4E128V  0x78000027
++#define MASK_VSSSEG4E128V   0xfc00707f
++#define MATCH_VLSSEG5E128V  0x98000007
++#define MASK_VLSSEG5E128V   0xfc00707f
++#define MATCH_VSSSEG5E128V  0x98000027
++#define MASK_VSSSEG5E128V   0xfc00707f
++#define MATCH_VLSSEG6E128V  0xb8000007
++#define MASK_VLSSEG6E128V   0xfc00707f
++#define MATCH_VSSSEG6E128V  0xb8000027
++#define MASK_VSSSEG6E128V   0xfc00707f
++#define MATCH_VLSSEG7E128V  0xd8000007
++#define MASK_VLSSEG7E128V   0xfc00707f
++#define MATCH_VSSSEG7E128V  0xd8000027
++#define MASK_VSSSEG7E128V   0xfc00707f
++#define MATCH_VLSSEG8E128V  0xf8000007
++#define MASK_VLSSEG8E128V   0xfc00707f
++#define MATCH_VSSSEG8E128V  0xf8000027
++#define MASK_VSSSEG8E128V   0xfc00707f
++
++#define MATCH_VLSSEG2E256V  0x38005007
++#define MASK_VLSSEG2E256V   0xfc00707f
++#define MATCH_VSSSEG2E256V  0x38005027
++#define MASK_VSSSEG2E256V   0xfc00707f
++#define MATCH_VLSSEG3E256V  0x58005007
++#define MASK_VLSSEG3E256V   0xfc00707f
++#define MATCH_VSSSEG3E256V  0x58005027
++#define MASK_VSSSEG3E256V   0xfc00707f
++#define MATCH_VLSSEG4E256V  0x78005007
++#define MASK_VLSSEG4E256V   0xfc00707f
++#define MATCH_VSSSEG4E256V  0x78005027
++#define MASK_VSSSEG4E256V   0xfc00707f
++#define MATCH_VLSSEG5E256V  0x98005007
++#define MASK_VLSSEG5E256V   0xfc00707f
++#define MATCH_VSSSEG5E256V  0x98005027
++#define MASK_VSSSEG5E256V   0xfc00707f
++#define MATCH_VLSSEG6E256V  0xb8005007
++#define MASK_VLSSEG6E256V   0xfc00707f
++#define MATCH_VSSSEG6E256V  0xb8005027
++#define MASK_VSSSEG6E256V   0xfc00707f
++#define MATCH_VLSSEG7E256V  0xd8005007
++#define MASK_VLSSEG7E256V   0xfc00707f
++#define MATCH_VSSSEG7E256V  0xd8005027
++#define MASK_VSSSEG7E256V   0xfc00707f
++#define MATCH_VLSSEG8E256V  0xf8005007
++#define MASK_VLSSEG8E256V   0xfc00707f
++#define MATCH_VSSSEG8E256V  0xf8005027
++#define MASK_VSSSEG8E256V   0xfc00707f
++
++#define MATCH_VLSSEG2E512V  0x38006007
++#define MASK_VLSSEG2E512V   0xfc00707f
++#define MATCH_VSSSEG2E512V  0x38006027
++#define MASK_VSSSEG2E512V   0xfc00707f
++#define MATCH_VLSSEG3E512V  0x58006007
++#define MASK_VLSSEG3E512V   0xfc00707f
++#define MATCH_VSSSEG3E512V  0x58006027
++#define MASK_VSSSEG3E512V   0xfc00707f
++#define MATCH_VLSSEG4E512V  0x78006007
++#define MASK_VLSSEG4E512V   0xfc00707f
++#define MATCH_VSSSEG4E512V  0x78006027
++#define MASK_VSSSEG4E512V   0xfc00707f
++#define MATCH_VLSSEG5E512V  0x98006007
++#define MASK_VLSSEG5E512V   0xfc00707f
++#define MATCH_VSSSEG5E512V  0x98006027
++#define MASK_VSSSEG5E512V   0xfc00707f
++#define MATCH_VLSSEG6E512V  0xb8006007
++#define MASK_VLSSEG6E512V   0xfc00707f
++#define MATCH_VSSSEG6E512V  0xb8006027
++#define MASK_VSSSEG6E512V   0xfc00707f
++#define MATCH_VLSSEG7E512V  0xd8006007
++#define MASK_VLSSEG7E512V   0xfc00707f
++#define MATCH_VSSSEG7E512V  0xd8006027
++#define MASK_VSSSEG7E512V   0xfc00707f
++#define MATCH_VLSSEG8E512V  0xf8006007
++#define MASK_VLSSEG8E512V   0xfc00707f
++#define MATCH_VSSSEG8E512V  0xf8006027
++#define MASK_VSSSEG8E512V   0xfc00707f
++
++#define MATCH_VLSSEG2E1024V  0x38007007
++#define MASK_VLSSEG2E1024V   0xfc00707f
++#define MATCH_VSSSEG2E1024V  0x38007027
++#define MASK_VSSSEG2E1024V   0xfc00707f
++#define MATCH_VLSSEG3E1024V  0x58007007
++#define MASK_VLSSEG3E1024V   0xfc00707f
++#define MATCH_VSSSEG3E1024V  0x58007027
++#define MASK_VSSSEG3E1024V   0xfc00707f
++#define MATCH_VLSSEG4E1024V  0x78007007
++#define MASK_VLSSEG4E1024V   0xfc00707f
++#define MATCH_VSSSEG4E1024V  0x78007027
++#define MASK_VSSSEG4E1024V   0xfc00707f
++#define MATCH_VLSSEG5E1024V  0x98007007
++#define MASK_VLSSEG5E1024V   0xfc00707f
++#define MATCH_VSSSEG5E1024V  0x98007027
++#define MASK_VSSSEG5E1024V   0xfc00707f
++#define MATCH_VLSSEG6E1024V  0xb8007007
++#define MASK_VLSSEG6E1024V   0xfc00707f
++#define MATCH_VSSSEG6E1024V  0xb8007027
++#define MASK_VSSSEG6E1024V   0xfc00707f
++#define MATCH_VLSSEG7E1024V  0xd8007007
++#define MASK_VLSSEG7E1024V   0xfc00707f
++#define MATCH_VSSSEG7E1024V  0xd8007027
++#define MASK_VSSSEG7E1024V   0xfc00707f
++#define MATCH_VLSSEG8E1024V  0xf8007007
++#define MASK_VLSSEG8E1024V   0xfc00707f
++#define MATCH_VSSSEG8E1024V  0xf8007027
++#define MASK_VSSSEG8E1024V   0xfc00707f
++
++#define MATCH_VLXSEG2EI8V  0x2c000007
++#define MASK_VLXSEG2EI8V   0xfc00707f
++#define MATCH_VSXSEG2EI8V  0x2c000027
++#define MASK_VSXSEG2EI8V   0xfc00707f
++#define MATCH_VLXSEG3EI8V  0x4c000007
++#define MASK_VLXSEG3EI8V   0xfc00707f
++#define MATCH_VSXSEG3EI8V  0x4c000027
++#define MASK_VSXSEG3EI8V   0xfc00707f
++#define MATCH_VLXSEG4EI8V  0x6c000007
++#define MASK_VLXSEG4EI8V   0xfc00707f
++#define MATCH_VSXSEG4EI8V  0x6c000027
++#define MASK_VSXSEG4EI8V   0xfc00707f
++#define MATCH_VLXSEG5EI8V  0x8c000007
++#define MASK_VLXSEG5EI8V   0xfc00707f
++#define MATCH_VSXSEG5EI8V  0x8c000027
++#define MASK_VSXSEG5EI8V   0xfc00707f
++#define MATCH_VLXSEG6EI8V  0xac000007
++#define MASK_VLXSEG6EI8V   0xfc00707f
++#define MATCH_VSXSEG6EI8V  0xac000027
++#define MASK_VSXSEG6EI8V   0xfc00707f
++#define MATCH_VLXSEG7EI8V  0xcc000007
++#define MASK_VLXSEG7EI8V   0xfc00707f
++#define MATCH_VSXSEG7EI8V  0xcc000027
++#define MASK_VSXSEG7EI8V   0xfc00707f
++#define MATCH_VLXSEG8EI8V  0xec000007
++#define MASK_VLXSEG8EI8V   0xfc00707f
++#define MATCH_VSXSEG8EI8V  0xec000027
++#define MASK_VSXSEG8EI8V   0xfc00707f
++
++#define MATCH_VLXSEG2EI16V  0x2c005007
++#define MASK_VLXSEG2EI16V   0xfc00707f
++#define MATCH_VSXSEG2EI16V  0x2c005027
++#define MASK_VSXSEG2EI16V   0xfc00707f
++#define MATCH_VLXSEG3EI16V  0x4c005007
++#define MASK_VLXSEG3EI16V   0xfc00707f
++#define MATCH_VSXSEG3EI16V  0x4c005027
++#define MASK_VSXSEG3EI16V   0xfc00707f
++#define MATCH_VLXSEG4EI16V  0x6c005007
++#define MASK_VLXSEG4EI16V   0xfc00707f
++#define MATCH_VSXSEG4EI16V  0x6c005027
++#define MASK_VSXSEG4EI16V   0xfc00707f
++#define MATCH_VLXSEG5EI16V  0x8c005007
++#define MASK_VLXSEG5EI16V   0xfc00707f
++#define MATCH_VSXSEG5EI16V  0x8c005027
++#define MASK_VSXSEG5EI16V   0xfc00707f
++#define MATCH_VLXSEG6EI16V  0xac005007
++#define MASK_VLXSEG6EI16V   0xfc00707f
++#define MATCH_VSXSEG6EI16V  0xac005027
++#define MASK_VSXSEG6EI16V   0xfc00707f
++#define MATCH_VLXSEG7EI16V  0xcc005007
++#define MASK_VLXSEG7EI16V   0xfc00707f
++#define MATCH_VSXSEG7EI16V  0xcc005027
++#define MASK_VSXSEG7EI16V   0xfc00707f
++#define MATCH_VLXSEG8EI16V  0xec005007
++#define MASK_VLXSEG8EI16V   0xfc00707f
++#define MATCH_VSXSEG8EI16V  0xec005027
++#define MASK_VSXSEG8EI16V   0xfc00707f
++
++#define MATCH_VLXSEG2EI32V  0x2c006007
++#define MASK_VLXSEG2EI32V   0xfc00707f
++#define MATCH_VSXSEG2EI32V  0x2c006027
++#define MASK_VSXSEG2EI32V   0xfc00707f
++#define MATCH_VLXSEG3EI32V  0x4c006007
++#define MASK_VLXSEG3EI32V   0xfc00707f
++#define MATCH_VSXSEG3EI32V  0x4c006027
++#define MASK_VSXSEG3EI32V   0xfc00707f
++#define MATCH_VLXSEG4EI32V  0x6c006007
++#define MASK_VLXSEG4EI32V   0xfc00707f
++#define MATCH_VSXSEG4EI32V  0x6c006027
++#define MASK_VSXSEG4EI32V   0xfc00707f
++#define MATCH_VLXSEG5EI32V  0x8c006007
++#define MASK_VLXSEG5EI32V   0xfc00707f
++#define MATCH_VSXSEG5EI32V  0x8c006027
++#define MASK_VSXSEG5EI32V   0xfc00707f
++#define MATCH_VLXSEG6EI32V  0xac006007
++#define MASK_VLXSEG6EI32V   0xfc00707f
++#define MATCH_VSXSEG6EI32V  0xac006027
++#define MASK_VSXSEG6EI32V   0xfc00707f
++#define MATCH_VLXSEG7EI32V  0xcc006007
++#define MASK_VLXSEG7EI32V   0xfc00707f
++#define MATCH_VSXSEG7EI32V  0xcc006027
++#define MASK_VSXSEG7EI32V   0xfc00707f
++#define MATCH_VLXSEG8EI32V  0xec006007
++#define MASK_VLXSEG8EI32V   0xfc00707f
++#define MATCH_VSXSEG8EI32V  0xec006027
++#define MASK_VSXSEG8EI32V   0xfc00707f
++
++#define MATCH_VLXSEG2EI64V  0x2c007007
++#define MASK_VLXSEG2EI64V   0xfc00707f
++#define MATCH_VSXSEG2EI64V  0x2c007027
++#define MASK_VSXSEG2EI64V   0xfc00707f
++#define MATCH_VLXSEG3EI64V  0x4c007007
++#define MASK_VLXSEG3EI64V   0xfc00707f
++#define MATCH_VSXSEG3EI64V  0x4c007027
++#define MASK_VSXSEG3EI64V   0xfc00707f
++#define MATCH_VLXSEG4EI64V  0x6c007007
++#define MASK_VLXSEG4EI64V   0xfc00707f
++#define MATCH_VSXSEG4EI64V  0x6c007027
++#define MASK_VSXSEG4EI64V   0xfc00707f
++#define MATCH_VLXSEG5EI64V  0x8c007007
++#define MASK_VLXSEG5EI64V   0xfc00707f
++#define MATCH_VSXSEG5EI64V  0x8c007027
++#define MASK_VSXSEG5EI64V   0xfc00707f
++#define MATCH_VLXSEG6EI64V  0xac007007
++#define MASK_VLXSEG6EI64V   0xfc00707f
++#define MATCH_VSXSEG6EI64V  0xac007027
++#define MASK_VSXSEG6EI64V   0xfc00707f
++#define MATCH_VLXSEG7EI64V  0xcc007007
++#define MASK_VLXSEG7EI64V   0xfc00707f
++#define MATCH_VSXSEG7EI64V  0xcc007027
++#define MASK_VSXSEG7EI64V   0xfc00707f
++#define MATCH_VLXSEG8EI64V  0xec007007
++#define MASK_VLXSEG8EI64V   0xfc00707f
++#define MATCH_VSXSEG8EI64V  0xec007027
++#define MASK_VSXSEG8EI64V   0xfc00707f
++
++#define MATCH_VLXSEG2EI128V  0x3c000007
++#define MASK_VLXSEG2EI128V   0xfc00707f
++#define MATCH_VSXSEG2EI128V  0x3c000027
++#define MASK_VSXSEG2EI128V   0xfc00707f
++#define MATCH_VLXSEG3EI128V  0x5c000007
++#define MASK_VLXSEG3EI128V   0xfc00707f
++#define MATCH_VSXSEG3EI128V  0x5c000027
++#define MASK_VSXSEG3EI128V   0xfc00707f
++#define MATCH_VLXSEG4EI128V  0x7c000007
++#define MASK_VLXSEG4EI128V   0xfc00707f
++#define MATCH_VSXSEG4EI128V  0x7c000027
++#define MASK_VSXSEG4EI128V   0xfc00707f
++#define MATCH_VLXSEG5EI128V  0x9c000007
++#define MASK_VLXSEG5EI128V   0xfc00707f
++#define MATCH_VSXSEG5EI128V  0x9c000027
++#define MASK_VSXSEG5EI128V   0xfc00707f
++#define MATCH_VLXSEG6EI128V  0xbc000007
++#define MASK_VLXSEG6EI128V   0xfc00707f
++#define MATCH_VSXSEG6EI128V  0xbc000027
++#define MASK_VSXSEG6EI128V   0xfc00707f
++#define MATCH_VLXSEG7EI128V  0xdc000007
++#define MASK_VLXSEG7EI128V   0xfc00707f
++#define MATCH_VSXSEG7EI128V  0xdc000027
++#define MASK_VSXSEG7EI128V   0xfc00707f
++#define MATCH_VLXSEG8EI128V  0xfc000007
++#define MASK_VLXSEG8EI128V   0xfc00707f
++#define MATCH_VSXSEG8EI128V  0xfc000027
++#define MASK_VSXSEG8EI128V   0xfc00707f
++
++#define MATCH_VLXSEG2EI256V  0x3c005007
++#define MASK_VLXSEG2EI256V   0xfc00707f
++#define MATCH_VSXSEG2EI256V  0x3c005027
++#define MASK_VSXSEG2EI256V   0xfc00707f
++#define MATCH_VLXSEG3EI256V  0x5c005007
++#define MASK_VLXSEG3EI256V   0xfc00707f
++#define MATCH_VSXSEG3EI256V  0x5c005027
++#define MASK_VSXSEG3EI256V   0xfc00707f
++#define MATCH_VLXSEG4EI256V  0x7c005007
++#define MASK_VLXSEG4EI256V   0xfc00707f
++#define MATCH_VSXSEG4EI256V  0x7c005027
++#define MASK_VSXSEG4EI256V   0xfc00707f
++#define MATCH_VLXSEG5EI256V  0x9c005007
++#define MASK_VLXSEG5EI256V   0xfc00707f
++#define MATCH_VSXSEG5EI256V  0x9c005027
++#define MASK_VSXSEG5EI256V   0xfc00707f
++#define MATCH_VLXSEG6EI256V  0xbc005007
++#define MASK_VLXSEG6EI256V   0xfc00707f
++#define MATCH_VSXSEG6EI256V  0xbc005027
++#define MASK_VSXSEG6EI256V   0xfc00707f
++#define MATCH_VLXSEG7EI256V  0xdc005007
++#define MASK_VLXSEG7EI256V   0xfc00707f
++#define MATCH_VSXSEG7EI256V  0xdc005027
++#define MASK_VSXSEG7EI256V   0xfc00707f
++#define MATCH_VLXSEG8EI256V  0xfc005007
++#define MASK_VLXSEG8EI256V   0xfc00707f
++#define MATCH_VSXSEG8EI256V  0xfc005027
++#define MASK_VSXSEG8EI256V   0xfc00707f
++
++#define MATCH_VLXSEG2EI512V  0x3c006007
++#define MASK_VLXSEG2EI512V   0xfc00707f
++#define MATCH_VSXSEG2EI512V  0x3c006027
++#define MASK_VSXSEG2EI512V   0xfc00707f
++#define MATCH_VLXSEG3EI512V  0x5c006007
++#define MASK_VLXSEG3EI512V   0xfc00707f
++#define MATCH_VSXSEG3EI512V  0x5c006027
++#define MASK_VSXSEG3EI512V   0xfc00707f
++#define MATCH_VLXSEG4EI512V  0x7c006007
++#define MASK_VLXSEG4EI512V   0xfc00707f
++#define MATCH_VSXSEG4EI512V  0x7c006027
++#define MASK_VSXSEG4EI512V   0xfc00707f
++#define MATCH_VLXSEG5EI512V  0x9c006007
++#define MASK_VLXSEG5EI512V   0xfc00707f
++#define MATCH_VSXSEG5EI512V  0x9c006027
++#define MASK_VSXSEG5EI512V   0xfc00707f
++#define MATCH_VLXSEG6EI512V  0xbc006007
++#define MASK_VLXSEG6EI512V   0xfc00707f
++#define MATCH_VSXSEG6EI512V  0xbc006027
++#define MASK_VSXSEG6EI512V   0xfc00707f
++#define MATCH_VLXSEG7EI512V  0xdc006007
++#define MASK_VLXSEG7EI512V   0xfc00707f
++#define MATCH_VSXSEG7EI512V  0xdc006027
++#define MASK_VSXSEG7EI512V   0xfc00707f
++#define MATCH_VLXSEG8EI512V  0xfc006007
++#define MASK_VLXSEG8EI512V   0xfc00707f
++#define MATCH_VSXSEG8EI512V  0xfc006027
++#define MASK_VSXSEG8EI512V   0xfc00707f
++
++#define MATCH_VLXSEG2EI1024V  0x3c007007
++#define MASK_VLXSEG2EI1024V   0xfc00707f
++#define MATCH_VSXSEG2EI1024V  0x3c007027
++#define MASK_VSXSEG2EI1024V   0xfc00707f
++#define MATCH_VLXSEG3EI1024V  0x5c007007
++#define MASK_VLXSEG3EI1024V   0xfc00707f
++#define MATCH_VSXSEG3EI1024V  0x5c007027
++#define MASK_VSXSEG3EI1024V   0xfc00707f
++#define MATCH_VLXSEG4EI1024V  0x7c007007
++#define MASK_VLXSEG4EI1024V   0xfc00707f
++#define MATCH_VSXSEG4EI1024V  0x7c007027
++#define MASK_VSXSEG4EI1024V   0xfc00707f
++#define MATCH_VLXSEG5EI1024V  0x9c007007
++#define MASK_VLXSEG5EI1024V   0xfc00707f
++#define MATCH_VSXSEG5EI1024V  0x9c007027
++#define MASK_VSXSEG5EI1024V   0xfc00707f
++#define MATCH_VLXSEG6EI1024V  0xbc007007
++#define MASK_VLXSEG6EI1024V   0xfc00707f
++#define MATCH_VSXSEG6EI1024V  0xbc007027
++#define MASK_VSXSEG6EI1024V   0xfc00707f
++#define MATCH_VLXSEG7EI1024V  0xdc007007
++#define MASK_VLXSEG7EI1024V   0xfc00707f
++#define MATCH_VSXSEG7EI1024V  0xdc007027
++#define MASK_VSXSEG7EI1024V   0xfc00707f
++#define MATCH_VLXSEG8EI1024V  0xfc007007
++#define MASK_VLXSEG8EI1024V   0xfc00707f
++#define MATCH_VSXSEG8EI1024V  0xfc007027
++#define MASK_VSXSEG8EI1024V   0xfc00707f
++
++#define MATCH_VLSEG2E8FFV  0x21000007
++#define MASK_VLSEG2E8FFV   0xfdf0707f
++#define MATCH_VLSEG3E8FFV  0x41000007
++#define MASK_VLSEG3E8FFV   0xfdf0707f
++#define MATCH_VLSEG4E8FFV  0x61000007
++#define MASK_VLSEG4E8FFV   0xfdf0707f
++#define MATCH_VLSEG5E8FFV  0x81000007
++#define MASK_VLSEG5E8FFV   0xfdf0707f
++#define MATCH_VLSEG6E8FFV  0xa1000007
++#define MASK_VLSEG6E8FFV   0xfdf0707f
++#define MATCH_VLSEG7E8FFV  0xc1000007
++#define MASK_VLSEG7E8FFV   0xfdf0707f
++#define MATCH_VLSEG8E8FFV  0xe1000007
++#define MASK_VLSEG8E8FFV   0xfdf0707f
++
++#define MATCH_VLSEG2E16FFV  0x21005007
++#define MASK_VLSEG2E16FFV   0xfdf0707f
++#define MATCH_VLSEG3E16FFV  0x41005007
++#define MASK_VLSEG3E16FFV   0xfdf0707f
++#define MATCH_VLSEG4E16FFV  0x61005007
++#define MASK_VLSEG4E16FFV   0xfdf0707f
++#define MATCH_VLSEG5E16FFV  0x81005007
++#define MASK_VLSEG5E16FFV   0xfdf0707f
++#define MATCH_VLSEG6E16FFV  0xa1005007
++#define MASK_VLSEG6E16FFV   0xfdf0707f
++#define MATCH_VLSEG7E16FFV  0xc1005007
++#define MASK_VLSEG7E16FFV   0xfdf0707f
++#define MATCH_VLSEG8E16FFV  0xe1005007
++#define MASK_VLSEG8E16FFV   0xfdf0707f
++
++#define MATCH_VLSEG2E32FFV  0x21006007
++#define MASK_VLSEG2E32FFV   0xfdf0707f
++#define MATCH_VLSEG3E32FFV  0x41006007
++#define MASK_VLSEG3E32FFV   0xfdf0707f
++#define MATCH_VLSEG4E32FFV  0x61006007
++#define MASK_VLSEG4E32FFV   0xfdf0707f
++#define MATCH_VLSEG5E32FFV  0x81006007
++#define MASK_VLSEG5E32FFV   0xfdf0707f
++#define MATCH_VLSEG6E32FFV  0xa1006007
++#define MASK_VLSEG6E32FFV   0xfdf0707f
++#define MATCH_VLSEG7E32FFV  0xc1006007
++#define MASK_VLSEG7E32FFV   0xfdf0707f
++#define MATCH_VLSEG8E32FFV  0xe1006007
++#define MASK_VLSEG8E32FFV   0xfdf0707f
++
++#define MATCH_VLSEG2E64FFV  0x21007007
++#define MASK_VLSEG2E64FFV   0xfdf0707f
++#define MATCH_VLSEG3E64FFV  0x41007007
++#define MASK_VLSEG3E64FFV   0xfdf0707f
++#define MATCH_VLSEG4E64FFV  0x61007007
++#define MASK_VLSEG4E64FFV   0xfdf0707f
++#define MATCH_VLSEG5E64FFV  0x81007007
++#define MASK_VLSEG5E64FFV   0xfdf0707f
++#define MATCH_VLSEG6E64FFV  0xa1007007
++#define MASK_VLSEG6E64FFV   0xfdf0707f
++#define MATCH_VLSEG7E64FFV  0xc1007007
++#define MASK_VLSEG7E64FFV   0xfdf0707f
++#define MATCH_VLSEG8E64FFV  0xe1007007
++#define MASK_VLSEG8E64FFV   0xfdf0707f
++
++#define MATCH_VLSEG2E128FFV  0x31000007
++#define MASK_VLSEG2E128FFV   0xfdf0707f
++#define MATCH_VLSEG3E128FFV  0x51000007
++#define MASK_VLSEG3E128FFV   0xfdf0707f
++#define MATCH_VLSEG4E128FFV  0x71000007
++#define MASK_VLSEG4E128FFV   0xfdf0707f
++#define MATCH_VLSEG5E128FFV  0x91000007
++#define MASK_VLSEG5E128FFV   0xfdf0707f
++#define MATCH_VLSEG6E128FFV  0xb1000007
++#define MASK_VLSEG6E128FFV   0xfdf0707f
++#define MATCH_VLSEG7E128FFV  0xd1000007
++#define MASK_VLSEG7E128FFV   0xfdf0707f
++#define MATCH_VLSEG8E128FFV  0xf1000007
++#define MASK_VLSEG8E128FFV   0xfdf0707f
++
++#define MATCH_VLSEG2E256FFV  0x31005007
++#define MASK_VLSEG2E256FFV   0xfdf0707f
++#define MATCH_VLSEG3E256FFV  0x51005007
++#define MASK_VLSEG3E256FFV   0xfdf0707f
++#define MATCH_VLSEG4E256FFV  0x71005007
++#define MASK_VLSEG4E256FFV   0xfdf0707f
++#define MATCH_VLSEG5E256FFV  0x91005007
++#define MASK_VLSEG5E256FFV   0xfdf0707f
++#define MATCH_VLSEG6E256FFV  0xb1005007
++#define MASK_VLSEG6E256FFV   0xfdf0707f
++#define MATCH_VLSEG7E256FFV  0xd1005007
++#define MASK_VLSEG7E256FFV   0xfdf0707f
++#define MATCH_VLSEG8E256FFV  0xf1005007
++#define MASK_VLSEG8E256FFV   0xfdf0707f
++
++#define MATCH_VLSEG2E512FFV  0x31006007
++#define MASK_VLSEG2E512FFV   0xfdf0707f
++#define MATCH_VLSEG3E512FFV  0x51006007
++#define MASK_VLSEG3E512FFV   0xfdf0707f
++#define MATCH_VLSEG4E512FFV  0x71006007
++#define MASK_VLSEG4E512FFV   0xfdf0707f
++#define MATCH_VLSEG5E512FFV  0x91006007
++#define MASK_VLSEG5E512FFV   0xfdf0707f
++#define MATCH_VLSEG6E512FFV  0xb1006007
++#define MASK_VLSEG6E512FFV   0xfdf0707f
++#define MATCH_VLSEG7E512FFV  0xd1006007
++#define MASK_VLSEG7E512FFV   0xfdf0707f
++#define MATCH_VLSEG8E512FFV  0xf1006007
++#define MASK_VLSEG8E512FFV   0xfdf0707f
++
++#define MATCH_VLSEG2E1024FFV  0x31007007
++#define MASK_VLSEG2E1024FFV   0xfdf0707f
++#define MATCH_VLSEG3E1024FFV  0x51007007
++#define MASK_VLSEG3E1024FFV   0xfdf0707f
++#define MATCH_VLSEG4E1024FFV  0x71007007
++#define MASK_VLSEG4E1024FFV   0xfdf0707f
++#define MATCH_VLSEG5E1024FFV  0x91007007
++#define MASK_VLSEG5E1024FFV   0xfdf0707f
++#define MATCH_VLSEG6E1024FFV  0xb1007007
++#define MASK_VLSEG6E1024FFV   0xfdf0707f
++#define MATCH_VLSEG7E1024FFV  0xd1007007
++#define MASK_VLSEG7E1024FFV   0xfdf0707f
++#define MATCH_VLSEG8E1024FFV  0xf1007007
++#define MASK_VLSEG8E1024FFV   0xfdf0707f
++
++#define MATCH_VL1RV  0x02800007
++#define MASK_VL1RV   0xfff0707f
++#define MATCH_VS1RV  0x02800027
++#define MASK_VS1RV   0xfff0707f
++
++/* Temporary AMO encoding info
++
++width
++010 AMO*.W
++011 AMO*.D
++100 AMO*.Q
++000 VAMO*EI8.V
++101 VAMO*EI16.V
++110 VAMO*EI32.V
++111 VAMO*EI64.V
++
++amoop
++00001 vamoswap
++00000 vamoadd
++00100 vamoxor
++01100 vamoand
++01000 vamoor
++10000 vamomin
++10100 vamomax
++11000 vamominu
++11100 vamomaxu
++
++   31-27 26 25 24-20 19-15 14-12 11-7    6-0
++   amoop wd vm  vs2   rs1  width vs3/vd  opcode
++   00001 x 1 xxxxx xxxxx 110 xxxxx 0101111
++   0000 1x1x xxxx xxxx x110 xxxx x010 1111
++   1111 1010 0000 0000 0111 0000 0111 1111 */
++
++#define MATCH_VAMOADDEI8V   0x0000002f
++#define MASK_VAMOADDEI8V    0xf800707f
++#define MATCH_VAMOSWAPEI8V  0x0800002f
++#define MASK_VAMOSWAPEI8V   0xf800707f
++#define MATCH_VAMOXOREI8V   0x2000002f
++#define MASK_VAMOXOREI8V    0xf800707f
++#define MATCH_VAMOANDEI8V   0x6000002f
++#define MASK_VAMOANDEI8V    0xf800707f
++#define MATCH_VAMOOREI8V    0x4000002f
++#define MASK_VAMOOREI8V     0xf800707f
++#define MATCH_VAMOMINEI8V   0x8000002f
++#define MASK_VAMOMINEI8V    0xf800707f
++#define MATCH_VAMOMAXEI8V   0xa000002f
++#define MASK_VAMOMAXEI8V    0xf800707f
++#define MATCH_VAMOMINUEI8V  0xc000002f
++#define MASK_VAMOMINUEI8V   0xf800707f
++#define MATCH_VAMOMAXUEI8V  0xe000002f
++#define MASK_VAMOMAXUEI8V   0xf800707f
++
++#define MATCH_VAMOADDEI16V   0x0000502f
++#define MASK_VAMOADDEI16V    0xf800707f
++#define MATCH_VAMOSWAPEI16V  0x0800502f
++#define MASK_VAMOSWAPEI16V   0xf800707f
++#define MATCH_VAMOXOREI16V   0x2000502f
++#define MASK_VAMOXOREI16V    0xf800707f
++#define MATCH_VAMOANDEI16V   0x6000502f
++#define MASK_VAMOANDEI16V    0xf800707f
++#define MATCH_VAMOOREI16V    0x4000502f
++#define MASK_VAMOOREI16V     0xf800707f
++#define MATCH_VAMOMINEI16V   0x8000502f
++#define MASK_VAMOMINEI16V    0xf800707f
++#define MATCH_VAMOMAXEI16V   0xa000502f
++#define MASK_VAMOMAXEI16V    0xf800707f
++#define MATCH_VAMOMINUEI16V  0xc000502f
++#define MASK_VAMOMINUEI16V   0xf800707f
++#define MATCH_VAMOMAXUEI16V  0xe000502f
++#define MASK_VAMOMAXUEI16V   0xf800707f
++
++#define MATCH_VAMOADDEI32V   0x0000602f
++#define MASK_VAMOADDEI32V    0xf800707f
++#define MATCH_VAMOSWAPEI32V  0x0800602f
++#define MASK_VAMOSWAPEI32V   0xf800707f
++#define MATCH_VAMOXOREI32V   0x2000602f
++#define MASK_VAMOXOREI32V    0xf800707f
++#define MATCH_VAMOANDEI32V   0x6000602f
++#define MASK_VAMOANDEI32V    0xf800707f
++#define MATCH_VAMOOREI32V    0x4000602f
++#define MASK_VAMOOREI32V     0xf800707f
++#define MATCH_VAMOMINEI32V   0x8000602f
++#define MASK_VAMOMINEI32V    0xf800707f
++#define MATCH_VAMOMAXEI32V   0xa000602f
++#define MASK_VAMOMAXEI32V    0xf800707f
++#define MATCH_VAMOMINUEI32V  0xc000602f
++#define MASK_VAMOMINUEI32V   0xf800707f
++#define MATCH_VAMOMAXUEI32V  0xe000602f
++#define MASK_VAMOMAXUEI32V   0xf800707f
++
++#define MATCH_VAMOADDEI64V   0x0000702f
++#define MASK_VAMOADDEI64V    0xf800707f
++#define MATCH_VAMOSWAPEI64V  0x0800702f
++#define MASK_VAMOSWAPEI64V   0xf800707f
++#define MATCH_VAMOXOREI64V   0x2000702f
++#define MASK_VAMOXOREI64V    0xf800707f
++#define MATCH_VAMOANDEI64V   0x6000702f
++#define MASK_VAMOANDEI64V    0xf800707f
++#define MATCH_VAMOOREI64V    0x4000702f
++#define MASK_VAMOOREI64V     0xf800707f
++#define MATCH_VAMOMINEI64V   0x8000702f
++#define MASK_VAMOMINEI64V    0xf800707f
++#define MATCH_VAMOMAXEI64V   0xa000702f
++#define MASK_VAMOMAXEI64V    0xf800707f
++#define MATCH_VAMOMINUEI64V  0xc000702f
++#define MASK_VAMOMINUEI64V   0xf800707f
++#define MATCH_VAMOMAXUEI64V  0xe000702f
++#define MASK_VAMOMAXUEI64V   0xf800707f
++
++/* Temporary ALU encoding info
++
++funct3
++000 OPIVV vv
++001 OPFVV vv
++010 OPMVV vv
++011 OPIVI vi  simm[4:0]
++100 OPIVX vx  GPR x-reg rs1
++101 OPFVF vf  FP f-reg rs1
++110 OPMVX vx  GPR x-reg rs1
++111 OPCFG si  GPR x-reg rs1 & rs2/imm
++
++INT OPI
++funct6
++000000 vadd
++000001
++000010 vsub
++000011 vrsub
++000100 vminu
++000101 vmin
++000110 vmaxu
++000111 vmax
++001000
++001001 vand
++001010 vor
++001011 vxor
++001100 vrgather
++001101
++001110 vslideup
++001111 vslidedown
++010000 vadc
++010001 vmadc
++010010 vsbc
++010011 vmsbc
++010100
++010101
++010110
++010111 vmerge/vmv
++011000 vmseq
++011001 vmsne
++011010 vmsltu
++011011 vmslt
++011100 vmsleu
++011101 vmsle
++011110 vmsgtu
++011111 vmsgt
++100000 vsaddu
++100001 vsadd
++100010 vssubu
++100011 vssub
++100100
++100101 vsll
++100110
++100111 vmv<nf>r (nf = 1, 2, 4, 8)
++101000 vsrl
++101001 vsra
++101010 vssrl
++101011 vssra
++101100 vnsrl
++101101 vnsra
++101110 vnclipu
++101111 vnclip
++110000 vwredsumu
++110001 vwredsum
++110010
++110011
++110100
++110101
++110110
++110111
++111000 vdotu **
++111001 vdot **
++111010
++111011
++111100 vqmaccu
++111101 vqmacc
++111110 vqmaccus
++111111 vqmaccsu
++
++INT OPM
++funct6
++000000 vredsum
++000001 vredand
++000010 vredor
++000011 vredxor
++000100 vredminu
++000101 vredmin
++000110 vredmaxu
++000111 vredmax
++001000 vaaddu
++001001 vaadd
++001010 vasubu
++001011 vasub
++001100
++001101
++001110 vslide1up
++001111 vslide1down
++010000 VRXUNARY0/VWXUNARY0
++010001
++010010 VXUNARY0
++010011
++010100 VMUNARY0
++010101
++010110
++010111 vcompress
++011000 vmandnot
++011001 vmand
++011010 vmor
++011011 vmxor
++011100 vmornot
++011101 vmnand
++011110 vmnor
++011111 vmxnor
++100000 vdivu
++100001 vdiv
++100010 vremu
++100011 vrem
++100100 vmulhu
++100101 vmul
++100110 vmulhsu
++100111 vmulh
++101000
++101001 vmadd
++101010
++101011 vnmsub
++101100
++101101 vmacc
++101110
++101111 vnmsac
++110000 vwaddu
++110001 vwadd
++110010 vwsubu
++110011 vwsub
++110100 vwaddu.w
++110101 vwadd.w
++110110 vwsubu.w
++110111 vwsub.w
++111000 vwmulu
++111001
++111010 vwmulsu
++111011 vwmul
++111100 vwmaccu
++111101 vwmacc
++111110 vwmaccus
++111111 vwmaccsu
++
++VRXUNARY0
++vs2, funct3=X
++00000 vmv.s.x
++
++VWXUNARY0
++vs1, funct3=V
++00000 vmv.x.s
++10000 vpopc
++10001 vfirst
++
++VXUNARY0
++vs1, funct3=V
++00010 vzext.vf8
++00011 vsext.vf8
++00100 vzext.vf4
++00101 vsext.vf4
++00110 vzext.vf2
++00111 vsext.vf2
++
++VMUNARY0
++rs1
++00001 vmsbf
++00010 vmsof
++00011 vmsif
++10000 viota
++10001 vid
++
++VFLOAT
++funct6
++000000 vfadd
++000001 vfredsum
++000010 vfsub
++000011 vfredosum
++000100 vfmin
++000101 vfredmin
++000110 vfmax
++000111 vfredmax
++001000 vfsgnj
++001001 vfsgnn
++001010 vfsgnx
++001011
++001100
++001101
++001110 vfslide1up
++001111 vfslide1down
++010000 VRFUNARY0/VWFUNARY0
++010001
++010010 VFUNARY0
++010011 VFUNARY1
++010100
++010101
++010110
++010111 vfmerge/vfmv
++011000 vmfeq
++011001 vmfle
++011010
++011011 vmflt
++011100 vmfne
++011101 vmfgt
++011110
++011111 vmfge
++100000 vfdiv
++100001 vfrdiv
++100010
++100011
++100100 vfmul
++100101
++100110
++100111 vfrsub
++101000 vfmadd
++101001 vfnmadd
++101010 vfmsub
++101011 vfnmsub
++101100 vfmacc
++101101 vfnmacc
++101110 vfmsac
++101111 vfnmsac
++110000 vfwadd
++110001 vfwredsum
++110010 vfwsub
++110011 vfwredosum
++110100 vfwadd.w
++110101
++110110 vfwsub.w
++110111
++111000 vfwmul
++111001 vfdot
++111010
++111011
++111100 vfwmacc
++111101 vfwnmacc
++111110 vfwmsac
++111111 vfwnmsac
++
++VRFUNARY0
++vs2, funct3=F
++00000 vfmv.s.f
++
++VWFUNARY0
++vs1, funct3=V
++00000 vfmv.f.s
++
++VFUNARY0
++vs1
++00000 vfcvt.xu.f.v
++00001 vfcvt.x.f.v
++00010 vfcvt.f.xu.v
++00011 vfcvt.f.x.v
++00110 vfcvt.rtz.xu.f.v
++00111 vfcvt.rtz.x.f.v
++
++01000 vfwcvt.xu.f.v
++01001 vfwcvt.x.f.v
++01010 vfwcvt.f.xu.v
++01011 vfwcvt.f.x.v
++01100 vfwcvt.f.f.v
++01110 vfwcvt.rtz.xu.f.v
++01111 vfwcvt.rtz.x.f.v
++
++10000 vfncvt.xu.f.w
++10001 vfncvt.x.f.w
++10010 vfncvt.f.xu.w
++10011 vfncvt.f.x.w
++10100 vfncvt.f.f.w
++10101 vfncvt.rod.f.f.w
++10110 vfncvt.rtz.xu.f.v
++10111 vfncvt.rtz.x.f.v
++
++VFUNARY1
++vs1
++00000 vfsqrt.v
++10000 vfclass.v
++
++31-26 25 24-20   19-15     14-12 11-7 6-0
++funct6 VM  VS2  VS1/RS1/IMM funct3 VD   opcode
++010000 x xxxxx 00000 001 xxxxx 1010111
++0100 00xx xxxx 0000 0001 xxxx x101 0111
++*/
++
++#define MATCH_VADDVV  0x00000057
++#define MASK_VADDVV   0xfc00707f
++#define MATCH_VADDVX  0x00004057
++#define MASK_VADDVX   0xfc00707f
++#define MATCH_VADDVI  0x00003057
++#define MASK_VADDVI   0xfc00707f
++#define MATCH_VSUBVV  0x08000057
++#define MASK_VSUBVV   0xfc00707f
++#define MATCH_VSUBVX  0x08004057
++#define MASK_VSUBVX   0xfc00707f
++#define MATCH_VRSUBVX 0x0c004057
++#define MASK_VRSUBVX  0xfc00707f
++#define MATCH_VRSUBVI 0x0c003057
++#define MASK_VRSUBVI  0xfc00707f
++
++#define MATCH_VWCVTXXV  0xc4006057
++#define MASK_VWCVTXXV   0xfc0ff07f
++#define MATCH_VWCVTUXXV 0xc0006057
++#define MASK_VWCVTUXXV  0xfc0ff07f
++
++#define MATCH_VWADDVV  0xc4002057
++#define MASK_VWADDVV   0xfc00707f
++#define MATCH_VWADDVX  0xc4006057
++#define MASK_VWADDVX   0xfc00707f
++#define MATCH_VWSUBVV  0xcc002057
++#define MASK_VWSUBVV   0xfc00707f
++#define MATCH_VWSUBVX  0xcc006057
++#define MASK_VWSUBVX   0xfc00707f
++#define MATCH_VWADDWV  0xd4002057
++#define MASK_VWADDWV   0xfc00707f
++#define MATCH_VWADDWX  0xd4006057
++#define MASK_VWADDWX   0xfc00707f
++#define MATCH_VWSUBWV  0xdc002057
++#define MASK_VWSUBWV   0xfc00707f
++#define MATCH_VWSUBWX  0xdc006057
++#define MASK_VWSUBWX   0xfc00707f
++#define MATCH_VWADDUVV  0xc0002057
++#define MASK_VWADDUVV   0xfc00707f
++#define MATCH_VWADDUVX  0xc0006057
++#define MASK_VWADDUVX   0xfc00707f
++#define MATCH_VWSUBUVV  0xc8002057
++#define MASK_VWSUBUVV   0xfc00707f
++#define MATCH_VWSUBUVX  0xc8006057
++#define MASK_VWSUBUVX   0xfc00707f
++#define MATCH_VWADDUWV  0xd0002057
++#define MASK_VWADDUWV   0xfc00707f
++#define MATCH_VWADDUWX  0xd0006057
++#define MASK_VWADDUWX   0xfc00707f
++#define MATCH_VWSUBUWV  0xd8002057
++#define MASK_VWSUBUWV   0xfc00707f
++#define MATCH_VWSUBUWX  0xd8006057
++#define MASK_VWSUBUWX   0xfc00707f
++
++#define MATCH_VZEXT_VF8 0x48012057
++#define MASK_VZEXT_VF8  0xfc0ff07f
++#define MATCH_VSEXT_VF8 0x4801a057
++#define MASK_VSEXT_VF8  0xfc0ff07f
++#define MATCH_VZEXT_VF4 0x48022057
++#define MASK_VZEXT_VF4  0xfc0ff07f
++#define MATCH_VSEXT_VF4 0x4802a057
++#define MASK_VSEXT_VF4  0xfc0ff07f
++#define MATCH_VZEXT_VF2 0x48032057
++#define MASK_VZEXT_VF2  0xfc0ff07f
++#define MATCH_VSEXT_VF2 0x4803a057
++#define MASK_VSEXT_VF2  0xfc0ff07f
++
++#define MATCH_VADCVVM  0x40000057
++#define MASK_VADCVVM   0xfe00707f
++#define MATCH_VADCVXM  0x40004057
++#define MASK_VADCVXM   0xfe00707f
++#define MATCH_VADCVIM  0x40003057
++#define MASK_VADCVIM   0xfe00707f
++#define MATCH_VMADCVVM 0x44000057
++#define MASK_VMADCVVM  0xfe00707f
++#define MATCH_VMADCVXM 0x44004057
++#define MASK_VMADCVXM  0xfe00707f
++#define MATCH_VMADCVIM 0x44003057
++#define MASK_VMADCVIM  0xfe00707f
++#define MATCH_VMADCVV  0x46000057
++#define MASK_VMADCVV   0xfe00707f
++#define MATCH_VMADCVX  0x46004057
++#define MASK_VMADCVX   0xfe00707f
++#define MATCH_VMADCVI  0x46003057
++#define MASK_VMADCVI   0xfe00707f
++#define MATCH_VSBCVVM  0x48000057
++#define MASK_VSBCVVM   0xfe00707f
++#define MATCH_VSBCVXM  0x48004057
++#define MASK_VSBCVXM   0xfe00707f
++#define MATCH_VMSBCVVM 0x4c000057
++#define MASK_VMSBCVVM  0xfe00707f
++#define MATCH_VMSBCVXM 0x4c004057
++#define MASK_VMSBCVXM  0xfe00707f
++#define MATCH_VMSBCVV  0x4e000057
++#define MASK_VMSBCVV   0xfe00707f
++#define MATCH_VMSBCVX  0x4e004057
++#define MASK_VMSBCVX   0xfe00707f
++
++#define MATCH_VNOTV   0x2c0fb057
++#define MASK_VNOTV    0xfc0ff07f
++
++#define MATCH_VANDVV  0x24000057
++#define MASK_VANDVV   0xfc00707f
++#define MATCH_VANDVX  0x24004057
++#define MASK_VANDVX   0xfc00707f
++#define MATCH_VANDVI  0x24003057
++#define MASK_VANDVI   0xfc00707f
++#define MATCH_VORVV   0x28000057
++#define MASK_VORVV    0xfc00707f
++#define MATCH_VORVX   0x28004057
++#define MASK_VORVX    0xfc00707f
++#define MATCH_VORVI   0x28003057
++#define MASK_VORVI    0xfc00707f
++#define MATCH_VXORVV  0x2c000057
++#define MASK_VXORVV   0xfc00707f
++#define MATCH_VXORVX  0x2c004057
++#define MASK_VXORVX   0xfc00707f
++#define MATCH_VXORVI  0x2c003057
++#define MASK_VXORVI   0xfc00707f
++
++#define MATCH_VSLLVV 0x94000057
++#define MASK_VSLLVV  0xfc00707f
++#define MATCH_VSLLVX 0x94004057
++#define MASK_VSLLVX  0xfc00707f
++#define MATCH_VSLLVI 0x94003057
++#define MASK_VSLLVI  0xfc00707f
++#define MATCH_VSRLVV 0xa0000057
++#define MASK_VSRLVV  0xfc00707f
++#define MATCH_VSRLVX 0xa0004057
++#define MASK_VSRLVX  0xfc00707f
++#define MATCH_VSRLVI 0xa0003057
++#define MASK_VSRLVI  0xfc00707f
++#define MATCH_VSRAVV 0xa4000057
++#define MASK_VSRAVV  0xfc00707f
++#define MATCH_VSRAVX 0xa4004057
++#define MASK_VSRAVX  0xfc00707f
++#define MATCH_VSRAVI 0xa4003057
++#define MASK_VSRAVI  0xfc00707f
++
++#define MATCH_VNSRLWV  0xb0000057
++#define MASK_VNSRLWV   0xfc00707f
++#define MATCH_VNSRLWX  0xb0004057
++#define MASK_VNSRLWX   0xfc00707f
++#define MATCH_VNSRLWI  0xb0003057
++#define MASK_VNSRLWI   0xfc00707f
++#define MATCH_VNSRAWV  0xb4000057
++#define MASK_VNSRAWV   0xfc00707f
++#define MATCH_VNSRAWX  0xb4004057
++#define MASK_VNSRAWX   0xfc00707f
++#define MATCH_VNSRAWI  0xb4003057
++#define MASK_VNSRAWI   0xfc00707f
++
++#define MATCH_VMSEQVV  0x60000057
++#define MASK_VMSEQVV   0xfc00707f
++#define MATCH_VMSEQVX  0x60004057
++#define MASK_VMSEQVX   0xfc00707f
++#define MATCH_VMSEQVI  0x60003057
++#define MASK_VMSEQVI   0xfc00707f
++#define MATCH_VMSNEVV  0x64000057
++#define MASK_VMSNEVV   0xfc00707f
++#define MATCH_VMSNEVX  0x64004057
++#define MASK_VMSNEVX   0xfc00707f
++#define MATCH_VMSNEVI  0x64003057
++#define MASK_VMSNEVI   0xfc00707f
++#define MATCH_VMSLTVV  0x6c000057
++#define MASK_VMSLTVV   0xfc00707f
++#define MATCH_VMSLTVX  0x6c004057
++#define MASK_VMSLTVX   0xfc00707f
++#define MATCH_VMSLTUVV 0x68000057
++#define MASK_VMSLTUVV  0xfc00707f
++#define MATCH_VMSLTUVX 0x68004057
++#define MASK_VMSLTUVX  0xfc00707f
++#define MATCH_VMSLEVV  0x74000057
++#define MASK_VMSLEVV   0xfc00707f
++#define MATCH_VMSLEVX  0x74004057
++#define MASK_VMSLEVX   0xfc00707f
++#define MATCH_VMSLEVI  0x74003057
++#define MASK_VMSLEVI   0xfc00707f
++#define MATCH_VMSLEUVV 0x70000057
++#define MASK_VMSLEUVV  0xfc00707f
++#define MATCH_VMSLEUVX 0x70004057
++#define MASK_VMSLEUVX  0xfc00707f
++#define MATCH_VMSLEUVI 0x70003057
++#define MASK_VMSLEUVI  0xfc00707f
++#define MATCH_VMSGTVX  0x7c004057
++#define MASK_VMSGTVX   0xfc00707f
++#define MATCH_VMSGTVI  0x7c003057
++#define MASK_VMSGTVI   0xfc00707f
++#define MATCH_VMSGTUVX 0x78004057
++#define MASK_VMSGTUVX  0xfc00707f
++#define MATCH_VMSGTUVI 0x78003057
++#define MASK_VMSGTUVI  0xfc00707f
++
++#define MATCH_VMINVV  0x14000057
++#define MASK_VMINVV   0xfc00707f
++#define MATCH_VMINVX  0x14004057
++#define MASK_VMINVX   0xfc00707f
++#define MATCH_VMAXVV  0x1c000057
++#define MASK_VMAXVV   0xfc00707f
++#define MATCH_VMAXVX  0x1c004057
++#define MASK_VMAXVX   0xfc00707f
++#define MATCH_VMINUVV 0x10000057
++#define MASK_VMINUVV  0xfc00707f
++#define MATCH_VMINUVX 0x10004057
++#define MASK_VMINUVX  0xfc00707f
++#define MATCH_VMAXUVV 0x18000057
++#define MASK_VMAXUVV  0xfc00707f
++#define MATCH_VMAXUVX 0x18004057
++#define MASK_VMAXUVX  0xfc00707f
++
++#define MATCH_VMULVV    0x94002057
++#define MASK_VMULVV     0xfc00707f
++#define MATCH_VMULVX    0x94006057
++#define MASK_VMULVX     0xfc00707f
++#define MATCH_VMULHVV   0x9c002057
++#define MASK_VMULHVV    0xfc00707f
++#define MATCH_VMULHVX   0x9c006057
++#define MASK_VMULHVX    0xfc00707f
++#define MATCH_VMULHUVV  0x90002057
++#define MASK_VMULHUVV   0xfc00707f
++#define MATCH_VMULHUVX  0x90006057
++#define MASK_VMULHUVX   0xfc00707f
++#define MATCH_VMULHSUVV 0x98002057
++#define MASK_VMULHSUVV  0xfc00707f
++#define MATCH_VMULHSUVX 0x98006057
++#define MASK_VMULHSUVX  0xfc00707f
++
++#define MATCH_VWMULVV   0xec002057
++#define MASK_VWMULVV    0xfc00707f
++#define MATCH_VWMULVX   0xec006057
++#define MASK_VWMULVX    0xfc00707f
++#define MATCH_VWMULUVV  0xe0002057
++#define MASK_VWMULUVV   0xfc00707f
++#define MATCH_VWMULUVX  0xe0006057
++#define MASK_VWMULUVX   0xfc00707f
++#define MATCH_VWMULSUVV 0xe8002057
++#define MASK_VWMULSUVV  0xfc00707f
++#define MATCH_VWMULSUVX 0xe8006057
++#define MASK_VWMULSUVX  0xfc00707f
++
++#define MATCH_VMACCVV  0xb4002057
++#define MASK_VMACCVV   0xfc00707f
++#define MATCH_VMACCVX  0xb4006057
++#define MASK_VMACCVX   0xfc00707f
++#define MATCH_VNMSACVV 0xbc002057
++#define MASK_VNMSACVV  0xfc00707f
++#define MATCH_VNMSACVX 0xbc006057
++#define MASK_VNMSACVX  0xfc00707f
++#define MATCH_VMADDVV  0xa4002057
++#define MASK_VMADDVV   0xfc00707f
++#define MATCH_VMADDVX  0xa4006057
++#define MASK_VMADDVX   0xfc00707f
++#define MATCH_VNMSUBVV 0xac002057
++#define MASK_VNMSUBVV  0xfc00707f
++#define MATCH_VNMSUBVX 0xac006057
++#define MASK_VNMSUBVX  0xfc00707f
++
++#define MATCH_VWMACCUVV  0xf0002057
++#define MASK_VWMACCUVV   0xfc00707f
++#define MATCH_VWMACCUVX  0xf0006057
++#define MASK_VWMACCUVX   0xfc00707f
++#define MATCH_VWMACCVV   0xf4002057
++#define MASK_VWMACCVV    0xfc00707f
++#define MATCH_VWMACCVX   0xf4006057
++#define MASK_VWMACCVX    0xfc00707f
++#define MATCH_VWMACCSUVV 0xfc002057
++#define MASK_VWMACCSUVV  0xfc00707f
++#define MATCH_VWMACCSUVX 0xfc006057
++#define MASK_VWMACCSUVX  0xfc00707f
++#define MATCH_VWMACCUSVX 0xf8006057
++#define MASK_VWMACCUSVX  0xfc00707f
++
++#define MATCH_VQMACCUVV  0xf0000057
++#define MASK_VQMACCUVV   0xfc00707f
++#define MATCH_VQMACCUVX  0xf0004057
++#define MASK_VQMACCUVX   0xfc00707f
++#define MATCH_VQMACCVV   0xf4000057
++#define MASK_VQMACCVV    0xfc00707f
++#define MATCH_VQMACCVX   0xf4004057
++#define MASK_VQMACCVX    0xfc00707f
++#define MATCH_VQMACCSUVV 0xfc000057
++#define MASK_VQMACCSUVV  0xfc00707f
++#define MATCH_VQMACCSUVX 0xfc004057
++#define MASK_VQMACCSUVX  0xfc00707f
++#define MATCH_VQMACCUSVX 0xf8004057
++#define MASK_VQMACCUSVX  0xfc00707f
++
++#define MATCH_VDIVVV  0x84002057
++#define MASK_VDIVVV   0xfc00707f
++#define MATCH_VDIVVX  0x84006057
++#define MASK_VDIVVX   0xfc00707f
++#define MATCH_VDIVUVV 0x80002057
++#define MASK_VDIVUVV  0xfc00707f
++#define MATCH_VDIVUVX 0x80006057
++#define MASK_VDIVUVX  0xfc00707f
++#define MATCH_VREMVV  0x8c002057
++#define MASK_VREMVV   0xfc00707f
++#define MATCH_VREMVX  0x8c006057
++#define MASK_VREMVX   0xfc00707f
++#define MATCH_VREMUVV 0x88002057
++#define MASK_VREMUVV  0xfc00707f
++#define MATCH_VREMUVX 0x88006057
++#define MASK_VREMUVX  0xfc00707f
++
++#define MATCH_VMERGEVVM 0x5c000057
++#define MASK_VMERGEVVM  0xfe00707f
++#define MATCH_VMERGEVXM 0x5c004057
++#define MASK_VMERGEVXM  0xfe00707f
++#define MATCH_VMERGEVIM 0x5c003057
++#define MASK_VMERGEVIM  0xfe00707f
++
++#define MATCH_VMVVV    0x5e000057
++#define MASK_VMVVV     0xfff0707f
++#define MATCH_VMVVX    0x5e004057
++#define MASK_VMVVX     0xfff0707f
++#define MATCH_VMVVI    0x5e003057
++#define MASK_VMVVI     0xfff0707f
++
++#define MATCH_VSADDUVV 0x80000057
++#define MASK_VSADDUVV  0xfc00707f
++#define MATCH_VSADDUVX 0x80004057
++#define MASK_VSADDUVX  0xfc00707f
++#define MATCH_VSADDUVI 0x80003057
++#define MASK_VSADDUVI  0xfc00707f
++#define MATCH_VSADDVV  0x84000057
++#define MASK_VSADDVV   0xfc00707f
++#define MATCH_VSADDVX  0x84004057
++#define MASK_VSADDVX   0xfc00707f
++#define MATCH_VSADDVI  0x84003057
++#define MASK_VSADDVI   0xfc00707f
++#define MATCH_VSSUBUVV 0x88000057
++#define MASK_VSSUBUVV  0xfc00707f
++#define MATCH_VSSUBUVX 0x88004057
++#define MASK_VSSUBUVX  0xfc00707f
++#define MATCH_VSSUBVV  0x8c000057
++#define MASK_VSSUBVV   0xfc00707f
++#define MATCH_VSSUBVX  0x8c004057
++#define MASK_VSSUBVX   0xfc00707f
++
++#define MATCH_VAADDUVV 0x20002057
++#define MASK_VAADDUVV  0xfc00707f
++#define MATCH_VAADDUVX 0x20006057
++#define MASK_VAADDUVX  0xfc00707f
++#define MATCH_VAADDVV  0x24002057
++#define MASK_VAADDVV   0xfc00707f
++#define MATCH_VAADDVX  0x24006057
++#define MASK_VAADDVX   0xfc00707f
++#define MATCH_VASUBUVV 0x28002057
++#define MASK_VASUBUVV  0xfc00707f
++#define MATCH_VASUBUVX 0x28006057
++#define MASK_VASUBUVX  0xfc00707f
++#define MATCH_VASUBVV  0x2c002057
++#define MASK_VASUBVV   0xfc00707f
++#define MATCH_VASUBVX  0x2c006057
++#define MASK_VASUBVX   0xfc00707f
++
++#define MATCH_VSMULVV  0x9c000057
++#define MASK_VSMULVV   0xfc00707f
++#define MATCH_VSMULVX  0x9c004057
++#define MASK_VSMULVX   0xfc00707f
++
++#define MATCH_VSSRLVV   0xa8000057
++#define MASK_VSSRLVV    0xfc00707f
++#define MATCH_VSSRLVX   0xa8004057
++#define MASK_VSSRLVX    0xfc00707f
++#define MATCH_VSSRLVI   0xa8003057
++#define MASK_VSSRLVI    0xfc00707f
++#define MATCH_VSSRAVV   0xac000057
++#define MASK_VSSRAVV    0xfc00707f
++#define MATCH_VSSRAVX   0xac004057
++#define MASK_VSSRAVX    0xfc00707f
++#define MATCH_VSSRAVI   0xac003057
++#define MASK_VSSRAVI    0xfc00707f
++
++#define MATCH_VNCLIPUWV 0xb8000057
++#define MASK_VNCLIPUWV  0xfc00707f
++#define MATCH_VNCLIPUWX 0xb8004057
++#define MASK_VNCLIPUWX  0xfc00707f
++#define MATCH_VNCLIPUWI 0xb8003057
++#define MASK_VNCLIPUWI  0xfc00707f
++#define MATCH_VNCLIPWV  0xbc000057
++#define MASK_VNCLIPWV   0xfc00707f
++#define MATCH_VNCLIPWX  0xbc004057
++#define MASK_VNCLIPWX   0xfc00707f
++#define MATCH_VNCLIPWI  0xbc003057
++#define MASK_VNCLIPWI   0xfc00707f
++
++#define MATCH_VFADDVV  0x00001057
++#define MASK_VFADDVV   0xfc00707f
++#define MATCH_VFADDVF  0x00005057
++#define MASK_VFADDVF   0xfc00707f
++#define MATCH_VFSUBVV  0x08001057
++#define MASK_VFSUBVV   0xfc00707f
++#define MATCH_VFSUBVF  0x08005057
++#define MASK_VFSUBVF   0xfc00707f
++#define MATCH_VFRSUBVF 0x9c005057
++#define MASK_VFRSUBVF  0xfc00707f
++
++#define MATCH_VFWADDVV  0xc0001057
++#define MASK_VFWADDVV   0xfc00707f
++#define MATCH_VFWADDVF  0xc0005057
++#define MASK_VFWADDVF   0xfc00707f
++#define MATCH_VFWSUBVV  0xc8001057
++#define MASK_VFWSUBVV   0xfc00707f
++#define MATCH_VFWSUBVF  0xc8005057
++#define MASK_VFWSUBVF   0xfc00707f
++#define MATCH_VFWADDWV  0xd0001057
++#define MASK_VFWADDWV   0xfc00707f
++#define MATCH_VFWADDWF  0xd0005057
++#define MASK_VFWADDWF   0xfc00707f
++#define MATCH_VFWSUBWV  0xd8001057
++#define MASK_VFWSUBWV   0xfc00707f
++#define MATCH_VFWSUBWF  0xd8005057
++#define MASK_VFWSUBWF   0xfc00707f
++
++#define MATCH_VFMULVV  0x90001057
++#define MASK_VFMULVV   0xfc00707f
++#define MATCH_VFMULVF  0x90005057
++#define MASK_VFMULVF   0xfc00707f
++#define MATCH_VFDIVVV  0x80001057
++#define MASK_VFDIVVV   0xfc00707f
++#define MATCH_VFDIVVF  0x80005057
++#define MASK_VFDIVVF   0xfc00707f
++#define MATCH_VFRDIVVF 0x84005057
++#define MASK_VFRDIVVF  0xfc00707f
++
++#define MATCH_VFWMULVV 0xe0001057
++#define MASK_VFWMULVV  0xfc00707f
++#define MATCH_VFWMULVF 0xe0005057
++#define MASK_VFWMULVF  0xfc00707f
++
++#define MATCH_VFMADDVV  0xa0001057
++#define MASK_VFMADDVV   0xfc00707f
++#define MATCH_VFMADDVF  0xa0005057
++#define MASK_VFMADDVF   0xfc00707f
++#define MATCH_VFNMADDVV 0xa4001057
++#define MASK_VFNMADDVV  0xfc00707f
++#define MATCH_VFNMADDVF 0xa4005057
++#define MASK_VFNMADDVF  0xfc00707f
++#define MATCH_VFMSUBVV  0xa8001057
++#define MASK_VFMSUBVV   0xfc00707f
++#define MATCH_VFMSUBVF  0xa8005057
++#define MASK_VFMSUBVF   0xfc00707f
++#define MATCH_VFNMSUBVV 0xac001057
++#define MASK_VFNMSUBVV  0xfc00707f
++#define MATCH_VFNMSUBVF 0xac005057
++#define MASK_VFNMSUBVF  0xfc00707f
++#define MATCH_VFMACCVV  0xb0001057
++#define MASK_VFMACCVV   0xfc00707f
++#define MATCH_VFMACCVF  0xb0005057
++#define MASK_VFMACCVF   0xfc00707f
++#define MATCH_VFNMACCVV 0xb4001057
++#define MASK_VFNMACCVV  0xfc00707f
++#define MATCH_VFNMACCVF 0xb4005057
++#define MASK_VFNMACCVF  0xfc00707f
++#define MATCH_VFMSACVV  0xb8001057
++#define MASK_VFMSACVV   0xfc00707f
++#define MATCH_VFMSACVF  0xb8005057
++#define MASK_VFMSACVF   0xfc00707f
++#define MATCH_VFNMSACVV 0xbc001057
++#define MASK_VFNMSACVV  0xfc00707f
++#define MATCH_VFNMSACVF 0xbc005057
++#define MASK_VFNMSACVF  0xfc00707f
++
++#define MATCH_VFWMACCVV  0xf0001057
++#define MASK_VFWMACCVV   0xfc00707f
++#define MATCH_VFWMACCVF  0xf0005057
++#define MASK_VFWMACCVF   0xfc00707f
++#define MATCH_VFWNMACCVV 0xf4001057
++#define MASK_VFWNMACCVV  0xfc00707f
++#define MATCH_VFWNMACCVF 0xf4005057
++#define MASK_VFWNMACCVF  0xfc00707f
++#define MATCH_VFWMSACVV  0xf8001057
++#define MASK_VFWMSACVV   0xfc00707f
++#define MATCH_VFWMSACVF  0xf8005057
++#define MASK_VFWMSACVF   0xfc00707f
++#define MATCH_VFWNMSACVV 0xfc001057
++#define MASK_VFWNMSACVV  0xfc00707f
++#define MATCH_VFWNMSACVF 0xfc005057
++#define MASK_VFWNMSACVF  0xfc00707f
++
++#define MATCH_VFSQRTV 0x4c001057
++#define MASK_VFSQRTV  0xfc0ff07f
++
++#define MATCH_VFMINVV  0x10001057
++#define MASK_VFMINVV   0xfc00707f
++#define MATCH_VFMINVF  0x10005057
++#define MASK_VFMINVF   0xfc00707f
++#define MATCH_VFMAXVV  0x18001057
++#define MASK_VFMAXVV   0xfc00707f
++#define MATCH_VFMAXVF  0x18005057
++#define MASK_VFMAXVF   0xfc00707f
++
++#define MATCH_VFSGNJVV  0x20001057
++#define MASK_VFSGNJVV   0xfc00707f
++#define MATCH_VFSGNJVF  0x20005057
++#define MASK_VFSGNJVF   0xfc00707f
++#define MATCH_VFSGNJNVV 0x24001057
++#define MASK_VFSGNJNVV  0xfc00707f
++#define MATCH_VFSGNJNVF 0x24005057
++#define MASK_VFSGNJNVF  0xfc00707f
++#define MATCH_VFSGNJXVV 0x28001057
++#define MASK_VFSGNJXVV  0xfc00707f
++#define MATCH_VFSGNJXVF 0x28005057
++#define MASK_VFSGNJXVF  0xfc00707f
++
++#define MATCH_VMFEQVV   0x60001057
++#define MASK_VMFEQVV    0xfc00707f
++#define MATCH_VMFEQVF   0x60005057
++#define MASK_VMFEQVF    0xfc00707f
++#define MATCH_VMFNEVV   0x70001057
++#define MASK_VMFNEVV    0xfc00707f
++#define MATCH_VMFNEVF   0x70005057
++#define MASK_VMFNEVF    0xfc00707f
++#define MATCH_VMFLTVV   0x6c001057
++#define MASK_VMFLTVV    0xfc00707f
++#define MATCH_VMFLTVF   0x6c005057
++#define MASK_VMFLTVF    0xfc00707f
++#define MATCH_VMFLEVV  0x64001057
++#define MASK_VMFLEVV   0xfc00707f
++#define MATCH_VMFLEVF  0x64005057
++#define MASK_VMFLEVF   0xfc00707f
++#define MATCH_VMFGTVF   0x74005057
++#define MASK_VMFGTVF    0xfc00707f
++#define MATCH_VMFGEVF  0x7c005057
++#define MASK_VMFGEVF   0xfc00707f
++
++#define MATCH_VFCLASSV 0x4c081057
++#define MASK_VFCLASSV  0xfc0ff07f
++
++#define MATCH_VFMERGEVFM 0x5c005057
++#define MASK_VFMERGEVFM  0xfe00707f
++#define MATCH_VFMVVF     0x5e005057
++#define MASK_VFMVVF      0xfff0707f
++
++#define MATCH_VFCVTXUFV 0x48001057
++#define MASK_VFCVTXUFV  0xfc0ff07f
++#define MATCH_VFCVTXFV 0x48009057
++#define MASK_VFCVTXFV  0xfc0ff07f
++#define MATCH_VFCVTFXUV 0x48011057
++#define MASK_VFCVTFXUV  0xfc0ff07f
++#define MATCH_VFCVTFXV 0x48019057
++#define MASK_VFCVTFXV  0xfc0ff07f
++#define MATCH_VFCVTRTZXUFV 0x48031057
++#define MASK_VFCVTRTZXUFV  0xfc0ff07f
++#define MATCH_VFCVTRTZXFV 0x48039057
++#define MASK_VFCVTRTZXFV  0xfc0ff07f
++#define MATCH_VFWCVTXUFV 0x48041057
++#define MASK_VFWCVTXUFV  0xfc0ff07f
++#define MATCH_VFWCVTXFV 0x48049057
++#define MASK_VFWCVTXFV  0xfc0ff07f
++#define MATCH_VFWCVTFXUV 0x48051057
++#define MASK_VFWCVTFXUV  0xfc0ff07f
++#define MATCH_VFWCVTFXV 0x48059057
++#define MASK_VFWCVTFXV  0xfc0ff07f
++#define MATCH_VFWCVTFFV 0x48061057
++#define MASK_VFWCVTFFV  0xfc0ff07f
++#define MATCH_VFWCVTRTZXUFV 0x48071057
++#define MASK_VFWCVTRTZXUFV  0xfc0ff07f
++#define MATCH_VFWCVTRTZXFV 0x48079057
++#define MASK_VFWCVTRTZXFV  0xfc0ff07f
++#define MATCH_VFNCVTXUFW 0x48081057
++#define MASK_VFNCVTXUFW  0xfc0ff07f
++#define MATCH_VFNCVTXFW 0x48089057
++#define MASK_VFNCVTXFW  0xfc0ff07f
++#define MATCH_VFNCVTFXUW 0x48091057
++#define MASK_VFNCVTFXUW  0xfc0ff07f
++#define MATCH_VFNCVTFXW 0x48099057
++#define MASK_VFNCVTFXW  0xfc0ff07f
++#define MATCH_VFNCVTFFW 0x480a1057
++#define MASK_VFNCVTFFW  0xfc0ff07f
++#define MATCH_VFNCVTRODFFW 0x480a9057
++#define MASK_VFNCVTRODFFW  0xfc0ff07f
++#define MATCH_VFNCVTRTZXUFW 0x480b1057
++#define MASK_VFNCVTRTZXUFW  0xfc0ff07f
++#define MATCH_VFNCVTRTZXFW 0x480b9057
++#define MASK_VFNCVTRTZXFW  0xfc0ff07f
++
++#define MATCH_VREDSUMVS  0x00002057
++#define MASK_VREDSUMVS   0xfc00707f
++#define MATCH_VREDMAXVS  0x1c002057
++#define MASK_VREDMAXVS   0xfc00707f
++#define MATCH_VREDMAXUVS 0x18002057
++#define MASK_VREDMAXUVS  0xfc00707f
++#define MATCH_VREDMINVS  0x14002057
++#define MASK_VREDMINVS   0xfc00707f
++#define MATCH_VREDMINUVS 0x10002057
++#define MASK_VREDMINUVS  0xfc00707f
++#define MATCH_VREDANDVS  0x04002057
++#define MASK_VREDANDVS   0xfc00707f
++#define MATCH_VREDORVS   0x08002057
++#define MASK_VREDORVS    0xfc00707f
++#define MATCH_VREDXORVS  0x0c002057
++#define MASK_VREDXORVS   0xfc00707f
++
++#define MATCH_VWREDSUMUVS 0xc0000057
++#define MASK_VWREDSUMUVS  0xfc00707f
++#define MATCH_VWREDSUMVS  0xc4000057
++#define MASK_VWREDSUMVS   0xfc00707f
++
++#define MATCH_VFREDOSUMVS 0x0c001057
++#define MASK_VFREDOSUMVS  0xfc00707f
++#define MATCH_VFREDSUMVS  0x04001057
++#define MASK_VFREDSUMVS   0xfc00707f
++#define MATCH_VFREDMAXVS  0x1c001057
++#define MASK_VFREDMAXVS   0xfc00707f
++#define MATCH_VFREDMINVS  0x14001057
++#define MASK_VFREDMINVS   0xfc00707f
++
++#define MATCH_VFWREDOSUMVS 0xcc001057
++#define MASK_VFWREDOSUMVS  0xfc00707f
++#define MATCH_VFWREDSUMVS  0xc4001057
++#define MASK_VFWREDSUMVS   0xfc00707f
++
++#define MATCH_VMANDMM    0x66002057
++#define MASK_VMANDMM     0xfe00707f
++#define MATCH_VMNANDMM   0x76002057
++#define MASK_VMNANDMM    0xfe00707f
++#define MATCH_VMANDNOTMM 0x62002057
++#define MASK_VMANDNOTMM  0xfe00707f
++#define MATCH_VMXORMM    0x6e002057
++#define MASK_VMXORMM     0xfe00707f
++#define MATCH_VMORMM     0x6a002057
++#define MASK_VMORMM      0xfe00707f
++#define MATCH_VMNORMM    0x7a002057
++#define MASK_VMNORMM     0xfe00707f
++#define MATCH_VMORNOTMM  0x72002057
++#define MASK_VMORNOTMM   0xfe00707f
++#define MATCH_VMXNORMM   0x7e002057
++#define MASK_VMXNORMM    0xfe00707f
++
++#define MATCH_VPOPCM   0x40082057
++#define MASK_VPOPCM    0xfc0ff07f
++#define MATCH_VFIRSTM  0x4008a057
++#define MASK_VFIRSTM   0xfc0ff07f
++
++#define MATCH_VMSBFM   0x5000a057
++#define MASK_VMSBFM    0xfc0ff07f
++#define MATCH_VMSIFM   0x5001a057
++#define MASK_VMSIFM    0xfc0ff07f
++#define MATCH_VMSOFM   0x50012057
++#define MASK_VMSOFM    0xfc0ff07f
++#define MATCH_VIOTAM   0x50082057
++#define MASK_VIOTAM    0xfc0ff07f
++#define MATCH_VIDV     0x5008a057
++#define MASK_VIDV      0xfdfff07f
++
++#define MATCH_VMVXS    0x42002057
++#define MASK_VMVXS     0xfe0ff07f
++#define MATCH_VMVSX    0x42006057
++#define MASK_VMVSX     0xfff0707f
++
++#define MATCH_VFMVFS   0x42001057
++#define MASK_VFMVFS    0xfe0ff07f
++#define MATCH_VFMVSF   0x42005057
++#define MASK_VFMVSF    0xfff0707f
++
++#define MATCH_VSLIDEUPVX   0x38004057
++#define MASK_VSLIDEUPVX    0xfc00707f
++#define MATCH_VSLIDEUPVI   0x38003057
++#define MASK_VSLIDEUPVI    0xfc00707f
++#define MATCH_VSLIDEDOWNVX 0x3c004057
++#define MASK_VSLIDEDOWNVX  0xfc00707f
++#define MATCH_VSLIDEDOWNVI 0x3c003057
++#define MASK_VSLIDEDOWNVI  0xfc00707f
++
++#define MATCH_VSLIDE1UPVX   0x38006057
++#define MASK_VSLIDE1UPVX    0xfc00707f
++#define MATCH_VSLIDE1DOWNVX 0x3c006057
++#define MASK_VSLIDE1DOWNVX  0xfc00707f
++
++#define MATCH_VFSLIDE1UPVF   0x38005057
++#define MASK_VFSLIDE1UPVF    0xfc00707f
++#define MATCH_VFSLIDE1DOWNVF 0x3c005057
++#define MASK_VFSLIDE1DOWNVF  0xfc00707f
++
++#define MATCH_VRGATHERVV   0x30000057
++#define MASK_VRGATHERVV    0xfc00707f
++#define MATCH_VRGATHERVX   0x30004057
++#define MASK_VRGATHERVX    0xfc00707f
++#define MATCH_VRGATHERVI   0x30003057
++#define MASK_VRGATHERVI    0xfc00707f
++
++#define MATCH_VCOMPRESSVM   0x5e002057
++#define MASK_VCOMPRESSVM    0xfe00707f
++
++#define MATCH_VMV1RV 0x9e003057
++#define MASK_VMV1RV  0xfe0ff07f
++#define MATCH_VMV2RV 0x9e00b057
++#define MASK_VMV2RV  0xfe0ff07f
++#define MATCH_VMV4RV 0x9e01b057
++#define MASK_VMV4RV  0xfe0ff07f
++#define MATCH_VMV8RV 0x9e03b057
++#define MASK_VMV8RV  0xfe0ff07f
++
++#define MATCH_VDOTVV    0xe4000057
++#define MASK_VDOTVV     0xfc00707f
++#define MATCH_VDOTUVV   0xe0000057
++#define MASK_VDOTUVV    0xfc00707f
++#define MATCH_VFDOTVV   0xe4001057
++#define MASK_VFDOTVV    0xfc00707f
++/* END RVV */
++
+ #define MATCH_CUSTOM0 0xb
+ #define MASK_CUSTOM0  0x707f
+ #define MATCH_CUSTOM0_RS1 0x200b
+@@ -830,6 +2954,13 @@
+ #define CSR_FFLAGS 0x1
+ #define CSR_FRM 0x2
+ #define CSR_FCSR 0x3
++#define CSR_VSTART 0x008
++#define CSR_VXSAT 0x009
++#define CSR_VXRM 0x00a
++#define CSR_VCSR 0x00f
++#define CSR_VL 0xc20
++#define CSR_VTYPE 0xc21
++#define CSR_VLENB 0xc22
+ #define CSR_DCSR 0x7b0
+ #define CSR_DPC 0x7b1
+ #define CSR_DSCRATCH0 0x7b2
+@@ -1365,6 +3496,13 @@ DECLARE_CSR(mhcounteren, CSR_MHCOUNTEREN, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9P1, PR
+ DECLARE_CSR(fflags, CSR_FFLAGS, CSR_CLASS_F, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE)
+ DECLARE_CSR(frm, CSR_FRM, CSR_CLASS_F, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE)
+ DECLARE_CSR(fcsr, CSR_FCSR, CSR_CLASS_F, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE)
++DECLARE_CSR(vstart, CSR_VSTART, CSR_CLASS_V, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE)
++DECLARE_CSR(vxsat, CSR_VXSAT, CSR_CLASS_V, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE)
++DECLARE_CSR(vxrm, CSR_VXRM, CSR_CLASS_V, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE)
++DECLARE_CSR(vcsr, CSR_VCSR, CSR_CLASS_V, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE)
++DECLARE_CSR(vl, CSR_VL, CSR_CLASS_V, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE)
++DECLARE_CSR(vtype, CSR_VTYPE, CSR_CLASS_V, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE)
++DECLARE_CSR(vlenb, CSR_VLENB, CSR_CLASS_V, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE)
+ DECLARE_CSR(dcsr, CSR_DCSR, CSR_CLASS_DEBUG, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE)
+ DECLARE_CSR(dpc, CSR_DPC, CSR_CLASS_DEBUG, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE)
+ DECLARE_CSR(dscratch0, CSR_DSCRATCH0, CSR_CLASS_DEBUG, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE)
+diff --git a/include/opcode/riscv.h b/include/opcode/riscv.h
+index 680780a664..62049bdd23 100644
+--- a/include/opcode/riscv.h
++++ b/include/opcode/riscv.h
+@@ -52,6 +52,34 @@ static const char * const riscv_pred_succ[16] =
+   "i", "iw", "ir", "irw", "io", "iow", "ior", "iorw"
+ };
+ 
++/* List of vsetvli vsew constants.  */
++static const char * const riscv_vsew[8] =
++{
++  "e8", "e16", "e32", "e64", "e128", "e256", "e512", "e1024"
++};
++
++/* List of vsetvli vlmul constants.  */
++static const char * const riscv_vlmul[8] =
++{
++  "m1", "m2", "m4", "m8", 0, "mf8", "mf4", "mf2"
++};
++
++/* List of vsetvli vediv constants.  */
++static const char * const riscv_vediv[4] =
++{
++  "d1", "d2", "d4", "d8"
++};
++
++static const char * const riscv_vta[2] =
++{
++  "tu", "ta"
++};
++
++static const char * const riscv_vma[2] =
++{
++  "mu", "ma"
++};
++
+ #define RVC_JUMP_BITS 11
+ #define RVC_JUMP_REACH ((1ULL << RVC_JUMP_BITS) * RISCV_JUMP_ALIGN)
+ 
+@@ -99,6 +127,14 @@ static const char * const riscv_pred_succ[16] =
+   ((RV_X(x, 3, 2) << 1) | (RV_X(x, 10, 2) << 3) | (RV_X(x, 2, 1) << 5) | (RV_X(x, 5, 2) << 6) | (-RV_X(x, 12, 1) << 8))
+ #define EXTRACT_RVC_J_IMM(x) \
+   ((RV_X(x, 3, 3) << 1) | (RV_X(x, 11, 1) << 4) | (RV_X(x, 2, 1) << 5) | (RV_X(x, 7, 1) << 6) | (RV_X(x, 6, 1) << 7) | (RV_X(x, 9, 2) << 8) | (RV_X(x, 8, 1) << 10) | (-RV_X(x, 12, 1) << 11))
++#define EXTRACT_RVV_VI_IMM(x) \
++  (RV_X(x, 15, 5) | (-RV_X(x, 19, 1) << 5))
++#define EXTRACT_RVV_VI_UIMM(x) \
++  (RV_X(x, 15, 5))
++#define EXTRACT_RVV_OFFSET(x) \
++  (RV_X(x, 29, 3))
++#define EXTRACT_RVV_VC_IMM(x) \
++  (RV_X(x, 20, 11))
+ 
+ #define ENCODE_ITYPE_IMM(x) \
+   (RV_X(x, 0, 12) << 20)
+@@ -138,6 +174,8 @@ static const char * const riscv_pred_succ[16] =
+   ((RV_X(x, 1, 2) << 3) | (RV_X(x, 3, 2) << 10) | (RV_X(x, 5, 1) << 2) | (RV_X(x, 6, 2) << 5) | (RV_X(x, 8, 1) << 12))
+ #define ENCODE_RVC_J_IMM(x) \
+   ((RV_X(x, 1, 3) << 3) | (RV_X(x, 4, 1) << 11) | (RV_X(x, 5, 1) << 2) | (RV_X(x, 6, 1) << 7) | (RV_X(x, 7, 1) << 6) | (RV_X(x, 8, 2) << 9) | (RV_X(x, 10, 1) << 8) | (RV_X(x, 11, 1) << 12))
++#define ENCODE_RVV_VC_IMM(x) \
++  (RV_X(x, 0, 11) << 20)
+ 
+ #define VALID_ITYPE_IMM(x) (EXTRACT_ITYPE_IMM(ENCODE_ITYPE_IMM(x)) == (x))
+ #define VALID_STYPE_IMM(x) (EXTRACT_STYPE_IMM(ENCODE_STYPE_IMM(x)) == (x))
+@@ -158,6 +196,7 @@ static const char * const riscv_pred_succ[16] =
+ #define VALID_RVC_SDSP_IMM(x) (EXTRACT_RVC_SDSP_IMM(ENCODE_RVC_SDSP_IMM(x)) == (x))
+ #define VALID_RVC_B_IMM(x) (EXTRACT_RVC_B_IMM(ENCODE_RVC_B_IMM(x)) == (x))
+ #define VALID_RVC_J_IMM(x) (EXTRACT_RVC_J_IMM(ENCODE_RVC_J_IMM(x)) == (x))
++#define VALID_RVV_VC_IMM(x) (EXTRACT_RVV_VC_IMM(ENCODE_RVV_VC_IMM(x)) == (x))
+ 
+ #define RISCV_RTYPE(insn, rd, rs1, rs2) \
+   ((MATCH_ ## insn) | ((rd) << OP_SH_RD) | ((rs1) << OP_SH_RS1) | ((rs2) << OP_SH_RS2))
+@@ -256,6 +295,37 @@ static const char * const riscv_pred_succ[16] =
+ #define OP_MASK_CFUNCT2                0x3
+ #define OP_SH_CFUNCT2          5
+ 
++/* RVV fields.  */
++
++#define OP_MASK_VD		0x1f
++#define OP_SH_VD		7
++#define OP_MASK_VS1		0x1f
++#define OP_SH_VS1		15
++#define OP_MASK_VS2		0x1f
++#define OP_SH_VS2		20
++#define OP_MASK_VIMM		0x1f
++#define OP_SH_VIMM		15
++#define OP_MASK_VMASK		0x1
++#define OP_SH_VMASK		25
++#define OP_MASK_VFUNCT6		0x3f
++#define OP_SH_VFUNCT6		26
++
++#define OP_MASK_VLMUL		0x23
++#define OP_SH_VLMUL		0
++#define OP_MASK_VSEW		0x7
++#define OP_SH_VSEW		2
++#define OP_MASK_VEDIV		0x3
++#define OP_SH_VEDIV		8
++#define OP_MASK_VTYPE_RES	0x1
++#define OP_SH_VTYPE_RES		10
++#define OP_MASK_VTA		0x1
++#define OP_SH_VTA		6
++#define OP_MASK_VMA		0x1
++#define OP_SH_VMA		7
++
++#define OP_MASK_VWD		0x1
++#define OP_SH_VWD		26
++
+ /* ABI names for selected x-registers.  */
+ 
+ #define X_RA 1
+@@ -269,6 +339,8 @@ static const char * const riscv_pred_succ[16] =
+ 
+ #define NGPR 32
+ #define NFPR 32
++#define NVECR 32
++#define NVECM 1
+ 
+ /* These fake label defines are use by both the assembler, and
+    libopcodes.  The assembler uses this when it needs to generate a fake
+@@ -282,6 +354,10 @@ static const char * const riscv_pred_succ[16] =
+   (STRUCT) = (((STRUCT) & ~((insn_t)(MASK) << (SHIFT))) \
+ 	      | ((insn_t)((VALUE) & (MASK)) << (SHIFT)))
+ 
++#define INSERT_VLMUL(STRUCT, VALUE) \
++  INSERT_BITS (STRUCT, (VALUE & 0x3), (OP_MASK_VLMUL & 0x3), 0), \
++  INSERT_BITS (STRUCT, (((VALUE & 0x4) >> 2) <<5), (OP_MASK_VLMUL & 0x20), 0)
++
+ /* Extract bits MASK << SHIFT from STRUCT and shift them right
+    SHIFT places.  */
+ #define EXTRACT_BITS(STRUCT, MASK, SHIFT) \
+@@ -291,6 +367,11 @@ static const char * const riscv_pred_succ[16] =
+ #define EXTRACT_OPERAND(FIELD, INSN) \
+   EXTRACT_BITS ((INSN), OP_MASK_##FIELD, OP_SH_##FIELD)
+ 
++/* Extract the vlmul value from vsetvli instrucion.  */
++#define EXTRACT_VLMUL(INSN) \
++  (((EXTRACT_OPERAND (VLMUL, INSN) >> 5) << 2) \
++   | (EXTRACT_OPERAND (VLMUL, INSN) & 0x3))
++
+ /* The maximal number of subset can be required. */
+ #define MAX_SUBSET_NUM 4
+ 
+@@ -309,6 +390,12 @@ enum riscv_insn_class
+    INSN_CLASS_D_AND_C,
+    INSN_CLASS_F_AND_C,
+    INSN_CLASS_Q,
++   INSN_CLASS_V,
++   INSN_CLASS_V_AND_F,
++   INSN_CLASS_V_OR_ZVAMO,
++   INSN_CLASS_V_AND_ZVEDIV,
++   INSN_CLASS_V_OR_ZVLSSEG,
++   INSN_CLASS_V_AND_ZVQMAC,
+   };
+ 
+ /* This structure holds information for a particular instruction.  */
+@@ -335,8 +422,11 @@ struct riscv_opcode
+      INSN_MACRO, then this field is the macro identifier.  */
+   insn_t mask;
+   /* A function to determine if a word corresponds to this instruction.
+-     Usually, this computes ((word & mask) == match).  */
+-  int (*match_func) (const struct riscv_opcode *op, insn_t word);
++     Usually, this computes ((word & mask) == match).  If the constraints
++     checking is disable, then most of the function should check only the
++     basic encoding for the instruction.  */
++  int (*match_func) (const struct riscv_opcode *op, insn_t word,
++		     int constraints);
+   /* For a macro, this is INSN_MACRO.  Otherwise, it is a collection
+      of bits describing the instruction, notably any relevant hazard
+      information.  */
+@@ -375,6 +465,7 @@ enum riscv_csr_class
+   CSR_CLASS_I,
+   CSR_CLASS_I_32,      /* rv32 only */
+   CSR_CLASS_F,         /* f-ext only */
++  CSR_CLASS_V,         /* v-ext only */
+   CSR_CLASS_DEBUG      /* debug CSR */
+ };
+ 
+@@ -478,6 +569,8 @@ enum
+   M_CALL,
+   M_J,
+   M_LI,
++  M_VMSGE,
++  M_VMSGEU,
+   M_NUM_MACROS
+ };
+ 
+@@ -486,6 +579,8 @@ extern const char * const riscv_gpr_names_numeric[NGPR];
+ extern const char * const riscv_gpr_names_abi[NGPR];
+ extern const char * const riscv_fpr_names_numeric[NFPR];
+ extern const char * const riscv_fpr_names_abi[NFPR];
++extern const char * const riscv_vecr_names_numeric[NVECR];
++extern const char * const riscv_vecm_names_numeric[NVECM];
+ 
+ extern const struct riscv_opcode riscv_opcodes[];
+ extern const struct riscv_opcode riscv_insn_types[];
+diff --git a/opcodes/riscv-dis.c b/opcodes/riscv-dis.c
+index 655ce4ad0b..25e0a93e88 100644
+--- a/opcodes/riscv-dis.c
++++ b/opcodes/riscv-dis.c
+@@ -43,6 +43,7 @@ struct riscv_private_data
+ 
+ static const char * const *riscv_gpr_names;
+ static const char * const *riscv_fpr_names;
++static const char * const *riscv_vecr_names;
+ 
+ /* Other options.  */
+ static int no_aliases;	/* If set disassemble as most general inst.  */
+@@ -52,6 +53,7 @@ set_default_riscv_dis_options (void)
+ {
+   riscv_gpr_names = riscv_gpr_names_abi;
+   riscv_fpr_names = riscv_fpr_names_abi;
++  riscv_vecr_names = riscv_vecr_names_numeric;
+   no_aliases = 0;
+ }
+ 
+@@ -401,6 +403,88 @@ print_insn_args (const char *d, insn_t l, bfd_vma pc, disassemble_info *info)
+ 	  print (info->stream, "%d", rs1);
+ 	  break;
+ 
++	case 'V': /* RVV */
++	  switch (*++d)
++	    {
++	    case 'd':
++	    case 'f':
++	      print (info->stream, "%s",
++		      riscv_vecr_names[EXTRACT_OPERAND (VD, l)]);
++	      break;
++
++	    case 'e':
++	      if (!EXTRACT_OPERAND (VWD, l))
++		print (info->stream, "%s", riscv_gpr_names[0]);
++	      else
++		print (info->stream, "%s",
++		       riscv_vecr_names[EXTRACT_OPERAND (VD, l)]);
++	      break;
++
++	    case 's':
++	      print (info->stream, "%s",
++		      riscv_vecr_names[EXTRACT_OPERAND (VS1, l)]);
++	      break;
++
++	    case 't':
++	    case 'u': /* VS1 == VS2 already verified at this point.  */
++	    case 'v': /* VD == VS1 == VS2 already verified at this point.  */
++	      print (info->stream, "%s",
++		      riscv_vecr_names[EXTRACT_OPERAND (VS2, l)]);
++	      break;
++
++	    case '0':
++	      print (info->stream, "%s", riscv_vecr_names[0]);
++	      break;
++
++	    case 'c':
++	      {
++		int imm = EXTRACT_RVV_VC_IMM (l);
++		unsigned int imm_vlmul = EXTRACT_VLMUL (imm);
++		unsigned int imm_vsew = EXTRACT_OPERAND (VSEW, imm);
++		unsigned int imm_vediv = EXTRACT_OPERAND (VEDIV, imm);
++		unsigned int imm_vta = EXTRACT_OPERAND (VTA, imm);
++		unsigned int imm_vma = EXTRACT_OPERAND (VMA, imm);
++		unsigned int imm_vtype_res = EXTRACT_OPERAND (VTYPE_RES, imm);
++
++		if (imm_vsew < ARRAY_SIZE (riscv_vsew)
++		    && imm_vlmul < ARRAY_SIZE (riscv_vlmul)
++		    && imm_vediv < ARRAY_SIZE (riscv_vediv)
++		    && imm_vta < ARRAY_SIZE (riscv_vta)
++		    && imm_vma < ARRAY_SIZE (riscv_vma)
++		    && ! imm_vtype_res)
++		  print (info->stream, "%s,%s,%s,%s,%s", riscv_vsew[imm_vsew],
++			 riscv_vlmul[imm_vlmul], riscv_vta[imm_vta],
++			 riscv_vma[imm_vma], riscv_vediv[imm_vediv]);
++		else
++		  print (info->stream, "%d", imm);
++	      }
++	      break;
++
++	    case 'i':
++	      print (info->stream, "%d", (int)EXTRACT_RVV_VI_IMM (l));
++	      break;
++
++	    case 'j':
++	      print (info->stream, "%d", (int)EXTRACT_RVV_VI_UIMM (l));
++	      break;
++
++	    case 'k':
++	      print (info->stream, "%d", (int)EXTRACT_RVV_OFFSET (l));
++	      break;
++
++	    case 'm':
++	      if (! EXTRACT_OPERAND (VMASK, l))
++		print (info->stream, ",%s", riscv_vecm_names_numeric[0]);
++	      break;
++
++	    default:
++	      /* xgettext:c-format */
++	      print (info->stream, _("# internal error, undefined modifier (V%c)"),
++		     *d);
++	      return;
++	    }
++	  break;
++
+ 	default:
+ 	  /* xgettext:c-format */
+ 	  print (info->stream, _("# internal error, undefined modifier (%c)"),
+@@ -488,7 +572,7 @@ riscv_disassemble_insn (bfd_vma memaddr, insn_t word, disassemble_info *info)
+       for (; op->name; op++)
+ 	{
+ 	  /* Does the opcode match?  */
+-	  if (! (op->match_func) (op, word))
++	  if (! (op->match_func) (op, word, 0))
+ 	    continue;
+ 	  /* Is this a pseudo-instruction and may we print it as such?  */
+ 	  if (no_aliases && (op->pinfo & INSN_ALIAS))
+diff --git a/opcodes/riscv-opc.c b/opcodes/riscv-opc.c
+index 7ca44dc5b8..fcd87e2261 100644
+--- a/opcodes/riscv-opc.c
++++ b/opcodes/riscv-opc.c
+@@ -56,6 +56,19 @@ const char * const riscv_fpr_names_abi[NFPR] = {
+   "fs8", "fs9", "fs10", "fs11", "ft8", "ft9", "ft10", "ft11"
+ };
+ 
++const char * const riscv_vecr_names_numeric[NVECR] =
++{
++  "v0",   "v1",   "v2",   "v3",   "v4",   "v5",   "v6",   "v7",
++  "v8",   "v9",   "v10",  "v11",  "v12",  "v13",  "v14",  "v15",
++  "v16",  "v17",  "v18",  "v19",  "v20",  "v21",  "v22",  "v23",
++  "v24",  "v25",  "v26",  "v27",  "v28",  "v29",  "v30",  "v31"
++};
++
++const char * const riscv_vecm_names_numeric[NVECM] =
++{
++  "v0.t"
++};
++
+ /* The order of overloaded instructions matters.  Label arguments and
+    register arguments look the same. Instructions that can have either
+    for arguments must apear in the correct order in this table for the
+@@ -79,68 +92,112 @@ const char * const riscv_fpr_names_abi[NFPR] = {
+ #define MASK_AQ (OP_MASK_AQ << OP_SH_AQ)
+ #define MASK_RL (OP_MASK_RL << OP_SH_RL)
+ #define MASK_AQRL (MASK_AQ | MASK_RL)
++#define MASK_VD  (OP_MASK_VD << OP_SH_VD)
++#define MASK_VS1 (OP_MASK_VS1 << OP_SH_VS1)
++#define MASK_VS2 (OP_MASK_VS2 << OP_SH_VS2)
++#define MASK_VMASK (OP_MASK_VMASK << OP_SH_VMASK)
+ 
+ static int
+-match_opcode (const struct riscv_opcode *op, insn_t insn)
++match_opcode (const struct riscv_opcode *op,
++	      insn_t insn,
++	      int constraints ATTRIBUTE_UNUSED)
+ {
+   return ((insn ^ op->match) & op->mask) == 0;
+ }
+ 
+ static int
+ match_never (const struct riscv_opcode *op ATTRIBUTE_UNUSED,
+-	     insn_t insn ATTRIBUTE_UNUSED)
++	     insn_t insn ATTRIBUTE_UNUSED,
++	     int constraints ATTRIBUTE_UNUSED)
+ {
+   return 0;
+ }
+ 
+ static int
+-match_rs1_eq_rs2 (const struct riscv_opcode *op, insn_t insn)
++match_rs1_eq_rs2 (const struct riscv_opcode *op,
++		  insn_t insn,
++		  int constraints ATTRIBUTE_UNUSED)
+ {
+   int rs1 = (insn & MASK_RS1) >> OP_SH_RS1;
+   int rs2 = (insn & MASK_RS2) >> OP_SH_RS2;
+-  return match_opcode (op, insn) && rs1 == rs2;
++  return match_opcode (op, insn, 0) && rs1 == rs2;
++}
++
++static int
++match_vs1_eq_vs2 (const struct riscv_opcode *op,
++		  insn_t insn,
++		  int constraints ATTRIBUTE_UNUSED)
++{
++  int vs1 = (insn & MASK_VS1) >> OP_SH_VS1;
++  int vs2 = (insn & MASK_VS2) >> OP_SH_VS2;
++
++  return match_opcode (op, insn, 0) && vs1 == vs2;
++}
++
++static int
++match_vd_eq_vs1_eq_vs2 (const struct riscv_opcode *op,
++			insn_t insn,
++			int constraints ATTRIBUTE_UNUSED)
++{
++  int vd =  (insn & MASK_VD) >> OP_SH_VD;
++  int vs1 = (insn & MASK_VS1) >> OP_SH_VS1;
++  int vs2 = (insn & MASK_VS2) >> OP_SH_VS2;
++
++  return match_opcode (op, insn, 0) && vd == vs1 && vs1 == vs2;
+ }
+ 
+ static int
+-match_rd_nonzero (const struct riscv_opcode *op, insn_t insn)
++match_rd_nonzero (const struct riscv_opcode *op,
++		  insn_t insn,
++		  int constraints ATTRIBUTE_UNUSED)
+ {
+-  return match_opcode (op, insn) && ((insn & MASK_RD) != 0);
++  return match_opcode (op, insn, 0) && ((insn & MASK_RD) != 0);
+ }
+ 
+ static int
+-match_c_add (const struct riscv_opcode *op, insn_t insn)
++match_c_add (const struct riscv_opcode *op,
++	     insn_t insn,
++	     int constraints ATTRIBUTE_UNUSED)
+ {
+-  return match_rd_nonzero (op, insn) && ((insn & MASK_CRS2) != 0);
++  return match_rd_nonzero (op, insn, 0) && ((insn & MASK_CRS2) != 0);
+ }
+ 
+ /* We don't allow mv zero,X to become a c.mv hint, so we need a separate
+    matching function for this.  */
+ 
+ static int
+-match_c_add_with_hint (const struct riscv_opcode *op, insn_t insn)
++match_c_add_with_hint (const struct riscv_opcode *op,
++		       insn_t insn,
++		       int constraints ATTRIBUTE_UNUSED)
+ {
+-  return match_opcode (op, insn) && ((insn & MASK_CRS2) != 0);
++  return match_opcode (op, insn, 0) && ((insn & MASK_CRS2) != 0);
+ }
+ 
+ static int
+-match_c_nop (const struct riscv_opcode *op, insn_t insn)
++match_c_nop (const struct riscv_opcode *op,
++	     insn_t insn,
++	     int constraints ATTRIBUTE_UNUSED)
+ {
+-  return (match_opcode (op, insn)
++  return (match_opcode (op, insn, 0)
+ 	  && (((insn & MASK_RD) >> OP_SH_RD) == 0));
+ }
+ 
+ static int
+-match_c_addi16sp (const struct riscv_opcode *op, insn_t insn)
++match_c_addi16sp (const struct riscv_opcode *op,
++		  insn_t insn,
++		  int constraints ATTRIBUTE_UNUSED)
+ {
+-  return (match_opcode (op, insn)
++  return (match_opcode (op, insn, 0)
+ 	  && (((insn & MASK_RD) >> OP_SH_RD) == 2)
+ 	  && EXTRACT_RVC_ADDI16SP_IMM (insn) != 0);
+ }
+ 
+ static int
+-match_c_lui (const struct riscv_opcode *op, insn_t insn)
++match_c_lui (const struct riscv_opcode *op,
++	     insn_t insn,
++	     int constraints ATTRIBUTE_UNUSED)
+ {
+-  return (match_rd_nonzero (op, insn)
++  return (match_rd_nonzero (op, insn, 0)
+ 	  && (((insn & MASK_RD) >> OP_SH_RD) != 2)
+ 	  && EXTRACT_RVC_LUI_IMM (insn) != 0);
+ }
+@@ -149,50 +206,275 @@ match_c_lui (const struct riscv_opcode *op, insn_t insn)
+    matching function for this.  */
+ 
+ static int
+-match_c_lui_with_hint (const struct riscv_opcode *op, insn_t insn)
++match_c_lui_with_hint (const struct riscv_opcode *op,
++		       insn_t insn,
++		       int constraints ATTRIBUTE_UNUSED)
+ {
+-  return (match_opcode (op, insn)
++  return (match_opcode (op, insn, 0)
+ 	  && (((insn & MASK_RD) >> OP_SH_RD) != 2)
+ 	  && EXTRACT_RVC_LUI_IMM (insn) != 0);
+ }
+ 
+ static int
+-match_c_addi4spn (const struct riscv_opcode *op, insn_t insn)
++match_c_addi4spn (const struct riscv_opcode *op,
++		  insn_t insn,
++		  int constraints ATTRIBUTE_UNUSED)
+ {
+-  return match_opcode (op, insn) && EXTRACT_RVC_ADDI4SPN_IMM (insn) != 0;
++  return match_opcode (op, insn, 0) && EXTRACT_RVC_ADDI4SPN_IMM (insn) != 0;
+ }
+ 
+ /* This requires a non-zero shift.  A zero rd is a hint, so is allowed.  */
+ 
+ static int
+-match_c_slli (const struct riscv_opcode *op, insn_t insn)
++match_c_slli (const struct riscv_opcode *op,
++	      insn_t insn,
++	      int constraints ATTRIBUTE_UNUSED)
+ {
+-  return match_opcode (op, insn) && EXTRACT_RVC_IMM (insn) != 0;
++  return match_opcode (op, insn, 0) && EXTRACT_RVC_IMM (insn) != 0;
+ }
+ 
+ /* This requires a non-zero rd, and a non-zero shift.  */
+ 
+ static int
+-match_slli_as_c_slli (const struct riscv_opcode *op, insn_t insn)
++match_slli_as_c_slli (const struct riscv_opcode *op,
++		      insn_t insn,
++		      int constraints ATTRIBUTE_UNUSED)
+ {
+-  return match_rd_nonzero (op, insn) && EXTRACT_RVC_IMM (insn) != 0;
++  return match_rd_nonzero (op, insn, 0) && EXTRACT_RVC_IMM (insn) != 0;
+ }
+ 
+ /* This requires a zero shift.  A zero rd is a hint, so is allowed.  */
+ 
+ static int
+-match_c_slli64 (const struct riscv_opcode *op, insn_t insn)
++match_c_slli64 (const struct riscv_opcode *op,
++		insn_t insn,
++		int constraints ATTRIBUTE_UNUSED)
+ {
+-  return match_opcode (op, insn) && EXTRACT_RVC_IMM (insn) == 0;
++  return match_opcode (op, insn, 0) && EXTRACT_RVC_IMM (insn) == 0;
+ }
+ 
+ /* This is used for both srli and srai.  This requires a non-zero shift.
+    A zero rd is not possible.  */
+ 
+ static int
+-match_srxi_as_c_srxi (const struct riscv_opcode *op, insn_t insn)
++match_srxi_as_c_srxi (const struct riscv_opcode *op,
++		      insn_t insn,
++		      int constraints ATTRIBUTE_UNUSED)
++{
++  return match_opcode (op, insn, 0) && EXTRACT_RVC_IMM (insn) != 0;
++}
++
++/* These are used to check the vector constraints.  */
++
++static int
++match_widen_vd_neq_vs1_neq_vs2_neq_vm (const struct riscv_opcode *op,
++				       insn_t insn,
++				       int constraints)
++{
++  int vd = (insn & MASK_VD) >> OP_SH_VD;
++  int vs1 = (insn & MASK_VS1) >> OP_SH_VS1;
++  int vs2 = (insn & MASK_VS2) >> OP_SH_VS2;
++  int vm = (insn & MASK_VMASK) >> OP_SH_VMASK;
++
++  if (constraints
++      && ((vd % 2) != 0
++	  || (vs1 >= vd && vs1 <= (vd + 1))
++	  || (vs2 >= vd && vs2 <= (vd + 1))
++	  || (!vm && vm >= vd && vm <= (vd + 1))))
++    return 0;
++
++  return match_opcode (op, insn, 0);
++}
++
++static int
++match_widen_vd_neq_vs1_neq_vm (const struct riscv_opcode *op,
++			       insn_t insn,
++			       int constraints)
++{
++  int vd = (insn & MASK_VD) >> OP_SH_VD;
++  int vs1 = (insn & MASK_VS1) >> OP_SH_VS1;
++  int vs2 = (insn & MASK_VS2) >> OP_SH_VS2;
++  int vm = (insn & MASK_VMASK) >> OP_SH_VMASK;
++
++  if (constraints
++      && ((vd % 2) != 0
++	  || (vs2 % 2) != 0
++	  || (vs1 >= vd && vs1 <= (vd + 1))
++	  || (!vm && vm >= vd && vm <= (vd + 1))))
++    return 0;
++
++  return match_opcode (op, insn, 0);
++}
++
++static int
++match_widen_vd_neq_vs2_neq_vm (const struct riscv_opcode *op,
++			       insn_t insn,
++			       int constraints)
++{
++  int vd = (insn & MASK_VD) >> OP_SH_VD;
++  int vs2 = (insn & MASK_VS2) >> OP_SH_VS2;
++  int vm = (insn & MASK_VMASK) >> OP_SH_VMASK;
++
++  if (constraints
++      && ((vd % 2) != 0
++	  || (vs2 >= vd && vs2 <= (vd + 1))
++	  || (!vm && vm >= vd && vm <= (vd + 1))))
++    return 0;
++
++  return match_opcode (op, insn, 0);
++}
++
++static int
++match_widen_vd_neq_vm (const struct riscv_opcode *op,
++		       insn_t insn,
++		       int constraints)
++{
++  int vd = (insn & MASK_VD) >> OP_SH_VD;
++  int vs2 = (insn & MASK_VS2) >> OP_SH_VS2;
++  int vm = (insn & MASK_VMASK) >> OP_SH_VMASK;
++
++  if (constraints
++      && ((vd % 2) != 0
++	  || (vs2 % 2) != 0
++	  || (!vm && vm >= vd && vm <= (vd + 1))))
++    return 0;
++
++  return match_opcode (op, insn, 0);
++}
++
++static int
++match_quad_vd_neq_vs1_neq_vs2_neq_vm (const struct riscv_opcode *op,
++				      insn_t insn,
++				      int constraints)
++{
++  int vd = (insn & MASK_VD) >> OP_SH_VD;
++  int vs1 = (insn & MASK_VS1) >> OP_SH_VS1;
++  int vs2 = (insn & MASK_VS2) >> OP_SH_VS2;
++  int vm = (insn & MASK_VMASK) >> OP_SH_VMASK;
++
++  if (constraints
++      && ((vd % 4) != 0
++	  || (vs1 >= vd && vs1 <= (vd + 3))
++	  || (vs2 >= vd && vs2 <= (vd + 3))
++	  || (!vm && vm >= vd && vm <= (vd + 3))))
++    return 0;
++
++  return match_opcode (op, insn, 0);
++}
++
++static int
++match_quad_vd_neq_vs2_neq_vm (const struct riscv_opcode *op,
++			      insn_t insn,
++			      int constraints)
++{
++  int vd = (insn & MASK_VD) >> OP_SH_VD;
++  int vs2 = (insn & MASK_VS2) >> OP_SH_VS2;
++  int vm = (insn & MASK_VMASK) >> OP_SH_VMASK;
++
++  if (constraints
++      && ((vd % 4) != 0
++	  || (vs2 >= vd && vs2 <= (vd + 3))
++	  || (!vm && vm >= vd && vm <= (vd + 3))))
++    return 0;
++
++  return match_opcode (op, insn, 0);
++}
++
++static int
++match_narrow_vd_neq_vs2 (const struct riscv_opcode *op,
++			 insn_t insn,
++			 int constraints)
++{
++  int vd = (insn & MASK_VD) >> OP_SH_VD;
++  int vs2 = (insn & MASK_VS2) >> OP_SH_VS2;
++
++  if (constraints
++      && ((vs2 % 2) != 0
++	  || (vd >= vs2 && vd <= (vs2 + 1))))
++    return 0;
++
++  return match_opcode (op, insn, 0);
++}
++
++static int
++match_vd_neq_vs1_neq_vs2_neq_vm (const struct riscv_opcode *op,
++				 insn_t insn,
++				 int constraints)
++{
++  int vd = (insn & MASK_VD) >> OP_SH_VD;
++  int vs1 = (insn & MASK_VS1) >> OP_SH_VS1;
++  int vs2 = (insn & MASK_VS2) >> OP_SH_VS2;
++  int vm = (insn & MASK_VMASK) >> OP_SH_VMASK;
++
++  if (constraints
++      && (vs1 == vd
++	  || vs2 == vd
++	  || (!vm && vm == vd)))
++    return 0;
++
++  return match_opcode (op, insn, 0);
++}
++
++static int
++match_vd_neq_vs2_neq_vm (const struct riscv_opcode *op,
++			 insn_t insn,
++			 int constraints)
++{
++  int vd = (insn & MASK_VD) >> OP_SH_VD;
++  int vs2 = (insn & MASK_VS2) >> OP_SH_VS2;
++  int vm = (insn & MASK_VMASK) >> OP_SH_VMASK;
++
++   if (constraints
++      && (vs2 == vd
++	  || (!vm && vm == vd)))
++    return 0;
++
++  return match_opcode (op, insn, 0);
++}
++
++static int
++match_vd_neq_vs2 (const struct riscv_opcode *op,
++		  insn_t insn,
++		  int constraints)
++{
++  int vd = (insn & MASK_VD) >> OP_SH_VD;
++  int vs2 = (insn & MASK_VS2) >> OP_SH_VS2;
++
++   if (constraints && vs2 == vd)
++    return 0;
++
++  return match_opcode (op, insn, 0);
++}
++
++static int
++match_vd_neq_vm (const struct riscv_opcode *op,
++		 insn_t insn,
++		 int constraints)
+ {
+-  return match_opcode (op, insn) && EXTRACT_RVC_IMM (insn) != 0;
++  int vd = (insn & MASK_VD) >> OP_SH_VD;
++  int vm = (insn & MASK_VMASK) >> OP_SH_VMASK;
++
++  if (constraints && !vm && vm == vd)
++    return 0;
++
++  return match_opcode (op, insn, 0);
++}
++
++static int
++match_vmv_nf_rv (const struct riscv_opcode *op,
++		 insn_t insn,
++		 int constraints)
++{
++  int vd = (insn & MASK_VD) >> OP_SH_VD;
++  int vs2 = (insn & MASK_VS2) >> OP_SH_VS2;
++  int nf = ((insn & (0x7 << 15) ) >> 15) + 1;
++
++  if (constraints
++      && ((vd % nf) != 0
++	  || (vs2 % nf) != 0))
++    return 0;
++
++  return match_opcode (op, insn, 0);
+ }
+ 
+ const struct riscv_opcode riscv_opcodes[] =
+@@ -780,6 +1062,954 @@ const struct riscv_opcode riscv_opcodes[] =
+ {"sfence.vma", 0, INSN_CLASS_I,   "s,t",  MATCH_SFENCE_VMA, MASK_SFENCE_VMA, match_opcode, 0 },
+ {"wfi",        0, INSN_CLASS_I,   "",     MATCH_WFI, MASK_WFI, match_opcode, 0 },
+ 
++/* RVV */
++{"vsetvl",     0, INSN_CLASS_V,  "d,s,t", MATCH_VSETVL, MASK_VSETVL, match_opcode, 0},
++{"vsetvli",    0, INSN_CLASS_V,  "d,s,Vc", MATCH_VSETVLI, MASK_VSETVLI, match_opcode, 0},
++
++{"vle8.v",     0, INSN_CLASS_V,  "Vd,0(s)Vm", MATCH_VLE8V, MASK_VLE8V, match_opcode, INSN_DREF },
++{"vle16.v",    0, INSN_CLASS_V,  "Vd,0(s)Vm", MATCH_VLE16V, MASK_VLE16V, match_opcode, INSN_DREF },
++{"vle32.v",    0, INSN_CLASS_V,  "Vd,0(s)Vm", MATCH_VLE32V, MASK_VLE32V, match_opcode, INSN_DREF },
++{"vle64.v",    0, INSN_CLASS_V,  "Vd,0(s)Vm", MATCH_VLE64V, MASK_VLE64V, match_opcode, INSN_DREF },
++{"vle128.v",   0, INSN_CLASS_V,  "Vd,0(s)Vm", MATCH_VLE128V, MASK_VLE128V, match_opcode, INSN_DREF },
++{"vle256.v",   0, INSN_CLASS_V,  "Vd,0(s)Vm", MATCH_VLE256V, MASK_VLE256V, match_opcode, INSN_DREF },
++{"vle512.v",   0, INSN_CLASS_V,  "Vd,0(s)Vm", MATCH_VLE512V, MASK_VLE512V, match_opcode, INSN_DREF },
++{"vle1024.v",  0, INSN_CLASS_V,  "Vd,0(s)Vm", MATCH_VLE1024V, MASK_VLE1024V, match_opcode, INSN_DREF },
++
++{"vse8.v",     0, INSN_CLASS_V,  "Vd,0(s)Vm", MATCH_VSE8V, MASK_VSE8V, match_opcode, INSN_DREF },
++{"vse16.v",    0, INSN_CLASS_V,  "Vd,0(s)Vm", MATCH_VSE16V, MASK_VSE16V, match_opcode, INSN_DREF },
++{"vse32.v",    0, INSN_CLASS_V,  "Vd,0(s)Vm", MATCH_VSE32V, MASK_VSE32V, match_opcode, INSN_DREF },
++{"vse64.v",    0, INSN_CLASS_V,  "Vd,0(s)Vm", MATCH_VSE64V, MASK_VSE64V, match_opcode, INSN_DREF },
++{"vse128.v",   0, INSN_CLASS_V,  "Vd,0(s)Vm", MATCH_VSE128V, MASK_VSE128V, match_opcode, INSN_DREF },
++{"vse256.v",   0, INSN_CLASS_V,  "Vd,0(s)Vm", MATCH_VSE256V, MASK_VSE256V, match_opcode, INSN_DREF },
++{"vse512.v",   0, INSN_CLASS_V,  "Vd,0(s)Vm", MATCH_VSE512V, MASK_VSE512V, match_opcode, INSN_DREF },
++{"vse1024.v",  0, INSN_CLASS_V,  "Vd,0(s)Vm", MATCH_VSE1024V, MASK_VSE1024V, match_opcode, INSN_DREF },
++
++{"vlse8.v",    0, INSN_CLASS_V,  "Vd,0(s),tVm", MATCH_VLSE8V, MASK_VLSE8V, match_opcode, INSN_DREF },
++{"vlse16.v",   0, INSN_CLASS_V,  "Vd,0(s),tVm", MATCH_VLSE16V, MASK_VLSE16V, match_opcode, INSN_DREF },
++{"vlse32.v",   0, INSN_CLASS_V,  "Vd,0(s),tVm", MATCH_VLSE32V, MASK_VLSE32V, match_opcode, INSN_DREF },
++{"vlse64.v",   0, INSN_CLASS_V,  "Vd,0(s),tVm", MATCH_VLSE64V, MASK_VLSE64V, match_opcode, INSN_DREF },
++{"vlse128.v",  0, INSN_CLASS_V,  "Vd,0(s),tVm", MATCH_VLSE128V, MASK_VLSE128V, match_opcode, INSN_DREF },
++{"vlse256.v",  0, INSN_CLASS_V,  "Vd,0(s),tVm", MATCH_VLSE256V, MASK_VLSE256V, match_opcode, INSN_DREF },
++{"vlse512.v",  0, INSN_CLASS_V,  "Vd,0(s),tVm", MATCH_VLSE512V, MASK_VLSE512V, match_opcode, INSN_DREF },
++{"vlse1024.v", 0, INSN_CLASS_V,  "Vd,0(s),tVm", MATCH_VLSE1024V, MASK_VLSE1024V, match_opcode, INSN_DREF },
++
++{"vsse8.v",    0, INSN_CLASS_V,  "Vd,0(s),tVm", MATCH_VSSE8V, MASK_VSSE8V, match_opcode, INSN_DREF },
++{"vsse16.v",   0, INSN_CLASS_V,  "Vd,0(s),tVm", MATCH_VSSE16V, MASK_VSSE16V, match_opcode, INSN_DREF },
++{"vsse32.v",   0, INSN_CLASS_V,  "Vd,0(s),tVm", MATCH_VSSE32V, MASK_VSSE32V, match_opcode, INSN_DREF },
++{"vsse64.v",   0, INSN_CLASS_V,  "Vd,0(s),tVm", MATCH_VSSE64V, MASK_VSSE64V, match_opcode, INSN_DREF },
++{"vsse128.v",  0, INSN_CLASS_V,  "Vd,0(s),tVm", MATCH_VSSE128V, MASK_VSSE128V, match_opcode, INSN_DREF },
++{"vsse256.v",  0, INSN_CLASS_V,  "Vd,0(s),tVm", MATCH_VSSE256V, MASK_VSSE256V, match_opcode, INSN_DREF },
++{"vsse512.v",  0, INSN_CLASS_V,  "Vd,0(s),tVm", MATCH_VSSE512V, MASK_VSSE512V, match_opcode, INSN_DREF },
++{"vsse1024.v", 0, INSN_CLASS_V,  "Vd,0(s),tVm", MATCH_VSSE1024V, MASK_VSSE1024V, match_opcode, INSN_DREF },
++
++{"vlxei8.v",   0, INSN_CLASS_V,  "Vd,0(s),VtVm", MATCH_VLXEI8V, MASK_VLXEI8V, match_opcode, INSN_DREF },
++{"vlxei16.v",  0, INSN_CLASS_V,  "Vd,0(s),VtVm", MATCH_VLXEI16V, MASK_VLXEI16V, match_opcode, INSN_DREF },
++{"vlxei32.v",  0, INSN_CLASS_V,  "Vd,0(s),VtVm", MATCH_VLXEI32V, MASK_VLXEI32V, match_opcode, INSN_DREF },
++{"vlxei64.v",  0, INSN_CLASS_V,  "Vd,0(s),VtVm", MATCH_VLXEI64V, MASK_VLXEI64V, match_opcode, INSN_DREF },
++{"vlxei128.v", 0, INSN_CLASS_V,  "Vd,0(s),VtVm", MATCH_VLXEI128V, MASK_VLXEI128V, match_opcode, INSN_DREF },
++{"vlxei256.v", 0, INSN_CLASS_V,  "Vd,0(s),VtVm", MATCH_VLXEI256V, MASK_VLXEI256V, match_opcode, INSN_DREF },
++{"vlxei512.v", 0, INSN_CLASS_V,  "Vd,0(s),VtVm", MATCH_VLXEI512V, MASK_VLXEI512V, match_opcode, INSN_DREF },
++{"vlxei1024.v",0, INSN_CLASS_V,  "Vd,0(s),VtVm", MATCH_VLXEI1024V, MASK_VLXEI1024V, match_opcode, INSN_DREF },
++
++{"vsxei8.v",   0, INSN_CLASS_V,  "Vd,0(s),VtVm", MATCH_VSXEI8V, MASK_VSXEI8V, match_opcode, INSN_DREF },
++{"vsxei16.v",  0, INSN_CLASS_V,  "Vd,0(s),VtVm", MATCH_VSXEI16V, MASK_VSXEI16V, match_opcode, INSN_DREF },
++{"vsxei32.v",  0, INSN_CLASS_V,  "Vd,0(s),VtVm", MATCH_VSXEI32V, MASK_VSXEI32V, match_opcode, INSN_DREF },
++{"vsxei64.v",  0, INSN_CLASS_V,  "Vd,0(s),VtVm", MATCH_VSXEI64V, MASK_VSXEI64V, match_opcode, INSN_DREF },
++{"vsxei128.v", 0, INSN_CLASS_V,  "Vd,0(s),VtVm", MATCH_VSXEI128V, MASK_VSXEI128V, match_opcode, INSN_DREF },
++{"vsxei256.v", 0, INSN_CLASS_V,  "Vd,0(s),VtVm", MATCH_VSXEI256V, MASK_VSXEI256V, match_opcode, INSN_DREF },
++{"vsxei512.v", 0, INSN_CLASS_V,  "Vd,0(s),VtVm", MATCH_VSXEI512V, MASK_VSXEI512V, match_opcode, INSN_DREF },
++{"vsxei1024.v",0, INSN_CLASS_V,  "Vd,0(s),VtVm", MATCH_VSXEI1024V, MASK_VSXEI1024V, match_opcode, INSN_DREF },
++
++{"vsuxei8.v",   0, INSN_CLASS_V,  "Vd,0(s),VtVm", MATCH_VSUXEI8V, MASK_VSUXEI8V, match_opcode, INSN_DREF },
++{"vsuxei16.v",  0, INSN_CLASS_V,  "Vd,0(s),VtVm", MATCH_VSUXEI16V, MASK_VSUXEI16V, match_opcode, INSN_DREF },
++{"vsuxei32.v",  0, INSN_CLASS_V,  "Vd,0(s),VtVm", MATCH_VSUXEI32V, MASK_VSUXEI32V, match_opcode, INSN_DREF },
++{"vsuxei64.v",  0, INSN_CLASS_V,  "Vd,0(s),VtVm", MATCH_VSUXEI64V, MASK_VSUXEI64V, match_opcode, INSN_DREF },
++{"vsuxei128.v", 0, INSN_CLASS_V,  "Vd,0(s),VtVm", MATCH_VSUXEI128V, MASK_VSUXEI128V, match_opcode, INSN_DREF },
++{"vsuxei256.v", 0, INSN_CLASS_V,  "Vd,0(s),VtVm", MATCH_VSUXEI256V, MASK_VSUXEI256V, match_opcode, INSN_DREF },
++{"vsuxei512.v", 0, INSN_CLASS_V,  "Vd,0(s),VtVm", MATCH_VSUXEI512V, MASK_VSUXEI512V, match_opcode, INSN_DREF },
++{"vsuxei1024.v",0, INSN_CLASS_V,  "Vd,0(s),VtVm", MATCH_VSUXEI1024V, MASK_VSUXEI1024V, match_opcode, INSN_DREF },
++
++{"vle8ff.v",    0, INSN_CLASS_V,  "Vd,0(s)Vm", MATCH_VLE8FFV, MASK_VLE8FFV, match_opcode, INSN_DREF },
++{"vle16ff.v",   0, INSN_CLASS_V,  "Vd,0(s)Vm", MATCH_VLE16FFV, MASK_VLE16FFV, match_opcode, INSN_DREF },
++{"vle32ff.v",   0, INSN_CLASS_V,  "Vd,0(s)Vm", MATCH_VLE32FFV, MASK_VLE32FFV, match_opcode, INSN_DREF },
++{"vle64ff.v",   0, INSN_CLASS_V,  "Vd,0(s)Vm", MATCH_VLE64FFV, MASK_VLE64FFV, match_opcode, INSN_DREF },
++{"vle128ff.v",  0, INSN_CLASS_V,  "Vd,0(s)Vm", MATCH_VLE128FFV, MASK_VLE128FFV, match_opcode, INSN_DREF },
++{"vle256ff.v",  0, INSN_CLASS_V,  "Vd,0(s)Vm", MATCH_VLE256FFV, MASK_VLE256FFV, match_opcode, INSN_DREF },
++{"vle512ff.v",  0, INSN_CLASS_V,  "Vd,0(s)Vm", MATCH_VLE512FFV, MASK_VLE512FFV, match_opcode, INSN_DREF },
++{"vle1024ff.v", 0, INSN_CLASS_V,  "Vd,0(s)Vm", MATCH_VLE1024FFV, MASK_VLE1024FFV, match_opcode, INSN_DREF },
++
++{"vlseg2e8.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s)Vm", MATCH_VLSEG2E8V, MASK_VLSEG2E8V, match_vd_neq_vm, INSN_DREF },
++{"vsseg2e8.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s)Vm", MATCH_VSSEG2E8V, MASK_VSSEG2E8V, match_opcode, INSN_DREF },
++{"vlseg3e8.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s)Vm", MATCH_VLSEG3E8V, MASK_VLSEG3E8V, match_vd_neq_vm, INSN_DREF },
++{"vsseg3e8.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s)Vm", MATCH_VSSEG3E8V, MASK_VSSEG3E8V, match_opcode, INSN_DREF },
++{"vlseg4e8.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s)Vm", MATCH_VLSEG4E8V, MASK_VLSEG4E8V, match_vd_neq_vm, INSN_DREF },
++{"vsseg4e8.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s)Vm", MATCH_VSSEG4E8V, MASK_VSSEG4E8V, match_opcode, INSN_DREF },
++{"vlseg5e8.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s)Vm", MATCH_VLSEG5E8V, MASK_VLSEG5E8V, match_vd_neq_vm, INSN_DREF },
++{"vsseg5e8.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s)Vm", MATCH_VSSEG5E8V, MASK_VSSEG5E8V, match_opcode, INSN_DREF },
++{"vlseg6e8.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s)Vm", MATCH_VLSEG6E8V, MASK_VLSEG6E8V, match_vd_neq_vm, INSN_DREF },
++{"vsseg6e8.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s)Vm", MATCH_VSSEG6E8V, MASK_VSSEG6E8V, match_opcode, INSN_DREF },
++{"vlseg7e8.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s)Vm", MATCH_VLSEG7E8V, MASK_VLSEG7E8V, match_vd_neq_vm, INSN_DREF },
++{"vsseg7e8.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s)Vm", MATCH_VSSEG7E8V, MASK_VSSEG7E8V, match_opcode, INSN_DREF },
++{"vlseg8e8.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s)Vm", MATCH_VLSEG8E8V, MASK_VLSEG8E8V, match_vd_neq_vm, INSN_DREF },
++{"vsseg8e8.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s)Vm", MATCH_VSSEG8E8V, MASK_VSSEG8E8V, match_opcode, INSN_DREF },
++
++{"vlseg2e16.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s)Vm", MATCH_VLSEG2E16V, MASK_VLSEG2E16V, match_vd_neq_vm, INSN_DREF },
++{"vsseg2e16.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s)Vm", MATCH_VSSEG2E16V, MASK_VSSEG2E16V, match_opcode, INSN_DREF },
++{"vlseg3e16.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s)Vm", MATCH_VLSEG3E16V, MASK_VLSEG3E16V, match_vd_neq_vm, INSN_DREF },
++{"vsseg3e16.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s)Vm", MATCH_VSSEG3E16V, MASK_VSSEG3E16V, match_opcode, INSN_DREF },
++{"vlseg4e16.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s)Vm", MATCH_VLSEG4E16V, MASK_VLSEG4E16V, match_vd_neq_vm, INSN_DREF },
++{"vsseg4e16.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s)Vm", MATCH_VSSEG4E16V, MASK_VSSEG4E16V, match_opcode, INSN_DREF },
++{"vlseg5e16.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s)Vm", MATCH_VLSEG5E16V, MASK_VLSEG5E16V, match_vd_neq_vm, INSN_DREF },
++{"vsseg5e16.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s)Vm", MATCH_VSSEG5E16V, MASK_VSSEG5E16V, match_opcode, INSN_DREF },
++{"vlseg6e16.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s)Vm", MATCH_VLSEG6E16V, MASK_VLSEG6E16V, match_vd_neq_vm, INSN_DREF },
++{"vsseg6e16.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s)Vm", MATCH_VSSEG6E16V, MASK_VSSEG6E16V, match_opcode, INSN_DREF },
++{"vlseg7e16.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s)Vm", MATCH_VLSEG7E16V, MASK_VLSEG7E16V, match_vd_neq_vm, INSN_DREF },
++{"vsseg7e16.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s)Vm", MATCH_VSSEG7E16V, MASK_VSSEG7E16V, match_opcode, INSN_DREF },
++{"vlseg8e16.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s)Vm", MATCH_VLSEG8E16V, MASK_VLSEG8E16V, match_vd_neq_vm, INSN_DREF },
++{"vsseg8e16.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s)Vm", MATCH_VSSEG8E16V, MASK_VSSEG8E16V, match_opcode, INSN_DREF },
++
++{"vlseg2e32.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s)Vm", MATCH_VLSEG2E32V, MASK_VLSEG2E32V, match_vd_neq_vm, INSN_DREF },
++{"vsseg2e32.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s)Vm", MATCH_VSSEG2E32V, MASK_VSSEG2E32V, match_opcode, INSN_DREF },
++{"vlseg3e32.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s)Vm", MATCH_VLSEG3E32V, MASK_VLSEG3E32V, match_vd_neq_vm, INSN_DREF },
++{"vsseg3e32.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s)Vm", MATCH_VSSEG3E32V, MASK_VSSEG3E32V, match_opcode, INSN_DREF },
++{"vlseg4e32.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s)Vm", MATCH_VLSEG4E32V, MASK_VLSEG4E32V, match_vd_neq_vm, INSN_DREF },
++{"vsseg4e32.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s)Vm", MATCH_VSSEG4E32V, MASK_VSSEG4E32V, match_opcode, INSN_DREF },
++{"vlseg5e32.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s)Vm", MATCH_VLSEG5E32V, MASK_VLSEG5E32V, match_vd_neq_vm, INSN_DREF },
++{"vsseg5e32.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s)Vm", MATCH_VSSEG5E32V, MASK_VSSEG5E32V, match_opcode, INSN_DREF },
++{"vlseg6e32.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s)Vm", MATCH_VLSEG6E32V, MASK_VLSEG6E32V, match_vd_neq_vm, INSN_DREF },
++{"vsseg6e32.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s)Vm", MATCH_VSSEG6E32V, MASK_VSSEG6E32V, match_opcode, INSN_DREF },
++{"vlseg7e32.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s)Vm", MATCH_VLSEG7E32V, MASK_VLSEG7E32V, match_vd_neq_vm, INSN_DREF },
++{"vsseg7e32.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s)Vm", MATCH_VSSEG7E32V, MASK_VSSEG7E32V, match_opcode, INSN_DREF },
++{"vlseg8e32.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s)Vm", MATCH_VLSEG8E32V, MASK_VLSEG8E32V, match_vd_neq_vm, INSN_DREF },
++{"vsseg8e32.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s)Vm", MATCH_VSSEG8E32V, MASK_VSSEG8E32V, match_opcode, INSN_DREF },
++
++{"vlseg2e64.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s)Vm", MATCH_VLSEG2E64V, MASK_VLSEG2E64V, match_vd_neq_vm, INSN_DREF },
++{"vsseg2e64.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s)Vm", MATCH_VSSEG2E64V, MASK_VSSEG2E64V, match_opcode, INSN_DREF },
++{"vlseg3e64.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s)Vm", MATCH_VLSEG3E64V, MASK_VLSEG3E64V, match_vd_neq_vm, INSN_DREF },
++{"vsseg3e64.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s)Vm", MATCH_VSSEG3E64V, MASK_VSSEG3E64V, match_opcode, INSN_DREF },
++{"vlseg4e64.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s)Vm", MATCH_VLSEG4E64V, MASK_VLSEG4E64V, match_vd_neq_vm, INSN_DREF },
++{"vsseg4e64.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s)Vm", MATCH_VSSEG4E64V, MASK_VSSEG4E64V, match_opcode, INSN_DREF },
++{"vlseg5e64.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s)Vm", MATCH_VLSEG5E64V, MASK_VLSEG5E64V, match_vd_neq_vm, INSN_DREF },
++{"vsseg5e64.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s)Vm", MATCH_VSSEG5E64V, MASK_VSSEG5E64V, match_opcode, INSN_DREF },
++{"vlseg6e64.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s)Vm", MATCH_VLSEG6E64V, MASK_VLSEG6E64V, match_vd_neq_vm, INSN_DREF },
++{"vsseg6e64.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s)Vm", MATCH_VSSEG6E64V, MASK_VSSEG6E64V, match_opcode, INSN_DREF },
++{"vlseg7e64.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s)Vm", MATCH_VLSEG7E64V, MASK_VLSEG7E64V, match_vd_neq_vm, INSN_DREF },
++{"vsseg7e64.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s)Vm", MATCH_VSSEG7E64V, MASK_VSSEG7E64V, match_opcode, INSN_DREF },
++{"vlseg8e64.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s)Vm", MATCH_VLSEG8E64V, MASK_VLSEG8E64V, match_vd_neq_vm, INSN_DREF },
++{"vsseg8e64.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s)Vm", MATCH_VSSEG8E64V, MASK_VSSEG8E64V, match_opcode, INSN_DREF },
++
++{"vlseg2e128.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s)Vm", MATCH_VLSEG2E128V, MASK_VLSEG2E128V, match_vd_neq_vm, INSN_DREF },
++{"vsseg2e128.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s)Vm", MATCH_VSSEG2E128V, MASK_VSSEG2E128V, match_opcode, INSN_DREF },
++{"vlseg3e128.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s)Vm", MATCH_VLSEG3E128V, MASK_VLSEG3E128V, match_vd_neq_vm, INSN_DREF },
++{"vsseg3e128.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s)Vm", MATCH_VSSEG3E128V, MASK_VSSEG3E128V, match_opcode, INSN_DREF },
++{"vlseg4e128.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s)Vm", MATCH_VLSEG4E128V, MASK_VLSEG4E128V, match_vd_neq_vm, INSN_DREF },
++{"vsseg4e128.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s)Vm", MATCH_VSSEG4E128V, MASK_VSSEG4E128V, match_opcode, INSN_DREF },
++{"vlseg5e128.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s)Vm", MATCH_VLSEG5E128V, MASK_VLSEG5E128V, match_vd_neq_vm, INSN_DREF },
++{"vsseg5e128.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s)Vm", MATCH_VSSEG5E128V, MASK_VSSEG5E128V, match_opcode, INSN_DREF },
++{"vlseg6e128.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s)Vm", MATCH_VLSEG6E128V, MASK_VLSEG6E128V, match_vd_neq_vm, INSN_DREF },
++{"vsseg6e128.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s)Vm", MATCH_VSSEG6E128V, MASK_VSSEG6E128V, match_opcode, INSN_DREF },
++{"vlseg7e128.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s)Vm", MATCH_VLSEG7E128V, MASK_VLSEG7E128V, match_vd_neq_vm, INSN_DREF },
++{"vsseg7e128.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s)Vm", MATCH_VSSEG7E128V, MASK_VSSEG7E128V, match_opcode, INSN_DREF },
++{"vlseg8e128.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s)Vm", MATCH_VLSEG8E128V, MASK_VLSEG8E128V, match_vd_neq_vm, INSN_DREF },
++{"vsseg8e128.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s)Vm", MATCH_VSSEG8E128V, MASK_VSSEG8E128V, match_opcode, INSN_DREF },
++
++{"vlseg2e256.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s)Vm", MATCH_VLSEG2E256V, MASK_VLSEG2E256V, match_vd_neq_vm, INSN_DREF },
++{"vsseg2e256.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s)Vm", MATCH_VSSEG2E256V, MASK_VSSEG2E256V, match_opcode, INSN_DREF },
++{"vlseg3e256.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s)Vm", MATCH_VLSEG3E256V, MASK_VLSEG3E256V, match_vd_neq_vm, INSN_DREF },
++{"vsseg3e256.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s)Vm", MATCH_VSSEG3E256V, MASK_VSSEG3E256V, match_opcode, INSN_DREF },
++{"vlseg4e256.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s)Vm", MATCH_VLSEG4E256V, MASK_VLSEG4E256V, match_vd_neq_vm, INSN_DREF },
++{"vsseg4e256.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s)Vm", MATCH_VSSEG4E256V, MASK_VSSEG4E256V, match_opcode, INSN_DREF },
++{"vlseg5e256.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s)Vm", MATCH_VLSEG5E256V, MASK_VLSEG5E256V, match_vd_neq_vm, INSN_DREF },
++{"vsseg5e256.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s)Vm", MATCH_VSSEG5E256V, MASK_VSSEG5E256V, match_opcode, INSN_DREF },
++{"vlseg6e256.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s)Vm", MATCH_VLSEG6E256V, MASK_VLSEG6E256V, match_vd_neq_vm, INSN_DREF },
++{"vsseg6e256.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s)Vm", MATCH_VSSEG6E256V, MASK_VSSEG6E256V, match_opcode, INSN_DREF },
++{"vlseg7e256.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s)Vm", MATCH_VLSEG7E256V, MASK_VLSEG7E256V, match_vd_neq_vm, INSN_DREF },
++{"vsseg7e256.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s)Vm", MATCH_VSSEG7E256V, MASK_VSSEG7E256V, match_opcode, INSN_DREF },
++{"vlseg8e256.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s)Vm", MATCH_VLSEG8E256V, MASK_VLSEG8E256V, match_vd_neq_vm, INSN_DREF },
++{"vsseg8e256.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s)Vm", MATCH_VSSEG8E256V, MASK_VSSEG8E256V, match_opcode, INSN_DREF },
++
++{"vlseg2e512.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s)Vm", MATCH_VLSEG2E512V, MASK_VLSEG2E512V, match_vd_neq_vm, INSN_DREF },
++{"vsseg2e512.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s)Vm", MATCH_VSSEG2E512V, MASK_VSSEG2E512V, match_opcode, INSN_DREF },
++{"vlseg3e512.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s)Vm", MATCH_VLSEG3E512V, MASK_VLSEG3E512V, match_vd_neq_vm, INSN_DREF },
++{"vsseg3e512.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s)Vm", MATCH_VSSEG3E512V, MASK_VSSEG3E512V, match_opcode, INSN_DREF },
++{"vlseg4e512.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s)Vm", MATCH_VLSEG4E512V, MASK_VLSEG4E512V, match_vd_neq_vm, INSN_DREF },
++{"vsseg4e512.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s)Vm", MATCH_VSSEG4E512V, MASK_VSSEG4E512V, match_opcode, INSN_DREF },
++{"vlseg5e512.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s)Vm", MATCH_VLSEG5E512V, MASK_VLSEG5E512V, match_vd_neq_vm, INSN_DREF },
++{"vsseg5e512.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s)Vm", MATCH_VSSEG5E512V, MASK_VSSEG5E512V, match_opcode, INSN_DREF },
++{"vlseg6e512.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s)Vm", MATCH_VLSEG6E512V, MASK_VLSEG6E512V, match_vd_neq_vm, INSN_DREF },
++{"vsseg6e512.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s)Vm", MATCH_VSSEG6E512V, MASK_VSSEG6E512V, match_opcode, INSN_DREF },
++{"vlseg7e512.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s)Vm", MATCH_VLSEG7E512V, MASK_VLSEG7E512V, match_vd_neq_vm, INSN_DREF },
++{"vsseg7e512.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s)Vm", MATCH_VSSEG7E512V, MASK_VSSEG7E512V, match_opcode, INSN_DREF },
++{"vlseg8e512.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s)Vm", MATCH_VLSEG8E512V, MASK_VLSEG8E512V, match_vd_neq_vm, INSN_DREF },
++{"vsseg8e512.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s)Vm", MATCH_VSSEG8E512V, MASK_VSSEG8E512V, match_opcode, INSN_DREF },
++
++{"vlseg2e1024.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s)Vm", MATCH_VLSEG2E1024V, MASK_VLSEG2E1024V, match_vd_neq_vm, INSN_DREF },
++{"vsseg2e1024.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s)Vm", MATCH_VSSEG2E1024V, MASK_VSSEG2E1024V, match_opcode, INSN_DREF },
++{"vlseg3e1024.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s)Vm", MATCH_VLSEG3E1024V, MASK_VLSEG3E1024V, match_vd_neq_vm, INSN_DREF },
++{"vsseg3e1024.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s)Vm", MATCH_VSSEG3E1024V, MASK_VSSEG3E1024V, match_opcode, INSN_DREF },
++{"vlseg4e1024.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s)Vm", MATCH_VLSEG4E1024V, MASK_VLSEG4E1024V, match_vd_neq_vm, INSN_DREF },
++{"vsseg4e1024.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s)Vm", MATCH_VSSEG4E1024V, MASK_VSSEG4E1024V, match_opcode, INSN_DREF },
++{"vlseg5e1024.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s)Vm", MATCH_VLSEG5E1024V, MASK_VLSEG5E1024V, match_vd_neq_vm, INSN_DREF },
++{"vsseg5e1024.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s)Vm", MATCH_VSSEG5E1024V, MASK_VSSEG5E1024V, match_opcode, INSN_DREF },
++{"vlseg6e1024.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s)Vm", MATCH_VLSEG6E1024V, MASK_VLSEG6E1024V, match_vd_neq_vm, INSN_DREF },
++{"vsseg6e1024.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s)Vm", MATCH_VSSEG6E1024V, MASK_VSSEG6E1024V, match_opcode, INSN_DREF },
++{"vlseg7e1024.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s)Vm", MATCH_VLSEG7E1024V, MASK_VLSEG7E1024V, match_vd_neq_vm, INSN_DREF },
++{"vsseg7e1024.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s)Vm", MATCH_VSSEG7E1024V, MASK_VSSEG7E1024V, match_opcode, INSN_DREF },
++{"vlseg8e1024.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s)Vm", MATCH_VLSEG8E1024V, MASK_VLSEG8E1024V, match_vd_neq_vm, INSN_DREF },
++{"vsseg8e1024.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s)Vm", MATCH_VSSEG8E1024V, MASK_VSSEG8E1024V, match_opcode, INSN_DREF },
++
++{"vlsseg2e8.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),tVm", MATCH_VLSSEG2E8V, MASK_VLSSEG2E8V, match_vd_neq_vm, INSN_DREF },
++{"vssseg2e8.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),tVm", MATCH_VSSSEG2E8V, MASK_VSSSEG2E8V, match_opcode, INSN_DREF },
++{"vlsseg3e8.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),tVm", MATCH_VLSSEG3E8V, MASK_VLSSEG3E8V, match_vd_neq_vm, INSN_DREF },
++{"vssseg3e8.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),tVm", MATCH_VSSSEG3E8V, MASK_VSSSEG3E8V, match_opcode, INSN_DREF },
++{"vlsseg4e8.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),tVm", MATCH_VLSSEG4E8V, MASK_VLSSEG4E8V, match_vd_neq_vm, INSN_DREF },
++{"vssseg4e8.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),tVm", MATCH_VSSSEG4E8V, MASK_VSSSEG4E8V, match_opcode, INSN_DREF },
++{"vlsseg5e8.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),tVm", MATCH_VLSSEG5E8V, MASK_VLSSEG5E8V, match_vd_neq_vm, INSN_DREF },
++{"vssseg5e8.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),tVm", MATCH_VSSSEG5E8V, MASK_VSSSEG5E8V, match_opcode, INSN_DREF },
++{"vlsseg6e8.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),tVm", MATCH_VLSSEG6E8V, MASK_VLSSEG6E8V, match_vd_neq_vm, INSN_DREF },
++{"vssseg6e8.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),tVm", MATCH_VSSSEG6E8V, MASK_VSSSEG6E8V, match_opcode, INSN_DREF },
++{"vlsseg7e8.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),tVm", MATCH_VLSSEG7E8V, MASK_VLSSEG7E8V, match_vd_neq_vm, INSN_DREF },
++{"vssseg7e8.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),tVm", MATCH_VSSSEG7E8V, MASK_VSSSEG7E8V, match_opcode, INSN_DREF },
++{"vlsseg8e8.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),tVm", MATCH_VLSSEG8E8V, MASK_VLSSEG8E8V, match_vd_neq_vm, INSN_DREF },
++{"vssseg8e8.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),tVm", MATCH_VSSSEG8E8V, MASK_VSSSEG8E8V, match_opcode, INSN_DREF },
++
++{"vlsseg2e16.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),tVm", MATCH_VLSSEG2E16V, MASK_VLSSEG2E16V, match_vd_neq_vm, INSN_DREF },
++{"vssseg2e16.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),tVm", MATCH_VSSSEG2E16V, MASK_VSSSEG2E16V, match_opcode, INSN_DREF },
++{"vlsseg3e16.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),tVm", MATCH_VLSSEG3E16V, MASK_VLSSEG3E16V, match_vd_neq_vm, INSN_DREF },
++{"vssseg3e16.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),tVm", MATCH_VSSSEG3E16V, MASK_VSSSEG3E16V, match_opcode, INSN_DREF },
++{"vlsseg4e16.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),tVm", MATCH_VLSSEG4E16V, MASK_VLSSEG4E16V, match_vd_neq_vm, INSN_DREF },
++{"vssseg4e16.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),tVm", MATCH_VSSSEG4E16V, MASK_VSSSEG4E16V, match_opcode, INSN_DREF },
++{"vlsseg5e16.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),tVm", MATCH_VLSSEG5E16V, MASK_VLSSEG5E16V, match_vd_neq_vm, INSN_DREF },
++{"vssseg5e16.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),tVm", MATCH_VSSSEG5E16V, MASK_VSSSEG5E16V, match_opcode, INSN_DREF },
++{"vlsseg6e16.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),tVm", MATCH_VLSSEG6E16V, MASK_VLSSEG6E16V, match_vd_neq_vm, INSN_DREF },
++{"vssseg6e16.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),tVm", MATCH_VSSSEG6E16V, MASK_VSSSEG6E16V, match_opcode, INSN_DREF },
++{"vlsseg7e16.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),tVm", MATCH_VLSSEG7E16V, MASK_VLSSEG7E16V, match_vd_neq_vm, INSN_DREF },
++{"vssseg7e16.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),tVm", MATCH_VSSSEG7E16V, MASK_VSSSEG7E16V, match_opcode, INSN_DREF },
++{"vlsseg8e16.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),tVm", MATCH_VLSSEG8E16V, MASK_VLSSEG8E16V, match_vd_neq_vm, INSN_DREF },
++{"vssseg8e16.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),tVm", MATCH_VSSSEG8E16V, MASK_VSSSEG8E16V, match_opcode, INSN_DREF },
++
++{"vlsseg2e32.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),tVm", MATCH_VLSSEG2E32V, MASK_VLSSEG2E32V, match_vd_neq_vm, INSN_DREF },
++{"vssseg2e32.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),tVm", MATCH_VSSSEG2E32V, MASK_VSSSEG2E32V, match_opcode, INSN_DREF },
++{"vlsseg3e32.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),tVm", MATCH_VLSSEG3E32V, MASK_VLSSEG3E32V, match_vd_neq_vm, INSN_DREF },
++{"vssseg3e32.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),tVm", MATCH_VSSSEG3E32V, MASK_VSSSEG3E32V, match_opcode, INSN_DREF },
++{"vlsseg4e32.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),tVm", MATCH_VLSSEG4E32V, MASK_VLSSEG4E32V, match_vd_neq_vm, INSN_DREF },
++{"vssseg4e32.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),tVm", MATCH_VSSSEG4E32V, MASK_VSSSEG4E32V, match_opcode, INSN_DREF },
++{"vlsseg5e32.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),tVm", MATCH_VLSSEG5E32V, MASK_VLSSEG5E32V, match_vd_neq_vm, INSN_DREF },
++{"vssseg5e32.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),tVm", MATCH_VSSSEG5E32V, MASK_VSSSEG5E32V, match_opcode, INSN_DREF },
++{"vlsseg6e32.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),tVm", MATCH_VLSSEG6E32V, MASK_VLSSEG6E32V, match_vd_neq_vm, INSN_DREF },
++{"vssseg6e32.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),tVm", MATCH_VSSSEG6E32V, MASK_VSSSEG6E32V, match_opcode, INSN_DREF },
++{"vlsseg7e32.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),tVm", MATCH_VLSSEG7E32V, MASK_VLSSEG7E32V, match_vd_neq_vm, INSN_DREF },
++{"vssseg7e32.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),tVm", MATCH_VSSSEG7E32V, MASK_VSSSEG7E32V, match_opcode, INSN_DREF },
++{"vlsseg8e32.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),tVm", MATCH_VLSSEG8E32V, MASK_VLSSEG8E32V, match_vd_neq_vm, INSN_DREF },
++{"vssseg8e32.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),tVm", MATCH_VSSSEG8E32V, MASK_VSSSEG8E32V, match_opcode, INSN_DREF },
++
++{"vlsseg2e64.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),tVm", MATCH_VLSSEG2E64V, MASK_VLSSEG2E64V, match_vd_neq_vm, INSN_DREF },
++{"vssseg2e64.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),tVm", MATCH_VSSSEG2E64V, MASK_VSSSEG2E64V, match_opcode, INSN_DREF },
++{"vlsseg3e64.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),tVm", MATCH_VLSSEG3E64V, MASK_VLSSEG3E64V, match_vd_neq_vm, INSN_DREF },
++{"vssseg3e64.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),tVm", MATCH_VSSSEG3E64V, MASK_VSSSEG3E64V, match_opcode, INSN_DREF },
++{"vlsseg4e64.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),tVm", MATCH_VLSSEG4E64V, MASK_VLSSEG4E64V, match_vd_neq_vm, INSN_DREF },
++{"vssseg4e64.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),tVm", MATCH_VSSSEG4E64V, MASK_VSSSEG4E64V, match_opcode, INSN_DREF },
++{"vlsseg5e64.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),tVm", MATCH_VLSSEG5E64V, MASK_VLSSEG5E64V, match_vd_neq_vm, INSN_DREF },
++{"vssseg5e64.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),tVm", MATCH_VSSSEG5E64V, MASK_VSSSEG5E64V, match_opcode, INSN_DREF },
++{"vlsseg6e64.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),tVm", MATCH_VLSSEG6E64V, MASK_VLSSEG6E64V, match_vd_neq_vm, INSN_DREF },
++{"vssseg6e64.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),tVm", MATCH_VSSSEG6E64V, MASK_VSSSEG6E64V, match_opcode, INSN_DREF },
++{"vlsseg7e64.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),tVm", MATCH_VLSSEG7E64V, MASK_VLSSEG7E64V, match_vd_neq_vm, INSN_DREF },
++{"vssseg7e64.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),tVm", MATCH_VSSSEG7E64V, MASK_VSSSEG7E64V, match_opcode, INSN_DREF },
++{"vlsseg8e64.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),tVm", MATCH_VLSSEG8E64V, MASK_VLSSEG8E64V, match_vd_neq_vm, INSN_DREF },
++{"vssseg8e64.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),tVm", MATCH_VSSSEG8E64V, MASK_VSSSEG8E64V, match_opcode, INSN_DREF },
++
++{"vlsseg2e128.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),tVm", MATCH_VLSSEG2E128V, MASK_VLSSEG2E128V, match_vd_neq_vm, INSN_DREF },
++{"vssseg2e128.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),tVm", MATCH_VSSSEG2E128V, MASK_VSSSEG2E128V, match_opcode, INSN_DREF },
++{"vlsseg3e128.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),tVm", MATCH_VLSSEG3E128V, MASK_VLSSEG3E128V, match_vd_neq_vm, INSN_DREF },
++{"vssseg3e128.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),tVm", MATCH_VSSSEG3E128V, MASK_VSSSEG3E128V, match_opcode, INSN_DREF },
++{"vlsseg4e128.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),tVm", MATCH_VLSSEG4E128V, MASK_VLSSEG4E128V, match_vd_neq_vm, INSN_DREF },
++{"vssseg4e128.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),tVm", MATCH_VSSSEG4E128V, MASK_VSSSEG4E128V, match_opcode, INSN_DREF },
++{"vlsseg5e128.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),tVm", MATCH_VLSSEG5E128V, MASK_VLSSEG5E128V, match_vd_neq_vm, INSN_DREF },
++{"vssseg5e128.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),tVm", MATCH_VSSSEG5E128V, MASK_VSSSEG5E128V, match_opcode, INSN_DREF },
++{"vlsseg6e128.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),tVm", MATCH_VLSSEG6E128V, MASK_VLSSEG6E128V, match_vd_neq_vm, INSN_DREF },
++{"vssseg6e128.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),tVm", MATCH_VSSSEG6E128V, MASK_VSSSEG6E128V, match_opcode, INSN_DREF },
++{"vlsseg7e128.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),tVm", MATCH_VLSSEG7E128V, MASK_VLSSEG7E128V, match_vd_neq_vm, INSN_DREF },
++{"vssseg7e128.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),tVm", MATCH_VSSSEG7E128V, MASK_VSSSEG7E128V, match_opcode, INSN_DREF },
++{"vlsseg8e128.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),tVm", MATCH_VLSSEG8E128V, MASK_VLSSEG8E128V, match_vd_neq_vm, INSN_DREF },
++{"vssseg8e128.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),tVm", MATCH_VSSSEG8E128V, MASK_VSSSEG8E128V, match_opcode, INSN_DREF },
++
++{"vlsseg2e256.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),tVm", MATCH_VLSSEG2E256V, MASK_VLSSEG2E256V, match_vd_neq_vm, INSN_DREF },
++{"vssseg2e256.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),tVm", MATCH_VSSSEG2E256V, MASK_VSSSEG2E256V, match_opcode, INSN_DREF },
++{"vlsseg3e256.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),tVm", MATCH_VLSSEG3E256V, MASK_VLSSEG3E256V, match_vd_neq_vm, INSN_DREF },
++{"vssseg3e256.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),tVm", MATCH_VSSSEG3E256V, MASK_VSSSEG3E256V, match_opcode, INSN_DREF },
++{"vlsseg4e256.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),tVm", MATCH_VLSSEG4E256V, MASK_VLSSEG4E256V, match_vd_neq_vm, INSN_DREF },
++{"vssseg4e256.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),tVm", MATCH_VSSSEG4E256V, MASK_VSSSEG4E256V, match_opcode, INSN_DREF },
++{"vlsseg5e256.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),tVm", MATCH_VLSSEG5E256V, MASK_VLSSEG5E256V, match_vd_neq_vm, INSN_DREF },
++{"vssseg5e256.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),tVm", MATCH_VSSSEG5E256V, MASK_VSSSEG5E256V, match_opcode, INSN_DREF },
++{"vlsseg6e256.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),tVm", MATCH_VLSSEG6E256V, MASK_VLSSEG6E256V, match_vd_neq_vm, INSN_DREF },
++{"vssseg6e256.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),tVm", MATCH_VSSSEG6E256V, MASK_VSSSEG6E256V, match_opcode, INSN_DREF },
++{"vlsseg7e256.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),tVm", MATCH_VLSSEG7E256V, MASK_VLSSEG7E256V, match_vd_neq_vm, INSN_DREF },
++{"vssseg7e256.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),tVm", MATCH_VSSSEG7E256V, MASK_VSSSEG7E256V, match_opcode, INSN_DREF },
++{"vlsseg8e256.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),tVm", MATCH_VLSSEG8E256V, MASK_VLSSEG8E256V, match_vd_neq_vm, INSN_DREF },
++{"vssseg8e256.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),tVm", MATCH_VSSSEG8E256V, MASK_VSSSEG8E256V, match_opcode, INSN_DREF },
++
++{"vlsseg2e512.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),tVm", MATCH_VLSSEG2E512V, MASK_VLSSEG2E512V, match_vd_neq_vm, INSN_DREF },
++{"vssseg2e512.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),tVm", MATCH_VSSSEG2E512V, MASK_VSSSEG2E512V, match_opcode, INSN_DREF },
++{"vlsseg3e512.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),tVm", MATCH_VLSSEG3E512V, MASK_VLSSEG3E512V, match_vd_neq_vm, INSN_DREF },
++{"vssseg3e512.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),tVm", MATCH_VSSSEG3E512V, MASK_VSSSEG3E512V, match_opcode, INSN_DREF },
++{"vlsseg4e512.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),tVm", MATCH_VLSSEG4E512V, MASK_VLSSEG4E512V, match_vd_neq_vm, INSN_DREF },
++{"vssseg4e512.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),tVm", MATCH_VSSSEG4E512V, MASK_VSSSEG4E512V, match_opcode, INSN_DREF },
++{"vlsseg5e512.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),tVm", MATCH_VLSSEG5E512V, MASK_VLSSEG5E512V, match_vd_neq_vm, INSN_DREF },
++{"vssseg5e512.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),tVm", MATCH_VSSSEG5E512V, MASK_VSSSEG5E512V, match_opcode, INSN_DREF },
++{"vlsseg6e512.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),tVm", MATCH_VLSSEG6E512V, MASK_VLSSEG6E512V, match_vd_neq_vm, INSN_DREF },
++{"vssseg6e512.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),tVm", MATCH_VSSSEG6E512V, MASK_VSSSEG6E512V, match_opcode, INSN_DREF },
++{"vlsseg7e512.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),tVm", MATCH_VLSSEG7E512V, MASK_VLSSEG7E512V, match_vd_neq_vm, INSN_DREF },
++{"vssseg7e512.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),tVm", MATCH_VSSSEG7E512V, MASK_VSSSEG7E512V, match_opcode, INSN_DREF },
++{"vlsseg8e512.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),tVm", MATCH_VLSSEG8E512V, MASK_VLSSEG8E512V, match_vd_neq_vm, INSN_DREF },
++{"vssseg8e512.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),tVm", MATCH_VSSSEG8E512V, MASK_VSSSEG8E512V, match_opcode, INSN_DREF },
++
++{"vlsseg2e1024.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),tVm", MATCH_VLSSEG2E1024V, MASK_VLSSEG2E1024V, match_vd_neq_vm, INSN_DREF },
++{"vssseg2e1024.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),tVm", MATCH_VSSSEG2E1024V, MASK_VSSSEG2E1024V, match_opcode, INSN_DREF },
++{"vlsseg3e1024.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),tVm", MATCH_VLSSEG3E1024V, MASK_VLSSEG3E1024V, match_vd_neq_vm, INSN_DREF },
++{"vssseg3e1024.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),tVm", MATCH_VSSSEG3E1024V, MASK_VSSSEG3E1024V, match_opcode, INSN_DREF },
++{"vlsseg4e1024.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),tVm", MATCH_VLSSEG4E1024V, MASK_VLSSEG4E1024V, match_vd_neq_vm, INSN_DREF },
++{"vssseg4e1024.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),tVm", MATCH_VSSSEG4E1024V, MASK_VSSSEG4E1024V, match_opcode, INSN_DREF },
++{"vlsseg5e1024.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),tVm", MATCH_VLSSEG5E1024V, MASK_VLSSEG5E1024V, match_vd_neq_vm, INSN_DREF },
++{"vssseg5e1024.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),tVm", MATCH_VSSSEG5E1024V, MASK_VSSSEG5E1024V, match_opcode, INSN_DREF },
++{"vlsseg6e1024.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),tVm", MATCH_VLSSEG6E1024V, MASK_VLSSEG6E1024V, match_vd_neq_vm, INSN_DREF },
++{"vssseg6e1024.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),tVm", MATCH_VSSSEG6E1024V, MASK_VSSSEG6E1024V, match_opcode, INSN_DREF },
++{"vlsseg7e1024.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),tVm", MATCH_VLSSEG7E1024V, MASK_VLSSEG7E1024V, match_vd_neq_vm, INSN_DREF },
++{"vssseg7e1024.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),tVm", MATCH_VSSSEG7E1024V, MASK_VSSSEG7E1024V, match_opcode, INSN_DREF },
++{"vlsseg8e1024.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),tVm", MATCH_VLSSEG8E1024V, MASK_VLSSEG8E1024V, match_vd_neq_vm, INSN_DREF },
++{"vssseg8e1024.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),tVm", MATCH_VSSSEG8E1024V, MASK_VSSSEG8E1024V, match_opcode, INSN_DREF },
++
++{"vlxseg2ei8.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),VtVm", MATCH_VLXSEG2EI8V, MASK_VLXSEG2EI8V, match_vd_neq_vs2_neq_vm, INSN_DREF },
++{"vsxseg2ei8.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),VtVm", MATCH_VSXSEG2EI8V, MASK_VSXSEG2EI8V, match_vd_neq_vs2_neq_vm, INSN_DREF },
++{"vlxseg3ei8.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),VtVm", MATCH_VLXSEG3EI8V, MASK_VLXSEG3EI8V, match_vd_neq_vs2_neq_vm, INSN_DREF },
++{"vsxseg3ei8.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),VtVm", MATCH_VSXSEG3EI8V, MASK_VSXSEG3EI8V, match_vd_neq_vs2_neq_vm, INSN_DREF },
++{"vlxseg4ei8.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),VtVm", MATCH_VLXSEG4EI8V, MASK_VLXSEG4EI8V, match_vd_neq_vs2_neq_vm, INSN_DREF },
++{"vsxseg4ei8.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),VtVm", MATCH_VSXSEG4EI8V, MASK_VSXSEG4EI8V, match_vd_neq_vs2_neq_vm, INSN_DREF },
++{"vlxseg5ei8.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),VtVm", MATCH_VLXSEG5EI8V, MASK_VLXSEG5EI8V, match_vd_neq_vs2_neq_vm, INSN_DREF },
++{"vsxseg5ei8.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),VtVm", MATCH_VSXSEG5EI8V, MASK_VSXSEG5EI8V, match_vd_neq_vs2_neq_vm, INSN_DREF },
++{"vlxseg6ei8.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),VtVm", MATCH_VLXSEG6EI8V, MASK_VLXSEG6EI8V, match_vd_neq_vs2_neq_vm, INSN_DREF },
++{"vsxseg6ei8.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),VtVm", MATCH_VSXSEG6EI8V, MASK_VSXSEG6EI8V, match_vd_neq_vs2_neq_vm, INSN_DREF },
++{"vlxseg7ei8.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),VtVm", MATCH_VLXSEG7EI8V, MASK_VLXSEG7EI8V, match_vd_neq_vs2_neq_vm, INSN_DREF },
++{"vsxseg7ei8.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),VtVm", MATCH_VSXSEG7EI8V, MASK_VSXSEG7EI8V, match_vd_neq_vs2_neq_vm, INSN_DREF },
++{"vlxseg8ei8.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),VtVm", MATCH_VLXSEG8EI8V, MASK_VLXSEG8EI8V, match_vd_neq_vs2_neq_vm, INSN_DREF },
++{"vsxseg8ei8.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),VtVm", MATCH_VSXSEG8EI8V, MASK_VSXSEG8EI8V, match_vd_neq_vs2_neq_vm, INSN_DREF },
++
++{"vlxseg2ei16.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),VtVm", MATCH_VLXSEG2EI16V, MASK_VLXSEG2EI16V, match_vd_neq_vs2_neq_vm, INSN_DREF },
++{"vsxseg2ei16.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),VtVm", MATCH_VSXSEG2EI16V, MASK_VSXSEG2EI16V, match_vd_neq_vs2_neq_vm, INSN_DREF },
++{"vlxseg3ei16.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),VtVm", MATCH_VLXSEG3EI16V, MASK_VLXSEG3EI16V, match_vd_neq_vs2_neq_vm, INSN_DREF },
++{"vsxseg3ei16.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),VtVm", MATCH_VSXSEG3EI16V, MASK_VSXSEG3EI16V, match_vd_neq_vs2_neq_vm, INSN_DREF },
++{"vlxseg4ei16.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),VtVm", MATCH_VLXSEG4EI16V, MASK_VLXSEG4EI16V, match_vd_neq_vs2_neq_vm, INSN_DREF },
++{"vsxseg4ei16.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),VtVm", MATCH_VSXSEG4EI16V, MASK_VSXSEG4EI16V, match_vd_neq_vs2_neq_vm, INSN_DREF },
++{"vlxseg5ei16.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),VtVm", MATCH_VLXSEG5EI16V, MASK_VLXSEG5EI16V, match_vd_neq_vs2_neq_vm, INSN_DREF },
++{"vsxseg5ei16.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),VtVm", MATCH_VSXSEG5EI16V, MASK_VSXSEG5EI16V, match_vd_neq_vs2_neq_vm, INSN_DREF },
++{"vlxseg6ei16.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),VtVm", MATCH_VLXSEG6EI16V, MASK_VLXSEG6EI16V, match_vd_neq_vs2_neq_vm, INSN_DREF },
++{"vsxseg6ei16.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),VtVm", MATCH_VSXSEG6EI16V, MASK_VSXSEG6EI16V, match_vd_neq_vs2_neq_vm, INSN_DREF },
++{"vlxseg7ei16.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),VtVm", MATCH_VLXSEG7EI16V, MASK_VLXSEG7EI16V, match_vd_neq_vs2_neq_vm, INSN_DREF },
++{"vsxseg7ei16.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),VtVm", MATCH_VSXSEG7EI16V, MASK_VSXSEG7EI16V, match_vd_neq_vs2_neq_vm, INSN_DREF },
++{"vlxseg8ei16.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),VtVm", MATCH_VLXSEG8EI16V, MASK_VLXSEG8EI16V, match_vd_neq_vs2_neq_vm, INSN_DREF },
++{"vsxseg8ei16.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),VtVm", MATCH_VSXSEG8EI16V, MASK_VSXSEG8EI16V, match_vd_neq_vs2_neq_vm, INSN_DREF },
++
++{"vlxseg2ei32.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),VtVm", MATCH_VLXSEG2EI32V, MASK_VLXSEG2EI32V, match_vd_neq_vs2_neq_vm, INSN_DREF },
++{"vsxseg2ei32.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),VtVm", MATCH_VSXSEG2EI32V, MASK_VSXSEG2EI32V, match_vd_neq_vs2_neq_vm, INSN_DREF },
++{"vlxseg3ei32.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),VtVm", MATCH_VLXSEG3EI32V, MASK_VLXSEG3EI32V, match_vd_neq_vs2_neq_vm, INSN_DREF },
++{"vsxseg3ei32.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),VtVm", MATCH_VSXSEG3EI32V, MASK_VSXSEG3EI32V, match_vd_neq_vs2_neq_vm, INSN_DREF },
++{"vlxseg4ei32.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),VtVm", MATCH_VLXSEG4EI32V, MASK_VLXSEG4EI32V, match_vd_neq_vs2_neq_vm, INSN_DREF },
++{"vsxseg4ei32.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),VtVm", MATCH_VSXSEG4EI32V, MASK_VSXSEG4EI32V, match_vd_neq_vs2_neq_vm, INSN_DREF },
++{"vlxseg5ei32.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),VtVm", MATCH_VLXSEG5EI32V, MASK_VLXSEG5EI32V, match_vd_neq_vs2_neq_vm, INSN_DREF },
++{"vsxseg5ei32.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),VtVm", MATCH_VSXSEG5EI32V, MASK_VSXSEG5EI32V, match_vd_neq_vs2_neq_vm, INSN_DREF },
++{"vlxseg6ei32.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),VtVm", MATCH_VLXSEG6EI32V, MASK_VLXSEG6EI32V, match_vd_neq_vs2_neq_vm, INSN_DREF },
++{"vsxseg6ei32.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),VtVm", MATCH_VSXSEG6EI32V, MASK_VSXSEG6EI32V, match_vd_neq_vs2_neq_vm, INSN_DREF },
++{"vlxseg7ei32.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),VtVm", MATCH_VLXSEG7EI32V, MASK_VLXSEG7EI32V, match_vd_neq_vs2_neq_vm, INSN_DREF },
++{"vsxseg7ei32.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),VtVm", MATCH_VSXSEG7EI32V, MASK_VSXSEG7EI32V, match_vd_neq_vs2_neq_vm, INSN_DREF },
++{"vlxseg8ei32.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),VtVm", MATCH_VLXSEG8EI32V, MASK_VLXSEG8EI32V, match_vd_neq_vs2_neq_vm, INSN_DREF },
++{"vsxseg8ei32.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),VtVm", MATCH_VSXSEG8EI32V, MASK_VSXSEG8EI32V, match_vd_neq_vs2_neq_vm, INSN_DREF },
++
++{"vlxseg2ei64.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),VtVm", MATCH_VLXSEG2EI64V, MASK_VLXSEG2EI64V, match_vd_neq_vs2_neq_vm, INSN_DREF },
++{"vsxseg2ei64.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),VtVm", MATCH_VSXSEG2EI64V, MASK_VSXSEG2EI64V, match_vd_neq_vs2_neq_vm, INSN_DREF },
++{"vlxseg3ei64.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),VtVm", MATCH_VLXSEG3EI64V, MASK_VLXSEG3EI64V, match_vd_neq_vs2_neq_vm, INSN_DREF },
++{"vsxseg3ei64.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),VtVm", MATCH_VSXSEG3EI64V, MASK_VSXSEG3EI64V, match_vd_neq_vs2_neq_vm, INSN_DREF },
++{"vlxseg4ei64.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),VtVm", MATCH_VLXSEG4EI64V, MASK_VLXSEG4EI64V, match_vd_neq_vs2_neq_vm, INSN_DREF },
++{"vsxseg4ei64.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),VtVm", MATCH_VSXSEG4EI64V, MASK_VSXSEG4EI64V, match_vd_neq_vs2_neq_vm, INSN_DREF },
++{"vlxseg5ei64.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),VtVm", MATCH_VLXSEG5EI64V, MASK_VLXSEG5EI64V, match_vd_neq_vs2_neq_vm, INSN_DREF },
++{"vsxseg5ei64.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),VtVm", MATCH_VSXSEG5EI64V, MASK_VSXSEG5EI64V, match_vd_neq_vs2_neq_vm, INSN_DREF },
++{"vlxseg6ei64.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),VtVm", MATCH_VLXSEG6EI64V, MASK_VLXSEG6EI64V, match_vd_neq_vs2_neq_vm, INSN_DREF },
++{"vsxseg6ei64.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),VtVm", MATCH_VSXSEG6EI64V, MASK_VSXSEG6EI64V, match_vd_neq_vs2_neq_vm, INSN_DREF },
++{"vlxseg7ei64.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),VtVm", MATCH_VLXSEG7EI64V, MASK_VLXSEG7EI64V, match_vd_neq_vs2_neq_vm, INSN_DREF },
++{"vsxseg7ei64.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),VtVm", MATCH_VSXSEG7EI64V, MASK_VSXSEG7EI64V, match_vd_neq_vs2_neq_vm, INSN_DREF },
++{"vlxseg8ei64.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),VtVm", MATCH_VLXSEG8EI64V, MASK_VLXSEG8EI64V, match_vd_neq_vs2_neq_vm, INSN_DREF },
++{"vsxseg8ei64.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),VtVm", MATCH_VSXSEG8EI64V, MASK_VSXSEG8EI64V, match_vd_neq_vs2_neq_vm, INSN_DREF },
++
++{"vlxseg2ei128.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),VtVm", MATCH_VLXSEG2EI128V, MASK_VLXSEG2EI128V, match_vd_neq_vs2_neq_vm, INSN_DREF },
++{"vsxseg2ei128.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),VtVm", MATCH_VSXSEG2EI128V, MASK_VSXSEG2EI128V, match_vd_neq_vs2_neq_vm, INSN_DREF },
++{"vlxseg3ei128.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),VtVm", MATCH_VLXSEG3EI128V, MASK_VLXSEG3EI128V, match_vd_neq_vs2_neq_vm, INSN_DREF },
++{"vsxseg3ei128.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),VtVm", MATCH_VSXSEG3EI128V, MASK_VSXSEG3EI128V, match_vd_neq_vs2_neq_vm, INSN_DREF },
++{"vlxseg4ei128.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),VtVm", MATCH_VLXSEG4EI128V, MASK_VLXSEG4EI128V, match_vd_neq_vs2_neq_vm, INSN_DREF },
++{"vsxseg4ei128.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),VtVm", MATCH_VSXSEG4EI128V, MASK_VSXSEG4EI128V, match_vd_neq_vs2_neq_vm, INSN_DREF },
++{"vlxseg5ei128.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),VtVm", MATCH_VLXSEG5EI128V, MASK_VLXSEG5EI128V, match_vd_neq_vs2_neq_vm, INSN_DREF },
++{"vsxseg5ei128.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),VtVm", MATCH_VSXSEG5EI128V, MASK_VSXSEG5EI128V, match_vd_neq_vs2_neq_vm, INSN_DREF },
++{"vlxseg6ei128.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),VtVm", MATCH_VLXSEG6EI128V, MASK_VLXSEG6EI128V, match_vd_neq_vs2_neq_vm, INSN_DREF },
++{"vsxseg6ei128.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),VtVm", MATCH_VSXSEG6EI128V, MASK_VSXSEG6EI128V, match_vd_neq_vs2_neq_vm, INSN_DREF },
++{"vlxseg7ei128.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),VtVm", MATCH_VLXSEG7EI128V, MASK_VLXSEG7EI128V, match_vd_neq_vs2_neq_vm, INSN_DREF },
++{"vsxseg7ei128.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),VtVm", MATCH_VSXSEG7EI128V, MASK_VSXSEG7EI128V, match_vd_neq_vs2_neq_vm, INSN_DREF },
++{"vlxseg8ei128.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),VtVm", MATCH_VLXSEG8EI128V, MASK_VLXSEG8EI128V, match_vd_neq_vs2_neq_vm, INSN_DREF },
++{"vsxseg8ei128.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),VtVm", MATCH_VSXSEG8EI128V, MASK_VSXSEG8EI128V, match_vd_neq_vs2_neq_vm, INSN_DREF },
++
++{"vlxseg2ei256.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),VtVm", MATCH_VLXSEG2EI256V, MASK_VLXSEG2EI256V, match_vd_neq_vs2_neq_vm, INSN_DREF },
++{"vsxseg2ei256.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),VtVm", MATCH_VSXSEG2EI256V, MASK_VSXSEG2EI256V, match_vd_neq_vs2_neq_vm, INSN_DREF },
++{"vlxseg3ei256.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),VtVm", MATCH_VLXSEG3EI256V, MASK_VLXSEG3EI256V, match_vd_neq_vs2_neq_vm, INSN_DREF },
++{"vsxseg3ei256.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),VtVm", MATCH_VSXSEG3EI256V, MASK_VSXSEG3EI256V, match_vd_neq_vs2_neq_vm, INSN_DREF },
++{"vlxseg4ei256.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),VtVm", MATCH_VLXSEG4EI256V, MASK_VLXSEG4EI256V, match_vd_neq_vs2_neq_vm, INSN_DREF },
++{"vsxseg4ei256.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),VtVm", MATCH_VSXSEG4EI256V, MASK_VSXSEG4EI256V, match_vd_neq_vs2_neq_vm, INSN_DREF },
++{"vlxseg5ei256.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),VtVm", MATCH_VLXSEG5EI256V, MASK_VLXSEG5EI256V, match_vd_neq_vs2_neq_vm, INSN_DREF },
++{"vsxseg5ei256.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),VtVm", MATCH_VSXSEG5EI256V, MASK_VSXSEG5EI256V, match_vd_neq_vs2_neq_vm, INSN_DREF },
++{"vlxseg6ei256.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),VtVm", MATCH_VLXSEG6EI256V, MASK_VLXSEG6EI256V, match_vd_neq_vs2_neq_vm, INSN_DREF },
++{"vsxseg6ei256.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),VtVm", MATCH_VSXSEG6EI256V, MASK_VSXSEG6EI256V, match_vd_neq_vs2_neq_vm, INSN_DREF },
++{"vlxseg7ei256.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),VtVm", MATCH_VLXSEG7EI256V, MASK_VLXSEG7EI256V, match_vd_neq_vs2_neq_vm, INSN_DREF },
++{"vsxseg7ei256.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),VtVm", MATCH_VSXSEG7EI256V, MASK_VSXSEG7EI256V, match_vd_neq_vs2_neq_vm, INSN_DREF },
++{"vlxseg8ei256.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),VtVm", MATCH_VLXSEG8EI256V, MASK_VLXSEG8EI256V, match_vd_neq_vs2_neq_vm, INSN_DREF },
++{"vsxseg8ei256.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),VtVm", MATCH_VSXSEG8EI256V, MASK_VSXSEG8EI256V, match_vd_neq_vs2_neq_vm, INSN_DREF },
++
++{"vlxseg2ei512.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),VtVm", MATCH_VLXSEG2EI512V, MASK_VLXSEG2EI512V, match_vd_neq_vs2_neq_vm, INSN_DREF },
++{"vsxseg2ei512.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),VtVm", MATCH_VSXSEG2EI512V, MASK_VSXSEG2EI512V, match_vd_neq_vs2_neq_vm, INSN_DREF },
++{"vlxseg3ei512.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),VtVm", MATCH_VLXSEG3EI512V, MASK_VLXSEG3EI512V, match_vd_neq_vs2_neq_vm, INSN_DREF },
++{"vsxseg3ei512.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),VtVm", MATCH_VSXSEG3EI512V, MASK_VSXSEG3EI512V, match_vd_neq_vs2_neq_vm, INSN_DREF },
++{"vlxseg4ei512.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),VtVm", MATCH_VLXSEG4EI512V, MASK_VLXSEG4EI512V, match_vd_neq_vs2_neq_vm, INSN_DREF },
++{"vsxseg4ei512.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),VtVm", MATCH_VSXSEG4EI512V, MASK_VSXSEG4EI512V, match_vd_neq_vs2_neq_vm, INSN_DREF },
++{"vlxseg5ei512.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),VtVm", MATCH_VLXSEG5EI512V, MASK_VLXSEG5EI512V, match_vd_neq_vs2_neq_vm, INSN_DREF },
++{"vsxseg5ei512.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),VtVm", MATCH_VSXSEG5EI512V, MASK_VSXSEG5EI512V, match_vd_neq_vs2_neq_vm, INSN_DREF },
++{"vlxseg6ei512.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),VtVm", MATCH_VLXSEG6EI512V, MASK_VLXSEG6EI512V, match_vd_neq_vs2_neq_vm, INSN_DREF },
++{"vsxseg6ei512.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),VtVm", MATCH_VSXSEG6EI512V, MASK_VSXSEG6EI512V, match_vd_neq_vs2_neq_vm, INSN_DREF },
++{"vlxseg7ei512.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),VtVm", MATCH_VLXSEG7EI512V, MASK_VLXSEG7EI512V, match_vd_neq_vs2_neq_vm, INSN_DREF },
++{"vsxseg7ei512.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),VtVm", MATCH_VSXSEG7EI512V, MASK_VSXSEG7EI512V, match_vd_neq_vs2_neq_vm, INSN_DREF },
++{"vlxseg8ei512.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),VtVm", MATCH_VLXSEG8EI512V, MASK_VLXSEG8EI512V, match_vd_neq_vs2_neq_vm, INSN_DREF },
++{"vsxseg8ei512.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),VtVm", MATCH_VSXSEG8EI512V, MASK_VSXSEG8EI512V, match_vd_neq_vs2_neq_vm, INSN_DREF },
++
++{"vlxseg2ei1024.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),VtVm", MATCH_VLXSEG2EI1024V, MASK_VLXSEG2EI1024V, match_vd_neq_vs2_neq_vm, INSN_DREF },
++{"vsxseg2ei1024.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),VtVm", MATCH_VSXSEG2EI1024V, MASK_VSXSEG2EI1024V, match_vd_neq_vs2_neq_vm, INSN_DREF },
++{"vlxseg3ei1024.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),VtVm", MATCH_VLXSEG3EI1024V, MASK_VLXSEG3EI1024V, match_vd_neq_vs2_neq_vm, INSN_DREF },
++{"vsxseg3ei1024.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),VtVm", MATCH_VSXSEG3EI1024V, MASK_VSXSEG3EI1024V, match_vd_neq_vs2_neq_vm, INSN_DREF },
++{"vlxseg4ei1024.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),VtVm", MATCH_VLXSEG4EI1024V, MASK_VLXSEG4EI1024V, match_vd_neq_vs2_neq_vm, INSN_DREF },
++{"vsxseg4ei1024.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),VtVm", MATCH_VSXSEG4EI1024V, MASK_VSXSEG4EI1024V, match_vd_neq_vs2_neq_vm, INSN_DREF },
++{"vlxseg5ei1024.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),VtVm", MATCH_VLXSEG5EI1024V, MASK_VLXSEG5EI1024V, match_vd_neq_vs2_neq_vm, INSN_DREF },
++{"vsxseg5ei1024.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),VtVm", MATCH_VSXSEG5EI1024V, MASK_VSXSEG5EI1024V, match_vd_neq_vs2_neq_vm, INSN_DREF },
++{"vlxseg6ei1024.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),VtVm", MATCH_VLXSEG6EI1024V, MASK_VLXSEG6EI1024V, match_vd_neq_vs2_neq_vm, INSN_DREF },
++{"vsxseg6ei1024.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),VtVm", MATCH_VSXSEG6EI1024V, MASK_VSXSEG6EI1024V, match_vd_neq_vs2_neq_vm, INSN_DREF },
++{"vlxseg7ei1024.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),VtVm", MATCH_VLXSEG7EI1024V, MASK_VLXSEG7EI1024V, match_vd_neq_vs2_neq_vm, INSN_DREF },
++{"vsxseg7ei1024.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),VtVm", MATCH_VSXSEG7EI1024V, MASK_VSXSEG7EI1024V, match_vd_neq_vs2_neq_vm, INSN_DREF },
++{"vlxseg8ei1024.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),VtVm", MATCH_VLXSEG8EI1024V, MASK_VLXSEG8EI1024V, match_vd_neq_vs2_neq_vm, INSN_DREF },
++{"vsxseg8ei1024.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),VtVm", MATCH_VSXSEG8EI1024V, MASK_VSXSEG8EI1024V, match_vd_neq_vs2_neq_vm, INSN_DREF },
++
++{"vlseg2e8ff.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s)Vm", MATCH_VLSEG2E8FFV, MASK_VLSEG2E8FFV, match_vd_neq_vm, INSN_DREF },
++{"vlseg3e8ff.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s)Vm", MATCH_VLSEG3E8FFV, MASK_VLSEG3E8FFV, match_vd_neq_vm, INSN_DREF },
++{"vlseg4e8ff.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s)Vm", MATCH_VLSEG4E8FFV, MASK_VLSEG4E8FFV, match_vd_neq_vm, INSN_DREF },
++{"vlseg5e8ff.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s)Vm", MATCH_VLSEG5E8FFV, MASK_VLSEG5E8FFV, match_vd_neq_vm, INSN_DREF },
++{"vlseg6e8ff.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s)Vm", MATCH_VLSEG6E8FFV, MASK_VLSEG6E8FFV, match_vd_neq_vm, INSN_DREF },
++{"vlseg7e8ff.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s)Vm", MATCH_VLSEG7E8FFV, MASK_VLSEG7E8FFV, match_vd_neq_vm, INSN_DREF },
++{"vlseg8e8ff.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s)Vm", MATCH_VLSEG8E8FFV, MASK_VLSEG8E8FFV, match_vd_neq_vm, INSN_DREF },
++
++{"vlseg2e16ff.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s)Vm", MATCH_VLSEG2E16FFV, MASK_VLSEG2E16FFV, match_vd_neq_vm, INSN_DREF },
++{"vlseg3e16ff.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s)Vm", MATCH_VLSEG3E16FFV, MASK_VLSEG3E16FFV, match_vd_neq_vm, INSN_DREF },
++{"vlseg4e16ff.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s)Vm", MATCH_VLSEG4E16FFV, MASK_VLSEG4E16FFV, match_vd_neq_vm, INSN_DREF },
++{"vlseg5e16ff.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s)Vm", MATCH_VLSEG5E16FFV, MASK_VLSEG5E16FFV, match_vd_neq_vm, INSN_DREF },
++{"vlseg6e16ff.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s)Vm", MATCH_VLSEG6E16FFV, MASK_VLSEG6E16FFV, match_vd_neq_vm, INSN_DREF },
++{"vlseg7e16ff.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s)Vm", MATCH_VLSEG7E16FFV, MASK_VLSEG7E16FFV, match_vd_neq_vm, INSN_DREF },
++{"vlseg8e16ff.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s)Vm", MATCH_VLSEG8E16FFV, MASK_VLSEG8E16FFV, match_vd_neq_vm, INSN_DREF },
++
++{"vlseg2e32ff.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s)Vm", MATCH_VLSEG2E32FFV, MASK_VLSEG2E32FFV, match_vd_neq_vm, INSN_DREF },
++{"vlseg3e32ff.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s)Vm", MATCH_VLSEG3E32FFV, MASK_VLSEG3E32FFV, match_vd_neq_vm, INSN_DREF },
++{"vlseg4e32ff.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s)Vm", MATCH_VLSEG4E32FFV, MASK_VLSEG4E32FFV, match_vd_neq_vm, INSN_DREF },
++{"vlseg5e32ff.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s)Vm", MATCH_VLSEG5E32FFV, MASK_VLSEG5E32FFV, match_vd_neq_vm, INSN_DREF },
++{"vlseg6e32ff.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s)Vm", MATCH_VLSEG6E32FFV, MASK_VLSEG6E32FFV, match_vd_neq_vm, INSN_DREF },
++{"vlseg7e32ff.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s)Vm", MATCH_VLSEG7E32FFV, MASK_VLSEG7E32FFV, match_vd_neq_vm, INSN_DREF },
++{"vlseg8e32ff.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s)Vm", MATCH_VLSEG8E32FFV, MASK_VLSEG8E32FFV, match_vd_neq_vm, INSN_DREF },
++
++{"vlseg2e64ff.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s)Vm", MATCH_VLSEG2E64FFV, MASK_VLSEG2E64FFV, match_vd_neq_vm, INSN_DREF },
++{"vlseg3e64ff.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s)Vm", MATCH_VLSEG3E64FFV, MASK_VLSEG3E64FFV, match_vd_neq_vm, INSN_DREF },
++{"vlseg4e64ff.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s)Vm", MATCH_VLSEG4E64FFV, MASK_VLSEG4E64FFV, match_vd_neq_vm, INSN_DREF },
++{"vlseg5e64ff.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s)Vm", MATCH_VLSEG5E64FFV, MASK_VLSEG5E64FFV, match_vd_neq_vm, INSN_DREF },
++{"vlseg6e64ff.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s)Vm", MATCH_VLSEG6E64FFV, MASK_VLSEG6E64FFV, match_vd_neq_vm, INSN_DREF },
++{"vlseg7e64ff.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s)Vm", MATCH_VLSEG7E64FFV, MASK_VLSEG7E64FFV, match_vd_neq_vm, INSN_DREF },
++{"vlseg8e64ff.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s)Vm", MATCH_VLSEG8E64FFV, MASK_VLSEG8E64FFV, match_vd_neq_vm, INSN_DREF },
++
++{"vlseg2e128ff.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s)Vm", MATCH_VLSEG2E128FFV, MASK_VLSEG2E128FFV, match_vd_neq_vm, INSN_DREF },
++{"vlseg3e128ff.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s)Vm", MATCH_VLSEG3E128FFV, MASK_VLSEG3E128FFV, match_vd_neq_vm, INSN_DREF },
++{"vlseg4e128ff.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s)Vm", MATCH_VLSEG4E128FFV, MASK_VLSEG4E128FFV, match_vd_neq_vm, INSN_DREF },
++{"vlseg5e128ff.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s)Vm", MATCH_VLSEG5E128FFV, MASK_VLSEG5E128FFV, match_vd_neq_vm, INSN_DREF },
++{"vlseg6e128ff.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s)Vm", MATCH_VLSEG6E128FFV, MASK_VLSEG6E128FFV, match_vd_neq_vm, INSN_DREF },
++{"vlseg7e128ff.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s)Vm", MATCH_VLSEG7E128FFV, MASK_VLSEG7E128FFV, match_vd_neq_vm, INSN_DREF },
++{"vlseg8e128ff.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s)Vm", MATCH_VLSEG8E128FFV, MASK_VLSEG8E128FFV, match_vd_neq_vm, INSN_DREF },
++
++{"vlseg2e256ff.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s)Vm", MATCH_VLSEG2E256FFV, MASK_VLSEG2E256FFV, match_vd_neq_vm, INSN_DREF },
++{"vlseg3e256ff.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s)Vm", MATCH_VLSEG3E256FFV, MASK_VLSEG3E256FFV, match_vd_neq_vm, INSN_DREF },
++{"vlseg4e256ff.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s)Vm", MATCH_VLSEG4E256FFV, MASK_VLSEG4E256FFV, match_vd_neq_vm, INSN_DREF },
++{"vlseg5e256ff.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s)Vm", MATCH_VLSEG5E256FFV, MASK_VLSEG5E256FFV, match_vd_neq_vm, INSN_DREF },
++{"vlseg6e256ff.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s)Vm", MATCH_VLSEG6E256FFV, MASK_VLSEG6E256FFV, match_vd_neq_vm, INSN_DREF },
++{"vlseg7e256ff.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s)Vm", MATCH_VLSEG7E256FFV, MASK_VLSEG7E256FFV, match_vd_neq_vm, INSN_DREF },
++{"vlseg8e256ff.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s)Vm", MATCH_VLSEG8E256FFV, MASK_VLSEG8E256FFV, match_vd_neq_vm, INSN_DREF },
++
++{"vlseg2e512ff.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s)Vm", MATCH_VLSEG2E512FFV, MASK_VLSEG2E512FFV, match_vd_neq_vm, INSN_DREF },
++{"vlseg3e512ff.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s)Vm", MATCH_VLSEG3E512FFV, MASK_VLSEG3E512FFV, match_vd_neq_vm, INSN_DREF },
++{"vlseg4e512ff.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s)Vm", MATCH_VLSEG4E512FFV, MASK_VLSEG4E512FFV, match_vd_neq_vm, INSN_DREF },
++{"vlseg5e512ff.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s)Vm", MATCH_VLSEG5E512FFV, MASK_VLSEG5E512FFV, match_vd_neq_vm, INSN_DREF },
++{"vlseg6e512ff.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s)Vm", MATCH_VLSEG6E512FFV, MASK_VLSEG6E512FFV, match_vd_neq_vm, INSN_DREF },
++{"vlseg7e512ff.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s)Vm", MATCH_VLSEG7E512FFV, MASK_VLSEG7E512FFV, match_vd_neq_vm, INSN_DREF },
++{"vlseg8e512ff.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s)Vm", MATCH_VLSEG8E512FFV, MASK_VLSEG8E512FFV, match_vd_neq_vm, INSN_DREF },
++
++{"vlseg2e1024ff.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s)Vm", MATCH_VLSEG2E1024FFV, MASK_VLSEG2E1024FFV, match_vd_neq_vm, INSN_DREF },
++{"vlseg3e1024ff.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s)Vm", MATCH_VLSEG3E1024FFV, MASK_VLSEG3E1024FFV, match_vd_neq_vm, INSN_DREF },
++{"vlseg4e1024ff.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s)Vm", MATCH_VLSEG4E1024FFV, MASK_VLSEG4E1024FFV, match_vd_neq_vm, INSN_DREF },
++{"vlseg5e1024ff.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s)Vm", MATCH_VLSEG5E1024FFV, MASK_VLSEG5E1024FFV, match_vd_neq_vm, INSN_DREF },
++{"vlseg6e1024ff.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s)Vm", MATCH_VLSEG6E1024FFV, MASK_VLSEG6E1024FFV, match_vd_neq_vm, INSN_DREF },
++{"vlseg7e1024ff.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s)Vm", MATCH_VLSEG7E1024FFV, MASK_VLSEG7E1024FFV, match_vd_neq_vm, INSN_DREF },
++{"vlseg8e1024ff.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s)Vm", MATCH_VLSEG8E1024FFV, MASK_VLSEG8E1024FFV, match_vd_neq_vm, INSN_DREF },
++
++{"vl1r.v",  0, INSN_CLASS_V,  "Vd,0(s)", MATCH_VL1RV, MASK_VL1RV, match_opcode, INSN_DREF },
++{"vs1r.v",  0, INSN_CLASS_V,  "Vd,0(s)", MATCH_VS1RV, MASK_VS1RV, match_opcode, INSN_DREF },
++
++{"vamoaddei8.v",   0, INSN_CLASS_V_OR_ZVAMO,  "Ve,0(s),Vt,VfVm", MATCH_VAMOADDEI8V, MASK_VAMOADDEI8V, match_opcode, INSN_DREF},
++{"vamoswapei8.v",  0, INSN_CLASS_V_OR_ZVAMO,  "Ve,0(s),Vt,VfVm", MATCH_VAMOSWAPEI8V, MASK_VAMOSWAPEI8V, match_opcode, INSN_DREF},
++{"vamoxorei8.v",   0, INSN_CLASS_V_OR_ZVAMO,  "Ve,0(s),Vt,VfVm", MATCH_VAMOXOREI8V, MASK_VAMOXOREI8V, match_opcode, INSN_DREF},
++{"vamoandei8.v",   0, INSN_CLASS_V_OR_ZVAMO,  "Ve,0(s),Vt,VfVm", MATCH_VAMOANDEI8V, MASK_VAMOANDEI8V, match_opcode, INSN_DREF},
++{"vamoorei8.v",    0, INSN_CLASS_V_OR_ZVAMO,  "Ve,0(s),Vt,VfVm", MATCH_VAMOOREI8V, MASK_VAMOOREI8V, match_opcode, INSN_DREF},
++{"vamominei8.v",   0, INSN_CLASS_V_OR_ZVAMO,  "Ve,0(s),Vt,VfVm", MATCH_VAMOMINEI8V, MASK_VAMOMINEI8V, match_opcode, INSN_DREF},
++{"vamomaxei8.v",   0, INSN_CLASS_V_OR_ZVAMO,  "Ve,0(s),Vt,VfVm", MATCH_VAMOMAXEI8V, MASK_VAMOMAXEI8V, match_opcode, INSN_DREF},
++{"vamominuei8.v",  0, INSN_CLASS_V_OR_ZVAMO,  "Ve,0(s),Vt,VfVm", MATCH_VAMOMINUEI8V, MASK_VAMOMINUEI8V, match_opcode, INSN_DREF},
++{"vamomaxuei8.v",  0, INSN_CLASS_V_OR_ZVAMO,  "Ve,0(s),Vt,VfVm", MATCH_VAMOMAXUEI8V, MASK_VAMOMAXUEI8V, match_opcode, INSN_DREF},
++
++{"vamoaddei16.v",   0, INSN_CLASS_V_OR_ZVAMO,  "Ve,0(s),Vt,VfVm", MATCH_VAMOADDEI16V, MASK_VAMOADDEI16V, match_opcode, INSN_DREF},
++{"vamoswapei16.v",  0, INSN_CLASS_V_OR_ZVAMO,  "Ve,0(s),Vt,VfVm", MATCH_VAMOSWAPEI16V, MASK_VAMOSWAPEI16V, match_opcode, INSN_DREF},
++{"vamoxorei16.v",   0, INSN_CLASS_V_OR_ZVAMO,  "Ve,0(s),Vt,VfVm", MATCH_VAMOXOREI16V, MASK_VAMOXOREI16V, match_opcode, INSN_DREF},
++{"vamoandei16.v",   0, INSN_CLASS_V_OR_ZVAMO,  "Ve,0(s),Vt,VfVm", MATCH_VAMOANDEI16V, MASK_VAMOANDEI16V, match_opcode, INSN_DREF},
++{"vamoorei16.v",    0, INSN_CLASS_V_OR_ZVAMO,  "Ve,0(s),Vt,VfVm", MATCH_VAMOOREI16V, MASK_VAMOOREI16V, match_opcode, INSN_DREF},
++{"vamominei16.v",   0, INSN_CLASS_V_OR_ZVAMO,  "Ve,0(s),Vt,VfVm", MATCH_VAMOMINEI16V, MASK_VAMOMINEI16V, match_opcode, INSN_DREF},
++{"vamomaxei16.v",   0, INSN_CLASS_V_OR_ZVAMO,  "Ve,0(s),Vt,VfVm", MATCH_VAMOMAXEI16V, MASK_VAMOMAXEI16V, match_opcode, INSN_DREF},
++{"vamominuei16.v",  0, INSN_CLASS_V_OR_ZVAMO,  "Ve,0(s),Vt,VfVm", MATCH_VAMOMINUEI16V, MASK_VAMOMINUEI16V, match_opcode, INSN_DREF},
++{"vamomaxuei16.v",  0, INSN_CLASS_V_OR_ZVAMO,  "Ve,0(s),Vt,VfVm", MATCH_VAMOMAXUEI16V, MASK_VAMOMAXUEI16V, match_opcode, INSN_DREF},
++
++{"vamoaddei32.v",   0, INSN_CLASS_V_OR_ZVAMO,  "Ve,0(s),Vt,VfVm", MATCH_VAMOADDEI32V, MASK_VAMOADDEI32V, match_opcode, INSN_DREF},
++{"vamoswapei32.v",  0, INSN_CLASS_V_OR_ZVAMO,  "Ve,0(s),Vt,VfVm", MATCH_VAMOSWAPEI32V, MASK_VAMOSWAPEI32V, match_opcode, INSN_DREF},
++{"vamoxorei32.v",   0, INSN_CLASS_V_OR_ZVAMO,  "Ve,0(s),Vt,VfVm", MATCH_VAMOXOREI32V, MASK_VAMOXOREI32V, match_opcode, INSN_DREF},
++{"vamoandei32.v",   0, INSN_CLASS_V_OR_ZVAMO,  "Ve,0(s),Vt,VfVm", MATCH_VAMOANDEI32V, MASK_VAMOANDEI32V, match_opcode, INSN_DREF},
++{"vamoorei32.v",    0, INSN_CLASS_V_OR_ZVAMO,  "Ve,0(s),Vt,VfVm", MATCH_VAMOOREI32V, MASK_VAMOOREI32V, match_opcode, INSN_DREF},
++{"vamominei32.v",   0, INSN_CLASS_V_OR_ZVAMO,  "Ve,0(s),Vt,VfVm", MATCH_VAMOMINEI32V, MASK_VAMOMINEI32V, match_opcode, INSN_DREF},
++{"vamomaxei32.v",   0, INSN_CLASS_V_OR_ZVAMO,  "Ve,0(s),Vt,VfVm", MATCH_VAMOMAXEI32V, MASK_VAMOMAXEI32V, match_opcode, INSN_DREF},
++{"vamominuei32.v",  0, INSN_CLASS_V_OR_ZVAMO,  "Ve,0(s),Vt,VfVm", MATCH_VAMOMINUEI32V, MASK_VAMOMINUEI32V, match_opcode, INSN_DREF},
++{"vamomaxuei32.v",  0, INSN_CLASS_V_OR_ZVAMO,  "Ve,0(s),Vt,VfVm", MATCH_VAMOMAXUEI32V, MASK_VAMOMAXUEI32V, match_opcode, INSN_DREF},
++
++{"vamoaddei64.v",   0, INSN_CLASS_V_OR_ZVAMO,  "Ve,0(s),Vt,VfVm", MATCH_VAMOADDEI64V, MASK_VAMOADDEI64V, match_opcode, INSN_DREF},
++{"vamoswapei64.v",  0, INSN_CLASS_V_OR_ZVAMO,  "Ve,0(s),Vt,VfVm", MATCH_VAMOSWAPEI64V, MASK_VAMOSWAPEI64V, match_opcode, INSN_DREF},
++{"vamoxorei64.v",   0, INSN_CLASS_V_OR_ZVAMO,  "Ve,0(s),Vt,VfVm", MATCH_VAMOXOREI64V, MASK_VAMOXOREI64V, match_opcode, INSN_DREF},
++{"vamoandei64.v",   0, INSN_CLASS_V_OR_ZVAMO,  "Ve,0(s),Vt,VfVm", MATCH_VAMOANDEI64V, MASK_VAMOANDEI64V, match_opcode, INSN_DREF},
++{"vamoorei64.v",    0, INSN_CLASS_V_OR_ZVAMO,  "Ve,0(s),Vt,VfVm", MATCH_VAMOOREI64V, MASK_VAMOOREI64V, match_opcode, INSN_DREF},
++{"vamominei64.v",   0, INSN_CLASS_V_OR_ZVAMO,  "Ve,0(s),Vt,VfVm", MATCH_VAMOMINEI64V, MASK_VAMOMINEI64V, match_opcode, INSN_DREF},
++{"vamomaxei64.v",   0, INSN_CLASS_V_OR_ZVAMO,  "Ve,0(s),Vt,VfVm", MATCH_VAMOMAXEI64V, MASK_VAMOMAXEI64V, match_opcode, INSN_DREF},
++{"vamominuei64.v",  0, INSN_CLASS_V_OR_ZVAMO,  "Ve,0(s),Vt,VfVm", MATCH_VAMOMINUEI64V, MASK_VAMOMINUEI64V, match_opcode, INSN_DREF},
++{"vamomaxuei64.v",  0, INSN_CLASS_V_OR_ZVAMO,  "Ve,0(s),Vt,VfVm", MATCH_VAMOMAXUEI64V, MASK_VAMOMAXUEI64V, match_opcode, INSN_DREF},
++
++{"vadd.vv",    0, INSN_CLASS_V,  "Vd,Vt,VsVm", MATCH_VADDVV, MASK_VADDVV, match_opcode, 0 },
++{"vadd.vx",    0, INSN_CLASS_V,  "Vd,Vt,sVm", MATCH_VADDVX, MASK_VADDVX, match_opcode, 0 },
++{"vadd.vi",    0, INSN_CLASS_V,  "Vd,Vt,ViVm", MATCH_VADDVI, MASK_VADDVI, match_opcode, 0 },
++{"vsub.vv",    0, INSN_CLASS_V,  "Vd,Vt,VsVm", MATCH_VSUBVV, MASK_VSUBVV, match_opcode, 0 },
++{"vsub.vx",    0, INSN_CLASS_V,  "Vd,Vt,sVm", MATCH_VSUBVX, MASK_VSUBVX, match_opcode, 0 },
++{"vrsub.vx",   0, INSN_CLASS_V,  "Vd,Vt,sVm", MATCH_VRSUBVX, MASK_VRSUBVX, match_opcode, 0 },
++{"vrsub.vi",   0, INSN_CLASS_V,  "Vd,Vt,ViVm", MATCH_VRSUBVI, MASK_VRSUBVI, match_opcode, 0 },
++
++{"vwcvt.x.x.v",  0, INSN_CLASS_V,  "Vd,VtVm", MATCH_VWCVTXXV, MASK_VWCVTXXV, match_widen_vd_neq_vs2_neq_vm, INSN_ALIAS },
++{"vwcvtu.x.x.v", 0, INSN_CLASS_V,  "Vd,VtVm", MATCH_VWCVTUXXV, MASK_VWCVTUXXV, match_widen_vd_neq_vs2_neq_vm, INSN_ALIAS },
++
++{"vwaddu.vv",  0, INSN_CLASS_V,  "Vd,Vt,VsVm", MATCH_VWADDUVV, MASK_VWADDUVV, match_widen_vd_neq_vs1_neq_vs2_neq_vm, 0 },
++{"vwaddu.vx",  0, INSN_CLASS_V,  "Vd,Vt,sVm", MATCH_VWADDUVX, MASK_VWADDUVX, match_widen_vd_neq_vs2_neq_vm, 0 },
++{"vwsubu.vv",  0, INSN_CLASS_V,  "Vd,Vt,VsVm", MATCH_VWSUBUVV, MASK_VWSUBUVV, match_widen_vd_neq_vs1_neq_vs2_neq_vm, 0 },
++{"vwsubu.vx",  0, INSN_CLASS_V,  "Vd,Vt,sVm", MATCH_VWSUBUVX, MASK_VWSUBUVX, match_widen_vd_neq_vs2_neq_vm, 0 },
++{"vwadd.vv",   0, INSN_CLASS_V,  "Vd,Vt,VsVm", MATCH_VWADDVV, MASK_VWADDVV, match_widen_vd_neq_vs1_neq_vs2_neq_vm, 0 },
++{"vwadd.vx",   0, INSN_CLASS_V,  "Vd,Vt,sVm", MATCH_VWADDVX, MASK_VWADDVX, match_widen_vd_neq_vs2_neq_vm, 0 },
++{"vwsub.vv",   0, INSN_CLASS_V,  "Vd,Vt,VsVm", MATCH_VWSUBVV, MASK_VWSUBVV, match_widen_vd_neq_vs1_neq_vs2_neq_vm, 0 },
++{"vwsub.vx",   0, INSN_CLASS_V,  "Vd,Vt,sVm", MATCH_VWSUBVX, MASK_VWSUBVX, match_widen_vd_neq_vs2_neq_vm, 0 },
++{"vwaddu.wv",  0, INSN_CLASS_V,  "Vd,Vt,VsVm", MATCH_VWADDUWV, MASK_VWADDUWV, match_widen_vd_neq_vs1_neq_vm, 0 },
++{"vwaddu.wx",  0, INSN_CLASS_V,  "Vd,Vt,sVm", MATCH_VWADDUWX, MASK_VWADDUWX, match_widen_vd_neq_vm, 0 },
++{"vwsubu.wv",  0, INSN_CLASS_V,  "Vd,Vt,VsVm", MATCH_VWSUBUWV, MASK_VWSUBUWV, match_widen_vd_neq_vs1_neq_vm, 0 },
++{"vwsubu.wx",  0, INSN_CLASS_V,  "Vd,Vt,sVm", MATCH_VWSUBUWX, MASK_VWSUBUWX, match_widen_vd_neq_vm, 0 },
++{"vwadd.wv",   0, INSN_CLASS_V,  "Vd,Vt,VsVm", MATCH_VWADDWV, MASK_VWADDWV, match_widen_vd_neq_vs1_neq_vm, 0 },
++{"vwadd.wx",   0, INSN_CLASS_V,  "Vd,Vt,sVm", MATCH_VWADDWX, MASK_VWADDWX, match_widen_vd_neq_vm, 0 },
++{"vwsub.wv",   0, INSN_CLASS_V,  "Vd,Vt,VsVm", MATCH_VWSUBWV, MASK_VWSUBWV, match_widen_vd_neq_vs1_neq_vm, 0 },
++{"vwsub.wx",   0, INSN_CLASS_V,  "Vd,Vt,sVm", MATCH_VWSUBWX, MASK_VWSUBWX, match_widen_vd_neq_vm, 0 },
++
++{"vzext.vf2",  0, INSN_CLASS_V,  "Vd,VtVm", MATCH_VZEXT_VF2, MASK_VZEXT_VF2, match_opcode, 0 },
++{"vsext.vf2",  0, INSN_CLASS_V,  "Vd,VtVm", MATCH_VSEXT_VF2, MASK_VSEXT_VF2, match_opcode, 0 },
++{"vzext.vf4",  0, INSN_CLASS_V,  "Vd,VtVm", MATCH_VZEXT_VF4, MASK_VZEXT_VF4, match_opcode, 0 },
++{"vsext.vf4",  0, INSN_CLASS_V,  "Vd,VtVm", MATCH_VSEXT_VF4, MASK_VSEXT_VF4, match_opcode, 0 },
++{"vzext.vf8",  0, INSN_CLASS_V,  "Vd,VtVm", MATCH_VZEXT_VF8, MASK_VZEXT_VF8, match_opcode, 0 },
++{"vsext.vf8",  0, INSN_CLASS_V,  "Vd,VtVm", MATCH_VSEXT_VF8, MASK_VSEXT_VF8, match_opcode, 0 },
++
++{"vadc.vvm",   0, INSN_CLASS_V,  "Vd,Vt,Vs,V0", MATCH_VADCVVM, MASK_VADCVVM, match_opcode, 0 },
++{"vadc.vxm",   0, INSN_CLASS_V,  "Vd,Vt,s,V0", MATCH_VADCVXM, MASK_VADCVXM, match_opcode, 0 },
++{"vadc.vim",   0, INSN_CLASS_V,  "Vd,Vt,Vi,V0", MATCH_VADCVIM, MASK_VADCVIM, match_opcode, 0 },
++{"vmadc.vvm",  0, INSN_CLASS_V,  "Vd,Vt,Vs,V0", MATCH_VMADCVVM, MASK_VMADCVVM, match_opcode, 0 },
++{"vmadc.vxm",  0, INSN_CLASS_V,  "Vd,Vt,s,V0", MATCH_VMADCVXM, MASK_VMADCVXM, match_opcode, 0 },
++{"vmadc.vim",  0, INSN_CLASS_V,  "Vd,Vt,Vi,V0", MATCH_VMADCVIM, MASK_VMADCVIM, match_opcode, 0 },
++{"vmadc.vv",   0, INSN_CLASS_V,  "Vd,Vt,Vs", MATCH_VMADCVV, MASK_VMADCVV, match_opcode, 0 },
++{"vmadc.vx",   0, INSN_CLASS_V,  "Vd,Vt,s", MATCH_VMADCVX, MASK_VMADCVX, match_opcode, 0 },
++{"vmadc.vi",   0, INSN_CLASS_V,  "Vd,Vt,Vi", MATCH_VMADCVI, MASK_VMADCVI, match_opcode, 0 },
++{"vsbc.vvm",   0, INSN_CLASS_V,  "Vd,Vt,Vs,V0", MATCH_VSBCVVM, MASK_VSBCVVM, match_opcode, 0 },
++{"vsbc.vxm",   0, INSN_CLASS_V,  "Vd,Vt,s,V0", MATCH_VSBCVXM, MASK_VSBCVXM, match_opcode, 0 },
++{"vmsbc.vvm",  0, INSN_CLASS_V,  "Vd,Vt,Vs,V0", MATCH_VMSBCVVM, MASK_VMSBCVVM, match_opcode, 0 },
++{"vmsbc.vxm",  0, INSN_CLASS_V,  "Vd,Vt,s,V0", MATCH_VMSBCVXM, MASK_VMSBCVXM, match_opcode, 0 },
++{"vmsbc.vv",   0, INSN_CLASS_V,  "Vd,Vt,Vs", MATCH_VMSBCVV, MASK_VMSBCVV, match_opcode, 0 },
++{"vmsbc.vx",   0, INSN_CLASS_V,  "Vd,Vt,s", MATCH_VMSBCVX, MASK_VMSBCVX, match_opcode, 0 },
++
++{"vnot.v",     0, INSN_CLASS_V,  "Vd,VtVm", MATCH_VNOTV, MASK_VNOTV, match_opcode, INSN_ALIAS },
++
++{"vand.vv",    0, INSN_CLASS_V,  "Vd,Vt,VsVm", MATCH_VANDVV, MASK_VANDVV, match_opcode, 0 },
++{"vand.vx",    0, INSN_CLASS_V,  "Vd,Vt,sVm", MATCH_VANDVX, MASK_VANDVX, match_opcode, 0 },
++{"vand.vi",    0, INSN_CLASS_V,  "Vd,Vt,ViVm", MATCH_VANDVI, MASK_VANDVI, match_opcode, 0 },
++{"vor.vv",     0, INSN_CLASS_V,  "Vd,Vt,VsVm", MATCH_VORVV, MASK_VORVV, match_opcode, 0 },
++{"vor.vx",     0, INSN_CLASS_V,  "Vd,Vt,sVm", MATCH_VORVX, MASK_VORVX, match_opcode, 0 },
++{"vor.vi",     0, INSN_CLASS_V,  "Vd,Vt,ViVm", MATCH_VORVI, MASK_VORVI, match_opcode, 0 },
++{"vxor.vv",    0, INSN_CLASS_V,  "Vd,Vt,VsVm", MATCH_VXORVV, MASK_VXORVV, match_opcode, 0 },
++{"vxor.vx",    0, INSN_CLASS_V,  "Vd,Vt,sVm", MATCH_VXORVX, MASK_VXORVX, match_opcode, 0 },
++{"vxor.vi",    0, INSN_CLASS_V,  "Vd,Vt,ViVm", MATCH_VXORVI, MASK_VXORVI, match_opcode, 0 },
++
++{"vsll.vv",    0, INSN_CLASS_V,  "Vd,Vt,VsVm", MATCH_VSLLVV, MASK_VSLLVV, match_opcode, 0 },
++{"vsll.vx",    0, INSN_CLASS_V,  "Vd,Vt,sVm", MATCH_VSLLVX, MASK_VSLLVX, match_opcode, 0 },
++{"vsll.vi",    0, INSN_CLASS_V,  "Vd,Vt,VjVm", MATCH_VSLLVI, MASK_VSLLVI, match_opcode, 0 },
++{"vsrl.vv",    0, INSN_CLASS_V,  "Vd,Vt,VsVm", MATCH_VSRLVV, MASK_VSRLVV, match_opcode, 0 },
++{"vsrl.vx",    0, INSN_CLASS_V,  "Vd,Vt,sVm", MATCH_VSRLVX, MASK_VSRLVX, match_opcode, 0 },
++{"vsrl.vi",    0, INSN_CLASS_V,  "Vd,Vt,VjVm", MATCH_VSRLVI, MASK_VSRLVI, match_opcode, 0 },
++{"vsra.vv",    0, INSN_CLASS_V,  "Vd,Vt,VsVm", MATCH_VSRAVV, MASK_VSRAVV, match_opcode, 0 },
++{"vsra.vx",    0, INSN_CLASS_V,  "Vd,Vt,sVm", MATCH_VSRAVX, MASK_VSRAVX, match_opcode, 0 },
++{"vsra.vi",    0, INSN_CLASS_V,  "Vd,Vt,VjVm", MATCH_VSRAVI, MASK_VSRAVI, match_opcode, 0 },
++
++{"vnsrl.wv",   0, INSN_CLASS_V,  "Vd,Vt,VsVm", MATCH_VNSRLWV, MASK_VNSRLWV, match_narrow_vd_neq_vs2, 0 },
++{"vnsrl.wx",   0, INSN_CLASS_V,  "Vd,Vt,sVm", MATCH_VNSRLWX, MASK_VNSRLWX, match_narrow_vd_neq_vs2, 0 },
++{"vnsrl.wi",   0, INSN_CLASS_V,  "Vd,Vt,VjVm", MATCH_VNSRLWI, MASK_VNSRLWI, match_narrow_vd_neq_vs2, 0 },
++{"vnsra.wv",   0, INSN_CLASS_V,  "Vd,Vt,VsVm", MATCH_VNSRAWV, MASK_VNSRAWV, match_narrow_vd_neq_vs2, 0 },
++{"vnsra.wx",   0, INSN_CLASS_V,  "Vd,Vt,sVm", MATCH_VNSRAWX, MASK_VNSRAWX, match_narrow_vd_neq_vs2, 0 },
++{"vnsra.wi",   0, INSN_CLASS_V,  "Vd,Vt,VjVm", MATCH_VNSRAWI, MASK_VNSRAWI, match_narrow_vd_neq_vs2, 0 },
++
++{"vmseq.vv",   0, INSN_CLASS_V,  "Vd,Vt,VsVm", MATCH_VMSEQVV, MASK_VMSEQVV, match_opcode, 0 },
++{"vmseq.vx",   0, INSN_CLASS_V,  "Vd,Vt,sVm", MATCH_VMSEQVX, MASK_VMSEQVX, match_opcode, 0 },
++{"vmseq.vi",   0, INSN_CLASS_V,  "Vd,Vt,ViVm", MATCH_VMSEQVI, MASK_VMSEQVI, match_opcode, 0 },
++{"vmsne.vv",   0, INSN_CLASS_V,  "Vd,Vt,VsVm", MATCH_VMSNEVV, MASK_VMSNEVV, match_opcode, 0 },
++{"vmsne.vx",   0, INSN_CLASS_V,  "Vd,Vt,sVm", MATCH_VMSNEVX, MASK_VMSNEVX, match_opcode, 0 },
++{"vmsne.vi",   0, INSN_CLASS_V,  "Vd,Vt,ViVm", MATCH_VMSNEVI, MASK_VMSNEVI, match_opcode, 0 },
++{"vmsltu.vv",  0, INSN_CLASS_V,  "Vd,Vt,VsVm", MATCH_VMSLTUVV, MASK_VMSLTUVV, match_opcode, 0 },
++{"vmsltu.vx",  0, INSN_CLASS_V,  "Vd,Vt,sVm", MATCH_VMSLTUVX, MASK_VMSLTUVX, match_opcode, 0 },
++{"vmslt.vv",   0, INSN_CLASS_V,  "Vd,Vt,VsVm", MATCH_VMSLTVV, MASK_VMSLTVV, match_opcode, 0 },
++{"vmslt.vx",   0, INSN_CLASS_V,  "Vd,Vt,sVm", MATCH_VMSLTVX, MASK_VMSLTVX, match_opcode, 0 },
++{"vmsleu.vv",  0, INSN_CLASS_V,  "Vd,Vt,VsVm", MATCH_VMSLEUVV, MASK_VMSLEUVV, match_opcode, 0 },
++{"vmsleu.vx",  0, INSN_CLASS_V,  "Vd,Vt,sVm", MATCH_VMSLEUVX, MASK_VMSLEUVX, match_opcode, 0 },
++{"vmsleu.vi",  0, INSN_CLASS_V,  "Vd,Vt,ViVm", MATCH_VMSLEUVI, MASK_VMSLEUVI, match_opcode, 0 },
++{"vmsle.vv",   0, INSN_CLASS_V,  "Vd,Vt,VsVm", MATCH_VMSLEVV, MASK_VMSLEVV, match_opcode, 0 },
++{"vmsle.vx",   0, INSN_CLASS_V,  "Vd,Vt,sVm", MATCH_VMSLEVX, MASK_VMSLEVX, match_opcode, 0 },
++{"vmsle.vi",   0, INSN_CLASS_V,  "Vd,Vt,ViVm", MATCH_VMSLEVI, MASK_VMSLEVI, match_opcode, 0 },
++{"vmsgtu.vx",  0, INSN_CLASS_V,  "Vd,Vt,sVm", MATCH_VMSGTUVX, MASK_VMSGTUVX, match_opcode, 0 },
++{"vmsgtu.vi",  0, INSN_CLASS_V,  "Vd,Vt,ViVm", MATCH_VMSGTUVI, MASK_VMSGTUVI, match_opcode, 0 },
++{"vmsgt.vx",   0, INSN_CLASS_V,  "Vd,Vt,sVm", MATCH_VMSGTVX, MASK_VMSGTVX, match_opcode, 0 },
++{"vmsgt.vi",   0, INSN_CLASS_V,  "Vd,Vt,ViVm", MATCH_VMSGTVI, MASK_VMSGTVI, match_opcode, 0 },
++
++/* These aliases are for assembly but not disassembly.  */
++{"vmsgt.vv",   0, INSN_CLASS_V,  "Vd,Vs,VtVm", MATCH_VMSLTVV, MASK_VMSLTVV, match_opcode, INSN_ALIAS },
++{"vmsgtu.vv",  0, INSN_CLASS_V,  "Vd,Vs,VtVm", MATCH_VMSLTUVV, MASK_VMSLTUVV, match_opcode, INSN_ALIAS },
++{"vmsge.vv",   0, INSN_CLASS_V,  "Vd,Vs,VtVm", MATCH_VMSLEVV, MASK_VMSLEVV, match_opcode, INSN_ALIAS },
++{"vmsgeu.vv",  0, INSN_CLASS_V,  "Vd,Vs,VtVm", MATCH_VMSLEUVV, MASK_VMSLEUVV, match_opcode, INSN_ALIAS },
++{"vmslt.vi",   0, INSN_CLASS_V,  "Vd,Vt,VkVm", MATCH_VMSLEVI, MASK_VMSLEVI, match_opcode, INSN_ALIAS },
++{"vmsltu.vi",  0, INSN_CLASS_V,  "Vd,Vu,0Vm", MATCH_VMSNEVV, MASK_VMSNEVV, match_opcode, INSN_ALIAS },
++{"vmsltu.vi",  0, INSN_CLASS_V,  "Vd,Vt,VkVm", MATCH_VMSLEUVI, MASK_VMSLEUVI, match_opcode, INSN_ALIAS },
++{"vmsge.vi",   0, INSN_CLASS_V,  "Vd,Vt,VkVm", MATCH_VMSGTVI, MASK_VMSGTVI, match_opcode, INSN_ALIAS },
++{"vmsgeu.vi",  0, INSN_CLASS_V,  "Vd,Vu,0Vm", MATCH_VMSEQVV, MASK_VMSEQVV, match_opcode, INSN_ALIAS },
++{"vmsgeu.vi",  0, INSN_CLASS_V,  "Vd,Vt,VkVm", MATCH_VMSGTUVI, MASK_VMSGTUVI, match_opcode, INSN_ALIAS },
++
++{"vmsge.vx",   0, INSN_CLASS_V, "Vd,Vt,sVm", 0, (int) M_VMSGE, match_never, INSN_MACRO },
++{"vmsge.vx",   0, INSN_CLASS_V, "Vd,Vt,s,VM,VT", 0, (int) M_VMSGE, match_never, INSN_MACRO },
++{"vmsgeu.vx",  0, INSN_CLASS_V, "Vd,Vt,sVm", 0, (int) M_VMSGEU, match_never, INSN_MACRO },
++{"vmsgeu.vx",  0, INSN_CLASS_V, "Vd,Vt,s,VM,VT", 0, (int) M_VMSGEU, match_never, INSN_MACRO },
++
++{"vminu.vv",   0, INSN_CLASS_V,  "Vd,Vt,VsVm", MATCH_VMINUVV, MASK_VMINUVV, match_opcode, 0},
++{"vminu.vx",   0, INSN_CLASS_V,  "Vd,Vt,sVm", MATCH_VMINUVX, MASK_VMINUVX, match_opcode, 0},
++{"vmin.vv",    0, INSN_CLASS_V,  "Vd,Vt,VsVm", MATCH_VMINVV, MASK_VMINVV, match_opcode, 0},
++{"vmin.vx",    0, INSN_CLASS_V,  "Vd,Vt,sVm", MATCH_VMINVX, MASK_VMINVX, match_opcode, 0},
++{"vmaxu.vv",   0, INSN_CLASS_V,  "Vd,Vt,VsVm", MATCH_VMAXUVV, MASK_VMAXUVV, match_opcode, 0},
++{"vmaxu.vx",   0, INSN_CLASS_V,  "Vd,Vt,sVm", MATCH_VMAXUVX, MASK_VMAXUVX, match_opcode, 0},
++{"vmax.vv",    0, INSN_CLASS_V,  "Vd,Vt,VsVm", MATCH_VMAXVV, MASK_VMAXVV, match_opcode, 0},
++{"vmax.vx",    0, INSN_CLASS_V,  "Vd,Vt,sVm", MATCH_VMAXVX, MASK_VMAXVX, match_opcode, 0},
++
++{"vmul.vv",    0, INSN_CLASS_V,  "Vd,Vt,VsVm", MATCH_VMULVV, MASK_VMULVV, match_opcode, 0 },
++{"vmul.vx",    0, INSN_CLASS_V,  "Vd,Vt,sVm", MATCH_VMULVX, MASK_VMULVX, match_opcode, 0 },
++{"vmulh.vv",   0, INSN_CLASS_V,  "Vd,Vt,VsVm", MATCH_VMULHVV, MASK_VMULHVV, match_opcode, 0 },
++{"vmulh.vx",   0, INSN_CLASS_V,  "Vd,Vt,sVm", MATCH_VMULHVX, MASK_VMULHVX, match_opcode, 0 },
++{"vmulhu.vv",  0, INSN_CLASS_V,  "Vd,Vt,VsVm", MATCH_VMULHUVV, MASK_VMULHUVV, match_opcode, 0 },
++{"vmulhu.vx",  0, INSN_CLASS_V,  "Vd,Vt,sVm", MATCH_VMULHUVX, MASK_VMULHUVX, match_opcode, 0 },
++{"vmulhsu.vv", 0, INSN_CLASS_V,  "Vd,Vt,VsVm", MATCH_VMULHSUVV, MASK_VMULHSUVV, match_opcode, 0 },
++{"vmulhsu.vx", 0, INSN_CLASS_V,  "Vd,Vt,sVm", MATCH_VMULHSUVX, MASK_VMULHSUVX, match_opcode, 0 },
++
++{"vwmul.vv",   0, INSN_CLASS_V,  "Vd,Vt,VsVm", MATCH_VWMULVV, MASK_VWMULVV, match_widen_vd_neq_vs1_neq_vs2_neq_vm, 0 },
++{"vwmul.vx",   0, INSN_CLASS_V,  "Vd,Vt,sVm", MATCH_VWMULVX, MASK_VWMULVX, match_widen_vd_neq_vs2_neq_vm, 0 },
++{"vwmulu.vv",  0, INSN_CLASS_V,  "Vd,Vt,VsVm", MATCH_VWMULUVV, MASK_VWMULUVV, match_widen_vd_neq_vs1_neq_vs2_neq_vm, 0 },
++{"vwmulu.vx",  0, INSN_CLASS_V,  "Vd,Vt,sVm", MATCH_VWMULUVX, MASK_VWMULUVX, match_widen_vd_neq_vs2_neq_vm, 0 },
++{"vwmulsu.vv", 0, INSN_CLASS_V,  "Vd,Vt,VsVm", MATCH_VWMULSUVV, MASK_VWMULSUVV, match_widen_vd_neq_vs1_neq_vs2_neq_vm, 0 },
++{"vwmulsu.vx", 0, INSN_CLASS_V,  "Vd,Vt,sVm", MATCH_VWMULSUVX, MASK_VWMULSUVX, match_widen_vd_neq_vs2_neq_vm, 0 },
++
++{"vmacc.vv",   0, INSN_CLASS_V,  "Vd,Vs,VtVm", MATCH_VMACCVV, MASK_VMACCVV, match_opcode, 0},
++{"vmacc.vx",   0, INSN_CLASS_V,  "Vd,s,VtVm", MATCH_VMACCVX, MASK_VMACCVX, match_opcode, 0},
++{"vnmsac.vv",  0, INSN_CLASS_V,  "Vd,Vs,VtVm", MATCH_VNMSACVV, MASK_VNMSACVV, match_opcode, 0},
++{"vnmsac.vx",  0, INSN_CLASS_V,  "Vd,s,VtVm", MATCH_VNMSACVX, MASK_VNMSACVX, match_opcode, 0},
++{"vmadd.vv",   0, INSN_CLASS_V,  "Vd,Vs,VtVm", MATCH_VMADDVV, MASK_VMADDVV, match_opcode, 0},
++{"vmadd.vx",   0, INSN_CLASS_V,  "Vd,s,VtVm", MATCH_VMADDVX, MASK_VMADDVX, match_opcode, 0},
++{"vnmsub.vv",  0, INSN_CLASS_V,  "Vd,Vs,VtVm", MATCH_VNMSUBVV, MASK_VNMSUBVV, match_opcode, 0},
++{"vnmsub.vx",  0, INSN_CLASS_V,  "Vd,s,VtVm", MATCH_VNMSUBVX, MASK_VNMSUBVX, match_opcode, 0},
++
++{"vwmaccu.vv",  0, INSN_CLASS_V,  "Vd,Vs,VtVm", MATCH_VWMACCUVV, MASK_VWMACCUVV, match_widen_vd_neq_vs1_neq_vs2_neq_vm, 0},
++{"vwmaccu.vx",  0, INSN_CLASS_V,  "Vd,s,VtVm", MATCH_VWMACCUVX, MASK_VWMACCUVX, match_widen_vd_neq_vs2_neq_vm, 0},
++{"vwmacc.vv",   0, INSN_CLASS_V,  "Vd,Vs,VtVm", MATCH_VWMACCVV, MASK_VWMACCVV, match_widen_vd_neq_vs1_neq_vs2_neq_vm, 0},
++{"vwmacc.vx",   0, INSN_CLASS_V,  "Vd,s,VtVm", MATCH_VWMACCVX, MASK_VWMACCVX, match_widen_vd_neq_vs2_neq_vm, 0},
++{"vwmaccsu.vv", 0, INSN_CLASS_V,  "Vd,Vs,VtVm", MATCH_VWMACCSUVV, MASK_VWMACCSUVV, match_widen_vd_neq_vs1_neq_vs2_neq_vm, 0},
++{"vwmaccsu.vx", 0, INSN_CLASS_V,  "Vd,s,VtVm", MATCH_VWMACCSUVX, MASK_VWMACCSUVX, match_widen_vd_neq_vs2_neq_vm, 0},
++{"vwmaccus.vx", 0, INSN_CLASS_V,  "Vd,s,VtVm", MATCH_VWMACCUSVX, MASK_VWMACCUSVX, match_widen_vd_neq_vs2_neq_vm, 0},
++
++{"vqmaccu.vv",  0, INSN_CLASS_V_AND_ZVQMAC,  "Vd,Vs,VtVm", MATCH_VQMACCUVV, MASK_VQMACCUVV, match_quad_vd_neq_vs1_neq_vs2_neq_vm, 0},
++{"vqmaccu.vx",  0, INSN_CLASS_V_AND_ZVQMAC,  "Vd,s,VtVm",  MATCH_VQMACCUVX, MASK_VQMACCUVX, match_quad_vd_neq_vs2_neq_vm, 0},
++{"vqmacc.vv",   0, INSN_CLASS_V_AND_ZVQMAC,  "Vd,Vs,VtVm", MATCH_VQMACCVV, MASK_VQMACCVV, match_quad_vd_neq_vs1_neq_vs2_neq_vm, 0},
++{"vqmacc.vx",   0, INSN_CLASS_V_AND_ZVQMAC,  "Vd,s,VtVm",  MATCH_VQMACCVX, MASK_VQMACCVX, match_quad_vd_neq_vs2_neq_vm, 0},
++{"vqmaccsu.vv", 0, INSN_CLASS_V_AND_ZVQMAC,  "Vd,Vs,VtVm", MATCH_VQMACCSUVV, MASK_VQMACCSUVV, match_quad_vd_neq_vs1_neq_vs2_neq_vm, 0},
++{"vqmaccsu.vx", 0, INSN_CLASS_V_AND_ZVQMAC,  "Vd,s,VtVm",  MATCH_VQMACCSUVX, MASK_VQMACCSUVX, match_quad_vd_neq_vs2_neq_vm, 0},
++{"vqmaccus.vx", 0, INSN_CLASS_V_AND_ZVQMAC,  "Vd,s,VtVm",  MATCH_VQMACCUSVX, MASK_VQMACCUSVX, match_quad_vd_neq_vs2_neq_vm, 0},
++
++{"vdivu.vv",   0, INSN_CLASS_V,  "Vd,Vt,VsVm", MATCH_VDIVUVV, MASK_VDIVUVV, match_opcode, 0 },
++{"vdivu.vx",   0, INSN_CLASS_V,  "Vd,Vt,sVm", MATCH_VDIVUVX, MASK_VDIVUVX, match_opcode, 0 },
++{"vdiv.vv",    0, INSN_CLASS_V,  "Vd,Vt,VsVm", MATCH_VDIVVV, MASK_VDIVVV, match_opcode, 0 },
++{"vdiv.vx",    0, INSN_CLASS_V,  "Vd,Vt,sVm", MATCH_VDIVVX, MASK_VDIVVX, match_opcode, 0 },
++{"vremu.vv",   0, INSN_CLASS_V,  "Vd,Vt,VsVm", MATCH_VREMUVV, MASK_VREMUVV, match_opcode, 0 },
++{"vremu.vx",   0, INSN_CLASS_V,  "Vd,Vt,sVm", MATCH_VREMUVX, MASK_VREMUVX, match_opcode, 0 },
++{"vrem.vv",    0, INSN_CLASS_V,  "Vd,Vt,VsVm", MATCH_VREMVV, MASK_VREMVV, match_opcode, 0 },
++{"vrem.vx",    0, INSN_CLASS_V,  "Vd,Vt,sVm", MATCH_VREMVX, MASK_VREMVX, match_opcode, 0 },
++
++{"vmerge.vvm", 0, INSN_CLASS_V,  "Vd,Vt,Vs,V0", MATCH_VMERGEVVM, MASK_VMERGEVVM, match_opcode, 0 },
++{"vmerge.vxm", 0, INSN_CLASS_V,  "Vd,Vt,s,V0", MATCH_VMERGEVXM, MASK_VMERGEVXM, match_opcode, 0 },
++{"vmerge.vim", 0, INSN_CLASS_V,  "Vd,Vt,Vi,V0", MATCH_VMERGEVIM, MASK_VMERGEVIM, match_opcode, 0 },
++
++{"vmv.v.v",    0, INSN_CLASS_V,  "Vd,Vs", MATCH_VMVVV, MASK_VMVVV, match_opcode, 0 },
++{"vmv.v.x",    0, INSN_CLASS_V,  "Vd,s", MATCH_VMVVX, MASK_VMVVX, match_opcode, 0 },
++{"vmv.v.i",    0, INSN_CLASS_V,  "Vd,Vi", MATCH_VMVVI, MASK_VMVVI, match_opcode, 0 },
++
++{"vsaddu.vv",  0, INSN_CLASS_V,  "Vd,Vt,VsVm", MATCH_VSADDUVV, MASK_VSADDUVV, match_opcode, 0 },
++{"vsaddu.vx",  0, INSN_CLASS_V,  "Vd,Vt,sVm", MATCH_VSADDUVX, MASK_VSADDUVX, match_opcode, 0 },
++{"vsaddu.vi",  0, INSN_CLASS_V,  "Vd,Vt,ViVm", MATCH_VSADDUVI, MASK_VSADDUVI, match_opcode, 0 },
++{"vsadd.vv",   0, INSN_CLASS_V,  "Vd,Vt,VsVm", MATCH_VSADDVV, MASK_VSADDVV, match_opcode, 0 },
++{"vsadd.vx",   0, INSN_CLASS_V,  "Vd,Vt,sVm", MATCH_VSADDVX, MASK_VSADDVX, match_opcode, 0 },
++{"vsadd.vi",   0, INSN_CLASS_V,  "Vd,Vt,ViVm", MATCH_VSADDVI, MASK_VSADDVI, match_opcode, 0 },
++{"vssubu.vv",  0, INSN_CLASS_V,  "Vd,Vt,VsVm", MATCH_VSSUBUVV, MASK_VSSUBUVV, match_opcode, 0 },
++{"vssubu.vx",  0, INSN_CLASS_V,  "Vd,Vt,sVm", MATCH_VSSUBUVX, MASK_VSSUBUVX, match_opcode, 0 },
++{"vssub.vv",   0, INSN_CLASS_V,  "Vd,Vt,VsVm", MATCH_VSSUBVV, MASK_VSSUBVV, match_opcode, 0 },
++{"vssub.vx",   0, INSN_CLASS_V,  "Vd,Vt,sVm", MATCH_VSSUBVX, MASK_VSSUBVX, match_opcode, 0 },
++
++{"vaaddu.vv",  0, INSN_CLASS_V,  "Vd,Vt,VsVm", MATCH_VAADDUVV, MASK_VAADDUVV, match_opcode, 0 },
++{"vaaddu.vx",  0, INSN_CLASS_V,  "Vd,Vt,sVm", MATCH_VAADDUVX, MASK_VAADDUVX, match_opcode, 0 },
++{"vaadd.vv",   0, INSN_CLASS_V,  "Vd,Vt,VsVm", MATCH_VAADDVV, MASK_VAADDVV, match_opcode, 0 },
++{"vaadd.vx",   0, INSN_CLASS_V,  "Vd,Vt,sVm", MATCH_VAADDVX, MASK_VAADDVX, match_opcode, 0 },
++{"vasubu.vv",  0, INSN_CLASS_V,  "Vd,Vt,VsVm", MATCH_VASUBUVV, MASK_VASUBUVV, match_opcode, 0 },
++{"vasubu.vx",  0, INSN_CLASS_V,  "Vd,Vt,sVm", MATCH_VASUBUVX, MASK_VASUBUVX, match_opcode, 0 },
++{"vasub.vv",   0, INSN_CLASS_V,  "Vd,Vt,VsVm", MATCH_VASUBVV, MASK_VASUBVV, match_opcode, 0 },
++{"vasub.vx",   0, INSN_CLASS_V,  "Vd,Vt,sVm", MATCH_VASUBVX, MASK_VASUBVX, match_opcode, 0 },
++
++{"vsmul.vv",   0, INSN_CLASS_V,  "Vd,Vt,VsVm", MATCH_VSMULVV, MASK_VSMULVV, match_opcode, 0 },
++{"vsmul.vx",   0, INSN_CLASS_V,  "Vd,Vt,sVm", MATCH_VSMULVX, MASK_VSMULVX, match_opcode, 0 },
++
++{"vssrl.vv",    0, INSN_CLASS_V,  "Vd,Vt,VsVm", MATCH_VSSRLVV, MASK_VSSRLVV, match_opcode, 0 },
++{"vssrl.vx",    0, INSN_CLASS_V,  "Vd,Vt,sVm", MATCH_VSSRLVX, MASK_VSSRLVX, match_opcode, 0 },
++{"vssrl.vi",    0, INSN_CLASS_V,  "Vd,Vt,VjVm", MATCH_VSSRLVI, MASK_VSSRLVI, match_opcode, 0 },
++{"vssra.vv",    0, INSN_CLASS_V,  "Vd,Vt,VsVm", MATCH_VSSRAVV, MASK_VSSRAVV, match_opcode, 0 },
++{"vssra.vx",    0, INSN_CLASS_V,  "Vd,Vt,sVm", MATCH_VSSRAVX, MASK_VSSRAVX, match_opcode, 0 },
++{"vssra.vi",    0, INSN_CLASS_V,  "Vd,Vt,VjVm", MATCH_VSSRAVI, MASK_VSSRAVI, match_opcode, 0 },
++
++{"vnclipu.wv",   0, INSN_CLASS_V,  "Vd,Vt,VsVm", MATCH_VNCLIPUWV, MASK_VNCLIPUWV, match_narrow_vd_neq_vs2, 0 },
++{"vnclipu.wx",   0, INSN_CLASS_V,  "Vd,Vt,sVm", MATCH_VNCLIPUWX, MASK_VNCLIPUWX, match_narrow_vd_neq_vs2, 0 },
++{"vnclipu.wi",   0, INSN_CLASS_V,  "Vd,Vt,VjVm", MATCH_VNCLIPUWI, MASK_VNCLIPUWI, match_narrow_vd_neq_vs2, 0 },
++{"vnclip.wv",   0, INSN_CLASS_V,  "Vd,Vt,VsVm", MATCH_VNCLIPWV, MASK_VNCLIPWV, match_narrow_vd_neq_vs2, 0 },
++{"vnclip.wx",   0, INSN_CLASS_V,  "Vd,Vt,sVm", MATCH_VNCLIPWX, MASK_VNCLIPWX, match_narrow_vd_neq_vs2, 0 },
++{"vnclip.wi",   0, INSN_CLASS_V,  "Vd,Vt,VjVm", MATCH_VNCLIPWI, MASK_VNCLIPWI, match_narrow_vd_neq_vs2, 0 },
++
++{"vfadd.vv",   0, INSN_CLASS_V_AND_F, "Vd,Vt,VsVm", MATCH_VFADDVV, MASK_VFADDVV, match_opcode, 0},
++{"vfadd.vf",   0, INSN_CLASS_V_AND_F, "Vd,Vt,SVm", MATCH_VFADDVF, MASK_VFADDVF, match_opcode, 0},
++{"vfsub.vv",   0, INSN_CLASS_V_AND_F, "Vd,Vt,VsVm", MATCH_VFSUBVV, MASK_VFSUBVV, match_opcode, 0},
++{"vfsub.vf",   0, INSN_CLASS_V_AND_F, "Vd,Vt,SVm", MATCH_VFSUBVF, MASK_VFSUBVF, match_opcode, 0},
++{"vfrsub.vf",  0, INSN_CLASS_V_AND_F, "Vd,Vt,SVm", MATCH_VFRSUBVF, MASK_VFRSUBVF, match_opcode, 0},
++
++{"vfwadd.vv",   0, INSN_CLASS_V_AND_F, "Vd,Vt,VsVm", MATCH_VFWADDVV, MASK_VFWADDVV, match_widen_vd_neq_vs1_neq_vs2_neq_vm, 0},
++{"vfwadd.vf",   0, INSN_CLASS_V_AND_F, "Vd,Vt,SVm", MATCH_VFWADDVF, MASK_VFWADDVF, match_widen_vd_neq_vs2_neq_vm, 0},
++{"vfwsub.vv",   0, INSN_CLASS_V_AND_F, "Vd,Vt,VsVm", MATCH_VFWSUBVV, MASK_VFWSUBVV, match_widen_vd_neq_vs1_neq_vs2_neq_vm, 0},
++{"vfwsub.vf",   0, INSN_CLASS_V_AND_F, "Vd,Vt,SVm", MATCH_VFWSUBVF, MASK_VFWSUBVF, match_widen_vd_neq_vs2_neq_vm, 0},
++{"vfwadd.wv",   0, INSN_CLASS_V_AND_F, "Vd,Vt,VsVm", MATCH_VFWADDWV, MASK_VFWADDWV, match_widen_vd_neq_vs1_neq_vm, 0},
++{"vfwadd.wf",   0, INSN_CLASS_V_AND_F, "Vd,Vt,SVm", MATCH_VFWADDWF, MASK_VFWADDWF, match_widen_vd_neq_vm, 0},
++{"vfwsub.wv",   0, INSN_CLASS_V_AND_F, "Vd,Vt,VsVm", MATCH_VFWSUBWV, MASK_VFWSUBWV, match_widen_vd_neq_vs1_neq_vm, 0},
++{"vfwsub.wf",   0, INSN_CLASS_V_AND_F, "Vd,Vt,SVm", MATCH_VFWSUBWF, MASK_VFWSUBWF, match_widen_vd_neq_vm, 0},
++
++{"vfmul.vv",   0, INSN_CLASS_V_AND_F, "Vd,Vt,VsVm", MATCH_VFMULVV, MASK_VFMULVV, match_opcode, 0},
++{"vfmul.vf",   0, INSN_CLASS_V_AND_F, "Vd,Vt,SVm", MATCH_VFMULVF, MASK_VFMULVF, match_opcode, 0},
++{"vfdiv.vv",   0, INSN_CLASS_V_AND_F, "Vd,Vt,VsVm", MATCH_VFDIVVV, MASK_VFDIVVV, match_opcode, 0},
++{"vfdiv.vf",   0, INSN_CLASS_V_AND_F, "Vd,Vt,SVm", MATCH_VFDIVVF, MASK_VFDIVVF, match_opcode, 0},
++{"vfrdiv.vf",  0, INSN_CLASS_V_AND_F, "Vd,Vt,SVm", MATCH_VFRDIVVF, MASK_VFRDIVVF, match_opcode, 0},
++
++{"vfwmul.vv",  0, INSN_CLASS_V_AND_F, "Vd,Vt,VsVm", MATCH_VFWMULVV, MASK_VFWMULVV, match_widen_vd_neq_vs1_neq_vs2_neq_vm, 0},
++{"vfwmul.vf",  0, INSN_CLASS_V_AND_F, "Vd,Vt,SVm", MATCH_VFWMULVF, MASK_VFWMULVF, match_widen_vd_neq_vs2_neq_vm, 0},
++
++{"vfmadd.vv",  0, INSN_CLASS_V_AND_F, "Vd,Vs,VtVm", MATCH_VFMADDVV, MASK_VFMADDVV, match_opcode, 0},
++{"vfmadd.vf",  0, INSN_CLASS_V_AND_F, "Vd,S,VtVm", MATCH_VFMADDVF, MASK_VFMADDVF, match_opcode, 0},
++{"vfnmadd.vv", 0, INSN_CLASS_V_AND_F, "Vd,Vs,VtVm", MATCH_VFNMADDVV, MASK_VFNMADDVV, match_opcode, 0},
++{"vfnmadd.vf", 0, INSN_CLASS_V_AND_F, "Vd,S,VtVm", MATCH_VFNMADDVF, MASK_VFNMADDVF, match_opcode, 0},
++{"vfmsub.vv",  0, INSN_CLASS_V_AND_F, "Vd,Vs,VtVm", MATCH_VFMSUBVV, MASK_VFMSUBVV, match_opcode, 0},
++{"vfmsub.vf",  0, INSN_CLASS_V_AND_F, "Vd,S,VtVm", MATCH_VFMSUBVF, MASK_VFMSUBVF, match_opcode, 0},
++{"vfnmsub.vv", 0, INSN_CLASS_V_AND_F, "Vd,Vs,VtVm", MATCH_VFNMSUBVV, MASK_VFNMSUBVV, match_opcode, 0},
++{"vfnmsub.vf", 0, INSN_CLASS_V_AND_F, "Vd,S,VtVm", MATCH_VFNMSUBVF, MASK_VFNMSUBVF, match_opcode, 0},
++{"vfmacc.vv",  0, INSN_CLASS_V_AND_F, "Vd,Vs,VtVm", MATCH_VFMACCVV, MASK_VFMACCVV, match_opcode, 0},
++{"vfmacc.vf",  0, INSN_CLASS_V_AND_F, "Vd,S,VtVm", MATCH_VFMACCVF, MASK_VFMACCVF, match_opcode, 0},
++{"vfnmacc.vv", 0, INSN_CLASS_V_AND_F, "Vd,Vs,VtVm", MATCH_VFNMACCVV, MASK_VFNMACCVV, match_opcode, 0},
++{"vfnmacc.vf", 0, INSN_CLASS_V_AND_F, "Vd,S,VtVm", MATCH_VFNMACCVF, MASK_VFNMACCVF, match_opcode, 0},
++{"vfmsac.vv",  0, INSN_CLASS_V_AND_F, "Vd,Vs,VtVm", MATCH_VFMSACVV, MASK_VFMSACVV, match_opcode, 0},
++{"vfmsac.vf",  0, INSN_CLASS_V_AND_F, "Vd,S,VtVm", MATCH_VFMSACVF, MASK_VFMSACVF, match_opcode, 0},
++{"vfnmsac.vv", 0, INSN_CLASS_V_AND_F, "Vd,Vs,VtVm", MATCH_VFNMSACVV, MASK_VFNMSACVV, match_opcode, 0},
++{"vfnmsac.vf", 0, INSN_CLASS_V_AND_F, "Vd,S,VtVm", MATCH_VFNMSACVF, MASK_VFNMSACVF, match_opcode, 0},
++
++{"vfwmacc.vv",  0, INSN_CLASS_V_AND_F, "Vd,Vs,VtVm", MATCH_VFWMACCVV, MASK_VFWMACCVV, match_widen_vd_neq_vs1_neq_vs2_neq_vm, 0},
++{"vfwmacc.vf",  0, INSN_CLASS_V_AND_F, "Vd,S,VtVm", MATCH_VFWMACCVF, MASK_VFWMACCVF, match_widen_vd_neq_vs2_neq_vm, 0},
++{"vfwnmacc.vv", 0, INSN_CLASS_V_AND_F, "Vd,Vs,VtVm", MATCH_VFWNMACCVV, MASK_VFWNMACCVV, match_widen_vd_neq_vs1_neq_vs2_neq_vm, 0},
++{"vfwnmacc.vf", 0, INSN_CLASS_V_AND_F, "Vd,S,VtVm", MATCH_VFWNMACCVF, MASK_VFWNMACCVF, match_widen_vd_neq_vs2_neq_vm, 0},
++{"vfwmsac.vv",  0, INSN_CLASS_V_AND_F, "Vd,Vs,VtVm", MATCH_VFWMSACVV, MASK_VFWMSACVV, match_widen_vd_neq_vs1_neq_vs2_neq_vm, 0},
++{"vfwmsac.vf",  0, INSN_CLASS_V_AND_F, "Vd,S,VtVm", MATCH_VFWMSACVF, MASK_VFWMSACVF, match_widen_vd_neq_vs2_neq_vm, 0},
++{"vfwnmsac.vv", 0, INSN_CLASS_V_AND_F, "Vd,Vs,VtVm", MATCH_VFWNMSACVV, MASK_VFWNMSACVV, match_widen_vd_neq_vs1_neq_vs2_neq_vm, 0},
++{"vfwnmsac.vf", 0, INSN_CLASS_V_AND_F, "Vd,S,VtVm", MATCH_VFWNMSACVF, MASK_VFWNMSACVF, match_widen_vd_neq_vs2_neq_vm, 0},
++
++{"vfsqrt.v",   0, INSN_CLASS_V_AND_F, "Vd,VtVm", MATCH_VFSQRTV, MASK_VFSQRTV, match_opcode, 0},
++
++{"vfmin.vv",   0, INSN_CLASS_V_AND_F, "Vd,Vt,VsVm", MATCH_VFMINVV, MASK_VFMINVV, match_opcode, 0},
++{"vfmin.vf",   0, INSN_CLASS_V_AND_F, "Vd,Vt,SVm", MATCH_VFMINVF, MASK_VFMINVF, match_opcode, 0},
++{"vfmax.vv",   0, INSN_CLASS_V_AND_F, "Vd,Vt,VsVm", MATCH_VFMAXVV, MASK_VFMAXVV, match_opcode, 0},
++{"vfmax.vf",   0, INSN_CLASS_V_AND_F, "Vd,Vt,SVm", MATCH_VFMAXVF, MASK_VFMAXVF, match_opcode, 0},
++
++{"vfsgnj.vv",  0, INSN_CLASS_V_AND_F, "Vd,Vt,VsVm", MATCH_VFSGNJVV, MASK_VFSGNJVV, match_opcode, 0},
++{"vfsgnj.vf",  0, INSN_CLASS_V_AND_F, "Vd,Vt,SVm", MATCH_VFSGNJVF, MASK_VFSGNJVF, match_opcode, 0},
++{"vfsgnjn.vv", 0, INSN_CLASS_V_AND_F, "Vd,Vt,VsVm", MATCH_VFSGNJNVV, MASK_VFSGNJNVV, match_opcode, 0},
++{"vfsgnjn.vf", 0, INSN_CLASS_V_AND_F, "Vd,Vt,SVm", MATCH_VFSGNJNVF, MASK_VFSGNJNVF, match_opcode, 0},
++{"vfsgnjx.vv", 0, INSN_CLASS_V_AND_F, "Vd,Vt,VsVm", MATCH_VFSGNJXVV, MASK_VFSGNJXVV, match_opcode, 0},
++{"vfsgnjx.vf", 0, INSN_CLASS_V_AND_F, "Vd,Vt,SVm", MATCH_VFSGNJXVF, MASK_VFSGNJXVF, match_opcode, 0},
++
++{"vmfeq.vv",   0, INSN_CLASS_V_AND_F, "Vd,Vt,VsVm", MATCH_VMFEQVV, MASK_VMFEQVV, match_opcode, 0},
++{"vmfeq.vf",   0, INSN_CLASS_V_AND_F, "Vd,Vt,SVm", MATCH_VMFEQVF, MASK_VMFEQVF, match_opcode, 0},
++{"vmfne.vv",   0, INSN_CLASS_V_AND_F, "Vd,Vt,VsVm", MATCH_VMFNEVV, MASK_VMFNEVV, match_opcode, 0},
++{"vmfne.vf",   0, INSN_CLASS_V_AND_F, "Vd,Vt,SVm", MATCH_VMFNEVF, MASK_VMFNEVF, match_opcode, 0},
++{"vmflt.vv",   0, INSN_CLASS_V_AND_F, "Vd,Vt,VsVm", MATCH_VMFLTVV, MASK_VMFLTVV, match_opcode, 0},
++{"vmflt.vf",   0, INSN_CLASS_V_AND_F, "Vd,Vt,SVm", MATCH_VMFLTVF, MASK_VMFLTVF, match_opcode, 0},
++{"vmfle.vv",   0, INSN_CLASS_V_AND_F, "Vd,Vt,VsVm", MATCH_VMFLEVV, MASK_VMFLEVV, match_opcode, 0},
++{"vmfle.vf",   0, INSN_CLASS_V_AND_F, "Vd,Vt,SVm", MATCH_VMFLEVF, MASK_VMFLEVF, match_opcode, 0},
++{"vmfgt.vf",   0, INSN_CLASS_V_AND_F, "Vd,Vt,SVm", MATCH_VMFGTVF, MASK_VMFGTVF, match_opcode, 0},
++{"vmfge.vf",   0, INSN_CLASS_V_AND_F, "Vd,Vt,SVm", MATCH_VMFGEVF, MASK_VMFGEVF, match_opcode, 0},
++
++/* These aliases are for assembly but not disassembly.  */
++{"vmfgt.vv",    0, INSN_CLASS_V_AND_F, "Vd,Vs,VtVm", MATCH_VMFLTVV, MASK_VMFLTVV, match_opcode, INSN_ALIAS},
++{"vmfge.vv",   0, INSN_CLASS_V_AND_F, "Vd,Vs,VtVm", MATCH_VMFLEVV, MASK_VMFLEVV, match_opcode, INSN_ALIAS},
++
++{"vfclass.v",  0, INSN_CLASS_V_AND_F, "Vd,VtVm", MATCH_VFCLASSV, MASK_VFCLASSV, match_opcode, 0},
++
++{"vfmerge.vfm",0, INSN_CLASS_V_AND_F, "Vd,Vt,S,V0", MATCH_VFMERGEVFM, MASK_VFMERGEVFM, match_opcode, 0},
++{"vfmv.v.f",   0, INSN_CLASS_V_AND_F, "Vd,S", MATCH_VFMVVF, MASK_VFMVVF, match_opcode, 0 },
++
++{"vfcvt.xu.f.v",     0, INSN_CLASS_V_AND_F, "Vd,VtVm", MATCH_VFCVTXUFV, MASK_VFCVTXUFV, match_opcode, 0},
++{"vfcvt.x.f.v",      0, INSN_CLASS_V_AND_F, "Vd,VtVm", MATCH_VFCVTXFV, MASK_VFCVTXFV, match_opcode, 0},
++{"vfcvt.rtz.xu.f.v", 0, INSN_CLASS_V_AND_F, "Vd,VtVm", MATCH_VFCVTRTZXUFV, MASK_VFCVTRTZXUFV, match_opcode, 0},
++{"vfcvt.rtz.x.f.v",  0, INSN_CLASS_V_AND_F, "Vd,VtVm", MATCH_VFCVTRTZXFV, MASK_VFCVTRTZXFV, match_opcode, 0},
++{"vfcvt.f.xu.v",     0, INSN_CLASS_V_AND_F, "Vd,VtVm", MATCH_VFCVTFXUV, MASK_VFCVTFXUV, match_opcode, 0},
++{"vfcvt.f.x.v",      0, INSN_CLASS_V_AND_F, "Vd,VtVm", MATCH_VFCVTFXV, MASK_VFCVTFXV, match_opcode, 0},
++
++{"vfwcvt.xu.f.v",     0, INSN_CLASS_V_AND_F, "Vd,VtVm", MATCH_VFWCVTXUFV, MASK_VFWCVTXUFV, match_widen_vd_neq_vs2_neq_vm, 0},
++{"vfwcvt.x.f.v",      0, INSN_CLASS_V_AND_F, "Vd,VtVm", MATCH_VFWCVTXFV, MASK_VFWCVTXFV, match_widen_vd_neq_vs2_neq_vm, 0},
++{"vfwcvt.rtz.xu.f.v", 0, INSN_CLASS_V_AND_F, "Vd,VtVm", MATCH_VFWCVTRTZXUFV, MASK_VFWCVTRTZXUFV, match_widen_vd_neq_vs2_neq_vm, 0},
++{"vfwcvt.rtz.x.f.v",  0, INSN_CLASS_V_AND_F, "Vd,VtVm", MATCH_VFWCVTRTZXFV, MASK_VFWCVTRTZXFV, match_widen_vd_neq_vs2_neq_vm, 0},
++{"vfwcvt.f.xu.v",     0, INSN_CLASS_V_AND_F, "Vd,VtVm", MATCH_VFWCVTFXUV, MASK_VFWCVTFXUV, match_widen_vd_neq_vs2_neq_vm, 0},
++{"vfwcvt.f.x.v",      0, INSN_CLASS_V_AND_F, "Vd,VtVm", MATCH_VFWCVTFXV, MASK_VFWCVTFXV, match_widen_vd_neq_vs2_neq_vm, 0},
++{"vfwcvt.f.f.v",      0, INSN_CLASS_V_AND_F, "Vd,VtVm", MATCH_VFWCVTFFV, MASK_VFWCVTFFV, match_widen_vd_neq_vs2_neq_vm, 0},
++
++{"vfncvt.xu.f.w",     0, INSN_CLASS_V_AND_F, "Vd,VtVm", MATCH_VFNCVTXUFW, MASK_VFNCVTXUFW, match_narrow_vd_neq_vs2, 0},
++{"vfncvt.x.f.w",      0, INSN_CLASS_V_AND_F, "Vd,VtVm", MATCH_VFNCVTXFW, MASK_VFNCVTXFW, match_narrow_vd_neq_vs2, 0},
++{"vfncvt.rtz.xu.f.w", 0, INSN_CLASS_V_AND_F, "Vd,VtVm", MATCH_VFNCVTRTZXUFW, MASK_VFNCVTRTZXUFW, match_narrow_vd_neq_vs2, 0},
++{"vfncvt.rtz.x.f.w",  0, INSN_CLASS_V_AND_F, "Vd,VtVm", MATCH_VFNCVTRTZXFW, MASK_VFNCVTRTZXFW, match_narrow_vd_neq_vs2, 0},
++{"vfncvt.f.xu.w",     0, INSN_CLASS_V_AND_F, "Vd,VtVm", MATCH_VFNCVTFXUW, MASK_VFNCVTFXUW, match_narrow_vd_neq_vs2, 0},
++{"vfncvt.f.x.w",      0, INSN_CLASS_V_AND_F, "Vd,VtVm", MATCH_VFNCVTFXW, MASK_VFNCVTFXW, match_narrow_vd_neq_vs2, 0},
++{"vfncvt.f.f.w",      0, INSN_CLASS_V_AND_F, "Vd,VtVm", MATCH_VFNCVTFFW, MASK_VFNCVTFFW, match_narrow_vd_neq_vs2, 0},
++{"vfncvt.rod.f.f.w",  0, INSN_CLASS_V_AND_F, "Vd,VtVm", MATCH_VFNCVTRODFFW, MASK_VFNCVTRODFFW, match_narrow_vd_neq_vs2, 0},
++
++{"vredsum.vs", 0, INSN_CLASS_V, "Vd,Vt,VsVm", MATCH_VREDSUMVS, MASK_VREDSUMVS, match_opcode, 0},
++{"vredmaxu.vs",0, INSN_CLASS_V, "Vd,Vt,VsVm", MATCH_VREDMAXUVS, MASK_VREDMAXUVS, match_opcode, 0},
++{"vredmax.vs", 0, INSN_CLASS_V, "Vd,Vt,VsVm", MATCH_VREDMAXVS, MASK_VREDMAXVS, match_opcode, 0},
++{"vredminu.vs",0, INSN_CLASS_V, "Vd,Vt,VsVm", MATCH_VREDMINUVS, MASK_VREDMINUVS, match_opcode, 0},
++{"vredmin.vs", 0, INSN_CLASS_V, "Vd,Vt,VsVm", MATCH_VREDMINVS, MASK_VREDMINVS, match_opcode, 0},
++{"vredand.vs", 0, INSN_CLASS_V, "Vd,Vt,VsVm", MATCH_VREDANDVS, MASK_VREDANDVS, match_opcode, 0},
++{"vredor.vs",  0, INSN_CLASS_V, "Vd,Vt,VsVm", MATCH_VREDORVS, MASK_VREDORVS, match_opcode, 0},
++{"vredxor.vs", 0, INSN_CLASS_V, "Vd,Vt,VsVm", MATCH_VREDXORVS, MASK_VREDXORVS, match_opcode, 0},
++
++{"vwredsumu.vs",0, INSN_CLASS_V, "Vd,Vt,VsVm", MATCH_VWREDSUMUVS, MASK_VWREDSUMUVS, match_opcode, 0},
++{"vwredsum.vs",0, INSN_CLASS_V, "Vd,Vt,VsVm", MATCH_VWREDSUMVS, MASK_VWREDSUMVS, match_opcode, 0},
++
++{"vfredosum.vs",0, INSN_CLASS_V_AND_F, "Vd,Vt,VsVm", MATCH_VFREDOSUMVS, MASK_VFREDOSUMVS, match_opcode, 0},
++{"vfredsum.vs", 0, INSN_CLASS_V_AND_F, "Vd,Vt,VsVm", MATCH_VFREDSUMVS, MASK_VFREDSUMVS, match_opcode, 0},
++{"vfredmax.vs", 0, INSN_CLASS_V_AND_F, "Vd,Vt,VsVm", MATCH_VFREDMAXVS, MASK_VFREDMAXVS, match_opcode, 0},
++{"vfredmin.vs", 0, INSN_CLASS_V_AND_F, "Vd,Vt,VsVm", MATCH_VFREDMINVS, MASK_VFREDMINVS, match_opcode, 0},
++
++{"vfwredosum.vs",0, INSN_CLASS_V_AND_F, "Vd,Vt,VsVm", MATCH_VFWREDOSUMVS, MASK_VFWREDOSUMVS, match_opcode, 0},
++{"vfwredsum.vs", 0, INSN_CLASS_V_AND_F, "Vd,Vt,VsVm", MATCH_VFWREDSUMVS, MASK_VFWREDSUMVS, match_opcode, 0},
++
++{"vmmv.m",     0, INSN_CLASS_V, "Vd,Vu", MATCH_VMANDMM, MASK_VMANDMM, match_vs1_eq_vs2, INSN_ALIAS},
++{"vmcpy.m",    0, INSN_CLASS_V, "Vd,Vu", MATCH_VMANDMM, MASK_VMANDMM, match_vs1_eq_vs2, INSN_ALIAS},
++{"vmclr.m",    0, INSN_CLASS_V, "Vv", MATCH_VMXORMM, MASK_VMXORMM, match_vd_eq_vs1_eq_vs2, INSN_ALIAS},
++{"vmset.m",    0, INSN_CLASS_V, "Vv", MATCH_VMXNORMM, MASK_VMXNORMM, match_vd_eq_vs1_eq_vs2, INSN_ALIAS},
++{"vmnot.m",    0, INSN_CLASS_V, "Vd,Vu", MATCH_VMNANDMM, MASK_VMNANDMM, match_vs1_eq_vs2, INSN_ALIAS},
++
++{"vmand.mm",   0, INSN_CLASS_V, "Vd,Vt,Vs", MATCH_VMANDMM, MASK_VMANDMM, match_opcode, 0},
++{"vmnand.mm",  0, INSN_CLASS_V, "Vd,Vt,Vs", MATCH_VMNANDMM, MASK_VMNANDMM, match_opcode, 0},
++{"vmandnot.mm",0, INSN_CLASS_V, "Vd,Vt,Vs", MATCH_VMANDNOTMM, MASK_VMANDNOTMM, match_opcode, 0},
++{"vmxor.mm",   0, INSN_CLASS_V, "Vd,Vt,Vs", MATCH_VMXORMM, MASK_VMXORMM, match_opcode, 0},
++{"vmor.mm",    0, INSN_CLASS_V, "Vd,Vt,Vs", MATCH_VMORMM, MASK_VMORMM, match_opcode, 0},
++{"vmnor.mm",   0, INSN_CLASS_V, "Vd,Vt,Vs", MATCH_VMNORMM, MASK_VMNORMM, match_opcode, 0},
++{"vmornot.mm", 0, INSN_CLASS_V, "Vd,Vt,Vs", MATCH_VMORNOTMM, MASK_VMORNOTMM, match_opcode, 0},
++{"vmxnor.mm",  0, INSN_CLASS_V, "Vd,Vt,Vs", MATCH_VMXNORMM, MASK_VMXNORMM, match_opcode, 0},
++
++{"vpopc.m",    0, INSN_CLASS_V, "d,VtVm", MATCH_VPOPCM, MASK_VPOPCM, match_opcode, 0},
++{"vfirst.m",   0, INSN_CLASS_V, "d,VtVm", MATCH_VFIRSTM, MASK_VFIRSTM, match_opcode, 0},
++{"vmsbf.m",    0, INSN_CLASS_V, "Vd,VtVm", MATCH_VMSBFM, MASK_VMSBFM, match_opcode, 0},
++{"vmsif.m",    0, INSN_CLASS_V, "Vd,VtVm", MATCH_VMSIFM, MASK_VMSIFM, match_opcode, 0},
++{"vmsof.m",    0, INSN_CLASS_V, "Vd,VtVm", MATCH_VMSOFM, MASK_VMSOFM, match_opcode, 0},
++{"viota.m",    0, INSN_CLASS_V, "Vd,VtVm", MATCH_VIOTAM, MASK_VIOTAM, match_vd_neq_vs2_neq_vm, 0},
++{"vid.v",      0, INSN_CLASS_V, "VdVm", MATCH_VIDV, MASK_VIDV, match_opcode, 0},
++
++{"vmv.x.s",    0, INSN_CLASS_V, "d,Vt", MATCH_VMVXS, MASK_VMVXS, match_opcode, 0},
++{"vmv.s.x",    0, INSN_CLASS_V, "Vd,s", MATCH_VMVSX, MASK_VMVSX, match_opcode, 0},
++
++{"vfmv.f.s",   0, INSN_CLASS_V_AND_F, "D,Vt", MATCH_VFMVFS, MASK_VFMVFS, match_opcode, 0},
++{"vfmv.s.f",   0, INSN_CLASS_V_AND_F, "Vd,S", MATCH_VFMVSF, MASK_VFMVSF, match_opcode, 0},
++
++{"vslideup.vx",0, INSN_CLASS_V, "Vd,Vt,sVm", MATCH_VSLIDEUPVX, MASK_VSLIDEUPVX, match_vd_neq_vs2, 0},
++{"vslideup.vi",0, INSN_CLASS_V, "Vd,Vt,VjVm", MATCH_VSLIDEUPVI, MASK_VSLIDEUPVI, match_vd_neq_vs2, 0},
++{"vslidedown.vx",0,INSN_CLASS_V, "Vd,Vt,sVm", MATCH_VSLIDEDOWNVX, MASK_VSLIDEDOWNVX, match_opcode, 0},
++{"vslidedown.vi",0,INSN_CLASS_V, "Vd,Vt,VjVm", MATCH_VSLIDEDOWNVI, MASK_VSLIDEDOWNVI, match_opcode, 0},
++
++{"vslide1up.vx",    0, INSN_CLASS_V, "Vd,Vt,sVm", MATCH_VSLIDE1UPVX, MASK_VSLIDE1UPVX, match_vd_neq_vs2, 0},
++{"vslide1down.vx",  0, INSN_CLASS_V, "Vd,Vt,sVm", MATCH_VSLIDE1DOWNVX, MASK_VSLIDE1DOWNVX, match_opcode, 0},
++{"vfslide1up.vf",   0, INSN_CLASS_V_AND_F, "Vd,Vt,SVm", MATCH_VFSLIDE1UPVF, MASK_VFSLIDE1UPVF, match_vd_neq_vs2, 0},
++{"vfslide1down.vf", 0, INSN_CLASS_V_AND_F, "Vd,Vt,SVm", MATCH_VFSLIDE1DOWNVF, MASK_VFSLIDE1DOWNVF, match_opcode, 0},
++
++{"vrgather.vv",0, INSN_CLASS_V, "Vd,Vt,VsVm", MATCH_VRGATHERVV, MASK_VRGATHERVV, match_vd_neq_vs1_neq_vs2_neq_vm, 0},
++{"vrgather.vx",0, INSN_CLASS_V, "Vd,Vt,sVm", MATCH_VRGATHERVX, MASK_VRGATHERVX, match_vd_neq_vs2_neq_vm, 0},
++{"vrgather.vi",0, INSN_CLASS_V, "Vd,Vt,VjVm", MATCH_VRGATHERVI, MASK_VRGATHERVI, match_vd_neq_vs2_neq_vm, 0},
++
++{"vcompress.vm",0, INSN_CLASS_V, "Vd,Vt,Vs", MATCH_VCOMPRESSVM, MASK_VCOMPRESSVM, match_vd_neq_vs1_neq_vs2_neq_vm, 0},
++
++{"vmv1r.v",    0, INSN_CLASS_V, "Vd,Vt", MATCH_VMV1RV, MASK_VMV1RV, match_vmv_nf_rv, 0},
++{"vmv2r.v",    0, INSN_CLASS_V, "Vd,Vt", MATCH_VMV2RV, MASK_VMV2RV, match_vmv_nf_rv, 0},
++{"vmv4r.v",    0, INSN_CLASS_V, "Vd,Vt", MATCH_VMV4RV, MASK_VMV4RV, match_vmv_nf_rv, 0},
++{"vmv8r.v",    0, INSN_CLASS_V, "Vd,Vt", MATCH_VMV8RV, MASK_VMV8RV, match_vmv_nf_rv, 0},
++
++{"vdot.vv",    0, INSN_CLASS_V,  "Vd,Vt,VsVm", MATCH_VDOTVV, MASK_VDOTVV, match_opcode, 0},
++{"vdotu.vv",   0, INSN_CLASS_V,  "Vd,Vt,VsVm", MATCH_VDOTUVV, MASK_VDOTUVV, match_opcode, 0},
++{"vfdot.vv",   0, INSN_CLASS_V,  "Vd,Vt,VsVm", MATCH_VFDOTVV, MASK_VFDOTVV, match_opcode, 0},
++/* END RVV */
++
+ /* Terminate the list.  */
+ {0, 0, INSN_CLASS_NONE, 0, 0, 0, 0, 0}
+ };
+@@ -797,6 +2027,26 @@ const struct riscv_opcode riscv_insn_types[] =
+ {"r",       0, INSN_CLASS_F,  "O4,F3,F7,d,S,T",     0,    0,  match_opcode, 0 },
+ {"r",       0, INSN_CLASS_F,  "O4,F3,F7,D,S,T",     0,    0,  match_opcode, 0 },
+ 
++{"r",       0, INSN_CLASS_V,        "O4,F3,F7,Vd,s,t",    0,    0,  match_opcode, 0 },
++{"r",       0, INSN_CLASS_V_AND_F,  "O4,F3,F7,Vd,S,t",    0,    0,  match_opcode, 0 },
++{"r",       0, INSN_CLASS_V_AND_F,  "O4,F3,F7,Vd,s,T",    0,    0,  match_opcode, 0 },
++{"r",       0, INSN_CLASS_V_AND_F,  "O4,F3,F7,Vd,S,T",    0,    0,  match_opcode, 0 },
++{"r",       0, INSN_CLASS_V,        "O4,F3,F7,d,Vs,t",    0,    0,  match_opcode, 0 },
++{"r",       0, INSN_CLASS_V_AND_F,  "O4,F3,F7,D,Vs,t",    0,    0,  match_opcode, 0 },
++{"r",       0, INSN_CLASS_V_AND_F,  "O4,F3,F7,d,Vs,T",    0,    0,  match_opcode, 0 },
++{"r",       0, INSN_CLASS_V_AND_F,  "O4,F3,F7,D,Vs,T",    0,    0,  match_opcode, 0 },
++{"r",       0, INSN_CLASS_V,        "O4,F3,F7,d,s,Vt",    0,    0,  match_opcode, 0 },
++{"r",       0, INSN_CLASS_V_AND_F,  "O4,F3,F7,D,s,Vt",    0,    0,  match_opcode, 0 },
++{"r",       0, INSN_CLASS_V_AND_F,  "O4,F3,F7,d,S,Vt",    0,    0,  match_opcode, 0 },
++{"r",       0, INSN_CLASS_V_AND_F,  "O4,F3,F7,D,S,Vt",    0,    0,  match_opcode, 0 },
++{"r",       0, INSN_CLASS_V,        "O4,F3,F7,Vd,Vs,t",   0,    0,  match_opcode, 0 },
++{"r",       0, INSN_CLASS_V_AND_F,  "O4,F3,F7,Vd,Vs,T",   0,    0,  match_opcode, 0 },
++{"r",       0, INSN_CLASS_V,        "O4,F3,F7,Vd,s,Vt",   0,    0,  match_opcode, 0 },
++{"r",       0, INSN_CLASS_V_AND_F,  "O4,F3,F7,Vd,S,Vt",   0,    0,  match_opcode, 0 },
++{"r",       0, INSN_CLASS_V,        "O4,F3,F7,d,Vs,Vt",   0,    0,  match_opcode, 0 },
++{"r",       0, INSN_CLASS_V_AND_F,  "O4,F3,F7,D,Vs,Vt",   0,    0,  match_opcode, 0 },
++{"r",       0, INSN_CLASS_V,        "O4,F3,F7,Vd,Vs,Vt",  0,    0,  match_opcode, 0 },
++
+ {"r",       0, INSN_CLASS_I,  "O4,F3,F2,d,s,t,r",   0,    0,  match_opcode, 0 },
+ {"r",       0, INSN_CLASS_F,  "O4,F3,F2,D,s,t,r",   0,    0,  match_opcode, 0 },
+ {"r",       0, INSN_CLASS_F,  "O4,F3,F2,d,S,t,r",   0,    0,  match_opcode, 0 },
+-- 
+2.33.0
+

+ 132 - 0
recipes-devtools/gdb/files/0013-Extend-the-VL-nf-R-and-VS-nf-R-instruction-when-nf-i.patch

@@ -0,0 +1,132 @@
+From 3eca424ccd778b50ce4a0b862c79afcd57fc3a82 Mon Sep 17 00:00:00 2001
+From: Nelson Chu <nelson.chu@sifive.com>
+Date: Fri, 3 Jul 2020 12:54:09 +0800
+Subject: [PATCH 13/48] Extend the VL<nf>R and VS<nf>R instruction, when <nf>
+ is 2, 4, 8.
+
+These instruction are added back in the risc-v vector spec,
+
+commit 0fec0e257cca5e389a0e1774e7d5aaac729b4ad2,
+Added clarifications on loads/stores.
+
+Note that the base V extension only enable the single register load/store
+variant with <nf> is 0.  It is clear to me that how to enable other register
+load/store is <nf> is 2, 4, 8, so I will add the limitation when it is
+clarified.
+---
+ gas/testsuite/gas/riscv/vector-insns.d | 12 ++++++++++++
+ gas/testsuite/gas/riscv/vector-insns.s | 13 +++++++++++++
+ include/opcode/riscv-opc.h             | 17 +++++++++++++++--
+ opcodes/riscv-opc.c                    |  7 +++++++
+ 4 files changed, 47 insertions(+), 2 deletions(-)
+
+diff --git a/gas/testsuite/gas/riscv/vector-insns.d b/gas/testsuite/gas/riscv/vector-insns.d
+index 5e7267c3f8..70366fb787 100644
+--- a/gas/testsuite/gas/riscv/vector-insns.d
++++ b/gas/testsuite/gas/riscv/vector-insns.d
+@@ -1396,8 +1396,20 @@ Disassembly of section .text:
+ [ 	]+[0-9a-f]+:[ 	]+f1057207[ 	]+vlseg8e1024ff.v[ 	]+v4,\(a0\),v0.t
+ [ 	]+[0-9a-f]+:[ 	]+02850187[ 	]+vl1r.v[ 	]+v3,\(a0\)
+ [ 	]+[0-9a-f]+:[ 	]+02850187[ 	]+vl1r.v[ 	]+v3,\(a0\)
++[ 	]+[0-9a-f]+:[ 	]+22850107[ 	]+vl2r.v[ 	]+v2,\(a0\)
++[ 	]+[0-9a-f]+:[ 	]+22850107[ 	]+vl2r.v[ 	]+v2,\(a0\)
++[ 	]+[0-9a-f]+:[ 	]+62850207[ 	]+vl4r.v[ 	]+v4,\(a0\)
++[ 	]+[0-9a-f]+:[ 	]+62850207[ 	]+vl4r.v[ 	]+v4,\(a0\)
++[ 	]+[0-9a-f]+:[ 	]+e2850407[ 	]+vl8r.v[ 	]+v8,\(a0\)
++[ 	]+[0-9a-f]+:[ 	]+e2850407[ 	]+vl8r.v[ 	]+v8,\(a0\)
+ [ 	]+[0-9a-f]+:[ 	]+028581a7[ 	]+vs1r.v[ 	]+v3,\(a1\)
+ [ 	]+[0-9a-f]+:[ 	]+028581a7[ 	]+vs1r.v[ 	]+v3,\(a1\)
++[ 	]+[0-9a-f]+:[ 	]+22858127[ 	]+vs2r.v[ 	]+v2,\(a1\)
++[ 	]+[0-9a-f]+:[ 	]+22858127[ 	]+vs2r.v[ 	]+v2,\(a1\)
++[ 	]+[0-9a-f]+:[ 	]+62858227[ 	]+vs4r.v[ 	]+v4,\(a1\)
++[ 	]+[0-9a-f]+:[ 	]+62858227[ 	]+vs4r.v[ 	]+v4,\(a1\)
++[ 	]+[0-9a-f]+:[ 	]+e2858427[ 	]+vs8r.v[ 	]+v8,\(a1\)
++[ 	]+[0-9a-f]+:[ 	]+e2858427[ 	]+vs8r.v[ 	]+v8,\(a1\)
+ [ 	]+[0-9a-f]+:[ 	]+0685822f[ 	]+vamoaddei8.v[ 	]+v4,\(a1\),v8,v4
+ [ 	]+[0-9a-f]+:[ 	]+0285822f[ 	]+vamoaddei8.v[ 	]+zero,\(a1\),v8,v4
+ [ 	]+[0-9a-f]+:[ 	]+0485822f[ 	]+vamoaddei8.v[ 	]+v4,\(a1\),v8,v4,v0.t
+diff --git a/gas/testsuite/gas/riscv/vector-insns.s b/gas/testsuite/gas/riscv/vector-insns.s
+index 8b9a894418..edd94d7d29 100644
+--- a/gas/testsuite/gas/riscv/vector-insns.s
++++ b/gas/testsuite/gas/riscv/vector-insns.s
+@@ -1644,8 +1644,21 @@
+ 
+ 	vl1r.v v3, (a0)
+ 	vl1r.v v3, 0(a0)
++	vl2r.v v2, (a0)
++	vl2r.v v2, 0(a0)
++	vl4r.v v4, (a0)
++	vl4r.v v4, 0(a0)
++	vl8r.v v8, (a0)
++	vl8r.v v8, 0(a0)
++
+ 	vs1r.v v3, (a1)
+ 	vs1r.v v3, 0(a1)
++	vs2r.v v2, (a1)
++	vs2r.v v2, 0(a1)
++	vs4r.v v4, (a1)
++	vs4r.v v4, 0(a1)
++	vs8r.v v8, (a1)
++	vs8r.v v8, 0(a1)
+ 
+ 	vamoaddei8.v v4, (a1), v8, v4
+ 	vamoaddei8.v x0, (a1), v8, v4
+diff --git a/include/opcode/riscv-opc.h b/include/opcode/riscv-opc.h
+index 6ec4c2a33a..579bae2670 100644
+--- a/include/opcode/riscv-opc.h
++++ b/include/opcode/riscv-opc.h
+@@ -611,8 +611,8 @@ NF MEW MOP VM LUMOP/RS2 RS1 WIDTH VD opcode
+ 000 - 11 x xxxxx xxxxx --- xxxxx 0100111 VSXE<EEW>I
+ 000 - 01 x xxxxx xxxxx --- xxxxx 0100111 VSUXE<EEW>I
+ 000 - 00 x 10000 xxxxx --- xxxxx 0000111 VLE<EEW>FF
+-000 0 00 1 01000 xxxxx 000 xxxxx 0000111 VL<nf>R, nf = 1
+-000 0 00 1 01000 xxxxx 000 xxxxx 0100111 VS<nf>R, nf = 1
++xxx 0 00 1 01000 xxxxx 000 xxxxx 0000111 VL<nf>R, nf = 1,2,4,8
++xxx 0 00 1 01000 xxxxx 000 xxxxx 0100111 VS<nf>R, nf = 1,2,4,8
+ 
+ xxx - 00 x 00000 xxxxx --- xxxxx 0000111 VLSEG<nf>E<EEW>
+ xxx - 00 x 00000 xxxxx --- xxxxx 0100111 VSSEG<nf>E<EEW>
+@@ -1577,8 +1577,21 @@ xxx - 00 x 10000 xxxxx --- xxxxx 0000111 VLSEG<nf>E<EEW>FF
+ 
+ #define MATCH_VL1RV  0x02800007
+ #define MASK_VL1RV   0xfff0707f
++#define MATCH_VL2RV  0x22800007
++#define MASK_VL2RV   0xfff0707f
++#define MATCH_VL4RV  0x62800007
++#define MASK_VL4RV   0xfff0707f
++#define MATCH_VL8RV  0xe2800007
++#define MASK_VL8RV   0xfff0707f
++
+ #define MATCH_VS1RV  0x02800027
+ #define MASK_VS1RV   0xfff0707f
++#define MATCH_VS2RV  0x22800027
++#define MASK_VS2RV   0xfff0707f
++#define MATCH_VS4RV  0x62800027
++#define MASK_VS4RV   0xfff0707f
++#define MATCH_VS8RV  0xe2800027
++#define MASK_VS8RV   0xfff0707f
+ 
+ /* Temporary AMO encoding info
+ 
+diff --git a/opcodes/riscv-opc.c b/opcodes/riscv-opc.c
+index fcd87e2261..ce9b10e411 100644
+--- a/opcodes/riscv-opc.c
++++ b/opcodes/riscv-opc.c
+@@ -1563,7 +1563,14 @@ const struct riscv_opcode riscv_opcodes[] =
+ {"vlseg8e1024ff.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s)Vm", MATCH_VLSEG8E1024FFV, MASK_VLSEG8E1024FFV, match_vd_neq_vm, INSN_DREF },
+ 
+ {"vl1r.v",  0, INSN_CLASS_V,  "Vd,0(s)", MATCH_VL1RV, MASK_VL1RV, match_opcode, INSN_DREF },
++{"vl2r.v",  0, INSN_CLASS_V,  "Vd,0(s)", MATCH_VL2RV, MASK_VL2RV, match_opcode, INSN_DREF },
++{"vl4r.v",  0, INSN_CLASS_V,  "Vd,0(s)", MATCH_VL4RV, MASK_VL4RV, match_opcode, INSN_DREF },
++{"vl8r.v",  0, INSN_CLASS_V,  "Vd,0(s)", MATCH_VL8RV, MASK_VL8RV, match_opcode, INSN_DREF },
++
+ {"vs1r.v",  0, INSN_CLASS_V,  "Vd,0(s)", MATCH_VS1RV, MASK_VS1RV, match_opcode, INSN_DREF },
++{"vs2r.v",  0, INSN_CLASS_V,  "Vd,0(s)", MATCH_VS2RV, MASK_VS2RV, match_opcode, INSN_DREF },
++{"vs4r.v",  0, INSN_CLASS_V,  "Vd,0(s)", MATCH_VS4RV, MASK_VS4RV, match_opcode, INSN_DREF },
++{"vs8r.v",  0, INSN_CLASS_V,  "Vd,0(s)", MATCH_VS8RV, MASK_VS8RV, match_opcode, INSN_DREF },
+ 
+ {"vamoaddei8.v",   0, INSN_CLASS_V_OR_ZVAMO,  "Ve,0(s),Vt,VfVm", MATCH_VAMOADDEI8V, MASK_VAMOADDEI8V, match_opcode, INSN_DREF},
+ {"vamoswapei8.v",  0, INSN_CLASS_V_OR_ZVAMO,  "Ve,0(s),Vt,VfVm", MATCH_VAMOSWAPEI8V, MASK_VAMOSWAPEI8V, match_opcode, INSN_DREF},
+-- 
+2.33.0
+

+ 212 - 0
recipes-devtools/gdb/files/0014-Remove-Vector-indexed-instruction-when-EEW-128.patch

@@ -0,0 +1,212 @@
+From f9e8a9be0538c55b9bbe7a85b0cbce1a0d5cd574 Mon Sep 17 00:00:00 2001
+From: Nelson Chu <nelson.chu@sifive.com>
+Date: Mon, 6 Jul 2020 13:27:29 +0800
+Subject: [PATCH 14/48] Remove Vector indexed instruction when EEW >= 128.
+
+These instruction are removed in the risc-v vector spec,
+
+commit 0fec0e257cca5e389a0e1774e7d5aaac729b4ad2,
+Added clarifications on loads/stores.
+---
+ gas/testsuite/gas/riscv/vector-insns.d | 36 -----------------------
+ gas/testsuite/gas/riscv/vector-insns.s | 40 --------------------------
+ include/opcode/riscv-opc.h             | 30 ++-----------------
+ opcodes/riscv-opc.c                    | 12 --------
+ 4 files changed, 3 insertions(+), 115 deletions(-)
+
+diff --git a/gas/testsuite/gas/riscv/vector-insns.d b/gas/testsuite/gas/riscv/vector-insns.d
+index 70366fb787..634ff2945c 100644
+--- a/gas/testsuite/gas/riscv/vector-insns.d
++++ b/gas/testsuite/gas/riscv/vector-insns.d
+@@ -158,42 +158,6 @@ Disassembly of section .text:
+ [ 	]+[0-9a-f]+:[ 	]+06c57227[ 	]+vsuxei64.v[ 	]+v4,\(a0\),v12
+ [ 	]+[0-9a-f]+:[ 	]+06c57227[ 	]+vsuxei64.v[ 	]+v4,\(a0\),v12
+ [ 	]+[0-9a-f]+:[ 	]+04c57227[ 	]+vsuxei64.v[ 	]+v4,\(a0\),v12,v0.t
+-[ 	]+[0-9a-f]+:[ 	]+1ec50207[ 	]+vlxei128.v[ 	]+v4,\(a0\),v12
+-[ 	]+[0-9a-f]+:[ 	]+1ec50207[ 	]+vlxei128.v[ 	]+v4,\(a0\),v12
+-[ 	]+[0-9a-f]+:[ 	]+1cc50207[ 	]+vlxei128.v[ 	]+v4,\(a0\),v12,v0.t
+-[ 	]+[0-9a-f]+:[ 	]+1ec50227[ 	]+vsxei128.v[ 	]+v4,\(a0\),v12
+-[ 	]+[0-9a-f]+:[ 	]+1ec50227[ 	]+vsxei128.v[ 	]+v4,\(a0\),v12
+-[ 	]+[0-9a-f]+:[ 	]+1cc50227[ 	]+vsxei128.v[ 	]+v4,\(a0\),v12,v0.t
+-[ 	]+[0-9a-f]+:[ 	]+16c50227[ 	]+vsuxei128.v[ 	]+v4,\(a0\),v12
+-[ 	]+[0-9a-f]+:[ 	]+16c50227[ 	]+vsuxei128.v[ 	]+v4,\(a0\),v12
+-[ 	]+[0-9a-f]+:[ 	]+14c50227[ 	]+vsuxei128.v[ 	]+v4,\(a0\),v12,v0.t
+-[ 	]+[0-9a-f]+:[ 	]+1ec55207[ 	]+vlxei256.v[ 	]+v4,\(a0\),v12
+-[ 	]+[0-9a-f]+:[ 	]+1ec55207[ 	]+vlxei256.v[ 	]+v4,\(a0\),v12
+-[ 	]+[0-9a-f]+:[ 	]+1cc55207[ 	]+vlxei256.v[ 	]+v4,\(a0\),v12,v0.t
+-[ 	]+[0-9a-f]+:[ 	]+1ec55227[ 	]+vsxei256.v[ 	]+v4,\(a0\),v12
+-[ 	]+[0-9a-f]+:[ 	]+1ec55227[ 	]+vsxei256.v[ 	]+v4,\(a0\),v12
+-[ 	]+[0-9a-f]+:[ 	]+1cc55227[ 	]+vsxei256.v[ 	]+v4,\(a0\),v12,v0.t
+-[ 	]+[0-9a-f]+:[ 	]+16c55227[ 	]+vsuxei256.v[ 	]+v4,\(a0\),v12
+-[ 	]+[0-9a-f]+:[ 	]+16c55227[ 	]+vsuxei256.v[ 	]+v4,\(a0\),v12
+-[ 	]+[0-9a-f]+:[ 	]+14c55227[ 	]+vsuxei256.v[ 	]+v4,\(a0\),v12,v0.t
+-[ 	]+[0-9a-f]+:[ 	]+1ec56207[ 	]+vlxei512.v[ 	]+v4,\(a0\),v12
+-[ 	]+[0-9a-f]+:[ 	]+1ec56207[ 	]+vlxei512.v[ 	]+v4,\(a0\),v12
+-[ 	]+[0-9a-f]+:[ 	]+1cc56207[ 	]+vlxei512.v[ 	]+v4,\(a0\),v12,v0.t
+-[ 	]+[0-9a-f]+:[ 	]+1ec56227[ 	]+vsxei512.v[ 	]+v4,\(a0\),v12
+-[ 	]+[0-9a-f]+:[ 	]+1ec56227[ 	]+vsxei512.v[ 	]+v4,\(a0\),v12
+-[ 	]+[0-9a-f]+:[ 	]+1cc56227[ 	]+vsxei512.v[ 	]+v4,\(a0\),v12,v0.t
+-[ 	]+[0-9a-f]+:[ 	]+16c56227[ 	]+vsuxei512.v[ 	]+v4,\(a0\),v12
+-[ 	]+[0-9a-f]+:[ 	]+16c56227[ 	]+vsuxei512.v[ 	]+v4,\(a0\),v12
+-[ 	]+[0-9a-f]+:[ 	]+14c56227[ 	]+vsuxei512.v[ 	]+v4,\(a0\),v12,v0.t
+-[ 	]+[0-9a-f]+:[ 	]+1ec57207[ 	]+vlxei1024.v[ 	]+v4,\(a0\),v12
+-[ 	]+[0-9a-f]+:[ 	]+1ec57207[ 	]+vlxei1024.v[ 	]+v4,\(a0\),v12
+-[ 	]+[0-9a-f]+:[ 	]+1cc57207[ 	]+vlxei1024.v[ 	]+v4,\(a0\),v12,v0.t
+-[ 	]+[0-9a-f]+:[ 	]+1ec57227[ 	]+vsxei1024.v[ 	]+v4,\(a0\),v12
+-[ 	]+[0-9a-f]+:[ 	]+1ec57227[ 	]+vsxei1024.v[ 	]+v4,\(a0\),v12
+-[ 	]+[0-9a-f]+:[ 	]+1cc57227[ 	]+vsxei1024.v[ 	]+v4,\(a0\),v12,v0.t
+-[ 	]+[0-9a-f]+:[ 	]+16c57227[ 	]+vsuxei1024.v[ 	]+v4,\(a0\),v12
+-[ 	]+[0-9a-f]+:[ 	]+16c57227[ 	]+vsuxei1024.v[ 	]+v4,\(a0\),v12
+-[ 	]+[0-9a-f]+:[ 	]+14c57227[ 	]+vsuxei1024.v[ 	]+v4,\(a0\),v12,v0.t
+ [ 	]+[0-9a-f]+:[ 	]+03050207[ 	]+vle8ff.v[ 	]+v4,\(a0\)
+ [ 	]+[0-9a-f]+:[ 	]+03050207[ 	]+vle8ff.v[ 	]+v4,\(a0\)
+ [ 	]+[0-9a-f]+:[ 	]+01050207[ 	]+vle8ff.v[ 	]+v4,\(a0\),v0.t
+diff --git a/gas/testsuite/gas/riscv/vector-insns.s b/gas/testsuite/gas/riscv/vector-insns.s
+index edd94d7d29..e6cfcad9ba 100644
+--- a/gas/testsuite/gas/riscv/vector-insns.s
++++ b/gas/testsuite/gas/riscv/vector-insns.s
+@@ -170,46 +170,6 @@
+ 	vsuxei64.v v4, 0(a0), v12
+ 	vsuxei64.v v4, (a0), v12, v0.t
+ 
+-	vlxei128.v v4, (a0), v12
+-	vlxei128.v v4, 0(a0), v12
+-	vlxei128.v v4, (a0), v12, v0.t
+-	vsxei128.v v4, (a0), v12
+-	vsxei128.v v4, 0(a0), v12
+-	vsxei128.v v4, (a0), v12, v0.t
+-	vsuxei128.v v4, (a0), v12
+-	vsuxei128.v v4, 0(a0), v12
+-	vsuxei128.v v4, (a0), v12, v0.t
+-
+-	vlxei256.v v4, (a0), v12
+-	vlxei256.v v4, 0(a0), v12
+-	vlxei256.v v4, (a0), v12, v0.t
+-	vsxei256.v v4, (a0), v12
+-	vsxei256.v v4, 0(a0), v12
+-	vsxei256.v v4, (a0), v12, v0.t
+-	vsuxei256.v v4, (a0), v12
+-	vsuxei256.v v4, 0(a0), v12
+-	vsuxei256.v v4, (a0), v12, v0.t
+-
+-	vlxei512.v v4, (a0), v12
+-	vlxei512.v v4, 0(a0), v12
+-	vlxei512.v v4, (a0), v12, v0.t
+-	vsxei512.v v4, (a0), v12
+-	vsxei512.v v4, 0(a0), v12
+-	vsxei512.v v4, (a0), v12, v0.t
+-	vsuxei512.v v4, (a0), v12
+-	vsuxei512.v v4, 0(a0), v12
+-	vsuxei512.v v4, (a0), v12, v0.t
+-
+-	vlxei1024.v v4, (a0), v12
+-	vlxei1024.v v4, 0(a0), v12
+-	vlxei1024.v v4, (a0), v12, v0.t
+-	vsxei1024.v v4, (a0), v12
+-	vsxei1024.v v4, 0(a0), v12
+-	vsxei1024.v v4, (a0), v12, v0.t
+-	vsuxei1024.v v4, (a0), v12
+-	vsuxei1024.v v4, 0(a0), v12
+-	vsuxei1024.v v4, (a0), v12, v0.t
+-
+ 	vle8ff.v v4, (a0)
+ 	vle8ff.v v4, 0(a0)
+ 	vle8ff.v v4, (a0), v0.t
+diff --git a/include/opcode/riscv-opc.h b/include/opcode/riscv-opc.h
+index 579bae2670..e196e27736 100644
+--- a/include/opcode/riscv-opc.h
++++ b/include/opcode/riscv-opc.h
+@@ -607,9 +607,9 @@ NF MEW MOP VM LUMOP/RS2 RS1 WIDTH VD opcode
+ 000 - 00 x 00000 xxxxx --- xxxxx 0100111 VSE<EEW>
+ 000 - 10 x xxxxx xxxxx --- xxxxx 0000111 VLSE<EEW>
+ 000 - 10 x xxxxx xxxxx --- xxxxx 0100111 VSSE<EEW>
+-000 - 11 x xxxxx xxxxx --- xxxxx 0000111 VLXE<EEW>I
+-000 - 11 x xxxxx xxxxx --- xxxxx 0100111 VSXE<EEW>I
+-000 - 01 x xxxxx xxxxx --- xxxxx 0100111 VSUXE<EEW>I
++000 0 11 x xxxxx xxxxx --- xxxxx 0000111 VLXE<EEW>I
++000 0 11 x xxxxx xxxxx --- xxxxx 0100111 VSXE<EEW>I
++000 0 01 x xxxxx xxxxx --- xxxxx 0100111 VSUXE<EEW>I
+ 000 - 00 x 10000 xxxxx --- xxxxx 0000111 VLE<EEW>FF
+ xxx 0 00 1 01000 xxxxx 000 xxxxx 0000111 VL<nf>R, nf = 1,2,4,8
+ xxx 0 00 1 01000 xxxxx 000 xxxxx 0100111 VS<nf>R, nf = 1,2,4,8
+@@ -699,14 +699,6 @@ xxx - 00 x 10000 xxxxx --- xxxxx 0000111 VLSEG<nf>E<EEW>FF
+ #define MASK_VLXEI32V    0xfc00707f
+ #define MATCH_VLXEI64V   0x0c007007
+ #define MASK_VLXEI64V    0xfc00707f
+-#define MATCH_VLXEI128V  0x1c000007
+-#define MASK_VLXEI128V   0xfc00707f
+-#define MATCH_VLXEI256V  0x1c005007
+-#define MASK_VLXEI256V   0xfc00707f
+-#define MATCH_VLXEI512V  0x1c006007
+-#define MASK_VLXEI512V   0xfc00707f
+-#define MATCH_VLXEI1024V 0x1c007007
+-#define MASK_VLXEI1024V  0xfc00707f
+ 
+ #define MATCH_VSXEI8V    0x0c000027
+ #define MASK_VSXEI8V     0xfc00707f
+@@ -716,14 +708,6 @@ xxx - 00 x 10000 xxxxx --- xxxxx 0000111 VLSEG<nf>E<EEW>FF
+ #define MASK_VSXEI32V    0xfc00707f
+ #define MATCH_VSXEI64V   0x0c007027
+ #define MASK_VSXEI64V    0xfc00707f
+-#define MATCH_VSXEI128V  0x1c000027
+-#define MASK_VSXEI128V   0xfc00707f
+-#define MATCH_VSXEI256V  0x1c005027
+-#define MASK_VSXEI256V   0xfc00707f
+-#define MATCH_VSXEI512V  0x1c006027
+-#define MASK_VSXEI512V   0xfc00707f
+-#define MATCH_VSXEI1024V 0x1c007027
+-#define MASK_VSXEI1024V  0xfc00707f
+ 
+ #define MATCH_VSUXEI8V    0x04000027
+ #define MASK_VSUXEI8V     0xfc00707f
+@@ -733,14 +717,6 @@ xxx - 00 x 10000 xxxxx --- xxxxx 0000111 VLSEG<nf>E<EEW>FF
+ #define MASK_VSUXEI32V    0xfc00707f
+ #define MATCH_VSUXEI64V   0x04007027
+ #define MASK_VSUXEI64V    0xfc00707f
+-#define MATCH_VSUXEI128V  0x14000027
+-#define MASK_VSUXEI128V   0xfc00707f
+-#define MATCH_VSUXEI256V  0x14005027
+-#define MASK_VSUXEI256V   0xfc00707f
+-#define MATCH_VSUXEI512V  0x14006027
+-#define MASK_VSUXEI512V   0xfc00707f
+-#define MATCH_VSUXEI1024V 0x14007027
+-#define MASK_VSUXEI1024V  0xfc00707f
+ 
+ #define MATCH_VLE8FFV    0x01000007
+ #define MASK_VLE8FFV     0xfdf0707f
+diff --git a/opcodes/riscv-opc.c b/opcodes/riscv-opc.c
+index ce9b10e411..475c65d7e5 100644
+--- a/opcodes/riscv-opc.c
++++ b/opcodes/riscv-opc.c
+@@ -1106,28 +1106,16 @@ const struct riscv_opcode riscv_opcodes[] =
+ {"vlxei16.v",  0, INSN_CLASS_V,  "Vd,0(s),VtVm", MATCH_VLXEI16V, MASK_VLXEI16V, match_opcode, INSN_DREF },
+ {"vlxei32.v",  0, INSN_CLASS_V,  "Vd,0(s),VtVm", MATCH_VLXEI32V, MASK_VLXEI32V, match_opcode, INSN_DREF },
+ {"vlxei64.v",  0, INSN_CLASS_V,  "Vd,0(s),VtVm", MATCH_VLXEI64V, MASK_VLXEI64V, match_opcode, INSN_DREF },
+-{"vlxei128.v", 0, INSN_CLASS_V,  "Vd,0(s),VtVm", MATCH_VLXEI128V, MASK_VLXEI128V, match_opcode, INSN_DREF },
+-{"vlxei256.v", 0, INSN_CLASS_V,  "Vd,0(s),VtVm", MATCH_VLXEI256V, MASK_VLXEI256V, match_opcode, INSN_DREF },
+-{"vlxei512.v", 0, INSN_CLASS_V,  "Vd,0(s),VtVm", MATCH_VLXEI512V, MASK_VLXEI512V, match_opcode, INSN_DREF },
+-{"vlxei1024.v",0, INSN_CLASS_V,  "Vd,0(s),VtVm", MATCH_VLXEI1024V, MASK_VLXEI1024V, match_opcode, INSN_DREF },
+ 
+ {"vsxei8.v",   0, INSN_CLASS_V,  "Vd,0(s),VtVm", MATCH_VSXEI8V, MASK_VSXEI8V, match_opcode, INSN_DREF },
+ {"vsxei16.v",  0, INSN_CLASS_V,  "Vd,0(s),VtVm", MATCH_VSXEI16V, MASK_VSXEI16V, match_opcode, INSN_DREF },
+ {"vsxei32.v",  0, INSN_CLASS_V,  "Vd,0(s),VtVm", MATCH_VSXEI32V, MASK_VSXEI32V, match_opcode, INSN_DREF },
+ {"vsxei64.v",  0, INSN_CLASS_V,  "Vd,0(s),VtVm", MATCH_VSXEI64V, MASK_VSXEI64V, match_opcode, INSN_DREF },
+-{"vsxei128.v", 0, INSN_CLASS_V,  "Vd,0(s),VtVm", MATCH_VSXEI128V, MASK_VSXEI128V, match_opcode, INSN_DREF },
+-{"vsxei256.v", 0, INSN_CLASS_V,  "Vd,0(s),VtVm", MATCH_VSXEI256V, MASK_VSXEI256V, match_opcode, INSN_DREF },
+-{"vsxei512.v", 0, INSN_CLASS_V,  "Vd,0(s),VtVm", MATCH_VSXEI512V, MASK_VSXEI512V, match_opcode, INSN_DREF },
+-{"vsxei1024.v",0, INSN_CLASS_V,  "Vd,0(s),VtVm", MATCH_VSXEI1024V, MASK_VSXEI1024V, match_opcode, INSN_DREF },
+ 
+ {"vsuxei8.v",   0, INSN_CLASS_V,  "Vd,0(s),VtVm", MATCH_VSUXEI8V, MASK_VSUXEI8V, match_opcode, INSN_DREF },
+ {"vsuxei16.v",  0, INSN_CLASS_V,  "Vd,0(s),VtVm", MATCH_VSUXEI16V, MASK_VSUXEI16V, match_opcode, INSN_DREF },
+ {"vsuxei32.v",  0, INSN_CLASS_V,  "Vd,0(s),VtVm", MATCH_VSUXEI32V, MASK_VSUXEI32V, match_opcode, INSN_DREF },
+ {"vsuxei64.v",  0, INSN_CLASS_V,  "Vd,0(s),VtVm", MATCH_VSUXEI64V, MASK_VSUXEI64V, match_opcode, INSN_DREF },
+-{"vsuxei128.v", 0, INSN_CLASS_V,  "Vd,0(s),VtVm", MATCH_VSUXEI128V, MASK_VSUXEI128V, match_opcode, INSN_DREF },
+-{"vsuxei256.v", 0, INSN_CLASS_V,  "Vd,0(s),VtVm", MATCH_VSUXEI256V, MASK_VSUXEI256V, match_opcode, INSN_DREF },
+-{"vsuxei512.v", 0, INSN_CLASS_V,  "Vd,0(s),VtVm", MATCH_VSUXEI512V, MASK_VSUXEI512V, match_opcode, INSN_DREF },
+-{"vsuxei1024.v",0, INSN_CLASS_V,  "Vd,0(s),VtVm", MATCH_VSUXEI1024V, MASK_VSUXEI1024V, match_opcode, INSN_DREF },
+ 
+ {"vle8ff.v",    0, INSN_CLASS_V,  "Vd,0(s)Vm", MATCH_VLE8FFV, MASK_VLE8FFV, match_opcode, INSN_DREF },
+ {"vle16ff.v",   0, INSN_CLASS_V,  "Vd,0(s)Vm", MATCH_VLE16FFV, MASK_VLE16FFV, match_opcode, INSN_DREF },
+-- 
+2.33.0
+

+ 103 - 0
recipes-devtools/gdb/files/0015-Add-assembly-pseudo-instructions-vncvt.x.x.v.patch

@@ -0,0 +1,103 @@
+From ed4bec347a9a77c8845a43d6dfe23317bc8091e0 Mon Sep 17 00:00:00 2001
+From: Nelson Chu <nelson.chu@sifive.com>
+Date: Mon, 6 Jul 2020 14:31:14 +0800
+Subject: [PATCH 15/48] Add assembly pseudo instructions vncvt.x.x.v.
+
+An integer value can be halved in width using the narrowing integer
+shift instructions with a scalar operand of x0. Can define assembly
+pseudo instruction "vncvt.x.x.v vd,vs,vm" to "vnsrl.wx vd,vs,x0,vm".
+---
+ gas/testsuite/gas/riscv/vector-insns-fail-05.l | 3 +++
+ gas/testsuite/gas/riscv/vector-insns-fail-05.s | 6 ++++++
+ gas/testsuite/gas/riscv/vector-insns.d         | 2 ++
+ gas/testsuite/gas/riscv/vector-insns.s         | 4 ++++
+ include/opcode/riscv-opc.h                     | 3 +++
+ opcodes/riscv-opc.c                            | 2 ++
+ 6 files changed, 20 insertions(+)
+
+diff --git a/gas/testsuite/gas/riscv/vector-insns-fail-05.l b/gas/testsuite/gas/riscv/vector-insns-fail-05.l
+index fa519ffcf9..f2bee3d1e0 100644
+--- a/gas/testsuite/gas/riscv/vector-insns-fail-05.l
++++ b/gas/testsuite/gas/riscv/vector-insns-fail-05.l
+@@ -1,4 +1,7 @@
+ .*: Assembler messages:
++.*Error: illegal operands `vncvt.x.x.v v2,v2'
++.*Error: illegal operands `vncvt.x.x.v v2,v3'
++.*Error: illegal operands `vncvt.x.x.v v3,v2'
+ .*Error: illegal operands `vnsrl.wv v2,v2,v4'
+ .*Error: illegal operands `vnsrl.wv v2,v3,v4'
+ .*Error: illegal operands `vnsrl.wv v3,v2,v4'
+diff --git a/gas/testsuite/gas/riscv/vector-insns-fail-05.s b/gas/testsuite/gas/riscv/vector-insns-fail-05.s
+index 2ec027299c..6b68680fd9 100644
+--- a/gas/testsuite/gas/riscv/vector-insns-fail-05.s
++++ b/gas/testsuite/gas/riscv/vector-insns-fail-05.s
+@@ -1,5 +1,11 @@
+ # Narrowing Vector Arithmetic Instructions
+ 
++	vncvt.x.x.v v0, v2		# OK
++	vncvt.x.x.v v2, v2		# vd overlap vs2
++	vncvt.x.x.v v2, v3		# vs2 should be multiple of 2
++	vncvt.x.x.v v3, v2		# vd overlap vs2
++	vncvt.x.x.v v0, v2, v0.t	# We can't know the LMUL, so skip the vm checking
++
+ 	vnsrl.wv v0, v2, v4		# OK
+ 	vnsrl.wv v2, v2, v4		# vd overlap vs2
+ 	vnsrl.wv v2, v3, v4		# vs2 should be multiple of 2
+diff --git a/gas/testsuite/gas/riscv/vector-insns.d b/gas/testsuite/gas/riscv/vector-insns.d
+index 634ff2945c..99eb5abf70 100644
+--- a/gas/testsuite/gas/riscv/vector-insns.d
++++ b/gas/testsuite/gas/riscv/vector-insns.d
+@@ -1796,6 +1796,8 @@ Disassembly of section .text:
+ [ 	]+[0-9a-f]+:[ 	]+a485c257[ 	]+vsra.vx[ 	]+v4,v8,a1,v0.t
+ [ 	]+[0-9a-f]+:[ 	]+a480b257[ 	]+vsra.vi[ 	]+v4,v8,1,v0.t
+ [ 	]+[0-9a-f]+:[ 	]+a48fb257[ 	]+vsra.vi[ 	]+v4,v8,31,v0.t
++[ 	]+[0-9a-f]+:[ 	]+b2804257[ 	]+vncvt.x.x.v[ 	]+v4,v8
++[ 	]+[0-9a-f]+:[ 	]+b0804257[ 	]+vncvt.x.x.v[ 	]+v4,v8,v0.t
+ [ 	]+[0-9a-f]+:[ 	]+b2860257[ 	]+vnsrl.wv[ 	]+v4,v8,v12
+ [ 	]+[0-9a-f]+:[ 	]+b285c257[ 	]+vnsrl.wx[ 	]+v4,v8,a1
+ [ 	]+[0-9a-f]+:[ 	]+b280b257[ 	]+vnsrl.wi[ 	]+v4,v8,1
+diff --git a/gas/testsuite/gas/riscv/vector-insns.s b/gas/testsuite/gas/riscv/vector-insns.s
+index e6cfcad9ba..3b489685c9 100644
+--- a/gas/testsuite/gas/riscv/vector-insns.s
++++ b/gas/testsuite/gas/riscv/vector-insns.s
+@@ -2076,6 +2076,10 @@
+ 	vsra.vi v4, v8, 1, v0.t
+ 	vsra.vi v4, v8, 31, v0.t
+ 
++	# Aliases
++	vncvt.x.x.v v4, v8
++	vncvt.x.x.v v4, v8, v0.t
++
+ 	vnsrl.wv v4, v8, v12
+ 	vnsrl.wx v4, v8, a1
+ 	vnsrl.wi v4, v8, 1
+diff --git a/include/opcode/riscv-opc.h b/include/opcode/riscv-opc.h
+index e196e27736..4e4ecc91d0 100644
+--- a/include/opcode/riscv-opc.h
++++ b/include/opcode/riscv-opc.h
+@@ -2096,6 +2096,9 @@ funct6 VM  VS2  VS1/RS1/IMM funct3 VD   opcode
+ #define MATCH_VSRAVI 0xa4003057
+ #define MASK_VSRAVI  0xfc00707f
+ 
++#define MATCH_VNCVTXXV 0xb0004057
++#define MASK_VNCVTXXV  0xfc0ff07f
++
+ #define MATCH_VNSRLWV  0xb0000057
+ #define MASK_VNSRLWV   0xfc00707f
+ #define MATCH_VNSRLWX  0xb0004057
+diff --git a/opcodes/riscv-opc.c b/opcodes/riscv-opc.c
+index 475c65d7e5..66c3046150 100644
+--- a/opcodes/riscv-opc.c
++++ b/opcodes/riscv-opc.c
+@@ -1673,6 +1673,8 @@ const struct riscv_opcode riscv_opcodes[] =
+ {"vsra.vx",    0, INSN_CLASS_V,  "Vd,Vt,sVm", MATCH_VSRAVX, MASK_VSRAVX, match_opcode, 0 },
+ {"vsra.vi",    0, INSN_CLASS_V,  "Vd,Vt,VjVm", MATCH_VSRAVI, MASK_VSRAVI, match_opcode, 0 },
+ 
++{"vncvt.x.x.v",0, INSN_CLASS_V,  "Vd,VtVm", MATCH_VNCVTXXV, MASK_VNCVTXXV, match_narrow_vd_neq_vs2, INSN_ALIAS },
++
+ {"vnsrl.wv",   0, INSN_CLASS_V,  "Vd,Vt,VsVm", MATCH_VNSRLWV, MASK_VNSRLWV, match_narrow_vd_neq_vs2, 0 },
+ {"vnsrl.wx",   0, INSN_CLASS_V,  "Vd,Vt,sVm", MATCH_VNSRLWX, MASK_VNSRLWX, match_narrow_vd_neq_vs2, 0 },
+ {"vnsrl.wi",   0, INSN_CLASS_V,  "Vd,Vt,VjVm", MATCH_VNSRLWI, MASK_VNSRLWI, match_narrow_vd_neq_vs2, 0 },
+-- 
+2.33.0
+

+ 26 - 0
recipes-devtools/gdb/files/0016-Update-the-vector-spec-version-tag-Version-1.0-draft.patch

@@ -0,0 +1,26 @@
+From 9b95cdf2e388df25849206c0eab086f63b12c3e9 Mon Sep 17 00:00:00 2001
+From: Nelson Chu <nelson.chu@sifive.com>
+Date: Mon, 6 Jul 2020 14:46:21 +0800
+Subject: [PATCH 16/48] Update the vector spec version tag (Version
+ 1.0-draft-20200702).
+
+---
+ include/opcode/riscv-opc.h | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+diff --git a/include/opcode/riscv-opc.h b/include/opcode/riscv-opc.h
+index 4e4ecc91d0..71eb770f5a 100644
+--- a/include/opcode/riscv-opc.h
++++ b/include/opcode/riscv-opc.h
+@@ -549,7 +549,7 @@
+ #define MASK_C_SDSP  0xe003
+ 
+ /* RVV */
+-/* Version 1.0-draft-20200516.  */
++/* Version 1.0-draft-20200702.  */
+ 
+ #define MATCH_VSETVL  0x80007057
+ #define MASK_VSETVL   0xfe00707f
+-- 
+2.33.0
+

+ 134 - 0
recipes-devtools/gdb/files/0017-Added-reciprocal-and-reciprocal-square-root-estimate.patch

@@ -0,0 +1,134 @@
+From aefce8023a15dad4835317dbc26c5e8bf93061f2 Mon Sep 17 00:00:00 2001
+From: Nelson Chu <nelson.chu@sifive.com>
+Date: Mon, 6 Jul 2020 15:31:05 +0800
+Subject: [PATCH 17/48] Added reciprocal and reciprocal square-root estimate
+ instruction.
+
+Add new instruction vfrsqrte7.v and vfrece7.v.  The former set VFUNARY1 (vs1)
+to 00100, and the later set VFUNARY1 to 00101.
+---
+ gas/testsuite/gas/riscv/vector-insns.d |  8 ++++++--
+ gas/testsuite/gas/riscv/vector-insns.s |  9 ++++++---
+ include/opcode/riscv-opc.h             | 15 ++++++++++-----
+ opcodes/riscv-opc.c                    |  5 +++--
+ 4 files changed, 25 insertions(+), 12 deletions(-)
+
+diff --git a/gas/testsuite/gas/riscv/vector-insns.d b/gas/testsuite/gas/riscv/vector-insns.d
+index 99eb5abf70..8909e822a0 100644
+--- a/gas/testsuite/gas/riscv/vector-insns.d
++++ b/gas/testsuite/gas/riscv/vector-insns.d
+@@ -2168,6 +2168,12 @@ Disassembly of section .text:
+ [ 	]+[0-9a-f]+:[ 	]+fc865257[ 	]+vfwnmsac.vf[ 	]+v4,fa2,v8,v0.t
+ [ 	]+[0-9a-f]+:[ 	]+4e801257[ 	]+vfsqrt.v[ 	]+v4,v8
+ [ 	]+[0-9a-f]+:[ 	]+4c801257[ 	]+vfsqrt.v[ 	]+v4,v8,v0.t
++[ 	]+[0-9a-f]+:[ 	]+4e821257[ 	]+vfrsqrte7.v[ 	]+v4,v8
++[ 	]+[0-9a-f]+:[ 	]+4c821257[ 	]+vfrsqrte7.v[ 	]+v4,v8,v0.t
++[ 	]+[0-9a-f]+:[ 	]+4e829257[ 	]+vfrece7.v[ 	]+v4,v8
++[ 	]+[0-9a-f]+:[ 	]+4c829257[ 	]+vfrece7.v[ 	]+v4,v8,v0.t
++[ 	]+[0-9a-f]+:[ 	]+4e881257[ 	]+vfclass.v[ 	]+v4,v8
++[ 	]+[0-9a-f]+:[ 	]+4c881257[ 	]+vfclass.v[ 	]+v4,v8,v0.t
+ [ 	]+[0-9a-f]+:[ 	]+12861257[ 	]+vfmin.vv[ 	]+v4,v8,v12
+ [ 	]+[0-9a-f]+:[ 	]+12865257[ 	]+vfmin.vf[ 	]+v4,v8,fa2
+ [ 	]+[0-9a-f]+:[ 	]+1a861257[ 	]+vfmax.vv[ 	]+v4,v8,v12
+@@ -2212,8 +2218,6 @@ Disassembly of section .text:
+ [ 	]+[0-9a-f]+:[ 	]+64865257[ 	]+vmfle.vf[ 	]+v4,v8,fa2,v0.t
+ [ 	]+[0-9a-f]+:[ 	]+74865257[ 	]+vmfgt.vf[ 	]+v4,v8,fa2,v0.t
+ [ 	]+[0-9a-f]+:[ 	]+7c865257[ 	]+vmfge.vf[ 	]+v4,v8,fa2,v0.t
+-[ 	]+[0-9a-f]+:[ 	]+4e881257[ 	]+vfclass.v[ 	]+v4,v8
+-[ 	]+[0-9a-f]+:[ 	]+4c881257[ 	]+vfclass.v[ 	]+v4,v8,v0.t
+ [ 	]+[0-9a-f]+:[ 	]+5c865257[ 	]+vfmerge.vfm[ 	]+v4,v8,fa2,v0
+ [ 	]+[0-9a-f]+:[ 	]+5e05d257[ 	]+vfmv.v.f[ 	]+v4,fa1
+ [ 	]+[0-9a-f]+:[ 	]+4a801257[ 	]+vfcvt.xu.f.v[ 	]+v4,v8
+diff --git a/gas/testsuite/gas/riscv/vector-insns.s b/gas/testsuite/gas/riscv/vector-insns.s
+index 3b489685c9..39da92bab7 100644
+--- a/gas/testsuite/gas/riscv/vector-insns.s
++++ b/gas/testsuite/gas/riscv/vector-insns.s
+@@ -2474,6 +2474,12 @@
+ 
+ 	vfsqrt.v v4, v8
+ 	vfsqrt.v v4, v8, v0.t
++	vfrsqrte7.v v4, v8
++	vfrsqrte7.v v4, v8, v0.t
++	vfrece7.v v4, v8
++	vfrece7.v v4, v8, v0.t
++	vfclass.v v4, v8
++	vfclass.v v4, v8, v0.t
+ 
+ 	vfmin.vv v4, v8, v12
+ 	vfmin.vf v4, v8, fa2
+@@ -2524,9 +2530,6 @@
+ 	vmfgt.vf v4, v8, fa2, v0.t
+ 	vmfge.vf v4, v8, fa2, v0.t
+ 
+-	vfclass.v v4, v8
+-	vfclass.v v4, v8, v0.t
+-
+ 	vfmerge.vfm v4, v8, fa2, v0
+ 	vfmv.v.f v4, fa1
+ 
+diff --git a/include/opcode/riscv-opc.h b/include/opcode/riscv-opc.h
+index 71eb770f5a..2da0574cc0 100644
+--- a/include/opcode/riscv-opc.h
++++ b/include/opcode/riscv-opc.h
+@@ -1950,6 +1950,8 @@ vs1
+ VFUNARY1
+ vs1
+ 00000 vfsqrt.v
++00100 vfrsqrte7.v
++00101 vfrece7.v
+ 10000 vfclass.v
+ 
+ 31-26 25 24-20   19-15     14-12 11-7 6-0
+@@ -2441,8 +2443,14 @@ funct6 VM  VS2  VS1/RS1/IMM funct3 VD   opcode
+ #define MATCH_VFWNMSACVF 0xfc005057
+ #define MASK_VFWNMSACVF  0xfc00707f
+ 
+-#define MATCH_VFSQRTV 0x4c001057
+-#define MASK_VFSQRTV  0xfc0ff07f
++#define MATCH_VFSQRTV    0x4c001057
++#define MASK_VFSQRTV     0xfc0ff07f
++#define MATCH_VFRSQRTE7V 0x4c021057
++#define MASK_VFRSQRTE7V  0xfc0ff07f
++#define MATCH_VFRECE7V   0x4c029057
++#define MASK_VFRECE7V    0xfc0ff07f
++#define MATCH_VFCLASSV   0x4c081057
++#define MASK_VFCLASSV    0xfc0ff07f
+ 
+ #define MATCH_VFMINVV  0x10001057
+ #define MASK_VFMINVV   0xfc00707f
+@@ -2487,9 +2495,6 @@ funct6 VM  VS2  VS1/RS1/IMM funct3 VD   opcode
+ #define MATCH_VMFGEVF  0x7c005057
+ #define MASK_VMFGEVF   0xfc00707f
+ 
+-#define MATCH_VFCLASSV 0x4c081057
+-#define MASK_VFCLASSV  0xfc0ff07f
+-
+ #define MATCH_VFMERGEVFM 0x5c005057
+ #define MASK_VFMERGEVFM  0xfe00707f
+ #define MATCH_VFMVVF     0x5e005057
+diff --git a/opcodes/riscv-opc.c b/opcodes/riscv-opc.c
+index 66c3046150..cb89f59208 100644
+--- a/opcodes/riscv-opc.c
++++ b/opcodes/riscv-opc.c
+@@ -1875,6 +1875,9 @@ const struct riscv_opcode riscv_opcodes[] =
+ {"vfwnmsac.vf", 0, INSN_CLASS_V_AND_F, "Vd,S,VtVm", MATCH_VFWNMSACVF, MASK_VFWNMSACVF, match_widen_vd_neq_vs2_neq_vm, 0},
+ 
+ {"vfsqrt.v",   0, INSN_CLASS_V_AND_F, "Vd,VtVm", MATCH_VFSQRTV, MASK_VFSQRTV, match_opcode, 0},
++{"vfrsqrte7.v",0, INSN_CLASS_V_AND_F, "Vd,VtVm", MATCH_VFRSQRTE7V, MASK_VFRSQRTE7V, match_opcode, 0},
++{"vfrece7.v",  0, INSN_CLASS_V_AND_F, "Vd,VtVm", MATCH_VFRECE7V, MASK_VFRECE7V, match_opcode, 0},
++{"vfclass.v",  0, INSN_CLASS_V_AND_F, "Vd,VtVm", MATCH_VFCLASSV, MASK_VFCLASSV, match_opcode, 0},
+ 
+ {"vfmin.vv",   0, INSN_CLASS_V_AND_F, "Vd,Vt,VsVm", MATCH_VFMINVV, MASK_VFMINVV, match_opcode, 0},
+ {"vfmin.vf",   0, INSN_CLASS_V_AND_F, "Vd,Vt,SVm", MATCH_VFMINVF, MASK_VFMINVF, match_opcode, 0},
+@@ -1903,8 +1906,6 @@ const struct riscv_opcode riscv_opcodes[] =
+ {"vmfgt.vv",    0, INSN_CLASS_V_AND_F, "Vd,Vs,VtVm", MATCH_VMFLTVV, MASK_VMFLTVV, match_opcode, INSN_ALIAS},
+ {"vmfge.vv",   0, INSN_CLASS_V_AND_F, "Vd,Vs,VtVm", MATCH_VMFLEVV, MASK_VMFLEVV, match_opcode, INSN_ALIAS},
+ 
+-{"vfclass.v",  0, INSN_CLASS_V_AND_F, "Vd,VtVm", MATCH_VFCLASSV, MASK_VFCLASSV, match_opcode, 0},
+-
+ {"vfmerge.vfm",0, INSN_CLASS_V_AND_F, "Vd,Vt,S,V0", MATCH_VFMERGEVFM, MASK_VFMERGEVFM, match_opcode, 0},
+ {"vfmv.v.f",   0, INSN_CLASS_V_AND_F, "Vd,S", MATCH_VFMVVF, MASK_VFMVVF, match_opcode, 0 },
+ 
+-- 
+2.33.0
+

+ 377 - 0
recipes-devtools/gdb/files/0018-Added-element-width-hint-to-whole-register-loads-sto.patch

@@ -0,0 +1,377 @@
+From 33636301c48d21eaf665355c124af357ef5777c2 Mon Sep 17 00:00:00 2001
+From: Nelson Chu <nelson.chu@sifive.com>
+Date: Mon, 6 Jul 2020 22:34:19 +0800
+Subject: [PATCH 18/48] Added element width hint to whole register
+ loads/stores.
+
+Add load instructions which have an EEW encoded in the `mew` and `width`.
+---
+ gas/testsuite/gas/riscv/vector-insns.d | 64 +++++++++++++++++
+ gas/testsuite/gas/riscv/vector-insns.s | 67 ++++++++++++++++++
+ include/opcode/riscv-opc.h             | 98 +++++++++++++++++++++-----
+ opcodes/riscv-opc.c                    | 43 +++++++++--
+ 4 files changed, 249 insertions(+), 23 deletions(-)
+
+diff --git a/gas/testsuite/gas/riscv/vector-insns.d b/gas/testsuite/gas/riscv/vector-insns.d
+index 8909e822a0..e53d2f3242 100644
+--- a/gas/testsuite/gas/riscv/vector-insns.d
++++ b/gas/testsuite/gas/riscv/vector-insns.d
+@@ -1360,12 +1360,76 @@ Disassembly of section .text:
+ [ 	]+[0-9a-f]+:[ 	]+f1057207[ 	]+vlseg8e1024ff.v[ 	]+v4,\(a0\),v0.t
+ [ 	]+[0-9a-f]+:[ 	]+02850187[ 	]+vl1r.v[ 	]+v3,\(a0\)
+ [ 	]+[0-9a-f]+:[ 	]+02850187[ 	]+vl1r.v[ 	]+v3,\(a0\)
++[ 	]+[0-9a-f]+:[ 	]+02850187[ 	]+vl1r.v[ 	]+v3,\(a0\)
++[ 	]+[0-9a-f]+:[ 	]+02850187[ 	]+vl1r.v[ 	]+v3,\(a0\)
++[ 	]+[0-9a-f]+:[ 	]+02855187[ 	]+vl1re16.v[ 	]+v3,\(a0\)
++[ 	]+[0-9a-f]+:[ 	]+02855187[ 	]+vl1re16.v[ 	]+v3,\(a0\)
++[ 	]+[0-9a-f]+:[ 	]+02856187[ 	]+vl1re32.v[ 	]+v3,\(a0\)
++[ 	]+[0-9a-f]+:[ 	]+02856187[ 	]+vl1re32.v[ 	]+v3,\(a0\)
++[ 	]+[0-9a-f]+:[ 	]+02857187[ 	]+vl1re64.v[ 	]+v3,\(a0\)
++[ 	]+[0-9a-f]+:[ 	]+02857187[ 	]+vl1re64.v[ 	]+v3,\(a0\)
++[ 	]+[0-9a-f]+:[ 	]+12850187[ 	]+vl1re128.v[ 	]+v3,\(a0\)
++[ 	]+[0-9a-f]+:[ 	]+12850187[ 	]+vl1re128.v[ 	]+v3,\(a0\)
++[ 	]+[0-9a-f]+:[ 	]+12855187[ 	]+vl1re256.v[ 	]+v3,\(a0\)
++[ 	]+[0-9a-f]+:[ 	]+12855187[ 	]+vl1re256.v[ 	]+v3,\(a0\)
++[ 	]+[0-9a-f]+:[ 	]+12856187[ 	]+vl1re512.v[ 	]+v3,\(a0\)
++[ 	]+[0-9a-f]+:[ 	]+12856187[ 	]+vl1re512.v[ 	]+v3,\(a0\)
++[ 	]+[0-9a-f]+:[ 	]+12857187[ 	]+vl1re1024.v[ 	]+v3,\(a0\)
++[ 	]+[0-9a-f]+:[ 	]+12857187[ 	]+vl1re1024.v[ 	]+v3,\(a0\)
++[ 	]+[0-9a-f]+:[ 	]+22850107[ 	]+vl2r.v[ 	]+v2,\(a0\)
++[ 	]+[0-9a-f]+:[ 	]+22850107[ 	]+vl2r.v[ 	]+v2,\(a0\)
+ [ 	]+[0-9a-f]+:[ 	]+22850107[ 	]+vl2r.v[ 	]+v2,\(a0\)
+ [ 	]+[0-9a-f]+:[ 	]+22850107[ 	]+vl2r.v[ 	]+v2,\(a0\)
++[ 	]+[0-9a-f]+:[ 	]+22855107[ 	]+vl2re16.v[ 	]+v2,\(a0\)
++[ 	]+[0-9a-f]+:[ 	]+22855107[ 	]+vl2re16.v[ 	]+v2,\(a0\)
++[ 	]+[0-9a-f]+:[ 	]+22856107[ 	]+vl2re32.v[ 	]+v2,\(a0\)
++[ 	]+[0-9a-f]+:[ 	]+22856107[ 	]+vl2re32.v[ 	]+v2,\(a0\)
++[ 	]+[0-9a-f]+:[ 	]+22857107[ 	]+vl2re64.v[ 	]+v2,\(a0\)
++[ 	]+[0-9a-f]+:[ 	]+22857107[ 	]+vl2re64.v[ 	]+v2,\(a0\)
++[ 	]+[0-9a-f]+:[ 	]+32850107[ 	]+vl2re128.v[ 	]+v2,\(a0\)
++[ 	]+[0-9a-f]+:[ 	]+32850107[ 	]+vl2re128.v[ 	]+v2,\(a0\)
++[ 	]+[0-9a-f]+:[ 	]+32855107[ 	]+vl2re256.v[ 	]+v2,\(a0\)
++[ 	]+[0-9a-f]+:[ 	]+32855107[ 	]+vl2re256.v[ 	]+v2,\(a0\)
++[ 	]+[0-9a-f]+:[ 	]+32856107[ 	]+vl2re512.v[ 	]+v2,\(a0\)
++[ 	]+[0-9a-f]+:[ 	]+32856107[ 	]+vl2re512.v[ 	]+v2,\(a0\)
++[ 	]+[0-9a-f]+:[ 	]+32857107[ 	]+vl2re1024.v[ 	]+v2,\(a0\)
++[ 	]+[0-9a-f]+:[ 	]+32857107[ 	]+vl2re1024.v[ 	]+v2,\(a0\)
+ [ 	]+[0-9a-f]+:[ 	]+62850207[ 	]+vl4r.v[ 	]+v4,\(a0\)
+ [ 	]+[0-9a-f]+:[ 	]+62850207[ 	]+vl4r.v[ 	]+v4,\(a0\)
++[ 	]+[0-9a-f]+:[ 	]+62850207[ 	]+vl4r.v[ 	]+v4,\(a0\)
++[ 	]+[0-9a-f]+:[ 	]+62850207[ 	]+vl4r.v[ 	]+v4,\(a0\)
++[ 	]+[0-9a-f]+:[ 	]+62855207[ 	]+vl4re16.v[ 	]+v4,\(a0\)
++[ 	]+[0-9a-f]+:[ 	]+62855207[ 	]+vl4re16.v[ 	]+v4,\(a0\)
++[ 	]+[0-9a-f]+:[ 	]+62856207[ 	]+vl4re32.v[ 	]+v4,\(a0\)
++[ 	]+[0-9a-f]+:[ 	]+62856207[ 	]+vl4re32.v[ 	]+v4,\(a0\)
++[ 	]+[0-9a-f]+:[ 	]+62857207[ 	]+vl4re64.v[ 	]+v4,\(a0\)
++[ 	]+[0-9a-f]+:[ 	]+62857207[ 	]+vl4re64.v[ 	]+v4,\(a0\)
++[ 	]+[0-9a-f]+:[ 	]+72850207[ 	]+vl4re128.v[ 	]+v4,\(a0\)
++[ 	]+[0-9a-f]+:[ 	]+72850207[ 	]+vl4re128.v[ 	]+v4,\(a0\)
++[ 	]+[0-9a-f]+:[ 	]+72855207[ 	]+vl4re256.v[ 	]+v4,\(a0\)
++[ 	]+[0-9a-f]+:[ 	]+72855207[ 	]+vl4re256.v[ 	]+v4,\(a0\)
++[ 	]+[0-9a-f]+:[ 	]+72856207[ 	]+vl4re512.v[ 	]+v4,\(a0\)
++[ 	]+[0-9a-f]+:[ 	]+72856207[ 	]+vl4re512.v[ 	]+v4,\(a0\)
++[ 	]+[0-9a-f]+:[ 	]+72857207[ 	]+vl4re1024.v[ 	]+v4,\(a0\)
++[ 	]+[0-9a-f]+:[ 	]+72857207[ 	]+vl4re1024.v[ 	]+v4,\(a0\)
++[ 	]+[0-9a-f]+:[ 	]+e2850407[ 	]+vl8r.v[ 	]+v8,\(a0\)
++[ 	]+[0-9a-f]+:[ 	]+e2850407[ 	]+vl8r.v[ 	]+v8,\(a0\)
+ [ 	]+[0-9a-f]+:[ 	]+e2850407[ 	]+vl8r.v[ 	]+v8,\(a0\)
+ [ 	]+[0-9a-f]+:[ 	]+e2850407[ 	]+vl8r.v[ 	]+v8,\(a0\)
++[ 	]+[0-9a-f]+:[ 	]+e2855407[ 	]+vl8re16.v[ 	]+v8,\(a0\)
++[ 	]+[0-9a-f]+:[ 	]+e2855407[ 	]+vl8re16.v[ 	]+v8,\(a0\)
++[ 	]+[0-9a-f]+:[ 	]+e2856407[ 	]+vl8re32.v[ 	]+v8,\(a0\)
++[ 	]+[0-9a-f]+:[ 	]+e2856407[ 	]+vl8re32.v[ 	]+v8,\(a0\)
++[ 	]+[0-9a-f]+:[ 	]+e2857407[ 	]+vl8re64.v[ 	]+v8,\(a0\)
++[ 	]+[0-9a-f]+:[ 	]+e2857407[ 	]+vl8re64.v[ 	]+v8,\(a0\)
++[ 	]+[0-9a-f]+:[ 	]+f2850407[ 	]+vl8re128.v[ 	]+v8,\(a0\)
++[ 	]+[0-9a-f]+:[ 	]+f2850407[ 	]+vl8re128.v[ 	]+v8,\(a0\)
++[ 	]+[0-9a-f]+:[ 	]+f2855407[ 	]+vl8re256.v[ 	]+v8,\(a0\)
++[ 	]+[0-9a-f]+:[ 	]+f2855407[ 	]+vl8re256.v[ 	]+v8,\(a0\)
++[ 	]+[0-9a-f]+:[ 	]+f2856407[ 	]+vl8re512.v[ 	]+v8,\(a0\)
++[ 	]+[0-9a-f]+:[ 	]+f2856407[ 	]+vl8re512.v[ 	]+v8,\(a0\)
++[ 	]+[0-9a-f]+:[ 	]+f2857407[ 	]+vl8re1024.v[ 	]+v8,\(a0\)
++[ 	]+[0-9a-f]+:[ 	]+f2857407[ 	]+vl8re1024.v[ 	]+v8,\(a0\)
+ [ 	]+[0-9a-f]+:[ 	]+028581a7[ 	]+vs1r.v[ 	]+v3,\(a1\)
+ [ 	]+[0-9a-f]+:[ 	]+028581a7[ 	]+vs1r.v[ 	]+v3,\(a1\)
+ [ 	]+[0-9a-f]+:[ 	]+22858127[ 	]+vs2r.v[ 	]+v2,\(a1\)
+diff --git a/gas/testsuite/gas/riscv/vector-insns.s b/gas/testsuite/gas/riscv/vector-insns.s
+index 39da92bab7..5046dd3bda 100644
+--- a/gas/testsuite/gas/riscv/vector-insns.s
++++ b/gas/testsuite/gas/riscv/vector-insns.s
+@@ -1604,12 +1604,79 @@
+ 
+ 	vl1r.v v3, (a0)
+ 	vl1r.v v3, 0(a0)
++	vl1re8.v v3, (a0)
++	vl1re8.v v3, 0(a0)
++	vl1re16.v v3, (a0)
++	vl1re16.v v3, 0(a0)
++	vl1re32.v v3, (a0)
++	vl1re32.v v3, 0(a0)
++	vl1re64.v v3, (a0)
++	vl1re64.v v3, 0(a0)
++	vl1re128.v v3, (a0)
++	vl1re128.v v3, 0(a0)
++	vl1re256.v v3, (a0)
++	vl1re256.v v3, 0(a0)
++	vl1re512.v v3, (a0)
++	vl1re512.v v3, 0(a0)
++	vl1re1024.v v3, (a0)
++	vl1re1024.v v3, 0(a0)
++
+ 	vl2r.v v2, (a0)
+ 	vl2r.v v2, 0(a0)
++	vl2re8.v v2, (a0)
++	vl2re8.v v2, 0(a0)
++	vl2re16.v v2, (a0)
++	vl2re16.v v2, 0(a0)
++	vl2re32.v v2, (a0)
++	vl2re32.v v2, 0(a0)
++	vl2re64.v v2, (a0)
++	vl2re64.v v2, 0(a0)
++	vl2re128.v v2, (a0)
++	vl2re128.v v2, 0(a0)
++	vl2re256.v v2, (a0)
++	vl2re256.v v2, 0(a0)
++	vl2re512.v v2, (a0)
++	vl2re512.v v2, 0(a0)
++	vl2re1024.v v2, (a0)
++	vl2re1024.v v2, 0(a0)
++
+ 	vl4r.v v4, (a0)
+ 	vl4r.v v4, 0(a0)
++	vl4re8.v v4, (a0)
++	vl4re8.v v4, 0(a0)
++	vl4re16.v v4, (a0)
++	vl4re16.v v4, 0(a0)
++	vl4re32.v v4, (a0)
++	vl4re32.v v4, 0(a0)
++	vl4re64.v v4, (a0)
++	vl4re64.v v4, 0(a0)
++	vl4re128.v v4, (a0)
++	vl4re128.v v4, 0(a0)
++	vl4re256.v v4, (a0)
++	vl4re256.v v4, 0(a0)
++	vl4re512.v v4, (a0)
++	vl4re512.v v4, 0(a0)
++	vl4re1024.v v4, (a0)
++	vl4re1024.v v4, 0(a0)
++
+ 	vl8r.v v8, (a0)
+ 	vl8r.v v8, 0(a0)
++	vl8re8.v v8, (a0)
++	vl8re8.v v8, 0(a0)
++	vl8re16.v v8, (a0)
++	vl8re16.v v8, 0(a0)
++	vl8re32.v v8, (a0)
++	vl8re32.v v8, 0(a0)
++	vl8re64.v v8, (a0)
++	vl8re64.v v8, 0(a0)
++	vl8re128.v v8, (a0)
++	vl8re128.v v8, 0(a0)
++	vl8re256.v v8, (a0)
++	vl8re256.v v8, 0(a0)
++	vl8re512.v v8, (a0)
++	vl8re512.v v8, 0(a0)
++	vl8re1024.v v8, (a0)
++	vl8re1024.v v8, 0(a0)
+ 
+ 	vs1r.v v3, (a1)
+ 	vs1r.v v3, 0(a1)
+diff --git a/include/opcode/riscv-opc.h b/include/opcode/riscv-opc.h
+index 2da0574cc0..a17a1e8ca3 100644
+--- a/include/opcode/riscv-opc.h
++++ b/include/opcode/riscv-opc.h
+@@ -558,13 +558,13 @@
+ 
+ /* Temporary Load/store encoding info
+ MOP load
+-00 unit-stride	VLE<EEW>, VLE<EEW>FF, VL<nf>RV (nf = 1)
++00 unit-stride	VLE<EEW>, VLE<EEW>FF, VL<nf>RE<EEW> (nf = 1, 2, 4, 8)
+ 01 reserved
+ 10 strided	VLSE<EEW>
+ 11 indexed	VLXEI<EEW>
+ 
+ MOP store
+-00 unit-stride		VSE<EEW>, VS<nf>RV (nf = 1)
++00 unit-stride		VSE<EEW>, VS<nf>R (nf = 1, 2, 4, 8)
+ 01 indexed-unordered	VSUXEI<EEW>
+ 10 strided		VSSE<EEW>
+ 11 indexed-ordered	VSXEI<EEW>
+@@ -587,20 +587,21 @@ SUMOP
+ 01xxx reserved, x!=0
+ 1xxxx reserved
+ 
++EEW =
+ MEW WIDTH
+ - ---
+ x 001	FLH/FSH
+ x 010	FLW/FSW
+ x 011	FLD/FSW
+ x 100	FLQ/FSQ
+-0 000	VLxE8/VSxE8
+-0 101	VLxE16/VSxE16
+-0 110	VLxE32/VSxE32
+-0 111	VLxE64/VSxE64
+-1 000	VLxE128/VSxE128
+-1 101	VLxE256/VSxE256
+-1 110	VLxE512/VSxE512
+-1 111	VLxE1024/VSxE1024
++0 000	VLxE8/VSxE8, VLxEI8/VSxEI8, VL<nf>RE8, VS<nf>R
++0 101	VLxE16/VSxE16, VLxEI16/VSxEI16, VL<nf>RE16
++0 110	VLxE32/VSxE32, VLxEI32/VSxEI32, VL<nf>RE32
++0 111	VLxE64/VSxE64, VLxEI64/VSxEI64, VL<nf>RE64
++1 000	VLxE128/VSxE128, VL<nf>RE128
++1 101	VLxE256/VSxE256, VL<nf>RE256
++1 110	VLxE512/VSxE512, VL<nf>RE512
++1 111	VLxE1024/VSxE1024, VL<nf>RE1024
+ 
+ NF MEW MOP VM LUMOP/RS2 RS1 WIDTH VD opcode
+ 000 - 00 x 00000 xxxxx --- xxxxx 0000111 VLE<EEW>
+@@ -611,7 +612,7 @@ NF MEW MOP VM LUMOP/RS2 RS1 WIDTH VD opcode
+ 000 0 11 x xxxxx xxxxx --- xxxxx 0100111 VSXE<EEW>I
+ 000 0 01 x xxxxx xxxxx --- xxxxx 0100111 VSUXE<EEW>I
+ 000 - 00 x 10000 xxxxx --- xxxxx 0000111 VLE<EEW>FF
+-xxx 0 00 1 01000 xxxxx 000 xxxxx 0000111 VL<nf>R, nf = 1,2,4,8
++xxx - 00 1 01000 xxxxx --- xxxxx 0000111 VL<nf>RE<EEW>, nf = 1,2,4,8
+ xxx 0 00 1 01000 xxxxx 000 xxxxx 0100111 VS<nf>R, nf = 1,2,4,8
+ 
+ xxx - 00 x 00000 xxxxx --- xxxxx 0000111 VLSEG<nf>E<EEW>
+@@ -1551,14 +1552,73 @@ xxx - 00 x 10000 xxxxx --- xxxxx 0000111 VLSEG<nf>E<EEW>FF
+ #define MATCH_VLSEG8E1024FFV  0xf1007007
+ #define MASK_VLSEG8E1024FFV   0xfdf0707f
+ 
+-#define MATCH_VL1RV  0x02800007
+-#define MASK_VL1RV   0xfff0707f
+-#define MATCH_VL2RV  0x22800007
+-#define MASK_VL2RV   0xfff0707f
+-#define MATCH_VL4RV  0x62800007
+-#define MASK_VL4RV   0xfff0707f
+-#define MATCH_VL8RV  0xe2800007
+-#define MASK_VL8RV   0xfff0707f
++#define MATCH_VL1RE8V    0x02800007
++#define MASK_VL1RE8V     0xfff0707f
++#define MATCH_VL1RE16V   0x02805007
++#define MASK_VL1RE16V    0xfff0707f
++#define MATCH_VL1RE32V   0x02806007
++#define MASK_VL1RE32V    0xfff0707f
++#define MATCH_VL1RE64V   0x02807007
++#define MASK_VL1RE64V    0xfff0707f
++#define MATCH_VL1RE128V  0x12800007
++#define MASK_VL1RE128V   0xfff0707f
++#define MATCH_VL1RE256V  0x12805007
++#define MASK_VL1RE256V   0xfff0707f
++#define MATCH_VL1RE512V  0x12806007
++#define MASK_VL1RE512V   0xfff0707f
++#define MATCH_VL1RE1024V 0x12807007
++#define MASK_VL1RE1024V  0xfff0707f
++
++#define MATCH_VL2RE8V    0x22800007
++#define MASK_VL2RE8V     0xfff0707f
++#define MATCH_VL2RE16V   0x22805007
++#define MASK_VL2RE16V    0xfff0707f
++#define MATCH_VL2RE32V   0x22806007
++#define MASK_VL2RE32V    0xfff0707f
++#define MATCH_VL2RE64V   0x22807007
++#define MASK_VL2RE64V    0xfff0707f
++#define MATCH_VL2RE128V  0x32800007
++#define MASK_VL2RE128V   0xfff0707f
++#define MATCH_VL2RE256V  0x32805007
++#define MASK_VL2RE256V   0xfff0707f
++#define MATCH_VL2RE512V  0x32806007
++#define MASK_VL2RE512V   0xfff0707f
++#define MATCH_VL2RE1024V 0x32807007
++#define MASK_VL2RE1024V  0xfff0707f
++
++#define MATCH_VL4RE8V    0x62800007
++#define MASK_VL4RE8V     0xfff0707f
++#define MATCH_VL4RE16V   0x62805007
++#define MASK_VL4RE16V    0xfff0707f
++#define MATCH_VL4RE32V   0x62806007
++#define MASK_VL4RE32V    0xfff0707f
++#define MATCH_VL4RE64V   0x62807007
++#define MASK_VL4RE64V    0xfff0707f
++#define MATCH_VL4RE128V  0x72800007
++#define MASK_VL4RE128V   0xfff0707f
++#define MATCH_VL4RE256V  0x72805007
++#define MASK_VL4RE256V   0xfff0707f
++#define MATCH_VL4RE512V  0x72806007
++#define MASK_VL4RE512V   0xfff0707f
++#define MATCH_VL4RE1024V 0x72807007
++#define MASK_VL4RE1024V  0xfff0707f
++
++#define MATCH_VL8RE8V    0xe2800007
++#define MASK_VL8RE8V     0xfff0707f
++#define MATCH_VL8RE16V   0xe2805007
++#define MASK_VL8RE16V    0xfff0707f
++#define MATCH_VL8RE32V   0xe2806007
++#define MASK_VL8RE32V    0xfff0707f
++#define MATCH_VL8RE64V   0xe2807007
++#define MASK_VL8RE64V    0xfff0707f
++#define MATCH_VL8RE128V  0xf2800007
++#define MASK_VL8RE128V   0xfff0707f
++#define MATCH_VL8RE256V  0xf2805007
++#define MASK_VL8RE256V   0xfff0707f
++#define MATCH_VL8RE512V  0xf2806007
++#define MASK_VL8RE512V   0xfff0707f
++#define MATCH_VL8RE1024V 0xf2807007
++#define MASK_VL8RE1024V  0xfff0707f
+ 
+ #define MATCH_VS1RV  0x02800027
+ #define MASK_VS1RV   0xfff0707f
+diff --git a/opcodes/riscv-opc.c b/opcodes/riscv-opc.c
+index cb89f59208..208d3ce31b 100644
+--- a/opcodes/riscv-opc.c
++++ b/opcodes/riscv-opc.c
+@@ -1550,10 +1550,45 @@ const struct riscv_opcode riscv_opcodes[] =
+ {"vlseg7e1024ff.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s)Vm", MATCH_VLSEG7E1024FFV, MASK_VLSEG7E1024FFV, match_vd_neq_vm, INSN_DREF },
+ {"vlseg8e1024ff.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s)Vm", MATCH_VLSEG8E1024FFV, MASK_VLSEG8E1024FFV, match_vd_neq_vm, INSN_DREF },
+ 
+-{"vl1r.v",  0, INSN_CLASS_V,  "Vd,0(s)", MATCH_VL1RV, MASK_VL1RV, match_opcode, INSN_DREF },
+-{"vl2r.v",  0, INSN_CLASS_V,  "Vd,0(s)", MATCH_VL2RV, MASK_VL2RV, match_opcode, INSN_DREF },
+-{"vl4r.v",  0, INSN_CLASS_V,  "Vd,0(s)", MATCH_VL4RV, MASK_VL4RV, match_opcode, INSN_DREF },
+-{"vl8r.v",  0, INSN_CLASS_V,  "Vd,0(s)", MATCH_VL8RV, MASK_VL8RV, match_opcode, INSN_DREF },
++{"vl1r.v",      0, INSN_CLASS_V,  "Vd,0(s)", MATCH_VL1RE8V, MASK_VL1RE8V, match_opcode, INSN_DREF|INSN_ALIAS },
++{"vl1re8.v",    0, INSN_CLASS_V,  "Vd,0(s)", MATCH_VL1RE8V, MASK_VL1RE8V, match_opcode, INSN_DREF },
++{"vl1re16.v",   0, INSN_CLASS_V,  "Vd,0(s)", MATCH_VL1RE16V, MASK_VL1RE16V, match_opcode, INSN_DREF },
++{"vl1re32.v",   0, INSN_CLASS_V,  "Vd,0(s)", MATCH_VL1RE32V, MASK_VL1RE32V, match_opcode, INSN_DREF },
++{"vl1re64.v",   0, INSN_CLASS_V,  "Vd,0(s)", MATCH_VL1RE64V, MASK_VL1RE64V, match_opcode, INSN_DREF },
++{"vl1re128.v",  0, INSN_CLASS_V,  "Vd,0(s)", MATCH_VL1RE128V, MASK_VL1RE128V, match_opcode, INSN_DREF },
++{"vl1re256.v",  0, INSN_CLASS_V,  "Vd,0(s)", MATCH_VL1RE256V, MASK_VL1RE256V, match_opcode, INSN_DREF },
++{"vl1re512.v",  0, INSN_CLASS_V,  "Vd,0(s)", MATCH_VL1RE512V, MASK_VL1RE512V, match_opcode, INSN_DREF },
++{"vl1re1024.v", 0, INSN_CLASS_V,  "Vd,0(s)", MATCH_VL1RE1024V, MASK_VL1RE1024V, match_opcode, INSN_DREF },
++
++{"vl2r.v",      0, INSN_CLASS_V,  "Vd,0(s)", MATCH_VL2RE8V, MASK_VL2RE8V, match_opcode, INSN_DREF|INSN_ALIAS },
++{"vl2re8.v",    0, INSN_CLASS_V,  "Vd,0(s)", MATCH_VL2RE8V, MASK_VL2RE8V, match_opcode, INSN_DREF },
++{"vl2re16.v",   0, INSN_CLASS_V,  "Vd,0(s)", MATCH_VL2RE16V, MASK_VL2RE16V, match_opcode, INSN_DREF },
++{"vl2re32.v",   0, INSN_CLASS_V,  "Vd,0(s)", MATCH_VL2RE32V, MASK_VL2RE32V, match_opcode, INSN_DREF },
++{"vl2re64.v",   0, INSN_CLASS_V,  "Vd,0(s)", MATCH_VL2RE64V, MASK_VL2RE64V, match_opcode, INSN_DREF },
++{"vl2re128.v",  0, INSN_CLASS_V,  "Vd,0(s)", MATCH_VL2RE128V, MASK_VL2RE128V, match_opcode, INSN_DREF },
++{"vl2re256.v",  0, INSN_CLASS_V,  "Vd,0(s)", MATCH_VL2RE256V, MASK_VL2RE256V, match_opcode, INSN_DREF },
++{"vl2re512.v",  0, INSN_CLASS_V,  "Vd,0(s)", MATCH_VL2RE512V, MASK_VL2RE512V, match_opcode, INSN_DREF },
++{"vl2re1024.v", 0, INSN_CLASS_V,  "Vd,0(s)", MATCH_VL2RE1024V, MASK_VL2RE1024V, match_opcode, INSN_DREF },
++
++{"vl4r.v",      0, INSN_CLASS_V,  "Vd,0(s)", MATCH_VL4RE8V, MASK_VL4RE8V, match_opcode, INSN_DREF|INSN_ALIAS },
++{"vl4re8.v",    0, INSN_CLASS_V,  "Vd,0(s)", MATCH_VL4RE8V, MASK_VL4RE8V, match_opcode, INSN_DREF },
++{"vl4re16.v",   0, INSN_CLASS_V,  "Vd,0(s)", MATCH_VL4RE16V, MASK_VL4RE16V, match_opcode, INSN_DREF },
++{"vl4re32.v",   0, INSN_CLASS_V,  "Vd,0(s)", MATCH_VL4RE32V, MASK_VL4RE32V, match_opcode, INSN_DREF },
++{"vl4re64.v",   0, INSN_CLASS_V,  "Vd,0(s)", MATCH_VL4RE64V, MASK_VL4RE64V, match_opcode, INSN_DREF },
++{"vl4re128.v",  0, INSN_CLASS_V,  "Vd,0(s)", MATCH_VL4RE128V, MASK_VL4RE128V, match_opcode, INSN_DREF },
++{"vl4re256.v",  0, INSN_CLASS_V,  "Vd,0(s)", MATCH_VL4RE256V, MASK_VL4RE256V, match_opcode, INSN_DREF },
++{"vl4re512.v",  0, INSN_CLASS_V,  "Vd,0(s)", MATCH_VL4RE512V, MASK_VL4RE512V, match_opcode, INSN_DREF },
++{"vl4re1024.v", 0, INSN_CLASS_V,  "Vd,0(s)", MATCH_VL4RE1024V, MASK_VL4RE1024V, match_opcode, INSN_DREF },
++
++{"vl8r.v",      0, INSN_CLASS_V,  "Vd,0(s)", MATCH_VL8RE8V, MASK_VL8RE8V, match_opcode, INSN_DREF|INSN_ALIAS },
++{"vl8re8.v",    0, INSN_CLASS_V,  "Vd,0(s)", MATCH_VL8RE8V, MASK_VL8RE8V, match_opcode, INSN_DREF },
++{"vl8re16.v",   0, INSN_CLASS_V,  "Vd,0(s)", MATCH_VL8RE16V, MASK_VL8RE16V, match_opcode, INSN_DREF },
++{"vl8re32.v",   0, INSN_CLASS_V,  "Vd,0(s)", MATCH_VL8RE32V, MASK_VL8RE32V, match_opcode, INSN_DREF },
++{"vl8re64.v",   0, INSN_CLASS_V,  "Vd,0(s)", MATCH_VL8RE64V, MASK_VL8RE64V, match_opcode, INSN_DREF },
++{"vl8re128.v",  0, INSN_CLASS_V,  "Vd,0(s)", MATCH_VL8RE128V, MASK_VL8RE128V, match_opcode, INSN_DREF },
++{"vl8re256.v",  0, INSN_CLASS_V,  "Vd,0(s)", MATCH_VL8RE256V, MASK_VL8RE256V, match_opcode, INSN_DREF },
++{"vl8re512.v",  0, INSN_CLASS_V,  "Vd,0(s)", MATCH_VL8RE512V, MASK_VL8RE512V, match_opcode, INSN_DREF },
++{"vl8re1024.v", 0, INSN_CLASS_V,  "Vd,0(s)", MATCH_VL8RE1024V, MASK_VL8RE1024V, match_opcode, INSN_DREF },
+ 
+ {"vs1r.v",  0, INSN_CLASS_V,  "Vd,0(s)", MATCH_VS1RV, MASK_VS1RV, match_opcode, INSN_DREF },
+ {"vs2r.v",  0, INSN_CLASS_V,  "Vd,0(s)", MATCH_VS2RV, MASK_VS2RV, match_opcode, INSN_DREF },
+-- 
+2.33.0
+

+ 26 - 0
recipes-devtools/gdb/files/0019-Update-the-vector-spec-version-tag-Version-1.0-draft.patch

@@ -0,0 +1,26 @@
+From 9d6a0b42daeecddb2bc855a3caed62b6ca1b44dd Mon Sep 17 00:00:00 2001
+From: Nelson Chu <nelson.chu@sifive.com>
+Date: Mon, 6 Jul 2020 22:36:34 +0800
+Subject: [PATCH 19/48] Update the vector spec version tag (Version
+ 1.0-draft-20200703).
+
+---
+ include/opcode/riscv-opc.h | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+diff --git a/include/opcode/riscv-opc.h b/include/opcode/riscv-opc.h
+index a17a1e8ca3..14527e8515 100644
+--- a/include/opcode/riscv-opc.h
++++ b/include/opcode/riscv-opc.h
+@@ -549,7 +549,7 @@
+ #define MASK_C_SDSP  0xe003
+ 
+ /* RVV */
+-/* Version 1.0-draft-20200702.  */
++/* Version 1.0-draft-20200703.  */
+ 
+ #define MATCH_VSETVL  0x80007057
+ #define MASK_VSETVL   0xfe00707f
+-- 
+2.33.0
+

+ 127 - 0
recipes-devtools/gdb/files/0020-Added-vrgatherei16-instruction.patch

@@ -0,0 +1,127 @@
+From 2e29338cd430f94e7504a96804f0a75112279992 Mon Sep 17 00:00:00 2001
+From: Nelson Chu <nelson.chu@sifive.com>
+Date: Mon, 20 Jul 2020 10:43:00 +0800
+Subject: [PATCH 20/48] Added vrgatherei16 instruction.
+
+---
+ gas/testsuite/gas/riscv/vector-insns-fail-06.l |  3 +++
+ gas/testsuite/gas/riscv/vector-insns-fail-06.s |  6 ++++++
+ gas/testsuite/gas/riscv/vector-insns.d         |  2 ++
+ gas/testsuite/gas/riscv/vector-insns.s         |  3 +++
+ include/opcode/riscv-opc.h                     | 16 +++++++++-------
+ opcodes/riscv-opc.c                            |  7 ++++---
+ 6 files changed, 27 insertions(+), 10 deletions(-)
+
+diff --git a/gas/testsuite/gas/riscv/vector-insns-fail-06.l b/gas/testsuite/gas/riscv/vector-insns-fail-06.l
+index 9a86dd37b5..4c540eb272 100644
+--- a/gas/testsuite/gas/riscv/vector-insns-fail-06.l
++++ b/gas/testsuite/gas/riscv/vector-insns-fail-06.l
+@@ -12,6 +12,9 @@
+ .*Error: illegal operands `vrgather.vx v0,v2,a4,v0.t'
+ .*Error: illegal operands `vrgather.vi v2,v2,1'
+ .*Error: illegal operands `vrgather.vi v0,v2,1,v0.t'
++.*Error: illegal operands `vrgatherei16.vv v2,v2,v4'
++.*Error: illegal operands `vrgatherei16.vv v4,v2,v4'
++.*Error: illegal operands `vrgatherei16.vv v0,v2,v4,v0.t'
+ .*Error: illegal operands `vcompress.vm v2,v2,v4'
+ .*Error: illegal operands `vcompress.vm v4,v2,v4'
+ .*Error: illegal operands `vmv2r.v v1,v2'
+diff --git a/gas/testsuite/gas/riscv/vector-insns-fail-06.s b/gas/testsuite/gas/riscv/vector-insns-fail-06.s
+index df0edd44c9..3a35aadb49 100644
+--- a/gas/testsuite/gas/riscv/vector-insns-fail-06.s
++++ b/gas/testsuite/gas/riscv/vector-insns-fail-06.s
+@@ -46,6 +46,12 @@
+ 	vrgather.vi v2, v2, 1		# vd overlap vs2
+ 	vrgather.vi v0, v2, 1, v0.t	# vd overlap vm
+ 
++	vrgatherei16.vv v0, v2, v4	# OK
++	vrgatherei16.vv v1, v2, v4	# OK
++	vrgatherei16.vv v2, v2, v4	# vd overlap vs2
++	vrgatherei16.vv v4, v2, v4	# vd overlap vs1
++	vrgatherei16.vv v0, v2, v4, v0.t# vd overlap vm
++
+ 	vcompress.vm v0, v2, v4		# OK
+ 	vcompress.vm v1, v2, v4		# OK
+ 	vcompress.vm v2, v2, v4		# vd overlap vs2
+diff --git a/gas/testsuite/gas/riscv/vector-insns.d b/gas/testsuite/gas/riscv/vector-insns.d
+index e53d2f3242..8ac80fba1b 100644
+--- a/gas/testsuite/gas/riscv/vector-insns.d
++++ b/gas/testsuite/gas/riscv/vector-insns.d
+@@ -2417,6 +2417,8 @@ Disassembly of section .text:
+ [ 	]+[0-9a-f]+:[ 	]+3085c257[ 	]+vrgather.vx[ 	]+v4,v8,a1,v0.t
+ [ 	]+[0-9a-f]+:[ 	]+30803257[ 	]+vrgather.vi[ 	]+v4,v8,0,v0.t
+ [ 	]+[0-9a-f]+:[ 	]+308fb257[ 	]+vrgather.vi[ 	]+v4,v8,31,v0.t
++[ 	]+[0-9a-f]+:[ 	]+3a860257[ 	]+vrgatherei16.vv[ 	]+v4,v8,v12
++[ 	]+[0-9a-f]+:[ 	]+38860257[ 	]+vrgatherei16.vv[ 	]+v4,v8,v12,v0.t
+ [ 	]+[0-9a-f]+:[ 	]+5e862257[ 	]+vcompress.vm[ 	]+v4,v8,v12
+ [ 	]+[0-9a-f]+:[ 	]+9e2030d7[ 	]+vmv1r.v[ 	]+v1,v2
+ [ 	]+[0-9a-f]+:[ 	]+9e40b157[ 	]+vmv2r.v[ 	]+v2,v4
+diff --git a/gas/testsuite/gas/riscv/vector-insns.s b/gas/testsuite/gas/riscv/vector-insns.s
+index 5046dd3bda..afec58c03b 100644
+--- a/gas/testsuite/gas/riscv/vector-insns.s
++++ b/gas/testsuite/gas/riscv/vector-insns.s
+@@ -2750,6 +2750,9 @@
+ 	vrgather.vi v4, v8, 0, v0.t
+ 	vrgather.vi v4, v8, 31, v0.t
+ 
++	vrgatherei16.vv v4, v8, v12
++	vrgatherei16.vv v4, v8, v12, v0.t
++
+ 	vcompress.vm v4, v8, v12
+ 
+ 	vmv1r.v v1, v2
+diff --git a/include/opcode/riscv-opc.h b/include/opcode/riscv-opc.h
+index 14527e8515..cd1395a010 100644
+--- a/include/opcode/riscv-opc.h
++++ b/include/opcode/riscv-opc.h
+@@ -1761,7 +1761,7 @@ funct6
+ 001011 vxor
+ 001100 vrgather
+ 001101
+-001110 vslideup
++001110 vslideup, vrgatherei16
+ 001111 vslidedown
+ 010000 vadc
+ 010001 vmadc
+@@ -2701,12 +2701,14 @@ funct6 VM  VS2  VS1/RS1/IMM funct3 VD   opcode
+ #define MATCH_VFSLIDE1DOWNVF 0x3c005057
+ #define MASK_VFSLIDE1DOWNVF  0xfc00707f
+ 
+-#define MATCH_VRGATHERVV   0x30000057
+-#define MASK_VRGATHERVV    0xfc00707f
+-#define MATCH_VRGATHERVX   0x30004057
+-#define MASK_VRGATHERVX    0xfc00707f
+-#define MATCH_VRGATHERVI   0x30003057
+-#define MASK_VRGATHERVI    0xfc00707f
++#define MATCH_VRGATHERVV      0x30000057
++#define MASK_VRGATHERVV       0xfc00707f
++#define MATCH_VRGATHERVX      0x30004057
++#define MASK_VRGATHERVX       0xfc00707f
++#define MATCH_VRGATHERVI      0x30003057
++#define MASK_VRGATHERVI       0xfc00707f
++#define MATCH_VRGATHEREI16VV  0x38000057
++#define MASK_VRGATHEREI16VV   0xfc00707f
+ 
+ #define MATCH_VCOMPRESSVM   0x5e002057
+ #define MASK_VCOMPRESSVM    0xfe00707f
+diff --git a/opcodes/riscv-opc.c b/opcodes/riscv-opc.c
+index 208d3ce31b..bc8c5b5d32 100644
+--- a/opcodes/riscv-opc.c
++++ b/opcodes/riscv-opc.c
+@@ -2027,9 +2027,10 @@ const struct riscv_opcode riscv_opcodes[] =
+ {"vfslide1up.vf",   0, INSN_CLASS_V_AND_F, "Vd,Vt,SVm", MATCH_VFSLIDE1UPVF, MASK_VFSLIDE1UPVF, match_vd_neq_vs2, 0},
+ {"vfslide1down.vf", 0, INSN_CLASS_V_AND_F, "Vd,Vt,SVm", MATCH_VFSLIDE1DOWNVF, MASK_VFSLIDE1DOWNVF, match_opcode, 0},
+ 
+-{"vrgather.vv",0, INSN_CLASS_V, "Vd,Vt,VsVm", MATCH_VRGATHERVV, MASK_VRGATHERVV, match_vd_neq_vs1_neq_vs2_neq_vm, 0},
+-{"vrgather.vx",0, INSN_CLASS_V, "Vd,Vt,sVm", MATCH_VRGATHERVX, MASK_VRGATHERVX, match_vd_neq_vs2_neq_vm, 0},
+-{"vrgather.vi",0, INSN_CLASS_V, "Vd,Vt,VjVm", MATCH_VRGATHERVI, MASK_VRGATHERVI, match_vd_neq_vs2_neq_vm, 0},
++{"vrgather.vv",    0, INSN_CLASS_V, "Vd,Vt,VsVm", MATCH_VRGATHERVV, MASK_VRGATHERVV, match_vd_neq_vs1_neq_vs2_neq_vm, 0},
++{"vrgather.vx",    0, INSN_CLASS_V, "Vd,Vt,sVm", MATCH_VRGATHERVX, MASK_VRGATHERVX, match_vd_neq_vs2_neq_vm, 0},
++{"vrgather.vi",    0, INSN_CLASS_V, "Vd,Vt,VjVm", MATCH_VRGATHERVI, MASK_VRGATHERVI, match_vd_neq_vs2_neq_vm, 0},
++{"vrgatherei16.vv",0, INSN_CLASS_V, "Vd,Vt,VsVm", MATCH_VRGATHEREI16VV, MASK_VRGATHEREI16VV, match_vd_neq_vs1_neq_vs2_neq_vm, 0},
+ 
+ {"vcompress.vm",0, INSN_CLASS_V, "Vd,Vt,Vs", MATCH_VCOMPRESSVM, MASK_VCOMPRESSVM, match_vd_neq_vs1_neq_vs2_neq_vm, 0},
+ 
+-- 
+2.33.0
+

+ 157 - 0
recipes-devtools/gdb/files/0021-Make-vlmul-bits-contiguous-in-vtype.patch

@@ -0,0 +1,157 @@
+From 3013bd5c37a680dfafd903b0bb06c5c8ad31ce7f Mon Sep 17 00:00:00 2001
+From: Nelson Chu <nelson.chu@sifive.com>
+Date: Wed, 22 Jul 2020 10:38:15 +0800
+Subject: [PATCH 21/48] Make vlmul bits contiguous in vtype.
+
+---
+ gas/config/tc-riscv.c                  |  6 +++---
+ gas/testsuite/gas/riscv/insn.d         |  4 ++--
+ gas/testsuite/gas/riscv/vector-insns.d | 30 +++++++++++++-------------
+ include/opcode/riscv.h                 | 21 ++++++------------
+ opcodes/riscv-dis.c                    |  2 +-
+ 5 files changed, 27 insertions(+), 36 deletions(-)
+
+diff --git a/gas/config/tc-riscv.c b/gas/config/tc-riscv.c
+index 222214d7e4..67353ab725 100644
+--- a/gas/config/tc-riscv.c
++++ b/gas/config/tc-riscv.c
+@@ -1880,11 +1880,11 @@ my_getVsetvliExpression (expressionS *ep, char *str)
+   if (vsew_found || vlmul_found || vediv_found || vta_found || vma_found)
+     {
+       ep->X_op = O_constant;
+-      ep->X_add_number = (vediv_value << OP_SH_VEDIV)
++      ep->X_add_number = (vlmul_value << OP_SH_VLMUL)
+ 			 | (vsew_value << OP_SH_VSEW)
+ 			 | (vta_value << OP_SH_VTA)
+-			 | (vma_value << OP_SH_VMA) ;
+-      INSERT_VLMUL (ep->X_add_number, vlmul_value);
++			 | (vma_value << OP_SH_VMA)
++			 | (vediv_value << OP_SH_VEDIV);
+       expr_end = str;
+     }
+   else
+diff --git a/gas/testsuite/gas/riscv/insn.d b/gas/testsuite/gas/riscv/insn.d
+index 9d417b0794..e55f21c179 100644
+--- a/gas/testsuite/gas/riscv/insn.d
++++ b/gas/testsuite/gas/riscv/insn.d
+@@ -122,8 +122,8 @@ Disassembly of section .text:
+ [^:]+:[ 	]+00d655d7[ 	]+vfadd.vf[ 	]+v11,v13,fa2,v0.t
+ [^:]+:[ 	]+38d665d7[ 	]+vslide1up.vx[ 	]+v11,v13,a2,v0.t
+ [^:]+:[ 	]+3cd665d7[ 	]+vslide1down.vx[ 	]+v11,v13,a2,v0.t
+-[^:]+:[ 	]+00d675d7[ 	]+vsetvli[ 	]+a1,a2,e64,m2,tu,mu,d1
+-[^:]+:[ 	]+00d675d7[ 	]+vsetvli[ 	]+a1,a2,e64,m2,tu,mu,d1
++[^:]+:[ 	]+00d675d7[ 	]+vsetvli[ 	]+a1,a2,e16,mf8,tu,mu,d1
++[^:]+:[ 	]+00d675d7[ 	]+vsetvli[ 	]+a1,a2,e16,mf8,tu,mu,d1
+ [^:]+:[ 	]+00d035d7[ 	]+vadd.vi[ 	]+v11,v13,0,v0.t
+ [^:]+:[ 	]+00d0b5d7[ 	]+vadd.vi[ 	]+v11,v13,1,v0.t
+ [^:]+:[ 	]+00d7b5d7[ 	]+vadd.vi[ 	]+v11,v13,15,v0.t
+diff --git a/gas/testsuite/gas/riscv/vector-insns.d b/gas/testsuite/gas/riscv/vector-insns.d
+index 8ac80fba1b..24a559cee5 100644
+--- a/gas/testsuite/gas/riscv/vector-insns.d
++++ b/gas/testsuite/gas/riscv/vector-insns.d
+@@ -10,22 +10,22 @@ Disassembly of section .text:
+ [ 	]+[0-9a-f]+:[ 	]+80c5f557[ 	]+vsetvl[ 	]+a0,a1,a2
+ [ 	]+[0-9a-f]+:[ 	]+0005f557[ 	]+vsetvli[ 	]+a0,a1,e8,m1,tu,mu,d1
+ [ 	]+[0-9a-f]+:[ 	]+7ff5f557[ 	]+vsetvli[ 	]+a0,a1,2047
+-[ 	]+[0-9a-f]+:[ 	]+2055f557[ 	]+vsetvli[ 	]+a0,a1,e16,m2,tu,mu,d4
+-[ 	]+[0-9a-f]+:[ 	]+3175f557[ 	]+vsetvli[ 	]+a0,a1,e256,m8,tu,mu,d8
+-[ 	]+[0-9a-f]+:[ 	]+31b5f557[ 	]+vsetvli[ 	]+a0,a1,e512,m8,tu,mu,d8
+-[ 	]+[0-9a-f]+:[ 	]+31f5f557[ 	]+vsetvli[ 	]+a0,a1,e1024,m8,tu,mu,d8
+-[ 	]+[0-9a-f]+:[ 	]+31c5f557[ 	]+vsetvli[ 	]+a0,a1,e1024,m1,tu,mu,d8
++[ 	]+[0-9a-f]+:[ 	]+2095f557[ 	]+vsetvli[ 	]+a0,a1,e16,m2,tu,mu,d4
++[ 	]+[0-9a-f]+:[ 	]+32b5f557[ 	]+vsetvli[ 	]+a0,a1,e256,m8,tu,mu,d8
++[ 	]+[0-9a-f]+:[ 	]+3335f557[ 	]+vsetvli[ 	]+a0,a1,e512,m8,tu,mu,d8
++[ 	]+[0-9a-f]+:[ 	]+33b5f557[ 	]+vsetvli[ 	]+a0,a1,e1024,m8,tu,mu,d8
++[ 	]+[0-9a-f]+:[ 	]+3385f557[ 	]+vsetvli[ 	]+a0,a1,e1024,m1,tu,mu,d8
+ [ 	]+[0-9a-f]+:[ 	]+33f5f557[ 	]+vsetvli[ 	]+a0,a1,e1024,mf2,tu,mu,d8
+-[ 	]+[0-9a-f]+:[ 	]+13a5f557[ 	]+vsetvli[ 	]+a0,a1,e512,mf4,tu,mu,d2
+-[ 	]+[0-9a-f]+:[ 	]+2355f557[ 	]+vsetvli[ 	]+a0,a1,e256,mf8,tu,mu,d4
+-[ 	]+[0-9a-f]+:[ 	]+2555f557[ 	]+vsetvli[ 	]+a0,a1,e256,m2,ta,mu,d4
+-[ 	]+[0-9a-f]+:[ 	]+2955f557[ 	]+vsetvli[ 	]+a0,a1,e256,m2,tu,ma,d4
+-[ 	]+[0-9a-f]+:[ 	]+2155f557[ 	]+vsetvli[ 	]+a0,a1,e256,m2,tu,mu,d4
+-[ 	]+[0-9a-f]+:[ 	]+2155f557[ 	]+vsetvli[ 	]+a0,a1,e256,m2,tu,mu,d4
+-[ 	]+[0-9a-f]+:[ 	]+2d55f557[ 	]+vsetvli[ 	]+a0,a1,e256,m2,ta,ma,d4
+-[ 	]+[0-9a-f]+:[ 	]+2955f557[ 	]+vsetvli[ 	]+a0,a1,e256,m2,tu,ma,d4
+-[ 	]+[0-9a-f]+:[ 	]+2555f557[ 	]+vsetvli[ 	]+a0,a1,e256,m2,ta,mu,d4
+-[ 	]+[0-9a-f]+:[ 	]+2155f557[ 	]+vsetvli[ 	]+a0,a1,e256,m2,tu,mu,d4
++[ 	]+[0-9a-f]+:[ 	]+1365f557[ 	]+vsetvli[ 	]+a0,a1,e512,mf4,tu,mu,d2
++[ 	]+[0-9a-f]+:[ 	]+22d5f557[ 	]+vsetvli[ 	]+a0,a1,e256,mf8,tu,mu,d4
++[ 	]+[0-9a-f]+:[ 	]+2695f557[ 	]+vsetvli[ 	]+a0,a1,e256,m2,ta,mu,d4
++[ 	]+[0-9a-f]+:[ 	]+2a95f557[ 	]+vsetvli[ 	]+a0,a1,e256,m2,tu,ma,d4
++[ 	]+[0-9a-f]+:[ 	]+2295f557[ 	]+vsetvli[ 	]+a0,a1,e256,m2,tu,mu,d4
++[ 	]+[0-9a-f]+:[ 	]+2295f557[ 	]+vsetvli[ 	]+a0,a1,e256,m2,tu,mu,d4
++[ 	]+[0-9a-f]+:[ 	]+2e95f557[ 	]+vsetvli[ 	]+a0,a1,e256,m2,ta,ma,d4
++[ 	]+[0-9a-f]+:[ 	]+2a95f557[ 	]+vsetvli[ 	]+a0,a1,e256,m2,tu,ma,d4
++[ 	]+[0-9a-f]+:[ 	]+2695f557[ 	]+vsetvli[ 	]+a0,a1,e256,m2,ta,mu,d4
++[ 	]+[0-9a-f]+:[ 	]+2295f557[ 	]+vsetvli[ 	]+a0,a1,e256,m2,tu,mu,d4
+ [ 	]+[0-9a-f]+:[ 	]+02050207[ 	]+vle8.v[ 	]+v4,\(a0\)
+ [ 	]+[0-9a-f]+:[ 	]+02050207[ 	]+vle8.v[ 	]+v4,\(a0\)
+ [ 	]+[0-9a-f]+:[ 	]+00050207[ 	]+vle8.v[ 	]+v4,\(a0\),v0.t
+diff --git a/include/opcode/riscv.h b/include/opcode/riscv.h
+index 62049bdd23..b1d3c068db 100644
+--- a/include/opcode/riscv.h
++++ b/include/opcode/riscv.h
+@@ -310,18 +310,18 @@ static const char * const riscv_vma[2] =
+ #define OP_MASK_VFUNCT6		0x3f
+ #define OP_SH_VFUNCT6		26
+ 
+-#define OP_MASK_VLMUL		0x23
++#define OP_MASK_VLMUL		0x7
+ #define OP_SH_VLMUL		0
+ #define OP_MASK_VSEW		0x7
+-#define OP_SH_VSEW		2
+-#define OP_MASK_VEDIV		0x3
+-#define OP_SH_VEDIV		8
+-#define OP_MASK_VTYPE_RES	0x1
+-#define OP_SH_VTYPE_RES		10
++#define OP_SH_VSEW		3
+ #define OP_MASK_VTA		0x1
+ #define OP_SH_VTA		6
+ #define OP_MASK_VMA		0x1
+ #define OP_SH_VMA		7
++#define OP_MASK_VEDIV		0x3
++#define OP_SH_VEDIV		8
++#define OP_MASK_VTYPE_RES	0x1
++#define OP_SH_VTYPE_RES 	10
+ 
+ #define OP_MASK_VWD		0x1
+ #define OP_SH_VWD		26
+@@ -354,10 +354,6 @@ static const char * const riscv_vma[2] =
+   (STRUCT) = (((STRUCT) & ~((insn_t)(MASK) << (SHIFT))) \
+ 	      | ((insn_t)((VALUE) & (MASK)) << (SHIFT)))
+ 
+-#define INSERT_VLMUL(STRUCT, VALUE) \
+-  INSERT_BITS (STRUCT, (VALUE & 0x3), (OP_MASK_VLMUL & 0x3), 0), \
+-  INSERT_BITS (STRUCT, (((VALUE & 0x4) >> 2) <<5), (OP_MASK_VLMUL & 0x20), 0)
+-
+ /* Extract bits MASK << SHIFT from STRUCT and shift them right
+    SHIFT places.  */
+ #define EXTRACT_BITS(STRUCT, MASK, SHIFT) \
+@@ -367,11 +363,6 @@ static const char * const riscv_vma[2] =
+ #define EXTRACT_OPERAND(FIELD, INSN) \
+   EXTRACT_BITS ((INSN), OP_MASK_##FIELD, OP_SH_##FIELD)
+ 
+-/* Extract the vlmul value from vsetvli instrucion.  */
+-#define EXTRACT_VLMUL(INSN) \
+-  (((EXTRACT_OPERAND (VLMUL, INSN) >> 5) << 2) \
+-   | (EXTRACT_OPERAND (VLMUL, INSN) & 0x3))
+-
+ /* The maximal number of subset can be required. */
+ #define MAX_SUBSET_NUM 4
+ 
+diff --git a/opcodes/riscv-dis.c b/opcodes/riscv-dis.c
+index 25e0a93e88..875b69a1da 100644
+--- a/opcodes/riscv-dis.c
++++ b/opcodes/riscv-dis.c
+@@ -439,7 +439,7 @@ print_insn_args (const char *d, insn_t l, bfd_vma pc, disassemble_info *info)
+ 	    case 'c':
+ 	      {
+ 		int imm = EXTRACT_RVV_VC_IMM (l);
+-		unsigned int imm_vlmul = EXTRACT_VLMUL (imm);
++		unsigned int imm_vlmul = EXTRACT_OPERAND (VLMUL, imm);
+ 		unsigned int imm_vsew = EXTRACT_OPERAND (VSEW, imm);
+ 		unsigned int imm_vediv = EXTRACT_OPERAND (VEDIV, imm);
+ 		unsigned int imm_vta = EXTRACT_OPERAND (VTA, imm);
+-- 
+2.33.0
+

+ 70 - 0
recipes-devtools/gdb/files/0022-RISC-V-Clarify-the-supported-versions-for-the-unrati.patch

@@ -0,0 +1,70 @@
+From 91df5cd432661a07b23f9a35d6c0741f0a2f7c96 Mon Sep 17 00:00:00 2001
+From: Nelson Chu <nelson.chu@sifive.com>
+Date: Thu, 9 Jul 2020 10:56:09 +0800
+Subject: [PATCH 22/48] RISC-V: Clarify the supported versions for the
+ unratified extensions.
+
+Remove the V-ext v0.7 in the riscv_ext_version_table, and regard V-ext
+as a non-ISA spec extension temporarily.  Since we only support the v1.0
+for now, and not yet upstreamed.  Also, we define other unratified
+extensions to the non-ISA spec extension, too.
+---
+ gas/config/tc-riscv.c                             | 3 ++-
+ gas/testsuite/gas/riscv/attribute-15-unratified.d | 6 ++++++
+ opcodes/riscv-opc.c                               | 7 +++++++
+ 3 files changed, 15 insertions(+), 1 deletion(-)
+ create mode 100644 gas/testsuite/gas/riscv/attribute-15-unratified.d
+
+diff --git a/gas/config/tc-riscv.c b/gas/config/tc-riscv.c
+index 67353ab725..2dc55ca5aa 100644
+--- a/gas/config/tc-riscv.c
++++ b/gas/config/tc-riscv.c
+@@ -298,7 +298,8 @@ riscv_get_default_ext_version (const char *name,
+ 	 && ext->name
+ 	 && strcmp (ext->name, name) == 0)
+     {
+-      if (ext->isa_spec_class == default_isa_spec)
++      if (ext->isa_spec_class == ISA_SPEC_CLASS_NONE
++	  || ext->isa_spec_class == default_isa_spec)
+ 	{
+ 	  *major_version = ext->major_version;
+ 	  *minor_version = ext->minor_version;
+diff --git a/gas/testsuite/gas/riscv/attribute-15-unratified.d b/gas/testsuite/gas/riscv/attribute-15-unratified.d
+new file mode 100644
+index 0000000000..09d64edbe6
+--- /dev/null
++++ b/gas/testsuite/gas/riscv/attribute-15-unratified.d
+@@ -0,0 +1,6 @@
++#as: -march-attr -march=rv32ifv_zvamo_zvediv_zvlsseg_zvqmac
++#readelf: -A
++#source: empty.s
++Attribute Section: riscv
++File Attributes
++  Tag_RISCV_arch: ".*_v1p0_zvamo1p0_zvediv1p0_zvlsseg1p0_zvqmac1p0"
+diff --git a/opcodes/riscv-opc.c b/opcodes/riscv-opc.c
+index bc8c5b5d32..c7ecb7c965 100644
+--- a/opcodes/riscv-opc.c
++++ b/opcodes/riscv-opc.c
+@@ -2205,12 +2205,19 @@ const struct riscv_ext_version riscv_ext_version_table[] =
+ {"c", ISA_SPEC_CLASS_20190608, 2, 0},
+ {"c", ISA_SPEC_CLASS_2P2,      2, 0},
+ 
++{"v", ISA_SPEC_CLASS_NONE,     1, 0},
++
+ {"zicsr", ISA_SPEC_CLASS_20191213, 2, 0},
+ {"zicsr", ISA_SPEC_CLASS_20190608, 2, 0},
+ 
+ {"zifencei", ISA_SPEC_CLASS_20191213, 2, 0},
+ {"zifencei", ISA_SPEC_CLASS_20190608, 2, 0},
+ 
++{"zvamo",   ISA_SPEC_CLASS_NONE, 1, 0},
++{"zvediv",  ISA_SPEC_CLASS_NONE, 1, 0},
++{"zvlsseg", ISA_SPEC_CLASS_NONE, 1, 0},
++{"zvqmac",  ISA_SPEC_CLASS_NONE, 1, 0},
++
+ /* Terminate the list.  */
+ {NULL, 0, 0, 0}
+ };
+-- 
+2.33.0
+

+ 41 - 0
recipes-devtools/gdb/files/0023-RISC-V-Convert-CSR-dwarf-numbers-to-gdb-register-num.patch

@@ -0,0 +1,41 @@
+From 7f2e74524afaeef6ad75cc0205406ef479173bd8 Mon Sep 17 00:00:00 2001
+From: Hsiangkai Wang <kai.wang@sifive.com>
+Date: Fri, 21 Aug 2020 16:10:16 +0800
+Subject: [PATCH 23/48] RISC-V: Convert CSR dwarf numbers to gdb register
+ numbers.
+
+---
+ gdb/riscv-tdep.c | 3 +++
+ gdb/riscv-tdep.h | 2 ++
+ 2 files changed, 5 insertions(+)
+
+diff --git a/gdb/riscv-tdep.c b/gdb/riscv-tdep.c
+index b86ba63054..7f0c14d0ba 100644
+--- a/gdb/riscv-tdep.c
++++ b/gdb/riscv-tdep.c
+@@ -3150,6 +3150,9 @@ riscv_dwarf_reg_to_regnum (struct gdbarch *gdbarch, int reg)
+   else if (reg < RISCV_DWARF_REGNUM_F31)
+     return RISCV_FIRST_FP_REGNUM + (reg - RISCV_DWARF_REGNUM_F0);
+ 
++  else if (RISCV_DWARF_REGNUM_CSR_BEGIN <= reg && reg <= RISCV_DWARF_REGNUM_CSR_END)
++    return RISCV_FIRST_CSR_REGNUM + (reg - RISCV_DWARF_REGNUM_CSR_BEGIN);
++
+   return -1;
+ }
+ 
+diff --git a/gdb/riscv-tdep.h b/gdb/riscv-tdep.h
+index 0ff555b063..fc5adedad3 100644
+--- a/gdb/riscv-tdep.h
++++ b/gdb/riscv-tdep.h
+@@ -63,6 +63,8 @@ enum
+   RISCV_DWARF_REGNUM_X31 = 31,
+   RISCV_DWARF_REGNUM_F0 = 32,
+   RISCV_DWARF_REGNUM_F31 = 63,
++  RISCV_DWARF_REGNUM_CSR_BEGIN = 4096,
++  RISCV_DWARF_REGNUM_CSR_END = 8191,
+ };
+ 
+ /* RISC-V specific per-architecture information.  */
+-- 
+2.33.0
+

+ 7031 - 0
recipes-devtools/gdb/files/0024-RISC-V-Update-the-vector-mask-constraints.patch

@@ -0,0 +1,7031 @@
+From 74aac3ffbc31ab5640f1cf2ed0bacaeef35b4e68 Mon Sep 17 00:00:00 2001
+From: Nelson Chu <nelson.chu@sifive.com>
+Date: Thu, 13 Aug 2020 15:32:14 +0800
+Subject: [PATCH 24/48] RISC-V: Update the vector mask constraints.
+
+For now, the destination vector register group for most of masked vector
+instruction can not overlap the source mask register.  Unless,
+
+1. Comparison instruction.
+2. Reduction instruction.
+
+V0 is a special case.  It is a carry-in register for v[m]adc and v[m]sbc,
+and is used to choose vs1/rs1/frs1/imm or vs2 for v[f]merge.  For vadc and
+vsbc, vd can not overlap the carry-in V0.  I use the match_vd_neq_vm to
+check the constraints since V0 and VM have the same encoding.
+
+I regard vdot[u].vv as a reduction instruction, too.  Therefore, I don't
+check the VM constraints for it.
+
+Besides, I also rewrite the vector failed testcases since their names are
+hard to understand and maintain.
+
+	opcodes/
+	* riscv-opc.c (match_narrow_vd_neq_vs2): Add the vm checking.
+	Renamed to match_narrow_vd_neq_vs2_neq_vm.
+	(match_vd_neq_vs2): Removed.  Replace it with match_vd_neq_vs2_vm.
+	(riscv_opcodes): Updated.
+
+	gas/
+	* config/tc-riscv.c (riscv_ip): Update the comment for V0.
+
+	* testsuite/gas/riscv/vector-insns-fail-zvamo.d: New failed testcase
+	for vector AMO operations.
+	* testsuite/gas/riscv/vector-insns-fail-zvamo.l: Likewise.
+	* testsuite/gas/riscv/vector-insns-fail-zvamo.s: Likewise.
+	* testsuite/gas/riscv/vector-insns-fail-zvqmac.d: New failed testcase
+	for vector quad-widening instructions.
+	* testsuite/gas/riscv/vector-insns-fail-zvqmac.l: Likewise.
+	* testsuite/gas/riscv/vector-insns-fail-zvqmac.s: Likewise.
+	* testsuite/gas/riscv/vector-insns-fail-load-store.d: New failed testcase
+	for vector load and store instructions.
+	* testsuite/gas/riscv/vector-insns-fail-load-store.l: Likewise.
+	* testsuite/gas/riscv/vector-insns-fail-load-store.s: Likewise.
+	* testsuite/gas/riscv/vector-insns-fail-arith-int.d: New failed testcase
+	for vector integer arithmetic instructions.
+	* testsuite/gas/riscv/vector-insns-fail-arith-int.l: Likewise.
+	* testsuite/gas/riscv/vector-insns-fail-arith-int.s: Likewise.
+	* testsuite/gas/riscv/vector-insns-fail-arith-fixp.d: New failed testcase
+	for vector fixed-point arithmetic instructions.
+	* testsuite/gas/riscv/vector-insns-fail-arith-fixp.l: Likewise.
+	* testsuite/gas/riscv/vector-insns-fail-arith-fixp.s: Likewise.
+	* testsuite/gas/riscv/vector-insns-fail-arith-floatp.d: New failed testcase
+	for vector floating-point arithmetic instructions.
+	* testsuite/gas/riscv/vector-insns-fail-arith-floatp.l: Likewise.
+	* testsuite/gas/riscv/vector-insns-fail-arith-floatp.s: Likewise.
+	* testsuite/gas/riscv/vector-insns-fail-arith-widen.d: New failed testcase
+	for vector widening instructions.
+	* testsuite/gas/riscv/vector-insns-fail-arith-widen.l: Likewise.
+	* testsuite/gas/riscv/vector-insns-fail-arith-widen.s: Likewise.
+	* testsuite/gas/riscv/vector-insns-fail-arith-narrow.d: New failed testcase
+	for vector narrowing instructions.
+	* testsuite/gas/riscv/vector-insns-fail-arith-narrow.l: Likewise.
+	* testsuite/gas/riscv/vector-insns-fail-arith-narrow.s: Likewise.
+	* testsuite/gas/riscv/vector-insns-fail-mask.d: New failed testcase
+	for vector mask instructions.
+	* testsuite/gas/riscv/vector-insns-fail-mask.l: Likewise.
+	* testsuite/gas/riscv/vector-insns-fail-mask.s: Likewise.
+	* testsuite/gas/riscv/vector-insns-fail-permutation.d: New failed testcase
+	for vector permutation instructions.
+	* testsuite/gas/riscv/vector-insns-fail-permutation.l: Likewise.
+	* testsuite/gas/riscv/vector-insns-fail-permutation.s: Likewise.
+
+	* testsuite/gas/riscv/vector-insns-fail-01.d: Removed.
+	* testsuite/gas/riscv/vector-insns-fail-01.l: Likewise.
+	* testsuite/gas/riscv/vector-insns-fail-01.s: Likewise.
+	* testsuite/gas/riscv/vector-insns-fail-02.d: Likewise.
+	* testsuite/gas/riscv/vector-insns-fail-02.l: Likewise.
+	* testsuite/gas/riscv/vector-insns-fail-02.s: Likewise.
+	* testsuite/gas/riscv/vector-insns-fail-03.d: Likewise.
+	* testsuite/gas/riscv/vector-insns-fail-03.l: Likewise.
+	* testsuite/gas/riscv/vector-insns-fail-03.s: Likewise.
+	* testsuite/gas/riscv/vector-insns-fail-04.d: Likewise.
+	* testsuite/gas/riscv/vector-insns-fail-04.l: Likewise.
+	* testsuite/gas/riscv/vector-insns-fail-04.s: Likewise.
+	* testsuite/gas/riscv/vector-insns-fail-05.d: Likewise.
+	* testsuite/gas/riscv/vector-insns-fail-05.l: Likewise.
+	* testsuite/gas/riscv/vector-insns-fail-05.s: Likewise.
+	* testsuite/gas/riscv/vector-insns-fail-06.d: Likewise.
+	* testsuite/gas/riscv/vector-insns-fail-06.l: Likewise.
+	* testsuite/gas/riscv/vector-insns-fail-06.s: Likewise.
+---
+ gas/config/tc-riscv.c                         |    6 +-
+ .../gas/riscv/vector-insns-fail-01.d          |    3 -
+ .../gas/riscv/vector-insns-fail-01.l          |  393 -------
+ .../gas/riscv/vector-insns-fail-01.s          | 1037 -----------------
+ .../gas/riscv/vector-insns-fail-02.d          |    3 -
+ .../gas/riscv/vector-insns-fail-02.l          |  121 --
+ .../gas/riscv/vector-insns-fail-02.s          |  162 ---
+ .../gas/riscv/vector-insns-fail-03.d          |    3 -
+ .../gas/riscv/vector-insns-fail-03.l          |  125 --
+ .../gas/riscv/vector-insns-fail-03.s          |  187 ---
+ .../gas/riscv/vector-insns-fail-04.d          |    3 -
+ .../gas/riscv/vector-insns-fail-04.l          |   49 -
+ .../gas/riscv/vector-insns-fail-04.s          |   85 --
+ .../gas/riscv/vector-insns-fail-05.d          |    3 -
+ .../gas/riscv/vector-insns-fail-05.s          |  139 ---
+ .../gas/riscv/vector-insns-fail-06.d          |    3 -
+ .../gas/riscv/vector-insns-fail-06.l          |   25 -
+ .../gas/riscv/vector-insns-fail-06.s          |   73 --
+ .../gas/riscv/vector-insns-fail-arith-fixp.d  |    3 +
+ .../gas/riscv/vector-insns-fail-arith-fixp.l  |   27 +
+ .../gas/riscv/vector-insns-fail-arith-fixp.s  |   81 ++
+ .../riscv/vector-insns-fail-arith-floatp.d    |    3 +
+ .../riscv/vector-insns-fail-arith-floatp.l    |   47 +
+ .../riscv/vector-insns-fail-arith-floatp.s    |  152 +++
+ .../gas/riscv/vector-insns-fail-arith-int.d   |    3 +
+ .../gas/riscv/vector-insns-fail-arith-int.l   |   70 ++
+ .../gas/riscv/vector-insns-fail-arith-int.s   |  210 ++++
+ .../riscv/vector-insns-fail-arith-narrow.d    |    3 +
+ ...-05.l => vector-insns-fail-arith-narrow.l} |   45 +-
+ .../riscv/vector-insns-fail-arith-narrow.s    |  100 ++
+ .../gas/riscv/vector-insns-fail-arith-widen.d |    3 +
+ .../gas/riscv/vector-insns-fail-arith-widen.l |  253 ++++
+ .../gas/riscv/vector-insns-fail-arith-widen.s |  297 +++++
+ .../gas/riscv/vector-insns-fail-load-store.d  |    3 +
+ .../gas/riscv/vector-insns-fail-load-store.l  |  557 +++++++++
+ .../gas/riscv/vector-insns-fail-load-store.s  |  610 ++++++++++
+ .../gas/riscv/vector-insns-fail-mask.d        |    3 +
+ .../gas/riscv/vector-insns-fail-mask.l        |    7 +
+ .../gas/riscv/vector-insns-fail-mask.s        |   20 +
+ .../gas/riscv/vector-insns-fail-permutation.d |    3 +
+ .../gas/riscv/vector-insns-fail-permutation.l |   31 +
+ .../gas/riscv/vector-insns-fail-permutation.s |   56 +
+ .../gas/riscv/vector-insns-fail-zvamo.d       |    3 +
+ .../gas/riscv/vector-insns-fail-zvamo.l       |  109 ++
+ .../gas/riscv/vector-insns-fail-zvamo.s       |  217 ++++
+ .../gas/riscv/vector-insns-fail-zvqmac.d      |    3 +
+ .../gas/riscv/vector-insns-fail-zvqmac.l      |   35 +
+ .../gas/riscv/vector-insns-fail-zvqmac.s      |   39 +
+ opcodes/riscv-opc.c                           |  817 +++++++------
+ 49 files changed, 3391 insertions(+), 2839 deletions(-)
+ delete mode 100644 gas/testsuite/gas/riscv/vector-insns-fail-01.d
+ delete mode 100644 gas/testsuite/gas/riscv/vector-insns-fail-01.l
+ delete mode 100644 gas/testsuite/gas/riscv/vector-insns-fail-01.s
+ delete mode 100644 gas/testsuite/gas/riscv/vector-insns-fail-02.d
+ delete mode 100644 gas/testsuite/gas/riscv/vector-insns-fail-02.l
+ delete mode 100644 gas/testsuite/gas/riscv/vector-insns-fail-02.s
+ delete mode 100644 gas/testsuite/gas/riscv/vector-insns-fail-03.d
+ delete mode 100644 gas/testsuite/gas/riscv/vector-insns-fail-03.l
+ delete mode 100644 gas/testsuite/gas/riscv/vector-insns-fail-03.s
+ delete mode 100644 gas/testsuite/gas/riscv/vector-insns-fail-04.d
+ delete mode 100644 gas/testsuite/gas/riscv/vector-insns-fail-04.l
+ delete mode 100644 gas/testsuite/gas/riscv/vector-insns-fail-04.s
+ delete mode 100644 gas/testsuite/gas/riscv/vector-insns-fail-05.d
+ delete mode 100644 gas/testsuite/gas/riscv/vector-insns-fail-05.s
+ delete mode 100644 gas/testsuite/gas/riscv/vector-insns-fail-06.d
+ delete mode 100644 gas/testsuite/gas/riscv/vector-insns-fail-06.l
+ delete mode 100644 gas/testsuite/gas/riscv/vector-insns-fail-06.s
+ create mode 100644 gas/testsuite/gas/riscv/vector-insns-fail-arith-fixp.d
+ create mode 100644 gas/testsuite/gas/riscv/vector-insns-fail-arith-fixp.l
+ create mode 100644 gas/testsuite/gas/riscv/vector-insns-fail-arith-fixp.s
+ create mode 100644 gas/testsuite/gas/riscv/vector-insns-fail-arith-floatp.d
+ create mode 100644 gas/testsuite/gas/riscv/vector-insns-fail-arith-floatp.l
+ create mode 100644 gas/testsuite/gas/riscv/vector-insns-fail-arith-floatp.s
+ create mode 100644 gas/testsuite/gas/riscv/vector-insns-fail-arith-int.d
+ create mode 100644 gas/testsuite/gas/riscv/vector-insns-fail-arith-int.l
+ create mode 100644 gas/testsuite/gas/riscv/vector-insns-fail-arith-int.s
+ create mode 100644 gas/testsuite/gas/riscv/vector-insns-fail-arith-narrow.d
+ rename gas/testsuite/gas/riscv/{vector-insns-fail-05.l => vector-insns-fail-arith-narrow.l} (59%)
+ create mode 100644 gas/testsuite/gas/riscv/vector-insns-fail-arith-narrow.s
+ create mode 100644 gas/testsuite/gas/riscv/vector-insns-fail-arith-widen.d
+ create mode 100644 gas/testsuite/gas/riscv/vector-insns-fail-arith-widen.l
+ create mode 100644 gas/testsuite/gas/riscv/vector-insns-fail-arith-widen.s
+ create mode 100644 gas/testsuite/gas/riscv/vector-insns-fail-load-store.d
+ create mode 100644 gas/testsuite/gas/riscv/vector-insns-fail-load-store.l
+ create mode 100644 gas/testsuite/gas/riscv/vector-insns-fail-load-store.s
+ create mode 100644 gas/testsuite/gas/riscv/vector-insns-fail-mask.d
+ create mode 100644 gas/testsuite/gas/riscv/vector-insns-fail-mask.l
+ create mode 100644 gas/testsuite/gas/riscv/vector-insns-fail-mask.s
+ create mode 100644 gas/testsuite/gas/riscv/vector-insns-fail-permutation.d
+ create mode 100644 gas/testsuite/gas/riscv/vector-insns-fail-permutation.l
+ create mode 100644 gas/testsuite/gas/riscv/vector-insns-fail-permutation.s
+ create mode 100644 gas/testsuite/gas/riscv/vector-insns-fail-zvamo.d
+ create mode 100644 gas/testsuite/gas/riscv/vector-insns-fail-zvamo.l
+ create mode 100644 gas/testsuite/gas/riscv/vector-insns-fail-zvamo.s
+ create mode 100644 gas/testsuite/gas/riscv/vector-insns-fail-zvqmac.d
+ create mode 100644 gas/testsuite/gas/riscv/vector-insns-fail-zvqmac.l
+ create mode 100644 gas/testsuite/gas/riscv/vector-insns-fail-zvqmac.s
+
+diff --git a/gas/config/tc-riscv.c b/gas/config/tc-riscv.c
+index 2dc55ca5aa..e998890b92 100644
+--- a/gas/config/tc-riscv.c
++++ b/gas/config/tc-riscv.c
+@@ -2826,7 +2826,11 @@ riscv_ip (char *str, struct riscv_cl_insn *ip, expressionS *imm_expr,
+ 		  INSERT_OPERAND (VS2, *ip, regno);
+ 		  continue;
+ 
+-		case '0': /* required vector mask register without .t */
++		/* The `V0` is carry-in register for v[m]adc and v[m]sbc,
++		   and is used to choose vs1/rs1/frs1/imm or vs2 for
++		   v[f]merge.  It use the same encoding as the vector mask
++		   register.  */
++		case '0':
+ 		  if (reg_lookup (&s, RCLASS_VECR, &regno) && regno == 0)
+ 		    continue;
+ 		  break;
+diff --git a/gas/testsuite/gas/riscv/vector-insns-fail-01.d b/gas/testsuite/gas/riscv/vector-insns-fail-01.d
+deleted file mode 100644
+index ade7888937..0000000000
+--- a/gas/testsuite/gas/riscv/vector-insns-fail-01.d
++++ /dev/null
+@@ -1,3 +0,0 @@
+-#as: -march=rv32ifv -mcheck-constraints
+-#source: vector-insns-fail-01.s
+-#error_output: vector-insns-fail-01.l
+diff --git a/gas/testsuite/gas/riscv/vector-insns-fail-01.l b/gas/testsuite/gas/riscv/vector-insns-fail-01.l
+deleted file mode 100644
+index 61687938c9..0000000000
+--- a/gas/testsuite/gas/riscv/vector-insns-fail-01.l
++++ /dev/null
+@@ -1,393 +0,0 @@
+-.*: Assembler messages:
+-.*Error: illegal operands `vlseg2e8.v v0,\(a0\),v0.t'
+-.*Error: illegal operands `vlseg2e8ff.v v0,\(a0\),v0.t'
+-.*Error: illegal operands `vlseg3e8.v v0,\(a0\),v0.t'
+-.*Error: illegal operands `vlseg3e8ff.v v0,\(a0\),v0.t'
+-.*Error: illegal operands `vlseg4e8.v v0,\(a0\),v0.t'
+-.*Error: illegal operands `vlseg4e8ff.v v0,\(a0\),v0.t'
+-.*Error: illegal operands `vlseg5e8.v v0,\(a0\),v0.t'
+-.*Error: illegal operands `vlseg5e8ff.v v0,\(a0\),v0.t'
+-.*Error: illegal operands `vlseg6e8.v v0,\(a0\),v0.t'
+-.*Error: illegal operands `vlseg6e8ff.v v0,\(a0\),v0.t'
+-.*Error: illegal operands `vlseg7e8.v v0,\(a0\),v0.t'
+-.*Error: illegal operands `vlseg7e8ff.v v0,\(a0\),v0.t'
+-.*Error: illegal operands `vlseg8e8.v v0,\(a0\),v0.t'
+-.*Error: illegal operands `vlseg8e8ff.v v0,\(a0\),v0.t'
+-.*Error: illegal operands `vlseg2e16.v v0,\(a0\),v0.t'
+-.*Error: illegal operands `vlseg2e16ff.v v0,\(a0\),v0.t'
+-.*Error: illegal operands `vlseg3e16.v v0,\(a0\),v0.t'
+-.*Error: illegal operands `vlseg3e16ff.v v0,\(a0\),v0.t'
+-.*Error: illegal operands `vlseg4e16.v v0,\(a0\),v0.t'
+-.*Error: illegal operands `vlseg4e16ff.v v0,\(a0\),v0.t'
+-.*Error: illegal operands `vlseg5e16.v v0,\(a0\),v0.t'
+-.*Error: illegal operands `vlseg5e16ff.v v0,\(a0\),v0.t'
+-.*Error: illegal operands `vlseg6e16.v v0,\(a0\),v0.t'
+-.*Error: illegal operands `vlseg6e16ff.v v0,\(a0\),v0.t'
+-.*Error: illegal operands `vlseg7e16.v v0,\(a0\),v0.t'
+-.*Error: illegal operands `vlseg7e16ff.v v0,\(a0\),v0.t'
+-.*Error: illegal operands `vlseg8e16.v v0,\(a0\),v0.t'
+-.*Error: illegal operands `vlseg8e16ff.v v0,\(a0\),v0.t'
+-.*Error: illegal operands `vlseg2e32.v v0,\(a0\),v0.t'
+-.*Error: illegal operands `vlseg2e32ff.v v0,\(a0\),v0.t'
+-.*Error: illegal operands `vlseg3e32.v v0,\(a0\),v0.t'
+-.*Error: illegal operands `vlseg3e32ff.v v0,\(a0\),v0.t'
+-.*Error: illegal operands `vlseg4e32.v v0,\(a0\),v0.t'
+-.*Error: illegal operands `vlseg4e32ff.v v0,\(a0\),v0.t'
+-.*Error: illegal operands `vlseg5e32.v v0,\(a0\),v0.t'
+-.*Error: illegal operands `vlseg5e32ff.v v0,\(a0\),v0.t'
+-.*Error: illegal operands `vlseg6e32.v v0,\(a0\),v0.t'
+-.*Error: illegal operands `vlseg6e32ff.v v0,\(a0\),v0.t'
+-.*Error: illegal operands `vlseg7e32.v v0,\(a0\),v0.t'
+-.*Error: illegal operands `vlseg7e32ff.v v0,\(a0\),v0.t'
+-.*Error: illegal operands `vlseg8e32.v v0,\(a0\),v0.t'
+-.*Error: illegal operands `vlseg8e32ff.v v0,\(a0\),v0.t'
+-.*Error: illegal operands `vlseg2e64.v v0,\(a0\),v0.t'
+-.*Error: illegal operands `vlseg2e64ff.v v0,\(a0\),v0.t'
+-.*Error: illegal operands `vlseg3e64.v v0,\(a0\),v0.t'
+-.*Error: illegal operands `vlseg3e64ff.v v0,\(a0\),v0.t'
+-.*Error: illegal operands `vlseg4e64.v v0,\(a0\),v0.t'
+-.*Error: illegal operands `vlseg4e64ff.v v0,\(a0\),v0.t'
+-.*Error: illegal operands `vlseg5e64.v v0,\(a0\),v0.t'
+-.*Error: illegal operands `vlseg5e64ff.v v0,\(a0\),v0.t'
+-.*Error: illegal operands `vlseg6e64.v v0,\(a0\),v0.t'
+-.*Error: illegal operands `vlseg6e64ff.v v0,\(a0\),v0.t'
+-.*Error: illegal operands `vlseg7e64.v v0,\(a0\),v0.t'
+-.*Error: illegal operands `vlseg7e64ff.v v0,\(a0\),v0.t'
+-.*Error: illegal operands `vlseg8e64.v v0,\(a0\),v0.t'
+-.*Error: illegal operands `vlseg8e64ff.v v0,\(a0\),v0.t'
+-.*Error: illegal operands `vlseg2e128.v v0,\(a0\),v0.t'
+-.*Error: illegal operands `vlseg2e128ff.v v0,\(a0\),v0.t'
+-.*Error: illegal operands `vlseg3e128.v v0,\(a0\),v0.t'
+-.*Error: illegal operands `vlseg3e128ff.v v0,\(a0\),v0.t'
+-.*Error: illegal operands `vlseg4e128.v v0,\(a0\),v0.t'
+-.*Error: illegal operands `vlseg4e128ff.v v0,\(a0\),v0.t'
+-.*Error: illegal operands `vlseg5e128.v v0,\(a0\),v0.t'
+-.*Error: illegal operands `vlseg5e128ff.v v0,\(a0\),v0.t'
+-.*Error: illegal operands `vlseg6e128.v v0,\(a0\),v0.t'
+-.*Error: illegal operands `vlseg6e128ff.v v0,\(a0\),v0.t'
+-.*Error: illegal operands `vlseg7e128.v v0,\(a0\),v0.t'
+-.*Error: illegal operands `vlseg7e128ff.v v0,\(a0\),v0.t'
+-.*Error: illegal operands `vlseg8e128.v v0,\(a0\),v0.t'
+-.*Error: illegal operands `vlseg8e128ff.v v0,\(a0\),v0.t'
+-.*Error: illegal operands `vlseg2e256.v v0,\(a0\),v0.t'
+-.*Error: illegal operands `vlseg2e256ff.v v0,\(a0\),v0.t'
+-.*Error: illegal operands `vlseg3e256.v v0,\(a0\),v0.t'
+-.*Error: illegal operands `vlseg3e256ff.v v0,\(a0\),v0.t'
+-.*Error: illegal operands `vlseg4e256.v v0,\(a0\),v0.t'
+-.*Error: illegal operands `vlseg4e256ff.v v0,\(a0\),v0.t'
+-.*Error: illegal operands `vlseg5e256.v v0,\(a0\),v0.t'
+-.*Error: illegal operands `vlseg5e256ff.v v0,\(a0\),v0.t'
+-.*Error: illegal operands `vlseg6e256.v v0,\(a0\),v0.t'
+-.*Error: illegal operands `vlseg6e256ff.v v0,\(a0\),v0.t'
+-.*Error: illegal operands `vlseg7e256.v v0,\(a0\),v0.t'
+-.*Error: illegal operands `vlseg7e256ff.v v0,\(a0\),v0.t'
+-.*Error: illegal operands `vlseg8e256.v v0,\(a0\),v0.t'
+-.*Error: illegal operands `vlseg8e256ff.v v0,\(a0\),v0.t'
+-.*Error: illegal operands `vlseg2e512.v v0,\(a0\),v0.t'
+-.*Error: illegal operands `vlseg2e512ff.v v0,\(a0\),v0.t'
+-.*Error: illegal operands `vlseg3e512.v v0,\(a0\),v0.t'
+-.*Error: illegal operands `vlseg3e512ff.v v0,\(a0\),v0.t'
+-.*Error: illegal operands `vlseg4e512.v v0,\(a0\),v0.t'
+-.*Error: illegal operands `vlseg4e512ff.v v0,\(a0\),v0.t'
+-.*Error: illegal operands `vlseg5e512.v v0,\(a0\),v0.t'
+-.*Error: illegal operands `vlseg5e512ff.v v0,\(a0\),v0.t'
+-.*Error: illegal operands `vlseg6e512.v v0,\(a0\),v0.t'
+-.*Error: illegal operands `vlseg6e512ff.v v0,\(a0\),v0.t'
+-.*Error: illegal operands `vlseg7e512.v v0,\(a0\),v0.t'
+-.*Error: illegal operands `vlseg7e512ff.v v0,\(a0\),v0.t'
+-.*Error: illegal operands `vlseg8e512.v v0,\(a0\),v0.t'
+-.*Error: illegal operands `vlseg8e512ff.v v0,\(a0\),v0.t'
+-.*Error: illegal operands `vlseg2e1024.v v0,\(a0\),v0.t'
+-.*Error: illegal operands `vlseg2e1024ff.v v0,\(a0\),v0.t'
+-.*Error: illegal operands `vlseg3e1024.v v0,\(a0\),v0.t'
+-.*Error: illegal operands `vlseg3e1024ff.v v0,\(a0\),v0.t'
+-.*Error: illegal operands `vlseg4e1024.v v0,\(a0\),v0.t'
+-.*Error: illegal operands `vlseg4e1024ff.v v0,\(a0\),v0.t'
+-.*Error: illegal operands `vlseg5e1024.v v0,\(a0\),v0.t'
+-.*Error: illegal operands `vlseg5e1024ff.v v0,\(a0\),v0.t'
+-.*Error: illegal operands `vlseg6e1024.v v0,\(a0\),v0.t'
+-.*Error: illegal operands `vlseg6e1024ff.v v0,\(a0\),v0.t'
+-.*Error: illegal operands `vlseg7e1024.v v0,\(a0\),v0.t'
+-.*Error: illegal operands `vlseg7e1024ff.v v0,\(a0\),v0.t'
+-.*Error: illegal operands `vlseg8e1024.v v0,\(a0\),v0.t'
+-.*Error: illegal operands `vlseg8e1024ff.v v0,\(a0\),v0.t'
+-.*Error: illegal operands `vlsseg2e8.v v0,\(a0\),a1,v0.t'
+-.*Error: illegal operands `vlsseg3e8.v v0,\(a0\),a1,v0.t'
+-.*Error: illegal operands `vlsseg4e8.v v0,\(a0\),a1,v0.t'
+-.*Error: illegal operands `vlsseg5e8.v v0,\(a0\),a1,v0.t'
+-.*Error: illegal operands `vlsseg6e8.v v0,\(a0\),a1,v0.t'
+-.*Error: illegal operands `vlsseg7e8.v v0,\(a0\),a1,v0.t'
+-.*Error: illegal operands `vlsseg8e8.v v0,\(a0\),a1,v0.t'
+-.*Error: illegal operands `vlsseg2e16.v v0,\(a0\),a1,v0.t'
+-.*Error: illegal operands `vlsseg3e16.v v0,\(a0\),a1,v0.t'
+-.*Error: illegal operands `vlsseg4e16.v v0,\(a0\),a1,v0.t'
+-.*Error: illegal operands `vlsseg5e16.v v0,\(a0\),a1,v0.t'
+-.*Error: illegal operands `vlsseg6e16.v v0,\(a0\),a1,v0.t'
+-.*Error: illegal operands `vlsseg7e16.v v0,\(a0\),a1,v0.t'
+-.*Error: illegal operands `vlsseg8e16.v v0,\(a0\),a1,v0.t'
+-.*Error: illegal operands `vlsseg2e32.v v0,\(a0\),a1,v0.t'
+-.*Error: illegal operands `vlsseg3e32.v v0,\(a0\),a1,v0.t'
+-.*Error: illegal operands `vlsseg4e32.v v0,\(a0\),a1,v0.t'
+-.*Error: illegal operands `vlsseg5e32.v v0,\(a0\),a1,v0.t'
+-.*Error: illegal operands `vlsseg6e32.v v0,\(a0\),a1,v0.t'
+-.*Error: illegal operands `vlsseg7e32.v v0,\(a0\),a1,v0.t'
+-.*Error: illegal operands `vlsseg8e32.v v0,\(a0\),a1,v0.t'
+-.*Error: illegal operands `vlsseg2e64.v v0,\(a0\),a1,v0.t'
+-.*Error: illegal operands `vlsseg3e64.v v0,\(a0\),a1,v0.t'
+-.*Error: illegal operands `vlsseg4e64.v v0,\(a0\),a1,v0.t'
+-.*Error: illegal operands `vlsseg5e64.v v0,\(a0\),a1,v0.t'
+-.*Error: illegal operands `vlsseg6e64.v v0,\(a0\),a1,v0.t'
+-.*Error: illegal operands `vlsseg7e64.v v0,\(a0\),a1,v0.t'
+-.*Error: illegal operands `vlsseg8e64.v v0,\(a0\),a1,v0.t'
+-.*Error: illegal operands `vlsseg2e128.v v0,\(a0\),a1,v0.t'
+-.*Error: illegal operands `vlsseg3e128.v v0,\(a0\),a1,v0.t'
+-.*Error: illegal operands `vlsseg4e128.v v0,\(a0\),a1,v0.t'
+-.*Error: illegal operands `vlsseg5e128.v v0,\(a0\),a1,v0.t'
+-.*Error: illegal operands `vlsseg6e128.v v0,\(a0\),a1,v0.t'
+-.*Error: illegal operands `vlsseg7e128.v v0,\(a0\),a1,v0.t'
+-.*Error: illegal operands `vlsseg8e128.v v0,\(a0\),a1,v0.t'
+-.*Error: illegal operands `vlsseg2e256.v v0,\(a0\),a1,v0.t'
+-.*Error: illegal operands `vlsseg3e256.v v0,\(a0\),a1,v0.t'
+-.*Error: illegal operands `vlsseg4e256.v v0,\(a0\),a1,v0.t'
+-.*Error: illegal operands `vlsseg5e256.v v0,\(a0\),a1,v0.t'
+-.*Error: illegal operands `vlsseg6e256.v v0,\(a0\),a1,v0.t'
+-.*Error: illegal operands `vlsseg7e256.v v0,\(a0\),a1,v0.t'
+-.*Error: illegal operands `vlsseg8e256.v v0,\(a0\),a1,v0.t'
+-.*Error: illegal operands `vlsseg2e512.v v0,\(a0\),a1,v0.t'
+-.*Error: illegal operands `vlsseg3e512.v v0,\(a0\),a1,v0.t'
+-.*Error: illegal operands `vlsseg4e512.v v0,\(a0\),a1,v0.t'
+-.*Error: illegal operands `vlsseg5e512.v v0,\(a0\),a1,v0.t'
+-.*Error: illegal operands `vlsseg6e512.v v0,\(a0\),a1,v0.t'
+-.*Error: illegal operands `vlsseg7e512.v v0,\(a0\),a1,v0.t'
+-.*Error: illegal operands `vlsseg8e512.v v0,\(a0\),a1,v0.t'
+-.*Error: illegal operands `vlsseg2e1024.v v0,\(a0\),a1,v0.t'
+-.*Error: illegal operands `vlsseg3e1024.v v0,\(a0\),a1,v0.t'
+-.*Error: illegal operands `vlsseg4e1024.v v0,\(a0\),a1,v0.t'
+-.*Error: illegal operands `vlsseg5e1024.v v0,\(a0\),a1,v0.t'
+-.*Error: illegal operands `vlsseg6e1024.v v0,\(a0\),a1,v0.t'
+-.*Error: illegal operands `vlsseg7e1024.v v0,\(a0\),a1,v0.t'
+-.*Error: illegal operands `vlsseg8e1024.v v0,\(a0\),a1,v0.t'
+-.*Error: illegal operands `vlxseg2ei8.v v2,\(a0\),v2'
+-.*Error: illegal operands `vlxseg2ei8.v v0,\(a0\),v2,v0.t'
+-.*Error: illegal operands `vsxseg2ei8.v v2,\(a0\),v2'
+-.*Error: illegal operands `vsxseg2ei8.v v0,\(a0\),v2,v0.t'
+-.*Error: illegal operands `vlxseg3ei8.v v2,\(a0\),v2'
+-.*Error: illegal operands `vlxseg3ei8.v v0,\(a0\),v2,v0.t'
+-.*Error: illegal operands `vsxseg3ei8.v v2,\(a0\),v2'
+-.*Error: illegal operands `vsxseg3ei8.v v0,\(a0\),v2,v0.t'
+-.*Error: illegal operands `vlxseg4ei8.v v2,\(a0\),v2'
+-.*Error: illegal operands `vlxseg4ei8.v v0,\(a0\),v2,v0.t'
+-.*Error: illegal operands `vsxseg4ei8.v v2,\(a0\),v2'
+-.*Error: illegal operands `vsxseg4ei8.v v0,\(a0\),v2,v0.t'
+-.*Error: illegal operands `vlxseg5ei8.v v2,\(a0\),v2'
+-.*Error: illegal operands `vlxseg5ei8.v v0,\(a0\),v2,v0.t'
+-.*Error: illegal operands `vsxseg5ei8.v v2,\(a0\),v2'
+-.*Error: illegal operands `vsxseg5ei8.v v0,\(a0\),v2,v0.t'
+-.*Error: illegal operands `vlxseg6ei8.v v2,\(a0\),v2'
+-.*Error: illegal operands `vlxseg6ei8.v v0,\(a0\),v2,v0.t'
+-.*Error: illegal operands `vsxseg6ei8.v v2,\(a0\),v2'
+-.*Error: illegal operands `vsxseg6ei8.v v0,\(a0\),v2,v0.t'
+-.*Error: illegal operands `vlxseg7ei8.v v2,\(a0\),v2'
+-.*Error: illegal operands `vlxseg7ei8.v v0,\(a0\),v2,v0.t'
+-.*Error: illegal operands `vsxseg7ei8.v v2,\(a0\),v2'
+-.*Error: illegal operands `vsxseg7ei8.v v0,\(a0\),v2,v0.t'
+-.*Error: illegal operands `vlxseg8ei8.v v2,\(a0\),v2'
+-.*Error: illegal operands `vlxseg8ei8.v v0,\(a0\),v2,v0.t'
+-.*Error: illegal operands `vsxseg8ei8.v v2,\(a0\),v2'
+-.*Error: illegal operands `vsxseg8ei8.v v0,\(a0\),v2,v0.t'
+-.*Error: illegal operands `vlxseg2ei16.v v2,\(a0\),v2'
+-.*Error: illegal operands `vlxseg2ei16.v v0,\(a0\),v2,v0.t'
+-.*Error: illegal operands `vsxseg2ei16.v v2,\(a0\),v2'
+-.*Error: illegal operands `vsxseg2ei16.v v0,\(a0\),v2,v0.t'
+-.*Error: illegal operands `vlxseg3ei16.v v2,\(a0\),v2'
+-.*Error: illegal operands `vlxseg3ei16.v v0,\(a0\),v2,v0.t'
+-.*Error: illegal operands `vsxseg3ei16.v v2,\(a0\),v2'
+-.*Error: illegal operands `vsxseg3ei16.v v0,\(a0\),v2,v0.t'
+-.*Error: illegal operands `vlxseg4ei16.v v2,\(a0\),v2'
+-.*Error: illegal operands `vlxseg4ei16.v v0,\(a0\),v2,v0.t'
+-.*Error: illegal operands `vsxseg4ei16.v v2,\(a0\),v2'
+-.*Error: illegal operands `vsxseg4ei16.v v0,\(a0\),v2,v0.t'
+-.*Error: illegal operands `vlxseg5ei16.v v2,\(a0\),v2'
+-.*Error: illegal operands `vlxseg5ei16.v v0,\(a0\),v2,v0.t'
+-.*Error: illegal operands `vsxseg5ei16.v v2,\(a0\),v2'
+-.*Error: illegal operands `vsxseg5ei16.v v0,\(a0\),v2,v0.t'
+-.*Error: illegal operands `vlxseg6ei16.v v2,\(a0\),v2'
+-.*Error: illegal operands `vlxseg6ei16.v v0,\(a0\),v2,v0.t'
+-.*Error: illegal operands `vsxseg6ei16.v v2,\(a0\),v2'
+-.*Error: illegal operands `vsxseg6ei16.v v0,\(a0\),v2,v0.t'
+-.*Error: illegal operands `vlxseg7ei16.v v2,\(a0\),v2'
+-.*Error: illegal operands `vlxseg7ei16.v v0,\(a0\),v2,v0.t'
+-.*Error: illegal operands `vsxseg7ei16.v v2,\(a0\),v2'
+-.*Error: illegal operands `vsxseg7ei16.v v0,\(a0\),v2,v0.t'
+-.*Error: illegal operands `vlxseg8ei16.v v2,\(a0\),v2'
+-.*Error: illegal operands `vlxseg8ei16.v v0,\(a0\),v2,v0.t'
+-.*Error: illegal operands `vsxseg8ei16.v v2,\(a0\),v2'
+-.*Error: illegal operands `vsxseg8ei16.v v0,\(a0\),v2,v0.t'
+-.*Error: illegal operands `vlxseg2ei32.v v2,\(a0\),v2'
+-.*Error: illegal operands `vlxseg2ei32.v v0,\(a0\),v2,v0.t'
+-.*Error: illegal operands `vsxseg2ei32.v v2,\(a0\),v2'
+-.*Error: illegal operands `vsxseg2ei32.v v0,\(a0\),v2,v0.t'
+-.*Error: illegal operands `vlxseg3ei32.v v2,\(a0\),v2'
+-.*Error: illegal operands `vlxseg3ei32.v v0,\(a0\),v2,v0.t'
+-.*Error: illegal operands `vsxseg3ei32.v v2,\(a0\),v2'
+-.*Error: illegal operands `vsxseg3ei32.v v0,\(a0\),v2,v0.t'
+-.*Error: illegal operands `vlxseg4ei32.v v2,\(a0\),v2'
+-.*Error: illegal operands `vlxseg4ei32.v v0,\(a0\),v2,v0.t'
+-.*Error: illegal operands `vsxseg4ei32.v v2,\(a0\),v2'
+-.*Error: illegal operands `vsxseg4ei32.v v0,\(a0\),v2,v0.t'
+-.*Error: illegal operands `vlxseg5ei32.v v2,\(a0\),v2'
+-.*Error: illegal operands `vlxseg5ei32.v v0,\(a0\),v2,v0.t'
+-.*Error: illegal operands `vsxseg5ei32.v v2,\(a0\),v2'
+-.*Error: illegal operands `vsxseg5ei32.v v0,\(a0\),v2,v0.t'
+-.*Error: illegal operands `vlxseg6ei32.v v2,\(a0\),v2'
+-.*Error: illegal operands `vlxseg6ei32.v v0,\(a0\),v2,v0.t'
+-.*Error: illegal operands `vsxseg6ei32.v v2,\(a0\),v2'
+-.*Error: illegal operands `vsxseg6ei32.v v0,\(a0\),v2,v0.t'
+-.*Error: illegal operands `vlxseg7ei32.v v2,\(a0\),v2'
+-.*Error: illegal operands `vlxseg7ei32.v v0,\(a0\),v2,v0.t'
+-.*Error: illegal operands `vsxseg7ei32.v v2,\(a0\),v2'
+-.*Error: illegal operands `vsxseg7ei32.v v0,\(a0\),v2,v0.t'
+-.*Error: illegal operands `vlxseg8ei32.v v2,\(a0\),v2'
+-.*Error: illegal operands `vlxseg8ei32.v v0,\(a0\),v2,v0.t'
+-.*Error: illegal operands `vsxseg8ei32.v v2,\(a0\),v2'
+-.*Error: illegal operands `vsxseg8ei32.v v0,\(a0\),v2,v0.t'
+-.*Error: illegal operands `vlxseg2ei64.v v2,\(a0\),v2'
+-.*Error: illegal operands `vlxseg2ei64.v v0,\(a0\),v2,v0.t'
+-.*Error: illegal operands `vsxseg2ei64.v v2,\(a0\),v2'
+-.*Error: illegal operands `vsxseg2ei64.v v0,\(a0\),v2,v0.t'
+-.*Error: illegal operands `vlxseg3ei64.v v2,\(a0\),v2'
+-.*Error: illegal operands `vlxseg3ei64.v v0,\(a0\),v2,v0.t'
+-.*Error: illegal operands `vsxseg3ei64.v v2,\(a0\),v2'
+-.*Error: illegal operands `vsxseg3ei64.v v0,\(a0\),v2,v0.t'
+-.*Error: illegal operands `vlxseg4ei64.v v2,\(a0\),v2'
+-.*Error: illegal operands `vlxseg4ei64.v v0,\(a0\),v2,v0.t'
+-.*Error: illegal operands `vsxseg4ei64.v v2,\(a0\),v2'
+-.*Error: illegal operands `vsxseg4ei64.v v0,\(a0\),v2,v0.t'
+-.*Error: illegal operands `vlxseg5ei64.v v2,\(a0\),v2'
+-.*Error: illegal operands `vlxseg5ei64.v v0,\(a0\),v2,v0.t'
+-.*Error: illegal operands `vsxseg5ei64.v v2,\(a0\),v2'
+-.*Error: illegal operands `vsxseg5ei64.v v0,\(a0\),v2,v0.t'
+-.*Error: illegal operands `vlxseg6ei64.v v2,\(a0\),v2'
+-.*Error: illegal operands `vlxseg6ei64.v v0,\(a0\),v2,v0.t'
+-.*Error: illegal operands `vsxseg6ei64.v v2,\(a0\),v2'
+-.*Error: illegal operands `vsxseg6ei64.v v0,\(a0\),v2,v0.t'
+-.*Error: illegal operands `vlxseg7ei64.v v2,\(a0\),v2'
+-.*Error: illegal operands `vlxseg7ei64.v v0,\(a0\),v2,v0.t'
+-.*Error: illegal operands `vsxseg7ei64.v v2,\(a0\),v2'
+-.*Error: illegal operands `vsxseg7ei64.v v0,\(a0\),v2,v0.t'
+-.*Error: illegal operands `vlxseg8ei64.v v2,\(a0\),v2'
+-.*Error: illegal operands `vlxseg8ei64.v v0,\(a0\),v2,v0.t'
+-.*Error: illegal operands `vsxseg8ei64.v v2,\(a0\),v2'
+-.*Error: illegal operands `vsxseg8ei64.v v0,\(a0\),v2,v0.t'
+-.*Error: illegal operands `vlxseg2ei128.v v2,\(a0\),v2'
+-.*Error: illegal operands `vlxseg2ei128.v v0,\(a0\),v2,v0.t'
+-.*Error: illegal operands `vsxseg2ei128.v v2,\(a0\),v2'
+-.*Error: illegal operands `vsxseg2ei128.v v0,\(a0\),v2,v0.t'
+-.*Error: illegal operands `vlxseg3ei128.v v2,\(a0\),v2'
+-.*Error: illegal operands `vlxseg3ei128.v v0,\(a0\),v2,v0.t'
+-.*Error: illegal operands `vsxseg3ei128.v v2,\(a0\),v2'
+-.*Error: illegal operands `vsxseg3ei128.v v0,\(a0\),v2,v0.t'
+-.*Error: illegal operands `vlxseg4ei128.v v2,\(a0\),v2'
+-.*Error: illegal operands `vlxseg4ei128.v v0,\(a0\),v2,v0.t'
+-.*Error: illegal operands `vsxseg4ei128.v v2,\(a0\),v2'
+-.*Error: illegal operands `vsxseg4ei128.v v0,\(a0\),v2,v0.t'
+-.*Error: illegal operands `vlxseg5ei128.v v2,\(a0\),v2'
+-.*Error: illegal operands `vlxseg5ei128.v v0,\(a0\),v2,v0.t'
+-.*Error: illegal operands `vsxseg5ei128.v v2,\(a0\),v2'
+-.*Error: illegal operands `vsxseg5ei128.v v0,\(a0\),v2,v0.t'
+-.*Error: illegal operands `vlxseg6ei128.v v2,\(a0\),v2'
+-.*Error: illegal operands `vlxseg6ei128.v v0,\(a0\),v2,v0.t'
+-.*Error: illegal operands `vsxseg6ei128.v v2,\(a0\),v2'
+-.*Error: illegal operands `vsxseg6ei128.v v0,\(a0\),v2,v0.t'
+-.*Error: illegal operands `vlxseg7ei128.v v2,\(a0\),v2'
+-.*Error: illegal operands `vlxseg7ei128.v v0,\(a0\),v2,v0.t'
+-.*Error: illegal operands `vsxseg7ei128.v v2,\(a0\),v2'
+-.*Error: illegal operands `vsxseg7ei128.v v0,\(a0\),v2,v0.t'
+-.*Error: illegal operands `vlxseg8ei128.v v2,\(a0\),v2'
+-.*Error: illegal operands `vlxseg8ei128.v v0,\(a0\),v2,v0.t'
+-.*Error: illegal operands `vsxseg8ei128.v v2,\(a0\),v2'
+-.*Error: illegal operands `vsxseg8ei128.v v0,\(a0\),v2,v0.t'
+-.*Error: illegal operands `vlxseg2ei256.v v2,\(a0\),v2'
+-.*Error: illegal operands `vlxseg2ei256.v v0,\(a0\),v2,v0.t'
+-.*Error: illegal operands `vsxseg2ei256.v v2,\(a0\),v2'
+-.*Error: illegal operands `vsxseg2ei256.v v0,\(a0\),v2,v0.t'
+-.*Error: illegal operands `vlxseg3ei256.v v2,\(a0\),v2'
+-.*Error: illegal operands `vlxseg3ei256.v v0,\(a0\),v2,v0.t'
+-.*Error: illegal operands `vsxseg3ei256.v v2,\(a0\),v2'
+-.*Error: illegal operands `vsxseg3ei256.v v0,\(a0\),v2,v0.t'
+-.*Error: illegal operands `vlxseg4ei256.v v2,\(a0\),v2'
+-.*Error: illegal operands `vlxseg4ei256.v v0,\(a0\),v2,v0.t'
+-.*Error: illegal operands `vsxseg4ei256.v v2,\(a0\),v2'
+-.*Error: illegal operands `vsxseg4ei256.v v0,\(a0\),v2,v0.t'
+-.*Error: illegal operands `vlxseg5ei256.v v2,\(a0\),v2'
+-.*Error: illegal operands `vlxseg5ei256.v v0,\(a0\),v2,v0.t'
+-.*Error: illegal operands `vsxseg5ei256.v v2,\(a0\),v2'
+-.*Error: illegal operands `vsxseg5ei256.v v0,\(a0\),v2,v0.t'
+-.*Error: illegal operands `vlxseg6ei256.v v2,\(a0\),v2'
+-.*Error: illegal operands `vlxseg6ei256.v v0,\(a0\),v2,v0.t'
+-.*Error: illegal operands `vsxseg6ei256.v v2,\(a0\),v2'
+-.*Error: illegal operands `vsxseg6ei256.v v0,\(a0\),v2,v0.t'
+-.*Error: illegal operands `vlxseg7ei256.v v2,\(a0\),v2'
+-.*Error: illegal operands `vlxseg7ei256.v v0,\(a0\),v2,v0.t'
+-.*Error: illegal operands `vsxseg7ei256.v v2,\(a0\),v2'
+-.*Error: illegal operands `vsxseg7ei256.v v0,\(a0\),v2,v0.t'
+-.*Error: illegal operands `vlxseg8ei256.v v2,\(a0\),v2'
+-.*Error: illegal operands `vlxseg8ei256.v v0,\(a0\),v2,v0.t'
+-.*Error: illegal operands `vsxseg8ei256.v v2,\(a0\),v2'
+-.*Error: illegal operands `vsxseg8ei256.v v0,\(a0\),v2,v0.t'
+-.*Error: illegal operands `vlxseg2ei512.v v2,\(a0\),v2'
+-.*Error: illegal operands `vlxseg2ei512.v v0,\(a0\),v2,v0.t'
+-.*Error: illegal operands `vsxseg2ei512.v v2,\(a0\),v2'
+-.*Error: illegal operands `vsxseg2ei512.v v0,\(a0\),v2,v0.t'
+-.*Error: illegal operands `vlxseg3ei512.v v2,\(a0\),v2'
+-.*Error: illegal operands `vlxseg3ei512.v v0,\(a0\),v2,v0.t'
+-.*Error: illegal operands `vsxseg3ei512.v v2,\(a0\),v2'
+-.*Error: illegal operands `vsxseg3ei512.v v0,\(a0\),v2,v0.t'
+-.*Error: illegal operands `vlxseg4ei512.v v2,\(a0\),v2'
+-.*Error: illegal operands `vlxseg4ei512.v v0,\(a0\),v2,v0.t'
+-.*Error: illegal operands `vsxseg4ei512.v v2,\(a0\),v2'
+-.*Error: illegal operands `vsxseg4ei512.v v0,\(a0\),v2,v0.t'
+-.*Error: illegal operands `vlxseg5ei512.v v2,\(a0\),v2'
+-.*Error: illegal operands `vlxseg5ei512.v v0,\(a0\),v2,v0.t'
+-.*Error: illegal operands `vsxseg5ei512.v v2,\(a0\),v2'
+-.*Error: illegal operands `vsxseg5ei512.v v0,\(a0\),v2,v0.t'
+-.*Error: illegal operands `vlxseg6ei512.v v2,\(a0\),v2'
+-.*Error: illegal operands `vlxseg6ei512.v v0,\(a0\),v2,v0.t'
+-.*Error: illegal operands `vsxseg6ei512.v v2,\(a0\),v2'
+-.*Error: illegal operands `vsxseg6ei512.v v0,\(a0\),v2,v0.t'
+-.*Error: illegal operands `vlxseg7ei512.v v2,\(a0\),v2'
+-.*Error: illegal operands `vlxseg7ei512.v v0,\(a0\),v2,v0.t'
+-.*Error: illegal operands `vsxseg7ei512.v v2,\(a0\),v2'
+-.*Error: illegal operands `vsxseg7ei512.v v0,\(a0\),v2,v0.t'
+-.*Error: illegal operands `vlxseg8ei512.v v2,\(a0\),v2'
+-.*Error: illegal operands `vlxseg8ei512.v v0,\(a0\),v2,v0.t'
+-.*Error: illegal operands `vsxseg8ei512.v v2,\(a0\),v2'
+-.*Error: illegal operands `vsxseg8ei512.v v0,\(a0\),v2,v0.t'
+-.*Error: illegal operands `vlxseg2ei1024.v v2,\(a0\),v2'
+-.*Error: illegal operands `vlxseg2ei1024.v v0,\(a0\),v2,v0.t'
+-.*Error: illegal operands `vsxseg2ei1024.v v2,\(a0\),v2'
+-.*Error: illegal operands `vsxseg2ei1024.v v0,\(a0\),v2,v0.t'
+-.*Error: illegal operands `vlxseg3ei1024.v v2,\(a0\),v2'
+-.*Error: illegal operands `vlxseg3ei1024.v v0,\(a0\),v2,v0.t'
+-.*Error: illegal operands `vsxseg3ei1024.v v2,\(a0\),v2'
+-.*Error: illegal operands `vsxseg3ei1024.v v0,\(a0\),v2,v0.t'
+-.*Error: illegal operands `vlxseg4ei1024.v v2,\(a0\),v2'
+-.*Error: illegal operands `vlxseg4ei1024.v v0,\(a0\),v2,v0.t'
+-.*Error: illegal operands `vsxseg4ei1024.v v2,\(a0\),v2'
+-.*Error: illegal operands `vsxseg4ei1024.v v0,\(a0\),v2,v0.t'
+-.*Error: illegal operands `vlxseg5ei1024.v v2,\(a0\),v2'
+-.*Error: illegal operands `vlxseg5ei1024.v v0,\(a0\),v2,v0.t'
+-.*Error: illegal operands `vsxseg5ei1024.v v2,\(a0\),v2'
+-.*Error: illegal operands `vsxseg5ei1024.v v0,\(a0\),v2,v0.t'
+-.*Error: illegal operands `vlxseg6ei1024.v v2,\(a0\),v2'
+-.*Error: illegal operands `vlxseg6ei1024.v v0,\(a0\),v2,v0.t'
+-.*Error: illegal operands `vsxseg6ei1024.v v2,\(a0\),v2'
+-.*Error: illegal operands `vsxseg6ei1024.v v0,\(a0\),v2,v0.t'
+-.*Error: illegal operands `vlxseg7ei1024.v v2,\(a0\),v2'
+-.*Error: illegal operands `vlxseg7ei1024.v v0,\(a0\),v2,v0.t'
+-.*Error: illegal operands `vsxseg7ei1024.v v2,\(a0\),v2'
+-.*Error: illegal operands `vsxseg7ei1024.v v0,\(a0\),v2,v0.t'
+-.*Error: illegal operands `vlxseg8ei1024.v v2,\(a0\),v2'
+-.*Error: illegal operands `vlxseg8ei1024.v v0,\(a0\),v2,v0.t'
+-.*Error: illegal operands `vsxseg8ei1024.v v2,\(a0\),v2'
+-.*Error: illegal operands `vsxseg8ei1024.v v0,\(a0\),v2,v0.t'
+diff --git a/gas/testsuite/gas/riscv/vector-insns-fail-01.s b/gas/testsuite/gas/riscv/vector-insns-fail-01.s
+deleted file mode 100644
+index 4c1a913f2d..0000000000
+--- a/gas/testsuite/gas/riscv/vector-insns-fail-01.s
++++ /dev/null
+@@ -1,1037 +0,0 @@
+-# Vector Unit-Stride Segment Loads and Stores
+-
+-	vlseg2e8.v v0, (a0), v0.t	# vd overlap vm
+-	vlseg2e8.v v4, (a0), v0.t	# OK
+-	vsseg2e8.v v0, (a0), v0.t	# OK
+-	vsseg2e8.v v4, (a0), v0.t	# OK
+-	vlseg2e8ff.v v0, (a0), v0.t	# vd overlap vm
+-	vlseg2e8ff.v v4, (a0), v0.t	# OK
+-	vlseg3e8.v v0, (a0), v0.t	# vd overlap vm
+-	vlseg3e8.v v4, (a0), v0.t	# OK
+-	vsseg3e8.v v0, (a0), v0.t	# OK
+-	vsseg3e8.v v4, (a0), v0.t	# OK
+-	vlseg3e8ff.v v0, (a0), v0.t	# vd overlap vm
+-	vlseg3e8ff.v v4, (a0), v0.t	# OK
+-	vlseg4e8.v v0, (a0), v0.t	# vd overlap vm
+-	vlseg4e8.v v4, (a0), v0.t	# OK
+-	vsseg4e8.v v0, (a0), v0.t	# OK
+-	vsseg4e8.v v4, (a0), v0.t	# OK
+-	vlseg4e8ff.v v0, (a0), v0.t	# vd overlap vm
+-	vlseg4e8ff.v v4, (a0), v0.t	# OK
+-	vlseg5e8.v v0, (a0), v0.t	# vd overlap vm
+-	vlseg5e8.v v4, (a0), v0.t	# OK
+-	vsseg5e8.v v0, (a0), v0.t	# OK
+-	vsseg5e8.v v4, (a0), v0.t	# OK
+-	vlseg5e8ff.v v0, (a0), v0.t	# vd overlap vm
+-	vlseg5e8ff.v v4, (a0), v0.t	# OK
+-	vlseg6e8.v v0, (a0), v0.t	# vd overlap vm
+-	vlseg6e8.v v4, (a0), v0.t	# OK
+-	vsseg6e8.v v0, (a0), v0.t	# OK
+-	vsseg6e8.v v4, (a0), v0.t	# OK
+-	vlseg6e8ff.v v0, (a0), v0.t	# vd overlap vm
+-	vlseg6e8ff.v v4, (a0), v0.t	# OK
+-	vlseg7e8.v v0, (a0), v0.t	# vd overlap vm
+-	vlseg7e8.v v4, (a0), v0.t	# OK
+-	vsseg7e8.v v0, (a0), v0.t	# OK
+-	vsseg7e8.v v4, (a0), v0.t	# OK
+-	vlseg7e8ff.v v0, (a0), v0.t	# vd overlap vm
+-	vlseg7e8ff.v v4, (a0), v0.t	# OK
+-	vlseg8e8.v v0, (a0), v0.t	# vd overlap vm
+-	vlseg8e8.v v4, (a0), v0.t	# OK
+-	vsseg8e8.v v0, (a0), v0.t	# OK
+-	vsseg8e8.v v4, (a0), v0.t	# OK
+-	vlseg8e8ff.v v0, (a0), v0.t	# vd overlap vm
+-	vlseg8e8ff.v v4, (a0), v0.t	# OK
+-
+-	vlseg2e16.v v0, (a0), v0.t	# vd overlap vm
+-	vlseg2e16.v v4, (a0), v0.t	# OK
+-	vsseg2e16.v v0, (a0), v0.t	# OK
+-	vsseg2e16.v v4, (a0), v0.t	# OK
+-	vlseg2e16ff.v v0, (a0), v0.t	# vd overlap vm
+-	vlseg2e16ff.v v4, (a0), v0.t	# OK
+-	vlseg3e16.v v0, (a0), v0.t	# vd overlap vm
+-	vlseg3e16.v v4, (a0), v0.t	# OK
+-	vsseg3e16.v v0, (a0), v0.t	# OK
+-	vsseg3e16.v v4, (a0), v0.t	# OK
+-	vlseg3e16ff.v v0, (a0), v0.t	# vd overlap vm
+-	vlseg3e16ff.v v4, (a0), v0.t	# OK
+-	vlseg4e16.v v0, (a0), v0.t	# vd overlap vm
+-	vlseg4e16.v v4, (a0), v0.t	# OK
+-	vsseg4e16.v v0, (a0), v0.t	# OK
+-	vsseg4e16.v v4, (a0), v0.t	# OK
+-	vlseg4e16ff.v v0, (a0), v0.t	# vd overlap vm
+-	vlseg4e16ff.v v4, (a0), v0.t	# OK
+-	vlseg5e16.v v0, (a0), v0.t	# vd overlap vm
+-	vlseg5e16.v v4, (a0), v0.t	# OK
+-	vsseg5e16.v v0, (a0), v0.t	# OK
+-	vsseg5e16.v v4, (a0), v0.t	# OK
+-	vlseg5e16ff.v v0, (a0), v0.t	# vd overlap vm
+-	vlseg5e16ff.v v4, (a0), v0.t	# OK
+-	vlseg6e16.v v0, (a0), v0.t	# vd overlap vm
+-	vlseg6e16.v v4, (a0), v0.t	# OK
+-	vsseg6e16.v v0, (a0), v0.t	# OK
+-	vsseg6e16.v v4, (a0), v0.t	# OK
+-	vlseg6e16ff.v v0, (a0), v0.t	# vd overlap vm
+-	vlseg6e16ff.v v4, (a0), v0.t	# OK
+-	vlseg7e16.v v0, (a0), v0.t	# vd overlap vm
+-	vlseg7e16.v v4, (a0), v0.t	# OK
+-	vsseg7e16.v v0, (a0), v0.t	# OK
+-	vsseg7e16.v v4, (a0), v0.t	# OK
+-	vlseg7e16ff.v v0, (a0), v0.t	# vd overlap vm
+-	vlseg7e16ff.v v4, (a0), v0.t	# OK
+-	vlseg8e16.v v0, (a0), v0.t	# vd overlap vm
+-	vlseg8e16.v v4, (a0), v0.t	# OK
+-	vsseg8e16.v v0, (a0), v0.t	# OK
+-	vsseg8e16.v v4, (a0), v0.t	# OK
+-	vlseg8e16ff.v v0, (a0), v0.t	# vd overlap vm
+-	vlseg8e16ff.v v4, (a0), v0.t	# OK
+-
+-	vlseg2e32.v v0, (a0), v0.t	# vd overlap vm
+-	vlseg2e32.v v4, (a0), v0.t	# OK
+-	vsseg2e32.v v0, (a0), v0.t	# OK
+-	vsseg2e32.v v4, (a0), v0.t	# OK
+-	vlseg2e32ff.v v0, (a0), v0.t	# vd overlap vm
+-	vlseg2e32ff.v v4, (a0), v0.t	# OK
+-	vlseg3e32.v v0, (a0), v0.t	# vd overlap vm
+-	vlseg3e32.v v4, (a0), v0.t	# OK
+-	vsseg3e32.v v0, (a0), v0.t	# OK
+-	vsseg3e32.v v4, (a0), v0.t	# OK
+-	vlseg3e32ff.v v0, (a0), v0.t	# vd overlap vm
+-	vlseg3e32ff.v v4, (a0), v0.t	# OK
+-	vlseg4e32.v v0, (a0), v0.t	# vd overlap vm
+-	vlseg4e32.v v4, (a0), v0.t	# OK
+-	vsseg4e32.v v0, (a0), v0.t	# OK
+-	vsseg4e32.v v4, (a0), v0.t	# OK
+-	vlseg4e32ff.v v0, (a0), v0.t	# vd overlap vm
+-	vlseg4e32ff.v v4, (a0), v0.t	# OK
+-	vlseg5e32.v v0, (a0), v0.t	# vd overlap vm
+-	vlseg5e32.v v4, (a0), v0.t	# OK
+-	vsseg5e32.v v0, (a0), v0.t	# OK
+-	vsseg5e32.v v4, (a0), v0.t	# OK
+-	vlseg5e32ff.v v0, (a0), v0.t	# vd overlap vm
+-	vlseg5e32ff.v v4, (a0), v0.t	# OK
+-	vlseg6e32.v v0, (a0), v0.t	# vd overlap vm
+-	vlseg6e32.v v4, (a0), v0.t	# OK
+-	vsseg6e32.v v0, (a0), v0.t	# OK
+-	vsseg6e32.v v4, (a0), v0.t	# OK
+-	vlseg6e32ff.v v0, (a0), v0.t	# vd overlap vm
+-	vlseg6e32ff.v v4, (a0), v0.t	# OK
+-	vlseg7e32.v v0, (a0), v0.t	# vd overlap vm
+-	vlseg7e32.v v4, (a0), v0.t	# OK
+-	vsseg7e32.v v0, (a0), v0.t	# OK
+-	vsseg7e32.v v4, (a0), v0.t	# OK
+-	vlseg7e32ff.v v0, (a0), v0.t	# vd overlap vm
+-	vlseg7e32ff.v v4, (a0), v0.t	# OK
+-	vlseg8e32.v v0, (a0), v0.t	# vd overlap vm
+-	vlseg8e32.v v4, (a0), v0.t	# OK
+-	vsseg8e32.v v0, (a0), v0.t	# OK
+-	vsseg8e32.v v4, (a0), v0.t	# OK
+-	vlseg8e32ff.v v0, (a0), v0.t	# vd overlap vm
+-	vlseg8e32ff.v v4, (a0), v0.t	# OK
+-
+-	vlseg2e64.v v0, (a0), v0.t	# vd overlap vm
+-	vlseg2e64.v v4, (a0), v0.t	# OK
+-	vsseg2e64.v v0, (a0), v0.t	# OK
+-	vsseg2e64.v v4, (a0), v0.t	# OK
+-	vlseg2e64ff.v v0, (a0), v0.t	# vd overlap vm
+-	vlseg2e64ff.v v4, (a0), v0.t	# OK
+-	vlseg3e64.v v0, (a0), v0.t	# vd overlap vm
+-	vlseg3e64.v v4, (a0), v0.t	# OK
+-	vsseg3e64.v v0, (a0), v0.t	# OK
+-	vsseg3e64.v v4, (a0), v0.t	# OK
+-	vlseg3e64ff.v v0, (a0), v0.t	# vd overlap vm
+-	vlseg3e64ff.v v4, (a0), v0.t	# OK
+-	vlseg4e64.v v0, (a0), v0.t	# vd overlap vm
+-	vlseg4e64.v v4, (a0), v0.t	# OK
+-	vsseg4e64.v v0, (a0), v0.t	# OK
+-	vsseg4e64.v v4, (a0), v0.t	# OK
+-	vlseg4e64ff.v v0, (a0), v0.t	# vd overlap vm
+-	vlseg4e64ff.v v4, (a0), v0.t	# OK
+-	vlseg5e64.v v0, (a0), v0.t	# vd overlap vm
+-	vlseg5e64.v v4, (a0), v0.t	# OK
+-	vsseg5e64.v v0, (a0), v0.t	# OK
+-	vsseg5e64.v v4, (a0), v0.t	# OK
+-	vlseg5e64ff.v v0, (a0), v0.t	# vd overlap vm
+-	vlseg5e64ff.v v4, (a0), v0.t	# OK
+-	vlseg6e64.v v0, (a0), v0.t	# vd overlap vm
+-	vlseg6e64.v v4, (a0), v0.t	# OK
+-	vsseg6e64.v v0, (a0), v0.t	# OK
+-	vsseg6e64.v v4, (a0), v0.t	# OK
+-	vlseg6e64ff.v v0, (a0), v0.t	# vd overlap vm
+-	vlseg6e64ff.v v4, (a0), v0.t	# OK
+-	vlseg7e64.v v0, (a0), v0.t	# vd overlap vm
+-	vlseg7e64.v v4, (a0), v0.t	# OK
+-	vsseg7e64.v v0, (a0), v0.t	# OK
+-	vsseg7e64.v v4, (a0), v0.t	# OK
+-	vlseg7e64ff.v v0, (a0), v0.t	# vd overlap vm
+-	vlseg7e64ff.v v4, (a0), v0.t	# OK
+-	vlseg8e64.v v0, (a0), v0.t	# vd overlap vm
+-	vlseg8e64.v v4, (a0), v0.t	# OK
+-	vsseg8e64.v v0, (a0), v0.t	# OK
+-	vsseg8e64.v v4, (a0), v0.t	# OK
+-	vlseg8e64ff.v v0, (a0), v0.t	# vd overlap vm
+-	vlseg8e64ff.v v4, (a0), v0.t	# OK
+-
+-	vlseg2e128.v v0, (a0), v0.t	# vd overlap vm
+-	vlseg2e128.v v4, (a0), v0.t	# OK
+-	vsseg2e128.v v0, (a0), v0.t	# OK
+-	vsseg2e128.v v4, (a0), v0.t	# OK
+-	vlseg2e128ff.v v0, (a0), v0.t	# vd overlap vm
+-	vlseg2e128ff.v v4, (a0), v0.t	# OK
+-	vlseg3e128.v v0, (a0), v0.t	# vd overlap vm
+-	vlseg3e128.v v4, (a0), v0.t	# OK
+-	vsseg3e128.v v0, (a0), v0.t	# OK
+-	vsseg3e128.v v4, (a0), v0.t	# OK
+-	vlseg3e128ff.v v0, (a0), v0.t	# vd overlap vm
+-	vlseg3e128ff.v v4, (a0), v0.t	# OK
+-	vlseg4e128.v v0, (a0), v0.t	# vd overlap vm
+-	vlseg4e128.v v4, (a0), v0.t	# OK
+-	vsseg4e128.v v0, (a0), v0.t	# OK
+-	vsseg4e128.v v4, (a0), v0.t	# OK
+-	vlseg4e128ff.v v0, (a0), v0.t	# vd overlap vm
+-	vlseg4e128ff.v v4, (a0), v0.t	# OK
+-	vlseg5e128.v v0, (a0), v0.t	# vd overlap vm
+-	vlseg5e128.v v4, (a0), v0.t	# OK
+-	vsseg5e128.v v0, (a0), v0.t	# OK
+-	vsseg5e128.v v4, (a0), v0.t	# OK
+-	vlseg5e128ff.v v0, (a0), v0.t	# vd overlap vm
+-	vlseg5e128ff.v v4, (a0), v0.t	# OK
+-	vlseg6e128.v v0, (a0), v0.t	# vd overlap vm
+-	vlseg6e128.v v4, (a0), v0.t	# OK
+-	vsseg6e128.v v0, (a0), v0.t	# OK
+-	vsseg6e128.v v4, (a0), v0.t	# OK
+-	vlseg6e128ff.v v0, (a0), v0.t	# vd overlap vm
+-	vlseg6e128ff.v v4, (a0), v0.t	# OK
+-	vlseg7e128.v v0, (a0), v0.t	# vd overlap vm
+-	vlseg7e128.v v4, (a0), v0.t	# OK
+-	vsseg7e128.v v0, (a0), v0.t	# OK
+-	vsseg7e128.v v4, (a0), v0.t	# OK
+-	vlseg7e128ff.v v0, (a0), v0.t	# vd overlap vm
+-	vlseg7e128ff.v v4, (a0), v0.t	# OK
+-	vlseg8e128.v v0, (a0), v0.t	# vd overlap vm
+-	vlseg8e128.v v4, (a0), v0.t	# OK
+-	vsseg8e128.v v0, (a0), v0.t	# OK
+-	vsseg8e128.v v4, (a0), v0.t	# OK
+-	vlseg8e128ff.v v0, (a0), v0.t	# vd overlap vm
+-	vlseg8e128ff.v v4, (a0), v0.t	# OK
+-
+-	vlseg2e256.v v0, (a0), v0.t	# vd overlap vm
+-	vlseg2e256.v v4, (a0), v0.t	# OK
+-	vsseg2e256.v v0, (a0), v0.t	# OK
+-	vsseg2e256.v v4, (a0), v0.t	# OK
+-	vlseg2e256ff.v v0, (a0), v0.t	# vd overlap vm
+-	vlseg2e256ff.v v4, (a0), v0.t	# OK
+-	vlseg3e256.v v0, (a0), v0.t	# vd overlap vm
+-	vlseg3e256.v v4, (a0), v0.t	# OK
+-	vsseg3e256.v v0, (a0), v0.t	# OK
+-	vsseg3e256.v v4, (a0), v0.t	# OK
+-	vlseg3e256ff.v v0, (a0), v0.t	# vd overlap vm
+-	vlseg3e256ff.v v4, (a0), v0.t	# OK
+-	vlseg4e256.v v0, (a0), v0.t	# vd overlap vm
+-	vlseg4e256.v v4, (a0), v0.t	# OK
+-	vsseg4e256.v v0, (a0), v0.t	# OK
+-	vsseg4e256.v v4, (a0), v0.t	# OK
+-	vlseg4e256ff.v v0, (a0), v0.t	# vd overlap vm
+-	vlseg4e256ff.v v4, (a0), v0.t	# OK
+-	vlseg5e256.v v0, (a0), v0.t	# vd overlap vm
+-	vlseg5e256.v v4, (a0), v0.t	# OK
+-	vsseg5e256.v v0, (a0), v0.t	# OK
+-	vsseg5e256.v v4, (a0), v0.t	# OK
+-	vlseg5e256ff.v v0, (a0), v0.t	# vd overlap vm
+-	vlseg5e256ff.v v4, (a0), v0.t	# OK
+-	vlseg6e256.v v0, (a0), v0.t	# vd overlap vm
+-	vlseg6e256.v v4, (a0), v0.t	# OK
+-	vsseg6e256.v v0, (a0), v0.t	# OK
+-	vsseg6e256.v v4, (a0), v0.t	# OK
+-	vlseg6e256ff.v v0, (a0), v0.t	# vd overlap vm
+-	vlseg6e256ff.v v4, (a0), v0.t	# OK
+-	vlseg7e256.v v0, (a0), v0.t	# vd overlap vm
+-	vlseg7e256.v v4, (a0), v0.t	# OK
+-	vsseg7e256.v v0, (a0), v0.t	# OK
+-	vsseg7e256.v v4, (a0), v0.t	# OK
+-	vlseg7e256ff.v v0, (a0), v0.t	# vd overlap vm
+-	vlseg7e256ff.v v4, (a0), v0.t	# OK
+-	vlseg8e256.v v0, (a0), v0.t	# vd overlap vm
+-	vlseg8e256.v v4, (a0), v0.t	# OK
+-	vsseg8e256.v v0, (a0), v0.t	# OK
+-	vsseg8e256.v v4, (a0), v0.t	# OK
+-	vlseg8e256ff.v v0, (a0), v0.t	# vd overlap vm
+-	vlseg8e256ff.v v4, (a0), v0.t	# OK
+-
+-	vlseg2e512.v v0, (a0), v0.t	# vd overlap vm
+-	vlseg2e512.v v4, (a0), v0.t	# OK
+-	vsseg2e512.v v0, (a0), v0.t	# OK
+-	vsseg2e512.v v4, (a0), v0.t	# OK
+-	vlseg2e512ff.v v0, (a0), v0.t	# vd overlap vm
+-	vlseg2e512ff.v v4, (a0), v0.t	# OK
+-	vlseg3e512.v v0, (a0), v0.t	# vd overlap vm
+-	vlseg3e512.v v4, (a0), v0.t	# OK
+-	vsseg3e512.v v0, (a0), v0.t	# OK
+-	vsseg3e512.v v4, (a0), v0.t	# OK
+-	vlseg3e512ff.v v0, (a0), v0.t	# vd overlap vm
+-	vlseg3e512ff.v v4, (a0), v0.t	# OK
+-	vlseg4e512.v v0, (a0), v0.t	# vd overlap vm
+-	vlseg4e512.v v4, (a0), v0.t	# OK
+-	vsseg4e512.v v0, (a0), v0.t	# OK
+-	vsseg4e512.v v4, (a0), v0.t	# OK
+-	vlseg4e512ff.v v0, (a0), v0.t	# vd overlap vm
+-	vlseg4e512ff.v v4, (a0), v0.t	# OK
+-	vlseg5e512.v v0, (a0), v0.t	# vd overlap vm
+-	vlseg5e512.v v4, (a0), v0.t	# OK
+-	vsseg5e512.v v0, (a0), v0.t	# OK
+-	vsseg5e512.v v4, (a0), v0.t	# OK
+-	vlseg5e512ff.v v0, (a0), v0.t	# vd overlap vm
+-	vlseg5e512ff.v v4, (a0), v0.t	# OK
+-	vlseg6e512.v v0, (a0), v0.t	# vd overlap vm
+-	vlseg6e512.v v4, (a0), v0.t	# OK
+-	vsseg6e512.v v0, (a0), v0.t	# OK
+-	vsseg6e512.v v4, (a0), v0.t	# OK
+-	vlseg6e512ff.v v0, (a0), v0.t	# vd overlap vm
+-	vlseg6e512ff.v v4, (a0), v0.t	# OK
+-	vlseg7e512.v v0, (a0), v0.t	# vd overlap vm
+-	vlseg7e512.v v4, (a0), v0.t	# OK
+-	vsseg7e512.v v0, (a0), v0.t	# OK
+-	vsseg7e512.v v4, (a0), v0.t	# OK
+-	vlseg7e512ff.v v0, (a0), v0.t	# vd overlap vm
+-	vlseg7e512ff.v v4, (a0), v0.t	# OK
+-	vlseg8e512.v v0, (a0), v0.t	# vd overlap vm
+-	vlseg8e512.v v4, (a0), v0.t	# OK
+-	vsseg8e512.v v0, (a0), v0.t	# OK
+-	vsseg8e512.v v4, (a0), v0.t	# OK
+-	vlseg8e512ff.v v0, (a0), v0.t	# vd overlap vm
+-	vlseg8e512ff.v v4, (a0), v0.t	# OK
+-
+-	vlseg2e1024.v v0, (a0), v0.t	# vd overlap vm
+-	vlseg2e1024.v v4, (a0), v0.t	# OK
+-	vsseg2e1024.v v0, (a0), v0.t	# OK
+-	vsseg2e1024.v v4, (a0), v0.t	# OK
+-	vlseg2e1024ff.v v0, (a0), v0.t	# vd overlap vm
+-	vlseg2e1024ff.v v4, (a0), v0.t	# OK
+-	vlseg3e1024.v v0, (a0), v0.t	# vd overlap vm
+-	vlseg3e1024.v v4, (a0), v0.t	# OK
+-	vsseg3e1024.v v0, (a0), v0.t	# OK
+-	vsseg3e1024.v v4, (a0), v0.t	# OK
+-	vlseg3e1024ff.v v0, (a0), v0.t	# vd overlap vm
+-	vlseg3e1024ff.v v4, (a0), v0.t	# OK
+-	vlseg4e1024.v v0, (a0), v0.t	# vd overlap vm
+-	vlseg4e1024.v v4, (a0), v0.t	# OK
+-	vsseg4e1024.v v0, (a0), v0.t	# OK
+-	vsseg4e1024.v v4, (a0), v0.t	# OK
+-	vlseg4e1024ff.v v0, (a0), v0.t	# vd overlap vm
+-	vlseg4e1024ff.v v4, (a0), v0.t	# OK
+-	vlseg5e1024.v v0, (a0), v0.t	# vd overlap vm
+-	vlseg5e1024.v v4, (a0), v0.t	# OK
+-	vsseg5e1024.v v0, (a0), v0.t	# OK
+-	vsseg5e1024.v v4, (a0), v0.t	# OK
+-	vlseg5e1024ff.v v0, (a0), v0.t	# vd overlap vm
+-	vlseg5e1024ff.v v4, (a0), v0.t	# OK
+-	vlseg6e1024.v v0, (a0), v0.t	# vd overlap vm
+-	vlseg6e1024.v v4, (a0), v0.t	# OK
+-	vsseg6e1024.v v0, (a0), v0.t	# OK
+-	vsseg6e1024.v v4, (a0), v0.t	# OK
+-	vlseg6e1024ff.v v0, (a0), v0.t	# vd overlap vm
+-	vlseg6e1024ff.v v4, (a0), v0.t	# OK
+-	vlseg7e1024.v v0, (a0), v0.t	# vd overlap vm
+-	vlseg7e1024.v v4, (a0), v0.t	# OK
+-	vsseg7e1024.v v0, (a0), v0.t	# OK
+-	vsseg7e1024.v v4, (a0), v0.t	# OK
+-	vlseg7e1024ff.v v0, (a0), v0.t	# vd overlap vm
+-	vlseg7e1024ff.v v4, (a0), v0.t	# OK
+-	vlseg8e1024.v v0, (a0), v0.t	# vd overlap vm
+-	vlseg8e1024.v v4, (a0), v0.t	# OK
+-	vsseg8e1024.v v0, (a0), v0.t	# OK
+-	vsseg8e1024.v v4, (a0), v0.t	# OK
+-	vlseg8e1024ff.v v0, (a0), v0.t	# vd overlap vm
+-	vlseg8e1024ff.v v4, (a0), v0.t	# OK
+-
+-# Vector Strided Segment Loads and Stores
+-
+-	vlsseg2e8.v v0, (a0), a1, v0.t	# vd overlap vm
+-	vlsseg2e8.v v4, (a0), a1, v0.t	# OK
+-	vssseg2e8.v v0, (a0), a1, v0.t	# vd overlap vm
+-	vssseg2e8.v v4, (a0), a1, v0.t	# OK
+-	vlsseg3e8.v v0, (a0), a1, v0.t	# vd overlap vm
+-	vlsseg3e8.v v4, (a0), a1, v0.t	# OK
+-	vssseg3e8.v v0, (a0), a1, v0.t	# vd overlap vm
+-	vssseg3e8.v v4, (a0), a1, v0.t	# OK
+-	vlsseg4e8.v v0, (a0), a1, v0.t	# vd overlap vm
+-	vlsseg4e8.v v4, (a0), a1, v0.t	# OK
+-	vssseg4e8.v v0, (a0), a1, v0.t	# vd overlap vm
+-	vssseg4e8.v v4, (a0), a1, v0.t	# OK
+-	vlsseg5e8.v v0, (a0), a1, v0.t	# vd overlap vm
+-	vlsseg5e8.v v4, (a0), a1, v0.t	# OK
+-	vssseg5e8.v v0, (a0), a1, v0.t	# vd overlap vm
+-	vssseg5e8.v v4, (a0), a1, v0.t	# OK
+-	vlsseg6e8.v v0, (a0), a1, v0.t	# vd overlap vm
+-	vlsseg6e8.v v4, (a0), a1, v0.t	# OK
+-	vssseg6e8.v v0, (a0), a1, v0.t	# vd overlap vm
+-	vssseg6e8.v v4, (a0), a1, v0.t	# OK
+-	vlsseg7e8.v v0, (a0), a1, v0.t	# vd overlap vm
+-	vlsseg7e8.v v4, (a0), a1, v0.t	# OK
+-	vssseg7e8.v v0, (a0), a1, v0.t	# vd overlap vm
+-	vssseg7e8.v v4, (a0), a1, v0.t	# OK
+-	vlsseg8e8.v v0, (a0), a1, v0.t	# vd overlap vm
+-	vlsseg8e8.v v4, (a0), a1, v0.t	# OK
+-	vssseg8e8.v v0, (a0), a1, v0.t	# vd overlap vm
+-	vssseg8e8.v v4, (a0), a1, v0.t	# OK
+-
+-	vlsseg2e16.v v0, (a0), a1, v0.t	# vd overlap vm
+-	vlsseg2e16.v v4, (a0), a1, v0.t	# OK
+-	vssseg2e16.v v0, (a0), a1, v0.t	# vd overlap vm
+-	vssseg2e16.v v4, (a0), a1, v0.t	# OK
+-	vlsseg3e16.v v0, (a0), a1, v0.t	# vd overlap vm
+-	vlsseg3e16.v v4, (a0), a1, v0.t	# OK
+-	vssseg3e16.v v0, (a0), a1, v0.t	# vd overlap vm
+-	vssseg3e16.v v4, (a0), a1, v0.t	# OK
+-	vlsseg4e16.v v0, (a0), a1, v0.t	# vd overlap vm
+-	vlsseg4e16.v v4, (a0), a1, v0.t	# OK
+-	vssseg4e16.v v0, (a0), a1, v0.t	# vd overlap vm
+-	vssseg4e16.v v4, (a0), a1, v0.t	# OK
+-	vlsseg5e16.v v0, (a0), a1, v0.t	# vd overlap vm
+-	vlsseg5e16.v v4, (a0), a1, v0.t	# OK
+-	vssseg5e16.v v0, (a0), a1, v0.t	# vd overlap vm
+-	vssseg5e16.v v4, (a0), a1, v0.t	# OK
+-	vlsseg6e16.v v0, (a0), a1, v0.t	# vd overlap vm
+-	vlsseg6e16.v v4, (a0), a1, v0.t	# OK
+-	vssseg6e16.v v0, (a0), a1, v0.t	# vd overlap vm
+-	vssseg6e16.v v4, (a0), a1, v0.t	# OK
+-	vlsseg7e16.v v0, (a0), a1, v0.t	# vd overlap vm
+-	vlsseg7e16.v v4, (a0), a1, v0.t	# OK
+-	vssseg7e16.v v0, (a0), a1, v0.t	# vd overlap vm
+-	vssseg7e16.v v4, (a0), a1, v0.t	# OK
+-	vlsseg8e16.v v0, (a0), a1, v0.t	# vd overlap vm
+-	vlsseg8e16.v v4, (a0), a1, v0.t	# OK
+-	vssseg8e16.v v0, (a0), a1, v0.t	# vd overlap vm
+-	vssseg8e16.v v4, (a0), a1, v0.t	# OK
+-
+-	vlsseg2e32.v v0, (a0), a1, v0.t	# vd overlap vm
+-	vlsseg2e32.v v4, (a0), a1, v0.t	# OK
+-	vssseg2e32.v v0, (a0), a1, v0.t	# vd overlap vm
+-	vssseg2e32.v v4, (a0), a1, v0.t	# OK
+-	vlsseg3e32.v v0, (a0), a1, v0.t	# vd overlap vm
+-	vlsseg3e32.v v4, (a0), a1, v0.t	# OK
+-	vssseg3e32.v v0, (a0), a1, v0.t	# vd overlap vm
+-	vssseg3e32.v v4, (a0), a1, v0.t	# OK
+-	vlsseg4e32.v v0, (a0), a1, v0.t	# vd overlap vm
+-	vlsseg4e32.v v4, (a0), a1, v0.t	# OK
+-	vssseg4e32.v v0, (a0), a1, v0.t	# vd overlap vm
+-	vssseg4e32.v v4, (a0), a1, v0.t	# OK
+-	vlsseg5e32.v v0, (a0), a1, v0.t	# vd overlap vm
+-	vlsseg5e32.v v4, (a0), a1, v0.t	# OK
+-	vssseg5e32.v v0, (a0), a1, v0.t	# vd overlap vm
+-	vssseg5e32.v v4, (a0), a1, v0.t	# OK
+-	vlsseg6e32.v v0, (a0), a1, v0.t	# vd overlap vm
+-	vlsseg6e32.v v4, (a0), a1, v0.t	# OK
+-	vssseg6e32.v v0, (a0), a1, v0.t	# vd overlap vm
+-	vssseg6e32.v v4, (a0), a1, v0.t	# OK
+-	vlsseg7e32.v v0, (a0), a1, v0.t	# vd overlap vm
+-	vlsseg7e32.v v4, (a0), a1, v0.t	# OK
+-	vssseg7e32.v v0, (a0), a1, v0.t	# vd overlap vm
+-	vssseg7e32.v v4, (a0), a1, v0.t	# OK
+-	vlsseg8e32.v v0, (a0), a1, v0.t	# vd overlap vm
+-	vlsseg8e32.v v4, (a0), a1, v0.t	# OK
+-	vssseg8e32.v v0, (a0), a1, v0.t	# vd overlap vm
+-	vssseg8e32.v v4, (a0), a1, v0.t	# OK
+-
+-	vlsseg2e64.v v0, (a0), a1, v0.t	# vd overlap vm
+-	vlsseg2e64.v v4, (a0), a1, v0.t	# OK
+-	vssseg2e64.v v0, (a0), a1, v0.t	# vd overlap vm
+-	vssseg2e64.v v4, (a0), a1, v0.t	# OK
+-	vlsseg3e64.v v0, (a0), a1, v0.t	# vd overlap vm
+-	vlsseg3e64.v v4, (a0), a1, v0.t	# OK
+-	vssseg3e64.v v0, (a0), a1, v0.t	# vd overlap vm
+-	vssseg3e64.v v4, (a0), a1, v0.t	# OK
+-	vlsseg4e64.v v0, (a0), a1, v0.t	# vd overlap vm
+-	vlsseg4e64.v v4, (a0), a1, v0.t	# OK
+-	vssseg4e64.v v0, (a0), a1, v0.t	# vd overlap vm
+-	vssseg4e64.v v4, (a0), a1, v0.t	# OK
+-	vlsseg5e64.v v0, (a0), a1, v0.t	# vd overlap vm
+-	vlsseg5e64.v v4, (a0), a1, v0.t	# OK
+-	vssseg5e64.v v0, (a0), a1, v0.t	# vd overlap vm
+-	vssseg5e64.v v4, (a0), a1, v0.t	# OK
+-	vlsseg6e64.v v0, (a0), a1, v0.t	# vd overlap vm
+-	vlsseg6e64.v v4, (a0), a1, v0.t	# OK
+-	vssseg6e64.v v0, (a0), a1, v0.t	# vd overlap vm
+-	vssseg6e64.v v4, (a0), a1, v0.t	# OK
+-	vlsseg7e64.v v0, (a0), a1, v0.t	# vd overlap vm
+-	vlsseg7e64.v v4, (a0), a1, v0.t	# OK
+-	vssseg7e64.v v0, (a0), a1, v0.t	# vd overlap vm
+-	vssseg7e64.v v4, (a0), a1, v0.t	# OK
+-	vlsseg8e64.v v0, (a0), a1, v0.t	# vd overlap vm
+-	vlsseg8e64.v v4, (a0), a1, v0.t	# OK
+-	vssseg8e64.v v0, (a0), a1, v0.t	# vd overlap vm
+-	vssseg8e64.v v4, (a0), a1, v0.t	# OK
+-
+-	vlsseg2e128.v v0, (a0), a1, v0.t	# vd overlap vm
+-	vlsseg2e128.v v4, (a0), a1, v0.t	# OK
+-	vssseg2e128.v v0, (a0), a1, v0.t	# vd overlap vm
+-	vssseg2e128.v v4, (a0), a1, v0.t	# OK
+-	vlsseg3e128.v v0, (a0), a1, v0.t	# vd overlap vm
+-	vlsseg3e128.v v4, (a0), a1, v0.t	# OK
+-	vssseg3e128.v v0, (a0), a1, v0.t	# vd overlap vm
+-	vssseg3e128.v v4, (a0), a1, v0.t	# OK
+-	vlsseg4e128.v v0, (a0), a1, v0.t	# vd overlap vm
+-	vlsseg4e128.v v4, (a0), a1, v0.t	# OK
+-	vssseg4e128.v v0, (a0), a1, v0.t	# vd overlap vm
+-	vssseg4e128.v v4, (a0), a1, v0.t	# OK
+-	vlsseg5e128.v v0, (a0), a1, v0.t	# vd overlap vm
+-	vlsseg5e128.v v4, (a0), a1, v0.t	# OK
+-	vssseg5e128.v v0, (a0), a1, v0.t	# vd overlap vm
+-	vssseg5e128.v v4, (a0), a1, v0.t	# OK
+-	vlsseg6e128.v v0, (a0), a1, v0.t	# vd overlap vm
+-	vlsseg6e128.v v4, (a0), a1, v0.t	# OK
+-	vssseg6e128.v v0, (a0), a1, v0.t	# vd overlap vm
+-	vssseg6e128.v v4, (a0), a1, v0.t	# OK
+-	vlsseg7e128.v v0, (a0), a1, v0.t	# vd overlap vm
+-	vlsseg7e128.v v4, (a0), a1, v0.t	# OK
+-	vssseg7e128.v v0, (a0), a1, v0.t	# vd overlap vm
+-	vssseg7e128.v v4, (a0), a1, v0.t	# OK
+-	vlsseg8e128.v v0, (a0), a1, v0.t	# vd overlap vm
+-	vlsseg8e128.v v4, (a0), a1, v0.t	# OK
+-	vssseg8e128.v v0, (a0), a1, v0.t	# vd overlap vm
+-	vssseg8e128.v v4, (a0), a1, v0.t	# OK
+-
+-	vlsseg2e256.v v0, (a0), a1, v0.t	# vd overlap vm
+-	vlsseg2e256.v v4, (a0), a1, v0.t	# OK
+-	vssseg2e256.v v0, (a0), a1, v0.t	# vd overlap vm
+-	vssseg2e256.v v4, (a0), a1, v0.t	# OK
+-	vlsseg3e256.v v0, (a0), a1, v0.t	# vd overlap vm
+-	vlsseg3e256.v v4, (a0), a1, v0.t	# OK
+-	vssseg3e256.v v0, (a0), a1, v0.t	# vd overlap vm
+-	vssseg3e256.v v4, (a0), a1, v0.t	# OK
+-	vlsseg4e256.v v0, (a0), a1, v0.t	# vd overlap vm
+-	vlsseg4e256.v v4, (a0), a1, v0.t	# OK
+-	vssseg4e256.v v0, (a0), a1, v0.t	# vd overlap vm
+-	vssseg4e256.v v4, (a0), a1, v0.t	# OK
+-	vlsseg5e256.v v0, (a0), a1, v0.t	# vd overlap vm
+-	vlsseg5e256.v v4, (a0), a1, v0.t	# OK
+-	vssseg5e256.v v0, (a0), a1, v0.t	# vd overlap vm
+-	vssseg5e256.v v4, (a0), a1, v0.t	# OK
+-	vlsseg6e256.v v0, (a0), a1, v0.t	# vd overlap vm
+-	vlsseg6e256.v v4, (a0), a1, v0.t	# OK
+-	vssseg6e256.v v0, (a0), a1, v0.t	# vd overlap vm
+-	vssseg6e256.v v4, (a0), a1, v0.t	# OK
+-	vlsseg7e256.v v0, (a0), a1, v0.t	# vd overlap vm
+-	vlsseg7e256.v v4, (a0), a1, v0.t	# OK
+-	vssseg7e256.v v0, (a0), a1, v0.t	# vd overlap vm
+-	vssseg7e256.v v4, (a0), a1, v0.t	# OK
+-	vlsseg8e256.v v0, (a0), a1, v0.t	# vd overlap vm
+-	vlsseg8e256.v v4, (a0), a1, v0.t	# OK
+-	vssseg8e256.v v0, (a0), a1, v0.t	# vd overlap vm
+-	vssseg8e256.v v4, (a0), a1, v0.t	# OK
+-
+-	vlsseg2e512.v v0, (a0), a1, v0.t	# vd overlap vm
+-	vlsseg2e512.v v4, (a0), a1, v0.t	# OK
+-	vssseg2e512.v v0, (a0), a1, v0.t	# vd overlap vm
+-	vssseg2e512.v v4, (a0), a1, v0.t	# OK
+-	vlsseg3e512.v v0, (a0), a1, v0.t	# vd overlap vm
+-	vlsseg3e512.v v4, (a0), a1, v0.t	# OK
+-	vssseg3e512.v v0, (a0), a1, v0.t	# vd overlap vm
+-	vssseg3e512.v v4, (a0), a1, v0.t	# OK
+-	vlsseg4e512.v v0, (a0), a1, v0.t	# vd overlap vm
+-	vlsseg4e512.v v4, (a0), a1, v0.t	# OK
+-	vssseg4e512.v v0, (a0), a1, v0.t	# vd overlap vm
+-	vssseg4e512.v v4, (a0), a1, v0.t	# OK
+-	vlsseg5e512.v v0, (a0), a1, v0.t	# vd overlap vm
+-	vlsseg5e512.v v4, (a0), a1, v0.t	# OK
+-	vssseg5e512.v v0, (a0), a1, v0.t	# vd overlap vm
+-	vssseg5e512.v v4, (a0), a1, v0.t	# OK
+-	vlsseg6e512.v v0, (a0), a1, v0.t	# vd overlap vm
+-	vlsseg6e512.v v4, (a0), a1, v0.t	# OK
+-	vssseg6e512.v v0, (a0), a1, v0.t	# vd overlap vm
+-	vssseg6e512.v v4, (a0), a1, v0.t	# OK
+-	vlsseg7e512.v v0, (a0), a1, v0.t	# vd overlap vm
+-	vlsseg7e512.v v4, (a0), a1, v0.t	# OK
+-	vssseg7e512.v v0, (a0), a1, v0.t	# vd overlap vm
+-	vssseg7e512.v v4, (a0), a1, v0.t	# OK
+-	vlsseg8e512.v v0, (a0), a1, v0.t	# vd overlap vm
+-	vlsseg8e512.v v4, (a0), a1, v0.t	# OK
+-	vssseg8e512.v v0, (a0), a1, v0.t	# vd overlap vm
+-	vssseg8e512.v v4, (a0), a1, v0.t	# OK
+-
+-	vlsseg2e1024.v v0, (a0), a1, v0.t	# vd overlap vm
+-	vlsseg2e1024.v v4, (a0), a1, v0.t	# OK
+-	vssseg2e1024.v v0, (a0), a1, v0.t	# vd overlap vm
+-	vssseg2e1024.v v4, (a0), a1, v0.t	# OK
+-	vlsseg3e1024.v v0, (a0), a1, v0.t	# vd overlap vm
+-	vlsseg3e1024.v v4, (a0), a1, v0.t	# OK
+-	vssseg3e1024.v v0, (a0), a1, v0.t	# vd overlap vm
+-	vssseg3e1024.v v4, (a0), a1, v0.t	# OK
+-	vlsseg4e1024.v v0, (a0), a1, v0.t	# vd overlap vm
+-	vlsseg4e1024.v v4, (a0), a1, v0.t	# OK
+-	vssseg4e1024.v v0, (a0), a1, v0.t	# vd overlap vm
+-	vssseg4e1024.v v4, (a0), a1, v0.t	# OK
+-	vlsseg5e1024.v v0, (a0), a1, v0.t	# vd overlap vm
+-	vlsseg5e1024.v v4, (a0), a1, v0.t	# OK
+-	vssseg5e1024.v v0, (a0), a1, v0.t	# vd overlap vm
+-	vssseg5e1024.v v4, (a0), a1, v0.t	# OK
+-	vlsseg6e1024.v v0, (a0), a1, v0.t	# vd overlap vm
+-	vlsseg6e1024.v v4, (a0), a1, v0.t	# OK
+-	vssseg6e1024.v v0, (a0), a1, v0.t	# vd overlap vm
+-	vssseg6e1024.v v4, (a0), a1, v0.t	# OK
+-	vlsseg7e1024.v v0, (a0), a1, v0.t	# vd overlap vm
+-	vlsseg7e1024.v v4, (a0), a1, v0.t	# OK
+-	vssseg7e1024.v v0, (a0), a1, v0.t	# vd overlap vm
+-	vssseg7e1024.v v4, (a0), a1, v0.t	# OK
+-	vlsseg8e1024.v v0, (a0), a1, v0.t	# vd overlap vm
+-	vlsseg8e1024.v v4, (a0), a1, v0.t	# OK
+-	vssseg8e1024.v v0, (a0), a1, v0.t	# vd overlap vm
+-	vssseg8e1024.v v4, (a0), a1, v0.t	# OK
+-
+-# Vector Indexed Segment Loads and Stores
+-
+-	vlxseg2ei8.v v0, (a0), v2		# OK
+-	vlxseg2ei8.v v1, (a0), v2		# OK
+-	vlxseg2ei8.v v2, (a0), v2		# vd overlap vs2
+-	vlxseg2ei8.v v0, (a0), v2, v0.t		# vd overlap vm
+-	vsxseg2ei8.v v0, (a0), v2
+-	vsxseg2ei8.v v1, (a0), v2
+-	vsxseg2ei8.v v2, (a0), v2
+-	vsxseg2ei8.v v0, (a0), v2, v0.t
+-	vlxseg3ei8.v v0, (a0), v2
+-	vlxseg3ei8.v v1, (a0), v2
+-	vlxseg3ei8.v v2, (a0), v2
+-	vlxseg3ei8.v v0, (a0), v2, v0.t
+-	vsxseg3ei8.v v0, (a0), v2
+-	vsxseg3ei8.v v1, (a0), v2
+-	vsxseg3ei8.v v2, (a0), v2
+-	vsxseg3ei8.v v0, (a0), v2, v0.t
+-	vlxseg4ei8.v v0, (a0), v2
+-	vlxseg4ei8.v v1, (a0), v2
+-	vlxseg4ei8.v v2, (a0), v2
+-	vlxseg4ei8.v v0, (a0), v2, v0.t
+-	vsxseg4ei8.v v0, (a0), v2
+-	vsxseg4ei8.v v1, (a0), v2
+-	vsxseg4ei8.v v2, (a0), v2
+-	vsxseg4ei8.v v0, (a0), v2, v0.t
+-	vlxseg5ei8.v v0, (a0), v2
+-	vlxseg5ei8.v v1, (a0), v2
+-	vlxseg5ei8.v v2, (a0), v2
+-	vlxseg5ei8.v v0, (a0), v2, v0.t
+-	vsxseg5ei8.v v0, (a0), v2
+-	vsxseg5ei8.v v1, (a0), v2
+-	vsxseg5ei8.v v2, (a0), v2
+-	vsxseg5ei8.v v0, (a0), v2, v0.t
+-	vlxseg6ei8.v v0, (a0), v2
+-	vlxseg6ei8.v v1, (a0), v2
+-	vlxseg6ei8.v v2, (a0), v2
+-	vlxseg6ei8.v v0, (a0), v2, v0.t
+-	vsxseg6ei8.v v0, (a0), v2
+-	vsxseg6ei8.v v1, (a0), v2
+-	vsxseg6ei8.v v2, (a0), v2
+-	vsxseg6ei8.v v0, (a0), v2, v0.t
+-	vlxseg7ei8.v v0, (a0), v2
+-	vlxseg7ei8.v v1, (a0), v2
+-	vlxseg7ei8.v v2, (a0), v2
+-	vlxseg7ei8.v v0, (a0), v2, v0.t
+-	vsxseg7ei8.v v0, (a0), v2
+-	vsxseg7ei8.v v1, (a0), v2
+-	vsxseg7ei8.v v2, (a0), v2
+-	vsxseg7ei8.v v0, (a0), v2, v0.t
+-	vlxseg8ei8.v v0, (a0), v2
+-	vlxseg8ei8.v v1, (a0), v2
+-	vlxseg8ei8.v v2, (a0), v2
+-	vlxseg8ei8.v v0, (a0), v2, v0.t
+-	vsxseg8ei8.v v0, (a0), v2
+-	vsxseg8ei8.v v1, (a0), v2
+-	vsxseg8ei8.v v2, (a0), v2
+-	vsxseg8ei8.v v0, (a0), v2, v0.t
+-
+-	vlxseg2ei16.v v0, (a0), v2		# OK
+-	vlxseg2ei16.v v1, (a0), v2		# OK
+-	vlxseg2ei16.v v2, (a0), v2		# vd overlap vs2
+-	vlxseg2ei16.v v0, (a0), v2, v0.t	# vd overlap vm
+-	vsxseg2ei16.v v0, (a0), v2
+-	vsxseg2ei16.v v1, (a0), v2
+-	vsxseg2ei16.v v2, (a0), v2
+-	vsxseg2ei16.v v0, (a0), v2, v0.t
+-	vlxseg3ei16.v v0, (a0), v2
+-	vlxseg3ei16.v v1, (a0), v2
+-	vlxseg3ei16.v v2, (a0), v2
+-	vlxseg3ei16.v v0, (a0), v2, v0.t
+-	vsxseg3ei16.v v0, (a0), v2
+-	vsxseg3ei16.v v1, (a0), v2
+-	vsxseg3ei16.v v2, (a0), v2
+-	vsxseg3ei16.v v0, (a0), v2, v0.t
+-	vlxseg4ei16.v v0, (a0), v2
+-	vlxseg4ei16.v v1, (a0), v2
+-	vlxseg4ei16.v v2, (a0), v2
+-	vlxseg4ei16.v v0, (a0), v2, v0.t
+-	vsxseg4ei16.v v0, (a0), v2
+-	vsxseg4ei16.v v1, (a0), v2
+-	vsxseg4ei16.v v2, (a0), v2
+-	vsxseg4ei16.v v0, (a0), v2, v0.t
+-	vlxseg5ei16.v v0, (a0), v2
+-	vlxseg5ei16.v v1, (a0), v2
+-	vlxseg5ei16.v v2, (a0), v2
+-	vlxseg5ei16.v v0, (a0), v2, v0.t
+-	vsxseg5ei16.v v0, (a0), v2
+-	vsxseg5ei16.v v1, (a0), v2
+-	vsxseg5ei16.v v2, (a0), v2
+-	vsxseg5ei16.v v0, (a0), v2, v0.t
+-	vlxseg6ei16.v v0, (a0), v2
+-	vlxseg6ei16.v v1, (a0), v2
+-	vlxseg6ei16.v v2, (a0), v2
+-	vlxseg6ei16.v v0, (a0), v2, v0.t
+-	vsxseg6ei16.v v0, (a0), v2
+-	vsxseg6ei16.v v1, (a0), v2
+-	vsxseg6ei16.v v2, (a0), v2
+-	vsxseg6ei16.v v0, (a0), v2, v0.t
+-	vlxseg7ei16.v v0, (a0), v2
+-	vlxseg7ei16.v v1, (a0), v2
+-	vlxseg7ei16.v v2, (a0), v2
+-	vlxseg7ei16.v v0, (a0), v2, v0.t
+-	vsxseg7ei16.v v0, (a0), v2
+-	vsxseg7ei16.v v1, (a0), v2
+-	vsxseg7ei16.v v2, (a0), v2
+-	vsxseg7ei16.v v0, (a0), v2, v0.t
+-	vlxseg8ei16.v v0, (a0), v2
+-	vlxseg8ei16.v v1, (a0), v2
+-	vlxseg8ei16.v v2, (a0), v2
+-	vlxseg8ei16.v v0, (a0), v2, v0.t
+-	vsxseg8ei16.v v0, (a0), v2
+-	vsxseg8ei16.v v1, (a0), v2
+-	vsxseg8ei16.v v2, (a0), v2
+-	vsxseg8ei16.v v0, (a0), v2, v0.t
+-
+-	vlxseg2ei32.v v0, (a0), v2		# OK
+-	vlxseg2ei32.v v1, (a0), v2		# OK
+-	vlxseg2ei32.v v2, (a0), v2		# vd overlap vs2
+-	vlxseg2ei32.v v0, (a0), v2, v0.t	# vd overlap vm
+-	vsxseg2ei32.v v0, (a0), v2
+-	vsxseg2ei32.v v1, (a0), v2
+-	vsxseg2ei32.v v2, (a0), v2
+-	vsxseg2ei32.v v0, (a0), v2, v0.t
+-	vlxseg3ei32.v v0, (a0), v2
+-	vlxseg3ei32.v v1, (a0), v2
+-	vlxseg3ei32.v v2, (a0), v2
+-	vlxseg3ei32.v v0, (a0), v2, v0.t
+-	vsxseg3ei32.v v0, (a0), v2
+-	vsxseg3ei32.v v1, (a0), v2
+-	vsxseg3ei32.v v2, (a0), v2
+-	vsxseg3ei32.v v0, (a0), v2, v0.t
+-	vlxseg4ei32.v v0, (a0), v2
+-	vlxseg4ei32.v v1, (a0), v2
+-	vlxseg4ei32.v v2, (a0), v2
+-	vlxseg4ei32.v v0, (a0), v2, v0.t
+-	vsxseg4ei32.v v0, (a0), v2
+-	vsxseg4ei32.v v1, (a0), v2
+-	vsxseg4ei32.v v2, (a0), v2
+-	vsxseg4ei32.v v0, (a0), v2, v0.t
+-	vlxseg5ei32.v v0, (a0), v2
+-	vlxseg5ei32.v v1, (a0), v2
+-	vlxseg5ei32.v v2, (a0), v2
+-	vlxseg5ei32.v v0, (a0), v2, v0.t
+-	vsxseg5ei32.v v0, (a0), v2
+-	vsxseg5ei32.v v1, (a0), v2
+-	vsxseg5ei32.v v2, (a0), v2
+-	vsxseg5ei32.v v0, (a0), v2, v0.t
+-	vlxseg6ei32.v v0, (a0), v2
+-	vlxseg6ei32.v v1, (a0), v2
+-	vlxseg6ei32.v v2, (a0), v2
+-	vlxseg6ei32.v v0, (a0), v2, v0.t
+-	vsxseg6ei32.v v0, (a0), v2
+-	vsxseg6ei32.v v1, (a0), v2
+-	vsxseg6ei32.v v2, (a0), v2
+-	vsxseg6ei32.v v0, (a0), v2, v0.t
+-	vlxseg7ei32.v v0, (a0), v2
+-	vlxseg7ei32.v v1, (a0), v2
+-	vlxseg7ei32.v v2, (a0), v2
+-	vlxseg7ei32.v v0, (a0), v2, v0.t
+-	vsxseg7ei32.v v0, (a0), v2
+-	vsxseg7ei32.v v1, (a0), v2
+-	vsxseg7ei32.v v2, (a0), v2
+-	vsxseg7ei32.v v0, (a0), v2, v0.t
+-	vlxseg8ei32.v v0, (a0), v2
+-	vlxseg8ei32.v v1, (a0), v2
+-	vlxseg8ei32.v v2, (a0), v2
+-	vlxseg8ei32.v v0, (a0), v2, v0.t
+-	vsxseg8ei32.v v0, (a0), v2
+-	vsxseg8ei32.v v1, (a0), v2
+-	vsxseg8ei32.v v2, (a0), v2
+-	vsxseg8ei32.v v0, (a0), v2, v0.t
+-
+-	vlxseg2ei64.v v0, (a0), v2		# OK
+-	vlxseg2ei64.v v1, (a0), v2		# OK
+-	vlxseg2ei64.v v2, (a0), v2		# vd overlap vs2
+-	vlxseg2ei64.v v0, (a0), v2, v0.t	# vd overlap vm
+-	vsxseg2ei64.v v0, (a0), v2
+-	vsxseg2ei64.v v1, (a0), v2
+-	vsxseg2ei64.v v2, (a0), v2
+-	vsxseg2ei64.v v0, (a0), v2, v0.t
+-	vlxseg3ei64.v v0, (a0), v2
+-	vlxseg3ei64.v v1, (a0), v2
+-	vlxseg3ei64.v v2, (a0), v2
+-	vlxseg3ei64.v v0, (a0), v2, v0.t
+-	vsxseg3ei64.v v0, (a0), v2
+-	vsxseg3ei64.v v1, (a0), v2
+-	vsxseg3ei64.v v2, (a0), v2
+-	vsxseg3ei64.v v0, (a0), v2, v0.t
+-	vlxseg4ei64.v v0, (a0), v2
+-	vlxseg4ei64.v v1, (a0), v2
+-	vlxseg4ei64.v v2, (a0), v2
+-	vlxseg4ei64.v v0, (a0), v2, v0.t
+-	vsxseg4ei64.v v0, (a0), v2
+-	vsxseg4ei64.v v1, (a0), v2
+-	vsxseg4ei64.v v2, (a0), v2
+-	vsxseg4ei64.v v0, (a0), v2, v0.t
+-	vlxseg5ei64.v v0, (a0), v2
+-	vlxseg5ei64.v v1, (a0), v2
+-	vlxseg5ei64.v v2, (a0), v2
+-	vlxseg5ei64.v v0, (a0), v2, v0.t
+-	vsxseg5ei64.v v0, (a0), v2
+-	vsxseg5ei64.v v1, (a0), v2
+-	vsxseg5ei64.v v2, (a0), v2
+-	vsxseg5ei64.v v0, (a0), v2, v0.t
+-	vlxseg6ei64.v v0, (a0), v2
+-	vlxseg6ei64.v v1, (a0), v2
+-	vlxseg6ei64.v v2, (a0), v2
+-	vlxseg6ei64.v v0, (a0), v2, v0.t
+-	vsxseg6ei64.v v0, (a0), v2
+-	vsxseg6ei64.v v1, (a0), v2
+-	vsxseg6ei64.v v2, (a0), v2
+-	vsxseg6ei64.v v0, (a0), v2, v0.t
+-	vlxseg7ei64.v v0, (a0), v2
+-	vlxseg7ei64.v v1, (a0), v2
+-	vlxseg7ei64.v v2, (a0), v2
+-	vlxseg7ei64.v v0, (a0), v2, v0.t
+-	vsxseg7ei64.v v0, (a0), v2
+-	vsxseg7ei64.v v1, (a0), v2
+-	vsxseg7ei64.v v2, (a0), v2
+-	vsxseg7ei64.v v0, (a0), v2, v0.t
+-	vlxseg8ei64.v v0, (a0), v2
+-	vlxseg8ei64.v v1, (a0), v2
+-	vlxseg8ei64.v v2, (a0), v2
+-	vlxseg8ei64.v v0, (a0), v2, v0.t
+-	vsxseg8ei64.v v0, (a0), v2
+-	vsxseg8ei64.v v1, (a0), v2
+-	vsxseg8ei64.v v2, (a0), v2
+-	vsxseg8ei64.v v0, (a0), v2, v0.t
+-
+-	vlxseg2ei128.v v0, (a0), v2		# OK
+-	vlxseg2ei128.v v1, (a0), v2		# OK
+-	vlxseg2ei128.v v2, (a0), v2		# vd overlap vs2
+-	vlxseg2ei128.v v0, (a0), v2, v0.t	# vd overlap vm
+-	vsxseg2ei128.v v0, (a0), v2
+-	vsxseg2ei128.v v1, (a0), v2
+-	vsxseg2ei128.v v2, (a0), v2
+-	vsxseg2ei128.v v0, (a0), v2, v0.t
+-	vlxseg3ei128.v v0, (a0), v2
+-	vlxseg3ei128.v v1, (a0), v2
+-	vlxseg3ei128.v v2, (a0), v2
+-	vlxseg3ei128.v v0, (a0), v2, v0.t
+-	vsxseg3ei128.v v0, (a0), v2
+-	vsxseg3ei128.v v1, (a0), v2
+-	vsxseg3ei128.v v2, (a0), v2
+-	vsxseg3ei128.v v0, (a0), v2, v0.t
+-	vlxseg4ei128.v v0, (a0), v2
+-	vlxseg4ei128.v v1, (a0), v2
+-	vlxseg4ei128.v v2, (a0), v2
+-	vlxseg4ei128.v v0, (a0), v2, v0.t
+-	vsxseg4ei128.v v0, (a0), v2
+-	vsxseg4ei128.v v1, (a0), v2
+-	vsxseg4ei128.v v2, (a0), v2
+-	vsxseg4ei128.v v0, (a0), v2, v0.t
+-	vlxseg5ei128.v v0, (a0), v2
+-	vlxseg5ei128.v v1, (a0), v2
+-	vlxseg5ei128.v v2, (a0), v2
+-	vlxseg5ei128.v v0, (a0), v2, v0.t
+-	vsxseg5ei128.v v0, (a0), v2
+-	vsxseg5ei128.v v1, (a0), v2
+-	vsxseg5ei128.v v2, (a0), v2
+-	vsxseg5ei128.v v0, (a0), v2, v0.t
+-	vlxseg6ei128.v v0, (a0), v2
+-	vlxseg6ei128.v v1, (a0), v2
+-	vlxseg6ei128.v v2, (a0), v2
+-	vlxseg6ei128.v v0, (a0), v2, v0.t
+-	vsxseg6ei128.v v0, (a0), v2
+-	vsxseg6ei128.v v1, (a0), v2
+-	vsxseg6ei128.v v2, (a0), v2
+-	vsxseg6ei128.v v0, (a0), v2, v0.t
+-	vlxseg7ei128.v v0, (a0), v2
+-	vlxseg7ei128.v v1, (a0), v2
+-	vlxseg7ei128.v v2, (a0), v2
+-	vlxseg7ei128.v v0, (a0), v2, v0.t
+-	vsxseg7ei128.v v0, (a0), v2
+-	vsxseg7ei128.v v1, (a0), v2
+-	vsxseg7ei128.v v2, (a0), v2
+-	vsxseg7ei128.v v0, (a0), v2, v0.t
+-	vlxseg8ei128.v v0, (a0), v2
+-	vlxseg8ei128.v v1, (a0), v2
+-	vlxseg8ei128.v v2, (a0), v2
+-	vlxseg8ei128.v v0, (a0), v2, v0.t
+-	vsxseg8ei128.v v0, (a0), v2
+-	vsxseg8ei128.v v1, (a0), v2
+-	vsxseg8ei128.v v2, (a0), v2
+-	vsxseg8ei128.v v0, (a0), v2, v0.t
+-
+-	vlxseg2ei256.v v0, (a0), v2		# OK
+-	vlxseg2ei256.v v1, (a0), v2		# OK
+-	vlxseg2ei256.v v2, (a0), v2		# vd overlap vs2
+-	vlxseg2ei256.v v0, (a0), v2, v0.t	# vd overlap vm
+-	vsxseg2ei256.v v0, (a0), v2
+-	vsxseg2ei256.v v1, (a0), v2
+-	vsxseg2ei256.v v2, (a0), v2
+-	vsxseg2ei256.v v0, (a0), v2, v0.t
+-	vlxseg3ei256.v v0, (a0), v2
+-	vlxseg3ei256.v v1, (a0), v2
+-	vlxseg3ei256.v v2, (a0), v2
+-	vlxseg3ei256.v v0, (a0), v2, v0.t
+-	vsxseg3ei256.v v0, (a0), v2
+-	vsxseg3ei256.v v1, (a0), v2
+-	vsxseg3ei256.v v2, (a0), v2
+-	vsxseg3ei256.v v0, (a0), v2, v0.t
+-	vlxseg4ei256.v v0, (a0), v2
+-	vlxseg4ei256.v v1, (a0), v2
+-	vlxseg4ei256.v v2, (a0), v2
+-	vlxseg4ei256.v v0, (a0), v2, v0.t
+-	vsxseg4ei256.v v0, (a0), v2
+-	vsxseg4ei256.v v1, (a0), v2
+-	vsxseg4ei256.v v2, (a0), v2
+-	vsxseg4ei256.v v0, (a0), v2, v0.t
+-	vlxseg5ei256.v v0, (a0), v2
+-	vlxseg5ei256.v v1, (a0), v2
+-	vlxseg5ei256.v v2, (a0), v2
+-	vlxseg5ei256.v v0, (a0), v2, v0.t
+-	vsxseg5ei256.v v0, (a0), v2
+-	vsxseg5ei256.v v1, (a0), v2
+-	vsxseg5ei256.v v2, (a0), v2
+-	vsxseg5ei256.v v0, (a0), v2, v0.t
+-	vlxseg6ei256.v v0, (a0), v2
+-	vlxseg6ei256.v v1, (a0), v2
+-	vlxseg6ei256.v v2, (a0), v2
+-	vlxseg6ei256.v v0, (a0), v2, v0.t
+-	vsxseg6ei256.v v0, (a0), v2
+-	vsxseg6ei256.v v1, (a0), v2
+-	vsxseg6ei256.v v2, (a0), v2
+-	vsxseg6ei256.v v0, (a0), v2, v0.t
+-	vlxseg7ei256.v v0, (a0), v2
+-	vlxseg7ei256.v v1, (a0), v2
+-	vlxseg7ei256.v v2, (a0), v2
+-	vlxseg7ei256.v v0, (a0), v2, v0.t
+-	vsxseg7ei256.v v0, (a0), v2
+-	vsxseg7ei256.v v1, (a0), v2
+-	vsxseg7ei256.v v2, (a0), v2
+-	vsxseg7ei256.v v0, (a0), v2, v0.t
+-	vlxseg8ei256.v v0, (a0), v2
+-	vlxseg8ei256.v v1, (a0), v2
+-	vlxseg8ei256.v v2, (a0), v2
+-	vlxseg8ei256.v v0, (a0), v2, v0.t
+-	vsxseg8ei256.v v0, (a0), v2
+-	vsxseg8ei256.v v1, (a0), v2
+-	vsxseg8ei256.v v2, (a0), v2
+-	vsxseg8ei256.v v0, (a0), v2, v0.t
+-
+-	vlxseg2ei512.v v0, (a0), v2		# OK
+-	vlxseg2ei512.v v1, (a0), v2		# OK
+-	vlxseg2ei512.v v2, (a0), v2		# vd overlap vs2
+-	vlxseg2ei512.v v0, (a0), v2, v0.t	# vd overlap vm
+-	vsxseg2ei512.v v0, (a0), v2
+-	vsxseg2ei512.v v1, (a0), v2
+-	vsxseg2ei512.v v2, (a0), v2
+-	vsxseg2ei512.v v0, (a0), v2, v0.t
+-	vlxseg3ei512.v v0, (a0), v2
+-	vlxseg3ei512.v v1, (a0), v2
+-	vlxseg3ei512.v v2, (a0), v2
+-	vlxseg3ei512.v v0, (a0), v2, v0.t
+-	vsxseg3ei512.v v0, (a0), v2
+-	vsxseg3ei512.v v1, (a0), v2
+-	vsxseg3ei512.v v2, (a0), v2
+-	vsxseg3ei512.v v0, (a0), v2, v0.t
+-	vlxseg4ei512.v v0, (a0), v2
+-	vlxseg4ei512.v v1, (a0), v2
+-	vlxseg4ei512.v v2, (a0), v2
+-	vlxseg4ei512.v v0, (a0), v2, v0.t
+-	vsxseg4ei512.v v0, (a0), v2
+-	vsxseg4ei512.v v1, (a0), v2
+-	vsxseg4ei512.v v2, (a0), v2
+-	vsxseg4ei512.v v0, (a0), v2, v0.t
+-	vlxseg5ei512.v v0, (a0), v2
+-	vlxseg5ei512.v v1, (a0), v2
+-	vlxseg5ei512.v v2, (a0), v2
+-	vlxseg5ei512.v v0, (a0), v2, v0.t
+-	vsxseg5ei512.v v0, (a0), v2
+-	vsxseg5ei512.v v1, (a0), v2
+-	vsxseg5ei512.v v2, (a0), v2
+-	vsxseg5ei512.v v0, (a0), v2, v0.t
+-	vlxseg6ei512.v v0, (a0), v2
+-	vlxseg6ei512.v v1, (a0), v2
+-	vlxseg6ei512.v v2, (a0), v2
+-	vlxseg6ei512.v v0, (a0), v2, v0.t
+-	vsxseg6ei512.v v0, (a0), v2
+-	vsxseg6ei512.v v1, (a0), v2
+-	vsxseg6ei512.v v2, (a0), v2
+-	vsxseg6ei512.v v0, (a0), v2, v0.t
+-	vlxseg7ei512.v v0, (a0), v2
+-	vlxseg7ei512.v v1, (a0), v2
+-	vlxseg7ei512.v v2, (a0), v2
+-	vlxseg7ei512.v v0, (a0), v2, v0.t
+-	vsxseg7ei512.v v0, (a0), v2
+-	vsxseg7ei512.v v1, (a0), v2
+-	vsxseg7ei512.v v2, (a0), v2
+-	vsxseg7ei512.v v0, (a0), v2, v0.t
+-	vlxseg8ei512.v v0, (a0), v2
+-	vlxseg8ei512.v v1, (a0), v2
+-	vlxseg8ei512.v v2, (a0), v2
+-	vlxseg8ei512.v v0, (a0), v2, v0.t
+-	vsxseg8ei512.v v0, (a0), v2
+-	vsxseg8ei512.v v1, (a0), v2
+-	vsxseg8ei512.v v2, (a0), v2
+-	vsxseg8ei512.v v0, (a0), v2, v0.t
+-
+-	vlxseg2ei1024.v v0, (a0), v2		# OK
+-	vlxseg2ei1024.v v1, (a0), v2		# OK
+-	vlxseg2ei1024.v v2, (a0), v2		# vd overlap vs2
+-	vlxseg2ei1024.v v0, (a0), v2, v0.t	# vd overlap vm
+-	vsxseg2ei1024.v v0, (a0), v2
+-	vsxseg2ei1024.v v1, (a0), v2
+-	vsxseg2ei1024.v v2, (a0), v2
+-	vsxseg2ei1024.v v0, (a0), v2, v0.t
+-	vlxseg3ei1024.v v0, (a0), v2
+-	vlxseg3ei1024.v v1, (a0), v2
+-	vlxseg3ei1024.v v2, (a0), v2
+-	vlxseg3ei1024.v v0, (a0), v2, v0.t
+-	vsxseg3ei1024.v v0, (a0), v2
+-	vsxseg3ei1024.v v1, (a0), v2
+-	vsxseg3ei1024.v v2, (a0), v2
+-	vsxseg3ei1024.v v0, (a0), v2, v0.t
+-	vlxseg4ei1024.v v0, (a0), v2
+-	vlxseg4ei1024.v v1, (a0), v2
+-	vlxseg4ei1024.v v2, (a0), v2
+-	vlxseg4ei1024.v v0, (a0), v2, v0.t
+-	vsxseg4ei1024.v v0, (a0), v2
+-	vsxseg4ei1024.v v1, (a0), v2
+-	vsxseg4ei1024.v v2, (a0), v2
+-	vsxseg4ei1024.v v0, (a0), v2, v0.t
+-	vlxseg5ei1024.v v0, (a0), v2
+-	vlxseg5ei1024.v v1, (a0), v2
+-	vlxseg5ei1024.v v2, (a0), v2
+-	vlxseg5ei1024.v v0, (a0), v2, v0.t
+-	vsxseg5ei1024.v v0, (a0), v2
+-	vsxseg5ei1024.v v1, (a0), v2
+-	vsxseg5ei1024.v v2, (a0), v2
+-	vsxseg5ei1024.v v0, (a0), v2, v0.t
+-	vlxseg6ei1024.v v0, (a0), v2
+-	vlxseg6ei1024.v v1, (a0), v2
+-	vlxseg6ei1024.v v2, (a0), v2
+-	vlxseg6ei1024.v v0, (a0), v2, v0.t
+-	vsxseg6ei1024.v v0, (a0), v2
+-	vsxseg6ei1024.v v1, (a0), v2
+-	vsxseg6ei1024.v v2, (a0), v2
+-	vsxseg6ei1024.v v0, (a0), v2, v0.t
+-	vlxseg7ei1024.v v0, (a0), v2
+-	vlxseg7ei1024.v v1, (a0), v2
+-	vlxseg7ei1024.v v2, (a0), v2
+-	vlxseg7ei1024.v v0, (a0), v2, v0.t
+-	vsxseg7ei1024.v v0, (a0), v2
+-	vsxseg7ei1024.v v1, (a0), v2
+-	vsxseg7ei1024.v v2, (a0), v2
+-	vsxseg7ei1024.v v0, (a0), v2, v0.t
+-	vlxseg8ei1024.v v0, (a0), v2
+-	vlxseg8ei1024.v v1, (a0), v2
+-	vlxseg8ei1024.v v2, (a0), v2
+-	vlxseg8ei1024.v v0, (a0), v2, v0.t
+-	vsxseg8ei1024.v v0, (a0), v2
+-	vsxseg8ei1024.v v1, (a0), v2
+-	vsxseg8ei1024.v v2, (a0), v2
+-	vsxseg8ei1024.v v0, (a0), v2, v0.t
+diff --git a/gas/testsuite/gas/riscv/vector-insns-fail-02.d b/gas/testsuite/gas/riscv/vector-insns-fail-02.d
+deleted file mode 100644
+index 6780b8553d..0000000000
+--- a/gas/testsuite/gas/riscv/vector-insns-fail-02.d
++++ /dev/null
+@@ -1,3 +0,0 @@
+-#as: -march=rv32ifv_zvqmac -mcheck-constraints
+-#source: vector-insns-fail-02.s
+-#error_output: vector-insns-fail-02.l
+diff --git a/gas/testsuite/gas/riscv/vector-insns-fail-02.l b/gas/testsuite/gas/riscv/vector-insns-fail-02.l
+deleted file mode 100644
+index c015fd75fc..0000000000
+--- a/gas/testsuite/gas/riscv/vector-insns-fail-02.l
++++ /dev/null
+@@ -1,121 +0,0 @@
+-.*: Assembler messages:
+-.*Error: illegal operands `vwaddu.vv v1,v2,v4'
+-.*Error: illegal operands `vwaddu.vv v2,v2,v4'
+-.*Error: illegal operands `vwaddu.vv v2,v3,v4'
+-.*Error: illegal operands `vwaddu.vv v4,v2,v4'
+-.*Error: illegal operands `vwaddu.vv v4,v2,v5'
+-.*Error: illegal operands `vwaddu.vv v0,v2,v4,v0.t'
+-.*Error: illegal operands `vwsubu.vv v1,v2,v4'
+-.*Error: illegal operands `vwsubu.vv v2,v2,v4'
+-.*Error: illegal operands `vwsubu.vv v2,v3,v4'
+-.*Error: illegal operands `vwsubu.vv v4,v2,v4'
+-.*Error: illegal operands `vwsubu.vv v4,v2,v5'
+-.*Error: illegal operands `vwsubu.vv v0,v2,v4,v0.t'
+-.*Error: illegal operands `vwadd.vv v1,v2,v4'
+-.*Error: illegal operands `vwadd.vv v2,v2,v4'
+-.*Error: illegal operands `vwadd.vv v2,v3,v4'
+-.*Error: illegal operands `vwadd.vv v4,v2,v4'
+-.*Error: illegal operands `vwadd.vv v4,v2,v5'
+-.*Error: illegal operands `vwadd.vv v0,v2,v4,v0.t'
+-.*Error: illegal operands `vwsub.vv v1,v2,v4'
+-.*Error: illegal operands `vwsub.vv v2,v2,v4'
+-.*Error: illegal operands `vwsub.vv v2,v3,v4'
+-.*Error: illegal operands `vwsub.vv v4,v2,v4'
+-.*Error: illegal operands `vwsub.vv v4,v2,v5'
+-.*Error: illegal operands `vwsub.vv v0,v2,v4,v0.t'
+-.*Error: illegal operands `vwmul.vv v1,v2,v4'
+-.*Error: illegal operands `vwmul.vv v2,v2,v4'
+-.*Error: illegal operands `vwmul.vv v2,v3,v4'
+-.*Error: illegal operands `vwmul.vv v4,v2,v4'
+-.*Error: illegal operands `vwmul.vv v4,v2,v5'
+-.*Error: illegal operands `vwmul.vv v0,v2,v4,v0.t'
+-.*Error: illegal operands `vwmulu.vv v1,v2,v4'
+-.*Error: illegal operands `vwmulu.vv v2,v2,v4'
+-.*Error: illegal operands `vwmulu.vv v2,v3,v4'
+-.*Error: illegal operands `vwmulu.vv v4,v2,v4'
+-.*Error: illegal operands `vwmulu.vv v4,v2,v5'
+-.*Error: illegal operands `vwmulu.vv v0,v2,v4,v0.t'
+-.*Error: illegal operands `vwmulsu.vv v1,v2,v4'
+-.*Error: illegal operands `vwmulsu.vv v2,v2,v4'
+-.*Error: illegal operands `vwmulsu.vv v2,v3,v4'
+-.*Error: illegal operands `vwmulsu.vv v4,v2,v4'
+-.*Error: illegal operands `vwmulsu.vv v4,v2,v5'
+-.*Error: illegal operands `vwmulsu.vv v0,v2,v4,v0.t'
+-.*Error: illegal operands `vwmaccu.vv v1,v2,v4'
+-.*Error: illegal operands `vwmaccu.vv v2,v2,v4'
+-.*Error: illegal operands `vwmaccu.vv v2,v3,v4'
+-.*Error: illegal operands `vwmaccu.vv v4,v2,v4'
+-.*Error: illegal operands `vwmaccu.vv v4,v2,v5'
+-.*Error: illegal operands `vwmaccu.vv v0,v2,v4,v0.t'
+-.*Error: illegal operands `vwmacc.vv v1,v2,v4'
+-.*Error: illegal operands `vwmacc.vv v2,v2,v4'
+-.*Error: illegal operands `vwmacc.vv v2,v3,v4'
+-.*Error: illegal operands `vwmacc.vv v4,v2,v4'
+-.*Error: illegal operands `vwmacc.vv v4,v2,v5'
+-.*Error: illegal operands `vwmacc.vv v0,v2,v4,v0.t'
+-.*Error: illegal operands `vwmaccsu.vv v1,v2,v4'
+-.*Error: illegal operands `vwmaccsu.vv v2,v2,v4'
+-.*Error: illegal operands `vwmaccsu.vv v2,v3,v4'
+-.*Error: illegal operands `vwmaccsu.vv v4,v2,v4'
+-.*Error: illegal operands `vwmaccsu.vv v4,v2,v5'
+-.*Error: illegal operands `vwmaccsu.vv v0,v2,v4,v0.t'
+-.*Error: illegal operands `vqmaccu.vv v2,v4,v8'
+-.*Error: illegal operands `vqmaccu.vv v4,v4,v8'
+-.*Error: illegal operands `vqmaccu.vv v4,v6,v8'
+-.*Error: illegal operands `vqmaccu.vv v8,v4,v8'
+-.*Error: illegal operands `vqmaccu.vv v8,v4,v10'
+-.*Error: illegal operands `vqmaccu.vv v0,v4,v8,v0.t'
+-.*Error: illegal operands `vqmacc.vv v2,v4,v8'
+-.*Error: illegal operands `vqmacc.vv v4,v4,v8'
+-.*Error: illegal operands `vqmacc.vv v4,v6,v8'
+-.*Error: illegal operands `vqmacc.vv v8,v4,v8'
+-.*Error: illegal operands `vqmacc.vv v8,v4,v10'
+-.*Error: illegal operands `vqmacc.vv v0,v4,v8,v0.t'
+-.*Error: illegal operands `vqmaccsu.vv v2,v4,v8'
+-.*Error: illegal operands `vqmaccsu.vv v4,v4,v8'
+-.*Error: illegal operands `vqmaccsu.vv v4,v6,v8'
+-.*Error: illegal operands `vqmaccsu.vv v8,v4,v8'
+-.*Error: illegal operands `vqmaccsu.vv v8,v4,v10'
+-.*Error: illegal operands `vqmaccsu.vv v0,v4,v8,v0.t'
+-.*Error: illegal operands `vfwadd.vv v1,v2,v4'
+-.*Error: illegal operands `vfwadd.vv v2,v2,v4'
+-.*Error: illegal operands `vfwadd.vv v2,v3,v4'
+-.*Error: illegal operands `vfwadd.vv v4,v2,v4'
+-.*Error: illegal operands `vfwadd.vv v4,v2,v5'
+-.*Error: illegal operands `vfwadd.vv v0,v2,v4,v0.t'
+-.*Error: illegal operands `vfwsub.vv v1,v2,v4'
+-.*Error: illegal operands `vfwsub.vv v2,v2,v4'
+-.*Error: illegal operands `vfwsub.vv v2,v3,v4'
+-.*Error: illegal operands `vfwsub.vv v4,v2,v4'
+-.*Error: illegal operands `vfwsub.vv v4,v2,v5'
+-.*Error: illegal operands `vfwsub.vv v0,v2,v4,v0.t'
+-.*Error: illegal operands `vfwmul.vv v1,v2,v4'
+-.*Error: illegal operands `vfwmul.vv v2,v2,v4'
+-.*Error: illegal operands `vfwmul.vv v2,v3,v4'
+-.*Error: illegal operands `vfwmul.vv v4,v2,v4'
+-.*Error: illegal operands `vfwmul.vv v4,v2,v5'
+-.*Error: illegal operands `vfwmul.vv v0,v2,v4,v0.t'
+-.*Error: illegal operands `vfwmacc.vv v1,v2,v4'
+-.*Error: illegal operands `vfwmacc.vv v2,v2,v4'
+-.*Error: illegal operands `vfwmacc.vv v2,v3,v4'
+-.*Error: illegal operands `vfwmacc.vv v4,v2,v4'
+-.*Error: illegal operands `vfwmacc.vv v4,v2,v5'
+-.*Error: illegal operands `vfwmacc.vv v0,v2,v4,v0.t'
+-.*Error: illegal operands `vfwnmacc.vv v1,v2,v4'
+-.*Error: illegal operands `vfwnmacc.vv v2,v2,v4'
+-.*Error: illegal operands `vfwnmacc.vv v2,v3,v4'
+-.*Error: illegal operands `vfwnmacc.vv v4,v2,v4'
+-.*Error: illegal operands `vfwnmacc.vv v4,v2,v5'
+-.*Error: illegal operands `vfwnmacc.vv v0,v2,v4,v0.t'
+-.*Error: illegal operands `vfwmsac.vv v1,v2,v4'
+-.*Error: illegal operands `vfwmsac.vv v2,v2,v4'
+-.*Error: illegal operands `vfwmsac.vv v2,v3,v4'
+-.*Error: illegal operands `vfwmsac.vv v4,v2,v4'
+-.*Error: illegal operands `vfwmsac.vv v4,v2,v5'
+-.*Error: illegal operands `vfwmsac.vv v0,v2,v4,v0.t'
+-.*Error: illegal operands `vfwnmsac.vv v1,v2,v4'
+-.*Error: illegal operands `vfwnmsac.vv v2,v2,v4'
+-.*Error: illegal operands `vfwnmsac.vv v2,v3,v4'
+-.*Error: illegal operands `vfwnmsac.vv v4,v2,v4'
+-.*Error: illegal operands `vfwnmsac.vv v4,v2,v5'
+-.*Error: illegal operands `vfwnmsac.vv v0,v2,v4,v0.t'
+diff --git a/gas/testsuite/gas/riscv/vector-insns-fail-02.s b/gas/testsuite/gas/riscv/vector-insns-fail-02.s
+deleted file mode 100644
+index bf493c8ddb..0000000000
+--- a/gas/testsuite/gas/riscv/vector-insns-fail-02.s
++++ /dev/null
+@@ -1,162 +0,0 @@
+-# Widening Vector Arithmetic Instructions (VV)
+-# Quad-Widening Vector Arithmetic Instructions (VV)
+-
+-	vwaddu.vv v0, v2, v4		# OK
+-	vwaddu.vv v1, v2, v4		# vd should be multiple of 2
+-	vwaddu.vv v2, v2, v4		# vd overlap vs2
+-	vwaddu.vv v2, v3, v4		# vd overlap vs2
+-	vwaddu.vv v4, v2, v4		# vd overlap vs1
+-	vwaddu.vv v4, v2, v5		# vd overlap vs1
+-	vwaddu.vv v0, v2, v4, v0.t	# vd overlap vm
+-
+-	vwsubu.vv v0, v2, v4		# OK
+-	vwsubu.vv v1, v2, v4		# vd should be multiple of 2
+-	vwsubu.vv v2, v2, v4		# vd overlap vs2
+-	vwsubu.vv v2, v3, v4		# vd overlap vs2
+-	vwsubu.vv v4, v2, v4		# vd overlap vs1
+-	vwsubu.vv v4, v2, v5		# vd overlap vs1
+-	vwsubu.vv v0, v2, v4, v0.t	# vd overlap vm
+-
+-	vwadd.vv v0, v2, v4		# OK
+-	vwadd.vv v1, v2, v4		# vd should be multiple of 2
+-	vwadd.vv v2, v2, v4		# vd overlap vs2
+-	vwadd.vv v2, v3, v4		# vd overlap vs2
+-	vwadd.vv v4, v2, v4		# vd overlap vs1
+-	vwadd.vv v4, v2, v5		# vd overlap vs1
+-	vwadd.vv v0, v2, v4, v0.t	# vd overlap vm
+-
+-	vwsub.vv v0, v2, v4		# OK
+-	vwsub.vv v1, v2, v4		# vd should be multiple of 2
+-	vwsub.vv v2, v2, v4		# vd overlap vs2
+-	vwsub.vv v2, v3, v4		# vd overlap vs2
+-	vwsub.vv v4, v2, v4		# vd overlap vs1
+-	vwsub.vv v4, v2, v5		# vd overlap vs1
+-	vwsub.vv v0, v2, v4, v0.t	# vd overlap vm
+-
+-	vwmul.vv v0, v2, v4		# OK
+-	vwmul.vv v1, v2, v4		# vd should be multiple of 2
+-	vwmul.vv v2, v2, v4		# vd overlap vs2
+-	vwmul.vv v2, v3, v4		# vd overlap vs2
+-	vwmul.vv v4, v2, v4		# vd overlap vs1
+-	vwmul.vv v4, v2, v5		# vd overlap vs1
+-	vwmul.vv v0, v2, v4, v0.t	# vd overlap vm
+-
+-	vwmulu.vv v0, v2, v4		# OK
+-	vwmulu.vv v1, v2, v4		# vd should be multiple of 2
+-	vwmulu.vv v2, v2, v4		# vd overlap vs2
+-	vwmulu.vv v2, v3, v4		# vd overlap vs2
+-	vwmulu.vv v4, v2, v4		# vd overlap vs1
+-	vwmulu.vv v4, v2, v5		# vd overlap vs1
+-	vwmulu.vv v0, v2, v4, v0.t	# vd overlap vm
+-
+-	vwmulsu.vv v0, v2, v4		# OK
+-	vwmulsu.vv v1, v2, v4		# vd should be multiple of 2
+-	vwmulsu.vv v2, v2, v4		# vd overlap vs2
+-	vwmulsu.vv v2, v3, v4		# vd overlap vs2
+-	vwmulsu.vv v4, v2, v4		# vd overlap vs1
+-	vwmulsu.vv v4, v2, v5		# vd overlap vs1
+-	vwmulsu.vv v0, v2, v4, v0.t	# vd overlap vm
+-
+-	vwmaccu.vv v0, v2, v4		# OK
+-	vwmaccu.vv v1, v2, v4		# vd should be multiple of 2
+-	vwmaccu.vv v2, v2, v4		# vd overlap vs1
+-	vwmaccu.vv v2, v3, v4		# vd overlap vs1
+-	vwmaccu.vv v4, v2, v4		# vd overlap vs2
+-	vwmaccu.vv v4, v2, v5		# vd overlap vs2
+-	vwmaccu.vv v0, v2, v4, v0.t	# vd overlap vm
+-
+-	vwmacc.vv v0, v2, v4		# OK
+-	vwmacc.vv v1, v2, v4		# vd should be multiple of 2
+-	vwmacc.vv v2, v2, v4		# vd overlap vs1
+-	vwmacc.vv v2, v3, v4		# vd overlap vs1
+-	vwmacc.vv v4, v2, v4		# vd overlap vs2
+-	vwmacc.vv v4, v2, v5		# vd overlap vs2
+-	vwmacc.vv v0, v2, v4, v0.t	# vd overlap vm
+-
+-	vwmaccsu.vv v0, v2, v4		# OK
+-	vwmaccsu.vv v1, v2, v4		# vd should be multiple of 2
+-	vwmaccsu.vv v2, v2, v4		# vd overlap vs1
+-	vwmaccsu.vv v2, v3, v4		# vd overlap vs1
+-	vwmaccsu.vv v4, v2, v4		# vd overlap vs2
+-	vwmaccsu.vv v4, v2, v5		# vd overlap vs2
+-	vwmaccsu.vv v0, v2, v4, v0.t	# vd overlap vm
+-
+-	vqmaccu.vv v0, v4, v8		# OK
+-	vqmaccu.vv v2, v4, v8		# vd should be multiple of 4
+-	vqmaccu.vv v4, v4, v8		# vd overlap vs1
+-	vqmaccu.vv v4, v6, v8		# vd overlap vs1
+-	vqmaccu.vv v8, v4, v8		# vd overlap vs2
+-	vqmaccu.vv v8, v4, v10		# vd overlap vs2
+-	vqmaccu.vv v0, v4, v8, v0.t	# vd overlap vm
+-
+-	vqmacc.vv v0, v4, v8		# OK
+-	vqmacc.vv v2, v4, v8		# vd should be multiple of 4
+-	vqmacc.vv v4, v4, v8		# vd overlap vs1
+-	vqmacc.vv v4, v6, v8		# vd overlap vs1
+-	vqmacc.vv v8, v4, v8		# vd overlap vs2
+-	vqmacc.vv v8, v4, v10		# vd overlap vs2
+-	vqmacc.vv v0, v4, v8, v0.t	# vd overlap vm
+-
+-	vqmaccsu.vv v0, v4, v8		# OK
+-	vqmaccsu.vv v2, v4, v8		# vd should be multiple of 4
+-	vqmaccsu.vv v4, v4, v8		# vd overlap vs1
+-	vqmaccsu.vv v4, v6, v8		# vd overlap vs1
+-	vqmaccsu.vv v8, v4, v8		# vd overlap vs2
+-	vqmaccsu.vv v8, v4, v10		# vd overlap vs2
+-	vqmaccsu.vv v0, v4, v8, v0.t	# vd overlap vm
+-
+-	vfwadd.vv v0, v2, v4		# OK
+-	vfwadd.vv v1, v2, v4		# vd should be multiple of 2
+-	vfwadd.vv v2, v2, v4		# vd overlap vs2
+-	vfwadd.vv v2, v3, v4		# vd overlap vs2
+-	vfwadd.vv v4, v2, v4		# vd overlap vs1
+-	vfwadd.vv v4, v2, v5		# vd overlap vs1
+-	vfwadd.vv v0, v2, v4, v0.t	# vd overlap vm
+-
+-	vfwsub.vv v0, v2, v4		# OK
+-	vfwsub.vv v1, v2, v4		# vd should be multiple of 2
+-	vfwsub.vv v2, v2, v4		# vd overlap vs2
+-	vfwsub.vv v2, v3, v4		# vd overlap vs2
+-	vfwsub.vv v4, v2, v4		# vd overlap vs1
+-	vfwsub.vv v4, v2, v5		# vd overlap vs1
+-	vfwsub.vv v0, v2, v4, v0.t	# vd overlap vm
+-
+-	vfwmul.vv v0, v2, v4		# OK
+-	vfwmul.vv v1, v2, v4		# vd should be multiple of 2
+-	vfwmul.vv v2, v2, v4		# vd overlap vs2
+-	vfwmul.vv v2, v3, v4		# vd overlap vs2
+-	vfwmul.vv v4, v2, v4		# vd overlap vs1
+-	vfwmul.vv v4, v2, v5		# vd overlap vs1
+-	vfwmul.vv v0, v2, v4, v0.t	# vd overlap vm
+-
+-	vfwmacc.vv v0, v2, v4		# OK
+-	vfwmacc.vv v1, v2, v4		# vd should be multiple of 2
+-	vfwmacc.vv v2, v2, v4		# vd overlap vs1
+-	vfwmacc.vv v2, v3, v4		# vd overlap vs1
+-	vfwmacc.vv v4, v2, v4		# vd overlap vs2
+-	vfwmacc.vv v4, v2, v5		# vd overlap vs2
+-	vfwmacc.vv v0, v2, v4, v0.t	# vd overlap vm
+-
+-	vfwnmacc.vv v0, v2, v4		# OK
+-	vfwnmacc.vv v1, v2, v4		# vd should be multiple of 2
+-	vfwnmacc.vv v2, v2, v4		# vd overlap vs1
+-	vfwnmacc.vv v2, v3, v4		# vd overlap vs1
+-	vfwnmacc.vv v4, v2, v4		# vd overlap vs2
+-	vfwnmacc.vv v4, v2, v5		# vd overlap vs2
+-	vfwnmacc.vv v0, v2, v4, v0.t	# vd overlap vm
+-
+-	vfwmsac.vv v0, v2, v4		# OK
+-	vfwmsac.vv v1, v2, v4		# vd should be multiple of 2
+-	vfwmsac.vv v2, v2, v4		# vd overlap vs1
+-	vfwmsac.vv v2, v3, v4		# vd overlap vs1
+-	vfwmsac.vv v4, v2, v4		# vd overlap vs2
+-	vfwmsac.vv v4, v2, v5		# vd overlap vs2
+-	vfwmsac.vv v0, v2, v4, v0.t	# vd overlap vm
+-
+-	vfwnmsac.vv v0, v2, v4		# OK
+-	vfwnmsac.vv v1, v2, v4		# vd should be multiple of 2
+-	vfwnmsac.vv v2, v2, v4		# vd overlap vs1
+-	vfwnmsac.vv v2, v3, v4		# vd overlap vs1
+-	vfwnmsac.vv v4, v2, v4		# vd overlap vs2
+-	vfwnmsac.vv v4, v2, v5		# vd overlap vs2
+-	vfwnmsac.vv v0, v2, v4, v0.t	# vd overlap vm
+diff --git a/gas/testsuite/gas/riscv/vector-insns-fail-03.d b/gas/testsuite/gas/riscv/vector-insns-fail-03.d
+deleted file mode 100644
+index 1bfe441872..0000000000
+--- a/gas/testsuite/gas/riscv/vector-insns-fail-03.d
++++ /dev/null
+@@ -1,3 +0,0 @@
+-#as: -march=rv32ifv_zvqmac -mcheck-constraints
+-#source: vector-insns-fail-03.s
+-#error_output: vector-insns-fail-03.l
+diff --git a/gas/testsuite/gas/riscv/vector-insns-fail-03.l b/gas/testsuite/gas/riscv/vector-insns-fail-03.l
+deleted file mode 100644
+index 128e22726d..0000000000
+--- a/gas/testsuite/gas/riscv/vector-insns-fail-03.l
++++ /dev/null
+@@ -1,125 +0,0 @@
+-.*: Assembler messages:
+-.*Error: illegal operands `vwcvt.x.x.v v1,v2'
+-.*Error: illegal operands `vwcvt.x.x.v v2,v2'
+-.*Error: illegal operands `vwcvt.x.x.v v2,v3'
+-.*Error: illegal operands `vwcvt.x.x.v v0,v2,v0.t'
+-.*Error: illegal operands `vwcvtu.x.x.v v1,v2'
+-.*Error: illegal operands `vwcvtu.x.x.v v2,v2'
+-.*Error: illegal operands `vwcvtu.x.x.v v2,v3'
+-.*Error: illegal operands `vwcvtu.x.x.v v0,v2,v0.t'
+-.*Error: illegal operands `vwaddu.vx v1,v2,a1'
+-.*Error: illegal operands `vwaddu.vx v2,v2,a1'
+-.*Error: illegal operands `vwaddu.vx v2,v3,a1'
+-.*Error: illegal operands `vwaddu.vx v0,v2,a1,v0.t'
+-.*Error: illegal operands `vwsubu.vx v1,v2,a1'
+-.*Error: illegal operands `vwsubu.vx v2,v2,a1'
+-.*Error: illegal operands `vwsubu.vx v2,v3,a1'
+-.*Error: illegal operands `vwsubu.vx v0,v2,a1,v0.t'
+-.*Error: illegal operands `vwadd.vx v1,v2,a1'
+-.*Error: illegal operands `vwadd.vx v2,v2,a1'
+-.*Error: illegal operands `vwadd.vx v2,v3,a1'
+-.*Error: illegal operands `vwadd.vx v0,v2,a1,v0.t'
+-.*Error: illegal operands `vwsub.vx v1,v2,a1'
+-.*Error: illegal operands `vwsub.vx v2,v2,a1'
+-.*Error: illegal operands `vwsub.vx v2,v3,a1'
+-.*Error: illegal operands `vwsub.vx v0,v2,a1,v0.t'
+-.*Error: illegal operands `vwmul.vx v1,v2,a1'
+-.*Error: illegal operands `vwmul.vx v2,v2,a1'
+-.*Error: illegal operands `vwmul.vx v2,v3,a1'
+-.*Error: illegal operands `vwmul.vx v0,v2,a1,v0.t'
+-.*Error: illegal operands `vwmulu.vx v1,v2,a1'
+-.*Error: illegal operands `vwmulu.vx v2,v2,a1'
+-.*Error: illegal operands `vwmulu.vx v2,v3,a1'
+-.*Error: illegal operands `vwmulu.vx v0,v2,a1,v0.t'
+-.*Error: illegal operands `vwmulsu.vx v1,v2,a1'
+-.*Error: illegal operands `vwmulsu.vx v2,v2,a1'
+-.*Error: illegal operands `vwmulsu.vx v2,v3,a1'
+-.*Error: illegal operands `vwmulsu.vx v0,v2,a1,v0.t'
+-.*Error: illegal operands `vwmaccu.vx v1,a1,v4'
+-.*Error: illegal operands `vwmaccu.vx v4,a1,v4'
+-.*Error: illegal operands `vwmaccu.vx v4,a1,v5'
+-.*Error: illegal operands `vwmaccu.vx v0,a1,v4,v0.t'
+-.*Error: illegal operands `vwmacc.vx v1,a1,v4'
+-.*Error: illegal operands `vwmacc.vx v4,a1,v4'
+-.*Error: illegal operands `vwmacc.vx v4,a1,v5'
+-.*Error: illegal operands `vwmacc.vx v0,a1,v4,v0.t'
+-.*Error: illegal operands `vwmaccsu.vx v1,a1,v4'
+-.*Error: illegal operands `vwmaccsu.vx v4,a1,v4'
+-.*Error: illegal operands `vwmaccsu.vx v4,a1,v5'
+-.*Error: illegal operands `vwmaccsu.vx v0,a1,v4,v0.t'
+-.*Error: illegal operands `vwmaccus.vx v1,a1,v4'
+-.*Error: illegal operands `vwmaccus.vx v4,a1,v4'
+-.*Error: illegal operands `vwmaccus.vx v4,a1,v5'
+-.*Error: illegal operands `vwmaccus.vx v0,a1,v4,v0.t'
+-.*Error: illegal operands `vqmaccu.vx v2,a1,v4'
+-.*Error: illegal operands `vqmaccu.vx v4,a1,v4'
+-.*Error: illegal operands `vqmaccu.vx v4,a1,v6'
+-.*Error: illegal operands `vqmaccu.vx v0,a1,v4,v0.t'
+-.*Error: illegal operands `vqmacc.vx v2,a1,v4'
+-.*Error: illegal operands `vqmacc.vx v4,a1,v4'
+-.*Error: illegal operands `vqmacc.vx v4,a1,v6'
+-.*Error: illegal operands `vqmacc.vx v0,a1,v4,v0.t'
+-.*Error: illegal operands `vqmaccsu.vx v2,a1,v4'
+-.*Error: illegal operands `vqmaccsu.vx v4,a1,v4'
+-.*Error: illegal operands `vqmaccsu.vx v4,a1,v6'
+-.*Error: illegal operands `vqmaccsu.vx v0,a1,v4,v0.t'
+-.*Error: illegal operands `vqmaccus.vx v2,a1,v4'
+-.*Error: illegal operands `vqmaccus.vx v4,a1,v4'
+-.*Error: illegal operands `vqmaccus.vx v4,a1,v6'
+-.*Error: illegal operands `vqmaccus.vx v0,a1,v4,v0.t'
+-.*Error: illegal operands `vfwadd.vf v1,v2,fa1'
+-.*Error: illegal operands `vfwadd.vf v2,v2,fa1'
+-.*Error: illegal operands `vfwadd.vf v2,v3,fa1'
+-.*Error: illegal operands `vfwadd.vf v0,v2,fa1,v0.t'
+-.*Error: illegal operands `vfwsub.vf v1,v2,fa1'
+-.*Error: illegal operands `vfwsub.vf v2,v2,fa1'
+-.*Error: illegal operands `vfwsub.vf v2,v3,fa1'
+-.*Error: illegal operands `vfwsub.vf v0,v2,fa1,v0.t'
+-.*Error: illegal operands `vfwmul.vf v1,v2,fa1'
+-.*Error: illegal operands `vfwmul.vf v2,v2,fa1'
+-.*Error: illegal operands `vfwmul.vf v2,v3,fa1'
+-.*Error: illegal operands `vfwmul.vf v0,v2,fa1,v0.t'
+-.*Error: illegal operands `vfwmacc.vf v1,fa1,v4'
+-.*Error: illegal operands `vfwmacc.vf v4,fa1,v4'
+-.*Error: illegal operands `vfwmacc.vf v4,fa1,v5'
+-.*Error: illegal operands `vfwmacc.vf v0,fa1,v4,v0.t'
+-.*Error: illegal operands `vfwnmacc.vf v1,fa1,v4'
+-.*Error: illegal operands `vfwnmacc.vf v4,fa1,v4'
+-.*Error: illegal operands `vfwnmacc.vf v4,fa1,v5'
+-.*Error: illegal operands `vfwnmacc.vf v0,fa1,v4,v0.t'
+-.*Error: illegal operands `vfwmsac.vf v1,fa1,v4'
+-.*Error: illegal operands `vfwmsac.vf v4,fa1,v4'
+-.*Error: illegal operands `vfwmsac.vf v4,fa1,v5'
+-.*Error: illegal operands `vfwmsac.vf v0,fa1,v4,v0.t'
+-.*Error: illegal operands `vfwnmsac.vf v1,fa1,v4'
+-.*Error: illegal operands `vfwnmsac.vf v4,fa1,v4'
+-.*Error: illegal operands `vfwnmsac.vf v4,fa1,v5'
+-.*Error: illegal operands `vfwnmsac.vf v0,fa1,v4,v0.t'
+-.*Error: illegal operands `vfwcvt.xu.f.v v1,v2'
+-.*Error: illegal operands `vfwcvt.xu.f.v v2,v2'
+-.*Error: illegal operands `vfwcvt.xu.f.v v2,v3'
+-.*Error: illegal operands `vfwcvt.xu.f.v v0,v2,v0.t'
+-.*Error: illegal operands `vfwcvt.x.f.v v1,v2'
+-.*Error: illegal operands `vfwcvt.x.f.v v2,v2'
+-.*Error: illegal operands `vfwcvt.x.f.v v2,v3'
+-.*Error: illegal operands `vfwcvt.x.f.v v0,v2,v0.t'
+-.*Error: illegal operands `vfwcvt.rtz.xu.f.v v1,v2'
+-.*Error: illegal operands `vfwcvt.rtz.xu.f.v v2,v2'
+-.*Error: illegal operands `vfwcvt.rtz.xu.f.v v2,v3'
+-.*Error: illegal operands `vfwcvt.rtz.xu.f.v v0,v2,v0.t'
+-.*Error: illegal operands `vfwcvt.rtz.x.f.v v1,v2'
+-.*Error: illegal operands `vfwcvt.rtz.x.f.v v2,v2'
+-.*Error: illegal operands `vfwcvt.rtz.x.f.v v2,v3'
+-.*Error: illegal operands `vfwcvt.rtz.x.f.v v0,v2,v0.t'
+-.*Error: illegal operands `vfwcvt.f.xu.v v1,v2'
+-.*Error: illegal operands `vfwcvt.f.xu.v v2,v2'
+-.*Error: illegal operands `vfwcvt.f.xu.v v2,v3'
+-.*Error: illegal operands `vfwcvt.f.xu.v v0,v2,v0.t'
+-.*Error: illegal operands `vfwcvt.f.x.v v1,v2'
+-.*Error: illegal operands `vfwcvt.f.x.v v2,v2'
+-.*Error: illegal operands `vfwcvt.f.x.v v2,v3'
+-.*Error: illegal operands `vfwcvt.f.x.v v0,v2,v0.t'
+-.*Error: illegal operands `vfwcvt.f.f.v v1,v2'
+-.*Error: illegal operands `vfwcvt.f.f.v v2,v2'
+-.*Error: illegal operands `vfwcvt.f.f.v v2,v3'
+-.*Error: illegal operands `vfwcvt.f.f.v v0,v2,v0.t'
+diff --git a/gas/testsuite/gas/riscv/vector-insns-fail-03.s b/gas/testsuite/gas/riscv/vector-insns-fail-03.s
+deleted file mode 100644
+index 9450b9ceb0..0000000000
+--- a/gas/testsuite/gas/riscv/vector-insns-fail-03.s
++++ /dev/null
+@@ -1,187 +0,0 @@
+-# Widening Vector Arithmetic Instructions (V[X|F])
+-
+-	vwcvt.x.x.v v0, v2		# OK
+-	vwcvt.x.x.v v1, v2		# vd should be multiple of 2
+-	vwcvt.x.x.v v2, v2		# vd overlap vs2
+-	vwcvt.x.x.v v2, v3		# vd overlap vs2
+-	vwcvt.x.x.v v0, v2, v0.t	# vd overlap vm
+-
+-	vwcvtu.x.x.v v0, v2		# OK
+-	vwcvtu.x.x.v v1, v2		# vd should be multiple of 2
+-	vwcvtu.x.x.v v2, v2		# vd overlap vs2
+-	vwcvtu.x.x.v v2, v3		# vd overlap vs2
+-	vwcvtu.x.x.v v0, v2, v0.t	# vd overlap vm
+-
+-	vwaddu.vx v0, v2, a1		# OK
+-	vwaddu.vx v1, v2, a1		# vd should be multiple of 2
+-	vwaddu.vx v2, v2, a1		# vd overlap vs2
+-	vwaddu.vx v2, v3, a1		# vd overlap vs2
+-	vwaddu.vx v0, v2, a1, v0.t	# vd overlap vm
+-
+-	vwsubu.vx v0, v2, a1		# OK
+-	vwsubu.vx v1, v2, a1		# vd should be multiple of 2
+-	vwsubu.vx v2, v2, a1		# vd overlap vs2
+-	vwsubu.vx v2, v3, a1		# vd overlap vs2
+-	vwsubu.vx v0, v2, a1, v0.t	# vd overlap vm
+-
+-	vwadd.vx v0, v2, a1		# OK
+-	vwadd.vx v1, v2, a1		# vd should be multiple of 2
+-	vwadd.vx v2, v2, a1		# vd overlap vs2
+-	vwadd.vx v2, v3, a1		# vd overlap vs2
+-	vwadd.vx v0, v2, a1, v0.t	# vd overlap vm
+-
+-	vwsub.vx v0, v2, a1		# OK
+-	vwsub.vx v1, v2, a1		# vd should be multiple of 2
+-	vwsub.vx v2, v2, a1		# vd overlap vs2
+-	vwsub.vx v2, v3, a1		# vd overlap vs2
+-	vwsub.vx v0, v2, a1, v0.t	# vd overlap vm
+-
+-	vwmul.vx v0, v2, a1		# OK
+-	vwmul.vx v1, v2, a1		# vd should be multiple of 2
+-	vwmul.vx v2, v2, a1		# vd overlap vs2
+-	vwmul.vx v2, v3, a1		# vd overlap vs2
+-	vwmul.vx v0, v2, a1, v0.t	# vd overlap vm
+-
+-	vwmulu.vx v0, v2, a1		# OK
+-	vwmulu.vx v1, v2, a1		# vd should be multiple of 2
+-	vwmulu.vx v2, v2, a1		# vd overlap vs2
+-	vwmulu.vx v2, v3, a1		# vd overlap vs2
+-	vwmulu.vx v0, v2, a1, v0.t	# vd overlap vm
+-
+-	vwmulsu.vx v0, v2, a1		# OK
+-	vwmulsu.vx v1, v2, a1		# vd should be multiple of 2
+-	vwmulsu.vx v2, v2, a1		# vd overlap vs2
+-	vwmulsu.vx v2, v3, a1		# vd overlap vs2
+-	vwmulsu.vx v0, v2, a1, v0.t	# vd overlap vm
+-
+-	vwmaccu.vx v0, a1, v4		# OK
+-	vwmaccu.vx v1, a1, v4		# vd should be multiple of 2
+-	vwmaccu.vx v4, a1, v4		# vd overlap vs2
+-	vwmaccu.vx v4, a1, v5		# vd overlap vs2
+-	vwmaccu.vx v0, a1, v4, v0.t	# vd overlap vm
+-
+-	vwmacc.vx v0, a1, v4		# OK
+-	vwmacc.vx v1, a1, v4		# vd should be multiple of 2
+-	vwmacc.vx v4, a1, v4		# vd overlap vs2
+-	vwmacc.vx v4, a1, v5		# vd overlap vs2
+-	vwmacc.vx v0, a1, v4, v0.t	# vd overlap vm
+-
+-	vwmaccsu.vx v0, a1, v4		# OK
+-	vwmaccsu.vx v1, a1, v4		# vd should be multiple of 2
+-	vwmaccsu.vx v4, a1, v4		# vd overlap vs2
+-	vwmaccsu.vx v4, a1, v5		# vd overlap vs2
+-	vwmaccsu.vx v0, a1, v4, v0.t	# vd overlap vm
+-
+-	vwmaccus.vx v0, a1, v4		# OK
+-	vwmaccus.vx v1, a1, v4		# vd should be multiple of 2
+-	vwmaccus.vx v4, a1, v4		# vd overlap vs2
+-	vwmaccus.vx v4, a1, v5		# vd overlap vs2
+-	vwmaccus.vx v0, a1, v4, v0.t	# vd overlap vm
+-
+-	vqmaccu.vx v0, a1, v4		# OK
+-	vqmaccu.vx v2, a1, v4		# vd should be multiple of 4
+-	vqmaccu.vx v4, a1, v4		# vd overlap vs2
+-	vqmaccu.vx v4, a1, v6		# vd overlap vs2
+-	vqmaccu.vx v0, a1, v4, v0.t	# vd overlap vm
+-
+-	vqmacc.vx v0, a1, v4		# OK
+-	vqmacc.vx v2, a1, v4		# vd should be multiple of 4
+-	vqmacc.vx v4, a1, v4		# vd overlap vs2
+-	vqmacc.vx v4, a1, v6		# vd overlap vs2
+-	vqmacc.vx v0, a1, v4, v0.t	# vd overlap vm
+-
+-	vqmaccsu.vx v0, a1, v4		# OK
+-	vqmaccsu.vx v2, a1, v4		# vd should be multiple of 4
+-	vqmaccsu.vx v4, a1, v4		# vd overlap vs2
+-	vqmaccsu.vx v4, a1, v6		# vd overlap vs2
+-	vqmaccsu.vx v0, a1, v4, v0.t	# vd overlap vm
+-
+-	vqmaccus.vx v0, a1, v4		# OK
+-	vqmaccus.vx v2, a1, v4		# vd should be multiple of 4
+-	vqmaccus.vx v4, a1, v4		# vd overlap vs2
+-	vqmaccus.vx v4, a1, v6		# vd overlap vs2
+-	vqmaccus.vx v0, a1, v4, v0.t	# vd overlap vm
+-
+-	vfwadd.vf v0, v2, fa1		# OK
+-	vfwadd.vf v1, v2, fa1		# vd should be multiple of 2
+-	vfwadd.vf v2, v2, fa1		# vd overlap vs2
+-	vfwadd.vf v2, v3, fa1		# vd overlap vs2
+-	vfwadd.vf v0, v2, fa1, v0.t	# vd overlap vm
+-
+-	vfwsub.vf v0, v2, fa1		# OK
+-	vfwsub.vf v1, v2, fa1		# vd should be multiple of 2
+-	vfwsub.vf v2, v2, fa1		# vd overlap vs2
+-	vfwsub.vf v2, v3, fa1		# vd overlap vs2
+-	vfwsub.vf v0, v2, fa1, v0.t	# vd overlap vm
+-
+-	vfwmul.vf v0, v2, fa1		# OK
+-	vfwmul.vf v1, v2, fa1		# vd should be multiple of 2
+-	vfwmul.vf v2, v2, fa1		# vd overlap vs2
+-	vfwmul.vf v2, v3, fa1		# vd overlap vs2
+-	vfwmul.vf v0, v2, fa1, v0.t	# vd overlap vm
+-
+-	vfwmacc.vf v0, fa1, v4		# OK
+-	vfwmacc.vf v1, fa1, v4		# vd should be multiple of 2
+-	vfwmacc.vf v4, fa1, v4		# vd overlap vs2
+-	vfwmacc.vf v4, fa1, v5		# vd overlap vs2
+-	vfwmacc.vf v0, fa1, v4, v0.t	# vd overlap vm
+-
+-	vfwnmacc.vf v0, fa1, v4		# OK
+-	vfwnmacc.vf v1, fa1, v4		# vd should be multiple of 2
+-	vfwnmacc.vf v4, fa1, v4		# vd overlap vs2
+-	vfwnmacc.vf v4, fa1, v5		# vd overlap vs2
+-	vfwnmacc.vf v0, fa1, v4, v0.t	# vd overlap vm
+-
+-	vfwmsac.vf v0, fa1, v4		# OK
+-	vfwmsac.vf v1, fa1, v4		# vd should be multiple of 2
+-	vfwmsac.vf v4, fa1, v4		# vd overlap vs2
+-	vfwmsac.vf v4, fa1, v5		# vd overlap vs2
+-	vfwmsac.vf v0, fa1, v4, v0.t	# vd overlap vm
+-
+-	vfwnmsac.vf v0, fa1, v4		# OK
+-	vfwnmsac.vf v1, fa1, v4		# vd should be multiple of 2
+-	vfwnmsac.vf v4, fa1, v4		# vd overlap vs2
+-	vfwnmsac.vf v4, fa1, v5		# vd overlap vs2
+-	vfwnmsac.vf v0, fa1, v4, v0.t	# vd overlap vm
+-
+-	vfwcvt.xu.f.v v0, v2		# OK
+-	vfwcvt.xu.f.v v1, v2		# vd should be multiple of 2
+-	vfwcvt.xu.f.v v2, v2		# vd overlap vs2
+-	vfwcvt.xu.f.v v2, v3		# vd overlap vs2
+-	vfwcvt.xu.f.v v0, v2, v0.t	# vd overlap vm
+-
+-	vfwcvt.x.f.v v0, v2		# OK
+-	vfwcvt.x.f.v v1, v2		# vd should be multiple of 2
+-	vfwcvt.x.f.v v2, v2		# vd overlap vs2
+-	vfwcvt.x.f.v v2, v3		# vd overlap vs2
+-	vfwcvt.x.f.v v0, v2, v0.t	# vd overlap vm
+-
+-	vfwcvt.rtz.xu.f.v v0, v2	# OK
+-	vfwcvt.rtz.xu.f.v v1, v2	# vd should be multiple of 2
+-	vfwcvt.rtz.xu.f.v v2, v2	# vd overlap vs2
+-	vfwcvt.rtz.xu.f.v v2, v3	# vd overlap vs2
+-	vfwcvt.rtz.xu.f.v v0, v2, v0.t	# vd overlap vm
+-
+-	vfwcvt.rtz.x.f.v v0, v2		# OK
+-	vfwcvt.rtz.x.f.v v1, v2		# vd should be multiple of 2
+-	vfwcvt.rtz.x.f.v v2, v2		# vd overlap vs2
+-	vfwcvt.rtz.x.f.v v2, v3		# vd overlap vs2
+-	vfwcvt.rtz.x.f.v v0, v2, v0.t	# vd overlap vm
+-
+-	vfwcvt.f.xu.v v0, v2		# OK
+-	vfwcvt.f.xu.v v1, v2		# vd should be multiple of 2
+-	vfwcvt.f.xu.v v2, v2		# vd overlap vs2
+-	vfwcvt.f.xu.v v2, v3		# vd overlap vs2
+-	vfwcvt.f.xu.v v0, v2, v0.t	# vd overlap vm
+-
+-	vfwcvt.f.x.v v0, v2		# OK
+-	vfwcvt.f.x.v v1, v2		# vd should be multiple of 2
+-	vfwcvt.f.x.v v2, v2		# vd overlap vs2
+-	vfwcvt.f.x.v v2, v3		# vd overlap vs2
+-	vfwcvt.f.x.v v0, v2, v0.t	# vd overlap vm
+-
+-	vfwcvt.f.f.v v0, v2		# OK
+-	vfwcvt.f.f.v v1, v2		# vd should be multiple of 2
+-	vfwcvt.f.f.v v2, v2		# vd overlap vs2
+-	vfwcvt.f.f.v v2, v3		# vd overlap vs2
+-	vfwcvt.f.f.v v0, v2, v0.t	# vd overlap vm
+diff --git a/gas/testsuite/gas/riscv/vector-insns-fail-04.d b/gas/testsuite/gas/riscv/vector-insns-fail-04.d
+deleted file mode 100644
+index d483884544..0000000000
+--- a/gas/testsuite/gas/riscv/vector-insns-fail-04.d
++++ /dev/null
+@@ -1,3 +0,0 @@
+-#as: -march=rv32ifv -mcheck-constraints
+-#source: vector-insns-fail-04.s
+-#error_output: vector-insns-fail-04.l
+diff --git a/gas/testsuite/gas/riscv/vector-insns-fail-04.l b/gas/testsuite/gas/riscv/vector-insns-fail-04.l
+deleted file mode 100644
+index 9a9c76c19d..0000000000
+--- a/gas/testsuite/gas/riscv/vector-insns-fail-04.l
++++ /dev/null
+@@ -1,49 +0,0 @@
+-.*: Assembler messages:
+-.*Error: illegal operands `vwaddu.wv v1,v2,v4'
+-.*Error: illegal operands `vwaddu.wv v2,v3,v4'
+-.*Error: illegal operands `vwaddu.wv v4,v2,v4'
+-.*Error: illegal operands `vwaddu.wv v4,v2,v5'
+-.*Error: illegal operands `vwaddu.wv v0,v2,v4,v0.t'
+-.*Error: illegal operands `vwsubu.wv v1,v2,v4'
+-.*Error: illegal operands `vwsubu.wv v2,v3,v4'
+-.*Error: illegal operands `vwsubu.wv v4,v2,v4'
+-.*Error: illegal operands `vwsubu.wv v4,v2,v5'
+-.*Error: illegal operands `vwsubu.wv v0,v2,v4,v0.t'
+-.*Error: illegal operands `vwadd.wv v1,v2,v4'
+-.*Error: illegal operands `vwadd.wv v2,v3,v4'
+-.*Error: illegal operands `vwadd.wv v4,v2,v4'
+-.*Error: illegal operands `vwadd.wv v4,v2,v5'
+-.*Error: illegal operands `vwadd.wv v0,v2,v4,v0.t'
+-.*Error: illegal operands `vwsub.wv v1,v2,v4'
+-.*Error: illegal operands `vwsub.wv v2,v3,v4'
+-.*Error: illegal operands `vwsub.wv v4,v2,v4'
+-.*Error: illegal operands `vwsub.wv v4,v2,v5'
+-.*Error: illegal operands `vwsub.wv v0,v2,v4,v0.t'
+-.*Error: illegal operands `vfwadd.wv v1,v2,v4'
+-.*Error: illegal operands `vfwadd.wv v2,v3,v4'
+-.*Error: illegal operands `vfwadd.wv v4,v2,v4'
+-.*Error: illegal operands `vfwadd.wv v4,v2,v5'
+-.*Error: illegal operands `vfwadd.wv v0,v2,v4,v0.t'
+-.*Error: illegal operands `vfwsub.wv v1,v2,v4'
+-.*Error: illegal operands `vfwsub.wv v2,v3,v4'
+-.*Error: illegal operands `vfwsub.wv v4,v2,v4'
+-.*Error: illegal operands `vfwsub.wv v4,v2,v5'
+-.*Error: illegal operands `vfwsub.wv v0,v2,v4,v0.t'
+-.*Error: illegal operands `vwaddu.wx v1,v2,a1'
+-.*Error: illegal operands `vwaddu.wx v2,v3,a1'
+-.*Error: illegal operands `vwaddu.wx v0,v2,a1,v0.t'
+-.*Error: illegal operands `vwsubu.wx v1,v2,a1'
+-.*Error: illegal operands `vwsubu.wx v2,v3,a1'
+-.*Error: illegal operands `vwsubu.wx v0,v2,a1,v0.t'
+-.*Error: illegal operands `vwadd.wx v1,v2,a1'
+-.*Error: illegal operands `vwadd.wx v2,v3,a1'
+-.*Error: illegal operands `vwadd.wx v0,v2,a1,v0.t'
+-.*Error: illegal operands `vwsub.wx v1,v2,a1'
+-.*Error: illegal operands `vwsub.wx v2,v3,a1'
+-.*Error: illegal operands `vwsub.wx v0,v2,a1,v0.t'
+-.*Error: illegal operands `vfwadd.wf v1,v2,fa1'
+-.*Error: illegal operands `vfwadd.wf v2,v3,fa1'
+-.*Error: illegal operands `vfwadd.wf v0,v2,fa1,v0.t'
+-.*Error: illegal operands `vfwsub.wf v1,v2,fa1'
+-.*Error: illegal operands `vfwsub.wf v2,v3,fa1'
+-.*Error: illegal operands `vfwsub.wf v0,v2,fa1,v0.t'
+diff --git a/gas/testsuite/gas/riscv/vector-insns-fail-04.s b/gas/testsuite/gas/riscv/vector-insns-fail-04.s
+deleted file mode 100644
+index e1db16d53b..0000000000
+--- a/gas/testsuite/gas/riscv/vector-insns-fail-04.s
++++ /dev/null
+@@ -1,85 +0,0 @@
+-# Widening Vector Arithmetic Instructions (W[V|X])
+-
+-	vwaddu.wv v0, v2, v4		# OK
+-	vwaddu.wv v1, v2, v4		# vd should be multiple of 2
+-	vwaddu.wv v2, v2, v4		# OK
+-	vwaddu.wv v2, v3, v4		# vs2 should be multiple of 2
+-	vwaddu.wv v4, v2, v4		# vd overlap vs1
+-	vwaddu.wv v4, v2, v5		# vd overlap vs1
+-	vwaddu.wv v0, v2, v4, v0.t	# vd overlap vm
+-
+-	vwsubu.wv v0, v2, v4		# OK
+-	vwsubu.wv v1, v2, v4		# vd should be multiple of 2
+-	vwsubu.wv v2, v2, v4		# OK
+-	vwsubu.wv v2, v3, v4		# vs2 should be multiple of 2
+-	vwsubu.wv v4, v2, v4		# vd overlap vs1
+-	vwsubu.wv v4, v2, v5		# vd overlap vs1
+-	vwsubu.wv v0, v2, v4, v0.t	# vd overlap vm
+-
+-	vwadd.wv v0, v2, v4		# OK
+-	vwadd.wv v1, v2, v4		# vd should be multiple of 2
+-	vwadd.wv v2, v2, v4		# OK
+-	vwadd.wv v2, v3, v4		# vs2 should be multiple of 2
+-	vwadd.wv v4, v2, v4		# vd overlap vs1
+-	vwadd.wv v4, v2, v5		# vd overlap vs1
+-	vwadd.wv v0, v2, v4, v0.t	# vd overlap vm
+-
+-	vwsub.wv v0, v2, v4		# OK
+-	vwsub.wv v1, v2, v4		# vd should be multiple of 2
+-	vwsub.wv v2, v2, v4		# OK
+-	vwsub.wv v2, v3, v4		# vs2 should be multiple of 2
+-	vwsub.wv v4, v2, v4		# vd overlap vs1
+-	vwsub.wv v4, v2, v5		# vd overlap vs1
+-	vwsub.wv v0, v2, v4, v0.t	# vd overlap vm
+-
+-	vfwadd.wv v0, v2, v4		# OK
+-	vfwadd.wv v1, v2, v4		# vd should be multiple of 2
+-	vfwadd.wv v2, v2, v4		# OK
+-	vfwadd.wv v2, v3, v4		# vs2 should be multiple of 2
+-	vfwadd.wv v4, v2, v4		# vd overlap vs1
+-	vfwadd.wv v4, v2, v5		# vd overlap vs1
+-	vfwadd.wv v0, v2, v4, v0.t	# vd overlap vm
+-
+-	vfwsub.wv v0, v2, v4		# OK
+-	vfwsub.wv v1, v2, v4		# vd should be multiple of 2
+-	vfwsub.wv v2, v2, v4		# OK
+-	vfwsub.wv v2, v3, v4		# vs2 should be multiple of 2
+-	vfwsub.wv v4, v2, v4		# vd overlap vs1
+-	vfwsub.wv v4, v2, v5		# vd overlap vs1
+-	vfwsub.wv v0, v2, v4, v0.t	# vd overlap vm
+-
+-	vwaddu.wx v0, v2, a1		# OK
+-	vwaddu.wx v1, v2, a1		# vd should be multiple of 2
+-	vwaddu.wx v2, v2, a1		# OK
+-	vwaddu.wx v2, v3, a1		# vs2 should be multiple of 2
+-	vwaddu.wx v0, v2, a1, v0.t	# vd overlap vm
+-
+-	vwsubu.wx v0, v2, a1		# OK
+-	vwsubu.wx v1, v2, a1		# vd should be multiple of 2
+-	vwsubu.wx v2, v2, a1		# OK
+-	vwsubu.wx v2, v3, a1		# vs2 should be multiple of 2
+-	vwsubu.wx v0, v2, a1, v0.t	# vd overlap vm
+-
+-	vwadd.wx v0, v2, a1		# OK
+-	vwadd.wx v1, v2, a1		# vd should be multiple of 2
+-	vwadd.wx v2, v2, a1		# OK
+-	vwadd.wx v2, v3, a1		# vs2 should be multiple of 2
+-	vwadd.wx v0, v2, a1, v0.t	# vd overlap vm
+-
+-	vwsub.wx v0, v2, a1		# OK
+-	vwsub.wx v1, v2, a1		# vd should be multiple of 2
+-	vwsub.wx v2, v2, a1		# OK
+-	vwsub.wx v2, v3, a1		# vs2 should be multiple of 2
+-	vwsub.wx v0, v2, a1, v0.t	# vd overlap vm
+-
+-	vfwadd.wf v0, v2, fa1		# OK
+-	vfwadd.wf v1, v2, fa1		# vd should be multiple of 2
+-	vfwadd.wf v2, v2, fa1		# OK
+-	vfwadd.wf v2, v3, fa1		# vs2 should be multiple of 2
+-	vfwadd.wf v0, v2, fa1, v0.t	# vd overlap vm
+-
+-	vfwsub.wf v0, v2, fa1		# OK
+-	vfwsub.wf v1, v2, fa1		# vd should be multiple of 2
+-	vfwsub.wf v2, v2, fa1		# OK
+-	vfwsub.wf v2, v3, fa1		# vs2 should be multiple of 2
+-	vfwsub.wf v0, v2, fa1, v0.t	# vd overlap vm
+diff --git a/gas/testsuite/gas/riscv/vector-insns-fail-05.d b/gas/testsuite/gas/riscv/vector-insns-fail-05.d
+deleted file mode 100644
+index b13053ab06..0000000000
+--- a/gas/testsuite/gas/riscv/vector-insns-fail-05.d
++++ /dev/null
+@@ -1,3 +0,0 @@
+-#as: -march=rv32ifv -mcheck-constraints
+-#source: vector-insns-fail-05.s
+-#error_output: vector-insns-fail-05.l
+diff --git a/gas/testsuite/gas/riscv/vector-insns-fail-05.s b/gas/testsuite/gas/riscv/vector-insns-fail-05.s
+deleted file mode 100644
+index 6b68680fd9..0000000000
+--- a/gas/testsuite/gas/riscv/vector-insns-fail-05.s
++++ /dev/null
+@@ -1,139 +0,0 @@
+-# Narrowing Vector Arithmetic Instructions
+-
+-	vncvt.x.x.v v0, v2		# OK
+-	vncvt.x.x.v v2, v2		# vd overlap vs2
+-	vncvt.x.x.v v2, v3		# vs2 should be multiple of 2
+-	vncvt.x.x.v v3, v2		# vd overlap vs2
+-	vncvt.x.x.v v0, v2, v0.t	# We can't know the LMUL, so skip the vm checking
+-
+-	vnsrl.wv v0, v2, v4		# OK
+-	vnsrl.wv v2, v2, v4		# vd overlap vs2
+-	vnsrl.wv v2, v3, v4		# vs2 should be multiple of 2
+-	vnsrl.wv v3, v2, v4		# vd overlap vs2
+-	vnsrl.wv v4, v2, v4		# OK
+-	vnsrl.wv v0, v2, v4, v0.t	# We can't know the LMUL, so skip the vm checking
+-
+-	vnsrl.wx v0, v2, a1		# OK
+-	vnsrl.wx v2, v2, a1		# vd overlap vs2
+-	vnsrl.wx v2, v3, a1		# vs2 should be multiple of 2
+-	vnsrl.wx v3, v2, a1		# vd overlap vs2
+-	vnsrl.wx v0, v2, a1, v0.t	# We can't know the LMUL, so skip the vm checking
+-
+-	vnsrl.wi v0, v2, 1		# OK
+-	vnsrl.wi v2, v2, 1		# vd overlap vs2
+-	vnsrl.wi v2, v3, 1		# vs2 should be multiple of 2
+-	vnsrl.wi v3, v2, 1		# vd overlap vs2
+-	vnsrl.wi v0, v2, 1, v0.t	# We can't know the LMUL, so skip the vm checking
+-
+-	vnsra.wv v0, v2, v4		# OK
+-	vnsra.wv v2, v2, v4		# vd overlap vs2
+-	vnsra.wv v2, v3, v4		# vs2 should be multiple of 2
+-	vnsra.wv v3, v2, v4		# vd overlap vs2
+-	vnsra.wv v4, v2, v4		# OK
+-	vnsra.wv v0, v2, v4, v0.t	# We can't know the LMUL, so skip the vm checking
+-
+-	vnsra.wx v0, v2, a1		# OK
+-	vnsra.wx v2, v2, a1		# vd overlap vs2
+-	vnsra.wx v2, v3, a1		# vs2 should be multiple of 2
+-	vnsra.wx v3, v2, a1		# vd overlap vs2
+-	vnsra.wx v0, v2, a1, v0.t	# We can't know the LMUL, so skip the vm checking
+-
+-	vnsra.wi v0, v2, 1		# OK
+-	vnsra.wi v2, v2, 1		# vd overlap vs2
+-	vnsra.wi v2, v3, 1		# vs2 should be multiple of 2
+-	vnsra.wi v3, v2, 1		# vd overlap vs2
+-	vnsra.wi v0, v2, 1, v0.t	# We can't know the LMUL, so skip the vm checking
+-
+-	vnclipu.wv v0, v2, v4		# OK
+-	vnclipu.wv v2, v2, v4		# vd overlap vs2
+-	vnclipu.wv v2, v3, v4		# vs2 should be multiple of 2
+-	vnclipu.wv v3, v2, v4		# vd overlap vs2
+-	vnclipu.wv v4, v2, v4		# OK
+-	vnclipu.wv v0, v2, v4, v0.t	# We can't know the LMUL, so skip the vm checking
+-
+-	vnclipu.wx v0, v2, a1		# OK
+-	vnclipu.wx v2, v2, a1		# vd overlap vs2
+-	vnclipu.wx v2, v3, a1		# vs2 should be multiple of 2
+-	vnclipu.wx v3, v2, a1		# vd overlap vs2
+-	vnclipu.wx v0, v2, a1, v0.t	# We can't know the LMUL, so skip the vm checking
+-
+-	vnclipu.wi v0, v2, 1		# OK
+-	vnclipu.wi v2, v2, 1		# vd overlap vs2
+-	vnclipu.wi v2, v3, 1		# vs2 should be multiple of 2
+-	vnclipu.wi v3, v2, 1		# vd overlap vs2
+-	vnclipu.wi v0, v2, 1, v0.t	# We can't know the LMUL, so skip the vm checking
+-
+-	vnclip.wv v0, v2, v4		# OK
+-	vnclip.wv v2, v2, v4		# vd overlap vs2
+-	vnclip.wv v2, v3, v4		# vs2 should be multiple of 2
+-	vnclip.wv v3, v2, v4		# vd overlap vs2
+-	vnclip.wv v4, v2, v4		# OK
+-	vnclip.wv v0, v2, v4, v0.t	# We can't know the LMUL, so skip the vm checking
+-
+-	vnclip.wx v0, v2, a1		# OK
+-	vnclip.wx v2, v2, a1		# vd overlap vs2
+-	vnclip.wx v2, v3, a1		# vs2 should be multiple of 2
+-	vnclip.wx v3, v2, a1		# vd overlap vs2
+-	vnclip.wx v0, v2, a1, v0.t	# We can't know the LMUL, so skip the vm checking
+-
+-	vnclip.wi v0, v2, 1		# OK
+-	vnclip.wi v2, v2, 1		# vd overlap vs2
+-	vnclip.wi v2, v3, 1		# vs2 should be multiple of 2
+-	vnclip.wi v3, v2, 1		# vd overlap vs2
+-	vnclip.wi v0, v2, 1, v0.t	# We can't know the LMUL, so skip the vm checking
+-
+-	vfncvt.xu.f.w v0, v2		# OK
+-	vfncvt.xu.f.w v2, v2		# vd overlap vs2
+-	vfncvt.xu.f.w v2, v3		# vs2 should be multiple of 2
+-	vfncvt.xu.f.w v3, v2		# vd overlap vs2
+-	vfncvt.xu.f.w v4, v2		# OK
+-	vfncvt.xu.f.w v0, v2, v0.t	# We can't know the LMUL, so skip the vm checking
+-
+-	vfncvt.x.f.w v0, v2		# OK
+-	vfncvt.x.f.w v2, v2		# vd overlap vs2
+-	vfncvt.x.f.w v2, v3		# vs2 should be multiple of 2
+-	vfncvt.x.f.w v3, v2		# vd overlap vs2
+-	vfncvt.x.f.w v4, v2		# OK
+-	vfncvt.x.f.w v0, v2, v0.t	# We can't know the LMUL, so skip the vm checking
+-
+-	vfncvt.rtz.xu.f.w v0, v2	# OK
+-	vfncvt.rtz.xu.f.w v2, v2	# vd overlap vs2
+-	vfncvt.rtz.xu.f.w v2, v3	# vs2 should be multiple of 2
+-	vfncvt.rtz.xu.f.w v3, v2	# vd overlap vs2
+-	vfncvt.rtz.xu.f.w v4, v2	# OK
+-	vfncvt.rtz.xu.f.w v0, v2, v0.t	# We can't know the LMUL, so skip the vm checking
+-
+-	vfncvt.rtz.x.f.w v0, v2		# OK
+-	vfncvt.rtz.x.f.w v2, v2		# vd overlap vs2
+-	vfncvt.rtz.x.f.w v2, v3		# vs2 should be multiple of 2
+-	vfncvt.rtz.x.f.w v3, v2		# vd overlap vs2
+-	vfncvt.rtz.x.f.w v4, v2		# OK
+-	vfncvt.rtz.x.f.w v0, v2, v0.t	# We can't know the LMUL, so skip the vm checking
+-
+-	vfncvt.f.xu.w v0, v2		# OK
+-	vfncvt.f.xu.w v2, v2		# vd overlap vs2
+-	vfncvt.f.xu.w v2, v3		# vs2 should be multiple of 2
+-	vfncvt.f.xu.w v3, v2		# vd overlap vs2
+-	vfncvt.f.xu.w v4, v2		# OK
+-	vfncvt.f.xu.w v0, v2, v0.t	# We can't know the LMUL, so skip the vm checking
+-
+-	vfncvt.f.x.w v0, v2		# OK
+-	vfncvt.f.x.w v2, v2		# vd overlap vs2
+-	vfncvt.f.x.w v2, v3		# vs2 should be multiple of 2
+-	vfncvt.f.x.w v3, v2		# vd overlap vs2
+-	vfncvt.f.x.w v4, v2		# OK
+-	vfncvt.f.x.w v0, v2, v0.t	# We can't know the LMUL, so skip the vm checking
+-
+-	vfncvt.f.f.w v0, v2		# OK
+-	vfncvt.f.f.w v2, v2		# vd overlap vs2
+-	vfncvt.f.f.w v2, v3		# vs2 should be multiple of 2
+-	vfncvt.f.f.w v3, v2		# vd overlap vs2
+-	vfncvt.f.f.w v4, v2		# OK
+-	vfncvt.f.f.w v0, v2, v0.t	# We can't know the LMUL, so skip the vm checking
+-
+-	vfncvt.rod.f.f.w v0, v2		# OK
+-	vfncvt.rod.f.f.w v2, v2		# vd overlap vs2
+-	vfncvt.rod.f.f.w v2, v3		# vs2 should be multiple of 2
+-	vfncvt.rod.f.f.w v3, v2		# vd overlap vs2
+-	vfncvt.rod.f.f.w v4, v2		# OK
+-	vfncvt.rod.f.f.w v0, v2, v0.t	# We can't know the LMUL, so skip the vm checking
+diff --git a/gas/testsuite/gas/riscv/vector-insns-fail-06.d b/gas/testsuite/gas/riscv/vector-insns-fail-06.d
+deleted file mode 100644
+index a2a2220d68..0000000000
+--- a/gas/testsuite/gas/riscv/vector-insns-fail-06.d
++++ /dev/null
+@@ -1,3 +0,0 @@
+-#as: -march=rv32ifv -mcheck-constraints
+-#source: vector-insns-fail-06.s
+-#error_output: vector-insns-fail-06.l
+diff --git a/gas/testsuite/gas/riscv/vector-insns-fail-06.l b/gas/testsuite/gas/riscv/vector-insns-fail-06.l
+deleted file mode 100644
+index 4c540eb272..0000000000
+--- a/gas/testsuite/gas/riscv/vector-insns-fail-06.l
++++ /dev/null
+@@ -1,25 +0,0 @@
+-.*: Assembler messages:
+-.*Error: illegal operands `viota.m v2,v2'
+-.*Error: illegal operands `viota.m v0,v2,v0.t'
+-.*Error: illegal operands `vslideup.vx v2,v2,a4'
+-.*Error: illegal operands `vslideup.vi v2,v2,1'
+-.*Error: illegal operands `vslide1up.vx v2,v2,a4'
+-.*Error: illegal operands `vfslide1up.vf v2,v2,fa4'
+-.*Error: illegal operands `vrgather.vv v2,v2,v4'
+-.*Error: illegal operands `vrgather.vv v4,v2,v4'
+-.*Error: illegal operands `vrgather.vv v0,v2,v4,v0.t'
+-.*Error: illegal operands `vrgather.vx v2,v2,a4'
+-.*Error: illegal operands `vrgather.vx v0,v2,a4,v0.t'
+-.*Error: illegal operands `vrgather.vi v2,v2,1'
+-.*Error: illegal operands `vrgather.vi v0,v2,1,v0.t'
+-.*Error: illegal operands `vrgatherei16.vv v2,v2,v4'
+-.*Error: illegal operands `vrgatherei16.vv v4,v2,v4'
+-.*Error: illegal operands `vrgatherei16.vv v0,v2,v4,v0.t'
+-.*Error: illegal operands `vcompress.vm v2,v2,v4'
+-.*Error: illegal operands `vcompress.vm v4,v2,v4'
+-.*Error: illegal operands `vmv2r.v v1,v2'
+-.*Error: illegal operands `vmv2r.v v2,v3'
+-.*Error: illegal operands `vmv4r.v v2,v4'
+-.*Error: illegal operands `vmv4r.v v4,v7'
+-.*Error: illegal operands `vmv8r.v v6,v8'
+-.*Error: illegal operands `vmv8r.v v8,v12'
+diff --git a/gas/testsuite/gas/riscv/vector-insns-fail-06.s b/gas/testsuite/gas/riscv/vector-insns-fail-06.s
+deleted file mode 100644
+index 3a35aadb49..0000000000
+--- a/gas/testsuite/gas/riscv/vector-insns-fail-06.s
++++ /dev/null
+@@ -1,73 +0,0 @@
+-# Vector Iota Instruction
+-# Vector Slideup Instructions
+-# Vector Slide1up
+-# Vector Register Gather Instruction
+-# Vector Compress Instruction
+-# Vector Load/Store Whole Register Instructions
+-# Whole Vector Register Move
+-
+-	viota.m v0, v2		# OK
+-	viota.m v2, v2		# vd overlap vs2
+-	viota.m v0, v2, v0.t	# vd overlap vm
+-
+-	vslideup.vx v0, v2, a4		# OK
+-	vslideup.vx v1, v2, a4		# OK
+-	vslideup.vx v2, v2, a4		# vd overlap vs2
+-	vslideup.vx v0, v2, a4, v0.t	# vd overlap vm
+-
+-	vslideup.vi v0, v2, 1		# OK
+-	vslideup.vi v1, v2, 1		# OK
+-	vslideup.vi v2, v2, 1		# vd overlap vs2
+-	vslideup.vi v0, v2, 1, v0.t	# vd overlap vm
+-
+-	vslide1up.vx v0, v2, a4		# OK
+-	vslide1up.vx v1, v2, a4		# OK
+-	vslide1up.vx v2, v2, a4		# vd overlap vs2
+-	vslide1up.vx v0, v2, a4, v0.t	# vd overlap vm
+-
+-	vfslide1up.vf v0, v2, fa4	# OK
+-	vfslide1up.vf v1, v2, fa4	# OK
+-	vfslide1up.vf v2, v2, fa4	# vd overlap vs2
+-	vfslide1up.vf v0, v2, fa4, v0.t	# vd overlap vm
+-
+-	vrgather.vv v0, v2, v4		# OK
+-	vrgather.vv v1, v2, v4		# OK
+-	vrgather.vv v2, v2, v4		# vd overlap vs2
+-	vrgather.vv v4, v2, v4		# vd overlap vs1
+-	vrgather.vv v0, v2, v4, v0.t	# vd overlap vm
+-
+-	vrgather.vx v0, v2, a4		# OK
+-	vrgather.vx v1, v2, a4		# OK
+-	vrgather.vx v2, v2, a4		# vd overlap vs2
+-	vrgather.vx v0, v2, a4, v0.t	# vd overlap vm
+-
+-	vrgather.vi v0, v2, 1		# OK
+-	vrgather.vi v1, v2, 1		# OK
+-	vrgather.vi v2, v2, 1		# vd overlap vs2
+-	vrgather.vi v0, v2, 1, v0.t	# vd overlap vm
+-
+-	vrgatherei16.vv v0, v2, v4	# OK
+-	vrgatherei16.vv v1, v2, v4	# OK
+-	vrgatherei16.vv v2, v2, v4	# vd overlap vs2
+-	vrgatherei16.vv v4, v2, v4	# vd overlap vs1
+-	vrgatherei16.vv v0, v2, v4, v0.t# vd overlap vm
+-
+-	vcompress.vm v0, v2, v4		# OK
+-	vcompress.vm v1, v2, v4		# OK
+-	vcompress.vm v2, v2, v4		# vd overlap vs2
+-	vcompress.vm v4, v2, v4		# vd overlap vs1
+-
+-	vmv1r.v v0, v1		# OK
+-	vmv1r.v v2, v3		# OK
+-
+-	vmv2r.v v0, v2		# OK
+-	vmv2r.v v1, v2		# vd must be aligned to 2
+-	vmv2r.v v2, v3		# vs2 must be aligned to 2
+-
+-	vmv4r.v v0, v4		# OK
+-	vmv4r.v v2, v4		# vd must be aligned to 4
+-	vmv4r.v v4, v7		# vs2 must be aligned to 4
+-
+-	vmv8r.v v0, v8		# OK
+-	vmv8r.v v6, v8		# vd must be aligned to 8
+-	vmv8r.v v8, v12		# vs2 must be aligned to 8
+diff --git a/gas/testsuite/gas/riscv/vector-insns-fail-arith-fixp.d b/gas/testsuite/gas/riscv/vector-insns-fail-arith-fixp.d
+new file mode 100644
+index 0000000000..df48418486
+--- /dev/null
++++ b/gas/testsuite/gas/riscv/vector-insns-fail-arith-fixp.d
+@@ -0,0 +1,3 @@
++#as: -march=rv32iv -mcheck-constraints
++#source: vector-insns-fail-arith-fixp.s
++#error_output: vector-insns-fail-arith-fixp.l
+diff --git a/gas/testsuite/gas/riscv/vector-insns-fail-arith-fixp.l b/gas/testsuite/gas/riscv/vector-insns-fail-arith-fixp.l
+new file mode 100644
+index 0000000000..a3c126d8ec
+--- /dev/null
++++ b/gas/testsuite/gas/riscv/vector-insns-fail-arith-fixp.l
+@@ -0,0 +1,27 @@
++.*: Assembler messages:
++.*Error: illegal operands `vsaddu.vv v0,v4,v8,v0.t'
++.*Error: illegal operands `vsaddu.vx v0,v4,a1,v0.t'
++.*Error: illegal operands `vsaddu.vi v0,v4,15,v0.t'
++.*Error: illegal operands `vsadd.vv v0,v4,v8,v0.t'
++.*Error: illegal operands `vsadd.vx v0,v4,a1,v0.t'
++.*Error: illegal operands `vsadd.vi v0,v4,15,v0.t'
++.*Error: illegal operands `vssubu.vv v0,v4,v8,v0.t'
++.*Error: illegal operands `vssubu.vx v0,v4,a1,v0.t'
++.*Error: illegal operands `vssub.vv v0,v4,v8,v0.t'
++.*Error: illegal operands `vssub.vx v0,v4,a1,v0.t'
++.*Error: illegal operands `vaaddu.vv v0,v4,v8,v0.t'
++.*Error: illegal operands `vaaddu.vx v0,v4,a1,v0.t'
++.*Error: illegal operands `vaadd.vv v0,v4,v8,v0.t'
++.*Error: illegal operands `vaadd.vx v0,v4,a1,v0.t'
++.*Error: illegal operands `vasubu.vv v0,v4,v8,v0.t'
++.*Error: illegal operands `vasubu.vx v0,v4,a1,v0.t'
++.*Error: illegal operands `vasub.vv v0,v4,v8,v0.t'
++.*Error: illegal operands `vasub.vx v0,v4,a1,v0.t'
++.*Error: illegal operands `vsmul.vv v0,v4,v8,v0.t'
++.*Error: illegal operands `vsmul.vx v0,v4,a1,v0.t'
++.*Error: illegal operands `vssrl.vv v0,v4,v8,v0.t'
++.*Error: illegal operands `vssrl.vx v0,v4,a1,v0.t'
++.*Error: illegal operands `vssrl.vi v0,v4,31,v0.t'
++.*Error: illegal operands `vssra.vv v0,v4,v8,v0.t'
++.*Error: illegal operands `vssra.vx v0,v4,a1,v0.t'
++.*Error: illegal operands `vssra.vi v0,v4,31,v0.t'
+diff --git a/gas/testsuite/gas/riscv/vector-insns-fail-arith-fixp.s b/gas/testsuite/gas/riscv/vector-insns-fail-arith-fixp.s
+new file mode 100644
+index 0000000000..1fbcb601ea
+--- /dev/null
++++ b/gas/testsuite/gas/riscv/vector-insns-fail-arith-fixp.s
+@@ -0,0 +1,81 @@
++# Vector Single-Width Saturating Add and Subtract
++
++	vsaddu.vv v4, v4, v8		# OK
++	vsaddu.vv v8, v4, v8		# OK
++	vsaddu.vv v0, v4, v8, v0.t	# vd overlap vm
++	vsaddu.vx v4, v4, a1		# OK
++	vsaddu.vx v0, v4, a1, v0.t	# vd overlap vm
++	vsaddu.vi v4, v4, 15		# OK
++	vsaddu.vi v0, v4, 15, v0.t	# vd overlap vm
++
++	vsadd.vv v4, v4, v8
++	vsadd.vv v8, v4, v8
++	vsadd.vv v0, v4, v8, v0.t
++	vsadd.vx v4, v4, a1
++	vsadd.vx v0, v4, a1, v0.t
++	vsadd.vi v4, v4, 15
++	vsadd.vi v0, v4, 15, v0.t
++
++	vssubu.vv v4, v4, v8		# OK
++	vssubu.vv v8, v4, v8		# OK
++	vssubu.vv v0, v4, v8, v0.t	# vd overlap vm
++	vssubu.vx v4, v4, a1		# OK
++	vssubu.vx v0, v4, a1, v0.t	# vd overlap vm
++
++	vssub.vv v4, v4, v8
++	vssub.vv v8, v4, v8
++	vssub.vv v0, v4, v8, v0.t
++	vssub.vx v4, v4, a1
++	vssub.vx v0, v4, a1, v0.t
++
++# Vector Single-Width Averaging Add and Subtract
++
++	vaaddu.vv v4, v4, v8		# OK
++	vaaddu.vv v8, v4, v8		# OK
++	vaaddu.vv v0, v4, v8, v0.t	# vd overlap vm
++	vaaddu.vx v4, v4, a1		# OK
++	vaaddu.vx v0, v4, a1, v0.t	# vd overlap vm
++
++	vaadd.vv v4, v4, v8
++	vaadd.vv v8, v4, v8
++	vaadd.vv v0, v4, v8, v0.t
++	vaadd.vx v4, v4, a1
++	vaadd.vx v0, v4, a1, v0.t
++
++	vasubu.vv v4, v4, v8
++	vasubu.vv v8, v4, v8
++	vasubu.vv v0, v4, v8, v0.t
++	vasubu.vx v4, v4, a1
++	vasubu.vx v0, v4, a1, v0.t
++
++	vasub.vv v4, v4, v8
++	vasub.vv v8, v4, v8
++	vasub.vv v0, v4, v8, v0.t
++	vasub.vx v4, v4, a1
++	vasub.vx v0, v4, a1, v0.t
++
++# Vector Single-Width Fractional Multiply with Rounding and Saturation
++
++	vsmul.vv v4, v4, v8		# OK
++	vsmul.vv v8, v4, v8		# OK
++	vsmul.vv v0, v4, v8, v0.t	# vd overlap vm
++	vsmul.vx v4, v4, a1		# OK
++	vsmul.vx v0, v4, a1, v0.t	# vd overlap vm
++
++# Vector Single-Width Scaling Shift Instructions
++
++	vssrl.vv v4, v4, v8		# OK
++	vssrl.vv v8, v4, v8		# OK
++	vssrl.vv v0, v4, v8, v0.t	# vd overlap vm
++	vssrl.vx v4, v4, a1		# OK
++	vssrl.vx v0, v4, a1, v0.t	# vd overlap vm
++	vssrl.vi v4, v4, 31		# OK
++	vssrl.vi v0, v4, 31, v0.t	# vd overlap vm
++
++	vssra.vv v4, v4, v8
++	vssra.vv v8, v4, v8
++	vssra.vv v0, v4, v8, v0.t
++	vssra.vx v4, v4, a1
++	vssra.vx v0, v4, a1, v0.t
++	vssra.vi v4, v4, 31
++	vssra.vi v0, v4, 31, v0.t
+diff --git a/gas/testsuite/gas/riscv/vector-insns-fail-arith-floatp.d b/gas/testsuite/gas/riscv/vector-insns-fail-arith-floatp.d
+new file mode 100644
+index 0000000000..796f7e2ded
+--- /dev/null
++++ b/gas/testsuite/gas/riscv/vector-insns-fail-arith-floatp.d
+@@ -0,0 +1,3 @@
++#as: -march=rv32ifv -mcheck-constraints
++#source: vector-insns-fail-arith-floatp.s
++#error_output: vector-insns-fail-arith-floatp.l
+diff --git a/gas/testsuite/gas/riscv/vector-insns-fail-arith-floatp.l b/gas/testsuite/gas/riscv/vector-insns-fail-arith-floatp.l
+new file mode 100644
+index 0000000000..0fc28a82d7
+--- /dev/null
++++ b/gas/testsuite/gas/riscv/vector-insns-fail-arith-floatp.l
+@@ -0,0 +1,47 @@
++.*: Assembler messages:
++.*Error: illegal operands `vfadd.vv v0,v4,v8,v0.t'
++.*Error: illegal operands `vfadd.vf v0,v4,fa1,v0.t'
++.*Error: illegal operands `vfsub.vv v0,v4,v8,v0.t'
++.*Error: illegal operands `vfsub.vf v0,v4,fa1,v0.t'
++.*Error: illegal operands `vfrsub.vf v0,v4,fa1,v0.t'
++.*Error: illegal operands `vfmul.vv v0,v4,v8,v0.t'
++.*Error: illegal operands `vfmul.vf v0,v4,fa1,v0.t'
++.*Error: illegal operands `vfdiv.vv v0,v4,v8,v0.t'
++.*Error: illegal operands `vfdiv.vf v0,v4,fa1,v0.t'
++.*Error: illegal operands `vfrdiv.vf v0,v4,fa1,v0.t'
++.*Error: illegal operands `vfmacc.vv v0,v4,v8,v0.t'
++.*Error: illegal operands `vfmacc.vf v0,fa1,v4,v0.t'
++.*Error: illegal operands `vfnmacc.vv v0,v4,v8,v0.t'
++.*Error: illegal operands `vfnmacc.vf v0,fa1,v4,v0.t'
++.*Error: illegal operands `vfmsac.vv v0,v4,v8,v0.t'
++.*Error: illegal operands `vfmsac.vf v0,fa1,v4,v0.t'
++.*Error: illegal operands `vfnmsac.vv v0,v4,v8,v0.t'
++.*Error: illegal operands `vfnmsac.vf v0,fa1,v4,v0.t'
++.*Error: illegal operands `vfmadd.vv v0,v4,v8,v0.t'
++.*Error: illegal operands `vfmadd.vf v0,fa1,v4,v0.t'
++.*Error: illegal operands `vfnmadd.vv v0,v4,v8,v0.t'
++.*Error: illegal operands `vfnmadd.vf v0,fa1,v4,v0.t'
++.*Error: illegal operands `vfmsub.vv v0,v4,v8,v0.t'
++.*Error: illegal operands `vfmsub.vf v0,fa1,v4,v0.t'
++.*Error: illegal operands `vfnmsub.vv v0,v4,v8,v0.t'
++.*Error: illegal operands `vfnmsub.vf v0,fa1,v4,v0.t'
++.*Error: illegal operands `vfsqrt.v v0,v4,v0.t'
++.*Error: illegal operands `vfrece7.v v0,v4,v0.t'
++.*Error: illegal operands `vfrsqrte7.v v0,v4,v0.t'
++.*Error: illegal operands `vfclass.v v0,v4,v0.t'
++.*Error: illegal operands `vfmin.vv v0,v4,v8,v0.t'
++.*Error: illegal operands `vfmin.vf v0,v4,fa1,v0.t'
++.*Error: illegal operands `vfmax.vv v0,v4,v8,v0.t'
++.*Error: illegal operands `vfmax.vf v0,v4,fa1,v0.t'
++.*Error: illegal operands `vfsgnj.vv v0,v4,v8,v0.t'
++.*Error: illegal operands `vfsgnj.vf v0,v4,fa1,v0.t'
++.*Error: illegal operands `vfsgnjn.vv v0,v4,v8,v0.t'
++.*Error: illegal operands `vfsgnjn.vf v0,v4,fa1,v0.t'
++.*Error: illegal operands `vfsgnjx.vv v0,v4,v8,v0.t'
++.*Error: illegal operands `vfsgnjx.vf v0,v4,fa1,v0.t'
++.*Error: illegal operands `vfcvt.xu.f.v v0,v4,v0.t'
++.*Error: illegal operands `vfcvt.x.f.v v0,v4,v0.t'
++.*Error: illegal operands `vfcvt.rtz.xu.f.v v0,v4,v0.t'
++.*Error: illegal operands `vfcvt.rtz.x.f.v v0,v4,v0.t'
++.*Error: illegal operands `vfcvt.f.xu.v v0,v4,v0.t'
++.*Error: illegal operands `vfcvt.f.x.v v0,v4,v0.t'
+diff --git a/gas/testsuite/gas/riscv/vector-insns-fail-arith-floatp.s b/gas/testsuite/gas/riscv/vector-insns-fail-arith-floatp.s
+new file mode 100644
+index 0000000000..3231c35ada
+--- /dev/null
++++ b/gas/testsuite/gas/riscv/vector-insns-fail-arith-floatp.s
+@@ -0,0 +1,152 @@
++# Vector Single-Width Floating-Point Add/Subtract Instructions
++
++	vfadd.vv v4, v4, v8		# OK
++	vfadd.vv v8, v4, v8		# OK
++	vfadd.vv v0, v4, v8, v0.t	# vd overlap vm
++	vfadd.vf v4, v4, fa1		# OK
++	vfadd.vf v0, v4, fa1, v0.t	# vd overlap vm
++
++	vfsub.vv v4, v4, v8
++	vfsub.vv v8, v4, v8
++	vfsub.vv v0, v4, v8, v0.t
++	vfsub.vf v4, v4, fa1
++	vfsub.vf v0, v4, fa1, v0.t
++
++	vfrsub.vf v4, v4, fa1		# OK
++	vfrsub.vf v0, v4, fa1, v0.t	# vd overlap vm
++
++# Vector Single-Width Floating-Point Multiply/Divide Instructions
++
++	vfmul.vv v4, v4, v8		# OK
++	vfmul.vv v8, v4, v8		# OK
++	vfmul.vv v0, v4, v8, v0.t	# vd overlap vm
++	vfmul.vf v4, v4, fa1		# OK
++	vfmul.vf v0, v4, fa1, v0.t	# vd overlap vm
++
++	vfdiv.vv v4, v4, v8
++	vfdiv.vv v8, v4, v8
++	vfdiv.vv v0, v4, v8, v0.t
++	vfdiv.vf v4, v4, fa1
++	vfdiv.vf v0, v4, fa1, v0.t
++
++	vfrdiv.vf v4, v4, fa1		# OK
++	vfrdiv.vf v0, v4, fa1, v0.t	# vd overlap vm
++
++# Vector Single-Width Floating-Point Fused Multiply-Add Instructions
++
++	vfmacc.vv v4, v4, v8		# OK
++	vfmacc.vv v8, v4, v8		# OK
++	vfmacc.vv v0, v4, v8, v0.t	# vd overlap vm
++	vfmacc.vf v4, fa1, v4		# OK
++	vfmacc.vf v0, fa1, v4, v0.t	# vd overlap vm
++
++	vfnmacc.vv v4, v4, v8
++	vfnmacc.vv v8, v4, v8
++	vfnmacc.vv v0, v4, v8, v0.t
++	vfnmacc.vf v4, fa1, v4
++	vfnmacc.vf v0, fa1, v4, v0.t
++
++	vfmsac.vv v4, v4, v8
++	vfmsac.vv v8, v4, v8
++	vfmsac.vv v0, v4, v8, v0.t
++	vfmsac.vf v4, fa1, v4
++	vfmsac.vf v0, fa1, v4, v0.t
++
++	vfnmsac.vv v4, v4, v8
++	vfnmsac.vv v8, v4, v8
++	vfnmsac.vv v0, v4, v8, v0.t
++	vfnmsac.vf v4, fa1, v4
++	vfnmsac.vf v0, fa1, v4, v0.t
++
++	vfmadd.vv v4, v4, v8
++	vfmadd.vv v8, v4, v8
++	vfmadd.vv v0, v4, v8, v0.t
++	vfmadd.vf v4, fa1, v4
++	vfmadd.vf v0, fa1, v4, v0.t
++
++	vfnmadd.vv v4, v4, v8
++	vfnmadd.vv v8, v4, v8
++	vfnmadd.vv v0, v4, v8, v0.t
++	vfnmadd.vf v4, fa1, v4
++	vfnmadd.vf v0, fa1, v4, v0.t
++
++	vfmsub.vv v4, v4, v8
++	vfmsub.vv v8, v4, v8
++	vfmsub.vv v0, v4, v8, v0.t
++	vfmsub.vf v4, fa1, v4
++	vfmsub.vf v0, fa1, v4, v0.t
++
++	vfnmsub.vv v4, v4, v8
++	vfnmsub.vv v8, v4, v8
++	vfnmsub.vv v0, v4, v8, v0.t
++	vfnmsub.vf v4, fa1, v4
++	vfnmsub.vf v0, fa1, v4, v0.t
++
++# Vector Floating-Point Square-Root Instruction
++
++	vfsqrt.v v4, v4			# OK
++	vfsqrt.v v0, v4, v0.t		# vd overlap vm
++
++# Vector Floating-Point Reciprocal Estimate Instruction
++
++	vfrece7.v v4, v4		# OK
++	vfrece7.v v0, v4, v0.t		# vd overlap vm
++
++# Vector Floating-Point Reciprocal Square-Root Estimate Instruction
++
++	vfrsqrte7.v v4, v4		# OK
++	vfrsqrte7.v v0, v4, v0.t	# vd overlap vm
++
++# Vector Floating-Point Classify Instruction
++
++	vfclass.v v4, v4		# OK
++	vfclass.v v0, v4, v0.t		# vd overlap vm
++
++# Vector Floating-Point MIN/MAX Instructions
++
++	vfmin.vv v4, v4, v8		# OK
++	vfmin.vv v8, v4, v8		# OK
++	vfmin.vv v0, v4, v8, v0.t	# vd overlap vm
++	vfmin.vf v4, v4, fa1		# OK
++	vfmin.vf v0, v4, fa1, v0.t	# vd overlap vm
++
++	vfmax.vv v4, v4, v8
++	vfmax.vv v8, v4, v8
++	vfmax.vv v0, v4, v8, v0.t
++	vfmax.vf v4, v4, fa1
++	vfmax.vf v0, v4, fa1, v0.t
++
++# Vector Floating-Point Sign-Injection Instructions
++
++	vfsgnj.vv v4, v4, v8		# OK
++	vfsgnj.vv v8, v4, v8		# OK
++	vfsgnj.vv v0, v4, v8, v0.t	# vd overlap vm
++	vfsgnj.vf v4, v4, fa1		# OK
++	vfsgnj.vf v0, v4, fa1, v0.t	# vd overlap vm
++
++	vfsgnjn.vv v4, v4, v8
++	vfsgnjn.vv v8, v4, v8
++	vfsgnjn.vv v0, v4, v8, v0.t
++	vfsgnjn.vf v4, v4, fa1
++	vfsgnjn.vf v0, v4, fa1, v0.t
++
++	vfsgnjx.vv v4, v4, v8
++	vfsgnjx.vv v8, v4, v8
++	vfsgnjx.vv v0, v4, v8, v0.t
++	vfsgnjx.vf v4, v4, fa1
++	vfsgnjx.vf v0, v4, fa1, v0.t
++
++# Single-Width Floating-Point/Integer Type-Convert Instructions
++
++	vfcvt.xu.f.v v4, v4		# OK
++	vfcvt.xu.f.v v0, v4, v0.t	# vd overlap vm
++	vfcvt.x.f.v v4, v4
++	vfcvt.x.f.v v0, v4, v0.t
++	vfcvt.rtz.xu.f.v v4, v4
++	vfcvt.rtz.xu.f.v v0, v4, v0.t
++	vfcvt.rtz.x.f.v v4, v4
++	vfcvt.rtz.x.f.v v0, v4, v0.t
++	vfcvt.f.xu.v v4, v4
++	vfcvt.f.xu.v v0, v4, v0.t
++	vfcvt.f.x.v v4, v4
++	vfcvt.f.x.v v0, v4, v0.t
+diff --git a/gas/testsuite/gas/riscv/vector-insns-fail-arith-int.d b/gas/testsuite/gas/riscv/vector-insns-fail-arith-int.d
+new file mode 100644
+index 0000000000..55b350bc85
+--- /dev/null
++++ b/gas/testsuite/gas/riscv/vector-insns-fail-arith-int.d
+@@ -0,0 +1,3 @@
++#as: -march=rv32iv -mcheck-constraints
++#source: vector-insns-fail-arith-int.s
++#error_output: vector-insns-fail-arith-int.l
+diff --git a/gas/testsuite/gas/riscv/vector-insns-fail-arith-int.l b/gas/testsuite/gas/riscv/vector-insns-fail-arith-int.l
+new file mode 100644
+index 0000000000..480406af93
+--- /dev/null
++++ b/gas/testsuite/gas/riscv/vector-insns-fail-arith-int.l
+@@ -0,0 +1,70 @@
++.*: Assembler messages:
++.*Error: illegal operands `vadd.vv v0,v4,v8,v0.t'
++.*Error: illegal operands `vadd.vx v0,v4,a1,v0.t'
++.*Error: illegal operands `vadd.vi v0,v4,15,v0.t'
++.*Error: illegal operands `vsub.vv v0,v4,v8,v0.t'
++.*Error: illegal operands `vsub.vx v0,v4,a1,v0.t'
++.*Error: illegal operands `vrsub.vx v0,v4,a1,v0.t'
++.*Error: illegal operands `vrsub.vi v0,v4,15,v0.t'
++.*Error: illegal operands `vzext.vf2 v0,v4,v0.t'
++.*Error: illegal operands `vsext.vf2 v0,v4,v0.t'
++.*Error: illegal operands `vzext.vf4 v0,v4,v0.t'
++.*Error: illegal operands `vsext.vf4 v0,v4,v0.t'
++.*Error: illegal operands `vzext.vf8 v0,v4,v0.t'
++.*Error: illegal operands `vsext.vf8 v0,v4,v0.t'
++.*Error: illegal operands `vadc.vvm v0,v4,v8,v0'
++.*Error: illegal operands `vadc.vxm v0,v4,a1,v0'
++.*Error: illegal operands `vadc.vim v0,v4,15,v0'
++.*Error: illegal operands `vsbc.vvm v0,v4,v8,v0'
++.*Error: illegal operands `vsbc.vxm v0,v4,a1,v0'
++.*Error: illegal operands `vnot.v v0,v4,v0.t'
++.*Error: illegal operands `vand.vv v0,v4,v8,v0.t'
++.*Error: illegal operands `vand.vx v0,v4,a1,v0.t'
++.*Error: illegal operands `vand.vi v0,v4,15,v0.t'
++.*Error: illegal operands `vor.vv v0,v4,v8,v0.t'
++.*Error: illegal operands `vor.vx v0,v4,a1,v0.t'
++.*Error: illegal operands `vor.vi v0,v4,15,v0.t'
++.*Error: illegal operands `vxor.vv v0,v4,v8,v0.t'
++.*Error: illegal operands `vxor.vx v0,v4,a1,v0.t'
++.*Error: illegal operands `vxor.vi v0,v4,15,v0.t'
++.*Error: illegal operands `vsll.vv v0,v4,v8,v0.t'
++.*Error: illegal operands `vsll.vx v0,v4,a1,v0.t'
++.*Error: illegal operands `vsll.vi v0,v4,31,v0.t'
++.*Error: illegal operands `vsrl.vv v0,v4,v8,v0.t'
++.*Error: illegal operands `vsrl.vx v0,v4,a1,v0.t'
++.*Error: illegal operands `vsrl.vi v0,v4,31,v0.t'
++.*Error: illegal operands `vsra.vv v0,v4,v8,v0.t'
++.*Error: illegal operands `vsra.vx v0,v4,a1,v0.t'
++.*Error: illegal operands `vsra.vi v0,v4,31,v0.t'
++.*Error: illegal operands `vminu.vv v0,v4,v8,v0.t'
++.*Error: illegal operands `vminu.vx v0,v4,a1,v0.t'
++.*Error: illegal operands `vmin.vv v0,v4,v8,v0.t'
++.*Error: illegal operands `vmin.vx v0,v4,a1,v0.t'
++.*Error: illegal operands `vmaxu.vv v0,v4,v8,v0.t'
++.*Error: illegal operands `vmaxu.vx v0,v4,a1,v0.t'
++.*Error: illegal operands `vmax.vv v0,v4,v8,v0.t'
++.*Error: illegal operands `vmax.vx v0,v4,a1,v0.t'
++.*Error: illegal operands `vmul.vv v0,v4,v8,v0.t'
++.*Error: illegal operands `vmul.vx v0,v4,a1,v0.t'
++.*Error: illegal operands `vmulh.vv v0,v4,v8,v0.t'
++.*Error: illegal operands `vmulh.vx v0,v4,a1,v0.t'
++.*Error: illegal operands `vmulhu.vv v0,v4,v8,v0.t'
++.*Error: illegal operands `vmulhu.vx v0,v4,a1,v0.t'
++.*Error: illegal operands `vmulhsu.vv v0,v4,v8,v0.t'
++.*Error: illegal operands `vmulhsu.vx v0,v4,a1,v0.t'
++.*Error: illegal operands `vdivu.vv v0,v4,v8,v0.t'
++.*Error: illegal operands `vdivu.vx v0,v4,a1,v0.t'
++.*Error: illegal operands `vdiv.vv v0,v4,v8,v0.t'
++.*Error: illegal operands `vdiv.vx v0,v4,a1,v0.t'
++.*Error: illegal operands `vremu.vv v0,v4,v8,v0.t'
++.*Error: illegal operands `vremu.vx v0,v4,a1,v0.t'
++.*Error: illegal operands `vrem.vv v0,v4,v8,v0.t'
++.*Error: illegal operands `vrem.vx v0,v4,a1,v0.t'
++.*Error: illegal operands `vmacc.vv v0,v4,v8,v0.t'
++.*Error: illegal operands `vmacc.vx v0,a1,v4,v0.t'
++.*Error: illegal operands `vnmsac.vv v0,v4,v8,v0.t'
++.*Error: illegal operands `vnmsac.vx v0,a1,v4,v0.t'
++.*Error: illegal operands `vmadd.vv v0,v4,v8,v0.t'
++.*Error: illegal operands `vmadd.vx v0,a1,v4,v0.t'
++.*Error: illegal operands `vnmsub.vv v0,v4,v8,v0.t'
++.*Error: illegal operands `vnmsub.vx v0,a1,v4,v0.t'
+diff --git a/gas/testsuite/gas/riscv/vector-insns-fail-arith-int.s b/gas/testsuite/gas/riscv/vector-insns-fail-arith-int.s
+new file mode 100644
+index 0000000000..e014125c29
+--- /dev/null
++++ b/gas/testsuite/gas/riscv/vector-insns-fail-arith-int.s
+@@ -0,0 +1,210 @@
++# Vector Single-Width Integer Add and Subtract
++
++	vadd.vv v4, v4, v8		# OK
++	vadd.vv v8, v4, v8		# OK
++	vadd.vv v0, v4, v8, v0.t	# vd overlap vm
++	vadd.vx v4, v4, a1		# OK
++	vadd.vx v0, v4, a1, v0.t	# vd overlap vm
++	vadd.vi v4, v4, 15		# OK
++	vadd.vi v0, v4, 15, v0.t	# vd overlap vm
++
++	vsub.vv v4, v4, v8		# OK
++	vsub.vv v8, v4, v8		# OK
++	vsub.vv v0, v4, v8, v0.t	# vd overlap vm
++	vsub.vx v4, v4, a1		# OK
++	vsub.vx v0, v4, a1, v0.t	# vd overlap vm
++
++	vrsub.vx v4, v4, a1		# OK
++	vrsub.vx v0, v4, a1, v0.t	# vd overlap vm
++	vrsub.vi v4, v4, 15		# OK
++	vrsub.vi v0, v4, 15, v0.t	# vd overlap vm
++
++# Vector Integer Extension
++
++	vzext.vf2 v4, v4		# OK
++	vzext.vf2 v0, v4, v0.t		# vd overlap vm
++	vsext.vf2 v4, v4
++	vsext.vf2 v0, v4, v0.t
++	vzext.vf4 v4, v4
++	vzext.vf4 v0, v4, v0.t
++	vsext.vf4 v4, v4
++	vsext.vf4 v0, v4, v0.t
++	vzext.vf8 v4, v4
++	vzext.vf8 v0, v4, v0.t
++	vsext.vf8 v4, v4
++	vsext.vf8 v0, v4, v0.t
++
++# Vector Integer Add-with-Carry / Subtract-with-Borrow Instructions
++
++	vadc.vvm v4, v4, v8, v0		# OK
++	vadc.vvm v8, v4, v8, v0		# OK
++	vadc.vvm v0, v4, v8, v0		# vd overlap vm
++	vadc.vxm v4, v4, a1, v0		# OK
++	vadc.vxm v0, v4, a1, v0		# vd overlap vm
++	vadc.vim v4, v4, 15, v0		# OK
++	vadc.vim v0, v4, 15, v0		# vd overlap vm
++
++	vsbc.vvm v4, v4, v8, v0		# OK
++	vsbc.vvm v8, v4, v8, v0		# OK
++	vsbc.vvm v0, v4, v8, v0		# vd overlap vm
++	vsbc.vxm v4, v4, a1, v0		# OK
++	vsbc.vxm v0, v4, a1, v0		# vd overlap vm
++
++# Vector Bitwise Logical Instructions
++
++	vnot.v v4, v4			# OK
++	vnot.v v0, v4, v0.t		# vd overlap vm
++
++	vand.vv	v4, v4, v8		# OK
++	vand.vv v8, v4, v8		# OK
++	vand.vv v0, v4, v8, v0.t	# vd overlap vm
++	vand.vx v4, v4, a1		# OK
++	vand.vx v0, v4, a1, v0.t	# vd overlap vm
++	vand.vi v4, v4, 15		# OK
++	vand.vi v0, v4, 15, v0.t	# vd overlap vm
++
++	vor.vv	v4, v4, v8
++	vor.vv v8, v4, v8
++	vor.vv v0, v4, v8, v0.t
++	vor.vx v4, v4, a1
++	vor.vx v0, v4, a1, v0.t
++	vor.vi v4, v4, 15
++	vor.vi v0, v4, 15, v0.t
++
++	vxor.vv	v4, v4, v8
++	vxor.vv v8, v4, v8
++	vxor.vv v0, v4, v8, v0.t
++	vxor.vx v4, v4, a1
++	vxor.vx v0, v4, a1, v0.t
++	vxor.vi v4, v4, 15
++	vxor.vi v0, v4, 15, v0.t
++
++# Vector Single-Width Bit Shift Instructions
++
++	vsll.vv v4, v4, v8		# OK
++	vsll.vv v8, v4, v8		# OK
++	vsll.vv v0, v4, v8, v0.t	# vd overlap vm
++	vsll.vx v4, v4, a1		# OK
++	vsll.vx v0, v4, a1, v0.t	# vd overlap vm
++	vsll.vi v4, v4, 31		# OK
++	vsll.vi v0, v4, 31, v0.t	# vd overlap vm
++
++	vsrl.vv v4, v4, v8
++	vsrl.vv v8, v4, v8
++	vsrl.vv v0, v4, v8, v0.t
++	vsrl.vx v4, v4, a1
++	vsrl.vx v0, v4, a1, v0.t
++	vsrl.vi v4, v4, 31
++	vsrl.vi v0, v4, 31, v0.t
++
++	vsra.vv v4, v4, v8
++	vsra.vv v8, v4, v8
++	vsra.vv v0, v4, v8, v0.t
++	vsra.vx v4, v4, a1
++	vsra.vx v0, v4, a1, v0.t
++	vsra.vi v4, v4, 31
++	vsra.vi v0, v4, 31, v0.t
++
++# Vector Integer Min/Max Instructions
++
++	vminu.vv v4, v4, v8		# OK
++	vminu.vv v8, v4, v8		# OK
++	vminu.vv v0, v4, v8, v0.t	# vd overlap vm
++	vminu.vx v4, v4, a1		# OK
++	vminu.vx v0, v4, a1, v0.t	# vd overlap vm
++
++	vmin.vv v4, v4, v8
++	vmin.vv v8, v4, v8
++	vmin.vv v0, v4, v8, v0.t
++	vmin.vx v4, v4, a1
++	vmin.vx v0, v4, a1, v0.t
++
++	vmaxu.vv v4, v4, v8
++	vmaxu.vv v8, v4, v8
++	vmaxu.vv v0, v4, v8, v0.t
++	vmaxu.vx v4, v4, a1
++	vmaxu.vx v0, v4, a1, v0.t
++
++	vmax.vv v4, v4, v8
++	vmax.vv v8, v4, v8
++	vmax.vv v0, v4, v8, v0.t
++	vmax.vx v4, v4, a1
++	vmax.vx v0, v4, a1, v0.t
++
++# Vector Single-Width Integer Multiply Instructions
++
++	vmul.vv v4, v4, v8		# OK
++	vmul.vv v8, v4, v8		# OK
++	vmul.vv v0, v4, v8, v0.t	# vd overlap vm
++	vmul.vx v4, v4, a1		# OK
++	vmul.vx v0, v4, a1, v0.t	# vd overlap vm
++
++	vmulh.vv v4, v4, v8
++	vmulh.vv v8, v4, v8
++	vmulh.vv v0, v4, v8, v0.t
++	vmulh.vx v4, v4, a1
++	vmulh.vx v0, v4, a1, v0.t
++
++	vmulhu.vv v4, v4, v8
++	vmulhu.vv v8, v4, v8
++	vmulhu.vv v0, v4, v8, v0.t
++	vmulhu.vx v4, v4, a1
++	vmulhu.vx v0, v4, a1, v0.t
++
++	vmulhsu.vv v4, v4, v8
++	vmulhsu.vv v8, v4, v8
++	vmulhsu.vv v0, v4, v8, v0.t
++	vmulhsu.vx v4, v4, a1
++	vmulhsu.vx v0, v4, a1, v0.t
++
++# Vector Integer Divide Instructions
++
++	vdivu.vv v4, v4, v8		# OK
++	vdivu.vv v8, v4, v8		# OK
++	vdivu.vv v0, v4, v8, v0.t	# vd overlap vm
++	vdivu.vx v4, v4, a1		# OK
++	vdivu.vx v0, v4, a1, v0.t	# vd overlap vm
++
++	vdiv.vv v4, v4, v8
++	vdiv.vv v8, v4, v8
++	vdiv.vv v0, v4, v8, v0.t
++	vdiv.vx v4, v4, a1
++	vdiv.vx v0, v4, a1, v0.t
++
++	vremu.vv v4, v4, v8
++	vremu.vv v8, v4, v8
++	vremu.vv v0, v4, v8, v0.t
++	vremu.vx v4, v4, a1
++	vremu.vx v0, v4, a1, v0.t
++
++	vrem.vv v4, v4, v8
++	vrem.vv v8, v4, v8
++	vrem.vv v0, v4, v8, v0.t
++	vrem.vx v4, v4, a1
++	vrem.vx v0, v4, a1, v0.t
++
++# Vector Single-Width Integer Multiply-Add Instructions
++
++	vmacc.vv v4, v4, v8		# OK
++	vmacc.vv v8, v4, v8		# OK
++	vmacc.vv v0, v4, v8, v0.t	# vd overlap vm
++	vmacc.vx v4, a1, v4		# OK
++	vmacc.vx v0, a1, v4, v0.t	# vd overlap vm
++
++	vnmsac.vv v4, v4, v8
++	vnmsac.vv v8, v4, v8
++	vnmsac.vv v0, v4, v8, v0.t
++	vnmsac.vx v4, a1, v4
++	vnmsac.vx v0, a1, v4, v0.t
++
++	vmadd.vv v4, v4, v8
++	vmadd.vv v8, v4, v8
++	vmadd.vv v0, v4, v8, v0.t
++	vmadd.vx v4, a1, v4
++	vmadd.vx v0, a1, v4, v0.t
++
++	vnmsub.vv v4, v4, v8
++	vnmsub.vv v8, v4, v8
++	vnmsub.vv v0, v4, v8, v0.t
++	vnmsub.vx v4, a1, v4
++	vnmsub.vx v0, a1, v4, v0.t
+diff --git a/gas/testsuite/gas/riscv/vector-insns-fail-arith-narrow.d b/gas/testsuite/gas/riscv/vector-insns-fail-arith-narrow.d
+new file mode 100644
+index 0000000000..e7a4d4e00c
+--- /dev/null
++++ b/gas/testsuite/gas/riscv/vector-insns-fail-arith-narrow.d
+@@ -0,0 +1,3 @@
++#as: -march=rv32ifv -mcheck-constraints
++#source: vector-insns-fail-arith-narrow.s
++#error_output: vector-insns-fail-arith-narrow.l
+diff --git a/gas/testsuite/gas/riscv/vector-insns-fail-05.l b/gas/testsuite/gas/riscv/vector-insns-fail-arith-narrow.l
+similarity index 59%
+rename from gas/testsuite/gas/riscv/vector-insns-fail-05.l
+rename to gas/testsuite/gas/riscv/vector-insns-fail-arith-narrow.l
+index f2bee3d1e0..dcbe3b3f79 100644
+--- a/gas/testsuite/gas/riscv/vector-insns-fail-05.l
++++ b/gas/testsuite/gas/riscv/vector-insns-fail-arith-narrow.l
+@@ -2,63 +2,84 @@
+ .*Error: illegal operands `vncvt.x.x.v v2,v2'
+ .*Error: illegal operands `vncvt.x.x.v v2,v3'
+ .*Error: illegal operands `vncvt.x.x.v v3,v2'
++.*Error: illegal operands `vncvt.x.x.v v0,v2,v0.t'
+ .*Error: illegal operands `vnsrl.wv v2,v2,v4'
+ .*Error: illegal operands `vnsrl.wv v2,v3,v4'
+ .*Error: illegal operands `vnsrl.wv v3,v2,v4'
++.*Error: illegal operands `vnsrl.wv v0,v2,v4,v0.t'
+ .*Error: illegal operands `vnsrl.wx v2,v2,a1'
+ .*Error: illegal operands `vnsrl.wx v2,v3,a1'
+ .*Error: illegal operands `vnsrl.wx v3,v2,a1'
+-.*Error: illegal operands `vnsrl.wi v2,v2,1'
+-.*Error: illegal operands `vnsrl.wi v2,v3,1'
+-.*Error: illegal operands `vnsrl.wi v3,v2,1'
++.*Error: illegal operands `vnsrl.wx v0,v2,a1,v0.t'
++.*Error: illegal operands `vnsrl.wi v2,v2,31'
++.*Error: illegal operands `vnsrl.wi v2,v3,31'
++.*Error: illegal operands `vnsrl.wi v3,v2,31'
++.*Error: illegal operands `vnsrl.wi v0,v2,31,v0.t'
+ .*Error: illegal operands `vnsra.wv v2,v2,v4'
+ .*Error: illegal operands `vnsra.wv v2,v3,v4'
+ .*Error: illegal operands `vnsra.wv v3,v2,v4'
++.*Error: illegal operands `vnsra.wv v0,v2,v4,v0.t'
+ .*Error: illegal operands `vnsra.wx v2,v2,a1'
+ .*Error: illegal operands `vnsra.wx v2,v3,a1'
+ .*Error: illegal operands `vnsra.wx v3,v2,a1'
+-.*Error: illegal operands `vnsra.wi v2,v2,1'
+-.*Error: illegal operands `vnsra.wi v2,v3,1'
+-.*Error: illegal operands `vnsra.wi v3,v2,1'
++.*Error: illegal operands `vnsra.wx v0,v2,a1,v0.t'
++.*Error: illegal operands `vnsra.wi v2,v2,31'
++.*Error: illegal operands `vnsra.wi v2,v3,31'
++.*Error: illegal operands `vnsra.wi v3,v2,31'
++.*Error: illegal operands `vnsra.wi v0,v2,31,v0.t'
+ .*Error: illegal operands `vnclipu.wv v2,v2,v4'
+ .*Error: illegal operands `vnclipu.wv v2,v3,v4'
+ .*Error: illegal operands `vnclipu.wv v3,v2,v4'
++.*Error: illegal operands `vnclipu.wv v0,v2,v4,v0.t'
+ .*Error: illegal operands `vnclipu.wx v2,v2,a1'
+ .*Error: illegal operands `vnclipu.wx v2,v3,a1'
+ .*Error: illegal operands `vnclipu.wx v3,v2,a1'
+-.*Error: illegal operands `vnclipu.wi v2,v2,1'
+-.*Error: illegal operands `vnclipu.wi v2,v3,1'
+-.*Error: illegal operands `vnclipu.wi v3,v2,1'
++.*Error: illegal operands `vnclipu.wx v0,v2,a1,v0.t'
++.*Error: illegal operands `vnclipu.wi v2,v2,31'
++.*Error: illegal operands `vnclipu.wi v2,v3,31'
++.*Error: illegal operands `vnclipu.wi v3,v2,31'
++.*Error: illegal operands `vnclipu.wi v0,v2,31,v0.t'
+ .*Error: illegal operands `vnclip.wv v2,v2,v4'
+ .*Error: illegal operands `vnclip.wv v2,v3,v4'
+ .*Error: illegal operands `vnclip.wv v3,v2,v4'
++.*Error: illegal operands `vnclip.wv v0,v2,v4,v0.t'
+ .*Error: illegal operands `vnclip.wx v2,v2,a1'
+ .*Error: illegal operands `vnclip.wx v2,v3,a1'
+ .*Error: illegal operands `vnclip.wx v3,v2,a1'
+-.*Error: illegal operands `vnclip.wi v2,v2,1'
+-.*Error: illegal operands `vnclip.wi v2,v3,1'
+-.*Error: illegal operands `vnclip.wi v3,v2,1'
++.*Error: illegal operands `vnclip.wx v0,v2,a1,v0.t'
++.*Error: illegal operands `vnclip.wi v2,v2,31'
++.*Error: illegal operands `vnclip.wi v2,v3,31'
++.*Error: illegal operands `vnclip.wi v3,v2,31'
++.*Error: illegal operands `vnclip.wi v0,v2,31,v0.t'
+ .*Error: illegal operands `vfncvt.xu.f.w v2,v2'
+ .*Error: illegal operands `vfncvt.xu.f.w v2,v3'
+ .*Error: illegal operands `vfncvt.xu.f.w v3,v2'
++.*Error: illegal operands `vfncvt.xu.f.w v0,v2,v0.t'
+ .*Error: illegal operands `vfncvt.x.f.w v2,v2'
+ .*Error: illegal operands `vfncvt.x.f.w v2,v3'
+ .*Error: illegal operands `vfncvt.x.f.w v3,v2'
++.*Error: illegal operands `vfncvt.x.f.w v0,v2,v0.t'
+ .*Error: illegal operands `vfncvt.rtz.xu.f.w v2,v2'
+ .*Error: illegal operands `vfncvt.rtz.xu.f.w v2,v3'
+ .*Error: illegal operands `vfncvt.rtz.xu.f.w v3,v2'
++.*Error: illegal operands `vfncvt.rtz.xu.f.w v0,v2,v0.t'
+ .*Error: illegal operands `vfncvt.rtz.x.f.w v2,v2'
+ .*Error: illegal operands `vfncvt.rtz.x.f.w v2,v3'
+ .*Error: illegal operands `vfncvt.rtz.x.f.w v3,v2'
++.*Error: illegal operands `vfncvt.rtz.x.f.w v0,v2,v0.t'
+ .*Error: illegal operands `vfncvt.f.xu.w v2,v2'
+ .*Error: illegal operands `vfncvt.f.xu.w v2,v3'
+ .*Error: illegal operands `vfncvt.f.xu.w v3,v2'
++.*Error: illegal operands `vfncvt.f.xu.w v0,v2,v0.t'
+ .*Error: illegal operands `vfncvt.f.x.w v2,v2'
+ .*Error: illegal operands `vfncvt.f.x.w v2,v3'
+ .*Error: illegal operands `vfncvt.f.x.w v3,v2'
++.*Error: illegal operands `vfncvt.f.x.w v0,v2,v0.t'
+ .*Error: illegal operands `vfncvt.f.f.w v2,v2'
+ .*Error: illegal operands `vfncvt.f.f.w v2,v3'
+ .*Error: illegal operands `vfncvt.f.f.w v3,v2'
++.*Error: illegal operands `vfncvt.f.f.w v0,v2,v0.t'
+ .*Error: illegal operands `vfncvt.rod.f.f.w v2,v2'
+ .*Error: illegal operands `vfncvt.rod.f.f.w v2,v3'
+ .*Error: illegal operands `vfncvt.rod.f.f.w v3,v2'
++.*Error: illegal operands `vfncvt.rod.f.f.w v0,v2,v0.t'
+diff --git a/gas/testsuite/gas/riscv/vector-insns-fail-arith-narrow.s b/gas/testsuite/gas/riscv/vector-insns-fail-arith-narrow.s
+new file mode 100644
+index 0000000000..a843d076ff
+--- /dev/null
++++ b/gas/testsuite/gas/riscv/vector-insns-fail-arith-narrow.s
+@@ -0,0 +1,100 @@
++# Vector Narrowing Integer Right Shift Instructions
++
++	# vncvt.x.x.v vd,vs,vm = vnsrl.wx vd,vs,x0,vm
++	vncvt.x.x.v v2, v2		# vd overlap vs2
++	vncvt.x.x.v v2, v3		# vs2 should be multiple of 2
++	vncvt.x.x.v v3, v2		# vd overlap vs2
++	vncvt.x.x.v v0, v2, v0.t	# vd overlap vm
++
++	vnsrl.wv v2, v2, v4		# vd overlap vs2
++	vnsrl.wv v2, v3, v4		# vs2 should be multiple of 2
++	vnsrl.wv v3, v2, v4		# vd overlap vs2
++	vnsrl.wv v4, v2, v4		# OK
++	vnsrl.wv v0, v2, v4, v0.t	# vd overlap vm
++	vnsrl.wx v2, v2, a1		# vd overlap vs2
++	vnsrl.wx v2, v3, a1		# vs2 should be multiple of 2
++	vnsrl.wx v3, v2, a1		# vd overlap vs2
++	vnsrl.wx v0, v2, a1, v0.t	# vd overlap vm
++	vnsrl.wi v2, v2, 31		# vd overlap vs2
++	vnsrl.wi v2, v3, 31		# vs2 should be multiple of 2
++	vnsrl.wi v3, v2, 31		# vd overlap vs2
++	vnsrl.wi v0, v2, 31, v0.t	# vd overlap vm
++
++	vnsra.wv v2, v2, v4
++	vnsra.wv v2, v3, v4
++	vnsra.wv v3, v2, v4
++	vnsra.wv v4, v2, v4
++	vnsra.wv v0, v2, v4, v0.t
++	vnsra.wx v2, v2, a1
++	vnsra.wx v2, v3, a1
++	vnsra.wx v3, v2, a1
++	vnsra.wx v0, v2, a1, v0.t
++	vnsra.wi v2, v2, 31
++	vnsra.wi v2, v3, 31
++	vnsra.wi v3, v2, 31
++	vnsra.wi v0, v2, 31, v0.t
++
++# Vector Narrowing Fixed-Point Clip Instructions
++
++	vnclipu.wv v2, v2, v4		# vd overlap vs2
++	vnclipu.wv v2, v3, v4		# vs2 should be multiple of 2
++	vnclipu.wv v3, v2, v4		# vd overlap vs2
++	vnclipu.wv v4, v2, v4		# OK
++	vnclipu.wv v0, v2, v4, v0.t	# vd overlap vm
++	vnclipu.wx v2, v2, a1		# vd overlap vs2
++	vnclipu.wx v2, v3, a1		# vs2 should be multiple of 2
++	vnclipu.wx v3, v2, a1		# vd overlap vs2
++	vnclipu.wx v0, v2, a1, v0.t	# vd overlap vm
++	vnclipu.wi v2, v2, 31		# vd overlap vs2
++	vnclipu.wi v2, v3, 31		# vs2 should be multiple of 2
++	vnclipu.wi v3, v2, 31		# vd overlap vs2
++	vnclipu.wi v0, v2, 31, v0.t	# vd overlap vm
++
++	vnclip.wv v2, v2, v4
++	vnclip.wv v2, v3, v4
++	vnclip.wv v3, v2, v4
++	vnclip.wv v4, v2, v4
++	vnclip.wv v0, v2, v4, v0.t
++	vnclip.wx v2, v2, a1
++	vnclip.wx v2, v3, a1
++	vnclip.wx v3, v2, a1
++	vnclip.wx v0, v2, a1, v0.t
++	vnclip.wi v2, v2, 31
++	vnclip.wi v2, v3, 31
++	vnclip.wi v3, v2, 31
++	vnclip.wi v0, v2, 31, v0.t
++
++# Narrowing Floating-Point/Integer Type-Convert Instructions
++
++	vfncvt.xu.f.w v2, v2		# vd overlap vs2
++	vfncvt.xu.f.w v2, v3		# vs2 should be multiple of 2
++	vfncvt.xu.f.w v3, v2		# vd overlap vs2
++	vfncvt.xu.f.w v0, v2, v0.t	# vd overlap vm
++	vfncvt.x.f.w v2, v2
++	vfncvt.x.f.w v2, v3
++	vfncvt.x.f.w v3, v2
++	vfncvt.x.f.w v0, v2, v0.t
++	vfncvt.rtz.xu.f.w v2, v2
++	vfncvt.rtz.xu.f.w v2, v3
++	vfncvt.rtz.xu.f.w v3, v2
++	vfncvt.rtz.xu.f.w v0, v2, v0.t
++	vfncvt.rtz.x.f.w v2, v2
++	vfncvt.rtz.x.f.w v2, v3
++	vfncvt.rtz.x.f.w v3, v2
++	vfncvt.rtz.x.f.w v0, v2, v0.t
++	vfncvt.f.xu.w v2, v2
++	vfncvt.f.xu.w v2, v3
++	vfncvt.f.xu.w v3, v2
++	vfncvt.f.xu.w v0, v2, v0.t
++	vfncvt.f.x.w v2, v2
++	vfncvt.f.x.w v2, v3
++	vfncvt.f.x.w v3, v2
++	vfncvt.f.x.w v0, v2, v0.t
++	vfncvt.f.f.w v2, v2
++	vfncvt.f.f.w v2, v3
++	vfncvt.f.f.w v3, v2
++	vfncvt.f.f.w v0, v2, v0.t
++	vfncvt.rod.f.f.w v2, v2
++	vfncvt.rod.f.f.w v2, v3
++	vfncvt.rod.f.f.w v3, v2
++	vfncvt.rod.f.f.w v0, v2, v0.t
+diff --git a/gas/testsuite/gas/riscv/vector-insns-fail-arith-widen.d b/gas/testsuite/gas/riscv/vector-insns-fail-arith-widen.d
+new file mode 100644
+index 0000000000..e5f034882c
+--- /dev/null
++++ b/gas/testsuite/gas/riscv/vector-insns-fail-arith-widen.d
+@@ -0,0 +1,3 @@
++#as: -march=rv32ifv -mcheck-constraints
++#source: vector-insns-fail-arith-widen.s
++#error_output: vector-insns-fail-arith-widen.l
+diff --git a/gas/testsuite/gas/riscv/vector-insns-fail-arith-widen.l b/gas/testsuite/gas/riscv/vector-insns-fail-arith-widen.l
+new file mode 100644
+index 0000000000..5684601697
+--- /dev/null
++++ b/gas/testsuite/gas/riscv/vector-insns-fail-arith-widen.l
+@@ -0,0 +1,253 @@
++.*: Assembler messages:
++.*Error: illegal operands `vwcvtu.x.x.v v1,v2'
++.*Error: illegal operands `vwcvtu.x.x.v v2,v2'
++.*Error: illegal operands `vwcvtu.x.x.v v2,v3'
++.*Error: illegal operands `vwcvtu.x.x.v v0,v2,v0.t'
++.*Error: illegal operands `vwcvt.x.x.v v1,v2'
++.*Error: illegal operands `vwcvt.x.x.v v2,v2'
++.*Error: illegal operands `vwcvt.x.x.v v2,v3'
++.*Error: illegal operands `vwcvt.x.x.v v0,v2,v0.t'
++.*Error: illegal operands `vwaddu.vv v1,v2,v4'
++.*Error: illegal operands `vwaddu.vv v2,v2,v4'
++.*Error: illegal operands `vwaddu.vv v2,v3,v4'
++.*Error: illegal operands `vwaddu.vv v4,v2,v4'
++.*Error: illegal operands `vwaddu.vv v4,v2,v5'
++.*Error: illegal operands `vwaddu.vv v0,v2,v4,v0.t'
++.*Error: illegal operands `vwaddu.vx v1,v2,a1'
++.*Error: illegal operands `vwaddu.vx v2,v2,a1'
++.*Error: illegal operands `vwaddu.vx v2,v3,a1'
++.*Error: illegal operands `vwaddu.vx v0,v2,a1,v0.t'
++.*Error: illegal operands `vwaddu.wv v1,v2,v4'
++.*Error: illegal operands `vwaddu.wv v2,v3,v4'
++.*Error: illegal operands `vwaddu.wv v4,v2,v4'
++.*Error: illegal operands `vwaddu.wv v4,v2,v5'
++.*Error: illegal operands `vwaddu.wv v0,v2,v4,v0.t'
++.*Error: illegal operands `vwaddu.wx v1,v2,a1'
++.*Error: illegal operands `vwaddu.wx v2,v3,a1'
++.*Error: illegal operands `vwaddu.wx v0,v2,a1,v0.t'
++.*Error: illegal operands `vwsubu.vv v1,v2,v4'
++.*Error: illegal operands `vwsubu.vv v2,v2,v4'
++.*Error: illegal operands `vwsubu.vv v2,v3,v4'
++.*Error: illegal operands `vwsubu.vv v4,v2,v4'
++.*Error: illegal operands `vwsubu.vv v4,v2,v5'
++.*Error: illegal operands `vwsubu.vv v0,v2,v4,v0.t'
++.*Error: illegal operands `vwsubu.vx v1,v2,a1'
++.*Error: illegal operands `vwsubu.vx v2,v2,a1'
++.*Error: illegal operands `vwsubu.vx v2,v3,a1'
++.*Error: illegal operands `vwsubu.vx v0,v2,a1,v0.t'
++.*Error: illegal operands `vwsubu.wv v1,v2,v4'
++.*Error: illegal operands `vwsubu.wv v2,v3,v4'
++.*Error: illegal operands `vwsubu.wv v4,v2,v4'
++.*Error: illegal operands `vwsubu.wv v4,v2,v5'
++.*Error: illegal operands `vwsubu.wv v0,v2,v4,v0.t'
++.*Error: illegal operands `vwsubu.wx v1,v2,a1'
++.*Error: illegal operands `vwsubu.wx v2,v3,a1'
++.*Error: illegal operands `vwsubu.wx v0,v2,a1,v0.t'
++.*Error: illegal operands `vwadd.vv v1,v2,v4'
++.*Error: illegal operands `vwadd.vv v2,v2,v4'
++.*Error: illegal operands `vwadd.vv v2,v3,v4'
++.*Error: illegal operands `vwadd.vv v4,v2,v4'
++.*Error: illegal operands `vwadd.vv v4,v2,v5'
++.*Error: illegal operands `vwadd.vv v0,v2,v4,v0.t'
++.*Error: illegal operands `vwadd.vx v1,v2,a1'
++.*Error: illegal operands `vwadd.vx v2,v2,a1'
++.*Error: illegal operands `vwadd.vx v2,v3,a1'
++.*Error: illegal operands `vwadd.vx v0,v2,a1,v0.t'
++.*Error: illegal operands `vwadd.wv v1,v2,v4'
++.*Error: illegal operands `vwadd.wv v2,v3,v4'
++.*Error: illegal operands `vwadd.wv v4,v2,v4'
++.*Error: illegal operands `vwadd.wv v4,v2,v5'
++.*Error: illegal operands `vwadd.wv v0,v2,v4,v0.t'
++.*Error: illegal operands `vwadd.wx v1,v2,a1'
++.*Error: illegal operands `vwadd.wx v2,v3,a1'
++.*Error: illegal operands `vwadd.wx v0,v2,a1,v0.t'
++.*Error: illegal operands `vwsub.vv v1,v2,v4'
++.*Error: illegal operands `vwsub.vv v2,v2,v4'
++.*Error: illegal operands `vwsub.vv v2,v3,v4'
++.*Error: illegal operands `vwsub.vv v4,v2,v4'
++.*Error: illegal operands `vwsub.vv v4,v2,v5'
++.*Error: illegal operands `vwsub.vv v0,v2,v4,v0.t'
++.*Error: illegal operands `vwsub.vx v1,v2,a1'
++.*Error: illegal operands `vwsub.vx v2,v2,a1'
++.*Error: illegal operands `vwsub.vx v2,v3,a1'
++.*Error: illegal operands `vwsub.vx v0,v2,a1,v0.t'
++.*Error: illegal operands `vwsub.wv v1,v2,v4'
++.*Error: illegal operands `vwsub.wv v2,v3,v4'
++.*Error: illegal operands `vwsub.wv v4,v2,v4'
++.*Error: illegal operands `vwsub.wv v4,v2,v5'
++.*Error: illegal operands `vwsub.wv v0,v2,v4,v0.t'
++.*Error: illegal operands `vwsub.wx v1,v2,a1'
++.*Error: illegal operands `vwsub.wx v2,v3,a1'
++.*Error: illegal operands `vwsub.wx v0,v2,a1,v0.t'
++.*Error: illegal operands `vwmul.vv v1,v2,v4'
++.*Error: illegal operands `vwmul.vv v2,v2,v4'
++.*Error: illegal operands `vwmul.vv v2,v3,v4'
++.*Error: illegal operands `vwmul.vv v4,v2,v4'
++.*Error: illegal operands `vwmul.vv v4,v2,v5'
++.*Error: illegal operands `vwmul.vv v0,v2,v4,v0.t'
++.*Error: illegal operands `vwmul.vx v1,v2,a1'
++.*Error: illegal operands `vwmul.vx v2,v2,a1'
++.*Error: illegal operands `vwmul.vx v2,v3,a1'
++.*Error: illegal operands `vwmul.vx v0,v2,a1,v0.t'
++.*Error: illegal operands `vwmulu.vv v1,v2,v4'
++.*Error: illegal operands `vwmulu.vv v2,v2,v4'
++.*Error: illegal operands `vwmulu.vv v2,v3,v4'
++.*Error: illegal operands `vwmulu.vv v4,v2,v4'
++.*Error: illegal operands `vwmulu.vv v4,v2,v5'
++.*Error: illegal operands `vwmulu.vv v0,v2,v4,v0.t'
++.*Error: illegal operands `vwmulu.vx v1,v2,a1'
++.*Error: illegal operands `vwmulu.vx v2,v2,a1'
++.*Error: illegal operands `vwmulu.vx v2,v3,a1'
++.*Error: illegal operands `vwmulu.vx v0,v2,a1,v0.t'
++.*Error: illegal operands `vwmulsu.vv v1,v2,v4'
++.*Error: illegal operands `vwmulsu.vv v2,v2,v4'
++.*Error: illegal operands `vwmulsu.vv v2,v3,v4'
++.*Error: illegal operands `vwmulsu.vv v4,v2,v4'
++.*Error: illegal operands `vwmulsu.vv v4,v2,v5'
++.*Error: illegal operands `vwmulsu.vv v0,v2,v4,v0.t'
++.*Error: illegal operands `vwmulsu.vx v1,v2,a1'
++.*Error: illegal operands `vwmulsu.vx v2,v2,a1'
++.*Error: illegal operands `vwmulsu.vx v2,v3,a1'
++.*Error: illegal operands `vwmulsu.vx v0,v2,a1,v0.t'
++.*Error: illegal operands `vwmaccu.vv v1,v2,v4'
++.*Error: illegal operands `vwmaccu.vv v2,v2,v4'
++.*Error: illegal operands `vwmaccu.vv v2,v3,v4'
++.*Error: illegal operands `vwmaccu.vv v4,v2,v4'
++.*Error: illegal operands `vwmaccu.vv v4,v2,v5'
++.*Error: illegal operands `vwmaccu.vv v0,v2,v4,v0.t'
++.*Error: illegal operands `vwmaccu.vx v1,a1,v2'
++.*Error: illegal operands `vwmaccu.vx v2,a1,v2'
++.*Error: illegal operands `vwmaccu.vx v2,a1,v3'
++.*Error: illegal operands `vwmaccu.vx v0,a1,v2,v0.t'
++.*Error: illegal operands `vwmacc.vv v1,v2,v4'
++.*Error: illegal operands `vwmacc.vv v2,v2,v4'
++.*Error: illegal operands `vwmacc.vv v2,v3,v4'
++.*Error: illegal operands `vwmacc.vv v4,v2,v4'
++.*Error: illegal operands `vwmacc.vv v4,v2,v5'
++.*Error: illegal operands `vwmacc.vv v0,v2,v4,v0.t'
++.*Error: illegal operands `vwmacc.vx v1,a1,v2'
++.*Error: illegal operands `vwmacc.vx v2,a1,v2'
++.*Error: illegal operands `vwmacc.vx v2,a1,v3'
++.*Error: illegal operands `vwmacc.vx v0,a1,v2,v0.t'
++.*Error: illegal operands `vwmaccsu.vv v1,v2,v4'
++.*Error: illegal operands `vwmaccsu.vv v2,v2,v4'
++.*Error: illegal operands `vwmaccsu.vv v2,v3,v4'
++.*Error: illegal operands `vwmaccsu.vv v4,v2,v4'
++.*Error: illegal operands `vwmaccsu.vv v4,v2,v5'
++.*Error: illegal operands `vwmaccsu.vv v0,v2,v4,v0.t'
++.*Error: illegal operands `vwmaccsu.vx v1,a1,v2'
++.*Error: illegal operands `vwmaccsu.vx v2,a1,v2'
++.*Error: illegal operands `vwmaccsu.vx v2,a1,v3'
++.*Error: illegal operands `vwmaccsu.vx v0,a1,v2,v0.t'
++.*Error: illegal operands `vwmaccus.vx v1,a1,v2'
++.*Error: illegal operands `vwmaccus.vx v2,a1,v2'
++.*Error: illegal operands `vwmaccus.vx v2,a1,v3'
++.*Error: illegal operands `vwmaccus.vx v0,a1,v2,v0.t'
++.*Error: illegal operands `vfwadd.vv v1,v2,v4'
++.*Error: illegal operands `vfwadd.vv v2,v2,v4'
++.*Error: illegal operands `vfwadd.vv v2,v3,v4'
++.*Error: illegal operands `vfwadd.vv v4,v2,v4'
++.*Error: illegal operands `vfwadd.vv v4,v2,v5'
++.*Error: illegal operands `vfwadd.vv v0,v2,v4,v0.t'
++.*Error: illegal operands `vfwadd.vf v1,v2,fa1'
++.*Error: illegal operands `vfwadd.vf v2,v2,fa1'
++.*Error: illegal operands `vfwadd.vf v2,v3,fa1'
++.*Error: illegal operands `vfwadd.vf v0,v2,fa1,v0.t'
++.*Error: illegal operands `vfwadd.wv v1,v2,v4'
++.*Error: illegal operands `vfwadd.wv v2,v3,v4'
++.*Error: illegal operands `vfwadd.wv v4,v2,v4'
++.*Error: illegal operands `vfwadd.wv v4,v2,v5'
++.*Error: illegal operands `vfwadd.wv v0,v2,v4,v0.t'
++.*Error: illegal operands `vfwsub.vv v1,v2,v4'
++.*Error: illegal operands `vfwsub.vv v2,v2,v4'
++.*Error: illegal operands `vfwsub.vv v2,v3,v4'
++.*Error: illegal operands `vfwsub.vv v4,v2,v4'
++.*Error: illegal operands `vfwsub.vv v4,v2,v5'
++.*Error: illegal operands `vfwsub.vv v0,v2,v4,v0.t'
++.*Error: illegal operands `vfwsub.vf v1,v2,fa1'
++.*Error: illegal operands `vfwsub.vf v2,v2,fa1'
++.*Error: illegal operands `vfwsub.vf v2,v3,fa1'
++.*Error: illegal operands `vfwsub.vf v0,v2,fa1,v0.t'
++.*Error: illegal operands `vfwsub.wv v1,v2,v4'
++.*Error: illegal operands `vfwsub.wv v2,v3,v4'
++.*Error: illegal operands `vfwsub.wv v4,v2,v4'
++.*Error: illegal operands `vfwsub.wv v4,v2,v5'
++.*Error: illegal operands `vfwsub.wv v0,v2,v4,v0.t'
++.*Error: illegal operands `vfwmul.vv v1,v2,v4'
++.*Error: illegal operands `vfwmul.vv v2,v2,v4'
++.*Error: illegal operands `vfwmul.vv v2,v3,v4'
++.*Error: illegal operands `vfwmul.vv v4,v2,v4'
++.*Error: illegal operands `vfwmul.vv v4,v2,v5'
++.*Error: illegal operands `vfwmul.vv v0,v2,v4,v0.t'
++.*Error: illegal operands `vfwsub.vf v1,v2,fa1'
++.*Error: illegal operands `vfwsub.vf v2,v2,fa1'
++.*Error: illegal operands `vfwsub.vf v2,v3,fa1'
++.*Error: illegal operands `vfwsub.vf v0,v2,fa1,v0.t'
++.*Error: illegal operands `vfwmacc.vv v1,v2,v4'
++.*Error: illegal operands `vfwmacc.vv v2,v2,v4'
++.*Error: illegal operands `vfwmacc.vv v2,v3,v4'
++.*Error: illegal operands `vfwmacc.vv v4,v2,v4'
++.*Error: illegal operands `vfwmacc.vv v4,v2,v5'
++.*Error: illegal operands `vfwmacc.vv v0,v2,v4,v0.t'
++.*Error: illegal operands `vfwmacc.vf v1,fa1,v2'
++.*Error: illegal operands `vfwmacc.vf v2,fa1,v2'
++.*Error: illegal operands `vfwmacc.vf v2,fa1,v3'
++.*Error: illegal operands `vfwmacc.vf v0,fa1,v2,v0.t'
++.*Error: illegal operands `vfwnmacc.vv v1,v2,v4'
++.*Error: illegal operands `vfwnmacc.vv v2,v2,v4'
++.*Error: illegal operands `vfwnmacc.vv v2,v3,v4'
++.*Error: illegal operands `vfwnmacc.vv v4,v2,v4'
++.*Error: illegal operands `vfwnmacc.vv v4,v2,v5'
++.*Error: illegal operands `vfwnmacc.vv v0,v2,v4,v0.t'
++.*Error: illegal operands `vfwnmacc.vf v1,fa1,v2'
++.*Error: illegal operands `vfwnmacc.vf v2,fa1,v2'
++.*Error: illegal operands `vfwnmacc.vf v2,fa1,v3'
++.*Error: illegal operands `vfwnmacc.vf v0,fa1,v2,v0.t'
++.*Error: illegal operands `vfwmsac.vv v1,v2,v4'
++.*Error: illegal operands `vfwmsac.vv v2,v2,v4'
++.*Error: illegal operands `vfwmsac.vv v2,v3,v4'
++.*Error: illegal operands `vfwmsac.vv v4,v2,v4'
++.*Error: illegal operands `vfwmsac.vv v4,v2,v5'
++.*Error: illegal operands `vfwmsac.vv v0,v2,v4,v0.t'
++.*Error: illegal operands `vfwmsac.vf v1,fa1,v2'
++.*Error: illegal operands `vfwmsac.vf v2,fa1,v2'
++.*Error: illegal operands `vfwmsac.vf v2,fa1,v3'
++.*Error: illegal operands `vfwmsac.vf v0,fa1,v2,v0.t'
++.*Error: illegal operands `vfwnmsac.vv v1,v2,v4'
++.*Error: illegal operands `vfwnmsac.vv v2,v2,v4'
++.*Error: illegal operands `vfwnmsac.vv v2,v3,v4'
++.*Error: illegal operands `vfwnmsac.vv v4,v2,v4'
++.*Error: illegal operands `vfwnmsac.vv v4,v2,v5'
++.*Error: illegal operands `vfwnmsac.vv v0,v2,v4,v0.t'
++.*Error: illegal operands `vfwnmsac.vf v1,fa1,v2'
++.*Error: illegal operands `vfwnmsac.vf v2,fa1,v2'
++.*Error: illegal operands `vfwnmsac.vf v2,fa1,v3'
++.*Error: illegal operands `vfwnmsac.vf v0,fa1,v2,v0.t'
++.*Error: illegal operands `vfwcvt.xu.f.v v1,v2'
++.*Error: illegal operands `vfwcvt.xu.f.v v2,v2'
++.*Error: illegal operands `vfwcvt.xu.f.v v2,v3'
++.*Error: illegal operands `vfwcvt.xu.f.v v0,v2,v0.t'
++.*Error: illegal operands `vfwcvt.x.f.v v1,v2'
++.*Error: illegal operands `vfwcvt.x.f.v v2,v2'
++.*Error: illegal operands `vfwcvt.x.f.v v2,v3'
++.*Error: illegal operands `vfwcvt.x.f.v v0,v2,v0.t'
++.*Error: illegal operands `vfwcvt.rtz.xu.f.v v1,v2'
++.*Error: illegal operands `vfwcvt.rtz.xu.f.v v2,v2'
++.*Error: illegal operands `vfwcvt.rtz.xu.f.v v2,v3'
++.*Error: illegal operands `vfwcvt.rtz.xu.f.v v0,v2,v0.t'
++.*Error: illegal operands `vfwcvt.rtz.x.f.v v1,v2'
++.*Error: illegal operands `vfwcvt.rtz.x.f.v v2,v2'
++.*Error: illegal operands `vfwcvt.rtz.x.f.v v2,v3'
++.*Error: illegal operands `vfwcvt.rtz.x.f.v v0,v2,v0.t'
++.*Error: illegal operands `vfwcvt.f.xu.v v1,v2'
++.*Error: illegal operands `vfwcvt.f.xu.v v2,v2'
++.*Error: illegal operands `vfwcvt.f.xu.v v2,v3'
++.*Error: illegal operands `vfwcvt.f.xu.v v0,v2,v0.t'
++.*Error: illegal operands `vfwcvt.f.x.v v1,v2'
++.*Error: illegal operands `vfwcvt.f.x.v v2,v2'
++.*Error: illegal operands `vfwcvt.f.x.v v2,v3'
++.*Error: illegal operands `vfwcvt.f.x.v v0,v2,v0.t'
++.*Error: illegal operands `vfwcvt.f.f.v v1,v2'
++.*Error: illegal operands `vfwcvt.f.f.v v2,v2'
++.*Error: illegal operands `vfwcvt.f.f.v v2,v3'
++.*Error: illegal operands `vfwcvt.f.f.v v0,v2,v0.t'
+diff --git a/gas/testsuite/gas/riscv/vector-insns-fail-arith-widen.s b/gas/testsuite/gas/riscv/vector-insns-fail-arith-widen.s
+new file mode 100644
+index 0000000000..addedd4dc2
+--- /dev/null
++++ b/gas/testsuite/gas/riscv/vector-insns-fail-arith-widen.s
+@@ -0,0 +1,297 @@
++# Vector Widening Integer Add/Subtract
++
++	# vwcvtu.x.x.v vd,vs,vm = vwaddu.vx vd,vs,x0,vm
++	vwcvtu.x.x.v v1, v2		# vd should be multiple of 2
++	vwcvtu.x.x.v v2, v2		# vd overlap vs2
++	vwcvtu.x.x.v v2, v3		# vd overlap vs2
++	vwcvtu.x.x.v v0, v2, v0.t	# vd overlap vm
++
++	# vwcvt.x.x.v vd,vs,vm = vwadd.vx vd,vs,x0,vm
++	vwcvt.x.x.v v1, v2
++	vwcvt.x.x.v v2, v2
++	vwcvt.x.x.v v2, v3
++	vwcvt.x.x.v v0, v2, v0.t
++
++	vwaddu.vv v1, v2, v4		# vd should be multiple of 2
++	vwaddu.vv v2, v2, v4		# vd overlap vs2
++	vwaddu.vv v2, v3, v4		# vd overlap vs2
++	vwaddu.vv v4, v2, v4		# vd overlap vs1
++	vwaddu.vv v4, v2, v5		# vd overlap vs1
++	vwaddu.vv v0, v2, v4, v0.t	# vd overlap vm
++	vwaddu.vx v1, v2, a1		# vd should be multiple of 2
++	vwaddu.vx v2, v2, a1		# vd overlap vs2
++	vwaddu.vx v2, v3, a1		# vd overlap vs2
++	vwaddu.vx v0, v2, a1, v0.t	# vd overlap vm
++	vwaddu.wv v1, v2, v4		# vd should be multiple of 2
++	vwaddu.wv v2, v2, v4		# OK
++	vwaddu.wv v2, v3, v4		# vs2 should be multiple of 2
++	vwaddu.wv v4, v2, v4		# vd overlap vs1
++	vwaddu.wv v4, v2, v5		# vd overlap vs1
++	vwaddu.wv v0, v2, v4, v0.t	# vd overlap vm
++	vwaddu.wx v1, v2, a1		# vd should be multiple of 2
++	vwaddu.wx v2, v2, a1		# OK
++	vwaddu.wx v2, v3, a1		# vs2 should be multiple of 2
++	vwaddu.wx v0, v2, a1, v0.t	# vd overlap vm
++
++	vwsubu.vv v1, v2, v4
++	vwsubu.vv v2, v2, v4
++	vwsubu.vv v2, v3, v4
++	vwsubu.vv v4, v2, v4
++	vwsubu.vv v4, v2, v5
++	vwsubu.vv v0, v2, v4, v0.t
++	vwsubu.vx v1, v2, a1
++	vwsubu.vx v2, v2, a1
++	vwsubu.vx v2, v3, a1
++	vwsubu.vx v0, v2, a1, v0.t
++	vwsubu.wv v1, v2, v4
++	vwsubu.wv v2, v2, v4
++	vwsubu.wv v2, v3, v4
++	vwsubu.wv v4, v2, v4
++	vwsubu.wv v4, v2, v5
++	vwsubu.wv v0, v2, v4, v0.t
++	vwsubu.wx v1, v2, a1
++	vwsubu.wx v2, v2, a1
++	vwsubu.wx v2, v3, a1
++	vwsubu.wx v0, v2, a1, v0.t
++
++	vwadd.vv v1, v2, v4
++	vwadd.vv v2, v2, v4
++	vwadd.vv v2, v3, v4
++	vwadd.vv v4, v2, v4
++	vwadd.vv v4, v2, v5
++	vwadd.vv v0, v2, v4, v0.t
++	vwadd.vx v1, v2, a1
++	vwadd.vx v2, v2, a1
++	vwadd.vx v2, v3, a1
++	vwadd.vx v0, v2, a1, v0.t
++	vwadd.wv v1, v2, v4
++	vwadd.wv v2, v2, v4
++	vwadd.wv v2, v3, v4
++	vwadd.wv v4, v2, v4
++	vwadd.wv v4, v2, v5
++	vwadd.wv v0, v2, v4, v0.t
++	vwadd.wx v1, v2, a1
++	vwadd.wx v2, v2, a1
++	vwadd.wx v2, v3, a1
++	vwadd.wx v0, v2, a1, v0.t
++
++	vwsub.vv v1, v2, v4
++	vwsub.vv v2, v2, v4
++	vwsub.vv v2, v3, v4
++	vwsub.vv v4, v2, v4
++	vwsub.vv v4, v2, v5
++	vwsub.vv v0, v2, v4, v0.t
++	vwsub.vx v1, v2, a1
++	vwsub.vx v2, v2, a1
++	vwsub.vx v2, v3, a1
++	vwsub.vx v0, v2, a1, v0.t
++	vwsub.wv v1, v2, v4
++	vwsub.wv v2, v2, v4
++	vwsub.wv v2, v3, v4
++	vwsub.wv v4, v2, v4
++	vwsub.wv v4, v2, v5
++	vwsub.wv v0, v2, v4, v0.t
++	vwsub.wx v1, v2, a1
++	vwsub.wx v2, v2, a1
++	vwsub.wx v2, v3, a1
++	vwsub.wx v0, v2, a1, v0.t
++
++# Vector Widening Integer Multiply Instructions
++
++	vwmul.vv v1, v2, v4		# vd should be multiple of 2
++	vwmul.vv v2, v2, v4		# vd overlap vs2
++	vwmul.vv v2, v3, v4		# vd overlap vs2
++	vwmul.vv v4, v2, v4		# vd overlap vs1
++	vwmul.vv v4, v2, v5		# vd overlap vs1
++	vwmul.vv v0, v2, v4, v0.t	# vd overlap vm
++	vwmul.vx v1, v2, a1		# vd should be multiple of 2
++	vwmul.vx v2, v2, a1		# vd overlap vs2
++	vwmul.vx v2, v3, a1		# vd overlap vs2
++	vwmul.vx v0, v2, a1, v0.t	# vd overlap vm
++
++	vwmulu.vv v1, v2, v4
++	vwmulu.vv v2, v2, v4
++	vwmulu.vv v2, v3, v4
++	vwmulu.vv v4, v2, v4
++	vwmulu.vv v4, v2, v5
++	vwmulu.vv v0, v2, v4, v0.t
++	vwmulu.vx v1, v2, a1
++	vwmulu.vx v2, v2, a1
++	vwmulu.vx v2, v3, a1
++	vwmulu.vx v0, v2, a1, v0.t
++
++	vwmulsu.vv v1, v2, v4
++	vwmulsu.vv v2, v2, v4
++	vwmulsu.vv v2, v3, v4
++	vwmulsu.vv v4, v2, v4
++	vwmulsu.vv v4, v2, v5
++	vwmulsu.vv v0, v2, v4, v0.t
++	vwmulsu.vx v1, v2, a1
++	vwmulsu.vx v2, v2, a1
++	vwmulsu.vx v2, v3, a1
++	vwmulsu.vx v0, v2, a1, v0.t
++
++# Vector Widening Integer Multiply-Add Instructions
++
++	vwmaccu.vv v1, v2, v4		# vd should be multiple of 2
++	vwmaccu.vv v2, v2, v4		# vd overlap vs1
++	vwmaccu.vv v2, v3, v4		# vd overlap vs1
++	vwmaccu.vv v4, v2, v4		# vd overlap vs2
++	vwmaccu.vv v4, v2, v5		# vd overlap vs2
++	vwmaccu.vv v0, v2, v4, v0.t	# vd overlap vm
++	vwmaccu.vx v1, a1, v2		# vd should be multiple of 2
++	vwmaccu.vx v2, a1, v2		# vd overlap vs2
++	vwmaccu.vx v2, a1, v3		# vd overlap vs2
++	vwmaccu.vx v0, a1, v2, v0.t	# vd overlap vm
++
++	vwmacc.vv v1, v2, v4
++	vwmacc.vv v2, v2, v4
++	vwmacc.vv v2, v3, v4
++	vwmacc.vv v4, v2, v4
++	vwmacc.vv v4, v2, v5
++	vwmacc.vv v0, v2, v4, v0.t
++	vwmacc.vx v1, a1, v2
++	vwmacc.vx v2, a1, v2
++	vwmacc.vx v2, a1, v3
++	vwmacc.vx v0, a1, v2, v0.t
++
++	vwmaccsu.vv v1, v2, v4
++	vwmaccsu.vv v2, v2, v4
++	vwmaccsu.vv v2, v3, v4
++	vwmaccsu.vv v4, v2, v4
++	vwmaccsu.vv v4, v2, v5
++	vwmaccsu.vv v0, v2, v4, v0.t
++	vwmaccsu.vx v1, a1, v2
++	vwmaccsu.vx v2, a1, v2
++	vwmaccsu.vx v2, a1, v3
++	vwmaccsu.vx v0, a1, v2, v0.t
++
++	vwmaccus.vx v1, a1, v2		# vd should be multiple of 2
++	vwmaccus.vx v2, a1, v2		# vd overlap vs2
++	vwmaccus.vx v2, a1, v3		# vd overlap vs2
++	vwmaccus.vx v0, a1, v2, v0.t	# vd overlap vm
++
++# Vector Widening Floating-Point Add/Subtract Instructions
++
++	vfwadd.vv v1, v2, v4		# vd should be multiple of 2
++	vfwadd.vv v2, v2, v4		# vd overlap vs2
++	vfwadd.vv v2, v3, v4		# vd overlap vs2
++	vfwadd.vv v4, v2, v4		# vd overlap vs1
++	vfwadd.vv v4, v2, v5		# vd overlap vs1
++	vfwadd.vv v0, v2, v4, v0.t	# vd overlap vm
++	vfwadd.vf v1, v2, fa1		# vd should be multiple of 2
++	vfwadd.vf v2, v2, fa1		# vd overlap vs2
++	vfwadd.vf v2, v3, fa1		# vd overlap vs2
++	vfwadd.vf v0, v2, fa1, v0.t	# vd overlap vm
++	vfwadd.wv v1, v2, v4		# vd should be multiple of 2
++	vfwadd.wv v2, v2, v4		# OK
++	vfwadd.wv v2, v3, v4		# vs2 should be multiple of 2
++	vfwadd.wv v4, v2, v4		# vd overlap vs1
++	vfwadd.wv v4, v2, v5		# vd overlap vs1
++	vfwadd.wv v0, v2, v4, v0.t	# vd overlap vm
++
++	vfwsub.vv v1, v2, v4
++	vfwsub.vv v2, v2, v4
++	vfwsub.vv v2, v3, v4
++	vfwsub.vv v4, v2, v4
++	vfwsub.vv v4, v2, v5
++	vfwsub.vv v0, v2, v4, v0.t
++	vfwsub.vf v1, v2, fa1
++	vfwsub.vf v2, v2, fa1
++	vfwsub.vf v2, v3, fa1
++	vfwsub.vf v0, v2, fa1, v0.t
++	vfwsub.wv v1, v2, v4
++	vfwsub.wv v2, v2, v4
++	vfwsub.wv v2, v3, v4
++	vfwsub.wv v4, v2, v4
++	vfwsub.wv v4, v2, v5
++	vfwsub.wv v0, v2, v4, v0.t
++
++# Vector Widening Floating-Point Multiply
++
++	vfwmul.vv v1, v2, v4		# vd should be multiple of 2
++	vfwmul.vv v2, v2, v4		# vd overlap vs2
++	vfwmul.vv v2, v3, v4		# vd overlap vs2
++	vfwmul.vv v4, v2, v4		# vd overlap vs1
++	vfwmul.vv v4, v2, v5		# vd overlap vs1
++	vfwmul.vv v0, v2, v4, v0.t	# vd overlap vm
++	vfwsub.vf v1, v2, fa1		# vd should be multiple of 2
++	vfwsub.vf v2, v2, fa1		# vd overlap vs2
++	vfwsub.vf v2, v3, fa1		# vd overlap vs2
++	vfwsub.vf v0, v2, fa1, v0.t	# vd overlap vm
++
++# Vector Widening Floating-Point Fused Multiply-Add Instructions
++	vfwmacc.vv v1, v2, v4		# vd should be multiple of 2
++	vfwmacc.vv v2, v2, v4		# vd overlap vs1
++	vfwmacc.vv v2, v3, v4		# vd overlap vs1
++	vfwmacc.vv v4, v2, v4		# vd overlap vs2
++	vfwmacc.vv v4, v2, v5		# vd overlap vs2
++	vfwmacc.vv v0, v2, v4, v0.t	# vd overlap vm
++	vfwmacc.vf v1, fa1, v2		# vd should be multiple of 2
++	vfwmacc.vf v2, fa1, v2		# vd overlap vs2
++	vfwmacc.vf v2, fa1, v3		# vd overlap vs2
++	vfwmacc.vf v0, fa1, v2, v0.t	# vd overlap vm
++
++	vfwnmacc.vv v1, v2, v4
++	vfwnmacc.vv v2, v2, v4
++	vfwnmacc.vv v2, v3, v4
++	vfwnmacc.vv v4, v2, v4
++	vfwnmacc.vv v4, v2, v5
++	vfwnmacc.vv v0, v2, v4, v0.t
++	vfwnmacc.vf v1, fa1, v2
++	vfwnmacc.vf v2, fa1, v2
++	vfwnmacc.vf v2, fa1, v3
++	vfwnmacc.vf v0, fa1, v2, v0.t
++
++	vfwmsac.vv v1, v2, v4
++	vfwmsac.vv v2, v2, v4
++	vfwmsac.vv v2, v3, v4
++	vfwmsac.vv v4, v2, v4
++	vfwmsac.vv v4, v2, v5
++	vfwmsac.vv v0, v2, v4, v0.t
++	vfwmsac.vf v1, fa1, v2
++	vfwmsac.vf v2, fa1, v2
++	vfwmsac.vf v2, fa1, v3
++	vfwmsac.vf v0, fa1, v2, v0.t
++
++	vfwnmsac.vv v1, v2, v4
++	vfwnmsac.vv v2, v2, v4
++	vfwnmsac.vv v2, v3, v4
++	vfwnmsac.vv v4, v2, v4
++	vfwnmsac.vv v4, v2, v5
++	vfwnmsac.vv v0, v2, v4, v0.t
++	vfwnmsac.vf v1, fa1, v2
++	vfwnmsac.vf v2, fa1, v2
++	vfwnmsac.vf v2, fa1, v3
++	vfwnmsac.vf v0, fa1, v2, v0.t
++
++# Widening Floating-Point/Integer Type-Convert Instructions
++
++	vfwcvt.xu.f.v v1, v2		# vd should be multiple of 2
++	vfwcvt.xu.f.v v2, v2		# vd overlap vs2
++	vfwcvt.xu.f.v v2, v3		# vd overlap vs2
++	vfwcvt.xu.f.v v0, v2, v0.t	# vd overlap vm
++	vfwcvt.x.f.v v1, v2
++	vfwcvt.x.f.v v2, v2
++	vfwcvt.x.f.v v2, v3
++	vfwcvt.x.f.v v0, v2, v0.t
++	vfwcvt.rtz.xu.f.v v1, v2
++	vfwcvt.rtz.xu.f.v v2, v2
++	vfwcvt.rtz.xu.f.v v2, v3
++	vfwcvt.rtz.xu.f.v v0, v2, v0.t
++	vfwcvt.rtz.x.f.v v1, v2
++	vfwcvt.rtz.x.f.v v2, v2
++	vfwcvt.rtz.x.f.v v2, v3
++	vfwcvt.rtz.x.f.v v0, v2, v0.t
++	vfwcvt.f.xu.v v1, v2
++	vfwcvt.f.xu.v v2, v2
++	vfwcvt.f.xu.v v2, v3
++	vfwcvt.f.xu.v v0, v2, v0.t
++	vfwcvt.f.x.v v1, v2
++	vfwcvt.f.x.v v2, v2
++	vfwcvt.f.x.v v2, v3
++	vfwcvt.f.x.v v0, v2, v0.t
++	vfwcvt.f.f.v v1, v2
++	vfwcvt.f.f.v v2, v2
++	vfwcvt.f.f.v v2, v3
++	vfwcvt.f.f.v v0, v2, v0.t
+diff --git a/gas/testsuite/gas/riscv/vector-insns-fail-load-store.d b/gas/testsuite/gas/riscv/vector-insns-fail-load-store.d
+new file mode 100644
+index 0000000000..763191f31e
+--- /dev/null
++++ b/gas/testsuite/gas/riscv/vector-insns-fail-load-store.d
+@@ -0,0 +1,3 @@
++#as: -march=rv32iv -mcheck-constraints
++#source: vector-insns-fail-load-store.s
++#error_output: vector-insns-fail-load-store.l
+diff --git a/gas/testsuite/gas/riscv/vector-insns-fail-load-store.l b/gas/testsuite/gas/riscv/vector-insns-fail-load-store.l
+new file mode 100644
+index 0000000000..bd04cbb263
+--- /dev/null
++++ b/gas/testsuite/gas/riscv/vector-insns-fail-load-store.l
+@@ -0,0 +1,557 @@
++.*: Assembler messages:
++.*Error: illegal operands `vle8.v v0,\(a0\),v0.t'
++.*Error: illegal operands `vle8ff.v v0,\(a0\),v0.t'
++.*Error: illegal operands `vle16.v v0,\(a0\),v0.t'
++.*Error: illegal operands `vle16ff.v v0,\(a0\),v0.t'
++.*Error: illegal operands `vle32.v v0,\(a0\),v0.t'
++.*Error: illegal operands `vle32ff.v v0,\(a0\),v0.t'
++.*Error: illegal operands `vle64.v v0,\(a0\),v0.t'
++.*Error: illegal operands `vle64ff.v v0,\(a0\),v0.t'
++.*Error: illegal operands `vle128.v v0,\(a0\),v0.t'
++.*Error: illegal operands `vle128ff.v v0,\(a0\),v0.t'
++.*Error: illegal operands `vle256.v v0,\(a0\),v0.t'
++.*Error: illegal operands `vle256ff.v v0,\(a0\),v0.t'
++.*Error: illegal operands `vle512.v v0,\(a0\),v0.t'
++.*Error: illegal operands `vle512ff.v v0,\(a0\),v0.t'
++.*Error: illegal operands `vle1024.v v0,\(a0\),v0.t'
++.*Error: illegal operands `vle1024ff.v v0,\(a0\),v0.t'
++.*Error: illegal operands `vse8.v v0,\(a0\),v0.t'
++.*Error: illegal operands `vse16.v v0,\(a0\),v0.t'
++.*Error: illegal operands `vse32.v v0,\(a0\),v0.t'
++.*Error: illegal operands `vse64.v v0,\(a0\),v0.t'
++.*Error: illegal operands `vse128.v v0,\(a0\),v0.t'
++.*Error: illegal operands `vse256.v v0,\(a0\),v0.t'
++.*Error: illegal operands `vse512.v v0,\(a0\),v0.t'
++.*Error: illegal operands `vse1024.v v0,\(a0\),v0.t'
++.*Error: illegal operands `vlse8.v v0,\(a0\),a1,v0.t'
++.*Error: illegal operands `vlse16.v v0,\(a0\),a1,v0.t'
++.*Error: illegal operands `vlse32.v v0,\(a0\),a1,v0.t'
++.*Error: illegal operands `vlse64.v v0,\(a0\),a1,v0.t'
++.*Error: illegal operands `vlse128.v v0,\(a0\),a1,v0.t'
++.*Error: illegal operands `vlse256.v v0,\(a0\),a1,v0.t'
++.*Error: illegal operands `vlse512.v v0,\(a0\),a1,v0.t'
++.*Error: illegal operands `vlse1024.v v0,\(a0\),a1,v0.t'
++.*Error: illegal operands `vsse8.v v0,\(a0\),a1,v0.t'
++.*Error: illegal operands `vsse16.v v0,\(a0\),a1,v0.t'
++.*Error: illegal operands `vsse32.v v0,\(a0\),a1,v0.t'
++.*Error: illegal operands `vsse64.v v0,\(a0\),a1,v0.t'
++.*Error: illegal operands `vsse128.v v0,\(a0\),a1,v0.t'
++.*Error: illegal operands `vsse256.v v0,\(a0\),a1,v0.t'
++.*Error: illegal operands `vsse512.v v0,\(a0\),a1,v0.t'
++.*Error: illegal operands `vsse1024.v v0,\(a0\),a1,v0.t'
++.*Error: illegal operands `vlxei8.v v0,\(a0\),v4,v0.t'
++.*Error: illegal operands `vlxei16.v v0,\(a0\),v4,v0.t'
++.*Error: illegal operands `vlxei32.v v0,\(a0\),v4,v0.t'
++.*Error: illegal operands `vlxei64.v v0,\(a0\),v4,v0.t'
++.*Error: illegal operands `vsxei8.v v0,\(a0\),v4,v0.t'
++.*Error: illegal operands `vsxei16.v v0,\(a0\),v4,v0.t'
++.*Error: illegal operands `vsxei32.v v0,\(a0\),v4,v0.t'
++.*Error: illegal operands `vsxei64.v v0,\(a0\),v4,v0.t'
++.*Error: illegal operands `vsuxei8.v v0,\(a0\),v4,v0.t'
++.*Error: illegal operands `vsuxei16.v v0,\(a0\),v4,v0.t'
++.*Error: illegal operands `vsuxei32.v v0,\(a0\),v4,v0.t'
++.*Error: illegal operands `vsuxei64.v v0,\(a0\),v4,v0.t'
++.*Error: illegal operands `vlseg2e8.v v0,\(a0\),v0.t'
++.*Error: illegal operands `vsseg2e8.v v0,\(a0\),v0.t'
++.*Error: illegal operands `vlseg2e8ff.v v0,\(a0\),v0.t'
++.*Error: illegal operands `vlseg3e8.v v0,\(a0\),v0.t'
++.*Error: illegal operands `vsseg3e8.v v0,\(a0\),v0.t'
++.*Error: illegal operands `vlseg3e8ff.v v0,\(a0\),v0.t'
++.*Error: illegal operands `vlseg4e8.v v0,\(a0\),v0.t'
++.*Error: illegal operands `vsseg4e8.v v0,\(a0\),v0.t'
++.*Error: illegal operands `vlseg4e8ff.v v0,\(a0\),v0.t'
++.*Error: illegal operands `vlseg5e8.v v0,\(a0\),v0.t'
++.*Error: illegal operands `vsseg5e8.v v0,\(a0\),v0.t'
++.*Error: illegal operands `vlseg5e8ff.v v0,\(a0\),v0.t'
++.*Error: illegal operands `vlseg6e8.v v0,\(a0\),v0.t'
++.*Error: illegal operands `vsseg6e8.v v0,\(a0\),v0.t'
++.*Error: illegal operands `vlseg6e8ff.v v0,\(a0\),v0.t'
++.*Error: illegal operands `vlseg7e8.v v0,\(a0\),v0.t'
++.*Error: illegal operands `vsseg7e8.v v0,\(a0\),v0.t'
++.*Error: illegal operands `vlseg7e8ff.v v0,\(a0\),v0.t'
++.*Error: illegal operands `vlseg8e8.v v0,\(a0\),v0.t'
++.*Error: illegal operands `vsseg8e8.v v0,\(a0\),v0.t'
++.*Error: illegal operands `vlseg8e8ff.v v0,\(a0\),v0.t'
++.*Error: illegal operands `vlseg2e16.v v0,\(a0\),v0.t'
++.*Error: illegal operands `vsseg2e16.v v0,\(a0\),v0.t'
++.*Error: illegal operands `vlseg2e16ff.v v0,\(a0\),v0.t'
++.*Error: illegal operands `vlseg3e16.v v0,\(a0\),v0.t'
++.*Error: illegal operands `vsseg3e16.v v0,\(a0\),v0.t'
++.*Error: illegal operands `vlseg3e16ff.v v0,\(a0\),v0.t'
++.*Error: illegal operands `vlseg4e16.v v0,\(a0\),v0.t'
++.*Error: illegal operands `vsseg4e16.v v0,\(a0\),v0.t'
++.*Error: illegal operands `vlseg4e16ff.v v0,\(a0\),v0.t'
++.*Error: illegal operands `vlseg5e16.v v0,\(a0\),v0.t'
++.*Error: illegal operands `vsseg5e16.v v0,\(a0\),v0.t'
++.*Error: illegal operands `vlseg5e16ff.v v0,\(a0\),v0.t'
++.*Error: illegal operands `vlseg6e16.v v0,\(a0\),v0.t'
++.*Error: illegal operands `vsseg6e16.v v0,\(a0\),v0.t'
++.*Error: illegal operands `vlseg6e16ff.v v0,\(a0\),v0.t'
++.*Error: illegal operands `vlseg7e16.v v0,\(a0\),v0.t'
++.*Error: illegal operands `vsseg7e16.v v0,\(a0\),v0.t'
++.*Error: illegal operands `vlseg7e16ff.v v0,\(a0\),v0.t'
++.*Error: illegal operands `vlseg8e16.v v0,\(a0\),v0.t'
++.*Error: illegal operands `vsseg8e16.v v0,\(a0\),v0.t'
++.*Error: illegal operands `vlseg8e16ff.v v0,\(a0\),v0.t'
++.*Error: illegal operands `vlseg2e32.v v0,\(a0\),v0.t'
++.*Error: illegal operands `vsseg2e32.v v0,\(a0\),v0.t'
++.*Error: illegal operands `vlseg2e32ff.v v0,\(a0\),v0.t'
++.*Error: illegal operands `vlseg3e32.v v0,\(a0\),v0.t'
++.*Error: illegal operands `vsseg3e32.v v0,\(a0\),v0.t'
++.*Error: illegal operands `vlseg3e32ff.v v0,\(a0\),v0.t'
++.*Error: illegal operands `vlseg4e32.v v0,\(a0\),v0.t'
++.*Error: illegal operands `vsseg4e32.v v0,\(a0\),v0.t'
++.*Error: illegal operands `vlseg4e32ff.v v0,\(a0\),v0.t'
++.*Error: illegal operands `vlseg5e32.v v0,\(a0\),v0.t'
++.*Error: illegal operands `vsseg5e32.v v0,\(a0\),v0.t'
++.*Error: illegal operands `vlseg5e32ff.v v0,\(a0\),v0.t'
++.*Error: illegal operands `vlseg6e32.v v0,\(a0\),v0.t'
++.*Error: illegal operands `vsseg6e32.v v0,\(a0\),v0.t'
++.*Error: illegal operands `vlseg6e32ff.v v0,\(a0\),v0.t'
++.*Error: illegal operands `vlseg7e32.v v0,\(a0\),v0.t'
++.*Error: illegal operands `vsseg7e32.v v0,\(a0\),v0.t'
++.*Error: illegal operands `vlseg7e32ff.v v0,\(a0\),v0.t'
++.*Error: illegal operands `vlseg8e32.v v0,\(a0\),v0.t'
++.*Error: illegal operands `vsseg8e32.v v0,\(a0\),v0.t'
++.*Error: illegal operands `vlseg8e32ff.v v0,\(a0\),v0.t'
++.*Error: illegal operands `vlseg2e64.v v0,\(a0\),v0.t'
++.*Error: illegal operands `vsseg2e64.v v0,\(a0\),v0.t'
++.*Error: illegal operands `vlseg2e64ff.v v0,\(a0\),v0.t'
++.*Error: illegal operands `vlseg3e64.v v0,\(a0\),v0.t'
++.*Error: illegal operands `vsseg3e64.v v0,\(a0\),v0.t'
++.*Error: illegal operands `vlseg3e64ff.v v0,\(a0\),v0.t'
++.*Error: illegal operands `vlseg4e64.v v0,\(a0\),v0.t'
++.*Error: illegal operands `vsseg4e64.v v0,\(a0\),v0.t'
++.*Error: illegal operands `vlseg4e64ff.v v0,\(a0\),v0.t'
++.*Error: illegal operands `vlseg5e64.v v0,\(a0\),v0.t'
++.*Error: illegal operands `vsseg5e64.v v0,\(a0\),v0.t'
++.*Error: illegal operands `vlseg5e64ff.v v0,\(a0\),v0.t'
++.*Error: illegal operands `vlseg6e64.v v0,\(a0\),v0.t'
++.*Error: illegal operands `vsseg6e64.v v0,\(a0\),v0.t'
++.*Error: illegal operands `vlseg6e64ff.v v0,\(a0\),v0.t'
++.*Error: illegal operands `vlseg7e64.v v0,\(a0\),v0.t'
++.*Error: illegal operands `vsseg7e64.v v0,\(a0\),v0.t'
++.*Error: illegal operands `vlseg7e64ff.v v0,\(a0\),v0.t'
++.*Error: illegal operands `vlseg8e64.v v0,\(a0\),v0.t'
++.*Error: illegal operands `vsseg8e64.v v0,\(a0\),v0.t'
++.*Error: illegal operands `vlseg8e64ff.v v0,\(a0\),v0.t'
++.*Error: illegal operands `vlseg2e128.v v0,\(a0\),v0.t'
++.*Error: illegal operands `vsseg2e128.v v0,\(a0\),v0.t'
++.*Error: illegal operands `vlseg2e128ff.v v0,\(a0\),v0.t'
++.*Error: illegal operands `vlseg3e128.v v0,\(a0\),v0.t'
++.*Error: illegal operands `vsseg3e128.v v0,\(a0\),v0.t'
++.*Error: illegal operands `vlseg3e128ff.v v0,\(a0\),v0.t'
++.*Error: illegal operands `vlseg4e128.v v0,\(a0\),v0.t'
++.*Error: illegal operands `vsseg4e128.v v0,\(a0\),v0.t'
++.*Error: illegal operands `vlseg4e128ff.v v0,\(a0\),v0.t'
++.*Error: illegal operands `vlseg5e128.v v0,\(a0\),v0.t'
++.*Error: illegal operands `vsseg5e128.v v0,\(a0\),v0.t'
++.*Error: illegal operands `vlseg5e128ff.v v0,\(a0\),v0.t'
++.*Error: illegal operands `vlseg6e128.v v0,\(a0\),v0.t'
++.*Error: illegal operands `vsseg6e128.v v0,\(a0\),v0.t'
++.*Error: illegal operands `vlseg6e128ff.v v0,\(a0\),v0.t'
++.*Error: illegal operands `vlseg7e128.v v0,\(a0\),v0.t'
++.*Error: illegal operands `vsseg7e128.v v0,\(a0\),v0.t'
++.*Error: illegal operands `vlseg7e128ff.v v0,\(a0\),v0.t'
++.*Error: illegal operands `vlseg8e128.v v0,\(a0\),v0.t'
++.*Error: illegal operands `vsseg8e128.v v0,\(a0\),v0.t'
++.*Error: illegal operands `vlseg8e128ff.v v0,\(a0\),v0.t'
++.*Error: illegal operands `vlseg2e256.v v0,\(a0\),v0.t'
++.*Error: illegal operands `vsseg2e256.v v0,\(a0\),v0.t'
++.*Error: illegal operands `vlseg2e256ff.v v0,\(a0\),v0.t'
++.*Error: illegal operands `vlseg3e256.v v0,\(a0\),v0.t'
++.*Error: illegal operands `vsseg3e256.v v0,\(a0\),v0.t'
++.*Error: illegal operands `vlseg3e256ff.v v0,\(a0\),v0.t'
++.*Error: illegal operands `vlseg4e256.v v0,\(a0\),v0.t'
++.*Error: illegal operands `vsseg4e256.v v0,\(a0\),v0.t'
++.*Error: illegal operands `vlseg4e256ff.v v0,\(a0\),v0.t'
++.*Error: illegal operands `vlseg5e256.v v0,\(a0\),v0.t'
++.*Error: illegal operands `vsseg5e256.v v0,\(a0\),v0.t'
++.*Error: illegal operands `vlseg5e256ff.v v0,\(a0\),v0.t'
++.*Error: illegal operands `vlseg6e256.v v0,\(a0\),v0.t'
++.*Error: illegal operands `vsseg6e256.v v0,\(a0\),v0.t'
++.*Error: illegal operands `vlseg6e256ff.v v0,\(a0\),v0.t'
++.*Error: illegal operands `vlseg7e256.v v0,\(a0\),v0.t'
++.*Error: illegal operands `vsseg7e256.v v0,\(a0\),v0.t'
++.*Error: illegal operands `vlseg7e256ff.v v0,\(a0\),v0.t'
++.*Error: illegal operands `vlseg8e256.v v0,\(a0\),v0.t'
++.*Error: illegal operands `vsseg8e256.v v0,\(a0\),v0.t'
++.*Error: illegal operands `vlseg8e256ff.v v0,\(a0\),v0.t'
++.*Error: illegal operands `vlseg2e512.v v0,\(a0\),v0.t'
++.*Error: illegal operands `vsseg2e512.v v0,\(a0\),v0.t'
++.*Error: illegal operands `vlseg2e512ff.v v0,\(a0\),v0.t'
++.*Error: illegal operands `vlseg3e512.v v0,\(a0\),v0.t'
++.*Error: illegal operands `vsseg3e512.v v0,\(a0\),v0.t'
++.*Error: illegal operands `vlseg3e512ff.v v0,\(a0\),v0.t'
++.*Error: illegal operands `vlseg4e512.v v0,\(a0\),v0.t'
++.*Error: illegal operands `vsseg4e512.v v0,\(a0\),v0.t'
++.*Error: illegal operands `vlseg4e512ff.v v0,\(a0\),v0.t'
++.*Error: illegal operands `vlseg5e512.v v0,\(a0\),v0.t'
++.*Error: illegal operands `vsseg5e512.v v0,\(a0\),v0.t'
++.*Error: illegal operands `vlseg5e512ff.v v0,\(a0\),v0.t'
++.*Error: illegal operands `vlseg6e512.v v0,\(a0\),v0.t'
++.*Error: illegal operands `vsseg6e512.v v0,\(a0\),v0.t'
++.*Error: illegal operands `vlseg6e512ff.v v0,\(a0\),v0.t'
++.*Error: illegal operands `vlseg7e512.v v0,\(a0\),v0.t'
++.*Error: illegal operands `vsseg7e512.v v0,\(a0\),v0.t'
++.*Error: illegal operands `vlseg7e512ff.v v0,\(a0\),v0.t'
++.*Error: illegal operands `vlseg8e512.v v0,\(a0\),v0.t'
++.*Error: illegal operands `vsseg8e512.v v0,\(a0\),v0.t'
++.*Error: illegal operands `vlseg8e512ff.v v0,\(a0\),v0.t'
++.*Error: illegal operands `vlseg2e1024.v v0,\(a0\),v0.t'
++.*Error: illegal operands `vsseg2e1024.v v0,\(a0\),v0.t'
++.*Error: illegal operands `vlseg2e1024ff.v v0,\(a0\),v0.t'
++.*Error: illegal operands `vlseg3e1024.v v0,\(a0\),v0.t'
++.*Error: illegal operands `vsseg3e1024.v v0,\(a0\),v0.t'
++.*Error: illegal operands `vlseg3e1024ff.v v0,\(a0\),v0.t'
++.*Error: illegal operands `vlseg4e1024.v v0,\(a0\),v0.t'
++.*Error: illegal operands `vsseg4e1024.v v0,\(a0\),v0.t'
++.*Error: illegal operands `vlseg4e1024ff.v v0,\(a0\),v0.t'
++.*Error: illegal operands `vlseg5e1024.v v0,\(a0\),v0.t'
++.*Error: illegal operands `vsseg5e1024.v v0,\(a0\),v0.t'
++.*Error: illegal operands `vlseg5e1024ff.v v0,\(a0\),v0.t'
++.*Error: illegal operands `vlseg6e1024.v v0,\(a0\),v0.t'
++.*Error: illegal operands `vsseg6e1024.v v0,\(a0\),v0.t'
++.*Error: illegal operands `vlseg6e1024ff.v v0,\(a0\),v0.t'
++.*Error: illegal operands `vlseg7e1024.v v0,\(a0\),v0.t'
++.*Error: illegal operands `vsseg7e1024.v v0,\(a0\),v0.t'
++.*Error: illegal operands `vlseg7e1024ff.v v0,\(a0\),v0.t'
++.*Error: illegal operands `vlseg8e1024.v v0,\(a0\),v0.t'
++.*Error: illegal operands `vsseg8e1024.v v0,\(a0\),v0.t'
++.*Error: illegal operands `vlseg8e1024ff.v v0,\(a0\),v0.t'
++.*Error: illegal operands `vlsseg2e8.v v0,\(a0\),a1,v0.t'
++.*Error: illegal operands `vssseg2e8.v v0,\(a0\),a1,v0.t'
++.*Error: illegal operands `vlsseg3e8.v v0,\(a0\),a1,v0.t'
++.*Error: illegal operands `vssseg3e8.v v0,\(a0\),a1,v0.t'
++.*Error: illegal operands `vlsseg4e8.v v0,\(a0\),a1,v0.t'
++.*Error: illegal operands `vssseg4e8.v v0,\(a0\),a1,v0.t'
++.*Error: illegal operands `vlsseg5e8.v v0,\(a0\),a1,v0.t'
++.*Error: illegal operands `vssseg5e8.v v0,\(a0\),a1,v0.t'
++.*Error: illegal operands `vlsseg6e8.v v0,\(a0\),a1,v0.t'
++.*Error: illegal operands `vssseg6e8.v v0,\(a0\),a1,v0.t'
++.*Error: illegal operands `vlsseg7e8.v v0,\(a0\),a1,v0.t'
++.*Error: illegal operands `vssseg7e8.v v0,\(a0\),a1,v0.t'
++.*Error: illegal operands `vlsseg8e8.v v0,\(a0\),a1,v0.t'
++.*Error: illegal operands `vssseg8e8.v v0,\(a0\),a1,v0.t'
++.*Error: illegal operands `vlsseg2e16.v v0,\(a0\),a1,v0.t'
++.*Error: illegal operands `vssseg2e16.v v0,\(a0\),a1,v0.t'
++.*Error: illegal operands `vlsseg3e16.v v0,\(a0\),a1,v0.t'
++.*Error: illegal operands `vssseg3e16.v v0,\(a0\),a1,v0.t'
++.*Error: illegal operands `vlsseg4e16.v v0,\(a0\),a1,v0.t'
++.*Error: illegal operands `vssseg4e16.v v0,\(a0\),a1,v0.t'
++.*Error: illegal operands `vlsseg5e16.v v0,\(a0\),a1,v0.t'
++.*Error: illegal operands `vssseg5e16.v v0,\(a0\),a1,v0.t'
++.*Error: illegal operands `vlsseg6e16.v v0,\(a0\),a1,v0.t'
++.*Error: illegal operands `vssseg6e16.v v0,\(a0\),a1,v0.t'
++.*Error: illegal operands `vlsseg7e16.v v0,\(a0\),a1,v0.t'
++.*Error: illegal operands `vssseg7e16.v v0,\(a0\),a1,v0.t'
++.*Error: illegal operands `vlsseg8e16.v v0,\(a0\),a1,v0.t'
++.*Error: illegal operands `vssseg8e16.v v0,\(a0\),a1,v0.t'
++.*Error: illegal operands `vlsseg2e32.v v0,\(a0\),a1,v0.t'
++.*Error: illegal operands `vssseg2e32.v v0,\(a0\),a1,v0.t'
++.*Error: illegal operands `vlsseg3e32.v v0,\(a0\),a1,v0.t'
++.*Error: illegal operands `vssseg3e32.v v0,\(a0\),a1,v0.t'
++.*Error: illegal operands `vlsseg4e32.v v0,\(a0\),a1,v0.t'
++.*Error: illegal operands `vssseg4e32.v v0,\(a0\),a1,v0.t'
++.*Error: illegal operands `vlsseg5e32.v v0,\(a0\),a1,v0.t'
++.*Error: illegal operands `vssseg5e32.v v0,\(a0\),a1,v0.t'
++.*Error: illegal operands `vlsseg6e32.v v0,\(a0\),a1,v0.t'
++.*Error: illegal operands `vssseg6e32.v v0,\(a0\),a1,v0.t'
++.*Error: illegal operands `vlsseg7e32.v v0,\(a0\),a1,v0.t'
++.*Error: illegal operands `vssseg7e32.v v0,\(a0\),a1,v0.t'
++.*Error: illegal operands `vlsseg8e32.v v0,\(a0\),a1,v0.t'
++.*Error: illegal operands `vssseg8e32.v v0,\(a0\),a1,v0.t'
++.*Error: illegal operands `vlsseg2e64.v v0,\(a0\),a1,v0.t'
++.*Error: illegal operands `vssseg2e64.v v0,\(a0\),a1,v0.t'
++.*Error: illegal operands `vlsseg3e64.v v0,\(a0\),a1,v0.t'
++.*Error: illegal operands `vssseg3e64.v v0,\(a0\),a1,v0.t'
++.*Error: illegal operands `vlsseg4e64.v v0,\(a0\),a1,v0.t'
++.*Error: illegal operands `vssseg4e64.v v0,\(a0\),a1,v0.t'
++.*Error: illegal operands `vlsseg5e64.v v0,\(a0\),a1,v0.t'
++.*Error: illegal operands `vssseg5e64.v v0,\(a0\),a1,v0.t'
++.*Error: illegal operands `vlsseg6e64.v v0,\(a0\),a1,v0.t'
++.*Error: illegal operands `vssseg6e64.v v0,\(a0\),a1,v0.t'
++.*Error: illegal operands `vlsseg7e64.v v0,\(a0\),a1,v0.t'
++.*Error: illegal operands `vssseg7e64.v v0,\(a0\),a1,v0.t'
++.*Error: illegal operands `vlsseg8e64.v v0,\(a0\),a1,v0.t'
++.*Error: illegal operands `vssseg8e64.v v0,\(a0\),a1,v0.t'
++.*Error: illegal operands `vlsseg2e128.v v0,\(a0\),a1,v0.t'
++.*Error: illegal operands `vssseg2e128.v v0,\(a0\),a1,v0.t'
++.*Error: illegal operands `vlsseg3e128.v v0,\(a0\),a1,v0.t'
++.*Error: illegal operands `vssseg3e128.v v0,\(a0\),a1,v0.t'
++.*Error: illegal operands `vlsseg4e128.v v0,\(a0\),a1,v0.t'
++.*Error: illegal operands `vssseg4e128.v v0,\(a0\),a1,v0.t'
++.*Error: illegal operands `vlsseg5e128.v v0,\(a0\),a1,v0.t'
++.*Error: illegal operands `vssseg5e128.v v0,\(a0\),a1,v0.t'
++.*Error: illegal operands `vlsseg6e128.v v0,\(a0\),a1,v0.t'
++.*Error: illegal operands `vssseg6e128.v v0,\(a0\),a1,v0.t'
++.*Error: illegal operands `vlsseg7e128.v v0,\(a0\),a1,v0.t'
++.*Error: illegal operands `vssseg7e128.v v0,\(a0\),a1,v0.t'
++.*Error: illegal operands `vlsseg8e128.v v0,\(a0\),a1,v0.t'
++.*Error: illegal operands `vssseg8e128.v v0,\(a0\),a1,v0.t'
++.*Error: illegal operands `vlsseg2e256.v v0,\(a0\),a1,v0.t'
++.*Error: illegal operands `vssseg2e256.v v0,\(a0\),a1,v0.t'
++.*Error: illegal operands `vlsseg3e256.v v0,\(a0\),a1,v0.t'
++.*Error: illegal operands `vssseg3e256.v v0,\(a0\),a1,v0.t'
++.*Error: illegal operands `vlsseg4e256.v v0,\(a0\),a1,v0.t'
++.*Error: illegal operands `vssseg4e256.v v0,\(a0\),a1,v0.t'
++.*Error: illegal operands `vlsseg5e256.v v0,\(a0\),a1,v0.t'
++.*Error: illegal operands `vssseg5e256.v v0,\(a0\),a1,v0.t'
++.*Error: illegal operands `vlsseg6e256.v v0,\(a0\),a1,v0.t'
++.*Error: illegal operands `vssseg6e256.v v0,\(a0\),a1,v0.t'
++.*Error: illegal operands `vlsseg7e256.v v0,\(a0\),a1,v0.t'
++.*Error: illegal operands `vssseg7e256.v v0,\(a0\),a1,v0.t'
++.*Error: illegal operands `vlsseg8e256.v v0,\(a0\),a1,v0.t'
++.*Error: illegal operands `vssseg8e256.v v0,\(a0\),a1,v0.t'
++.*Error: illegal operands `vlsseg2e512.v v0,\(a0\),a1,v0.t'
++.*Error: illegal operands `vssseg2e512.v v0,\(a0\),a1,v0.t'
++.*Error: illegal operands `vlsseg3e512.v v0,\(a0\),a1,v0.t'
++.*Error: illegal operands `vssseg3e512.v v0,\(a0\),a1,v0.t'
++.*Error: illegal operands `vlsseg4e512.v v0,\(a0\),a1,v0.t'
++.*Error: illegal operands `vssseg4e512.v v0,\(a0\),a1,v0.t'
++.*Error: illegal operands `vlsseg5e512.v v0,\(a0\),a1,v0.t'
++.*Error: illegal operands `vssseg5e512.v v0,\(a0\),a1,v0.t'
++.*Error: illegal operands `vlsseg6e512.v v0,\(a0\),a1,v0.t'
++.*Error: illegal operands `vssseg6e512.v v0,\(a0\),a1,v0.t'
++.*Error: illegal operands `vlsseg7e512.v v0,\(a0\),a1,v0.t'
++.*Error: illegal operands `vssseg7e512.v v0,\(a0\),a1,v0.t'
++.*Error: illegal operands `vlsseg8e512.v v0,\(a0\),a1,v0.t'
++.*Error: illegal operands `vssseg8e512.v v0,\(a0\),a1,v0.t'
++.*Error: illegal operands `vlsseg2e1024.v v0,\(a0\),a1,v0.t'
++.*Error: illegal operands `vssseg2e1024.v v0,\(a0\),a1,v0.t'
++.*Error: illegal operands `vlsseg3e1024.v v0,\(a0\),a1,v0.t'
++.*Error: illegal operands `vssseg3e1024.v v0,\(a0\),a1,v0.t'
++.*Error: illegal operands `vlsseg4e1024.v v0,\(a0\),a1,v0.t'
++.*Error: illegal operands `vssseg4e1024.v v0,\(a0\),a1,v0.t'
++.*Error: illegal operands `vlsseg5e1024.v v0,\(a0\),a1,v0.t'
++.*Error: illegal operands `vssseg5e1024.v v0,\(a0\),a1,v0.t'
++.*Error: illegal operands `vlsseg6e1024.v v0,\(a0\),a1,v0.t'
++.*Error: illegal operands `vssseg6e1024.v v0,\(a0\),a1,v0.t'
++.*Error: illegal operands `vlsseg7e1024.v v0,\(a0\),a1,v0.t'
++.*Error: illegal operands `vssseg7e1024.v v0,\(a0\),a1,v0.t'
++.*Error: illegal operands `vlsseg8e1024.v v0,\(a0\),a1,v0.t'
++.*Error: illegal operands `vssseg8e1024.v v0,\(a0\),a1,v0.t'
++.*Error: illegal operands `vlxseg2ei8.v v4,\(a0\),v4'
++.*Error: illegal operands `vlxseg2ei8.v v0,\(a0\),v4,v0.t'
++.*Error: illegal operands `vsxseg2ei8.v v4,\(a0\),v4'
++.*Error: illegal operands `vsxseg2ei8.v v0,\(a0\),v4,v0.t'
++.*Error: illegal operands `vlxseg3ei8.v v4,\(a0\),v4'
++.*Error: illegal operands `vlxseg3ei8.v v0,\(a0\),v4,v0.t'
++.*Error: illegal operands `vsxseg3ei8.v v4,\(a0\),v4'
++.*Error: illegal operands `vsxseg3ei8.v v0,\(a0\),v4,v0.t'
++.*Error: illegal operands `vlxseg4ei8.v v4,\(a0\),v4'
++.*Error: illegal operands `vlxseg4ei8.v v0,\(a0\),v4,v0.t'
++.*Error: illegal operands `vsxseg4ei8.v v4,\(a0\),v4'
++.*Error: illegal operands `vsxseg4ei8.v v0,\(a0\),v4,v0.t'
++.*Error: illegal operands `vlxseg5ei8.v v4,\(a0\),v4'
++.*Error: illegal operands `vlxseg5ei8.v v0,\(a0\),v4,v0.t'
++.*Error: illegal operands `vsxseg5ei8.v v4,\(a0\),v4'
++.*Error: illegal operands `vsxseg5ei8.v v0,\(a0\),v4,v0.t'
++.*Error: illegal operands `vlxseg6ei8.v v4,\(a0\),v4'
++.*Error: illegal operands `vlxseg6ei8.v v0,\(a0\),v4,v0.t'
++.*Error: illegal operands `vsxseg6ei8.v v4,\(a0\),v4'
++.*Error: illegal operands `vsxseg6ei8.v v0,\(a0\),v4,v0.t'
++.*Error: illegal operands `vlxseg7ei8.v v4,\(a0\),v4'
++.*Error: illegal operands `vlxseg7ei8.v v0,\(a0\),v4,v0.t'
++.*Error: illegal operands `vsxseg7ei8.v v4,\(a0\),v4'
++.*Error: illegal operands `vsxseg7ei8.v v0,\(a0\),v4,v0.t'
++.*Error: illegal operands `vlxseg8ei8.v v4,\(a0\),v4'
++.*Error: illegal operands `vlxseg8ei8.v v0,\(a0\),v4,v0.t'
++.*Error: illegal operands `vsxseg8ei8.v v4,\(a0\),v4'
++.*Error: illegal operands `vsxseg8ei8.v v0,\(a0\),v4,v0.t'
++.*Error: illegal operands `vlxseg2ei16.v v4,\(a0\),v4'
++.*Error: illegal operands `vlxseg2ei16.v v0,\(a0\),v4,v0.t'
++.*Error: illegal operands `vsxseg2ei16.v v4,\(a0\),v4'
++.*Error: illegal operands `vsxseg2ei16.v v0,\(a0\),v4,v0.t'
++.*Error: illegal operands `vlxseg3ei16.v v4,\(a0\),v4'
++.*Error: illegal operands `vlxseg3ei16.v v0,\(a0\),v4,v0.t'
++.*Error: illegal operands `vsxseg3ei16.v v4,\(a0\),v4'
++.*Error: illegal operands `vsxseg3ei16.v v0,\(a0\),v4,v0.t'
++.*Error: illegal operands `vlxseg4ei16.v v4,\(a0\),v4'
++.*Error: illegal operands `vlxseg4ei16.v v0,\(a0\),v4,v0.t'
++.*Error: illegal operands `vsxseg4ei16.v v4,\(a0\),v4'
++.*Error: illegal operands `vsxseg4ei16.v v0,\(a0\),v4,v0.t'
++.*Error: illegal operands `vlxseg5ei16.v v4,\(a0\),v4'
++.*Error: illegal operands `vlxseg5ei16.v v0,\(a0\),v4,v0.t'
++.*Error: illegal operands `vsxseg5ei16.v v4,\(a0\),v4'
++.*Error: illegal operands `vsxseg5ei16.v v0,\(a0\),v4,v0.t'
++.*Error: illegal operands `vlxseg6ei16.v v4,\(a0\),v4'
++.*Error: illegal operands `vlxseg6ei16.v v0,\(a0\),v4,v0.t'
++.*Error: illegal operands `vsxseg6ei16.v v4,\(a0\),v4'
++.*Error: illegal operands `vsxseg6ei16.v v0,\(a0\),v4,v0.t'
++.*Error: illegal operands `vlxseg7ei16.v v4,\(a0\),v4'
++.*Error: illegal operands `vlxseg7ei16.v v0,\(a0\),v4,v0.t'
++.*Error: illegal operands `vsxseg7ei16.v v4,\(a0\),v4'
++.*Error: illegal operands `vsxseg7ei16.v v0,\(a0\),v4,v0.t'
++.*Error: illegal operands `vlxseg8ei16.v v4,\(a0\),v4'
++.*Error: illegal operands `vlxseg8ei16.v v0,\(a0\),v4,v0.t'
++.*Error: illegal operands `vsxseg8ei16.v v4,\(a0\),v4'
++.*Error: illegal operands `vsxseg8ei16.v v0,\(a0\),v4,v0.t'
++.*Error: illegal operands `vlxseg2ei32.v v4,\(a0\),v4'
++.*Error: illegal operands `vlxseg2ei32.v v0,\(a0\),v4,v0.t'
++.*Error: illegal operands `vsxseg2ei32.v v4,\(a0\),v4'
++.*Error: illegal operands `vsxseg2ei32.v v0,\(a0\),v4,v0.t'
++.*Error: illegal operands `vlxseg3ei32.v v4,\(a0\),v4'
++.*Error: illegal operands `vlxseg3ei32.v v0,\(a0\),v4,v0.t'
++.*Error: illegal operands `vsxseg3ei32.v v4,\(a0\),v4'
++.*Error: illegal operands `vsxseg3ei32.v v0,\(a0\),v4,v0.t'
++.*Error: illegal operands `vlxseg4ei32.v v4,\(a0\),v4'
++.*Error: illegal operands `vlxseg4ei32.v v0,\(a0\),v4,v0.t'
++.*Error: illegal operands `vsxseg4ei32.v v4,\(a0\),v4'
++.*Error: illegal operands `vsxseg4ei32.v v0,\(a0\),v4,v0.t'
++.*Error: illegal operands `vlxseg5ei32.v v4,\(a0\),v4'
++.*Error: illegal operands `vlxseg5ei32.v v0,\(a0\),v4,v0.t'
++.*Error: illegal operands `vsxseg5ei32.v v4,\(a0\),v4'
++.*Error: illegal operands `vsxseg5ei32.v v0,\(a0\),v4,v0.t'
++.*Error: illegal operands `vlxseg6ei32.v v4,\(a0\),v4'
++.*Error: illegal operands `vlxseg6ei32.v v0,\(a0\),v4,v0.t'
++.*Error: illegal operands `vsxseg6ei32.v v4,\(a0\),v4'
++.*Error: illegal operands `vsxseg6ei32.v v0,\(a0\),v4,v0.t'
++.*Error: illegal operands `vlxseg7ei32.v v4,\(a0\),v4'
++.*Error: illegal operands `vlxseg7ei32.v v0,\(a0\),v4,v0.t'
++.*Error: illegal operands `vsxseg7ei32.v v4,\(a0\),v4'
++.*Error: illegal operands `vsxseg7ei32.v v0,\(a0\),v4,v0.t'
++.*Error: illegal operands `vlxseg8ei32.v v4,\(a0\),v4'
++.*Error: illegal operands `vlxseg8ei32.v v0,\(a0\),v4,v0.t'
++.*Error: illegal operands `vsxseg8ei32.v v4,\(a0\),v4'
++.*Error: illegal operands `vsxseg8ei32.v v0,\(a0\),v4,v0.t'
++.*Error: illegal operands `vlxseg2ei64.v v4,\(a0\),v4'
++.*Error: illegal operands `vlxseg2ei64.v v0,\(a0\),v4,v0.t'
++.*Error: illegal operands `vsxseg2ei64.v v4,\(a0\),v4'
++.*Error: illegal operands `vsxseg2ei64.v v0,\(a0\),v4,v0.t'
++.*Error: illegal operands `vlxseg3ei64.v v4,\(a0\),v4'
++.*Error: illegal operands `vlxseg3ei64.v v0,\(a0\),v4,v0.t'
++.*Error: illegal operands `vsxseg3ei64.v v4,\(a0\),v4'
++.*Error: illegal operands `vsxseg3ei64.v v0,\(a0\),v4,v0.t'
++.*Error: illegal operands `vlxseg4ei64.v v4,\(a0\),v4'
++.*Error: illegal operands `vlxseg4ei64.v v0,\(a0\),v4,v0.t'
++.*Error: illegal operands `vsxseg4ei64.v v4,\(a0\),v4'
++.*Error: illegal operands `vsxseg4ei64.v v0,\(a0\),v4,v0.t'
++.*Error: illegal operands `vlxseg5ei64.v v4,\(a0\),v4'
++.*Error: illegal operands `vlxseg5ei64.v v0,\(a0\),v4,v0.t'
++.*Error: illegal operands `vsxseg5ei64.v v4,\(a0\),v4'
++.*Error: illegal operands `vsxseg5ei64.v v0,\(a0\),v4,v0.t'
++.*Error: illegal operands `vlxseg6ei64.v v4,\(a0\),v4'
++.*Error: illegal operands `vlxseg6ei64.v v0,\(a0\),v4,v0.t'
++.*Error: illegal operands `vsxseg6ei64.v v4,\(a0\),v4'
++.*Error: illegal operands `vsxseg6ei64.v v0,\(a0\),v4,v0.t'
++.*Error: illegal operands `vlxseg7ei64.v v4,\(a0\),v4'
++.*Error: illegal operands `vlxseg7ei64.v v0,\(a0\),v4,v0.t'
++.*Error: illegal operands `vsxseg7ei64.v v4,\(a0\),v4'
++.*Error: illegal operands `vsxseg7ei64.v v0,\(a0\),v4,v0.t'
++.*Error: illegal operands `vlxseg8ei64.v v4,\(a0\),v4'
++.*Error: illegal operands `vlxseg8ei64.v v0,\(a0\),v4,v0.t'
++.*Error: illegal operands `vsxseg8ei64.v v4,\(a0\),v4'
++.*Error: illegal operands `vsxseg8ei64.v v0,\(a0\),v4,v0.t'
++.*Error: illegal operands `vlxseg2ei128.v v4,\(a0\),v4'
++.*Error: illegal operands `vlxseg2ei128.v v0,\(a0\),v4,v0.t'
++.*Error: illegal operands `vsxseg2ei128.v v4,\(a0\),v4'
++.*Error: illegal operands `vsxseg2ei128.v v0,\(a0\),v4,v0.t'
++.*Error: illegal operands `vlxseg3ei128.v v4,\(a0\),v4'
++.*Error: illegal operands `vlxseg3ei128.v v0,\(a0\),v4,v0.t'
++.*Error: illegal operands `vsxseg3ei128.v v4,\(a0\),v4'
++.*Error: illegal operands `vsxseg3ei128.v v0,\(a0\),v4,v0.t'
++.*Error: illegal operands `vlxseg4ei128.v v4,\(a0\),v4'
++.*Error: illegal operands `vlxseg4ei128.v v0,\(a0\),v4,v0.t'
++.*Error: illegal operands `vsxseg4ei128.v v4,\(a0\),v4'
++.*Error: illegal operands `vsxseg4ei128.v v0,\(a0\),v4,v0.t'
++.*Error: illegal operands `vlxseg5ei128.v v4,\(a0\),v4'
++.*Error: illegal operands `vlxseg5ei128.v v0,\(a0\),v4,v0.t'
++.*Error: illegal operands `vsxseg5ei128.v v4,\(a0\),v4'
++.*Error: illegal operands `vsxseg5ei128.v v0,\(a0\),v4,v0.t'
++.*Error: illegal operands `vlxseg6ei128.v v4,\(a0\),v4'
++.*Error: illegal operands `vlxseg6ei128.v v0,\(a0\),v4,v0.t'
++.*Error: illegal operands `vsxseg6ei128.v v4,\(a0\),v4'
++.*Error: illegal operands `vsxseg6ei128.v v0,\(a0\),v4,v0.t'
++.*Error: illegal operands `vlxseg7ei128.v v4,\(a0\),v4'
++.*Error: illegal operands `vlxseg7ei128.v v0,\(a0\),v4,v0.t'
++.*Error: illegal operands `vsxseg7ei128.v v4,\(a0\),v4'
++.*Error: illegal operands `vsxseg7ei128.v v0,\(a0\),v4,v0.t'
++.*Error: illegal operands `vlxseg8ei128.v v4,\(a0\),v4'
++.*Error: illegal operands `vlxseg8ei128.v v0,\(a0\),v4,v0.t'
++.*Error: illegal operands `vsxseg8ei128.v v4,\(a0\),v4'
++.*Error: illegal operands `vsxseg8ei128.v v0,\(a0\),v4,v0.t'
++.*Error: illegal operands `vlxseg2ei256.v v4,\(a0\),v4'
++.*Error: illegal operands `vlxseg2ei256.v v0,\(a0\),v4,v0.t'
++.*Error: illegal operands `vsxseg2ei256.v v4,\(a0\),v4'
++.*Error: illegal operands `vsxseg2ei256.v v0,\(a0\),v4,v0.t'
++.*Error: illegal operands `vlxseg3ei256.v v4,\(a0\),v4'
++.*Error: illegal operands `vlxseg3ei256.v v0,\(a0\),v4,v0.t'
++.*Error: illegal operands `vsxseg3ei256.v v4,\(a0\),v4'
++.*Error: illegal operands `vsxseg3ei256.v v0,\(a0\),v4,v0.t'
++.*Error: illegal operands `vlxseg4ei256.v v4,\(a0\),v4'
++.*Error: illegal operands `vlxseg4ei256.v v0,\(a0\),v4,v0.t'
++.*Error: illegal operands `vsxseg4ei256.v v4,\(a0\),v4'
++.*Error: illegal operands `vsxseg4ei256.v v0,\(a0\),v4,v0.t'
++.*Error: illegal operands `vlxseg5ei256.v v4,\(a0\),v4'
++.*Error: illegal operands `vlxseg5ei256.v v0,\(a0\),v4,v0.t'
++.*Error: illegal operands `vsxseg5ei256.v v4,\(a0\),v4'
++.*Error: illegal operands `vsxseg5ei256.v v0,\(a0\),v4,v0.t'
++.*Error: illegal operands `vlxseg6ei256.v v4,\(a0\),v4'
++.*Error: illegal operands `vlxseg6ei256.v v0,\(a0\),v4,v0.t'
++.*Error: illegal operands `vsxseg6ei256.v v4,\(a0\),v4'
++.*Error: illegal operands `vsxseg6ei256.v v0,\(a0\),v4,v0.t'
++.*Error: illegal operands `vlxseg7ei256.v v4,\(a0\),v4'
++.*Error: illegal operands `vlxseg7ei256.v v0,\(a0\),v4,v0.t'
++.*Error: illegal operands `vsxseg7ei256.v v4,\(a0\),v4'
++.*Error: illegal operands `vsxseg7ei256.v v0,\(a0\),v4,v0.t'
++.*Error: illegal operands `vlxseg8ei256.v v4,\(a0\),v4'
++.*Error: illegal operands `vlxseg8ei256.v v0,\(a0\),v4,v0.t'
++.*Error: illegal operands `vsxseg8ei256.v v4,\(a0\),v4'
++.*Error: illegal operands `vsxseg8ei256.v v0,\(a0\),v4,v0.t'
++.*Error: illegal operands `vlxseg2ei512.v v4,\(a0\),v4'
++.*Error: illegal operands `vlxseg2ei512.v v0,\(a0\),v4,v0.t'
++.*Error: illegal operands `vsxseg2ei512.v v4,\(a0\),v4'
++.*Error: illegal operands `vsxseg2ei512.v v0,\(a0\),v4,v0.t'
++.*Error: illegal operands `vlxseg3ei512.v v4,\(a0\),v4'
++.*Error: illegal operands `vlxseg3ei512.v v0,\(a0\),v4,v0.t'
++.*Error: illegal operands `vsxseg3ei512.v v4,\(a0\),v4'
++.*Error: illegal operands `vsxseg3ei512.v v0,\(a0\),v4,v0.t'
++.*Error: illegal operands `vlxseg4ei512.v v4,\(a0\),v4'
++.*Error: illegal operands `vlxseg4ei512.v v0,\(a0\),v4,v0.t'
++.*Error: illegal operands `vsxseg4ei512.v v4,\(a0\),v4'
++.*Error: illegal operands `vsxseg4ei512.v v0,\(a0\),v4,v0.t'
++.*Error: illegal operands `vlxseg5ei512.v v4,\(a0\),v4'
++.*Error: illegal operands `vlxseg5ei512.v v0,\(a0\),v4,v0.t'
++.*Error: illegal operands `vsxseg5ei512.v v4,\(a0\),v4'
++.*Error: illegal operands `vsxseg5ei512.v v0,\(a0\),v4,v0.t'
++.*Error: illegal operands `vlxseg6ei512.v v4,\(a0\),v4'
++.*Error: illegal operands `vlxseg6ei512.v v0,\(a0\),v4,v0.t'
++.*Error: illegal operands `vsxseg6ei512.v v4,\(a0\),v4'
++.*Error: illegal operands `vsxseg6ei512.v v0,\(a0\),v4,v0.t'
++.*Error: illegal operands `vlxseg7ei512.v v4,\(a0\),v4'
++.*Error: illegal operands `vlxseg7ei512.v v0,\(a0\),v4,v0.t'
++.*Error: illegal operands `vsxseg7ei512.v v4,\(a0\),v4'
++.*Error: illegal operands `vsxseg7ei512.v v0,\(a0\),v4,v0.t'
++.*Error: illegal operands `vlxseg8ei512.v v4,\(a0\),v4'
++.*Error: illegal operands `vlxseg8ei512.v v0,\(a0\),v4,v0.t'
++.*Error: illegal operands `vsxseg8ei512.v v4,\(a0\),v4'
++.*Error: illegal operands `vsxseg8ei512.v v0,\(a0\),v4,v0.t'
++.*Error: illegal operands `vlxseg2ei1024.v v4,\(a0\),v4'
++.*Error: illegal operands `vlxseg2ei1024.v v0,\(a0\),v4,v0.t'
++.*Error: illegal operands `vsxseg2ei1024.v v4,\(a0\),v4'
++.*Error: illegal operands `vsxseg2ei1024.v v0,\(a0\),v4,v0.t'
++.*Error: illegal operands `vlxseg3ei1024.v v4,\(a0\),v4'
++.*Error: illegal operands `vlxseg3ei1024.v v0,\(a0\),v4,v0.t'
++.*Error: illegal operands `vsxseg3ei1024.v v4,\(a0\),v4'
++.*Error: illegal operands `vsxseg3ei1024.v v0,\(a0\),v4,v0.t'
++.*Error: illegal operands `vlxseg4ei1024.v v4,\(a0\),v4'
++.*Error: illegal operands `vlxseg4ei1024.v v0,\(a0\),v4,v0.t'
++.*Error: illegal operands `vsxseg4ei1024.v v4,\(a0\),v4'
++.*Error: illegal operands `vsxseg4ei1024.v v0,\(a0\),v4,v0.t'
++.*Error: illegal operands `vlxseg5ei1024.v v4,\(a0\),v4'
++.*Error: illegal operands `vlxseg5ei1024.v v0,\(a0\),v4,v0.t'
++.*Error: illegal operands `vsxseg5ei1024.v v4,\(a0\),v4'
++.*Error: illegal operands `vsxseg5ei1024.v v0,\(a0\),v4,v0.t'
++.*Error: illegal operands `vlxseg6ei1024.v v4,\(a0\),v4'
++.*Error: illegal operands `vlxseg6ei1024.v v0,\(a0\),v4,v0.t'
++.*Error: illegal operands `vsxseg6ei1024.v v4,\(a0\),v4'
++.*Error: illegal operands `vsxseg6ei1024.v v0,\(a0\),v4,v0.t'
++.*Error: illegal operands `vlxseg7ei1024.v v4,\(a0\),v4'
++.*Error: illegal operands `vlxseg7ei1024.v v0,\(a0\),v4,v0.t'
++.*Error: illegal operands `vsxseg7ei1024.v v4,\(a0\),v4'
++.*Error: illegal operands `vsxseg7ei1024.v v0,\(a0\),v4,v0.t'
++.*Error: illegal operands `vlxseg8ei1024.v v4,\(a0\),v4'
++.*Error: illegal operands `vlxseg8ei1024.v v0,\(a0\),v4,v0.t'
++.*Error: illegal operands `vsxseg8ei1024.v v4,\(a0\),v4'
++.*Error: illegal operands `vsxseg8ei1024.v v0,\(a0\),v4,v0.t'
+diff --git a/gas/testsuite/gas/riscv/vector-insns-fail-load-store.s b/gas/testsuite/gas/riscv/vector-insns-fail-load-store.s
+new file mode 100644
+index 0000000000..05f9358aed
+--- /dev/null
++++ b/gas/testsuite/gas/riscv/vector-insns-fail-load-store.s
+@@ -0,0 +1,610 @@
++# Vector Unit-Stride Loads and Stores
++
++	vle8.v v0, (a0), v0.t		# vd overlap vm
++	vle8ff.v v0, (a0), v0.t		# vd overlap vm
++	vle16.v v0, (a0), v0.t
++	vle16ff.v v0, (a0), v0.t
++	vle32.v v0, (a0), v0.t
++	vle32ff.v v0, (a0), v0.t
++	vle64.v v0, (a0), v0.t
++	vle64ff.v v0, (a0), v0.t
++	vle128.v v0, (a0), v0.t
++	vle128ff.v v0, (a0), v0.t
++	vle256.v v0, (a0), v0.t
++	vle256ff.v v0, (a0), v0.t
++	vle512.v v0, (a0), v0.t
++	vle512ff.v v0, (a0), v0.t
++	vle1024.v v0, (a0), v0.t
++	vle1024ff.v v0, (a0), v0.t
++
++	vse8.v v0, (a0), v0.t		# vd overlap vm
++	vse16.v v0, (a0), v0.t
++	vse32.v v0, (a0), v0.t
++	vse64.v v0, (a0), v0.t
++	vse128.v v0, (a0), v0.t
++	vse256.v v0, (a0), v0.t
++	vse512.v v0, (a0), v0.t
++	vse1024.v v0, (a0), v0.t
++
++# Vector Strided Loads and Stores
++
++	vlse8.v v0, (a0), a1, v0.t	# vd overlap vm
++	vlse16.v v0, (a0), a1, v0.t
++	vlse32.v v0, (a0), a1, v0.t
++	vlse64.v v0, (a0), a1, v0.t
++	vlse128.v v0, (a0), a1, v0.t
++	vlse256.v v0, (a0), a1, v0.t
++	vlse512.v v0, (a0), a1, v0.t
++	vlse1024.v v0, (a0), a1, v0.t
++
++	vsse8.v v0, (a0), a1, v0.t
++	vsse16.v v0, (a0), a1, v0.t
++	vsse32.v v0, (a0), a1, v0.t
++	vsse64.v v0, (a0), a1, v0.t
++	vsse128.v v0, (a0), a1, v0.t
++	vsse256.v v0, (a0), a1, v0.t
++	vsse512.v v0, (a0), a1, v0.t
++	vsse1024.v v0, (a0), a1, v0.t
++
++# Vector Indexed Loads and Stores
++
++	vlxei8.v v4, (a0), v4		# OK
++	vlxei8.v v0, (a0), v4, v0.t	# vd overlap vm
++	vlxei16.v v4, (a0), v4
++	vlxei16.v v0, (a0), v4, v0.t
++	vlxei32.v v4, (a0), v4
++	vlxei32.v v0, (a0), v4, v0.t
++	vlxei64.v v4, (a0), v4
++	vlxei64.v v0, (a0), v4, v0.t
++
++	vsxei8.v v4, (a0), v4
++	vsxei8.v v0, (a0), v4, v0.t
++	vsxei16.v v4, (a0), v4
++	vsxei16.v v0, (a0), v4, v0.t
++	vsxei32.v v4, (a0), v4
++	vsxei32.v v0, (a0), v4, v0.t
++	vsxei64.v v4, (a0), v4
++	vsxei64.v v0, (a0), v4, v0.t
++
++	vsuxei8.v v4, (a0), v4
++	vsuxei8.v v0, (a0), v4, v0.t
++	vsuxei16.v v4, (a0), v4
++	vsuxei16.v v0, (a0), v4, v0.t
++	vsuxei32.v v4, (a0), v4
++	vsuxei32.v v0, (a0), v4, v0.t
++	vsuxei64.v v4, (a0), v4
++	vsuxei64.v v0, (a0), v4, v0.t
++
++# Vector Unit-Stride Segment Loads and Stores
++
++	vlseg2e8.v v0, (a0), v0.t	# vd overlap vm
++	vsseg2e8.v v0, (a0), v0.t	# vd overlap vm
++	vlseg2e8ff.v v0, (a0), v0.t	# vd overlap vm
++	vlseg3e8.v v0, (a0), v0.t
++	vsseg3e8.v v0, (a0), v0.t
++	vlseg3e8ff.v v0, (a0), v0.t
++	vlseg4e8.v v0, (a0), v0.t
++	vsseg4e8.v v0, (a0), v0.t
++	vlseg4e8ff.v v0, (a0), v0.t
++	vlseg5e8.v v0, (a0), v0.t
++	vsseg5e8.v v0, (a0), v0.t
++	vlseg5e8ff.v v0, (a0), v0.t
++	vlseg6e8.v v0, (a0), v0.t
++	vsseg6e8.v v0, (a0), v0.t
++	vlseg6e8ff.v v0, (a0), v0.t
++	vlseg7e8.v v0, (a0), v0.t
++	vsseg7e8.v v0, (a0), v0.t
++	vlseg7e8ff.v v0, (a0), v0.t
++	vlseg8e8.v v0, (a0), v0.t
++	vsseg8e8.v v0, (a0), v0.t
++	vlseg8e8ff.v v0, (a0), v0.t
++
++	vlseg2e16.v v0, (a0), v0.t
++	vsseg2e16.v v0, (a0), v0.t
++	vlseg2e16ff.v v0, (a0), v0.t
++	vlseg3e16.v v0, (a0), v0.t
++	vsseg3e16.v v0, (a0), v0.t
++	vlseg3e16ff.v v0, (a0), v0.t
++	vlseg4e16.v v0, (a0), v0.t
++	vsseg4e16.v v0, (a0), v0.t
++	vlseg4e16ff.v v0, (a0), v0.t
++	vlseg5e16.v v0, (a0), v0.t
++	vsseg5e16.v v0, (a0), v0.t
++	vlseg5e16ff.v v0, (a0), v0.t
++	vlseg6e16.v v0, (a0), v0.t
++	vsseg6e16.v v0, (a0), v0.t
++	vlseg6e16ff.v v0, (a0), v0.t
++	vlseg7e16.v v0, (a0), v0.t
++	vsseg7e16.v v0, (a0), v0.t
++	vlseg7e16ff.v v0, (a0), v0.t
++	vlseg8e16.v v0, (a0), v0.t
++	vsseg8e16.v v0, (a0), v0.t
++	vlseg8e16ff.v v0, (a0), v0.t
++
++	vlseg2e32.v v0, (a0), v0.t
++	vsseg2e32.v v0, (a0), v0.t
++	vlseg2e32ff.v v0, (a0), v0.t
++	vlseg3e32.v v0, (a0), v0.t
++	vsseg3e32.v v0, (a0), v0.t
++	vlseg3e32ff.v v0, (a0), v0.t
++	vlseg4e32.v v0, (a0), v0.t
++	vsseg4e32.v v0, (a0), v0.t
++	vlseg4e32ff.v v0, (a0), v0.t
++	vlseg5e32.v v0, (a0), v0.t
++	vsseg5e32.v v0, (a0), v0.t
++	vlseg5e32ff.v v0, (a0), v0.t
++	vlseg6e32.v v0, (a0), v0.t
++	vsseg6e32.v v0, (a0), v0.t
++	vlseg6e32ff.v v0, (a0), v0.t
++	vlseg7e32.v v0, (a0), v0.t
++	vsseg7e32.v v0, (a0), v0.t
++	vlseg7e32ff.v v0, (a0), v0.t
++	vlseg8e32.v v0, (a0), v0.t
++	vsseg8e32.v v0, (a0), v0.t
++	vlseg8e32ff.v v0, (a0), v0.t
++
++	vlseg2e64.v v0, (a0), v0.t
++	vsseg2e64.v v0, (a0), v0.t
++	vlseg2e64ff.v v0, (a0), v0.t
++	vlseg3e64.v v0, (a0), v0.t
++	vsseg3e64.v v0, (a0), v0.t
++	vlseg3e64ff.v v0, (a0), v0.t
++	vlseg4e64.v v0, (a0), v0.t
++	vsseg4e64.v v0, (a0), v0.t
++	vlseg4e64ff.v v0, (a0), v0.t
++	vlseg5e64.v v0, (a0), v0.t
++	vsseg5e64.v v0, (a0), v0.t
++	vlseg5e64ff.v v0, (a0), v0.t
++	vlseg6e64.v v0, (a0), v0.t
++	vsseg6e64.v v0, (a0), v0.t
++	vlseg6e64ff.v v0, (a0), v0.t
++	vlseg7e64.v v0, (a0), v0.t
++	vsseg7e64.v v0, (a0), v0.t
++	vlseg7e64ff.v v0, (a0), v0.t
++	vlseg8e64.v v0, (a0), v0.t
++	vsseg8e64.v v0, (a0), v0.t
++	vlseg8e64ff.v v0, (a0), v0.t
++
++	vlseg2e128.v v0, (a0), v0.t
++	vsseg2e128.v v0, (a0), v0.t
++	vlseg2e128ff.v v0, (a0), v0.t
++	vlseg3e128.v v0, (a0), v0.t
++	vsseg3e128.v v0, (a0), v0.t
++	vlseg3e128ff.v v0, (a0), v0.t
++	vlseg4e128.v v0, (a0), v0.t
++	vsseg4e128.v v0, (a0), v0.t
++	vlseg4e128ff.v v0, (a0), v0.t
++	vlseg5e128.v v0, (a0), v0.t
++	vsseg5e128.v v0, (a0), v0.t
++	vlseg5e128ff.v v0, (a0), v0.t
++	vlseg6e128.v v0, (a0), v0.t
++	vsseg6e128.v v0, (a0), v0.t
++	vlseg6e128ff.v v0, (a0), v0.t
++	vlseg7e128.v v0, (a0), v0.t
++	vsseg7e128.v v0, (a0), v0.t
++	vlseg7e128ff.v v0, (a0), v0.t
++	vlseg8e128.v v0, (a0), v0.t
++	vsseg8e128.v v0, (a0), v0.t
++	vlseg8e128ff.v v0, (a0), v0.t
++
++	vlseg2e256.v v0, (a0), v0.t
++	vsseg2e256.v v0, (a0), v0.t
++	vlseg2e256ff.v v0, (a0), v0.t
++	vlseg3e256.v v0, (a0), v0.t
++	vsseg3e256.v v0, (a0), v0.t
++	vlseg3e256ff.v v0, (a0), v0.t
++	vlseg4e256.v v0, (a0), v0.t
++	vsseg4e256.v v0, (a0), v0.t
++	vlseg4e256ff.v v0, (a0), v0.t
++	vlseg5e256.v v0, (a0), v0.t
++	vsseg5e256.v v0, (a0), v0.t
++	vlseg5e256ff.v v0, (a0), v0.t
++	vlseg6e256.v v0, (a0), v0.t
++	vsseg6e256.v v0, (a0), v0.t
++	vlseg6e256ff.v v0, (a0), v0.t
++	vlseg7e256.v v0, (a0), v0.t
++	vsseg7e256.v v0, (a0), v0.t
++	vlseg7e256ff.v v0, (a0), v0.t
++	vlseg8e256.v v0, (a0), v0.t
++	vsseg8e256.v v0, (a0), v0.t
++	vlseg8e256ff.v v0, (a0), v0.t
++
++	vlseg2e512.v v0, (a0), v0.t
++	vsseg2e512.v v0, (a0), v0.t
++	vlseg2e512ff.v v0, (a0), v0.t
++	vlseg3e512.v v0, (a0), v0.t
++	vsseg3e512.v v0, (a0), v0.t
++	vlseg3e512ff.v v0, (a0), v0.t
++	vlseg4e512.v v0, (a0), v0.t
++	vsseg4e512.v v0, (a0), v0.t
++	vlseg4e512ff.v v0, (a0), v0.t
++	vlseg5e512.v v0, (a0), v0.t
++	vsseg5e512.v v0, (a0), v0.t
++	vlseg5e512ff.v v0, (a0), v0.t
++	vlseg6e512.v v0, (a0), v0.t
++	vsseg6e512.v v0, (a0), v0.t
++	vlseg6e512ff.v v0, (a0), v0.t
++	vlseg7e512.v v0, (a0), v0.t
++	vsseg7e512.v v0, (a0), v0.t
++	vlseg7e512ff.v v0, (a0), v0.t
++	vlseg8e512.v v0, (a0), v0.t
++	vsseg8e512.v v0, (a0), v0.t
++	vlseg8e512ff.v v0, (a0), v0.t
++
++	vlseg2e1024.v v0, (a0), v0.t
++	vsseg2e1024.v v0, (a0), v0.t
++	vlseg2e1024ff.v v0, (a0), v0.t
++	vlseg3e1024.v v0, (a0), v0.t
++	vsseg3e1024.v v0, (a0), v0.t
++	vlseg3e1024ff.v v0, (a0), v0.t
++	vlseg4e1024.v v0, (a0), v0.t
++	vsseg4e1024.v v0, (a0), v0.t
++	vlseg4e1024ff.v v0, (a0), v0.t
++	vlseg5e1024.v v0, (a0), v0.t
++	vsseg5e1024.v v0, (a0), v0.t
++	vlseg5e1024ff.v v0, (a0), v0.t
++	vlseg6e1024.v v0, (a0), v0.t
++	vsseg6e1024.v v0, (a0), v0.t
++	vlseg6e1024ff.v v0, (a0), v0.t
++	vlseg7e1024.v v0, (a0), v0.t
++	vsseg7e1024.v v0, (a0), v0.t
++	vlseg7e1024ff.v v0, (a0), v0.t
++	vlseg8e1024.v v0, (a0), v0.t
++	vsseg8e1024.v v0, (a0), v0.t
++	vlseg8e1024ff.v v0, (a0), v0.t
++
++# Vector Strided Segment Loads and Stores
++
++	vlsseg2e8.v v0, (a0), a1, v0.t		# vd overlap vm
++	vssseg2e8.v v0, (a0), a1, v0.t		# vd overlap vm
++	vlsseg3e8.v v0, (a0), a1, v0.t
++	vssseg3e8.v v0, (a0), a1, v0.t
++	vlsseg4e8.v v0, (a0), a1, v0.t
++	vssseg4e8.v v0, (a0), a1, v0.t
++	vlsseg5e8.v v0, (a0), a1, v0.t
++	vssseg5e8.v v0, (a0), a1, v0.t
++	vlsseg6e8.v v0, (a0), a1, v0.t
++	vssseg6e8.v v0, (a0), a1, v0.t
++	vlsseg7e8.v v0, (a0), a1, v0.t
++	vssseg7e8.v v0, (a0), a1, v0.t
++	vlsseg8e8.v v0, (a0), a1, v0.t
++	vssseg8e8.v v0, (a0), a1, v0.t
++
++	vlsseg2e16.v v0, (a0), a1, v0.t
++	vssseg2e16.v v0, (a0), a1, v0.t
++	vlsseg3e16.v v0, (a0), a1, v0.t
++	vssseg3e16.v v0, (a0), a1, v0.t
++	vlsseg4e16.v v0, (a0), a1, v0.t
++	vssseg4e16.v v0, (a0), a1, v0.t
++	vlsseg5e16.v v0, (a0), a1, v0.t
++	vssseg5e16.v v0, (a0), a1, v0.t
++	vlsseg6e16.v v0, (a0), a1, v0.t
++	vssseg6e16.v v0, (a0), a1, v0.t
++	vlsseg7e16.v v0, (a0), a1, v0.t
++	vssseg7e16.v v0, (a0), a1, v0.t
++	vlsseg8e16.v v0, (a0), a1, v0.t
++	vssseg8e16.v v0, (a0), a1, v0.t
++
++	vlsseg2e32.v v0, (a0), a1, v0.t
++	vssseg2e32.v v0, (a0), a1, v0.t
++	vlsseg3e32.v v0, (a0), a1, v0.t
++	vssseg3e32.v v0, (a0), a1, v0.t
++	vlsseg4e32.v v0, (a0), a1, v0.t
++	vssseg4e32.v v0, (a0), a1, v0.t
++	vlsseg5e32.v v0, (a0), a1, v0.t
++	vssseg5e32.v v0, (a0), a1, v0.t
++	vlsseg6e32.v v0, (a0), a1, v0.t
++	vssseg6e32.v v0, (a0), a1, v0.t
++	vlsseg7e32.v v0, (a0), a1, v0.t
++	vssseg7e32.v v0, (a0), a1, v0.t
++	vlsseg8e32.v v0, (a0), a1, v0.t
++	vssseg8e32.v v0, (a0), a1, v0.t
++
++	vlsseg2e64.v v0, (a0), a1, v0.t
++	vssseg2e64.v v0, (a0), a1, v0.t
++	vlsseg3e64.v v0, (a0), a1, v0.t
++	vssseg3e64.v v0, (a0), a1, v0.t
++	vlsseg4e64.v v0, (a0), a1, v0.t
++	vssseg4e64.v v0, (a0), a1, v0.t
++	vlsseg5e64.v v0, (a0), a1, v0.t
++	vssseg5e64.v v0, (a0), a1, v0.t
++	vlsseg6e64.v v0, (a0), a1, v0.t
++	vssseg6e64.v v0, (a0), a1, v0.t
++	vlsseg7e64.v v0, (a0), a1, v0.t
++	vssseg7e64.v v0, (a0), a1, v0.t
++	vlsseg8e64.v v0, (a0), a1, v0.t
++	vssseg8e64.v v0, (a0), a1, v0.t
++
++	vlsseg2e128.v v0, (a0), a1, v0.t
++	vssseg2e128.v v0, (a0), a1, v0.t
++	vlsseg3e128.v v0, (a0), a1, v0.t
++	vssseg3e128.v v0, (a0), a1, v0.t
++	vlsseg4e128.v v0, (a0), a1, v0.t
++	vssseg4e128.v v0, (a0), a1, v0.t
++	vlsseg5e128.v v0, (a0), a1, v0.t
++	vssseg5e128.v v0, (a0), a1, v0.t
++	vlsseg6e128.v v0, (a0), a1, v0.t
++	vssseg6e128.v v0, (a0), a1, v0.t
++	vlsseg7e128.v v0, (a0), a1, v0.t
++	vssseg7e128.v v0, (a0), a1, v0.t
++	vlsseg8e128.v v0, (a0), a1, v0.t
++	vssseg8e128.v v0, (a0), a1, v0.t
++
++	vlsseg2e256.v v0, (a0), a1, v0.t
++	vssseg2e256.v v0, (a0), a1, v0.t
++	vlsseg3e256.v v0, (a0), a1, v0.t
++	vssseg3e256.v v0, (a0), a1, v0.t
++	vlsseg4e256.v v0, (a0), a1, v0.t
++	vssseg4e256.v v0, (a0), a1, v0.t
++	vlsseg5e256.v v0, (a0), a1, v0.t
++	vssseg5e256.v v0, (a0), a1, v0.t
++	vlsseg6e256.v v0, (a0), a1, v0.t
++	vssseg6e256.v v0, (a0), a1, v0.t
++	vlsseg7e256.v v0, (a0), a1, v0.t
++	vssseg7e256.v v0, (a0), a1, v0.t
++	vlsseg8e256.v v0, (a0), a1, v0.t
++	vssseg8e256.v v0, (a0), a1, v0.t
++
++	vlsseg2e512.v v0, (a0), a1, v0.t
++	vssseg2e512.v v0, (a0), a1, v0.t
++	vlsseg3e512.v v0, (a0), a1, v0.t
++	vssseg3e512.v v0, (a0), a1, v0.t
++	vlsseg4e512.v v0, (a0), a1, v0.t
++	vssseg4e512.v v0, (a0), a1, v0.t
++	vlsseg5e512.v v0, (a0), a1, v0.t
++	vssseg5e512.v v0, (a0), a1, v0.t
++	vlsseg6e512.v v0, (a0), a1, v0.t
++	vssseg6e512.v v0, (a0), a1, v0.t
++	vlsseg7e512.v v0, (a0), a1, v0.t
++	vssseg7e512.v v0, (a0), a1, v0.t
++	vlsseg8e512.v v0, (a0), a1, v0.t
++	vssseg8e512.v v0, (a0), a1, v0.t
++
++	vlsseg2e1024.v v0, (a0), a1, v0.t
++	vssseg2e1024.v v0, (a0), a1, v0.t
++	vlsseg3e1024.v v0, (a0), a1, v0.t
++	vssseg3e1024.v v0, (a0), a1, v0.t
++	vlsseg4e1024.v v0, (a0), a1, v0.t
++	vssseg4e1024.v v0, (a0), a1, v0.t
++	vlsseg5e1024.v v0, (a0), a1, v0.t
++	vssseg5e1024.v v0, (a0), a1, v0.t
++	vlsseg6e1024.v v0, (a0), a1, v0.t
++	vssseg6e1024.v v0, (a0), a1, v0.t
++	vlsseg7e1024.v v0, (a0), a1, v0.t
++	vssseg7e1024.v v0, (a0), a1, v0.t
++	vlsseg8e1024.v v0, (a0), a1, v0.t
++	vssseg8e1024.v v0, (a0), a1, v0.t
++
++# Vector Indexed Segment Loads and Stores
++
++	vlxseg2ei8.v v4, (a0), v4		# vd overlap vs2
++	vlxseg2ei8.v v0, (a0), v4, v0.t		# vd overlap vm
++	vsxseg2ei8.v v4, (a0), v4		# vd overlap vs2
++	vsxseg2ei8.v v0, (a0), v4, v0.t		# vd overlap vm
++	vlxseg3ei8.v v4, (a0), v4
++	vlxseg3ei8.v v0, (a0), v4, v0.t
++	vsxseg3ei8.v v4, (a0), v4
++	vsxseg3ei8.v v0, (a0), v4, v0.t
++	vlxseg4ei8.v v4, (a0), v4
++	vlxseg4ei8.v v0, (a0), v4, v0.t
++	vsxseg4ei8.v v4, (a0), v4
++	vsxseg4ei8.v v0, (a0), v4, v0.t
++	vlxseg5ei8.v v4, (a0), v4
++	vlxseg5ei8.v v0, (a0), v4, v0.t
++	vsxseg5ei8.v v4, (a0), v4
++	vsxseg5ei8.v v0, (a0), v4, v0.t
++	vlxseg6ei8.v v4, (a0), v4
++	vlxseg6ei8.v v0, (a0), v4, v0.t
++	vsxseg6ei8.v v4, (a0), v4
++	vsxseg6ei8.v v0, (a0), v4, v0.t
++	vlxseg7ei8.v v4, (a0), v4
++	vlxseg7ei8.v v0, (a0), v4, v0.t
++	vsxseg7ei8.v v4, (a0), v4
++	vsxseg7ei8.v v0, (a0), v4, v0.t
++	vlxseg8ei8.v v4, (a0), v4
++	vlxseg8ei8.v v0, (a0), v4, v0.t
++	vsxseg8ei8.v v4, (a0), v4
++	vsxseg8ei8.v v0, (a0), v4, v0.t
++
++	vlxseg2ei16.v v4, (a0), v4
++	vlxseg2ei16.v v0, (a0), v4, v0.t
++	vsxseg2ei16.v v4, (a0), v4
++	vsxseg2ei16.v v0, (a0), v4, v0.t
++	vlxseg3ei16.v v4, (a0), v4
++	vlxseg3ei16.v v0, (a0), v4, v0.t
++	vsxseg3ei16.v v4, (a0), v4
++	vsxseg3ei16.v v0, (a0), v4, v0.t
++	vlxseg4ei16.v v4, (a0), v4
++	vlxseg4ei16.v v0, (a0), v4, v0.t
++	vsxseg4ei16.v v4, (a0), v4
++	vsxseg4ei16.v v0, (a0), v4, v0.t
++	vlxseg5ei16.v v4, (a0), v4
++	vlxseg5ei16.v v0, (a0), v4, v0.t
++	vsxseg5ei16.v v4, (a0), v4
++	vsxseg5ei16.v v0, (a0), v4, v0.t
++	vlxseg6ei16.v v4, (a0), v4
++	vlxseg6ei16.v v0, (a0), v4, v0.t
++	vsxseg6ei16.v v4, (a0), v4
++	vsxseg6ei16.v v0, (a0), v4, v0.t
++	vlxseg7ei16.v v4, (a0), v4
++	vlxseg7ei16.v v0, (a0), v4, v0.t
++	vsxseg7ei16.v v4, (a0), v4
++	vsxseg7ei16.v v0, (a0), v4, v0.t
++	vlxseg8ei16.v v4, (a0), v4
++	vlxseg8ei16.v v0, (a0), v4, v0.t
++	vsxseg8ei16.v v4, (a0), v4
++	vsxseg8ei16.v v0, (a0), v4, v0.t
++
++	vlxseg2ei32.v v4, (a0), v4
++	vlxseg2ei32.v v0, (a0), v4, v0.t
++	vsxseg2ei32.v v4, (a0), v4
++	vsxseg2ei32.v v0, (a0), v4, v0.t
++	vlxseg3ei32.v v4, (a0), v4
++	vlxseg3ei32.v v0, (a0), v4, v0.t
++	vsxseg3ei32.v v4, (a0), v4
++	vsxseg3ei32.v v0, (a0), v4, v0.t
++	vlxseg4ei32.v v4, (a0), v4
++	vlxseg4ei32.v v0, (a0), v4, v0.t
++	vsxseg4ei32.v v4, (a0), v4
++	vsxseg4ei32.v v0, (a0), v4, v0.t
++	vlxseg5ei32.v v4, (a0), v4
++	vlxseg5ei32.v v0, (a0), v4, v0.t
++	vsxseg5ei32.v v4, (a0), v4
++	vsxseg5ei32.v v0, (a0), v4, v0.t
++	vlxseg6ei32.v v4, (a0), v4
++	vlxseg6ei32.v v0, (a0), v4, v0.t
++	vsxseg6ei32.v v4, (a0), v4
++	vsxseg6ei32.v v0, (a0), v4, v0.t
++	vlxseg7ei32.v v4, (a0), v4
++	vlxseg7ei32.v v0, (a0), v4, v0.t
++	vsxseg7ei32.v v4, (a0), v4
++	vsxseg7ei32.v v0, (a0), v4, v0.t
++	vlxseg8ei32.v v4, (a0), v4
++	vlxseg8ei32.v v0, (a0), v4, v0.t
++	vsxseg8ei32.v v4, (a0), v4
++	vsxseg8ei32.v v0, (a0), v4, v0.t
++
++	vlxseg2ei64.v v4, (a0), v4
++	vlxseg2ei64.v v0, (a0), v4, v0.t
++	vsxseg2ei64.v v4, (a0), v4
++	vsxseg2ei64.v v0, (a0), v4, v0.t
++	vlxseg3ei64.v v4, (a0), v4
++	vlxseg3ei64.v v0, (a0), v4, v0.t
++	vsxseg3ei64.v v4, (a0), v4
++	vsxseg3ei64.v v0, (a0), v4, v0.t
++	vlxseg4ei64.v v4, (a0), v4
++	vlxseg4ei64.v v0, (a0), v4, v0.t
++	vsxseg4ei64.v v4, (a0), v4
++	vsxseg4ei64.v v0, (a0), v4, v0.t
++	vlxseg5ei64.v v4, (a0), v4
++	vlxseg5ei64.v v0, (a0), v4, v0.t
++	vsxseg5ei64.v v4, (a0), v4
++	vsxseg5ei64.v v0, (a0), v4, v0.t
++	vlxseg6ei64.v v4, (a0), v4
++	vlxseg6ei64.v v0, (a0), v4, v0.t
++	vsxseg6ei64.v v4, (a0), v4
++	vsxseg6ei64.v v0, (a0), v4, v0.t
++	vlxseg7ei64.v v4, (a0), v4
++	vlxseg7ei64.v v0, (a0), v4, v0.t
++	vsxseg7ei64.v v4, (a0), v4
++	vsxseg7ei64.v v0, (a0), v4, v0.t
++	vlxseg8ei64.v v4, (a0), v4
++	vlxseg8ei64.v v0, (a0), v4, v0.t
++	vsxseg8ei64.v v4, (a0), v4
++	vsxseg8ei64.v v0, (a0), v4, v0.t
++
++	vlxseg2ei128.v v4, (a0), v4
++	vlxseg2ei128.v v0, (a0), v4, v0.t
++	vsxseg2ei128.v v4, (a0), v4
++	vsxseg2ei128.v v0, (a0), v4, v0.t
++	vlxseg3ei128.v v4, (a0), v4
++	vlxseg3ei128.v v0, (a0), v4, v0.t
++	vsxseg3ei128.v v4, (a0), v4
++	vsxseg3ei128.v v0, (a0), v4, v0.t
++	vlxseg4ei128.v v4, (a0), v4
++	vlxseg4ei128.v v0, (a0), v4, v0.t
++	vsxseg4ei128.v v4, (a0), v4
++	vsxseg4ei128.v v0, (a0), v4, v0.t
++	vlxseg5ei128.v v4, (a0), v4
++	vlxseg5ei128.v v0, (a0), v4, v0.t
++	vsxseg5ei128.v v4, (a0), v4
++	vsxseg5ei128.v v0, (a0), v4, v0.t
++	vlxseg6ei128.v v4, (a0), v4
++	vlxseg6ei128.v v0, (a0), v4, v0.t
++	vsxseg6ei128.v v4, (a0), v4
++	vsxseg6ei128.v v0, (a0), v4, v0.t
++	vlxseg7ei128.v v4, (a0), v4
++	vlxseg7ei128.v v0, (a0), v4, v0.t
++	vsxseg7ei128.v v4, (a0), v4
++	vsxseg7ei128.v v0, (a0), v4, v0.t
++	vlxseg8ei128.v v4, (a0), v4
++	vlxseg8ei128.v v0, (a0), v4, v0.t
++	vsxseg8ei128.v v4, (a0), v4
++	vsxseg8ei128.v v0, (a0), v4, v0.t
++
++	vlxseg2ei256.v v4, (a0), v4
++	vlxseg2ei256.v v0, (a0), v4, v0.t
++	vsxseg2ei256.v v4, (a0), v4
++	vsxseg2ei256.v v0, (a0), v4, v0.t
++	vlxseg3ei256.v v4, (a0), v4
++	vlxseg3ei256.v v0, (a0), v4, v0.t
++	vsxseg3ei256.v v4, (a0), v4
++	vsxseg3ei256.v v0, (a0), v4, v0.t
++	vlxseg4ei256.v v4, (a0), v4
++	vlxseg4ei256.v v0, (a0), v4, v0.t
++	vsxseg4ei256.v v4, (a0), v4
++	vsxseg4ei256.v v0, (a0), v4, v0.t
++	vlxseg5ei256.v v4, (a0), v4
++	vlxseg5ei256.v v0, (a0), v4, v0.t
++	vsxseg5ei256.v v4, (a0), v4
++	vsxseg5ei256.v v0, (a0), v4, v0.t
++	vlxseg6ei256.v v4, (a0), v4
++	vlxseg6ei256.v v0, (a0), v4, v0.t
++	vsxseg6ei256.v v4, (a0), v4
++	vsxseg6ei256.v v0, (a0), v4, v0.t
++	vlxseg7ei256.v v4, (a0), v4
++	vlxseg7ei256.v v0, (a0), v4, v0.t
++	vsxseg7ei256.v v4, (a0), v4
++	vsxseg7ei256.v v0, (a0), v4, v0.t
++	vlxseg8ei256.v v4, (a0), v4
++	vlxseg8ei256.v v0, (a0), v4, v0.t
++	vsxseg8ei256.v v4, (a0), v4
++	vsxseg8ei256.v v0, (a0), v4, v0.t
++
++	vlxseg2ei512.v v4, (a0), v4
++	vlxseg2ei512.v v0, (a0), v4, v0.t
++	vsxseg2ei512.v v4, (a0), v4
++	vsxseg2ei512.v v0, (a0), v4, v0.t
++	vlxseg3ei512.v v4, (a0), v4
++	vlxseg3ei512.v v0, (a0), v4, v0.t
++	vsxseg3ei512.v v4, (a0), v4
++	vsxseg3ei512.v v0, (a0), v4, v0.t
++	vlxseg4ei512.v v4, (a0), v4
++	vlxseg4ei512.v v0, (a0), v4, v0.t
++	vsxseg4ei512.v v4, (a0), v4
++	vsxseg4ei512.v v0, (a0), v4, v0.t
++	vlxseg5ei512.v v4, (a0), v4
++	vlxseg5ei512.v v0, (a0), v4, v0.t
++	vsxseg5ei512.v v4, (a0), v4
++	vsxseg5ei512.v v0, (a0), v4, v0.t
++	vlxseg6ei512.v v4, (a0), v4
++	vlxseg6ei512.v v0, (a0), v4, v0.t
++	vsxseg6ei512.v v4, (a0), v4
++	vsxseg6ei512.v v0, (a0), v4, v0.t
++	vlxseg7ei512.v v4, (a0), v4
++	vlxseg7ei512.v v0, (a0), v4, v0.t
++	vsxseg7ei512.v v4, (a0), v4
++	vsxseg7ei512.v v0, (a0), v4, v0.t
++	vlxseg8ei512.v v4, (a0), v4
++	vlxseg8ei512.v v0, (a0), v4, v0.t
++	vsxseg8ei512.v v4, (a0), v4
++	vsxseg8ei512.v v0, (a0), v4, v0.t
++
++	vlxseg2ei1024.v v4, (a0), v4
++	vlxseg2ei1024.v v0, (a0), v4, v0.t
++	vsxseg2ei1024.v v4, (a0), v4
++	vsxseg2ei1024.v v0, (a0), v4, v0.t
++	vlxseg3ei1024.v v4, (a0), v4
++	vlxseg3ei1024.v v0, (a0), v4, v0.t
++	vsxseg3ei1024.v v4, (a0), v4
++	vsxseg3ei1024.v v0, (a0), v4, v0.t
++	vlxseg4ei1024.v v4, (a0), v4
++	vlxseg4ei1024.v v0, (a0), v4, v0.t
++	vsxseg4ei1024.v v4, (a0), v4
++	vsxseg4ei1024.v v0, (a0), v4, v0.t
++	vlxseg5ei1024.v v4, (a0), v4
++	vlxseg5ei1024.v v0, (a0), v4, v0.t
++	vsxseg5ei1024.v v4, (a0), v4
++	vsxseg5ei1024.v v0, (a0), v4, v0.t
++	vlxseg6ei1024.v v4, (a0), v4
++	vlxseg6ei1024.v v0, (a0), v4, v0.t
++	vsxseg6ei1024.v v4, (a0), v4
++	vsxseg6ei1024.v v0, (a0), v4, v0.t
++	vlxseg7ei1024.v v4, (a0), v4
++	vlxseg7ei1024.v v0, (a0), v4, v0.t
++	vsxseg7ei1024.v v4, (a0), v4
++	vsxseg7ei1024.v v0, (a0), v4, v0.t
++	vlxseg8ei1024.v v4, (a0), v4
++	vlxseg8ei1024.v v0, (a0), v4, v0.t
++	vsxseg8ei1024.v v4, (a0), v4
++	vsxseg8ei1024.v v0, (a0), v4, v0.t
+diff --git a/gas/testsuite/gas/riscv/vector-insns-fail-mask.d b/gas/testsuite/gas/riscv/vector-insns-fail-mask.d
+new file mode 100644
+index 0000000000..35f9e2c32c
+--- /dev/null
++++ b/gas/testsuite/gas/riscv/vector-insns-fail-mask.d
+@@ -0,0 +1,3 @@
++#as: -march=rv32iv -mcheck-constraints
++#source: vector-insns-fail-mask.s
++#error_output: vector-insns-fail-mask.l
+diff --git a/gas/testsuite/gas/riscv/vector-insns-fail-mask.l b/gas/testsuite/gas/riscv/vector-insns-fail-mask.l
+new file mode 100644
+index 0000000000..5c4e881489
+--- /dev/null
++++ b/gas/testsuite/gas/riscv/vector-insns-fail-mask.l
+@@ -0,0 +1,7 @@
++.*: Assembler messages:
++.*Error: illegal operands `vmsbf.m v0,v4,v0.t'
++.*Error: illegal operands `vmsif.m v0,v4,v0.t'
++.*Error: illegal operands `vmsof.m v0,v4,v0.t'
++.*Error: illegal operands `viota.m v4,v4'
++.*Error: illegal operands `viota.m v0,v4,v0.t'
++.*Error: illegal operands `vid.v v0,v0.t'
+diff --git a/gas/testsuite/gas/riscv/vector-insns-fail-mask.s b/gas/testsuite/gas/riscv/vector-insns-fail-mask.s
+new file mode 100644
+index 0000000000..580b101c77
+--- /dev/null
++++ b/gas/testsuite/gas/riscv/vector-insns-fail-mask.s
+@@ -0,0 +1,20 @@
++# Vector Set-before-first Mask Bit
++
++	vmsbf.m v0, v4, v0.t	# vd overlap vm
++
++# Vector Set-including-first Mask Bit
++
++	vmsif.m v0, v4, v0.t	# vd overlap vm
++
++# Vector Set-only-first Mask Bit
++
++	vmsof.m v0, v4, v0.t	# vd overlap vm
++
++# Vector Iota Instruction
++
++	viota.m v4, v4		# vd overlap vs2
++	viota.m v0, v4, v0.t	# vd overlap vm
++
++# Vector Element Index Instruction
++
++	vid.v v0, v0.t		# vd overlap vm
+diff --git a/gas/testsuite/gas/riscv/vector-insns-fail-permutation.d b/gas/testsuite/gas/riscv/vector-insns-fail-permutation.d
+new file mode 100644
+index 0000000000..9822e2919a
+--- /dev/null
++++ b/gas/testsuite/gas/riscv/vector-insns-fail-permutation.d
+@@ -0,0 +1,3 @@
++#as: -march=rv32ifv -mcheck-constraints
++#source: vector-insns-fail-permutation.s
++#error_output: vector-insns-fail-permutation.l
+diff --git a/gas/testsuite/gas/riscv/vector-insns-fail-permutation.l b/gas/testsuite/gas/riscv/vector-insns-fail-permutation.l
+new file mode 100644
+index 0000000000..c208f5710f
+--- /dev/null
++++ b/gas/testsuite/gas/riscv/vector-insns-fail-permutation.l
+@@ -0,0 +1,31 @@
++.*: Assembler messages:
++.*Error: illegal operands `vslideup.vx v4,v4,a1'
++.*Error: illegal operands `vslideup.vx v0,v4,a1,v0.t'
++.*Error: illegal operands `vslideup.vi v4,v4,31'
++.*Error: illegal operands `vslideup.vi v0,v4,31,v0.t'
++.*Error: illegal operands `vslidedown.vx v0,v4,a1,v0.t'
++.*Error: illegal operands `vslidedown.vi v0,v4,31,v0.t'
++.*Error: illegal operands `vslide1up.vx v4,v4,a1'
++.*Error: illegal operands `vslide1up.vx v0,v4,a1,v0.t'
++.*Error: illegal operands `vfslide1up.vf v4,v4,fa1'
++.*Error: illegal operands `vfslide1up.vf v0,v4,fa1,v0.t'
++.*Error: illegal operands `vslide1down.vx v0,v4,a1,v0.t'
++.*Error: illegal operands `vfslide1down.vf v0,v4,fa1,v0.t'
++.*Error: illegal operands `vrgather.vv v4,v4,v8'
++.*Error: illegal operands `vrgather.vv v8,v4,v8'
++.*Error: illegal operands `vrgather.vv v0,v4,v8,v0.t'
++.*Error: illegal operands `vrgather.vx v4,v4,a1'
++.*Error: illegal operands `vrgather.vx v0,v4,a1,v0.t'
++.*Error: illegal operands `vrgather.vi v4,v4,31'
++.*Error: illegal operands `vrgather.vi v0,v4,31,v0.t'
++.*Error: illegal operands `vrgatherei16.vv v4,v4,v8'
++.*Error: illegal operands `vrgatherei16.vv v8,v4,v8'
++.*Error: illegal operands `vrgatherei16.vv v0,v4,v8,v0.t'
++.*Error: illegal operands `vcompress.vm v4,v4,v8'
++.*Error: illegal operands `vcompress.vm v8,v4,v8'
++.*Error: illegal operands `vmv2r.v v30,v31'
++.*Error: illegal operands `vmv2r.v v31,v30'
++.*Error: illegal operands `vmv4r.v v28,v30'
++.*Error: illegal operands `vmv4r.v v30,v28'
++.*Error: illegal operands `vmv8r.v v24,v26'
++.*Error: illegal operands `vmv8r.v v26,v24'
+diff --git a/gas/testsuite/gas/riscv/vector-insns-fail-permutation.s b/gas/testsuite/gas/riscv/vector-insns-fail-permutation.s
+new file mode 100644
+index 0000000000..85116457ff
+--- /dev/null
++++ b/gas/testsuite/gas/riscv/vector-insns-fail-permutation.s
+@@ -0,0 +1,56 @@
++# Vector Slideup Instructions
++
++	vslideup.vx v4, v4, a1			# vd overlap vs2
++	vslideup.vx v0, v4, a1, v0.t		# vd overlap vm
++	vslideup.vi v4, v4, 31			# vd overlap vs2
++	vslideup.vi v0, v4, 31, v0.t		# vd overlap vm
++
++	vslidedown.vx v4, v4, a1		# OK
++	vslidedown.vx v0, v4, a1, v0.t		# vd overlap vm
++	vslidedown.vi v4, v4, 31		# OK
++	vslidedown.vi v0, v4, 31, v0.t		# vd overlap vm
++
++	vslide1up.vx v4, v4, a1			# vd overlap vs2
++	vslide1up.vx v0, v4, a1, v0.t		# vd overlap vm
++	vfslide1up.vf v4, v4, fa1		# vd overlap vs2
++	vfslide1up.vf v0, v4, fa1, v0.t		# vd overlap vm
++
++	vslide1down.vx v4, v4, a1		# OK
++	vslide1down.vx v0, v4, a1, v0.t		# vd overlap vm
++	vfslide1down.vf v4, v4, fa1		# OK
++	vfslide1down.vf v0, v4, fa1, v0.t	# vd overlap vm
++
++# Vector Register Gather Instructions
++
++	vrgather.vv v4, v4, v8			# vd overlap vs2
++	vrgather.vv v8, v4, v8			# vd overlap vs1
++	vrgather.vv v0, v4, v8, v0.t		# vd overlap vm
++	vrgather.vx v4, v4, a1			# vd overlap vs2
++	vrgather.vx v0, v4, a1, v0.t		# vd overlap vm
++	vrgather.vi v4, v4, 31			# vd overlap vs2
++	vrgather.vi v0, v4, 31, v0.t		# vd overlap vm
++
++	vrgatherei16.vv v4, v4, v8		# vd overlap vs2
++	vrgatherei16.vv v8, v4, v8		# vd overlap vs1
++	vrgatherei16.vv v0, v4, v8, v0.t	# vd overlap vm
++
++# Vector Compress Instruction
++
++	vcompress.vm v4, v4, v8			# vd overlap vs2
++	vcompress.vm v8, v4, v8			# vd overlap vs1
++
++# Whole Vector Register Move
++
++	vmv1r.v v31, v31			# OK, HINT
++
++	vmv2r.v v30, v30			# OK, HINT
++	vmv2r.v v30, v31			# vs2 must be aligned to 2
++	vmv2r.v v31, v30			# vd must be aligned to 2
++
++	vmv4r.v v28, v28			# OK, HINT
++	vmv4r.v v28, v30			# vs2 must be aligned to 4
++	vmv4r.v v30, v28			# vd must be aligned to 4
++
++	vmv8r.v v24, v24			# OK, HINT
++	vmv8r.v v24, v26			# vs2 must be aligned to 8
++	vmv8r.v v26, v24			# vd must be aligned to 8
+diff --git a/gas/testsuite/gas/riscv/vector-insns-fail-zvamo.d b/gas/testsuite/gas/riscv/vector-insns-fail-zvamo.d
+new file mode 100644
+index 0000000000..5749449bd0
+--- /dev/null
++++ b/gas/testsuite/gas/riscv/vector-insns-fail-zvamo.d
+@@ -0,0 +1,3 @@
++#as: -march=rv32iav -mcheck-constraints
++#source: vector-insns-fail-zvamo.s
++#error_output: vector-insns-fail-zvamo.l
+diff --git a/gas/testsuite/gas/riscv/vector-insns-fail-zvamo.l b/gas/testsuite/gas/riscv/vector-insns-fail-zvamo.l
+new file mode 100644
+index 0000000000..6207fb2fee
+--- /dev/null
++++ b/gas/testsuite/gas/riscv/vector-insns-fail-zvamo.l
+@@ -0,0 +1,109 @@
++.*: Assembler messages:
++.*Error: illegal operands `vamoaddei8.v v4,\(a1\),v4,v0'
++.*Error: illegal operands `vamoaddei8.v v0,\(a1\),v4,v0,v0.t'
++.*Error: illegal operands `vamoaddei8.v x0,\(a1\),v4,v0,v0.t'
++.*Error: illegal operands `vamoswapei8.v v4,\(a1\),v4,v0'
++.*Error: illegal operands `vamoswapei8.v v0,\(a1\),v4,v0,v0.t'
++.*Error: illegal operands `vamoswapei8.v x0,\(a1\),v4,v0,v0.t'
++.*Error: illegal operands `vamoxorei8.v v4,\(a1\),v4,v0'
++.*Error: illegal operands `vamoxorei8.v v0,\(a1\),v4,v0,v0.t'
++.*Error: illegal operands `vamoxorei8.v x0,\(a1\),v4,v0,v0.t'
++.*Error: illegal operands `vamoandei8.v v4,\(a1\),v4,v0'
++.*Error: illegal operands `vamoandei8.v v0,\(a1\),v4,v0,v0.t'
++.*Error: illegal operands `vamoandei8.v x0,\(a1\),v4,v0,v0.t'
++.*Error: illegal operands `vamoorei8.v v4,\(a1\),v4,v0'
++.*Error: illegal operands `vamoorei8.v v0,\(a1\),v4,v0,v0.t'
++.*Error: illegal operands `vamoorei8.v x0,\(a1\),v4,v0,v0.t'
++.*Error: illegal operands `vamominei8.v v4,\(a1\),v4,v0'
++.*Error: illegal operands `vamominei8.v v0,\(a1\),v4,v0,v0.t'
++.*Error: illegal operands `vamominei8.v x0,\(a1\),v4,v0,v0.t'
++.*Error: illegal operands `vamomaxei8.v v4,\(a1\),v4,v0'
++.*Error: illegal operands `vamomaxei8.v v0,\(a1\),v4,v0,v0.t'
++.*Error: illegal operands `vamomaxei8.v x0,\(a1\),v4,v0,v0.t'
++.*Error: illegal operands `vamominuei8.v v4,\(a1\),v4,v0'
++.*Error: illegal operands `vamominuei8.v v0,\(a1\),v4,v0,v0.t'
++.*Error: illegal operands `vamominuei8.v x0,\(a1\),v4,v0,v0.t'
++.*Error: illegal operands `vamomaxuei8.v v4,\(a1\),v4,v0'
++.*Error: illegal operands `vamomaxuei8.v v0,\(a1\),v4,v0,v0.t'
++.*Error: illegal operands `vamomaxuei8.v x0,\(a1\),v4,v0,v0.t'
++.*Error: illegal operands `vamoaddei16.v v4,\(a1\),v4,v0'
++.*Error: illegal operands `vamoaddei16.v v0,\(a1\),v4,v0,v0.t'
++.*Error: illegal operands `vamoaddei16.v x0,\(a1\),v4,v0,v0.t'
++.*Error: illegal operands `vamoswapei16.v v0,\(a1\),v4,v0,v0.t'
++.*Error: illegal operands `vamoswapei16.v v4,\(a1\),v4,v0'
++.*Error: illegal operands `vamoswapei16.v x0,\(a1\),v4,v0,v0.t'
++.*Error: illegal operands `vamoxorei16.v v0,\(a1\),v4,v0,v0.t'
++.*Error: illegal operands `vamoxorei16.v v4,\(a1\),v4,v0'
++.*Error: illegal operands `vamoxorei16.v x0,\(a1\),v4,v0,v0.t'
++.*Error: illegal operands `vamoandei16.v v0,\(a1\),v4,v0,v0.t'
++.*Error: illegal operands `vamoandei16.v v4,\(a1\),v4,v0'
++.*Error: illegal operands `vamoandei16.v x0,\(a1\),v4,v0,v0.t'
++.*Error: illegal operands `vamoorei16.v v0,\(a1\),v4,v0,v0.t'
++.*Error: illegal operands `vamoorei16.v v4,\(a1\),v4,v0'
++.*Error: illegal operands `vamoorei16.v x0,\(a1\),v4,v0,v0.t'
++.*Error: illegal operands `vamominei16.v v0,\(a1\),v4,v0,v0.t'
++.*Error: illegal operands `vamominei16.v v4,\(a1\),v4,v0'
++.*Error: illegal operands `vamominei16.v x0,\(a1\),v4,v0,v0.t'
++.*Error: illegal operands `vamomaxei16.v v0,\(a1\),v4,v0,v0.t'
++.*Error: illegal operands `vamomaxei16.v v4,\(a1\),v4,v0'
++.*Error: illegal operands `vamomaxei16.v x0,\(a1\),v4,v0,v0.t'
++.*Error: illegal operands `vamominuei16.v v0,\(a1\),v4,v0,v0.t'
++.*Error: illegal operands `vamominuei16.v v4,\(a1\),v4,v0'
++.*Error: illegal operands `vamominuei16.v x0,\(a1\),v4,v0,v0.t'
++.*Error: illegal operands `vamomaxuei16.v v0,\(a1\),v4,v0,v0.t'
++.*Error: illegal operands `vamomaxuei16.v v4,\(a1\),v4,v0'
++.*Error: illegal operands `vamomaxuei16.v x0,\(a1\),v4,v0,v0.t'
++.*Error: illegal operands `vamoaddei32.v v0,\(a1\),v4,v0,v0.t'
++.*Error: illegal operands `vamoaddei32.v v4,\(a1\),v4,v0'
++.*Error: illegal operands `vamoaddei32.v x0,\(a1\),v4,v0,v0.t'
++.*Error: illegal operands `vamoswapei32.v v4,\(a1\),v4,v0'
++.*Error: illegal operands `vamoswapei32.v v0,\(a1\),v4,v0,v0.t'
++.*Error: illegal operands `vamoswapei32.v x0,\(a1\),v4,v0,v0.t'
++.*Error: illegal operands `vamoxorei32.v v4,\(a1\),v4,v0'
++.*Error: illegal operands `vamoxorei32.v v0,\(a1\),v4,v0,v0.t'
++.*Error: illegal operands `vamoxorei32.v x0,\(a1\),v4,v0,v0.t'
++.*Error: illegal operands `vamoandei32.v v4,\(a1\),v4,v0'
++.*Error: illegal operands `vamoandei32.v v0,\(a1\),v4,v0,v0.t'
++.*Error: illegal operands `vamoandei32.v x0,\(a1\),v4,v0,v0.t'
++.*Error: illegal operands `vamoorei32.v v4,\(a1\),v4,v0'
++.*Error: illegal operands `vamoorei32.v v0,\(a1\),v4,v0,v0.t'
++.*Error: illegal operands `vamoorei32.v x0,\(a1\),v4,v0,v0.t'
++.*Error: illegal operands `vamominei32.v v4,\(a1\),v4,v0'
++.*Error: illegal operands `vamominei32.v v0,\(a1\),v4,v0,v0.t'
++.*Error: illegal operands `vamominei32.v x0,\(a1\),v4,v0,v0.t'
++.*Error: illegal operands `vamomaxei32.v v4,\(a1\),v4,v0'
++.*Error: illegal operands `vamomaxei32.v v0,\(a1\),v4,v0,v0.t'
++.*Error: illegal operands `vamomaxei32.v x0,\(a1\),v4,v0,v0.t'
++.*Error: illegal operands `vamominuei32.v v4,\(a1\),v4,v0'
++.*Error: illegal operands `vamominuei32.v v0,\(a1\),v4,v0,v0.t'
++.*Error: illegal operands `vamominuei32.v x0,\(a1\),v4,v0,v0.t'
++.*Error: illegal operands `vamomaxuei32.v v4,\(a1\),v4,v0'
++.*Error: illegal operands `vamomaxuei32.v v0,\(a1\),v4,v0,v0.t'
++.*Error: illegal operands `vamomaxuei32.v x0,\(a1\),v4,v0,v0.t'
++.*Error: illegal operands `vamoaddei64.v v4,\(a1\),v4,v0'
++.*Error: illegal operands `vamoaddei64.v v0,\(a1\),v4,v0,v0.t'
++.*Error: illegal operands `vamoaddei64.v x0,\(a1\),v4,v0,v0.t'
++.*Error: illegal operands `vamoswapei64.v v4,\(a1\),v4,v0'
++.*Error: illegal operands `vamoswapei64.v v0,\(a1\),v4,v0,v0.t'
++.*Error: illegal operands `vamoswapei64.v x0,\(a1\),v4,v0,v0.t'
++.*Error: illegal operands `vamoxorei64.v v4,\(a1\),v4,v0'
++.*Error: illegal operands `vamoxorei64.v v0,\(a1\),v4,v0,v0.t'
++.*Error: illegal operands `vamoxorei64.v x0,\(a1\),v4,v0,v0.t'
++.*Error: illegal operands `vamoandei64.v v4,\(a1\),v4,v0'
++.*Error: illegal operands `vamoandei64.v v0,\(a1\),v4,v0,v0.t'
++.*Error: illegal operands `vamoandei64.v x0,\(a1\),v4,v0,v0.t'
++.*Error: illegal operands `vamoorei64.v v4,\(a1\),v4,v0'
++.*Error: illegal operands `vamoorei64.v v0,\(a1\),v4,v0,v0.t'
++.*Error: illegal operands `vamoorei64.v x0,\(a1\),v4,v0,v0.t'
++.*Error: illegal operands `vamominei64.v v4,\(a1\),v4,v0'
++.*Error: illegal operands `vamominei64.v v0,\(a1\),v4,v0,v0.t'
++.*Error: illegal operands `vamominei64.v x0,\(a1\),v4,v0,v0.t'
++.*Error: illegal operands `vamomaxei64.v v4,\(a1\),v4,v0'
++.*Error: illegal operands `vamomaxei64.v v0,\(a1\),v4,v0,v0.t'
++.*Error: illegal operands `vamomaxei64.v x0,\(a1\),v4,v0,v0.t'
++.*Error: illegal operands `vamominuei64.v v4,\(a1\),v4,v0'
++.*Error: illegal operands `vamominuei64.v v0,\(a1\),v4,v0,v0.t'
++.*Error: illegal operands `vamominuei64.v x0,\(a1\),v4,v0,v0.t'
++.*Error: illegal operands `vamomaxuei64.v v4,\(a1\),v4,v0'
++.*Error: illegal operands `vamomaxuei64.v v0,\(a1\),v4,v0,v0.t'
++.*Error: illegal operands `vamomaxuei64.v x0,\(a1\),v4,v0,v0.t'
+diff --git a/gas/testsuite/gas/riscv/vector-insns-fail-zvamo.s b/gas/testsuite/gas/riscv/vector-insns-fail-zvamo.s
+new file mode 100644
+index 0000000000..0fd3c26a58
+--- /dev/null
++++ b/gas/testsuite/gas/riscv/vector-insns-fail-zvamo.s
+@@ -0,0 +1,217 @@
++# Vector AMO Operations
++
++	vamoaddei8.v v0, (a1), v4, v0		# OK
++	vamoaddei8.v v4, (a1), v4, v0		# vd must match vs3
++	vamoaddei8.v v0, (a1), v4, v0, v0.t	# vd overlap vm
++	vamoaddei8.v x0, (a1), v4, v0		# OK
++	vamoaddei8.v x0, (a1), v4, v0, v0.t	# vs3 overlap vm
++
++	vamoswapei8.v v0, (a1), v4, v0
++	vamoswapei8.v v4, (a1), v4, v0
++	vamoswapei8.v v0, (a1), v4, v0, v0.t
++	vamoswapei8.v x0, (a1), v4, v0
++	vamoswapei8.v x0, (a1), v4, v0, v0.t
++
++	vamoxorei8.v v0, (a1), v4, v0
++	vamoxorei8.v v4, (a1), v4, v0
++	vamoxorei8.v v0, (a1), v4, v0, v0.t
++	vamoxorei8.v x0, (a1), v4, v0
++	vamoxorei8.v x0, (a1), v4, v0, v0.t
++
++	vamoandei8.v v0, (a1), v4, v0
++	vamoandei8.v v4, (a1), v4, v0
++	vamoandei8.v v0, (a1), v4, v0, v0.t
++	vamoandei8.v x0, (a1), v4, v0
++	vamoandei8.v x0, (a1), v4, v0, v0.t
++
++	vamoorei8.v v0, (a1), v4, v0
++	vamoorei8.v v4, (a1), v4, v0
++	vamoorei8.v v0, (a1), v4, v0, v0.t
++	vamoorei8.v x0, (a1), v4, v0
++	vamoorei8.v x0, (a1), v4, v0, v0.t
++
++	vamominei8.v v0, (a1), v4, v0
++	vamominei8.v v4, (a1), v4, v0
++	vamominei8.v v0, (a1), v4, v0, v0.t
++	vamominei8.v x0, (a1), v4, v0
++	vamominei8.v x0, (a1), v4, v0, v0.t
++
++	vamomaxei8.v v0, (a1), v4, v0
++	vamomaxei8.v v4, (a1), v4, v0
++	vamomaxei8.v v0, (a1), v4, v0, v0.t
++	vamomaxei8.v x0, (a1), v4, v0
++	vamomaxei8.v x0, (a1), v4, v0, v0.t
++
++	vamominuei8.v v0, (a1), v4, v0
++	vamominuei8.v v4, (a1), v4, v0
++	vamominuei8.v v0, (a1), v4, v0, v0.t
++	vamominuei8.v x0, (a1), v4, v0
++	vamominuei8.v x0, (a1), v4, v0, v0.t
++
++	vamomaxuei8.v v0, (a1), v4, v0
++	vamomaxuei8.v v4, (a1), v4, v0
++	vamomaxuei8.v v0, (a1), v4, v0, v0.t
++	vamomaxuei8.v x0, (a1), v4, v0
++	vamomaxuei8.v x0, (a1), v4, v0, v0.t
++
++	vamoaddei16.v v0, (a1), v4, v0
++	vamoaddei16.v v4, (a1), v4, v0
++	vamoaddei16.v v0, (a1), v4, v0, v0.t
++	vamoaddei16.v x0, (a1), v4, v0
++	vamoaddei16.v x0, (a1), v4, v0, v0.t
++
++	vamoswapei16.v v0, (a1), v4, v0
++	vamoswapei16.v v0, (a1), v4, v0, v0.t
++	vamoswapei16.v v4, (a1), v4, v0
++	vamoswapei16.v x0, (a1), v4, v0
++	vamoswapei16.v x0, (a1), v4, v0, v0.t
++
++	vamoxorei16.v v0, (a1), v4, v0
++	vamoxorei16.v v0, (a1), v4, v0, v0.t
++	vamoxorei16.v v4, (a1), v4, v0
++	vamoxorei16.v x0, (a1), v4, v0
++	vamoxorei16.v x0, (a1), v4, v0, v0.t
++
++	vamoandei16.v v0, (a1), v4, v0
++	vamoandei16.v v0, (a1), v4, v0, v0.t
++	vamoandei16.v v4, (a1), v4, v0
++	vamoandei16.v x0, (a1), v4, v0
++	vamoandei16.v x0, (a1), v4, v0, v0.t
++
++	vamoorei16.v v0, (a1), v4, v0
++	vamoorei16.v v0, (a1), v4, v0, v0.t
++	vamoorei16.v v4, (a1), v4, v0
++	vamoorei16.v x0, (a1), v4, v0
++	vamoorei16.v x0, (a1), v4, v0, v0.t
++
++	vamominei16.v v0, (a1), v4, v0
++	vamominei16.v v0, (a1), v4, v0, v0.t
++	vamominei16.v v4, (a1), v4, v0
++	vamominei16.v x0, (a1), v4, v0
++	vamominei16.v x0, (a1), v4, v0, v0.t
++
++	vamomaxei16.v v0, (a1), v4, v0
++	vamomaxei16.v v0, (a1), v4, v0, v0.t
++	vamomaxei16.v v4, (a1), v4, v0
++	vamomaxei16.v x0, (a1), v4, v0
++	vamomaxei16.v x0, (a1), v4, v0, v0.t
++
++	vamominuei16.v v0, (a1), v4, v0
++	vamominuei16.v v0, (a1), v4, v0, v0.t
++	vamominuei16.v v4, (a1), v4, v0
++	vamominuei16.v x0, (a1), v4, v0
++	vamominuei16.v x0, (a1), v4, v0, v0.t
++
++	vamomaxuei16.v v0, (a1), v4, v0
++	vamomaxuei16.v v0, (a1), v4, v0, v0.t
++	vamomaxuei16.v v4, (a1), v4, v0
++	vamomaxuei16.v x0, (a1), v4, v0
++	vamomaxuei16.v x0, (a1), v4, v0, v0.t
++
++	vamoaddei32.v v0, (a1), v4, v0
++	vamoaddei32.v v0, (a1), v4, v0, v0.t
++	vamoaddei32.v v4, (a1), v4, v0
++	vamoaddei32.v x0, (a1), v4, v0
++	vamoaddei32.v x0, (a1), v4, v0, v0.t
++
++	vamoswapei32.v v0, (a1), v4, v0
++	vamoswapei32.v v4, (a1), v4, v0
++	vamoswapei32.v v0, (a1), v4, v0, v0.t
++	vamoswapei32.v x0, (a1), v4, v0
++	vamoswapei32.v x0, (a1), v4, v0, v0.t
++
++	vamoxorei32.v v0, (a1), v4, v0
++	vamoxorei32.v v4, (a1), v4, v0
++	vamoxorei32.v v0, (a1), v4, v0, v0.t
++	vamoxorei32.v x0, (a1), v4, v0
++	vamoxorei32.v x0, (a1), v4, v0, v0.t
++
++	vamoandei32.v v0, (a1), v4, v0
++	vamoandei32.v v4, (a1), v4, v0
++	vamoandei32.v v0, (a1), v4, v0, v0.t
++	vamoandei32.v x0, (a1), v4, v0
++	vamoandei32.v x0, (a1), v4, v0, v0.t
++
++	vamoorei32.v v0, (a1), v4, v0
++	vamoorei32.v v4, (a1), v4, v0
++	vamoorei32.v v0, (a1), v4, v0, v0.t
++	vamoorei32.v x0, (a1), v4, v0
++	vamoorei32.v x0, (a1), v4, v0, v0.t
++
++	vamominei32.v v0, (a1), v4, v0
++	vamominei32.v v4, (a1), v4, v0
++	vamominei32.v v0, (a1), v4, v0, v0.t
++	vamominei32.v x0, (a1), v4, v0
++	vamominei32.v x0, (a1), v4, v0, v0.t
++
++	vamomaxei32.v v0, (a1), v4, v0
++	vamomaxei32.v v4, (a1), v4, v0
++	vamomaxei32.v v0, (a1), v4, v0, v0.t
++	vamomaxei32.v x0, (a1), v4, v0
++	vamomaxei32.v x0, (a1), v4, v0, v0.t
++
++	vamominuei32.v v0, (a1), v4, v0
++	vamominuei32.v v4, (a1), v4, v0
++	vamominuei32.v v0, (a1), v4, v0, v0.t
++	vamominuei32.v x0, (a1), v4, v0
++	vamominuei32.v x0, (a1), v4, v0, v0.t
++
++	vamomaxuei32.v v0, (a1), v4, v0
++	vamomaxuei32.v v4, (a1), v4, v0
++	vamomaxuei32.v v0, (a1), v4, v0, v0.t
++	vamomaxuei32.v x0, (a1), v4, v0
++	vamomaxuei32.v x0, (a1), v4, v0, v0.t
++
++	vamoaddei64.v v0, (a1), v4, v0
++	vamoaddei64.v v4, (a1), v4, v0
++	vamoaddei64.v v0, (a1), v4, v0, v0.t
++	vamoaddei64.v x0, (a1), v4, v0
++	vamoaddei64.v x0, (a1), v4, v0, v0.t
++
++	vamoswapei64.v v0, (a1), v4, v0
++	vamoswapei64.v v4, (a1), v4, v0
++	vamoswapei64.v v0, (a1), v4, v0, v0.t
++	vamoswapei64.v x0, (a1), v4, v0
++	vamoswapei64.v x0, (a1), v4, v0, v0.t
++
++	vamoxorei64.v v0, (a1), v4, v0
++	vamoxorei64.v v4, (a1), v4, v0
++	vamoxorei64.v v0, (a1), v4, v0, v0.t
++	vamoxorei64.v x0, (a1), v4, v0
++	vamoxorei64.v x0, (a1), v4, v0, v0.t
++
++	vamoandei64.v v0, (a1), v4, v0
++	vamoandei64.v v4, (a1), v4, v0
++	vamoandei64.v v0, (a1), v4, v0, v0.t
++	vamoandei64.v x0, (a1), v4, v0
++	vamoandei64.v x0, (a1), v4, v0, v0.t
++
++	vamoorei64.v v0, (a1), v4, v0
++	vamoorei64.v v4, (a1), v4, v0
++	vamoorei64.v v0, (a1), v4, v0, v0.t
++	vamoorei64.v x0, (a1), v4, v0
++	vamoorei64.v x0, (a1), v4, v0, v0.t
++
++	vamominei64.v v0, (a1), v4, v0
++	vamominei64.v v4, (a1), v4, v0
++	vamominei64.v v0, (a1), v4, v0, v0.t
++	vamominei64.v x0, (a1), v4, v0
++	vamominei64.v x0, (a1), v4, v0, v0.t
++
++	vamomaxei64.v v0, (a1), v4, v0
++	vamomaxei64.v v4, (a1), v4, v0
++	vamomaxei64.v v0, (a1), v4, v0, v0.t
++	vamomaxei64.v x0, (a1), v4, v0
++	vamomaxei64.v x0, (a1), v4, v0, v0.t
++
++	vamominuei64.v v0, (a1), v4, v0
++	vamominuei64.v v4, (a1), v4, v0
++	vamominuei64.v v0, (a1), v4, v0, v0.t
++	vamominuei64.v x0, (a1), v4, v0
++	vamominuei64.v x0, (a1), v4, v0, v0.t
++
++	vamomaxuei64.v v0, (a1), v4, v0
++	vamomaxuei64.v v4, (a1), v4, v0
++	vamomaxuei64.v v0, (a1), v4, v0, v0.t
++	vamomaxuei64.v x0, (a1), v4, v0
++	vamomaxuei64.v x0, (a1), v4, v0, v0.t
+diff --git a/gas/testsuite/gas/riscv/vector-insns-fail-zvqmac.d b/gas/testsuite/gas/riscv/vector-insns-fail-zvqmac.d
+new file mode 100644
+index 0000000000..912408ed06
+--- /dev/null
++++ b/gas/testsuite/gas/riscv/vector-insns-fail-zvqmac.d
+@@ -0,0 +1,3 @@
++#as: -march=rv32iv_zvqmac -mcheck-constraints
++#source: vector-insns-fail-zvqmac.s
++#error_output: vector-insns-fail-zvqmac.l
+diff --git a/gas/testsuite/gas/riscv/vector-insns-fail-zvqmac.l b/gas/testsuite/gas/riscv/vector-insns-fail-zvqmac.l
+new file mode 100644
+index 0000000000..e5c157fd89
+--- /dev/null
++++ b/gas/testsuite/gas/riscv/vector-insns-fail-zvqmac.l
+@@ -0,0 +1,35 @@
++.*: Assembler messages:
++.*Error: illegal operands `vqmaccu.vv v2,v4,v8'
++.*Error: illegal operands `vqmaccu.vv v4,v4,v8'
++.*Error: illegal operands `vqmaccu.vv v4,v7,v8'
++.*Error: illegal operands `vqmaccu.vv v8,v4,v8'
++.*Error: illegal operands `vqmaccu.vv v8,v4,v11'
++.*Error: illegal operands `vqmaccu.vv v0,v4,v8,v0.t'
++.*Error: illegal operands `vqmaccu.vx v2,a1,v4'
++.*Error: illegal operands `vqmaccu.vx v4,a1,v4'
++.*Error: illegal operands `vqmaccu.vx v4,a1,v7'
++.*Error: illegal operands `vqmaccu.vx v0,a1,v4,v0.t'
++.*Error: illegal operands `vqmacc.vv v2,v4,v8'
++.*Error: illegal operands `vqmacc.vv v4,v4,v8'
++.*Error: illegal operands `vqmacc.vv v4,v7,v8'
++.*Error: illegal operands `vqmacc.vv v8,v4,v8'
++.*Error: illegal operands `vqmacc.vv v8,v4,v11'
++.*Error: illegal operands `vqmacc.vv v0,v4,v8,v0.t'
++.*Error: illegal operands `vqmacc.vx v2,a1,v4'
++.*Error: illegal operands `vqmacc.vx v4,a1,v4'
++.*Error: illegal operands `vqmacc.vx v4,a1,v7'
++.*Error: illegal operands `vqmacc.vx v0,a1,v4,v0.t'
++.*Error: illegal operands `vqmaccsu.vv v2,v4,v8'
++.*Error: illegal operands `vqmaccsu.vv v4,v4,v8'
++.*Error: illegal operands `vqmaccsu.vv v4,v7,v8'
++.*Error: illegal operands `vqmaccsu.vv v8,v4,v8'
++.*Error: illegal operands `vqmaccsu.vv v8,v4,v11'
++.*Error: illegal operands `vqmaccsu.vv v0,v4,v8,v0.t'
++.*Error: illegal operands `vqmaccsu.vx v2,a1,v4'
++.*Error: illegal operands `vqmaccsu.vx v4,a1,v4'
++.*Error: illegal operands `vqmaccsu.vx v4,a1,v7'
++.*Error: illegal operands `vqmaccsu.vx v0,a1,v4,v0.t'
++.*Error: illegal operands `vqmaccus.vx v2,a1,v4'
++.*Error: illegal operands `vqmaccus.vx v4,a1,v4'
++.*Error: illegal operands `vqmaccus.vx v4,a1,v7'
++.*Error: illegal operands `vqmaccus.vx v0,a1,v4,v0.t'
+diff --git a/gas/testsuite/gas/riscv/vector-insns-fail-zvqmac.s b/gas/testsuite/gas/riscv/vector-insns-fail-zvqmac.s
+new file mode 100644
+index 0000000000..930e211dae
+--- /dev/null
++++ b/gas/testsuite/gas/riscv/vector-insns-fail-zvqmac.s
+@@ -0,0 +1,39 @@
++# Quad-Widening Vector Arithmetic Instructions
++
++	vqmaccu.vv v2, v4, v8		# vd should be multiple of 4
++	vqmaccu.vv v4, v4, v8		# vd overlap vs1
++	vqmaccu.vv v4, v7, v8		# vd overlap vs1
++	vqmaccu.vv v8, v4, v8		# vd overlap vs2
++	vqmaccu.vv v8, v4, v11		# vd overlap vs2
++	vqmaccu.vv v0, v4, v8, v0.t	# vd overlap vm
++	vqmaccu.vx v2, a1, v4		# vd should be multiple of 4
++	vqmaccu.vx v4, a1, v4		# vd overlap vs2
++	vqmaccu.vx v4, a1, v7		# vd overlap vs2
++	vqmaccu.vx v0, a1, v4, v0.t	# vd overlap vm
++
++	vqmacc.vv v2, v4, v8
++	vqmacc.vv v4, v4, v8
++	vqmacc.vv v4, v7, v8
++	vqmacc.vv v8, v4, v8
++	vqmacc.vv v8, v4, v11
++	vqmacc.vv v0, v4, v8, v0.t
++	vqmacc.vx v2, a1, v4
++	vqmacc.vx v4, a1, v4
++	vqmacc.vx v4, a1, v7
++	vqmacc.vx v0, a1, v4, v0.t
++
++	vqmaccsu.vv v2, v4, v8
++	vqmaccsu.vv v4, v4, v8
++	vqmaccsu.vv v4, v7, v8
++	vqmaccsu.vv v8, v4, v8
++	vqmaccsu.vv v8, v4, v11
++	vqmaccsu.vv v0, v4, v8, v0.t
++	vqmaccsu.vx v2, a1, v4
++	vqmaccsu.vx v4, a1, v4
++	vqmaccsu.vx v4, a1, v7
++	vqmaccsu.vx v0, a1, v4, v0.t
++
++	vqmaccus.vx v2, a1, v4		# vd should be multiple of 4
++	vqmaccus.vx v4, a1, v4		# vd overlap vs2
++	vqmaccus.vx v4, a1, v7		# vd overlap vs2
++	vqmaccus.vx v0, a1, v4, v0.t	# vd overlap vm
+diff --git a/opcodes/riscv-opc.c b/opcodes/riscv-opc.c
+index c7ecb7c965..58190fd7c9 100644
+--- a/opcodes/riscv-opc.c
++++ b/opcodes/riscv-opc.c
+@@ -381,16 +381,18 @@ match_quad_vd_neq_vs2_neq_vm (const struct riscv_opcode *op,
+ }
+ 
+ static int
+-match_narrow_vd_neq_vs2 (const struct riscv_opcode *op,
+-			 insn_t insn,
+-			 int constraints)
++match_narrow_vd_neq_vs2_neq_vm (const struct riscv_opcode *op,
++				insn_t insn,
++				int constraints)
+ {
+   int vd = (insn & MASK_VD) >> OP_SH_VD;
+   int vs2 = (insn & MASK_VS2) >> OP_SH_VS2;
++  int vm = (insn & MASK_VMASK) >> OP_SH_VMASK;
+ 
+   if (constraints
+       && ((vs2 % 2) != 0
+-	  || (vd >= vs2 && vd <= (vs2 + 1))))
++	  || (vd >= vs2 && vd <= (vs2 + 1))
++	  || (!vm && vd >= vm && vd <= (vm + 1))))
+     return 0;
+ 
+   return match_opcode (op, insn, 0);
+@@ -432,19 +434,10 @@ match_vd_neq_vs2_neq_vm (const struct riscv_opcode *op,
+   return match_opcode (op, insn, 0);
+ }
+ 
+-static int
+-match_vd_neq_vs2 (const struct riscv_opcode *op,
+-		  insn_t insn,
+-		  int constraints)
+-{
+-  int vd = (insn & MASK_VD) >> OP_SH_VD;
+-  int vs2 = (insn & MASK_VS2) >> OP_SH_VS2;
+-
+-   if (constraints && vs2 == vd)
+-    return 0;
+-
+-  return match_opcode (op, insn, 0);
+-}
++/* v[m]adc and v[m]sbc use the vm encoding to encode the
++   carry-in v0 register.  The carry-in v0 register can not
++   overlap with the vd, too.  Therefore, we use the same
++   match_vd_neq_vm to check the overlap constraints.  */
+ 
+ static int
+ match_vd_neq_vm (const struct riscv_opcode *op,
+@@ -1066,305 +1059,305 @@ const struct riscv_opcode riscv_opcodes[] =
+ {"vsetvl",     0, INSN_CLASS_V,  "d,s,t", MATCH_VSETVL, MASK_VSETVL, match_opcode, 0},
+ {"vsetvli",    0, INSN_CLASS_V,  "d,s,Vc", MATCH_VSETVLI, MASK_VSETVLI, match_opcode, 0},
+ 
+-{"vle8.v",     0, INSN_CLASS_V,  "Vd,0(s)Vm", MATCH_VLE8V, MASK_VLE8V, match_opcode, INSN_DREF },
+-{"vle16.v",    0, INSN_CLASS_V,  "Vd,0(s)Vm", MATCH_VLE16V, MASK_VLE16V, match_opcode, INSN_DREF },
+-{"vle32.v",    0, INSN_CLASS_V,  "Vd,0(s)Vm", MATCH_VLE32V, MASK_VLE32V, match_opcode, INSN_DREF },
+-{"vle64.v",    0, INSN_CLASS_V,  "Vd,0(s)Vm", MATCH_VLE64V, MASK_VLE64V, match_opcode, INSN_DREF },
+-{"vle128.v",   0, INSN_CLASS_V,  "Vd,0(s)Vm", MATCH_VLE128V, MASK_VLE128V, match_opcode, INSN_DREF },
+-{"vle256.v",   0, INSN_CLASS_V,  "Vd,0(s)Vm", MATCH_VLE256V, MASK_VLE256V, match_opcode, INSN_DREF },
+-{"vle512.v",   0, INSN_CLASS_V,  "Vd,0(s)Vm", MATCH_VLE512V, MASK_VLE512V, match_opcode, INSN_DREF },
+-{"vle1024.v",  0, INSN_CLASS_V,  "Vd,0(s)Vm", MATCH_VLE1024V, MASK_VLE1024V, match_opcode, INSN_DREF },
+-
+-{"vse8.v",     0, INSN_CLASS_V,  "Vd,0(s)Vm", MATCH_VSE8V, MASK_VSE8V, match_opcode, INSN_DREF },
+-{"vse16.v",    0, INSN_CLASS_V,  "Vd,0(s)Vm", MATCH_VSE16V, MASK_VSE16V, match_opcode, INSN_DREF },
+-{"vse32.v",    0, INSN_CLASS_V,  "Vd,0(s)Vm", MATCH_VSE32V, MASK_VSE32V, match_opcode, INSN_DREF },
+-{"vse64.v",    0, INSN_CLASS_V,  "Vd,0(s)Vm", MATCH_VSE64V, MASK_VSE64V, match_opcode, INSN_DREF },
+-{"vse128.v",   0, INSN_CLASS_V,  "Vd,0(s)Vm", MATCH_VSE128V, MASK_VSE128V, match_opcode, INSN_DREF },
+-{"vse256.v",   0, INSN_CLASS_V,  "Vd,0(s)Vm", MATCH_VSE256V, MASK_VSE256V, match_opcode, INSN_DREF },
+-{"vse512.v",   0, INSN_CLASS_V,  "Vd,0(s)Vm", MATCH_VSE512V, MASK_VSE512V, match_opcode, INSN_DREF },
+-{"vse1024.v",  0, INSN_CLASS_V,  "Vd,0(s)Vm", MATCH_VSE1024V, MASK_VSE1024V, match_opcode, INSN_DREF },
+-
+-{"vlse8.v",    0, INSN_CLASS_V,  "Vd,0(s),tVm", MATCH_VLSE8V, MASK_VLSE8V, match_opcode, INSN_DREF },
+-{"vlse16.v",   0, INSN_CLASS_V,  "Vd,0(s),tVm", MATCH_VLSE16V, MASK_VLSE16V, match_opcode, INSN_DREF },
+-{"vlse32.v",   0, INSN_CLASS_V,  "Vd,0(s),tVm", MATCH_VLSE32V, MASK_VLSE32V, match_opcode, INSN_DREF },
+-{"vlse64.v",   0, INSN_CLASS_V,  "Vd,0(s),tVm", MATCH_VLSE64V, MASK_VLSE64V, match_opcode, INSN_DREF },
+-{"vlse128.v",  0, INSN_CLASS_V,  "Vd,0(s),tVm", MATCH_VLSE128V, MASK_VLSE128V, match_opcode, INSN_DREF },
+-{"vlse256.v",  0, INSN_CLASS_V,  "Vd,0(s),tVm", MATCH_VLSE256V, MASK_VLSE256V, match_opcode, INSN_DREF },
+-{"vlse512.v",  0, INSN_CLASS_V,  "Vd,0(s),tVm", MATCH_VLSE512V, MASK_VLSE512V, match_opcode, INSN_DREF },
+-{"vlse1024.v", 0, INSN_CLASS_V,  "Vd,0(s),tVm", MATCH_VLSE1024V, MASK_VLSE1024V, match_opcode, INSN_DREF },
+-
+-{"vsse8.v",    0, INSN_CLASS_V,  "Vd,0(s),tVm", MATCH_VSSE8V, MASK_VSSE8V, match_opcode, INSN_DREF },
+-{"vsse16.v",   0, INSN_CLASS_V,  "Vd,0(s),tVm", MATCH_VSSE16V, MASK_VSSE16V, match_opcode, INSN_DREF },
+-{"vsse32.v",   0, INSN_CLASS_V,  "Vd,0(s),tVm", MATCH_VSSE32V, MASK_VSSE32V, match_opcode, INSN_DREF },
+-{"vsse64.v",   0, INSN_CLASS_V,  "Vd,0(s),tVm", MATCH_VSSE64V, MASK_VSSE64V, match_opcode, INSN_DREF },
+-{"vsse128.v",  0, INSN_CLASS_V,  "Vd,0(s),tVm", MATCH_VSSE128V, MASK_VSSE128V, match_opcode, INSN_DREF },
+-{"vsse256.v",  0, INSN_CLASS_V,  "Vd,0(s),tVm", MATCH_VSSE256V, MASK_VSSE256V, match_opcode, INSN_DREF },
+-{"vsse512.v",  0, INSN_CLASS_V,  "Vd,0(s),tVm", MATCH_VSSE512V, MASK_VSSE512V, match_opcode, INSN_DREF },
+-{"vsse1024.v", 0, INSN_CLASS_V,  "Vd,0(s),tVm", MATCH_VSSE1024V, MASK_VSSE1024V, match_opcode, INSN_DREF },
+-
+-{"vlxei8.v",   0, INSN_CLASS_V,  "Vd,0(s),VtVm", MATCH_VLXEI8V, MASK_VLXEI8V, match_opcode, INSN_DREF },
+-{"vlxei16.v",  0, INSN_CLASS_V,  "Vd,0(s),VtVm", MATCH_VLXEI16V, MASK_VLXEI16V, match_opcode, INSN_DREF },
+-{"vlxei32.v",  0, INSN_CLASS_V,  "Vd,0(s),VtVm", MATCH_VLXEI32V, MASK_VLXEI32V, match_opcode, INSN_DREF },
+-{"vlxei64.v",  0, INSN_CLASS_V,  "Vd,0(s),VtVm", MATCH_VLXEI64V, MASK_VLXEI64V, match_opcode, INSN_DREF },
+-
+-{"vsxei8.v",   0, INSN_CLASS_V,  "Vd,0(s),VtVm", MATCH_VSXEI8V, MASK_VSXEI8V, match_opcode, INSN_DREF },
+-{"vsxei16.v",  0, INSN_CLASS_V,  "Vd,0(s),VtVm", MATCH_VSXEI16V, MASK_VSXEI16V, match_opcode, INSN_DREF },
+-{"vsxei32.v",  0, INSN_CLASS_V,  "Vd,0(s),VtVm", MATCH_VSXEI32V, MASK_VSXEI32V, match_opcode, INSN_DREF },
+-{"vsxei64.v",  0, INSN_CLASS_V,  "Vd,0(s),VtVm", MATCH_VSXEI64V, MASK_VSXEI64V, match_opcode, INSN_DREF },
+-
+-{"vsuxei8.v",   0, INSN_CLASS_V,  "Vd,0(s),VtVm", MATCH_VSUXEI8V, MASK_VSUXEI8V, match_opcode, INSN_DREF },
+-{"vsuxei16.v",  0, INSN_CLASS_V,  "Vd,0(s),VtVm", MATCH_VSUXEI16V, MASK_VSUXEI16V, match_opcode, INSN_DREF },
+-{"vsuxei32.v",  0, INSN_CLASS_V,  "Vd,0(s),VtVm", MATCH_VSUXEI32V, MASK_VSUXEI32V, match_opcode, INSN_DREF },
+-{"vsuxei64.v",  0, INSN_CLASS_V,  "Vd,0(s),VtVm", MATCH_VSUXEI64V, MASK_VSUXEI64V, match_opcode, INSN_DREF },
+-
+-{"vle8ff.v",    0, INSN_CLASS_V,  "Vd,0(s)Vm", MATCH_VLE8FFV, MASK_VLE8FFV, match_opcode, INSN_DREF },
+-{"vle16ff.v",   0, INSN_CLASS_V,  "Vd,0(s)Vm", MATCH_VLE16FFV, MASK_VLE16FFV, match_opcode, INSN_DREF },
+-{"vle32ff.v",   0, INSN_CLASS_V,  "Vd,0(s)Vm", MATCH_VLE32FFV, MASK_VLE32FFV, match_opcode, INSN_DREF },
+-{"vle64ff.v",   0, INSN_CLASS_V,  "Vd,0(s)Vm", MATCH_VLE64FFV, MASK_VLE64FFV, match_opcode, INSN_DREF },
+-{"vle128ff.v",  0, INSN_CLASS_V,  "Vd,0(s)Vm", MATCH_VLE128FFV, MASK_VLE128FFV, match_opcode, INSN_DREF },
+-{"vle256ff.v",  0, INSN_CLASS_V,  "Vd,0(s)Vm", MATCH_VLE256FFV, MASK_VLE256FFV, match_opcode, INSN_DREF },
+-{"vle512ff.v",  0, INSN_CLASS_V,  "Vd,0(s)Vm", MATCH_VLE512FFV, MASK_VLE512FFV, match_opcode, INSN_DREF },
+-{"vle1024ff.v", 0, INSN_CLASS_V,  "Vd,0(s)Vm", MATCH_VLE1024FFV, MASK_VLE1024FFV, match_opcode, INSN_DREF },
++{"vle8.v",     0, INSN_CLASS_V,  "Vd,0(s)Vm", MATCH_VLE8V, MASK_VLE8V, match_vd_neq_vm, INSN_DREF },
++{"vle16.v",    0, INSN_CLASS_V,  "Vd,0(s)Vm", MATCH_VLE16V, MASK_VLE16V, match_vd_neq_vm, INSN_DREF },
++{"vle32.v",    0, INSN_CLASS_V,  "Vd,0(s)Vm", MATCH_VLE32V, MASK_VLE32V, match_vd_neq_vm, INSN_DREF },
++{"vle64.v",    0, INSN_CLASS_V,  "Vd,0(s)Vm", MATCH_VLE64V, MASK_VLE64V, match_vd_neq_vm, INSN_DREF },
++{"vle128.v",   0, INSN_CLASS_V,  "Vd,0(s)Vm", MATCH_VLE128V, MASK_VLE128V, match_vd_neq_vm, INSN_DREF },
++{"vle256.v",   0, INSN_CLASS_V,  "Vd,0(s)Vm", MATCH_VLE256V, MASK_VLE256V, match_vd_neq_vm, INSN_DREF },
++{"vle512.v",   0, INSN_CLASS_V,  "Vd,0(s)Vm", MATCH_VLE512V, MASK_VLE512V, match_vd_neq_vm, INSN_DREF },
++{"vle1024.v",  0, INSN_CLASS_V,  "Vd,0(s)Vm", MATCH_VLE1024V, MASK_VLE1024V, match_vd_neq_vm, INSN_DREF },
++
++{"vse8.v",     0, INSN_CLASS_V,  "Vd,0(s)Vm", MATCH_VSE8V, MASK_VSE8V, match_vd_neq_vm, INSN_DREF },
++{"vse16.v",    0, INSN_CLASS_V,  "Vd,0(s)Vm", MATCH_VSE16V, MASK_VSE16V, match_vd_neq_vm, INSN_DREF },
++{"vse32.v",    0, INSN_CLASS_V,  "Vd,0(s)Vm", MATCH_VSE32V, MASK_VSE32V, match_vd_neq_vm, INSN_DREF },
++{"vse64.v",    0, INSN_CLASS_V,  "Vd,0(s)Vm", MATCH_VSE64V, MASK_VSE64V, match_vd_neq_vm, INSN_DREF },
++{"vse128.v",   0, INSN_CLASS_V,  "Vd,0(s)Vm", MATCH_VSE128V, MASK_VSE128V, match_vd_neq_vm, INSN_DREF },
++{"vse256.v",   0, INSN_CLASS_V,  "Vd,0(s)Vm", MATCH_VSE256V, MASK_VSE256V, match_vd_neq_vm, INSN_DREF },
++{"vse512.v",   0, INSN_CLASS_V,  "Vd,0(s)Vm", MATCH_VSE512V, MASK_VSE512V, match_vd_neq_vm, INSN_DREF },
++{"vse1024.v",  0, INSN_CLASS_V,  "Vd,0(s)Vm", MATCH_VSE1024V, MASK_VSE1024V, match_vd_neq_vm, INSN_DREF },
++
++{"vlse8.v",    0, INSN_CLASS_V,  "Vd,0(s),tVm", MATCH_VLSE8V, MASK_VLSE8V, match_vd_neq_vm, INSN_DREF },
++{"vlse16.v",   0, INSN_CLASS_V,  "Vd,0(s),tVm", MATCH_VLSE16V, MASK_VLSE16V, match_vd_neq_vm, INSN_DREF },
++{"vlse32.v",   0, INSN_CLASS_V,  "Vd,0(s),tVm", MATCH_VLSE32V, MASK_VLSE32V, match_vd_neq_vm, INSN_DREF },
++{"vlse64.v",   0, INSN_CLASS_V,  "Vd,0(s),tVm", MATCH_VLSE64V, MASK_VLSE64V, match_vd_neq_vm, INSN_DREF },
++{"vlse128.v",  0, INSN_CLASS_V,  "Vd,0(s),tVm", MATCH_VLSE128V, MASK_VLSE128V, match_vd_neq_vm, INSN_DREF },
++{"vlse256.v",  0, INSN_CLASS_V,  "Vd,0(s),tVm", MATCH_VLSE256V, MASK_VLSE256V, match_vd_neq_vm, INSN_DREF },
++{"vlse512.v",  0, INSN_CLASS_V,  "Vd,0(s),tVm", MATCH_VLSE512V, MASK_VLSE512V, match_vd_neq_vm, INSN_DREF },
++{"vlse1024.v", 0, INSN_CLASS_V,  "Vd,0(s),tVm", MATCH_VLSE1024V, MASK_VLSE1024V, match_vd_neq_vm, INSN_DREF },
++
++{"vsse8.v",    0, INSN_CLASS_V,  "Vd,0(s),tVm", MATCH_VSSE8V, MASK_VSSE8V, match_vd_neq_vm, INSN_DREF },
++{"vsse16.v",   0, INSN_CLASS_V,  "Vd,0(s),tVm", MATCH_VSSE16V, MASK_VSSE16V, match_vd_neq_vm, INSN_DREF },
++{"vsse32.v",   0, INSN_CLASS_V,  "Vd,0(s),tVm", MATCH_VSSE32V, MASK_VSSE32V, match_vd_neq_vm, INSN_DREF },
++{"vsse64.v",   0, INSN_CLASS_V,  "Vd,0(s),tVm", MATCH_VSSE64V, MASK_VSSE64V, match_vd_neq_vm, INSN_DREF },
++{"vsse128.v",  0, INSN_CLASS_V,  "Vd,0(s),tVm", MATCH_VSSE128V, MASK_VSSE128V, match_vd_neq_vm, INSN_DREF },
++{"vsse256.v",  0, INSN_CLASS_V,  "Vd,0(s),tVm", MATCH_VSSE256V, MASK_VSSE256V, match_vd_neq_vm, INSN_DREF },
++{"vsse512.v",  0, INSN_CLASS_V,  "Vd,0(s),tVm", MATCH_VSSE512V, MASK_VSSE512V, match_vd_neq_vm, INSN_DREF },
++{"vsse1024.v", 0, INSN_CLASS_V,  "Vd,0(s),tVm", MATCH_VSSE1024V, MASK_VSSE1024V, match_vd_neq_vm, INSN_DREF },
++
++{"vlxei8.v",   0, INSN_CLASS_V,  "Vd,0(s),VtVm", MATCH_VLXEI8V, MASK_VLXEI8V, match_vd_neq_vm, INSN_DREF },
++{"vlxei16.v",  0, INSN_CLASS_V,  "Vd,0(s),VtVm", MATCH_VLXEI16V, MASK_VLXEI16V, match_vd_neq_vm, INSN_DREF },
++{"vlxei32.v",  0, INSN_CLASS_V,  "Vd,0(s),VtVm", MATCH_VLXEI32V, MASK_VLXEI32V, match_vd_neq_vm, INSN_DREF },
++{"vlxei64.v",  0, INSN_CLASS_V,  "Vd,0(s),VtVm", MATCH_VLXEI64V, MASK_VLXEI64V, match_vd_neq_vm, INSN_DREF },
++
++{"vsxei8.v",   0, INSN_CLASS_V,  "Vd,0(s),VtVm", MATCH_VSXEI8V, MASK_VSXEI8V, match_vd_neq_vm, INSN_DREF },
++{"vsxei16.v",  0, INSN_CLASS_V,  "Vd,0(s),VtVm", MATCH_VSXEI16V, MASK_VSXEI16V, match_vd_neq_vm, INSN_DREF },
++{"vsxei32.v",  0, INSN_CLASS_V,  "Vd,0(s),VtVm", MATCH_VSXEI32V, MASK_VSXEI32V, match_vd_neq_vm, INSN_DREF },
++{"vsxei64.v",  0, INSN_CLASS_V,  "Vd,0(s),VtVm", MATCH_VSXEI64V, MASK_VSXEI64V, match_vd_neq_vm, INSN_DREF },
++
++{"vsuxei8.v",   0, INSN_CLASS_V,  "Vd,0(s),VtVm", MATCH_VSUXEI8V, MASK_VSUXEI8V, match_vd_neq_vm, INSN_DREF },
++{"vsuxei16.v",  0, INSN_CLASS_V,  "Vd,0(s),VtVm", MATCH_VSUXEI16V, MASK_VSUXEI16V, match_vd_neq_vm, INSN_DREF },
++{"vsuxei32.v",  0, INSN_CLASS_V,  "Vd,0(s),VtVm", MATCH_VSUXEI32V, MASK_VSUXEI32V, match_vd_neq_vm, INSN_DREF },
++{"vsuxei64.v",  0, INSN_CLASS_V,  "Vd,0(s),VtVm", MATCH_VSUXEI64V, MASK_VSUXEI64V, match_vd_neq_vm, INSN_DREF },
++
++{"vle8ff.v",    0, INSN_CLASS_V,  "Vd,0(s)Vm", MATCH_VLE8FFV, MASK_VLE8FFV, match_vd_neq_vm, INSN_DREF },
++{"vle16ff.v",   0, INSN_CLASS_V,  "Vd,0(s)Vm", MATCH_VLE16FFV, MASK_VLE16FFV, match_vd_neq_vm, INSN_DREF },
++{"vle32ff.v",   0, INSN_CLASS_V,  "Vd,0(s)Vm", MATCH_VLE32FFV, MASK_VLE32FFV, match_vd_neq_vm, INSN_DREF },
++{"vle64ff.v",   0, INSN_CLASS_V,  "Vd,0(s)Vm", MATCH_VLE64FFV, MASK_VLE64FFV, match_vd_neq_vm, INSN_DREF },
++{"vle128ff.v",  0, INSN_CLASS_V,  "Vd,0(s)Vm", MATCH_VLE128FFV, MASK_VLE128FFV, match_vd_neq_vm, INSN_DREF },
++{"vle256ff.v",  0, INSN_CLASS_V,  "Vd,0(s)Vm", MATCH_VLE256FFV, MASK_VLE256FFV, match_vd_neq_vm, INSN_DREF },
++{"vle512ff.v",  0, INSN_CLASS_V,  "Vd,0(s)Vm", MATCH_VLE512FFV, MASK_VLE512FFV, match_vd_neq_vm, INSN_DREF },
++{"vle1024ff.v", 0, INSN_CLASS_V,  "Vd,0(s)Vm", MATCH_VLE1024FFV, MASK_VLE1024FFV, match_vd_neq_vm, INSN_DREF },
+ 
+ {"vlseg2e8.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s)Vm", MATCH_VLSEG2E8V, MASK_VLSEG2E8V, match_vd_neq_vm, INSN_DREF },
+-{"vsseg2e8.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s)Vm", MATCH_VSSEG2E8V, MASK_VSSEG2E8V, match_opcode, INSN_DREF },
++{"vsseg2e8.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s)Vm", MATCH_VSSEG2E8V, MASK_VSSEG2E8V, match_vd_neq_vm, INSN_DREF },
+ {"vlseg3e8.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s)Vm", MATCH_VLSEG3E8V, MASK_VLSEG3E8V, match_vd_neq_vm, INSN_DREF },
+-{"vsseg3e8.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s)Vm", MATCH_VSSEG3E8V, MASK_VSSEG3E8V, match_opcode, INSN_DREF },
++{"vsseg3e8.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s)Vm", MATCH_VSSEG3E8V, MASK_VSSEG3E8V, match_vd_neq_vm, INSN_DREF },
+ {"vlseg4e8.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s)Vm", MATCH_VLSEG4E8V, MASK_VLSEG4E8V, match_vd_neq_vm, INSN_DREF },
+-{"vsseg4e8.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s)Vm", MATCH_VSSEG4E8V, MASK_VSSEG4E8V, match_opcode, INSN_DREF },
++{"vsseg4e8.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s)Vm", MATCH_VSSEG4E8V, MASK_VSSEG4E8V, match_vd_neq_vm, INSN_DREF },
+ {"vlseg5e8.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s)Vm", MATCH_VLSEG5E8V, MASK_VLSEG5E8V, match_vd_neq_vm, INSN_DREF },
+-{"vsseg5e8.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s)Vm", MATCH_VSSEG5E8V, MASK_VSSEG5E8V, match_opcode, INSN_DREF },
++{"vsseg5e8.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s)Vm", MATCH_VSSEG5E8V, MASK_VSSEG5E8V, match_vd_neq_vm, INSN_DREF },
+ {"vlseg6e8.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s)Vm", MATCH_VLSEG6E8V, MASK_VLSEG6E8V, match_vd_neq_vm, INSN_DREF },
+-{"vsseg6e8.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s)Vm", MATCH_VSSEG6E8V, MASK_VSSEG6E8V, match_opcode, INSN_DREF },
++{"vsseg6e8.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s)Vm", MATCH_VSSEG6E8V, MASK_VSSEG6E8V, match_vd_neq_vm, INSN_DREF },
+ {"vlseg7e8.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s)Vm", MATCH_VLSEG7E8V, MASK_VLSEG7E8V, match_vd_neq_vm, INSN_DREF },
+-{"vsseg7e8.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s)Vm", MATCH_VSSEG7E8V, MASK_VSSEG7E8V, match_opcode, INSN_DREF },
++{"vsseg7e8.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s)Vm", MATCH_VSSEG7E8V, MASK_VSSEG7E8V, match_vd_neq_vm, INSN_DREF },
+ {"vlseg8e8.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s)Vm", MATCH_VLSEG8E8V, MASK_VLSEG8E8V, match_vd_neq_vm, INSN_DREF },
+-{"vsseg8e8.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s)Vm", MATCH_VSSEG8E8V, MASK_VSSEG8E8V, match_opcode, INSN_DREF },
++{"vsseg8e8.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s)Vm", MATCH_VSSEG8E8V, MASK_VSSEG8E8V, match_vd_neq_vm, INSN_DREF },
+ 
+ {"vlseg2e16.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s)Vm", MATCH_VLSEG2E16V, MASK_VLSEG2E16V, match_vd_neq_vm, INSN_DREF },
+-{"vsseg2e16.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s)Vm", MATCH_VSSEG2E16V, MASK_VSSEG2E16V, match_opcode, INSN_DREF },
++{"vsseg2e16.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s)Vm", MATCH_VSSEG2E16V, MASK_VSSEG2E16V, match_vd_neq_vm, INSN_DREF },
+ {"vlseg3e16.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s)Vm", MATCH_VLSEG3E16V, MASK_VLSEG3E16V, match_vd_neq_vm, INSN_DREF },
+-{"vsseg3e16.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s)Vm", MATCH_VSSEG3E16V, MASK_VSSEG3E16V, match_opcode, INSN_DREF },
++{"vsseg3e16.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s)Vm", MATCH_VSSEG3E16V, MASK_VSSEG3E16V, match_vd_neq_vm, INSN_DREF },
+ {"vlseg4e16.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s)Vm", MATCH_VLSEG4E16V, MASK_VLSEG4E16V, match_vd_neq_vm, INSN_DREF },
+-{"vsseg4e16.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s)Vm", MATCH_VSSEG4E16V, MASK_VSSEG4E16V, match_opcode, INSN_DREF },
++{"vsseg4e16.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s)Vm", MATCH_VSSEG4E16V, MASK_VSSEG4E16V, match_vd_neq_vm, INSN_DREF },
+ {"vlseg5e16.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s)Vm", MATCH_VLSEG5E16V, MASK_VLSEG5E16V, match_vd_neq_vm, INSN_DREF },
+-{"vsseg5e16.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s)Vm", MATCH_VSSEG5E16V, MASK_VSSEG5E16V, match_opcode, INSN_DREF },
++{"vsseg5e16.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s)Vm", MATCH_VSSEG5E16V, MASK_VSSEG5E16V, match_vd_neq_vm, INSN_DREF },
+ {"vlseg6e16.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s)Vm", MATCH_VLSEG6E16V, MASK_VLSEG6E16V, match_vd_neq_vm, INSN_DREF },
+-{"vsseg6e16.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s)Vm", MATCH_VSSEG6E16V, MASK_VSSEG6E16V, match_opcode, INSN_DREF },
++{"vsseg6e16.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s)Vm", MATCH_VSSEG6E16V, MASK_VSSEG6E16V, match_vd_neq_vm, INSN_DREF },
+ {"vlseg7e16.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s)Vm", MATCH_VLSEG7E16V, MASK_VLSEG7E16V, match_vd_neq_vm, INSN_DREF },
+-{"vsseg7e16.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s)Vm", MATCH_VSSEG7E16V, MASK_VSSEG7E16V, match_opcode, INSN_DREF },
++{"vsseg7e16.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s)Vm", MATCH_VSSEG7E16V, MASK_VSSEG7E16V, match_vd_neq_vm, INSN_DREF },
+ {"vlseg8e16.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s)Vm", MATCH_VLSEG8E16V, MASK_VLSEG8E16V, match_vd_neq_vm, INSN_DREF },
+-{"vsseg8e16.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s)Vm", MATCH_VSSEG8E16V, MASK_VSSEG8E16V, match_opcode, INSN_DREF },
++{"vsseg8e16.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s)Vm", MATCH_VSSEG8E16V, MASK_VSSEG8E16V, match_vd_neq_vm, INSN_DREF },
+ 
+ {"vlseg2e32.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s)Vm", MATCH_VLSEG2E32V, MASK_VLSEG2E32V, match_vd_neq_vm, INSN_DREF },
+-{"vsseg2e32.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s)Vm", MATCH_VSSEG2E32V, MASK_VSSEG2E32V, match_opcode, INSN_DREF },
++{"vsseg2e32.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s)Vm", MATCH_VSSEG2E32V, MASK_VSSEG2E32V, match_vd_neq_vm, INSN_DREF },
+ {"vlseg3e32.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s)Vm", MATCH_VLSEG3E32V, MASK_VLSEG3E32V, match_vd_neq_vm, INSN_DREF },
+-{"vsseg3e32.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s)Vm", MATCH_VSSEG3E32V, MASK_VSSEG3E32V, match_opcode, INSN_DREF },
++{"vsseg3e32.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s)Vm", MATCH_VSSEG3E32V, MASK_VSSEG3E32V, match_vd_neq_vm, INSN_DREF },
+ {"vlseg4e32.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s)Vm", MATCH_VLSEG4E32V, MASK_VLSEG4E32V, match_vd_neq_vm, INSN_DREF },
+-{"vsseg4e32.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s)Vm", MATCH_VSSEG4E32V, MASK_VSSEG4E32V, match_opcode, INSN_DREF },
++{"vsseg4e32.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s)Vm", MATCH_VSSEG4E32V, MASK_VSSEG4E32V, match_vd_neq_vm, INSN_DREF },
+ {"vlseg5e32.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s)Vm", MATCH_VLSEG5E32V, MASK_VLSEG5E32V, match_vd_neq_vm, INSN_DREF },
+-{"vsseg5e32.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s)Vm", MATCH_VSSEG5E32V, MASK_VSSEG5E32V, match_opcode, INSN_DREF },
++{"vsseg5e32.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s)Vm", MATCH_VSSEG5E32V, MASK_VSSEG5E32V, match_vd_neq_vm, INSN_DREF },
+ {"vlseg6e32.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s)Vm", MATCH_VLSEG6E32V, MASK_VLSEG6E32V, match_vd_neq_vm, INSN_DREF },
+-{"vsseg6e32.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s)Vm", MATCH_VSSEG6E32V, MASK_VSSEG6E32V, match_opcode, INSN_DREF },
++{"vsseg6e32.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s)Vm", MATCH_VSSEG6E32V, MASK_VSSEG6E32V, match_vd_neq_vm, INSN_DREF },
+ {"vlseg7e32.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s)Vm", MATCH_VLSEG7E32V, MASK_VLSEG7E32V, match_vd_neq_vm, INSN_DREF },
+-{"vsseg7e32.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s)Vm", MATCH_VSSEG7E32V, MASK_VSSEG7E32V, match_opcode, INSN_DREF },
++{"vsseg7e32.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s)Vm", MATCH_VSSEG7E32V, MASK_VSSEG7E32V, match_vd_neq_vm, INSN_DREF },
+ {"vlseg8e32.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s)Vm", MATCH_VLSEG8E32V, MASK_VLSEG8E32V, match_vd_neq_vm, INSN_DREF },
+-{"vsseg8e32.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s)Vm", MATCH_VSSEG8E32V, MASK_VSSEG8E32V, match_opcode, INSN_DREF },
++{"vsseg8e32.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s)Vm", MATCH_VSSEG8E32V, MASK_VSSEG8E32V, match_vd_neq_vm, INSN_DREF },
+ 
+ {"vlseg2e64.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s)Vm", MATCH_VLSEG2E64V, MASK_VLSEG2E64V, match_vd_neq_vm, INSN_DREF },
+-{"vsseg2e64.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s)Vm", MATCH_VSSEG2E64V, MASK_VSSEG2E64V, match_opcode, INSN_DREF },
++{"vsseg2e64.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s)Vm", MATCH_VSSEG2E64V, MASK_VSSEG2E64V, match_vd_neq_vm, INSN_DREF },
+ {"vlseg3e64.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s)Vm", MATCH_VLSEG3E64V, MASK_VLSEG3E64V, match_vd_neq_vm, INSN_DREF },
+-{"vsseg3e64.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s)Vm", MATCH_VSSEG3E64V, MASK_VSSEG3E64V, match_opcode, INSN_DREF },
++{"vsseg3e64.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s)Vm", MATCH_VSSEG3E64V, MASK_VSSEG3E64V, match_vd_neq_vm, INSN_DREF },
+ {"vlseg4e64.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s)Vm", MATCH_VLSEG4E64V, MASK_VLSEG4E64V, match_vd_neq_vm, INSN_DREF },
+-{"vsseg4e64.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s)Vm", MATCH_VSSEG4E64V, MASK_VSSEG4E64V, match_opcode, INSN_DREF },
++{"vsseg4e64.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s)Vm", MATCH_VSSEG4E64V, MASK_VSSEG4E64V, match_vd_neq_vm, INSN_DREF },
+ {"vlseg5e64.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s)Vm", MATCH_VLSEG5E64V, MASK_VLSEG5E64V, match_vd_neq_vm, INSN_DREF },
+-{"vsseg5e64.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s)Vm", MATCH_VSSEG5E64V, MASK_VSSEG5E64V, match_opcode, INSN_DREF },
++{"vsseg5e64.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s)Vm", MATCH_VSSEG5E64V, MASK_VSSEG5E64V, match_vd_neq_vm, INSN_DREF },
+ {"vlseg6e64.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s)Vm", MATCH_VLSEG6E64V, MASK_VLSEG6E64V, match_vd_neq_vm, INSN_DREF },
+-{"vsseg6e64.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s)Vm", MATCH_VSSEG6E64V, MASK_VSSEG6E64V, match_opcode, INSN_DREF },
++{"vsseg6e64.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s)Vm", MATCH_VSSEG6E64V, MASK_VSSEG6E64V, match_vd_neq_vm, INSN_DREF },
+ {"vlseg7e64.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s)Vm", MATCH_VLSEG7E64V, MASK_VLSEG7E64V, match_vd_neq_vm, INSN_DREF },
+-{"vsseg7e64.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s)Vm", MATCH_VSSEG7E64V, MASK_VSSEG7E64V, match_opcode, INSN_DREF },
++{"vsseg7e64.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s)Vm", MATCH_VSSEG7E64V, MASK_VSSEG7E64V, match_vd_neq_vm, INSN_DREF },
+ {"vlseg8e64.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s)Vm", MATCH_VLSEG8E64V, MASK_VLSEG8E64V, match_vd_neq_vm, INSN_DREF },
+-{"vsseg8e64.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s)Vm", MATCH_VSSEG8E64V, MASK_VSSEG8E64V, match_opcode, INSN_DREF },
++{"vsseg8e64.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s)Vm", MATCH_VSSEG8E64V, MASK_VSSEG8E64V, match_vd_neq_vm, INSN_DREF },
+ 
+ {"vlseg2e128.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s)Vm", MATCH_VLSEG2E128V, MASK_VLSEG2E128V, match_vd_neq_vm, INSN_DREF },
+-{"vsseg2e128.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s)Vm", MATCH_VSSEG2E128V, MASK_VSSEG2E128V, match_opcode, INSN_DREF },
++{"vsseg2e128.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s)Vm", MATCH_VSSEG2E128V, MASK_VSSEG2E128V, match_vd_neq_vm, INSN_DREF },
+ {"vlseg3e128.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s)Vm", MATCH_VLSEG3E128V, MASK_VLSEG3E128V, match_vd_neq_vm, INSN_DREF },
+-{"vsseg3e128.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s)Vm", MATCH_VSSEG3E128V, MASK_VSSEG3E128V, match_opcode, INSN_DREF },
++{"vsseg3e128.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s)Vm", MATCH_VSSEG3E128V, MASK_VSSEG3E128V, match_vd_neq_vm, INSN_DREF },
+ {"vlseg4e128.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s)Vm", MATCH_VLSEG4E128V, MASK_VLSEG4E128V, match_vd_neq_vm, INSN_DREF },
+-{"vsseg4e128.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s)Vm", MATCH_VSSEG4E128V, MASK_VSSEG4E128V, match_opcode, INSN_DREF },
++{"vsseg4e128.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s)Vm", MATCH_VSSEG4E128V, MASK_VSSEG4E128V, match_vd_neq_vm, INSN_DREF },
+ {"vlseg5e128.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s)Vm", MATCH_VLSEG5E128V, MASK_VLSEG5E128V, match_vd_neq_vm, INSN_DREF },
+-{"vsseg5e128.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s)Vm", MATCH_VSSEG5E128V, MASK_VSSEG5E128V, match_opcode, INSN_DREF },
++{"vsseg5e128.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s)Vm", MATCH_VSSEG5E128V, MASK_VSSEG5E128V, match_vd_neq_vm, INSN_DREF },
+ {"vlseg6e128.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s)Vm", MATCH_VLSEG6E128V, MASK_VLSEG6E128V, match_vd_neq_vm, INSN_DREF },
+-{"vsseg6e128.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s)Vm", MATCH_VSSEG6E128V, MASK_VSSEG6E128V, match_opcode, INSN_DREF },
++{"vsseg6e128.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s)Vm", MATCH_VSSEG6E128V, MASK_VSSEG6E128V, match_vd_neq_vm, INSN_DREF },
+ {"vlseg7e128.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s)Vm", MATCH_VLSEG7E128V, MASK_VLSEG7E128V, match_vd_neq_vm, INSN_DREF },
+-{"vsseg7e128.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s)Vm", MATCH_VSSEG7E128V, MASK_VSSEG7E128V, match_opcode, INSN_DREF },
++{"vsseg7e128.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s)Vm", MATCH_VSSEG7E128V, MASK_VSSEG7E128V, match_vd_neq_vm, INSN_DREF },
+ {"vlseg8e128.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s)Vm", MATCH_VLSEG8E128V, MASK_VLSEG8E128V, match_vd_neq_vm, INSN_DREF },
+-{"vsseg8e128.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s)Vm", MATCH_VSSEG8E128V, MASK_VSSEG8E128V, match_opcode, INSN_DREF },
++{"vsseg8e128.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s)Vm", MATCH_VSSEG8E128V, MASK_VSSEG8E128V, match_vd_neq_vm, INSN_DREF },
+ 
+ {"vlseg2e256.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s)Vm", MATCH_VLSEG2E256V, MASK_VLSEG2E256V, match_vd_neq_vm, INSN_DREF },
+-{"vsseg2e256.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s)Vm", MATCH_VSSEG2E256V, MASK_VSSEG2E256V, match_opcode, INSN_DREF },
++{"vsseg2e256.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s)Vm", MATCH_VSSEG2E256V, MASK_VSSEG2E256V, match_vd_neq_vm, INSN_DREF },
+ {"vlseg3e256.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s)Vm", MATCH_VLSEG3E256V, MASK_VLSEG3E256V, match_vd_neq_vm, INSN_DREF },
+-{"vsseg3e256.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s)Vm", MATCH_VSSEG3E256V, MASK_VSSEG3E256V, match_opcode, INSN_DREF },
++{"vsseg3e256.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s)Vm", MATCH_VSSEG3E256V, MASK_VSSEG3E256V, match_vd_neq_vm, INSN_DREF },
+ {"vlseg4e256.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s)Vm", MATCH_VLSEG4E256V, MASK_VLSEG4E256V, match_vd_neq_vm, INSN_DREF },
+-{"vsseg4e256.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s)Vm", MATCH_VSSEG4E256V, MASK_VSSEG4E256V, match_opcode, INSN_DREF },
++{"vsseg4e256.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s)Vm", MATCH_VSSEG4E256V, MASK_VSSEG4E256V, match_vd_neq_vm, INSN_DREF },
+ {"vlseg5e256.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s)Vm", MATCH_VLSEG5E256V, MASK_VLSEG5E256V, match_vd_neq_vm, INSN_DREF },
+-{"vsseg5e256.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s)Vm", MATCH_VSSEG5E256V, MASK_VSSEG5E256V, match_opcode, INSN_DREF },
++{"vsseg5e256.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s)Vm", MATCH_VSSEG5E256V, MASK_VSSEG5E256V, match_vd_neq_vm, INSN_DREF },
+ {"vlseg6e256.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s)Vm", MATCH_VLSEG6E256V, MASK_VLSEG6E256V, match_vd_neq_vm, INSN_DREF },
+-{"vsseg6e256.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s)Vm", MATCH_VSSEG6E256V, MASK_VSSEG6E256V, match_opcode, INSN_DREF },
++{"vsseg6e256.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s)Vm", MATCH_VSSEG6E256V, MASK_VSSEG6E256V, match_vd_neq_vm, INSN_DREF },
+ {"vlseg7e256.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s)Vm", MATCH_VLSEG7E256V, MASK_VLSEG7E256V, match_vd_neq_vm, INSN_DREF },
+-{"vsseg7e256.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s)Vm", MATCH_VSSEG7E256V, MASK_VSSEG7E256V, match_opcode, INSN_DREF },
++{"vsseg7e256.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s)Vm", MATCH_VSSEG7E256V, MASK_VSSEG7E256V, match_vd_neq_vm, INSN_DREF },
+ {"vlseg8e256.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s)Vm", MATCH_VLSEG8E256V, MASK_VLSEG8E256V, match_vd_neq_vm, INSN_DREF },
+-{"vsseg8e256.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s)Vm", MATCH_VSSEG8E256V, MASK_VSSEG8E256V, match_opcode, INSN_DREF },
++{"vsseg8e256.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s)Vm", MATCH_VSSEG8E256V, MASK_VSSEG8E256V, match_vd_neq_vm, INSN_DREF },
+ 
+ {"vlseg2e512.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s)Vm", MATCH_VLSEG2E512V, MASK_VLSEG2E512V, match_vd_neq_vm, INSN_DREF },
+-{"vsseg2e512.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s)Vm", MATCH_VSSEG2E512V, MASK_VSSEG2E512V, match_opcode, INSN_DREF },
++{"vsseg2e512.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s)Vm", MATCH_VSSEG2E512V, MASK_VSSEG2E512V, match_vd_neq_vm, INSN_DREF },
+ {"vlseg3e512.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s)Vm", MATCH_VLSEG3E512V, MASK_VLSEG3E512V, match_vd_neq_vm, INSN_DREF },
+-{"vsseg3e512.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s)Vm", MATCH_VSSEG3E512V, MASK_VSSEG3E512V, match_opcode, INSN_DREF },
++{"vsseg3e512.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s)Vm", MATCH_VSSEG3E512V, MASK_VSSEG3E512V, match_vd_neq_vm, INSN_DREF },
+ {"vlseg4e512.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s)Vm", MATCH_VLSEG4E512V, MASK_VLSEG4E512V, match_vd_neq_vm, INSN_DREF },
+-{"vsseg4e512.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s)Vm", MATCH_VSSEG4E512V, MASK_VSSEG4E512V, match_opcode, INSN_DREF },
++{"vsseg4e512.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s)Vm", MATCH_VSSEG4E512V, MASK_VSSEG4E512V, match_vd_neq_vm, INSN_DREF },
+ {"vlseg5e512.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s)Vm", MATCH_VLSEG5E512V, MASK_VLSEG5E512V, match_vd_neq_vm, INSN_DREF },
+-{"vsseg5e512.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s)Vm", MATCH_VSSEG5E512V, MASK_VSSEG5E512V, match_opcode, INSN_DREF },
++{"vsseg5e512.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s)Vm", MATCH_VSSEG5E512V, MASK_VSSEG5E512V, match_vd_neq_vm, INSN_DREF },
+ {"vlseg6e512.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s)Vm", MATCH_VLSEG6E512V, MASK_VLSEG6E512V, match_vd_neq_vm, INSN_DREF },
+-{"vsseg6e512.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s)Vm", MATCH_VSSEG6E512V, MASK_VSSEG6E512V, match_opcode, INSN_DREF },
++{"vsseg6e512.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s)Vm", MATCH_VSSEG6E512V, MASK_VSSEG6E512V, match_vd_neq_vm, INSN_DREF },
+ {"vlseg7e512.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s)Vm", MATCH_VLSEG7E512V, MASK_VLSEG7E512V, match_vd_neq_vm, INSN_DREF },
+-{"vsseg7e512.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s)Vm", MATCH_VSSEG7E512V, MASK_VSSEG7E512V, match_opcode, INSN_DREF },
++{"vsseg7e512.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s)Vm", MATCH_VSSEG7E512V, MASK_VSSEG7E512V, match_vd_neq_vm, INSN_DREF },
+ {"vlseg8e512.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s)Vm", MATCH_VLSEG8E512V, MASK_VLSEG8E512V, match_vd_neq_vm, INSN_DREF },
+-{"vsseg8e512.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s)Vm", MATCH_VSSEG8E512V, MASK_VSSEG8E512V, match_opcode, INSN_DREF },
++{"vsseg8e512.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s)Vm", MATCH_VSSEG8E512V, MASK_VSSEG8E512V, match_vd_neq_vm, INSN_DREF },
+ 
+ {"vlseg2e1024.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s)Vm", MATCH_VLSEG2E1024V, MASK_VLSEG2E1024V, match_vd_neq_vm, INSN_DREF },
+-{"vsseg2e1024.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s)Vm", MATCH_VSSEG2E1024V, MASK_VSSEG2E1024V, match_opcode, INSN_DREF },
++{"vsseg2e1024.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s)Vm", MATCH_VSSEG2E1024V, MASK_VSSEG2E1024V, match_vd_neq_vm, INSN_DREF },
+ {"vlseg3e1024.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s)Vm", MATCH_VLSEG3E1024V, MASK_VLSEG3E1024V, match_vd_neq_vm, INSN_DREF },
+-{"vsseg3e1024.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s)Vm", MATCH_VSSEG3E1024V, MASK_VSSEG3E1024V, match_opcode, INSN_DREF },
++{"vsseg3e1024.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s)Vm", MATCH_VSSEG3E1024V, MASK_VSSEG3E1024V, match_vd_neq_vm, INSN_DREF },
+ {"vlseg4e1024.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s)Vm", MATCH_VLSEG4E1024V, MASK_VLSEG4E1024V, match_vd_neq_vm, INSN_DREF },
+-{"vsseg4e1024.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s)Vm", MATCH_VSSEG4E1024V, MASK_VSSEG4E1024V, match_opcode, INSN_DREF },
++{"vsseg4e1024.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s)Vm", MATCH_VSSEG4E1024V, MASK_VSSEG4E1024V, match_vd_neq_vm, INSN_DREF },
+ {"vlseg5e1024.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s)Vm", MATCH_VLSEG5E1024V, MASK_VLSEG5E1024V, match_vd_neq_vm, INSN_DREF },
+-{"vsseg5e1024.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s)Vm", MATCH_VSSEG5E1024V, MASK_VSSEG5E1024V, match_opcode, INSN_DREF },
++{"vsseg5e1024.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s)Vm", MATCH_VSSEG5E1024V, MASK_VSSEG5E1024V, match_vd_neq_vm, INSN_DREF },
+ {"vlseg6e1024.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s)Vm", MATCH_VLSEG6E1024V, MASK_VLSEG6E1024V, match_vd_neq_vm, INSN_DREF },
+-{"vsseg6e1024.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s)Vm", MATCH_VSSEG6E1024V, MASK_VSSEG6E1024V, match_opcode, INSN_DREF },
++{"vsseg6e1024.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s)Vm", MATCH_VSSEG6E1024V, MASK_VSSEG6E1024V, match_vd_neq_vm, INSN_DREF },
+ {"vlseg7e1024.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s)Vm", MATCH_VLSEG7E1024V, MASK_VLSEG7E1024V, match_vd_neq_vm, INSN_DREF },
+-{"vsseg7e1024.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s)Vm", MATCH_VSSEG7E1024V, MASK_VSSEG7E1024V, match_opcode, INSN_DREF },
++{"vsseg7e1024.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s)Vm", MATCH_VSSEG7E1024V, MASK_VSSEG7E1024V, match_vd_neq_vm, INSN_DREF },
+ {"vlseg8e1024.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s)Vm", MATCH_VLSEG8E1024V, MASK_VLSEG8E1024V, match_vd_neq_vm, INSN_DREF },
+-{"vsseg8e1024.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s)Vm", MATCH_VSSEG8E1024V, MASK_VSSEG8E1024V, match_opcode, INSN_DREF },
++{"vsseg8e1024.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s)Vm", MATCH_VSSEG8E1024V, MASK_VSSEG8E1024V, match_vd_neq_vm, INSN_DREF },
+ 
+ {"vlsseg2e8.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),tVm", MATCH_VLSSEG2E8V, MASK_VLSSEG2E8V, match_vd_neq_vm, INSN_DREF },
+-{"vssseg2e8.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),tVm", MATCH_VSSSEG2E8V, MASK_VSSSEG2E8V, match_opcode, INSN_DREF },
++{"vssseg2e8.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),tVm", MATCH_VSSSEG2E8V, MASK_VSSSEG2E8V, match_vd_neq_vm, INSN_DREF },
+ {"vlsseg3e8.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),tVm", MATCH_VLSSEG3E8V, MASK_VLSSEG3E8V, match_vd_neq_vm, INSN_DREF },
+-{"vssseg3e8.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),tVm", MATCH_VSSSEG3E8V, MASK_VSSSEG3E8V, match_opcode, INSN_DREF },
++{"vssseg3e8.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),tVm", MATCH_VSSSEG3E8V, MASK_VSSSEG3E8V, match_vd_neq_vm, INSN_DREF },
+ {"vlsseg4e8.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),tVm", MATCH_VLSSEG4E8V, MASK_VLSSEG4E8V, match_vd_neq_vm, INSN_DREF },
+-{"vssseg4e8.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),tVm", MATCH_VSSSEG4E8V, MASK_VSSSEG4E8V, match_opcode, INSN_DREF },
++{"vssseg4e8.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),tVm", MATCH_VSSSEG4E8V, MASK_VSSSEG4E8V, match_vd_neq_vm, INSN_DREF },
+ {"vlsseg5e8.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),tVm", MATCH_VLSSEG5E8V, MASK_VLSSEG5E8V, match_vd_neq_vm, INSN_DREF },
+-{"vssseg5e8.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),tVm", MATCH_VSSSEG5E8V, MASK_VSSSEG5E8V, match_opcode, INSN_DREF },
++{"vssseg5e8.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),tVm", MATCH_VSSSEG5E8V, MASK_VSSSEG5E8V, match_vd_neq_vm, INSN_DREF },
+ {"vlsseg6e8.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),tVm", MATCH_VLSSEG6E8V, MASK_VLSSEG6E8V, match_vd_neq_vm, INSN_DREF },
+-{"vssseg6e8.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),tVm", MATCH_VSSSEG6E8V, MASK_VSSSEG6E8V, match_opcode, INSN_DREF },
++{"vssseg6e8.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),tVm", MATCH_VSSSEG6E8V, MASK_VSSSEG6E8V, match_vd_neq_vm, INSN_DREF },
+ {"vlsseg7e8.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),tVm", MATCH_VLSSEG7E8V, MASK_VLSSEG7E8V, match_vd_neq_vm, INSN_DREF },
+-{"vssseg7e8.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),tVm", MATCH_VSSSEG7E8V, MASK_VSSSEG7E8V, match_opcode, INSN_DREF },
++{"vssseg7e8.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),tVm", MATCH_VSSSEG7E8V, MASK_VSSSEG7E8V, match_vd_neq_vm, INSN_DREF },
+ {"vlsseg8e8.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),tVm", MATCH_VLSSEG8E8V, MASK_VLSSEG8E8V, match_vd_neq_vm, INSN_DREF },
+-{"vssseg8e8.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),tVm", MATCH_VSSSEG8E8V, MASK_VSSSEG8E8V, match_opcode, INSN_DREF },
++{"vssseg8e8.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),tVm", MATCH_VSSSEG8E8V, MASK_VSSSEG8E8V, match_vd_neq_vm, INSN_DREF },
+ 
+ {"vlsseg2e16.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),tVm", MATCH_VLSSEG2E16V, MASK_VLSSEG2E16V, match_vd_neq_vm, INSN_DREF },
+-{"vssseg2e16.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),tVm", MATCH_VSSSEG2E16V, MASK_VSSSEG2E16V, match_opcode, INSN_DREF },
++{"vssseg2e16.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),tVm", MATCH_VSSSEG2E16V, MASK_VSSSEG2E16V, match_vd_neq_vm, INSN_DREF },
+ {"vlsseg3e16.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),tVm", MATCH_VLSSEG3E16V, MASK_VLSSEG3E16V, match_vd_neq_vm, INSN_DREF },
+-{"vssseg3e16.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),tVm", MATCH_VSSSEG3E16V, MASK_VSSSEG3E16V, match_opcode, INSN_DREF },
++{"vssseg3e16.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),tVm", MATCH_VSSSEG3E16V, MASK_VSSSEG3E16V, match_vd_neq_vm, INSN_DREF },
+ {"vlsseg4e16.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),tVm", MATCH_VLSSEG4E16V, MASK_VLSSEG4E16V, match_vd_neq_vm, INSN_DREF },
+-{"vssseg4e16.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),tVm", MATCH_VSSSEG4E16V, MASK_VSSSEG4E16V, match_opcode, INSN_DREF },
++{"vssseg4e16.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),tVm", MATCH_VSSSEG4E16V, MASK_VSSSEG4E16V, match_vd_neq_vm, INSN_DREF },
+ {"vlsseg5e16.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),tVm", MATCH_VLSSEG5E16V, MASK_VLSSEG5E16V, match_vd_neq_vm, INSN_DREF },
+-{"vssseg5e16.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),tVm", MATCH_VSSSEG5E16V, MASK_VSSSEG5E16V, match_opcode, INSN_DREF },
++{"vssseg5e16.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),tVm", MATCH_VSSSEG5E16V, MASK_VSSSEG5E16V, match_vd_neq_vm, INSN_DREF },
+ {"vlsseg6e16.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),tVm", MATCH_VLSSEG6E16V, MASK_VLSSEG6E16V, match_vd_neq_vm, INSN_DREF },
+-{"vssseg6e16.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),tVm", MATCH_VSSSEG6E16V, MASK_VSSSEG6E16V, match_opcode, INSN_DREF },
++{"vssseg6e16.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),tVm", MATCH_VSSSEG6E16V, MASK_VSSSEG6E16V, match_vd_neq_vm, INSN_DREF },
+ {"vlsseg7e16.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),tVm", MATCH_VLSSEG7E16V, MASK_VLSSEG7E16V, match_vd_neq_vm, INSN_DREF },
+-{"vssseg7e16.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),tVm", MATCH_VSSSEG7E16V, MASK_VSSSEG7E16V, match_opcode, INSN_DREF },
++{"vssseg7e16.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),tVm", MATCH_VSSSEG7E16V, MASK_VSSSEG7E16V, match_vd_neq_vm, INSN_DREF },
+ {"vlsseg8e16.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),tVm", MATCH_VLSSEG8E16V, MASK_VLSSEG8E16V, match_vd_neq_vm, INSN_DREF },
+-{"vssseg8e16.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),tVm", MATCH_VSSSEG8E16V, MASK_VSSSEG8E16V, match_opcode, INSN_DREF },
++{"vssseg8e16.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),tVm", MATCH_VSSSEG8E16V, MASK_VSSSEG8E16V, match_vd_neq_vm, INSN_DREF },
+ 
+ {"vlsseg2e32.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),tVm", MATCH_VLSSEG2E32V, MASK_VLSSEG2E32V, match_vd_neq_vm, INSN_DREF },
+-{"vssseg2e32.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),tVm", MATCH_VSSSEG2E32V, MASK_VSSSEG2E32V, match_opcode, INSN_DREF },
++{"vssseg2e32.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),tVm", MATCH_VSSSEG2E32V, MASK_VSSSEG2E32V, match_vd_neq_vm, INSN_DREF },
+ {"vlsseg3e32.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),tVm", MATCH_VLSSEG3E32V, MASK_VLSSEG3E32V, match_vd_neq_vm, INSN_DREF },
+-{"vssseg3e32.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),tVm", MATCH_VSSSEG3E32V, MASK_VSSSEG3E32V, match_opcode, INSN_DREF },
++{"vssseg3e32.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),tVm", MATCH_VSSSEG3E32V, MASK_VSSSEG3E32V, match_vd_neq_vm, INSN_DREF },
+ {"vlsseg4e32.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),tVm", MATCH_VLSSEG4E32V, MASK_VLSSEG4E32V, match_vd_neq_vm, INSN_DREF },
+-{"vssseg4e32.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),tVm", MATCH_VSSSEG4E32V, MASK_VSSSEG4E32V, match_opcode, INSN_DREF },
++{"vssseg4e32.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),tVm", MATCH_VSSSEG4E32V, MASK_VSSSEG4E32V, match_vd_neq_vm, INSN_DREF },
+ {"vlsseg5e32.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),tVm", MATCH_VLSSEG5E32V, MASK_VLSSEG5E32V, match_vd_neq_vm, INSN_DREF },
+-{"vssseg5e32.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),tVm", MATCH_VSSSEG5E32V, MASK_VSSSEG5E32V, match_opcode, INSN_DREF },
++{"vssseg5e32.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),tVm", MATCH_VSSSEG5E32V, MASK_VSSSEG5E32V, match_vd_neq_vm, INSN_DREF },
+ {"vlsseg6e32.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),tVm", MATCH_VLSSEG6E32V, MASK_VLSSEG6E32V, match_vd_neq_vm, INSN_DREF },
+-{"vssseg6e32.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),tVm", MATCH_VSSSEG6E32V, MASK_VSSSEG6E32V, match_opcode, INSN_DREF },
++{"vssseg6e32.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),tVm", MATCH_VSSSEG6E32V, MASK_VSSSEG6E32V, match_vd_neq_vm, INSN_DREF },
+ {"vlsseg7e32.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),tVm", MATCH_VLSSEG7E32V, MASK_VLSSEG7E32V, match_vd_neq_vm, INSN_DREF },
+-{"vssseg7e32.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),tVm", MATCH_VSSSEG7E32V, MASK_VSSSEG7E32V, match_opcode, INSN_DREF },
++{"vssseg7e32.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),tVm", MATCH_VSSSEG7E32V, MASK_VSSSEG7E32V, match_vd_neq_vm, INSN_DREF },
+ {"vlsseg8e32.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),tVm", MATCH_VLSSEG8E32V, MASK_VLSSEG8E32V, match_vd_neq_vm, INSN_DREF },
+-{"vssseg8e32.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),tVm", MATCH_VSSSEG8E32V, MASK_VSSSEG8E32V, match_opcode, INSN_DREF },
++{"vssseg8e32.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),tVm", MATCH_VSSSEG8E32V, MASK_VSSSEG8E32V, match_vd_neq_vm, INSN_DREF },
+ 
+ {"vlsseg2e64.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),tVm", MATCH_VLSSEG2E64V, MASK_VLSSEG2E64V, match_vd_neq_vm, INSN_DREF },
+-{"vssseg2e64.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),tVm", MATCH_VSSSEG2E64V, MASK_VSSSEG2E64V, match_opcode, INSN_DREF },
++{"vssseg2e64.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),tVm", MATCH_VSSSEG2E64V, MASK_VSSSEG2E64V, match_vd_neq_vm, INSN_DREF },
+ {"vlsseg3e64.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),tVm", MATCH_VLSSEG3E64V, MASK_VLSSEG3E64V, match_vd_neq_vm, INSN_DREF },
+-{"vssseg3e64.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),tVm", MATCH_VSSSEG3E64V, MASK_VSSSEG3E64V, match_opcode, INSN_DREF },
++{"vssseg3e64.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),tVm", MATCH_VSSSEG3E64V, MASK_VSSSEG3E64V, match_vd_neq_vm, INSN_DREF },
+ {"vlsseg4e64.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),tVm", MATCH_VLSSEG4E64V, MASK_VLSSEG4E64V, match_vd_neq_vm, INSN_DREF },
+-{"vssseg4e64.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),tVm", MATCH_VSSSEG4E64V, MASK_VSSSEG4E64V, match_opcode, INSN_DREF },
++{"vssseg4e64.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),tVm", MATCH_VSSSEG4E64V, MASK_VSSSEG4E64V, match_vd_neq_vm, INSN_DREF },
+ {"vlsseg5e64.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),tVm", MATCH_VLSSEG5E64V, MASK_VLSSEG5E64V, match_vd_neq_vm, INSN_DREF },
+-{"vssseg5e64.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),tVm", MATCH_VSSSEG5E64V, MASK_VSSSEG5E64V, match_opcode, INSN_DREF },
++{"vssseg5e64.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),tVm", MATCH_VSSSEG5E64V, MASK_VSSSEG5E64V, match_vd_neq_vm, INSN_DREF },
+ {"vlsseg6e64.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),tVm", MATCH_VLSSEG6E64V, MASK_VLSSEG6E64V, match_vd_neq_vm, INSN_DREF },
+-{"vssseg6e64.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),tVm", MATCH_VSSSEG6E64V, MASK_VSSSEG6E64V, match_opcode, INSN_DREF },
++{"vssseg6e64.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),tVm", MATCH_VSSSEG6E64V, MASK_VSSSEG6E64V, match_vd_neq_vm, INSN_DREF },
+ {"vlsseg7e64.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),tVm", MATCH_VLSSEG7E64V, MASK_VLSSEG7E64V, match_vd_neq_vm, INSN_DREF },
+-{"vssseg7e64.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),tVm", MATCH_VSSSEG7E64V, MASK_VSSSEG7E64V, match_opcode, INSN_DREF },
++{"vssseg7e64.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),tVm", MATCH_VSSSEG7E64V, MASK_VSSSEG7E64V, match_vd_neq_vm, INSN_DREF },
+ {"vlsseg8e64.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),tVm", MATCH_VLSSEG8E64V, MASK_VLSSEG8E64V, match_vd_neq_vm, INSN_DREF },
+-{"vssseg8e64.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),tVm", MATCH_VSSSEG8E64V, MASK_VSSSEG8E64V, match_opcode, INSN_DREF },
++{"vssseg8e64.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),tVm", MATCH_VSSSEG8E64V, MASK_VSSSEG8E64V, match_vd_neq_vm, INSN_DREF },
+ 
+ {"vlsseg2e128.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),tVm", MATCH_VLSSEG2E128V, MASK_VLSSEG2E128V, match_vd_neq_vm, INSN_DREF },
+-{"vssseg2e128.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),tVm", MATCH_VSSSEG2E128V, MASK_VSSSEG2E128V, match_opcode, INSN_DREF },
++{"vssseg2e128.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),tVm", MATCH_VSSSEG2E128V, MASK_VSSSEG2E128V, match_vd_neq_vm, INSN_DREF },
+ {"vlsseg3e128.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),tVm", MATCH_VLSSEG3E128V, MASK_VLSSEG3E128V, match_vd_neq_vm, INSN_DREF },
+-{"vssseg3e128.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),tVm", MATCH_VSSSEG3E128V, MASK_VSSSEG3E128V, match_opcode, INSN_DREF },
++{"vssseg3e128.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),tVm", MATCH_VSSSEG3E128V, MASK_VSSSEG3E128V, match_vd_neq_vm, INSN_DREF },
+ {"vlsseg4e128.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),tVm", MATCH_VLSSEG4E128V, MASK_VLSSEG4E128V, match_vd_neq_vm, INSN_DREF },
+-{"vssseg4e128.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),tVm", MATCH_VSSSEG4E128V, MASK_VSSSEG4E128V, match_opcode, INSN_DREF },
++{"vssseg4e128.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),tVm", MATCH_VSSSEG4E128V, MASK_VSSSEG4E128V, match_vd_neq_vm, INSN_DREF },
+ {"vlsseg5e128.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),tVm", MATCH_VLSSEG5E128V, MASK_VLSSEG5E128V, match_vd_neq_vm, INSN_DREF },
+-{"vssseg5e128.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),tVm", MATCH_VSSSEG5E128V, MASK_VSSSEG5E128V, match_opcode, INSN_DREF },
++{"vssseg5e128.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),tVm", MATCH_VSSSEG5E128V, MASK_VSSSEG5E128V, match_vd_neq_vm, INSN_DREF },
+ {"vlsseg6e128.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),tVm", MATCH_VLSSEG6E128V, MASK_VLSSEG6E128V, match_vd_neq_vm, INSN_DREF },
+-{"vssseg6e128.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),tVm", MATCH_VSSSEG6E128V, MASK_VSSSEG6E128V, match_opcode, INSN_DREF },
++{"vssseg6e128.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),tVm", MATCH_VSSSEG6E128V, MASK_VSSSEG6E128V, match_vd_neq_vm, INSN_DREF },
+ {"vlsseg7e128.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),tVm", MATCH_VLSSEG7E128V, MASK_VLSSEG7E128V, match_vd_neq_vm, INSN_DREF },
+-{"vssseg7e128.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),tVm", MATCH_VSSSEG7E128V, MASK_VSSSEG7E128V, match_opcode, INSN_DREF },
++{"vssseg7e128.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),tVm", MATCH_VSSSEG7E128V, MASK_VSSSEG7E128V, match_vd_neq_vm, INSN_DREF },
+ {"vlsseg8e128.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),tVm", MATCH_VLSSEG8E128V, MASK_VLSSEG8E128V, match_vd_neq_vm, INSN_DREF },
+-{"vssseg8e128.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),tVm", MATCH_VSSSEG8E128V, MASK_VSSSEG8E128V, match_opcode, INSN_DREF },
++{"vssseg8e128.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),tVm", MATCH_VSSSEG8E128V, MASK_VSSSEG8E128V, match_vd_neq_vm, INSN_DREF },
+ 
+ {"vlsseg2e256.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),tVm", MATCH_VLSSEG2E256V, MASK_VLSSEG2E256V, match_vd_neq_vm, INSN_DREF },
+-{"vssseg2e256.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),tVm", MATCH_VSSSEG2E256V, MASK_VSSSEG2E256V, match_opcode, INSN_DREF },
++{"vssseg2e256.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),tVm", MATCH_VSSSEG2E256V, MASK_VSSSEG2E256V, match_vd_neq_vm, INSN_DREF },
+ {"vlsseg3e256.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),tVm", MATCH_VLSSEG3E256V, MASK_VLSSEG3E256V, match_vd_neq_vm, INSN_DREF },
+-{"vssseg3e256.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),tVm", MATCH_VSSSEG3E256V, MASK_VSSSEG3E256V, match_opcode, INSN_DREF },
++{"vssseg3e256.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),tVm", MATCH_VSSSEG3E256V, MASK_VSSSEG3E256V, match_vd_neq_vm, INSN_DREF },
+ {"vlsseg4e256.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),tVm", MATCH_VLSSEG4E256V, MASK_VLSSEG4E256V, match_vd_neq_vm, INSN_DREF },
+-{"vssseg4e256.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),tVm", MATCH_VSSSEG4E256V, MASK_VSSSEG4E256V, match_opcode, INSN_DREF },
++{"vssseg4e256.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),tVm", MATCH_VSSSEG4E256V, MASK_VSSSEG4E256V, match_vd_neq_vm, INSN_DREF },
+ {"vlsseg5e256.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),tVm", MATCH_VLSSEG5E256V, MASK_VLSSEG5E256V, match_vd_neq_vm, INSN_DREF },
+-{"vssseg5e256.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),tVm", MATCH_VSSSEG5E256V, MASK_VSSSEG5E256V, match_opcode, INSN_DREF },
++{"vssseg5e256.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),tVm", MATCH_VSSSEG5E256V, MASK_VSSSEG5E256V, match_vd_neq_vm, INSN_DREF },
+ {"vlsseg6e256.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),tVm", MATCH_VLSSEG6E256V, MASK_VLSSEG6E256V, match_vd_neq_vm, INSN_DREF },
+-{"vssseg6e256.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),tVm", MATCH_VSSSEG6E256V, MASK_VSSSEG6E256V, match_opcode, INSN_DREF },
++{"vssseg6e256.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),tVm", MATCH_VSSSEG6E256V, MASK_VSSSEG6E256V, match_vd_neq_vm, INSN_DREF },
+ {"vlsseg7e256.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),tVm", MATCH_VLSSEG7E256V, MASK_VLSSEG7E256V, match_vd_neq_vm, INSN_DREF },
+-{"vssseg7e256.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),tVm", MATCH_VSSSEG7E256V, MASK_VSSSEG7E256V, match_opcode, INSN_DREF },
++{"vssseg7e256.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),tVm", MATCH_VSSSEG7E256V, MASK_VSSSEG7E256V, match_vd_neq_vm, INSN_DREF },
+ {"vlsseg8e256.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),tVm", MATCH_VLSSEG8E256V, MASK_VLSSEG8E256V, match_vd_neq_vm, INSN_DREF },
+-{"vssseg8e256.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),tVm", MATCH_VSSSEG8E256V, MASK_VSSSEG8E256V, match_opcode, INSN_DREF },
++{"vssseg8e256.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),tVm", MATCH_VSSSEG8E256V, MASK_VSSSEG8E256V, match_vd_neq_vm, INSN_DREF },
+ 
+ {"vlsseg2e512.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),tVm", MATCH_VLSSEG2E512V, MASK_VLSSEG2E512V, match_vd_neq_vm, INSN_DREF },
+-{"vssseg2e512.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),tVm", MATCH_VSSSEG2E512V, MASK_VSSSEG2E512V, match_opcode, INSN_DREF },
++{"vssseg2e512.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),tVm", MATCH_VSSSEG2E512V, MASK_VSSSEG2E512V, match_vd_neq_vm, INSN_DREF },
+ {"vlsseg3e512.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),tVm", MATCH_VLSSEG3E512V, MASK_VLSSEG3E512V, match_vd_neq_vm, INSN_DREF },
+-{"vssseg3e512.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),tVm", MATCH_VSSSEG3E512V, MASK_VSSSEG3E512V, match_opcode, INSN_DREF },
++{"vssseg3e512.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),tVm", MATCH_VSSSEG3E512V, MASK_VSSSEG3E512V, match_vd_neq_vm, INSN_DREF },
+ {"vlsseg4e512.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),tVm", MATCH_VLSSEG4E512V, MASK_VLSSEG4E512V, match_vd_neq_vm, INSN_DREF },
+-{"vssseg4e512.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),tVm", MATCH_VSSSEG4E512V, MASK_VSSSEG4E512V, match_opcode, INSN_DREF },
++{"vssseg4e512.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),tVm", MATCH_VSSSEG4E512V, MASK_VSSSEG4E512V, match_vd_neq_vm, INSN_DREF },
+ {"vlsseg5e512.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),tVm", MATCH_VLSSEG5E512V, MASK_VLSSEG5E512V, match_vd_neq_vm, INSN_DREF },
+-{"vssseg5e512.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),tVm", MATCH_VSSSEG5E512V, MASK_VSSSEG5E512V, match_opcode, INSN_DREF },
++{"vssseg5e512.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),tVm", MATCH_VSSSEG5E512V, MASK_VSSSEG5E512V, match_vd_neq_vm, INSN_DREF },
+ {"vlsseg6e512.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),tVm", MATCH_VLSSEG6E512V, MASK_VLSSEG6E512V, match_vd_neq_vm, INSN_DREF },
+-{"vssseg6e512.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),tVm", MATCH_VSSSEG6E512V, MASK_VSSSEG6E512V, match_opcode, INSN_DREF },
++{"vssseg6e512.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),tVm", MATCH_VSSSEG6E512V, MASK_VSSSEG6E512V, match_vd_neq_vm, INSN_DREF },
+ {"vlsseg7e512.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),tVm", MATCH_VLSSEG7E512V, MASK_VLSSEG7E512V, match_vd_neq_vm, INSN_DREF },
+-{"vssseg7e512.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),tVm", MATCH_VSSSEG7E512V, MASK_VSSSEG7E512V, match_opcode, INSN_DREF },
++{"vssseg7e512.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),tVm", MATCH_VSSSEG7E512V, MASK_VSSSEG7E512V, match_vd_neq_vm, INSN_DREF },
+ {"vlsseg8e512.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),tVm", MATCH_VLSSEG8E512V, MASK_VLSSEG8E512V, match_vd_neq_vm, INSN_DREF },
+-{"vssseg8e512.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),tVm", MATCH_VSSSEG8E512V, MASK_VSSSEG8E512V, match_opcode, INSN_DREF },
++{"vssseg8e512.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),tVm", MATCH_VSSSEG8E512V, MASK_VSSSEG8E512V, match_vd_neq_vm, INSN_DREF },
+ 
+ {"vlsseg2e1024.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),tVm", MATCH_VLSSEG2E1024V, MASK_VLSSEG2E1024V, match_vd_neq_vm, INSN_DREF },
+-{"vssseg2e1024.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),tVm", MATCH_VSSSEG2E1024V, MASK_VSSSEG2E1024V, match_opcode, INSN_DREF },
++{"vssseg2e1024.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),tVm", MATCH_VSSSEG2E1024V, MASK_VSSSEG2E1024V, match_vd_neq_vm, INSN_DREF },
+ {"vlsseg3e1024.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),tVm", MATCH_VLSSEG3E1024V, MASK_VLSSEG3E1024V, match_vd_neq_vm, INSN_DREF },
+-{"vssseg3e1024.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),tVm", MATCH_VSSSEG3E1024V, MASK_VSSSEG3E1024V, match_opcode, INSN_DREF },
++{"vssseg3e1024.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),tVm", MATCH_VSSSEG3E1024V, MASK_VSSSEG3E1024V, match_vd_neq_vm, INSN_DREF },
+ {"vlsseg4e1024.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),tVm", MATCH_VLSSEG4E1024V, MASK_VLSSEG4E1024V, match_vd_neq_vm, INSN_DREF },
+-{"vssseg4e1024.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),tVm", MATCH_VSSSEG4E1024V, MASK_VSSSEG4E1024V, match_opcode, INSN_DREF },
++{"vssseg4e1024.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),tVm", MATCH_VSSSEG4E1024V, MASK_VSSSEG4E1024V, match_vd_neq_vm, INSN_DREF },
+ {"vlsseg5e1024.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),tVm", MATCH_VLSSEG5E1024V, MASK_VLSSEG5E1024V, match_vd_neq_vm, INSN_DREF },
+-{"vssseg5e1024.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),tVm", MATCH_VSSSEG5E1024V, MASK_VSSSEG5E1024V, match_opcode, INSN_DREF },
++{"vssseg5e1024.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),tVm", MATCH_VSSSEG5E1024V, MASK_VSSSEG5E1024V, match_vd_neq_vm, INSN_DREF },
+ {"vlsseg6e1024.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),tVm", MATCH_VLSSEG6E1024V, MASK_VLSSEG6E1024V, match_vd_neq_vm, INSN_DREF },
+-{"vssseg6e1024.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),tVm", MATCH_VSSSEG6E1024V, MASK_VSSSEG6E1024V, match_opcode, INSN_DREF },
++{"vssseg6e1024.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),tVm", MATCH_VSSSEG6E1024V, MASK_VSSSEG6E1024V, match_vd_neq_vm, INSN_DREF },
+ {"vlsseg7e1024.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),tVm", MATCH_VLSSEG7E1024V, MASK_VLSSEG7E1024V, match_vd_neq_vm, INSN_DREF },
+-{"vssseg7e1024.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),tVm", MATCH_VSSSEG7E1024V, MASK_VSSSEG7E1024V, match_opcode, INSN_DREF },
++{"vssseg7e1024.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),tVm", MATCH_VSSSEG7E1024V, MASK_VSSSEG7E1024V, match_vd_neq_vm, INSN_DREF },
+ {"vlsseg8e1024.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),tVm", MATCH_VLSSEG8E1024V, MASK_VLSSEG8E1024V, match_vd_neq_vm, INSN_DREF },
+-{"vssseg8e1024.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),tVm", MATCH_VSSSEG8E1024V, MASK_VSSSEG8E1024V, match_opcode, INSN_DREF },
++{"vssseg8e1024.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),tVm", MATCH_VSSSEG8E1024V, MASK_VSSSEG8E1024V, match_vd_neq_vm, INSN_DREF },
+ 
+ {"vlxseg2ei8.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),VtVm", MATCH_VLXSEG2EI8V, MASK_VLXSEG2EI8V, match_vd_neq_vs2_neq_vm, INSN_DREF },
+ {"vsxseg2ei8.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),VtVm", MATCH_VSXSEG2EI8V, MASK_VSXSEG2EI8V, match_vd_neq_vs2_neq_vm, INSN_DREF },
+@@ -1595,53 +1588,53 @@ const struct riscv_opcode riscv_opcodes[] =
+ {"vs4r.v",  0, INSN_CLASS_V,  "Vd,0(s)", MATCH_VS4RV, MASK_VS4RV, match_opcode, INSN_DREF },
+ {"vs8r.v",  0, INSN_CLASS_V,  "Vd,0(s)", MATCH_VS8RV, MASK_VS8RV, match_opcode, INSN_DREF },
+ 
+-{"vamoaddei8.v",   0, INSN_CLASS_V_OR_ZVAMO,  "Ve,0(s),Vt,VfVm", MATCH_VAMOADDEI8V, MASK_VAMOADDEI8V, match_opcode, INSN_DREF},
+-{"vamoswapei8.v",  0, INSN_CLASS_V_OR_ZVAMO,  "Ve,0(s),Vt,VfVm", MATCH_VAMOSWAPEI8V, MASK_VAMOSWAPEI8V, match_opcode, INSN_DREF},
+-{"vamoxorei8.v",   0, INSN_CLASS_V_OR_ZVAMO,  "Ve,0(s),Vt,VfVm", MATCH_VAMOXOREI8V, MASK_VAMOXOREI8V, match_opcode, INSN_DREF},
+-{"vamoandei8.v",   0, INSN_CLASS_V_OR_ZVAMO,  "Ve,0(s),Vt,VfVm", MATCH_VAMOANDEI8V, MASK_VAMOANDEI8V, match_opcode, INSN_DREF},
+-{"vamoorei8.v",    0, INSN_CLASS_V_OR_ZVAMO,  "Ve,0(s),Vt,VfVm", MATCH_VAMOOREI8V, MASK_VAMOOREI8V, match_opcode, INSN_DREF},
+-{"vamominei8.v",   0, INSN_CLASS_V_OR_ZVAMO,  "Ve,0(s),Vt,VfVm", MATCH_VAMOMINEI8V, MASK_VAMOMINEI8V, match_opcode, INSN_DREF},
+-{"vamomaxei8.v",   0, INSN_CLASS_V_OR_ZVAMO,  "Ve,0(s),Vt,VfVm", MATCH_VAMOMAXEI8V, MASK_VAMOMAXEI8V, match_opcode, INSN_DREF},
+-{"vamominuei8.v",  0, INSN_CLASS_V_OR_ZVAMO,  "Ve,0(s),Vt,VfVm", MATCH_VAMOMINUEI8V, MASK_VAMOMINUEI8V, match_opcode, INSN_DREF},
+-{"vamomaxuei8.v",  0, INSN_CLASS_V_OR_ZVAMO,  "Ve,0(s),Vt,VfVm", MATCH_VAMOMAXUEI8V, MASK_VAMOMAXUEI8V, match_opcode, INSN_DREF},
+-
+-{"vamoaddei16.v",   0, INSN_CLASS_V_OR_ZVAMO,  "Ve,0(s),Vt,VfVm", MATCH_VAMOADDEI16V, MASK_VAMOADDEI16V, match_opcode, INSN_DREF},
+-{"vamoswapei16.v",  0, INSN_CLASS_V_OR_ZVAMO,  "Ve,0(s),Vt,VfVm", MATCH_VAMOSWAPEI16V, MASK_VAMOSWAPEI16V, match_opcode, INSN_DREF},
+-{"vamoxorei16.v",   0, INSN_CLASS_V_OR_ZVAMO,  "Ve,0(s),Vt,VfVm", MATCH_VAMOXOREI16V, MASK_VAMOXOREI16V, match_opcode, INSN_DREF},
+-{"vamoandei16.v",   0, INSN_CLASS_V_OR_ZVAMO,  "Ve,0(s),Vt,VfVm", MATCH_VAMOANDEI16V, MASK_VAMOANDEI16V, match_opcode, INSN_DREF},
+-{"vamoorei16.v",    0, INSN_CLASS_V_OR_ZVAMO,  "Ve,0(s),Vt,VfVm", MATCH_VAMOOREI16V, MASK_VAMOOREI16V, match_opcode, INSN_DREF},
+-{"vamominei16.v",   0, INSN_CLASS_V_OR_ZVAMO,  "Ve,0(s),Vt,VfVm", MATCH_VAMOMINEI16V, MASK_VAMOMINEI16V, match_opcode, INSN_DREF},
+-{"vamomaxei16.v",   0, INSN_CLASS_V_OR_ZVAMO,  "Ve,0(s),Vt,VfVm", MATCH_VAMOMAXEI16V, MASK_VAMOMAXEI16V, match_opcode, INSN_DREF},
+-{"vamominuei16.v",  0, INSN_CLASS_V_OR_ZVAMO,  "Ve,0(s),Vt,VfVm", MATCH_VAMOMINUEI16V, MASK_VAMOMINUEI16V, match_opcode, INSN_DREF},
+-{"vamomaxuei16.v",  0, INSN_CLASS_V_OR_ZVAMO,  "Ve,0(s),Vt,VfVm", MATCH_VAMOMAXUEI16V, MASK_VAMOMAXUEI16V, match_opcode, INSN_DREF},
+-
+-{"vamoaddei32.v",   0, INSN_CLASS_V_OR_ZVAMO,  "Ve,0(s),Vt,VfVm", MATCH_VAMOADDEI32V, MASK_VAMOADDEI32V, match_opcode, INSN_DREF},
+-{"vamoswapei32.v",  0, INSN_CLASS_V_OR_ZVAMO,  "Ve,0(s),Vt,VfVm", MATCH_VAMOSWAPEI32V, MASK_VAMOSWAPEI32V, match_opcode, INSN_DREF},
+-{"vamoxorei32.v",   0, INSN_CLASS_V_OR_ZVAMO,  "Ve,0(s),Vt,VfVm", MATCH_VAMOXOREI32V, MASK_VAMOXOREI32V, match_opcode, INSN_DREF},
+-{"vamoandei32.v",   0, INSN_CLASS_V_OR_ZVAMO,  "Ve,0(s),Vt,VfVm", MATCH_VAMOANDEI32V, MASK_VAMOANDEI32V, match_opcode, INSN_DREF},
+-{"vamoorei32.v",    0, INSN_CLASS_V_OR_ZVAMO,  "Ve,0(s),Vt,VfVm", MATCH_VAMOOREI32V, MASK_VAMOOREI32V, match_opcode, INSN_DREF},
+-{"vamominei32.v",   0, INSN_CLASS_V_OR_ZVAMO,  "Ve,0(s),Vt,VfVm", MATCH_VAMOMINEI32V, MASK_VAMOMINEI32V, match_opcode, INSN_DREF},
+-{"vamomaxei32.v",   0, INSN_CLASS_V_OR_ZVAMO,  "Ve,0(s),Vt,VfVm", MATCH_VAMOMAXEI32V, MASK_VAMOMAXEI32V, match_opcode, INSN_DREF},
+-{"vamominuei32.v",  0, INSN_CLASS_V_OR_ZVAMO,  "Ve,0(s),Vt,VfVm", MATCH_VAMOMINUEI32V, MASK_VAMOMINUEI32V, match_opcode, INSN_DREF},
+-{"vamomaxuei32.v",  0, INSN_CLASS_V_OR_ZVAMO,  "Ve,0(s),Vt,VfVm", MATCH_VAMOMAXUEI32V, MASK_VAMOMAXUEI32V, match_opcode, INSN_DREF},
+-
+-{"vamoaddei64.v",   0, INSN_CLASS_V_OR_ZVAMO,  "Ve,0(s),Vt,VfVm", MATCH_VAMOADDEI64V, MASK_VAMOADDEI64V, match_opcode, INSN_DREF},
+-{"vamoswapei64.v",  0, INSN_CLASS_V_OR_ZVAMO,  "Ve,0(s),Vt,VfVm", MATCH_VAMOSWAPEI64V, MASK_VAMOSWAPEI64V, match_opcode, INSN_DREF},
+-{"vamoxorei64.v",   0, INSN_CLASS_V_OR_ZVAMO,  "Ve,0(s),Vt,VfVm", MATCH_VAMOXOREI64V, MASK_VAMOXOREI64V, match_opcode, INSN_DREF},
+-{"vamoandei64.v",   0, INSN_CLASS_V_OR_ZVAMO,  "Ve,0(s),Vt,VfVm", MATCH_VAMOANDEI64V, MASK_VAMOANDEI64V, match_opcode, INSN_DREF},
+-{"vamoorei64.v",    0, INSN_CLASS_V_OR_ZVAMO,  "Ve,0(s),Vt,VfVm", MATCH_VAMOOREI64V, MASK_VAMOOREI64V, match_opcode, INSN_DREF},
+-{"vamominei64.v",   0, INSN_CLASS_V_OR_ZVAMO,  "Ve,0(s),Vt,VfVm", MATCH_VAMOMINEI64V, MASK_VAMOMINEI64V, match_opcode, INSN_DREF},
+-{"vamomaxei64.v",   0, INSN_CLASS_V_OR_ZVAMO,  "Ve,0(s),Vt,VfVm", MATCH_VAMOMAXEI64V, MASK_VAMOMAXEI64V, match_opcode, INSN_DREF},
+-{"vamominuei64.v",  0, INSN_CLASS_V_OR_ZVAMO,  "Ve,0(s),Vt,VfVm", MATCH_VAMOMINUEI64V, MASK_VAMOMINUEI64V, match_opcode, INSN_DREF},
+-{"vamomaxuei64.v",  0, INSN_CLASS_V_OR_ZVAMO,  "Ve,0(s),Vt,VfVm", MATCH_VAMOMAXUEI64V, MASK_VAMOMAXUEI64V, match_opcode, INSN_DREF},
+-
+-{"vadd.vv",    0, INSN_CLASS_V,  "Vd,Vt,VsVm", MATCH_VADDVV, MASK_VADDVV, match_opcode, 0 },
+-{"vadd.vx",    0, INSN_CLASS_V,  "Vd,Vt,sVm", MATCH_VADDVX, MASK_VADDVX, match_opcode, 0 },
+-{"vadd.vi",    0, INSN_CLASS_V,  "Vd,Vt,ViVm", MATCH_VADDVI, MASK_VADDVI, match_opcode, 0 },
+-{"vsub.vv",    0, INSN_CLASS_V,  "Vd,Vt,VsVm", MATCH_VSUBVV, MASK_VSUBVV, match_opcode, 0 },
+-{"vsub.vx",    0, INSN_CLASS_V,  "Vd,Vt,sVm", MATCH_VSUBVX, MASK_VSUBVX, match_opcode, 0 },
+-{"vrsub.vx",   0, INSN_CLASS_V,  "Vd,Vt,sVm", MATCH_VRSUBVX, MASK_VRSUBVX, match_opcode, 0 },
+-{"vrsub.vi",   0, INSN_CLASS_V,  "Vd,Vt,ViVm", MATCH_VRSUBVI, MASK_VRSUBVI, match_opcode, 0 },
++{"vamoaddei8.v",   0, INSN_CLASS_V_OR_ZVAMO,  "Ve,0(s),Vt,VfVm", MATCH_VAMOADDEI8V, MASK_VAMOADDEI8V, match_vd_neq_vm, INSN_DREF},
++{"vamoswapei8.v",  0, INSN_CLASS_V_OR_ZVAMO,  "Ve,0(s),Vt,VfVm", MATCH_VAMOSWAPEI8V, MASK_VAMOSWAPEI8V, match_vd_neq_vm, INSN_DREF},
++{"vamoxorei8.v",   0, INSN_CLASS_V_OR_ZVAMO,  "Ve,0(s),Vt,VfVm", MATCH_VAMOXOREI8V, MASK_VAMOXOREI8V, match_vd_neq_vm, INSN_DREF},
++{"vamoandei8.v",   0, INSN_CLASS_V_OR_ZVAMO,  "Ve,0(s),Vt,VfVm", MATCH_VAMOANDEI8V, MASK_VAMOANDEI8V, match_vd_neq_vm, INSN_DREF},
++{"vamoorei8.v",    0, INSN_CLASS_V_OR_ZVAMO,  "Ve,0(s),Vt,VfVm", MATCH_VAMOOREI8V, MASK_VAMOOREI8V, match_vd_neq_vm, INSN_DREF},
++{"vamominei8.v",   0, INSN_CLASS_V_OR_ZVAMO,  "Ve,0(s),Vt,VfVm", MATCH_VAMOMINEI8V, MASK_VAMOMINEI8V, match_vd_neq_vm, INSN_DREF},
++{"vamomaxei8.v",   0, INSN_CLASS_V_OR_ZVAMO,  "Ve,0(s),Vt,VfVm", MATCH_VAMOMAXEI8V, MASK_VAMOMAXEI8V, match_vd_neq_vm, INSN_DREF},
++{"vamominuei8.v",  0, INSN_CLASS_V_OR_ZVAMO,  "Ve,0(s),Vt,VfVm", MATCH_VAMOMINUEI8V, MASK_VAMOMINUEI8V, match_vd_neq_vm, INSN_DREF},
++{"vamomaxuei8.v",  0, INSN_CLASS_V_OR_ZVAMO,  "Ve,0(s),Vt,VfVm", MATCH_VAMOMAXUEI8V, MASK_VAMOMAXUEI8V, match_vd_neq_vm, INSN_DREF},
++
++{"vamoaddei16.v",   0, INSN_CLASS_V_OR_ZVAMO,  "Ve,0(s),Vt,VfVm", MATCH_VAMOADDEI16V, MASK_VAMOADDEI16V, match_vd_neq_vm, INSN_DREF},
++{"vamoswapei16.v",  0, INSN_CLASS_V_OR_ZVAMO,  "Ve,0(s),Vt,VfVm", MATCH_VAMOSWAPEI16V, MASK_VAMOSWAPEI16V, match_vd_neq_vm, INSN_DREF},
++{"vamoxorei16.v",   0, INSN_CLASS_V_OR_ZVAMO,  "Ve,0(s),Vt,VfVm", MATCH_VAMOXOREI16V, MASK_VAMOXOREI16V, match_vd_neq_vm, INSN_DREF},
++{"vamoandei16.v",   0, INSN_CLASS_V_OR_ZVAMO,  "Ve,0(s),Vt,VfVm", MATCH_VAMOANDEI16V, MASK_VAMOANDEI16V, match_vd_neq_vm, INSN_DREF},
++{"vamoorei16.v",    0, INSN_CLASS_V_OR_ZVAMO,  "Ve,0(s),Vt,VfVm", MATCH_VAMOOREI16V, MASK_VAMOOREI16V, match_vd_neq_vm, INSN_DREF},
++{"vamominei16.v",   0, INSN_CLASS_V_OR_ZVAMO,  "Ve,0(s),Vt,VfVm", MATCH_VAMOMINEI16V, MASK_VAMOMINEI16V, match_vd_neq_vm, INSN_DREF},
++{"vamomaxei16.v",   0, INSN_CLASS_V_OR_ZVAMO,  "Ve,0(s),Vt,VfVm", MATCH_VAMOMAXEI16V, MASK_VAMOMAXEI16V, match_vd_neq_vm, INSN_DREF},
++{"vamominuei16.v",  0, INSN_CLASS_V_OR_ZVAMO,  "Ve,0(s),Vt,VfVm", MATCH_VAMOMINUEI16V, MASK_VAMOMINUEI16V, match_vd_neq_vm, INSN_DREF},
++{"vamomaxuei16.v",  0, INSN_CLASS_V_OR_ZVAMO,  "Ve,0(s),Vt,VfVm", MATCH_VAMOMAXUEI16V, MASK_VAMOMAXUEI16V, match_vd_neq_vm, INSN_DREF},
++
++{"vamoaddei32.v",   0, INSN_CLASS_V_OR_ZVAMO,  "Ve,0(s),Vt,VfVm", MATCH_VAMOADDEI32V, MASK_VAMOADDEI32V, match_vd_neq_vm, INSN_DREF},
++{"vamoswapei32.v",  0, INSN_CLASS_V_OR_ZVAMO,  "Ve,0(s),Vt,VfVm", MATCH_VAMOSWAPEI32V, MASK_VAMOSWAPEI32V, match_vd_neq_vm, INSN_DREF},
++{"vamoxorei32.v",   0, INSN_CLASS_V_OR_ZVAMO,  "Ve,0(s),Vt,VfVm", MATCH_VAMOXOREI32V, MASK_VAMOXOREI32V, match_vd_neq_vm, INSN_DREF},
++{"vamoandei32.v",   0, INSN_CLASS_V_OR_ZVAMO,  "Ve,0(s),Vt,VfVm", MATCH_VAMOANDEI32V, MASK_VAMOANDEI32V, match_vd_neq_vm, INSN_DREF},
++{"vamoorei32.v",    0, INSN_CLASS_V_OR_ZVAMO,  "Ve,0(s),Vt,VfVm", MATCH_VAMOOREI32V, MASK_VAMOOREI32V, match_vd_neq_vm, INSN_DREF},
++{"vamominei32.v",   0, INSN_CLASS_V_OR_ZVAMO,  "Ve,0(s),Vt,VfVm", MATCH_VAMOMINEI32V, MASK_VAMOMINEI32V, match_vd_neq_vm, INSN_DREF},
++{"vamomaxei32.v",   0, INSN_CLASS_V_OR_ZVAMO,  "Ve,0(s),Vt,VfVm", MATCH_VAMOMAXEI32V, MASK_VAMOMAXEI32V, match_vd_neq_vm, INSN_DREF},
++{"vamominuei32.v",  0, INSN_CLASS_V_OR_ZVAMO,  "Ve,0(s),Vt,VfVm", MATCH_VAMOMINUEI32V, MASK_VAMOMINUEI32V, match_vd_neq_vm, INSN_DREF},
++{"vamomaxuei32.v",  0, INSN_CLASS_V_OR_ZVAMO,  "Ve,0(s),Vt,VfVm", MATCH_VAMOMAXUEI32V, MASK_VAMOMAXUEI32V, match_vd_neq_vm, INSN_DREF},
++
++{"vamoaddei64.v",   0, INSN_CLASS_V_OR_ZVAMO,  "Ve,0(s),Vt,VfVm", MATCH_VAMOADDEI64V, MASK_VAMOADDEI64V, match_vd_neq_vm, INSN_DREF},
++{"vamoswapei64.v",  0, INSN_CLASS_V_OR_ZVAMO,  "Ve,0(s),Vt,VfVm", MATCH_VAMOSWAPEI64V, MASK_VAMOSWAPEI64V, match_vd_neq_vm, INSN_DREF},
++{"vamoxorei64.v",   0, INSN_CLASS_V_OR_ZVAMO,  "Ve,0(s),Vt,VfVm", MATCH_VAMOXOREI64V, MASK_VAMOXOREI64V, match_vd_neq_vm, INSN_DREF},
++{"vamoandei64.v",   0, INSN_CLASS_V_OR_ZVAMO,  "Ve,0(s),Vt,VfVm", MATCH_VAMOANDEI64V, MASK_VAMOANDEI64V, match_vd_neq_vm, INSN_DREF},
++{"vamoorei64.v",    0, INSN_CLASS_V_OR_ZVAMO,  "Ve,0(s),Vt,VfVm", MATCH_VAMOOREI64V, MASK_VAMOOREI64V, match_vd_neq_vm, INSN_DREF},
++{"vamominei64.v",   0, INSN_CLASS_V_OR_ZVAMO,  "Ve,0(s),Vt,VfVm", MATCH_VAMOMINEI64V, MASK_VAMOMINEI64V, match_vd_neq_vm, INSN_DREF},
++{"vamomaxei64.v",   0, INSN_CLASS_V_OR_ZVAMO,  "Ve,0(s),Vt,VfVm", MATCH_VAMOMAXEI64V, MASK_VAMOMAXEI64V, match_vd_neq_vm, INSN_DREF},
++{"vamominuei64.v",  0, INSN_CLASS_V_OR_ZVAMO,  "Ve,0(s),Vt,VfVm", MATCH_VAMOMINUEI64V, MASK_VAMOMINUEI64V, match_vd_neq_vm, INSN_DREF},
++{"vamomaxuei64.v",  0, INSN_CLASS_V_OR_ZVAMO,  "Ve,0(s),Vt,VfVm", MATCH_VAMOMAXUEI64V, MASK_VAMOMAXUEI64V, match_vd_neq_vm, INSN_DREF},
++
++{"vadd.vv",    0, INSN_CLASS_V,  "Vd,Vt,VsVm", MATCH_VADDVV, MASK_VADDVV, match_vd_neq_vm, 0 },
++{"vadd.vx",    0, INSN_CLASS_V,  "Vd,Vt,sVm", MATCH_VADDVX, MASK_VADDVX, match_vd_neq_vm, 0 },
++{"vadd.vi",    0, INSN_CLASS_V,  "Vd,Vt,ViVm", MATCH_VADDVI, MASK_VADDVI, match_vd_neq_vm, 0 },
++{"vsub.vv",    0, INSN_CLASS_V,  "Vd,Vt,VsVm", MATCH_VSUBVV, MASK_VSUBVV, match_vd_neq_vm, 0 },
++{"vsub.vx",    0, INSN_CLASS_V,  "Vd,Vt,sVm", MATCH_VSUBVX, MASK_VSUBVX, match_vd_neq_vm, 0 },
++{"vrsub.vx",   0, INSN_CLASS_V,  "Vd,Vt,sVm", MATCH_VRSUBVX, MASK_VRSUBVX, match_vd_neq_vm, 0 },
++{"vrsub.vi",   0, INSN_CLASS_V,  "Vd,Vt,ViVm", MATCH_VRSUBVI, MASK_VRSUBVI, match_vd_neq_vm, 0 },
+ 
+ {"vwcvt.x.x.v",  0, INSN_CLASS_V,  "Vd,VtVm", MATCH_VWCVTXXV, MASK_VWCVTXXV, match_widen_vd_neq_vs2_neq_vm, INSN_ALIAS },
+ {"vwcvtu.x.x.v", 0, INSN_CLASS_V,  "Vd,VtVm", MATCH_VWCVTUXXV, MASK_VWCVTUXXV, match_widen_vd_neq_vs2_neq_vm, INSN_ALIAS },
+@@ -1663,59 +1656,59 @@ const struct riscv_opcode riscv_opcodes[] =
+ {"vwsub.wv",   0, INSN_CLASS_V,  "Vd,Vt,VsVm", MATCH_VWSUBWV, MASK_VWSUBWV, match_widen_vd_neq_vs1_neq_vm, 0 },
+ {"vwsub.wx",   0, INSN_CLASS_V,  "Vd,Vt,sVm", MATCH_VWSUBWX, MASK_VWSUBWX, match_widen_vd_neq_vm, 0 },
+ 
+-{"vzext.vf2",  0, INSN_CLASS_V,  "Vd,VtVm", MATCH_VZEXT_VF2, MASK_VZEXT_VF2, match_opcode, 0 },
+-{"vsext.vf2",  0, INSN_CLASS_V,  "Vd,VtVm", MATCH_VSEXT_VF2, MASK_VSEXT_VF2, match_opcode, 0 },
+-{"vzext.vf4",  0, INSN_CLASS_V,  "Vd,VtVm", MATCH_VZEXT_VF4, MASK_VZEXT_VF4, match_opcode, 0 },
+-{"vsext.vf4",  0, INSN_CLASS_V,  "Vd,VtVm", MATCH_VSEXT_VF4, MASK_VSEXT_VF4, match_opcode, 0 },
+-{"vzext.vf8",  0, INSN_CLASS_V,  "Vd,VtVm", MATCH_VZEXT_VF8, MASK_VZEXT_VF8, match_opcode, 0 },
+-{"vsext.vf8",  0, INSN_CLASS_V,  "Vd,VtVm", MATCH_VSEXT_VF8, MASK_VSEXT_VF8, match_opcode, 0 },
++{"vzext.vf2",  0, INSN_CLASS_V,  "Vd,VtVm", MATCH_VZEXT_VF2, MASK_VZEXT_VF2, match_vd_neq_vm, 0 },
++{"vsext.vf2",  0, INSN_CLASS_V,  "Vd,VtVm", MATCH_VSEXT_VF2, MASK_VSEXT_VF2, match_vd_neq_vm, 0 },
++{"vzext.vf4",  0, INSN_CLASS_V,  "Vd,VtVm", MATCH_VZEXT_VF4, MASK_VZEXT_VF4, match_vd_neq_vm, 0 },
++{"vsext.vf4",  0, INSN_CLASS_V,  "Vd,VtVm", MATCH_VSEXT_VF4, MASK_VSEXT_VF4, match_vd_neq_vm, 0 },
++{"vzext.vf8",  0, INSN_CLASS_V,  "Vd,VtVm", MATCH_VZEXT_VF8, MASK_VZEXT_VF8, match_vd_neq_vm, 0 },
++{"vsext.vf8",  0, INSN_CLASS_V,  "Vd,VtVm", MATCH_VSEXT_VF8, MASK_VSEXT_VF8, match_vd_neq_vm, 0 },
+ 
+-{"vadc.vvm",   0, INSN_CLASS_V,  "Vd,Vt,Vs,V0", MATCH_VADCVVM, MASK_VADCVVM, match_opcode, 0 },
+-{"vadc.vxm",   0, INSN_CLASS_V,  "Vd,Vt,s,V0", MATCH_VADCVXM, MASK_VADCVXM, match_opcode, 0 },
+-{"vadc.vim",   0, INSN_CLASS_V,  "Vd,Vt,Vi,V0", MATCH_VADCVIM, MASK_VADCVIM, match_opcode, 0 },
++{"vadc.vvm",   0, INSN_CLASS_V,  "Vd,Vt,Vs,V0", MATCH_VADCVVM, MASK_VADCVVM, match_vd_neq_vm, 0 },
++{"vadc.vxm",   0, INSN_CLASS_V,  "Vd,Vt,s,V0", MATCH_VADCVXM, MASK_VADCVXM, match_vd_neq_vm, 0 },
++{"vadc.vim",   0, INSN_CLASS_V,  "Vd,Vt,Vi,V0", MATCH_VADCVIM, MASK_VADCVIM, match_vd_neq_vm, 0 },
+ {"vmadc.vvm",  0, INSN_CLASS_V,  "Vd,Vt,Vs,V0", MATCH_VMADCVVM, MASK_VMADCVVM, match_opcode, 0 },
+ {"vmadc.vxm",  0, INSN_CLASS_V,  "Vd,Vt,s,V0", MATCH_VMADCVXM, MASK_VMADCVXM, match_opcode, 0 },
+ {"vmadc.vim",  0, INSN_CLASS_V,  "Vd,Vt,Vi,V0", MATCH_VMADCVIM, MASK_VMADCVIM, match_opcode, 0 },
+ {"vmadc.vv",   0, INSN_CLASS_V,  "Vd,Vt,Vs", MATCH_VMADCVV, MASK_VMADCVV, match_opcode, 0 },
+ {"vmadc.vx",   0, INSN_CLASS_V,  "Vd,Vt,s", MATCH_VMADCVX, MASK_VMADCVX, match_opcode, 0 },
+ {"vmadc.vi",   0, INSN_CLASS_V,  "Vd,Vt,Vi", MATCH_VMADCVI, MASK_VMADCVI, match_opcode, 0 },
+-{"vsbc.vvm",   0, INSN_CLASS_V,  "Vd,Vt,Vs,V0", MATCH_VSBCVVM, MASK_VSBCVVM, match_opcode, 0 },
+-{"vsbc.vxm",   0, INSN_CLASS_V,  "Vd,Vt,s,V0", MATCH_VSBCVXM, MASK_VSBCVXM, match_opcode, 0 },
++{"vsbc.vvm",   0, INSN_CLASS_V,  "Vd,Vt,Vs,V0", MATCH_VSBCVVM, MASK_VSBCVVM, match_vd_neq_vm, 0 },
++{"vsbc.vxm",   0, INSN_CLASS_V,  "Vd,Vt,s,V0", MATCH_VSBCVXM, MASK_VSBCVXM, match_vd_neq_vm, 0 },
+ {"vmsbc.vvm",  0, INSN_CLASS_V,  "Vd,Vt,Vs,V0", MATCH_VMSBCVVM, MASK_VMSBCVVM, match_opcode, 0 },
+ {"vmsbc.vxm",  0, INSN_CLASS_V,  "Vd,Vt,s,V0", MATCH_VMSBCVXM, MASK_VMSBCVXM, match_opcode, 0 },
+ {"vmsbc.vv",   0, INSN_CLASS_V,  "Vd,Vt,Vs", MATCH_VMSBCVV, MASK_VMSBCVV, match_opcode, 0 },
+ {"vmsbc.vx",   0, INSN_CLASS_V,  "Vd,Vt,s", MATCH_VMSBCVX, MASK_VMSBCVX, match_opcode, 0 },
+ 
+-{"vnot.v",     0, INSN_CLASS_V,  "Vd,VtVm", MATCH_VNOTV, MASK_VNOTV, match_opcode, INSN_ALIAS },
+-
+-{"vand.vv",    0, INSN_CLASS_V,  "Vd,Vt,VsVm", MATCH_VANDVV, MASK_VANDVV, match_opcode, 0 },
+-{"vand.vx",    0, INSN_CLASS_V,  "Vd,Vt,sVm", MATCH_VANDVX, MASK_VANDVX, match_opcode, 0 },
+-{"vand.vi",    0, INSN_CLASS_V,  "Vd,Vt,ViVm", MATCH_VANDVI, MASK_VANDVI, match_opcode, 0 },
+-{"vor.vv",     0, INSN_CLASS_V,  "Vd,Vt,VsVm", MATCH_VORVV, MASK_VORVV, match_opcode, 0 },
+-{"vor.vx",     0, INSN_CLASS_V,  "Vd,Vt,sVm", MATCH_VORVX, MASK_VORVX, match_opcode, 0 },
+-{"vor.vi",     0, INSN_CLASS_V,  "Vd,Vt,ViVm", MATCH_VORVI, MASK_VORVI, match_opcode, 0 },
+-{"vxor.vv",    0, INSN_CLASS_V,  "Vd,Vt,VsVm", MATCH_VXORVV, MASK_VXORVV, match_opcode, 0 },
+-{"vxor.vx",    0, INSN_CLASS_V,  "Vd,Vt,sVm", MATCH_VXORVX, MASK_VXORVX, match_opcode, 0 },
+-{"vxor.vi",    0, INSN_CLASS_V,  "Vd,Vt,ViVm", MATCH_VXORVI, MASK_VXORVI, match_opcode, 0 },
+-
+-{"vsll.vv",    0, INSN_CLASS_V,  "Vd,Vt,VsVm", MATCH_VSLLVV, MASK_VSLLVV, match_opcode, 0 },
+-{"vsll.vx",    0, INSN_CLASS_V,  "Vd,Vt,sVm", MATCH_VSLLVX, MASK_VSLLVX, match_opcode, 0 },
+-{"vsll.vi",    0, INSN_CLASS_V,  "Vd,Vt,VjVm", MATCH_VSLLVI, MASK_VSLLVI, match_opcode, 0 },
+-{"vsrl.vv",    0, INSN_CLASS_V,  "Vd,Vt,VsVm", MATCH_VSRLVV, MASK_VSRLVV, match_opcode, 0 },
+-{"vsrl.vx",    0, INSN_CLASS_V,  "Vd,Vt,sVm", MATCH_VSRLVX, MASK_VSRLVX, match_opcode, 0 },
+-{"vsrl.vi",    0, INSN_CLASS_V,  "Vd,Vt,VjVm", MATCH_VSRLVI, MASK_VSRLVI, match_opcode, 0 },
+-{"vsra.vv",    0, INSN_CLASS_V,  "Vd,Vt,VsVm", MATCH_VSRAVV, MASK_VSRAVV, match_opcode, 0 },
+-{"vsra.vx",    0, INSN_CLASS_V,  "Vd,Vt,sVm", MATCH_VSRAVX, MASK_VSRAVX, match_opcode, 0 },
+-{"vsra.vi",    0, INSN_CLASS_V,  "Vd,Vt,VjVm", MATCH_VSRAVI, MASK_VSRAVI, match_opcode, 0 },
+-
+-{"vncvt.x.x.v",0, INSN_CLASS_V,  "Vd,VtVm", MATCH_VNCVTXXV, MASK_VNCVTXXV, match_narrow_vd_neq_vs2, INSN_ALIAS },
+-
+-{"vnsrl.wv",   0, INSN_CLASS_V,  "Vd,Vt,VsVm", MATCH_VNSRLWV, MASK_VNSRLWV, match_narrow_vd_neq_vs2, 0 },
+-{"vnsrl.wx",   0, INSN_CLASS_V,  "Vd,Vt,sVm", MATCH_VNSRLWX, MASK_VNSRLWX, match_narrow_vd_neq_vs2, 0 },
+-{"vnsrl.wi",   0, INSN_CLASS_V,  "Vd,Vt,VjVm", MATCH_VNSRLWI, MASK_VNSRLWI, match_narrow_vd_neq_vs2, 0 },
+-{"vnsra.wv",   0, INSN_CLASS_V,  "Vd,Vt,VsVm", MATCH_VNSRAWV, MASK_VNSRAWV, match_narrow_vd_neq_vs2, 0 },
+-{"vnsra.wx",   0, INSN_CLASS_V,  "Vd,Vt,sVm", MATCH_VNSRAWX, MASK_VNSRAWX, match_narrow_vd_neq_vs2, 0 },
+-{"vnsra.wi",   0, INSN_CLASS_V,  "Vd,Vt,VjVm", MATCH_VNSRAWI, MASK_VNSRAWI, match_narrow_vd_neq_vs2, 0 },
++{"vnot.v",     0, INSN_CLASS_V,  "Vd,VtVm", MATCH_VNOTV, MASK_VNOTV, match_vd_neq_vm, INSN_ALIAS },
++
++{"vand.vv",    0, INSN_CLASS_V,  "Vd,Vt,VsVm", MATCH_VANDVV, MASK_VANDVV, match_vd_neq_vm, 0 },
++{"vand.vx",    0, INSN_CLASS_V,  "Vd,Vt,sVm", MATCH_VANDVX, MASK_VANDVX, match_vd_neq_vm, 0 },
++{"vand.vi",    0, INSN_CLASS_V,  "Vd,Vt,ViVm", MATCH_VANDVI, MASK_VANDVI, match_vd_neq_vm, 0 },
++{"vor.vv",     0, INSN_CLASS_V,  "Vd,Vt,VsVm", MATCH_VORVV, MASK_VORVV, match_vd_neq_vm, 0 },
++{"vor.vx",     0, INSN_CLASS_V,  "Vd,Vt,sVm", MATCH_VORVX, MASK_VORVX, match_vd_neq_vm, 0 },
++{"vor.vi",     0, INSN_CLASS_V,  "Vd,Vt,ViVm", MATCH_VORVI, MASK_VORVI, match_vd_neq_vm, 0 },
++{"vxor.vv",    0, INSN_CLASS_V,  "Vd,Vt,VsVm", MATCH_VXORVV, MASK_VXORVV, match_vd_neq_vm, 0 },
++{"vxor.vx",    0, INSN_CLASS_V,  "Vd,Vt,sVm", MATCH_VXORVX, MASK_VXORVX, match_vd_neq_vm, 0 },
++{"vxor.vi",    0, INSN_CLASS_V,  "Vd,Vt,ViVm", MATCH_VXORVI, MASK_VXORVI, match_vd_neq_vm, 0 },
++
++{"vsll.vv",    0, INSN_CLASS_V,  "Vd,Vt,VsVm", MATCH_VSLLVV, MASK_VSLLVV, match_vd_neq_vm, 0 },
++{"vsll.vx",    0, INSN_CLASS_V,  "Vd,Vt,sVm", MATCH_VSLLVX, MASK_VSLLVX, match_vd_neq_vm, 0 },
++{"vsll.vi",    0, INSN_CLASS_V,  "Vd,Vt,VjVm", MATCH_VSLLVI, MASK_VSLLVI, match_vd_neq_vm, 0 },
++{"vsrl.vv",    0, INSN_CLASS_V,  "Vd,Vt,VsVm", MATCH_VSRLVV, MASK_VSRLVV, match_vd_neq_vm, 0 },
++{"vsrl.vx",    0, INSN_CLASS_V,  "Vd,Vt,sVm", MATCH_VSRLVX, MASK_VSRLVX, match_vd_neq_vm, 0 },
++{"vsrl.vi",    0, INSN_CLASS_V,  "Vd,Vt,VjVm", MATCH_VSRLVI, MASK_VSRLVI, match_vd_neq_vm, 0 },
++{"vsra.vv",    0, INSN_CLASS_V,  "Vd,Vt,VsVm", MATCH_VSRAVV, MASK_VSRAVV, match_vd_neq_vm, 0 },
++{"vsra.vx",    0, INSN_CLASS_V,  "Vd,Vt,sVm", MATCH_VSRAVX, MASK_VSRAVX, match_vd_neq_vm, 0 },
++{"vsra.vi",    0, INSN_CLASS_V,  "Vd,Vt,VjVm", MATCH_VSRAVI, MASK_VSRAVI, match_vd_neq_vm, 0 },
++
++{"vncvt.x.x.v",0, INSN_CLASS_V,  "Vd,VtVm", MATCH_VNCVTXXV, MASK_VNCVTXXV, match_narrow_vd_neq_vs2_neq_vm, INSN_ALIAS },
++
++{"vnsrl.wv",   0, INSN_CLASS_V,  "Vd,Vt,VsVm", MATCH_VNSRLWV, MASK_VNSRLWV, match_narrow_vd_neq_vs2_neq_vm, 0 },
++{"vnsrl.wx",   0, INSN_CLASS_V,  "Vd,Vt,sVm", MATCH_VNSRLWX, MASK_VNSRLWX, match_narrow_vd_neq_vs2_neq_vm, 0 },
++{"vnsrl.wi",   0, INSN_CLASS_V,  "Vd,Vt,VjVm", MATCH_VNSRLWI, MASK_VNSRLWI, match_narrow_vd_neq_vs2_neq_vm, 0 },
++{"vnsra.wv",   0, INSN_CLASS_V,  "Vd,Vt,VsVm", MATCH_VNSRAWV, MASK_VNSRAWV, match_narrow_vd_neq_vs2_neq_vm, 0 },
++{"vnsra.wx",   0, INSN_CLASS_V,  "Vd,Vt,sVm", MATCH_VNSRAWX, MASK_VNSRAWX, match_narrow_vd_neq_vs2_neq_vm, 0 },
++{"vnsra.wi",   0, INSN_CLASS_V,  "Vd,Vt,VjVm", MATCH_VNSRAWI, MASK_VNSRAWI, match_narrow_vd_neq_vs2_neq_vm, 0 },
+ 
+ {"vmseq.vv",   0, INSN_CLASS_V,  "Vd,Vt,VsVm", MATCH_VMSEQVV, MASK_VMSEQVV, match_opcode, 0 },
+ {"vmseq.vx",   0, INSN_CLASS_V,  "Vd,Vt,sVm", MATCH_VMSEQVX, MASK_VMSEQVX, match_opcode, 0 },
+@@ -1755,23 +1748,23 @@ const struct riscv_opcode riscv_opcodes[] =
+ {"vmsgeu.vx",  0, INSN_CLASS_V, "Vd,Vt,sVm", 0, (int) M_VMSGEU, match_never, INSN_MACRO },
+ {"vmsgeu.vx",  0, INSN_CLASS_V, "Vd,Vt,s,VM,VT", 0, (int) M_VMSGEU, match_never, INSN_MACRO },
+ 
+-{"vminu.vv",   0, INSN_CLASS_V,  "Vd,Vt,VsVm", MATCH_VMINUVV, MASK_VMINUVV, match_opcode, 0},
+-{"vminu.vx",   0, INSN_CLASS_V,  "Vd,Vt,sVm", MATCH_VMINUVX, MASK_VMINUVX, match_opcode, 0},
+-{"vmin.vv",    0, INSN_CLASS_V,  "Vd,Vt,VsVm", MATCH_VMINVV, MASK_VMINVV, match_opcode, 0},
+-{"vmin.vx",    0, INSN_CLASS_V,  "Vd,Vt,sVm", MATCH_VMINVX, MASK_VMINVX, match_opcode, 0},
+-{"vmaxu.vv",   0, INSN_CLASS_V,  "Vd,Vt,VsVm", MATCH_VMAXUVV, MASK_VMAXUVV, match_opcode, 0},
+-{"vmaxu.vx",   0, INSN_CLASS_V,  "Vd,Vt,sVm", MATCH_VMAXUVX, MASK_VMAXUVX, match_opcode, 0},
+-{"vmax.vv",    0, INSN_CLASS_V,  "Vd,Vt,VsVm", MATCH_VMAXVV, MASK_VMAXVV, match_opcode, 0},
+-{"vmax.vx",    0, INSN_CLASS_V,  "Vd,Vt,sVm", MATCH_VMAXVX, MASK_VMAXVX, match_opcode, 0},
+-
+-{"vmul.vv",    0, INSN_CLASS_V,  "Vd,Vt,VsVm", MATCH_VMULVV, MASK_VMULVV, match_opcode, 0 },
+-{"vmul.vx",    0, INSN_CLASS_V,  "Vd,Vt,sVm", MATCH_VMULVX, MASK_VMULVX, match_opcode, 0 },
+-{"vmulh.vv",   0, INSN_CLASS_V,  "Vd,Vt,VsVm", MATCH_VMULHVV, MASK_VMULHVV, match_opcode, 0 },
+-{"vmulh.vx",   0, INSN_CLASS_V,  "Vd,Vt,sVm", MATCH_VMULHVX, MASK_VMULHVX, match_opcode, 0 },
+-{"vmulhu.vv",  0, INSN_CLASS_V,  "Vd,Vt,VsVm", MATCH_VMULHUVV, MASK_VMULHUVV, match_opcode, 0 },
+-{"vmulhu.vx",  0, INSN_CLASS_V,  "Vd,Vt,sVm", MATCH_VMULHUVX, MASK_VMULHUVX, match_opcode, 0 },
+-{"vmulhsu.vv", 0, INSN_CLASS_V,  "Vd,Vt,VsVm", MATCH_VMULHSUVV, MASK_VMULHSUVV, match_opcode, 0 },
+-{"vmulhsu.vx", 0, INSN_CLASS_V,  "Vd,Vt,sVm", MATCH_VMULHSUVX, MASK_VMULHSUVX, match_opcode, 0 },
++{"vminu.vv",   0, INSN_CLASS_V,  "Vd,Vt,VsVm", MATCH_VMINUVV, MASK_VMINUVV, match_vd_neq_vm, 0},
++{"vminu.vx",   0, INSN_CLASS_V,  "Vd,Vt,sVm", MATCH_VMINUVX, MASK_VMINUVX, match_vd_neq_vm, 0},
++{"vmin.vv",    0, INSN_CLASS_V,  "Vd,Vt,VsVm", MATCH_VMINVV, MASK_VMINVV, match_vd_neq_vm, 0},
++{"vmin.vx",    0, INSN_CLASS_V,  "Vd,Vt,sVm", MATCH_VMINVX, MASK_VMINVX, match_vd_neq_vm, 0},
++{"vmaxu.vv",   0, INSN_CLASS_V,  "Vd,Vt,VsVm", MATCH_VMAXUVV, MASK_VMAXUVV, match_vd_neq_vm, 0},
++{"vmaxu.vx",   0, INSN_CLASS_V,  "Vd,Vt,sVm", MATCH_VMAXUVX, MASK_VMAXUVX, match_vd_neq_vm, 0},
++{"vmax.vv",    0, INSN_CLASS_V,  "Vd,Vt,VsVm", MATCH_VMAXVV, MASK_VMAXVV, match_vd_neq_vm, 0},
++{"vmax.vx",    0, INSN_CLASS_V,  "Vd,Vt,sVm", MATCH_VMAXVX, MASK_VMAXVX, match_vd_neq_vm, 0},
++
++{"vmul.vv",    0, INSN_CLASS_V,  "Vd,Vt,VsVm", MATCH_VMULVV, MASK_VMULVV, match_vd_neq_vm, 0 },
++{"vmul.vx",    0, INSN_CLASS_V,  "Vd,Vt,sVm", MATCH_VMULVX, MASK_VMULVX, match_vd_neq_vm, 0 },
++{"vmulh.vv",   0, INSN_CLASS_V,  "Vd,Vt,VsVm", MATCH_VMULHVV, MASK_VMULHVV, match_vd_neq_vm, 0 },
++{"vmulh.vx",   0, INSN_CLASS_V,  "Vd,Vt,sVm", MATCH_VMULHVX, MASK_VMULHVX, match_vd_neq_vm, 0 },
++{"vmulhu.vv",  0, INSN_CLASS_V,  "Vd,Vt,VsVm", MATCH_VMULHUVV, MASK_VMULHUVV, match_vd_neq_vm, 0 },
++{"vmulhu.vx",  0, INSN_CLASS_V,  "Vd,Vt,sVm", MATCH_VMULHUVX, MASK_VMULHUVX, match_vd_neq_vm, 0 },
++{"vmulhsu.vv", 0, INSN_CLASS_V,  "Vd,Vt,VsVm", MATCH_VMULHSUVV, MASK_VMULHSUVV, match_vd_neq_vm, 0 },
++{"vmulhsu.vx", 0, INSN_CLASS_V,  "Vd,Vt,sVm", MATCH_VMULHSUVX, MASK_VMULHSUVX, match_vd_neq_vm, 0 },
+ 
+ {"vwmul.vv",   0, INSN_CLASS_V,  "Vd,Vt,VsVm", MATCH_VWMULVV, MASK_VWMULVV, match_widen_vd_neq_vs1_neq_vs2_neq_vm, 0 },
+ {"vwmul.vx",   0, INSN_CLASS_V,  "Vd,Vt,sVm", MATCH_VWMULVX, MASK_VWMULVX, match_widen_vd_neq_vs2_neq_vm, 0 },
+@@ -1780,14 +1773,14 @@ const struct riscv_opcode riscv_opcodes[] =
+ {"vwmulsu.vv", 0, INSN_CLASS_V,  "Vd,Vt,VsVm", MATCH_VWMULSUVV, MASK_VWMULSUVV, match_widen_vd_neq_vs1_neq_vs2_neq_vm, 0 },
+ {"vwmulsu.vx", 0, INSN_CLASS_V,  "Vd,Vt,sVm", MATCH_VWMULSUVX, MASK_VWMULSUVX, match_widen_vd_neq_vs2_neq_vm, 0 },
+ 
+-{"vmacc.vv",   0, INSN_CLASS_V,  "Vd,Vs,VtVm", MATCH_VMACCVV, MASK_VMACCVV, match_opcode, 0},
+-{"vmacc.vx",   0, INSN_CLASS_V,  "Vd,s,VtVm", MATCH_VMACCVX, MASK_VMACCVX, match_opcode, 0},
+-{"vnmsac.vv",  0, INSN_CLASS_V,  "Vd,Vs,VtVm", MATCH_VNMSACVV, MASK_VNMSACVV, match_opcode, 0},
+-{"vnmsac.vx",  0, INSN_CLASS_V,  "Vd,s,VtVm", MATCH_VNMSACVX, MASK_VNMSACVX, match_opcode, 0},
+-{"vmadd.vv",   0, INSN_CLASS_V,  "Vd,Vs,VtVm", MATCH_VMADDVV, MASK_VMADDVV, match_opcode, 0},
+-{"vmadd.vx",   0, INSN_CLASS_V,  "Vd,s,VtVm", MATCH_VMADDVX, MASK_VMADDVX, match_opcode, 0},
+-{"vnmsub.vv",  0, INSN_CLASS_V,  "Vd,Vs,VtVm", MATCH_VNMSUBVV, MASK_VNMSUBVV, match_opcode, 0},
+-{"vnmsub.vx",  0, INSN_CLASS_V,  "Vd,s,VtVm", MATCH_VNMSUBVX, MASK_VNMSUBVX, match_opcode, 0},
++{"vmacc.vv",   0, INSN_CLASS_V,  "Vd,Vs,VtVm", MATCH_VMACCVV, MASK_VMACCVV, match_vd_neq_vm, 0},
++{"vmacc.vx",   0, INSN_CLASS_V,  "Vd,s,VtVm", MATCH_VMACCVX, MASK_VMACCVX, match_vd_neq_vm, 0},
++{"vnmsac.vv",  0, INSN_CLASS_V,  "Vd,Vs,VtVm", MATCH_VNMSACVV, MASK_VNMSACVV, match_vd_neq_vm, 0},
++{"vnmsac.vx",  0, INSN_CLASS_V,  "Vd,s,VtVm", MATCH_VNMSACVX, MASK_VNMSACVX, match_vd_neq_vm, 0},
++{"vmadd.vv",   0, INSN_CLASS_V,  "Vd,Vs,VtVm", MATCH_VMADDVV, MASK_VMADDVV, match_vd_neq_vm, 0},
++{"vmadd.vx",   0, INSN_CLASS_V,  "Vd,s,VtVm", MATCH_VMADDVX, MASK_VMADDVX, match_vd_neq_vm, 0},
++{"vnmsub.vv",  0, INSN_CLASS_V,  "Vd,Vs,VtVm", MATCH_VNMSUBVV, MASK_VNMSUBVV, match_vd_neq_vm, 0},
++{"vnmsub.vx",  0, INSN_CLASS_V,  "Vd,s,VtVm", MATCH_VNMSUBVX, MASK_VNMSUBVX, match_vd_neq_vm, 0},
+ 
+ {"vwmaccu.vv",  0, INSN_CLASS_V,  "Vd,Vs,VtVm", MATCH_VWMACCUVV, MASK_VWMACCUVV, match_widen_vd_neq_vs1_neq_vs2_neq_vm, 0},
+ {"vwmaccu.vx",  0, INSN_CLASS_V,  "Vd,s,VtVm", MATCH_VWMACCUVX, MASK_VWMACCUVX, match_widen_vd_neq_vs2_neq_vm, 0},
+@@ -1805,14 +1798,14 @@ const struct riscv_opcode riscv_opcodes[] =
+ {"vqmaccsu.vx", 0, INSN_CLASS_V_AND_ZVQMAC,  "Vd,s,VtVm",  MATCH_VQMACCSUVX, MASK_VQMACCSUVX, match_quad_vd_neq_vs2_neq_vm, 0},
+ {"vqmaccus.vx", 0, INSN_CLASS_V_AND_ZVQMAC,  "Vd,s,VtVm",  MATCH_VQMACCUSVX, MASK_VQMACCUSVX, match_quad_vd_neq_vs2_neq_vm, 0},
+ 
+-{"vdivu.vv",   0, INSN_CLASS_V,  "Vd,Vt,VsVm", MATCH_VDIVUVV, MASK_VDIVUVV, match_opcode, 0 },
+-{"vdivu.vx",   0, INSN_CLASS_V,  "Vd,Vt,sVm", MATCH_VDIVUVX, MASK_VDIVUVX, match_opcode, 0 },
+-{"vdiv.vv",    0, INSN_CLASS_V,  "Vd,Vt,VsVm", MATCH_VDIVVV, MASK_VDIVVV, match_opcode, 0 },
+-{"vdiv.vx",    0, INSN_CLASS_V,  "Vd,Vt,sVm", MATCH_VDIVVX, MASK_VDIVVX, match_opcode, 0 },
+-{"vremu.vv",   0, INSN_CLASS_V,  "Vd,Vt,VsVm", MATCH_VREMUVV, MASK_VREMUVV, match_opcode, 0 },
+-{"vremu.vx",   0, INSN_CLASS_V,  "Vd,Vt,sVm", MATCH_VREMUVX, MASK_VREMUVX, match_opcode, 0 },
+-{"vrem.vv",    0, INSN_CLASS_V,  "Vd,Vt,VsVm", MATCH_VREMVV, MASK_VREMVV, match_opcode, 0 },
+-{"vrem.vx",    0, INSN_CLASS_V,  "Vd,Vt,sVm", MATCH_VREMVX, MASK_VREMVX, match_opcode, 0 },
++{"vdivu.vv",   0, INSN_CLASS_V,  "Vd,Vt,VsVm", MATCH_VDIVUVV, MASK_VDIVUVV, match_vd_neq_vm, 0 },
++{"vdivu.vx",   0, INSN_CLASS_V,  "Vd,Vt,sVm", MATCH_VDIVUVX, MASK_VDIVUVX, match_vd_neq_vm, 0 },
++{"vdiv.vv",    0, INSN_CLASS_V,  "Vd,Vt,VsVm", MATCH_VDIVVV, MASK_VDIVVV, match_vd_neq_vm, 0 },
++{"vdiv.vx",    0, INSN_CLASS_V,  "Vd,Vt,sVm", MATCH_VDIVVX, MASK_VDIVVX, match_vd_neq_vm, 0 },
++{"vremu.vv",   0, INSN_CLASS_V,  "Vd,Vt,VsVm", MATCH_VREMUVV, MASK_VREMUVV, match_vd_neq_vm, 0 },
++{"vremu.vx",   0, INSN_CLASS_V,  "Vd,Vt,sVm", MATCH_VREMUVX, MASK_VREMUVX, match_vd_neq_vm, 0 },
++{"vrem.vv",    0, INSN_CLASS_V,  "Vd,Vt,VsVm", MATCH_VREMVV, MASK_VREMVV, match_vd_neq_vm, 0 },
++{"vrem.vx",    0, INSN_CLASS_V,  "Vd,Vt,sVm", MATCH_VREMVX, MASK_VREMVX, match_vd_neq_vm, 0 },
+ 
+ {"vmerge.vvm", 0, INSN_CLASS_V,  "Vd,Vt,Vs,V0", MATCH_VMERGEVVM, MASK_VMERGEVVM, match_opcode, 0 },
+ {"vmerge.vxm", 0, INSN_CLASS_V,  "Vd,Vt,s,V0", MATCH_VMERGEVXM, MASK_VMERGEVXM, match_opcode, 0 },
+@@ -1822,48 +1815,48 @@ const struct riscv_opcode riscv_opcodes[] =
+ {"vmv.v.x",    0, INSN_CLASS_V,  "Vd,s", MATCH_VMVVX, MASK_VMVVX, match_opcode, 0 },
+ {"vmv.v.i",    0, INSN_CLASS_V,  "Vd,Vi", MATCH_VMVVI, MASK_VMVVI, match_opcode, 0 },
+ 
+-{"vsaddu.vv",  0, INSN_CLASS_V,  "Vd,Vt,VsVm", MATCH_VSADDUVV, MASK_VSADDUVV, match_opcode, 0 },
+-{"vsaddu.vx",  0, INSN_CLASS_V,  "Vd,Vt,sVm", MATCH_VSADDUVX, MASK_VSADDUVX, match_opcode, 0 },
+-{"vsaddu.vi",  0, INSN_CLASS_V,  "Vd,Vt,ViVm", MATCH_VSADDUVI, MASK_VSADDUVI, match_opcode, 0 },
+-{"vsadd.vv",   0, INSN_CLASS_V,  "Vd,Vt,VsVm", MATCH_VSADDVV, MASK_VSADDVV, match_opcode, 0 },
+-{"vsadd.vx",   0, INSN_CLASS_V,  "Vd,Vt,sVm", MATCH_VSADDVX, MASK_VSADDVX, match_opcode, 0 },
+-{"vsadd.vi",   0, INSN_CLASS_V,  "Vd,Vt,ViVm", MATCH_VSADDVI, MASK_VSADDVI, match_opcode, 0 },
+-{"vssubu.vv",  0, INSN_CLASS_V,  "Vd,Vt,VsVm", MATCH_VSSUBUVV, MASK_VSSUBUVV, match_opcode, 0 },
+-{"vssubu.vx",  0, INSN_CLASS_V,  "Vd,Vt,sVm", MATCH_VSSUBUVX, MASK_VSSUBUVX, match_opcode, 0 },
+-{"vssub.vv",   0, INSN_CLASS_V,  "Vd,Vt,VsVm", MATCH_VSSUBVV, MASK_VSSUBVV, match_opcode, 0 },
+-{"vssub.vx",   0, INSN_CLASS_V,  "Vd,Vt,sVm", MATCH_VSSUBVX, MASK_VSSUBVX, match_opcode, 0 },
+-
+-{"vaaddu.vv",  0, INSN_CLASS_V,  "Vd,Vt,VsVm", MATCH_VAADDUVV, MASK_VAADDUVV, match_opcode, 0 },
+-{"vaaddu.vx",  0, INSN_CLASS_V,  "Vd,Vt,sVm", MATCH_VAADDUVX, MASK_VAADDUVX, match_opcode, 0 },
+-{"vaadd.vv",   0, INSN_CLASS_V,  "Vd,Vt,VsVm", MATCH_VAADDVV, MASK_VAADDVV, match_opcode, 0 },
+-{"vaadd.vx",   0, INSN_CLASS_V,  "Vd,Vt,sVm", MATCH_VAADDVX, MASK_VAADDVX, match_opcode, 0 },
+-{"vasubu.vv",  0, INSN_CLASS_V,  "Vd,Vt,VsVm", MATCH_VASUBUVV, MASK_VASUBUVV, match_opcode, 0 },
+-{"vasubu.vx",  0, INSN_CLASS_V,  "Vd,Vt,sVm", MATCH_VASUBUVX, MASK_VASUBUVX, match_opcode, 0 },
+-{"vasub.vv",   0, INSN_CLASS_V,  "Vd,Vt,VsVm", MATCH_VASUBVV, MASK_VASUBVV, match_opcode, 0 },
+-{"vasub.vx",   0, INSN_CLASS_V,  "Vd,Vt,sVm", MATCH_VASUBVX, MASK_VASUBVX, match_opcode, 0 },
+-
+-{"vsmul.vv",   0, INSN_CLASS_V,  "Vd,Vt,VsVm", MATCH_VSMULVV, MASK_VSMULVV, match_opcode, 0 },
+-{"vsmul.vx",   0, INSN_CLASS_V,  "Vd,Vt,sVm", MATCH_VSMULVX, MASK_VSMULVX, match_opcode, 0 },
+-
+-{"vssrl.vv",    0, INSN_CLASS_V,  "Vd,Vt,VsVm", MATCH_VSSRLVV, MASK_VSSRLVV, match_opcode, 0 },
+-{"vssrl.vx",    0, INSN_CLASS_V,  "Vd,Vt,sVm", MATCH_VSSRLVX, MASK_VSSRLVX, match_opcode, 0 },
+-{"vssrl.vi",    0, INSN_CLASS_V,  "Vd,Vt,VjVm", MATCH_VSSRLVI, MASK_VSSRLVI, match_opcode, 0 },
+-{"vssra.vv",    0, INSN_CLASS_V,  "Vd,Vt,VsVm", MATCH_VSSRAVV, MASK_VSSRAVV, match_opcode, 0 },
+-{"vssra.vx",    0, INSN_CLASS_V,  "Vd,Vt,sVm", MATCH_VSSRAVX, MASK_VSSRAVX, match_opcode, 0 },
+-{"vssra.vi",    0, INSN_CLASS_V,  "Vd,Vt,VjVm", MATCH_VSSRAVI, MASK_VSSRAVI, match_opcode, 0 },
+-
+-{"vnclipu.wv",   0, INSN_CLASS_V,  "Vd,Vt,VsVm", MATCH_VNCLIPUWV, MASK_VNCLIPUWV, match_narrow_vd_neq_vs2, 0 },
+-{"vnclipu.wx",   0, INSN_CLASS_V,  "Vd,Vt,sVm", MATCH_VNCLIPUWX, MASK_VNCLIPUWX, match_narrow_vd_neq_vs2, 0 },
+-{"vnclipu.wi",   0, INSN_CLASS_V,  "Vd,Vt,VjVm", MATCH_VNCLIPUWI, MASK_VNCLIPUWI, match_narrow_vd_neq_vs2, 0 },
+-{"vnclip.wv",   0, INSN_CLASS_V,  "Vd,Vt,VsVm", MATCH_VNCLIPWV, MASK_VNCLIPWV, match_narrow_vd_neq_vs2, 0 },
+-{"vnclip.wx",   0, INSN_CLASS_V,  "Vd,Vt,sVm", MATCH_VNCLIPWX, MASK_VNCLIPWX, match_narrow_vd_neq_vs2, 0 },
+-{"vnclip.wi",   0, INSN_CLASS_V,  "Vd,Vt,VjVm", MATCH_VNCLIPWI, MASK_VNCLIPWI, match_narrow_vd_neq_vs2, 0 },
+-
+-{"vfadd.vv",   0, INSN_CLASS_V_AND_F, "Vd,Vt,VsVm", MATCH_VFADDVV, MASK_VFADDVV, match_opcode, 0},
+-{"vfadd.vf",   0, INSN_CLASS_V_AND_F, "Vd,Vt,SVm", MATCH_VFADDVF, MASK_VFADDVF, match_opcode, 0},
+-{"vfsub.vv",   0, INSN_CLASS_V_AND_F, "Vd,Vt,VsVm", MATCH_VFSUBVV, MASK_VFSUBVV, match_opcode, 0},
+-{"vfsub.vf",   0, INSN_CLASS_V_AND_F, "Vd,Vt,SVm", MATCH_VFSUBVF, MASK_VFSUBVF, match_opcode, 0},
+-{"vfrsub.vf",  0, INSN_CLASS_V_AND_F, "Vd,Vt,SVm", MATCH_VFRSUBVF, MASK_VFRSUBVF, match_opcode, 0},
++{"vsaddu.vv",  0, INSN_CLASS_V,  "Vd,Vt,VsVm", MATCH_VSADDUVV, MASK_VSADDUVV, match_vd_neq_vm, 0 },
++{"vsaddu.vx",  0, INSN_CLASS_V,  "Vd,Vt,sVm", MATCH_VSADDUVX, MASK_VSADDUVX, match_vd_neq_vm, 0 },
++{"vsaddu.vi",  0, INSN_CLASS_V,  "Vd,Vt,ViVm", MATCH_VSADDUVI, MASK_VSADDUVI, match_vd_neq_vm, 0 },
++{"vsadd.vv",   0, INSN_CLASS_V,  "Vd,Vt,VsVm", MATCH_VSADDVV, MASK_VSADDVV, match_vd_neq_vm, 0 },
++{"vsadd.vx",   0, INSN_CLASS_V,  "Vd,Vt,sVm", MATCH_VSADDVX, MASK_VSADDVX, match_vd_neq_vm, 0 },
++{"vsadd.vi",   0, INSN_CLASS_V,  "Vd,Vt,ViVm", MATCH_VSADDVI, MASK_VSADDVI, match_vd_neq_vm, 0 },
++{"vssubu.vv",  0, INSN_CLASS_V,  "Vd,Vt,VsVm", MATCH_VSSUBUVV, MASK_VSSUBUVV, match_vd_neq_vm, 0 },
++{"vssubu.vx",  0, INSN_CLASS_V,  "Vd,Vt,sVm", MATCH_VSSUBUVX, MASK_VSSUBUVX, match_vd_neq_vm, 0 },
++{"vssub.vv",   0, INSN_CLASS_V,  "Vd,Vt,VsVm", MATCH_VSSUBVV, MASK_VSSUBVV, match_vd_neq_vm, 0 },
++{"vssub.vx",   0, INSN_CLASS_V,  "Vd,Vt,sVm", MATCH_VSSUBVX, MASK_VSSUBVX, match_vd_neq_vm, 0 },
++
++{"vaaddu.vv",  0, INSN_CLASS_V,  "Vd,Vt,VsVm", MATCH_VAADDUVV, MASK_VAADDUVV, match_vd_neq_vm, 0 },
++{"vaaddu.vx",  0, INSN_CLASS_V,  "Vd,Vt,sVm", MATCH_VAADDUVX, MASK_VAADDUVX, match_vd_neq_vm, 0 },
++{"vaadd.vv",   0, INSN_CLASS_V,  "Vd,Vt,VsVm", MATCH_VAADDVV, MASK_VAADDVV, match_vd_neq_vm, 0 },
++{"vaadd.vx",   0, INSN_CLASS_V,  "Vd,Vt,sVm", MATCH_VAADDVX, MASK_VAADDVX, match_vd_neq_vm, 0 },
++{"vasubu.vv",  0, INSN_CLASS_V,  "Vd,Vt,VsVm", MATCH_VASUBUVV, MASK_VASUBUVV, match_vd_neq_vm, 0 },
++{"vasubu.vx",  0, INSN_CLASS_V,  "Vd,Vt,sVm", MATCH_VASUBUVX, MASK_VASUBUVX, match_vd_neq_vm, 0 },
++{"vasub.vv",   0, INSN_CLASS_V,  "Vd,Vt,VsVm", MATCH_VASUBVV, MASK_VASUBVV, match_vd_neq_vm, 0 },
++{"vasub.vx",   0, INSN_CLASS_V,  "Vd,Vt,sVm", MATCH_VASUBVX, MASK_VASUBVX, match_vd_neq_vm, 0 },
++
++{"vsmul.vv",   0, INSN_CLASS_V,  "Vd,Vt,VsVm", MATCH_VSMULVV, MASK_VSMULVV, match_vd_neq_vm, 0 },
++{"vsmul.vx",   0, INSN_CLASS_V,  "Vd,Vt,sVm", MATCH_VSMULVX, MASK_VSMULVX, match_vd_neq_vm, 0 },
++
++{"vssrl.vv",    0, INSN_CLASS_V,  "Vd,Vt,VsVm", MATCH_VSSRLVV, MASK_VSSRLVV, match_vd_neq_vm, 0 },
++{"vssrl.vx",    0, INSN_CLASS_V,  "Vd,Vt,sVm", MATCH_VSSRLVX, MASK_VSSRLVX, match_vd_neq_vm, 0 },
++{"vssrl.vi",    0, INSN_CLASS_V,  "Vd,Vt,VjVm", MATCH_VSSRLVI, MASK_VSSRLVI, match_vd_neq_vm, 0 },
++{"vssra.vv",    0, INSN_CLASS_V,  "Vd,Vt,VsVm", MATCH_VSSRAVV, MASK_VSSRAVV, match_vd_neq_vm, 0 },
++{"vssra.vx",    0, INSN_CLASS_V,  "Vd,Vt,sVm", MATCH_VSSRAVX, MASK_VSSRAVX, match_vd_neq_vm, 0 },
++{"vssra.vi",    0, INSN_CLASS_V,  "Vd,Vt,VjVm", MATCH_VSSRAVI, MASK_VSSRAVI, match_vd_neq_vm, 0 },
++
++{"vnclipu.wv",   0, INSN_CLASS_V,  "Vd,Vt,VsVm", MATCH_VNCLIPUWV, MASK_VNCLIPUWV, match_narrow_vd_neq_vs2_neq_vm, 0 },
++{"vnclipu.wx",   0, INSN_CLASS_V,  "Vd,Vt,sVm", MATCH_VNCLIPUWX, MASK_VNCLIPUWX, match_narrow_vd_neq_vs2_neq_vm, 0 },
++{"vnclipu.wi",   0, INSN_CLASS_V,  "Vd,Vt,VjVm", MATCH_VNCLIPUWI, MASK_VNCLIPUWI, match_narrow_vd_neq_vs2_neq_vm, 0 },
++{"vnclip.wv",   0, INSN_CLASS_V,  "Vd,Vt,VsVm", MATCH_VNCLIPWV, MASK_VNCLIPWV, match_narrow_vd_neq_vs2_neq_vm, 0 },
++{"vnclip.wx",   0, INSN_CLASS_V,  "Vd,Vt,sVm", MATCH_VNCLIPWX, MASK_VNCLIPWX, match_narrow_vd_neq_vs2_neq_vm, 0 },
++{"vnclip.wi",   0, INSN_CLASS_V,  "Vd,Vt,VjVm", MATCH_VNCLIPWI, MASK_VNCLIPWI, match_narrow_vd_neq_vs2_neq_vm, 0 },
++
++{"vfadd.vv",   0, INSN_CLASS_V_AND_F, "Vd,Vt,VsVm", MATCH_VFADDVV, MASK_VFADDVV, match_vd_neq_vm, 0},
++{"vfadd.vf",   0, INSN_CLASS_V_AND_F, "Vd,Vt,SVm", MATCH_VFADDVF, MASK_VFADDVF, match_vd_neq_vm, 0},
++{"vfsub.vv",   0, INSN_CLASS_V_AND_F, "Vd,Vt,VsVm", MATCH_VFSUBVV, MASK_VFSUBVV, match_vd_neq_vm, 0},
++{"vfsub.vf",   0, INSN_CLASS_V_AND_F, "Vd,Vt,SVm", MATCH_VFSUBVF, MASK_VFSUBVF, match_vd_neq_vm, 0},
++{"vfrsub.vf",  0, INSN_CLASS_V_AND_F, "Vd,Vt,SVm", MATCH_VFRSUBVF, MASK_VFRSUBVF, match_vd_neq_vm, 0},
+ 
+ {"vfwadd.vv",   0, INSN_CLASS_V_AND_F, "Vd,Vt,VsVm", MATCH_VFWADDVV, MASK_VFWADDVV, match_widen_vd_neq_vs1_neq_vs2_neq_vm, 0},
+ {"vfwadd.vf",   0, INSN_CLASS_V_AND_F, "Vd,Vt,SVm", MATCH_VFWADDVF, MASK_VFWADDVF, match_widen_vd_neq_vs2_neq_vm, 0},
+@@ -1874,31 +1867,31 @@ const struct riscv_opcode riscv_opcodes[] =
+ {"vfwsub.wv",   0, INSN_CLASS_V_AND_F, "Vd,Vt,VsVm", MATCH_VFWSUBWV, MASK_VFWSUBWV, match_widen_vd_neq_vs1_neq_vm, 0},
+ {"vfwsub.wf",   0, INSN_CLASS_V_AND_F, "Vd,Vt,SVm", MATCH_VFWSUBWF, MASK_VFWSUBWF, match_widen_vd_neq_vm, 0},
+ 
+-{"vfmul.vv",   0, INSN_CLASS_V_AND_F, "Vd,Vt,VsVm", MATCH_VFMULVV, MASK_VFMULVV, match_opcode, 0},
+-{"vfmul.vf",   0, INSN_CLASS_V_AND_F, "Vd,Vt,SVm", MATCH_VFMULVF, MASK_VFMULVF, match_opcode, 0},
+-{"vfdiv.vv",   0, INSN_CLASS_V_AND_F, "Vd,Vt,VsVm", MATCH_VFDIVVV, MASK_VFDIVVV, match_opcode, 0},
+-{"vfdiv.vf",   0, INSN_CLASS_V_AND_F, "Vd,Vt,SVm", MATCH_VFDIVVF, MASK_VFDIVVF, match_opcode, 0},
+-{"vfrdiv.vf",  0, INSN_CLASS_V_AND_F, "Vd,Vt,SVm", MATCH_VFRDIVVF, MASK_VFRDIVVF, match_opcode, 0},
++{"vfmul.vv",   0, INSN_CLASS_V_AND_F, "Vd,Vt,VsVm", MATCH_VFMULVV, MASK_VFMULVV, match_vd_neq_vm, 0},
++{"vfmul.vf",   0, INSN_CLASS_V_AND_F, "Vd,Vt,SVm", MATCH_VFMULVF, MASK_VFMULVF, match_vd_neq_vm, 0},
++{"vfdiv.vv",   0, INSN_CLASS_V_AND_F, "Vd,Vt,VsVm", MATCH_VFDIVVV, MASK_VFDIVVV, match_vd_neq_vm, 0},
++{"vfdiv.vf",   0, INSN_CLASS_V_AND_F, "Vd,Vt,SVm", MATCH_VFDIVVF, MASK_VFDIVVF, match_vd_neq_vm, 0},
++{"vfrdiv.vf",  0, INSN_CLASS_V_AND_F, "Vd,Vt,SVm", MATCH_VFRDIVVF, MASK_VFRDIVVF, match_vd_neq_vm, 0},
+ 
+ {"vfwmul.vv",  0, INSN_CLASS_V_AND_F, "Vd,Vt,VsVm", MATCH_VFWMULVV, MASK_VFWMULVV, match_widen_vd_neq_vs1_neq_vs2_neq_vm, 0},
+ {"vfwmul.vf",  0, INSN_CLASS_V_AND_F, "Vd,Vt,SVm", MATCH_VFWMULVF, MASK_VFWMULVF, match_widen_vd_neq_vs2_neq_vm, 0},
+ 
+-{"vfmadd.vv",  0, INSN_CLASS_V_AND_F, "Vd,Vs,VtVm", MATCH_VFMADDVV, MASK_VFMADDVV, match_opcode, 0},
+-{"vfmadd.vf",  0, INSN_CLASS_V_AND_F, "Vd,S,VtVm", MATCH_VFMADDVF, MASK_VFMADDVF, match_opcode, 0},
+-{"vfnmadd.vv", 0, INSN_CLASS_V_AND_F, "Vd,Vs,VtVm", MATCH_VFNMADDVV, MASK_VFNMADDVV, match_opcode, 0},
+-{"vfnmadd.vf", 0, INSN_CLASS_V_AND_F, "Vd,S,VtVm", MATCH_VFNMADDVF, MASK_VFNMADDVF, match_opcode, 0},
+-{"vfmsub.vv",  0, INSN_CLASS_V_AND_F, "Vd,Vs,VtVm", MATCH_VFMSUBVV, MASK_VFMSUBVV, match_opcode, 0},
+-{"vfmsub.vf",  0, INSN_CLASS_V_AND_F, "Vd,S,VtVm", MATCH_VFMSUBVF, MASK_VFMSUBVF, match_opcode, 0},
+-{"vfnmsub.vv", 0, INSN_CLASS_V_AND_F, "Vd,Vs,VtVm", MATCH_VFNMSUBVV, MASK_VFNMSUBVV, match_opcode, 0},
+-{"vfnmsub.vf", 0, INSN_CLASS_V_AND_F, "Vd,S,VtVm", MATCH_VFNMSUBVF, MASK_VFNMSUBVF, match_opcode, 0},
+-{"vfmacc.vv",  0, INSN_CLASS_V_AND_F, "Vd,Vs,VtVm", MATCH_VFMACCVV, MASK_VFMACCVV, match_opcode, 0},
+-{"vfmacc.vf",  0, INSN_CLASS_V_AND_F, "Vd,S,VtVm", MATCH_VFMACCVF, MASK_VFMACCVF, match_opcode, 0},
+-{"vfnmacc.vv", 0, INSN_CLASS_V_AND_F, "Vd,Vs,VtVm", MATCH_VFNMACCVV, MASK_VFNMACCVV, match_opcode, 0},
+-{"vfnmacc.vf", 0, INSN_CLASS_V_AND_F, "Vd,S,VtVm", MATCH_VFNMACCVF, MASK_VFNMACCVF, match_opcode, 0},
+-{"vfmsac.vv",  0, INSN_CLASS_V_AND_F, "Vd,Vs,VtVm", MATCH_VFMSACVV, MASK_VFMSACVV, match_opcode, 0},
+-{"vfmsac.vf",  0, INSN_CLASS_V_AND_F, "Vd,S,VtVm", MATCH_VFMSACVF, MASK_VFMSACVF, match_opcode, 0},
+-{"vfnmsac.vv", 0, INSN_CLASS_V_AND_F, "Vd,Vs,VtVm", MATCH_VFNMSACVV, MASK_VFNMSACVV, match_opcode, 0},
+-{"vfnmsac.vf", 0, INSN_CLASS_V_AND_F, "Vd,S,VtVm", MATCH_VFNMSACVF, MASK_VFNMSACVF, match_opcode, 0},
++{"vfmadd.vv",  0, INSN_CLASS_V_AND_F, "Vd,Vs,VtVm", MATCH_VFMADDVV, MASK_VFMADDVV, match_vd_neq_vm, 0},
++{"vfmadd.vf",  0, INSN_CLASS_V_AND_F, "Vd,S,VtVm", MATCH_VFMADDVF, MASK_VFMADDVF, match_vd_neq_vm, 0},
++{"vfnmadd.vv", 0, INSN_CLASS_V_AND_F, "Vd,Vs,VtVm", MATCH_VFNMADDVV, MASK_VFNMADDVV, match_vd_neq_vm, 0},
++{"vfnmadd.vf", 0, INSN_CLASS_V_AND_F, "Vd,S,VtVm", MATCH_VFNMADDVF, MASK_VFNMADDVF, match_vd_neq_vm, 0},
++{"vfmsub.vv",  0, INSN_CLASS_V_AND_F, "Vd,Vs,VtVm", MATCH_VFMSUBVV, MASK_VFMSUBVV, match_vd_neq_vm, 0},
++{"vfmsub.vf",  0, INSN_CLASS_V_AND_F, "Vd,S,VtVm", MATCH_VFMSUBVF, MASK_VFMSUBVF, match_vd_neq_vm, 0},
++{"vfnmsub.vv", 0, INSN_CLASS_V_AND_F, "Vd,Vs,VtVm", MATCH_VFNMSUBVV, MASK_VFNMSUBVV, match_vd_neq_vm, 0},
++{"vfnmsub.vf", 0, INSN_CLASS_V_AND_F, "Vd,S,VtVm", MATCH_VFNMSUBVF, MASK_VFNMSUBVF, match_vd_neq_vm, 0},
++{"vfmacc.vv",  0, INSN_CLASS_V_AND_F, "Vd,Vs,VtVm", MATCH_VFMACCVV, MASK_VFMACCVV, match_vd_neq_vm, 0},
++{"vfmacc.vf",  0, INSN_CLASS_V_AND_F, "Vd,S,VtVm", MATCH_VFMACCVF, MASK_VFMACCVF, match_vd_neq_vm, 0},
++{"vfnmacc.vv", 0, INSN_CLASS_V_AND_F, "Vd,Vs,VtVm", MATCH_VFNMACCVV, MASK_VFNMACCVV, match_vd_neq_vm, 0},
++{"vfnmacc.vf", 0, INSN_CLASS_V_AND_F, "Vd,S,VtVm", MATCH_VFNMACCVF, MASK_VFNMACCVF, match_vd_neq_vm, 0},
++{"vfmsac.vv",  0, INSN_CLASS_V_AND_F, "Vd,Vs,VtVm", MATCH_VFMSACVV, MASK_VFMSACVV, match_vd_neq_vm, 0},
++{"vfmsac.vf",  0, INSN_CLASS_V_AND_F, "Vd,S,VtVm", MATCH_VFMSACVF, MASK_VFMSACVF, match_vd_neq_vm, 0},
++{"vfnmsac.vv", 0, INSN_CLASS_V_AND_F, "Vd,Vs,VtVm", MATCH_VFNMSACVV, MASK_VFNMSACVV, match_vd_neq_vm, 0},
++{"vfnmsac.vf", 0, INSN_CLASS_V_AND_F, "Vd,S,VtVm", MATCH_VFNMSACVF, MASK_VFNMSACVF, match_vd_neq_vm, 0},
+ 
+ {"vfwmacc.vv",  0, INSN_CLASS_V_AND_F, "Vd,Vs,VtVm", MATCH_VFWMACCVV, MASK_VFWMACCVV, match_widen_vd_neq_vs1_neq_vs2_neq_vm, 0},
+ {"vfwmacc.vf",  0, INSN_CLASS_V_AND_F, "Vd,S,VtVm", MATCH_VFWMACCVF, MASK_VFWMACCVF, match_widen_vd_neq_vs2_neq_vm, 0},
+@@ -1909,22 +1902,22 @@ const struct riscv_opcode riscv_opcodes[] =
+ {"vfwnmsac.vv", 0, INSN_CLASS_V_AND_F, "Vd,Vs,VtVm", MATCH_VFWNMSACVV, MASK_VFWNMSACVV, match_widen_vd_neq_vs1_neq_vs2_neq_vm, 0},
+ {"vfwnmsac.vf", 0, INSN_CLASS_V_AND_F, "Vd,S,VtVm", MATCH_VFWNMSACVF, MASK_VFWNMSACVF, match_widen_vd_neq_vs2_neq_vm, 0},
+ 
+-{"vfsqrt.v",   0, INSN_CLASS_V_AND_F, "Vd,VtVm", MATCH_VFSQRTV, MASK_VFSQRTV, match_opcode, 0},
+-{"vfrsqrte7.v",0, INSN_CLASS_V_AND_F, "Vd,VtVm", MATCH_VFRSQRTE7V, MASK_VFRSQRTE7V, match_opcode, 0},
+-{"vfrece7.v",  0, INSN_CLASS_V_AND_F, "Vd,VtVm", MATCH_VFRECE7V, MASK_VFRECE7V, match_opcode, 0},
+-{"vfclass.v",  0, INSN_CLASS_V_AND_F, "Vd,VtVm", MATCH_VFCLASSV, MASK_VFCLASSV, match_opcode, 0},
++{"vfsqrt.v",   0, INSN_CLASS_V_AND_F, "Vd,VtVm", MATCH_VFSQRTV, MASK_VFSQRTV, match_vd_neq_vm, 0},
++{"vfrsqrte7.v",0, INSN_CLASS_V_AND_F, "Vd,VtVm", MATCH_VFRSQRTE7V, MASK_VFRSQRTE7V, match_vd_neq_vm, 0},
++{"vfrece7.v",  0, INSN_CLASS_V_AND_F, "Vd,VtVm", MATCH_VFRECE7V, MASK_VFRECE7V, match_vd_neq_vm, 0},
++{"vfclass.v",  0, INSN_CLASS_V_AND_F, "Vd,VtVm", MATCH_VFCLASSV, MASK_VFCLASSV, match_vd_neq_vm, 0},
+ 
+-{"vfmin.vv",   0, INSN_CLASS_V_AND_F, "Vd,Vt,VsVm", MATCH_VFMINVV, MASK_VFMINVV, match_opcode, 0},
+-{"vfmin.vf",   0, INSN_CLASS_V_AND_F, "Vd,Vt,SVm", MATCH_VFMINVF, MASK_VFMINVF, match_opcode, 0},
+-{"vfmax.vv",   0, INSN_CLASS_V_AND_F, "Vd,Vt,VsVm", MATCH_VFMAXVV, MASK_VFMAXVV, match_opcode, 0},
+-{"vfmax.vf",   0, INSN_CLASS_V_AND_F, "Vd,Vt,SVm", MATCH_VFMAXVF, MASK_VFMAXVF, match_opcode, 0},
++{"vfmin.vv",   0, INSN_CLASS_V_AND_F, "Vd,Vt,VsVm", MATCH_VFMINVV, MASK_VFMINVV, match_vd_neq_vm, 0},
++{"vfmin.vf",   0, INSN_CLASS_V_AND_F, "Vd,Vt,SVm", MATCH_VFMINVF, MASK_VFMINVF, match_vd_neq_vm, 0},
++{"vfmax.vv",   0, INSN_CLASS_V_AND_F, "Vd,Vt,VsVm", MATCH_VFMAXVV, MASK_VFMAXVV, match_vd_neq_vm, 0},
++{"vfmax.vf",   0, INSN_CLASS_V_AND_F, "Vd,Vt,SVm", MATCH_VFMAXVF, MASK_VFMAXVF, match_vd_neq_vm, 0},
+ 
+-{"vfsgnj.vv",  0, INSN_CLASS_V_AND_F, "Vd,Vt,VsVm", MATCH_VFSGNJVV, MASK_VFSGNJVV, match_opcode, 0},
+-{"vfsgnj.vf",  0, INSN_CLASS_V_AND_F, "Vd,Vt,SVm", MATCH_VFSGNJVF, MASK_VFSGNJVF, match_opcode, 0},
+-{"vfsgnjn.vv", 0, INSN_CLASS_V_AND_F, "Vd,Vt,VsVm", MATCH_VFSGNJNVV, MASK_VFSGNJNVV, match_opcode, 0},
+-{"vfsgnjn.vf", 0, INSN_CLASS_V_AND_F, "Vd,Vt,SVm", MATCH_VFSGNJNVF, MASK_VFSGNJNVF, match_opcode, 0},
+-{"vfsgnjx.vv", 0, INSN_CLASS_V_AND_F, "Vd,Vt,VsVm", MATCH_VFSGNJXVV, MASK_VFSGNJXVV, match_opcode, 0},
+-{"vfsgnjx.vf", 0, INSN_CLASS_V_AND_F, "Vd,Vt,SVm", MATCH_VFSGNJXVF, MASK_VFSGNJXVF, match_opcode, 0},
++{"vfsgnj.vv",  0, INSN_CLASS_V_AND_F, "Vd,Vt,VsVm", MATCH_VFSGNJVV, MASK_VFSGNJVV, match_vd_neq_vm, 0},
++{"vfsgnj.vf",  0, INSN_CLASS_V_AND_F, "Vd,Vt,SVm", MATCH_VFSGNJVF, MASK_VFSGNJVF, match_vd_neq_vm, 0},
++{"vfsgnjn.vv", 0, INSN_CLASS_V_AND_F, "Vd,Vt,VsVm", MATCH_VFSGNJNVV, MASK_VFSGNJNVV, match_vd_neq_vm, 0},
++{"vfsgnjn.vf", 0, INSN_CLASS_V_AND_F, "Vd,Vt,SVm", MATCH_VFSGNJNVF, MASK_VFSGNJNVF, match_vd_neq_vm, 0},
++{"vfsgnjx.vv", 0, INSN_CLASS_V_AND_F, "Vd,Vt,VsVm", MATCH_VFSGNJXVV, MASK_VFSGNJXVV, match_vd_neq_vm, 0},
++{"vfsgnjx.vf", 0, INSN_CLASS_V_AND_F, "Vd,Vt,SVm", MATCH_VFSGNJXVF, MASK_VFSGNJXVF, match_vd_neq_vm, 0},
+ 
+ {"vmfeq.vv",   0, INSN_CLASS_V_AND_F, "Vd,Vt,VsVm", MATCH_VMFEQVV, MASK_VMFEQVV, match_opcode, 0},
+ {"vmfeq.vf",   0, INSN_CLASS_V_AND_F, "Vd,Vt,SVm", MATCH_VMFEQVF, MASK_VMFEQVF, match_opcode, 0},
+@@ -1944,12 +1937,12 @@ const struct riscv_opcode riscv_opcodes[] =
+ {"vfmerge.vfm",0, INSN_CLASS_V_AND_F, "Vd,Vt,S,V0", MATCH_VFMERGEVFM, MASK_VFMERGEVFM, match_opcode, 0},
+ {"vfmv.v.f",   0, INSN_CLASS_V_AND_F, "Vd,S", MATCH_VFMVVF, MASK_VFMVVF, match_opcode, 0 },
+ 
+-{"vfcvt.xu.f.v",     0, INSN_CLASS_V_AND_F, "Vd,VtVm", MATCH_VFCVTXUFV, MASK_VFCVTXUFV, match_opcode, 0},
+-{"vfcvt.x.f.v",      0, INSN_CLASS_V_AND_F, "Vd,VtVm", MATCH_VFCVTXFV, MASK_VFCVTXFV, match_opcode, 0},
+-{"vfcvt.rtz.xu.f.v", 0, INSN_CLASS_V_AND_F, "Vd,VtVm", MATCH_VFCVTRTZXUFV, MASK_VFCVTRTZXUFV, match_opcode, 0},
+-{"vfcvt.rtz.x.f.v",  0, INSN_CLASS_V_AND_F, "Vd,VtVm", MATCH_VFCVTRTZXFV, MASK_VFCVTRTZXFV, match_opcode, 0},
+-{"vfcvt.f.xu.v",     0, INSN_CLASS_V_AND_F, "Vd,VtVm", MATCH_VFCVTFXUV, MASK_VFCVTFXUV, match_opcode, 0},
+-{"vfcvt.f.x.v",      0, INSN_CLASS_V_AND_F, "Vd,VtVm", MATCH_VFCVTFXV, MASK_VFCVTFXV, match_opcode, 0},
++{"vfcvt.xu.f.v",     0, INSN_CLASS_V_AND_F, "Vd,VtVm", MATCH_VFCVTXUFV, MASK_VFCVTXUFV, match_vd_neq_vm, 0},
++{"vfcvt.x.f.v",      0, INSN_CLASS_V_AND_F, "Vd,VtVm", MATCH_VFCVTXFV, MASK_VFCVTXFV, match_vd_neq_vm, 0},
++{"vfcvt.rtz.xu.f.v", 0, INSN_CLASS_V_AND_F, "Vd,VtVm", MATCH_VFCVTRTZXUFV, MASK_VFCVTRTZXUFV, match_vd_neq_vm, 0},
++{"vfcvt.rtz.x.f.v",  0, INSN_CLASS_V_AND_F, "Vd,VtVm", MATCH_VFCVTRTZXFV, MASK_VFCVTRTZXFV, match_vd_neq_vm, 0},
++{"vfcvt.f.xu.v",     0, INSN_CLASS_V_AND_F, "Vd,VtVm", MATCH_VFCVTFXUV, MASK_VFCVTFXUV, match_vd_neq_vm, 0},
++{"vfcvt.f.x.v",      0, INSN_CLASS_V_AND_F, "Vd,VtVm", MATCH_VFCVTFXV, MASK_VFCVTFXV, match_vd_neq_vm, 0},
+ 
+ {"vfwcvt.xu.f.v",     0, INSN_CLASS_V_AND_F, "Vd,VtVm", MATCH_VFWCVTXUFV, MASK_VFWCVTXUFV, match_widen_vd_neq_vs2_neq_vm, 0},
+ {"vfwcvt.x.f.v",      0, INSN_CLASS_V_AND_F, "Vd,VtVm", MATCH_VFWCVTXFV, MASK_VFWCVTXFV, match_widen_vd_neq_vs2_neq_vm, 0},
+@@ -1959,14 +1952,14 @@ const struct riscv_opcode riscv_opcodes[] =
+ {"vfwcvt.f.x.v",      0, INSN_CLASS_V_AND_F, "Vd,VtVm", MATCH_VFWCVTFXV, MASK_VFWCVTFXV, match_widen_vd_neq_vs2_neq_vm, 0},
+ {"vfwcvt.f.f.v",      0, INSN_CLASS_V_AND_F, "Vd,VtVm", MATCH_VFWCVTFFV, MASK_VFWCVTFFV, match_widen_vd_neq_vs2_neq_vm, 0},
+ 
+-{"vfncvt.xu.f.w",     0, INSN_CLASS_V_AND_F, "Vd,VtVm", MATCH_VFNCVTXUFW, MASK_VFNCVTXUFW, match_narrow_vd_neq_vs2, 0},
+-{"vfncvt.x.f.w",      0, INSN_CLASS_V_AND_F, "Vd,VtVm", MATCH_VFNCVTXFW, MASK_VFNCVTXFW, match_narrow_vd_neq_vs2, 0},
+-{"vfncvt.rtz.xu.f.w", 0, INSN_CLASS_V_AND_F, "Vd,VtVm", MATCH_VFNCVTRTZXUFW, MASK_VFNCVTRTZXUFW, match_narrow_vd_neq_vs2, 0},
+-{"vfncvt.rtz.x.f.w",  0, INSN_CLASS_V_AND_F, "Vd,VtVm", MATCH_VFNCVTRTZXFW, MASK_VFNCVTRTZXFW, match_narrow_vd_neq_vs2, 0},
+-{"vfncvt.f.xu.w",     0, INSN_CLASS_V_AND_F, "Vd,VtVm", MATCH_VFNCVTFXUW, MASK_VFNCVTFXUW, match_narrow_vd_neq_vs2, 0},
+-{"vfncvt.f.x.w",      0, INSN_CLASS_V_AND_F, "Vd,VtVm", MATCH_VFNCVTFXW, MASK_VFNCVTFXW, match_narrow_vd_neq_vs2, 0},
+-{"vfncvt.f.f.w",      0, INSN_CLASS_V_AND_F, "Vd,VtVm", MATCH_VFNCVTFFW, MASK_VFNCVTFFW, match_narrow_vd_neq_vs2, 0},
+-{"vfncvt.rod.f.f.w",  0, INSN_CLASS_V_AND_F, "Vd,VtVm", MATCH_VFNCVTRODFFW, MASK_VFNCVTRODFFW, match_narrow_vd_neq_vs2, 0},
++{"vfncvt.xu.f.w",     0, INSN_CLASS_V_AND_F, "Vd,VtVm", MATCH_VFNCVTXUFW, MASK_VFNCVTXUFW, match_narrow_vd_neq_vs2_neq_vm, 0},
++{"vfncvt.x.f.w",      0, INSN_CLASS_V_AND_F, "Vd,VtVm", MATCH_VFNCVTXFW, MASK_VFNCVTXFW, match_narrow_vd_neq_vs2_neq_vm, 0},
++{"vfncvt.rtz.xu.f.w", 0, INSN_CLASS_V_AND_F, "Vd,VtVm", MATCH_VFNCVTRTZXUFW, MASK_VFNCVTRTZXUFW, match_narrow_vd_neq_vs2_neq_vm, 0},
++{"vfncvt.rtz.x.f.w",  0, INSN_CLASS_V_AND_F, "Vd,VtVm", MATCH_VFNCVTRTZXFW, MASK_VFNCVTRTZXFW, match_narrow_vd_neq_vs2_neq_vm, 0},
++{"vfncvt.f.xu.w",     0, INSN_CLASS_V_AND_F, "Vd,VtVm", MATCH_VFNCVTFXUW, MASK_VFNCVTFXUW, match_narrow_vd_neq_vs2_neq_vm, 0},
++{"vfncvt.f.x.w",      0, INSN_CLASS_V_AND_F, "Vd,VtVm", MATCH_VFNCVTFXW, MASK_VFNCVTFXW, match_narrow_vd_neq_vs2_neq_vm, 0},
++{"vfncvt.f.f.w",      0, INSN_CLASS_V_AND_F, "Vd,VtVm", MATCH_VFNCVTFFW, MASK_VFNCVTFFW, match_narrow_vd_neq_vs2_neq_vm, 0},
++{"vfncvt.rod.f.f.w",  0, INSN_CLASS_V_AND_F, "Vd,VtVm", MATCH_VFNCVTRODFFW, MASK_VFNCVTRODFFW, match_narrow_vd_neq_vs2_neq_vm, 0},
+ 
+ {"vredsum.vs", 0, INSN_CLASS_V, "Vd,Vt,VsVm", MATCH_VREDSUMVS, MASK_VREDSUMVS, match_opcode, 0},
+ {"vredmaxu.vs",0, INSN_CLASS_V, "Vd,Vt,VsVm", MATCH_VREDMAXUVS, MASK_VREDMAXUVS, match_opcode, 0},
+@@ -2005,11 +1998,11 @@ const struct riscv_opcode riscv_opcodes[] =
+ 
+ {"vpopc.m",    0, INSN_CLASS_V, "d,VtVm", MATCH_VPOPCM, MASK_VPOPCM, match_opcode, 0},
+ {"vfirst.m",   0, INSN_CLASS_V, "d,VtVm", MATCH_VFIRSTM, MASK_VFIRSTM, match_opcode, 0},
+-{"vmsbf.m",    0, INSN_CLASS_V, "Vd,VtVm", MATCH_VMSBFM, MASK_VMSBFM, match_opcode, 0},
+-{"vmsif.m",    0, INSN_CLASS_V, "Vd,VtVm", MATCH_VMSIFM, MASK_VMSIFM, match_opcode, 0},
+-{"vmsof.m",    0, INSN_CLASS_V, "Vd,VtVm", MATCH_VMSOFM, MASK_VMSOFM, match_opcode, 0},
++{"vmsbf.m",    0, INSN_CLASS_V, "Vd,VtVm", MATCH_VMSBFM, MASK_VMSBFM, match_vd_neq_vm, 0},
++{"vmsif.m",    0, INSN_CLASS_V, "Vd,VtVm", MATCH_VMSIFM, MASK_VMSIFM, match_vd_neq_vm, 0},
++{"vmsof.m",    0, INSN_CLASS_V, "Vd,VtVm", MATCH_VMSOFM, MASK_VMSOFM, match_vd_neq_vm, 0},
+ {"viota.m",    0, INSN_CLASS_V, "Vd,VtVm", MATCH_VIOTAM, MASK_VIOTAM, match_vd_neq_vs2_neq_vm, 0},
+-{"vid.v",      0, INSN_CLASS_V, "VdVm", MATCH_VIDV, MASK_VIDV, match_opcode, 0},
++{"vid.v",      0, INSN_CLASS_V, "VdVm", MATCH_VIDV, MASK_VIDV, match_vd_neq_vm, 0},
+ 
+ {"vmv.x.s",    0, INSN_CLASS_V, "d,Vt", MATCH_VMVXS, MASK_VMVXS, match_opcode, 0},
+ {"vmv.s.x",    0, INSN_CLASS_V, "Vd,s", MATCH_VMVSX, MASK_VMVSX, match_opcode, 0},
+@@ -2017,15 +2010,15 @@ const struct riscv_opcode riscv_opcodes[] =
+ {"vfmv.f.s",   0, INSN_CLASS_V_AND_F, "D,Vt", MATCH_VFMVFS, MASK_VFMVFS, match_opcode, 0},
+ {"vfmv.s.f",   0, INSN_CLASS_V_AND_F, "Vd,S", MATCH_VFMVSF, MASK_VFMVSF, match_opcode, 0},
+ 
+-{"vslideup.vx",0, INSN_CLASS_V, "Vd,Vt,sVm", MATCH_VSLIDEUPVX, MASK_VSLIDEUPVX, match_vd_neq_vs2, 0},
+-{"vslideup.vi",0, INSN_CLASS_V, "Vd,Vt,VjVm", MATCH_VSLIDEUPVI, MASK_VSLIDEUPVI, match_vd_neq_vs2, 0},
+-{"vslidedown.vx",0,INSN_CLASS_V, "Vd,Vt,sVm", MATCH_VSLIDEDOWNVX, MASK_VSLIDEDOWNVX, match_opcode, 0},
+-{"vslidedown.vi",0,INSN_CLASS_V, "Vd,Vt,VjVm", MATCH_VSLIDEDOWNVI, MASK_VSLIDEDOWNVI, match_opcode, 0},
++{"vslideup.vx",0, INSN_CLASS_V, "Vd,Vt,sVm", MATCH_VSLIDEUPVX, MASK_VSLIDEUPVX, match_vd_neq_vs2_neq_vm, 0},
++{"vslideup.vi",0, INSN_CLASS_V, "Vd,Vt,VjVm", MATCH_VSLIDEUPVI, MASK_VSLIDEUPVI, match_vd_neq_vs2_neq_vm, 0},
++{"vslidedown.vx",0,INSN_CLASS_V, "Vd,Vt,sVm", MATCH_VSLIDEDOWNVX, MASK_VSLIDEDOWNVX, match_vd_neq_vm, 0},
++{"vslidedown.vi",0,INSN_CLASS_V, "Vd,Vt,VjVm", MATCH_VSLIDEDOWNVI, MASK_VSLIDEDOWNVI, match_vd_neq_vm, 0},
+ 
+-{"vslide1up.vx",    0, INSN_CLASS_V, "Vd,Vt,sVm", MATCH_VSLIDE1UPVX, MASK_VSLIDE1UPVX, match_vd_neq_vs2, 0},
+-{"vslide1down.vx",  0, INSN_CLASS_V, "Vd,Vt,sVm", MATCH_VSLIDE1DOWNVX, MASK_VSLIDE1DOWNVX, match_opcode, 0},
+-{"vfslide1up.vf",   0, INSN_CLASS_V_AND_F, "Vd,Vt,SVm", MATCH_VFSLIDE1UPVF, MASK_VFSLIDE1UPVF, match_vd_neq_vs2, 0},
+-{"vfslide1down.vf", 0, INSN_CLASS_V_AND_F, "Vd,Vt,SVm", MATCH_VFSLIDE1DOWNVF, MASK_VFSLIDE1DOWNVF, match_opcode, 0},
++{"vslide1up.vx",    0, INSN_CLASS_V, "Vd,Vt,sVm", MATCH_VSLIDE1UPVX, MASK_VSLIDE1UPVX, match_vd_neq_vs2_neq_vm, 0},
++{"vslide1down.vx",  0, INSN_CLASS_V, "Vd,Vt,sVm", MATCH_VSLIDE1DOWNVX, MASK_VSLIDE1DOWNVX, match_vd_neq_vm, 0},
++{"vfslide1up.vf",   0, INSN_CLASS_V_AND_F, "Vd,Vt,SVm", MATCH_VFSLIDE1UPVF, MASK_VFSLIDE1UPVF, match_vd_neq_vs2_neq_vm, 0},
++{"vfslide1down.vf", 0, INSN_CLASS_V_AND_F, "Vd,Vt,SVm", MATCH_VFSLIDE1DOWNVF, MASK_VFSLIDE1DOWNVF, match_vd_neq_vm, 0},
+ 
+ {"vrgather.vv",    0, INSN_CLASS_V, "Vd,Vt,VsVm", MATCH_VRGATHERVV, MASK_VRGATHERVV, match_vd_neq_vs1_neq_vs2_neq_vm, 0},
+ {"vrgather.vx",    0, INSN_CLASS_V, "Vd,Vt,sVm", MATCH_VRGATHERVX, MASK_VRGATHERVX, match_vd_neq_vs2_neq_vm, 0},
+-- 
+2.33.0
+

+ 233 - 0
recipes-devtools/gdb/files/0025-RISC-V-Add-the-missing-constraints-for-VL-nf-R-and-V.patch

@@ -0,0 +1,233 @@
+From 03a170a6d30138901805e77e48c00085573a409a Mon Sep 17 00:00:00 2001
+From: Nelson Chu <nelson.chu@sifive.com>
+Date: Thu, 13 Aug 2020 17:03:26 +0800
+Subject: [PATCH 25/48] RISC-V: Add the missing constraints for VL<nf>R and
+ VS<nf>R.
+
+The destination vector register must be aligned to <nf>.  The <nf>
+is 1, 2, 4, 8 for now.  Besides, under the aligned constraints, it
+is impossible to use the registers that don't exist (number > 31).
+
+	opcodes/
+	* riscv-opc.c (match_vls_nf_rv): New function.  It is used to
+	check the constraints for VL<nf>R and VS<nf>R.
+	(riscv_opcodes): Updated the match_func for VL<nf>R and VS<nf>R.
+
+	gas/
+	* testsuite/gas/riscv/vector-insns-fail-load-store.l: Add the
+	unaligned failed cases for VL<nf>R and VS<nf>R.
+	* testsuite/gas/riscv/vector-insns-fail-load-store.s: Likewise.
+---
+ .../gas/riscv/vector-insns-fail-load-store.l  |  30 +++++
+ .../gas/riscv/vector-insns-fail-load-store.s  |  38 +++++++
+ opcodes/riscv-opc.c                           | 103 ++++++++++--------
+ 3 files changed, 127 insertions(+), 44 deletions(-)
+
+diff --git a/gas/testsuite/gas/riscv/vector-insns-fail-load-store.l b/gas/testsuite/gas/riscv/vector-insns-fail-load-store.l
+index bd04cbb263..406d79e2b2 100644
+--- a/gas/testsuite/gas/riscv/vector-insns-fail-load-store.l
++++ b/gas/testsuite/gas/riscv/vector-insns-fail-load-store.l
+@@ -555,3 +555,33 @@
+ .*Error: illegal operands `vlxseg8ei1024.v v0,\(a0\),v4,v0.t'
+ .*Error: illegal operands `vsxseg8ei1024.v v4,\(a0\),v4'
+ .*Error: illegal operands `vsxseg8ei1024.v v0,\(a0\),v4,v0.t'
++.*Error: illegal operands `vl2r.v v31,\(a0\)'
++.*Error: illegal operands `vl2re8.v v31,\(a0\)'
++.*Error: illegal operands `vl2re16.v v31,\(a0\)'
++.*Error: illegal operands `vl2re32.v v31,\(a0\)'
++.*Error: illegal operands `vl2re64.v v31,\(a0\)'
++.*Error: illegal operands `vl2re128.v v31,\(a0\)'
++.*Error: illegal operands `vl2re256.v v31,\(a0\)'
++.*Error: illegal operands `vl2re512.v v31,\(a0\)'
++.*Error: illegal operands `vl2re1024.v v31,\(a0\)'
++.*Error: illegal operands `vl4r.v v30,\(a0\)'
++.*Error: illegal operands `vl4re8.v v30,\(a0\)'
++.*Error: illegal operands `vl4re16.v v30,\(a0\)'
++.*Error: illegal operands `vl4re32.v v30,\(a0\)'
++.*Error: illegal operands `vl4re64.v v30,\(a0\)'
++.*Error: illegal operands `vl4re128.v v30,\(a0\)'
++.*Error: illegal operands `vl4re256.v v30,\(a0\)'
++.*Error: illegal operands `vl4re512.v v30,\(a0\)'
++.*Error: illegal operands `vl4re1024.v v30,\(a0\)'
++.*Error: illegal operands `vl8r.v v26,\(a0\)'
++.*Error: illegal operands `vl8re8.v v26,\(a0\)'
++.*Error: illegal operands `vl8re16.v v26,\(a0\)'
++.*Error: illegal operands `vl8re32.v v26,\(a0\)'
++.*Error: illegal operands `vl8re64.v v26,\(a0\)'
++.*Error: illegal operands `vl8re128.v v26,\(a0\)'
++.*Error: illegal operands `vl8re256.v v26,\(a0\)'
++.*Error: illegal operands `vl8re512.v v26,\(a0\)'
++.*Error: illegal operands `vl8re1024.v v26,\(a0\)'
++.*Error: illegal operands `vs2r.v v31,\(a0\)'
++.*Error: illegal operands `vs4r.v v30,\(a0\)'
++.*Error: illegal operands `vs8r.v v26,\(a0\)'
+diff --git a/gas/testsuite/gas/riscv/vector-insns-fail-load-store.s b/gas/testsuite/gas/riscv/vector-insns-fail-load-store.s
+index 05f9358aed..e4f1085174 100644
+--- a/gas/testsuite/gas/riscv/vector-insns-fail-load-store.s
++++ b/gas/testsuite/gas/riscv/vector-insns-fail-load-store.s
+@@ -608,3 +608,41 @@
+ 	vlxseg8ei1024.v v0, (a0), v4, v0.t
+ 	vsxseg8ei1024.v v4, (a0), v4
+ 	vsxseg8ei1024.v v0, (a0), v4, v0.t
++
++# Vector Load/Store Whole Register Instructions
++
++	vl1r.v v31, (a0)		# OK
++
++	vl2r.v v31, (a0)		# vd must be aligned to 2
++	vl2re8.v v31, (a0)
++	vl2re16.v v31, (a0)
++	vl2re32.v v31, (a0)
++	vl2re64.v v31, (a0)
++	vl2re128.v v31, (a0)
++	vl2re256.v v31, (a0)
++	vl2re512.v v31, (a0)
++	vl2re1024.v v31, (a0)
++
++	vl4r.v v30, (a0)		# vd must be aligned to 4
++	vl4re8.v v30, (a0)
++	vl4re16.v v30, (a0)
++	vl4re32.v v30, (a0)
++	vl4re64.v v30, (a0)
++	vl4re128.v v30, (a0)
++	vl4re256.v v30, (a0)
++	vl4re512.v v30, (a0)
++	vl4re1024.v v30, (a0)
++
++	vl8r.v v26, (a0)		# vd must be aligned to 8
++	vl8re8.v v26, (a0)
++	vl8re16.v v26, (a0)
++	vl8re32.v v26, (a0)
++	vl8re64.v v26, (a0)
++	vl8re128.v v26, (a0)
++	vl8re256.v v26, (a0)
++	vl8re512.v v26, (a0)
++	vl8re1024.v v26, (a0)
++
++	vs2r.v v31, (a0)		# vs3 must be aligned to 2
++	vs4r.v v30, (a0)		# vs3 must be aligned to 4
++	vs8r.v v26, (a0)		# vs3 must be aligned to 8
+diff --git a/opcodes/riscv-opc.c b/opcodes/riscv-opc.c
+index 58190fd7c9..843b94aa46 100644
+--- a/opcodes/riscv-opc.c
++++ b/opcodes/riscv-opc.c
+@@ -453,6 +453,21 @@ match_vd_neq_vm (const struct riscv_opcode *op,
+   return match_opcode (op, insn, 0);
+ }
+ 
++static int
++match_vls_nf_rv (const struct riscv_opcode *op,
++		 insn_t insn,
++		 int constraints)
++{
++  int vd = (insn & MASK_VD) >> OP_SH_VD;
++  int nf = ((insn & (0x7 << 29) ) >> 29) + 1;
++
++  if (constraints
++      && ((vd % nf) != 0))
++    return 0;
++
++  return match_opcode (op, insn, 0);
++}
++
+ static int
+ match_vmv_nf_rv (const struct riscv_opcode *op,
+ 		 insn_t insn,
+@@ -1543,50 +1558,50 @@ const struct riscv_opcode riscv_opcodes[] =
+ {"vlseg7e1024ff.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s)Vm", MATCH_VLSEG7E1024FFV, MASK_VLSEG7E1024FFV, match_vd_neq_vm, INSN_DREF },
+ {"vlseg8e1024ff.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s)Vm", MATCH_VLSEG8E1024FFV, MASK_VLSEG8E1024FFV, match_vd_neq_vm, INSN_DREF },
+ 
+-{"vl1r.v",      0, INSN_CLASS_V,  "Vd,0(s)", MATCH_VL1RE8V, MASK_VL1RE8V, match_opcode, INSN_DREF|INSN_ALIAS },
+-{"vl1re8.v",    0, INSN_CLASS_V,  "Vd,0(s)", MATCH_VL1RE8V, MASK_VL1RE8V, match_opcode, INSN_DREF },
+-{"vl1re16.v",   0, INSN_CLASS_V,  "Vd,0(s)", MATCH_VL1RE16V, MASK_VL1RE16V, match_opcode, INSN_DREF },
+-{"vl1re32.v",   0, INSN_CLASS_V,  "Vd,0(s)", MATCH_VL1RE32V, MASK_VL1RE32V, match_opcode, INSN_DREF },
+-{"vl1re64.v",   0, INSN_CLASS_V,  "Vd,0(s)", MATCH_VL1RE64V, MASK_VL1RE64V, match_opcode, INSN_DREF },
+-{"vl1re128.v",  0, INSN_CLASS_V,  "Vd,0(s)", MATCH_VL1RE128V, MASK_VL1RE128V, match_opcode, INSN_DREF },
+-{"vl1re256.v",  0, INSN_CLASS_V,  "Vd,0(s)", MATCH_VL1RE256V, MASK_VL1RE256V, match_opcode, INSN_DREF },
+-{"vl1re512.v",  0, INSN_CLASS_V,  "Vd,0(s)", MATCH_VL1RE512V, MASK_VL1RE512V, match_opcode, INSN_DREF },
+-{"vl1re1024.v", 0, INSN_CLASS_V,  "Vd,0(s)", MATCH_VL1RE1024V, MASK_VL1RE1024V, match_opcode, INSN_DREF },
+-
+-{"vl2r.v",      0, INSN_CLASS_V,  "Vd,0(s)", MATCH_VL2RE8V, MASK_VL2RE8V, match_opcode, INSN_DREF|INSN_ALIAS },
+-{"vl2re8.v",    0, INSN_CLASS_V,  "Vd,0(s)", MATCH_VL2RE8V, MASK_VL2RE8V, match_opcode, INSN_DREF },
+-{"vl2re16.v",   0, INSN_CLASS_V,  "Vd,0(s)", MATCH_VL2RE16V, MASK_VL2RE16V, match_opcode, INSN_DREF },
+-{"vl2re32.v",   0, INSN_CLASS_V,  "Vd,0(s)", MATCH_VL2RE32V, MASK_VL2RE32V, match_opcode, INSN_DREF },
+-{"vl2re64.v",   0, INSN_CLASS_V,  "Vd,0(s)", MATCH_VL2RE64V, MASK_VL2RE64V, match_opcode, INSN_DREF },
+-{"vl2re128.v",  0, INSN_CLASS_V,  "Vd,0(s)", MATCH_VL2RE128V, MASK_VL2RE128V, match_opcode, INSN_DREF },
+-{"vl2re256.v",  0, INSN_CLASS_V,  "Vd,0(s)", MATCH_VL2RE256V, MASK_VL2RE256V, match_opcode, INSN_DREF },
+-{"vl2re512.v",  0, INSN_CLASS_V,  "Vd,0(s)", MATCH_VL2RE512V, MASK_VL2RE512V, match_opcode, INSN_DREF },
+-{"vl2re1024.v", 0, INSN_CLASS_V,  "Vd,0(s)", MATCH_VL2RE1024V, MASK_VL2RE1024V, match_opcode, INSN_DREF },
+-
+-{"vl4r.v",      0, INSN_CLASS_V,  "Vd,0(s)", MATCH_VL4RE8V, MASK_VL4RE8V, match_opcode, INSN_DREF|INSN_ALIAS },
+-{"vl4re8.v",    0, INSN_CLASS_V,  "Vd,0(s)", MATCH_VL4RE8V, MASK_VL4RE8V, match_opcode, INSN_DREF },
+-{"vl4re16.v",   0, INSN_CLASS_V,  "Vd,0(s)", MATCH_VL4RE16V, MASK_VL4RE16V, match_opcode, INSN_DREF },
+-{"vl4re32.v",   0, INSN_CLASS_V,  "Vd,0(s)", MATCH_VL4RE32V, MASK_VL4RE32V, match_opcode, INSN_DREF },
+-{"vl4re64.v",   0, INSN_CLASS_V,  "Vd,0(s)", MATCH_VL4RE64V, MASK_VL4RE64V, match_opcode, INSN_DREF },
+-{"vl4re128.v",  0, INSN_CLASS_V,  "Vd,0(s)", MATCH_VL4RE128V, MASK_VL4RE128V, match_opcode, INSN_DREF },
+-{"vl4re256.v",  0, INSN_CLASS_V,  "Vd,0(s)", MATCH_VL4RE256V, MASK_VL4RE256V, match_opcode, INSN_DREF },
+-{"vl4re512.v",  0, INSN_CLASS_V,  "Vd,0(s)", MATCH_VL4RE512V, MASK_VL4RE512V, match_opcode, INSN_DREF },
+-{"vl4re1024.v", 0, INSN_CLASS_V,  "Vd,0(s)", MATCH_VL4RE1024V, MASK_VL4RE1024V, match_opcode, INSN_DREF },
+-
+-{"vl8r.v",      0, INSN_CLASS_V,  "Vd,0(s)", MATCH_VL8RE8V, MASK_VL8RE8V, match_opcode, INSN_DREF|INSN_ALIAS },
+-{"vl8re8.v",    0, INSN_CLASS_V,  "Vd,0(s)", MATCH_VL8RE8V, MASK_VL8RE8V, match_opcode, INSN_DREF },
+-{"vl8re16.v",   0, INSN_CLASS_V,  "Vd,0(s)", MATCH_VL8RE16V, MASK_VL8RE16V, match_opcode, INSN_DREF },
+-{"vl8re32.v",   0, INSN_CLASS_V,  "Vd,0(s)", MATCH_VL8RE32V, MASK_VL8RE32V, match_opcode, INSN_DREF },
+-{"vl8re64.v",   0, INSN_CLASS_V,  "Vd,0(s)", MATCH_VL8RE64V, MASK_VL8RE64V, match_opcode, INSN_DREF },
+-{"vl8re128.v",  0, INSN_CLASS_V,  "Vd,0(s)", MATCH_VL8RE128V, MASK_VL8RE128V, match_opcode, INSN_DREF },
+-{"vl8re256.v",  0, INSN_CLASS_V,  "Vd,0(s)", MATCH_VL8RE256V, MASK_VL8RE256V, match_opcode, INSN_DREF },
+-{"vl8re512.v",  0, INSN_CLASS_V,  "Vd,0(s)", MATCH_VL8RE512V, MASK_VL8RE512V, match_opcode, INSN_DREF },
+-{"vl8re1024.v", 0, INSN_CLASS_V,  "Vd,0(s)", MATCH_VL8RE1024V, MASK_VL8RE1024V, match_opcode, INSN_DREF },
+-
+-{"vs1r.v",  0, INSN_CLASS_V,  "Vd,0(s)", MATCH_VS1RV, MASK_VS1RV, match_opcode, INSN_DREF },
+-{"vs2r.v",  0, INSN_CLASS_V,  "Vd,0(s)", MATCH_VS2RV, MASK_VS2RV, match_opcode, INSN_DREF },
+-{"vs4r.v",  0, INSN_CLASS_V,  "Vd,0(s)", MATCH_VS4RV, MASK_VS4RV, match_opcode, INSN_DREF },
+-{"vs8r.v",  0, INSN_CLASS_V,  "Vd,0(s)", MATCH_VS8RV, MASK_VS8RV, match_opcode, INSN_DREF },
++{"vl1r.v",      0, INSN_CLASS_V,  "Vd,0(s)", MATCH_VL1RE8V, MASK_VL1RE8V, match_vls_nf_rv, INSN_DREF|INSN_ALIAS },
++{"vl1re8.v",    0, INSN_CLASS_V,  "Vd,0(s)", MATCH_VL1RE8V, MASK_VL1RE8V, match_vls_nf_rv, INSN_DREF },
++{"vl1re16.v",   0, INSN_CLASS_V,  "Vd,0(s)", MATCH_VL1RE16V, MASK_VL1RE16V, match_vls_nf_rv, INSN_DREF },
++{"vl1re32.v",   0, INSN_CLASS_V,  "Vd,0(s)", MATCH_VL1RE32V, MASK_VL1RE32V, match_vls_nf_rv, INSN_DREF },
++{"vl1re64.v",   0, INSN_CLASS_V,  "Vd,0(s)", MATCH_VL1RE64V, MASK_VL1RE64V, match_vls_nf_rv, INSN_DREF },
++{"vl1re128.v",  0, INSN_CLASS_V,  "Vd,0(s)", MATCH_VL1RE128V, MASK_VL1RE128V, match_vls_nf_rv, INSN_DREF },
++{"vl1re256.v",  0, INSN_CLASS_V,  "Vd,0(s)", MATCH_VL1RE256V, MASK_VL1RE256V, match_vls_nf_rv, INSN_DREF },
++{"vl1re512.v",  0, INSN_CLASS_V,  "Vd,0(s)", MATCH_VL1RE512V, MASK_VL1RE512V, match_vls_nf_rv, INSN_DREF },
++{"vl1re1024.v", 0, INSN_CLASS_V,  "Vd,0(s)", MATCH_VL1RE1024V, MASK_VL1RE1024V, match_vls_nf_rv, INSN_DREF },
++
++{"vl2r.v",      0, INSN_CLASS_V,  "Vd,0(s)", MATCH_VL2RE8V, MASK_VL2RE8V, match_vls_nf_rv, INSN_DREF|INSN_ALIAS },
++{"vl2re8.v",    0, INSN_CLASS_V,  "Vd,0(s)", MATCH_VL2RE8V, MASK_VL2RE8V, match_vls_nf_rv, INSN_DREF },
++{"vl2re16.v",   0, INSN_CLASS_V,  "Vd,0(s)", MATCH_VL2RE16V, MASK_VL2RE16V, match_vls_nf_rv, INSN_DREF },
++{"vl2re32.v",   0, INSN_CLASS_V,  "Vd,0(s)", MATCH_VL2RE32V, MASK_VL2RE32V, match_vls_nf_rv, INSN_DREF },
++{"vl2re64.v",   0, INSN_CLASS_V,  "Vd,0(s)", MATCH_VL2RE64V, MASK_VL2RE64V, match_vls_nf_rv, INSN_DREF },
++{"vl2re128.v",  0, INSN_CLASS_V,  "Vd,0(s)", MATCH_VL2RE128V, MASK_VL2RE128V, match_vls_nf_rv, INSN_DREF },
++{"vl2re256.v",  0, INSN_CLASS_V,  "Vd,0(s)", MATCH_VL2RE256V, MASK_VL2RE256V, match_vls_nf_rv, INSN_DREF },
++{"vl2re512.v",  0, INSN_CLASS_V,  "Vd,0(s)", MATCH_VL2RE512V, MASK_VL2RE512V, match_vls_nf_rv, INSN_DREF },
++{"vl2re1024.v", 0, INSN_CLASS_V,  "Vd,0(s)", MATCH_VL2RE1024V, MASK_VL2RE1024V, match_vls_nf_rv, INSN_DREF },
++
++{"vl4r.v",      0, INSN_CLASS_V,  "Vd,0(s)", MATCH_VL4RE8V, MASK_VL4RE8V, match_vls_nf_rv, INSN_DREF|INSN_ALIAS },
++{"vl4re8.v",    0, INSN_CLASS_V,  "Vd,0(s)", MATCH_VL4RE8V, MASK_VL4RE8V, match_vls_nf_rv, INSN_DREF },
++{"vl4re16.v",   0, INSN_CLASS_V,  "Vd,0(s)", MATCH_VL4RE16V, MASK_VL4RE16V, match_vls_nf_rv, INSN_DREF },
++{"vl4re32.v",   0, INSN_CLASS_V,  "Vd,0(s)", MATCH_VL4RE32V, MASK_VL4RE32V, match_vls_nf_rv, INSN_DREF },
++{"vl4re64.v",   0, INSN_CLASS_V,  "Vd,0(s)", MATCH_VL4RE64V, MASK_VL4RE64V, match_vls_nf_rv, INSN_DREF },
++{"vl4re128.v",  0, INSN_CLASS_V,  "Vd,0(s)", MATCH_VL4RE128V, MASK_VL4RE128V, match_vls_nf_rv, INSN_DREF },
++{"vl4re256.v",  0, INSN_CLASS_V,  "Vd,0(s)", MATCH_VL4RE256V, MASK_VL4RE256V, match_vls_nf_rv, INSN_DREF },
++{"vl4re512.v",  0, INSN_CLASS_V,  "Vd,0(s)", MATCH_VL4RE512V, MASK_VL4RE512V, match_vls_nf_rv, INSN_DREF },
++{"vl4re1024.v", 0, INSN_CLASS_V,  "Vd,0(s)", MATCH_VL4RE1024V, MASK_VL4RE1024V, match_vls_nf_rv, INSN_DREF },
++
++{"vl8r.v",      0, INSN_CLASS_V,  "Vd,0(s)", MATCH_VL8RE8V, MASK_VL8RE8V, match_vls_nf_rv, INSN_DREF|INSN_ALIAS },
++{"vl8re8.v",    0, INSN_CLASS_V,  "Vd,0(s)", MATCH_VL8RE8V, MASK_VL8RE8V, match_vls_nf_rv, INSN_DREF },
++{"vl8re16.v",   0, INSN_CLASS_V,  "Vd,0(s)", MATCH_VL8RE16V, MASK_VL8RE16V, match_vls_nf_rv, INSN_DREF },
++{"vl8re32.v",   0, INSN_CLASS_V,  "Vd,0(s)", MATCH_VL8RE32V, MASK_VL8RE32V, match_vls_nf_rv, INSN_DREF },
++{"vl8re64.v",   0, INSN_CLASS_V,  "Vd,0(s)", MATCH_VL8RE64V, MASK_VL8RE64V, match_vls_nf_rv, INSN_DREF },
++{"vl8re128.v",  0, INSN_CLASS_V,  "Vd,0(s)", MATCH_VL8RE128V, MASK_VL8RE128V, match_vls_nf_rv, INSN_DREF },
++{"vl8re256.v",  0, INSN_CLASS_V,  "Vd,0(s)", MATCH_VL8RE256V, MASK_VL8RE256V, match_vls_nf_rv, INSN_DREF },
++{"vl8re512.v",  0, INSN_CLASS_V,  "Vd,0(s)", MATCH_VL8RE512V, MASK_VL8RE512V, match_vls_nf_rv, INSN_DREF },
++{"vl8re1024.v", 0, INSN_CLASS_V,  "Vd,0(s)", MATCH_VL8RE1024V, MASK_VL8RE1024V, match_vls_nf_rv, INSN_DREF },
++
++{"vs1r.v",  0, INSN_CLASS_V,  "Vd,0(s)", MATCH_VS1RV, MASK_VS1RV, match_vls_nf_rv, INSN_DREF },
++{"vs2r.v",  0, INSN_CLASS_V,  "Vd,0(s)", MATCH_VS2RV, MASK_VS2RV, match_vls_nf_rv, INSN_DREF },
++{"vs4r.v",  0, INSN_CLASS_V,  "Vd,0(s)", MATCH_VS4RV, MASK_VS4RV, match_vls_nf_rv, INSN_DREF },
++{"vs8r.v",  0, INSN_CLASS_V,  "Vd,0(s)", MATCH_VS8RV, MASK_VS8RV, match_vls_nf_rv, INSN_DREF },
+ 
+ {"vamoaddei8.v",   0, INSN_CLASS_V_OR_ZVAMO,  "Ve,0(s),Vt,VfVm", MATCH_VAMOADDEI8V, MASK_VAMOADDEI8V, match_vd_neq_vm, INSN_DREF},
+ {"vamoswapei8.v",  0, INSN_CLASS_V_OR_ZVAMO,  "Ve,0(s),Vt,VfVm", MATCH_VAMOSWAPEI8V, MASK_VAMOSWAPEI8V, match_vd_neq_vm, INSN_DREF},
+-- 
+2.33.0
+

+ 117 - 0
recipes-devtools/gdb/files/0026-RISC-V-Fix-the-constraints-for-vector-mask-and-compr.patch

@@ -0,0 +1,117 @@
+From ba89af6905dd35a3813fd8a12c327c12fb2efddc Mon Sep 17 00:00:00 2001
+From: Nelson Chu <nelson.chu@sifive.com>
+Date: Thu, 13 Aug 2020 17:27:33 +0800
+Subject: [PATCH 26/48] RISC-V: Fix the constraints for vector mask and
+ compress instructions.
+
+Add the missing constraints for vmsbf.m, vmsif.m and vmsof.m.  Their
+destination vector register can not overlap the source register.
+
+Besides, we don't need to check the VM overlap for vcompress.vm, so
+change the match_func from match_vd_neq_vs1_neq_vs2 to
+match_vd_neq_vs1_neq_vs2_neq_vm.
+
+	opcodes/
+	* riscv-opc.c (match_vd_neq_vs1_neq_vs2): New function.  Only
+	check if VD is overlap VS2.
+	(riscv_opcodes): We don't need to check the VM overlap for
+	vcompress.vm, so change the match_func to match_vd_neq_vs1_neq_vs2.
+
+	gas/
+	* testsuite/gas/riscv/vector-insns-fail-mask.l: Add the missing
+	overlap failed cases for vmsbf.m, vmsif.m and vmsof.m.
+	* testsuite/gas/riscv/vector-insns-fail-mask.s: Likewise.
+---
+ .../gas/riscv/vector-insns-fail-mask.l        |  3 +++
+ .../gas/riscv/vector-insns-fail-mask.s        |  3 +++
+ opcodes/riscv-opc.c                           | 25 ++++++++++++++++---
+ 3 files changed, 27 insertions(+), 4 deletions(-)
+
+diff --git a/gas/testsuite/gas/riscv/vector-insns-fail-mask.l b/gas/testsuite/gas/riscv/vector-insns-fail-mask.l
+index 5c4e881489..3b23becc16 100644
+--- a/gas/testsuite/gas/riscv/vector-insns-fail-mask.l
++++ b/gas/testsuite/gas/riscv/vector-insns-fail-mask.l
+@@ -1,6 +1,9 @@
+ .*: Assembler messages:
++.*Error: illegal operands `vmsbf.m v4,v4'
+ .*Error: illegal operands `vmsbf.m v0,v4,v0.t'
++.*Error: illegal operands `vmsif.m v4,v4'
+ .*Error: illegal operands `vmsif.m v0,v4,v0.t'
++.*Error: illegal operands `vmsof.m v4,v4'
+ .*Error: illegal operands `vmsof.m v0,v4,v0.t'
+ .*Error: illegal operands `viota.m v4,v4'
+ .*Error: illegal operands `viota.m v0,v4,v0.t'
+diff --git a/gas/testsuite/gas/riscv/vector-insns-fail-mask.s b/gas/testsuite/gas/riscv/vector-insns-fail-mask.s
+index 580b101c77..99b19f6bdd 100644
+--- a/gas/testsuite/gas/riscv/vector-insns-fail-mask.s
++++ b/gas/testsuite/gas/riscv/vector-insns-fail-mask.s
+@@ -1,13 +1,16 @@
+ # Vector Set-before-first Mask Bit
+ 
++	vmsbf.m v4, v4		# vd overlap vs2
+ 	vmsbf.m v0, v4, v0.t	# vd overlap vm
+ 
+ # Vector Set-including-first Mask Bit
+ 
++	vmsif.m v4, v4		# vd overlap vs2
+ 	vmsif.m v0, v4, v0.t	# vd overlap vm
+ 
+ # Vector Set-only-first Mask Bit
+ 
++	vmsof.m v4, v4		# vd overlap vs2
+ 	vmsof.m v0, v4, v0.t	# vd overlap vm
+ 
+ # Vector Iota Instruction
+diff --git a/opcodes/riscv-opc.c b/opcodes/riscv-opc.c
+index 843b94aa46..2d78218e2b 100644
+--- a/opcodes/riscv-opc.c
++++ b/opcodes/riscv-opc.c
+@@ -398,6 +398,23 @@ match_narrow_vd_neq_vs2_neq_vm (const struct riscv_opcode *op,
+   return match_opcode (op, insn, 0);
+ }
+ 
++static int
++match_vd_neq_vs1_neq_vs2 (const struct riscv_opcode *op,
++			  insn_t insn,
++			  int constraints)
++{
++  int vd = (insn & MASK_VD) >> OP_SH_VD;
++  int vs1 = (insn & MASK_VS1) >> OP_SH_VS1;
++  int vs2 = (insn & MASK_VS2) >> OP_SH_VS2;
++
++  if (constraints
++      && (vs1 == vd
++	  || vs2 == vd))
++    return 0;
++
++  return match_opcode (op, insn, 0);
++}
++
+ static int
+ match_vd_neq_vs1_neq_vs2_neq_vm (const struct riscv_opcode *op,
+ 				 insn_t insn,
+@@ -2013,9 +2030,9 @@ const struct riscv_opcode riscv_opcodes[] =
+ 
+ {"vpopc.m",    0, INSN_CLASS_V, "d,VtVm", MATCH_VPOPCM, MASK_VPOPCM, match_opcode, 0},
+ {"vfirst.m",   0, INSN_CLASS_V, "d,VtVm", MATCH_VFIRSTM, MASK_VFIRSTM, match_opcode, 0},
+-{"vmsbf.m",    0, INSN_CLASS_V, "Vd,VtVm", MATCH_VMSBFM, MASK_VMSBFM, match_vd_neq_vm, 0},
+-{"vmsif.m",    0, INSN_CLASS_V, "Vd,VtVm", MATCH_VMSIFM, MASK_VMSIFM, match_vd_neq_vm, 0},
+-{"vmsof.m",    0, INSN_CLASS_V, "Vd,VtVm", MATCH_VMSOFM, MASK_VMSOFM, match_vd_neq_vm, 0},
++{"vmsbf.m",    0, INSN_CLASS_V, "Vd,VtVm", MATCH_VMSBFM, MASK_VMSBFM, match_vd_neq_vs2_neq_vm, 0},
++{"vmsif.m",    0, INSN_CLASS_V, "Vd,VtVm", MATCH_VMSIFM, MASK_VMSIFM, match_vd_neq_vs2_neq_vm, 0},
++{"vmsof.m",    0, INSN_CLASS_V, "Vd,VtVm", MATCH_VMSOFM, MASK_VMSOFM, match_vd_neq_vs2_neq_vm, 0},
+ {"viota.m",    0, INSN_CLASS_V, "Vd,VtVm", MATCH_VIOTAM, MASK_VIOTAM, match_vd_neq_vs2_neq_vm, 0},
+ {"vid.v",      0, INSN_CLASS_V, "VdVm", MATCH_VIDV, MASK_VIDV, match_vd_neq_vm, 0},
+ 
+@@ -2040,7 +2057,7 @@ const struct riscv_opcode riscv_opcodes[] =
+ {"vrgather.vi",    0, INSN_CLASS_V, "Vd,Vt,VjVm", MATCH_VRGATHERVI, MASK_VRGATHERVI, match_vd_neq_vs2_neq_vm, 0},
+ {"vrgatherei16.vv",0, INSN_CLASS_V, "Vd,Vt,VsVm", MATCH_VRGATHEREI16VV, MASK_VRGATHEREI16VV, match_vd_neq_vs1_neq_vs2_neq_vm, 0},
+ 
+-{"vcompress.vm",0, INSN_CLASS_V, "Vd,Vt,Vs", MATCH_VCOMPRESSVM, MASK_VCOMPRESSVM, match_vd_neq_vs1_neq_vs2_neq_vm, 0},
++{"vcompress.vm",0, INSN_CLASS_V, "Vd,Vt,Vs", MATCH_VCOMPRESSVM, MASK_VCOMPRESSVM, match_vd_neq_vs1_neq_vs2, 0},
+ 
+ {"vmv1r.v",    0, INSN_CLASS_V, "Vd,Vt", MATCH_VMV1RV, MASK_VMV1RV, match_vmv_nf_rv, 0},
+ {"vmv2r.v",    0, INSN_CLASS_V, "Vd,Vt", MATCH_VMV2RV, MASK_VMV2RV, match_vmv_nf_rv, 0},
+-- 
+2.33.0
+

+ 3257 - 0
recipes-devtools/gdb/files/0027-RISC-V-Report-rvv-assembler-constraint-errors-in-det.patch

@@ -0,0 +1,3257 @@
+From 1263f0e6190b7dc9267199d83abacba8e3053eac Mon Sep 17 00:00:00 2001
+From: Nelson Chu <nelson.chu@sifive.com>
+Date: Fri, 14 Aug 2020 14:55:27 +0800
+Subject: [PATCH 27/48] RISC-V: Report rvv assembler constraint errors in
+ detail.
+
+I think it would be helpful if assembler can report more detailed
+errors when parsing instructions.  I tried to improve them before,
+but still have some problems need to be resolved.  In general,
+we can check the constraints when parsing the operands, or in the
+`match_func` when the parsing is done.  However, reporting detailed
+rvv constraints messages in the `match_func` is relatively clear and
+simple without any potential problems.  Besides, most of the rvv
+constraints are checked in their `match_func`, so I only improve
+them for now, and it should be enough to handle most of cases.
+
+	opcodes/
+	* riscv-opc.c (match_*): Add new argument `error` to store
+	different errors.  Only the `match_*` for checking rvv
+	constraints will store the detailed errors.
+	* riscv-dis.c (riscv_disassemble_insn): Updated since the
+	`match_func` is changed.
+
+	gas/
+	* config/tc-riscv.c (riscv_ip):  Reset the error message
+	before parsing the instruction, rather than the parsing is
+	done.  Pass the `error` to `match_func` to store the detailed
+	error messages.
+
+	* testsuite/gas/riscv/vector-insns-fail-load-store.l: Updated.
+	* testsuite/gas/riscv/vector-insns-fail-arith-int.l: Likewise.
+	* testsuite/gas/riscv/vector-insns-fail-arith-fixp.l: Likewise.
+	* testsuite/gas/riscv/vector-insns-fail-arith-floatp.l: Likewise.
+	* testsuite/gas/riscv/vector-insns-fail-arith-widen.l: Likewise.
+	* testsuite/gas/riscv/vector-insns-fail-arith-narrow.l: Likewise.
+	* testsuite/gas/riscv/vector-insns-fail-zvqmac.l: Likewise.
+	* testsuite/gas/riscv/vector-insns-fail-zvamo.l: Likewise.  We can
+	not report the detailed messages when parsing the operands, that is
+	the `Ve` cases here.
+	* testsuite/gas/riscv/vector-insns-fail-mask.: Likewise.
+	* testsuite/gas/riscv/vector-insns-fail-permutation.l: Likewise.
+
+	include/
+	* opcode/riscv.h (struct riscv_opcode): Update since the
+	`match_func` is changed..
+---
+ gas/config/tc-riscv.c                         |    6 +-
+ .../gas/riscv/vector-insns-fail-arith-fixp.l  |   52 +-
+ .../riscv/vector-insns-fail-arith-floatp.l    |   92 +-
+ .../gas/riscv/vector-insns-fail-arith-int.l   |  138 +-
+ .../riscv/vector-insns-fail-arith-narrow.l    |  168 +--
+ .../gas/riscv/vector-insns-fail-arith-widen.l |  504 +++----
+ .../gas/riscv/vector-insns-fail-load-store.l  | 1172 ++++++++---------
+ .../gas/riscv/vector-insns-fail-mask.l        |   18 +-
+ .../gas/riscv/vector-insns-fail-permutation.l |   60 +-
+ .../gas/riscv/vector-insns-fail-zvamo.l       |  144 +-
+ .../gas/riscv/vector-insns-fail-zvqmac.l      |   68 +-
+ include/opcode/riscv.h                        |    2 +-
+ opcodes/riscv-dis.c                           |    2 +-
+ opcodes/riscv-opc.c                           |  346 +++--
+ 14 files changed, 1434 insertions(+), 1338 deletions(-)
+
+diff --git a/gas/config/tc-riscv.c b/gas/config/tc-riscv.c
+index e998890b92..eca9fabb3f 100644
+--- a/gas/config/tc-riscv.c
++++ b/gas/config/tc-riscv.c
+@@ -2058,6 +2058,8 @@ riscv_ip (char *str, struct riscv_cl_insn *ip, expressionS *imm_expr,
+       if (!riscv_multi_subset_supports (insn->insn_class))
+ 	continue;
+ 
++      /* Reset error message of the previous round.  */
++      error = _("illegal operands");
+       create_insn (ip, insn);
+       argnum = 1;
+ 
+@@ -2074,7 +2076,8 @@ riscv_ip (char *str, struct riscv_cl_insn *ip, expressionS *imm_expr,
+ 	      if (insn->pinfo != INSN_MACRO)
+ 		{
+ 		  if (!insn->match_func (insn, ip->insn_opcode,
+-					 riscv_opts.check_constraints))
++					 riscv_opts.check_constraints,
++					 &error))
+ 		    break;
+ 
+ 		  /* For .insn, insn->match and insn->mask are 0.  */
+@@ -2923,7 +2926,6 @@ riscv_ip (char *str, struct riscv_cl_insn *ip, expressionS *imm_expr,
+ 	  break;
+ 	}
+       s = argsStart;
+-      error = _("illegal operands");
+       insn_with_csr = FALSE;
+     }
+ 
+diff --git a/gas/testsuite/gas/riscv/vector-insns-fail-arith-fixp.l b/gas/testsuite/gas/riscv/vector-insns-fail-arith-fixp.l
+index a3c126d8ec..3481174969 100644
+--- a/gas/testsuite/gas/riscv/vector-insns-fail-arith-fixp.l
++++ b/gas/testsuite/gas/riscv/vector-insns-fail-arith-fixp.l
+@@ -1,27 +1,27 @@
+ .*: Assembler messages:
+-.*Error: illegal operands `vsaddu.vv v0,v4,v8,v0.t'
+-.*Error: illegal operands `vsaddu.vx v0,v4,a1,v0.t'
+-.*Error: illegal operands `vsaddu.vi v0,v4,15,v0.t'
+-.*Error: illegal operands `vsadd.vv v0,v4,v8,v0.t'
+-.*Error: illegal operands `vsadd.vx v0,v4,a1,v0.t'
+-.*Error: illegal operands `vsadd.vi v0,v4,15,v0.t'
+-.*Error: illegal operands `vssubu.vv v0,v4,v8,v0.t'
+-.*Error: illegal operands `vssubu.vx v0,v4,a1,v0.t'
+-.*Error: illegal operands `vssub.vv v0,v4,v8,v0.t'
+-.*Error: illegal operands `vssub.vx v0,v4,a1,v0.t'
+-.*Error: illegal operands `vaaddu.vv v0,v4,v8,v0.t'
+-.*Error: illegal operands `vaaddu.vx v0,v4,a1,v0.t'
+-.*Error: illegal operands `vaadd.vv v0,v4,v8,v0.t'
+-.*Error: illegal operands `vaadd.vx v0,v4,a1,v0.t'
+-.*Error: illegal operands `vasubu.vv v0,v4,v8,v0.t'
+-.*Error: illegal operands `vasubu.vx v0,v4,a1,v0.t'
+-.*Error: illegal operands `vasub.vv v0,v4,v8,v0.t'
+-.*Error: illegal operands `vasub.vx v0,v4,a1,v0.t'
+-.*Error: illegal operands `vsmul.vv v0,v4,v8,v0.t'
+-.*Error: illegal operands `vsmul.vx v0,v4,a1,v0.t'
+-.*Error: illegal operands `vssrl.vv v0,v4,v8,v0.t'
+-.*Error: illegal operands `vssrl.vx v0,v4,a1,v0.t'
+-.*Error: illegal operands `vssrl.vi v0,v4,31,v0.t'
+-.*Error: illegal operands `vssra.vv v0,v4,v8,v0.t'
+-.*Error: illegal operands `vssra.vx v0,v4,a1,v0.t'
+-.*Error: illegal operands `vssra.vi v0,v4,31,v0.t'
++.*Error: illegal operands vd cannot overlap vm `vsaddu.vv v0,v4,v8,v0.t'
++.*Error: illegal operands vd cannot overlap vm `vsaddu.vx v0,v4,a1,v0.t'
++.*Error: illegal operands vd cannot overlap vm `vsaddu.vi v0,v4,15,v0.t'
++.*Error: illegal operands vd cannot overlap vm `vsadd.vv v0,v4,v8,v0.t'
++.*Error: illegal operands vd cannot overlap vm `vsadd.vx v0,v4,a1,v0.t'
++.*Error: illegal operands vd cannot overlap vm `vsadd.vi v0,v4,15,v0.t'
++.*Error: illegal operands vd cannot overlap vm `vssubu.vv v0,v4,v8,v0.t'
++.*Error: illegal operands vd cannot overlap vm `vssubu.vx v0,v4,a1,v0.t'
++.*Error: illegal operands vd cannot overlap vm `vssub.vv v0,v4,v8,v0.t'
++.*Error: illegal operands vd cannot overlap vm `vssub.vx v0,v4,a1,v0.t'
++.*Error: illegal operands vd cannot overlap vm `vaaddu.vv v0,v4,v8,v0.t'
++.*Error: illegal operands vd cannot overlap vm `vaaddu.vx v0,v4,a1,v0.t'
++.*Error: illegal operands vd cannot overlap vm `vaadd.vv v0,v4,v8,v0.t'
++.*Error: illegal operands vd cannot overlap vm `vaadd.vx v0,v4,a1,v0.t'
++.*Error: illegal operands vd cannot overlap vm `vasubu.vv v0,v4,v8,v0.t'
++.*Error: illegal operands vd cannot overlap vm `vasubu.vx v0,v4,a1,v0.t'
++.*Error: illegal operands vd cannot overlap vm `vasub.vv v0,v4,v8,v0.t'
++.*Error: illegal operands vd cannot overlap vm `vasub.vx v0,v4,a1,v0.t'
++.*Error: illegal operands vd cannot overlap vm `vsmul.vv v0,v4,v8,v0.t'
++.*Error: illegal operands vd cannot overlap vm `vsmul.vx v0,v4,a1,v0.t'
++.*Error: illegal operands vd cannot overlap vm `vssrl.vv v0,v4,v8,v0.t'
++.*Error: illegal operands vd cannot overlap vm `vssrl.vx v0,v4,a1,v0.t'
++.*Error: illegal operands vd cannot overlap vm `vssrl.vi v0,v4,31,v0.t'
++.*Error: illegal operands vd cannot overlap vm `vssra.vv v0,v4,v8,v0.t'
++.*Error: illegal operands vd cannot overlap vm `vssra.vx v0,v4,a1,v0.t'
++.*Error: illegal operands vd cannot overlap vm `vssra.vi v0,v4,31,v0.t'
+diff --git a/gas/testsuite/gas/riscv/vector-insns-fail-arith-floatp.l b/gas/testsuite/gas/riscv/vector-insns-fail-arith-floatp.l
+index 0fc28a82d7..c55c7d24cd 100644
+--- a/gas/testsuite/gas/riscv/vector-insns-fail-arith-floatp.l
++++ b/gas/testsuite/gas/riscv/vector-insns-fail-arith-floatp.l
+@@ -1,47 +1,47 @@
+ .*: Assembler messages:
+-.*Error: illegal operands `vfadd.vv v0,v4,v8,v0.t'
+-.*Error: illegal operands `vfadd.vf v0,v4,fa1,v0.t'
+-.*Error: illegal operands `vfsub.vv v0,v4,v8,v0.t'
+-.*Error: illegal operands `vfsub.vf v0,v4,fa1,v0.t'
+-.*Error: illegal operands `vfrsub.vf v0,v4,fa1,v0.t'
+-.*Error: illegal operands `vfmul.vv v0,v4,v8,v0.t'
+-.*Error: illegal operands `vfmul.vf v0,v4,fa1,v0.t'
+-.*Error: illegal operands `vfdiv.vv v0,v4,v8,v0.t'
+-.*Error: illegal operands `vfdiv.vf v0,v4,fa1,v0.t'
+-.*Error: illegal operands `vfrdiv.vf v0,v4,fa1,v0.t'
+-.*Error: illegal operands `vfmacc.vv v0,v4,v8,v0.t'
+-.*Error: illegal operands `vfmacc.vf v0,fa1,v4,v0.t'
+-.*Error: illegal operands `vfnmacc.vv v0,v4,v8,v0.t'
+-.*Error: illegal operands `vfnmacc.vf v0,fa1,v4,v0.t'
+-.*Error: illegal operands `vfmsac.vv v0,v4,v8,v0.t'
+-.*Error: illegal operands `vfmsac.vf v0,fa1,v4,v0.t'
+-.*Error: illegal operands `vfnmsac.vv v0,v4,v8,v0.t'
+-.*Error: illegal operands `vfnmsac.vf v0,fa1,v4,v0.t'
+-.*Error: illegal operands `vfmadd.vv v0,v4,v8,v0.t'
+-.*Error: illegal operands `vfmadd.vf v0,fa1,v4,v0.t'
+-.*Error: illegal operands `vfnmadd.vv v0,v4,v8,v0.t'
+-.*Error: illegal operands `vfnmadd.vf v0,fa1,v4,v0.t'
+-.*Error: illegal operands `vfmsub.vv v0,v4,v8,v0.t'
+-.*Error: illegal operands `vfmsub.vf v0,fa1,v4,v0.t'
+-.*Error: illegal operands `vfnmsub.vv v0,v4,v8,v0.t'
+-.*Error: illegal operands `vfnmsub.vf v0,fa1,v4,v0.t'
+-.*Error: illegal operands `vfsqrt.v v0,v4,v0.t'
+-.*Error: illegal operands `vfrece7.v v0,v4,v0.t'
+-.*Error: illegal operands `vfrsqrte7.v v0,v4,v0.t'
+-.*Error: illegal operands `vfclass.v v0,v4,v0.t'
+-.*Error: illegal operands `vfmin.vv v0,v4,v8,v0.t'
+-.*Error: illegal operands `vfmin.vf v0,v4,fa1,v0.t'
+-.*Error: illegal operands `vfmax.vv v0,v4,v8,v0.t'
+-.*Error: illegal operands `vfmax.vf v0,v4,fa1,v0.t'
+-.*Error: illegal operands `vfsgnj.vv v0,v4,v8,v0.t'
+-.*Error: illegal operands `vfsgnj.vf v0,v4,fa1,v0.t'
+-.*Error: illegal operands `vfsgnjn.vv v0,v4,v8,v0.t'
+-.*Error: illegal operands `vfsgnjn.vf v0,v4,fa1,v0.t'
+-.*Error: illegal operands `vfsgnjx.vv v0,v4,v8,v0.t'
+-.*Error: illegal operands `vfsgnjx.vf v0,v4,fa1,v0.t'
+-.*Error: illegal operands `vfcvt.xu.f.v v0,v4,v0.t'
+-.*Error: illegal operands `vfcvt.x.f.v v0,v4,v0.t'
+-.*Error: illegal operands `vfcvt.rtz.xu.f.v v0,v4,v0.t'
+-.*Error: illegal operands `vfcvt.rtz.x.f.v v0,v4,v0.t'
+-.*Error: illegal operands `vfcvt.f.xu.v v0,v4,v0.t'
+-.*Error: illegal operands `vfcvt.f.x.v v0,v4,v0.t'
++.*Error: illegal operands vd cannot overlap vm `vfadd.vv v0,v4,v8,v0.t'
++.*Error: illegal operands vd cannot overlap vm `vfadd.vf v0,v4,fa1,v0.t'
++.*Error: illegal operands vd cannot overlap vm `vfsub.vv v0,v4,v8,v0.t'
++.*Error: illegal operands vd cannot overlap vm `vfsub.vf v0,v4,fa1,v0.t'
++.*Error: illegal operands vd cannot overlap vm `vfrsub.vf v0,v4,fa1,v0.t'
++.*Error: illegal operands vd cannot overlap vm `vfmul.vv v0,v4,v8,v0.t'
++.*Error: illegal operands vd cannot overlap vm `vfmul.vf v0,v4,fa1,v0.t'
++.*Error: illegal operands vd cannot overlap vm `vfdiv.vv v0,v4,v8,v0.t'
++.*Error: illegal operands vd cannot overlap vm `vfdiv.vf v0,v4,fa1,v0.t'
++.*Error: illegal operands vd cannot overlap vm `vfrdiv.vf v0,v4,fa1,v0.t'
++.*Error: illegal operands vd cannot overlap vm `vfmacc.vv v0,v4,v8,v0.t'
++.*Error: illegal operands vd cannot overlap vm `vfmacc.vf v0,fa1,v4,v0.t'
++.*Error: illegal operands vd cannot overlap vm `vfnmacc.vv v0,v4,v8,v0.t'
++.*Error: illegal operands vd cannot overlap vm `vfnmacc.vf v0,fa1,v4,v0.t'
++.*Error: illegal operands vd cannot overlap vm `vfmsac.vv v0,v4,v8,v0.t'
++.*Error: illegal operands vd cannot overlap vm `vfmsac.vf v0,fa1,v4,v0.t'
++.*Error: illegal operands vd cannot overlap vm `vfnmsac.vv v0,v4,v8,v0.t'
++.*Error: illegal operands vd cannot overlap vm `vfnmsac.vf v0,fa1,v4,v0.t'
++.*Error: illegal operands vd cannot overlap vm `vfmadd.vv v0,v4,v8,v0.t'
++.*Error: illegal operands vd cannot overlap vm `vfmadd.vf v0,fa1,v4,v0.t'
++.*Error: illegal operands vd cannot overlap vm `vfnmadd.vv v0,v4,v8,v0.t'
++.*Error: illegal operands vd cannot overlap vm `vfnmadd.vf v0,fa1,v4,v0.t'
++.*Error: illegal operands vd cannot overlap vm `vfmsub.vv v0,v4,v8,v0.t'
++.*Error: illegal operands vd cannot overlap vm `vfmsub.vf v0,fa1,v4,v0.t'
++.*Error: illegal operands vd cannot overlap vm `vfnmsub.vv v0,v4,v8,v0.t'
++.*Error: illegal operands vd cannot overlap vm `vfnmsub.vf v0,fa1,v4,v0.t'
++.*Error: illegal operands vd cannot overlap vm `vfsqrt.v v0,v4,v0.t'
++.*Error: illegal operands vd cannot overlap vm `vfrece7.v v0,v4,v0.t'
++.*Error: illegal operands vd cannot overlap vm `vfrsqrte7.v v0,v4,v0.t'
++.*Error: illegal operands vd cannot overlap vm `vfclass.v v0,v4,v0.t'
++.*Error: illegal operands vd cannot overlap vm `vfmin.vv v0,v4,v8,v0.t'
++.*Error: illegal operands vd cannot overlap vm `vfmin.vf v0,v4,fa1,v0.t'
++.*Error: illegal operands vd cannot overlap vm `vfmax.vv v0,v4,v8,v0.t'
++.*Error: illegal operands vd cannot overlap vm `vfmax.vf v0,v4,fa1,v0.t'
++.*Error: illegal operands vd cannot overlap vm `vfsgnj.vv v0,v4,v8,v0.t'
++.*Error: illegal operands vd cannot overlap vm `vfsgnj.vf v0,v4,fa1,v0.t'
++.*Error: illegal operands vd cannot overlap vm `vfsgnjn.vv v0,v4,v8,v0.t'
++.*Error: illegal operands vd cannot overlap vm `vfsgnjn.vf v0,v4,fa1,v0.t'
++.*Error: illegal operands vd cannot overlap vm `vfsgnjx.vv v0,v4,v8,v0.t'
++.*Error: illegal operands vd cannot overlap vm `vfsgnjx.vf v0,v4,fa1,v0.t'
++.*Error: illegal operands vd cannot overlap vm `vfcvt.xu.f.v v0,v4,v0.t'
++.*Error: illegal operands vd cannot overlap vm `vfcvt.x.f.v v0,v4,v0.t'
++.*Error: illegal operands vd cannot overlap vm `vfcvt.rtz.xu.f.v v0,v4,v0.t'
++.*Error: illegal operands vd cannot overlap vm `vfcvt.rtz.x.f.v v0,v4,v0.t'
++.*Error: illegal operands vd cannot overlap vm `vfcvt.f.xu.v v0,v4,v0.t'
++.*Error: illegal operands vd cannot overlap vm `vfcvt.f.x.v v0,v4,v0.t'
+diff --git a/gas/testsuite/gas/riscv/vector-insns-fail-arith-int.l b/gas/testsuite/gas/riscv/vector-insns-fail-arith-int.l
+index 480406af93..3b1d780fa4 100644
+--- a/gas/testsuite/gas/riscv/vector-insns-fail-arith-int.l
++++ b/gas/testsuite/gas/riscv/vector-insns-fail-arith-int.l
+@@ -1,70 +1,70 @@
+ .*: Assembler messages:
+-.*Error: illegal operands `vadd.vv v0,v4,v8,v0.t'
+-.*Error: illegal operands `vadd.vx v0,v4,a1,v0.t'
+-.*Error: illegal operands `vadd.vi v0,v4,15,v0.t'
+-.*Error: illegal operands `vsub.vv v0,v4,v8,v0.t'
+-.*Error: illegal operands `vsub.vx v0,v4,a1,v0.t'
+-.*Error: illegal operands `vrsub.vx v0,v4,a1,v0.t'
+-.*Error: illegal operands `vrsub.vi v0,v4,15,v0.t'
+-.*Error: illegal operands `vzext.vf2 v0,v4,v0.t'
+-.*Error: illegal operands `vsext.vf2 v0,v4,v0.t'
+-.*Error: illegal operands `vzext.vf4 v0,v4,v0.t'
+-.*Error: illegal operands `vsext.vf4 v0,v4,v0.t'
+-.*Error: illegal operands `vzext.vf8 v0,v4,v0.t'
+-.*Error: illegal operands `vsext.vf8 v0,v4,v0.t'
+-.*Error: illegal operands `vadc.vvm v0,v4,v8,v0'
+-.*Error: illegal operands `vadc.vxm v0,v4,a1,v0'
+-.*Error: illegal operands `vadc.vim v0,v4,15,v0'
+-.*Error: illegal operands `vsbc.vvm v0,v4,v8,v0'
+-.*Error: illegal operands `vsbc.vxm v0,v4,a1,v0'
+-.*Error: illegal operands `vnot.v v0,v4,v0.t'
+-.*Error: illegal operands `vand.vv v0,v4,v8,v0.t'
+-.*Error: illegal operands `vand.vx v0,v4,a1,v0.t'
+-.*Error: illegal operands `vand.vi v0,v4,15,v0.t'
+-.*Error: illegal operands `vor.vv v0,v4,v8,v0.t'
+-.*Error: illegal operands `vor.vx v0,v4,a1,v0.t'
+-.*Error: illegal operands `vor.vi v0,v4,15,v0.t'
+-.*Error: illegal operands `vxor.vv v0,v4,v8,v0.t'
+-.*Error: illegal operands `vxor.vx v0,v4,a1,v0.t'
+-.*Error: illegal operands `vxor.vi v0,v4,15,v0.t'
+-.*Error: illegal operands `vsll.vv v0,v4,v8,v0.t'
+-.*Error: illegal operands `vsll.vx v0,v4,a1,v0.t'
+-.*Error: illegal operands `vsll.vi v0,v4,31,v0.t'
+-.*Error: illegal operands `vsrl.vv v0,v4,v8,v0.t'
+-.*Error: illegal operands `vsrl.vx v0,v4,a1,v0.t'
+-.*Error: illegal operands `vsrl.vi v0,v4,31,v0.t'
+-.*Error: illegal operands `vsra.vv v0,v4,v8,v0.t'
+-.*Error: illegal operands `vsra.vx v0,v4,a1,v0.t'
+-.*Error: illegal operands `vsra.vi v0,v4,31,v0.t'
+-.*Error: illegal operands `vminu.vv v0,v4,v8,v0.t'
+-.*Error: illegal operands `vminu.vx v0,v4,a1,v0.t'
+-.*Error: illegal operands `vmin.vv v0,v4,v8,v0.t'
+-.*Error: illegal operands `vmin.vx v0,v4,a1,v0.t'
+-.*Error: illegal operands `vmaxu.vv v0,v4,v8,v0.t'
+-.*Error: illegal operands `vmaxu.vx v0,v4,a1,v0.t'
+-.*Error: illegal operands `vmax.vv v0,v4,v8,v0.t'
+-.*Error: illegal operands `vmax.vx v0,v4,a1,v0.t'
+-.*Error: illegal operands `vmul.vv v0,v4,v8,v0.t'
+-.*Error: illegal operands `vmul.vx v0,v4,a1,v0.t'
+-.*Error: illegal operands `vmulh.vv v0,v4,v8,v0.t'
+-.*Error: illegal operands `vmulh.vx v0,v4,a1,v0.t'
+-.*Error: illegal operands `vmulhu.vv v0,v4,v8,v0.t'
+-.*Error: illegal operands `vmulhu.vx v0,v4,a1,v0.t'
+-.*Error: illegal operands `vmulhsu.vv v0,v4,v8,v0.t'
+-.*Error: illegal operands `vmulhsu.vx v0,v4,a1,v0.t'
+-.*Error: illegal operands `vdivu.vv v0,v4,v8,v0.t'
+-.*Error: illegal operands `vdivu.vx v0,v4,a1,v0.t'
+-.*Error: illegal operands `vdiv.vv v0,v4,v8,v0.t'
+-.*Error: illegal operands `vdiv.vx v0,v4,a1,v0.t'
+-.*Error: illegal operands `vremu.vv v0,v4,v8,v0.t'
+-.*Error: illegal operands `vremu.vx v0,v4,a1,v0.t'
+-.*Error: illegal operands `vrem.vv v0,v4,v8,v0.t'
+-.*Error: illegal operands `vrem.vx v0,v4,a1,v0.t'
+-.*Error: illegal operands `vmacc.vv v0,v4,v8,v0.t'
+-.*Error: illegal operands `vmacc.vx v0,a1,v4,v0.t'
+-.*Error: illegal operands `vnmsac.vv v0,v4,v8,v0.t'
+-.*Error: illegal operands `vnmsac.vx v0,a1,v4,v0.t'
+-.*Error: illegal operands `vmadd.vv v0,v4,v8,v0.t'
+-.*Error: illegal operands `vmadd.vx v0,a1,v4,v0.t'
+-.*Error: illegal operands `vnmsub.vv v0,v4,v8,v0.t'
+-.*Error: illegal operands `vnmsub.vx v0,a1,v4,v0.t'
++.*Error: illegal operands vd cannot overlap vm `vadd.vv v0,v4,v8,v0.t'
++.*Error: illegal operands vd cannot overlap vm `vadd.vx v0,v4,a1,v0.t'
++.*Error: illegal operands vd cannot overlap vm `vadd.vi v0,v4,15,v0.t'
++.*Error: illegal operands vd cannot overlap vm `vsub.vv v0,v4,v8,v0.t'
++.*Error: illegal operands vd cannot overlap vm `vsub.vx v0,v4,a1,v0.t'
++.*Error: illegal operands vd cannot overlap vm `vrsub.vx v0,v4,a1,v0.t'
++.*Error: illegal operands vd cannot overlap vm `vrsub.vi v0,v4,15,v0.t'
++.*Error: illegal operands vd cannot overlap vm `vzext.vf2 v0,v4,v0.t'
++.*Error: illegal operands vd cannot overlap vm `vsext.vf2 v0,v4,v0.t'
++.*Error: illegal operands vd cannot overlap vm `vzext.vf4 v0,v4,v0.t'
++.*Error: illegal operands vd cannot overlap vm `vsext.vf4 v0,v4,v0.t'
++.*Error: illegal operands vd cannot overlap vm `vzext.vf8 v0,v4,v0.t'
++.*Error: illegal operands vd cannot overlap vm `vsext.vf8 v0,v4,v0.t'
++.*Error: illegal operands vd cannot overlap vm `vadc.vvm v0,v4,v8,v0'
++.*Error: illegal operands vd cannot overlap vm `vadc.vxm v0,v4,a1,v0'
++.*Error: illegal operands vd cannot overlap vm `vadc.vim v0,v4,15,v0'
++.*Error: illegal operands vd cannot overlap vm `vsbc.vvm v0,v4,v8,v0'
++.*Error: illegal operands vd cannot overlap vm `vsbc.vxm v0,v4,a1,v0'
++.*Error: illegal operands vd cannot overlap vm `vnot.v v0,v4,v0.t'
++.*Error: illegal operands vd cannot overlap vm `vand.vv v0,v4,v8,v0.t'
++.*Error: illegal operands vd cannot overlap vm `vand.vx v0,v4,a1,v0.t'
++.*Error: illegal operands vd cannot overlap vm `vand.vi v0,v4,15,v0.t'
++.*Error: illegal operands vd cannot overlap vm `vor.vv v0,v4,v8,v0.t'
++.*Error: illegal operands vd cannot overlap vm `vor.vx v0,v4,a1,v0.t'
++.*Error: illegal operands vd cannot overlap vm `vor.vi v0,v4,15,v0.t'
++.*Error: illegal operands vd cannot overlap vm `vxor.vv v0,v4,v8,v0.t'
++.*Error: illegal operands vd cannot overlap vm `vxor.vx v0,v4,a1,v0.t'
++.*Error: illegal operands vd cannot overlap vm `vxor.vi v0,v4,15,v0.t'
++.*Error: illegal operands vd cannot overlap vm `vsll.vv v0,v4,v8,v0.t'
++.*Error: illegal operands vd cannot overlap vm `vsll.vx v0,v4,a1,v0.t'
++.*Error: illegal operands vd cannot overlap vm `vsll.vi v0,v4,31,v0.t'
++.*Error: illegal operands vd cannot overlap vm `vsrl.vv v0,v4,v8,v0.t'
++.*Error: illegal operands vd cannot overlap vm `vsrl.vx v0,v4,a1,v0.t'
++.*Error: illegal operands vd cannot overlap vm `vsrl.vi v0,v4,31,v0.t'
++.*Error: illegal operands vd cannot overlap vm `vsra.vv v0,v4,v8,v0.t'
++.*Error: illegal operands vd cannot overlap vm `vsra.vx v0,v4,a1,v0.t'
++.*Error: illegal operands vd cannot overlap vm `vsra.vi v0,v4,31,v0.t'
++.*Error: illegal operands vd cannot overlap vm `vminu.vv v0,v4,v8,v0.t'
++.*Error: illegal operands vd cannot overlap vm `vminu.vx v0,v4,a1,v0.t'
++.*Error: illegal operands vd cannot overlap vm `vmin.vv v0,v4,v8,v0.t'
++.*Error: illegal operands vd cannot overlap vm `vmin.vx v0,v4,a1,v0.t'
++.*Error: illegal operands vd cannot overlap vm `vmaxu.vv v0,v4,v8,v0.t'
++.*Error: illegal operands vd cannot overlap vm `vmaxu.vx v0,v4,a1,v0.t'
++.*Error: illegal operands vd cannot overlap vm `vmax.vv v0,v4,v8,v0.t'
++.*Error: illegal operands vd cannot overlap vm `vmax.vx v0,v4,a1,v0.t'
++.*Error: illegal operands vd cannot overlap vm `vmul.vv v0,v4,v8,v0.t'
++.*Error: illegal operands vd cannot overlap vm `vmul.vx v0,v4,a1,v0.t'
++.*Error: illegal operands vd cannot overlap vm `vmulh.vv v0,v4,v8,v0.t'
++.*Error: illegal operands vd cannot overlap vm `vmulh.vx v0,v4,a1,v0.t'
++.*Error: illegal operands vd cannot overlap vm `vmulhu.vv v0,v4,v8,v0.t'
++.*Error: illegal operands vd cannot overlap vm `vmulhu.vx v0,v4,a1,v0.t'
++.*Error: illegal operands vd cannot overlap vm `vmulhsu.vv v0,v4,v8,v0.t'
++.*Error: illegal operands vd cannot overlap vm `vmulhsu.vx v0,v4,a1,v0.t'
++.*Error: illegal operands vd cannot overlap vm `vdivu.vv v0,v4,v8,v0.t'
++.*Error: illegal operands vd cannot overlap vm `vdivu.vx v0,v4,a1,v0.t'
++.*Error: illegal operands vd cannot overlap vm `vdiv.vv v0,v4,v8,v0.t'
++.*Error: illegal operands vd cannot overlap vm `vdiv.vx v0,v4,a1,v0.t'
++.*Error: illegal operands vd cannot overlap vm `vremu.vv v0,v4,v8,v0.t'
++.*Error: illegal operands vd cannot overlap vm `vremu.vx v0,v4,a1,v0.t'
++.*Error: illegal operands vd cannot overlap vm `vrem.vv v0,v4,v8,v0.t'
++.*Error: illegal operands vd cannot overlap vm `vrem.vx v0,v4,a1,v0.t'
++.*Error: illegal operands vd cannot overlap vm `vmacc.vv v0,v4,v8,v0.t'
++.*Error: illegal operands vd cannot overlap vm `vmacc.vx v0,a1,v4,v0.t'
++.*Error: illegal operands vd cannot overlap vm `vnmsac.vv v0,v4,v8,v0.t'
++.*Error: illegal operands vd cannot overlap vm `vnmsac.vx v0,a1,v4,v0.t'
++.*Error: illegal operands vd cannot overlap vm `vmadd.vv v0,v4,v8,v0.t'
++.*Error: illegal operands vd cannot overlap vm `vmadd.vx v0,a1,v4,v0.t'
++.*Error: illegal operands vd cannot overlap vm `vnmsub.vv v0,v4,v8,v0.t'
++.*Error: illegal operands vd cannot overlap vm `vnmsub.vx v0,a1,v4,v0.t'
+diff --git a/gas/testsuite/gas/riscv/vector-insns-fail-arith-narrow.l b/gas/testsuite/gas/riscv/vector-insns-fail-arith-narrow.l
+index dcbe3b3f79..defca03d6d 100644
+--- a/gas/testsuite/gas/riscv/vector-insns-fail-arith-narrow.l
++++ b/gas/testsuite/gas/riscv/vector-insns-fail-arith-narrow.l
+@@ -1,85 +1,85 @@
+ .*: Assembler messages:
+-.*Error: illegal operands `vncvt.x.x.v v2,v2'
+-.*Error: illegal operands `vncvt.x.x.v v2,v3'
+-.*Error: illegal operands `vncvt.x.x.v v3,v2'
+-.*Error: illegal operands `vncvt.x.x.v v0,v2,v0.t'
+-.*Error: illegal operands `vnsrl.wv v2,v2,v4'
+-.*Error: illegal operands `vnsrl.wv v2,v3,v4'
+-.*Error: illegal operands `vnsrl.wv v3,v2,v4'
+-.*Error: illegal operands `vnsrl.wv v0,v2,v4,v0.t'
+-.*Error: illegal operands `vnsrl.wx v2,v2,a1'
+-.*Error: illegal operands `vnsrl.wx v2,v3,a1'
+-.*Error: illegal operands `vnsrl.wx v3,v2,a1'
+-.*Error: illegal operands `vnsrl.wx v0,v2,a1,v0.t'
+-.*Error: illegal operands `vnsrl.wi v2,v2,31'
+-.*Error: illegal operands `vnsrl.wi v2,v3,31'
+-.*Error: illegal operands `vnsrl.wi v3,v2,31'
+-.*Error: illegal operands `vnsrl.wi v0,v2,31,v0.t'
+-.*Error: illegal operands `vnsra.wv v2,v2,v4'
+-.*Error: illegal operands `vnsra.wv v2,v3,v4'
+-.*Error: illegal operands `vnsra.wv v3,v2,v4'
+-.*Error: illegal operands `vnsra.wv v0,v2,v4,v0.t'
+-.*Error: illegal operands `vnsra.wx v2,v2,a1'
+-.*Error: illegal operands `vnsra.wx v2,v3,a1'
+-.*Error: illegal operands `vnsra.wx v3,v2,a1'
+-.*Error: illegal operands `vnsra.wx v0,v2,a1,v0.t'
+-.*Error: illegal operands `vnsra.wi v2,v2,31'
+-.*Error: illegal operands `vnsra.wi v2,v3,31'
+-.*Error: illegal operands `vnsra.wi v3,v2,31'
+-.*Error: illegal operands `vnsra.wi v0,v2,31,v0.t'
+-.*Error: illegal operands `vnclipu.wv v2,v2,v4'
+-.*Error: illegal operands `vnclipu.wv v2,v3,v4'
+-.*Error: illegal operands `vnclipu.wv v3,v2,v4'
+-.*Error: illegal operands `vnclipu.wv v0,v2,v4,v0.t'
+-.*Error: illegal operands `vnclipu.wx v2,v2,a1'
+-.*Error: illegal operands `vnclipu.wx v2,v3,a1'
+-.*Error: illegal operands `vnclipu.wx v3,v2,a1'
+-.*Error: illegal operands `vnclipu.wx v0,v2,a1,v0.t'
+-.*Error: illegal operands `vnclipu.wi v2,v2,31'
+-.*Error: illegal operands `vnclipu.wi v2,v3,31'
+-.*Error: illegal operands `vnclipu.wi v3,v2,31'
+-.*Error: illegal operands `vnclipu.wi v0,v2,31,v0.t'
+-.*Error: illegal operands `vnclip.wv v2,v2,v4'
+-.*Error: illegal operands `vnclip.wv v2,v3,v4'
+-.*Error: illegal operands `vnclip.wv v3,v2,v4'
+-.*Error: illegal operands `vnclip.wv v0,v2,v4,v0.t'
+-.*Error: illegal operands `vnclip.wx v2,v2,a1'
+-.*Error: illegal operands `vnclip.wx v2,v3,a1'
+-.*Error: illegal operands `vnclip.wx v3,v2,a1'
+-.*Error: illegal operands `vnclip.wx v0,v2,a1,v0.t'
+-.*Error: illegal operands `vnclip.wi v2,v2,31'
+-.*Error: illegal operands `vnclip.wi v2,v3,31'
+-.*Error: illegal operands `vnclip.wi v3,v2,31'
+-.*Error: illegal operands `vnclip.wi v0,v2,31,v0.t'
+-.*Error: illegal operands `vfncvt.xu.f.w v2,v2'
+-.*Error: illegal operands `vfncvt.xu.f.w v2,v3'
+-.*Error: illegal operands `vfncvt.xu.f.w v3,v2'
+-.*Error: illegal operands `vfncvt.xu.f.w v0,v2,v0.t'
+-.*Error: illegal operands `vfncvt.x.f.w v2,v2'
+-.*Error: illegal operands `vfncvt.x.f.w v2,v3'
+-.*Error: illegal operands `vfncvt.x.f.w v3,v2'
+-.*Error: illegal operands `vfncvt.x.f.w v0,v2,v0.t'
+-.*Error: illegal operands `vfncvt.rtz.xu.f.w v2,v2'
+-.*Error: illegal operands `vfncvt.rtz.xu.f.w v2,v3'
+-.*Error: illegal operands `vfncvt.rtz.xu.f.w v3,v2'
+-.*Error: illegal operands `vfncvt.rtz.xu.f.w v0,v2,v0.t'
+-.*Error: illegal operands `vfncvt.rtz.x.f.w v2,v2'
+-.*Error: illegal operands `vfncvt.rtz.x.f.w v2,v3'
+-.*Error: illegal operands `vfncvt.rtz.x.f.w v3,v2'
+-.*Error: illegal operands `vfncvt.rtz.x.f.w v0,v2,v0.t'
+-.*Error: illegal operands `vfncvt.f.xu.w v2,v2'
+-.*Error: illegal operands `vfncvt.f.xu.w v2,v3'
+-.*Error: illegal operands `vfncvt.f.xu.w v3,v2'
+-.*Error: illegal operands `vfncvt.f.xu.w v0,v2,v0.t'
+-.*Error: illegal operands `vfncvt.f.x.w v2,v2'
+-.*Error: illegal operands `vfncvt.f.x.w v2,v3'
+-.*Error: illegal operands `vfncvt.f.x.w v3,v2'
+-.*Error: illegal operands `vfncvt.f.x.w v0,v2,v0.t'
+-.*Error: illegal operands `vfncvt.f.f.w v2,v2'
+-.*Error: illegal operands `vfncvt.f.f.w v2,v3'
+-.*Error: illegal operands `vfncvt.f.f.w v3,v2'
+-.*Error: illegal operands `vfncvt.f.f.w v0,v2,v0.t'
+-.*Error: illegal operands `vfncvt.rod.f.f.w v2,v2'
+-.*Error: illegal operands `vfncvt.rod.f.f.w v2,v3'
+-.*Error: illegal operands `vfncvt.rod.f.f.w v3,v2'
+-.*Error: illegal operands `vfncvt.rod.f.f.w v0,v2,v0.t'
++.*Error: illegal operands vd cannot overlap vs2 `vncvt.x.x.v v2,v2'
++.*Error: illegal operands vd must be multiple of 2 `vncvt.x.x.v v2,v3'
++.*Error: illegal operands vd cannot overlap vs2 `vncvt.x.x.v v3,v2'
++.*Error: illegal operands vd cannot overlap vm `vncvt.x.x.v v0,v2,v0.t'
++.*Error: illegal operands vd cannot overlap vs2 `vnsrl.wv v2,v2,v4'
++.*Error: illegal operands vd must be multiple of 2 `vnsrl.wv v2,v3,v4'
++.*Error: illegal operands vd cannot overlap vs2 `vnsrl.wv v3,v2,v4'
++.*Error: illegal operands vd cannot overlap vm `vnsrl.wv v0,v2,v4,v0.t'
++.*Error: illegal operands vd cannot overlap vs2 `vnsrl.wx v2,v2,a1'
++.*Error: illegal operands vd must be multiple of 2 `vnsrl.wx v2,v3,a1'
++.*Error: illegal operands vd cannot overlap vs2 `vnsrl.wx v3,v2,a1'
++.*Error: illegal operands vd cannot overlap vm `vnsrl.wx v0,v2,a1,v0.t'
++.*Error: illegal operands vd cannot overlap vs2 `vnsrl.wi v2,v2,31'
++.*Error: illegal operands vd must be multiple of 2 `vnsrl.wi v2,v3,31'
++.*Error: illegal operands vd cannot overlap vs2 `vnsrl.wi v3,v2,31'
++.*Error: illegal operands vd cannot overlap vm `vnsrl.wi v0,v2,31,v0.t'
++.*Error: illegal operands vd cannot overlap vs2 `vnsra.wv v2,v2,v4'
++.*Error: illegal operands vd must be multiple of 2 `vnsra.wv v2,v3,v4'
++.*Error: illegal operands vd cannot overlap vs2 `vnsra.wv v3,v2,v4'
++.*Error: illegal operands vd cannot overlap vm `vnsra.wv v0,v2,v4,v0.t'
++.*Error: illegal operands vd cannot overlap vs2 `vnsra.wx v2,v2,a1'
++.*Error: illegal operands vd must be multiple of 2 `vnsra.wx v2,v3,a1'
++.*Error: illegal operands vd cannot overlap vs2 `vnsra.wx v3,v2,a1'
++.*Error: illegal operands vd cannot overlap vm `vnsra.wx v0,v2,a1,v0.t'
++.*Error: illegal operands vd cannot overlap vs2 `vnsra.wi v2,v2,31'
++.*Error: illegal operands vd must be multiple of 2 `vnsra.wi v2,v3,31'
++.*Error: illegal operands vd cannot overlap vs2 `vnsra.wi v3,v2,31'
++.*Error: illegal operands vd cannot overlap vm `vnsra.wi v0,v2,31,v0.t'
++.*Error: illegal operands vd cannot overlap vs2 `vnclipu.wv v2,v2,v4'
++.*Error: illegal operands vd must be multiple of 2 `vnclipu.wv v2,v3,v4'
++.*Error: illegal operands vd cannot overlap vs2 `vnclipu.wv v3,v2,v4'
++.*Error: illegal operands vd cannot overlap vm `vnclipu.wv v0,v2,v4,v0.t'
++.*Error: illegal operands vd cannot overlap vs2 `vnclipu.wx v2,v2,a1'
++.*Error: illegal operands vd must be multiple of 2 `vnclipu.wx v2,v3,a1'
++.*Error: illegal operands vd cannot overlap vs2 `vnclipu.wx v3,v2,a1'
++.*Error: illegal operands vd cannot overlap vm `vnclipu.wx v0,v2,a1,v0.t'
++.*Error: illegal operands vd cannot overlap vs2 `vnclipu.wi v2,v2,31'
++.*Error: illegal operands vd must be multiple of 2 `vnclipu.wi v2,v3,31'
++.*Error: illegal operands vd cannot overlap vs2 `vnclipu.wi v3,v2,31'
++.*Error: illegal operands vd cannot overlap vm `vnclipu.wi v0,v2,31,v0.t'
++.*Error: illegal operands vd cannot overlap vs2 `vnclip.wv v2,v2,v4'
++.*Error: illegal operands vd must be multiple of 2 `vnclip.wv v2,v3,v4'
++.*Error: illegal operands vd cannot overlap vs2 `vnclip.wv v3,v2,v4'
++.*Error: illegal operands vd cannot overlap vm `vnclip.wv v0,v2,v4,v0.t'
++.*Error: illegal operands vd cannot overlap vs2 `vnclip.wx v2,v2,a1'
++.*Error: illegal operands vd must be multiple of 2 `vnclip.wx v2,v3,a1'
++.*Error: illegal operands vd cannot overlap vs2 `vnclip.wx v3,v2,a1'
++.*Error: illegal operands vd cannot overlap vm `vnclip.wx v0,v2,a1,v0.t'
++.*Error: illegal operands vd cannot overlap vs2 `vnclip.wi v2,v2,31'
++.*Error: illegal operands vd must be multiple of 2 `vnclip.wi v2,v3,31'
++.*Error: illegal operands vd cannot overlap vs2 `vnclip.wi v3,v2,31'
++.*Error: illegal operands vd cannot overlap vm `vnclip.wi v0,v2,31,v0.t'
++.*Error: illegal operands vd cannot overlap vs2 `vfncvt.xu.f.w v2,v2'
++.*Error: illegal operands vd must be multiple of 2 `vfncvt.xu.f.w v2,v3'
++.*Error: illegal operands vd cannot overlap vs2 `vfncvt.xu.f.w v3,v2'
++.*Error: illegal operands vd cannot overlap vm `vfncvt.xu.f.w v0,v2,v0.t'
++.*Error: illegal operands vd cannot overlap vs2 `vfncvt.x.f.w v2,v2'
++.*Error: illegal operands vd must be multiple of 2 `vfncvt.x.f.w v2,v3'
++.*Error: illegal operands vd cannot overlap vs2 `vfncvt.x.f.w v3,v2'
++.*Error: illegal operands vd cannot overlap vm `vfncvt.x.f.w v0,v2,v0.t'
++.*Error: illegal operands vd cannot overlap vs2 `vfncvt.rtz.xu.f.w v2,v2'
++.*Error: illegal operands vd must be multiple of 2 `vfncvt.rtz.xu.f.w v2,v3'
++.*Error: illegal operands vd cannot overlap vs2 `vfncvt.rtz.xu.f.w v3,v2'
++.*Error: illegal operands vd cannot overlap vm `vfncvt.rtz.xu.f.w v0,v2,v0.t'
++.*Error: illegal operands vd cannot overlap vs2 `vfncvt.rtz.x.f.w v2,v2'
++.*Error: illegal operands vd must be multiple of 2 `vfncvt.rtz.x.f.w v2,v3'
++.*Error: illegal operands vd cannot overlap vs2 `vfncvt.rtz.x.f.w v3,v2'
++.*Error: illegal operands vd cannot overlap vm `vfncvt.rtz.x.f.w v0,v2,v0.t'
++.*Error: illegal operands vd cannot overlap vs2 `vfncvt.f.xu.w v2,v2'
++.*Error: illegal operands vd must be multiple of 2 `vfncvt.f.xu.w v2,v3'
++.*Error: illegal operands vd cannot overlap vs2 `vfncvt.f.xu.w v3,v2'
++.*Error: illegal operands vd cannot overlap vm `vfncvt.f.xu.w v0,v2,v0.t'
++.*Error: illegal operands vd cannot overlap vs2 `vfncvt.f.x.w v2,v2'
++.*Error: illegal operands vd must be multiple of 2 `vfncvt.f.x.w v2,v3'
++.*Error: illegal operands vd cannot overlap vs2 `vfncvt.f.x.w v3,v2'
++.*Error: illegal operands vd cannot overlap vm `vfncvt.f.x.w v0,v2,v0.t'
++.*Error: illegal operands vd cannot overlap vs2 `vfncvt.f.f.w v2,v2'
++.*Error: illegal operands vd must be multiple of 2 `vfncvt.f.f.w v2,v3'
++.*Error: illegal operands vd cannot overlap vs2 `vfncvt.f.f.w v3,v2'
++.*Error: illegal operands vd cannot overlap vm `vfncvt.f.f.w v0,v2,v0.t'
++.*Error: illegal operands vd cannot overlap vs2 `vfncvt.rod.f.f.w v2,v2'
++.*Error: illegal operands vd must be multiple of 2 `vfncvt.rod.f.f.w v2,v3'
++.*Error: illegal operands vd cannot overlap vs2 `vfncvt.rod.f.f.w v3,v2'
++.*Error: illegal operands vd cannot overlap vm `vfncvt.rod.f.f.w v0,v2,v0.t'
+diff --git a/gas/testsuite/gas/riscv/vector-insns-fail-arith-widen.l b/gas/testsuite/gas/riscv/vector-insns-fail-arith-widen.l
+index 5684601697..5f22ca99e9 100644
+--- a/gas/testsuite/gas/riscv/vector-insns-fail-arith-widen.l
++++ b/gas/testsuite/gas/riscv/vector-insns-fail-arith-widen.l
+@@ -1,253 +1,253 @@
+ .*: Assembler messages:
+-.*Error: illegal operands `vwcvtu.x.x.v v1,v2'
+-.*Error: illegal operands `vwcvtu.x.x.v v2,v2'
+-.*Error: illegal operands `vwcvtu.x.x.v v2,v3'
+-.*Error: illegal operands `vwcvtu.x.x.v v0,v2,v0.t'
+-.*Error: illegal operands `vwcvt.x.x.v v1,v2'
+-.*Error: illegal operands `vwcvt.x.x.v v2,v2'
+-.*Error: illegal operands `vwcvt.x.x.v v2,v3'
+-.*Error: illegal operands `vwcvt.x.x.v v0,v2,v0.t'
+-.*Error: illegal operands `vwaddu.vv v1,v2,v4'
+-.*Error: illegal operands `vwaddu.vv v2,v2,v4'
+-.*Error: illegal operands `vwaddu.vv v2,v3,v4'
+-.*Error: illegal operands `vwaddu.vv v4,v2,v4'
+-.*Error: illegal operands `vwaddu.vv v4,v2,v5'
+-.*Error: illegal operands `vwaddu.vv v0,v2,v4,v0.t'
+-.*Error: illegal operands `vwaddu.vx v1,v2,a1'
+-.*Error: illegal operands `vwaddu.vx v2,v2,a1'
+-.*Error: illegal operands `vwaddu.vx v2,v3,a1'
+-.*Error: illegal operands `vwaddu.vx v0,v2,a1,v0.t'
+-.*Error: illegal operands `vwaddu.wv v1,v2,v4'
+-.*Error: illegal operands `vwaddu.wv v2,v3,v4'
+-.*Error: illegal operands `vwaddu.wv v4,v2,v4'
+-.*Error: illegal operands `vwaddu.wv v4,v2,v5'
+-.*Error: illegal operands `vwaddu.wv v0,v2,v4,v0.t'
+-.*Error: illegal operands `vwaddu.wx v1,v2,a1'
+-.*Error: illegal operands `vwaddu.wx v2,v3,a1'
+-.*Error: illegal operands `vwaddu.wx v0,v2,a1,v0.t'
+-.*Error: illegal operands `vwsubu.vv v1,v2,v4'
+-.*Error: illegal operands `vwsubu.vv v2,v2,v4'
+-.*Error: illegal operands `vwsubu.vv v2,v3,v4'
+-.*Error: illegal operands `vwsubu.vv v4,v2,v4'
+-.*Error: illegal operands `vwsubu.vv v4,v2,v5'
+-.*Error: illegal operands `vwsubu.vv v0,v2,v4,v0.t'
+-.*Error: illegal operands `vwsubu.vx v1,v2,a1'
+-.*Error: illegal operands `vwsubu.vx v2,v2,a1'
+-.*Error: illegal operands `vwsubu.vx v2,v3,a1'
+-.*Error: illegal operands `vwsubu.vx v0,v2,a1,v0.t'
+-.*Error: illegal operands `vwsubu.wv v1,v2,v4'
+-.*Error: illegal operands `vwsubu.wv v2,v3,v4'
+-.*Error: illegal operands `vwsubu.wv v4,v2,v4'
+-.*Error: illegal operands `vwsubu.wv v4,v2,v5'
+-.*Error: illegal operands `vwsubu.wv v0,v2,v4,v0.t'
+-.*Error: illegal operands `vwsubu.wx v1,v2,a1'
+-.*Error: illegal operands `vwsubu.wx v2,v3,a1'
+-.*Error: illegal operands `vwsubu.wx v0,v2,a1,v0.t'
+-.*Error: illegal operands `vwadd.vv v1,v2,v4'
+-.*Error: illegal operands `vwadd.vv v2,v2,v4'
+-.*Error: illegal operands `vwadd.vv v2,v3,v4'
+-.*Error: illegal operands `vwadd.vv v4,v2,v4'
+-.*Error: illegal operands `vwadd.vv v4,v2,v5'
+-.*Error: illegal operands `vwadd.vv v0,v2,v4,v0.t'
+-.*Error: illegal operands `vwadd.vx v1,v2,a1'
+-.*Error: illegal operands `vwadd.vx v2,v2,a1'
+-.*Error: illegal operands `vwadd.vx v2,v3,a1'
+-.*Error: illegal operands `vwadd.vx v0,v2,a1,v0.t'
+-.*Error: illegal operands `vwadd.wv v1,v2,v4'
+-.*Error: illegal operands `vwadd.wv v2,v3,v4'
+-.*Error: illegal operands `vwadd.wv v4,v2,v4'
+-.*Error: illegal operands `vwadd.wv v4,v2,v5'
+-.*Error: illegal operands `vwadd.wv v0,v2,v4,v0.t'
+-.*Error: illegal operands `vwadd.wx v1,v2,a1'
+-.*Error: illegal operands `vwadd.wx v2,v3,a1'
+-.*Error: illegal operands `vwadd.wx v0,v2,a1,v0.t'
+-.*Error: illegal operands `vwsub.vv v1,v2,v4'
+-.*Error: illegal operands `vwsub.vv v2,v2,v4'
+-.*Error: illegal operands `vwsub.vv v2,v3,v4'
+-.*Error: illegal operands `vwsub.vv v4,v2,v4'
+-.*Error: illegal operands `vwsub.vv v4,v2,v5'
+-.*Error: illegal operands `vwsub.vv v0,v2,v4,v0.t'
+-.*Error: illegal operands `vwsub.vx v1,v2,a1'
+-.*Error: illegal operands `vwsub.vx v2,v2,a1'
+-.*Error: illegal operands `vwsub.vx v2,v3,a1'
+-.*Error: illegal operands `vwsub.vx v0,v2,a1,v0.t'
+-.*Error: illegal operands `vwsub.wv v1,v2,v4'
+-.*Error: illegal operands `vwsub.wv v2,v3,v4'
+-.*Error: illegal operands `vwsub.wv v4,v2,v4'
+-.*Error: illegal operands `vwsub.wv v4,v2,v5'
+-.*Error: illegal operands `vwsub.wv v0,v2,v4,v0.t'
+-.*Error: illegal operands `vwsub.wx v1,v2,a1'
+-.*Error: illegal operands `vwsub.wx v2,v3,a1'
+-.*Error: illegal operands `vwsub.wx v0,v2,a1,v0.t'
+-.*Error: illegal operands `vwmul.vv v1,v2,v4'
+-.*Error: illegal operands `vwmul.vv v2,v2,v4'
+-.*Error: illegal operands `vwmul.vv v2,v3,v4'
+-.*Error: illegal operands `vwmul.vv v4,v2,v4'
+-.*Error: illegal operands `vwmul.vv v4,v2,v5'
+-.*Error: illegal operands `vwmul.vv v0,v2,v4,v0.t'
+-.*Error: illegal operands `vwmul.vx v1,v2,a1'
+-.*Error: illegal operands `vwmul.vx v2,v2,a1'
+-.*Error: illegal operands `vwmul.vx v2,v3,a1'
+-.*Error: illegal operands `vwmul.vx v0,v2,a1,v0.t'
+-.*Error: illegal operands `vwmulu.vv v1,v2,v4'
+-.*Error: illegal operands `vwmulu.vv v2,v2,v4'
+-.*Error: illegal operands `vwmulu.vv v2,v3,v4'
+-.*Error: illegal operands `vwmulu.vv v4,v2,v4'
+-.*Error: illegal operands `vwmulu.vv v4,v2,v5'
+-.*Error: illegal operands `vwmulu.vv v0,v2,v4,v0.t'
+-.*Error: illegal operands `vwmulu.vx v1,v2,a1'
+-.*Error: illegal operands `vwmulu.vx v2,v2,a1'
+-.*Error: illegal operands `vwmulu.vx v2,v3,a1'
+-.*Error: illegal operands `vwmulu.vx v0,v2,a1,v0.t'
+-.*Error: illegal operands `vwmulsu.vv v1,v2,v4'
+-.*Error: illegal operands `vwmulsu.vv v2,v2,v4'
+-.*Error: illegal operands `vwmulsu.vv v2,v3,v4'
+-.*Error: illegal operands `vwmulsu.vv v4,v2,v4'
+-.*Error: illegal operands `vwmulsu.vv v4,v2,v5'
+-.*Error: illegal operands `vwmulsu.vv v0,v2,v4,v0.t'
+-.*Error: illegal operands `vwmulsu.vx v1,v2,a1'
+-.*Error: illegal operands `vwmulsu.vx v2,v2,a1'
+-.*Error: illegal operands `vwmulsu.vx v2,v3,a1'
+-.*Error: illegal operands `vwmulsu.vx v0,v2,a1,v0.t'
+-.*Error: illegal operands `vwmaccu.vv v1,v2,v4'
+-.*Error: illegal operands `vwmaccu.vv v2,v2,v4'
+-.*Error: illegal operands `vwmaccu.vv v2,v3,v4'
+-.*Error: illegal operands `vwmaccu.vv v4,v2,v4'
+-.*Error: illegal operands `vwmaccu.vv v4,v2,v5'
+-.*Error: illegal operands `vwmaccu.vv v0,v2,v4,v0.t'
+-.*Error: illegal operands `vwmaccu.vx v1,a1,v2'
+-.*Error: illegal operands `vwmaccu.vx v2,a1,v2'
+-.*Error: illegal operands `vwmaccu.vx v2,a1,v3'
+-.*Error: illegal operands `vwmaccu.vx v0,a1,v2,v0.t'
+-.*Error: illegal operands `vwmacc.vv v1,v2,v4'
+-.*Error: illegal operands `vwmacc.vv v2,v2,v4'
+-.*Error: illegal operands `vwmacc.vv v2,v3,v4'
+-.*Error: illegal operands `vwmacc.vv v4,v2,v4'
+-.*Error: illegal operands `vwmacc.vv v4,v2,v5'
+-.*Error: illegal operands `vwmacc.vv v0,v2,v4,v0.t'
+-.*Error: illegal operands `vwmacc.vx v1,a1,v2'
+-.*Error: illegal operands `vwmacc.vx v2,a1,v2'
+-.*Error: illegal operands `vwmacc.vx v2,a1,v3'
+-.*Error: illegal operands `vwmacc.vx v0,a1,v2,v0.t'
+-.*Error: illegal operands `vwmaccsu.vv v1,v2,v4'
+-.*Error: illegal operands `vwmaccsu.vv v2,v2,v4'
+-.*Error: illegal operands `vwmaccsu.vv v2,v3,v4'
+-.*Error: illegal operands `vwmaccsu.vv v4,v2,v4'
+-.*Error: illegal operands `vwmaccsu.vv v4,v2,v5'
+-.*Error: illegal operands `vwmaccsu.vv v0,v2,v4,v0.t'
+-.*Error: illegal operands `vwmaccsu.vx v1,a1,v2'
+-.*Error: illegal operands `vwmaccsu.vx v2,a1,v2'
+-.*Error: illegal operands `vwmaccsu.vx v2,a1,v3'
+-.*Error: illegal operands `vwmaccsu.vx v0,a1,v2,v0.t'
+-.*Error: illegal operands `vwmaccus.vx v1,a1,v2'
+-.*Error: illegal operands `vwmaccus.vx v2,a1,v2'
+-.*Error: illegal operands `vwmaccus.vx v2,a1,v3'
+-.*Error: illegal operands `vwmaccus.vx v0,a1,v2,v0.t'
+-.*Error: illegal operands `vfwadd.vv v1,v2,v4'
+-.*Error: illegal operands `vfwadd.vv v2,v2,v4'
+-.*Error: illegal operands `vfwadd.vv v2,v3,v4'
+-.*Error: illegal operands `vfwadd.vv v4,v2,v4'
+-.*Error: illegal operands `vfwadd.vv v4,v2,v5'
+-.*Error: illegal operands `vfwadd.vv v0,v2,v4,v0.t'
+-.*Error: illegal operands `vfwadd.vf v1,v2,fa1'
+-.*Error: illegal operands `vfwadd.vf v2,v2,fa1'
+-.*Error: illegal operands `vfwadd.vf v2,v3,fa1'
+-.*Error: illegal operands `vfwadd.vf v0,v2,fa1,v0.t'
+-.*Error: illegal operands `vfwadd.wv v1,v2,v4'
+-.*Error: illegal operands `vfwadd.wv v2,v3,v4'
+-.*Error: illegal operands `vfwadd.wv v4,v2,v4'
+-.*Error: illegal operands `vfwadd.wv v4,v2,v5'
+-.*Error: illegal operands `vfwadd.wv v0,v2,v4,v0.t'
+-.*Error: illegal operands `vfwsub.vv v1,v2,v4'
+-.*Error: illegal operands `vfwsub.vv v2,v2,v4'
+-.*Error: illegal operands `vfwsub.vv v2,v3,v4'
+-.*Error: illegal operands `vfwsub.vv v4,v2,v4'
+-.*Error: illegal operands `vfwsub.vv v4,v2,v5'
+-.*Error: illegal operands `vfwsub.vv v0,v2,v4,v0.t'
+-.*Error: illegal operands `vfwsub.vf v1,v2,fa1'
+-.*Error: illegal operands `vfwsub.vf v2,v2,fa1'
+-.*Error: illegal operands `vfwsub.vf v2,v3,fa1'
+-.*Error: illegal operands `vfwsub.vf v0,v2,fa1,v0.t'
+-.*Error: illegal operands `vfwsub.wv v1,v2,v4'
+-.*Error: illegal operands `vfwsub.wv v2,v3,v4'
+-.*Error: illegal operands `vfwsub.wv v4,v2,v4'
+-.*Error: illegal operands `vfwsub.wv v4,v2,v5'
+-.*Error: illegal operands `vfwsub.wv v0,v2,v4,v0.t'
+-.*Error: illegal operands `vfwmul.vv v1,v2,v4'
+-.*Error: illegal operands `vfwmul.vv v2,v2,v4'
+-.*Error: illegal operands `vfwmul.vv v2,v3,v4'
+-.*Error: illegal operands `vfwmul.vv v4,v2,v4'
+-.*Error: illegal operands `vfwmul.vv v4,v2,v5'
+-.*Error: illegal operands `vfwmul.vv v0,v2,v4,v0.t'
+-.*Error: illegal operands `vfwsub.vf v1,v2,fa1'
+-.*Error: illegal operands `vfwsub.vf v2,v2,fa1'
+-.*Error: illegal operands `vfwsub.vf v2,v3,fa1'
+-.*Error: illegal operands `vfwsub.vf v0,v2,fa1,v0.t'
+-.*Error: illegal operands `vfwmacc.vv v1,v2,v4'
+-.*Error: illegal operands `vfwmacc.vv v2,v2,v4'
+-.*Error: illegal operands `vfwmacc.vv v2,v3,v4'
+-.*Error: illegal operands `vfwmacc.vv v4,v2,v4'
+-.*Error: illegal operands `vfwmacc.vv v4,v2,v5'
+-.*Error: illegal operands `vfwmacc.vv v0,v2,v4,v0.t'
+-.*Error: illegal operands `vfwmacc.vf v1,fa1,v2'
+-.*Error: illegal operands `vfwmacc.vf v2,fa1,v2'
+-.*Error: illegal operands `vfwmacc.vf v2,fa1,v3'
+-.*Error: illegal operands `vfwmacc.vf v0,fa1,v2,v0.t'
+-.*Error: illegal operands `vfwnmacc.vv v1,v2,v4'
+-.*Error: illegal operands `vfwnmacc.vv v2,v2,v4'
+-.*Error: illegal operands `vfwnmacc.vv v2,v3,v4'
+-.*Error: illegal operands `vfwnmacc.vv v4,v2,v4'
+-.*Error: illegal operands `vfwnmacc.vv v4,v2,v5'
+-.*Error: illegal operands `vfwnmacc.vv v0,v2,v4,v0.t'
+-.*Error: illegal operands `vfwnmacc.vf v1,fa1,v2'
+-.*Error: illegal operands `vfwnmacc.vf v2,fa1,v2'
+-.*Error: illegal operands `vfwnmacc.vf v2,fa1,v3'
+-.*Error: illegal operands `vfwnmacc.vf v0,fa1,v2,v0.t'
+-.*Error: illegal operands `vfwmsac.vv v1,v2,v4'
+-.*Error: illegal operands `vfwmsac.vv v2,v2,v4'
+-.*Error: illegal operands `vfwmsac.vv v2,v3,v4'
+-.*Error: illegal operands `vfwmsac.vv v4,v2,v4'
+-.*Error: illegal operands `vfwmsac.vv v4,v2,v5'
+-.*Error: illegal operands `vfwmsac.vv v0,v2,v4,v0.t'
+-.*Error: illegal operands `vfwmsac.vf v1,fa1,v2'
+-.*Error: illegal operands `vfwmsac.vf v2,fa1,v2'
+-.*Error: illegal operands `vfwmsac.vf v2,fa1,v3'
+-.*Error: illegal operands `vfwmsac.vf v0,fa1,v2,v0.t'
+-.*Error: illegal operands `vfwnmsac.vv v1,v2,v4'
+-.*Error: illegal operands `vfwnmsac.vv v2,v2,v4'
+-.*Error: illegal operands `vfwnmsac.vv v2,v3,v4'
+-.*Error: illegal operands `vfwnmsac.vv v4,v2,v4'
+-.*Error: illegal operands `vfwnmsac.vv v4,v2,v5'
+-.*Error: illegal operands `vfwnmsac.vv v0,v2,v4,v0.t'
+-.*Error: illegal operands `vfwnmsac.vf v1,fa1,v2'
+-.*Error: illegal operands `vfwnmsac.vf v2,fa1,v2'
+-.*Error: illegal operands `vfwnmsac.vf v2,fa1,v3'
+-.*Error: illegal operands `vfwnmsac.vf v0,fa1,v2,v0.t'
+-.*Error: illegal operands `vfwcvt.xu.f.v v1,v2'
+-.*Error: illegal operands `vfwcvt.xu.f.v v2,v2'
+-.*Error: illegal operands `vfwcvt.xu.f.v v2,v3'
+-.*Error: illegal operands `vfwcvt.xu.f.v v0,v2,v0.t'
+-.*Error: illegal operands `vfwcvt.x.f.v v1,v2'
+-.*Error: illegal operands `vfwcvt.x.f.v v2,v2'
+-.*Error: illegal operands `vfwcvt.x.f.v v2,v3'
+-.*Error: illegal operands `vfwcvt.x.f.v v0,v2,v0.t'
+-.*Error: illegal operands `vfwcvt.rtz.xu.f.v v1,v2'
+-.*Error: illegal operands `vfwcvt.rtz.xu.f.v v2,v2'
+-.*Error: illegal operands `vfwcvt.rtz.xu.f.v v2,v3'
+-.*Error: illegal operands `vfwcvt.rtz.xu.f.v v0,v2,v0.t'
+-.*Error: illegal operands `vfwcvt.rtz.x.f.v v1,v2'
+-.*Error: illegal operands `vfwcvt.rtz.x.f.v v2,v2'
+-.*Error: illegal operands `vfwcvt.rtz.x.f.v v2,v3'
+-.*Error: illegal operands `vfwcvt.rtz.x.f.v v0,v2,v0.t'
+-.*Error: illegal operands `vfwcvt.f.xu.v v1,v2'
+-.*Error: illegal operands `vfwcvt.f.xu.v v2,v2'
+-.*Error: illegal operands `vfwcvt.f.xu.v v2,v3'
+-.*Error: illegal operands `vfwcvt.f.xu.v v0,v2,v0.t'
+-.*Error: illegal operands `vfwcvt.f.x.v v1,v2'
+-.*Error: illegal operands `vfwcvt.f.x.v v2,v2'
+-.*Error: illegal operands `vfwcvt.f.x.v v2,v3'
+-.*Error: illegal operands `vfwcvt.f.x.v v0,v2,v0.t'
+-.*Error: illegal operands `vfwcvt.f.f.v v1,v2'
+-.*Error: illegal operands `vfwcvt.f.f.v v2,v2'
+-.*Error: illegal operands `vfwcvt.f.f.v v2,v3'
+-.*Error: illegal operands `vfwcvt.f.f.v v0,v2,v0.t'
++.*Error: illegal operands vd must be multiple of 2 `vwcvtu.x.x.v v1,v2'
++.*Error: illegal operands vd cannot overlap vs2 `vwcvtu.x.x.v v2,v2'
++.*Error: illegal operands vd cannot overlap vs2 `vwcvtu.x.x.v v2,v3'
++.*Error: illegal operands vd cannot overlap vm `vwcvtu.x.x.v v0,v2,v0.t'
++.*Error: illegal operands vd must be multiple of 2 `vwcvt.x.x.v v1,v2'
++.*Error: illegal operands vd cannot overlap vs2 `vwcvt.x.x.v v2,v2'
++.*Error: illegal operands vd cannot overlap vs2 `vwcvt.x.x.v v2,v3'
++.*Error: illegal operands vd cannot overlap vm `vwcvt.x.x.v v0,v2,v0.t'
++.*Error: illegal operands vd must be multiple of 2 `vwaddu.vv v1,v2,v4'
++.*Error: illegal operands vd cannot overlap vs2 `vwaddu.vv v2,v2,v4'
++.*Error: illegal operands vd cannot overlap vs2 `vwaddu.vv v2,v3,v4'
++.*Error: illegal operands vd cannot overlap vs1 `vwaddu.vv v4,v2,v4'
++.*Error: illegal operands vd cannot overlap vs1 `vwaddu.vv v4,v2,v5'
++.*Error: illegal operands vd cannot overlap vm `vwaddu.vv v0,v2,v4,v0.t'
++.*Error: illegal operands vd must be multiple of 2 `vwaddu.vx v1,v2,a1'
++.*Error: illegal operands vd cannot overlap vs2 `vwaddu.vx v2,v2,a1'
++.*Error: illegal operands vd cannot overlap vs2 `vwaddu.vx v2,v3,a1'
++.*Error: illegal operands vd cannot overlap vm `vwaddu.vx v0,v2,a1,v0.t'
++.*Error: illegal operands vd must be multiple of 2 `vwaddu.wv v1,v2,v4'
++.*Error: illegal operands vs2 must be multiple of 2 `vwaddu.wv v2,v3,v4'
++.*Error: illegal operands vd cannot overlap vs1 `vwaddu.wv v4,v2,v4'
++.*Error: illegal operands vd cannot overlap vs1 `vwaddu.wv v4,v2,v5'
++.*Error: illegal operands vd cannot overlap vm `vwaddu.wv v0,v2,v4,v0.t'
++.*Error: illegal operands vd must be multiple of 2 `vwaddu.wx v1,v2,a1'
++.*Error: illegal operands vs2 must be multiple of 2 `vwaddu.wx v2,v3,a1'
++.*Error: illegal operands vd cannot overlap vm `vwaddu.wx v0,v2,a1,v0.t'
++.*Error: illegal operands vd must be multiple of 2 `vwsubu.vv v1,v2,v4'
++.*Error: illegal operands vd cannot overlap vs2 `vwsubu.vv v2,v2,v4'
++.*Error: illegal operands vd cannot overlap vs2 `vwsubu.vv v2,v3,v4'
++.*Error: illegal operands vd cannot overlap vs1 `vwsubu.vv v4,v2,v4'
++.*Error: illegal operands vd cannot overlap vs1 `vwsubu.vv v4,v2,v5'
++.*Error: illegal operands vd cannot overlap vm `vwsubu.vv v0,v2,v4,v0.t'
++.*Error: illegal operands vd must be multiple of 2 `vwsubu.vx v1,v2,a1'
++.*Error: illegal operands vd cannot overlap vs2 `vwsubu.vx v2,v2,a1'
++.*Error: illegal operands vd cannot overlap vs2 `vwsubu.vx v2,v3,a1'
++.*Error: illegal operands vd cannot overlap vm `vwsubu.vx v0,v2,a1,v0.t'
++.*Error: illegal operands vd must be multiple of 2 `vwsubu.wv v1,v2,v4'
++.*Error: illegal operands vs2 must be multiple of 2 `vwsubu.wv v2,v3,v4'
++.*Error: illegal operands vd cannot overlap vs1 `vwsubu.wv v4,v2,v4'
++.*Error: illegal operands vd cannot overlap vs1 `vwsubu.wv v4,v2,v5'
++.*Error: illegal operands vd cannot overlap vm `vwsubu.wv v0,v2,v4,v0.t'
++.*Error: illegal operands vd must be multiple of 2 `vwsubu.wx v1,v2,a1'
++.*Error: illegal operands vs2 must be multiple of 2 `vwsubu.wx v2,v3,a1'
++.*Error: illegal operands vd cannot overlap vm `vwsubu.wx v0,v2,a1,v0.t'
++.*Error: illegal operands vd must be multiple of 2 `vwadd.vv v1,v2,v4'
++.*Error: illegal operands vd cannot overlap vs2 `vwadd.vv v2,v2,v4'
++.*Error: illegal operands vd cannot overlap vs2 `vwadd.vv v2,v3,v4'
++.*Error: illegal operands vd cannot overlap vs1 `vwadd.vv v4,v2,v4'
++.*Error: illegal operands vd cannot overlap vs1 `vwadd.vv v4,v2,v5'
++.*Error: illegal operands vd cannot overlap vm `vwadd.vv v0,v2,v4,v0.t'
++.*Error: illegal operands vd must be multiple of 2 `vwadd.vx v1,v2,a1'
++.*Error: illegal operands vd cannot overlap vs2 `vwadd.vx v2,v2,a1'
++.*Error: illegal operands vd cannot overlap vs2 `vwadd.vx v2,v3,a1'
++.*Error: illegal operands vd cannot overlap vm `vwadd.vx v0,v2,a1,v0.t'
++.*Error: illegal operands vd must be multiple of 2 `vwadd.wv v1,v2,v4'
++.*Error: illegal operands vs2 must be multiple of 2 `vwadd.wv v2,v3,v4'
++.*Error: illegal operands vd cannot overlap vs1 `vwadd.wv v4,v2,v4'
++.*Error: illegal operands vd cannot overlap vs1 `vwadd.wv v4,v2,v5'
++.*Error: illegal operands vd cannot overlap vm `vwadd.wv v0,v2,v4,v0.t'
++.*Error: illegal operands vd must be multiple of 2 `vwadd.wx v1,v2,a1'
++.*Error: illegal operands vs2 must be multiple of 2 `vwadd.wx v2,v3,a1'
++.*Error: illegal operands vd cannot overlap vm `vwadd.wx v0,v2,a1,v0.t'
++.*Error: illegal operands vd must be multiple of 2 `vwsub.vv v1,v2,v4'
++.*Error: illegal operands vd cannot overlap vs2 `vwsub.vv v2,v2,v4'
++.*Error: illegal operands vd cannot overlap vs2 `vwsub.vv v2,v3,v4'
++.*Error: illegal operands vd cannot overlap vs1 `vwsub.vv v4,v2,v4'
++.*Error: illegal operands vd cannot overlap vs1 `vwsub.vv v4,v2,v5'
++.*Error: illegal operands vd cannot overlap vm `vwsub.vv v0,v2,v4,v0.t'
++.*Error: illegal operands vd must be multiple of 2 `vwsub.vx v1,v2,a1'
++.*Error: illegal operands vd cannot overlap vs2 `vwsub.vx v2,v2,a1'
++.*Error: illegal operands vd cannot overlap vs2 `vwsub.vx v2,v3,a1'
++.*Error: illegal operands vd cannot overlap vm `vwsub.vx v0,v2,a1,v0.t'
++.*Error: illegal operands vd must be multiple of 2 `vwsub.wv v1,v2,v4'
++.*Error: illegal operands vs2 must be multiple of 2 `vwsub.wv v2,v3,v4'
++.*Error: illegal operands vd cannot overlap vs1 `vwsub.wv v4,v2,v4'
++.*Error: illegal operands vd cannot overlap vs1 `vwsub.wv v4,v2,v5'
++.*Error: illegal operands vd cannot overlap vm `vwsub.wv v0,v2,v4,v0.t'
++.*Error: illegal operands vd must be multiple of 2 `vwsub.wx v1,v2,a1'
++.*Error: illegal operands vs2 must be multiple of 2 `vwsub.wx v2,v3,a1'
++.*Error: illegal operands vd cannot overlap vm `vwsub.wx v0,v2,a1,v0.t'
++.*Error: illegal operands vd must be multiple of 2 `vwmul.vv v1,v2,v4'
++.*Error: illegal operands vd cannot overlap vs2 `vwmul.vv v2,v2,v4'
++.*Error: illegal operands vd cannot overlap vs2 `vwmul.vv v2,v3,v4'
++.*Error: illegal operands vd cannot overlap vs1 `vwmul.vv v4,v2,v4'
++.*Error: illegal operands vd cannot overlap vs1 `vwmul.vv v4,v2,v5'
++.*Error: illegal operands vd cannot overlap vm `vwmul.vv v0,v2,v4,v0.t'
++.*Error: illegal operands vd must be multiple of 2 `vwmul.vx v1,v2,a1'
++.*Error: illegal operands vd cannot overlap vs2 `vwmul.vx v2,v2,a1'
++.*Error: illegal operands vd cannot overlap vs2 `vwmul.vx v2,v3,a1'
++.*Error: illegal operands vd cannot overlap vm `vwmul.vx v0,v2,a1,v0.t'
++.*Error: illegal operands vd must be multiple of 2 `vwmulu.vv v1,v2,v4'
++.*Error: illegal operands vd cannot overlap vs2 `vwmulu.vv v2,v2,v4'
++.*Error: illegal operands vd cannot overlap vs2 `vwmulu.vv v2,v3,v4'
++.*Error: illegal operands vd cannot overlap vs1 `vwmulu.vv v4,v2,v4'
++.*Error: illegal operands vd cannot overlap vs1 `vwmulu.vv v4,v2,v5'
++.*Error: illegal operands vd cannot overlap vm `vwmulu.vv v0,v2,v4,v0.t'
++.*Error: illegal operands vd must be multiple of 2 `vwmulu.vx v1,v2,a1'
++.*Error: illegal operands vd cannot overlap vs2 `vwmulu.vx v2,v2,a1'
++.*Error: illegal operands vd cannot overlap vs2 `vwmulu.vx v2,v3,a1'
++.*Error: illegal operands vd cannot overlap vm `vwmulu.vx v0,v2,a1,v0.t'
++.*Error: illegal operands vd must be multiple of 2 `vwmulsu.vv v1,v2,v4'
++.*Error: illegal operands vd cannot overlap vs2 `vwmulsu.vv v2,v2,v4'
++.*Error: illegal operands vd cannot overlap vs2 `vwmulsu.vv v2,v3,v4'
++.*Error: illegal operands vd cannot overlap vs1 `vwmulsu.vv v4,v2,v4'
++.*Error: illegal operands vd cannot overlap vs1 `vwmulsu.vv v4,v2,v5'
++.*Error: illegal operands vd cannot overlap vm `vwmulsu.vv v0,v2,v4,v0.t'
++.*Error: illegal operands vd must be multiple of 2 `vwmulsu.vx v1,v2,a1'
++.*Error: illegal operands vd cannot overlap vs2 `vwmulsu.vx v2,v2,a1'
++.*Error: illegal operands vd cannot overlap vs2 `vwmulsu.vx v2,v3,a1'
++.*Error: illegal operands vd cannot overlap vm `vwmulsu.vx v0,v2,a1,v0.t'
++.*Error: illegal operands vd must be multiple of 2 `vwmaccu.vv v1,v2,v4'
++.*Error: illegal operands vd cannot overlap vs1 `vwmaccu.vv v2,v2,v4'
++.*Error: illegal operands vd cannot overlap vs1 `vwmaccu.vv v2,v3,v4'
++.*Error: illegal operands vd cannot overlap vs2 `vwmaccu.vv v4,v2,v4'
++.*Error: illegal operands vd cannot overlap vs2 `vwmaccu.vv v4,v2,v5'
++.*Error: illegal operands vd cannot overlap vm `vwmaccu.vv v0,v2,v4,v0.t'
++.*Error: illegal operands vd must be multiple of 2 `vwmaccu.vx v1,a1,v2'
++.*Error: illegal operands vd cannot overlap vs2 `vwmaccu.vx v2,a1,v2'
++.*Error: illegal operands vd cannot overlap vs2 `vwmaccu.vx v2,a1,v3'
++.*Error: illegal operands vd cannot overlap vm `vwmaccu.vx v0,a1,v2,v0.t'
++.*Error: illegal operands vd must be multiple of 2 `vwmacc.vv v1,v2,v4'
++.*Error: illegal operands vd cannot overlap vs1 `vwmacc.vv v2,v2,v4'
++.*Error: illegal operands vd cannot overlap vs1 `vwmacc.vv v2,v3,v4'
++.*Error: illegal operands vd cannot overlap vs2 `vwmacc.vv v4,v2,v4'
++.*Error: illegal operands vd cannot overlap vs2 `vwmacc.vv v4,v2,v5'
++.*Error: illegal operands vd cannot overlap vm `vwmacc.vv v0,v2,v4,v0.t'
++.*Error: illegal operands vd must be multiple of 2 `vwmacc.vx v1,a1,v2'
++.*Error: illegal operands vd cannot overlap vs2 `vwmacc.vx v2,a1,v2'
++.*Error: illegal operands vd cannot overlap vs2 `vwmacc.vx v2,a1,v3'
++.*Error: illegal operands vd cannot overlap vm `vwmacc.vx v0,a1,v2,v0.t'
++.*Error: illegal operands vd must be multiple of 2 `vwmaccsu.vv v1,v2,v4'
++.*Error: illegal operands vd cannot overlap vs1 `vwmaccsu.vv v2,v2,v4'
++.*Error: illegal operands vd cannot overlap vs1 `vwmaccsu.vv v2,v3,v4'
++.*Error: illegal operands vd cannot overlap vs2 `vwmaccsu.vv v4,v2,v4'
++.*Error: illegal operands vd cannot overlap vs2 `vwmaccsu.vv v4,v2,v5'
++.*Error: illegal operands vd cannot overlap vm `vwmaccsu.vv v0,v2,v4,v0.t'
++.*Error: illegal operands vd must be multiple of 2 `vwmaccsu.vx v1,a1,v2'
++.*Error: illegal operands vd cannot overlap vs2 `vwmaccsu.vx v2,a1,v2'
++.*Error: illegal operands vd cannot overlap vs2 `vwmaccsu.vx v2,a1,v3'
++.*Error: illegal operands vd cannot overlap vm `vwmaccsu.vx v0,a1,v2,v0.t'
++.*Error: illegal operands vd must be multiple of 2 `vwmaccus.vx v1,a1,v2'
++.*Error: illegal operands vd cannot overlap vs2 `vwmaccus.vx v2,a1,v2'
++.*Error: illegal operands vd cannot overlap vs2 `vwmaccus.vx v2,a1,v3'
++.*Error: illegal operands vd cannot overlap vm `vwmaccus.vx v0,a1,v2,v0.t'
++.*Error: illegal operands vd must be multiple of 2 `vfwadd.vv v1,v2,v4'
++.*Error: illegal operands vd cannot overlap vs2 `vfwadd.vv v2,v2,v4'
++.*Error: illegal operands vd cannot overlap vs2 `vfwadd.vv v2,v3,v4'
++.*Error: illegal operands vd cannot overlap vs1 `vfwadd.vv v4,v2,v4'
++.*Error: illegal operands vd cannot overlap vs1 `vfwadd.vv v4,v2,v5'
++.*Error: illegal operands vd cannot overlap vm `vfwadd.vv v0,v2,v4,v0.t'
++.*Error: illegal operands vd must be multiple of 2 `vfwadd.vf v1,v2,fa1'
++.*Error: illegal operands vd cannot overlap vs2 `vfwadd.vf v2,v2,fa1'
++.*Error: illegal operands vd cannot overlap vs2 `vfwadd.vf v2,v3,fa1'
++.*Error: illegal operands vd cannot overlap vm `vfwadd.vf v0,v2,fa1,v0.t'
++.*Error: illegal operands vd must be multiple of 2 `vfwadd.wv v1,v2,v4'
++.*Error: illegal operands vs2 must be multiple of 2 `vfwadd.wv v2,v3,v4'
++.*Error: illegal operands vd cannot overlap vs1 `vfwadd.wv v4,v2,v4'
++.*Error: illegal operands vd cannot overlap vs1 `vfwadd.wv v4,v2,v5'
++.*Error: illegal operands vd cannot overlap vm `vfwadd.wv v0,v2,v4,v0.t'
++.*Error: illegal operands vd must be multiple of 2 `vfwsub.vv v1,v2,v4'
++.*Error: illegal operands vd cannot overlap vs2 `vfwsub.vv v2,v2,v4'
++.*Error: illegal operands vd cannot overlap vs2 `vfwsub.vv v2,v3,v4'
++.*Error: illegal operands vd cannot overlap vs1 `vfwsub.vv v4,v2,v4'
++.*Error: illegal operands vd cannot overlap vs1 `vfwsub.vv v4,v2,v5'
++.*Error: illegal operands vd cannot overlap vm `vfwsub.vv v0,v2,v4,v0.t'
++.*Error: illegal operands vd must be multiple of 2 `vfwsub.vf v1,v2,fa1'
++.*Error: illegal operands vd cannot overlap vs2 `vfwsub.vf v2,v2,fa1'
++.*Error: illegal operands vd cannot overlap vs2 `vfwsub.vf v2,v3,fa1'
++.*Error: illegal operands vd cannot overlap vm `vfwsub.vf v0,v2,fa1,v0.t'
++.*Error: illegal operands vd must be multiple of 2 `vfwsub.wv v1,v2,v4'
++.*Error: illegal operands vs2 must be multiple of 2 `vfwsub.wv v2,v3,v4'
++.*Error: illegal operands vd cannot overlap vs1 `vfwsub.wv v4,v2,v4'
++.*Error: illegal operands vd cannot overlap vs1 `vfwsub.wv v4,v2,v5'
++.*Error: illegal operands vd cannot overlap vm `vfwsub.wv v0,v2,v4,v0.t'
++.*Error: illegal operands vd must be multiple of 2 `vfwmul.vv v1,v2,v4'
++.*Error: illegal operands vd cannot overlap vs2 `vfwmul.vv v2,v2,v4'
++.*Error: illegal operands vd cannot overlap vs2 `vfwmul.vv v2,v3,v4'
++.*Error: illegal operands vd cannot overlap vs1 `vfwmul.vv v4,v2,v4'
++.*Error: illegal operands vd cannot overlap vs1 `vfwmul.vv v4,v2,v5'
++.*Error: illegal operands vd cannot overlap vm `vfwmul.vv v0,v2,v4,v0.t'
++.*Error: illegal operands vd must be multiple of 2 `vfwsub.vf v1,v2,fa1'
++.*Error: illegal operands vd cannot overlap vs2 `vfwsub.vf v2,v2,fa1'
++.*Error: illegal operands vd cannot overlap vs2 `vfwsub.vf v2,v3,fa1'
++.*Error: illegal operands vd cannot overlap vm `vfwsub.vf v0,v2,fa1,v0.t'
++.*Error: illegal operands vd must be multiple of 2 `vfwmacc.vv v1,v2,v4'
++.*Error: illegal operands vd cannot overlap vs1 `vfwmacc.vv v2,v2,v4'
++.*Error: illegal operands vd cannot overlap vs1 `vfwmacc.vv v2,v3,v4'
++.*Error: illegal operands vd cannot overlap vs2 `vfwmacc.vv v4,v2,v4'
++.*Error: illegal operands vd cannot overlap vs2 `vfwmacc.vv v4,v2,v5'
++.*Error: illegal operands vd cannot overlap vm `vfwmacc.vv v0,v2,v4,v0.t'
++.*Error: illegal operands vd must be multiple of 2 `vfwmacc.vf v1,fa1,v2'
++.*Error: illegal operands vd cannot overlap vs2 `vfwmacc.vf v2,fa1,v2'
++.*Error: illegal operands vd cannot overlap vs2 `vfwmacc.vf v2,fa1,v3'
++.*Error: illegal operands vd cannot overlap vm `vfwmacc.vf v0,fa1,v2,v0.t'
++.*Error: illegal operands vd must be multiple of 2 `vfwnmacc.vv v1,v2,v4'
++.*Error: illegal operands vd cannot overlap vs1 `vfwnmacc.vv v2,v2,v4'
++.*Error: illegal operands vd cannot overlap vs1 `vfwnmacc.vv v2,v3,v4'
++.*Error: illegal operands vd cannot overlap vs2 `vfwnmacc.vv v4,v2,v4'
++.*Error: illegal operands vd cannot overlap vs2 `vfwnmacc.vv v4,v2,v5'
++.*Error: illegal operands vd cannot overlap vm `vfwnmacc.vv v0,v2,v4,v0.t'
++.*Error: illegal operands vd must be multiple of 2 `vfwnmacc.vf v1,fa1,v2'
++.*Error: illegal operands vd cannot overlap vs2 `vfwnmacc.vf v2,fa1,v2'
++.*Error: illegal operands vd cannot overlap vs2 `vfwnmacc.vf v2,fa1,v3'
++.*Error: illegal operands vd cannot overlap vm `vfwnmacc.vf v0,fa1,v2,v0.t'
++.*Error: illegal operands vd must be multiple of 2 `vfwmsac.vv v1,v2,v4'
++.*Error: illegal operands vd cannot overlap vs1 `vfwmsac.vv v2,v2,v4'
++.*Error: illegal operands vd cannot overlap vs1 `vfwmsac.vv v2,v3,v4'
++.*Error: illegal operands vd cannot overlap vs2 `vfwmsac.vv v4,v2,v4'
++.*Error: illegal operands vd cannot overlap vs2 `vfwmsac.vv v4,v2,v5'
++.*Error: illegal operands vd cannot overlap vm `vfwmsac.vv v0,v2,v4,v0.t'
++.*Error: illegal operands vd must be multiple of 2 `vfwmsac.vf v1,fa1,v2'
++.*Error: illegal operands vd cannot overlap vs2 `vfwmsac.vf v2,fa1,v2'
++.*Error: illegal operands vd cannot overlap vs2 `vfwmsac.vf v2,fa1,v3'
++.*Error: illegal operands vd cannot overlap vm `vfwmsac.vf v0,fa1,v2,v0.t'
++.*Error: illegal operands vd must be multiple of 2 `vfwnmsac.vv v1,v2,v4'
++.*Error: illegal operands vd cannot overlap vs1 `vfwnmsac.vv v2,v2,v4'
++.*Error: illegal operands vd cannot overlap vs1 `vfwnmsac.vv v2,v3,v4'
++.*Error: illegal operands vd cannot overlap vs2 `vfwnmsac.vv v4,v2,v4'
++.*Error: illegal operands vd cannot overlap vs2 `vfwnmsac.vv v4,v2,v5'
++.*Error: illegal operands vd cannot overlap vm `vfwnmsac.vv v0,v2,v4,v0.t'
++.*Error: illegal operands vd must be multiple of 2 `vfwnmsac.vf v1,fa1,v2'
++.*Error: illegal operands vd cannot overlap vs2 `vfwnmsac.vf v2,fa1,v2'
++.*Error: illegal operands vd cannot overlap vs2 `vfwnmsac.vf v2,fa1,v3'
++.*Error: illegal operands vd cannot overlap vm `vfwnmsac.vf v0,fa1,v2,v0.t'
++.*Error: illegal operands vd must be multiple of 2 `vfwcvt.xu.f.v v1,v2'
++.*Error: illegal operands vd cannot overlap vs2 `vfwcvt.xu.f.v v2,v2'
++.*Error: illegal operands vd cannot overlap vs2 `vfwcvt.xu.f.v v2,v3'
++.*Error: illegal operands vd cannot overlap vm `vfwcvt.xu.f.v v0,v2,v0.t'
++.*Error: illegal operands vd must be multiple of 2 `vfwcvt.x.f.v v1,v2'
++.*Error: illegal operands vd cannot overlap vs2 `vfwcvt.x.f.v v2,v2'
++.*Error: illegal operands vd cannot overlap vs2 `vfwcvt.x.f.v v2,v3'
++.*Error: illegal operands vd cannot overlap vm `vfwcvt.x.f.v v0,v2,v0.t'
++.*Error: illegal operands vd must be multiple of 2 `vfwcvt.rtz.xu.f.v v1,v2'
++.*Error: illegal operands vd cannot overlap vs2 `vfwcvt.rtz.xu.f.v v2,v2'
++.*Error: illegal operands vd cannot overlap vs2 `vfwcvt.rtz.xu.f.v v2,v3'
++.*Error: illegal operands vd cannot overlap vm `vfwcvt.rtz.xu.f.v v0,v2,v0.t'
++.*Error: illegal operands vd must be multiple of 2 `vfwcvt.rtz.x.f.v v1,v2'
++.*Error: illegal operands vd cannot overlap vs2 `vfwcvt.rtz.x.f.v v2,v2'
++.*Error: illegal operands vd cannot overlap vs2 `vfwcvt.rtz.x.f.v v2,v3'
++.*Error: illegal operands vd cannot overlap vm `vfwcvt.rtz.x.f.v v0,v2,v0.t'
++.*Error: illegal operands vd must be multiple of 2 `vfwcvt.f.xu.v v1,v2'
++.*Error: illegal operands vd cannot overlap vs2 `vfwcvt.f.xu.v v2,v2'
++.*Error: illegal operands vd cannot overlap vs2 `vfwcvt.f.xu.v v2,v3'
++.*Error: illegal operands vd cannot overlap vm `vfwcvt.f.xu.v v0,v2,v0.t'
++.*Error: illegal operands vd must be multiple of 2 `vfwcvt.f.x.v v1,v2'
++.*Error: illegal operands vd cannot overlap vs2 `vfwcvt.f.x.v v2,v2'
++.*Error: illegal operands vd cannot overlap vs2 `vfwcvt.f.x.v v2,v3'
++.*Error: illegal operands vd cannot overlap vm `vfwcvt.f.x.v v0,v2,v0.t'
++.*Error: illegal operands vd must be multiple of 2 `vfwcvt.f.f.v v1,v2'
++.*Error: illegal operands vd cannot overlap vs2 `vfwcvt.f.f.v v2,v2'
++.*Error: illegal operands vd cannot overlap vs2 `vfwcvt.f.f.v v2,v3'
++.*Error: illegal operands vd cannot overlap vm `vfwcvt.f.f.v v0,v2,v0.t'
+diff --git a/gas/testsuite/gas/riscv/vector-insns-fail-load-store.l b/gas/testsuite/gas/riscv/vector-insns-fail-load-store.l
+index 406d79e2b2..3e2a24390b 100644
+--- a/gas/testsuite/gas/riscv/vector-insns-fail-load-store.l
++++ b/gas/testsuite/gas/riscv/vector-insns-fail-load-store.l
+@@ -1,587 +1,587 @@
+ .*: Assembler messages:
+-.*Error: illegal operands `vle8.v v0,\(a0\),v0.t'
+-.*Error: illegal operands `vle8ff.v v0,\(a0\),v0.t'
+-.*Error: illegal operands `vle16.v v0,\(a0\),v0.t'
+-.*Error: illegal operands `vle16ff.v v0,\(a0\),v0.t'
+-.*Error: illegal operands `vle32.v v0,\(a0\),v0.t'
+-.*Error: illegal operands `vle32ff.v v0,\(a0\),v0.t'
+-.*Error: illegal operands `vle64.v v0,\(a0\),v0.t'
+-.*Error: illegal operands `vle64ff.v v0,\(a0\),v0.t'
+-.*Error: illegal operands `vle128.v v0,\(a0\),v0.t'
+-.*Error: illegal operands `vle128ff.v v0,\(a0\),v0.t'
+-.*Error: illegal operands `vle256.v v0,\(a0\),v0.t'
+-.*Error: illegal operands `vle256ff.v v0,\(a0\),v0.t'
+-.*Error: illegal operands `vle512.v v0,\(a0\),v0.t'
+-.*Error: illegal operands `vle512ff.v v0,\(a0\),v0.t'
+-.*Error: illegal operands `vle1024.v v0,\(a0\),v0.t'
+-.*Error: illegal operands `vle1024ff.v v0,\(a0\),v0.t'
+-.*Error: illegal operands `vse8.v v0,\(a0\),v0.t'
+-.*Error: illegal operands `vse16.v v0,\(a0\),v0.t'
+-.*Error: illegal operands `vse32.v v0,\(a0\),v0.t'
+-.*Error: illegal operands `vse64.v v0,\(a0\),v0.t'
+-.*Error: illegal operands `vse128.v v0,\(a0\),v0.t'
+-.*Error: illegal operands `vse256.v v0,\(a0\),v0.t'
+-.*Error: illegal operands `vse512.v v0,\(a0\),v0.t'
+-.*Error: illegal operands `vse1024.v v0,\(a0\),v0.t'
+-.*Error: illegal operands `vlse8.v v0,\(a0\),a1,v0.t'
+-.*Error: illegal operands `vlse16.v v0,\(a0\),a1,v0.t'
+-.*Error: illegal operands `vlse32.v v0,\(a0\),a1,v0.t'
+-.*Error: illegal operands `vlse64.v v0,\(a0\),a1,v0.t'
+-.*Error: illegal operands `vlse128.v v0,\(a0\),a1,v0.t'
+-.*Error: illegal operands `vlse256.v v0,\(a0\),a1,v0.t'
+-.*Error: illegal operands `vlse512.v v0,\(a0\),a1,v0.t'
+-.*Error: illegal operands `vlse1024.v v0,\(a0\),a1,v0.t'
+-.*Error: illegal operands `vsse8.v v0,\(a0\),a1,v0.t'
+-.*Error: illegal operands `vsse16.v v0,\(a0\),a1,v0.t'
+-.*Error: illegal operands `vsse32.v v0,\(a0\),a1,v0.t'
+-.*Error: illegal operands `vsse64.v v0,\(a0\),a1,v0.t'
+-.*Error: illegal operands `vsse128.v v0,\(a0\),a1,v0.t'
+-.*Error: illegal operands `vsse256.v v0,\(a0\),a1,v0.t'
+-.*Error: illegal operands `vsse512.v v0,\(a0\),a1,v0.t'
+-.*Error: illegal operands `vsse1024.v v0,\(a0\),a1,v0.t'
+-.*Error: illegal operands `vlxei8.v v0,\(a0\),v4,v0.t'
+-.*Error: illegal operands `vlxei16.v v0,\(a0\),v4,v0.t'
+-.*Error: illegal operands `vlxei32.v v0,\(a0\),v4,v0.t'
+-.*Error: illegal operands `vlxei64.v v0,\(a0\),v4,v0.t'
+-.*Error: illegal operands `vsxei8.v v0,\(a0\),v4,v0.t'
+-.*Error: illegal operands `vsxei16.v v0,\(a0\),v4,v0.t'
+-.*Error: illegal operands `vsxei32.v v0,\(a0\),v4,v0.t'
+-.*Error: illegal operands `vsxei64.v v0,\(a0\),v4,v0.t'
+-.*Error: illegal operands `vsuxei8.v v0,\(a0\),v4,v0.t'
+-.*Error: illegal operands `vsuxei16.v v0,\(a0\),v4,v0.t'
+-.*Error: illegal operands `vsuxei32.v v0,\(a0\),v4,v0.t'
+-.*Error: illegal operands `vsuxei64.v v0,\(a0\),v4,v0.t'
+-.*Error: illegal operands `vlseg2e8.v v0,\(a0\),v0.t'
+-.*Error: illegal operands `vsseg2e8.v v0,\(a0\),v0.t'
+-.*Error: illegal operands `vlseg2e8ff.v v0,\(a0\),v0.t'
+-.*Error: illegal operands `vlseg3e8.v v0,\(a0\),v0.t'
+-.*Error: illegal operands `vsseg3e8.v v0,\(a0\),v0.t'
+-.*Error: illegal operands `vlseg3e8ff.v v0,\(a0\),v0.t'
+-.*Error: illegal operands `vlseg4e8.v v0,\(a0\),v0.t'
+-.*Error: illegal operands `vsseg4e8.v v0,\(a0\),v0.t'
+-.*Error: illegal operands `vlseg4e8ff.v v0,\(a0\),v0.t'
+-.*Error: illegal operands `vlseg5e8.v v0,\(a0\),v0.t'
+-.*Error: illegal operands `vsseg5e8.v v0,\(a0\),v0.t'
+-.*Error: illegal operands `vlseg5e8ff.v v0,\(a0\),v0.t'
+-.*Error: illegal operands `vlseg6e8.v v0,\(a0\),v0.t'
+-.*Error: illegal operands `vsseg6e8.v v0,\(a0\),v0.t'
+-.*Error: illegal operands `vlseg6e8ff.v v0,\(a0\),v0.t'
+-.*Error: illegal operands `vlseg7e8.v v0,\(a0\),v0.t'
+-.*Error: illegal operands `vsseg7e8.v v0,\(a0\),v0.t'
+-.*Error: illegal operands `vlseg7e8ff.v v0,\(a0\),v0.t'
+-.*Error: illegal operands `vlseg8e8.v v0,\(a0\),v0.t'
+-.*Error: illegal operands `vsseg8e8.v v0,\(a0\),v0.t'
+-.*Error: illegal operands `vlseg8e8ff.v v0,\(a0\),v0.t'
+-.*Error: illegal operands `vlseg2e16.v v0,\(a0\),v0.t'
+-.*Error: illegal operands `vsseg2e16.v v0,\(a0\),v0.t'
+-.*Error: illegal operands `vlseg2e16ff.v v0,\(a0\),v0.t'
+-.*Error: illegal operands `vlseg3e16.v v0,\(a0\),v0.t'
+-.*Error: illegal operands `vsseg3e16.v v0,\(a0\),v0.t'
+-.*Error: illegal operands `vlseg3e16ff.v v0,\(a0\),v0.t'
+-.*Error: illegal operands `vlseg4e16.v v0,\(a0\),v0.t'
+-.*Error: illegal operands `vsseg4e16.v v0,\(a0\),v0.t'
+-.*Error: illegal operands `vlseg4e16ff.v v0,\(a0\),v0.t'
+-.*Error: illegal operands `vlseg5e16.v v0,\(a0\),v0.t'
+-.*Error: illegal operands `vsseg5e16.v v0,\(a0\),v0.t'
+-.*Error: illegal operands `vlseg5e16ff.v v0,\(a0\),v0.t'
+-.*Error: illegal operands `vlseg6e16.v v0,\(a0\),v0.t'
+-.*Error: illegal operands `vsseg6e16.v v0,\(a0\),v0.t'
+-.*Error: illegal operands `vlseg6e16ff.v v0,\(a0\),v0.t'
+-.*Error: illegal operands `vlseg7e16.v v0,\(a0\),v0.t'
+-.*Error: illegal operands `vsseg7e16.v v0,\(a0\),v0.t'
+-.*Error: illegal operands `vlseg7e16ff.v v0,\(a0\),v0.t'
+-.*Error: illegal operands `vlseg8e16.v v0,\(a0\),v0.t'
+-.*Error: illegal operands `vsseg8e16.v v0,\(a0\),v0.t'
+-.*Error: illegal operands `vlseg8e16ff.v v0,\(a0\),v0.t'
+-.*Error: illegal operands `vlseg2e32.v v0,\(a0\),v0.t'
+-.*Error: illegal operands `vsseg2e32.v v0,\(a0\),v0.t'
+-.*Error: illegal operands `vlseg2e32ff.v v0,\(a0\),v0.t'
+-.*Error: illegal operands `vlseg3e32.v v0,\(a0\),v0.t'
+-.*Error: illegal operands `vsseg3e32.v v0,\(a0\),v0.t'
+-.*Error: illegal operands `vlseg3e32ff.v v0,\(a0\),v0.t'
+-.*Error: illegal operands `vlseg4e32.v v0,\(a0\),v0.t'
+-.*Error: illegal operands `vsseg4e32.v v0,\(a0\),v0.t'
+-.*Error: illegal operands `vlseg4e32ff.v v0,\(a0\),v0.t'
+-.*Error: illegal operands `vlseg5e32.v v0,\(a0\),v0.t'
+-.*Error: illegal operands `vsseg5e32.v v0,\(a0\),v0.t'
+-.*Error: illegal operands `vlseg5e32ff.v v0,\(a0\),v0.t'
+-.*Error: illegal operands `vlseg6e32.v v0,\(a0\),v0.t'
+-.*Error: illegal operands `vsseg6e32.v v0,\(a0\),v0.t'
+-.*Error: illegal operands `vlseg6e32ff.v v0,\(a0\),v0.t'
+-.*Error: illegal operands `vlseg7e32.v v0,\(a0\),v0.t'
+-.*Error: illegal operands `vsseg7e32.v v0,\(a0\),v0.t'
+-.*Error: illegal operands `vlseg7e32ff.v v0,\(a0\),v0.t'
+-.*Error: illegal operands `vlseg8e32.v v0,\(a0\),v0.t'
+-.*Error: illegal operands `vsseg8e32.v v0,\(a0\),v0.t'
+-.*Error: illegal operands `vlseg8e32ff.v v0,\(a0\),v0.t'
+-.*Error: illegal operands `vlseg2e64.v v0,\(a0\),v0.t'
+-.*Error: illegal operands `vsseg2e64.v v0,\(a0\),v0.t'
+-.*Error: illegal operands `vlseg2e64ff.v v0,\(a0\),v0.t'
+-.*Error: illegal operands `vlseg3e64.v v0,\(a0\),v0.t'
+-.*Error: illegal operands `vsseg3e64.v v0,\(a0\),v0.t'
+-.*Error: illegal operands `vlseg3e64ff.v v0,\(a0\),v0.t'
+-.*Error: illegal operands `vlseg4e64.v v0,\(a0\),v0.t'
+-.*Error: illegal operands `vsseg4e64.v v0,\(a0\),v0.t'
+-.*Error: illegal operands `vlseg4e64ff.v v0,\(a0\),v0.t'
+-.*Error: illegal operands `vlseg5e64.v v0,\(a0\),v0.t'
+-.*Error: illegal operands `vsseg5e64.v v0,\(a0\),v0.t'
+-.*Error: illegal operands `vlseg5e64ff.v v0,\(a0\),v0.t'
+-.*Error: illegal operands `vlseg6e64.v v0,\(a0\),v0.t'
+-.*Error: illegal operands `vsseg6e64.v v0,\(a0\),v0.t'
+-.*Error: illegal operands `vlseg6e64ff.v v0,\(a0\),v0.t'
+-.*Error: illegal operands `vlseg7e64.v v0,\(a0\),v0.t'
+-.*Error: illegal operands `vsseg7e64.v v0,\(a0\),v0.t'
+-.*Error: illegal operands `vlseg7e64ff.v v0,\(a0\),v0.t'
+-.*Error: illegal operands `vlseg8e64.v v0,\(a0\),v0.t'
+-.*Error: illegal operands `vsseg8e64.v v0,\(a0\),v0.t'
+-.*Error: illegal operands `vlseg8e64ff.v v0,\(a0\),v0.t'
+-.*Error: illegal operands `vlseg2e128.v v0,\(a0\),v0.t'
+-.*Error: illegal operands `vsseg2e128.v v0,\(a0\),v0.t'
+-.*Error: illegal operands `vlseg2e128ff.v v0,\(a0\),v0.t'
+-.*Error: illegal operands `vlseg3e128.v v0,\(a0\),v0.t'
+-.*Error: illegal operands `vsseg3e128.v v0,\(a0\),v0.t'
+-.*Error: illegal operands `vlseg3e128ff.v v0,\(a0\),v0.t'
+-.*Error: illegal operands `vlseg4e128.v v0,\(a0\),v0.t'
+-.*Error: illegal operands `vsseg4e128.v v0,\(a0\),v0.t'
+-.*Error: illegal operands `vlseg4e128ff.v v0,\(a0\),v0.t'
+-.*Error: illegal operands `vlseg5e128.v v0,\(a0\),v0.t'
+-.*Error: illegal operands `vsseg5e128.v v0,\(a0\),v0.t'
+-.*Error: illegal operands `vlseg5e128ff.v v0,\(a0\),v0.t'
+-.*Error: illegal operands `vlseg6e128.v v0,\(a0\),v0.t'
+-.*Error: illegal operands `vsseg6e128.v v0,\(a0\),v0.t'
+-.*Error: illegal operands `vlseg6e128ff.v v0,\(a0\),v0.t'
+-.*Error: illegal operands `vlseg7e128.v v0,\(a0\),v0.t'
+-.*Error: illegal operands `vsseg7e128.v v0,\(a0\),v0.t'
+-.*Error: illegal operands `vlseg7e128ff.v v0,\(a0\),v0.t'
+-.*Error: illegal operands `vlseg8e128.v v0,\(a0\),v0.t'
+-.*Error: illegal operands `vsseg8e128.v v0,\(a0\),v0.t'
+-.*Error: illegal operands `vlseg8e128ff.v v0,\(a0\),v0.t'
+-.*Error: illegal operands `vlseg2e256.v v0,\(a0\),v0.t'
+-.*Error: illegal operands `vsseg2e256.v v0,\(a0\),v0.t'
+-.*Error: illegal operands `vlseg2e256ff.v v0,\(a0\),v0.t'
+-.*Error: illegal operands `vlseg3e256.v v0,\(a0\),v0.t'
+-.*Error: illegal operands `vsseg3e256.v v0,\(a0\),v0.t'
+-.*Error: illegal operands `vlseg3e256ff.v v0,\(a0\),v0.t'
+-.*Error: illegal operands `vlseg4e256.v v0,\(a0\),v0.t'
+-.*Error: illegal operands `vsseg4e256.v v0,\(a0\),v0.t'
+-.*Error: illegal operands `vlseg4e256ff.v v0,\(a0\),v0.t'
+-.*Error: illegal operands `vlseg5e256.v v0,\(a0\),v0.t'
+-.*Error: illegal operands `vsseg5e256.v v0,\(a0\),v0.t'
+-.*Error: illegal operands `vlseg5e256ff.v v0,\(a0\),v0.t'
+-.*Error: illegal operands `vlseg6e256.v v0,\(a0\),v0.t'
+-.*Error: illegal operands `vsseg6e256.v v0,\(a0\),v0.t'
+-.*Error: illegal operands `vlseg6e256ff.v v0,\(a0\),v0.t'
+-.*Error: illegal operands `vlseg7e256.v v0,\(a0\),v0.t'
+-.*Error: illegal operands `vsseg7e256.v v0,\(a0\),v0.t'
+-.*Error: illegal operands `vlseg7e256ff.v v0,\(a0\),v0.t'
+-.*Error: illegal operands `vlseg8e256.v v0,\(a0\),v0.t'
+-.*Error: illegal operands `vsseg8e256.v v0,\(a0\),v0.t'
+-.*Error: illegal operands `vlseg8e256ff.v v0,\(a0\),v0.t'
+-.*Error: illegal operands `vlseg2e512.v v0,\(a0\),v0.t'
+-.*Error: illegal operands `vsseg2e512.v v0,\(a0\),v0.t'
+-.*Error: illegal operands `vlseg2e512ff.v v0,\(a0\),v0.t'
+-.*Error: illegal operands `vlseg3e512.v v0,\(a0\),v0.t'
+-.*Error: illegal operands `vsseg3e512.v v0,\(a0\),v0.t'
+-.*Error: illegal operands `vlseg3e512ff.v v0,\(a0\),v0.t'
+-.*Error: illegal operands `vlseg4e512.v v0,\(a0\),v0.t'
+-.*Error: illegal operands `vsseg4e512.v v0,\(a0\),v0.t'
+-.*Error: illegal operands `vlseg4e512ff.v v0,\(a0\),v0.t'
+-.*Error: illegal operands `vlseg5e512.v v0,\(a0\),v0.t'
+-.*Error: illegal operands `vsseg5e512.v v0,\(a0\),v0.t'
+-.*Error: illegal operands `vlseg5e512ff.v v0,\(a0\),v0.t'
+-.*Error: illegal operands `vlseg6e512.v v0,\(a0\),v0.t'
+-.*Error: illegal operands `vsseg6e512.v v0,\(a0\),v0.t'
+-.*Error: illegal operands `vlseg6e512ff.v v0,\(a0\),v0.t'
+-.*Error: illegal operands `vlseg7e512.v v0,\(a0\),v0.t'
+-.*Error: illegal operands `vsseg7e512.v v0,\(a0\),v0.t'
+-.*Error: illegal operands `vlseg7e512ff.v v0,\(a0\),v0.t'
+-.*Error: illegal operands `vlseg8e512.v v0,\(a0\),v0.t'
+-.*Error: illegal operands `vsseg8e512.v v0,\(a0\),v0.t'
+-.*Error: illegal operands `vlseg8e512ff.v v0,\(a0\),v0.t'
+-.*Error: illegal operands `vlseg2e1024.v v0,\(a0\),v0.t'
+-.*Error: illegal operands `vsseg2e1024.v v0,\(a0\),v0.t'
+-.*Error: illegal operands `vlseg2e1024ff.v v0,\(a0\),v0.t'
+-.*Error: illegal operands `vlseg3e1024.v v0,\(a0\),v0.t'
+-.*Error: illegal operands `vsseg3e1024.v v0,\(a0\),v0.t'
+-.*Error: illegal operands `vlseg3e1024ff.v v0,\(a0\),v0.t'
+-.*Error: illegal operands `vlseg4e1024.v v0,\(a0\),v0.t'
+-.*Error: illegal operands `vsseg4e1024.v v0,\(a0\),v0.t'
+-.*Error: illegal operands `vlseg4e1024ff.v v0,\(a0\),v0.t'
+-.*Error: illegal operands `vlseg5e1024.v v0,\(a0\),v0.t'
+-.*Error: illegal operands `vsseg5e1024.v v0,\(a0\),v0.t'
+-.*Error: illegal operands `vlseg5e1024ff.v v0,\(a0\),v0.t'
+-.*Error: illegal operands `vlseg6e1024.v v0,\(a0\),v0.t'
+-.*Error: illegal operands `vsseg6e1024.v v0,\(a0\),v0.t'
+-.*Error: illegal operands `vlseg6e1024ff.v v0,\(a0\),v0.t'
+-.*Error: illegal operands `vlseg7e1024.v v0,\(a0\),v0.t'
+-.*Error: illegal operands `vsseg7e1024.v v0,\(a0\),v0.t'
+-.*Error: illegal operands `vlseg7e1024ff.v v0,\(a0\),v0.t'
+-.*Error: illegal operands `vlseg8e1024.v v0,\(a0\),v0.t'
+-.*Error: illegal operands `vsseg8e1024.v v0,\(a0\),v0.t'
+-.*Error: illegal operands `vlseg8e1024ff.v v0,\(a0\),v0.t'
+-.*Error: illegal operands `vlsseg2e8.v v0,\(a0\),a1,v0.t'
+-.*Error: illegal operands `vssseg2e8.v v0,\(a0\),a1,v0.t'
+-.*Error: illegal operands `vlsseg3e8.v v0,\(a0\),a1,v0.t'
+-.*Error: illegal operands `vssseg3e8.v v0,\(a0\),a1,v0.t'
+-.*Error: illegal operands `vlsseg4e8.v v0,\(a0\),a1,v0.t'
+-.*Error: illegal operands `vssseg4e8.v v0,\(a0\),a1,v0.t'
+-.*Error: illegal operands `vlsseg5e8.v v0,\(a0\),a1,v0.t'
+-.*Error: illegal operands `vssseg5e8.v v0,\(a0\),a1,v0.t'
+-.*Error: illegal operands `vlsseg6e8.v v0,\(a0\),a1,v0.t'
+-.*Error: illegal operands `vssseg6e8.v v0,\(a0\),a1,v0.t'
+-.*Error: illegal operands `vlsseg7e8.v v0,\(a0\),a1,v0.t'
+-.*Error: illegal operands `vssseg7e8.v v0,\(a0\),a1,v0.t'
+-.*Error: illegal operands `vlsseg8e8.v v0,\(a0\),a1,v0.t'
+-.*Error: illegal operands `vssseg8e8.v v0,\(a0\),a1,v0.t'
+-.*Error: illegal operands `vlsseg2e16.v v0,\(a0\),a1,v0.t'
+-.*Error: illegal operands `vssseg2e16.v v0,\(a0\),a1,v0.t'
+-.*Error: illegal operands `vlsseg3e16.v v0,\(a0\),a1,v0.t'
+-.*Error: illegal operands `vssseg3e16.v v0,\(a0\),a1,v0.t'
+-.*Error: illegal operands `vlsseg4e16.v v0,\(a0\),a1,v0.t'
+-.*Error: illegal operands `vssseg4e16.v v0,\(a0\),a1,v0.t'
+-.*Error: illegal operands `vlsseg5e16.v v0,\(a0\),a1,v0.t'
+-.*Error: illegal operands `vssseg5e16.v v0,\(a0\),a1,v0.t'
+-.*Error: illegal operands `vlsseg6e16.v v0,\(a0\),a1,v0.t'
+-.*Error: illegal operands `vssseg6e16.v v0,\(a0\),a1,v0.t'
+-.*Error: illegal operands `vlsseg7e16.v v0,\(a0\),a1,v0.t'
+-.*Error: illegal operands `vssseg7e16.v v0,\(a0\),a1,v0.t'
+-.*Error: illegal operands `vlsseg8e16.v v0,\(a0\),a1,v0.t'
+-.*Error: illegal operands `vssseg8e16.v v0,\(a0\),a1,v0.t'
+-.*Error: illegal operands `vlsseg2e32.v v0,\(a0\),a1,v0.t'
+-.*Error: illegal operands `vssseg2e32.v v0,\(a0\),a1,v0.t'
+-.*Error: illegal operands `vlsseg3e32.v v0,\(a0\),a1,v0.t'
+-.*Error: illegal operands `vssseg3e32.v v0,\(a0\),a1,v0.t'
+-.*Error: illegal operands `vlsseg4e32.v v0,\(a0\),a1,v0.t'
+-.*Error: illegal operands `vssseg4e32.v v0,\(a0\),a1,v0.t'
+-.*Error: illegal operands `vlsseg5e32.v v0,\(a0\),a1,v0.t'
+-.*Error: illegal operands `vssseg5e32.v v0,\(a0\),a1,v0.t'
+-.*Error: illegal operands `vlsseg6e32.v v0,\(a0\),a1,v0.t'
+-.*Error: illegal operands `vssseg6e32.v v0,\(a0\),a1,v0.t'
+-.*Error: illegal operands `vlsseg7e32.v v0,\(a0\),a1,v0.t'
+-.*Error: illegal operands `vssseg7e32.v v0,\(a0\),a1,v0.t'
+-.*Error: illegal operands `vlsseg8e32.v v0,\(a0\),a1,v0.t'
+-.*Error: illegal operands `vssseg8e32.v v0,\(a0\),a1,v0.t'
+-.*Error: illegal operands `vlsseg2e64.v v0,\(a0\),a1,v0.t'
+-.*Error: illegal operands `vssseg2e64.v v0,\(a0\),a1,v0.t'
+-.*Error: illegal operands `vlsseg3e64.v v0,\(a0\),a1,v0.t'
+-.*Error: illegal operands `vssseg3e64.v v0,\(a0\),a1,v0.t'
+-.*Error: illegal operands `vlsseg4e64.v v0,\(a0\),a1,v0.t'
+-.*Error: illegal operands `vssseg4e64.v v0,\(a0\),a1,v0.t'
+-.*Error: illegal operands `vlsseg5e64.v v0,\(a0\),a1,v0.t'
+-.*Error: illegal operands `vssseg5e64.v v0,\(a0\),a1,v0.t'
+-.*Error: illegal operands `vlsseg6e64.v v0,\(a0\),a1,v0.t'
+-.*Error: illegal operands `vssseg6e64.v v0,\(a0\),a1,v0.t'
+-.*Error: illegal operands `vlsseg7e64.v v0,\(a0\),a1,v0.t'
+-.*Error: illegal operands `vssseg7e64.v v0,\(a0\),a1,v0.t'
+-.*Error: illegal operands `vlsseg8e64.v v0,\(a0\),a1,v0.t'
+-.*Error: illegal operands `vssseg8e64.v v0,\(a0\),a1,v0.t'
+-.*Error: illegal operands `vlsseg2e128.v v0,\(a0\),a1,v0.t'
+-.*Error: illegal operands `vssseg2e128.v v0,\(a0\),a1,v0.t'
+-.*Error: illegal operands `vlsseg3e128.v v0,\(a0\),a1,v0.t'
+-.*Error: illegal operands `vssseg3e128.v v0,\(a0\),a1,v0.t'
+-.*Error: illegal operands `vlsseg4e128.v v0,\(a0\),a1,v0.t'
+-.*Error: illegal operands `vssseg4e128.v v0,\(a0\),a1,v0.t'
+-.*Error: illegal operands `vlsseg5e128.v v0,\(a0\),a1,v0.t'
+-.*Error: illegal operands `vssseg5e128.v v0,\(a0\),a1,v0.t'
+-.*Error: illegal operands `vlsseg6e128.v v0,\(a0\),a1,v0.t'
+-.*Error: illegal operands `vssseg6e128.v v0,\(a0\),a1,v0.t'
+-.*Error: illegal operands `vlsseg7e128.v v0,\(a0\),a1,v0.t'
+-.*Error: illegal operands `vssseg7e128.v v0,\(a0\),a1,v0.t'
+-.*Error: illegal operands `vlsseg8e128.v v0,\(a0\),a1,v0.t'
+-.*Error: illegal operands `vssseg8e128.v v0,\(a0\),a1,v0.t'
+-.*Error: illegal operands `vlsseg2e256.v v0,\(a0\),a1,v0.t'
+-.*Error: illegal operands `vssseg2e256.v v0,\(a0\),a1,v0.t'
+-.*Error: illegal operands `vlsseg3e256.v v0,\(a0\),a1,v0.t'
+-.*Error: illegal operands `vssseg3e256.v v0,\(a0\),a1,v0.t'
+-.*Error: illegal operands `vlsseg4e256.v v0,\(a0\),a1,v0.t'
+-.*Error: illegal operands `vssseg4e256.v v0,\(a0\),a1,v0.t'
+-.*Error: illegal operands `vlsseg5e256.v v0,\(a0\),a1,v0.t'
+-.*Error: illegal operands `vssseg5e256.v v0,\(a0\),a1,v0.t'
+-.*Error: illegal operands `vlsseg6e256.v v0,\(a0\),a1,v0.t'
+-.*Error: illegal operands `vssseg6e256.v v0,\(a0\),a1,v0.t'
+-.*Error: illegal operands `vlsseg7e256.v v0,\(a0\),a1,v0.t'
+-.*Error: illegal operands `vssseg7e256.v v0,\(a0\),a1,v0.t'
+-.*Error: illegal operands `vlsseg8e256.v v0,\(a0\),a1,v0.t'
+-.*Error: illegal operands `vssseg8e256.v v0,\(a0\),a1,v0.t'
+-.*Error: illegal operands `vlsseg2e512.v v0,\(a0\),a1,v0.t'
+-.*Error: illegal operands `vssseg2e512.v v0,\(a0\),a1,v0.t'
+-.*Error: illegal operands `vlsseg3e512.v v0,\(a0\),a1,v0.t'
+-.*Error: illegal operands `vssseg3e512.v v0,\(a0\),a1,v0.t'
+-.*Error: illegal operands `vlsseg4e512.v v0,\(a0\),a1,v0.t'
+-.*Error: illegal operands `vssseg4e512.v v0,\(a0\),a1,v0.t'
+-.*Error: illegal operands `vlsseg5e512.v v0,\(a0\),a1,v0.t'
+-.*Error: illegal operands `vssseg5e512.v v0,\(a0\),a1,v0.t'
+-.*Error: illegal operands `vlsseg6e512.v v0,\(a0\),a1,v0.t'
+-.*Error: illegal operands `vssseg6e512.v v0,\(a0\),a1,v0.t'
+-.*Error: illegal operands `vlsseg7e512.v v0,\(a0\),a1,v0.t'
+-.*Error: illegal operands `vssseg7e512.v v0,\(a0\),a1,v0.t'
+-.*Error: illegal operands `vlsseg8e512.v v0,\(a0\),a1,v0.t'
+-.*Error: illegal operands `vssseg8e512.v v0,\(a0\),a1,v0.t'
+-.*Error: illegal operands `vlsseg2e1024.v v0,\(a0\),a1,v0.t'
+-.*Error: illegal operands `vssseg2e1024.v v0,\(a0\),a1,v0.t'
+-.*Error: illegal operands `vlsseg3e1024.v v0,\(a0\),a1,v0.t'
+-.*Error: illegal operands `vssseg3e1024.v v0,\(a0\),a1,v0.t'
+-.*Error: illegal operands `vlsseg4e1024.v v0,\(a0\),a1,v0.t'
+-.*Error: illegal operands `vssseg4e1024.v v0,\(a0\),a1,v0.t'
+-.*Error: illegal operands `vlsseg5e1024.v v0,\(a0\),a1,v0.t'
+-.*Error: illegal operands `vssseg5e1024.v v0,\(a0\),a1,v0.t'
+-.*Error: illegal operands `vlsseg6e1024.v v0,\(a0\),a1,v0.t'
+-.*Error: illegal operands `vssseg6e1024.v v0,\(a0\),a1,v0.t'
+-.*Error: illegal operands `vlsseg7e1024.v v0,\(a0\),a1,v0.t'
+-.*Error: illegal operands `vssseg7e1024.v v0,\(a0\),a1,v0.t'
+-.*Error: illegal operands `vlsseg8e1024.v v0,\(a0\),a1,v0.t'
+-.*Error: illegal operands `vssseg8e1024.v v0,\(a0\),a1,v0.t'
+-.*Error: illegal operands `vlxseg2ei8.v v4,\(a0\),v4'
+-.*Error: illegal operands `vlxseg2ei8.v v0,\(a0\),v4,v0.t'
+-.*Error: illegal operands `vsxseg2ei8.v v4,\(a0\),v4'
+-.*Error: illegal operands `vsxseg2ei8.v v0,\(a0\),v4,v0.t'
+-.*Error: illegal operands `vlxseg3ei8.v v4,\(a0\),v4'
+-.*Error: illegal operands `vlxseg3ei8.v v0,\(a0\),v4,v0.t'
+-.*Error: illegal operands `vsxseg3ei8.v v4,\(a0\),v4'
+-.*Error: illegal operands `vsxseg3ei8.v v0,\(a0\),v4,v0.t'
+-.*Error: illegal operands `vlxseg4ei8.v v4,\(a0\),v4'
+-.*Error: illegal operands `vlxseg4ei8.v v0,\(a0\),v4,v0.t'
+-.*Error: illegal operands `vsxseg4ei8.v v4,\(a0\),v4'
+-.*Error: illegal operands `vsxseg4ei8.v v0,\(a0\),v4,v0.t'
+-.*Error: illegal operands `vlxseg5ei8.v v4,\(a0\),v4'
+-.*Error: illegal operands `vlxseg5ei8.v v0,\(a0\),v4,v0.t'
+-.*Error: illegal operands `vsxseg5ei8.v v4,\(a0\),v4'
+-.*Error: illegal operands `vsxseg5ei8.v v0,\(a0\),v4,v0.t'
+-.*Error: illegal operands `vlxseg6ei8.v v4,\(a0\),v4'
+-.*Error: illegal operands `vlxseg6ei8.v v0,\(a0\),v4,v0.t'
+-.*Error: illegal operands `vsxseg6ei8.v v4,\(a0\),v4'
+-.*Error: illegal operands `vsxseg6ei8.v v0,\(a0\),v4,v0.t'
+-.*Error: illegal operands `vlxseg7ei8.v v4,\(a0\),v4'
+-.*Error: illegal operands `vlxseg7ei8.v v0,\(a0\),v4,v0.t'
+-.*Error: illegal operands `vsxseg7ei8.v v4,\(a0\),v4'
+-.*Error: illegal operands `vsxseg7ei8.v v0,\(a0\),v4,v0.t'
+-.*Error: illegal operands `vlxseg8ei8.v v4,\(a0\),v4'
+-.*Error: illegal operands `vlxseg8ei8.v v0,\(a0\),v4,v0.t'
+-.*Error: illegal operands `vsxseg8ei8.v v4,\(a0\),v4'
+-.*Error: illegal operands `vsxseg8ei8.v v0,\(a0\),v4,v0.t'
+-.*Error: illegal operands `vlxseg2ei16.v v4,\(a0\),v4'
+-.*Error: illegal operands `vlxseg2ei16.v v0,\(a0\),v4,v0.t'
+-.*Error: illegal operands `vsxseg2ei16.v v4,\(a0\),v4'
+-.*Error: illegal operands `vsxseg2ei16.v v0,\(a0\),v4,v0.t'
+-.*Error: illegal operands `vlxseg3ei16.v v4,\(a0\),v4'
+-.*Error: illegal operands `vlxseg3ei16.v v0,\(a0\),v4,v0.t'
+-.*Error: illegal operands `vsxseg3ei16.v v4,\(a0\),v4'
+-.*Error: illegal operands `vsxseg3ei16.v v0,\(a0\),v4,v0.t'
+-.*Error: illegal operands `vlxseg4ei16.v v4,\(a0\),v4'
+-.*Error: illegal operands `vlxseg4ei16.v v0,\(a0\),v4,v0.t'
+-.*Error: illegal operands `vsxseg4ei16.v v4,\(a0\),v4'
+-.*Error: illegal operands `vsxseg4ei16.v v0,\(a0\),v4,v0.t'
+-.*Error: illegal operands `vlxseg5ei16.v v4,\(a0\),v4'
+-.*Error: illegal operands `vlxseg5ei16.v v0,\(a0\),v4,v0.t'
+-.*Error: illegal operands `vsxseg5ei16.v v4,\(a0\),v4'
+-.*Error: illegal operands `vsxseg5ei16.v v0,\(a0\),v4,v0.t'
+-.*Error: illegal operands `vlxseg6ei16.v v4,\(a0\),v4'
+-.*Error: illegal operands `vlxseg6ei16.v v0,\(a0\),v4,v0.t'
+-.*Error: illegal operands `vsxseg6ei16.v v4,\(a0\),v4'
+-.*Error: illegal operands `vsxseg6ei16.v v0,\(a0\),v4,v0.t'
+-.*Error: illegal operands `vlxseg7ei16.v v4,\(a0\),v4'
+-.*Error: illegal operands `vlxseg7ei16.v v0,\(a0\),v4,v0.t'
+-.*Error: illegal operands `vsxseg7ei16.v v4,\(a0\),v4'
+-.*Error: illegal operands `vsxseg7ei16.v v0,\(a0\),v4,v0.t'
+-.*Error: illegal operands `vlxseg8ei16.v v4,\(a0\),v4'
+-.*Error: illegal operands `vlxseg8ei16.v v0,\(a0\),v4,v0.t'
+-.*Error: illegal operands `vsxseg8ei16.v v4,\(a0\),v4'
+-.*Error: illegal operands `vsxseg8ei16.v v0,\(a0\),v4,v0.t'
+-.*Error: illegal operands `vlxseg2ei32.v v4,\(a0\),v4'
+-.*Error: illegal operands `vlxseg2ei32.v v0,\(a0\),v4,v0.t'
+-.*Error: illegal operands `vsxseg2ei32.v v4,\(a0\),v4'
+-.*Error: illegal operands `vsxseg2ei32.v v0,\(a0\),v4,v0.t'
+-.*Error: illegal operands `vlxseg3ei32.v v4,\(a0\),v4'
+-.*Error: illegal operands `vlxseg3ei32.v v0,\(a0\),v4,v0.t'
+-.*Error: illegal operands `vsxseg3ei32.v v4,\(a0\),v4'
+-.*Error: illegal operands `vsxseg3ei32.v v0,\(a0\),v4,v0.t'
+-.*Error: illegal operands `vlxseg4ei32.v v4,\(a0\),v4'
+-.*Error: illegal operands `vlxseg4ei32.v v0,\(a0\),v4,v0.t'
+-.*Error: illegal operands `vsxseg4ei32.v v4,\(a0\),v4'
+-.*Error: illegal operands `vsxseg4ei32.v v0,\(a0\),v4,v0.t'
+-.*Error: illegal operands `vlxseg5ei32.v v4,\(a0\),v4'
+-.*Error: illegal operands `vlxseg5ei32.v v0,\(a0\),v4,v0.t'
+-.*Error: illegal operands `vsxseg5ei32.v v4,\(a0\),v4'
+-.*Error: illegal operands `vsxseg5ei32.v v0,\(a0\),v4,v0.t'
+-.*Error: illegal operands `vlxseg6ei32.v v4,\(a0\),v4'
+-.*Error: illegal operands `vlxseg6ei32.v v0,\(a0\),v4,v0.t'
+-.*Error: illegal operands `vsxseg6ei32.v v4,\(a0\),v4'
+-.*Error: illegal operands `vsxseg6ei32.v v0,\(a0\),v4,v0.t'
+-.*Error: illegal operands `vlxseg7ei32.v v4,\(a0\),v4'
+-.*Error: illegal operands `vlxseg7ei32.v v0,\(a0\),v4,v0.t'
+-.*Error: illegal operands `vsxseg7ei32.v v4,\(a0\),v4'
+-.*Error: illegal operands `vsxseg7ei32.v v0,\(a0\),v4,v0.t'
+-.*Error: illegal operands `vlxseg8ei32.v v4,\(a0\),v4'
+-.*Error: illegal operands `vlxseg8ei32.v v0,\(a0\),v4,v0.t'
+-.*Error: illegal operands `vsxseg8ei32.v v4,\(a0\),v4'
+-.*Error: illegal operands `vsxseg8ei32.v v0,\(a0\),v4,v0.t'
+-.*Error: illegal operands `vlxseg2ei64.v v4,\(a0\),v4'
+-.*Error: illegal operands `vlxseg2ei64.v v0,\(a0\),v4,v0.t'
+-.*Error: illegal operands `vsxseg2ei64.v v4,\(a0\),v4'
+-.*Error: illegal operands `vsxseg2ei64.v v0,\(a0\),v4,v0.t'
+-.*Error: illegal operands `vlxseg3ei64.v v4,\(a0\),v4'
+-.*Error: illegal operands `vlxseg3ei64.v v0,\(a0\),v4,v0.t'
+-.*Error: illegal operands `vsxseg3ei64.v v4,\(a0\),v4'
+-.*Error: illegal operands `vsxseg3ei64.v v0,\(a0\),v4,v0.t'
+-.*Error: illegal operands `vlxseg4ei64.v v4,\(a0\),v4'
+-.*Error: illegal operands `vlxseg4ei64.v v0,\(a0\),v4,v0.t'
+-.*Error: illegal operands `vsxseg4ei64.v v4,\(a0\),v4'
+-.*Error: illegal operands `vsxseg4ei64.v v0,\(a0\),v4,v0.t'
+-.*Error: illegal operands `vlxseg5ei64.v v4,\(a0\),v4'
+-.*Error: illegal operands `vlxseg5ei64.v v0,\(a0\),v4,v0.t'
+-.*Error: illegal operands `vsxseg5ei64.v v4,\(a0\),v4'
+-.*Error: illegal operands `vsxseg5ei64.v v0,\(a0\),v4,v0.t'
+-.*Error: illegal operands `vlxseg6ei64.v v4,\(a0\),v4'
+-.*Error: illegal operands `vlxseg6ei64.v v0,\(a0\),v4,v0.t'
+-.*Error: illegal operands `vsxseg6ei64.v v4,\(a0\),v4'
+-.*Error: illegal operands `vsxseg6ei64.v v0,\(a0\),v4,v0.t'
+-.*Error: illegal operands `vlxseg7ei64.v v4,\(a0\),v4'
+-.*Error: illegal operands `vlxseg7ei64.v v0,\(a0\),v4,v0.t'
+-.*Error: illegal operands `vsxseg7ei64.v v4,\(a0\),v4'
+-.*Error: illegal operands `vsxseg7ei64.v v0,\(a0\),v4,v0.t'
+-.*Error: illegal operands `vlxseg8ei64.v v4,\(a0\),v4'
+-.*Error: illegal operands `vlxseg8ei64.v v0,\(a0\),v4,v0.t'
+-.*Error: illegal operands `vsxseg8ei64.v v4,\(a0\),v4'
+-.*Error: illegal operands `vsxseg8ei64.v v0,\(a0\),v4,v0.t'
+-.*Error: illegal operands `vlxseg2ei128.v v4,\(a0\),v4'
+-.*Error: illegal operands `vlxseg2ei128.v v0,\(a0\),v4,v0.t'
+-.*Error: illegal operands `vsxseg2ei128.v v4,\(a0\),v4'
+-.*Error: illegal operands `vsxseg2ei128.v v0,\(a0\),v4,v0.t'
+-.*Error: illegal operands `vlxseg3ei128.v v4,\(a0\),v4'
+-.*Error: illegal operands `vlxseg3ei128.v v0,\(a0\),v4,v0.t'
+-.*Error: illegal operands `vsxseg3ei128.v v4,\(a0\),v4'
+-.*Error: illegal operands `vsxseg3ei128.v v0,\(a0\),v4,v0.t'
+-.*Error: illegal operands `vlxseg4ei128.v v4,\(a0\),v4'
+-.*Error: illegal operands `vlxseg4ei128.v v0,\(a0\),v4,v0.t'
+-.*Error: illegal operands `vsxseg4ei128.v v4,\(a0\),v4'
+-.*Error: illegal operands `vsxseg4ei128.v v0,\(a0\),v4,v0.t'
+-.*Error: illegal operands `vlxseg5ei128.v v4,\(a0\),v4'
+-.*Error: illegal operands `vlxseg5ei128.v v0,\(a0\),v4,v0.t'
+-.*Error: illegal operands `vsxseg5ei128.v v4,\(a0\),v4'
+-.*Error: illegal operands `vsxseg5ei128.v v0,\(a0\),v4,v0.t'
+-.*Error: illegal operands `vlxseg6ei128.v v4,\(a0\),v4'
+-.*Error: illegal operands `vlxseg6ei128.v v0,\(a0\),v4,v0.t'
+-.*Error: illegal operands `vsxseg6ei128.v v4,\(a0\),v4'
+-.*Error: illegal operands `vsxseg6ei128.v v0,\(a0\),v4,v0.t'
+-.*Error: illegal operands `vlxseg7ei128.v v4,\(a0\),v4'
+-.*Error: illegal operands `vlxseg7ei128.v v0,\(a0\),v4,v0.t'
+-.*Error: illegal operands `vsxseg7ei128.v v4,\(a0\),v4'
+-.*Error: illegal operands `vsxseg7ei128.v v0,\(a0\),v4,v0.t'
+-.*Error: illegal operands `vlxseg8ei128.v v4,\(a0\),v4'
+-.*Error: illegal operands `vlxseg8ei128.v v0,\(a0\),v4,v0.t'
+-.*Error: illegal operands `vsxseg8ei128.v v4,\(a0\),v4'
+-.*Error: illegal operands `vsxseg8ei128.v v0,\(a0\),v4,v0.t'
+-.*Error: illegal operands `vlxseg2ei256.v v4,\(a0\),v4'
+-.*Error: illegal operands `vlxseg2ei256.v v0,\(a0\),v4,v0.t'
+-.*Error: illegal operands `vsxseg2ei256.v v4,\(a0\),v4'
+-.*Error: illegal operands `vsxseg2ei256.v v0,\(a0\),v4,v0.t'
+-.*Error: illegal operands `vlxseg3ei256.v v4,\(a0\),v4'
+-.*Error: illegal operands `vlxseg3ei256.v v0,\(a0\),v4,v0.t'
+-.*Error: illegal operands `vsxseg3ei256.v v4,\(a0\),v4'
+-.*Error: illegal operands `vsxseg3ei256.v v0,\(a0\),v4,v0.t'
+-.*Error: illegal operands `vlxseg4ei256.v v4,\(a0\),v4'
+-.*Error: illegal operands `vlxseg4ei256.v v0,\(a0\),v4,v0.t'
+-.*Error: illegal operands `vsxseg4ei256.v v4,\(a0\),v4'
+-.*Error: illegal operands `vsxseg4ei256.v v0,\(a0\),v4,v0.t'
+-.*Error: illegal operands `vlxseg5ei256.v v4,\(a0\),v4'
+-.*Error: illegal operands `vlxseg5ei256.v v0,\(a0\),v4,v0.t'
+-.*Error: illegal operands `vsxseg5ei256.v v4,\(a0\),v4'
+-.*Error: illegal operands `vsxseg5ei256.v v0,\(a0\),v4,v0.t'
+-.*Error: illegal operands `vlxseg6ei256.v v4,\(a0\),v4'
+-.*Error: illegal operands `vlxseg6ei256.v v0,\(a0\),v4,v0.t'
+-.*Error: illegal operands `vsxseg6ei256.v v4,\(a0\),v4'
+-.*Error: illegal operands `vsxseg6ei256.v v0,\(a0\),v4,v0.t'
+-.*Error: illegal operands `vlxseg7ei256.v v4,\(a0\),v4'
+-.*Error: illegal operands `vlxseg7ei256.v v0,\(a0\),v4,v0.t'
+-.*Error: illegal operands `vsxseg7ei256.v v4,\(a0\),v4'
+-.*Error: illegal operands `vsxseg7ei256.v v0,\(a0\),v4,v0.t'
+-.*Error: illegal operands `vlxseg8ei256.v v4,\(a0\),v4'
+-.*Error: illegal operands `vlxseg8ei256.v v0,\(a0\),v4,v0.t'
+-.*Error: illegal operands `vsxseg8ei256.v v4,\(a0\),v4'
+-.*Error: illegal operands `vsxseg8ei256.v v0,\(a0\),v4,v0.t'
+-.*Error: illegal operands `vlxseg2ei512.v v4,\(a0\),v4'
+-.*Error: illegal operands `vlxseg2ei512.v v0,\(a0\),v4,v0.t'
+-.*Error: illegal operands `vsxseg2ei512.v v4,\(a0\),v4'
+-.*Error: illegal operands `vsxseg2ei512.v v0,\(a0\),v4,v0.t'
+-.*Error: illegal operands `vlxseg3ei512.v v4,\(a0\),v4'
+-.*Error: illegal operands `vlxseg3ei512.v v0,\(a0\),v4,v0.t'
+-.*Error: illegal operands `vsxseg3ei512.v v4,\(a0\),v4'
+-.*Error: illegal operands `vsxseg3ei512.v v0,\(a0\),v4,v0.t'
+-.*Error: illegal operands `vlxseg4ei512.v v4,\(a0\),v4'
+-.*Error: illegal operands `vlxseg4ei512.v v0,\(a0\),v4,v0.t'
+-.*Error: illegal operands `vsxseg4ei512.v v4,\(a0\),v4'
+-.*Error: illegal operands `vsxseg4ei512.v v0,\(a0\),v4,v0.t'
+-.*Error: illegal operands `vlxseg5ei512.v v4,\(a0\),v4'
+-.*Error: illegal operands `vlxseg5ei512.v v0,\(a0\),v4,v0.t'
+-.*Error: illegal operands `vsxseg5ei512.v v4,\(a0\),v4'
+-.*Error: illegal operands `vsxseg5ei512.v v0,\(a0\),v4,v0.t'
+-.*Error: illegal operands `vlxseg6ei512.v v4,\(a0\),v4'
+-.*Error: illegal operands `vlxseg6ei512.v v0,\(a0\),v4,v0.t'
+-.*Error: illegal operands `vsxseg6ei512.v v4,\(a0\),v4'
+-.*Error: illegal operands `vsxseg6ei512.v v0,\(a0\),v4,v0.t'
+-.*Error: illegal operands `vlxseg7ei512.v v4,\(a0\),v4'
+-.*Error: illegal operands `vlxseg7ei512.v v0,\(a0\),v4,v0.t'
+-.*Error: illegal operands `vsxseg7ei512.v v4,\(a0\),v4'
+-.*Error: illegal operands `vsxseg7ei512.v v0,\(a0\),v4,v0.t'
+-.*Error: illegal operands `vlxseg8ei512.v v4,\(a0\),v4'
+-.*Error: illegal operands `vlxseg8ei512.v v0,\(a0\),v4,v0.t'
+-.*Error: illegal operands `vsxseg8ei512.v v4,\(a0\),v4'
+-.*Error: illegal operands `vsxseg8ei512.v v0,\(a0\),v4,v0.t'
+-.*Error: illegal operands `vlxseg2ei1024.v v4,\(a0\),v4'
+-.*Error: illegal operands `vlxseg2ei1024.v v0,\(a0\),v4,v0.t'
+-.*Error: illegal operands `vsxseg2ei1024.v v4,\(a0\),v4'
+-.*Error: illegal operands `vsxseg2ei1024.v v0,\(a0\),v4,v0.t'
+-.*Error: illegal operands `vlxseg3ei1024.v v4,\(a0\),v4'
+-.*Error: illegal operands `vlxseg3ei1024.v v0,\(a0\),v4,v0.t'
+-.*Error: illegal operands `vsxseg3ei1024.v v4,\(a0\),v4'
+-.*Error: illegal operands `vsxseg3ei1024.v v0,\(a0\),v4,v0.t'
+-.*Error: illegal operands `vlxseg4ei1024.v v4,\(a0\),v4'
+-.*Error: illegal operands `vlxseg4ei1024.v v0,\(a0\),v4,v0.t'
+-.*Error: illegal operands `vsxseg4ei1024.v v4,\(a0\),v4'
+-.*Error: illegal operands `vsxseg4ei1024.v v0,\(a0\),v4,v0.t'
+-.*Error: illegal operands `vlxseg5ei1024.v v4,\(a0\),v4'
+-.*Error: illegal operands `vlxseg5ei1024.v v0,\(a0\),v4,v0.t'
+-.*Error: illegal operands `vsxseg5ei1024.v v4,\(a0\),v4'
+-.*Error: illegal operands `vsxseg5ei1024.v v0,\(a0\),v4,v0.t'
+-.*Error: illegal operands `vlxseg6ei1024.v v4,\(a0\),v4'
+-.*Error: illegal operands `vlxseg6ei1024.v v0,\(a0\),v4,v0.t'
+-.*Error: illegal operands `vsxseg6ei1024.v v4,\(a0\),v4'
+-.*Error: illegal operands `vsxseg6ei1024.v v0,\(a0\),v4,v0.t'
+-.*Error: illegal operands `vlxseg7ei1024.v v4,\(a0\),v4'
+-.*Error: illegal operands `vlxseg7ei1024.v v0,\(a0\),v4,v0.t'
+-.*Error: illegal operands `vsxseg7ei1024.v v4,\(a0\),v4'
+-.*Error: illegal operands `vsxseg7ei1024.v v0,\(a0\),v4,v0.t'
+-.*Error: illegal operands `vlxseg8ei1024.v v4,\(a0\),v4'
+-.*Error: illegal operands `vlxseg8ei1024.v v0,\(a0\),v4,v0.t'
+-.*Error: illegal operands `vsxseg8ei1024.v v4,\(a0\),v4'
+-.*Error: illegal operands `vsxseg8ei1024.v v0,\(a0\),v4,v0.t'
+-.*Error: illegal operands `vl2r.v v31,\(a0\)'
+-.*Error: illegal operands `vl2re8.v v31,\(a0\)'
+-.*Error: illegal operands `vl2re16.v v31,\(a0\)'
+-.*Error: illegal operands `vl2re32.v v31,\(a0\)'
+-.*Error: illegal operands `vl2re64.v v31,\(a0\)'
+-.*Error: illegal operands `vl2re128.v v31,\(a0\)'
+-.*Error: illegal operands `vl2re256.v v31,\(a0\)'
+-.*Error: illegal operands `vl2re512.v v31,\(a0\)'
+-.*Error: illegal operands `vl2re1024.v v31,\(a0\)'
+-.*Error: illegal operands `vl4r.v v30,\(a0\)'
+-.*Error: illegal operands `vl4re8.v v30,\(a0\)'
+-.*Error: illegal operands `vl4re16.v v30,\(a0\)'
+-.*Error: illegal operands `vl4re32.v v30,\(a0\)'
+-.*Error: illegal operands `vl4re64.v v30,\(a0\)'
+-.*Error: illegal operands `vl4re128.v v30,\(a0\)'
+-.*Error: illegal operands `vl4re256.v v30,\(a0\)'
+-.*Error: illegal operands `vl4re512.v v30,\(a0\)'
+-.*Error: illegal operands `vl4re1024.v v30,\(a0\)'
+-.*Error: illegal operands `vl8r.v v26,\(a0\)'
+-.*Error: illegal operands `vl8re8.v v26,\(a0\)'
+-.*Error: illegal operands `vl8re16.v v26,\(a0\)'
+-.*Error: illegal operands `vl8re32.v v26,\(a0\)'
+-.*Error: illegal operands `vl8re64.v v26,\(a0\)'
+-.*Error: illegal operands `vl8re128.v v26,\(a0\)'
+-.*Error: illegal operands `vl8re256.v v26,\(a0\)'
+-.*Error: illegal operands `vl8re512.v v26,\(a0\)'
+-.*Error: illegal operands `vl8re1024.v v26,\(a0\)'
+-.*Error: illegal operands `vs2r.v v31,\(a0\)'
+-.*Error: illegal operands `vs4r.v v30,\(a0\)'
+-.*Error: illegal operands `vs8r.v v26,\(a0\)'
++.*Error: illegal operands vd cannot overlap vm `vle8.v v0,\(a0\),v0.t'
++.*Error: illegal operands vd cannot overlap vm `vle8ff.v v0,\(a0\),v0.t'
++.*Error: illegal operands vd cannot overlap vm `vle16.v v0,\(a0\),v0.t'
++.*Error: illegal operands vd cannot overlap vm `vle16ff.v v0,\(a0\),v0.t'
++.*Error: illegal operands vd cannot overlap vm `vle32.v v0,\(a0\),v0.t'
++.*Error: illegal operands vd cannot overlap vm `vle32ff.v v0,\(a0\),v0.t'
++.*Error: illegal operands vd cannot overlap vm `vle64.v v0,\(a0\),v0.t'
++.*Error: illegal operands vd cannot overlap vm `vle64ff.v v0,\(a0\),v0.t'
++.*Error: illegal operands vd cannot overlap vm `vle128.v v0,\(a0\),v0.t'
++.*Error: illegal operands vd cannot overlap vm `vle128ff.v v0,\(a0\),v0.t'
++.*Error: illegal operands vd cannot overlap vm `vle256.v v0,\(a0\),v0.t'
++.*Error: illegal operands vd cannot overlap vm `vle256ff.v v0,\(a0\),v0.t'
++.*Error: illegal operands vd cannot overlap vm `vle512.v v0,\(a0\),v0.t'
++.*Error: illegal operands vd cannot overlap vm `vle512ff.v v0,\(a0\),v0.t'
++.*Error: illegal operands vd cannot overlap vm `vle1024.v v0,\(a0\),v0.t'
++.*Error: illegal operands vd cannot overlap vm `vle1024ff.v v0,\(a0\),v0.t'
++.*Error: illegal operands vd cannot overlap vm `vse8.v v0,\(a0\),v0.t'
++.*Error: illegal operands vd cannot overlap vm `vse16.v v0,\(a0\),v0.t'
++.*Error: illegal operands vd cannot overlap vm `vse32.v v0,\(a0\),v0.t'
++.*Error: illegal operands vd cannot overlap vm `vse64.v v0,\(a0\),v0.t'
++.*Error: illegal operands vd cannot overlap vm `vse128.v v0,\(a0\),v0.t'
++.*Error: illegal operands vd cannot overlap vm `vse256.v v0,\(a0\),v0.t'
++.*Error: illegal operands vd cannot overlap vm `vse512.v v0,\(a0\),v0.t'
++.*Error: illegal operands vd cannot overlap vm `vse1024.v v0,\(a0\),v0.t'
++.*Error: illegal operands vd cannot overlap vm `vlse8.v v0,\(a0\),a1,v0.t'
++.*Error: illegal operands vd cannot overlap vm `vlse16.v v0,\(a0\),a1,v0.t'
++.*Error: illegal operands vd cannot overlap vm `vlse32.v v0,\(a0\),a1,v0.t'
++.*Error: illegal operands vd cannot overlap vm `vlse64.v v0,\(a0\),a1,v0.t'
++.*Error: illegal operands vd cannot overlap vm `vlse128.v v0,\(a0\),a1,v0.t'
++.*Error: illegal operands vd cannot overlap vm `vlse256.v v0,\(a0\),a1,v0.t'
++.*Error: illegal operands vd cannot overlap vm `vlse512.v v0,\(a0\),a1,v0.t'
++.*Error: illegal operands vd cannot overlap vm `vlse1024.v v0,\(a0\),a1,v0.t'
++.*Error: illegal operands vd cannot overlap vm `vsse8.v v0,\(a0\),a1,v0.t'
++.*Error: illegal operands vd cannot overlap vm `vsse16.v v0,\(a0\),a1,v0.t'
++.*Error: illegal operands vd cannot overlap vm `vsse32.v v0,\(a0\),a1,v0.t'
++.*Error: illegal operands vd cannot overlap vm `vsse64.v v0,\(a0\),a1,v0.t'
++.*Error: illegal operands vd cannot overlap vm `vsse128.v v0,\(a0\),a1,v0.t'
++.*Error: illegal operands vd cannot overlap vm `vsse256.v v0,\(a0\),a1,v0.t'
++.*Error: illegal operands vd cannot overlap vm `vsse512.v v0,\(a0\),a1,v0.t'
++.*Error: illegal operands vd cannot overlap vm `vsse1024.v v0,\(a0\),a1,v0.t'
++.*Error: illegal operands vd cannot overlap vm `vlxei8.v v0,\(a0\),v4,v0.t'
++.*Error: illegal operands vd cannot overlap vm `vlxei16.v v0,\(a0\),v4,v0.t'
++.*Error: illegal operands vd cannot overlap vm `vlxei32.v v0,\(a0\),v4,v0.t'
++.*Error: illegal operands vd cannot overlap vm `vlxei64.v v0,\(a0\),v4,v0.t'
++.*Error: illegal operands vd cannot overlap vm `vsxei8.v v0,\(a0\),v4,v0.t'
++.*Error: illegal operands vd cannot overlap vm `vsxei16.v v0,\(a0\),v4,v0.t'
++.*Error: illegal operands vd cannot overlap vm `vsxei32.v v0,\(a0\),v4,v0.t'
++.*Error: illegal operands vd cannot overlap vm `vsxei64.v v0,\(a0\),v4,v0.t'
++.*Error: illegal operands vd cannot overlap vm `vsuxei8.v v0,\(a0\),v4,v0.t'
++.*Error: illegal operands vd cannot overlap vm `vsuxei16.v v0,\(a0\),v4,v0.t'
++.*Error: illegal operands vd cannot overlap vm `vsuxei32.v v0,\(a0\),v4,v0.t'
++.*Error: illegal operands vd cannot overlap vm `vsuxei64.v v0,\(a0\),v4,v0.t'
++.*Error: illegal operands vd cannot overlap vm `vlseg2e8.v v0,\(a0\),v0.t'
++.*Error: illegal operands vd cannot overlap vm `vsseg2e8.v v0,\(a0\),v0.t'
++.*Error: illegal operands vd cannot overlap vm `vlseg2e8ff.v v0,\(a0\),v0.t'
++.*Error: illegal operands vd cannot overlap vm `vlseg3e8.v v0,\(a0\),v0.t'
++.*Error: illegal operands vd cannot overlap vm `vsseg3e8.v v0,\(a0\),v0.t'
++.*Error: illegal operands vd cannot overlap vm `vlseg3e8ff.v v0,\(a0\),v0.t'
++.*Error: illegal operands vd cannot overlap vm `vlseg4e8.v v0,\(a0\),v0.t'
++.*Error: illegal operands vd cannot overlap vm `vsseg4e8.v v0,\(a0\),v0.t'
++.*Error: illegal operands vd cannot overlap vm `vlseg4e8ff.v v0,\(a0\),v0.t'
++.*Error: illegal operands vd cannot overlap vm `vlseg5e8.v v0,\(a0\),v0.t'
++.*Error: illegal operands vd cannot overlap vm `vsseg5e8.v v0,\(a0\),v0.t'
++.*Error: illegal operands vd cannot overlap vm `vlseg5e8ff.v v0,\(a0\),v0.t'
++.*Error: illegal operands vd cannot overlap vm `vlseg6e8.v v0,\(a0\),v0.t'
++.*Error: illegal operands vd cannot overlap vm `vsseg6e8.v v0,\(a0\),v0.t'
++.*Error: illegal operands vd cannot overlap vm `vlseg6e8ff.v v0,\(a0\),v0.t'
++.*Error: illegal operands vd cannot overlap vm `vlseg7e8.v v0,\(a0\),v0.t'
++.*Error: illegal operands vd cannot overlap vm `vsseg7e8.v v0,\(a0\),v0.t'
++.*Error: illegal operands vd cannot overlap vm `vlseg7e8ff.v v0,\(a0\),v0.t'
++.*Error: illegal operands vd cannot overlap vm `vlseg8e8.v v0,\(a0\),v0.t'
++.*Error: illegal operands vd cannot overlap vm `vsseg8e8.v v0,\(a0\),v0.t'
++.*Error: illegal operands vd cannot overlap vm `vlseg8e8ff.v v0,\(a0\),v0.t'
++.*Error: illegal operands vd cannot overlap vm `vlseg2e16.v v0,\(a0\),v0.t'
++.*Error: illegal operands vd cannot overlap vm `vsseg2e16.v v0,\(a0\),v0.t'
++.*Error: illegal operands vd cannot overlap vm `vlseg2e16ff.v v0,\(a0\),v0.t'
++.*Error: illegal operands vd cannot overlap vm `vlseg3e16.v v0,\(a0\),v0.t'
++.*Error: illegal operands vd cannot overlap vm `vsseg3e16.v v0,\(a0\),v0.t'
++.*Error: illegal operands vd cannot overlap vm `vlseg3e16ff.v v0,\(a0\),v0.t'
++.*Error: illegal operands vd cannot overlap vm `vlseg4e16.v v0,\(a0\),v0.t'
++.*Error: illegal operands vd cannot overlap vm `vsseg4e16.v v0,\(a0\),v0.t'
++.*Error: illegal operands vd cannot overlap vm `vlseg4e16ff.v v0,\(a0\),v0.t'
++.*Error: illegal operands vd cannot overlap vm `vlseg5e16.v v0,\(a0\),v0.t'
++.*Error: illegal operands vd cannot overlap vm `vsseg5e16.v v0,\(a0\),v0.t'
++.*Error: illegal operands vd cannot overlap vm `vlseg5e16ff.v v0,\(a0\),v0.t'
++.*Error: illegal operands vd cannot overlap vm `vlseg6e16.v v0,\(a0\),v0.t'
++.*Error: illegal operands vd cannot overlap vm `vsseg6e16.v v0,\(a0\),v0.t'
++.*Error: illegal operands vd cannot overlap vm `vlseg6e16ff.v v0,\(a0\),v0.t'
++.*Error: illegal operands vd cannot overlap vm `vlseg7e16.v v0,\(a0\),v0.t'
++.*Error: illegal operands vd cannot overlap vm `vsseg7e16.v v0,\(a0\),v0.t'
++.*Error: illegal operands vd cannot overlap vm `vlseg7e16ff.v v0,\(a0\),v0.t'
++.*Error: illegal operands vd cannot overlap vm `vlseg8e16.v v0,\(a0\),v0.t'
++.*Error: illegal operands vd cannot overlap vm `vsseg8e16.v v0,\(a0\),v0.t'
++.*Error: illegal operands vd cannot overlap vm `vlseg8e16ff.v v0,\(a0\),v0.t'
++.*Error: illegal operands vd cannot overlap vm `vlseg2e32.v v0,\(a0\),v0.t'
++.*Error: illegal operands vd cannot overlap vm `vsseg2e32.v v0,\(a0\),v0.t'
++.*Error: illegal operands vd cannot overlap vm `vlseg2e32ff.v v0,\(a0\),v0.t'
++.*Error: illegal operands vd cannot overlap vm `vlseg3e32.v v0,\(a0\),v0.t'
++.*Error: illegal operands vd cannot overlap vm `vsseg3e32.v v0,\(a0\),v0.t'
++.*Error: illegal operands vd cannot overlap vm `vlseg3e32ff.v v0,\(a0\),v0.t'
++.*Error: illegal operands vd cannot overlap vm `vlseg4e32.v v0,\(a0\),v0.t'
++.*Error: illegal operands vd cannot overlap vm `vsseg4e32.v v0,\(a0\),v0.t'
++.*Error: illegal operands vd cannot overlap vm `vlseg4e32ff.v v0,\(a0\),v0.t'
++.*Error: illegal operands vd cannot overlap vm `vlseg5e32.v v0,\(a0\),v0.t'
++.*Error: illegal operands vd cannot overlap vm `vsseg5e32.v v0,\(a0\),v0.t'
++.*Error: illegal operands vd cannot overlap vm `vlseg5e32ff.v v0,\(a0\),v0.t'
++.*Error: illegal operands vd cannot overlap vm `vlseg6e32.v v0,\(a0\),v0.t'
++.*Error: illegal operands vd cannot overlap vm `vsseg6e32.v v0,\(a0\),v0.t'
++.*Error: illegal operands vd cannot overlap vm `vlseg6e32ff.v v0,\(a0\),v0.t'
++.*Error: illegal operands vd cannot overlap vm `vlseg7e32.v v0,\(a0\),v0.t'
++.*Error: illegal operands vd cannot overlap vm `vsseg7e32.v v0,\(a0\),v0.t'
++.*Error: illegal operands vd cannot overlap vm `vlseg7e32ff.v v0,\(a0\),v0.t'
++.*Error: illegal operands vd cannot overlap vm `vlseg8e32.v v0,\(a0\),v0.t'
++.*Error: illegal operands vd cannot overlap vm `vsseg8e32.v v0,\(a0\),v0.t'
++.*Error: illegal operands vd cannot overlap vm `vlseg8e32ff.v v0,\(a0\),v0.t'
++.*Error: illegal operands vd cannot overlap vm `vlseg2e64.v v0,\(a0\),v0.t'
++.*Error: illegal operands vd cannot overlap vm `vsseg2e64.v v0,\(a0\),v0.t'
++.*Error: illegal operands vd cannot overlap vm `vlseg2e64ff.v v0,\(a0\),v0.t'
++.*Error: illegal operands vd cannot overlap vm `vlseg3e64.v v0,\(a0\),v0.t'
++.*Error: illegal operands vd cannot overlap vm `vsseg3e64.v v0,\(a0\),v0.t'
++.*Error: illegal operands vd cannot overlap vm `vlseg3e64ff.v v0,\(a0\),v0.t'
++.*Error: illegal operands vd cannot overlap vm `vlseg4e64.v v0,\(a0\),v0.t'
++.*Error: illegal operands vd cannot overlap vm `vsseg4e64.v v0,\(a0\),v0.t'
++.*Error: illegal operands vd cannot overlap vm `vlseg4e64ff.v v0,\(a0\),v0.t'
++.*Error: illegal operands vd cannot overlap vm `vlseg5e64.v v0,\(a0\),v0.t'
++.*Error: illegal operands vd cannot overlap vm `vsseg5e64.v v0,\(a0\),v0.t'
++.*Error: illegal operands vd cannot overlap vm `vlseg5e64ff.v v0,\(a0\),v0.t'
++.*Error: illegal operands vd cannot overlap vm `vlseg6e64.v v0,\(a0\),v0.t'
++.*Error: illegal operands vd cannot overlap vm `vsseg6e64.v v0,\(a0\),v0.t'
++.*Error: illegal operands vd cannot overlap vm `vlseg6e64ff.v v0,\(a0\),v0.t'
++.*Error: illegal operands vd cannot overlap vm `vlseg7e64.v v0,\(a0\),v0.t'
++.*Error: illegal operands vd cannot overlap vm `vsseg7e64.v v0,\(a0\),v0.t'
++.*Error: illegal operands vd cannot overlap vm `vlseg7e64ff.v v0,\(a0\),v0.t'
++.*Error: illegal operands vd cannot overlap vm `vlseg8e64.v v0,\(a0\),v0.t'
++.*Error: illegal operands vd cannot overlap vm `vsseg8e64.v v0,\(a0\),v0.t'
++.*Error: illegal operands vd cannot overlap vm `vlseg8e64ff.v v0,\(a0\),v0.t'
++.*Error: illegal operands vd cannot overlap vm `vlseg2e128.v v0,\(a0\),v0.t'
++.*Error: illegal operands vd cannot overlap vm `vsseg2e128.v v0,\(a0\),v0.t'
++.*Error: illegal operands vd cannot overlap vm `vlseg2e128ff.v v0,\(a0\),v0.t'
++.*Error: illegal operands vd cannot overlap vm `vlseg3e128.v v0,\(a0\),v0.t'
++.*Error: illegal operands vd cannot overlap vm `vsseg3e128.v v0,\(a0\),v0.t'
++.*Error: illegal operands vd cannot overlap vm `vlseg3e128ff.v v0,\(a0\),v0.t'
++.*Error: illegal operands vd cannot overlap vm `vlseg4e128.v v0,\(a0\),v0.t'
++.*Error: illegal operands vd cannot overlap vm `vsseg4e128.v v0,\(a0\),v0.t'
++.*Error: illegal operands vd cannot overlap vm `vlseg4e128ff.v v0,\(a0\),v0.t'
++.*Error: illegal operands vd cannot overlap vm `vlseg5e128.v v0,\(a0\),v0.t'
++.*Error: illegal operands vd cannot overlap vm `vsseg5e128.v v0,\(a0\),v0.t'
++.*Error: illegal operands vd cannot overlap vm `vlseg5e128ff.v v0,\(a0\),v0.t'
++.*Error: illegal operands vd cannot overlap vm `vlseg6e128.v v0,\(a0\),v0.t'
++.*Error: illegal operands vd cannot overlap vm `vsseg6e128.v v0,\(a0\),v0.t'
++.*Error: illegal operands vd cannot overlap vm `vlseg6e128ff.v v0,\(a0\),v0.t'
++.*Error: illegal operands vd cannot overlap vm `vlseg7e128.v v0,\(a0\),v0.t'
++.*Error: illegal operands vd cannot overlap vm `vsseg7e128.v v0,\(a0\),v0.t'
++.*Error: illegal operands vd cannot overlap vm `vlseg7e128ff.v v0,\(a0\),v0.t'
++.*Error: illegal operands vd cannot overlap vm `vlseg8e128.v v0,\(a0\),v0.t'
++.*Error: illegal operands vd cannot overlap vm `vsseg8e128.v v0,\(a0\),v0.t'
++.*Error: illegal operands vd cannot overlap vm `vlseg8e128ff.v v0,\(a0\),v0.t'
++.*Error: illegal operands vd cannot overlap vm `vlseg2e256.v v0,\(a0\),v0.t'
++.*Error: illegal operands vd cannot overlap vm `vsseg2e256.v v0,\(a0\),v0.t'
++.*Error: illegal operands vd cannot overlap vm `vlseg2e256ff.v v0,\(a0\),v0.t'
++.*Error: illegal operands vd cannot overlap vm `vlseg3e256.v v0,\(a0\),v0.t'
++.*Error: illegal operands vd cannot overlap vm `vsseg3e256.v v0,\(a0\),v0.t'
++.*Error: illegal operands vd cannot overlap vm `vlseg3e256ff.v v0,\(a0\),v0.t'
++.*Error: illegal operands vd cannot overlap vm `vlseg4e256.v v0,\(a0\),v0.t'
++.*Error: illegal operands vd cannot overlap vm `vsseg4e256.v v0,\(a0\),v0.t'
++.*Error: illegal operands vd cannot overlap vm `vlseg4e256ff.v v0,\(a0\),v0.t'
++.*Error: illegal operands vd cannot overlap vm `vlseg5e256.v v0,\(a0\),v0.t'
++.*Error: illegal operands vd cannot overlap vm `vsseg5e256.v v0,\(a0\),v0.t'
++.*Error: illegal operands vd cannot overlap vm `vlseg5e256ff.v v0,\(a0\),v0.t'
++.*Error: illegal operands vd cannot overlap vm `vlseg6e256.v v0,\(a0\),v0.t'
++.*Error: illegal operands vd cannot overlap vm `vsseg6e256.v v0,\(a0\),v0.t'
++.*Error: illegal operands vd cannot overlap vm `vlseg6e256ff.v v0,\(a0\),v0.t'
++.*Error: illegal operands vd cannot overlap vm `vlseg7e256.v v0,\(a0\),v0.t'
++.*Error: illegal operands vd cannot overlap vm `vsseg7e256.v v0,\(a0\),v0.t'
++.*Error: illegal operands vd cannot overlap vm `vlseg7e256ff.v v0,\(a0\),v0.t'
++.*Error: illegal operands vd cannot overlap vm `vlseg8e256.v v0,\(a0\),v0.t'
++.*Error: illegal operands vd cannot overlap vm `vsseg8e256.v v0,\(a0\),v0.t'
++.*Error: illegal operands vd cannot overlap vm `vlseg8e256ff.v v0,\(a0\),v0.t'
++.*Error: illegal operands vd cannot overlap vm `vlseg2e512.v v0,\(a0\),v0.t'
++.*Error: illegal operands vd cannot overlap vm `vsseg2e512.v v0,\(a0\),v0.t'
++.*Error: illegal operands vd cannot overlap vm `vlseg2e512ff.v v0,\(a0\),v0.t'
++.*Error: illegal operands vd cannot overlap vm `vlseg3e512.v v0,\(a0\),v0.t'
++.*Error: illegal operands vd cannot overlap vm `vsseg3e512.v v0,\(a0\),v0.t'
++.*Error: illegal operands vd cannot overlap vm `vlseg3e512ff.v v0,\(a0\),v0.t'
++.*Error: illegal operands vd cannot overlap vm `vlseg4e512.v v0,\(a0\),v0.t'
++.*Error: illegal operands vd cannot overlap vm `vsseg4e512.v v0,\(a0\),v0.t'
++.*Error: illegal operands vd cannot overlap vm `vlseg4e512ff.v v0,\(a0\),v0.t'
++.*Error: illegal operands vd cannot overlap vm `vlseg5e512.v v0,\(a0\),v0.t'
++.*Error: illegal operands vd cannot overlap vm `vsseg5e512.v v0,\(a0\),v0.t'
++.*Error: illegal operands vd cannot overlap vm `vlseg5e512ff.v v0,\(a0\),v0.t'
++.*Error: illegal operands vd cannot overlap vm `vlseg6e512.v v0,\(a0\),v0.t'
++.*Error: illegal operands vd cannot overlap vm `vsseg6e512.v v0,\(a0\),v0.t'
++.*Error: illegal operands vd cannot overlap vm `vlseg6e512ff.v v0,\(a0\),v0.t'
++.*Error: illegal operands vd cannot overlap vm `vlseg7e512.v v0,\(a0\),v0.t'
++.*Error: illegal operands vd cannot overlap vm `vsseg7e512.v v0,\(a0\),v0.t'
++.*Error: illegal operands vd cannot overlap vm `vlseg7e512ff.v v0,\(a0\),v0.t'
++.*Error: illegal operands vd cannot overlap vm `vlseg8e512.v v0,\(a0\),v0.t'
++.*Error: illegal operands vd cannot overlap vm `vsseg8e512.v v0,\(a0\),v0.t'
++.*Error: illegal operands vd cannot overlap vm `vlseg8e512ff.v v0,\(a0\),v0.t'
++.*Error: illegal operands vd cannot overlap vm `vlseg2e1024.v v0,\(a0\),v0.t'
++.*Error: illegal operands vd cannot overlap vm `vsseg2e1024.v v0,\(a0\),v0.t'
++.*Error: illegal operands vd cannot overlap vm `vlseg2e1024ff.v v0,\(a0\),v0.t'
++.*Error: illegal operands vd cannot overlap vm `vlseg3e1024.v v0,\(a0\),v0.t'
++.*Error: illegal operands vd cannot overlap vm `vsseg3e1024.v v0,\(a0\),v0.t'
++.*Error: illegal operands vd cannot overlap vm `vlseg3e1024ff.v v0,\(a0\),v0.t'
++.*Error: illegal operands vd cannot overlap vm `vlseg4e1024.v v0,\(a0\),v0.t'
++.*Error: illegal operands vd cannot overlap vm `vsseg4e1024.v v0,\(a0\),v0.t'
++.*Error: illegal operands vd cannot overlap vm `vlseg4e1024ff.v v0,\(a0\),v0.t'
++.*Error: illegal operands vd cannot overlap vm `vlseg5e1024.v v0,\(a0\),v0.t'
++.*Error: illegal operands vd cannot overlap vm `vsseg5e1024.v v0,\(a0\),v0.t'
++.*Error: illegal operands vd cannot overlap vm `vlseg5e1024ff.v v0,\(a0\),v0.t'
++.*Error: illegal operands vd cannot overlap vm `vlseg6e1024.v v0,\(a0\),v0.t'
++.*Error: illegal operands vd cannot overlap vm `vsseg6e1024.v v0,\(a0\),v0.t'
++.*Error: illegal operands vd cannot overlap vm `vlseg6e1024ff.v v0,\(a0\),v0.t'
++.*Error: illegal operands vd cannot overlap vm `vlseg7e1024.v v0,\(a0\),v0.t'
++.*Error: illegal operands vd cannot overlap vm `vsseg7e1024.v v0,\(a0\),v0.t'
++.*Error: illegal operands vd cannot overlap vm `vlseg7e1024ff.v v0,\(a0\),v0.t'
++.*Error: illegal operands vd cannot overlap vm `vlseg8e1024.v v0,\(a0\),v0.t'
++.*Error: illegal operands vd cannot overlap vm `vsseg8e1024.v v0,\(a0\),v0.t'
++.*Error: illegal operands vd cannot overlap vm `vlseg8e1024ff.v v0,\(a0\),v0.t'
++.*Error: illegal operands vd cannot overlap vm `vlsseg2e8.v v0,\(a0\),a1,v0.t'
++.*Error: illegal operands vd cannot overlap vm `vssseg2e8.v v0,\(a0\),a1,v0.t'
++.*Error: illegal operands vd cannot overlap vm `vlsseg3e8.v v0,\(a0\),a1,v0.t'
++.*Error: illegal operands vd cannot overlap vm `vssseg3e8.v v0,\(a0\),a1,v0.t'
++.*Error: illegal operands vd cannot overlap vm `vlsseg4e8.v v0,\(a0\),a1,v0.t'
++.*Error: illegal operands vd cannot overlap vm `vssseg4e8.v v0,\(a0\),a1,v0.t'
++.*Error: illegal operands vd cannot overlap vm `vlsseg5e8.v v0,\(a0\),a1,v0.t'
++.*Error: illegal operands vd cannot overlap vm `vssseg5e8.v v0,\(a0\),a1,v0.t'
++.*Error: illegal operands vd cannot overlap vm `vlsseg6e8.v v0,\(a0\),a1,v0.t'
++.*Error: illegal operands vd cannot overlap vm `vssseg6e8.v v0,\(a0\),a1,v0.t'
++.*Error: illegal operands vd cannot overlap vm `vlsseg7e8.v v0,\(a0\),a1,v0.t'
++.*Error: illegal operands vd cannot overlap vm `vssseg7e8.v v0,\(a0\),a1,v0.t'
++.*Error: illegal operands vd cannot overlap vm `vlsseg8e8.v v0,\(a0\),a1,v0.t'
++.*Error: illegal operands vd cannot overlap vm `vssseg8e8.v v0,\(a0\),a1,v0.t'
++.*Error: illegal operands vd cannot overlap vm `vlsseg2e16.v v0,\(a0\),a1,v0.t'
++.*Error: illegal operands vd cannot overlap vm `vssseg2e16.v v0,\(a0\),a1,v0.t'
++.*Error: illegal operands vd cannot overlap vm `vlsseg3e16.v v0,\(a0\),a1,v0.t'
++.*Error: illegal operands vd cannot overlap vm `vssseg3e16.v v0,\(a0\),a1,v0.t'
++.*Error: illegal operands vd cannot overlap vm `vlsseg4e16.v v0,\(a0\),a1,v0.t'
++.*Error: illegal operands vd cannot overlap vm `vssseg4e16.v v0,\(a0\),a1,v0.t'
++.*Error: illegal operands vd cannot overlap vm `vlsseg5e16.v v0,\(a0\),a1,v0.t'
++.*Error: illegal operands vd cannot overlap vm `vssseg5e16.v v0,\(a0\),a1,v0.t'
++.*Error: illegal operands vd cannot overlap vm `vlsseg6e16.v v0,\(a0\),a1,v0.t'
++.*Error: illegal operands vd cannot overlap vm `vssseg6e16.v v0,\(a0\),a1,v0.t'
++.*Error: illegal operands vd cannot overlap vm `vlsseg7e16.v v0,\(a0\),a1,v0.t'
++.*Error: illegal operands vd cannot overlap vm `vssseg7e16.v v0,\(a0\),a1,v0.t'
++.*Error: illegal operands vd cannot overlap vm `vlsseg8e16.v v0,\(a0\),a1,v0.t'
++.*Error: illegal operands vd cannot overlap vm `vssseg8e16.v v0,\(a0\),a1,v0.t'
++.*Error: illegal operands vd cannot overlap vm `vlsseg2e32.v v0,\(a0\),a1,v0.t'
++.*Error: illegal operands vd cannot overlap vm `vssseg2e32.v v0,\(a0\),a1,v0.t'
++.*Error: illegal operands vd cannot overlap vm `vlsseg3e32.v v0,\(a0\),a1,v0.t'
++.*Error: illegal operands vd cannot overlap vm `vssseg3e32.v v0,\(a0\),a1,v0.t'
++.*Error: illegal operands vd cannot overlap vm `vlsseg4e32.v v0,\(a0\),a1,v0.t'
++.*Error: illegal operands vd cannot overlap vm `vssseg4e32.v v0,\(a0\),a1,v0.t'
++.*Error: illegal operands vd cannot overlap vm `vlsseg5e32.v v0,\(a0\),a1,v0.t'
++.*Error: illegal operands vd cannot overlap vm `vssseg5e32.v v0,\(a0\),a1,v0.t'
++.*Error: illegal operands vd cannot overlap vm `vlsseg6e32.v v0,\(a0\),a1,v0.t'
++.*Error: illegal operands vd cannot overlap vm `vssseg6e32.v v0,\(a0\),a1,v0.t'
++.*Error: illegal operands vd cannot overlap vm `vlsseg7e32.v v0,\(a0\),a1,v0.t'
++.*Error: illegal operands vd cannot overlap vm `vssseg7e32.v v0,\(a0\),a1,v0.t'
++.*Error: illegal operands vd cannot overlap vm `vlsseg8e32.v v0,\(a0\),a1,v0.t'
++.*Error: illegal operands vd cannot overlap vm `vssseg8e32.v v0,\(a0\),a1,v0.t'
++.*Error: illegal operands vd cannot overlap vm `vlsseg2e64.v v0,\(a0\),a1,v0.t'
++.*Error: illegal operands vd cannot overlap vm `vssseg2e64.v v0,\(a0\),a1,v0.t'
++.*Error: illegal operands vd cannot overlap vm `vlsseg3e64.v v0,\(a0\),a1,v0.t'
++.*Error: illegal operands vd cannot overlap vm `vssseg3e64.v v0,\(a0\),a1,v0.t'
++.*Error: illegal operands vd cannot overlap vm `vlsseg4e64.v v0,\(a0\),a1,v0.t'
++.*Error: illegal operands vd cannot overlap vm `vssseg4e64.v v0,\(a0\),a1,v0.t'
++.*Error: illegal operands vd cannot overlap vm `vlsseg5e64.v v0,\(a0\),a1,v0.t'
++.*Error: illegal operands vd cannot overlap vm `vssseg5e64.v v0,\(a0\),a1,v0.t'
++.*Error: illegal operands vd cannot overlap vm `vlsseg6e64.v v0,\(a0\),a1,v0.t'
++.*Error: illegal operands vd cannot overlap vm `vssseg6e64.v v0,\(a0\),a1,v0.t'
++.*Error: illegal operands vd cannot overlap vm `vlsseg7e64.v v0,\(a0\),a1,v0.t'
++.*Error: illegal operands vd cannot overlap vm `vssseg7e64.v v0,\(a0\),a1,v0.t'
++.*Error: illegal operands vd cannot overlap vm `vlsseg8e64.v v0,\(a0\),a1,v0.t'
++.*Error: illegal operands vd cannot overlap vm `vssseg8e64.v v0,\(a0\),a1,v0.t'
++.*Error: illegal operands vd cannot overlap vm `vlsseg2e128.v v0,\(a0\),a1,v0.t'
++.*Error: illegal operands vd cannot overlap vm `vssseg2e128.v v0,\(a0\),a1,v0.t'
++.*Error: illegal operands vd cannot overlap vm `vlsseg3e128.v v0,\(a0\),a1,v0.t'
++.*Error: illegal operands vd cannot overlap vm `vssseg3e128.v v0,\(a0\),a1,v0.t'
++.*Error: illegal operands vd cannot overlap vm `vlsseg4e128.v v0,\(a0\),a1,v0.t'
++.*Error: illegal operands vd cannot overlap vm `vssseg4e128.v v0,\(a0\),a1,v0.t'
++.*Error: illegal operands vd cannot overlap vm `vlsseg5e128.v v0,\(a0\),a1,v0.t'
++.*Error: illegal operands vd cannot overlap vm `vssseg5e128.v v0,\(a0\),a1,v0.t'
++.*Error: illegal operands vd cannot overlap vm `vlsseg6e128.v v0,\(a0\),a1,v0.t'
++.*Error: illegal operands vd cannot overlap vm `vssseg6e128.v v0,\(a0\),a1,v0.t'
++.*Error: illegal operands vd cannot overlap vm `vlsseg7e128.v v0,\(a0\),a1,v0.t'
++.*Error: illegal operands vd cannot overlap vm `vssseg7e128.v v0,\(a0\),a1,v0.t'
++.*Error: illegal operands vd cannot overlap vm `vlsseg8e128.v v0,\(a0\),a1,v0.t'
++.*Error: illegal operands vd cannot overlap vm `vssseg8e128.v v0,\(a0\),a1,v0.t'
++.*Error: illegal operands vd cannot overlap vm `vlsseg2e256.v v0,\(a0\),a1,v0.t'
++.*Error: illegal operands vd cannot overlap vm `vssseg2e256.v v0,\(a0\),a1,v0.t'
++.*Error: illegal operands vd cannot overlap vm `vlsseg3e256.v v0,\(a0\),a1,v0.t'
++.*Error: illegal operands vd cannot overlap vm `vssseg3e256.v v0,\(a0\),a1,v0.t'
++.*Error: illegal operands vd cannot overlap vm `vlsseg4e256.v v0,\(a0\),a1,v0.t'
++.*Error: illegal operands vd cannot overlap vm `vssseg4e256.v v0,\(a0\),a1,v0.t'
++.*Error: illegal operands vd cannot overlap vm `vlsseg5e256.v v0,\(a0\),a1,v0.t'
++.*Error: illegal operands vd cannot overlap vm `vssseg5e256.v v0,\(a0\),a1,v0.t'
++.*Error: illegal operands vd cannot overlap vm `vlsseg6e256.v v0,\(a0\),a1,v0.t'
++.*Error: illegal operands vd cannot overlap vm `vssseg6e256.v v0,\(a0\),a1,v0.t'
++.*Error: illegal operands vd cannot overlap vm `vlsseg7e256.v v0,\(a0\),a1,v0.t'
++.*Error: illegal operands vd cannot overlap vm `vssseg7e256.v v0,\(a0\),a1,v0.t'
++.*Error: illegal operands vd cannot overlap vm `vlsseg8e256.v v0,\(a0\),a1,v0.t'
++.*Error: illegal operands vd cannot overlap vm `vssseg8e256.v v0,\(a0\),a1,v0.t'
++.*Error: illegal operands vd cannot overlap vm `vlsseg2e512.v v0,\(a0\),a1,v0.t'
++.*Error: illegal operands vd cannot overlap vm `vssseg2e512.v v0,\(a0\),a1,v0.t'
++.*Error: illegal operands vd cannot overlap vm `vlsseg3e512.v v0,\(a0\),a1,v0.t'
++.*Error: illegal operands vd cannot overlap vm `vssseg3e512.v v0,\(a0\),a1,v0.t'
++.*Error: illegal operands vd cannot overlap vm `vlsseg4e512.v v0,\(a0\),a1,v0.t'
++.*Error: illegal operands vd cannot overlap vm `vssseg4e512.v v0,\(a0\),a1,v0.t'
++.*Error: illegal operands vd cannot overlap vm `vlsseg5e512.v v0,\(a0\),a1,v0.t'
++.*Error: illegal operands vd cannot overlap vm `vssseg5e512.v v0,\(a0\),a1,v0.t'
++.*Error: illegal operands vd cannot overlap vm `vlsseg6e512.v v0,\(a0\),a1,v0.t'
++.*Error: illegal operands vd cannot overlap vm `vssseg6e512.v v0,\(a0\),a1,v0.t'
++.*Error: illegal operands vd cannot overlap vm `vlsseg7e512.v v0,\(a0\),a1,v0.t'
++.*Error: illegal operands vd cannot overlap vm `vssseg7e512.v v0,\(a0\),a1,v0.t'
++.*Error: illegal operands vd cannot overlap vm `vlsseg8e512.v v0,\(a0\),a1,v0.t'
++.*Error: illegal operands vd cannot overlap vm `vssseg8e512.v v0,\(a0\),a1,v0.t'
++.*Error: illegal operands vd cannot overlap vm `vlsseg2e1024.v v0,\(a0\),a1,v0.t'
++.*Error: illegal operands vd cannot overlap vm `vssseg2e1024.v v0,\(a0\),a1,v0.t'
++.*Error: illegal operands vd cannot overlap vm `vlsseg3e1024.v v0,\(a0\),a1,v0.t'
++.*Error: illegal operands vd cannot overlap vm `vssseg3e1024.v v0,\(a0\),a1,v0.t'
++.*Error: illegal operands vd cannot overlap vm `vlsseg4e1024.v v0,\(a0\),a1,v0.t'
++.*Error: illegal operands vd cannot overlap vm `vssseg4e1024.v v0,\(a0\),a1,v0.t'
++.*Error: illegal operands vd cannot overlap vm `vlsseg5e1024.v v0,\(a0\),a1,v0.t'
++.*Error: illegal operands vd cannot overlap vm `vssseg5e1024.v v0,\(a0\),a1,v0.t'
++.*Error: illegal operands vd cannot overlap vm `vlsseg6e1024.v v0,\(a0\),a1,v0.t'
++.*Error: illegal operands vd cannot overlap vm `vssseg6e1024.v v0,\(a0\),a1,v0.t'
++.*Error: illegal operands vd cannot overlap vm `vlsseg7e1024.v v0,\(a0\),a1,v0.t'
++.*Error: illegal operands vd cannot overlap vm `vssseg7e1024.v v0,\(a0\),a1,v0.t'
++.*Error: illegal operands vd cannot overlap vm `vlsseg8e1024.v v0,\(a0\),a1,v0.t'
++.*Error: illegal operands vd cannot overlap vm `vssseg8e1024.v v0,\(a0\),a1,v0.t'
++.*Error: illegal operands vd cannot overlap vs2 `vlxseg2ei8.v v4,\(a0\),v4'
++.*Error: illegal operands vd cannot overlap vm `vlxseg2ei8.v v0,\(a0\),v4,v0.t'
++.*Error: illegal operands vd cannot overlap vs2 `vsxseg2ei8.v v4,\(a0\),v4'
++.*Error: illegal operands vd cannot overlap vm `vsxseg2ei8.v v0,\(a0\),v4,v0.t'
++.*Error: illegal operands vd cannot overlap vs2 `vlxseg3ei8.v v4,\(a0\),v4'
++.*Error: illegal operands vd cannot overlap vm `vlxseg3ei8.v v0,\(a0\),v4,v0.t'
++.*Error: illegal operands vd cannot overlap vs2 `vsxseg3ei8.v v4,\(a0\),v4'
++.*Error: illegal operands vd cannot overlap vm `vsxseg3ei8.v v0,\(a0\),v4,v0.t'
++.*Error: illegal operands vd cannot overlap vs2 `vlxseg4ei8.v v4,\(a0\),v4'
++.*Error: illegal operands vd cannot overlap vm `vlxseg4ei8.v v0,\(a0\),v4,v0.t'
++.*Error: illegal operands vd cannot overlap vs2 `vsxseg4ei8.v v4,\(a0\),v4'
++.*Error: illegal operands vd cannot overlap vm `vsxseg4ei8.v v0,\(a0\),v4,v0.t'
++.*Error: illegal operands vd cannot overlap vs2 `vlxseg5ei8.v v4,\(a0\),v4'
++.*Error: illegal operands vd cannot overlap vm `vlxseg5ei8.v v0,\(a0\),v4,v0.t'
++.*Error: illegal operands vd cannot overlap vs2 `vsxseg5ei8.v v4,\(a0\),v4'
++.*Error: illegal operands vd cannot overlap vm `vsxseg5ei8.v v0,\(a0\),v4,v0.t'
++.*Error: illegal operands vd cannot overlap vs2 `vlxseg6ei8.v v4,\(a0\),v4'
++.*Error: illegal operands vd cannot overlap vm `vlxseg6ei8.v v0,\(a0\),v4,v0.t'
++.*Error: illegal operands vd cannot overlap vs2 `vsxseg6ei8.v v4,\(a0\),v4'
++.*Error: illegal operands vd cannot overlap vm `vsxseg6ei8.v v0,\(a0\),v4,v0.t'
++.*Error: illegal operands vd cannot overlap vs2 `vlxseg7ei8.v v4,\(a0\),v4'
++.*Error: illegal operands vd cannot overlap vm `vlxseg7ei8.v v0,\(a0\),v4,v0.t'
++.*Error: illegal operands vd cannot overlap vs2 `vsxseg7ei8.v v4,\(a0\),v4'
++.*Error: illegal operands vd cannot overlap vm `vsxseg7ei8.v v0,\(a0\),v4,v0.t'
++.*Error: illegal operands vd cannot overlap vs2 `vlxseg8ei8.v v4,\(a0\),v4'
++.*Error: illegal operands vd cannot overlap vm `vlxseg8ei8.v v0,\(a0\),v4,v0.t'
++.*Error: illegal operands vd cannot overlap vs2 `vsxseg8ei8.v v4,\(a0\),v4'
++.*Error: illegal operands vd cannot overlap vm `vsxseg8ei8.v v0,\(a0\),v4,v0.t'
++.*Error: illegal operands vd cannot overlap vs2 `vlxseg2ei16.v v4,\(a0\),v4'
++.*Error: illegal operands vd cannot overlap vm `vlxseg2ei16.v v0,\(a0\),v4,v0.t'
++.*Error: illegal operands vd cannot overlap vs2 `vsxseg2ei16.v v4,\(a0\),v4'
++.*Error: illegal operands vd cannot overlap vm `vsxseg2ei16.v v0,\(a0\),v4,v0.t'
++.*Error: illegal operands vd cannot overlap vs2 `vlxseg3ei16.v v4,\(a0\),v4'
++.*Error: illegal operands vd cannot overlap vm `vlxseg3ei16.v v0,\(a0\),v4,v0.t'
++.*Error: illegal operands vd cannot overlap vs2 `vsxseg3ei16.v v4,\(a0\),v4'
++.*Error: illegal operands vd cannot overlap vm `vsxseg3ei16.v v0,\(a0\),v4,v0.t'
++.*Error: illegal operands vd cannot overlap vs2 `vlxseg4ei16.v v4,\(a0\),v4'
++.*Error: illegal operands vd cannot overlap vm `vlxseg4ei16.v v0,\(a0\),v4,v0.t'
++.*Error: illegal operands vd cannot overlap vs2 `vsxseg4ei16.v v4,\(a0\),v4'
++.*Error: illegal operands vd cannot overlap vm `vsxseg4ei16.v v0,\(a0\),v4,v0.t'
++.*Error: illegal operands vd cannot overlap vs2 `vlxseg5ei16.v v4,\(a0\),v4'
++.*Error: illegal operands vd cannot overlap vm `vlxseg5ei16.v v0,\(a0\),v4,v0.t'
++.*Error: illegal operands vd cannot overlap vs2 `vsxseg5ei16.v v4,\(a0\),v4'
++.*Error: illegal operands vd cannot overlap vm `vsxseg5ei16.v v0,\(a0\),v4,v0.t'
++.*Error: illegal operands vd cannot overlap vs2 `vlxseg6ei16.v v4,\(a0\),v4'
++.*Error: illegal operands vd cannot overlap vm `vlxseg6ei16.v v0,\(a0\),v4,v0.t'
++.*Error: illegal operands vd cannot overlap vs2 `vsxseg6ei16.v v4,\(a0\),v4'
++.*Error: illegal operands vd cannot overlap vm `vsxseg6ei16.v v0,\(a0\),v4,v0.t'
++.*Error: illegal operands vd cannot overlap vs2 `vlxseg7ei16.v v4,\(a0\),v4'
++.*Error: illegal operands vd cannot overlap vm `vlxseg7ei16.v v0,\(a0\),v4,v0.t'
++.*Error: illegal operands vd cannot overlap vs2 `vsxseg7ei16.v v4,\(a0\),v4'
++.*Error: illegal operands vd cannot overlap vm `vsxseg7ei16.v v0,\(a0\),v4,v0.t'
++.*Error: illegal operands vd cannot overlap vs2 `vlxseg8ei16.v v4,\(a0\),v4'
++.*Error: illegal operands vd cannot overlap vm `vlxseg8ei16.v v0,\(a0\),v4,v0.t'
++.*Error: illegal operands vd cannot overlap vs2 `vsxseg8ei16.v v4,\(a0\),v4'
++.*Error: illegal operands vd cannot overlap vm `vsxseg8ei16.v v0,\(a0\),v4,v0.t'
++.*Error: illegal operands vd cannot overlap vs2 `vlxseg2ei32.v v4,\(a0\),v4'
++.*Error: illegal operands vd cannot overlap vm `vlxseg2ei32.v v0,\(a0\),v4,v0.t'
++.*Error: illegal operands vd cannot overlap vs2 `vsxseg2ei32.v v4,\(a0\),v4'
++.*Error: illegal operands vd cannot overlap vm `vsxseg2ei32.v v0,\(a0\),v4,v0.t'
++.*Error: illegal operands vd cannot overlap vs2 `vlxseg3ei32.v v4,\(a0\),v4'
++.*Error: illegal operands vd cannot overlap vm `vlxseg3ei32.v v0,\(a0\),v4,v0.t'
++.*Error: illegal operands vd cannot overlap vs2 `vsxseg3ei32.v v4,\(a0\),v4'
++.*Error: illegal operands vd cannot overlap vm `vsxseg3ei32.v v0,\(a0\),v4,v0.t'
++.*Error: illegal operands vd cannot overlap vs2 `vlxseg4ei32.v v4,\(a0\),v4'
++.*Error: illegal operands vd cannot overlap vm `vlxseg4ei32.v v0,\(a0\),v4,v0.t'
++.*Error: illegal operands vd cannot overlap vs2 `vsxseg4ei32.v v4,\(a0\),v4'
++.*Error: illegal operands vd cannot overlap vm `vsxseg4ei32.v v0,\(a0\),v4,v0.t'
++.*Error: illegal operands vd cannot overlap vs2 `vlxseg5ei32.v v4,\(a0\),v4'
++.*Error: illegal operands vd cannot overlap vm `vlxseg5ei32.v v0,\(a0\),v4,v0.t'
++.*Error: illegal operands vd cannot overlap vs2 `vsxseg5ei32.v v4,\(a0\),v4'
++.*Error: illegal operands vd cannot overlap vm `vsxseg5ei32.v v0,\(a0\),v4,v0.t'
++.*Error: illegal operands vd cannot overlap vs2 `vlxseg6ei32.v v4,\(a0\),v4'
++.*Error: illegal operands vd cannot overlap vm `vlxseg6ei32.v v0,\(a0\),v4,v0.t'
++.*Error: illegal operands vd cannot overlap vs2 `vsxseg6ei32.v v4,\(a0\),v4'
++.*Error: illegal operands vd cannot overlap vm `vsxseg6ei32.v v0,\(a0\),v4,v0.t'
++.*Error: illegal operands vd cannot overlap vs2 `vlxseg7ei32.v v4,\(a0\),v4'
++.*Error: illegal operands vd cannot overlap vm `vlxseg7ei32.v v0,\(a0\),v4,v0.t'
++.*Error: illegal operands vd cannot overlap vs2 `vsxseg7ei32.v v4,\(a0\),v4'
++.*Error: illegal operands vd cannot overlap vm `vsxseg7ei32.v v0,\(a0\),v4,v0.t'
++.*Error: illegal operands vd cannot overlap vs2 `vlxseg8ei32.v v4,\(a0\),v4'
++.*Error: illegal operands vd cannot overlap vm `vlxseg8ei32.v v0,\(a0\),v4,v0.t'
++.*Error: illegal operands vd cannot overlap vs2 `vsxseg8ei32.v v4,\(a0\),v4'
++.*Error: illegal operands vd cannot overlap vm `vsxseg8ei32.v v0,\(a0\),v4,v0.t'
++.*Error: illegal operands vd cannot overlap vs2 `vlxseg2ei64.v v4,\(a0\),v4'
++.*Error: illegal operands vd cannot overlap vm `vlxseg2ei64.v v0,\(a0\),v4,v0.t'
++.*Error: illegal operands vd cannot overlap vs2 `vsxseg2ei64.v v4,\(a0\),v4'
++.*Error: illegal operands vd cannot overlap vm `vsxseg2ei64.v v0,\(a0\),v4,v0.t'
++.*Error: illegal operands vd cannot overlap vs2 `vlxseg3ei64.v v4,\(a0\),v4'
++.*Error: illegal operands vd cannot overlap vm `vlxseg3ei64.v v0,\(a0\),v4,v0.t'
++.*Error: illegal operands vd cannot overlap vs2 `vsxseg3ei64.v v4,\(a0\),v4'
++.*Error: illegal operands vd cannot overlap vm `vsxseg3ei64.v v0,\(a0\),v4,v0.t'
++.*Error: illegal operands vd cannot overlap vs2 `vlxseg4ei64.v v4,\(a0\),v4'
++.*Error: illegal operands vd cannot overlap vm `vlxseg4ei64.v v0,\(a0\),v4,v0.t'
++.*Error: illegal operands vd cannot overlap vs2 `vsxseg4ei64.v v4,\(a0\),v4'
++.*Error: illegal operands vd cannot overlap vm `vsxseg4ei64.v v0,\(a0\),v4,v0.t'
++.*Error: illegal operands vd cannot overlap vs2 `vlxseg5ei64.v v4,\(a0\),v4'
++.*Error: illegal operands vd cannot overlap vm `vlxseg5ei64.v v0,\(a0\),v4,v0.t'
++.*Error: illegal operands vd cannot overlap vs2 `vsxseg5ei64.v v4,\(a0\),v4'
++.*Error: illegal operands vd cannot overlap vm `vsxseg5ei64.v v0,\(a0\),v4,v0.t'
++.*Error: illegal operands vd cannot overlap vs2 `vlxseg6ei64.v v4,\(a0\),v4'
++.*Error: illegal operands vd cannot overlap vm `vlxseg6ei64.v v0,\(a0\),v4,v0.t'
++.*Error: illegal operands vd cannot overlap vs2 `vsxseg6ei64.v v4,\(a0\),v4'
++.*Error: illegal operands vd cannot overlap vm `vsxseg6ei64.v v0,\(a0\),v4,v0.t'
++.*Error: illegal operands vd cannot overlap vs2 `vlxseg7ei64.v v4,\(a0\),v4'
++.*Error: illegal operands vd cannot overlap vm `vlxseg7ei64.v v0,\(a0\),v4,v0.t'
++.*Error: illegal operands vd cannot overlap vs2 `vsxseg7ei64.v v4,\(a0\),v4'
++.*Error: illegal operands vd cannot overlap vm `vsxseg7ei64.v v0,\(a0\),v4,v0.t'
++.*Error: illegal operands vd cannot overlap vs2 `vlxseg8ei64.v v4,\(a0\),v4'
++.*Error: illegal operands vd cannot overlap vm `vlxseg8ei64.v v0,\(a0\),v4,v0.t'
++.*Error: illegal operands vd cannot overlap vs2 `vsxseg8ei64.v v4,\(a0\),v4'
++.*Error: illegal operands vd cannot overlap vm `vsxseg8ei64.v v0,\(a0\),v4,v0.t'
++.*Error: illegal operands vd cannot overlap vs2 `vlxseg2ei128.v v4,\(a0\),v4'
++.*Error: illegal operands vd cannot overlap vm `vlxseg2ei128.v v0,\(a0\),v4,v0.t'
++.*Error: illegal operands vd cannot overlap vs2 `vsxseg2ei128.v v4,\(a0\),v4'
++.*Error: illegal operands vd cannot overlap vm `vsxseg2ei128.v v0,\(a0\),v4,v0.t'
++.*Error: illegal operands vd cannot overlap vs2 `vlxseg3ei128.v v4,\(a0\),v4'
++.*Error: illegal operands vd cannot overlap vm `vlxseg3ei128.v v0,\(a0\),v4,v0.t'
++.*Error: illegal operands vd cannot overlap vs2 `vsxseg3ei128.v v4,\(a0\),v4'
++.*Error: illegal operands vd cannot overlap vm `vsxseg3ei128.v v0,\(a0\),v4,v0.t'
++.*Error: illegal operands vd cannot overlap vs2 `vlxseg4ei128.v v4,\(a0\),v4'
++.*Error: illegal operands vd cannot overlap vm `vlxseg4ei128.v v0,\(a0\),v4,v0.t'
++.*Error: illegal operands vd cannot overlap vs2 `vsxseg4ei128.v v4,\(a0\),v4'
++.*Error: illegal operands vd cannot overlap vm `vsxseg4ei128.v v0,\(a0\),v4,v0.t'
++.*Error: illegal operands vd cannot overlap vs2 `vlxseg5ei128.v v4,\(a0\),v4'
++.*Error: illegal operands vd cannot overlap vm `vlxseg5ei128.v v0,\(a0\),v4,v0.t'
++.*Error: illegal operands vd cannot overlap vs2 `vsxseg5ei128.v v4,\(a0\),v4'
++.*Error: illegal operands vd cannot overlap vm `vsxseg5ei128.v v0,\(a0\),v4,v0.t'
++.*Error: illegal operands vd cannot overlap vs2 `vlxseg6ei128.v v4,\(a0\),v4'
++.*Error: illegal operands vd cannot overlap vm `vlxseg6ei128.v v0,\(a0\),v4,v0.t'
++.*Error: illegal operands vd cannot overlap vs2 `vsxseg6ei128.v v4,\(a0\),v4'
++.*Error: illegal operands vd cannot overlap vm `vsxseg6ei128.v v0,\(a0\),v4,v0.t'
++.*Error: illegal operands vd cannot overlap vs2 `vlxseg7ei128.v v4,\(a0\),v4'
++.*Error: illegal operands vd cannot overlap vm `vlxseg7ei128.v v0,\(a0\),v4,v0.t'
++.*Error: illegal operands vd cannot overlap vs2 `vsxseg7ei128.v v4,\(a0\),v4'
++.*Error: illegal operands vd cannot overlap vm `vsxseg7ei128.v v0,\(a0\),v4,v0.t'
++.*Error: illegal operands vd cannot overlap vs2 `vlxseg8ei128.v v4,\(a0\),v4'
++.*Error: illegal operands vd cannot overlap vm `vlxseg8ei128.v v0,\(a0\),v4,v0.t'
++.*Error: illegal operands vd cannot overlap vs2 `vsxseg8ei128.v v4,\(a0\),v4'
++.*Error: illegal operands vd cannot overlap vm `vsxseg8ei128.v v0,\(a0\),v4,v0.t'
++.*Error: illegal operands vd cannot overlap vs2 `vlxseg2ei256.v v4,\(a0\),v4'
++.*Error: illegal operands vd cannot overlap vm `vlxseg2ei256.v v0,\(a0\),v4,v0.t'
++.*Error: illegal operands vd cannot overlap vs2 `vsxseg2ei256.v v4,\(a0\),v4'
++.*Error: illegal operands vd cannot overlap vm `vsxseg2ei256.v v0,\(a0\),v4,v0.t'
++.*Error: illegal operands vd cannot overlap vs2 `vlxseg3ei256.v v4,\(a0\),v4'
++.*Error: illegal operands vd cannot overlap vm `vlxseg3ei256.v v0,\(a0\),v4,v0.t'
++.*Error: illegal operands vd cannot overlap vs2 `vsxseg3ei256.v v4,\(a0\),v4'
++.*Error: illegal operands vd cannot overlap vm `vsxseg3ei256.v v0,\(a0\),v4,v0.t'
++.*Error: illegal operands vd cannot overlap vs2 `vlxseg4ei256.v v4,\(a0\),v4'
++.*Error: illegal operands vd cannot overlap vm `vlxseg4ei256.v v0,\(a0\),v4,v0.t'
++.*Error: illegal operands vd cannot overlap vs2 `vsxseg4ei256.v v4,\(a0\),v4'
++.*Error: illegal operands vd cannot overlap vm `vsxseg4ei256.v v0,\(a0\),v4,v0.t'
++.*Error: illegal operands vd cannot overlap vs2 `vlxseg5ei256.v v4,\(a0\),v4'
++.*Error: illegal operands vd cannot overlap vm `vlxseg5ei256.v v0,\(a0\),v4,v0.t'
++.*Error: illegal operands vd cannot overlap vs2 `vsxseg5ei256.v v4,\(a0\),v4'
++.*Error: illegal operands vd cannot overlap vm `vsxseg5ei256.v v0,\(a0\),v4,v0.t'
++.*Error: illegal operands vd cannot overlap vs2 `vlxseg6ei256.v v4,\(a0\),v4'
++.*Error: illegal operands vd cannot overlap vm `vlxseg6ei256.v v0,\(a0\),v4,v0.t'
++.*Error: illegal operands vd cannot overlap vs2 `vsxseg6ei256.v v4,\(a0\),v4'
++.*Error: illegal operands vd cannot overlap vm `vsxseg6ei256.v v0,\(a0\),v4,v0.t'
++.*Error: illegal operands vd cannot overlap vs2 `vlxseg7ei256.v v4,\(a0\),v4'
++.*Error: illegal operands vd cannot overlap vm `vlxseg7ei256.v v0,\(a0\),v4,v0.t'
++.*Error: illegal operands vd cannot overlap vs2 `vsxseg7ei256.v v4,\(a0\),v4'
++.*Error: illegal operands vd cannot overlap vm `vsxseg7ei256.v v0,\(a0\),v4,v0.t'
++.*Error: illegal operands vd cannot overlap vs2 `vlxseg8ei256.v v4,\(a0\),v4'
++.*Error: illegal operands vd cannot overlap vm `vlxseg8ei256.v v0,\(a0\),v4,v0.t'
++.*Error: illegal operands vd cannot overlap vs2 `vsxseg8ei256.v v4,\(a0\),v4'
++.*Error: illegal operands vd cannot overlap vm `vsxseg8ei256.v v0,\(a0\),v4,v0.t'
++.*Error: illegal operands vd cannot overlap vs2 `vlxseg2ei512.v v4,\(a0\),v4'
++.*Error: illegal operands vd cannot overlap vm `vlxseg2ei512.v v0,\(a0\),v4,v0.t'
++.*Error: illegal operands vd cannot overlap vs2 `vsxseg2ei512.v v4,\(a0\),v4'
++.*Error: illegal operands vd cannot overlap vm `vsxseg2ei512.v v0,\(a0\),v4,v0.t'
++.*Error: illegal operands vd cannot overlap vs2 `vlxseg3ei512.v v4,\(a0\),v4'
++.*Error: illegal operands vd cannot overlap vm `vlxseg3ei512.v v0,\(a0\),v4,v0.t'
++.*Error: illegal operands vd cannot overlap vs2 `vsxseg3ei512.v v4,\(a0\),v4'
++.*Error: illegal operands vd cannot overlap vm `vsxseg3ei512.v v0,\(a0\),v4,v0.t'
++.*Error: illegal operands vd cannot overlap vs2 `vlxseg4ei512.v v4,\(a0\),v4'
++.*Error: illegal operands vd cannot overlap vm `vlxseg4ei512.v v0,\(a0\),v4,v0.t'
++.*Error: illegal operands vd cannot overlap vs2 `vsxseg4ei512.v v4,\(a0\),v4'
++.*Error: illegal operands vd cannot overlap vm `vsxseg4ei512.v v0,\(a0\),v4,v0.t'
++.*Error: illegal operands vd cannot overlap vs2 `vlxseg5ei512.v v4,\(a0\),v4'
++.*Error: illegal operands vd cannot overlap vm `vlxseg5ei512.v v0,\(a0\),v4,v0.t'
++.*Error: illegal operands vd cannot overlap vs2 `vsxseg5ei512.v v4,\(a0\),v4'
++.*Error: illegal operands vd cannot overlap vm `vsxseg5ei512.v v0,\(a0\),v4,v0.t'
++.*Error: illegal operands vd cannot overlap vs2 `vlxseg6ei512.v v4,\(a0\),v4'
++.*Error: illegal operands vd cannot overlap vm `vlxseg6ei512.v v0,\(a0\),v4,v0.t'
++.*Error: illegal operands vd cannot overlap vs2 `vsxseg6ei512.v v4,\(a0\),v4'
++.*Error: illegal operands vd cannot overlap vm `vsxseg6ei512.v v0,\(a0\),v4,v0.t'
++.*Error: illegal operands vd cannot overlap vs2 `vlxseg7ei512.v v4,\(a0\),v4'
++.*Error: illegal operands vd cannot overlap vm `vlxseg7ei512.v v0,\(a0\),v4,v0.t'
++.*Error: illegal operands vd cannot overlap vs2 `vsxseg7ei512.v v4,\(a0\),v4'
++.*Error: illegal operands vd cannot overlap vm `vsxseg7ei512.v v0,\(a0\),v4,v0.t'
++.*Error: illegal operands vd cannot overlap vs2 `vlxseg8ei512.v v4,\(a0\),v4'
++.*Error: illegal operands vd cannot overlap vm `vlxseg8ei512.v v0,\(a0\),v4,v0.t'
++.*Error: illegal operands vd cannot overlap vs2 `vsxseg8ei512.v v4,\(a0\),v4'
++.*Error: illegal operands vd cannot overlap vm `vsxseg8ei512.v v0,\(a0\),v4,v0.t'
++.*Error: illegal operands vd cannot overlap vs2 `vlxseg2ei1024.v v4,\(a0\),v4'
++.*Error: illegal operands vd cannot overlap vm `vlxseg2ei1024.v v0,\(a0\),v4,v0.t'
++.*Error: illegal operands vd cannot overlap vs2 `vsxseg2ei1024.v v4,\(a0\),v4'
++.*Error: illegal operands vd cannot overlap vm `vsxseg2ei1024.v v0,\(a0\),v4,v0.t'
++.*Error: illegal operands vd cannot overlap vs2 `vlxseg3ei1024.v v4,\(a0\),v4'
++.*Error: illegal operands vd cannot overlap vm `vlxseg3ei1024.v v0,\(a0\),v4,v0.t'
++.*Error: illegal operands vd cannot overlap vs2 `vsxseg3ei1024.v v4,\(a0\),v4'
++.*Error: illegal operands vd cannot overlap vm `vsxseg3ei1024.v v0,\(a0\),v4,v0.t'
++.*Error: illegal operands vd cannot overlap vs2 `vlxseg4ei1024.v v4,\(a0\),v4'
++.*Error: illegal operands vd cannot overlap vm `vlxseg4ei1024.v v0,\(a0\),v4,v0.t'
++.*Error: illegal operands vd cannot overlap vs2 `vsxseg4ei1024.v v4,\(a0\),v4'
++.*Error: illegal operands vd cannot overlap vm `vsxseg4ei1024.v v0,\(a0\),v4,v0.t'
++.*Error: illegal operands vd cannot overlap vs2 `vlxseg5ei1024.v v4,\(a0\),v4'
++.*Error: illegal operands vd cannot overlap vm `vlxseg5ei1024.v v0,\(a0\),v4,v0.t'
++.*Error: illegal operands vd cannot overlap vs2 `vsxseg5ei1024.v v4,\(a0\),v4'
++.*Error: illegal operands vd cannot overlap vm `vsxseg5ei1024.v v0,\(a0\),v4,v0.t'
++.*Error: illegal operands vd cannot overlap vs2 `vlxseg6ei1024.v v4,\(a0\),v4'
++.*Error: illegal operands vd cannot overlap vm `vlxseg6ei1024.v v0,\(a0\),v4,v0.t'
++.*Error: illegal operands vd cannot overlap vs2 `vsxseg6ei1024.v v4,\(a0\),v4'
++.*Error: illegal operands vd cannot overlap vm `vsxseg6ei1024.v v0,\(a0\),v4,v0.t'
++.*Error: illegal operands vd cannot overlap vs2 `vlxseg7ei1024.v v4,\(a0\),v4'
++.*Error: illegal operands vd cannot overlap vm `vlxseg7ei1024.v v0,\(a0\),v4,v0.t'
++.*Error: illegal operands vd cannot overlap vs2 `vsxseg7ei1024.v v4,\(a0\),v4'
++.*Error: illegal operands vd cannot overlap vm `vsxseg7ei1024.v v0,\(a0\),v4,v0.t'
++.*Error: illegal operands vd cannot overlap vs2 `vlxseg8ei1024.v v4,\(a0\),v4'
++.*Error: illegal operands vd cannot overlap vm `vlxseg8ei1024.v v0,\(a0\),v4,v0.t'
++.*Error: illegal operands vd cannot overlap vs2 `vsxseg8ei1024.v v4,\(a0\),v4'
++.*Error: illegal operands vd cannot overlap vm `vsxseg8ei1024.v v0,\(a0\),v4,v0.t'
++.*Error: illegal operands vd must be multiple of nf `vl2r.v v31,\(a0\)'
++.*Error: illegal operands vd must be multiple of nf `vl2re8.v v31,\(a0\)'
++.*Error: illegal operands vd must be multiple of nf `vl2re16.v v31,\(a0\)'
++.*Error: illegal operands vd must be multiple of nf `vl2re32.v v31,\(a0\)'
++.*Error: illegal operands vd must be multiple of nf `vl2re64.v v31,\(a0\)'
++.*Error: illegal operands vd must be multiple of nf `vl2re128.v v31,\(a0\)'
++.*Error: illegal operands vd must be multiple of nf `vl2re256.v v31,\(a0\)'
++.*Error: illegal operands vd must be multiple of nf `vl2re512.v v31,\(a0\)'
++.*Error: illegal operands vd must be multiple of nf `vl2re1024.v v31,\(a0\)'
++.*Error: illegal operands vd must be multiple of nf `vl4r.v v30,\(a0\)'
++.*Error: illegal operands vd must be multiple of nf `vl4re8.v v30,\(a0\)'
++.*Error: illegal operands vd must be multiple of nf `vl4re16.v v30,\(a0\)'
++.*Error: illegal operands vd must be multiple of nf `vl4re32.v v30,\(a0\)'
++.*Error: illegal operands vd must be multiple of nf `vl4re64.v v30,\(a0\)'
++.*Error: illegal operands vd must be multiple of nf `vl4re128.v v30,\(a0\)'
++.*Error: illegal operands vd must be multiple of nf `vl4re256.v v30,\(a0\)'
++.*Error: illegal operands vd must be multiple of nf `vl4re512.v v30,\(a0\)'
++.*Error: illegal operands vd must be multiple of nf `vl4re1024.v v30,\(a0\)'
++.*Error: illegal operands vd must be multiple of nf `vl8r.v v26,\(a0\)'
++.*Error: illegal operands vd must be multiple of nf `vl8re8.v v26,\(a0\)'
++.*Error: illegal operands vd must be multiple of nf `vl8re16.v v26,\(a0\)'
++.*Error: illegal operands vd must be multiple of nf `vl8re32.v v26,\(a0\)'
++.*Error: illegal operands vd must be multiple of nf `vl8re64.v v26,\(a0\)'
++.*Error: illegal operands vd must be multiple of nf `vl8re128.v v26,\(a0\)'
++.*Error: illegal operands vd must be multiple of nf `vl8re256.v v26,\(a0\)'
++.*Error: illegal operands vd must be multiple of nf `vl8re512.v v26,\(a0\)'
++.*Error: illegal operands vd must be multiple of nf `vl8re1024.v v26,\(a0\)'
++.*Error: illegal operands vd must be multiple of nf `vs2r.v v31,\(a0\)'
++.*Error: illegal operands vd must be multiple of nf `vs4r.v v30,\(a0\)'
++.*Error: illegal operands vd must be multiple of nf `vs8r.v v26,\(a0\)'
+diff --git a/gas/testsuite/gas/riscv/vector-insns-fail-mask.l b/gas/testsuite/gas/riscv/vector-insns-fail-mask.l
+index 3b23becc16..7ff5a3c99e 100644
+--- a/gas/testsuite/gas/riscv/vector-insns-fail-mask.l
++++ b/gas/testsuite/gas/riscv/vector-insns-fail-mask.l
+@@ -1,10 +1,10 @@
+ .*: Assembler messages:
+-.*Error: illegal operands `vmsbf.m v4,v4'
+-.*Error: illegal operands `vmsbf.m v0,v4,v0.t'
+-.*Error: illegal operands `vmsif.m v4,v4'
+-.*Error: illegal operands `vmsif.m v0,v4,v0.t'
+-.*Error: illegal operands `vmsof.m v4,v4'
+-.*Error: illegal operands `vmsof.m v0,v4,v0.t'
+-.*Error: illegal operands `viota.m v4,v4'
+-.*Error: illegal operands `viota.m v0,v4,v0.t'
+-.*Error: illegal operands `vid.v v0,v0.t'
++.*Error: illegal operands vd cannot overlap vs2 `vmsbf.m v4,v4'
++.*Error: illegal operands vd cannot overlap vm `vmsbf.m v0,v4,v0.t'
++.*Error: illegal operands vd cannot overlap vs2 `vmsif.m v4,v4'
++.*Error: illegal operands vd cannot overlap vm `vmsif.m v0,v4,v0.t'
++.*Error: illegal operands vd cannot overlap vs2 `vmsof.m v4,v4'
++.*Error: illegal operands vd cannot overlap vm `vmsof.m v0,v4,v0.t'
++.*Error: illegal operands vd cannot overlap vs2 `viota.m v4,v4'
++.*Error: illegal operands vd cannot overlap vm `viota.m v0,v4,v0.t'
++.*Error: illegal operands vd cannot overlap vm `vid.v v0,v0.t'
+diff --git a/gas/testsuite/gas/riscv/vector-insns-fail-permutation.l b/gas/testsuite/gas/riscv/vector-insns-fail-permutation.l
+index c208f5710f..1ea27f274e 100644
+--- a/gas/testsuite/gas/riscv/vector-insns-fail-permutation.l
++++ b/gas/testsuite/gas/riscv/vector-insns-fail-permutation.l
+@@ -1,31 +1,31 @@
+ .*: Assembler messages:
+-.*Error: illegal operands `vslideup.vx v4,v4,a1'
+-.*Error: illegal operands `vslideup.vx v0,v4,a1,v0.t'
+-.*Error: illegal operands `vslideup.vi v4,v4,31'
+-.*Error: illegal operands `vslideup.vi v0,v4,31,v0.t'
+-.*Error: illegal operands `vslidedown.vx v0,v4,a1,v0.t'
+-.*Error: illegal operands `vslidedown.vi v0,v4,31,v0.t'
+-.*Error: illegal operands `vslide1up.vx v4,v4,a1'
+-.*Error: illegal operands `vslide1up.vx v0,v4,a1,v0.t'
+-.*Error: illegal operands `vfslide1up.vf v4,v4,fa1'
+-.*Error: illegal operands `vfslide1up.vf v0,v4,fa1,v0.t'
+-.*Error: illegal operands `vslide1down.vx v0,v4,a1,v0.t'
+-.*Error: illegal operands `vfslide1down.vf v0,v4,fa1,v0.t'
+-.*Error: illegal operands `vrgather.vv v4,v4,v8'
+-.*Error: illegal operands `vrgather.vv v8,v4,v8'
+-.*Error: illegal operands `vrgather.vv v0,v4,v8,v0.t'
+-.*Error: illegal operands `vrgather.vx v4,v4,a1'
+-.*Error: illegal operands `vrgather.vx v0,v4,a1,v0.t'
+-.*Error: illegal operands `vrgather.vi v4,v4,31'
+-.*Error: illegal operands `vrgather.vi v0,v4,31,v0.t'
+-.*Error: illegal operands `vrgatherei16.vv v4,v4,v8'
+-.*Error: illegal operands `vrgatherei16.vv v8,v4,v8'
+-.*Error: illegal operands `vrgatherei16.vv v0,v4,v8,v0.t'
+-.*Error: illegal operands `vcompress.vm v4,v4,v8'
+-.*Error: illegal operands `vcompress.vm v8,v4,v8'
+-.*Error: illegal operands `vmv2r.v v30,v31'
+-.*Error: illegal operands `vmv2r.v v31,v30'
+-.*Error: illegal operands `vmv4r.v v28,v30'
+-.*Error: illegal operands `vmv4r.v v30,v28'
+-.*Error: illegal operands `vmv8r.v v24,v26'
+-.*Error: illegal operands `vmv8r.v v26,v24'
++.*Error: illegal operands vd cannot overlap vs2 `vslideup.vx v4,v4,a1'
++.*Error: illegal operands vd cannot overlap vm `vslideup.vx v0,v4,a1,v0.t'
++.*Error: illegal operands vd cannot overlap vs2 `vslideup.vi v4,v4,31'
++.*Error: illegal operands vd cannot overlap vm `vslideup.vi v0,v4,31,v0.t'
++.*Error: illegal operands vd cannot overlap vm `vslidedown.vx v0,v4,a1,v0.t'
++.*Error: illegal operands vd cannot overlap vm `vslidedown.vi v0,v4,31,v0.t'
++.*Error: illegal operands vd cannot overlap vs2 `vslide1up.vx v4,v4,a1'
++.*Error: illegal operands vd cannot overlap vm `vslide1up.vx v0,v4,a1,v0.t'
++.*Error: illegal operands vd cannot overlap vs2 `vfslide1up.vf v4,v4,fa1'
++.*Error: illegal operands vd cannot overlap vm `vfslide1up.vf v0,v4,fa1,v0.t'
++.*Error: illegal operands vd cannot overlap vm `vslide1down.vx v0,v4,a1,v0.t'
++.*Error: illegal operands vd cannot overlap vm `vfslide1down.vf v0,v4,fa1,v0.t'
++.*Error: illegal operands vd cannot overlap vs2 `vrgather.vv v4,v4,v8'
++.*Error: illegal operands vd cannot overlap vs1 `vrgather.vv v8,v4,v8'
++.*Error: illegal operands vd cannot overlap vm `vrgather.vv v0,v4,v8,v0.t'
++.*Error: illegal operands vd cannot overlap vs2 `vrgather.vx v4,v4,a1'
++.*Error: illegal operands vd cannot overlap vm `vrgather.vx v0,v4,a1,v0.t'
++.*Error: illegal operands vd cannot overlap vs2 `vrgather.vi v4,v4,31'
++.*Error: illegal operands vd cannot overlap vm `vrgather.vi v0,v4,31,v0.t'
++.*Error: illegal operands vd cannot overlap vs2 `vrgatherei16.vv v4,v4,v8'
++.*Error: illegal operands vd cannot overlap vs1 `vrgatherei16.vv v8,v4,v8'
++.*Error: illegal operands vd cannot overlap vm `vrgatherei16.vv v0,v4,v8,v0.t'
++.*Error: illegal operands vd cannot overlap vs2 `vcompress.vm v4,v4,v8'
++.*Error: illegal operands vd cannot overlap vs1 `vcompress.vm v8,v4,v8'
++.*Error: illegal operands vs2 must be multiple of nf `vmv2r.v v30,v31'
++.*Error: illegal operands vd must be multiple of nf `vmv2r.v v31,v30'
++.*Error: illegal operands vs2 must be multiple of nf `vmv4r.v v28,v30'
++.*Error: illegal operands vd must be multiple of nf `vmv4r.v v30,v28'
++.*Error: illegal operands vs2 must be multiple of nf `vmv8r.v v24,v26'
++.*Error: illegal operands vd must be multiple of nf `vmv8r.v v26,v24'
+diff --git a/gas/testsuite/gas/riscv/vector-insns-fail-zvamo.l b/gas/testsuite/gas/riscv/vector-insns-fail-zvamo.l
+index 6207fb2fee..ae414f7b75 100644
+--- a/gas/testsuite/gas/riscv/vector-insns-fail-zvamo.l
++++ b/gas/testsuite/gas/riscv/vector-insns-fail-zvamo.l
+@@ -1,109 +1,109 @@
+ .*: Assembler messages:
+ .*Error: illegal operands `vamoaddei8.v v4,\(a1\),v4,v0'
+-.*Error: illegal operands `vamoaddei8.v v0,\(a1\),v4,v0,v0.t'
+-.*Error: illegal operands `vamoaddei8.v x0,\(a1\),v4,v0,v0.t'
++.*Error: illegal operands vd cannot overlap vm `vamoaddei8.v v0,\(a1\),v4,v0,v0.t'
++.*Error: illegal operands vd cannot overlap vm `vamoaddei8.v x0,\(a1\),v4,v0,v0.t'
+ .*Error: illegal operands `vamoswapei8.v v4,\(a1\),v4,v0'
+-.*Error: illegal operands `vamoswapei8.v v0,\(a1\),v4,v0,v0.t'
+-.*Error: illegal operands `vamoswapei8.v x0,\(a1\),v4,v0,v0.t'
++.*Error: illegal operands vd cannot overlap vm `vamoswapei8.v v0,\(a1\),v4,v0,v0.t'
++.*Error: illegal operands vd cannot overlap vm `vamoswapei8.v x0,\(a1\),v4,v0,v0.t'
+ .*Error: illegal operands `vamoxorei8.v v4,\(a1\),v4,v0'
+-.*Error: illegal operands `vamoxorei8.v v0,\(a1\),v4,v0,v0.t'
+-.*Error: illegal operands `vamoxorei8.v x0,\(a1\),v4,v0,v0.t'
++.*Error: illegal operands vd cannot overlap vm `vamoxorei8.v v0,\(a1\),v4,v0,v0.t'
++.*Error: illegal operands vd cannot overlap vm `vamoxorei8.v x0,\(a1\),v4,v0,v0.t'
+ .*Error: illegal operands `vamoandei8.v v4,\(a1\),v4,v0'
+-.*Error: illegal operands `vamoandei8.v v0,\(a1\),v4,v0,v0.t'
+-.*Error: illegal operands `vamoandei8.v x0,\(a1\),v4,v0,v0.t'
++.*Error: illegal operands vd cannot overlap vm `vamoandei8.v v0,\(a1\),v4,v0,v0.t'
++.*Error: illegal operands vd cannot overlap vm `vamoandei8.v x0,\(a1\),v4,v0,v0.t'
+ .*Error: illegal operands `vamoorei8.v v4,\(a1\),v4,v0'
+-.*Error: illegal operands `vamoorei8.v v0,\(a1\),v4,v0,v0.t'
+-.*Error: illegal operands `vamoorei8.v x0,\(a1\),v4,v0,v0.t'
++.*Error: illegal operands vd cannot overlap vm `vamoorei8.v v0,\(a1\),v4,v0,v0.t'
++.*Error: illegal operands vd cannot overlap vm `vamoorei8.v x0,\(a1\),v4,v0,v0.t'
+ .*Error: illegal operands `vamominei8.v v4,\(a1\),v4,v0'
+-.*Error: illegal operands `vamominei8.v v0,\(a1\),v4,v0,v0.t'
+-.*Error: illegal operands `vamominei8.v x0,\(a1\),v4,v0,v0.t'
++.*Error: illegal operands vd cannot overlap vm `vamominei8.v v0,\(a1\),v4,v0,v0.t'
++.*Error: illegal operands vd cannot overlap vm `vamominei8.v x0,\(a1\),v4,v0,v0.t'
+ .*Error: illegal operands `vamomaxei8.v v4,\(a1\),v4,v0'
+-.*Error: illegal operands `vamomaxei8.v v0,\(a1\),v4,v0,v0.t'
+-.*Error: illegal operands `vamomaxei8.v x0,\(a1\),v4,v0,v0.t'
++.*Error: illegal operands vd cannot overlap vm `vamomaxei8.v v0,\(a1\),v4,v0,v0.t'
++.*Error: illegal operands vd cannot overlap vm `vamomaxei8.v x0,\(a1\),v4,v0,v0.t'
+ .*Error: illegal operands `vamominuei8.v v4,\(a1\),v4,v0'
+-.*Error: illegal operands `vamominuei8.v v0,\(a1\),v4,v0,v0.t'
+-.*Error: illegal operands `vamominuei8.v x0,\(a1\),v4,v0,v0.t'
++.*Error: illegal operands vd cannot overlap vm `vamominuei8.v v0,\(a1\),v4,v0,v0.t'
++.*Error: illegal operands vd cannot overlap vm `vamominuei8.v x0,\(a1\),v4,v0,v0.t'
+ .*Error: illegal operands `vamomaxuei8.v v4,\(a1\),v4,v0'
+-.*Error: illegal operands `vamomaxuei8.v v0,\(a1\),v4,v0,v0.t'
+-.*Error: illegal operands `vamomaxuei8.v x0,\(a1\),v4,v0,v0.t'
++.*Error: illegal operands vd cannot overlap vm `vamomaxuei8.v v0,\(a1\),v4,v0,v0.t'
++.*Error: illegal operands vd cannot overlap vm `vamomaxuei8.v x0,\(a1\),v4,v0,v0.t'
+ .*Error: illegal operands `vamoaddei16.v v4,\(a1\),v4,v0'
+-.*Error: illegal operands `vamoaddei16.v v0,\(a1\),v4,v0,v0.t'
+-.*Error: illegal operands `vamoaddei16.v x0,\(a1\),v4,v0,v0.t'
+-.*Error: illegal operands `vamoswapei16.v v0,\(a1\),v4,v0,v0.t'
++.*Error: illegal operands vd cannot overlap vm `vamoaddei16.v v0,\(a1\),v4,v0,v0.t'
++.*Error: illegal operands vd cannot overlap vm `vamoaddei16.v x0,\(a1\),v4,v0,v0.t'
++.*Error: illegal operands vd cannot overlap vm `vamoswapei16.v v0,\(a1\),v4,v0,v0.t'
+ .*Error: illegal operands `vamoswapei16.v v4,\(a1\),v4,v0'
+-.*Error: illegal operands `vamoswapei16.v x0,\(a1\),v4,v0,v0.t'
+-.*Error: illegal operands `vamoxorei16.v v0,\(a1\),v4,v0,v0.t'
++.*Error: illegal operands vd cannot overlap vm `vamoswapei16.v x0,\(a1\),v4,v0,v0.t'
++.*Error: illegal operands vd cannot overlap vm `vamoxorei16.v v0,\(a1\),v4,v0,v0.t'
+ .*Error: illegal operands `vamoxorei16.v v4,\(a1\),v4,v0'
+-.*Error: illegal operands `vamoxorei16.v x0,\(a1\),v4,v0,v0.t'
+-.*Error: illegal operands `vamoandei16.v v0,\(a1\),v4,v0,v0.t'
++.*Error: illegal operands vd cannot overlap vm `vamoxorei16.v x0,\(a1\),v4,v0,v0.t'
++.*Error: illegal operands vd cannot overlap vm `vamoandei16.v v0,\(a1\),v4,v0,v0.t'
+ .*Error: illegal operands `vamoandei16.v v4,\(a1\),v4,v0'
+-.*Error: illegal operands `vamoandei16.v x0,\(a1\),v4,v0,v0.t'
+-.*Error: illegal operands `vamoorei16.v v0,\(a1\),v4,v0,v0.t'
++.*Error: illegal operands vd cannot overlap vm `vamoandei16.v x0,\(a1\),v4,v0,v0.t'
++.*Error: illegal operands vd cannot overlap vm `vamoorei16.v v0,\(a1\),v4,v0,v0.t'
+ .*Error: illegal operands `vamoorei16.v v4,\(a1\),v4,v0'
+-.*Error: illegal operands `vamoorei16.v x0,\(a1\),v4,v0,v0.t'
+-.*Error: illegal operands `vamominei16.v v0,\(a1\),v4,v0,v0.t'
++.*Error: illegal operands vd cannot overlap vm `vamoorei16.v x0,\(a1\),v4,v0,v0.t'
++.*Error: illegal operands vd cannot overlap vm `vamominei16.v v0,\(a1\),v4,v0,v0.t'
+ .*Error: illegal operands `vamominei16.v v4,\(a1\),v4,v0'
+-.*Error: illegal operands `vamominei16.v x0,\(a1\),v4,v0,v0.t'
+-.*Error: illegal operands `vamomaxei16.v v0,\(a1\),v4,v0,v0.t'
++.*Error: illegal operands vd cannot overlap vm `vamominei16.v x0,\(a1\),v4,v0,v0.t'
++.*Error: illegal operands vd cannot overlap vm `vamomaxei16.v v0,\(a1\),v4,v0,v0.t'
+ .*Error: illegal operands `vamomaxei16.v v4,\(a1\),v4,v0'
+-.*Error: illegal operands `vamomaxei16.v x0,\(a1\),v4,v0,v0.t'
+-.*Error: illegal operands `vamominuei16.v v0,\(a1\),v4,v0,v0.t'
++.*Error: illegal operands vd cannot overlap vm `vamomaxei16.v x0,\(a1\),v4,v0,v0.t'
++.*Error: illegal operands vd cannot overlap vm `vamominuei16.v v0,\(a1\),v4,v0,v0.t'
+ .*Error: illegal operands `vamominuei16.v v4,\(a1\),v4,v0'
+-.*Error: illegal operands `vamominuei16.v x0,\(a1\),v4,v0,v0.t'
+-.*Error: illegal operands `vamomaxuei16.v v0,\(a1\),v4,v0,v0.t'
++.*Error: illegal operands vd cannot overlap vm `vamominuei16.v x0,\(a1\),v4,v0,v0.t'
++.*Error: illegal operands vd cannot overlap vm `vamomaxuei16.v v0,\(a1\),v4,v0,v0.t'
+ .*Error: illegal operands `vamomaxuei16.v v4,\(a1\),v4,v0'
+-.*Error: illegal operands `vamomaxuei16.v x0,\(a1\),v4,v0,v0.t'
+-.*Error: illegal operands `vamoaddei32.v v0,\(a1\),v4,v0,v0.t'
++.*Error: illegal operands vd cannot overlap vm `vamomaxuei16.v x0,\(a1\),v4,v0,v0.t'
++.*Error: illegal operands vd cannot overlap vm `vamoaddei32.v v0,\(a1\),v4,v0,v0.t'
+ .*Error: illegal operands `vamoaddei32.v v4,\(a1\),v4,v0'
+-.*Error: illegal operands `vamoaddei32.v x0,\(a1\),v4,v0,v0.t'
++.*Error: illegal operands vd cannot overlap vm `vamoaddei32.v x0,\(a1\),v4,v0,v0.t'
+ .*Error: illegal operands `vamoswapei32.v v4,\(a1\),v4,v0'
+-.*Error: illegal operands `vamoswapei32.v v0,\(a1\),v4,v0,v0.t'
+-.*Error: illegal operands `vamoswapei32.v x0,\(a1\),v4,v0,v0.t'
++.*Error: illegal operands vd cannot overlap vm `vamoswapei32.v v0,\(a1\),v4,v0,v0.t'
++.*Error: illegal operands vd cannot overlap vm `vamoswapei32.v x0,\(a1\),v4,v0,v0.t'
+ .*Error: illegal operands `vamoxorei32.v v4,\(a1\),v4,v0'
+-.*Error: illegal operands `vamoxorei32.v v0,\(a1\),v4,v0,v0.t'
+-.*Error: illegal operands `vamoxorei32.v x0,\(a1\),v4,v0,v0.t'
++.*Error: illegal operands vd cannot overlap vm `vamoxorei32.v v0,\(a1\),v4,v0,v0.t'
++.*Error: illegal operands vd cannot overlap vm `vamoxorei32.v x0,\(a1\),v4,v0,v0.t'
+ .*Error: illegal operands `vamoandei32.v v4,\(a1\),v4,v0'
+-.*Error: illegal operands `vamoandei32.v v0,\(a1\),v4,v0,v0.t'
+-.*Error: illegal operands `vamoandei32.v x0,\(a1\),v4,v0,v0.t'
++.*Error: illegal operands vd cannot overlap vm `vamoandei32.v v0,\(a1\),v4,v0,v0.t'
++.*Error: illegal operands vd cannot overlap vm `vamoandei32.v x0,\(a1\),v4,v0,v0.t'
+ .*Error: illegal operands `vamoorei32.v v4,\(a1\),v4,v0'
+-.*Error: illegal operands `vamoorei32.v v0,\(a1\),v4,v0,v0.t'
+-.*Error: illegal operands `vamoorei32.v x0,\(a1\),v4,v0,v0.t'
++.*Error: illegal operands vd cannot overlap vm `vamoorei32.v v0,\(a1\),v4,v0,v0.t'
++.*Error: illegal operands vd cannot overlap vm `vamoorei32.v x0,\(a1\),v4,v0,v0.t'
+ .*Error: illegal operands `vamominei32.v v4,\(a1\),v4,v0'
+-.*Error: illegal operands `vamominei32.v v0,\(a1\),v4,v0,v0.t'
+-.*Error: illegal operands `vamominei32.v x0,\(a1\),v4,v0,v0.t'
++.*Error: illegal operands vd cannot overlap vm `vamominei32.v v0,\(a1\),v4,v0,v0.t'
++.*Error: illegal operands vd cannot overlap vm `vamominei32.v x0,\(a1\),v4,v0,v0.t'
+ .*Error: illegal operands `vamomaxei32.v v4,\(a1\),v4,v0'
+-.*Error: illegal operands `vamomaxei32.v v0,\(a1\),v4,v0,v0.t'
+-.*Error: illegal operands `vamomaxei32.v x0,\(a1\),v4,v0,v0.t'
++.*Error: illegal operands vd cannot overlap vm `vamomaxei32.v v0,\(a1\),v4,v0,v0.t'
++.*Error: illegal operands vd cannot overlap vm `vamomaxei32.v x0,\(a1\),v4,v0,v0.t'
+ .*Error: illegal operands `vamominuei32.v v4,\(a1\),v4,v0'
+-.*Error: illegal operands `vamominuei32.v v0,\(a1\),v4,v0,v0.t'
+-.*Error: illegal operands `vamominuei32.v x0,\(a1\),v4,v0,v0.t'
++.*Error: illegal operands vd cannot overlap vm `vamominuei32.v v0,\(a1\),v4,v0,v0.t'
++.*Error: illegal operands vd cannot overlap vm `vamominuei32.v x0,\(a1\),v4,v0,v0.t'
+ .*Error: illegal operands `vamomaxuei32.v v4,\(a1\),v4,v0'
+-.*Error: illegal operands `vamomaxuei32.v v0,\(a1\),v4,v0,v0.t'
+-.*Error: illegal operands `vamomaxuei32.v x0,\(a1\),v4,v0,v0.t'
++.*Error: illegal operands vd cannot overlap vm `vamomaxuei32.v v0,\(a1\),v4,v0,v0.t'
++.*Error: illegal operands vd cannot overlap vm `vamomaxuei32.v x0,\(a1\),v4,v0,v0.t'
+ .*Error: illegal operands `vamoaddei64.v v4,\(a1\),v4,v0'
+-.*Error: illegal operands `vamoaddei64.v v0,\(a1\),v4,v0,v0.t'
+-.*Error: illegal operands `vamoaddei64.v x0,\(a1\),v4,v0,v0.t'
++.*Error: illegal operands vd cannot overlap vm `vamoaddei64.v v0,\(a1\),v4,v0,v0.t'
++.*Error: illegal operands vd cannot overlap vm `vamoaddei64.v x0,\(a1\),v4,v0,v0.t'
+ .*Error: illegal operands `vamoswapei64.v v4,\(a1\),v4,v0'
+-.*Error: illegal operands `vamoswapei64.v v0,\(a1\),v4,v0,v0.t'
+-.*Error: illegal operands `vamoswapei64.v x0,\(a1\),v4,v0,v0.t'
++.*Error: illegal operands vd cannot overlap vm `vamoswapei64.v v0,\(a1\),v4,v0,v0.t'
++.*Error: illegal operands vd cannot overlap vm `vamoswapei64.v x0,\(a1\),v4,v0,v0.t'
+ .*Error: illegal operands `vamoxorei64.v v4,\(a1\),v4,v0'
+-.*Error: illegal operands `vamoxorei64.v v0,\(a1\),v4,v0,v0.t'
+-.*Error: illegal operands `vamoxorei64.v x0,\(a1\),v4,v0,v0.t'
++.*Error: illegal operands vd cannot overlap vm `vamoxorei64.v v0,\(a1\),v4,v0,v0.t'
++.*Error: illegal operands vd cannot overlap vm `vamoxorei64.v x0,\(a1\),v4,v0,v0.t'
+ .*Error: illegal operands `vamoandei64.v v4,\(a1\),v4,v0'
+-.*Error: illegal operands `vamoandei64.v v0,\(a1\),v4,v0,v0.t'
+-.*Error: illegal operands `vamoandei64.v x0,\(a1\),v4,v0,v0.t'
++.*Error: illegal operands vd cannot overlap vm `vamoandei64.v v0,\(a1\),v4,v0,v0.t'
++.*Error: illegal operands vd cannot overlap vm `vamoandei64.v x0,\(a1\),v4,v0,v0.t'
+ .*Error: illegal operands `vamoorei64.v v4,\(a1\),v4,v0'
+-.*Error: illegal operands `vamoorei64.v v0,\(a1\),v4,v0,v0.t'
+-.*Error: illegal operands `vamoorei64.v x0,\(a1\),v4,v0,v0.t'
++.*Error: illegal operands vd cannot overlap vm `vamoorei64.v v0,\(a1\),v4,v0,v0.t'
++.*Error: illegal operands vd cannot overlap vm `vamoorei64.v x0,\(a1\),v4,v0,v0.t'
+ .*Error: illegal operands `vamominei64.v v4,\(a1\),v4,v0'
+-.*Error: illegal operands `vamominei64.v v0,\(a1\),v4,v0,v0.t'
+-.*Error: illegal operands `vamominei64.v x0,\(a1\),v4,v0,v0.t'
++.*Error: illegal operands vd cannot overlap vm `vamominei64.v v0,\(a1\),v4,v0,v0.t'
++.*Error: illegal operands vd cannot overlap vm `vamominei64.v x0,\(a1\),v4,v0,v0.t'
+ .*Error: illegal operands `vamomaxei64.v v4,\(a1\),v4,v0'
+-.*Error: illegal operands `vamomaxei64.v v0,\(a1\),v4,v0,v0.t'
+-.*Error: illegal operands `vamomaxei64.v x0,\(a1\),v4,v0,v0.t'
++.*Error: illegal operands vd cannot overlap vm `vamomaxei64.v v0,\(a1\),v4,v0,v0.t'
++.*Error: illegal operands vd cannot overlap vm `vamomaxei64.v x0,\(a1\),v4,v0,v0.t'
+ .*Error: illegal operands `vamominuei64.v v4,\(a1\),v4,v0'
+-.*Error: illegal operands `vamominuei64.v v0,\(a1\),v4,v0,v0.t'
+-.*Error: illegal operands `vamominuei64.v x0,\(a1\),v4,v0,v0.t'
++.*Error: illegal operands vd cannot overlap vm `vamominuei64.v v0,\(a1\),v4,v0,v0.t'
++.*Error: illegal operands vd cannot overlap vm `vamominuei64.v x0,\(a1\),v4,v0,v0.t'
+ .*Error: illegal operands `vamomaxuei64.v v4,\(a1\),v4,v0'
+-.*Error: illegal operands `vamomaxuei64.v v0,\(a1\),v4,v0,v0.t'
+-.*Error: illegal operands `vamomaxuei64.v x0,\(a1\),v4,v0,v0.t'
++.*Error: illegal operands vd cannot overlap vm `vamomaxuei64.v v0,\(a1\),v4,v0,v0.t'
++.*Error: illegal operands vd cannot overlap vm `vamomaxuei64.v x0,\(a1\),v4,v0,v0.t'
+diff --git a/gas/testsuite/gas/riscv/vector-insns-fail-zvqmac.l b/gas/testsuite/gas/riscv/vector-insns-fail-zvqmac.l
+index e5c157fd89..10b2be32ca 100644
+--- a/gas/testsuite/gas/riscv/vector-insns-fail-zvqmac.l
++++ b/gas/testsuite/gas/riscv/vector-insns-fail-zvqmac.l
+@@ -1,35 +1,35 @@
+ .*: Assembler messages:
+-.*Error: illegal operands `vqmaccu.vv v2,v4,v8'
+-.*Error: illegal operands `vqmaccu.vv v4,v4,v8'
+-.*Error: illegal operands `vqmaccu.vv v4,v7,v8'
+-.*Error: illegal operands `vqmaccu.vv v8,v4,v8'
+-.*Error: illegal operands `vqmaccu.vv v8,v4,v11'
+-.*Error: illegal operands `vqmaccu.vv v0,v4,v8,v0.t'
+-.*Error: illegal operands `vqmaccu.vx v2,a1,v4'
+-.*Error: illegal operands `vqmaccu.vx v4,a1,v4'
+-.*Error: illegal operands `vqmaccu.vx v4,a1,v7'
+-.*Error: illegal operands `vqmaccu.vx v0,a1,v4,v0.t'
+-.*Error: illegal operands `vqmacc.vv v2,v4,v8'
+-.*Error: illegal operands `vqmacc.vv v4,v4,v8'
+-.*Error: illegal operands `vqmacc.vv v4,v7,v8'
+-.*Error: illegal operands `vqmacc.vv v8,v4,v8'
+-.*Error: illegal operands `vqmacc.vv v8,v4,v11'
+-.*Error: illegal operands `vqmacc.vv v0,v4,v8,v0.t'
+-.*Error: illegal operands `vqmacc.vx v2,a1,v4'
+-.*Error: illegal operands `vqmacc.vx v4,a1,v4'
+-.*Error: illegal operands `vqmacc.vx v4,a1,v7'
+-.*Error: illegal operands `vqmacc.vx v0,a1,v4,v0.t'
+-.*Error: illegal operands `vqmaccsu.vv v2,v4,v8'
+-.*Error: illegal operands `vqmaccsu.vv v4,v4,v8'
+-.*Error: illegal operands `vqmaccsu.vv v4,v7,v8'
+-.*Error: illegal operands `vqmaccsu.vv v8,v4,v8'
+-.*Error: illegal operands `vqmaccsu.vv v8,v4,v11'
+-.*Error: illegal operands `vqmaccsu.vv v0,v4,v8,v0.t'
+-.*Error: illegal operands `vqmaccsu.vx v2,a1,v4'
+-.*Error: illegal operands `vqmaccsu.vx v4,a1,v4'
+-.*Error: illegal operands `vqmaccsu.vx v4,a1,v7'
+-.*Error: illegal operands `vqmaccsu.vx v0,a1,v4,v0.t'
+-.*Error: illegal operands `vqmaccus.vx v2,a1,v4'
+-.*Error: illegal operands `vqmaccus.vx v4,a1,v4'
+-.*Error: illegal operands `vqmaccus.vx v4,a1,v7'
+-.*Error: illegal operands `vqmaccus.vx v0,a1,v4,v0.t'
++.*Error: illegal operands vd must be multiple of 4 `vqmaccu.vv v2,v4,v8'
++.*Error: illegal operands vd cannot overlap vs1 `vqmaccu.vv v4,v4,v8'
++.*Error: illegal operands vd cannot overlap vs1 `vqmaccu.vv v4,v7,v8'
++.*Error: illegal operands vd cannot overlap vs2 `vqmaccu.vv v8,v4,v8'
++.*Error: illegal operands vd cannot overlap vs2 `vqmaccu.vv v8,v4,v11'
++.*Error: illegal operands vd cannot overlap vm `vqmaccu.vv v0,v4,v8,v0.t'
++.*Error: illegal operands vd must be multiple of 4 `vqmaccu.vx v2,a1,v4'
++.*Error: illegal operands vd cannot overlap vs2 `vqmaccu.vx v4,a1,v4'
++.*Error: illegal operands vd cannot overlap vs2 `vqmaccu.vx v4,a1,v7'
++.*Error: illegal operands vd cannot overlap vm `vqmaccu.vx v0,a1,v4,v0.t'
++.*Error: illegal operands vd must be multiple of 4 `vqmacc.vv v2,v4,v8'
++.*Error: illegal operands vd cannot overlap vs1 `vqmacc.vv v4,v4,v8'
++.*Error: illegal operands vd cannot overlap vs1 `vqmacc.vv v4,v7,v8'
++.*Error: illegal operands vd cannot overlap vs2 `vqmacc.vv v8,v4,v8'
++.*Error: illegal operands vd cannot overlap vs2 `vqmacc.vv v8,v4,v11'
++.*Error: illegal operands vd cannot overlap vm `vqmacc.vv v0,v4,v8,v0.t'
++.*Error: illegal operands vd must be multiple of 4 `vqmacc.vx v2,a1,v4'
++.*Error: illegal operands vd cannot overlap vs2 `vqmacc.vx v4,a1,v4'
++.*Error: illegal operands vd cannot overlap vs2 `vqmacc.vx v4,a1,v7'
++.*Error: illegal operands vd cannot overlap vm `vqmacc.vx v0,a1,v4,v0.t'
++.*Error: illegal operands vd must be multiple of 4 `vqmaccsu.vv v2,v4,v8'
++.*Error: illegal operands vd cannot overlap vs1 `vqmaccsu.vv v4,v4,v8'
++.*Error: illegal operands vd cannot overlap vs1 `vqmaccsu.vv v4,v7,v8'
++.*Error: illegal operands vd cannot overlap vs2 `vqmaccsu.vv v8,v4,v8'
++.*Error: illegal operands vd cannot overlap vs2 `vqmaccsu.vv v8,v4,v11'
++.*Error: illegal operands vd cannot overlap vm `vqmaccsu.vv v0,v4,v8,v0.t'
++.*Error: illegal operands vd must be multiple of 4 `vqmaccsu.vx v2,a1,v4'
++.*Error: illegal operands vd cannot overlap vs2 `vqmaccsu.vx v4,a1,v4'
++.*Error: illegal operands vd cannot overlap vs2 `vqmaccsu.vx v4,a1,v7'
++.*Error: illegal operands vd cannot overlap vm `vqmaccsu.vx v0,a1,v4,v0.t'
++.*Error: illegal operands vd must be multiple of 4 `vqmaccus.vx v2,a1,v4'
++.*Error: illegal operands vd cannot overlap vs2 `vqmaccus.vx v4,a1,v4'
++.*Error: illegal operands vd cannot overlap vs2 `vqmaccus.vx v4,a1,v7'
++.*Error: illegal operands vd cannot overlap vm `vqmaccus.vx v0,a1,v4,v0.t'
+diff --git a/include/opcode/riscv.h b/include/opcode/riscv.h
+index b1d3c068db..5fd18beb88 100644
+--- a/include/opcode/riscv.h
++++ b/include/opcode/riscv.h
+@@ -417,7 +417,7 @@ struct riscv_opcode
+      checking is disable, then most of the function should check only the
+      basic encoding for the instruction.  */
+   int (*match_func) (const struct riscv_opcode *op, insn_t word,
+-		     int constraints);
++		     int constraints, const char **error);
+   /* For a macro, this is INSN_MACRO.  Otherwise, it is a collection
+      of bits describing the instruction, notably any relevant hazard
+      information.  */
+diff --git a/opcodes/riscv-dis.c b/opcodes/riscv-dis.c
+index 875b69a1da..2b64cf1d08 100644
+--- a/opcodes/riscv-dis.c
++++ b/opcodes/riscv-dis.c
+@@ -572,7 +572,7 @@ riscv_disassemble_insn (bfd_vma memaddr, insn_t word, disassemble_info *info)
+       for (; op->name; op++)
+ 	{
+ 	  /* Does the opcode match?  */
+-	  if (! (op->match_func) (op, word, 0))
++	  if (! (op->match_func) (op, word, 0, NULL))
+ 	    continue;
+ 	  /* Is this a pseudo-instruction and may we print it as such?  */
+ 	  if (no_aliases && (op->pinfo & INSN_ALIAS))
+diff --git a/opcodes/riscv-opc.c b/opcodes/riscv-opc.c
+index 2d78218e2b..7499abb7a6 100644
+--- a/opcodes/riscv-opc.c
++++ b/opcodes/riscv-opc.c
+@@ -100,7 +100,8 @@ const char * const riscv_vecm_names_numeric[NVECM] =
+ static int
+ match_opcode (const struct riscv_opcode *op,
+ 	      insn_t insn,
+-	      int constraints ATTRIBUTE_UNUSED)
++	      int constraints ATTRIBUTE_UNUSED,
++	      const char **error ATTRIBUTE_UNUSED)
+ {
+   return ((insn ^ op->match) & op->mask) == 0;
+ }
+@@ -108,7 +109,8 @@ match_opcode (const struct riscv_opcode *op,
+ static int
+ match_never (const struct riscv_opcode *op ATTRIBUTE_UNUSED,
+ 	     insn_t insn ATTRIBUTE_UNUSED,
+-	     int constraints ATTRIBUTE_UNUSED)
++	     int constraints ATTRIBUTE_UNUSED,
++	     const char **error ATTRIBUTE_UNUSED)
+ {
+   return 0;
+ }
+@@ -116,50 +118,55 @@ match_never (const struct riscv_opcode *op ATTRIBUTE_UNUSED,
+ static int
+ match_rs1_eq_rs2 (const struct riscv_opcode *op,
+ 		  insn_t insn,
+-		  int constraints ATTRIBUTE_UNUSED)
++		  int constraints ATTRIBUTE_UNUSED,
++		  const char **error ATTRIBUTE_UNUSED)
+ {
+   int rs1 = (insn & MASK_RS1) >> OP_SH_RS1;
+   int rs2 = (insn & MASK_RS2) >> OP_SH_RS2;
+-  return match_opcode (op, insn, 0) && rs1 == rs2;
++  return match_opcode (op, insn, 0, NULL) && rs1 == rs2;
+ }
+ 
+ static int
+ match_vs1_eq_vs2 (const struct riscv_opcode *op,
+ 		  insn_t insn,
+-		  int constraints ATTRIBUTE_UNUSED)
++		  int constraints ATTRIBUTE_UNUSED,
++		  const char **error ATTRIBUTE_UNUSED)
+ {
+   int vs1 = (insn & MASK_VS1) >> OP_SH_VS1;
+   int vs2 = (insn & MASK_VS2) >> OP_SH_VS2;
+ 
+-  return match_opcode (op, insn, 0) && vs1 == vs2;
++  return match_opcode (op, insn, 0, NULL) && vs1 == vs2;
+ }
+ 
+ static int
+ match_vd_eq_vs1_eq_vs2 (const struct riscv_opcode *op,
+ 			insn_t insn,
+-			int constraints ATTRIBUTE_UNUSED)
++			int constraints ATTRIBUTE_UNUSED,
++			const char **error ATTRIBUTE_UNUSED)
+ {
+   int vd =  (insn & MASK_VD) >> OP_SH_VD;
+   int vs1 = (insn & MASK_VS1) >> OP_SH_VS1;
+   int vs2 = (insn & MASK_VS2) >> OP_SH_VS2;
+ 
+-  return match_opcode (op, insn, 0) && vd == vs1 && vs1 == vs2;
++  return match_opcode (op, insn, 0, NULL) && vd == vs1 && vs1 == vs2;
+ }
+ 
+ static int
+ match_rd_nonzero (const struct riscv_opcode *op,
+ 		  insn_t insn,
+-		  int constraints ATTRIBUTE_UNUSED)
++		  int constraints ATTRIBUTE_UNUSED,
++		  const char **error ATTRIBUTE_UNUSED)
+ {
+-  return match_opcode (op, insn, 0) && ((insn & MASK_RD) != 0);
++  return match_opcode (op, insn, 0, NULL) && ((insn & MASK_RD) != 0);
+ }
+ 
+ static int
+ match_c_add (const struct riscv_opcode *op,
+ 	     insn_t insn,
+-	     int constraints ATTRIBUTE_UNUSED)
++	     int constraints ATTRIBUTE_UNUSED,
++	     const char **error ATTRIBUTE_UNUSED)
+ {
+-  return match_rd_nonzero (op, insn, 0) && ((insn & MASK_CRS2) != 0);
++  return match_rd_nonzero (op, insn, 0, NULL) && ((insn & MASK_CRS2) != 0);
+ }
+ 
+ /* We don't allow mv zero,X to become a c.mv hint, so we need a separate
+@@ -168,26 +175,29 @@ match_c_add (const struct riscv_opcode *op,
+ static int
+ match_c_add_with_hint (const struct riscv_opcode *op,
+ 		       insn_t insn,
+-		       int constraints ATTRIBUTE_UNUSED)
++		       int constraints ATTRIBUTE_UNUSED,
++		       const char **error ATTRIBUTE_UNUSED)
+ {
+-  return match_opcode (op, insn, 0) && ((insn & MASK_CRS2) != 0);
++  return match_opcode (op, insn, 0, NULL) && ((insn & MASK_CRS2) != 0);
+ }
+ 
+ static int
+ match_c_nop (const struct riscv_opcode *op,
+ 	     insn_t insn,
+-	     int constraints ATTRIBUTE_UNUSED)
++	     int constraints ATTRIBUTE_UNUSED,
++	     const char **error ATTRIBUTE_UNUSED)
+ {
+-  return (match_opcode (op, insn, 0)
++  return (match_opcode (op, insn, 0, NULL)
+ 	  && (((insn & MASK_RD) >> OP_SH_RD) == 0));
+ }
+ 
+ static int
+ match_c_addi16sp (const struct riscv_opcode *op,
+ 		  insn_t insn,
+-		  int constraints ATTRIBUTE_UNUSED)
++		  int constraints ATTRIBUTE_UNUSED,
++		  const char **error ATTRIBUTE_UNUSED)
+ {
+-  return (match_opcode (op, insn, 0)
++  return (match_opcode (op, insn, 0, NULL)
+ 	  && (((insn & MASK_RD) >> OP_SH_RD) == 2)
+ 	  && EXTRACT_RVC_ADDI16SP_IMM (insn) != 0);
+ }
+@@ -195,9 +205,10 @@ match_c_addi16sp (const struct riscv_opcode *op,
+ static int
+ match_c_lui (const struct riscv_opcode *op,
+ 	     insn_t insn,
+-	     int constraints ATTRIBUTE_UNUSED)
++	     int constraints ATTRIBUTE_UNUSED,
++	     const char **error ATTRIBUTE_UNUSED)
+ {
+-  return (match_rd_nonzero (op, insn, 0)
++  return (match_rd_nonzero (op, insn, 0, NULL)
+ 	  && (((insn & MASK_RD) >> OP_SH_RD) != 2)
+ 	  && EXTRACT_RVC_LUI_IMM (insn) != 0);
+ }
+@@ -208,9 +219,10 @@ match_c_lui (const struct riscv_opcode *op,
+ static int
+ match_c_lui_with_hint (const struct riscv_opcode *op,
+ 		       insn_t insn,
+-		       int constraints ATTRIBUTE_UNUSED)
++		       int constraints ATTRIBUTE_UNUSED,
++		       const char **error ATTRIBUTE_UNUSED)
+ {
+-  return (match_opcode (op, insn, 0)
++  return (match_opcode (op, insn, 0, NULL)
+ 	  && (((insn & MASK_RD) >> OP_SH_RD) != 2)
+ 	  && EXTRACT_RVC_LUI_IMM (insn) != 0);
+ }
+@@ -218,9 +230,11 @@ match_c_lui_with_hint (const struct riscv_opcode *op,
+ static int
+ match_c_addi4spn (const struct riscv_opcode *op,
+ 		  insn_t insn,
+-		  int constraints ATTRIBUTE_UNUSED)
++		  int constraints ATTRIBUTE_UNUSED,
++		  const char **error ATTRIBUTE_UNUSED)
+ {
+-  return match_opcode (op, insn, 0) && EXTRACT_RVC_ADDI4SPN_IMM (insn) != 0;
++  return (match_opcode (op, insn, 0, NULL)
++	  && EXTRACT_RVC_ADDI4SPN_IMM (insn) != 0);
+ }
+ 
+ /* This requires a non-zero shift.  A zero rd is a hint, so is allowed.  */
+@@ -228,9 +242,10 @@ match_c_addi4spn (const struct riscv_opcode *op,
+ static int
+ match_c_slli (const struct riscv_opcode *op,
+ 	      insn_t insn,
+-	      int constraints ATTRIBUTE_UNUSED)
++	      int constraints ATTRIBUTE_UNUSED,
++	      const char **error ATTRIBUTE_UNUSED)
+ {
+-  return match_opcode (op, insn, 0) && EXTRACT_RVC_IMM (insn) != 0;
++  return match_opcode (op, insn, 0, NULL) && EXTRACT_RVC_IMM (insn) != 0;
+ }
+ 
+ /* This requires a non-zero rd, and a non-zero shift.  */
+@@ -238,9 +253,11 @@ match_c_slli (const struct riscv_opcode *op,
+ static int
+ match_slli_as_c_slli (const struct riscv_opcode *op,
+ 		      insn_t insn,
+-		      int constraints ATTRIBUTE_UNUSED)
++		      int constraints ATTRIBUTE_UNUSED,
++		      const char **error ATTRIBUTE_UNUSED)
+ {
+-  return match_rd_nonzero (op, insn, 0) && EXTRACT_RVC_IMM (insn) != 0;
++  return (match_rd_nonzero (op, insn, 0, NULL)
++	  && EXTRACT_RVC_IMM (insn) != 0);
+ }
+ 
+ /* This requires a zero shift.  A zero rd is a hint, so is allowed.  */
+@@ -248,9 +265,10 @@ match_slli_as_c_slli (const struct riscv_opcode *op,
+ static int
+ match_c_slli64 (const struct riscv_opcode *op,
+ 		insn_t insn,
+-		int constraints ATTRIBUTE_UNUSED)
++		int constraints ATTRIBUTE_UNUSED,
++		const char **error ATTRIBUTE_UNUSED)
+ {
+-  return match_opcode (op, insn, 0) && EXTRACT_RVC_IMM (insn) == 0;
++  return match_opcode (op, insn, 0, NULL) && EXTRACT_RVC_IMM (insn) == 0;
+ }
+ 
+ /* This is used for both srli and srai.  This requires a non-zero shift.
+@@ -259,9 +277,10 @@ match_c_slli64 (const struct riscv_opcode *op,
+ static int
+ match_srxi_as_c_srxi (const struct riscv_opcode *op,
+ 		      insn_t insn,
+-		      int constraints ATTRIBUTE_UNUSED)
++		      int constraints ATTRIBUTE_UNUSED,
++		      const char **error ATTRIBUTE_UNUSED)
+ {
+-  return match_opcode (op, insn, 0) && EXTRACT_RVC_IMM (insn) != 0;
++  return match_opcode (op, insn, 0, NULL) && EXTRACT_RVC_IMM (insn) != 0;
+ }
+ 
+ /* These are used to check the vector constraints.  */
+@@ -269,186 +288,247 @@ match_srxi_as_c_srxi (const struct riscv_opcode *op,
+ static int
+ match_widen_vd_neq_vs1_neq_vs2_neq_vm (const struct riscv_opcode *op,
+ 				       insn_t insn,
+-				       int constraints)
++				       int constraints,
++				       const char **error)
+ {
+   int vd = (insn & MASK_VD) >> OP_SH_VD;
+   int vs1 = (insn & MASK_VS1) >> OP_SH_VS1;
+   int vs2 = (insn & MASK_VS2) >> OP_SH_VS2;
+   int vm = (insn & MASK_VMASK) >> OP_SH_VMASK;
+ 
+-  if (constraints
+-      && ((vd % 2) != 0
+-	  || (vs1 >= vd && vs1 <= (vd + 1))
+-	  || (vs2 >= vd && vs2 <= (vd + 1))
+-	  || (!vm && vm >= vd && vm <= (vd + 1))))
+-    return 0;
+-
+-  return match_opcode (op, insn, 0);
++  if (!constraints || error == NULL)
++    return match_opcode (op, insn, 0, NULL);
++
++  if ((vd % 2) != 0)
++    *error = "illegal operands vd must be multiple of 2";
++  else if (vs1 >= vd && vs1 <= (vd + 1))
++    *error = "illegal operands vd cannot overlap vs1";
++  else if (vs2 >= vd && vs2 <= (vd + 1))
++    *error = "illegal operands vd cannot overlap vs2";
++  else if (!vm && vm >= vd && vm <= (vd + 1))
++    *error = "illegal operands vd cannot overlap vm";
++  else
++    return match_opcode (op, insn, 0, NULL);
++  return 0;
+ }
+ 
+ static int
+ match_widen_vd_neq_vs1_neq_vm (const struct riscv_opcode *op,
+ 			       insn_t insn,
+-			       int constraints)
++			       int constraints,
++			       const char **error)
+ {
+   int vd = (insn & MASK_VD) >> OP_SH_VD;
+   int vs1 = (insn & MASK_VS1) >> OP_SH_VS1;
+   int vs2 = (insn & MASK_VS2) >> OP_SH_VS2;
+   int vm = (insn & MASK_VMASK) >> OP_SH_VMASK;
+ 
+-  if (constraints
+-      && ((vd % 2) != 0
+-	  || (vs2 % 2) != 0
+-	  || (vs1 >= vd && vs1 <= (vd + 1))
+-	  || (!vm && vm >= vd && vm <= (vd + 1))))
+-    return 0;
+-
+-  return match_opcode (op, insn, 0);
++  if (!constraints || error == NULL)
++    return match_opcode (op, insn, 0, NULL);
++
++  if ((vd % 2) != 0)
++    *error = "illegal operands vd must be multiple of 2";
++  else if ((vs2 % 2) != 0)
++    *error = "illegal operands vs2 must be multiple of 2";
++  else if (vs1 >= vd && vs1 <= (vd + 1))
++    *error = "illegal operands vd cannot overlap vs1";
++  else if (!vm && vm >= vd && vm <= (vd + 1))
++    *error = "illegal operands vd cannot overlap vm";
++  else
++    return match_opcode (op, insn, 0, NULL);
++  return 0;
+ }
+ 
+ static int
+ match_widen_vd_neq_vs2_neq_vm (const struct riscv_opcode *op,
+ 			       insn_t insn,
+-			       int constraints)
++			       int constraints,
++			       const char **error)
+ {
+   int vd = (insn & MASK_VD) >> OP_SH_VD;
+   int vs2 = (insn & MASK_VS2) >> OP_SH_VS2;
+   int vm = (insn & MASK_VMASK) >> OP_SH_VMASK;
+ 
+-  if (constraints
+-      && ((vd % 2) != 0
+-	  || (vs2 >= vd && vs2 <= (vd + 1))
+-	  || (!vm && vm >= vd && vm <= (vd + 1))))
+-    return 0;
+-
+-  return match_opcode (op, insn, 0);
++  if (!constraints || error == NULL)
++    return match_opcode (op, insn, 0, NULL);
++
++  if ((vd % 2) != 0)
++    *error = "illegal operands vd must be multiple of 2";
++  else if (vs2 >= vd && vs2 <= (vd + 1))
++    *error = "illegal operands vd cannot overlap vs2";
++  else if (!vm && vm >= vd && vm <= (vd + 1))
++    *error = "illegal operands vd cannot overlap vm";
++  else
++    return match_opcode (op, insn, 0, NULL);
++  return 0;
+ }
+ 
+ static int
+ match_widen_vd_neq_vm (const struct riscv_opcode *op,
+ 		       insn_t insn,
+-		       int constraints)
++		       int constraints,
++		       const char **error)
+ {
+   int vd = (insn & MASK_VD) >> OP_SH_VD;
+   int vs2 = (insn & MASK_VS2) >> OP_SH_VS2;
+   int vm = (insn & MASK_VMASK) >> OP_SH_VMASK;
+ 
+-  if (constraints
+-      && ((vd % 2) != 0
+-	  || (vs2 % 2) != 0
+-	  || (!vm && vm >= vd && vm <= (vd + 1))))
+-    return 0;
+-
+-  return match_opcode (op, insn, 0);
++  if (!constraints || error == NULL)
++    return match_opcode (op, insn, 0, NULL);
++
++  if ((vd % 2) != 0)
++    *error = "illegal operands vd must be multiple of 2";
++  else if ((vs2 % 2) != 0)
++    *error = "illegal operands vs2 must be multiple of 2";
++  else if (!vm && vm >= vd && vm <= (vd + 1))
++    *error = "illegal operands vd cannot overlap vm";
++  else
++    return match_opcode (op, insn, 0, NULL);
++  return 0;
+ }
+ 
+ static int
+ match_quad_vd_neq_vs1_neq_vs2_neq_vm (const struct riscv_opcode *op,
+ 				      insn_t insn,
+-				      int constraints)
++				      int constraints,
++				      const char **error)
+ {
+   int vd = (insn & MASK_VD) >> OP_SH_VD;
+   int vs1 = (insn & MASK_VS1) >> OP_SH_VS1;
+   int vs2 = (insn & MASK_VS2) >> OP_SH_VS2;
+   int vm = (insn & MASK_VMASK) >> OP_SH_VMASK;
+ 
+-  if (constraints
+-      && ((vd % 4) != 0
+-	  || (vs1 >= vd && vs1 <= (vd + 3))
+-	  || (vs2 >= vd && vs2 <= (vd + 3))
+-	  || (!vm && vm >= vd && vm <= (vd + 3))))
+-    return 0;
+-
+-  return match_opcode (op, insn, 0);
++  if (!constraints || error == NULL)
++    return match_opcode (op, insn, 0, NULL);
++
++  if ((vd % 4) != 0)
++    *error = "illegal operands vd must be multiple of 4";
++  else if (vs1 >= vd && vs1 <= (vd + 3))
++    *error = "illegal operands vd cannot overlap vs1";
++  else if (vs2 >= vd && vs2 <= (vd + 3))
++    *error = "illegal operands vd cannot overlap vs2";
++  else if (!vm && vm >= vd && vm <= (vd + 3))
++    *error = "illegal operands vd cannot overlap vm";
++  else
++    return match_opcode (op, insn, 0, NULL);
++  return 0;
+ }
+ 
+ static int
+ match_quad_vd_neq_vs2_neq_vm (const struct riscv_opcode *op,
+ 			      insn_t insn,
+-			      int constraints)
++			      int constraints,
++			      const char **error)
+ {
+   int vd = (insn & MASK_VD) >> OP_SH_VD;
+   int vs2 = (insn & MASK_VS2) >> OP_SH_VS2;
+   int vm = (insn & MASK_VMASK) >> OP_SH_VMASK;
+ 
+-  if (constraints
+-      && ((vd % 4) != 0
+-	  || (vs2 >= vd && vs2 <= (vd + 3))
+-	  || (!vm && vm >= vd && vm <= (vd + 3))))
+-    return 0;
+-
+-  return match_opcode (op, insn, 0);
++  if (!constraints || error == NULL)
++    return match_opcode (op, insn, 0, NULL);
++
++  if ((vd % 4) != 0)
++    *error = "illegal operands vd must be multiple of 4";
++  else if (vs2 >= vd && vs2 <= (vd + 3))
++    *error = "illegal operands vd cannot overlap vs2";
++  else if (!vm && vm >= vd && vm <= (vd + 3))
++    *error = "illegal operands vd cannot overlap vm";
++  else
++    return match_opcode (op, insn, 0, NULL);
++  return 0;
+ }
+ 
+ static int
+ match_narrow_vd_neq_vs2_neq_vm (const struct riscv_opcode *op,
+ 				insn_t insn,
+-				int constraints)
++				int constraints,
++				const char **error)
+ {
+   int vd = (insn & MASK_VD) >> OP_SH_VD;
+   int vs2 = (insn & MASK_VS2) >> OP_SH_VS2;
+   int vm = (insn & MASK_VMASK) >> OP_SH_VMASK;
+ 
+-  if (constraints
+-      && ((vs2 % 2) != 0
+-	  || (vd >= vs2 && vd <= (vs2 + 1))
+-	  || (!vm && vd >= vm && vd <= (vm + 1))))
+-    return 0;
+-
+-  return match_opcode (op, insn, 0);
++  if (!constraints || error == NULL)
++    return match_opcode (op, insn, 0, NULL);
++
++  if ((vs2 % 2) != 0)
++    *error = "illegal operands vd must be multiple of 2";
++  else if (vd >= vs2 && vd <= (vs2 + 1))
++    *error = "illegal operands vd cannot overlap vs2";
++  else if (!vm && vd >= vm && vd <= (vm + 1))
++    *error = "illegal operands vd cannot overlap vm";
++  else
++    return match_opcode (op, insn, 0, NULL);
++  return 0;
+ }
+ 
+ static int
+ match_vd_neq_vs1_neq_vs2 (const struct riscv_opcode *op,
+ 			  insn_t insn,
+-			  int constraints)
++			  int constraints,
++			  const char **error)
+ {
+   int vd = (insn & MASK_VD) >> OP_SH_VD;
+   int vs1 = (insn & MASK_VS1) >> OP_SH_VS1;
+   int vs2 = (insn & MASK_VS2) >> OP_SH_VS2;
+ 
+-  if (constraints
+-      && (vs1 == vd
+-	  || vs2 == vd))
+-    return 0;
++  if (!constraints || error == NULL)
++    return match_opcode (op, insn, 0, NULL);
+ 
+-  return match_opcode (op, insn, 0);
++  if (vs1 == vd)
++    *error = "illegal operands vd cannot overlap vs1";
++  else if (vs2 == vd)
++    *error = "illegal operands vd cannot overlap vs2";
++  else
++    return match_opcode (op, insn, 0, NULL);
++  return 0;
+ }
+ 
+ static int
+ match_vd_neq_vs1_neq_vs2_neq_vm (const struct riscv_opcode *op,
+ 				 insn_t insn,
+-				 int constraints)
++				 int constraints,
++				 const char **error)
+ {
+   int vd = (insn & MASK_VD) >> OP_SH_VD;
+   int vs1 = (insn & MASK_VS1) >> OP_SH_VS1;
+   int vs2 = (insn & MASK_VS2) >> OP_SH_VS2;
+   int vm = (insn & MASK_VMASK) >> OP_SH_VMASK;
+ 
+-  if (constraints
+-      && (vs1 == vd
+-	  || vs2 == vd
+-	  || (!vm && vm == vd)))
+-    return 0;
+-
+-  return match_opcode (op, insn, 0);
++  if (!constraints || error == NULL)
++    return match_opcode (op, insn, 0, NULL);
++
++  if (vs1 == vd)
++    *error = "illegal operands vd cannot overlap vs1";
++  else if (vs2 == vd)
++    *error = "illegal operands vd cannot overlap vs2";
++  else if (!vm && vm == vd)
++    *error = "illegal operands vd cannot overlap vm";
++  else
++    return match_opcode (op, insn, 0, NULL);
++  return 0;
+ }
+ 
+ static int
+ match_vd_neq_vs2_neq_vm (const struct riscv_opcode *op,
+ 			 insn_t insn,
+-			 int constraints)
++			 int constraints,
++			 const char **error)
+ {
+   int vd = (insn & MASK_VD) >> OP_SH_VD;
+   int vs2 = (insn & MASK_VS2) >> OP_SH_VS2;
+   int vm = (insn & MASK_VMASK) >> OP_SH_VMASK;
+ 
+-   if (constraints
+-      && (vs2 == vd
+-	  || (!vm && vm == vd)))
+-    return 0;
++  if (!constraints || error == NULL)
++    return match_opcode (op, insn, 0, NULL);
+ 
+-  return match_opcode (op, insn, 0);
++  if (vs2 == vd)
++    *error = "illegal operands vd cannot overlap vs2";
++  else if (!vm && vm == vd)
++    *error = "illegal operands vd cannot overlap vm";
++  else
++    return match_opcode (op, insn, 0, NULL);
++  return 0;
+ }
+ 
+ /* v[m]adc and v[m]sbc use the vm encoding to encode the
+@@ -459,47 +539,61 @@ match_vd_neq_vs2_neq_vm (const struct riscv_opcode *op,
+ static int
+ match_vd_neq_vm (const struct riscv_opcode *op,
+ 		 insn_t insn,
+-		 int constraints)
++		 int constraints,
++		 const char **error)
+ {
+   int vd = (insn & MASK_VD) >> OP_SH_VD;
+   int vm = (insn & MASK_VMASK) >> OP_SH_VMASK;
+ 
+-  if (constraints && !vm && vm == vd)
+-    return 0;
++  if (!constraints || error == NULL)
++    return match_opcode (op, insn, 0, NULL);
+ 
+-  return match_opcode (op, insn, 0);
++  if (!vm && vm == vd)
++    *error = "illegal operands vd cannot overlap vm";
++  else
++    return match_opcode (op, insn, 0, NULL);
++  return 0;
+ }
+ 
+ static int
+ match_vls_nf_rv (const struct riscv_opcode *op,
+ 		 insn_t insn,
+-		 int constraints)
++		 int constraints,
++		 const char **error)
+ {
+   int vd = (insn & MASK_VD) >> OP_SH_VD;
+   int nf = ((insn & (0x7 << 29) ) >> 29) + 1;
+ 
+-  if (constraints
+-      && ((vd % nf) != 0))
+-    return 0;
++  if (!constraints || error == NULL)
++    return match_opcode (op, insn, 0, NULL);
+ 
+-  return match_opcode (op, insn, 0);
++  if ((vd % nf) != 0)
++    *error = "illegal operands vd must be multiple of nf";
++  else
++    return match_opcode (op, insn, 0, NULL);
++  return 0;
+ }
+ 
+ static int
+ match_vmv_nf_rv (const struct riscv_opcode *op,
+ 		 insn_t insn,
+-		 int constraints)
++		 int constraints,
++		 const char **error)
+ {
+   int vd = (insn & MASK_VD) >> OP_SH_VD;
+   int vs2 = (insn & MASK_VS2) >> OP_SH_VS2;
+   int nf = ((insn & (0x7 << 15) ) >> 15) + 1;
+ 
+-  if (constraints
+-      && ((vd % nf) != 0
+-	  || (vs2 % nf) != 0))
+-    return 0;
++  if (!constraints || error == NULL)
++    return match_opcode (op, insn, 0, NULL);
+ 
+-  return match_opcode (op, insn, 0);
++  if ((vd % nf) != 0)
++    *error = "illegal operands vd must be multiple of nf";
++  else if ((vs2 % nf) != 0)
++    *error = "illegal operands vs2 must be multiple of nf";
++  else
++    return match_opcode (op, insn, 0, NULL);
++  return 0;
+ }
+ 
+ const struct riscv_opcode riscv_opcodes[] =
+-- 
+2.33.0
+

+ 550 - 0
recipes-devtools/gdb/files/0028-RISC-V-Support-Zfh-standard-extension-for-half-preci.patch

@@ -0,0 +1,550 @@
+From 4003a9ae6f2e2cdbd92cb9d85c48ec672228894c Mon Sep 17 00:00:00 2001
+From: Nelson Chu <nelson.chu@sifive.com>
+Date: Thu, 26 Mar 2020 18:38:27 +0800
+Subject: [PATCH 28/48] RISC-V: Support Zfh standard extension for
+ half-precision floating-point.
+
+---
+ bfd/elfxx-riscv.c                      |   2 +-
+ gas/config/tc-riscv.c                  |  23 +++++-
+ gas/testsuite/gas/riscv/fp-zfh-insns.d |  71 ++++++++++++++++
+ gas/testsuite/gas/riscv/fp-zfh-insns.s |  68 ++++++++++++++++
+ include/opcode/riscv-opc.h             | 108 +++++++++++++++++++++++++
+ include/opcode/riscv.h                 |   9 ++-
+ opcodes/riscv-opc.c                    |  65 +++++++++++++++
+ 7 files changed, 340 insertions(+), 6 deletions(-)
+ create mode 100644 gas/testsuite/gas/riscv/fp-zfh-insns.d
+ create mode 100644 gas/testsuite/gas/riscv/fp-zfh-insns.s
+
+diff --git a/bfd/elfxx-riscv.c b/bfd/elfxx-riscv.c
+index f797d28f59..67dbc2e682 100644
+--- a/bfd/elfxx-riscv.c
++++ b/bfd/elfxx-riscv.c
+@@ -1566,7 +1566,7 @@ riscv_parse_prefixed_ext (riscv_parse_subset_t *rps,
+ 
+ static const char * const riscv_std_z_ext_strtab[] =
+ {
+-  "zicsr", "zifencei",
++  "zicsr", "zifencei", "zfh",
+   "zvamo", "zvediv", "zvlsseg", "zvqmac",
+   NULL
+ };
+diff --git a/gas/config/tc-riscv.c b/gas/config/tc-riscv.c
+index eca9fabb3f..bb2819db4a 100644
+--- a/gas/config/tc-riscv.c
++++ b/gas/config/tc-riscv.c
+@@ -229,15 +229,22 @@ riscv_multi_subset_supports (enum riscv_insn_class insn_class)
+     case INSN_CLASS_C: return riscv_subset_supports ("c");
+     case INSN_CLASS_A: return riscv_subset_supports ("a");
+     case INSN_CLASS_M: return riscv_subset_supports ("m");
++
+     case INSN_CLASS_F: return riscv_subset_supports ("f");
++    case INSN_CLASS_F_AND_C:
++      return riscv_subset_supports ("f") && riscv_subset_supports ("c");
++    case INSN_CLASS_F_AND_ZFH:
++      return riscv_subset_supports ("f") && riscv_subset_supports ("zfh");
++
+     case INSN_CLASS_D: return riscv_subset_supports ("d");
+     case INSN_CLASS_D_AND_C:
+       return riscv_subset_supports ("d") && riscv_subset_supports ("c");
+-
+-    case INSN_CLASS_F_AND_C:
+-      return riscv_subset_supports ("f") && riscv_subset_supports ("c");
++    case INSN_CLASS_D_AND_ZFH:
++      return riscv_subset_supports ("d") && riscv_subset_supports ("zfh");
+ 
+     case INSN_CLASS_Q: return riscv_subset_supports ("q");
++    case INSN_CLASS_Q_AND_ZFH:
++      return riscv_subset_supports ("q") && riscv_subset_supports ("zfh");
+ 
+     case INSN_CLASS_V: return riscv_subset_supports ("v");
+     case INSN_CLASS_V_AND_F:
+@@ -1624,6 +1631,11 @@ macro (struct riscv_cl_insn *ip, expressionS *imm_expr,
+ 		  BFD_RELOC_RISCV_PCREL_HI20, BFD_RELOC_RISCV_PCREL_LO12_I);
+       break;
+ 
++    case M_FLH:
++      pcrel_load (rd, rs1, imm_expr, "flh",
++		  BFD_RELOC_RISCV_PCREL_HI20, BFD_RELOC_RISCV_PCREL_LO12_I);
++      break;
++
+     case M_FLW:
+       pcrel_load (rd, rs1, imm_expr, "flw",
+ 		  BFD_RELOC_RISCV_PCREL_HI20, BFD_RELOC_RISCV_PCREL_LO12_I);
+@@ -1654,6 +1666,11 @@ macro (struct riscv_cl_insn *ip, expressionS *imm_expr,
+ 		   BFD_RELOC_RISCV_PCREL_HI20, BFD_RELOC_RISCV_PCREL_LO12_S);
+       break;
+ 
++    case M_FSH:
++      pcrel_store (rs2, rs1, imm_expr, "fsh",
++		   BFD_RELOC_RISCV_PCREL_HI20, BFD_RELOC_RISCV_PCREL_LO12_S);
++      break;
++
+     case M_FSW:
+       pcrel_store (rs2, rs1, imm_expr, "fsw",
+ 		   BFD_RELOC_RISCV_PCREL_HI20, BFD_RELOC_RISCV_PCREL_LO12_S);
+diff --git a/gas/testsuite/gas/riscv/fp-zfh-insns.d b/gas/testsuite/gas/riscv/fp-zfh-insns.d
+new file mode 100644
+index 0000000000..e6c0ac502e
+--- /dev/null
++++ b/gas/testsuite/gas/riscv/fp-zfh-insns.d
+@@ -0,0 +1,71 @@
++#as: -march=rv64ifdq_zfh
++#source: fp-zfh-insns.s
++#objdump: -dr
++
++.*:[ 	]+file format .*
++
++
++Disassembly of section .text:
++
++0+000 <.text>:
++[ 	]+[0-9a-f]+:[ 	]+00059507[ 	]+flh[ 	]+fa0,0\(a1\)
++[ 	]+[0-9a-f]+:[ 	]+00a59027[ 	]+fsh[ 	]+fa0,0\(a1\)
++[ 	]+[0-9a-f]+:[ 	]+24b58553[ 	]+fmv.h[ 	]+fa0,fa1
++[ 	]+[0-9a-f]+:[ 	]+24b59553[ 	]+fneg.h[ 	]+fa0,fa1
++[ 	]+[0-9a-f]+:[ 	]+24b5a553[ 	]+fabs.h[ 	]+fa0,fa1
++[ 	]+[0-9a-f]+:[ 	]+24c58553[ 	]+fsgnj.h[ 	]+fa0,fa1,fa2
++[ 	]+[0-9a-f]+:[ 	]+24c59553[ 	]+fsgnjn.h[ 	]+fa0,fa1,fa2
++[ 	]+[0-9a-f]+:[ 	]+24c5a553[ 	]+fsgnjx.h[ 	]+fa0,fa1,fa2
++[ 	]+[0-9a-f]+:[ 	]+04c5f553[ 	]+fadd.h[ 	]+fa0,fa1,fa2
++[ 	]+[0-9a-f]+:[ 	]+04c58553[ 	]+fadd.h[ 	]+fa0,fa1,fa2,rne
++[ 	]+[0-9a-f]+:[ 	]+0cc5f553[ 	]+fsub.h[ 	]+fa0,fa1,fa2
++[ 	]+[0-9a-f]+:[ 	]+0cc58553[ 	]+fsub.h[ 	]+fa0,fa1,fa2,rne
++[ 	]+[0-9a-f]+:[ 	]+14c5f553[ 	]+fmul.h[ 	]+fa0,fa1,fa2
++[ 	]+[0-9a-f]+:[ 	]+14c58553[ 	]+fmul.h[ 	]+fa0,fa1,fa2,rne
++[ 	]+[0-9a-f]+:[ 	]+1cc5f553[ 	]+fdiv.h[ 	]+fa0,fa1,fa2
++[ 	]+[0-9a-f]+:[ 	]+1cc58553[ 	]+fdiv.h[ 	]+fa0,fa1,fa2,rne
++[ 	]+[0-9a-f]+:[ 	]+5c05f553[ 	]+fsqrt.h[ 	]+fa0,fa1
++[ 	]+[0-9a-f]+:[ 	]+5c058553[ 	]+fsqrt.h[ 	]+fa0,fa1,rne
++[ 	]+[0-9a-f]+:[ 	]+2cc58553[ 	]+fmin.h[ 	]+fa0,fa1,fa2
++[ 	]+[0-9a-f]+:[ 	]+2cc59553[ 	]+fmax.h[ 	]+fa0,fa1,fa2
++[ 	]+[0-9a-f]+:[ 	]+6cc5f543[ 	]+fmadd.h[ 	]+fa0,fa1,fa2,fa3
++[ 	]+[0-9a-f]+:[ 	]+6cc58543[ 	]+fmadd.h[ 	]+fa0,fa1,fa2,fa3,rne
++[ 	]+[0-9a-f]+:[ 	]+6cc5f54f[ 	]+fnmadd.h[ 	]+fa0,fa1,fa2,fa3
++[ 	]+[0-9a-f]+:[ 	]+6cc5854f[ 	]+fnmadd.h[ 	]+fa0,fa1,fa2,fa3,rne
++[ 	]+[0-9a-f]+:[ 	]+6cc5f547[ 	]+fmsub.h[ 	]+fa0,fa1,fa2,fa3
++[ 	]+[0-9a-f]+:[ 	]+6cc58547[ 	]+fmsub.h[ 	]+fa0,fa1,fa2,fa3,rne
++[ 	]+[0-9a-f]+:[ 	]+6cc5f54b[ 	]+fnmsub.h[ 	]+fa0,fa1,fa2,fa3
++[ 	]+[0-9a-f]+:[ 	]+6cc5854b[ 	]+fnmsub.h[ 	]+fa0,fa1,fa2,fa3,rne
++[ 	]+[0-9a-f]+:[ 	]+c405f553[ 	]+fcvt.w.h[ 	]+a0,fa1
++[ 	]+[0-9a-f]+:[ 	]+c4058553[ 	]+fcvt.w.h[ 	]+a0,fa1,rne
++[ 	]+[0-9a-f]+:[ 	]+c415f553[ 	]+fcvt.wu.h[ 	]+a0,fa1
++[ 	]+[0-9a-f]+:[ 	]+c4158553[ 	]+fcvt.wu.h[ 	]+a0,fa1,rne
++[ 	]+[0-9a-f]+:[ 	]+d405f553[ 	]+fcvt.h.w[ 	]+fa0,a1
++[ 	]+[0-9a-f]+:[ 	]+d4058553[ 	]+fcvt.h.w[ 	]+fa0,a1,rne
++[ 	]+[0-9a-f]+:[ 	]+d415f553[ 	]+fcvt.h.wu[ 	]+fa0,a1
++[ 	]+[0-9a-f]+:[ 	]+d4158553[ 	]+fcvt.h.wu[ 	]+fa0,a1,rne
++[ 	]+[0-9a-f]+:[ 	]+c425f553[ 	]+fcvt.l.h[ 	]+a0,fa1
++[ 	]+[0-9a-f]+:[ 	]+c4258553[ 	]+fcvt.l.h[ 	]+a0,fa1,rne
++[ 	]+[0-9a-f]+:[ 	]+c435f553[ 	]+fcvt.lu.h[ 	]+a0,fa1
++[ 	]+[0-9a-f]+:[ 	]+c4358553[ 	]+fcvt.lu.h[ 	]+a0,fa1,rne
++[ 	]+[0-9a-f]+:[ 	]+d425f553[ 	]+fcvt.h.l[ 	]+fa0,a1
++[ 	]+[0-9a-f]+:[ 	]+d4258553[ 	]+fcvt.h.l[ 	]+fa0,a1,rne
++[ 	]+[0-9a-f]+:[ 	]+d435f553[ 	]+fcvt.h.lu[ 	]+fa0,a1
++[ 	]+[0-9a-f]+:[ 	]+d4358553[ 	]+fcvt.h.lu[ 	]+fa0,a1,rne
++[ 	]+[0-9a-f]+:[ 	]+e4058553[ 	]+fmv.x.h[ 	]+a0,fa1
++[ 	]+[0-9a-f]+:[ 	]+f4058553[ 	]+fmv.h.x[ 	]+fa0,a1
++[ 	]+[0-9a-f]+:[ 	]+40258553[ 	]+fcvt.s.h[ 	]+fa0,fa1
++[ 	]+[0-9a-f]+:[ 	]+42258553[ 	]+fcvt.d.h[ 	]+fa0,fa1
++[ 	]+[0-9a-f]+:[ 	]+46358553[ 	]+fcvt.q.h[ 	]+fa0,fa1
++[ 	]+[0-9a-f]+:[ 	]+4405f553[ 	]+fcvt.h.s[ 	]+fa0,fa1
++[ 	]+[0-9a-f]+:[ 	]+44058553[ 	]+fcvt.h.s[ 	]+fa0,fa1,rne
++[ 	]+[0-9a-f]+:[ 	]+4415f553[ 	]+fcvt.h.d[ 	]+fa0,fa1
++[ 	]+[0-9a-f]+:[ 	]+44158553[ 	]+fcvt.h.d[ 	]+fa0,fa1,rne
++[ 	]+[0-9a-f]+:[ 	]+4425f553[ 	]+fcvt.h.q[ 	]+fa0,fa1
++[ 	]+[0-9a-f]+:[ 	]+44258553[ 	]+fcvt.h.q[ 	]+fa0,fa1,rne
++[ 	]+[0-9a-f]+:[ 	]+e4059553[ 	]+fclass.h[ 	]+a0,fa1
++[ 	]+[0-9a-f]+:[ 	]+a4c5a553[ 	]+feq.h[ 	]+a0,fa1,fa2
++[ 	]+[0-9a-f]+:[ 	]+a4c59553[ 	]+flt.h[ 	]+a0,fa1,fa2
++[ 	]+[0-9a-f]+:[ 	]+a4c58553[ 	]+fle.h[ 	]+a0,fa1,fa2
++[ 	]+[0-9a-f]+:[ 	]+a4c59553[ 	]+flt.h[ 	]+a0,fa1,fa2
++[ 	]+[0-9a-f]+:[ 	]+a4c58553[ 	]+fle.h[ 	]+a0,fa1,fa2
+diff --git a/gas/testsuite/gas/riscv/fp-zfh-insns.s b/gas/testsuite/gas/riscv/fp-zfh-insns.s
+new file mode 100644
+index 0000000000..1a04cc6400
+--- /dev/null
++++ b/gas/testsuite/gas/riscv/fp-zfh-insns.s
+@@ -0,0 +1,68 @@
++	flh		fa0, 0(a1)
++	fsh		fa0, 0(a1)
++
++	fmv.h		fa0, fa1
++	fneg.h		fa0, fa1
++	fabs.h		fa0, fa1
++	fsgnj.h		fa0, fa1, fa2
++	fsgnjn.h	fa0, fa1, fa2
++	fsgnjx.h	fa0, fa1, fa2
++
++	fadd.h		fa0, fa1, fa2
++	fadd.h		fa0, fa1, fa2, rne
++	fsub.h		fa0, fa1, fa2
++	fsub.h		fa0, fa1, fa2, rne
++	fmul.h		fa0, fa1, fa2
++	fmul.h		fa0, fa1, fa2, rne
++	fdiv.h		fa0, fa1, fa2
++	fdiv.h		fa0, fa1, fa2, rne
++	fsqrt.h		fa0, fa1
++	fsqrt.h		fa0, fa1, rne
++	fmin.h		fa0, fa1, fa2
++	fmax.h		fa0, fa1, fa2
++
++	fmadd.h		fa0, fa1, fa2, fa3
++	fmadd.h		fa0, fa1, fa2, fa3, rne
++	fnmadd.h	fa0, fa1, fa2, fa3
++	fnmadd.h	fa0, fa1, fa2, fa3, rne
++	fmsub.h		fa0, fa1, fa2, fa3
++	fmsub.h		fa0, fa1, fa2, fa3, rne
++	fnmsub.h	fa0, fa1, fa2, fa3
++	fnmsub.h	fa0, fa1, fa2, fa3, rne
++
++	fcvt.w.h	a0, fa1
++	fcvt.w.h	a0, fa1, rne
++	fcvt.wu.h	a0, fa1
++	fcvt.wu.h	a0, fa1, rne
++	fcvt.h.w	fa0, a1
++	fcvt.h.w	fa0, a1, rne
++	fcvt.h.wu	fa0, a1
++	fcvt.h.wu	fa0, a1, rne
++	fcvt.l.h	a0, fa1
++	fcvt.l.h	a0, fa1, rne
++	fcvt.lu.h	a0, fa1
++	fcvt.lu.h	a0, fa1, rne
++	fcvt.h.l	fa0, a1
++	fcvt.h.l	fa0, a1, rne
++	fcvt.h.lu	fa0, a1
++	fcvt.h.lu	fa0, a1, rne
++
++	fmv.x.h		a0, fa1
++	fmv.h.x		fa0, a1
++
++	fcvt.s.h	fa0, fa1
++	fcvt.d.h	fa0, fa1
++	fcvt.q.h	fa0, fa1
++	fcvt.h.s	fa0, fa1
++	fcvt.h.s	fa0, fa1, rne
++	fcvt.h.d	fa0, fa1
++	fcvt.h.d	fa0, fa1, rne
++	fcvt.h.q	fa0, fa1
++	fcvt.h.q	fa0, fa1, rne
++	fclass.h	a0, fa1
++
++	feq.h		a0, fa1, fa2
++	flt.h		a0, fa1, fa2
++	fle.h		a0, fa1, fa2
++	fgt.h		a0, fa2, fa1
++	fge.h		a0, fa2, fa1
+diff --git a/include/opcode/riscv-opc.h b/include/opcode/riscv-opc.h
+index cd1395a010..743060ca18 100644
+--- a/include/opcode/riscv-opc.h
++++ b/include/opcode/riscv-opc.h
+@@ -309,6 +309,38 @@
+ #define MASK_FCVT_D_S  0xfff0007f
+ #define MATCH_FSQRT_D 0x5a000053
+ #define MASK_FSQRT_D  0xfff0007f
++#define MATCH_FADD_H 0x4000053
++#define MASK_FADD_H  0xfe00007f
++#define MATCH_FSUB_H 0xc000053
++#define MASK_FSUB_H  0xfe00007f
++#define MATCH_FMUL_H 0x14000053
++#define MASK_FMUL_H  0xfe00007f
++#define MATCH_FDIV_H 0x1c000053
++#define MASK_FDIV_H  0xfe00007f
++#define MATCH_FSGNJ_H 0x24000053
++#define MASK_FSGNJ_H  0xfe00707f
++#define MATCH_FSGNJN_H 0x24001053
++#define MASK_FSGNJN_H  0xfe00707f
++#define MATCH_FSGNJX_H 0x24002053
++#define MASK_FSGNJX_H  0xfe00707f
++#define MATCH_FMIN_H 0x2c000053
++#define MASK_FMIN_H  0xfe00707f
++#define MATCH_FMAX_H 0x2c001053
++#define MASK_FMAX_H  0xfe00707f
++#define MATCH_FCVT_S_H 0x40200053
++#define MASK_FCVT_S_H  0xfff0007f
++#define MATCH_FCVT_H_S 0x44000053
++#define MASK_FCVT_H_S  0xfff0007f
++#define MATCH_FCVT_D_H 0x42200053
++#define MASK_FCVT_D_H  0xfff0007f
++#define MATCH_FCVT_H_D 0x44100053
++#define MASK_FCVT_H_D  0xfff0007f
++#define MATCH_FCVT_Q_H 0x46300053
++#define MASK_FCVT_Q_H  0xfff0007f
++#define MATCH_FCVT_H_Q 0x44200053
++#define MASK_FCVT_H_Q  0xfff0007f
++#define MATCH_FSQRT_H 0x5c000053
++#define MASK_FSQRT_H  0xfff0007f
+ #define MATCH_FADD_Q 0x6000053
+ #define MASK_FADD_Q  0xfe00007f
+ #define MATCH_FSUB_Q 0xe000053
+@@ -349,6 +381,12 @@
+ #define MASK_FLT_D  0xfe00707f
+ #define MATCH_FEQ_D 0xa2002053
+ #define MASK_FEQ_D  0xfe00707f
++#define MATCH_FLE_H 0xa4000053
++#define MASK_FLE_H  0xfe00707f
++#define MATCH_FLT_H 0xa4001053
++#define MASK_FLT_H  0xfe00707f
++#define MATCH_FEQ_H 0xa4002053
++#define MASK_FEQ_H  0xfe00707f
+ #define MATCH_FLE_Q 0xa6000053
+ #define MASK_FLE_Q  0xfe00707f
+ #define MATCH_FLT_Q 0xa6001053
+@@ -379,6 +417,18 @@
+ #define MASK_FMV_X_D  0xfff0707f
+ #define MATCH_FCLASS_D 0xe2001053
+ #define MASK_FCLASS_D  0xfff0707f
++#define MATCH_FCVT_W_H 0xc4000053
++#define MASK_FCVT_W_H  0xfff0007f
++#define MATCH_FCVT_WU_H 0xc4100053
++#define MASK_FCVT_WU_H  0xfff0007f
++#define MATCH_FCVT_L_H 0xc4200053
++#define MASK_FCVT_L_H  0xfff0007f
++#define MATCH_FCVT_LU_H 0xc4300053
++#define MASK_FCVT_LU_H  0xfff0007f
++#define MATCH_FMV_X_H 0xe4000053
++#define MASK_FMV_X_H  0xfff0707f
++#define MATCH_FCLASS_H 0xe4001053
++#define MASK_FCLASS_H  0xfff0707f
+ #define MATCH_FCVT_W_Q 0xc6000053
+ #define MASK_FCVT_W_Q  0xfff0007f
+ #define MATCH_FCVT_WU_Q 0xc6100053
+@@ -411,6 +461,16 @@
+ #define MASK_FCVT_D_LU  0xfff0007f
+ #define MATCH_FMV_D_X 0xf2000053
+ #define MASK_FMV_D_X  0xfff0707f
++#define MATCH_FCVT_H_W 0xd4000053
++#define MASK_FCVT_H_W  0xfff0007f
++#define MATCH_FCVT_H_WU 0xd4100053
++#define MASK_FCVT_H_WU  0xfff0007f
++#define MATCH_FCVT_H_L 0xd4200053
++#define MASK_FCVT_H_L  0xfff0007f
++#define MATCH_FCVT_H_LU 0xd4300053
++#define MASK_FCVT_H_LU  0xfff0007f
++#define MATCH_FMV_H_X 0xf4000053
++#define MASK_FMV_H_X  0xfff0707f
+ #define MATCH_FCVT_Q_W 0xd6000053
+ #define MASK_FCVT_Q_W  0xfff0007f
+ #define MATCH_FCVT_Q_WU 0xd6100053
+@@ -421,12 +481,16 @@
+ #define MASK_FCVT_Q_LU  0xfff0007f
+ #define MATCH_FMV_Q_X 0xf6000053
+ #define MASK_FMV_Q_X  0xfff0707f
++#define MATCH_FLH 0x1007
++#define MASK_FLH  0x707f
+ #define MATCH_FLW 0x2007
+ #define MASK_FLW  0x707f
+ #define MATCH_FLD 0x3007
+ #define MASK_FLD  0x707f
+ #define MATCH_FLQ 0x4007
+ #define MASK_FLQ  0x707f
++#define MATCH_FSH 0x1027
++#define MASK_FSH  0x707f
+ #define MATCH_FSW 0x2027
+ #define MASK_FSW  0x707f
+ #define MATCH_FSD 0x3027
+@@ -449,6 +513,14 @@
+ #define MASK_FNMSUB_D  0x600007f
+ #define MATCH_FNMADD_D 0x200004f
+ #define MASK_FNMADD_D  0x600007f
++#define MATCH_FMADD_H 0x4000043
++#define MASK_FMADD_H  0x600007f
++#define MATCH_FMSUB_H 0x4000047
++#define MASK_FMSUB_H  0x600007f
++#define MATCH_FNMSUB_H 0x400004b
++#define MASK_FNMSUB_H  0x600007f
++#define MATCH_FNMADD_H 0x400004f
++#define MASK_FNMADD_H  0x600007f
+ #define MATCH_FMADD_Q 0x6000043
+ #define MASK_FMADD_Q  0x600007f
+ #define MATCH_FMSUB_Q 0x6000047
+@@ -3177,6 +3249,22 @@ DECLARE_INSN(fmax_d, MATCH_FMAX_D, MASK_FMAX_D)
+ DECLARE_INSN(fcvt_s_d, MATCH_FCVT_S_D, MASK_FCVT_S_D)
+ DECLARE_INSN(fcvt_d_s, MATCH_FCVT_D_S, MASK_FCVT_D_S)
+ DECLARE_INSN(fsqrt_d, MATCH_FSQRT_D, MASK_FSQRT_D)
++DECLARE_INSN(fadd_h, MATCH_FADD_H, MASK_FADD_H)
++DECLARE_INSN(fsub_h, MATCH_FSUB_D, MASK_FSUB_H)
++DECLARE_INSN(fmul_h, MATCH_FMUL_D, MASK_FMUL_H)
++DECLARE_INSN(fdiv_h, MATCH_FDIV_D, MASK_FDIV_H)
++DECLARE_INSN(fsgnj_h, MATCH_FSGNJ_D, MASK_FSGNJ_H)
++DECLARE_INSN(fsgnjn_h, MATCH_FSGNJN_D, MASK_FSGNJN_H)
++DECLARE_INSN(fsgnjx_h, MATCH_FSGNJX_D, MASK_FSGNJX_H)
++DECLARE_INSN(fmin_h, MATCH_FMIN_D, MASK_FMIN_H)
++DECLARE_INSN(fmax_h, MATCH_FMAX_D, MASK_FMAX_H)
++DECLARE_INSN(fcvt_s_h, MATCH_FCVT_S_D, MASK_FCVT_S_H)
++DECLARE_INSN(fcvt_h_s, MATCH_FCVT_H_S, MASK_FCVT_H_S)
++DECLARE_INSN(fcvt_d_h, MATCH_FCVT_D_H, MASK_FCVT_D_H)
++DECLARE_INSN(fcvt_h_d, MATCH_FCVT_H_D, MASK_FCVT_H_D)
++DECLARE_INSN(fcvt_q_h, MATCH_FCVT_Q_H, MASK_FCVT_Q_H)
++DECLARE_INSN(fcvt_h_q, MATCH_FCVT_H_Q, MASK_FCVT_H_Q)
++DECLARE_INSN(fsqrt_h, MATCH_FSQRT_H, MASK_FSQRT_H)
+ DECLARE_INSN(fadd_q, MATCH_FADD_Q, MASK_FADD_Q)
+ DECLARE_INSN(fsub_q, MATCH_FSUB_Q, MASK_FSUB_Q)
+ DECLARE_INSN(fmul_q, MATCH_FMUL_Q, MASK_FMUL_Q)
+@@ -3197,6 +3285,9 @@ DECLARE_INSN(feq_s, MATCH_FEQ_S, MASK_FEQ_S)
+ DECLARE_INSN(fle_d, MATCH_FLE_D, MASK_FLE_D)
+ DECLARE_INSN(flt_d, MATCH_FLT_D, MASK_FLT_D)
+ DECLARE_INSN(feq_d, MATCH_FEQ_D, MASK_FEQ_D)
++DECLARE_INSN(fle_h, MATCH_FLE_H, MASK_FLE_H)
++DECLARE_INSN(flt_h, MATCH_FLT_H, MASK_FLT_H)
++DECLARE_INSN(feq_h, MATCH_FEQ_H, MASK_FEQ_H)
+ DECLARE_INSN(fle_q, MATCH_FLE_Q, MASK_FLE_Q)
+ DECLARE_INSN(flt_q, MATCH_FLT_Q, MASK_FLT_Q)
+ DECLARE_INSN(feq_q, MATCH_FEQ_Q, MASK_FEQ_Q)
+@@ -3212,6 +3303,12 @@ DECLARE_INSN(fcvt_l_d, MATCH_FCVT_L_D, MASK_FCVT_L_D)
+ DECLARE_INSN(fcvt_lu_d, MATCH_FCVT_LU_D, MASK_FCVT_LU_D)
+ DECLARE_INSN(fmv_x_d, MATCH_FMV_X_D, MASK_FMV_X_D)
+ DECLARE_INSN(fclass_d, MATCH_FCLASS_D, MASK_FCLASS_D)
++DECLARE_INSN(fcvt_w_h, MATCH_FCVT_W_H, MASK_FCVT_W_H)
++DECLARE_INSN(fcvt_wu_h, MATCH_FCVT_WU_H, MASK_FCVT_WU_H)
++DECLARE_INSN(fcvt_l_h, MATCH_FCVT_L_H, MASK_FCVT_L_H)
++DECLARE_INSN(fcvt_lu_h, MATCH_FCVT_LU_H, MASK_FCVT_LU_H)
++DECLARE_INSN(fmv_x_h, MATCH_FMV_X_H, MASK_FMV_X_H)
++DECLARE_INSN(fclass_h, MATCH_FCLASS_H, MASK_FCLASS_H)
+ DECLARE_INSN(fcvt_w_q, MATCH_FCVT_W_Q, MASK_FCVT_W_Q)
+ DECLARE_INSN(fcvt_wu_q, MATCH_FCVT_WU_Q, MASK_FCVT_WU_Q)
+ DECLARE_INSN(fcvt_l_q, MATCH_FCVT_L_Q, MASK_FCVT_L_Q)
+@@ -3228,14 +3325,21 @@ DECLARE_INSN(fcvt_d_wu, MATCH_FCVT_D_WU, MASK_FCVT_D_WU)
+ DECLARE_INSN(fcvt_d_l, MATCH_FCVT_D_L, MASK_FCVT_D_L)
+ DECLARE_INSN(fcvt_d_lu, MATCH_FCVT_D_LU, MASK_FCVT_D_LU)
+ DECLARE_INSN(fmv_d_x, MATCH_FMV_D_X, MASK_FMV_D_X)
++DECLARE_INSN(fcvt_h_w, MATCH_FCVT_H_W, MASK_FCVT_H_W)
++DECLARE_INSN(fcvt_h_wu, MATCH_FCVT_H_WU, MASK_FCVT_H_WU)
++DECLARE_INSN(fcvt_h_l, MATCH_FCVT_H_L, MASK_FCVT_H_L)
++DECLARE_INSN(fcvt_h_lu, MATCH_FCVT_H_LU, MASK_FCVT_H_LU)
++DECLARE_INSN(fmv_h_x, MATCH_FMV_H_X, MASK_FMV_H_X)
+ DECLARE_INSN(fcvt_q_w, MATCH_FCVT_Q_W, MASK_FCVT_Q_W)
+ DECLARE_INSN(fcvt_q_wu, MATCH_FCVT_Q_WU, MASK_FCVT_Q_WU)
+ DECLARE_INSN(fcvt_q_l, MATCH_FCVT_Q_L, MASK_FCVT_Q_L)
+ DECLARE_INSN(fcvt_q_lu, MATCH_FCVT_Q_LU, MASK_FCVT_Q_LU)
+ DECLARE_INSN(fmv_q_x, MATCH_FMV_Q_X, MASK_FMV_Q_X)
++DECLARE_INSN(flh, MATCH_FLH, MASK_FLH)
+ DECLARE_INSN(flw, MATCH_FLW, MASK_FLW)
+ DECLARE_INSN(fld, MATCH_FLD, MASK_FLD)
+ DECLARE_INSN(flq, MATCH_FLQ, MASK_FLQ)
++DECLARE_INSN(fsh, MATCH_FSH, MASK_FSH)
+ DECLARE_INSN(fsw, MATCH_FSW, MASK_FSW)
+ DECLARE_INSN(fsd, MATCH_FSD, MASK_FSD)
+ DECLARE_INSN(fsq, MATCH_FSQ, MASK_FSQ)
+@@ -3247,6 +3351,10 @@ DECLARE_INSN(fmadd_d, MATCH_FMADD_D, MASK_FMADD_D)
+ DECLARE_INSN(fmsub_d, MATCH_FMSUB_D, MASK_FMSUB_D)
+ DECLARE_INSN(fnmsub_d, MATCH_FNMSUB_D, MASK_FNMSUB_D)
+ DECLARE_INSN(fnmadd_d, MATCH_FNMADD_D, MASK_FNMADD_D)
++DECLARE_INSN(fmadd_h, MATCH_FMADD_H, MASK_FMADD_H)
++DECLARE_INSN(fmsub_h, MATCH_FMSUB_H, MASK_FMSUB_H)
++DECLARE_INSN(fnmsub_h, MATCH_FNMSUB_H, MASK_FNMSUB_H)
++DECLARE_INSN(fnmadd_h, MATCH_FNMADD_H, MASK_FNMADD_H)
+ DECLARE_INSN(fmadd_q, MATCH_FMADD_Q, MASK_FMADD_Q)
+ DECLARE_INSN(fmsub_q, MATCH_FMSUB_Q, MASK_FMSUB_Q)
+ DECLARE_INSN(fnmsub_q, MATCH_FNMSUB_Q, MASK_FNMSUB_Q)
+diff --git a/include/opcode/riscv.h b/include/opcode/riscv.h
+index 5fd18beb88..31bdcf95a9 100644
+--- a/include/opcode/riscv.h
++++ b/include/opcode/riscv.h
+@@ -378,10 +378,13 @@ enum riscv_insn_class
+    INSN_CLASS_M,
+    INSN_CLASS_F,
+    INSN_CLASS_D,
+-   INSN_CLASS_D_AND_C,
+-   INSN_CLASS_F_AND_C,
+    INSN_CLASS_Q,
+    INSN_CLASS_V,
++   INSN_CLASS_F_AND_C,
++   INSN_CLASS_F_AND_ZFH,
++   INSN_CLASS_D_AND_C,
++   INSN_CLASS_D_AND_ZFH,
++   INSN_CLASS_Q_AND_ZFH,
+    INSN_CLASS_V_AND_F,
+    INSN_CLASS_V_OR_ZVAMO,
+    INSN_CLASS_V_AND_ZVEDIV,
+@@ -551,9 +554,11 @@ enum
+   M_SH,
+   M_SW,
+   M_SD,
++  M_FLH,
+   M_FLW,
+   M_FLD,
+   M_FLQ,
++  M_FSH,
+   M_FSW,
+   M_FSD,
+   M_FSQ,
+diff --git a/opcodes/riscv-opc.c b/opcodes/riscv-opc.c
+index 7499abb7a6..89593ef979 100644
+--- a/opcodes/riscv-opc.c
++++ b/opcodes/riscv-opc.c
+@@ -898,6 +898,71 @@ const struct riscv_opcode riscv_opcodes[] =
+ {"remw",     64, INSN_CLASS_M, "d,s,t",  MATCH_REMW, MASK_REMW, match_opcode, 0 },
+ {"remuw",    64, INSN_CLASS_M, "d,s,t",  MATCH_REMUW, MASK_REMUW, match_opcode, 0 },
+ 
++/* Half-precision floating-point instruction subset */
++{"flh",        0, INSN_CLASS_F_AND_ZFH,   "D,o(s)",  MATCH_FLH, MASK_FLH, match_opcode, INSN_DREF|INSN_2_BYTE },
++{"flh",        0, INSN_CLASS_F_AND_ZFH,   "D,A,s",  0, (int) M_FLH, match_never, INSN_MACRO },
++{"fsh",        0, INSN_CLASS_F_AND_ZFH,   "T,q(s)",  MATCH_FSH, MASK_FSH, match_opcode, INSN_DREF|INSN_2_BYTE },
++{"fsh",        0, INSN_CLASS_F_AND_ZFH,   "T,A,s",  0, (int) M_FSH, match_never, INSN_MACRO },
++{"fmv.h",      0, INSN_CLASS_F_AND_ZFH,   "D,U",  MATCH_FSGNJ_H, MASK_FSGNJ_H, match_rs1_eq_rs2, INSN_ALIAS },
++{"fneg.h",     0, INSN_CLASS_F_AND_ZFH,   "D,U",  MATCH_FSGNJN_H, MASK_FSGNJN_H, match_rs1_eq_rs2, INSN_ALIAS },
++{"fabs.h",     0, INSN_CLASS_F_AND_ZFH,   "D,U",  MATCH_FSGNJX_H, MASK_FSGNJX_H, match_rs1_eq_rs2, INSN_ALIAS },
++{"fsgnj.h",    0, INSN_CLASS_F_AND_ZFH,   "D,S,T",  MATCH_FSGNJ_H, MASK_FSGNJ_H, match_opcode, 0 },
++{"fsgnjn.h",   0, INSN_CLASS_F_AND_ZFH,   "D,S,T",  MATCH_FSGNJN_H, MASK_FSGNJN_H, match_opcode, 0 },
++{"fsgnjx.h",   0, INSN_CLASS_F_AND_ZFH,   "D,S,T",  MATCH_FSGNJX_H, MASK_FSGNJX_H, match_opcode, 0 },
++{"fadd.h",     0, INSN_CLASS_F_AND_ZFH,   "D,S,T",  MATCH_FADD_H | MASK_RM, MASK_FADD_H | MASK_RM, match_opcode, 0 },
++{"fadd.h",     0, INSN_CLASS_F_AND_ZFH,   "D,S,T,m",  MATCH_FADD_H, MASK_FADD_H, match_opcode, 0 },
++{"fsub.h",     0, INSN_CLASS_F_AND_ZFH,   "D,S,T",  MATCH_FSUB_H | MASK_RM, MASK_FSUB_H | MASK_RM, match_opcode, 0 },
++{"fsub.h",     0, INSN_CLASS_F_AND_ZFH,   "D,S,T,m",  MATCH_FSUB_H, MASK_FSUB_H, match_opcode, 0 },
++{"fmul.h",     0, INSN_CLASS_F_AND_ZFH,   "D,S,T",  MATCH_FMUL_H | MASK_RM, MASK_FMUL_H | MASK_RM, match_opcode, 0 },
++{"fmul.h",     0, INSN_CLASS_F_AND_ZFH,   "D,S,T,m",  MATCH_FMUL_H, MASK_FMUL_H, match_opcode, 0 },
++{"fdiv.h",     0, INSN_CLASS_F_AND_ZFH,   "D,S,T",  MATCH_FDIV_H | MASK_RM, MASK_FDIV_H | MASK_RM, match_opcode, 0 },
++{"fdiv.h",     0, INSN_CLASS_F_AND_ZFH,   "D,S,T,m",  MATCH_FDIV_H, MASK_FDIV_H, match_opcode, 0 },
++{"fsqrt.h",    0, INSN_CLASS_F_AND_ZFH,   "D,S",  MATCH_FSQRT_H | MASK_RM, MASK_FSQRT_H | MASK_RM, match_opcode, 0 },
++{"fsqrt.h",    0, INSN_CLASS_F_AND_ZFH,   "D,S,m",  MATCH_FSQRT_H, MASK_FSQRT_H, match_opcode, 0 },
++{"fmin.h",     0, INSN_CLASS_F_AND_ZFH,   "D,S,T",  MATCH_FMIN_H, MASK_FMIN_H, match_opcode, 0 },
++{"fmax.h",     0, INSN_CLASS_F_AND_ZFH,   "D,S,T",  MATCH_FMAX_H, MASK_FMAX_H, match_opcode, 0 },
++{"fmadd.h",    0, INSN_CLASS_F_AND_ZFH,   "D,S,T,R",  MATCH_FMADD_H | MASK_RM, MASK_FMADD_H | MASK_RM, match_opcode, 0 },
++{"fmadd.h",    0, INSN_CLASS_F_AND_ZFH,   "D,S,T,R,m",  MATCH_FMADD_H, MASK_FMADD_H, match_opcode, 0 },
++{"fnmadd.h",   0, INSN_CLASS_F_AND_ZFH,   "D,S,T,R",  MATCH_FNMADD_H | MASK_RM, MASK_FNMADD_H | MASK_RM, match_opcode, 0 },
++{"fnmadd.h",   0, INSN_CLASS_F_AND_ZFH,   "D,S,T,R,m",  MATCH_FNMADD_H, MASK_FNMADD_H, match_opcode, 0 },
++{"fmsub.h",    0, INSN_CLASS_F_AND_ZFH,   "D,S,T,R",  MATCH_FMSUB_H | MASK_RM, MASK_FMSUB_H | MASK_RM, match_opcode, 0 },
++{"fmsub.h",    0, INSN_CLASS_F_AND_ZFH,   "D,S,T,R,m",  MATCH_FMSUB_H, MASK_FMSUB_H, match_opcode, 0 },
++{"fnmsub.h",   0, INSN_CLASS_F_AND_ZFH,   "D,S,T,R",  MATCH_FNMSUB_H | MASK_RM, MASK_FNMSUB_H | MASK_RM, match_opcode, 0 },
++{"fnmsub.h",   0, INSN_CLASS_F_AND_ZFH,   "D,S,T,R,m",  MATCH_FNMSUB_H, MASK_FNMSUB_H, match_opcode, 0 },
++{"fcvt.w.h",   0, INSN_CLASS_F_AND_ZFH,   "d,S",  MATCH_FCVT_W_H | MASK_RM, MASK_FCVT_W_H | MASK_RM, match_opcode, 0 },
++{"fcvt.w.h",   0, INSN_CLASS_F_AND_ZFH,   "d,S,m",  MATCH_FCVT_W_H, MASK_FCVT_W_H, match_opcode, 0 },
++{"fcvt.wu.h",  0, INSN_CLASS_F_AND_ZFH,   "d,S",  MATCH_FCVT_WU_H | MASK_RM, MASK_FCVT_WU_H | MASK_RM, match_opcode, 0 },
++{"fcvt.wu.h",  0, INSN_CLASS_F_AND_ZFH,   "d,S,m",  MATCH_FCVT_WU_H, MASK_FCVT_WU_H, match_opcode, 0 },
++{"fcvt.h.w",   0, INSN_CLASS_F_AND_ZFH,   "D,s",  MATCH_FCVT_H_W | MASK_RM, MASK_FCVT_H_W | MASK_RM, match_opcode, 0 },
++{"fcvt.h.w",   0, INSN_CLASS_F_AND_ZFH,   "D,s,m",  MATCH_FCVT_H_W, MASK_FCVT_H_W, match_opcode, 0 },
++{"fcvt.h.wu",  0, INSN_CLASS_F_AND_ZFH,   "D,s",  MATCH_FCVT_H_WU | MASK_RM, MASK_FCVT_H_WU | MASK_RM, match_opcode, 0 },
++{"fcvt.h.wu",  0, INSN_CLASS_F_AND_ZFH,   "D,s,m",  MATCH_FCVT_H_WU, MASK_FCVT_H_WU, match_opcode, 0 },
++{"fcvt.s.h",   0, INSN_CLASS_F_AND_ZFH,   "D,S",  MATCH_FCVT_S_H, MASK_FCVT_S_H | MASK_RM, match_opcode, 0 },
++{"fcvt.d.h",   0, INSN_CLASS_D_AND_ZFH,   "D,S",  MATCH_FCVT_D_H, MASK_FCVT_D_H | MASK_RM, match_opcode, 0 },
++{"fcvt.q.h",   0, INSN_CLASS_Q_AND_ZFH,   "D,S",  MATCH_FCVT_Q_H, MASK_FCVT_Q_H | MASK_RM, match_opcode, 0 },
++{"fcvt.h.s",   0, INSN_CLASS_F_AND_ZFH,   "D,S",  MATCH_FCVT_H_S | MASK_RM, MASK_FCVT_H_S | MASK_RM, match_opcode, 0 },
++{"fcvt.h.s",   0, INSN_CLASS_F_AND_ZFH,   "D,S,m",  MATCH_FCVT_H_S, MASK_FCVT_H_S, match_opcode, 0 },
++{"fcvt.h.d",   0, INSN_CLASS_D_AND_ZFH,   "D,S",  MATCH_FCVT_H_D | MASK_RM, MASK_FCVT_H_D | MASK_RM, match_opcode, 0 },
++{"fcvt.h.d",   0, INSN_CLASS_D_AND_ZFH,   "D,S,m",  MATCH_FCVT_H_D, MASK_FCVT_H_D, match_opcode, 0 },
++{"fcvt.h.q",   0, INSN_CLASS_Q_AND_ZFH,   "D,S",  MATCH_FCVT_H_Q | MASK_RM, MASK_FCVT_H_Q | MASK_RM, match_opcode, 0 },
++{"fcvt.h.q",   0, INSN_CLASS_Q_AND_ZFH,   "D,S,m",  MATCH_FCVT_H_Q, MASK_FCVT_H_Q, match_opcode, 0 },
++{"fclass.h",   0, INSN_CLASS_F_AND_ZFH,   "d,S",  MATCH_FCLASS_H, MASK_FCLASS_H, match_opcode, 0 },
++{"feq.h",      0, INSN_CLASS_F_AND_ZFH,   "d,S,T",  MATCH_FEQ_H, MASK_FEQ_H, match_opcode, 0 },
++{"flt.h",      0, INSN_CLASS_F_AND_ZFH,   "d,S,T",  MATCH_FLT_H, MASK_FLT_H, match_opcode, 0 },
++{"fle.h",      0, INSN_CLASS_F_AND_ZFH,   "d,S,T",  MATCH_FLE_H, MASK_FLE_H, match_opcode, 0 },
++{"fgt.h",      0, INSN_CLASS_F_AND_ZFH,   "d,T,S",  MATCH_FLT_H, MASK_FLT_H, match_opcode, 0 },
++{"fge.h",      0, INSN_CLASS_F_AND_ZFH,   "d,T,S",  MATCH_FLE_H, MASK_FLE_H, match_opcode, 0 },
++{"fmv.x.h",    0, INSN_CLASS_F_AND_ZFH,   "d,S",  MATCH_FMV_X_H, MASK_FMV_X_H, match_opcode, 0 },
++{"fmv.h.x",    0, INSN_CLASS_F_AND_ZFH,   "D,s",  MATCH_FMV_H_X, MASK_FMV_H_X, match_opcode, 0 },
++{"fcvt.l.h",  64, INSN_CLASS_F_AND_ZFH,   "d,S",  MATCH_FCVT_L_H | MASK_RM, MASK_FCVT_L_H | MASK_RM, match_opcode, 0 },
++{"fcvt.l.h",  64, INSN_CLASS_F_AND_ZFH,   "d,S,m",  MATCH_FCVT_L_H, MASK_FCVT_L_H, match_opcode, 0 },
++{"fcvt.lu.h", 64, INSN_CLASS_F_AND_ZFH,   "d,S",  MATCH_FCVT_LU_H | MASK_RM, MASK_FCVT_LU_H | MASK_RM, match_opcode, 0 },
++{"fcvt.lu.h", 64, INSN_CLASS_F_AND_ZFH,   "d,S,m",  MATCH_FCVT_LU_H, MASK_FCVT_LU_H, match_opcode, 0 },
++{"fcvt.h.l",  64, INSN_CLASS_F_AND_ZFH,   "D,s",  MATCH_FCVT_H_L | MASK_RM, MASK_FCVT_H_L | MASK_RM, match_opcode, 0 },
++{"fcvt.h.l",  64, INSN_CLASS_F_AND_ZFH,   "D,s,m",  MATCH_FCVT_H_L, MASK_FCVT_H_L, match_opcode, 0 },
++{"fcvt.h.lu", 64, INSN_CLASS_F_AND_ZFH,   "D,s",  MATCH_FCVT_H_LU | MASK_RM, MASK_FCVT_H_L | MASK_RM, match_opcode, 0 },
++{"fcvt.h.lu", 64, INSN_CLASS_F_AND_ZFH,   "D,s,m",  MATCH_FCVT_H_LU, MASK_FCVT_H_LU, match_opcode, 0 },
++
+ /* Single-precision floating-point instruction subset */
+ {"frcsr",     0, INSN_CLASS_F,   "d",  MATCH_FRCSR, MASK_FRCSR, match_opcode, INSN_ALIAS },
+ {"frsr",      0, INSN_CLASS_F,   "d",  MATCH_FRCSR, MASK_FRCSR, match_opcode, INSN_ALIAS },
+-- 
+2.33.0
+

+ 97 - 0
recipes-devtools/gdb/files/0029-RISC-V-Support-.float16-directive-for-assembler.patch

@@ -0,0 +1,97 @@
+From d1f2bc0a3f745ba7f49d2576300c7c000c5728ef Mon Sep 17 00:00:00 2001
+From: Nelson Chu <nelson.chu@sifive.com>
+Date: Tue, 21 Apr 2020 14:42:20 +0800
+Subject: [PATCH 29/48] RISC-V: Support .float16 directive for assembler.
+
+---
+ gas/config/tc-riscv.c             |  3 ++-
+ gas/read.c                        |  5 +++++
+ gas/testsuite/gas/riscv/float16.d | 10 ++++++++++
+ gas/testsuite/gas/riscv/float16.s | 21 +++++++++++++++++++++
+ 4 files changed, 38 insertions(+), 1 deletion(-)
+ create mode 100644 gas/testsuite/gas/riscv/float16.d
+ create mode 100644 gas/testsuite/gas/riscv/float16.s
+
+diff --git a/gas/config/tc-riscv.c b/gas/config/tc-riscv.c
+index bb2819db4a..57d2908fcd 100644
+--- a/gas/config/tc-riscv.c
++++ b/gas/config/tc-riscv.c
+@@ -362,7 +362,7 @@ const char EXP_CHARS[] = "eE";
+ /* Chars that mean this number is a floating point constant */
+ /* As in 0f12.456 */
+ /* or    0d1.2345e12 */
+-const char FLT_CHARS[] = "rRsSfFdDxXpP";
++const char FLT_CHARS[] = "rRsSfFdDxXpPhH";
+ 
+ /* Indicate we are already assemble any instructions or not.  */
+ static bfd_boolean start_assemble = FALSE;
+@@ -4182,6 +4182,7 @@ static const pseudo_typeS riscv_pseudo_table[] =
+   {"sleb128", s_riscv_leb128, 1},
+   {"insn", s_riscv_insn, 0},
+   {"attribute", s_riscv_attribute, 0},
++  {"float16", float_cons, 'h'},
+ 
+   { NULL, NULL, 0 },
+ };
+diff --git a/gas/read.c b/gas/read.c
+index cd06ea51d9..c549629268 100644
+--- a/gas/read.c
++++ b/gas/read.c
+@@ -4763,6 +4763,11 @@ hex_float (int float_type, char *bytes)
+ 
+   switch (float_type)
+     {
++    case 'h':
++    case 'H':
++      length = 2;
++      break;
++
+     case 'f':
+     case 'F':
+     case 's':
+diff --git a/gas/testsuite/gas/riscv/float16.d b/gas/testsuite/gas/riscv/float16.d
+new file mode 100644
+index 0000000000..e75971d941
+--- /dev/null
++++ b/gas/testsuite/gas/riscv/float16.d
+@@ -0,0 +1,10 @@
++# source: float16.s
++# objdump: -sj .data
++# as:
++
++.*:[ 	]+file format .*
++
++Contents of section \.data:
++ 0000 004adf2f 191cff7b 0100ff03 0004003c.*
++ 0010 013cff7f 007c00fc 00000080 00bce7bb.*
++ 0020 fffb0042 004a3e60 007e017e.*
+diff --git a/gas/testsuite/gas/riscv/float16.s b/gas/testsuite/gas/riscv/float16.s
+new file mode 100644
+index 0000000000..709ea0af7c
+--- /dev/null
++++ b/gas/testsuite/gas/riscv/float16.s
+@@ -0,0 +1,21 @@
++.data
++	.float16 12.0
++	.float16 0.123
++	.float16 0.004
++	.float16 65504
++	.float16 5.9605e-8
++	.float16 6.0976e-5
++	.float16 6.1035e-5
++	.float16 1
++	.float16 1.001
++	.float16 NaN
++	.float16 +Inf
++	.float16 -Inf
++	.float16 +0
++	.float16 -0
++	.float16 -1
++	.float16 -0.98765
++	.float16 -65504
++	.float16 3.0, 12.0, 543.123
++	.float16 0h:7e00	# qNaNh
++	.float16 0h:7e01	# sNaNh
+-- 
+2.33.0
+

+ 25 - 0
recipes-devtools/gdb/files/0030-Set-default-version-of-ZFH-to-0.1.patch

@@ -0,0 +1,25 @@
+From 40f63189157ba812686d572b8ec5e177fd40ed10 Mon Sep 17 00:00:00 2001
+From: Kito Cheng <kito.cheng@sifive.com>
+Date: Thu, 20 Aug 2020 14:25:29 +0800
+Subject: [PATCH 30/48] Set default version of ZFH to 0.1
+
+---
+ opcodes/riscv-opc.c | 2 ++
+ 1 file changed, 2 insertions(+)
+
+diff --git a/opcodes/riscv-opc.c b/opcodes/riscv-opc.c
+index 89593ef979..af3d787fe6 100644
+--- a/opcodes/riscv-opc.c
++++ b/opcodes/riscv-opc.c
+@@ -2397,6 +2397,8 @@ const struct riscv_ext_version riscv_ext_version_table[] =
+ {"zifencei", ISA_SPEC_CLASS_20191213, 2, 0},
+ {"zifencei", ISA_SPEC_CLASS_20190608, 2, 0},
+ 
++{"zfh", ISA_SPEC_CLASS_NONE, 0, 1},
++
+ {"zvamo",   ISA_SPEC_CLASS_NONE, 1, 0},
+ {"zvediv",  ISA_SPEC_CLASS_NONE, 1, 0},
+ {"zvlsseg", ISA_SPEC_CLASS_NONE, 1, 0},
+-- 
+2.33.0
+

+ 166 - 0
recipes-devtools/gdb/files/0031-RISC-V-Add-assembly-pseudoinstructions-vneg.v-and-vf.patch

@@ -0,0 +1,166 @@
+From 786771070f564a133c536e05939eb51b546dc02d Mon Sep 17 00:00:00 2001
+From: Nelson Chu <nelson.chu@sifive.com>
+Date: Mon, 23 Nov 2020 11:34:34 +0800
+Subject: [PATCH 31/48] RISC-V: Add assembly pseudoinstructions, vneg.v and
+ vfneg.v.
+
+vneg.v vd,vs = vrsub.vx vd,vs,x0
+vfneg.v vd,vs = vfsgnjn.vv vd,vs,vs
+---
+ .../riscv/vector-insns-fail-arith-floatp.l    |  1 +
+ .../riscv/vector-insns-fail-arith-floatp.s    |  3 +++
+ .../gas/riscv/vector-insns-fail-arith-int.l   |  1 +
+ .../gas/riscv/vector-insns-fail-arith-int.s   |  3 +++
+ gas/testsuite/gas/riscv/vector-insns.d        |  4 +++
+ gas/testsuite/gas/riscv/vector-insns.s        |  6 +++++
+ opcodes/riscv-opc.c                           | 25 +++++++++++++++++++
+ 7 files changed, 43 insertions(+)
+
+diff --git a/gas/testsuite/gas/riscv/vector-insns-fail-arith-floatp.l b/gas/testsuite/gas/riscv/vector-insns-fail-arith-floatp.l
+index c55c7d24cd..bcc49a0908 100644
+--- a/gas/testsuite/gas/riscv/vector-insns-fail-arith-floatp.l
++++ b/gas/testsuite/gas/riscv/vector-insns-fail-arith-floatp.l
+@@ -33,6 +33,7 @@
+ .*Error: illegal operands vd cannot overlap vm `vfmin.vf v0,v4,fa1,v0.t'
+ .*Error: illegal operands vd cannot overlap vm `vfmax.vv v0,v4,v8,v0.t'
+ .*Error: illegal operands vd cannot overlap vm `vfmax.vf v0,v4,fa1,v0.t'
++.*Error: illegal operands vd cannot overlap vm `vfneg.v v0,v4,v0.t'
+ .*Error: illegal operands vd cannot overlap vm `vfsgnj.vv v0,v4,v8,v0.t'
+ .*Error: illegal operands vd cannot overlap vm `vfsgnj.vf v0,v4,fa1,v0.t'
+ .*Error: illegal operands vd cannot overlap vm `vfsgnjn.vv v0,v4,v8,v0.t'
+diff --git a/gas/testsuite/gas/riscv/vector-insns-fail-arith-floatp.s b/gas/testsuite/gas/riscv/vector-insns-fail-arith-floatp.s
+index 3231c35ada..a48b1a3fd3 100644
+--- a/gas/testsuite/gas/riscv/vector-insns-fail-arith-floatp.s
++++ b/gas/testsuite/gas/riscv/vector-insns-fail-arith-floatp.s
+@@ -118,6 +118,9 @@
+ 
+ # Vector Floating-Point Sign-Injection Instructions
+ 
++	vfneg.v v4, v4			# OK
++	vfneg.v v0, v4, v0.t		# vd overlap vm
++
+ 	vfsgnj.vv v4, v4, v8		# OK
+ 	vfsgnj.vv v8, v4, v8		# OK
+ 	vfsgnj.vv v0, v4, v8, v0.t	# vd overlap vm
+diff --git a/gas/testsuite/gas/riscv/vector-insns-fail-arith-int.l b/gas/testsuite/gas/riscv/vector-insns-fail-arith-int.l
+index 3b1d780fa4..5c9016dd4c 100644
+--- a/gas/testsuite/gas/riscv/vector-insns-fail-arith-int.l
++++ b/gas/testsuite/gas/riscv/vector-insns-fail-arith-int.l
+@@ -1,4 +1,5 @@
+ .*: Assembler messages:
++.*Error: illegal operands vd cannot overlap vm `vneg.v v0,v4,v0.t'
+ .*Error: illegal operands vd cannot overlap vm `vadd.vv v0,v4,v8,v0.t'
+ .*Error: illegal operands vd cannot overlap vm `vadd.vx v0,v4,a1,v0.t'
+ .*Error: illegal operands vd cannot overlap vm `vadd.vi v0,v4,15,v0.t'
+diff --git a/gas/testsuite/gas/riscv/vector-insns-fail-arith-int.s b/gas/testsuite/gas/riscv/vector-insns-fail-arith-int.s
+index e014125c29..6ce4e420c7 100644
+--- a/gas/testsuite/gas/riscv/vector-insns-fail-arith-int.s
++++ b/gas/testsuite/gas/riscv/vector-insns-fail-arith-int.s
+@@ -1,5 +1,8 @@
+ # Vector Single-Width Integer Add and Subtract
+ 
++	vneg.v v4, v4			# OK
++	vneg.v v0, v4, v0.t		# vd overlap vm
++
+ 	vadd.vv v4, v4, v8		# OK
+ 	vadd.vv v8, v4, v8		# OK
+ 	vadd.vv v0, v4, v8, v0.t	# vd overlap vm
+diff --git a/gas/testsuite/gas/riscv/vector-insns.d b/gas/testsuite/gas/riscv/vector-insns.d
+index 24a559cee5..29a38b3716 100644
+--- a/gas/testsuite/gas/riscv/vector-insns.d
++++ b/gas/testsuite/gas/riscv/vector-insns.d
+@@ -1726,6 +1726,8 @@ Disassembly of section .text:
+ [ 	]+[0-9a-f]+:[ 	]+e285f22f[ 	]+vamomaxuei64.v[ 	]+zero,\(a1\),v8,v4
+ [ 	]+[0-9a-f]+:[ 	]+e485f22f[ 	]+vamomaxuei64.v[ 	]+v4,\(a1\),v8,v4,v0.t
+ [ 	]+[0-9a-f]+:[ 	]+e085f22f[ 	]+vamomaxuei64.v[ 	]+zero,\(a1\),v8,v4,v0.t
++[ 	]+[0-9a-f]+:[ 	]+0e804257[ 	]+vneg.v[ 	]+v4,v8
++[ 	]+[0-9a-f]+:[ 	]+0c804257[ 	]+vneg.v[ 	]+v4,v8,v0.t
+ [ 	]+[0-9a-f]+:[ 	]+02860257[ 	]+vadd.vv[ 	]+v4,v8,v12
+ [ 	]+[0-9a-f]+:[ 	]+0285c257[ 	]+vadd.vx[ 	]+v4,v8,a1
+ [ 	]+[0-9a-f]+:[ 	]+0287b257[ 	]+vadd.vi[ 	]+v4,v8,15
+@@ -2246,6 +2248,8 @@ Disassembly of section .text:
+ [ 	]+[0-9a-f]+:[ 	]+10865257[ 	]+vfmin.vf[ 	]+v4,v8,fa2,v0.t
+ [ 	]+[0-9a-f]+:[ 	]+18861257[ 	]+vfmax.vv[ 	]+v4,v8,v12,v0.t
+ [ 	]+[0-9a-f]+:[ 	]+18865257[ 	]+vfmax.vf[ 	]+v4,v8,fa2,v0.t
++[ 	]+[0-9a-f]+:[ 	]+26841257[ 	]+vfneg.v[ 	]+v4,v8
++[ 	]+[0-9a-f]+:[ 	]+24841257[ 	]+vfneg.v[ 	]+v4,v8,v0.t
+ [ 	]+[0-9a-f]+:[ 	]+22861257[ 	]+vfsgnj.vv[ 	]+v4,v8,v12
+ [ 	]+[0-9a-f]+:[ 	]+22865257[ 	]+vfsgnj.vf[ 	]+v4,v8,fa2
+ [ 	]+[0-9a-f]+:[ 	]+26861257[ 	]+vfsgnjn.vv[ 	]+v4,v8,v12
+diff --git a/gas/testsuite/gas/riscv/vector-insns.s b/gas/testsuite/gas/riscv/vector-insns.s
+index afec58c03b..b78604025a 100644
+--- a/gas/testsuite/gas/riscv/vector-insns.s
++++ b/gas/testsuite/gas/riscv/vector-insns.s
+@@ -1999,6 +1999,9 @@
+ 	vamomaxuei64.v v4, 0(a1), v8, v4, v0.t
+ 	vamomaxuei64.v x0, 0(a1), v8, v4, v0.t
+ 
++	vneg.v v4, v8
++	vneg.v v4, v8, v0.t
++
+ 	vadd.vv v4, v8, v12
+ 	vadd.vx v4, v8, a1
+ 	vadd.vi v4, v8, 15
+@@ -2557,6 +2560,9 @@
+ 	vfmax.vv v4, v8, v12, v0.t
+ 	vfmax.vf v4, v8, fa2, v0.t
+ 
++	vfneg.v v4, v8
++	vfneg.v v4, v8, v0.t
++
+ 	vfsgnj.vv v4, v8, v12
+ 	vfsgnj.vf v4, v8, fa2
+ 	vfsgnjn.vv v4, v8, v12
+diff --git a/opcodes/riscv-opc.c b/opcodes/riscv-opc.c
+index af3d787fe6..e0383d08e9 100644
+--- a/opcodes/riscv-opc.c
++++ b/opcodes/riscv-opc.c
+@@ -138,6 +138,27 @@ match_vs1_eq_vs2 (const struct riscv_opcode *op,
+   return match_opcode (op, insn, 0, NULL) && vs1 == vs2;
+ }
+ 
++static int
++match_vs1_eq_vs2_neq_vm (const struct riscv_opcode *op,
++			 insn_t insn,
++			 int constraints,
++			 const char **error)
++{
++  int vd = (insn & MASK_VD) >> OP_SH_VD;
++  int vs1 = (insn & MASK_VS1) >> OP_SH_VS1;
++  int vs2 = (insn & MASK_VS2) >> OP_SH_VS2;
++  int vm = (insn & MASK_VMASK) >> OP_SH_VMASK;
++
++  if (!constraints || error == NULL)
++    return match_opcode (op, insn, 0, NULL) && vs1 == vs2;
++
++  if (!vm && vm == vd)
++    *error = "illegal operands vd cannot overlap vm";
++  else
++    return match_opcode (op, insn, 0, NULL) && vs1 == vs2;
++  return 0;
++}
++
+ static int
+ match_vd_eq_vs1_eq_vs2 (const struct riscv_opcode *op,
+ 			insn_t insn,
+@@ -1819,6 +1840,8 @@ const struct riscv_opcode riscv_opcodes[] =
+ {"vamominuei64.v",  0, INSN_CLASS_V_OR_ZVAMO,  "Ve,0(s),Vt,VfVm", MATCH_VAMOMINUEI64V, MASK_VAMOMINUEI64V, match_vd_neq_vm, INSN_DREF},
+ {"vamomaxuei64.v",  0, INSN_CLASS_V_OR_ZVAMO,  "Ve,0(s),Vt,VfVm", MATCH_VAMOMAXUEI64V, MASK_VAMOMAXUEI64V, match_vd_neq_vm, INSN_DREF},
+ 
++{"vneg.v",     0, INSN_CLASS_V,  "Vd,VtVm",  MATCH_VRSUBVX, MASK_VRSUBVX | MASK_RS1, match_vd_neq_vm, INSN_ALIAS },
++
+ {"vadd.vv",    0, INSN_CLASS_V,  "Vd,Vt,VsVm", MATCH_VADDVV, MASK_VADDVV, match_vd_neq_vm, 0 },
+ {"vadd.vx",    0, INSN_CLASS_V,  "Vd,Vt,sVm", MATCH_VADDVX, MASK_VADDVX, match_vd_neq_vm, 0 },
+ {"vadd.vi",    0, INSN_CLASS_V,  "Vd,Vt,ViVm", MATCH_VADDVI, MASK_VADDVI, match_vd_neq_vm, 0 },
+@@ -2103,6 +2126,8 @@ const struct riscv_opcode riscv_opcodes[] =
+ {"vfmax.vv",   0, INSN_CLASS_V_AND_F, "Vd,Vt,VsVm", MATCH_VFMAXVV, MASK_VFMAXVV, match_vd_neq_vm, 0},
+ {"vfmax.vf",   0, INSN_CLASS_V_AND_F, "Vd,Vt,SVm", MATCH_VFMAXVF, MASK_VFMAXVF, match_vd_neq_vm, 0},
+ 
++{"vfneg.v",    0, INSN_CLASS_V_AND_F, "Vd,VuVm", MATCH_VFSGNJNVV, MASK_VFSGNJNVV, match_vs1_eq_vs2_neq_vm, INSN_ALIAS },
++
+ {"vfsgnj.vv",  0, INSN_CLASS_V_AND_F, "Vd,Vt,VsVm", MATCH_VFSGNJVV, MASK_VFSGNJVV, match_vd_neq_vm, 0},
+ {"vfsgnj.vf",  0, INSN_CLASS_V_AND_F, "Vd,Vt,SVm", MATCH_VFSGNJVF, MASK_VFSGNJVF, match_vd_neq_vm, 0},
+ {"vfsgnjn.vv", 0, INSN_CLASS_V_AND_F, "Vd,Vt,VsVm", MATCH_VFSGNJNVV, MASK_VFSGNJNVV, match_vd_neq_vm, 0},
+-- 
+2.33.0
+

+ 5057 - 0
recipes-devtools/gdb/files/0032-RISC-V-Added-ordered-unordered-vector-indexed-instru.patch

@@ -0,0 +1,5057 @@
+From 0b3aaf2a0ee9650beec58c39ce6fb248f4bd6a81 Mon Sep 17 00:00:00 2001
+From: Nelson Chu <nelson.chu@sifive.com>
+Date: Mon, 23 Nov 2020 13:32:07 +0800
+Subject: [PATCH 32/48] RISC-V: Added ordered/unordered vector indexed
+ instructions.
+
+The mop field 01 is indexed-unordered LOAD/STORE; and 11 is indexed-ordered
+LOAD/STORE.  Both vector indexed and vector indexed segment are need to
+support.
+---
+ .../gas/riscv/vector-insns-fail-load-store.l  |  692 +++++----
+ .../gas/riscv/vector-insns-fail-load-store.s  |  749 ++++++----
+ gas/testsuite/gas/riscv/vector-insns.d        | 1068 +++++++++-----
+ gas/testsuite/gas/riscv/vector-insns.s        | 1234 +++++++++++------
+ include/opcode/riscv-opc.h                    |  758 ++++++----
+ opcodes/riscv-opc.c                           |  379 +++--
+ 6 files changed, 3237 insertions(+), 1643 deletions(-)
+
+diff --git a/gas/testsuite/gas/riscv/vector-insns-fail-load-store.l b/gas/testsuite/gas/riscv/vector-insns-fail-load-store.l
+index 3e2a24390b..6de77bff4a 100644
+--- a/gas/testsuite/gas/riscv/vector-insns-fail-load-store.l
++++ b/gas/testsuite/gas/riscv/vector-insns-fail-load-store.l
+@@ -39,14 +39,18 @@
+ .*Error: illegal operands vd cannot overlap vm `vsse256.v v0,\(a0\),a1,v0.t'
+ .*Error: illegal operands vd cannot overlap vm `vsse512.v v0,\(a0\),a1,v0.t'
+ .*Error: illegal operands vd cannot overlap vm `vsse1024.v v0,\(a0\),a1,v0.t'
+-.*Error: illegal operands vd cannot overlap vm `vlxei8.v v0,\(a0\),v4,v0.t'
+-.*Error: illegal operands vd cannot overlap vm `vlxei16.v v0,\(a0\),v4,v0.t'
+-.*Error: illegal operands vd cannot overlap vm `vlxei32.v v0,\(a0\),v4,v0.t'
+-.*Error: illegal operands vd cannot overlap vm `vlxei64.v v0,\(a0\),v4,v0.t'
+-.*Error: illegal operands vd cannot overlap vm `vsxei8.v v0,\(a0\),v4,v0.t'
+-.*Error: illegal operands vd cannot overlap vm `vsxei16.v v0,\(a0\),v4,v0.t'
+-.*Error: illegal operands vd cannot overlap vm `vsxei32.v v0,\(a0\),v4,v0.t'
+-.*Error: illegal operands vd cannot overlap vm `vsxei64.v v0,\(a0\),v4,v0.t'
++.*Error: illegal operands vd cannot overlap vm `vloxei8.v v0,\(a0\),v4,v0.t'
++.*Error: illegal operands vd cannot overlap vm `vloxei16.v v0,\(a0\),v4,v0.t'
++.*Error: illegal operands vd cannot overlap vm `vloxei32.v v0,\(a0\),v4,v0.t'
++.*Error: illegal operands vd cannot overlap vm `vloxei64.v v0,\(a0\),v4,v0.t'
++.*Error: illegal operands vd cannot overlap vm `vsoxei8.v v0,\(a0\),v4,v0.t'
++.*Error: illegal operands vd cannot overlap vm `vsoxei16.v v0,\(a0\),v4,v0.t'
++.*Error: illegal operands vd cannot overlap vm `vsoxei32.v v0,\(a0\),v4,v0.t'
++.*Error: illegal operands vd cannot overlap vm `vsoxei64.v v0,\(a0\),v4,v0.t'
++.*Error: illegal operands vd cannot overlap vm `vluxei8.v v0,\(a0\),v4,v0.t'
++.*Error: illegal operands vd cannot overlap vm `vluxei16.v v0,\(a0\),v4,v0.t'
++.*Error: illegal operands vd cannot overlap vm `vluxei32.v v0,\(a0\),v4,v0.t'
++.*Error: illegal operands vd cannot overlap vm `vluxei64.v v0,\(a0\),v4,v0.t'
+ .*Error: illegal operands vd cannot overlap vm `vsuxei8.v v0,\(a0\),v4,v0.t'
+ .*Error: illegal operands vd cannot overlap vm `vsuxei16.v v0,\(a0\),v4,v0.t'
+ .*Error: illegal operands vd cannot overlap vm `vsuxei32.v v0,\(a0\),v4,v0.t'
+@@ -331,230 +335,454 @@
+ .*Error: illegal operands vd cannot overlap vm `vssseg7e1024.v v0,\(a0\),a1,v0.t'
+ .*Error: illegal operands vd cannot overlap vm `vlsseg8e1024.v v0,\(a0\),a1,v0.t'
+ .*Error: illegal operands vd cannot overlap vm `vssseg8e1024.v v0,\(a0\),a1,v0.t'
+-.*Error: illegal operands vd cannot overlap vs2 `vlxseg2ei8.v v4,\(a0\),v4'
+-.*Error: illegal operands vd cannot overlap vm `vlxseg2ei8.v v0,\(a0\),v4,v0.t'
+-.*Error: illegal operands vd cannot overlap vs2 `vsxseg2ei8.v v4,\(a0\),v4'
+-.*Error: illegal operands vd cannot overlap vm `vsxseg2ei8.v v0,\(a0\),v4,v0.t'
+-.*Error: illegal operands vd cannot overlap vs2 `vlxseg3ei8.v v4,\(a0\),v4'
+-.*Error: illegal operands vd cannot overlap vm `vlxseg3ei8.v v0,\(a0\),v4,v0.t'
+-.*Error: illegal operands vd cannot overlap vs2 `vsxseg3ei8.v v4,\(a0\),v4'
+-.*Error: illegal operands vd cannot overlap vm `vsxseg3ei8.v v0,\(a0\),v4,v0.t'
+-.*Error: illegal operands vd cannot overlap vs2 `vlxseg4ei8.v v4,\(a0\),v4'
+-.*Error: illegal operands vd cannot overlap vm `vlxseg4ei8.v v0,\(a0\),v4,v0.t'
+-.*Error: illegal operands vd cannot overlap vs2 `vsxseg4ei8.v v4,\(a0\),v4'
+-.*Error: illegal operands vd cannot overlap vm `vsxseg4ei8.v v0,\(a0\),v4,v0.t'
+-.*Error: illegal operands vd cannot overlap vs2 `vlxseg5ei8.v v4,\(a0\),v4'
+-.*Error: illegal operands vd cannot overlap vm `vlxseg5ei8.v v0,\(a0\),v4,v0.t'
+-.*Error: illegal operands vd cannot overlap vs2 `vsxseg5ei8.v v4,\(a0\),v4'
+-.*Error: illegal operands vd cannot overlap vm `vsxseg5ei8.v v0,\(a0\),v4,v0.t'
+-.*Error: illegal operands vd cannot overlap vs2 `vlxseg6ei8.v v4,\(a0\),v4'
+-.*Error: illegal operands vd cannot overlap vm `vlxseg6ei8.v v0,\(a0\),v4,v0.t'
+-.*Error: illegal operands vd cannot overlap vs2 `vsxseg6ei8.v v4,\(a0\),v4'
+-.*Error: illegal operands vd cannot overlap vm `vsxseg6ei8.v v0,\(a0\),v4,v0.t'
+-.*Error: illegal operands vd cannot overlap vs2 `vlxseg7ei8.v v4,\(a0\),v4'
+-.*Error: illegal operands vd cannot overlap vm `vlxseg7ei8.v v0,\(a0\),v4,v0.t'
+-.*Error: illegal operands vd cannot overlap vs2 `vsxseg7ei8.v v4,\(a0\),v4'
+-.*Error: illegal operands vd cannot overlap vm `vsxseg7ei8.v v0,\(a0\),v4,v0.t'
+-.*Error: illegal operands vd cannot overlap vs2 `vlxseg8ei8.v v4,\(a0\),v4'
+-.*Error: illegal operands vd cannot overlap vm `vlxseg8ei8.v v0,\(a0\),v4,v0.t'
+-.*Error: illegal operands vd cannot overlap vs2 `vsxseg8ei8.v v4,\(a0\),v4'
+-.*Error: illegal operands vd cannot overlap vm `vsxseg8ei8.v v0,\(a0\),v4,v0.t'
+-.*Error: illegal operands vd cannot overlap vs2 `vlxseg2ei16.v v4,\(a0\),v4'
+-.*Error: illegal operands vd cannot overlap vm `vlxseg2ei16.v v0,\(a0\),v4,v0.t'
+-.*Error: illegal operands vd cannot overlap vs2 `vsxseg2ei16.v v4,\(a0\),v4'
+-.*Error: illegal operands vd cannot overlap vm `vsxseg2ei16.v v0,\(a0\),v4,v0.t'
+-.*Error: illegal operands vd cannot overlap vs2 `vlxseg3ei16.v v4,\(a0\),v4'
+-.*Error: illegal operands vd cannot overlap vm `vlxseg3ei16.v v0,\(a0\),v4,v0.t'
+-.*Error: illegal operands vd cannot overlap vs2 `vsxseg3ei16.v v4,\(a0\),v4'
+-.*Error: illegal operands vd cannot overlap vm `vsxseg3ei16.v v0,\(a0\),v4,v0.t'
+-.*Error: illegal operands vd cannot overlap vs2 `vlxseg4ei16.v v4,\(a0\),v4'
+-.*Error: illegal operands vd cannot overlap vm `vlxseg4ei16.v v0,\(a0\),v4,v0.t'
+-.*Error: illegal operands vd cannot overlap vs2 `vsxseg4ei16.v v4,\(a0\),v4'
+-.*Error: illegal operands vd cannot overlap vm `vsxseg4ei16.v v0,\(a0\),v4,v0.t'
+-.*Error: illegal operands vd cannot overlap vs2 `vlxseg5ei16.v v4,\(a0\),v4'
+-.*Error: illegal operands vd cannot overlap vm `vlxseg5ei16.v v0,\(a0\),v4,v0.t'
+-.*Error: illegal operands vd cannot overlap vs2 `vsxseg5ei16.v v4,\(a0\),v4'
+-.*Error: illegal operands vd cannot overlap vm `vsxseg5ei16.v v0,\(a0\),v4,v0.t'
+-.*Error: illegal operands vd cannot overlap vs2 `vlxseg6ei16.v v4,\(a0\),v4'
+-.*Error: illegal operands vd cannot overlap vm `vlxseg6ei16.v v0,\(a0\),v4,v0.t'
+-.*Error: illegal operands vd cannot overlap vs2 `vsxseg6ei16.v v4,\(a0\),v4'
+-.*Error: illegal operands vd cannot overlap vm `vsxseg6ei16.v v0,\(a0\),v4,v0.t'
+-.*Error: illegal operands vd cannot overlap vs2 `vlxseg7ei16.v v4,\(a0\),v4'
+-.*Error: illegal operands vd cannot overlap vm `vlxseg7ei16.v v0,\(a0\),v4,v0.t'
+-.*Error: illegal operands vd cannot overlap vs2 `vsxseg7ei16.v v4,\(a0\),v4'
+-.*Error: illegal operands vd cannot overlap vm `vsxseg7ei16.v v0,\(a0\),v4,v0.t'
+-.*Error: illegal operands vd cannot overlap vs2 `vlxseg8ei16.v v4,\(a0\),v4'
+-.*Error: illegal operands vd cannot overlap vm `vlxseg8ei16.v v0,\(a0\),v4,v0.t'
+-.*Error: illegal operands vd cannot overlap vs2 `vsxseg8ei16.v v4,\(a0\),v4'
+-.*Error: illegal operands vd cannot overlap vm `vsxseg8ei16.v v0,\(a0\),v4,v0.t'
+-.*Error: illegal operands vd cannot overlap vs2 `vlxseg2ei32.v v4,\(a0\),v4'
+-.*Error: illegal operands vd cannot overlap vm `vlxseg2ei32.v v0,\(a0\),v4,v0.t'
+-.*Error: illegal operands vd cannot overlap vs2 `vsxseg2ei32.v v4,\(a0\),v4'
+-.*Error: illegal operands vd cannot overlap vm `vsxseg2ei32.v v0,\(a0\),v4,v0.t'
+-.*Error: illegal operands vd cannot overlap vs2 `vlxseg3ei32.v v4,\(a0\),v4'
+-.*Error: illegal operands vd cannot overlap vm `vlxseg3ei32.v v0,\(a0\),v4,v0.t'
+-.*Error: illegal operands vd cannot overlap vs2 `vsxseg3ei32.v v4,\(a0\),v4'
+-.*Error: illegal operands vd cannot overlap vm `vsxseg3ei32.v v0,\(a0\),v4,v0.t'
+-.*Error: illegal operands vd cannot overlap vs2 `vlxseg4ei32.v v4,\(a0\),v4'
+-.*Error: illegal operands vd cannot overlap vm `vlxseg4ei32.v v0,\(a0\),v4,v0.t'
+-.*Error: illegal operands vd cannot overlap vs2 `vsxseg4ei32.v v4,\(a0\),v4'
+-.*Error: illegal operands vd cannot overlap vm `vsxseg4ei32.v v0,\(a0\),v4,v0.t'
+-.*Error: illegal operands vd cannot overlap vs2 `vlxseg5ei32.v v4,\(a0\),v4'
+-.*Error: illegal operands vd cannot overlap vm `vlxseg5ei32.v v0,\(a0\),v4,v0.t'
+-.*Error: illegal operands vd cannot overlap vs2 `vsxseg5ei32.v v4,\(a0\),v4'
+-.*Error: illegal operands vd cannot overlap vm `vsxseg5ei32.v v0,\(a0\),v4,v0.t'
+-.*Error: illegal operands vd cannot overlap vs2 `vlxseg6ei32.v v4,\(a0\),v4'
+-.*Error: illegal operands vd cannot overlap vm `vlxseg6ei32.v v0,\(a0\),v4,v0.t'
+-.*Error: illegal operands vd cannot overlap vs2 `vsxseg6ei32.v v4,\(a0\),v4'
+-.*Error: illegal operands vd cannot overlap vm `vsxseg6ei32.v v0,\(a0\),v4,v0.t'
+-.*Error: illegal operands vd cannot overlap vs2 `vlxseg7ei32.v v4,\(a0\),v4'
+-.*Error: illegal operands vd cannot overlap vm `vlxseg7ei32.v v0,\(a0\),v4,v0.t'
+-.*Error: illegal operands vd cannot overlap vs2 `vsxseg7ei32.v v4,\(a0\),v4'
+-.*Error: illegal operands vd cannot overlap vm `vsxseg7ei32.v v0,\(a0\),v4,v0.t'
+-.*Error: illegal operands vd cannot overlap vs2 `vlxseg8ei32.v v4,\(a0\),v4'
+-.*Error: illegal operands vd cannot overlap vm `vlxseg8ei32.v v0,\(a0\),v4,v0.t'
+-.*Error: illegal operands vd cannot overlap vs2 `vsxseg8ei32.v v4,\(a0\),v4'
+-.*Error: illegal operands vd cannot overlap vm `vsxseg8ei32.v v0,\(a0\),v4,v0.t'
+-.*Error: illegal operands vd cannot overlap vs2 `vlxseg2ei64.v v4,\(a0\),v4'
+-.*Error: illegal operands vd cannot overlap vm `vlxseg2ei64.v v0,\(a0\),v4,v0.t'
+-.*Error: illegal operands vd cannot overlap vs2 `vsxseg2ei64.v v4,\(a0\),v4'
+-.*Error: illegal operands vd cannot overlap vm `vsxseg2ei64.v v0,\(a0\),v4,v0.t'
+-.*Error: illegal operands vd cannot overlap vs2 `vlxseg3ei64.v v4,\(a0\),v4'
+-.*Error: illegal operands vd cannot overlap vm `vlxseg3ei64.v v0,\(a0\),v4,v0.t'
+-.*Error: illegal operands vd cannot overlap vs2 `vsxseg3ei64.v v4,\(a0\),v4'
+-.*Error: illegal operands vd cannot overlap vm `vsxseg3ei64.v v0,\(a0\),v4,v0.t'
+-.*Error: illegal operands vd cannot overlap vs2 `vlxseg4ei64.v v4,\(a0\),v4'
+-.*Error: illegal operands vd cannot overlap vm `vlxseg4ei64.v v0,\(a0\),v4,v0.t'
+-.*Error: illegal operands vd cannot overlap vs2 `vsxseg4ei64.v v4,\(a0\),v4'
+-.*Error: illegal operands vd cannot overlap vm `vsxseg4ei64.v v0,\(a0\),v4,v0.t'
+-.*Error: illegal operands vd cannot overlap vs2 `vlxseg5ei64.v v4,\(a0\),v4'
+-.*Error: illegal operands vd cannot overlap vm `vlxseg5ei64.v v0,\(a0\),v4,v0.t'
+-.*Error: illegal operands vd cannot overlap vs2 `vsxseg5ei64.v v4,\(a0\),v4'
+-.*Error: illegal operands vd cannot overlap vm `vsxseg5ei64.v v0,\(a0\),v4,v0.t'
+-.*Error: illegal operands vd cannot overlap vs2 `vlxseg6ei64.v v4,\(a0\),v4'
+-.*Error: illegal operands vd cannot overlap vm `vlxseg6ei64.v v0,\(a0\),v4,v0.t'
+-.*Error: illegal operands vd cannot overlap vs2 `vsxseg6ei64.v v4,\(a0\),v4'
+-.*Error: illegal operands vd cannot overlap vm `vsxseg6ei64.v v0,\(a0\),v4,v0.t'
+-.*Error: illegal operands vd cannot overlap vs2 `vlxseg7ei64.v v4,\(a0\),v4'
+-.*Error: illegal operands vd cannot overlap vm `vlxseg7ei64.v v0,\(a0\),v4,v0.t'
+-.*Error: illegal operands vd cannot overlap vs2 `vsxseg7ei64.v v4,\(a0\),v4'
+-.*Error: illegal operands vd cannot overlap vm `vsxseg7ei64.v v0,\(a0\),v4,v0.t'
+-.*Error: illegal operands vd cannot overlap vs2 `vlxseg8ei64.v v4,\(a0\),v4'
+-.*Error: illegal operands vd cannot overlap vm `vlxseg8ei64.v v0,\(a0\),v4,v0.t'
+-.*Error: illegal operands vd cannot overlap vs2 `vsxseg8ei64.v v4,\(a0\),v4'
+-.*Error: illegal operands vd cannot overlap vm `vsxseg8ei64.v v0,\(a0\),v4,v0.t'
+-.*Error: illegal operands vd cannot overlap vs2 `vlxseg2ei128.v v4,\(a0\),v4'
+-.*Error: illegal operands vd cannot overlap vm `vlxseg2ei128.v v0,\(a0\),v4,v0.t'
+-.*Error: illegal operands vd cannot overlap vs2 `vsxseg2ei128.v v4,\(a0\),v4'
+-.*Error: illegal operands vd cannot overlap vm `vsxseg2ei128.v v0,\(a0\),v4,v0.t'
+-.*Error: illegal operands vd cannot overlap vs2 `vlxseg3ei128.v v4,\(a0\),v4'
+-.*Error: illegal operands vd cannot overlap vm `vlxseg3ei128.v v0,\(a0\),v4,v0.t'
+-.*Error: illegal operands vd cannot overlap vs2 `vsxseg3ei128.v v4,\(a0\),v4'
+-.*Error: illegal operands vd cannot overlap vm `vsxseg3ei128.v v0,\(a0\),v4,v0.t'
+-.*Error: illegal operands vd cannot overlap vs2 `vlxseg4ei128.v v4,\(a0\),v4'
+-.*Error: illegal operands vd cannot overlap vm `vlxseg4ei128.v v0,\(a0\),v4,v0.t'
+-.*Error: illegal operands vd cannot overlap vs2 `vsxseg4ei128.v v4,\(a0\),v4'
+-.*Error: illegal operands vd cannot overlap vm `vsxseg4ei128.v v0,\(a0\),v4,v0.t'
+-.*Error: illegal operands vd cannot overlap vs2 `vlxseg5ei128.v v4,\(a0\),v4'
+-.*Error: illegal operands vd cannot overlap vm `vlxseg5ei128.v v0,\(a0\),v4,v0.t'
+-.*Error: illegal operands vd cannot overlap vs2 `vsxseg5ei128.v v4,\(a0\),v4'
+-.*Error: illegal operands vd cannot overlap vm `vsxseg5ei128.v v0,\(a0\),v4,v0.t'
+-.*Error: illegal operands vd cannot overlap vs2 `vlxseg6ei128.v v4,\(a0\),v4'
+-.*Error: illegal operands vd cannot overlap vm `vlxseg6ei128.v v0,\(a0\),v4,v0.t'
+-.*Error: illegal operands vd cannot overlap vs2 `vsxseg6ei128.v v4,\(a0\),v4'
+-.*Error: illegal operands vd cannot overlap vm `vsxseg6ei128.v v0,\(a0\),v4,v0.t'
+-.*Error: illegal operands vd cannot overlap vs2 `vlxseg7ei128.v v4,\(a0\),v4'
+-.*Error: illegal operands vd cannot overlap vm `vlxseg7ei128.v v0,\(a0\),v4,v0.t'
+-.*Error: illegal operands vd cannot overlap vs2 `vsxseg7ei128.v v4,\(a0\),v4'
+-.*Error: illegal operands vd cannot overlap vm `vsxseg7ei128.v v0,\(a0\),v4,v0.t'
+-.*Error: illegal operands vd cannot overlap vs2 `vlxseg8ei128.v v4,\(a0\),v4'
+-.*Error: illegal operands vd cannot overlap vm `vlxseg8ei128.v v0,\(a0\),v4,v0.t'
+-.*Error: illegal operands vd cannot overlap vs2 `vsxseg8ei128.v v4,\(a0\),v4'
+-.*Error: illegal operands vd cannot overlap vm `vsxseg8ei128.v v0,\(a0\),v4,v0.t'
+-.*Error: illegal operands vd cannot overlap vs2 `vlxseg2ei256.v v4,\(a0\),v4'
+-.*Error: illegal operands vd cannot overlap vm `vlxseg2ei256.v v0,\(a0\),v4,v0.t'
+-.*Error: illegal operands vd cannot overlap vs2 `vsxseg2ei256.v v4,\(a0\),v4'
+-.*Error: illegal operands vd cannot overlap vm `vsxseg2ei256.v v0,\(a0\),v4,v0.t'
+-.*Error: illegal operands vd cannot overlap vs2 `vlxseg3ei256.v v4,\(a0\),v4'
+-.*Error: illegal operands vd cannot overlap vm `vlxseg3ei256.v v0,\(a0\),v4,v0.t'
+-.*Error: illegal operands vd cannot overlap vs2 `vsxseg3ei256.v v4,\(a0\),v4'
+-.*Error: illegal operands vd cannot overlap vm `vsxseg3ei256.v v0,\(a0\),v4,v0.t'
+-.*Error: illegal operands vd cannot overlap vs2 `vlxseg4ei256.v v4,\(a0\),v4'
+-.*Error: illegal operands vd cannot overlap vm `vlxseg4ei256.v v0,\(a0\),v4,v0.t'
+-.*Error: illegal operands vd cannot overlap vs2 `vsxseg4ei256.v v4,\(a0\),v4'
+-.*Error: illegal operands vd cannot overlap vm `vsxseg4ei256.v v0,\(a0\),v4,v0.t'
+-.*Error: illegal operands vd cannot overlap vs2 `vlxseg5ei256.v v4,\(a0\),v4'
+-.*Error: illegal operands vd cannot overlap vm `vlxseg5ei256.v v0,\(a0\),v4,v0.t'
+-.*Error: illegal operands vd cannot overlap vs2 `vsxseg5ei256.v v4,\(a0\),v4'
+-.*Error: illegal operands vd cannot overlap vm `vsxseg5ei256.v v0,\(a0\),v4,v0.t'
+-.*Error: illegal operands vd cannot overlap vs2 `vlxseg6ei256.v v4,\(a0\),v4'
+-.*Error: illegal operands vd cannot overlap vm `vlxseg6ei256.v v0,\(a0\),v4,v0.t'
+-.*Error: illegal operands vd cannot overlap vs2 `vsxseg6ei256.v v4,\(a0\),v4'
+-.*Error: illegal operands vd cannot overlap vm `vsxseg6ei256.v v0,\(a0\),v4,v0.t'
+-.*Error: illegal operands vd cannot overlap vs2 `vlxseg7ei256.v v4,\(a0\),v4'
+-.*Error: illegal operands vd cannot overlap vm `vlxseg7ei256.v v0,\(a0\),v4,v0.t'
+-.*Error: illegal operands vd cannot overlap vs2 `vsxseg7ei256.v v4,\(a0\),v4'
+-.*Error: illegal operands vd cannot overlap vm `vsxseg7ei256.v v0,\(a0\),v4,v0.t'
+-.*Error: illegal operands vd cannot overlap vs2 `vlxseg8ei256.v v4,\(a0\),v4'
+-.*Error: illegal operands vd cannot overlap vm `vlxseg8ei256.v v0,\(a0\),v4,v0.t'
+-.*Error: illegal operands vd cannot overlap vs2 `vsxseg8ei256.v v4,\(a0\),v4'
+-.*Error: illegal operands vd cannot overlap vm `vsxseg8ei256.v v0,\(a0\),v4,v0.t'
+-.*Error: illegal operands vd cannot overlap vs2 `vlxseg2ei512.v v4,\(a0\),v4'
+-.*Error: illegal operands vd cannot overlap vm `vlxseg2ei512.v v0,\(a0\),v4,v0.t'
+-.*Error: illegal operands vd cannot overlap vs2 `vsxseg2ei512.v v4,\(a0\),v4'
+-.*Error: illegal operands vd cannot overlap vm `vsxseg2ei512.v v0,\(a0\),v4,v0.t'
+-.*Error: illegal operands vd cannot overlap vs2 `vlxseg3ei512.v v4,\(a0\),v4'
+-.*Error: illegal operands vd cannot overlap vm `vlxseg3ei512.v v0,\(a0\),v4,v0.t'
+-.*Error: illegal operands vd cannot overlap vs2 `vsxseg3ei512.v v4,\(a0\),v4'
+-.*Error: illegal operands vd cannot overlap vm `vsxseg3ei512.v v0,\(a0\),v4,v0.t'
+-.*Error: illegal operands vd cannot overlap vs2 `vlxseg4ei512.v v4,\(a0\),v4'
+-.*Error: illegal operands vd cannot overlap vm `vlxseg4ei512.v v0,\(a0\),v4,v0.t'
+-.*Error: illegal operands vd cannot overlap vs2 `vsxseg4ei512.v v4,\(a0\),v4'
+-.*Error: illegal operands vd cannot overlap vm `vsxseg4ei512.v v0,\(a0\),v4,v0.t'
+-.*Error: illegal operands vd cannot overlap vs2 `vlxseg5ei512.v v4,\(a0\),v4'
+-.*Error: illegal operands vd cannot overlap vm `vlxseg5ei512.v v0,\(a0\),v4,v0.t'
+-.*Error: illegal operands vd cannot overlap vs2 `vsxseg5ei512.v v4,\(a0\),v4'
+-.*Error: illegal operands vd cannot overlap vm `vsxseg5ei512.v v0,\(a0\),v4,v0.t'
+-.*Error: illegal operands vd cannot overlap vs2 `vlxseg6ei512.v v4,\(a0\),v4'
+-.*Error: illegal operands vd cannot overlap vm `vlxseg6ei512.v v0,\(a0\),v4,v0.t'
+-.*Error: illegal operands vd cannot overlap vs2 `vsxseg6ei512.v v4,\(a0\),v4'
+-.*Error: illegal operands vd cannot overlap vm `vsxseg6ei512.v v0,\(a0\),v4,v0.t'
+-.*Error: illegal operands vd cannot overlap vs2 `vlxseg7ei512.v v4,\(a0\),v4'
+-.*Error: illegal operands vd cannot overlap vm `vlxseg7ei512.v v0,\(a0\),v4,v0.t'
+-.*Error: illegal operands vd cannot overlap vs2 `vsxseg7ei512.v v4,\(a0\),v4'
+-.*Error: illegal operands vd cannot overlap vm `vsxseg7ei512.v v0,\(a0\),v4,v0.t'
+-.*Error: illegal operands vd cannot overlap vs2 `vlxseg8ei512.v v4,\(a0\),v4'
+-.*Error: illegal operands vd cannot overlap vm `vlxseg8ei512.v v0,\(a0\),v4,v0.t'
+-.*Error: illegal operands vd cannot overlap vs2 `vsxseg8ei512.v v4,\(a0\),v4'
+-.*Error: illegal operands vd cannot overlap vm `vsxseg8ei512.v v0,\(a0\),v4,v0.t'
+-.*Error: illegal operands vd cannot overlap vs2 `vlxseg2ei1024.v v4,\(a0\),v4'
+-.*Error: illegal operands vd cannot overlap vm `vlxseg2ei1024.v v0,\(a0\),v4,v0.t'
+-.*Error: illegal operands vd cannot overlap vs2 `vsxseg2ei1024.v v4,\(a0\),v4'
+-.*Error: illegal operands vd cannot overlap vm `vsxseg2ei1024.v v0,\(a0\),v4,v0.t'
+-.*Error: illegal operands vd cannot overlap vs2 `vlxseg3ei1024.v v4,\(a0\),v4'
+-.*Error: illegal operands vd cannot overlap vm `vlxseg3ei1024.v v0,\(a0\),v4,v0.t'
+-.*Error: illegal operands vd cannot overlap vs2 `vsxseg3ei1024.v v4,\(a0\),v4'
+-.*Error: illegal operands vd cannot overlap vm `vsxseg3ei1024.v v0,\(a0\),v4,v0.t'
+-.*Error: illegal operands vd cannot overlap vs2 `vlxseg4ei1024.v v4,\(a0\),v4'
+-.*Error: illegal operands vd cannot overlap vm `vlxseg4ei1024.v v0,\(a0\),v4,v0.t'
+-.*Error: illegal operands vd cannot overlap vs2 `vsxseg4ei1024.v v4,\(a0\),v4'
+-.*Error: illegal operands vd cannot overlap vm `vsxseg4ei1024.v v0,\(a0\),v4,v0.t'
+-.*Error: illegal operands vd cannot overlap vs2 `vlxseg5ei1024.v v4,\(a0\),v4'
+-.*Error: illegal operands vd cannot overlap vm `vlxseg5ei1024.v v0,\(a0\),v4,v0.t'
+-.*Error: illegal operands vd cannot overlap vs2 `vsxseg5ei1024.v v4,\(a0\),v4'
+-.*Error: illegal operands vd cannot overlap vm `vsxseg5ei1024.v v0,\(a0\),v4,v0.t'
+-.*Error: illegal operands vd cannot overlap vs2 `vlxseg6ei1024.v v4,\(a0\),v4'
+-.*Error: illegal operands vd cannot overlap vm `vlxseg6ei1024.v v0,\(a0\),v4,v0.t'
+-.*Error: illegal operands vd cannot overlap vs2 `vsxseg6ei1024.v v4,\(a0\),v4'
+-.*Error: illegal operands vd cannot overlap vm `vsxseg6ei1024.v v0,\(a0\),v4,v0.t'
+-.*Error: illegal operands vd cannot overlap vs2 `vlxseg7ei1024.v v4,\(a0\),v4'
+-.*Error: illegal operands vd cannot overlap vm `vlxseg7ei1024.v v0,\(a0\),v4,v0.t'
+-.*Error: illegal operands vd cannot overlap vs2 `vsxseg7ei1024.v v4,\(a0\),v4'
+-.*Error: illegal operands vd cannot overlap vm `vsxseg7ei1024.v v0,\(a0\),v4,v0.t'
+-.*Error: illegal operands vd cannot overlap vs2 `vlxseg8ei1024.v v4,\(a0\),v4'
+-.*Error: illegal operands vd cannot overlap vm `vlxseg8ei1024.v v0,\(a0\),v4,v0.t'
+-.*Error: illegal operands vd cannot overlap vs2 `vsxseg8ei1024.v v4,\(a0\),v4'
+-.*Error: illegal operands vd cannot overlap vm `vsxseg8ei1024.v v0,\(a0\),v4,v0.t'
++.*Error: illegal operands vd cannot overlap vs2 `vloxseg2ei8.v v4,\(a0\),v4'
++.*Error: illegal operands vd cannot overlap vm `vloxseg2ei8.v v0,\(a0\),v4,v0.t'
++.*Error: illegal operands vd cannot overlap vs2 `vsoxseg2ei8.v v4,\(a0\),v4'
++.*Error: illegal operands vd cannot overlap vm `vsoxseg2ei8.v v0,\(a0\),v4,v0.t'
++.*Error: illegal operands vd cannot overlap vs2 `vloxseg3ei8.v v4,\(a0\),v4'
++.*Error: illegal operands vd cannot overlap vm `vloxseg3ei8.v v0,\(a0\),v4,v0.t'
++.*Error: illegal operands vd cannot overlap vs2 `vsoxseg3ei8.v v4,\(a0\),v4'
++.*Error: illegal operands vd cannot overlap vm `vsoxseg3ei8.v v0,\(a0\),v4,v0.t'
++.*Error: illegal operands vd cannot overlap vs2 `vloxseg4ei8.v v4,\(a0\),v4'
++.*Error: illegal operands vd cannot overlap vm `vloxseg4ei8.v v0,\(a0\),v4,v0.t'
++.*Error: illegal operands vd cannot overlap vs2 `vsoxseg4ei8.v v4,\(a0\),v4'
++.*Error: illegal operands vd cannot overlap vm `vsoxseg4ei8.v v0,\(a0\),v4,v0.t'
++.*Error: illegal operands vd cannot overlap vs2 `vloxseg5ei8.v v4,\(a0\),v4'
++.*Error: illegal operands vd cannot overlap vm `vloxseg5ei8.v v0,\(a0\),v4,v0.t'
++.*Error: illegal operands vd cannot overlap vs2 `vsoxseg5ei8.v v4,\(a0\),v4'
++.*Error: illegal operands vd cannot overlap vm `vsoxseg5ei8.v v0,\(a0\),v4,v0.t'
++.*Error: illegal operands vd cannot overlap vs2 `vloxseg6ei8.v v4,\(a0\),v4'
++.*Error: illegal operands vd cannot overlap vm `vloxseg6ei8.v v0,\(a0\),v4,v0.t'
++.*Error: illegal operands vd cannot overlap vs2 `vsoxseg6ei8.v v4,\(a0\),v4'
++.*Error: illegal operands vd cannot overlap vm `vsoxseg6ei8.v v0,\(a0\),v4,v0.t'
++.*Error: illegal operands vd cannot overlap vs2 `vloxseg7ei8.v v4,\(a0\),v4'
++.*Error: illegal operands vd cannot overlap vm `vloxseg7ei8.v v0,\(a0\),v4,v0.t'
++.*Error: illegal operands vd cannot overlap vs2 `vsoxseg7ei8.v v4,\(a0\),v4'
++.*Error: illegal operands vd cannot overlap vm `vsoxseg7ei8.v v0,\(a0\),v4,v0.t'
++.*Error: illegal operands vd cannot overlap vs2 `vloxseg8ei8.v v4,\(a0\),v4'
++.*Error: illegal operands vd cannot overlap vm `vloxseg8ei8.v v0,\(a0\),v4,v0.t'
++.*Error: illegal operands vd cannot overlap vs2 `vsoxseg8ei8.v v4,\(a0\),v4'
++.*Error: illegal operands vd cannot overlap vm `vsoxseg8ei8.v v0,\(a0\),v4,v0.t'
++.*Error: illegal operands vd cannot overlap vs2 `vloxseg2ei16.v v4,\(a0\),v4'
++.*Error: illegal operands vd cannot overlap vm `vloxseg2ei16.v v0,\(a0\),v4,v0.t'
++.*Error: illegal operands vd cannot overlap vs2 `vsoxseg2ei16.v v4,\(a0\),v4'
++.*Error: illegal operands vd cannot overlap vm `vsoxseg2ei16.v v0,\(a0\),v4,v0.t'
++.*Error: illegal operands vd cannot overlap vs2 `vloxseg3ei16.v v4,\(a0\),v4'
++.*Error: illegal operands vd cannot overlap vm `vloxseg3ei16.v v0,\(a0\),v4,v0.t'
++.*Error: illegal operands vd cannot overlap vs2 `vsoxseg3ei16.v v4,\(a0\),v4'
++.*Error: illegal operands vd cannot overlap vm `vsoxseg3ei16.v v0,\(a0\),v4,v0.t'
++.*Error: illegal operands vd cannot overlap vs2 `vloxseg4ei16.v v4,\(a0\),v4'
++.*Error: illegal operands vd cannot overlap vm `vloxseg4ei16.v v0,\(a0\),v4,v0.t'
++.*Error: illegal operands vd cannot overlap vs2 `vsoxseg4ei16.v v4,\(a0\),v4'
++.*Error: illegal operands vd cannot overlap vm `vsoxseg4ei16.v v0,\(a0\),v4,v0.t'
++.*Error: illegal operands vd cannot overlap vs2 `vloxseg5ei16.v v4,\(a0\),v4'
++.*Error: illegal operands vd cannot overlap vm `vloxseg5ei16.v v0,\(a0\),v4,v0.t'
++.*Error: illegal operands vd cannot overlap vs2 `vsoxseg5ei16.v v4,\(a0\),v4'
++.*Error: illegal operands vd cannot overlap vm `vsoxseg5ei16.v v0,\(a0\),v4,v0.t'
++.*Error: illegal operands vd cannot overlap vs2 `vloxseg6ei16.v v4,\(a0\),v4'
++.*Error: illegal operands vd cannot overlap vm `vloxseg6ei16.v v0,\(a0\),v4,v0.t'
++.*Error: illegal operands vd cannot overlap vs2 `vsoxseg6ei16.v v4,\(a0\),v4'
++.*Error: illegal operands vd cannot overlap vm `vsoxseg6ei16.v v0,\(a0\),v4,v0.t'
++.*Error: illegal operands vd cannot overlap vs2 `vloxseg7ei16.v v4,\(a0\),v4'
++.*Error: illegal operands vd cannot overlap vm `vloxseg7ei16.v v0,\(a0\),v4,v0.t'
++.*Error: illegal operands vd cannot overlap vs2 `vsoxseg7ei16.v v4,\(a0\),v4'
++.*Error: illegal operands vd cannot overlap vm `vsoxseg7ei16.v v0,\(a0\),v4,v0.t'
++.*Error: illegal operands vd cannot overlap vs2 `vloxseg8ei16.v v4,\(a0\),v4'
++.*Error: illegal operands vd cannot overlap vm `vloxseg8ei16.v v0,\(a0\),v4,v0.t'
++.*Error: illegal operands vd cannot overlap vs2 `vsoxseg8ei16.v v4,\(a0\),v4'
++.*Error: illegal operands vd cannot overlap vm `vsoxseg8ei16.v v0,\(a0\),v4,v0.t'
++.*Error: illegal operands vd cannot overlap vs2 `vloxseg2ei32.v v4,\(a0\),v4'
++.*Error: illegal operands vd cannot overlap vm `vloxseg2ei32.v v0,\(a0\),v4,v0.t'
++.*Error: illegal operands vd cannot overlap vs2 `vsoxseg2ei32.v v4,\(a0\),v4'
++.*Error: illegal operands vd cannot overlap vm `vsoxseg2ei32.v v0,\(a0\),v4,v0.t'
++.*Error: illegal operands vd cannot overlap vs2 `vloxseg3ei32.v v4,\(a0\),v4'
++.*Error: illegal operands vd cannot overlap vm `vloxseg3ei32.v v0,\(a0\),v4,v0.t'
++.*Error: illegal operands vd cannot overlap vs2 `vsoxseg3ei32.v v4,\(a0\),v4'
++.*Error: illegal operands vd cannot overlap vm `vsoxseg3ei32.v v0,\(a0\),v4,v0.t'
++.*Error: illegal operands vd cannot overlap vs2 `vloxseg4ei32.v v4,\(a0\),v4'
++.*Error: illegal operands vd cannot overlap vm `vloxseg4ei32.v v0,\(a0\),v4,v0.t'
++.*Error: illegal operands vd cannot overlap vs2 `vsoxseg4ei32.v v4,\(a0\),v4'
++.*Error: illegal operands vd cannot overlap vm `vsoxseg4ei32.v v0,\(a0\),v4,v0.t'
++.*Error: illegal operands vd cannot overlap vs2 `vloxseg5ei32.v v4,\(a0\),v4'
++.*Error: illegal operands vd cannot overlap vm `vloxseg5ei32.v v0,\(a0\),v4,v0.t'
++.*Error: illegal operands vd cannot overlap vs2 `vsoxseg5ei32.v v4,\(a0\),v4'
++.*Error: illegal operands vd cannot overlap vm `vsoxseg5ei32.v v0,\(a0\),v4,v0.t'
++.*Error: illegal operands vd cannot overlap vs2 `vloxseg6ei32.v v4,\(a0\),v4'
++.*Error: illegal operands vd cannot overlap vm `vloxseg6ei32.v v0,\(a0\),v4,v0.t'
++.*Error: illegal operands vd cannot overlap vs2 `vsoxseg6ei32.v v4,\(a0\),v4'
++.*Error: illegal operands vd cannot overlap vm `vsoxseg6ei32.v v0,\(a0\),v4,v0.t'
++.*Error: illegal operands vd cannot overlap vs2 `vloxseg7ei32.v v4,\(a0\),v4'
++.*Error: illegal operands vd cannot overlap vm `vloxseg7ei32.v v0,\(a0\),v4,v0.t'
++.*Error: illegal operands vd cannot overlap vs2 `vsoxseg7ei32.v v4,\(a0\),v4'
++.*Error: illegal operands vd cannot overlap vm `vsoxseg7ei32.v v0,\(a0\),v4,v0.t'
++.*Error: illegal operands vd cannot overlap vs2 `vloxseg8ei32.v v4,\(a0\),v4'
++.*Error: illegal operands vd cannot overlap vm `vloxseg8ei32.v v0,\(a0\),v4,v0.t'
++.*Error: illegal operands vd cannot overlap vs2 `vsoxseg8ei32.v v4,\(a0\),v4'
++.*Error: illegal operands vd cannot overlap vm `vsoxseg8ei32.v v0,\(a0\),v4,v0.t'
++.*Error: illegal operands vd cannot overlap vs2 `vloxseg2ei64.v v4,\(a0\),v4'
++.*Error: illegal operands vd cannot overlap vm `vloxseg2ei64.v v0,\(a0\),v4,v0.t'
++.*Error: illegal operands vd cannot overlap vs2 `vsoxseg2ei64.v v4,\(a0\),v4'
++.*Error: illegal operands vd cannot overlap vm `vsoxseg2ei64.v v0,\(a0\),v4,v0.t'
++.*Error: illegal operands vd cannot overlap vs2 `vloxseg3ei64.v v4,\(a0\),v4'
++.*Error: illegal operands vd cannot overlap vm `vloxseg3ei64.v v0,\(a0\),v4,v0.t'
++.*Error: illegal operands vd cannot overlap vs2 `vsoxseg3ei64.v v4,\(a0\),v4'
++.*Error: illegal operands vd cannot overlap vm `vsoxseg3ei64.v v0,\(a0\),v4,v0.t'
++.*Error: illegal operands vd cannot overlap vs2 `vloxseg4ei64.v v4,\(a0\),v4'
++.*Error: illegal operands vd cannot overlap vm `vloxseg4ei64.v v0,\(a0\),v4,v0.t'
++.*Error: illegal operands vd cannot overlap vs2 `vsoxseg4ei64.v v4,\(a0\),v4'
++.*Error: illegal operands vd cannot overlap vm `vsoxseg4ei64.v v0,\(a0\),v4,v0.t'
++.*Error: illegal operands vd cannot overlap vs2 `vloxseg5ei64.v v4,\(a0\),v4'
++.*Error: illegal operands vd cannot overlap vm `vloxseg5ei64.v v0,\(a0\),v4,v0.t'
++.*Error: illegal operands vd cannot overlap vs2 `vsoxseg5ei64.v v4,\(a0\),v4'
++.*Error: illegal operands vd cannot overlap vm `vsoxseg5ei64.v v0,\(a0\),v4,v0.t'
++.*Error: illegal operands vd cannot overlap vs2 `vloxseg6ei64.v v4,\(a0\),v4'
++.*Error: illegal operands vd cannot overlap vm `vloxseg6ei64.v v0,\(a0\),v4,v0.t'
++.*Error: illegal operands vd cannot overlap vs2 `vsoxseg6ei64.v v4,\(a0\),v4'
++.*Error: illegal operands vd cannot overlap vm `vsoxseg6ei64.v v0,\(a0\),v4,v0.t'
++.*Error: illegal operands vd cannot overlap vs2 `vloxseg7ei64.v v4,\(a0\),v4'
++.*Error: illegal operands vd cannot overlap vm `vloxseg7ei64.v v0,\(a0\),v4,v0.t'
++.*Error: illegal operands vd cannot overlap vs2 `vsoxseg7ei64.v v4,\(a0\),v4'
++.*Error: illegal operands vd cannot overlap vm `vsoxseg7ei64.v v0,\(a0\),v4,v0.t'
++.*Error: illegal operands vd cannot overlap vs2 `vloxseg8ei64.v v4,\(a0\),v4'
++.*Error: illegal operands vd cannot overlap vm `vloxseg8ei64.v v0,\(a0\),v4,v0.t'
++.*Error: illegal operands vd cannot overlap vs2 `vsoxseg8ei64.v v4,\(a0\),v4'
++.*Error: illegal operands vd cannot overlap vm `vsoxseg8ei64.v v0,\(a0\),v4,v0.t'
++.*Error: illegal operands vd cannot overlap vs2 `vloxseg2ei128.v v4,\(a0\),v4'
++.*Error: illegal operands vd cannot overlap vm `vloxseg2ei128.v v0,\(a0\),v4,v0.t'
++.*Error: illegal operands vd cannot overlap vs2 `vsoxseg2ei128.v v4,\(a0\),v4'
++.*Error: illegal operands vd cannot overlap vm `vsoxseg2ei128.v v0,\(a0\),v4,v0.t'
++.*Error: illegal operands vd cannot overlap vs2 `vloxseg3ei128.v v4,\(a0\),v4'
++.*Error: illegal operands vd cannot overlap vm `vloxseg3ei128.v v0,\(a0\),v4,v0.t'
++.*Error: illegal operands vd cannot overlap vs2 `vsoxseg3ei128.v v4,\(a0\),v4'
++.*Error: illegal operands vd cannot overlap vm `vsoxseg3ei128.v v0,\(a0\),v4,v0.t'
++.*Error: illegal operands vd cannot overlap vs2 `vloxseg4ei128.v v4,\(a0\),v4'
++.*Error: illegal operands vd cannot overlap vm `vloxseg4ei128.v v0,\(a0\),v4,v0.t'
++.*Error: illegal operands vd cannot overlap vs2 `vsoxseg4ei128.v v4,\(a0\),v4'
++.*Error: illegal operands vd cannot overlap vm `vsoxseg4ei128.v v0,\(a0\),v4,v0.t'
++.*Error: illegal operands vd cannot overlap vs2 `vloxseg5ei128.v v4,\(a0\),v4'
++.*Error: illegal operands vd cannot overlap vm `vloxseg5ei128.v v0,\(a0\),v4,v0.t'
++.*Error: illegal operands vd cannot overlap vs2 `vsoxseg5ei128.v v4,\(a0\),v4'
++.*Error: illegal operands vd cannot overlap vm `vsoxseg5ei128.v v0,\(a0\),v4,v0.t'
++.*Error: illegal operands vd cannot overlap vs2 `vloxseg6ei128.v v4,\(a0\),v4'
++.*Error: illegal operands vd cannot overlap vm `vloxseg6ei128.v v0,\(a0\),v4,v0.t'
++.*Error: illegal operands vd cannot overlap vs2 `vsoxseg6ei128.v v4,\(a0\),v4'
++.*Error: illegal operands vd cannot overlap vm `vsoxseg6ei128.v v0,\(a0\),v4,v0.t'
++.*Error: illegal operands vd cannot overlap vs2 `vloxseg7ei128.v v4,\(a0\),v4'
++.*Error: illegal operands vd cannot overlap vm `vloxseg7ei128.v v0,\(a0\),v4,v0.t'
++.*Error: illegal operands vd cannot overlap vs2 `vsoxseg7ei128.v v4,\(a0\),v4'
++.*Error: illegal operands vd cannot overlap vm `vsoxseg7ei128.v v0,\(a0\),v4,v0.t'
++.*Error: illegal operands vd cannot overlap vs2 `vloxseg8ei128.v v4,\(a0\),v4'
++.*Error: illegal operands vd cannot overlap vm `vloxseg8ei128.v v0,\(a0\),v4,v0.t'
++.*Error: illegal operands vd cannot overlap vs2 `vsoxseg8ei128.v v4,\(a0\),v4'
++.*Error: illegal operands vd cannot overlap vm `vsoxseg8ei128.v v0,\(a0\),v4,v0.t'
++.*Error: illegal operands vd cannot overlap vs2 `vloxseg2ei256.v v4,\(a0\),v4'
++.*Error: illegal operands vd cannot overlap vm `vloxseg2ei256.v v0,\(a0\),v4,v0.t'
++.*Error: illegal operands vd cannot overlap vs2 `vsoxseg2ei256.v v4,\(a0\),v4'
++.*Error: illegal operands vd cannot overlap vm `vsoxseg2ei256.v v0,\(a0\),v4,v0.t'
++.*Error: illegal operands vd cannot overlap vs2 `vloxseg3ei256.v v4,\(a0\),v4'
++.*Error: illegal operands vd cannot overlap vm `vloxseg3ei256.v v0,\(a0\),v4,v0.t'
++.*Error: illegal operands vd cannot overlap vs2 `vsoxseg3ei256.v v4,\(a0\),v4'
++.*Error: illegal operands vd cannot overlap vm `vsoxseg3ei256.v v0,\(a0\),v4,v0.t'
++.*Error: illegal operands vd cannot overlap vs2 `vloxseg4ei256.v v4,\(a0\),v4'
++.*Error: illegal operands vd cannot overlap vm `vloxseg4ei256.v v0,\(a0\),v4,v0.t'
++.*Error: illegal operands vd cannot overlap vs2 `vsoxseg4ei256.v v4,\(a0\),v4'
++.*Error: illegal operands vd cannot overlap vm `vsoxseg4ei256.v v0,\(a0\),v4,v0.t'
++.*Error: illegal operands vd cannot overlap vs2 `vloxseg5ei256.v v4,\(a0\),v4'
++.*Error: illegal operands vd cannot overlap vm `vloxseg5ei256.v v0,\(a0\),v4,v0.t'
++.*Error: illegal operands vd cannot overlap vs2 `vsoxseg5ei256.v v4,\(a0\),v4'
++.*Error: illegal operands vd cannot overlap vm `vsoxseg5ei256.v v0,\(a0\),v4,v0.t'
++.*Error: illegal operands vd cannot overlap vs2 `vloxseg6ei256.v v4,\(a0\),v4'
++.*Error: illegal operands vd cannot overlap vm `vloxseg6ei256.v v0,\(a0\),v4,v0.t'
++.*Error: illegal operands vd cannot overlap vs2 `vsoxseg6ei256.v v4,\(a0\),v4'
++.*Error: illegal operands vd cannot overlap vm `vsoxseg6ei256.v v0,\(a0\),v4,v0.t'
++.*Error: illegal operands vd cannot overlap vs2 `vloxseg7ei256.v v4,\(a0\),v4'
++.*Error: illegal operands vd cannot overlap vm `vloxseg7ei256.v v0,\(a0\),v4,v0.t'
++.*Error: illegal operands vd cannot overlap vs2 `vsoxseg7ei256.v v4,\(a0\),v4'
++.*Error: illegal operands vd cannot overlap vm `vsoxseg7ei256.v v0,\(a0\),v4,v0.t'
++.*Error: illegal operands vd cannot overlap vs2 `vloxseg8ei256.v v4,\(a0\),v4'
++.*Error: illegal operands vd cannot overlap vm `vloxseg8ei256.v v0,\(a0\),v4,v0.t'
++.*Error: illegal operands vd cannot overlap vs2 `vsoxseg8ei256.v v4,\(a0\),v4'
++.*Error: illegal operands vd cannot overlap vm `vsoxseg8ei256.v v0,\(a0\),v4,v0.t'
++.*Error: illegal operands vd cannot overlap vs2 `vloxseg2ei512.v v4,\(a0\),v4'
++.*Error: illegal operands vd cannot overlap vm `vloxseg2ei512.v v0,\(a0\),v4,v0.t'
++.*Error: illegal operands vd cannot overlap vs2 `vsoxseg2ei512.v v4,\(a0\),v4'
++.*Error: illegal operands vd cannot overlap vm `vsoxseg2ei512.v v0,\(a0\),v4,v0.t'
++.*Error: illegal operands vd cannot overlap vs2 `vloxseg3ei512.v v4,\(a0\),v4'
++.*Error: illegal operands vd cannot overlap vm `vloxseg3ei512.v v0,\(a0\),v4,v0.t'
++.*Error: illegal operands vd cannot overlap vs2 `vsoxseg3ei512.v v4,\(a0\),v4'
++.*Error: illegal operands vd cannot overlap vm `vsoxseg3ei512.v v0,\(a0\),v4,v0.t'
++.*Error: illegal operands vd cannot overlap vs2 `vloxseg4ei512.v v4,\(a0\),v4'
++.*Error: illegal operands vd cannot overlap vm `vloxseg4ei512.v v0,\(a0\),v4,v0.t'
++.*Error: illegal operands vd cannot overlap vs2 `vsoxseg4ei512.v v4,\(a0\),v4'
++.*Error: illegal operands vd cannot overlap vm `vsoxseg4ei512.v v0,\(a0\),v4,v0.t'
++.*Error: illegal operands vd cannot overlap vs2 `vloxseg5ei512.v v4,\(a0\),v4'
++.*Error: illegal operands vd cannot overlap vm `vloxseg5ei512.v v0,\(a0\),v4,v0.t'
++.*Error: illegal operands vd cannot overlap vs2 `vsoxseg5ei512.v v4,\(a0\),v4'
++.*Error: illegal operands vd cannot overlap vm `vsoxseg5ei512.v v0,\(a0\),v4,v0.t'
++.*Error: illegal operands vd cannot overlap vs2 `vloxseg6ei512.v v4,\(a0\),v4'
++.*Error: illegal operands vd cannot overlap vm `vloxseg6ei512.v v0,\(a0\),v4,v0.t'
++.*Error: illegal operands vd cannot overlap vs2 `vsoxseg6ei512.v v4,\(a0\),v4'
++.*Error: illegal operands vd cannot overlap vm `vsoxseg6ei512.v v0,\(a0\),v4,v0.t'
++.*Error: illegal operands vd cannot overlap vs2 `vloxseg7ei512.v v4,\(a0\),v4'
++.*Error: illegal operands vd cannot overlap vm `vloxseg7ei512.v v0,\(a0\),v4,v0.t'
++.*Error: illegal operands vd cannot overlap vs2 `vsoxseg7ei512.v v4,\(a0\),v4'
++.*Error: illegal operands vd cannot overlap vm `vsoxseg7ei512.v v0,\(a0\),v4,v0.t'
++.*Error: illegal operands vd cannot overlap vs2 `vloxseg8ei512.v v4,\(a0\),v4'
++.*Error: illegal operands vd cannot overlap vm `vloxseg8ei512.v v0,\(a0\),v4,v0.t'
++.*Error: illegal operands vd cannot overlap vs2 `vsoxseg8ei512.v v4,\(a0\),v4'
++.*Error: illegal operands vd cannot overlap vm `vsoxseg8ei512.v v0,\(a0\),v4,v0.t'
++.*Error: illegal operands vd cannot overlap vs2 `vloxseg2ei1024.v v4,\(a0\),v4'
++.*Error: illegal operands vd cannot overlap vm `vloxseg2ei1024.v v0,\(a0\),v4,v0.t'
++.*Error: illegal operands vd cannot overlap vs2 `vsoxseg2ei1024.v v4,\(a0\),v4'
++.*Error: illegal operands vd cannot overlap vm `vsoxseg2ei1024.v v0,\(a0\),v4,v0.t'
++.*Error: illegal operands vd cannot overlap vs2 `vloxseg3ei1024.v v4,\(a0\),v4'
++.*Error: illegal operands vd cannot overlap vm `vloxseg3ei1024.v v0,\(a0\),v4,v0.t'
++.*Error: illegal operands vd cannot overlap vs2 `vsoxseg3ei1024.v v4,\(a0\),v4'
++.*Error: illegal operands vd cannot overlap vm `vsoxseg3ei1024.v v0,\(a0\),v4,v0.t'
++.*Error: illegal operands vd cannot overlap vs2 `vloxseg4ei1024.v v4,\(a0\),v4'
++.*Error: illegal operands vd cannot overlap vm `vloxseg4ei1024.v v0,\(a0\),v4,v0.t'
++.*Error: illegal operands vd cannot overlap vs2 `vsoxseg4ei1024.v v4,\(a0\),v4'
++.*Error: illegal operands vd cannot overlap vm `vsoxseg4ei1024.v v0,\(a0\),v4,v0.t'
++.*Error: illegal operands vd cannot overlap vs2 `vloxseg5ei1024.v v4,\(a0\),v4'
++.*Error: illegal operands vd cannot overlap vm `vloxseg5ei1024.v v0,\(a0\),v4,v0.t'
++.*Error: illegal operands vd cannot overlap vs2 `vsoxseg5ei1024.v v4,\(a0\),v4'
++.*Error: illegal operands vd cannot overlap vm `vsoxseg5ei1024.v v0,\(a0\),v4,v0.t'
++.*Error: illegal operands vd cannot overlap vs2 `vloxseg6ei1024.v v4,\(a0\),v4'
++.*Error: illegal operands vd cannot overlap vm `vloxseg6ei1024.v v0,\(a0\),v4,v0.t'
++.*Error: illegal operands vd cannot overlap vs2 `vsoxseg6ei1024.v v4,\(a0\),v4'
++.*Error: illegal operands vd cannot overlap vm `vsoxseg6ei1024.v v0,\(a0\),v4,v0.t'
++.*Error: illegal operands vd cannot overlap vs2 `vloxseg7ei1024.v v4,\(a0\),v4'
++.*Error: illegal operands vd cannot overlap vm `vloxseg7ei1024.v v0,\(a0\),v4,v0.t'
++.*Error: illegal operands vd cannot overlap vs2 `vsoxseg7ei1024.v v4,\(a0\),v4'
++.*Error: illegal operands vd cannot overlap vm `vsoxseg7ei1024.v v0,\(a0\),v4,v0.t'
++.*Error: illegal operands vd cannot overlap vs2 `vloxseg8ei1024.v v4,\(a0\),v4'
++.*Error: illegal operands vd cannot overlap vm `vloxseg8ei1024.v v0,\(a0\),v4,v0.t'
++.*Error: illegal operands vd cannot overlap vs2 `vsoxseg8ei1024.v v4,\(a0\),v4'
++.*Error: illegal operands vd cannot overlap vm `vsoxseg8ei1024.v v0,\(a0\),v4,v0.t'
++.*Error: illegal operands vd cannot overlap vs2 `vluxseg2ei8.v v4,\(a0\),v4'
++.*Error: illegal operands vd cannot overlap vm `vluxseg2ei8.v v0,\(a0\),v4,v0.t'
++.*Error: illegal operands vd cannot overlap vs2 `vsuxseg2ei8.v v4,\(a0\),v4'
++.*Error: illegal operands vd cannot overlap vm `vsuxseg2ei8.v v0,\(a0\),v4,v0.t'
++.*Error: illegal operands vd cannot overlap vs2 `vluxseg3ei8.v v4,\(a0\),v4'
++.*Error: illegal operands vd cannot overlap vm `vluxseg3ei8.v v0,\(a0\),v4,v0.t'
++.*Error: illegal operands vd cannot overlap vs2 `vsuxseg3ei8.v v4,\(a0\),v4'
++.*Error: illegal operands vd cannot overlap vm `vsuxseg3ei8.v v0,\(a0\),v4,v0.t'
++.*Error: illegal operands vd cannot overlap vs2 `vluxseg4ei8.v v4,\(a0\),v4'
++.*Error: illegal operands vd cannot overlap vm `vluxseg4ei8.v v0,\(a0\),v4,v0.t'
++.*Error: illegal operands vd cannot overlap vs2 `vsuxseg4ei8.v v4,\(a0\),v4'
++.*Error: illegal operands vd cannot overlap vm `vsuxseg4ei8.v v0,\(a0\),v4,v0.t'
++.*Error: illegal operands vd cannot overlap vs2 `vluxseg5ei8.v v4,\(a0\),v4'
++.*Error: illegal operands vd cannot overlap vm `vluxseg5ei8.v v0,\(a0\),v4,v0.t'
++.*Error: illegal operands vd cannot overlap vs2 `vsuxseg5ei8.v v4,\(a0\),v4'
++.*Error: illegal operands vd cannot overlap vm `vsuxseg5ei8.v v0,\(a0\),v4,v0.t'
++.*Error: illegal operands vd cannot overlap vs2 `vluxseg6ei8.v v4,\(a0\),v4'
++.*Error: illegal operands vd cannot overlap vm `vluxseg6ei8.v v0,\(a0\),v4,v0.t'
++.*Error: illegal operands vd cannot overlap vs2 `vsuxseg6ei8.v v4,\(a0\),v4'
++.*Error: illegal operands vd cannot overlap vm `vsuxseg6ei8.v v0,\(a0\),v4,v0.t'
++.*Error: illegal operands vd cannot overlap vs2 `vluxseg7ei8.v v4,\(a0\),v4'
++.*Error: illegal operands vd cannot overlap vm `vluxseg7ei8.v v0,\(a0\),v4,v0.t'
++.*Error: illegal operands vd cannot overlap vs2 `vsuxseg7ei8.v v4,\(a0\),v4'
++.*Error: illegal operands vd cannot overlap vm `vsuxseg7ei8.v v0,\(a0\),v4,v0.t'
++.*Error: illegal operands vd cannot overlap vs2 `vluxseg8ei8.v v4,\(a0\),v4'
++.*Error: illegal operands vd cannot overlap vm `vluxseg8ei8.v v0,\(a0\),v4,v0.t'
++.*Error: illegal operands vd cannot overlap vs2 `vsuxseg8ei8.v v4,\(a0\),v4'
++.*Error: illegal operands vd cannot overlap vm `vsuxseg8ei8.v v0,\(a0\),v4,v0.t'
++.*Error: illegal operands vd cannot overlap vs2 `vluxseg2ei16.v v4,\(a0\),v4'
++.*Error: illegal operands vd cannot overlap vm `vluxseg2ei16.v v0,\(a0\),v4,v0.t'
++.*Error: illegal operands vd cannot overlap vs2 `vsuxseg2ei16.v v4,\(a0\),v4'
++.*Error: illegal operands vd cannot overlap vm `vsuxseg2ei16.v v0,\(a0\),v4,v0.t'
++.*Error: illegal operands vd cannot overlap vs2 `vluxseg3ei16.v v4,\(a0\),v4'
++.*Error: illegal operands vd cannot overlap vm `vluxseg3ei16.v v0,\(a0\),v4,v0.t'
++.*Error: illegal operands vd cannot overlap vs2 `vsuxseg3ei16.v v4,\(a0\),v4'
++.*Error: illegal operands vd cannot overlap vm `vsuxseg3ei16.v v0,\(a0\),v4,v0.t'
++.*Error: illegal operands vd cannot overlap vs2 `vluxseg4ei16.v v4,\(a0\),v4'
++.*Error: illegal operands vd cannot overlap vm `vluxseg4ei16.v v0,\(a0\),v4,v0.t'
++.*Error: illegal operands vd cannot overlap vs2 `vsuxseg4ei16.v v4,\(a0\),v4'
++.*Error: illegal operands vd cannot overlap vm `vsuxseg4ei16.v v0,\(a0\),v4,v0.t'
++.*Error: illegal operands vd cannot overlap vs2 `vluxseg5ei16.v v4,\(a0\),v4'
++.*Error: illegal operands vd cannot overlap vm `vluxseg5ei16.v v0,\(a0\),v4,v0.t'
++.*Error: illegal operands vd cannot overlap vs2 `vsuxseg5ei16.v v4,\(a0\),v4'
++.*Error: illegal operands vd cannot overlap vm `vsuxseg5ei16.v v0,\(a0\),v4,v0.t'
++.*Error: illegal operands vd cannot overlap vs2 `vluxseg6ei16.v v4,\(a0\),v4'
++.*Error: illegal operands vd cannot overlap vm `vluxseg6ei16.v v0,\(a0\),v4,v0.t'
++.*Error: illegal operands vd cannot overlap vs2 `vsuxseg6ei16.v v4,\(a0\),v4'
++.*Error: illegal operands vd cannot overlap vm `vsuxseg6ei16.v v0,\(a0\),v4,v0.t'
++.*Error: illegal operands vd cannot overlap vs2 `vluxseg7ei16.v v4,\(a0\),v4'
++.*Error: illegal operands vd cannot overlap vm `vluxseg7ei16.v v0,\(a0\),v4,v0.t'
++.*Error: illegal operands vd cannot overlap vs2 `vsuxseg7ei16.v v4,\(a0\),v4'
++.*Error: illegal operands vd cannot overlap vm `vsuxseg7ei16.v v0,\(a0\),v4,v0.t'
++.*Error: illegal operands vd cannot overlap vs2 `vluxseg8ei16.v v4,\(a0\),v4'
++.*Error: illegal operands vd cannot overlap vm `vluxseg8ei16.v v0,\(a0\),v4,v0.t'
++.*Error: illegal operands vd cannot overlap vs2 `vsuxseg8ei16.v v4,\(a0\),v4'
++.*Error: illegal operands vd cannot overlap vm `vsuxseg8ei16.v v0,\(a0\),v4,v0.t'
++.*Error: illegal operands vd cannot overlap vs2 `vluxseg2ei32.v v4,\(a0\),v4'
++.*Error: illegal operands vd cannot overlap vm `vluxseg2ei32.v v0,\(a0\),v4,v0.t'
++.*Error: illegal operands vd cannot overlap vs2 `vsuxseg2ei32.v v4,\(a0\),v4'
++.*Error: illegal operands vd cannot overlap vm `vsuxseg2ei32.v v0,\(a0\),v4,v0.t'
++.*Error: illegal operands vd cannot overlap vs2 `vluxseg3ei32.v v4,\(a0\),v4'
++.*Error: illegal operands vd cannot overlap vm `vluxseg3ei32.v v0,\(a0\),v4,v0.t'
++.*Error: illegal operands vd cannot overlap vs2 `vsuxseg3ei32.v v4,\(a0\),v4'
++.*Error: illegal operands vd cannot overlap vm `vsuxseg3ei32.v v0,\(a0\),v4,v0.t'
++.*Error: illegal operands vd cannot overlap vs2 `vluxseg4ei32.v v4,\(a0\),v4'
++.*Error: illegal operands vd cannot overlap vm `vluxseg4ei32.v v0,\(a0\),v4,v0.t'
++.*Error: illegal operands vd cannot overlap vs2 `vsuxseg4ei32.v v4,\(a0\),v4'
++.*Error: illegal operands vd cannot overlap vm `vsuxseg4ei32.v v0,\(a0\),v4,v0.t'
++.*Error: illegal operands vd cannot overlap vs2 `vluxseg5ei32.v v4,\(a0\),v4'
++.*Error: illegal operands vd cannot overlap vm `vluxseg5ei32.v v0,\(a0\),v4,v0.t'
++.*Error: illegal operands vd cannot overlap vs2 `vsuxseg5ei32.v v4,\(a0\),v4'
++.*Error: illegal operands vd cannot overlap vm `vsuxseg5ei32.v v0,\(a0\),v4,v0.t'
++.*Error: illegal operands vd cannot overlap vs2 `vluxseg6ei32.v v4,\(a0\),v4'
++.*Error: illegal operands vd cannot overlap vm `vluxseg6ei32.v v0,\(a0\),v4,v0.t'
++.*Error: illegal operands vd cannot overlap vs2 `vsuxseg6ei32.v v4,\(a0\),v4'
++.*Error: illegal operands vd cannot overlap vm `vsuxseg6ei32.v v0,\(a0\),v4,v0.t'
++.*Error: illegal operands vd cannot overlap vs2 `vluxseg7ei32.v v4,\(a0\),v4'
++.*Error: illegal operands vd cannot overlap vm `vluxseg7ei32.v v0,\(a0\),v4,v0.t'
++.*Error: illegal operands vd cannot overlap vs2 `vsuxseg7ei32.v v4,\(a0\),v4'
++.*Error: illegal operands vd cannot overlap vm `vsuxseg7ei32.v v0,\(a0\),v4,v0.t'
++.*Error: illegal operands vd cannot overlap vs2 `vluxseg8ei32.v v4,\(a0\),v4'
++.*Error: illegal operands vd cannot overlap vm `vluxseg8ei32.v v0,\(a0\),v4,v0.t'
++.*Error: illegal operands vd cannot overlap vs2 `vsuxseg8ei32.v v4,\(a0\),v4'
++.*Error: illegal operands vd cannot overlap vm `vsuxseg8ei32.v v0,\(a0\),v4,v0.t'
++.*Error: illegal operands vd cannot overlap vs2 `vluxseg2ei64.v v4,\(a0\),v4'
++.*Error: illegal operands vd cannot overlap vm `vluxseg2ei64.v v0,\(a0\),v4,v0.t'
++.*Error: illegal operands vd cannot overlap vs2 `vsuxseg2ei64.v v4,\(a0\),v4'
++.*Error: illegal operands vd cannot overlap vm `vsuxseg2ei64.v v0,\(a0\),v4,v0.t'
++.*Error: illegal operands vd cannot overlap vs2 `vluxseg3ei64.v v4,\(a0\),v4'
++.*Error: illegal operands vd cannot overlap vm `vluxseg3ei64.v v0,\(a0\),v4,v0.t'
++.*Error: illegal operands vd cannot overlap vs2 `vsuxseg3ei64.v v4,\(a0\),v4'
++.*Error: illegal operands vd cannot overlap vm `vsuxseg3ei64.v v0,\(a0\),v4,v0.t'
++.*Error: illegal operands vd cannot overlap vs2 `vluxseg4ei64.v v4,\(a0\),v4'
++.*Error: illegal operands vd cannot overlap vm `vluxseg4ei64.v v0,\(a0\),v4,v0.t'
++.*Error: illegal operands vd cannot overlap vs2 `vsuxseg4ei64.v v4,\(a0\),v4'
++.*Error: illegal operands vd cannot overlap vm `vsuxseg4ei64.v v0,\(a0\),v4,v0.t'
++.*Error: illegal operands vd cannot overlap vs2 `vluxseg5ei64.v v4,\(a0\),v4'
++.*Error: illegal operands vd cannot overlap vm `vluxseg5ei64.v v0,\(a0\),v4,v0.t'
++.*Error: illegal operands vd cannot overlap vs2 `vsuxseg5ei64.v v4,\(a0\),v4'
++.*Error: illegal operands vd cannot overlap vm `vsuxseg5ei64.v v0,\(a0\),v4,v0.t'
++.*Error: illegal operands vd cannot overlap vs2 `vluxseg6ei64.v v4,\(a0\),v4'
++.*Error: illegal operands vd cannot overlap vm `vluxseg6ei64.v v0,\(a0\),v4,v0.t'
++.*Error: illegal operands vd cannot overlap vs2 `vsuxseg6ei64.v v4,\(a0\),v4'
++.*Error: illegal operands vd cannot overlap vm `vsuxseg6ei64.v v0,\(a0\),v4,v0.t'
++.*Error: illegal operands vd cannot overlap vs2 `vluxseg7ei64.v v4,\(a0\),v4'
++.*Error: illegal operands vd cannot overlap vm `vluxseg7ei64.v v0,\(a0\),v4,v0.t'
++.*Error: illegal operands vd cannot overlap vs2 `vsuxseg7ei64.v v4,\(a0\),v4'
++.*Error: illegal operands vd cannot overlap vm `vsuxseg7ei64.v v0,\(a0\),v4,v0.t'
++.*Error: illegal operands vd cannot overlap vs2 `vluxseg8ei64.v v4,\(a0\),v4'
++.*Error: illegal operands vd cannot overlap vm `vluxseg8ei64.v v0,\(a0\),v4,v0.t'
++.*Error: illegal operands vd cannot overlap vs2 `vsuxseg8ei64.v v4,\(a0\),v4'
++.*Error: illegal operands vd cannot overlap vm `vsuxseg8ei64.v v0,\(a0\),v4,v0.t'
++.*Error: illegal operands vd cannot overlap vs2 `vluxseg2ei128.v v4,\(a0\),v4'
++.*Error: illegal operands vd cannot overlap vm `vluxseg2ei128.v v0,\(a0\),v4,v0.t'
++.*Error: illegal operands vd cannot overlap vs2 `vsuxseg2ei128.v v4,\(a0\),v4'
++.*Error: illegal operands vd cannot overlap vm `vsuxseg2ei128.v v0,\(a0\),v4,v0.t'
++.*Error: illegal operands vd cannot overlap vs2 `vluxseg3ei128.v v4,\(a0\),v4'
++.*Error: illegal operands vd cannot overlap vm `vluxseg3ei128.v v0,\(a0\),v4,v0.t'
++.*Error: illegal operands vd cannot overlap vs2 `vsuxseg3ei128.v v4,\(a0\),v4'
++.*Error: illegal operands vd cannot overlap vm `vsuxseg3ei128.v v0,\(a0\),v4,v0.t'
++.*Error: illegal operands vd cannot overlap vs2 `vluxseg4ei128.v v4,\(a0\),v4'
++.*Error: illegal operands vd cannot overlap vm `vluxseg4ei128.v v0,\(a0\),v4,v0.t'
++.*Error: illegal operands vd cannot overlap vs2 `vsuxseg4ei128.v v4,\(a0\),v4'
++.*Error: illegal operands vd cannot overlap vm `vsuxseg4ei128.v v0,\(a0\),v4,v0.t'
++.*Error: illegal operands vd cannot overlap vs2 `vluxseg5ei128.v v4,\(a0\),v4'
++.*Error: illegal operands vd cannot overlap vm `vluxseg5ei128.v v0,\(a0\),v4,v0.t'
++.*Error: illegal operands vd cannot overlap vs2 `vsuxseg5ei128.v v4,\(a0\),v4'
++.*Error: illegal operands vd cannot overlap vm `vsuxseg5ei128.v v0,\(a0\),v4,v0.t'
++.*Error: illegal operands vd cannot overlap vs2 `vluxseg6ei128.v v4,\(a0\),v4'
++.*Error: illegal operands vd cannot overlap vm `vluxseg6ei128.v v0,\(a0\),v4,v0.t'
++.*Error: illegal operands vd cannot overlap vs2 `vsuxseg6ei128.v v4,\(a0\),v4'
++.*Error: illegal operands vd cannot overlap vm `vsuxseg6ei128.v v0,\(a0\),v4,v0.t'
++.*Error: illegal operands vd cannot overlap vs2 `vluxseg7ei128.v v4,\(a0\),v4'
++.*Error: illegal operands vd cannot overlap vm `vluxseg7ei128.v v0,\(a0\),v4,v0.t'
++.*Error: illegal operands vd cannot overlap vs2 `vsuxseg7ei128.v v4,\(a0\),v4'
++.*Error: illegal operands vd cannot overlap vm `vsuxseg7ei128.v v0,\(a0\),v4,v0.t'
++.*Error: illegal operands vd cannot overlap vs2 `vluxseg8ei128.v v4,\(a0\),v4'
++.*Error: illegal operands vd cannot overlap vm `vluxseg8ei128.v v0,\(a0\),v4,v0.t'
++.*Error: illegal operands vd cannot overlap vs2 `vsuxseg8ei128.v v4,\(a0\),v4'
++.*Error: illegal operands vd cannot overlap vm `vsuxseg8ei128.v v0,\(a0\),v4,v0.t'
++.*Error: illegal operands vd cannot overlap vs2 `vluxseg2ei256.v v4,\(a0\),v4'
++.*Error: illegal operands vd cannot overlap vm `vluxseg2ei256.v v0,\(a0\),v4,v0.t'
++.*Error: illegal operands vd cannot overlap vs2 `vsuxseg2ei256.v v4,\(a0\),v4'
++.*Error: illegal operands vd cannot overlap vm `vsuxseg2ei256.v v0,\(a0\),v4,v0.t'
++.*Error: illegal operands vd cannot overlap vs2 `vluxseg3ei256.v v4,\(a0\),v4'
++.*Error: illegal operands vd cannot overlap vm `vluxseg3ei256.v v0,\(a0\),v4,v0.t'
++.*Error: illegal operands vd cannot overlap vs2 `vsuxseg3ei256.v v4,\(a0\),v4'
++.*Error: illegal operands vd cannot overlap vm `vsuxseg3ei256.v v0,\(a0\),v4,v0.t'
++.*Error: illegal operands vd cannot overlap vs2 `vluxseg4ei256.v v4,\(a0\),v4'
++.*Error: illegal operands vd cannot overlap vm `vluxseg4ei256.v v0,\(a0\),v4,v0.t'
++.*Error: illegal operands vd cannot overlap vs2 `vsuxseg4ei256.v v4,\(a0\),v4'
++.*Error: illegal operands vd cannot overlap vm `vsuxseg4ei256.v v0,\(a0\),v4,v0.t'
++.*Error: illegal operands vd cannot overlap vs2 `vluxseg5ei256.v v4,\(a0\),v4'
++.*Error: illegal operands vd cannot overlap vm `vluxseg5ei256.v v0,\(a0\),v4,v0.t'
++.*Error: illegal operands vd cannot overlap vs2 `vsuxseg5ei256.v v4,\(a0\),v4'
++.*Error: illegal operands vd cannot overlap vm `vsuxseg5ei256.v v0,\(a0\),v4,v0.t'
++.*Error: illegal operands vd cannot overlap vs2 `vluxseg6ei256.v v4,\(a0\),v4'
++.*Error: illegal operands vd cannot overlap vm `vluxseg6ei256.v v0,\(a0\),v4,v0.t'
++.*Error: illegal operands vd cannot overlap vs2 `vsuxseg6ei256.v v4,\(a0\),v4'
++.*Error: illegal operands vd cannot overlap vm `vsuxseg6ei256.v v0,\(a0\),v4,v0.t'
++.*Error: illegal operands vd cannot overlap vs2 `vluxseg7ei256.v v4,\(a0\),v4'
++.*Error: illegal operands vd cannot overlap vm `vluxseg7ei256.v v0,\(a0\),v4,v0.t'
++.*Error: illegal operands vd cannot overlap vs2 `vsuxseg7ei256.v v4,\(a0\),v4'
++.*Error: illegal operands vd cannot overlap vm `vsuxseg7ei256.v v0,\(a0\),v4,v0.t'
++.*Error: illegal operands vd cannot overlap vs2 `vluxseg8ei256.v v4,\(a0\),v4'
++.*Error: illegal operands vd cannot overlap vm `vluxseg8ei256.v v0,\(a0\),v4,v0.t'
++.*Error: illegal operands vd cannot overlap vs2 `vsuxseg8ei256.v v4,\(a0\),v4'
++.*Error: illegal operands vd cannot overlap vm `vsuxseg8ei256.v v0,\(a0\),v4,v0.t'
++.*Error: illegal operands vd cannot overlap vs2 `vluxseg2ei512.v v4,\(a0\),v4'
++.*Error: illegal operands vd cannot overlap vm `vluxseg2ei512.v v0,\(a0\),v4,v0.t'
++.*Error: illegal operands vd cannot overlap vs2 `vsuxseg2ei512.v v4,\(a0\),v4'
++.*Error: illegal operands vd cannot overlap vm `vsuxseg2ei512.v v0,\(a0\),v4,v0.t'
++.*Error: illegal operands vd cannot overlap vs2 `vluxseg3ei512.v v4,\(a0\),v4'
++.*Error: illegal operands vd cannot overlap vm `vluxseg3ei512.v v0,\(a0\),v4,v0.t'
++.*Error: illegal operands vd cannot overlap vs2 `vsuxseg3ei512.v v4,\(a0\),v4'
++.*Error: illegal operands vd cannot overlap vm `vsuxseg3ei512.v v0,\(a0\),v4,v0.t'
++.*Error: illegal operands vd cannot overlap vs2 `vluxseg4ei512.v v4,\(a0\),v4'
++.*Error: illegal operands vd cannot overlap vm `vluxseg4ei512.v v0,\(a0\),v4,v0.t'
++.*Error: illegal operands vd cannot overlap vs2 `vsuxseg4ei512.v v4,\(a0\),v4'
++.*Error: illegal operands vd cannot overlap vm `vsuxseg4ei512.v v0,\(a0\),v4,v0.t'
++.*Error: illegal operands vd cannot overlap vs2 `vluxseg5ei512.v v4,\(a0\),v4'
++.*Error: illegal operands vd cannot overlap vm `vluxseg5ei512.v v0,\(a0\),v4,v0.t'
++.*Error: illegal operands vd cannot overlap vs2 `vsuxseg5ei512.v v4,\(a0\),v4'
++.*Error: illegal operands vd cannot overlap vm `vsuxseg5ei512.v v0,\(a0\),v4,v0.t'
++.*Error: illegal operands vd cannot overlap vs2 `vluxseg6ei512.v v4,\(a0\),v4'
++.*Error: illegal operands vd cannot overlap vm `vluxseg6ei512.v v0,\(a0\),v4,v0.t'
++.*Error: illegal operands vd cannot overlap vs2 `vsuxseg6ei512.v v4,\(a0\),v4'
++.*Error: illegal operands vd cannot overlap vm `vsuxseg6ei512.v v0,\(a0\),v4,v0.t'
++.*Error: illegal operands vd cannot overlap vs2 `vluxseg7ei512.v v4,\(a0\),v4'
++.*Error: illegal operands vd cannot overlap vm `vluxseg7ei512.v v0,\(a0\),v4,v0.t'
++.*Error: illegal operands vd cannot overlap vs2 `vsuxseg7ei512.v v4,\(a0\),v4'
++.*Error: illegal operands vd cannot overlap vm `vsuxseg7ei512.v v0,\(a0\),v4,v0.t'
++.*Error: illegal operands vd cannot overlap vs2 `vluxseg8ei512.v v4,\(a0\),v4'
++.*Error: illegal operands vd cannot overlap vm `vluxseg8ei512.v v0,\(a0\),v4,v0.t'
++.*Error: illegal operands vd cannot overlap vs2 `vsuxseg8ei512.v v4,\(a0\),v4'
++.*Error: illegal operands vd cannot overlap vm `vsuxseg8ei512.v v0,\(a0\),v4,v0.t'
++.*Error: illegal operands vd cannot overlap vs2 `vluxseg2ei1024.v v4,\(a0\),v4'
++.*Error: illegal operands vd cannot overlap vm `vluxseg2ei1024.v v0,\(a0\),v4,v0.t'
++.*Error: illegal operands vd cannot overlap vs2 `vsuxseg2ei1024.v v4,\(a0\),v4'
++.*Error: illegal operands vd cannot overlap vm `vsuxseg2ei1024.v v0,\(a0\),v4,v0.t'
++.*Error: illegal operands vd cannot overlap vs2 `vluxseg3ei1024.v v4,\(a0\),v4'
++.*Error: illegal operands vd cannot overlap vm `vluxseg3ei1024.v v0,\(a0\),v4,v0.t'
++.*Error: illegal operands vd cannot overlap vs2 `vsuxseg3ei1024.v v4,\(a0\),v4'
++.*Error: illegal operands vd cannot overlap vm `vsuxseg3ei1024.v v0,\(a0\),v4,v0.t'
++.*Error: illegal operands vd cannot overlap vs2 `vluxseg4ei1024.v v4,\(a0\),v4'
++.*Error: illegal operands vd cannot overlap vm `vluxseg4ei1024.v v0,\(a0\),v4,v0.t'
++.*Error: illegal operands vd cannot overlap vs2 `vsuxseg4ei1024.v v4,\(a0\),v4'
++.*Error: illegal operands vd cannot overlap vm `vsuxseg4ei1024.v v0,\(a0\),v4,v0.t'
++.*Error: illegal operands vd cannot overlap vs2 `vluxseg5ei1024.v v4,\(a0\),v4'
++.*Error: illegal operands vd cannot overlap vm `vluxseg5ei1024.v v0,\(a0\),v4,v0.t'
++.*Error: illegal operands vd cannot overlap vs2 `vsuxseg5ei1024.v v4,\(a0\),v4'
++.*Error: illegal operands vd cannot overlap vm `vsuxseg5ei1024.v v0,\(a0\),v4,v0.t'
++.*Error: illegal operands vd cannot overlap vs2 `vluxseg6ei1024.v v4,\(a0\),v4'
++.*Error: illegal operands vd cannot overlap vm `vluxseg6ei1024.v v0,\(a0\),v4,v0.t'
++.*Error: illegal operands vd cannot overlap vs2 `vsuxseg6ei1024.v v4,\(a0\),v4'
++.*Error: illegal operands vd cannot overlap vm `vsuxseg6ei1024.v v0,\(a0\),v4,v0.t'
++.*Error: illegal operands vd cannot overlap vs2 `vluxseg7ei1024.v v4,\(a0\),v4'
++.*Error: illegal operands vd cannot overlap vm `vluxseg7ei1024.v v0,\(a0\),v4,v0.t'
++.*Error: illegal operands vd cannot overlap vs2 `vsuxseg7ei1024.v v4,\(a0\),v4'
++.*Error: illegal operands vd cannot overlap vm `vsuxseg7ei1024.v v0,\(a0\),v4,v0.t'
++.*Error: illegal operands vd cannot overlap vs2 `vluxseg8ei1024.v v4,\(a0\),v4'
++.*Error: illegal operands vd cannot overlap vm `vluxseg8ei1024.v v0,\(a0\),v4,v0.t'
++.*Error: illegal operands vd cannot overlap vs2 `vsuxseg8ei1024.v v4,\(a0\),v4'
++.*Error: illegal operands vd cannot overlap vm `vsuxseg8ei1024.v v0,\(a0\),v4,v0.t'
+ .*Error: illegal operands vd must be multiple of nf `vl2r.v v31,\(a0\)'
+ .*Error: illegal operands vd must be multiple of nf `vl2re8.v v31,\(a0\)'
+ .*Error: illegal operands vd must be multiple of nf `vl2re16.v v31,\(a0\)'
+diff --git a/gas/testsuite/gas/riscv/vector-insns-fail-load-store.s b/gas/testsuite/gas/riscv/vector-insns-fail-load-store.s
+index e4f1085174..85bcb3d03e 100644
+--- a/gas/testsuite/gas/riscv/vector-insns-fail-load-store.s
++++ b/gas/testsuite/gas/riscv/vector-insns-fail-load-store.s
+@@ -46,25 +46,36 @@
+ 	vsse512.v v0, (a0), a1, v0.t
+ 	vsse1024.v v0, (a0), a1, v0.t
+ 
+-# Vector Indexed Loads and Stores
+-
+-	vlxei8.v v4, (a0), v4		# OK
+-	vlxei8.v v0, (a0), v4, v0.t	# vd overlap vm
+-	vlxei16.v v4, (a0), v4
+-	vlxei16.v v0, (a0), v4, v0.t
+-	vlxei32.v v4, (a0), v4
+-	vlxei32.v v0, (a0), v4, v0.t
+-	vlxei64.v v4, (a0), v4
+-	vlxei64.v v0, (a0), v4, v0.t
+-
+-	vsxei8.v v4, (a0), v4
+-	vsxei8.v v0, (a0), v4, v0.t
+-	vsxei16.v v4, (a0), v4
+-	vsxei16.v v0, (a0), v4, v0.t
+-	vsxei32.v v4, (a0), v4
+-	vsxei32.v v0, (a0), v4, v0.t
+-	vsxei64.v v4, (a0), v4
+-	vsxei64.v v0, (a0), v4, v0.t
++# Vector Ordered Indexed Loads and Stores
++
++	vloxei8.v v4, (a0), v4		# OK
++	vloxei8.v v0, (a0), v4, v0.t	# vd overlap vm
++	vloxei16.v v4, (a0), v4
++	vloxei16.v v0, (a0), v4, v0.t
++	vloxei32.v v4, (a0), v4
++	vloxei32.v v0, (a0), v4, v0.t
++	vloxei64.v v4, (a0), v4
++	vloxei64.v v0, (a0), v4, v0.t
++
++	vsoxei8.v v4, (a0), v4
++	vsoxei8.v v0, (a0), v4, v0.t
++	vsoxei16.v v4, (a0), v4
++	vsoxei16.v v0, (a0), v4, v0.t
++	vsoxei32.v v4, (a0), v4
++	vsoxei32.v v0, (a0), v4, v0.t
++	vsoxei64.v v4, (a0), v4
++	vsoxei64.v v0, (a0), v4, v0.t
++
++# Vector Unordered Indexed Loads and Stores
++
++	vluxei8.v v4, (a0), v4		# OK
++	vluxei8.v v0, (a0), v4, v0.t	# vd overlap vm
++	vluxei16.v v4, (a0), v4
++	vluxei16.v v0, (a0), v4, v0.t
++	vluxei32.v v4, (a0), v4
++	vluxei32.v v0, (a0), v4, v0.t
++	vluxei64.v v4, (a0), v4
++	vluxei64.v v0, (a0), v4, v0.t
+ 
+ 	vsuxei8.v v4, (a0), v4
+ 	vsuxei8.v v0, (a0), v4, v0.t
+@@ -375,239 +386,473 @@
+ 	vlsseg8e1024.v v0, (a0), a1, v0.t
+ 	vssseg8e1024.v v0, (a0), a1, v0.t
+ 
+-# Vector Indexed Segment Loads and Stores
+-
+-	vlxseg2ei8.v v4, (a0), v4		# vd overlap vs2
+-	vlxseg2ei8.v v0, (a0), v4, v0.t		# vd overlap vm
+-	vsxseg2ei8.v v4, (a0), v4		# vd overlap vs2
+-	vsxseg2ei8.v v0, (a0), v4, v0.t		# vd overlap vm
+-	vlxseg3ei8.v v4, (a0), v4
+-	vlxseg3ei8.v v0, (a0), v4, v0.t
+-	vsxseg3ei8.v v4, (a0), v4
+-	vsxseg3ei8.v v0, (a0), v4, v0.t
+-	vlxseg4ei8.v v4, (a0), v4
+-	vlxseg4ei8.v v0, (a0), v4, v0.t
+-	vsxseg4ei8.v v4, (a0), v4
+-	vsxseg4ei8.v v0, (a0), v4, v0.t
+-	vlxseg5ei8.v v4, (a0), v4
+-	vlxseg5ei8.v v0, (a0), v4, v0.t
+-	vsxseg5ei8.v v4, (a0), v4
+-	vsxseg5ei8.v v0, (a0), v4, v0.t
+-	vlxseg6ei8.v v4, (a0), v4
+-	vlxseg6ei8.v v0, (a0), v4, v0.t
+-	vsxseg6ei8.v v4, (a0), v4
+-	vsxseg6ei8.v v0, (a0), v4, v0.t
+-	vlxseg7ei8.v v4, (a0), v4
+-	vlxseg7ei8.v v0, (a0), v4, v0.t
+-	vsxseg7ei8.v v4, (a0), v4
+-	vsxseg7ei8.v v0, (a0), v4, v0.t
+-	vlxseg8ei8.v v4, (a0), v4
+-	vlxseg8ei8.v v0, (a0), v4, v0.t
+-	vsxseg8ei8.v v4, (a0), v4
+-	vsxseg8ei8.v v0, (a0), v4, v0.t
+-
+-	vlxseg2ei16.v v4, (a0), v4
+-	vlxseg2ei16.v v0, (a0), v4, v0.t
+-	vsxseg2ei16.v v4, (a0), v4
+-	vsxseg2ei16.v v0, (a0), v4, v0.t
+-	vlxseg3ei16.v v4, (a0), v4
+-	vlxseg3ei16.v v0, (a0), v4, v0.t
+-	vsxseg3ei16.v v4, (a0), v4
+-	vsxseg3ei16.v v0, (a0), v4, v0.t
+-	vlxseg4ei16.v v4, (a0), v4
+-	vlxseg4ei16.v v0, (a0), v4, v0.t
+-	vsxseg4ei16.v v4, (a0), v4
+-	vsxseg4ei16.v v0, (a0), v4, v0.t
+-	vlxseg5ei16.v v4, (a0), v4
+-	vlxseg5ei16.v v0, (a0), v4, v0.t
+-	vsxseg5ei16.v v4, (a0), v4
+-	vsxseg5ei16.v v0, (a0), v4, v0.t
+-	vlxseg6ei16.v v4, (a0), v4
+-	vlxseg6ei16.v v0, (a0), v4, v0.t
+-	vsxseg6ei16.v v4, (a0), v4
+-	vsxseg6ei16.v v0, (a0), v4, v0.t
+-	vlxseg7ei16.v v4, (a0), v4
+-	vlxseg7ei16.v v0, (a0), v4, v0.t
+-	vsxseg7ei16.v v4, (a0), v4
+-	vsxseg7ei16.v v0, (a0), v4, v0.t
+-	vlxseg8ei16.v v4, (a0), v4
+-	vlxseg8ei16.v v0, (a0), v4, v0.t
+-	vsxseg8ei16.v v4, (a0), v4
+-	vsxseg8ei16.v v0, (a0), v4, v0.t
+-
+-	vlxseg2ei32.v v4, (a0), v4
+-	vlxseg2ei32.v v0, (a0), v4, v0.t
+-	vsxseg2ei32.v v4, (a0), v4
+-	vsxseg2ei32.v v0, (a0), v4, v0.t
+-	vlxseg3ei32.v v4, (a0), v4
+-	vlxseg3ei32.v v0, (a0), v4, v0.t
+-	vsxseg3ei32.v v4, (a0), v4
+-	vsxseg3ei32.v v0, (a0), v4, v0.t
+-	vlxseg4ei32.v v4, (a0), v4
+-	vlxseg4ei32.v v0, (a0), v4, v0.t
+-	vsxseg4ei32.v v4, (a0), v4
+-	vsxseg4ei32.v v0, (a0), v4, v0.t
+-	vlxseg5ei32.v v4, (a0), v4
+-	vlxseg5ei32.v v0, (a0), v4, v0.t
+-	vsxseg5ei32.v v4, (a0), v4
+-	vsxseg5ei32.v v0, (a0), v4, v0.t
+-	vlxseg6ei32.v v4, (a0), v4
+-	vlxseg6ei32.v v0, (a0), v4, v0.t
+-	vsxseg6ei32.v v4, (a0), v4
+-	vsxseg6ei32.v v0, (a0), v4, v0.t
+-	vlxseg7ei32.v v4, (a0), v4
+-	vlxseg7ei32.v v0, (a0), v4, v0.t
+-	vsxseg7ei32.v v4, (a0), v4
+-	vsxseg7ei32.v v0, (a0), v4, v0.t
+-	vlxseg8ei32.v v4, (a0), v4
+-	vlxseg8ei32.v v0, (a0), v4, v0.t
+-	vsxseg8ei32.v v4, (a0), v4
+-	vsxseg8ei32.v v0, (a0), v4, v0.t
+-
+-	vlxseg2ei64.v v4, (a0), v4
+-	vlxseg2ei64.v v0, (a0), v4, v0.t
+-	vsxseg2ei64.v v4, (a0), v4
+-	vsxseg2ei64.v v0, (a0), v4, v0.t
+-	vlxseg3ei64.v v4, (a0), v4
+-	vlxseg3ei64.v v0, (a0), v4, v0.t
+-	vsxseg3ei64.v v4, (a0), v4
+-	vsxseg3ei64.v v0, (a0), v4, v0.t
+-	vlxseg4ei64.v v4, (a0), v4
+-	vlxseg4ei64.v v0, (a0), v4, v0.t
+-	vsxseg4ei64.v v4, (a0), v4
+-	vsxseg4ei64.v v0, (a0), v4, v0.t
+-	vlxseg5ei64.v v4, (a0), v4
+-	vlxseg5ei64.v v0, (a0), v4, v0.t
+-	vsxseg5ei64.v v4, (a0), v4
+-	vsxseg5ei64.v v0, (a0), v4, v0.t
+-	vlxseg6ei64.v v4, (a0), v4
+-	vlxseg6ei64.v v0, (a0), v4, v0.t
+-	vsxseg6ei64.v v4, (a0), v4
+-	vsxseg6ei64.v v0, (a0), v4, v0.t
+-	vlxseg7ei64.v v4, (a0), v4
+-	vlxseg7ei64.v v0, (a0), v4, v0.t
+-	vsxseg7ei64.v v4, (a0), v4
+-	vsxseg7ei64.v v0, (a0), v4, v0.t
+-	vlxseg8ei64.v v4, (a0), v4
+-	vlxseg8ei64.v v0, (a0), v4, v0.t
+-	vsxseg8ei64.v v4, (a0), v4
+-	vsxseg8ei64.v v0, (a0), v4, v0.t
+-
+-	vlxseg2ei128.v v4, (a0), v4
+-	vlxseg2ei128.v v0, (a0), v4, v0.t
+-	vsxseg2ei128.v v4, (a0), v4
+-	vsxseg2ei128.v v0, (a0), v4, v0.t
+-	vlxseg3ei128.v v4, (a0), v4
+-	vlxseg3ei128.v v0, (a0), v4, v0.t
+-	vsxseg3ei128.v v4, (a0), v4
+-	vsxseg3ei128.v v0, (a0), v4, v0.t
+-	vlxseg4ei128.v v4, (a0), v4
+-	vlxseg4ei128.v v0, (a0), v4, v0.t
+-	vsxseg4ei128.v v4, (a0), v4
+-	vsxseg4ei128.v v0, (a0), v4, v0.t
+-	vlxseg5ei128.v v4, (a0), v4
+-	vlxseg5ei128.v v0, (a0), v4, v0.t
+-	vsxseg5ei128.v v4, (a0), v4
+-	vsxseg5ei128.v v0, (a0), v4, v0.t
+-	vlxseg6ei128.v v4, (a0), v4
+-	vlxseg6ei128.v v0, (a0), v4, v0.t
+-	vsxseg6ei128.v v4, (a0), v4
+-	vsxseg6ei128.v v0, (a0), v4, v0.t
+-	vlxseg7ei128.v v4, (a0), v4
+-	vlxseg7ei128.v v0, (a0), v4, v0.t
+-	vsxseg7ei128.v v4, (a0), v4
+-	vsxseg7ei128.v v0, (a0), v4, v0.t
+-	vlxseg8ei128.v v4, (a0), v4
+-	vlxseg8ei128.v v0, (a0), v4, v0.t
+-	vsxseg8ei128.v v4, (a0), v4
+-	vsxseg8ei128.v v0, (a0), v4, v0.t
+-
+-	vlxseg2ei256.v v4, (a0), v4
+-	vlxseg2ei256.v v0, (a0), v4, v0.t
+-	vsxseg2ei256.v v4, (a0), v4
+-	vsxseg2ei256.v v0, (a0), v4, v0.t
+-	vlxseg3ei256.v v4, (a0), v4
+-	vlxseg3ei256.v v0, (a0), v4, v0.t
+-	vsxseg3ei256.v v4, (a0), v4
+-	vsxseg3ei256.v v0, (a0), v4, v0.t
+-	vlxseg4ei256.v v4, (a0), v4
+-	vlxseg4ei256.v v0, (a0), v4, v0.t
+-	vsxseg4ei256.v v4, (a0), v4
+-	vsxseg4ei256.v v0, (a0), v4, v0.t
+-	vlxseg5ei256.v v4, (a0), v4
+-	vlxseg5ei256.v v0, (a0), v4, v0.t
+-	vsxseg5ei256.v v4, (a0), v4
+-	vsxseg5ei256.v v0, (a0), v4, v0.t
+-	vlxseg6ei256.v v4, (a0), v4
+-	vlxseg6ei256.v v0, (a0), v4, v0.t
+-	vsxseg6ei256.v v4, (a0), v4
+-	vsxseg6ei256.v v0, (a0), v4, v0.t
+-	vlxseg7ei256.v v4, (a0), v4
+-	vlxseg7ei256.v v0, (a0), v4, v0.t
+-	vsxseg7ei256.v v4, (a0), v4
+-	vsxseg7ei256.v v0, (a0), v4, v0.t
+-	vlxseg8ei256.v v4, (a0), v4
+-	vlxseg8ei256.v v0, (a0), v4, v0.t
+-	vsxseg8ei256.v v4, (a0), v4
+-	vsxseg8ei256.v v0, (a0), v4, v0.t
+-
+-	vlxseg2ei512.v v4, (a0), v4
+-	vlxseg2ei512.v v0, (a0), v4, v0.t
+-	vsxseg2ei512.v v4, (a0), v4
+-	vsxseg2ei512.v v0, (a0), v4, v0.t
+-	vlxseg3ei512.v v4, (a0), v4
+-	vlxseg3ei512.v v0, (a0), v4, v0.t
+-	vsxseg3ei512.v v4, (a0), v4
+-	vsxseg3ei512.v v0, (a0), v4, v0.t
+-	vlxseg4ei512.v v4, (a0), v4
+-	vlxseg4ei512.v v0, (a0), v4, v0.t
+-	vsxseg4ei512.v v4, (a0), v4
+-	vsxseg4ei512.v v0, (a0), v4, v0.t
+-	vlxseg5ei512.v v4, (a0), v4
+-	vlxseg5ei512.v v0, (a0), v4, v0.t
+-	vsxseg5ei512.v v4, (a0), v4
+-	vsxseg5ei512.v v0, (a0), v4, v0.t
+-	vlxseg6ei512.v v4, (a0), v4
+-	vlxseg6ei512.v v0, (a0), v4, v0.t
+-	vsxseg6ei512.v v4, (a0), v4
+-	vsxseg6ei512.v v0, (a0), v4, v0.t
+-	vlxseg7ei512.v v4, (a0), v4
+-	vlxseg7ei512.v v0, (a0), v4, v0.t
+-	vsxseg7ei512.v v4, (a0), v4
+-	vsxseg7ei512.v v0, (a0), v4, v0.t
+-	vlxseg8ei512.v v4, (a0), v4
+-	vlxseg8ei512.v v0, (a0), v4, v0.t
+-	vsxseg8ei512.v v4, (a0), v4
+-	vsxseg8ei512.v v0, (a0), v4, v0.t
+-
+-	vlxseg2ei1024.v v4, (a0), v4
+-	vlxseg2ei1024.v v0, (a0), v4, v0.t
+-	vsxseg2ei1024.v v4, (a0), v4
+-	vsxseg2ei1024.v v0, (a0), v4, v0.t
+-	vlxseg3ei1024.v v4, (a0), v4
+-	vlxseg3ei1024.v v0, (a0), v4, v0.t
+-	vsxseg3ei1024.v v4, (a0), v4
+-	vsxseg3ei1024.v v0, (a0), v4, v0.t
+-	vlxseg4ei1024.v v4, (a0), v4
+-	vlxseg4ei1024.v v0, (a0), v4, v0.t
+-	vsxseg4ei1024.v v4, (a0), v4
+-	vsxseg4ei1024.v v0, (a0), v4, v0.t
+-	vlxseg5ei1024.v v4, (a0), v4
+-	vlxseg5ei1024.v v0, (a0), v4, v0.t
+-	vsxseg5ei1024.v v4, (a0), v4
+-	vsxseg5ei1024.v v0, (a0), v4, v0.t
+-	vlxseg6ei1024.v v4, (a0), v4
+-	vlxseg6ei1024.v v0, (a0), v4, v0.t
+-	vsxseg6ei1024.v v4, (a0), v4
+-	vsxseg6ei1024.v v0, (a0), v4, v0.t
+-	vlxseg7ei1024.v v4, (a0), v4
+-	vlxseg7ei1024.v v0, (a0), v4, v0.t
+-	vsxseg7ei1024.v v4, (a0), v4
+-	vsxseg7ei1024.v v0, (a0), v4, v0.t
+-	vlxseg8ei1024.v v4, (a0), v4
+-	vlxseg8ei1024.v v0, (a0), v4, v0.t
+-	vsxseg8ei1024.v v4, (a0), v4
+-	vsxseg8ei1024.v v0, (a0), v4, v0.t
++# Vector Ordered Indexed Segment Loads and Stores
++
++	vloxseg2ei8.v v4, (a0), v4		# vd overlap vs2
++	vloxseg2ei8.v v0, (a0), v4, v0.t	# vd overlap vm
++	vsoxseg2ei8.v v4, (a0), v4		# vd overlap vs2
++	vsoxseg2ei8.v v0, (a0), v4, v0.t	# vd overlap vm
++	vloxseg3ei8.v v4, (a0), v4
++	vloxseg3ei8.v v0, (a0), v4, v0.t
++	vsoxseg3ei8.v v4, (a0), v4
++	vsoxseg3ei8.v v0, (a0), v4, v0.t
++	vloxseg4ei8.v v4, (a0), v4
++	vloxseg4ei8.v v0, (a0), v4, v0.t
++	vsoxseg4ei8.v v4, (a0), v4
++	vsoxseg4ei8.v v0, (a0), v4, v0.t
++	vloxseg5ei8.v v4, (a0), v4
++	vloxseg5ei8.v v0, (a0), v4, v0.t
++	vsoxseg5ei8.v v4, (a0), v4
++	vsoxseg5ei8.v v0, (a0), v4, v0.t
++	vloxseg6ei8.v v4, (a0), v4
++	vloxseg6ei8.v v0, (a0), v4, v0.t
++	vsoxseg6ei8.v v4, (a0), v4
++	vsoxseg6ei8.v v0, (a0), v4, v0.t
++	vloxseg7ei8.v v4, (a0), v4
++	vloxseg7ei8.v v0, (a0), v4, v0.t
++	vsoxseg7ei8.v v4, (a0), v4
++	vsoxseg7ei8.v v0, (a0), v4, v0.t
++	vloxseg8ei8.v v4, (a0), v4
++	vloxseg8ei8.v v0, (a0), v4, v0.t
++	vsoxseg8ei8.v v4, (a0), v4
++	vsoxseg8ei8.v v0, (a0), v4, v0.t
++
++	vloxseg2ei16.v v4, (a0), v4
++	vloxseg2ei16.v v0, (a0), v4, v0.t
++	vsoxseg2ei16.v v4, (a0), v4
++	vsoxseg2ei16.v v0, (a0), v4, v0.t
++	vloxseg3ei16.v v4, (a0), v4
++	vloxseg3ei16.v v0, (a0), v4, v0.t
++	vsoxseg3ei16.v v4, (a0), v4
++	vsoxseg3ei16.v v0, (a0), v4, v0.t
++	vloxseg4ei16.v v4, (a0), v4
++	vloxseg4ei16.v v0, (a0), v4, v0.t
++	vsoxseg4ei16.v v4, (a0), v4
++	vsoxseg4ei16.v v0, (a0), v4, v0.t
++	vloxseg5ei16.v v4, (a0), v4
++	vloxseg5ei16.v v0, (a0), v4, v0.t
++	vsoxseg5ei16.v v4, (a0), v4
++	vsoxseg5ei16.v v0, (a0), v4, v0.t
++	vloxseg6ei16.v v4, (a0), v4
++	vloxseg6ei16.v v0, (a0), v4, v0.t
++	vsoxseg6ei16.v v4, (a0), v4
++	vsoxseg6ei16.v v0, (a0), v4, v0.t
++	vloxseg7ei16.v v4, (a0), v4
++	vloxseg7ei16.v v0, (a0), v4, v0.t
++	vsoxseg7ei16.v v4, (a0), v4
++	vsoxseg7ei16.v v0, (a0), v4, v0.t
++	vloxseg8ei16.v v4, (a0), v4
++	vloxseg8ei16.v v0, (a0), v4, v0.t
++	vsoxseg8ei16.v v4, (a0), v4
++	vsoxseg8ei16.v v0, (a0), v4, v0.t
++
++	vloxseg2ei32.v v4, (a0), v4
++	vloxseg2ei32.v v0, (a0), v4, v0.t
++	vsoxseg2ei32.v v4, (a0), v4
++	vsoxseg2ei32.v v0, (a0), v4, v0.t
++	vloxseg3ei32.v v4, (a0), v4
++	vloxseg3ei32.v v0, (a0), v4, v0.t
++	vsoxseg3ei32.v v4, (a0), v4
++	vsoxseg3ei32.v v0, (a0), v4, v0.t
++	vloxseg4ei32.v v4, (a0), v4
++	vloxseg4ei32.v v0, (a0), v4, v0.t
++	vsoxseg4ei32.v v4, (a0), v4
++	vsoxseg4ei32.v v0, (a0), v4, v0.t
++	vloxseg5ei32.v v4, (a0), v4
++	vloxseg5ei32.v v0, (a0), v4, v0.t
++	vsoxseg5ei32.v v4, (a0), v4
++	vsoxseg5ei32.v v0, (a0), v4, v0.t
++	vloxseg6ei32.v v4, (a0), v4
++	vloxseg6ei32.v v0, (a0), v4, v0.t
++	vsoxseg6ei32.v v4, (a0), v4
++	vsoxseg6ei32.v v0, (a0), v4, v0.t
++	vloxseg7ei32.v v4, (a0), v4
++	vloxseg7ei32.v v0, (a0), v4, v0.t
++	vsoxseg7ei32.v v4, (a0), v4
++	vsoxseg7ei32.v v0, (a0), v4, v0.t
++	vloxseg8ei32.v v4, (a0), v4
++	vloxseg8ei32.v v0, (a0), v4, v0.t
++	vsoxseg8ei32.v v4, (a0), v4
++	vsoxseg8ei32.v v0, (a0), v4, v0.t
++
++	vloxseg2ei64.v v4, (a0), v4
++	vloxseg2ei64.v v0, (a0), v4, v0.t
++	vsoxseg2ei64.v v4, (a0), v4
++	vsoxseg2ei64.v v0, (a0), v4, v0.t
++	vloxseg3ei64.v v4, (a0), v4
++	vloxseg3ei64.v v0, (a0), v4, v0.t
++	vsoxseg3ei64.v v4, (a0), v4
++	vsoxseg3ei64.v v0, (a0), v4, v0.t
++	vloxseg4ei64.v v4, (a0), v4
++	vloxseg4ei64.v v0, (a0), v4, v0.t
++	vsoxseg4ei64.v v4, (a0), v4
++	vsoxseg4ei64.v v0, (a0), v4, v0.t
++	vloxseg5ei64.v v4, (a0), v4
++	vloxseg5ei64.v v0, (a0), v4, v0.t
++	vsoxseg5ei64.v v4, (a0), v4
++	vsoxseg5ei64.v v0, (a0), v4, v0.t
++	vloxseg6ei64.v v4, (a0), v4
++	vloxseg6ei64.v v0, (a0), v4, v0.t
++	vsoxseg6ei64.v v4, (a0), v4
++	vsoxseg6ei64.v v0, (a0), v4, v0.t
++	vloxseg7ei64.v v4, (a0), v4
++	vloxseg7ei64.v v0, (a0), v4, v0.t
++	vsoxseg7ei64.v v4, (a0), v4
++	vsoxseg7ei64.v v0, (a0), v4, v0.t
++	vloxseg8ei64.v v4, (a0), v4
++	vloxseg8ei64.v v0, (a0), v4, v0.t
++	vsoxseg8ei64.v v4, (a0), v4
++	vsoxseg8ei64.v v0, (a0), v4, v0.t
++
++	vloxseg2ei128.v v4, (a0), v4
++	vloxseg2ei128.v v0, (a0), v4, v0.t
++	vsoxseg2ei128.v v4, (a0), v4
++	vsoxseg2ei128.v v0, (a0), v4, v0.t
++	vloxseg3ei128.v v4, (a0), v4
++	vloxseg3ei128.v v0, (a0), v4, v0.t
++	vsoxseg3ei128.v v4, (a0), v4
++	vsoxseg3ei128.v v0, (a0), v4, v0.t
++	vloxseg4ei128.v v4, (a0), v4
++	vloxseg4ei128.v v0, (a0), v4, v0.t
++	vsoxseg4ei128.v v4, (a0), v4
++	vsoxseg4ei128.v v0, (a0), v4, v0.t
++	vloxseg5ei128.v v4, (a0), v4
++	vloxseg5ei128.v v0, (a0), v4, v0.t
++	vsoxseg5ei128.v v4, (a0), v4
++	vsoxseg5ei128.v v0, (a0), v4, v0.t
++	vloxseg6ei128.v v4, (a0), v4
++	vloxseg6ei128.v v0, (a0), v4, v0.t
++	vsoxseg6ei128.v v4, (a0), v4
++	vsoxseg6ei128.v v0, (a0), v4, v0.t
++	vloxseg7ei128.v v4, (a0), v4
++	vloxseg7ei128.v v0, (a0), v4, v0.t
++	vsoxseg7ei128.v v4, (a0), v4
++	vsoxseg7ei128.v v0, (a0), v4, v0.t
++	vloxseg8ei128.v v4, (a0), v4
++	vloxseg8ei128.v v0, (a0), v4, v0.t
++	vsoxseg8ei128.v v4, (a0), v4
++	vsoxseg8ei128.v v0, (a0), v4, v0.t
++
++	vloxseg2ei256.v v4, (a0), v4
++	vloxseg2ei256.v v0, (a0), v4, v0.t
++	vsoxseg2ei256.v v4, (a0), v4
++	vsoxseg2ei256.v v0, (a0), v4, v0.t
++	vloxseg3ei256.v v4, (a0), v4
++	vloxseg3ei256.v v0, (a0), v4, v0.t
++	vsoxseg3ei256.v v4, (a0), v4
++	vsoxseg3ei256.v v0, (a0), v4, v0.t
++	vloxseg4ei256.v v4, (a0), v4
++	vloxseg4ei256.v v0, (a0), v4, v0.t
++	vsoxseg4ei256.v v4, (a0), v4
++	vsoxseg4ei256.v v0, (a0), v4, v0.t
++	vloxseg5ei256.v v4, (a0), v4
++	vloxseg5ei256.v v0, (a0), v4, v0.t
++	vsoxseg5ei256.v v4, (a0), v4
++	vsoxseg5ei256.v v0, (a0), v4, v0.t
++	vloxseg6ei256.v v4, (a0), v4
++	vloxseg6ei256.v v0, (a0), v4, v0.t
++	vsoxseg6ei256.v v4, (a0), v4
++	vsoxseg6ei256.v v0, (a0), v4, v0.t
++	vloxseg7ei256.v v4, (a0), v4
++	vloxseg7ei256.v v0, (a0), v4, v0.t
++	vsoxseg7ei256.v v4, (a0), v4
++	vsoxseg7ei256.v v0, (a0), v4, v0.t
++	vloxseg8ei256.v v4, (a0), v4
++	vloxseg8ei256.v v0, (a0), v4, v0.t
++	vsoxseg8ei256.v v4, (a0), v4
++	vsoxseg8ei256.v v0, (a0), v4, v0.t
++
++	vloxseg2ei512.v v4, (a0), v4
++	vloxseg2ei512.v v0, (a0), v4, v0.t
++	vsoxseg2ei512.v v4, (a0), v4
++	vsoxseg2ei512.v v0, (a0), v4, v0.t
++	vloxseg3ei512.v v4, (a0), v4
++	vloxseg3ei512.v v0, (a0), v4, v0.t
++	vsoxseg3ei512.v v4, (a0), v4
++	vsoxseg3ei512.v v0, (a0), v4, v0.t
++	vloxseg4ei512.v v4, (a0), v4
++	vloxseg4ei512.v v0, (a0), v4, v0.t
++	vsoxseg4ei512.v v4, (a0), v4
++	vsoxseg4ei512.v v0, (a0), v4, v0.t
++	vloxseg5ei512.v v4, (a0), v4
++	vloxseg5ei512.v v0, (a0), v4, v0.t
++	vsoxseg5ei512.v v4, (a0), v4
++	vsoxseg5ei512.v v0, (a0), v4, v0.t
++	vloxseg6ei512.v v4, (a0), v4
++	vloxseg6ei512.v v0, (a0), v4, v0.t
++	vsoxseg6ei512.v v4, (a0), v4
++	vsoxseg6ei512.v v0, (a0), v4, v0.t
++	vloxseg7ei512.v v4, (a0), v4
++	vloxseg7ei512.v v0, (a0), v4, v0.t
++	vsoxseg7ei512.v v4, (a0), v4
++	vsoxseg7ei512.v v0, (a0), v4, v0.t
++	vloxseg8ei512.v v4, (a0), v4
++	vloxseg8ei512.v v0, (a0), v4, v0.t
++	vsoxseg8ei512.v v4, (a0), v4
++	vsoxseg8ei512.v v0, (a0), v4, v0.t
++
++	vloxseg2ei1024.v v4, (a0), v4
++	vloxseg2ei1024.v v0, (a0), v4, v0.t
++	vsoxseg2ei1024.v v4, (a0), v4
++	vsoxseg2ei1024.v v0, (a0), v4, v0.t
++	vloxseg3ei1024.v v4, (a0), v4
++	vloxseg3ei1024.v v0, (a0), v4, v0.t
++	vsoxseg3ei1024.v v4, (a0), v4
++	vsoxseg3ei1024.v v0, (a0), v4, v0.t
++	vloxseg4ei1024.v v4, (a0), v4
++	vloxseg4ei1024.v v0, (a0), v4, v0.t
++	vsoxseg4ei1024.v v4, (a0), v4
++	vsoxseg4ei1024.v v0, (a0), v4, v0.t
++	vloxseg5ei1024.v v4, (a0), v4
++	vloxseg5ei1024.v v0, (a0), v4, v0.t
++	vsoxseg5ei1024.v v4, (a0), v4
++	vsoxseg5ei1024.v v0, (a0), v4, v0.t
++	vloxseg6ei1024.v v4, (a0), v4
++	vloxseg6ei1024.v v0, (a0), v4, v0.t
++	vsoxseg6ei1024.v v4, (a0), v4
++	vsoxseg6ei1024.v v0, (a0), v4, v0.t
++	vloxseg7ei1024.v v4, (a0), v4
++	vloxseg7ei1024.v v0, (a0), v4, v0.t
++	vsoxseg7ei1024.v v4, (a0), v4
++	vsoxseg7ei1024.v v0, (a0), v4, v0.t
++	vloxseg8ei1024.v v4, (a0), v4
++	vloxseg8ei1024.v v0, (a0), v4, v0.t
++	vsoxseg8ei1024.v v4, (a0), v4
++	vsoxseg8ei1024.v v0, (a0), v4, v0.t
++
++# Vector Unordered Indexed Segment Loads and Stores
++
++	vluxseg2ei8.v v4, (a0), v4		# vd overlap vs2
++	vluxseg2ei8.v v0, (a0), v4, v0.t	# vd overlap vm
++	vsuxseg2ei8.v v4, (a0), v4		# vd overlap vs2
++	vsuxseg2ei8.v v0, (a0), v4, v0.t	# vd overlap vm
++	vluxseg3ei8.v v4, (a0), v4
++	vluxseg3ei8.v v0, (a0), v4, v0.t
++	vsuxseg3ei8.v v4, (a0), v4
++	vsuxseg3ei8.v v0, (a0), v4, v0.t
++	vluxseg4ei8.v v4, (a0), v4
++	vluxseg4ei8.v v0, (a0), v4, v0.t
++	vsuxseg4ei8.v v4, (a0), v4
++	vsuxseg4ei8.v v0, (a0), v4, v0.t
++	vluxseg5ei8.v v4, (a0), v4
++	vluxseg5ei8.v v0, (a0), v4, v0.t
++	vsuxseg5ei8.v v4, (a0), v4
++	vsuxseg5ei8.v v0, (a0), v4, v0.t
++	vluxseg6ei8.v v4, (a0), v4
++	vluxseg6ei8.v v0, (a0), v4, v0.t
++	vsuxseg6ei8.v v4, (a0), v4
++	vsuxseg6ei8.v v0, (a0), v4, v0.t
++	vluxseg7ei8.v v4, (a0), v4
++	vluxseg7ei8.v v0, (a0), v4, v0.t
++	vsuxseg7ei8.v v4, (a0), v4
++	vsuxseg7ei8.v v0, (a0), v4, v0.t
++	vluxseg8ei8.v v4, (a0), v4
++	vluxseg8ei8.v v0, (a0), v4, v0.t
++	vsuxseg8ei8.v v4, (a0), v4
++	vsuxseg8ei8.v v0, (a0), v4, v0.t
++
++	vluxseg2ei16.v v4, (a0), v4
++	vluxseg2ei16.v v0, (a0), v4, v0.t
++	vsuxseg2ei16.v v4, (a0), v4
++	vsuxseg2ei16.v v0, (a0), v4, v0.t
++	vluxseg3ei16.v v4, (a0), v4
++	vluxseg3ei16.v v0, (a0), v4, v0.t
++	vsuxseg3ei16.v v4, (a0), v4
++	vsuxseg3ei16.v v0, (a0), v4, v0.t
++	vluxseg4ei16.v v4, (a0), v4
++	vluxseg4ei16.v v0, (a0), v4, v0.t
++	vsuxseg4ei16.v v4, (a0), v4
++	vsuxseg4ei16.v v0, (a0), v4, v0.t
++	vluxseg5ei16.v v4, (a0), v4
++	vluxseg5ei16.v v0, (a0), v4, v0.t
++	vsuxseg5ei16.v v4, (a0), v4
++	vsuxseg5ei16.v v0, (a0), v4, v0.t
++	vluxseg6ei16.v v4, (a0), v4
++	vluxseg6ei16.v v0, (a0), v4, v0.t
++	vsuxseg6ei16.v v4, (a0), v4
++	vsuxseg6ei16.v v0, (a0), v4, v0.t
++	vluxseg7ei16.v v4, (a0), v4
++	vluxseg7ei16.v v0, (a0), v4, v0.t
++	vsuxseg7ei16.v v4, (a0), v4
++	vsuxseg7ei16.v v0, (a0), v4, v0.t
++	vluxseg8ei16.v v4, (a0), v4
++	vluxseg8ei16.v v0, (a0), v4, v0.t
++	vsuxseg8ei16.v v4, (a0), v4
++	vsuxseg8ei16.v v0, (a0), v4, v0.t
++
++	vluxseg2ei32.v v4, (a0), v4
++	vluxseg2ei32.v v0, (a0), v4, v0.t
++	vsuxseg2ei32.v v4, (a0), v4
++	vsuxseg2ei32.v v0, (a0), v4, v0.t
++	vluxseg3ei32.v v4, (a0), v4
++	vluxseg3ei32.v v0, (a0), v4, v0.t
++	vsuxseg3ei32.v v4, (a0), v4
++	vsuxseg3ei32.v v0, (a0), v4, v0.t
++	vluxseg4ei32.v v4, (a0), v4
++	vluxseg4ei32.v v0, (a0), v4, v0.t
++	vsuxseg4ei32.v v4, (a0), v4
++	vsuxseg4ei32.v v0, (a0), v4, v0.t
++	vluxseg5ei32.v v4, (a0), v4
++	vluxseg5ei32.v v0, (a0), v4, v0.t
++	vsuxseg5ei32.v v4, (a0), v4
++	vsuxseg5ei32.v v0, (a0), v4, v0.t
++	vluxseg6ei32.v v4, (a0), v4
++	vluxseg6ei32.v v0, (a0), v4, v0.t
++	vsuxseg6ei32.v v4, (a0), v4
++	vsuxseg6ei32.v v0, (a0), v4, v0.t
++	vluxseg7ei32.v v4, (a0), v4
++	vluxseg7ei32.v v0, (a0), v4, v0.t
++	vsuxseg7ei32.v v4, (a0), v4
++	vsuxseg7ei32.v v0, (a0), v4, v0.t
++	vluxseg8ei32.v v4, (a0), v4
++	vluxseg8ei32.v v0, (a0), v4, v0.t
++	vsuxseg8ei32.v v4, (a0), v4
++	vsuxseg8ei32.v v0, (a0), v4, v0.t
++
++	vluxseg2ei64.v v4, (a0), v4
++	vluxseg2ei64.v v0, (a0), v4, v0.t
++	vsuxseg2ei64.v v4, (a0), v4
++	vsuxseg2ei64.v v0, (a0), v4, v0.t
++	vluxseg3ei64.v v4, (a0), v4
++	vluxseg3ei64.v v0, (a0), v4, v0.t
++	vsuxseg3ei64.v v4, (a0), v4
++	vsuxseg3ei64.v v0, (a0), v4, v0.t
++	vluxseg4ei64.v v4, (a0), v4
++	vluxseg4ei64.v v0, (a0), v4, v0.t
++	vsuxseg4ei64.v v4, (a0), v4
++	vsuxseg4ei64.v v0, (a0), v4, v0.t
++	vluxseg5ei64.v v4, (a0), v4
++	vluxseg5ei64.v v0, (a0), v4, v0.t
++	vsuxseg5ei64.v v4, (a0), v4
++	vsuxseg5ei64.v v0, (a0), v4, v0.t
++	vluxseg6ei64.v v4, (a0), v4
++	vluxseg6ei64.v v0, (a0), v4, v0.t
++	vsuxseg6ei64.v v4, (a0), v4
++	vsuxseg6ei64.v v0, (a0), v4, v0.t
++	vluxseg7ei64.v v4, (a0), v4
++	vluxseg7ei64.v v0, (a0), v4, v0.t
++	vsuxseg7ei64.v v4, (a0), v4
++	vsuxseg7ei64.v v0, (a0), v4, v0.t
++	vluxseg8ei64.v v4, (a0), v4
++	vluxseg8ei64.v v0, (a0), v4, v0.t
++	vsuxseg8ei64.v v4, (a0), v4
++	vsuxseg8ei64.v v0, (a0), v4, v0.t
++
++	vluxseg2ei128.v v4, (a0), v4
++	vluxseg2ei128.v v0, (a0), v4, v0.t
++	vsuxseg2ei128.v v4, (a0), v4
++	vsuxseg2ei128.v v0, (a0), v4, v0.t
++	vluxseg3ei128.v v4, (a0), v4
++	vluxseg3ei128.v v0, (a0), v4, v0.t
++	vsuxseg3ei128.v v4, (a0), v4
++	vsuxseg3ei128.v v0, (a0), v4, v0.t
++	vluxseg4ei128.v v4, (a0), v4
++	vluxseg4ei128.v v0, (a0), v4, v0.t
++	vsuxseg4ei128.v v4, (a0), v4
++	vsuxseg4ei128.v v0, (a0), v4, v0.t
++	vluxseg5ei128.v v4, (a0), v4
++	vluxseg5ei128.v v0, (a0), v4, v0.t
++	vsuxseg5ei128.v v4, (a0), v4
++	vsuxseg5ei128.v v0, (a0), v4, v0.t
++	vluxseg6ei128.v v4, (a0), v4
++	vluxseg6ei128.v v0, (a0), v4, v0.t
++	vsuxseg6ei128.v v4, (a0), v4
++	vsuxseg6ei128.v v0, (a0), v4, v0.t
++	vluxseg7ei128.v v4, (a0), v4
++	vluxseg7ei128.v v0, (a0), v4, v0.t
++	vsuxseg7ei128.v v4, (a0), v4
++	vsuxseg7ei128.v v0, (a0), v4, v0.t
++	vluxseg8ei128.v v4, (a0), v4
++	vluxseg8ei128.v v0, (a0), v4, v0.t
++	vsuxseg8ei128.v v4, (a0), v4
++	vsuxseg8ei128.v v0, (a0), v4, v0.t
++
++	vluxseg2ei256.v v4, (a0), v4
++	vluxseg2ei256.v v0, (a0), v4, v0.t
++	vsuxseg2ei256.v v4, (a0), v4
++	vsuxseg2ei256.v v0, (a0), v4, v0.t
++	vluxseg3ei256.v v4, (a0), v4
++	vluxseg3ei256.v v0, (a0), v4, v0.t
++	vsuxseg3ei256.v v4, (a0), v4
++	vsuxseg3ei256.v v0, (a0), v4, v0.t
++	vluxseg4ei256.v v4, (a0), v4
++	vluxseg4ei256.v v0, (a0), v4, v0.t
++	vsuxseg4ei256.v v4, (a0), v4
++	vsuxseg4ei256.v v0, (a0), v4, v0.t
++	vluxseg5ei256.v v4, (a0), v4
++	vluxseg5ei256.v v0, (a0), v4, v0.t
++	vsuxseg5ei256.v v4, (a0), v4
++	vsuxseg5ei256.v v0, (a0), v4, v0.t
++	vluxseg6ei256.v v4, (a0), v4
++	vluxseg6ei256.v v0, (a0), v4, v0.t
++	vsuxseg6ei256.v v4, (a0), v4
++	vsuxseg6ei256.v v0, (a0), v4, v0.t
++	vluxseg7ei256.v v4, (a0), v4
++	vluxseg7ei256.v v0, (a0), v4, v0.t
++	vsuxseg7ei256.v v4, (a0), v4
++	vsuxseg7ei256.v v0, (a0), v4, v0.t
++	vluxseg8ei256.v v4, (a0), v4
++	vluxseg8ei256.v v0, (a0), v4, v0.t
++	vsuxseg8ei256.v v4, (a0), v4
++	vsuxseg8ei256.v v0, (a0), v4, v0.t
++
++	vluxseg2ei512.v v4, (a0), v4
++	vluxseg2ei512.v v0, (a0), v4, v0.t
++	vsuxseg2ei512.v v4, (a0), v4
++	vsuxseg2ei512.v v0, (a0), v4, v0.t
++	vluxseg3ei512.v v4, (a0), v4
++	vluxseg3ei512.v v0, (a0), v4, v0.t
++	vsuxseg3ei512.v v4, (a0), v4
++	vsuxseg3ei512.v v0, (a0), v4, v0.t
++	vluxseg4ei512.v v4, (a0), v4
++	vluxseg4ei512.v v0, (a0), v4, v0.t
++	vsuxseg4ei512.v v4, (a0), v4
++	vsuxseg4ei512.v v0, (a0), v4, v0.t
++	vluxseg5ei512.v v4, (a0), v4
++	vluxseg5ei512.v v0, (a0), v4, v0.t
++	vsuxseg5ei512.v v4, (a0), v4
++	vsuxseg5ei512.v v0, (a0), v4, v0.t
++	vluxseg6ei512.v v4, (a0), v4
++	vluxseg6ei512.v v0, (a0), v4, v0.t
++	vsuxseg6ei512.v v4, (a0), v4
++	vsuxseg6ei512.v v0, (a0), v4, v0.t
++	vluxseg7ei512.v v4, (a0), v4
++	vluxseg7ei512.v v0, (a0), v4, v0.t
++	vsuxseg7ei512.v v4, (a0), v4
++	vsuxseg7ei512.v v0, (a0), v4, v0.t
++	vluxseg8ei512.v v4, (a0), v4
++	vluxseg8ei512.v v0, (a0), v4, v0.t
++	vsuxseg8ei512.v v4, (a0), v4
++	vsuxseg8ei512.v v0, (a0), v4, v0.t
++
++	vluxseg2ei1024.v v4, (a0), v4
++	vluxseg2ei1024.v v0, (a0), v4, v0.t
++	vsuxseg2ei1024.v v4, (a0), v4
++	vsuxseg2ei1024.v v0, (a0), v4, v0.t
++	vluxseg3ei1024.v v4, (a0), v4
++	vluxseg3ei1024.v v0, (a0), v4, v0.t
++	vsuxseg3ei1024.v v4, (a0), v4
++	vsuxseg3ei1024.v v0, (a0), v4, v0.t
++	vluxseg4ei1024.v v4, (a0), v4
++	vluxseg4ei1024.v v0, (a0), v4, v0.t
++	vsuxseg4ei1024.v v4, (a0), v4
++	vsuxseg4ei1024.v v0, (a0), v4, v0.t
++	vluxseg5ei1024.v v4, (a0), v4
++	vluxseg5ei1024.v v0, (a0), v4, v0.t
++	vsuxseg5ei1024.v v4, (a0), v4
++	vsuxseg5ei1024.v v0, (a0), v4, v0.t
++	vluxseg6ei1024.v v4, (a0), v4
++	vluxseg6ei1024.v v0, (a0), v4, v0.t
++	vsuxseg6ei1024.v v4, (a0), v4
++	vsuxseg6ei1024.v v0, (a0), v4, v0.t
++	vluxseg7ei1024.v v4, (a0), v4
++	vluxseg7ei1024.v v0, (a0), v4, v0.t
++	vsuxseg7ei1024.v v4, (a0), v4
++	vsuxseg7ei1024.v v0, (a0), v4, v0.t
++	vluxseg8ei1024.v v4, (a0), v4
++	vluxseg8ei1024.v v0, (a0), v4, v0.t
++	vsuxseg8ei1024.v v4, (a0), v4
++	vsuxseg8ei1024.v v0, (a0), v4, v0.t
+ 
+ # Vector Load/Store Whole Register Instructions
+ 
+diff --git a/gas/testsuite/gas/riscv/vector-insns.d b/gas/testsuite/gas/riscv/vector-insns.d
+index 29a38b3716..d8a8aa6d09 100644
+--- a/gas/testsuite/gas/riscv/vector-insns.d
++++ b/gas/testsuite/gas/riscv/vector-insns.d
+@@ -122,39 +122,51 @@ Disassembly of section .text:
+ [ 	]+[0-9a-f]+:[ 	]+1ab57227[ 	]+vsse1024.v[ 	]+v4,\(a0\),a1
+ [ 	]+[0-9a-f]+:[ 	]+1ab57227[ 	]+vsse1024.v[ 	]+v4,\(a0\),a1
+ [ 	]+[0-9a-f]+:[ 	]+18b57227[ 	]+vsse1024.v[ 	]+v4,\(a0\),a1,v0.t
+-[ 	]+[0-9a-f]+:[ 	]+0ec50207[ 	]+vlxei8.v[ 	]+v4,\(a0\),v12
+-[ 	]+[0-9a-f]+:[ 	]+0ec50207[ 	]+vlxei8.v[ 	]+v4,\(a0\),v12
+-[ 	]+[0-9a-f]+:[ 	]+0cc50207[ 	]+vlxei8.v[ 	]+v4,\(a0\),v12,v0.t
+-[ 	]+[0-9a-f]+:[ 	]+0ec50227[ 	]+vsxei8.v[ 	]+v4,\(a0\),v12
+-[ 	]+[0-9a-f]+:[ 	]+0ec50227[ 	]+vsxei8.v[ 	]+v4,\(a0\),v12
+-[ 	]+[0-9a-f]+:[ 	]+0cc50227[ 	]+vsxei8.v[ 	]+v4,\(a0\),v12,v0.t
++[ 	]+[0-9a-f]+:[ 	]+0ec50207[ 	]+vloxei8.v[ 	]+v4,\(a0\),v12
++[ 	]+[0-9a-f]+:[ 	]+0ec50207[ 	]+vloxei8.v[ 	]+v4,\(a0\),v12
++[ 	]+[0-9a-f]+:[ 	]+0cc50207[ 	]+vloxei8.v[ 	]+v4,\(a0\),v12,v0.t
++[ 	]+[0-9a-f]+:[ 	]+0ec50227[ 	]+vsoxei8.v[ 	]+v4,\(a0\),v12
++[ 	]+[0-9a-f]+:[ 	]+0ec50227[ 	]+vsoxei8.v[ 	]+v4,\(a0\),v12
++[ 	]+[0-9a-f]+:[ 	]+0cc50227[ 	]+vsoxei8.v[ 	]+v4,\(a0\),v12,v0.t
++[ 	]+[0-9a-f]+:[ 	]+06c50207[ 	]+vluxei8.v[ 	]+v4,\(a0\),v12
++[ 	]+[0-9a-f]+:[ 	]+06c50207[ 	]+vluxei8.v[ 	]+v4,\(a0\),v12
++[ 	]+[0-9a-f]+:[ 	]+04c50207[ 	]+vluxei8.v[ 	]+v4,\(a0\),v12,v0.t
+ [ 	]+[0-9a-f]+:[ 	]+06c50227[ 	]+vsuxei8.v[ 	]+v4,\(a0\),v12
+ [ 	]+[0-9a-f]+:[ 	]+06c50227[ 	]+vsuxei8.v[ 	]+v4,\(a0\),v12
+ [ 	]+[0-9a-f]+:[ 	]+04c50227[ 	]+vsuxei8.v[ 	]+v4,\(a0\),v12,v0.t
+-[ 	]+[0-9a-f]+:[ 	]+0ec55207[ 	]+vlxei16.v[ 	]+v4,\(a0\),v12
+-[ 	]+[0-9a-f]+:[ 	]+0ec55207[ 	]+vlxei16.v[ 	]+v4,\(a0\),v12
+-[ 	]+[0-9a-f]+:[ 	]+0cc55207[ 	]+vlxei16.v[ 	]+v4,\(a0\),v12,v0.t
+-[ 	]+[0-9a-f]+:[ 	]+0ec55227[ 	]+vsxei16.v[ 	]+v4,\(a0\),v12
+-[ 	]+[0-9a-f]+:[ 	]+0ec55227[ 	]+vsxei16.v[ 	]+v4,\(a0\),v12
+-[ 	]+[0-9a-f]+:[ 	]+0cc55227[ 	]+vsxei16.v[ 	]+v4,\(a0\),v12,v0.t
++[ 	]+[0-9a-f]+:[ 	]+0ec55207[ 	]+vloxei16.v[ 	]+v4,\(a0\),v12
++[ 	]+[0-9a-f]+:[ 	]+0ec55207[ 	]+vloxei16.v[ 	]+v4,\(a0\),v12
++[ 	]+[0-9a-f]+:[ 	]+0cc55207[ 	]+vloxei16.v[ 	]+v4,\(a0\),v12,v0.t
++[ 	]+[0-9a-f]+:[ 	]+0ec55227[ 	]+vsoxei16.v[ 	]+v4,\(a0\),v12
++[ 	]+[0-9a-f]+:[ 	]+0ec55227[ 	]+vsoxei16.v[ 	]+v4,\(a0\),v12
++[ 	]+[0-9a-f]+:[ 	]+0cc55227[ 	]+vsoxei16.v[ 	]+v4,\(a0\),v12,v0.t
++[ 	]+[0-9a-f]+:[ 	]+06c55207[ 	]+vluxei16.v[ 	]+v4,\(a0\),v12
++[ 	]+[0-9a-f]+:[ 	]+06c55207[ 	]+vluxei16.v[ 	]+v4,\(a0\),v12
++[ 	]+[0-9a-f]+:[ 	]+04c55207[ 	]+vluxei16.v[ 	]+v4,\(a0\),v12,v0.t
+ [ 	]+[0-9a-f]+:[ 	]+06c55227[ 	]+vsuxei16.v[ 	]+v4,\(a0\),v12
+ [ 	]+[0-9a-f]+:[ 	]+06c55227[ 	]+vsuxei16.v[ 	]+v4,\(a0\),v12
+ [ 	]+[0-9a-f]+:[ 	]+04c55227[ 	]+vsuxei16.v[ 	]+v4,\(a0\),v12,v0.t
+-[ 	]+[0-9a-f]+:[ 	]+0ec56207[ 	]+vlxei32.v[ 	]+v4,\(a0\),v12
+-[ 	]+[0-9a-f]+:[ 	]+0ec56207[ 	]+vlxei32.v[ 	]+v4,\(a0\),v12
+-[ 	]+[0-9a-f]+:[ 	]+0cc56207[ 	]+vlxei32.v[ 	]+v4,\(a0\),v12,v0.t
+-[ 	]+[0-9a-f]+:[ 	]+0ec56227[ 	]+vsxei32.v[ 	]+v4,\(a0\),v12
+-[ 	]+[0-9a-f]+:[ 	]+0ec56227[ 	]+vsxei32.v[ 	]+v4,\(a0\),v12
+-[ 	]+[0-9a-f]+:[ 	]+0cc56227[ 	]+vsxei32.v[ 	]+v4,\(a0\),v12,v0.t
++[ 	]+[0-9a-f]+:[ 	]+0ec56207[ 	]+vloxei32.v[ 	]+v4,\(a0\),v12
++[ 	]+[0-9a-f]+:[ 	]+0ec56207[ 	]+vloxei32.v[ 	]+v4,\(a0\),v12
++[ 	]+[0-9a-f]+:[ 	]+0cc56207[ 	]+vloxei32.v[ 	]+v4,\(a0\),v12,v0.t
++[ 	]+[0-9a-f]+:[ 	]+0ec56227[ 	]+vsoxei32.v[ 	]+v4,\(a0\),v12
++[ 	]+[0-9a-f]+:[ 	]+0ec56227[ 	]+vsoxei32.v[ 	]+v4,\(a0\),v12
++[ 	]+[0-9a-f]+:[ 	]+0cc56227[ 	]+vsoxei32.v[ 	]+v4,\(a0\),v12,v0.t
++[ 	]+[0-9a-f]+:[ 	]+06c56207[ 	]+vluxei32.v[ 	]+v4,\(a0\),v12
++[ 	]+[0-9a-f]+:[ 	]+06c56207[ 	]+vluxei32.v[ 	]+v4,\(a0\),v12
++[ 	]+[0-9a-f]+:[ 	]+04c56207[ 	]+vluxei32.v[ 	]+v4,\(a0\),v12,v0.t
+ [ 	]+[0-9a-f]+:[ 	]+06c56227[ 	]+vsuxei32.v[ 	]+v4,\(a0\),v12
+ [ 	]+[0-9a-f]+:[ 	]+06c56227[ 	]+vsuxei32.v[ 	]+v4,\(a0\),v12
+ [ 	]+[0-9a-f]+:[ 	]+04c56227[ 	]+vsuxei32.v[ 	]+v4,\(a0\),v12,v0.t
+-[ 	]+[0-9a-f]+:[ 	]+0ec57207[ 	]+vlxei64.v[ 	]+v4,\(a0\),v12
+-[ 	]+[0-9a-f]+:[ 	]+0ec57207[ 	]+vlxei64.v[ 	]+v4,\(a0\),v12
+-[ 	]+[0-9a-f]+:[ 	]+0cc57207[ 	]+vlxei64.v[ 	]+v4,\(a0\),v12,v0.t
+-[ 	]+[0-9a-f]+:[ 	]+0ec57227[ 	]+vsxei64.v[ 	]+v4,\(a0\),v12
+-[ 	]+[0-9a-f]+:[ 	]+0ec57227[ 	]+vsxei64.v[ 	]+v4,\(a0\),v12
+-[ 	]+[0-9a-f]+:[ 	]+0cc57227[ 	]+vsxei64.v[ 	]+v4,\(a0\),v12,v0.t
++[ 	]+[0-9a-f]+:[ 	]+0ec57207[ 	]+vloxei64.v[ 	]+v4,\(a0\),v12
++[ 	]+[0-9a-f]+:[ 	]+0ec57207[ 	]+vloxei64.v[ 	]+v4,\(a0\),v12
++[ 	]+[0-9a-f]+:[ 	]+0cc57207[ 	]+vloxei64.v[ 	]+v4,\(a0\),v12,v0.t
++[ 	]+[0-9a-f]+:[ 	]+0ec57227[ 	]+vsoxei64.v[ 	]+v4,\(a0\),v12
++[ 	]+[0-9a-f]+:[ 	]+0ec57227[ 	]+vsoxei64.v[ 	]+v4,\(a0\),v12
++[ 	]+[0-9a-f]+:[ 	]+0cc57227[ 	]+vsoxei64.v[ 	]+v4,\(a0\),v12,v0.t
++[ 	]+[0-9a-f]+:[ 	]+06c57207[ 	]+vluxei64.v[ 	]+v4,\(a0\),v12
++[ 	]+[0-9a-f]+:[ 	]+06c57207[ 	]+vluxei64.v[ 	]+v4,\(a0\),v12
++[ 	]+[0-9a-f]+:[ 	]+04c57207[ 	]+vluxei64.v[ 	]+v4,\(a0\),v12,v0.t
+ [ 	]+[0-9a-f]+:[ 	]+06c57227[ 	]+vsuxei64.v[ 	]+v4,\(a0\),v12
+ [ 	]+[0-9a-f]+:[ 	]+06c57227[ 	]+vsuxei64.v[ 	]+v4,\(a0\),v12
+ [ 	]+[0-9a-f]+:[ 	]+04c57227[ 	]+vsuxei64.v[ 	]+v4,\(a0\),v12,v0.t
+@@ -854,342 +866,678 @@ Disassembly of section .text:
+ [ 	]+[0-9a-f]+:[ 	]+fab57227[ 	]+vssseg8e1024.v[ 	]+v4,\(a0\),a1
+ [ 	]+[0-9a-f]+:[ 	]+fab57227[ 	]+vssseg8e1024.v[ 	]+v4,\(a0\),a1
+ [ 	]+[0-9a-f]+:[ 	]+f8b57227[ 	]+vssseg8e1024.v[ 	]+v4,\(a0\),a1,v0.t
+-[ 	]+[0-9a-f]+:[ 	]+2ec50207[ 	]+vlxseg2ei8.v[ 	]+v4,\(a0\),v12
+-[ 	]+[0-9a-f]+:[ 	]+2ec50207[ 	]+vlxseg2ei8.v[ 	]+v4,\(a0\),v12
+-[ 	]+[0-9a-f]+:[ 	]+2cc50207[ 	]+vlxseg2ei8.v[ 	]+v4,\(a0\),v12,v0.t
+-[ 	]+[0-9a-f]+:[ 	]+2ec50227[ 	]+vsxseg2ei8.v[ 	]+v4,\(a0\),v12
+-[ 	]+[0-9a-f]+:[ 	]+2ec50227[ 	]+vsxseg2ei8.v[ 	]+v4,\(a0\),v12
+-[ 	]+[0-9a-f]+:[ 	]+2cc50227[ 	]+vsxseg2ei8.v[ 	]+v4,\(a0\),v12,v0.t
+-[ 	]+[0-9a-f]+:[ 	]+4ec50207[ 	]+vlxseg3ei8.v[ 	]+v4,\(a0\),v12
+-[ 	]+[0-9a-f]+:[ 	]+4ec50207[ 	]+vlxseg3ei8.v[ 	]+v4,\(a0\),v12
+-[ 	]+[0-9a-f]+:[ 	]+4cc50207[ 	]+vlxseg3ei8.v[ 	]+v4,\(a0\),v12,v0.t
+-[ 	]+[0-9a-f]+:[ 	]+4ec50227[ 	]+vsxseg3ei8.v[ 	]+v4,\(a0\),v12
+-[ 	]+[0-9a-f]+:[ 	]+4ec50227[ 	]+vsxseg3ei8.v[ 	]+v4,\(a0\),v12
+-[ 	]+[0-9a-f]+:[ 	]+4cc50227[ 	]+vsxseg3ei8.v[ 	]+v4,\(a0\),v12,v0.t
+-[ 	]+[0-9a-f]+:[ 	]+6ec50207[ 	]+vlxseg4ei8.v[ 	]+v4,\(a0\),v12
+-[ 	]+[0-9a-f]+:[ 	]+6ec50207[ 	]+vlxseg4ei8.v[ 	]+v4,\(a0\),v12
+-[ 	]+[0-9a-f]+:[ 	]+6cc50207[ 	]+vlxseg4ei8.v[ 	]+v4,\(a0\),v12,v0.t
+-[ 	]+[0-9a-f]+:[ 	]+6ec50227[ 	]+vsxseg4ei8.v[ 	]+v4,\(a0\),v12
+-[ 	]+[0-9a-f]+:[ 	]+6ec50227[ 	]+vsxseg4ei8.v[ 	]+v4,\(a0\),v12
+-[ 	]+[0-9a-f]+:[ 	]+6cc50227[ 	]+vsxseg4ei8.v[ 	]+v4,\(a0\),v12,v0.t
+-[ 	]+[0-9a-f]+:[ 	]+8ec50207[ 	]+vlxseg5ei8.v[ 	]+v4,\(a0\),v12
+-[ 	]+[0-9a-f]+:[ 	]+8ec50207[ 	]+vlxseg5ei8.v[ 	]+v4,\(a0\),v12
+-[ 	]+[0-9a-f]+:[ 	]+8cc50207[ 	]+vlxseg5ei8.v[ 	]+v4,\(a0\),v12,v0.t
+-[ 	]+[0-9a-f]+:[ 	]+8ec50227[ 	]+vsxseg5ei8.v[ 	]+v4,\(a0\),v12
+-[ 	]+[0-9a-f]+:[ 	]+8ec50227[ 	]+vsxseg5ei8.v[ 	]+v4,\(a0\),v12
+-[ 	]+[0-9a-f]+:[ 	]+8cc50227[ 	]+vsxseg5ei8.v[ 	]+v4,\(a0\),v12,v0.t
+-[ 	]+[0-9a-f]+:[ 	]+aec50207[ 	]+vlxseg6ei8.v[ 	]+v4,\(a0\),v12
+-[ 	]+[0-9a-f]+:[ 	]+aec50207[ 	]+vlxseg6ei8.v[ 	]+v4,\(a0\),v12
+-[ 	]+[0-9a-f]+:[ 	]+acc50207[ 	]+vlxseg6ei8.v[ 	]+v4,\(a0\),v12,v0.t
+-[ 	]+[0-9a-f]+:[ 	]+aec50227[ 	]+vsxseg6ei8.v[ 	]+v4,\(a0\),v12
+-[ 	]+[0-9a-f]+:[ 	]+aec50227[ 	]+vsxseg6ei8.v[ 	]+v4,\(a0\),v12
+-[ 	]+[0-9a-f]+:[ 	]+acc50227[ 	]+vsxseg6ei8.v[ 	]+v4,\(a0\),v12,v0.t
+-[ 	]+[0-9a-f]+:[ 	]+cec50207[ 	]+vlxseg7ei8.v[ 	]+v4,\(a0\),v12
+-[ 	]+[0-9a-f]+:[ 	]+cec50207[ 	]+vlxseg7ei8.v[ 	]+v4,\(a0\),v12
+-[ 	]+[0-9a-f]+:[ 	]+ccc50207[ 	]+vlxseg7ei8.v[ 	]+v4,\(a0\),v12,v0.t
+-[ 	]+[0-9a-f]+:[ 	]+cec50227[ 	]+vsxseg7ei8.v[ 	]+v4,\(a0\),v12
+-[ 	]+[0-9a-f]+:[ 	]+cec50227[ 	]+vsxseg7ei8.v[ 	]+v4,\(a0\),v12
+-[ 	]+[0-9a-f]+:[ 	]+ccc50227[ 	]+vsxseg7ei8.v[ 	]+v4,\(a0\),v12,v0.t
+-[ 	]+[0-9a-f]+:[ 	]+eec50207[ 	]+vlxseg8ei8.v[ 	]+v4,\(a0\),v12
+-[ 	]+[0-9a-f]+:[ 	]+eec50207[ 	]+vlxseg8ei8.v[ 	]+v4,\(a0\),v12
+-[ 	]+[0-9a-f]+:[ 	]+ecc50207[ 	]+vlxseg8ei8.v[ 	]+v4,\(a0\),v12,v0.t
+-[ 	]+[0-9a-f]+:[ 	]+eec50227[ 	]+vsxseg8ei8.v[ 	]+v4,\(a0\),v12
+-[ 	]+[0-9a-f]+:[ 	]+eec50227[ 	]+vsxseg8ei8.v[ 	]+v4,\(a0\),v12
+-[ 	]+[0-9a-f]+:[ 	]+ecc50227[ 	]+vsxseg8ei8.v[ 	]+v4,\(a0\),v12,v0.t
+-[ 	]+[0-9a-f]+:[ 	]+2ec55207[ 	]+vlxseg2ei16.v[ 	]+v4,\(a0\),v12
+-[ 	]+[0-9a-f]+:[ 	]+2ec55207[ 	]+vlxseg2ei16.v[ 	]+v4,\(a0\),v12
+-[ 	]+[0-9a-f]+:[ 	]+2cc55207[ 	]+vlxseg2ei16.v[ 	]+v4,\(a0\),v12,v0.t
+-[ 	]+[0-9a-f]+:[ 	]+2ec55227[ 	]+vsxseg2ei16.v[ 	]+v4,\(a0\),v12
+-[ 	]+[0-9a-f]+:[ 	]+2ec55227[ 	]+vsxseg2ei16.v[ 	]+v4,\(a0\),v12
+-[ 	]+[0-9a-f]+:[ 	]+2cc55227[ 	]+vsxseg2ei16.v[ 	]+v4,\(a0\),v12,v0.t
+-[ 	]+[0-9a-f]+:[ 	]+4ec55207[ 	]+vlxseg3ei16.v[ 	]+v4,\(a0\),v12
+-[ 	]+[0-9a-f]+:[ 	]+4ec55207[ 	]+vlxseg3ei16.v[ 	]+v4,\(a0\),v12
+-[ 	]+[0-9a-f]+:[ 	]+4cc55207[ 	]+vlxseg3ei16.v[ 	]+v4,\(a0\),v12,v0.t
+-[ 	]+[0-9a-f]+:[ 	]+4ec55227[ 	]+vsxseg3ei16.v[ 	]+v4,\(a0\),v12
+-[ 	]+[0-9a-f]+:[ 	]+4ec55227[ 	]+vsxseg3ei16.v[ 	]+v4,\(a0\),v12
+-[ 	]+[0-9a-f]+:[ 	]+4cc55227[ 	]+vsxseg3ei16.v[ 	]+v4,\(a0\),v12,v0.t
+-[ 	]+[0-9a-f]+:[ 	]+6ec55207[ 	]+vlxseg4ei16.v[ 	]+v4,\(a0\),v12
+-[ 	]+[0-9a-f]+:[ 	]+6ec55207[ 	]+vlxseg4ei16.v[ 	]+v4,\(a0\),v12
+-[ 	]+[0-9a-f]+:[ 	]+6cc55207[ 	]+vlxseg4ei16.v[ 	]+v4,\(a0\),v12,v0.t
+-[ 	]+[0-9a-f]+:[ 	]+6ec55227[ 	]+vsxseg4ei16.v[ 	]+v4,\(a0\),v12
+-[ 	]+[0-9a-f]+:[ 	]+6ec55227[ 	]+vsxseg4ei16.v[ 	]+v4,\(a0\),v12
+-[ 	]+[0-9a-f]+:[ 	]+6cc55227[ 	]+vsxseg4ei16.v[ 	]+v4,\(a0\),v12,v0.t
+-[ 	]+[0-9a-f]+:[ 	]+8ec55207[ 	]+vlxseg5ei16.v[ 	]+v4,\(a0\),v12
+-[ 	]+[0-9a-f]+:[ 	]+8ec55207[ 	]+vlxseg5ei16.v[ 	]+v4,\(a0\),v12
+-[ 	]+[0-9a-f]+:[ 	]+8cc55207[ 	]+vlxseg5ei16.v[ 	]+v4,\(a0\),v12,v0.t
+-[ 	]+[0-9a-f]+:[ 	]+8ec55227[ 	]+vsxseg5ei16.v[ 	]+v4,\(a0\),v12
+-[ 	]+[0-9a-f]+:[ 	]+8ec55227[ 	]+vsxseg5ei16.v[ 	]+v4,\(a0\),v12
+-[ 	]+[0-9a-f]+:[ 	]+8cc55227[ 	]+vsxseg5ei16.v[ 	]+v4,\(a0\),v12,v0.t
+-[ 	]+[0-9a-f]+:[ 	]+aec55207[ 	]+vlxseg6ei16.v[ 	]+v4,\(a0\),v12
+-[ 	]+[0-9a-f]+:[ 	]+aec55207[ 	]+vlxseg6ei16.v[ 	]+v4,\(a0\),v12
+-[ 	]+[0-9a-f]+:[ 	]+acc55207[ 	]+vlxseg6ei16.v[ 	]+v4,\(a0\),v12,v0.t
+-[ 	]+[0-9a-f]+:[ 	]+aec55227[ 	]+vsxseg6ei16.v[ 	]+v4,\(a0\),v12
+-[ 	]+[0-9a-f]+:[ 	]+aec55227[ 	]+vsxseg6ei16.v[ 	]+v4,\(a0\),v12
+-[ 	]+[0-9a-f]+:[ 	]+acc55227[ 	]+vsxseg6ei16.v[ 	]+v4,\(a0\),v12,v0.t
+-[ 	]+[0-9a-f]+:[ 	]+cec55207[ 	]+vlxseg7ei16.v[ 	]+v4,\(a0\),v12
+-[ 	]+[0-9a-f]+:[ 	]+cec55207[ 	]+vlxseg7ei16.v[ 	]+v4,\(a0\),v12
+-[ 	]+[0-9a-f]+:[ 	]+ccc55207[ 	]+vlxseg7ei16.v[ 	]+v4,\(a0\),v12,v0.t
+-[ 	]+[0-9a-f]+:[ 	]+cec55227[ 	]+vsxseg7ei16.v[ 	]+v4,\(a0\),v12
+-[ 	]+[0-9a-f]+:[ 	]+cec55227[ 	]+vsxseg7ei16.v[ 	]+v4,\(a0\),v12
+-[ 	]+[0-9a-f]+:[ 	]+ccc55227[ 	]+vsxseg7ei16.v[ 	]+v4,\(a0\),v12,v0.t
+-[ 	]+[0-9a-f]+:[ 	]+eec55207[ 	]+vlxseg8ei16.v[ 	]+v4,\(a0\),v12
+-[ 	]+[0-9a-f]+:[ 	]+eec55207[ 	]+vlxseg8ei16.v[ 	]+v4,\(a0\),v12
+-[ 	]+[0-9a-f]+:[ 	]+ecc55207[ 	]+vlxseg8ei16.v[ 	]+v4,\(a0\),v12,v0.t
+-[ 	]+[0-9a-f]+:[ 	]+eec55227[ 	]+vsxseg8ei16.v[ 	]+v4,\(a0\),v12
+-[ 	]+[0-9a-f]+:[ 	]+eec55227[ 	]+vsxseg8ei16.v[ 	]+v4,\(a0\),v12
+-[ 	]+[0-9a-f]+:[ 	]+ecc55227[ 	]+vsxseg8ei16.v[ 	]+v4,\(a0\),v12,v0.t
+-[ 	]+[0-9a-f]+:[ 	]+2ec56207[ 	]+vlxseg2ei32.v[ 	]+v4,\(a0\),v12
+-[ 	]+[0-9a-f]+:[ 	]+2ec56207[ 	]+vlxseg2ei32.v[ 	]+v4,\(a0\),v12
+-[ 	]+[0-9a-f]+:[ 	]+2cc56207[ 	]+vlxseg2ei32.v[ 	]+v4,\(a0\),v12,v0.t
+-[ 	]+[0-9a-f]+:[ 	]+2ec56227[ 	]+vsxseg2ei32.v[ 	]+v4,\(a0\),v12
+-[ 	]+[0-9a-f]+:[ 	]+2ec56227[ 	]+vsxseg2ei32.v[ 	]+v4,\(a0\),v12
+-[ 	]+[0-9a-f]+:[ 	]+2cc56227[ 	]+vsxseg2ei32.v[ 	]+v4,\(a0\),v12,v0.t
+-[ 	]+[0-9a-f]+:[ 	]+4ec56207[ 	]+vlxseg3ei32.v[ 	]+v4,\(a0\),v12
+-[ 	]+[0-9a-f]+:[ 	]+4ec56207[ 	]+vlxseg3ei32.v[ 	]+v4,\(a0\),v12
+-[ 	]+[0-9a-f]+:[ 	]+4cc56207[ 	]+vlxseg3ei32.v[ 	]+v4,\(a0\),v12,v0.t
+-[ 	]+[0-9a-f]+:[ 	]+4ec56227[ 	]+vsxseg3ei32.v[ 	]+v4,\(a0\),v12
+-[ 	]+[0-9a-f]+:[ 	]+4ec56227[ 	]+vsxseg3ei32.v[ 	]+v4,\(a0\),v12
+-[ 	]+[0-9a-f]+:[ 	]+4cc56227[ 	]+vsxseg3ei32.v[ 	]+v4,\(a0\),v12,v0.t
+-[ 	]+[0-9a-f]+:[ 	]+6ec56207[ 	]+vlxseg4ei32.v[ 	]+v4,\(a0\),v12
+-[ 	]+[0-9a-f]+:[ 	]+6ec56207[ 	]+vlxseg4ei32.v[ 	]+v4,\(a0\),v12
+-[ 	]+[0-9a-f]+:[ 	]+6cc56207[ 	]+vlxseg4ei32.v[ 	]+v4,\(a0\),v12,v0.t
+-[ 	]+[0-9a-f]+:[ 	]+6ec56227[ 	]+vsxseg4ei32.v[ 	]+v4,\(a0\),v12
+-[ 	]+[0-9a-f]+:[ 	]+6ec56227[ 	]+vsxseg4ei32.v[ 	]+v4,\(a0\),v12
+-[ 	]+[0-9a-f]+:[ 	]+6cc56227[ 	]+vsxseg4ei32.v[ 	]+v4,\(a0\),v12,v0.t
+-[ 	]+[0-9a-f]+:[ 	]+8ec56207[ 	]+vlxseg5ei32.v[ 	]+v4,\(a0\),v12
+-[ 	]+[0-9a-f]+:[ 	]+8ec56207[ 	]+vlxseg5ei32.v[ 	]+v4,\(a0\),v12
+-[ 	]+[0-9a-f]+:[ 	]+8cc56207[ 	]+vlxseg5ei32.v[ 	]+v4,\(a0\),v12,v0.t
+-[ 	]+[0-9a-f]+:[ 	]+8ec56227[ 	]+vsxseg5ei32.v[ 	]+v4,\(a0\),v12
+-[ 	]+[0-9a-f]+:[ 	]+8ec56227[ 	]+vsxseg5ei32.v[ 	]+v4,\(a0\),v12
+-[ 	]+[0-9a-f]+:[ 	]+8cc56227[ 	]+vsxseg5ei32.v[ 	]+v4,\(a0\),v12,v0.t
+-[ 	]+[0-9a-f]+:[ 	]+aec56207[ 	]+vlxseg6ei32.v[ 	]+v4,\(a0\),v12
+-[ 	]+[0-9a-f]+:[ 	]+aec56207[ 	]+vlxseg6ei32.v[ 	]+v4,\(a0\),v12
+-[ 	]+[0-9a-f]+:[ 	]+acc56207[ 	]+vlxseg6ei32.v[ 	]+v4,\(a0\),v12,v0.t
+-[ 	]+[0-9a-f]+:[ 	]+aec56227[ 	]+vsxseg6ei32.v[ 	]+v4,\(a0\),v12
+-[ 	]+[0-9a-f]+:[ 	]+aec56227[ 	]+vsxseg6ei32.v[ 	]+v4,\(a0\),v12
+-[ 	]+[0-9a-f]+:[ 	]+acc56227[ 	]+vsxseg6ei32.v[ 	]+v4,\(a0\),v12,v0.t
+-[ 	]+[0-9a-f]+:[ 	]+cec56207[ 	]+vlxseg7ei32.v[ 	]+v4,\(a0\),v12
+-[ 	]+[0-9a-f]+:[ 	]+cec56207[ 	]+vlxseg7ei32.v[ 	]+v4,\(a0\),v12
+-[ 	]+[0-9a-f]+:[ 	]+ccc56207[ 	]+vlxseg7ei32.v[ 	]+v4,\(a0\),v12,v0.t
+-[ 	]+[0-9a-f]+:[ 	]+cec56227[ 	]+vsxseg7ei32.v[ 	]+v4,\(a0\),v12
+-[ 	]+[0-9a-f]+:[ 	]+cec56227[ 	]+vsxseg7ei32.v[ 	]+v4,\(a0\),v12
+-[ 	]+[0-9a-f]+:[ 	]+ccc56227[ 	]+vsxseg7ei32.v[ 	]+v4,\(a0\),v12,v0.t
+-[ 	]+[0-9a-f]+:[ 	]+eec56207[ 	]+vlxseg8ei32.v[ 	]+v4,\(a0\),v12
+-[ 	]+[0-9a-f]+:[ 	]+eec56207[ 	]+vlxseg8ei32.v[ 	]+v4,\(a0\),v12
+-[ 	]+[0-9a-f]+:[ 	]+ecc56207[ 	]+vlxseg8ei32.v[ 	]+v4,\(a0\),v12,v0.t
+-[ 	]+[0-9a-f]+:[ 	]+eec56227[ 	]+vsxseg8ei32.v[ 	]+v4,\(a0\),v12
+-[ 	]+[0-9a-f]+:[ 	]+eec56227[ 	]+vsxseg8ei32.v[ 	]+v4,\(a0\),v12
+-[ 	]+[0-9a-f]+:[ 	]+ecc56227[ 	]+vsxseg8ei32.v[ 	]+v4,\(a0\),v12,v0.t
+-[ 	]+[0-9a-f]+:[ 	]+2ec57207[ 	]+vlxseg2ei64.v[ 	]+v4,\(a0\),v12
+-[ 	]+[0-9a-f]+:[ 	]+2ec57207[ 	]+vlxseg2ei64.v[ 	]+v4,\(a0\),v12
+-[ 	]+[0-9a-f]+:[ 	]+2cc57207[ 	]+vlxseg2ei64.v[ 	]+v4,\(a0\),v12,v0.t
+-[ 	]+[0-9a-f]+:[ 	]+2ec57227[ 	]+vsxseg2ei64.v[ 	]+v4,\(a0\),v12
+-[ 	]+[0-9a-f]+:[ 	]+2ec57227[ 	]+vsxseg2ei64.v[ 	]+v4,\(a0\),v12
+-[ 	]+[0-9a-f]+:[ 	]+2cc57227[ 	]+vsxseg2ei64.v[ 	]+v4,\(a0\),v12,v0.t
+-[ 	]+[0-9a-f]+:[ 	]+4ec57207[ 	]+vlxseg3ei64.v[ 	]+v4,\(a0\),v12
+-[ 	]+[0-9a-f]+:[ 	]+4ec57207[ 	]+vlxseg3ei64.v[ 	]+v4,\(a0\),v12
+-[ 	]+[0-9a-f]+:[ 	]+4cc57207[ 	]+vlxseg3ei64.v[ 	]+v4,\(a0\),v12,v0.t
+-[ 	]+[0-9a-f]+:[ 	]+4ec57227[ 	]+vsxseg3ei64.v[ 	]+v4,\(a0\),v12
+-[ 	]+[0-9a-f]+:[ 	]+4ec57227[ 	]+vsxseg3ei64.v[ 	]+v4,\(a0\),v12
+-[ 	]+[0-9a-f]+:[ 	]+4cc57227[ 	]+vsxseg3ei64.v[ 	]+v4,\(a0\),v12,v0.t
+-[ 	]+[0-9a-f]+:[ 	]+6ec57207[ 	]+vlxseg4ei64.v[ 	]+v4,\(a0\),v12
+-[ 	]+[0-9a-f]+:[ 	]+6ec57207[ 	]+vlxseg4ei64.v[ 	]+v4,\(a0\),v12
+-[ 	]+[0-9a-f]+:[ 	]+6cc57207[ 	]+vlxseg4ei64.v[ 	]+v4,\(a0\),v12,v0.t
+-[ 	]+[0-9a-f]+:[ 	]+6ec57227[ 	]+vsxseg4ei64.v[ 	]+v4,\(a0\),v12
+-[ 	]+[0-9a-f]+:[ 	]+6ec57227[ 	]+vsxseg4ei64.v[ 	]+v4,\(a0\),v12
+-[ 	]+[0-9a-f]+:[ 	]+6cc57227[ 	]+vsxseg4ei64.v[ 	]+v4,\(a0\),v12,v0.t
+-[ 	]+[0-9a-f]+:[ 	]+8ec57207[ 	]+vlxseg5ei64.v[ 	]+v4,\(a0\),v12
+-[ 	]+[0-9a-f]+:[ 	]+8ec57207[ 	]+vlxseg5ei64.v[ 	]+v4,\(a0\),v12
+-[ 	]+[0-9a-f]+:[ 	]+8cc57207[ 	]+vlxseg5ei64.v[ 	]+v4,\(a0\),v12,v0.t
+-[ 	]+[0-9a-f]+:[ 	]+8ec57227[ 	]+vsxseg5ei64.v[ 	]+v4,\(a0\),v12
+-[ 	]+[0-9a-f]+:[ 	]+8ec57227[ 	]+vsxseg5ei64.v[ 	]+v4,\(a0\),v12
+-[ 	]+[0-9a-f]+:[ 	]+8cc57227[ 	]+vsxseg5ei64.v[ 	]+v4,\(a0\),v12,v0.t
+-[ 	]+[0-9a-f]+:[ 	]+aec57207[ 	]+vlxseg6ei64.v[ 	]+v4,\(a0\),v12
+-[ 	]+[0-9a-f]+:[ 	]+aec57207[ 	]+vlxseg6ei64.v[ 	]+v4,\(a0\),v12
+-[ 	]+[0-9a-f]+:[ 	]+acc57207[ 	]+vlxseg6ei64.v[ 	]+v4,\(a0\),v12,v0.t
+-[ 	]+[0-9a-f]+:[ 	]+aec57227[ 	]+vsxseg6ei64.v[ 	]+v4,\(a0\),v12
+-[ 	]+[0-9a-f]+:[ 	]+aec57227[ 	]+vsxseg6ei64.v[ 	]+v4,\(a0\),v12
+-[ 	]+[0-9a-f]+:[ 	]+acc57227[ 	]+vsxseg6ei64.v[ 	]+v4,\(a0\),v12,v0.t
+-[ 	]+[0-9a-f]+:[ 	]+cec57207[ 	]+vlxseg7ei64.v[ 	]+v4,\(a0\),v12
+-[ 	]+[0-9a-f]+:[ 	]+cec57207[ 	]+vlxseg7ei64.v[ 	]+v4,\(a0\),v12
+-[ 	]+[0-9a-f]+:[ 	]+ccc57207[ 	]+vlxseg7ei64.v[ 	]+v4,\(a0\),v12,v0.t
+-[ 	]+[0-9a-f]+:[ 	]+cec57227[ 	]+vsxseg7ei64.v[ 	]+v4,\(a0\),v12
+-[ 	]+[0-9a-f]+:[ 	]+cec57227[ 	]+vsxseg7ei64.v[ 	]+v4,\(a0\),v12
+-[ 	]+[0-9a-f]+:[ 	]+ccc57227[ 	]+vsxseg7ei64.v[ 	]+v4,\(a0\),v12,v0.t
+-[ 	]+[0-9a-f]+:[ 	]+eec57207[ 	]+vlxseg8ei64.v[ 	]+v4,\(a0\),v12
+-[ 	]+[0-9a-f]+:[ 	]+eec57207[ 	]+vlxseg8ei64.v[ 	]+v4,\(a0\),v12
+-[ 	]+[0-9a-f]+:[ 	]+ecc57207[ 	]+vlxseg8ei64.v[ 	]+v4,\(a0\),v12,v0.t
+-[ 	]+[0-9a-f]+:[ 	]+eec57227[ 	]+vsxseg8ei64.v[ 	]+v4,\(a0\),v12
+-[ 	]+[0-9a-f]+:[ 	]+eec57227[ 	]+vsxseg8ei64.v[ 	]+v4,\(a0\),v12
+-[ 	]+[0-9a-f]+:[ 	]+ecc57227[ 	]+vsxseg8ei64.v[ 	]+v4,\(a0\),v12,v0.t
+-[ 	]+[0-9a-f]+:[ 	]+3ec50207[ 	]+vlxseg2ei128.v[ 	]+v4,\(a0\),v12
+-[ 	]+[0-9a-f]+:[ 	]+3ec50207[ 	]+vlxseg2ei128.v[ 	]+v4,\(a0\),v12
+-[ 	]+[0-9a-f]+:[ 	]+3cc50207[ 	]+vlxseg2ei128.v[ 	]+v4,\(a0\),v12,v0.t
+-[ 	]+[0-9a-f]+:[ 	]+3ec50227[ 	]+vsxseg2ei128.v[ 	]+v4,\(a0\),v12
+-[ 	]+[0-9a-f]+:[ 	]+3ec50227[ 	]+vsxseg2ei128.v[ 	]+v4,\(a0\),v12
+-[ 	]+[0-9a-f]+:[ 	]+3cc50227[ 	]+vsxseg2ei128.v[ 	]+v4,\(a0\),v12,v0.t
+-[ 	]+[0-9a-f]+:[ 	]+5ec50207[ 	]+vlxseg3ei128.v[ 	]+v4,\(a0\),v12
+-[ 	]+[0-9a-f]+:[ 	]+5ec50207[ 	]+vlxseg3ei128.v[ 	]+v4,\(a0\),v12
+-[ 	]+[0-9a-f]+:[ 	]+5cc50207[ 	]+vlxseg3ei128.v[ 	]+v4,\(a0\),v12,v0.t
+-[ 	]+[0-9a-f]+:[ 	]+5ec50227[ 	]+vsxseg3ei128.v[ 	]+v4,\(a0\),v12
+-[ 	]+[0-9a-f]+:[ 	]+5ec50227[ 	]+vsxseg3ei128.v[ 	]+v4,\(a0\),v12
+-[ 	]+[0-9a-f]+:[ 	]+5cc50227[ 	]+vsxseg3ei128.v[ 	]+v4,\(a0\),v12,v0.t
+-[ 	]+[0-9a-f]+:[ 	]+7ec50207[ 	]+vlxseg4ei128.v[ 	]+v4,\(a0\),v12
+-[ 	]+[0-9a-f]+:[ 	]+7ec50207[ 	]+vlxseg4ei128.v[ 	]+v4,\(a0\),v12
+-[ 	]+[0-9a-f]+:[ 	]+7cc50207[ 	]+vlxseg4ei128.v[ 	]+v4,\(a0\),v12,v0.t
+-[ 	]+[0-9a-f]+:[ 	]+7ec50227[ 	]+vsxseg4ei128.v[ 	]+v4,\(a0\),v12
+-[ 	]+[0-9a-f]+:[ 	]+7ec50227[ 	]+vsxseg4ei128.v[ 	]+v4,\(a0\),v12
+-[ 	]+[0-9a-f]+:[ 	]+7cc50227[ 	]+vsxseg4ei128.v[ 	]+v4,\(a0\),v12,v0.t
+-[ 	]+[0-9a-f]+:[ 	]+9ec50207[ 	]+vlxseg5ei128.v[ 	]+v4,\(a0\),v12
+-[ 	]+[0-9a-f]+:[ 	]+9ec50207[ 	]+vlxseg5ei128.v[ 	]+v4,\(a0\),v12
+-[ 	]+[0-9a-f]+:[ 	]+9cc50207[ 	]+vlxseg5ei128.v[ 	]+v4,\(a0\),v12,v0.t
+-[ 	]+[0-9a-f]+:[ 	]+9ec50227[ 	]+vsxseg5ei128.v[ 	]+v4,\(a0\),v12
+-[ 	]+[0-9a-f]+:[ 	]+9ec50227[ 	]+vsxseg5ei128.v[ 	]+v4,\(a0\),v12
+-[ 	]+[0-9a-f]+:[ 	]+9cc50227[ 	]+vsxseg5ei128.v[ 	]+v4,\(a0\),v12,v0.t
+-[ 	]+[0-9a-f]+:[ 	]+bec50207[ 	]+vlxseg6ei128.v[ 	]+v4,\(a0\),v12
+-[ 	]+[0-9a-f]+:[ 	]+bec50207[ 	]+vlxseg6ei128.v[ 	]+v4,\(a0\),v12
+-[ 	]+[0-9a-f]+:[ 	]+bcc50207[ 	]+vlxseg6ei128.v[ 	]+v4,\(a0\),v12,v0.t
+-[ 	]+[0-9a-f]+:[ 	]+bec50227[ 	]+vsxseg6ei128.v[ 	]+v4,\(a0\),v12
+-[ 	]+[0-9a-f]+:[ 	]+bec50227[ 	]+vsxseg6ei128.v[ 	]+v4,\(a0\),v12
+-[ 	]+[0-9a-f]+:[ 	]+bcc50227[ 	]+vsxseg6ei128.v[ 	]+v4,\(a0\),v12,v0.t
+-[ 	]+[0-9a-f]+:[ 	]+dec50207[ 	]+vlxseg7ei128.v[ 	]+v4,\(a0\),v12
+-[ 	]+[0-9a-f]+:[ 	]+dec50207[ 	]+vlxseg7ei128.v[ 	]+v4,\(a0\),v12
+-[ 	]+[0-9a-f]+:[ 	]+dcc50207[ 	]+vlxseg7ei128.v[ 	]+v4,\(a0\),v12,v0.t
+-[ 	]+[0-9a-f]+:[ 	]+dec50227[ 	]+vsxseg7ei128.v[ 	]+v4,\(a0\),v12
+-[ 	]+[0-9a-f]+:[ 	]+dec50227[ 	]+vsxseg7ei128.v[ 	]+v4,\(a0\),v12
+-[ 	]+[0-9a-f]+:[ 	]+dcc50227[ 	]+vsxseg7ei128.v[ 	]+v4,\(a0\),v12,v0.t
+-[ 	]+[0-9a-f]+:[ 	]+fec50207[ 	]+vlxseg8ei128.v[ 	]+v4,\(a0\),v12
+-[ 	]+[0-9a-f]+:[ 	]+fec50207[ 	]+vlxseg8ei128.v[ 	]+v4,\(a0\),v12
+-[ 	]+[0-9a-f]+:[ 	]+fcc50207[ 	]+vlxseg8ei128.v[ 	]+v4,\(a0\),v12,v0.t
+-[ 	]+[0-9a-f]+:[ 	]+fec50227[ 	]+vsxseg8ei128.v[ 	]+v4,\(a0\),v12
+-[ 	]+[0-9a-f]+:[ 	]+fec50227[ 	]+vsxseg8ei128.v[ 	]+v4,\(a0\),v12
+-[ 	]+[0-9a-f]+:[ 	]+fcc50227[ 	]+vsxseg8ei128.v[ 	]+v4,\(a0\),v12,v0.t
+-[ 	]+[0-9a-f]+:[ 	]+3ec55207[ 	]+vlxseg2ei256.v[ 	]+v4,\(a0\),v12
+-[ 	]+[0-9a-f]+:[ 	]+3ec55207[ 	]+vlxseg2ei256.v[ 	]+v4,\(a0\),v12
+-[ 	]+[0-9a-f]+:[ 	]+3cc55207[ 	]+vlxseg2ei256.v[ 	]+v4,\(a0\),v12,v0.t
+-[ 	]+[0-9a-f]+:[ 	]+3ec55227[ 	]+vsxseg2ei256.v[ 	]+v4,\(a0\),v12
+-[ 	]+[0-9a-f]+:[ 	]+3ec55227[ 	]+vsxseg2ei256.v[ 	]+v4,\(a0\),v12
+-[ 	]+[0-9a-f]+:[ 	]+3cc55227[ 	]+vsxseg2ei256.v[ 	]+v4,\(a0\),v12,v0.t
+-[ 	]+[0-9a-f]+:[ 	]+5ec55207[ 	]+vlxseg3ei256.v[ 	]+v4,\(a0\),v12
+-[ 	]+[0-9a-f]+:[ 	]+5ec55207[ 	]+vlxseg3ei256.v[ 	]+v4,\(a0\),v12
+-[ 	]+[0-9a-f]+:[ 	]+5cc55207[ 	]+vlxseg3ei256.v[ 	]+v4,\(a0\),v12,v0.t
+-[ 	]+[0-9a-f]+:[ 	]+5ec55227[ 	]+vsxseg3ei256.v[ 	]+v4,\(a0\),v12
+-[ 	]+[0-9a-f]+:[ 	]+5ec55227[ 	]+vsxseg3ei256.v[ 	]+v4,\(a0\),v12
+-[ 	]+[0-9a-f]+:[ 	]+5cc55227[ 	]+vsxseg3ei256.v[ 	]+v4,\(a0\),v12,v0.t
+-[ 	]+[0-9a-f]+:[ 	]+7ec55207[ 	]+vlxseg4ei256.v[ 	]+v4,\(a0\),v12
+-[ 	]+[0-9a-f]+:[ 	]+7ec55207[ 	]+vlxseg4ei256.v[ 	]+v4,\(a0\),v12
+-[ 	]+[0-9a-f]+:[ 	]+7cc55207[ 	]+vlxseg4ei256.v[ 	]+v4,\(a0\),v12,v0.t
+-[ 	]+[0-9a-f]+:[ 	]+7ec55227[ 	]+vsxseg4ei256.v[ 	]+v4,\(a0\),v12
+-[ 	]+[0-9a-f]+:[ 	]+7ec55227[ 	]+vsxseg4ei256.v[ 	]+v4,\(a0\),v12
+-[ 	]+[0-9a-f]+:[ 	]+7cc55227[ 	]+vsxseg4ei256.v[ 	]+v4,\(a0\),v12,v0.t
+-[ 	]+[0-9a-f]+:[ 	]+9ec55207[ 	]+vlxseg5ei256.v[ 	]+v4,\(a0\),v12
+-[ 	]+[0-9a-f]+:[ 	]+9ec55207[ 	]+vlxseg5ei256.v[ 	]+v4,\(a0\),v12
+-[ 	]+[0-9a-f]+:[ 	]+9cc55207[ 	]+vlxseg5ei256.v[ 	]+v4,\(a0\),v12,v0.t
+-[ 	]+[0-9a-f]+:[ 	]+9ec55227[ 	]+vsxseg5ei256.v[ 	]+v4,\(a0\),v12
+-[ 	]+[0-9a-f]+:[ 	]+9ec55227[ 	]+vsxseg5ei256.v[ 	]+v4,\(a0\),v12
+-[ 	]+[0-9a-f]+:[ 	]+9cc55227[ 	]+vsxseg5ei256.v[ 	]+v4,\(a0\),v12,v0.t
+-[ 	]+[0-9a-f]+:[ 	]+bec55207[ 	]+vlxseg6ei256.v[ 	]+v4,\(a0\),v12
+-[ 	]+[0-9a-f]+:[ 	]+bec55207[ 	]+vlxseg6ei256.v[ 	]+v4,\(a0\),v12
+-[ 	]+[0-9a-f]+:[ 	]+bcc55207[ 	]+vlxseg6ei256.v[ 	]+v4,\(a0\),v12,v0.t
+-[ 	]+[0-9a-f]+:[ 	]+bec55227[ 	]+vsxseg6ei256.v[ 	]+v4,\(a0\),v12
+-[ 	]+[0-9a-f]+:[ 	]+bec55227[ 	]+vsxseg6ei256.v[ 	]+v4,\(a0\),v12
+-[ 	]+[0-9a-f]+:[ 	]+bcc55227[ 	]+vsxseg6ei256.v[ 	]+v4,\(a0\),v12,v0.t
+-[ 	]+[0-9a-f]+:[ 	]+dec55207[ 	]+vlxseg7ei256.v[ 	]+v4,\(a0\),v12
+-[ 	]+[0-9a-f]+:[ 	]+dec55207[ 	]+vlxseg7ei256.v[ 	]+v4,\(a0\),v12
+-[ 	]+[0-9a-f]+:[ 	]+dcc55207[ 	]+vlxseg7ei256.v[ 	]+v4,\(a0\),v12,v0.t
+-[ 	]+[0-9a-f]+:[ 	]+dec55227[ 	]+vsxseg7ei256.v[ 	]+v4,\(a0\),v12
+-[ 	]+[0-9a-f]+:[ 	]+dec55227[ 	]+vsxseg7ei256.v[ 	]+v4,\(a0\),v12
+-[ 	]+[0-9a-f]+:[ 	]+dcc55227[ 	]+vsxseg7ei256.v[ 	]+v4,\(a0\),v12,v0.t
+-[ 	]+[0-9a-f]+:[ 	]+fec55207[ 	]+vlxseg8ei256.v[ 	]+v4,\(a0\),v12
+-[ 	]+[0-9a-f]+:[ 	]+fec55207[ 	]+vlxseg8ei256.v[ 	]+v4,\(a0\),v12
+-[ 	]+[0-9a-f]+:[ 	]+fcc55207[ 	]+vlxseg8ei256.v[ 	]+v4,\(a0\),v12,v0.t
+-[ 	]+[0-9a-f]+:[ 	]+fec55227[ 	]+vsxseg8ei256.v[ 	]+v4,\(a0\),v12
+-[ 	]+[0-9a-f]+:[ 	]+fec55227[ 	]+vsxseg8ei256.v[ 	]+v4,\(a0\),v12
+-[ 	]+[0-9a-f]+:[ 	]+fcc55227[ 	]+vsxseg8ei256.v[ 	]+v4,\(a0\),v12,v0.t
+-[ 	]+[0-9a-f]+:[ 	]+3ec56207[ 	]+vlxseg2ei512.v[ 	]+v4,\(a0\),v12
+-[ 	]+[0-9a-f]+:[ 	]+3ec56207[ 	]+vlxseg2ei512.v[ 	]+v4,\(a0\),v12
+-[ 	]+[0-9a-f]+:[ 	]+3cc56207[ 	]+vlxseg2ei512.v[ 	]+v4,\(a0\),v12,v0.t
+-[ 	]+[0-9a-f]+:[ 	]+3ec56227[ 	]+vsxseg2ei512.v[ 	]+v4,\(a0\),v12
+-[ 	]+[0-9a-f]+:[ 	]+3ec56227[ 	]+vsxseg2ei512.v[ 	]+v4,\(a0\),v12
+-[ 	]+[0-9a-f]+:[ 	]+3cc56227[ 	]+vsxseg2ei512.v[ 	]+v4,\(a0\),v12,v0.t
+-[ 	]+[0-9a-f]+:[ 	]+5ec56207[ 	]+vlxseg3ei512.v[ 	]+v4,\(a0\),v12
+-[ 	]+[0-9a-f]+:[ 	]+5ec56207[ 	]+vlxseg3ei512.v[ 	]+v4,\(a0\),v12
+-[ 	]+[0-9a-f]+:[ 	]+5cc56207[ 	]+vlxseg3ei512.v[ 	]+v4,\(a0\),v12,v0.t
+-[ 	]+[0-9a-f]+:[ 	]+5ec56227[ 	]+vsxseg3ei512.v[ 	]+v4,\(a0\),v12
+-[ 	]+[0-9a-f]+:[ 	]+5ec56227[ 	]+vsxseg3ei512.v[ 	]+v4,\(a0\),v12
+-[ 	]+[0-9a-f]+:[ 	]+5cc56227[ 	]+vsxseg3ei512.v[ 	]+v4,\(a0\),v12,v0.t
+-[ 	]+[0-9a-f]+:[ 	]+7ec56207[ 	]+vlxseg4ei512.v[ 	]+v4,\(a0\),v12
+-[ 	]+[0-9a-f]+:[ 	]+7ec56207[ 	]+vlxseg4ei512.v[ 	]+v4,\(a0\),v12
+-[ 	]+[0-9a-f]+:[ 	]+7cc56207[ 	]+vlxseg4ei512.v[ 	]+v4,\(a0\),v12,v0.t
+-[ 	]+[0-9a-f]+:[ 	]+7ec56227[ 	]+vsxseg4ei512.v[ 	]+v4,\(a0\),v12
+-[ 	]+[0-9a-f]+:[ 	]+7ec56227[ 	]+vsxseg4ei512.v[ 	]+v4,\(a0\),v12
+-[ 	]+[0-9a-f]+:[ 	]+7cc56227[ 	]+vsxseg4ei512.v[ 	]+v4,\(a0\),v12,v0.t
+-[ 	]+[0-9a-f]+:[ 	]+9ec56207[ 	]+vlxseg5ei512.v[ 	]+v4,\(a0\),v12
+-[ 	]+[0-9a-f]+:[ 	]+9ec56207[ 	]+vlxseg5ei512.v[ 	]+v4,\(a0\),v12
+-[ 	]+[0-9a-f]+:[ 	]+9cc56207[ 	]+vlxseg5ei512.v[ 	]+v4,\(a0\),v12,v0.t
+-[ 	]+[0-9a-f]+:[ 	]+9ec56227[ 	]+vsxseg5ei512.v[ 	]+v4,\(a0\),v12
+-[ 	]+[0-9a-f]+:[ 	]+9ec56227[ 	]+vsxseg5ei512.v[ 	]+v4,\(a0\),v12
+-[ 	]+[0-9a-f]+:[ 	]+9cc56227[ 	]+vsxseg5ei512.v[ 	]+v4,\(a0\),v12,v0.t
+-[ 	]+[0-9a-f]+:[ 	]+bec56207[ 	]+vlxseg6ei512.v[ 	]+v4,\(a0\),v12
+-[ 	]+[0-9a-f]+:[ 	]+bec56207[ 	]+vlxseg6ei512.v[ 	]+v4,\(a0\),v12
+-[ 	]+[0-9a-f]+:[ 	]+bcc56207[ 	]+vlxseg6ei512.v[ 	]+v4,\(a0\),v12,v0.t
+-[ 	]+[0-9a-f]+:[ 	]+bec56227[ 	]+vsxseg6ei512.v[ 	]+v4,\(a0\),v12
+-[ 	]+[0-9a-f]+:[ 	]+bec56227[ 	]+vsxseg6ei512.v[ 	]+v4,\(a0\),v12
+-[ 	]+[0-9a-f]+:[ 	]+bcc56227[ 	]+vsxseg6ei512.v[ 	]+v4,\(a0\),v12,v0.t
+-[ 	]+[0-9a-f]+:[ 	]+dec56207[ 	]+vlxseg7ei512.v[ 	]+v4,\(a0\),v12
+-[ 	]+[0-9a-f]+:[ 	]+dec56207[ 	]+vlxseg7ei512.v[ 	]+v4,\(a0\),v12
+-[ 	]+[0-9a-f]+:[ 	]+dcc56207[ 	]+vlxseg7ei512.v[ 	]+v4,\(a0\),v12,v0.t
+-[ 	]+[0-9a-f]+:[ 	]+dec56227[ 	]+vsxseg7ei512.v[ 	]+v4,\(a0\),v12
+-[ 	]+[0-9a-f]+:[ 	]+dec56227[ 	]+vsxseg7ei512.v[ 	]+v4,\(a0\),v12
+-[ 	]+[0-9a-f]+:[ 	]+dcc56227[ 	]+vsxseg7ei512.v[ 	]+v4,\(a0\),v12,v0.t
+-[ 	]+[0-9a-f]+:[ 	]+fec56207[ 	]+vlxseg8ei512.v[ 	]+v4,\(a0\),v12
+-[ 	]+[0-9a-f]+:[ 	]+fec56207[ 	]+vlxseg8ei512.v[ 	]+v4,\(a0\),v12
+-[ 	]+[0-9a-f]+:[ 	]+fcc56207[ 	]+vlxseg8ei512.v[ 	]+v4,\(a0\),v12,v0.t
+-[ 	]+[0-9a-f]+:[ 	]+fec56227[ 	]+vsxseg8ei512.v[ 	]+v4,\(a0\),v12
+-[ 	]+[0-9a-f]+:[ 	]+fec56227[ 	]+vsxseg8ei512.v[ 	]+v4,\(a0\),v12
+-[ 	]+[0-9a-f]+:[ 	]+fcc56227[ 	]+vsxseg8ei512.v[ 	]+v4,\(a0\),v12,v0.t
+-[ 	]+[0-9a-f]+:[ 	]+3ec57207[ 	]+vlxseg2ei1024.v[ 	]+v4,\(a0\),v12
+-[ 	]+[0-9a-f]+:[ 	]+3ec57207[ 	]+vlxseg2ei1024.v[ 	]+v4,\(a0\),v12
+-[ 	]+[0-9a-f]+:[ 	]+3cc57207[ 	]+vlxseg2ei1024.v[ 	]+v4,\(a0\),v12,v0.t
+-[ 	]+[0-9a-f]+:[ 	]+3ec57227[ 	]+vsxseg2ei1024.v[ 	]+v4,\(a0\),v12
+-[ 	]+[0-9a-f]+:[ 	]+3ec57227[ 	]+vsxseg2ei1024.v[ 	]+v4,\(a0\),v12
+-[ 	]+[0-9a-f]+:[ 	]+3cc57227[ 	]+vsxseg2ei1024.v[ 	]+v4,\(a0\),v12,v0.t
+-[ 	]+[0-9a-f]+:[ 	]+5ec57207[ 	]+vlxseg3ei1024.v[ 	]+v4,\(a0\),v12
+-[ 	]+[0-9a-f]+:[ 	]+5ec57207[ 	]+vlxseg3ei1024.v[ 	]+v4,\(a0\),v12
+-[ 	]+[0-9a-f]+:[ 	]+5cc57207[ 	]+vlxseg3ei1024.v[ 	]+v4,\(a0\),v12,v0.t
+-[ 	]+[0-9a-f]+:[ 	]+5ec57227[ 	]+vsxseg3ei1024.v[ 	]+v4,\(a0\),v12
+-[ 	]+[0-9a-f]+:[ 	]+5ec57227[ 	]+vsxseg3ei1024.v[ 	]+v4,\(a0\),v12
+-[ 	]+[0-9a-f]+:[ 	]+5cc57227[ 	]+vsxseg3ei1024.v[ 	]+v4,\(a0\),v12,v0.t
+-[ 	]+[0-9a-f]+:[ 	]+7ec57207[ 	]+vlxseg4ei1024.v[ 	]+v4,\(a0\),v12
+-[ 	]+[0-9a-f]+:[ 	]+7ec57207[ 	]+vlxseg4ei1024.v[ 	]+v4,\(a0\),v12
+-[ 	]+[0-9a-f]+:[ 	]+7cc57207[ 	]+vlxseg4ei1024.v[ 	]+v4,\(a0\),v12,v0.t
+-[ 	]+[0-9a-f]+:[ 	]+7ec57227[ 	]+vsxseg4ei1024.v[ 	]+v4,\(a0\),v12
+-[ 	]+[0-9a-f]+:[ 	]+7ec57227[ 	]+vsxseg4ei1024.v[ 	]+v4,\(a0\),v12
+-[ 	]+[0-9a-f]+:[ 	]+7cc57227[ 	]+vsxseg4ei1024.v[ 	]+v4,\(a0\),v12,v0.t
+-[ 	]+[0-9a-f]+:[ 	]+9ec57207[ 	]+vlxseg5ei1024.v[ 	]+v4,\(a0\),v12
+-[ 	]+[0-9a-f]+:[ 	]+9ec57207[ 	]+vlxseg5ei1024.v[ 	]+v4,\(a0\),v12
+-[ 	]+[0-9a-f]+:[ 	]+9cc57207[ 	]+vlxseg5ei1024.v[ 	]+v4,\(a0\),v12,v0.t
+-[ 	]+[0-9a-f]+:[ 	]+9ec57227[ 	]+vsxseg5ei1024.v[ 	]+v4,\(a0\),v12
+-[ 	]+[0-9a-f]+:[ 	]+9ec57227[ 	]+vsxseg5ei1024.v[ 	]+v4,\(a0\),v12
+-[ 	]+[0-9a-f]+:[ 	]+9cc57227[ 	]+vsxseg5ei1024.v[ 	]+v4,\(a0\),v12,v0.t
+-[ 	]+[0-9a-f]+:[ 	]+bec57207[ 	]+vlxseg6ei1024.v[ 	]+v4,\(a0\),v12
+-[ 	]+[0-9a-f]+:[ 	]+bec57207[ 	]+vlxseg6ei1024.v[ 	]+v4,\(a0\),v12
+-[ 	]+[0-9a-f]+:[ 	]+bcc57207[ 	]+vlxseg6ei1024.v[ 	]+v4,\(a0\),v12,v0.t
+-[ 	]+[0-9a-f]+:[ 	]+bec57227[ 	]+vsxseg6ei1024.v[ 	]+v4,\(a0\),v12
+-[ 	]+[0-9a-f]+:[ 	]+bec57227[ 	]+vsxseg6ei1024.v[ 	]+v4,\(a0\),v12
+-[ 	]+[0-9a-f]+:[ 	]+bcc57227[ 	]+vsxseg6ei1024.v[ 	]+v4,\(a0\),v12,v0.t
+-[ 	]+[0-9a-f]+:[ 	]+dec57207[ 	]+vlxseg7ei1024.v[ 	]+v4,\(a0\),v12
+-[ 	]+[0-9a-f]+:[ 	]+dec57207[ 	]+vlxseg7ei1024.v[ 	]+v4,\(a0\),v12
+-[ 	]+[0-9a-f]+:[ 	]+dcc57207[ 	]+vlxseg7ei1024.v[ 	]+v4,\(a0\),v12,v0.t
+-[ 	]+[0-9a-f]+:[ 	]+dec57227[ 	]+vsxseg7ei1024.v[ 	]+v4,\(a0\),v12
+-[ 	]+[0-9a-f]+:[ 	]+dec57227[ 	]+vsxseg7ei1024.v[ 	]+v4,\(a0\),v12
+-[ 	]+[0-9a-f]+:[ 	]+dcc57227[ 	]+vsxseg7ei1024.v[ 	]+v4,\(a0\),v12,v0.t
+-[ 	]+[0-9a-f]+:[ 	]+fec57207[ 	]+vlxseg8ei1024.v[ 	]+v4,\(a0\),v12
+-[ 	]+[0-9a-f]+:[ 	]+fec57207[ 	]+vlxseg8ei1024.v[ 	]+v4,\(a0\),v12
+-[ 	]+[0-9a-f]+:[ 	]+fcc57207[ 	]+vlxseg8ei1024.v[ 	]+v4,\(a0\),v12,v0.t
+-[ 	]+[0-9a-f]+:[ 	]+fec57227[ 	]+vsxseg8ei1024.v[ 	]+v4,\(a0\),v12
+-[ 	]+[0-9a-f]+:[ 	]+fec57227[ 	]+vsxseg8ei1024.v[ 	]+v4,\(a0\),v12
+-[ 	]+[0-9a-f]+:[ 	]+fcc57227[ 	]+vsxseg8ei1024.v[ 	]+v4,\(a0\),v12,v0.t
++[ 	]+[0-9a-f]+:[ 	]+2ec50207[ 	]+vloxseg2ei8.v[ 	]+v4,\(a0\),v12
++[ 	]+[0-9a-f]+:[ 	]+2ec50207[ 	]+vloxseg2ei8.v[ 	]+v4,\(a0\),v12
++[ 	]+[0-9a-f]+:[ 	]+2cc50207[ 	]+vloxseg2ei8.v[ 	]+v4,\(a0\),v12,v0.t
++[ 	]+[0-9a-f]+:[ 	]+2ec50227[ 	]+vsoxseg2ei8.v[ 	]+v4,\(a0\),v12
++[ 	]+[0-9a-f]+:[ 	]+2ec50227[ 	]+vsoxseg2ei8.v[ 	]+v4,\(a0\),v12
++[ 	]+[0-9a-f]+:[ 	]+2cc50227[ 	]+vsoxseg2ei8.v[ 	]+v4,\(a0\),v12,v0.t
++[ 	]+[0-9a-f]+:[ 	]+4ec50207[ 	]+vloxseg3ei8.v[ 	]+v4,\(a0\),v12
++[ 	]+[0-9a-f]+:[ 	]+4ec50207[ 	]+vloxseg3ei8.v[ 	]+v4,\(a0\),v12
++[ 	]+[0-9a-f]+:[ 	]+4cc50207[ 	]+vloxseg3ei8.v[ 	]+v4,\(a0\),v12,v0.t
++[ 	]+[0-9a-f]+:[ 	]+4ec50227[ 	]+vsoxseg3ei8.v[ 	]+v4,\(a0\),v12
++[ 	]+[0-9a-f]+:[ 	]+4ec50227[ 	]+vsoxseg3ei8.v[ 	]+v4,\(a0\),v12
++[ 	]+[0-9a-f]+:[ 	]+4cc50227[ 	]+vsoxseg3ei8.v[ 	]+v4,\(a0\),v12,v0.t
++[ 	]+[0-9a-f]+:[ 	]+6ec50207[ 	]+vloxseg4ei8.v[ 	]+v4,\(a0\),v12
++[ 	]+[0-9a-f]+:[ 	]+6ec50207[ 	]+vloxseg4ei8.v[ 	]+v4,\(a0\),v12
++[ 	]+[0-9a-f]+:[ 	]+6cc50207[ 	]+vloxseg4ei8.v[ 	]+v4,\(a0\),v12,v0.t
++[ 	]+[0-9a-f]+:[ 	]+6ec50227[ 	]+vsoxseg4ei8.v[ 	]+v4,\(a0\),v12
++[ 	]+[0-9a-f]+:[ 	]+6ec50227[ 	]+vsoxseg4ei8.v[ 	]+v4,\(a0\),v12
++[ 	]+[0-9a-f]+:[ 	]+6cc50227[ 	]+vsoxseg4ei8.v[ 	]+v4,\(a0\),v12,v0.t
++[ 	]+[0-9a-f]+:[ 	]+8ec50207[ 	]+vloxseg5ei8.v[ 	]+v4,\(a0\),v12
++[ 	]+[0-9a-f]+:[ 	]+8ec50207[ 	]+vloxseg5ei8.v[ 	]+v4,\(a0\),v12
++[ 	]+[0-9a-f]+:[ 	]+8cc50207[ 	]+vloxseg5ei8.v[ 	]+v4,\(a0\),v12,v0.t
++[ 	]+[0-9a-f]+:[ 	]+8ec50227[ 	]+vsoxseg5ei8.v[ 	]+v4,\(a0\),v12
++[ 	]+[0-9a-f]+:[ 	]+8ec50227[ 	]+vsoxseg5ei8.v[ 	]+v4,\(a0\),v12
++[ 	]+[0-9a-f]+:[ 	]+8cc50227[ 	]+vsoxseg5ei8.v[ 	]+v4,\(a0\),v12,v0.t
++[ 	]+[0-9a-f]+:[ 	]+aec50207[ 	]+vloxseg6ei8.v[ 	]+v4,\(a0\),v12
++[ 	]+[0-9a-f]+:[ 	]+aec50207[ 	]+vloxseg6ei8.v[ 	]+v4,\(a0\),v12
++[ 	]+[0-9a-f]+:[ 	]+acc50207[ 	]+vloxseg6ei8.v[ 	]+v4,\(a0\),v12,v0.t
++[ 	]+[0-9a-f]+:[ 	]+aec50227[ 	]+vsoxseg6ei8.v[ 	]+v4,\(a0\),v12
++[ 	]+[0-9a-f]+:[ 	]+aec50227[ 	]+vsoxseg6ei8.v[ 	]+v4,\(a0\),v12
++[ 	]+[0-9a-f]+:[ 	]+acc50227[ 	]+vsoxseg6ei8.v[ 	]+v4,\(a0\),v12,v0.t
++[ 	]+[0-9a-f]+:[ 	]+cec50207[ 	]+vloxseg7ei8.v[ 	]+v4,\(a0\),v12
++[ 	]+[0-9a-f]+:[ 	]+cec50207[ 	]+vloxseg7ei8.v[ 	]+v4,\(a0\),v12
++[ 	]+[0-9a-f]+:[ 	]+ccc50207[ 	]+vloxseg7ei8.v[ 	]+v4,\(a0\),v12,v0.t
++[ 	]+[0-9a-f]+:[ 	]+cec50227[ 	]+vsoxseg7ei8.v[ 	]+v4,\(a0\),v12
++[ 	]+[0-9a-f]+:[ 	]+cec50227[ 	]+vsoxseg7ei8.v[ 	]+v4,\(a0\),v12
++[ 	]+[0-9a-f]+:[ 	]+ccc50227[ 	]+vsoxseg7ei8.v[ 	]+v4,\(a0\),v12,v0.t
++[ 	]+[0-9a-f]+:[ 	]+eec50207[ 	]+vloxseg8ei8.v[ 	]+v4,\(a0\),v12
++[ 	]+[0-9a-f]+:[ 	]+eec50207[ 	]+vloxseg8ei8.v[ 	]+v4,\(a0\),v12
++[ 	]+[0-9a-f]+:[ 	]+ecc50207[ 	]+vloxseg8ei8.v[ 	]+v4,\(a0\),v12,v0.t
++[ 	]+[0-9a-f]+:[ 	]+eec50227[ 	]+vsoxseg8ei8.v[ 	]+v4,\(a0\),v12
++[ 	]+[0-9a-f]+:[ 	]+eec50227[ 	]+vsoxseg8ei8.v[ 	]+v4,\(a0\),v12
++[ 	]+[0-9a-f]+:[ 	]+ecc50227[ 	]+vsoxseg8ei8.v[ 	]+v4,\(a0\),v12,v0.t
++[ 	]+[0-9a-f]+:[ 	]+2ec55207[ 	]+vloxseg2ei16.v[ 	]+v4,\(a0\),v12
++[ 	]+[0-9a-f]+:[ 	]+2ec55207[ 	]+vloxseg2ei16.v[ 	]+v4,\(a0\),v12
++[ 	]+[0-9a-f]+:[ 	]+2cc55207[ 	]+vloxseg2ei16.v[ 	]+v4,\(a0\),v12,v0.t
++[ 	]+[0-9a-f]+:[ 	]+2ec55227[ 	]+vsoxseg2ei16.v[ 	]+v4,\(a0\),v12
++[ 	]+[0-9a-f]+:[ 	]+2ec55227[ 	]+vsoxseg2ei16.v[ 	]+v4,\(a0\),v12
++[ 	]+[0-9a-f]+:[ 	]+2cc55227[ 	]+vsoxseg2ei16.v[ 	]+v4,\(a0\),v12,v0.t
++[ 	]+[0-9a-f]+:[ 	]+4ec55207[ 	]+vloxseg3ei16.v[ 	]+v4,\(a0\),v12
++[ 	]+[0-9a-f]+:[ 	]+4ec55207[ 	]+vloxseg3ei16.v[ 	]+v4,\(a0\),v12
++[ 	]+[0-9a-f]+:[ 	]+4cc55207[ 	]+vloxseg3ei16.v[ 	]+v4,\(a0\),v12,v0.t
++[ 	]+[0-9a-f]+:[ 	]+4ec55227[ 	]+vsoxseg3ei16.v[ 	]+v4,\(a0\),v12
++[ 	]+[0-9a-f]+:[ 	]+4ec55227[ 	]+vsoxseg3ei16.v[ 	]+v4,\(a0\),v12
++[ 	]+[0-9a-f]+:[ 	]+4cc55227[ 	]+vsoxseg3ei16.v[ 	]+v4,\(a0\),v12,v0.t
++[ 	]+[0-9a-f]+:[ 	]+6ec55207[ 	]+vloxseg4ei16.v[ 	]+v4,\(a0\),v12
++[ 	]+[0-9a-f]+:[ 	]+6ec55207[ 	]+vloxseg4ei16.v[ 	]+v4,\(a0\),v12
++[ 	]+[0-9a-f]+:[ 	]+6cc55207[ 	]+vloxseg4ei16.v[ 	]+v4,\(a0\),v12,v0.t
++[ 	]+[0-9a-f]+:[ 	]+6ec55227[ 	]+vsoxseg4ei16.v[ 	]+v4,\(a0\),v12
++[ 	]+[0-9a-f]+:[ 	]+6ec55227[ 	]+vsoxseg4ei16.v[ 	]+v4,\(a0\),v12
++[ 	]+[0-9a-f]+:[ 	]+6cc55227[ 	]+vsoxseg4ei16.v[ 	]+v4,\(a0\),v12,v0.t
++[ 	]+[0-9a-f]+:[ 	]+8ec55207[ 	]+vloxseg5ei16.v[ 	]+v4,\(a0\),v12
++[ 	]+[0-9a-f]+:[ 	]+8ec55207[ 	]+vloxseg5ei16.v[ 	]+v4,\(a0\),v12
++[ 	]+[0-9a-f]+:[ 	]+8cc55207[ 	]+vloxseg5ei16.v[ 	]+v4,\(a0\),v12,v0.t
++[ 	]+[0-9a-f]+:[ 	]+8ec55227[ 	]+vsoxseg5ei16.v[ 	]+v4,\(a0\),v12
++[ 	]+[0-9a-f]+:[ 	]+8ec55227[ 	]+vsoxseg5ei16.v[ 	]+v4,\(a0\),v12
++[ 	]+[0-9a-f]+:[ 	]+8cc55227[ 	]+vsoxseg5ei16.v[ 	]+v4,\(a0\),v12,v0.t
++[ 	]+[0-9a-f]+:[ 	]+aec55207[ 	]+vloxseg6ei16.v[ 	]+v4,\(a0\),v12
++[ 	]+[0-9a-f]+:[ 	]+aec55207[ 	]+vloxseg6ei16.v[ 	]+v4,\(a0\),v12
++[ 	]+[0-9a-f]+:[ 	]+acc55207[ 	]+vloxseg6ei16.v[ 	]+v4,\(a0\),v12,v0.t
++[ 	]+[0-9a-f]+:[ 	]+aec55227[ 	]+vsoxseg6ei16.v[ 	]+v4,\(a0\),v12
++[ 	]+[0-9a-f]+:[ 	]+aec55227[ 	]+vsoxseg6ei16.v[ 	]+v4,\(a0\),v12
++[ 	]+[0-9a-f]+:[ 	]+acc55227[ 	]+vsoxseg6ei16.v[ 	]+v4,\(a0\),v12,v0.t
++[ 	]+[0-9a-f]+:[ 	]+cec55207[ 	]+vloxseg7ei16.v[ 	]+v4,\(a0\),v12
++[ 	]+[0-9a-f]+:[ 	]+cec55207[ 	]+vloxseg7ei16.v[ 	]+v4,\(a0\),v12
++[ 	]+[0-9a-f]+:[ 	]+ccc55207[ 	]+vloxseg7ei16.v[ 	]+v4,\(a0\),v12,v0.t
++[ 	]+[0-9a-f]+:[ 	]+cec55227[ 	]+vsoxseg7ei16.v[ 	]+v4,\(a0\),v12
++[ 	]+[0-9a-f]+:[ 	]+cec55227[ 	]+vsoxseg7ei16.v[ 	]+v4,\(a0\),v12
++[ 	]+[0-9a-f]+:[ 	]+ccc55227[ 	]+vsoxseg7ei16.v[ 	]+v4,\(a0\),v12,v0.t
++[ 	]+[0-9a-f]+:[ 	]+eec55207[ 	]+vloxseg8ei16.v[ 	]+v4,\(a0\),v12
++[ 	]+[0-9a-f]+:[ 	]+eec55207[ 	]+vloxseg8ei16.v[ 	]+v4,\(a0\),v12
++[ 	]+[0-9a-f]+:[ 	]+ecc55207[ 	]+vloxseg8ei16.v[ 	]+v4,\(a0\),v12,v0.t
++[ 	]+[0-9a-f]+:[ 	]+eec55227[ 	]+vsoxseg8ei16.v[ 	]+v4,\(a0\),v12
++[ 	]+[0-9a-f]+:[ 	]+eec55227[ 	]+vsoxseg8ei16.v[ 	]+v4,\(a0\),v12
++[ 	]+[0-9a-f]+:[ 	]+ecc55227[ 	]+vsoxseg8ei16.v[ 	]+v4,\(a0\),v12,v0.t
++[ 	]+[0-9a-f]+:[ 	]+2ec56207[ 	]+vloxseg2ei32.v[ 	]+v4,\(a0\),v12
++[ 	]+[0-9a-f]+:[ 	]+2ec56207[ 	]+vloxseg2ei32.v[ 	]+v4,\(a0\),v12
++[ 	]+[0-9a-f]+:[ 	]+2cc56207[ 	]+vloxseg2ei32.v[ 	]+v4,\(a0\),v12,v0.t
++[ 	]+[0-9a-f]+:[ 	]+2ec56227[ 	]+vsoxseg2ei32.v[ 	]+v4,\(a0\),v12
++[ 	]+[0-9a-f]+:[ 	]+2ec56227[ 	]+vsoxseg2ei32.v[ 	]+v4,\(a0\),v12
++[ 	]+[0-9a-f]+:[ 	]+2cc56227[ 	]+vsoxseg2ei32.v[ 	]+v4,\(a0\),v12,v0.t
++[ 	]+[0-9a-f]+:[ 	]+4ec56207[ 	]+vloxseg3ei32.v[ 	]+v4,\(a0\),v12
++[ 	]+[0-9a-f]+:[ 	]+4ec56207[ 	]+vloxseg3ei32.v[ 	]+v4,\(a0\),v12
++[ 	]+[0-9a-f]+:[ 	]+4cc56207[ 	]+vloxseg3ei32.v[ 	]+v4,\(a0\),v12,v0.t
++[ 	]+[0-9a-f]+:[ 	]+4ec56227[ 	]+vsoxseg3ei32.v[ 	]+v4,\(a0\),v12
++[ 	]+[0-9a-f]+:[ 	]+4ec56227[ 	]+vsoxseg3ei32.v[ 	]+v4,\(a0\),v12
++[ 	]+[0-9a-f]+:[ 	]+4cc56227[ 	]+vsoxseg3ei32.v[ 	]+v4,\(a0\),v12,v0.t
++[ 	]+[0-9a-f]+:[ 	]+6ec56207[ 	]+vloxseg4ei32.v[ 	]+v4,\(a0\),v12
++[ 	]+[0-9a-f]+:[ 	]+6ec56207[ 	]+vloxseg4ei32.v[ 	]+v4,\(a0\),v12
++[ 	]+[0-9a-f]+:[ 	]+6cc56207[ 	]+vloxseg4ei32.v[ 	]+v4,\(a0\),v12,v0.t
++[ 	]+[0-9a-f]+:[ 	]+6ec56227[ 	]+vsoxseg4ei32.v[ 	]+v4,\(a0\),v12
++[ 	]+[0-9a-f]+:[ 	]+6ec56227[ 	]+vsoxseg4ei32.v[ 	]+v4,\(a0\),v12
++[ 	]+[0-9a-f]+:[ 	]+6cc56227[ 	]+vsoxseg4ei32.v[ 	]+v4,\(a0\),v12,v0.t
++[ 	]+[0-9a-f]+:[ 	]+8ec56207[ 	]+vloxseg5ei32.v[ 	]+v4,\(a0\),v12
++[ 	]+[0-9a-f]+:[ 	]+8ec56207[ 	]+vloxseg5ei32.v[ 	]+v4,\(a0\),v12
++[ 	]+[0-9a-f]+:[ 	]+8cc56207[ 	]+vloxseg5ei32.v[ 	]+v4,\(a0\),v12,v0.t
++[ 	]+[0-9a-f]+:[ 	]+8ec56227[ 	]+vsoxseg5ei32.v[ 	]+v4,\(a0\),v12
++[ 	]+[0-9a-f]+:[ 	]+8ec56227[ 	]+vsoxseg5ei32.v[ 	]+v4,\(a0\),v12
++[ 	]+[0-9a-f]+:[ 	]+8cc56227[ 	]+vsoxseg5ei32.v[ 	]+v4,\(a0\),v12,v0.t
++[ 	]+[0-9a-f]+:[ 	]+aec56207[ 	]+vloxseg6ei32.v[ 	]+v4,\(a0\),v12
++[ 	]+[0-9a-f]+:[ 	]+aec56207[ 	]+vloxseg6ei32.v[ 	]+v4,\(a0\),v12
++[ 	]+[0-9a-f]+:[ 	]+acc56207[ 	]+vloxseg6ei32.v[ 	]+v4,\(a0\),v12,v0.t
++[ 	]+[0-9a-f]+:[ 	]+aec56227[ 	]+vsoxseg6ei32.v[ 	]+v4,\(a0\),v12
++[ 	]+[0-9a-f]+:[ 	]+aec56227[ 	]+vsoxseg6ei32.v[ 	]+v4,\(a0\),v12
++[ 	]+[0-9a-f]+:[ 	]+acc56227[ 	]+vsoxseg6ei32.v[ 	]+v4,\(a0\),v12,v0.t
++[ 	]+[0-9a-f]+:[ 	]+cec56207[ 	]+vloxseg7ei32.v[ 	]+v4,\(a0\),v12
++[ 	]+[0-9a-f]+:[ 	]+cec56207[ 	]+vloxseg7ei32.v[ 	]+v4,\(a0\),v12
++[ 	]+[0-9a-f]+:[ 	]+ccc56207[ 	]+vloxseg7ei32.v[ 	]+v4,\(a0\),v12,v0.t
++[ 	]+[0-9a-f]+:[ 	]+cec56227[ 	]+vsoxseg7ei32.v[ 	]+v4,\(a0\),v12
++[ 	]+[0-9a-f]+:[ 	]+cec56227[ 	]+vsoxseg7ei32.v[ 	]+v4,\(a0\),v12
++[ 	]+[0-9a-f]+:[ 	]+ccc56227[ 	]+vsoxseg7ei32.v[ 	]+v4,\(a0\),v12,v0.t
++[ 	]+[0-9a-f]+:[ 	]+eec56207[ 	]+vloxseg8ei32.v[ 	]+v4,\(a0\),v12
++[ 	]+[0-9a-f]+:[ 	]+eec56207[ 	]+vloxseg8ei32.v[ 	]+v4,\(a0\),v12
++[ 	]+[0-9a-f]+:[ 	]+ecc56207[ 	]+vloxseg8ei32.v[ 	]+v4,\(a0\),v12,v0.t
++[ 	]+[0-9a-f]+:[ 	]+eec56227[ 	]+vsoxseg8ei32.v[ 	]+v4,\(a0\),v12
++[ 	]+[0-9a-f]+:[ 	]+eec56227[ 	]+vsoxseg8ei32.v[ 	]+v4,\(a0\),v12
++[ 	]+[0-9a-f]+:[ 	]+ecc56227[ 	]+vsoxseg8ei32.v[ 	]+v4,\(a0\),v12,v0.t
++[ 	]+[0-9a-f]+:[ 	]+2ec57207[ 	]+vloxseg2ei64.v[ 	]+v4,\(a0\),v12
++[ 	]+[0-9a-f]+:[ 	]+2ec57207[ 	]+vloxseg2ei64.v[ 	]+v4,\(a0\),v12
++[ 	]+[0-9a-f]+:[ 	]+2cc57207[ 	]+vloxseg2ei64.v[ 	]+v4,\(a0\),v12,v0.t
++[ 	]+[0-9a-f]+:[ 	]+2ec57227[ 	]+vsoxseg2ei64.v[ 	]+v4,\(a0\),v12
++[ 	]+[0-9a-f]+:[ 	]+2ec57227[ 	]+vsoxseg2ei64.v[ 	]+v4,\(a0\),v12
++[ 	]+[0-9a-f]+:[ 	]+2cc57227[ 	]+vsoxseg2ei64.v[ 	]+v4,\(a0\),v12,v0.t
++[ 	]+[0-9a-f]+:[ 	]+4ec57207[ 	]+vloxseg3ei64.v[ 	]+v4,\(a0\),v12
++[ 	]+[0-9a-f]+:[ 	]+4ec57207[ 	]+vloxseg3ei64.v[ 	]+v4,\(a0\),v12
++[ 	]+[0-9a-f]+:[ 	]+4cc57207[ 	]+vloxseg3ei64.v[ 	]+v4,\(a0\),v12,v0.t
++[ 	]+[0-9a-f]+:[ 	]+4ec57227[ 	]+vsoxseg3ei64.v[ 	]+v4,\(a0\),v12
++[ 	]+[0-9a-f]+:[ 	]+4ec57227[ 	]+vsoxseg3ei64.v[ 	]+v4,\(a0\),v12
++[ 	]+[0-9a-f]+:[ 	]+4cc57227[ 	]+vsoxseg3ei64.v[ 	]+v4,\(a0\),v12,v0.t
++[ 	]+[0-9a-f]+:[ 	]+6ec57207[ 	]+vloxseg4ei64.v[ 	]+v4,\(a0\),v12
++[ 	]+[0-9a-f]+:[ 	]+6ec57207[ 	]+vloxseg4ei64.v[ 	]+v4,\(a0\),v12
++[ 	]+[0-9a-f]+:[ 	]+6cc57207[ 	]+vloxseg4ei64.v[ 	]+v4,\(a0\),v12,v0.t
++[ 	]+[0-9a-f]+:[ 	]+6ec57227[ 	]+vsoxseg4ei64.v[ 	]+v4,\(a0\),v12
++[ 	]+[0-9a-f]+:[ 	]+6ec57227[ 	]+vsoxseg4ei64.v[ 	]+v4,\(a0\),v12
++[ 	]+[0-9a-f]+:[ 	]+6cc57227[ 	]+vsoxseg4ei64.v[ 	]+v4,\(a0\),v12,v0.t
++[ 	]+[0-9a-f]+:[ 	]+8ec57207[ 	]+vloxseg5ei64.v[ 	]+v4,\(a0\),v12
++[ 	]+[0-9a-f]+:[ 	]+8ec57207[ 	]+vloxseg5ei64.v[ 	]+v4,\(a0\),v12
++[ 	]+[0-9a-f]+:[ 	]+8cc57207[ 	]+vloxseg5ei64.v[ 	]+v4,\(a0\),v12,v0.t
++[ 	]+[0-9a-f]+:[ 	]+8ec57227[ 	]+vsoxseg5ei64.v[ 	]+v4,\(a0\),v12
++[ 	]+[0-9a-f]+:[ 	]+8ec57227[ 	]+vsoxseg5ei64.v[ 	]+v4,\(a0\),v12
++[ 	]+[0-9a-f]+:[ 	]+8cc57227[ 	]+vsoxseg5ei64.v[ 	]+v4,\(a0\),v12,v0.t
++[ 	]+[0-9a-f]+:[ 	]+aec57207[ 	]+vloxseg6ei64.v[ 	]+v4,\(a0\),v12
++[ 	]+[0-9a-f]+:[ 	]+aec57207[ 	]+vloxseg6ei64.v[ 	]+v4,\(a0\),v12
++[ 	]+[0-9a-f]+:[ 	]+acc57207[ 	]+vloxseg6ei64.v[ 	]+v4,\(a0\),v12,v0.t
++[ 	]+[0-9a-f]+:[ 	]+aec57227[ 	]+vsoxseg6ei64.v[ 	]+v4,\(a0\),v12
++[ 	]+[0-9a-f]+:[ 	]+aec57227[ 	]+vsoxseg6ei64.v[ 	]+v4,\(a0\),v12
++[ 	]+[0-9a-f]+:[ 	]+acc57227[ 	]+vsoxseg6ei64.v[ 	]+v4,\(a0\),v12,v0.t
++[ 	]+[0-9a-f]+:[ 	]+cec57207[ 	]+vloxseg7ei64.v[ 	]+v4,\(a0\),v12
++[ 	]+[0-9a-f]+:[ 	]+cec57207[ 	]+vloxseg7ei64.v[ 	]+v4,\(a0\),v12
++[ 	]+[0-9a-f]+:[ 	]+ccc57207[ 	]+vloxseg7ei64.v[ 	]+v4,\(a0\),v12,v0.t
++[ 	]+[0-9a-f]+:[ 	]+cec57227[ 	]+vsoxseg7ei64.v[ 	]+v4,\(a0\),v12
++[ 	]+[0-9a-f]+:[ 	]+cec57227[ 	]+vsoxseg7ei64.v[ 	]+v4,\(a0\),v12
++[ 	]+[0-9a-f]+:[ 	]+ccc57227[ 	]+vsoxseg7ei64.v[ 	]+v4,\(a0\),v12,v0.t
++[ 	]+[0-9a-f]+:[ 	]+eec57207[ 	]+vloxseg8ei64.v[ 	]+v4,\(a0\),v12
++[ 	]+[0-9a-f]+:[ 	]+eec57207[ 	]+vloxseg8ei64.v[ 	]+v4,\(a0\),v12
++[ 	]+[0-9a-f]+:[ 	]+ecc57207[ 	]+vloxseg8ei64.v[ 	]+v4,\(a0\),v12,v0.t
++[ 	]+[0-9a-f]+:[ 	]+eec57227[ 	]+vsoxseg8ei64.v[ 	]+v4,\(a0\),v12
++[ 	]+[0-9a-f]+:[ 	]+eec57227[ 	]+vsoxseg8ei64.v[ 	]+v4,\(a0\),v12
++[ 	]+[0-9a-f]+:[ 	]+ecc57227[ 	]+vsoxseg8ei64.v[ 	]+v4,\(a0\),v12,v0.t
++[ 	]+[0-9a-f]+:[ 	]+3ec50207[ 	]+vloxseg2ei128.v[ 	]+v4,\(a0\),v12
++[ 	]+[0-9a-f]+:[ 	]+3ec50207[ 	]+vloxseg2ei128.v[ 	]+v4,\(a0\),v12
++[ 	]+[0-9a-f]+:[ 	]+3cc50207[ 	]+vloxseg2ei128.v[ 	]+v4,\(a0\),v12,v0.t
++[ 	]+[0-9a-f]+:[ 	]+3ec50227[ 	]+vsoxseg2ei128.v[ 	]+v4,\(a0\),v12
++[ 	]+[0-9a-f]+:[ 	]+3ec50227[ 	]+vsoxseg2ei128.v[ 	]+v4,\(a0\),v12
++[ 	]+[0-9a-f]+:[ 	]+3cc50227[ 	]+vsoxseg2ei128.v[ 	]+v4,\(a0\),v12,v0.t
++[ 	]+[0-9a-f]+:[ 	]+5ec50207[ 	]+vloxseg3ei128.v[ 	]+v4,\(a0\),v12
++[ 	]+[0-9a-f]+:[ 	]+5ec50207[ 	]+vloxseg3ei128.v[ 	]+v4,\(a0\),v12
++[ 	]+[0-9a-f]+:[ 	]+5cc50207[ 	]+vloxseg3ei128.v[ 	]+v4,\(a0\),v12,v0.t
++[ 	]+[0-9a-f]+:[ 	]+5ec50227[ 	]+vsoxseg3ei128.v[ 	]+v4,\(a0\),v12
++[ 	]+[0-9a-f]+:[ 	]+5ec50227[ 	]+vsoxseg3ei128.v[ 	]+v4,\(a0\),v12
++[ 	]+[0-9a-f]+:[ 	]+5cc50227[ 	]+vsoxseg3ei128.v[ 	]+v4,\(a0\),v12,v0.t
++[ 	]+[0-9a-f]+:[ 	]+7ec50207[ 	]+vloxseg4ei128.v[ 	]+v4,\(a0\),v12
++[ 	]+[0-9a-f]+:[ 	]+7ec50207[ 	]+vloxseg4ei128.v[ 	]+v4,\(a0\),v12
++[ 	]+[0-9a-f]+:[ 	]+7cc50207[ 	]+vloxseg4ei128.v[ 	]+v4,\(a0\),v12,v0.t
++[ 	]+[0-9a-f]+:[ 	]+7ec50227[ 	]+vsoxseg4ei128.v[ 	]+v4,\(a0\),v12
++[ 	]+[0-9a-f]+:[ 	]+7ec50227[ 	]+vsoxseg4ei128.v[ 	]+v4,\(a0\),v12
++[ 	]+[0-9a-f]+:[ 	]+7cc50227[ 	]+vsoxseg4ei128.v[ 	]+v4,\(a0\),v12,v0.t
++[ 	]+[0-9a-f]+:[ 	]+9ec50207[ 	]+vloxseg5ei128.v[ 	]+v4,\(a0\),v12
++[ 	]+[0-9a-f]+:[ 	]+9ec50207[ 	]+vloxseg5ei128.v[ 	]+v4,\(a0\),v12
++[ 	]+[0-9a-f]+:[ 	]+9cc50207[ 	]+vloxseg5ei128.v[ 	]+v4,\(a0\),v12,v0.t
++[ 	]+[0-9a-f]+:[ 	]+9ec50227[ 	]+vsoxseg5ei128.v[ 	]+v4,\(a0\),v12
++[ 	]+[0-9a-f]+:[ 	]+9ec50227[ 	]+vsoxseg5ei128.v[ 	]+v4,\(a0\),v12
++[ 	]+[0-9a-f]+:[ 	]+9cc50227[ 	]+vsoxseg5ei128.v[ 	]+v4,\(a0\),v12,v0.t
++[ 	]+[0-9a-f]+:[ 	]+bec50207[ 	]+vloxseg6ei128.v[ 	]+v4,\(a0\),v12
++[ 	]+[0-9a-f]+:[ 	]+bec50207[ 	]+vloxseg6ei128.v[ 	]+v4,\(a0\),v12
++[ 	]+[0-9a-f]+:[ 	]+bcc50207[ 	]+vloxseg6ei128.v[ 	]+v4,\(a0\),v12,v0.t
++[ 	]+[0-9a-f]+:[ 	]+bec50227[ 	]+vsoxseg6ei128.v[ 	]+v4,\(a0\),v12
++[ 	]+[0-9a-f]+:[ 	]+bec50227[ 	]+vsoxseg6ei128.v[ 	]+v4,\(a0\),v12
++[ 	]+[0-9a-f]+:[ 	]+bcc50227[ 	]+vsoxseg6ei128.v[ 	]+v4,\(a0\),v12,v0.t
++[ 	]+[0-9a-f]+:[ 	]+dec50207[ 	]+vloxseg7ei128.v[ 	]+v4,\(a0\),v12
++[ 	]+[0-9a-f]+:[ 	]+dec50207[ 	]+vloxseg7ei128.v[ 	]+v4,\(a0\),v12
++[ 	]+[0-9a-f]+:[ 	]+dcc50207[ 	]+vloxseg7ei128.v[ 	]+v4,\(a0\),v12,v0.t
++[ 	]+[0-9a-f]+:[ 	]+dec50227[ 	]+vsoxseg7ei128.v[ 	]+v4,\(a0\),v12
++[ 	]+[0-9a-f]+:[ 	]+dec50227[ 	]+vsoxseg7ei128.v[ 	]+v4,\(a0\),v12
++[ 	]+[0-9a-f]+:[ 	]+dcc50227[ 	]+vsoxseg7ei128.v[ 	]+v4,\(a0\),v12,v0.t
++[ 	]+[0-9a-f]+:[ 	]+fec50207[ 	]+vloxseg8ei128.v[ 	]+v4,\(a0\),v12
++[ 	]+[0-9a-f]+:[ 	]+fec50207[ 	]+vloxseg8ei128.v[ 	]+v4,\(a0\),v12
++[ 	]+[0-9a-f]+:[ 	]+fcc50207[ 	]+vloxseg8ei128.v[ 	]+v4,\(a0\),v12,v0.t
++[ 	]+[0-9a-f]+:[ 	]+fec50227[ 	]+vsoxseg8ei128.v[ 	]+v4,\(a0\),v12
++[ 	]+[0-9a-f]+:[ 	]+fec50227[ 	]+vsoxseg8ei128.v[ 	]+v4,\(a0\),v12
++[ 	]+[0-9a-f]+:[ 	]+fcc50227[ 	]+vsoxseg8ei128.v[ 	]+v4,\(a0\),v12,v0.t
++[ 	]+[0-9a-f]+:[ 	]+3ec55207[ 	]+vloxseg2ei256.v[ 	]+v4,\(a0\),v12
++[ 	]+[0-9a-f]+:[ 	]+3ec55207[ 	]+vloxseg2ei256.v[ 	]+v4,\(a0\),v12
++[ 	]+[0-9a-f]+:[ 	]+3cc55207[ 	]+vloxseg2ei256.v[ 	]+v4,\(a0\),v12,v0.t
++[ 	]+[0-9a-f]+:[ 	]+3ec55227[ 	]+vsoxseg2ei256.v[ 	]+v4,\(a0\),v12
++[ 	]+[0-9a-f]+:[ 	]+3ec55227[ 	]+vsoxseg2ei256.v[ 	]+v4,\(a0\),v12
++[ 	]+[0-9a-f]+:[ 	]+3cc55227[ 	]+vsoxseg2ei256.v[ 	]+v4,\(a0\),v12,v0.t
++[ 	]+[0-9a-f]+:[ 	]+5ec55207[ 	]+vloxseg3ei256.v[ 	]+v4,\(a0\),v12
++[ 	]+[0-9a-f]+:[ 	]+5ec55207[ 	]+vloxseg3ei256.v[ 	]+v4,\(a0\),v12
++[ 	]+[0-9a-f]+:[ 	]+5cc55207[ 	]+vloxseg3ei256.v[ 	]+v4,\(a0\),v12,v0.t
++[ 	]+[0-9a-f]+:[ 	]+5ec55227[ 	]+vsoxseg3ei256.v[ 	]+v4,\(a0\),v12
++[ 	]+[0-9a-f]+:[ 	]+5ec55227[ 	]+vsoxseg3ei256.v[ 	]+v4,\(a0\),v12
++[ 	]+[0-9a-f]+:[ 	]+5cc55227[ 	]+vsoxseg3ei256.v[ 	]+v4,\(a0\),v12,v0.t
++[ 	]+[0-9a-f]+:[ 	]+7ec55207[ 	]+vloxseg4ei256.v[ 	]+v4,\(a0\),v12
++[ 	]+[0-9a-f]+:[ 	]+7ec55207[ 	]+vloxseg4ei256.v[ 	]+v4,\(a0\),v12
++[ 	]+[0-9a-f]+:[ 	]+7cc55207[ 	]+vloxseg4ei256.v[ 	]+v4,\(a0\),v12,v0.t
++[ 	]+[0-9a-f]+:[ 	]+7ec55227[ 	]+vsoxseg4ei256.v[ 	]+v4,\(a0\),v12
++[ 	]+[0-9a-f]+:[ 	]+7ec55227[ 	]+vsoxseg4ei256.v[ 	]+v4,\(a0\),v12
++[ 	]+[0-9a-f]+:[ 	]+7cc55227[ 	]+vsoxseg4ei256.v[ 	]+v4,\(a0\),v12,v0.t
++[ 	]+[0-9a-f]+:[ 	]+9ec55207[ 	]+vloxseg5ei256.v[ 	]+v4,\(a0\),v12
++[ 	]+[0-9a-f]+:[ 	]+9ec55207[ 	]+vloxseg5ei256.v[ 	]+v4,\(a0\),v12
++[ 	]+[0-9a-f]+:[ 	]+9cc55207[ 	]+vloxseg5ei256.v[ 	]+v4,\(a0\),v12,v0.t
++[ 	]+[0-9a-f]+:[ 	]+9ec55227[ 	]+vsoxseg5ei256.v[ 	]+v4,\(a0\),v12
++[ 	]+[0-9a-f]+:[ 	]+9ec55227[ 	]+vsoxseg5ei256.v[ 	]+v4,\(a0\),v12
++[ 	]+[0-9a-f]+:[ 	]+9cc55227[ 	]+vsoxseg5ei256.v[ 	]+v4,\(a0\),v12,v0.t
++[ 	]+[0-9a-f]+:[ 	]+bec55207[ 	]+vloxseg6ei256.v[ 	]+v4,\(a0\),v12
++[ 	]+[0-9a-f]+:[ 	]+bec55207[ 	]+vloxseg6ei256.v[ 	]+v4,\(a0\),v12
++[ 	]+[0-9a-f]+:[ 	]+bcc55207[ 	]+vloxseg6ei256.v[ 	]+v4,\(a0\),v12,v0.t
++[ 	]+[0-9a-f]+:[ 	]+bec55227[ 	]+vsoxseg6ei256.v[ 	]+v4,\(a0\),v12
++[ 	]+[0-9a-f]+:[ 	]+bec55227[ 	]+vsoxseg6ei256.v[ 	]+v4,\(a0\),v12
++[ 	]+[0-9a-f]+:[ 	]+bcc55227[ 	]+vsoxseg6ei256.v[ 	]+v4,\(a0\),v12,v0.t
++[ 	]+[0-9a-f]+:[ 	]+dec55207[ 	]+vloxseg7ei256.v[ 	]+v4,\(a0\),v12
++[ 	]+[0-9a-f]+:[ 	]+dec55207[ 	]+vloxseg7ei256.v[ 	]+v4,\(a0\),v12
++[ 	]+[0-9a-f]+:[ 	]+dcc55207[ 	]+vloxseg7ei256.v[ 	]+v4,\(a0\),v12,v0.t
++[ 	]+[0-9a-f]+:[ 	]+dec55227[ 	]+vsoxseg7ei256.v[ 	]+v4,\(a0\),v12
++[ 	]+[0-9a-f]+:[ 	]+dec55227[ 	]+vsoxseg7ei256.v[ 	]+v4,\(a0\),v12
++[ 	]+[0-9a-f]+:[ 	]+dcc55227[ 	]+vsoxseg7ei256.v[ 	]+v4,\(a0\),v12,v0.t
++[ 	]+[0-9a-f]+:[ 	]+fec55207[ 	]+vloxseg8ei256.v[ 	]+v4,\(a0\),v12
++[ 	]+[0-9a-f]+:[ 	]+fec55207[ 	]+vloxseg8ei256.v[ 	]+v4,\(a0\),v12
++[ 	]+[0-9a-f]+:[ 	]+fcc55207[ 	]+vloxseg8ei256.v[ 	]+v4,\(a0\),v12,v0.t
++[ 	]+[0-9a-f]+:[ 	]+fec55227[ 	]+vsoxseg8ei256.v[ 	]+v4,\(a0\),v12
++[ 	]+[0-9a-f]+:[ 	]+fec55227[ 	]+vsoxseg8ei256.v[ 	]+v4,\(a0\),v12
++[ 	]+[0-9a-f]+:[ 	]+fcc55227[ 	]+vsoxseg8ei256.v[ 	]+v4,\(a0\),v12,v0.t
++[ 	]+[0-9a-f]+:[ 	]+3ec56207[ 	]+vloxseg2ei512.v[ 	]+v4,\(a0\),v12
++[ 	]+[0-9a-f]+:[ 	]+3ec56207[ 	]+vloxseg2ei512.v[ 	]+v4,\(a0\),v12
++[ 	]+[0-9a-f]+:[ 	]+3cc56207[ 	]+vloxseg2ei512.v[ 	]+v4,\(a0\),v12,v0.t
++[ 	]+[0-9a-f]+:[ 	]+3ec56227[ 	]+vsoxseg2ei512.v[ 	]+v4,\(a0\),v12
++[ 	]+[0-9a-f]+:[ 	]+3ec56227[ 	]+vsoxseg2ei512.v[ 	]+v4,\(a0\),v12
++[ 	]+[0-9a-f]+:[ 	]+3cc56227[ 	]+vsoxseg2ei512.v[ 	]+v4,\(a0\),v12,v0.t
++[ 	]+[0-9a-f]+:[ 	]+5ec56207[ 	]+vloxseg3ei512.v[ 	]+v4,\(a0\),v12
++[ 	]+[0-9a-f]+:[ 	]+5ec56207[ 	]+vloxseg3ei512.v[ 	]+v4,\(a0\),v12
++[ 	]+[0-9a-f]+:[ 	]+5cc56207[ 	]+vloxseg3ei512.v[ 	]+v4,\(a0\),v12,v0.t
++[ 	]+[0-9a-f]+:[ 	]+5ec56227[ 	]+vsoxseg3ei512.v[ 	]+v4,\(a0\),v12
++[ 	]+[0-9a-f]+:[ 	]+5ec56227[ 	]+vsoxseg3ei512.v[ 	]+v4,\(a0\),v12
++[ 	]+[0-9a-f]+:[ 	]+5cc56227[ 	]+vsoxseg3ei512.v[ 	]+v4,\(a0\),v12,v0.t
++[ 	]+[0-9a-f]+:[ 	]+7ec56207[ 	]+vloxseg4ei512.v[ 	]+v4,\(a0\),v12
++[ 	]+[0-9a-f]+:[ 	]+7ec56207[ 	]+vloxseg4ei512.v[ 	]+v4,\(a0\),v12
++[ 	]+[0-9a-f]+:[ 	]+7cc56207[ 	]+vloxseg4ei512.v[ 	]+v4,\(a0\),v12,v0.t
++[ 	]+[0-9a-f]+:[ 	]+7ec56227[ 	]+vsoxseg4ei512.v[ 	]+v4,\(a0\),v12
++[ 	]+[0-9a-f]+:[ 	]+7ec56227[ 	]+vsoxseg4ei512.v[ 	]+v4,\(a0\),v12
++[ 	]+[0-9a-f]+:[ 	]+7cc56227[ 	]+vsoxseg4ei512.v[ 	]+v4,\(a0\),v12,v0.t
++[ 	]+[0-9a-f]+:[ 	]+9ec56207[ 	]+vloxseg5ei512.v[ 	]+v4,\(a0\),v12
++[ 	]+[0-9a-f]+:[ 	]+9ec56207[ 	]+vloxseg5ei512.v[ 	]+v4,\(a0\),v12
++[ 	]+[0-9a-f]+:[ 	]+9cc56207[ 	]+vloxseg5ei512.v[ 	]+v4,\(a0\),v12,v0.t
++[ 	]+[0-9a-f]+:[ 	]+9ec56227[ 	]+vsoxseg5ei512.v[ 	]+v4,\(a0\),v12
++[ 	]+[0-9a-f]+:[ 	]+9ec56227[ 	]+vsoxseg5ei512.v[ 	]+v4,\(a0\),v12
++[ 	]+[0-9a-f]+:[ 	]+9cc56227[ 	]+vsoxseg5ei512.v[ 	]+v4,\(a0\),v12,v0.t
++[ 	]+[0-9a-f]+:[ 	]+bec56207[ 	]+vloxseg6ei512.v[ 	]+v4,\(a0\),v12
++[ 	]+[0-9a-f]+:[ 	]+bec56207[ 	]+vloxseg6ei512.v[ 	]+v4,\(a0\),v12
++[ 	]+[0-9a-f]+:[ 	]+bcc56207[ 	]+vloxseg6ei512.v[ 	]+v4,\(a0\),v12,v0.t
++[ 	]+[0-9a-f]+:[ 	]+bec56227[ 	]+vsoxseg6ei512.v[ 	]+v4,\(a0\),v12
++[ 	]+[0-9a-f]+:[ 	]+bec56227[ 	]+vsoxseg6ei512.v[ 	]+v4,\(a0\),v12
++[ 	]+[0-9a-f]+:[ 	]+bcc56227[ 	]+vsoxseg6ei512.v[ 	]+v4,\(a0\),v12,v0.t
++[ 	]+[0-9a-f]+:[ 	]+dec56207[ 	]+vloxseg7ei512.v[ 	]+v4,\(a0\),v12
++[ 	]+[0-9a-f]+:[ 	]+dec56207[ 	]+vloxseg7ei512.v[ 	]+v4,\(a0\),v12
++[ 	]+[0-9a-f]+:[ 	]+dcc56207[ 	]+vloxseg7ei512.v[ 	]+v4,\(a0\),v12,v0.t
++[ 	]+[0-9a-f]+:[ 	]+dec56227[ 	]+vsoxseg7ei512.v[ 	]+v4,\(a0\),v12
++[ 	]+[0-9a-f]+:[ 	]+dec56227[ 	]+vsoxseg7ei512.v[ 	]+v4,\(a0\),v12
++[ 	]+[0-9a-f]+:[ 	]+dcc56227[ 	]+vsoxseg7ei512.v[ 	]+v4,\(a0\),v12,v0.t
++[ 	]+[0-9a-f]+:[ 	]+fec56207[ 	]+vloxseg8ei512.v[ 	]+v4,\(a0\),v12
++[ 	]+[0-9a-f]+:[ 	]+fec56207[ 	]+vloxseg8ei512.v[ 	]+v4,\(a0\),v12
++[ 	]+[0-9a-f]+:[ 	]+fcc56207[ 	]+vloxseg8ei512.v[ 	]+v4,\(a0\),v12,v0.t
++[ 	]+[0-9a-f]+:[ 	]+fec56227[ 	]+vsoxseg8ei512.v[ 	]+v4,\(a0\),v12
++[ 	]+[0-9a-f]+:[ 	]+fec56227[ 	]+vsoxseg8ei512.v[ 	]+v4,\(a0\),v12
++[ 	]+[0-9a-f]+:[ 	]+fcc56227[ 	]+vsoxseg8ei512.v[ 	]+v4,\(a0\),v12,v0.t
++[ 	]+[0-9a-f]+:[ 	]+3ec57207[ 	]+vloxseg2ei1024.v[ 	]+v4,\(a0\),v12
++[ 	]+[0-9a-f]+:[ 	]+3ec57207[ 	]+vloxseg2ei1024.v[ 	]+v4,\(a0\),v12
++[ 	]+[0-9a-f]+:[ 	]+3cc57207[ 	]+vloxseg2ei1024.v[ 	]+v4,\(a0\),v12,v0.t
++[ 	]+[0-9a-f]+:[ 	]+3ec57227[ 	]+vsoxseg2ei1024.v[ 	]+v4,\(a0\),v12
++[ 	]+[0-9a-f]+:[ 	]+3ec57227[ 	]+vsoxseg2ei1024.v[ 	]+v4,\(a0\),v12
++[ 	]+[0-9a-f]+:[ 	]+3cc57227[ 	]+vsoxseg2ei1024.v[ 	]+v4,\(a0\),v12,v0.t
++[ 	]+[0-9a-f]+:[ 	]+5ec57207[ 	]+vloxseg3ei1024.v[ 	]+v4,\(a0\),v12
++[ 	]+[0-9a-f]+:[ 	]+5ec57207[ 	]+vloxseg3ei1024.v[ 	]+v4,\(a0\),v12
++[ 	]+[0-9a-f]+:[ 	]+5cc57207[ 	]+vloxseg3ei1024.v[ 	]+v4,\(a0\),v12,v0.t
++[ 	]+[0-9a-f]+:[ 	]+5ec57227[ 	]+vsoxseg3ei1024.v[ 	]+v4,\(a0\),v12
++[ 	]+[0-9a-f]+:[ 	]+5ec57227[ 	]+vsoxseg3ei1024.v[ 	]+v4,\(a0\),v12
++[ 	]+[0-9a-f]+:[ 	]+5cc57227[ 	]+vsoxseg3ei1024.v[ 	]+v4,\(a0\),v12,v0.t
++[ 	]+[0-9a-f]+:[ 	]+7ec57207[ 	]+vloxseg4ei1024.v[ 	]+v4,\(a0\),v12
++[ 	]+[0-9a-f]+:[ 	]+7ec57207[ 	]+vloxseg4ei1024.v[ 	]+v4,\(a0\),v12
++[ 	]+[0-9a-f]+:[ 	]+7cc57207[ 	]+vloxseg4ei1024.v[ 	]+v4,\(a0\),v12,v0.t
++[ 	]+[0-9a-f]+:[ 	]+7ec57227[ 	]+vsoxseg4ei1024.v[ 	]+v4,\(a0\),v12
++[ 	]+[0-9a-f]+:[ 	]+7ec57227[ 	]+vsoxseg4ei1024.v[ 	]+v4,\(a0\),v12
++[ 	]+[0-9a-f]+:[ 	]+7cc57227[ 	]+vsoxseg4ei1024.v[ 	]+v4,\(a0\),v12,v0.t
++[ 	]+[0-9a-f]+:[ 	]+9ec57207[ 	]+vloxseg5ei1024.v[ 	]+v4,\(a0\),v12
++[ 	]+[0-9a-f]+:[ 	]+9ec57207[ 	]+vloxseg5ei1024.v[ 	]+v4,\(a0\),v12
++[ 	]+[0-9a-f]+:[ 	]+9cc57207[ 	]+vloxseg5ei1024.v[ 	]+v4,\(a0\),v12,v0.t
++[ 	]+[0-9a-f]+:[ 	]+9ec57227[ 	]+vsoxseg5ei1024.v[ 	]+v4,\(a0\),v12
++[ 	]+[0-9a-f]+:[ 	]+9ec57227[ 	]+vsoxseg5ei1024.v[ 	]+v4,\(a0\),v12
++[ 	]+[0-9a-f]+:[ 	]+9cc57227[ 	]+vsoxseg5ei1024.v[ 	]+v4,\(a0\),v12,v0.t
++[ 	]+[0-9a-f]+:[ 	]+bec57207[ 	]+vloxseg6ei1024.v[ 	]+v4,\(a0\),v12
++[ 	]+[0-9a-f]+:[ 	]+bec57207[ 	]+vloxseg6ei1024.v[ 	]+v4,\(a0\),v12
++[ 	]+[0-9a-f]+:[ 	]+bcc57207[ 	]+vloxseg6ei1024.v[ 	]+v4,\(a0\),v12,v0.t
++[ 	]+[0-9a-f]+:[ 	]+bec57227[ 	]+vsoxseg6ei1024.v[ 	]+v4,\(a0\),v12
++[ 	]+[0-9a-f]+:[ 	]+bec57227[ 	]+vsoxseg6ei1024.v[ 	]+v4,\(a0\),v12
++[ 	]+[0-9a-f]+:[ 	]+bcc57227[ 	]+vsoxseg6ei1024.v[ 	]+v4,\(a0\),v12,v0.t
++[ 	]+[0-9a-f]+:[ 	]+dec57207[ 	]+vloxseg7ei1024.v[ 	]+v4,\(a0\),v12
++[ 	]+[0-9a-f]+:[ 	]+dec57207[ 	]+vloxseg7ei1024.v[ 	]+v4,\(a0\),v12
++[ 	]+[0-9a-f]+:[ 	]+dcc57207[ 	]+vloxseg7ei1024.v[ 	]+v4,\(a0\),v12,v0.t
++[ 	]+[0-9a-f]+:[ 	]+dec57227[ 	]+vsoxseg7ei1024.v[ 	]+v4,\(a0\),v12
++[ 	]+[0-9a-f]+:[ 	]+dec57227[ 	]+vsoxseg7ei1024.v[ 	]+v4,\(a0\),v12
++[ 	]+[0-9a-f]+:[ 	]+dcc57227[ 	]+vsoxseg7ei1024.v[ 	]+v4,\(a0\),v12,v0.t
++[ 	]+[0-9a-f]+:[ 	]+fec57207[ 	]+vloxseg8ei1024.v[ 	]+v4,\(a0\),v12
++[ 	]+[0-9a-f]+:[ 	]+fec57207[ 	]+vloxseg8ei1024.v[ 	]+v4,\(a0\),v12
++[ 	]+[0-9a-f]+:[ 	]+fcc57207[ 	]+vloxseg8ei1024.v[ 	]+v4,\(a0\),v12,v0.t
++[ 	]+[0-9a-f]+:[ 	]+fec57227[ 	]+vsoxseg8ei1024.v[ 	]+v4,\(a0\),v12
++[ 	]+[0-9a-f]+:[ 	]+fec57227[ 	]+vsoxseg8ei1024.v[ 	]+v4,\(a0\),v12
++[ 	]+[0-9a-f]+:[ 	]+fcc57227[ 	]+vsoxseg8ei1024.v[ 	]+v4,\(a0\),v12,v0.t
++[ 	]+[0-9a-f]+:[ 	]+26c50207[ 	]+vluxseg2ei8.v[ 	]+v4,\(a0\),v12
++[ 	]+[0-9a-f]+:[ 	]+26c50207[ 	]+vluxseg2ei8.v[ 	]+v4,\(a0\),v12
++[ 	]+[0-9a-f]+:[ 	]+24c50207[ 	]+vluxseg2ei8.v[ 	]+v4,\(a0\),v12,v0.t
++[ 	]+[0-9a-f]+:[ 	]+26c50227[ 	]+vsuxseg2ei8.v[ 	]+v4,\(a0\),v12
++[ 	]+[0-9a-f]+:[ 	]+26c50227[ 	]+vsuxseg2ei8.v[ 	]+v4,\(a0\),v12
++[ 	]+[0-9a-f]+:[ 	]+24c50227[ 	]+vsuxseg2ei8.v[ 	]+v4,\(a0\),v12,v0.t
++[ 	]+[0-9a-f]+:[ 	]+46c50207[ 	]+vluxseg3ei8.v[ 	]+v4,\(a0\),v12
++[ 	]+[0-9a-f]+:[ 	]+46c50207[ 	]+vluxseg3ei8.v[ 	]+v4,\(a0\),v12
++[ 	]+[0-9a-f]+:[ 	]+44c50207[ 	]+vluxseg3ei8.v[ 	]+v4,\(a0\),v12,v0.t
++[ 	]+[0-9a-f]+:[ 	]+46c50227[ 	]+vsuxseg3ei8.v[ 	]+v4,\(a0\),v12
++[ 	]+[0-9a-f]+:[ 	]+46c50227[ 	]+vsuxseg3ei8.v[ 	]+v4,\(a0\),v12
++[ 	]+[0-9a-f]+:[ 	]+44c50227[ 	]+vsuxseg3ei8.v[ 	]+v4,\(a0\),v12,v0.t
++[ 	]+[0-9a-f]+:[ 	]+66c50207[ 	]+vluxseg4ei8.v[ 	]+v4,\(a0\),v12
++[ 	]+[0-9a-f]+:[ 	]+66c50207[ 	]+vluxseg4ei8.v[ 	]+v4,\(a0\),v12
++[ 	]+[0-9a-f]+:[ 	]+64c50207[ 	]+vluxseg4ei8.v[ 	]+v4,\(a0\),v12,v0.t
++[ 	]+[0-9a-f]+:[ 	]+66c50227[ 	]+vsuxseg4ei8.v[ 	]+v4,\(a0\),v12
++[ 	]+[0-9a-f]+:[ 	]+66c50227[ 	]+vsuxseg4ei8.v[ 	]+v4,\(a0\),v12
++[ 	]+[0-9a-f]+:[ 	]+64c50227[ 	]+vsuxseg4ei8.v[ 	]+v4,\(a0\),v12,v0.t
++[ 	]+[0-9a-f]+:[ 	]+86c50207[ 	]+vluxseg5ei8.v[ 	]+v4,\(a0\),v12
++[ 	]+[0-9a-f]+:[ 	]+86c50207[ 	]+vluxseg5ei8.v[ 	]+v4,\(a0\),v12
++[ 	]+[0-9a-f]+:[ 	]+84c50207[ 	]+vluxseg5ei8.v[ 	]+v4,\(a0\),v12,v0.t
++[ 	]+[0-9a-f]+:[ 	]+86c50227[ 	]+vsuxseg5ei8.v[ 	]+v4,\(a0\),v12
++[ 	]+[0-9a-f]+:[ 	]+86c50227[ 	]+vsuxseg5ei8.v[ 	]+v4,\(a0\),v12
++[ 	]+[0-9a-f]+:[ 	]+84c50227[ 	]+vsuxseg5ei8.v[ 	]+v4,\(a0\),v12,v0.t
++[ 	]+[0-9a-f]+:[ 	]+a6c50207[ 	]+vluxseg6ei8.v[ 	]+v4,\(a0\),v12
++[ 	]+[0-9a-f]+:[ 	]+a6c50207[ 	]+vluxseg6ei8.v[ 	]+v4,\(a0\),v12
++[ 	]+[0-9a-f]+:[ 	]+a4c50207[ 	]+vluxseg6ei8.v[ 	]+v4,\(a0\),v12,v0.t
++[ 	]+[0-9a-f]+:[ 	]+a6c50227[ 	]+vsuxseg6ei8.v[ 	]+v4,\(a0\),v12
++[ 	]+[0-9a-f]+:[ 	]+a6c50227[ 	]+vsuxseg6ei8.v[ 	]+v4,\(a0\),v12
++[ 	]+[0-9a-f]+:[ 	]+a4c50227[ 	]+vsuxseg6ei8.v[ 	]+v4,\(a0\),v12,v0.t
++[ 	]+[0-9a-f]+:[ 	]+c6c50207[ 	]+vluxseg7ei8.v[ 	]+v4,\(a0\),v12
++[ 	]+[0-9a-f]+:[ 	]+c6c50207[ 	]+vluxseg7ei8.v[ 	]+v4,\(a0\),v12
++[ 	]+[0-9a-f]+:[ 	]+c4c50207[ 	]+vluxseg7ei8.v[ 	]+v4,\(a0\),v12,v0.t
++[ 	]+[0-9a-f]+:[ 	]+c6c50227[ 	]+vsuxseg7ei8.v[ 	]+v4,\(a0\),v12
++[ 	]+[0-9a-f]+:[ 	]+c6c50227[ 	]+vsuxseg7ei8.v[ 	]+v4,\(a0\),v12
++[ 	]+[0-9a-f]+:[ 	]+c4c50227[ 	]+vsuxseg7ei8.v[ 	]+v4,\(a0\),v12,v0.t
++[ 	]+[0-9a-f]+:[ 	]+e6c50207[ 	]+vluxseg8ei8.v[ 	]+v4,\(a0\),v12
++[ 	]+[0-9a-f]+:[ 	]+e6c50207[ 	]+vluxseg8ei8.v[ 	]+v4,\(a0\),v12
++[ 	]+[0-9a-f]+:[ 	]+e4c50207[ 	]+vluxseg8ei8.v[ 	]+v4,\(a0\),v12,v0.t
++[ 	]+[0-9a-f]+:[ 	]+e6c50227[ 	]+vsuxseg8ei8.v[ 	]+v4,\(a0\),v12
++[ 	]+[0-9a-f]+:[ 	]+e6c50227[ 	]+vsuxseg8ei8.v[ 	]+v4,\(a0\),v12
++[ 	]+[0-9a-f]+:[ 	]+e4c50227[ 	]+vsuxseg8ei8.v[ 	]+v4,\(a0\),v12,v0.t
++[ 	]+[0-9a-f]+:[ 	]+26c55207[ 	]+vluxseg2ei16.v[ 	]+v4,\(a0\),v12
++[ 	]+[0-9a-f]+:[ 	]+26c55207[ 	]+vluxseg2ei16.v[ 	]+v4,\(a0\),v12
++[ 	]+[0-9a-f]+:[ 	]+24c55207[ 	]+vluxseg2ei16.v[ 	]+v4,\(a0\),v12,v0.t
++[ 	]+[0-9a-f]+:[ 	]+26c55227[ 	]+vsuxseg2ei16.v[ 	]+v4,\(a0\),v12
++[ 	]+[0-9a-f]+:[ 	]+26c55227[ 	]+vsuxseg2ei16.v[ 	]+v4,\(a0\),v12
++[ 	]+[0-9a-f]+:[ 	]+24c55227[ 	]+vsuxseg2ei16.v[ 	]+v4,\(a0\),v12,v0.t
++[ 	]+[0-9a-f]+:[ 	]+46c55207[ 	]+vluxseg3ei16.v[ 	]+v4,\(a0\),v12
++[ 	]+[0-9a-f]+:[ 	]+46c55207[ 	]+vluxseg3ei16.v[ 	]+v4,\(a0\),v12
++[ 	]+[0-9a-f]+:[ 	]+44c55207[ 	]+vluxseg3ei16.v[ 	]+v4,\(a0\),v12,v0.t
++[ 	]+[0-9a-f]+:[ 	]+46c55227[ 	]+vsuxseg3ei16.v[ 	]+v4,\(a0\),v12
++[ 	]+[0-9a-f]+:[ 	]+46c55227[ 	]+vsuxseg3ei16.v[ 	]+v4,\(a0\),v12
++[ 	]+[0-9a-f]+:[ 	]+44c55227[ 	]+vsuxseg3ei16.v[ 	]+v4,\(a0\),v12,v0.t
++[ 	]+[0-9a-f]+:[ 	]+66c55207[ 	]+vluxseg4ei16.v[ 	]+v4,\(a0\),v12
++[ 	]+[0-9a-f]+:[ 	]+66c55207[ 	]+vluxseg4ei16.v[ 	]+v4,\(a0\),v12
++[ 	]+[0-9a-f]+:[ 	]+64c55207[ 	]+vluxseg4ei16.v[ 	]+v4,\(a0\),v12,v0.t
++[ 	]+[0-9a-f]+:[ 	]+66c55227[ 	]+vsuxseg4ei16.v[ 	]+v4,\(a0\),v12
++[ 	]+[0-9a-f]+:[ 	]+66c55227[ 	]+vsuxseg4ei16.v[ 	]+v4,\(a0\),v12
++[ 	]+[0-9a-f]+:[ 	]+64c55227[ 	]+vsuxseg4ei16.v[ 	]+v4,\(a0\),v12,v0.t
++[ 	]+[0-9a-f]+:[ 	]+86c55207[ 	]+vluxseg5ei16.v[ 	]+v4,\(a0\),v12
++[ 	]+[0-9a-f]+:[ 	]+86c55207[ 	]+vluxseg5ei16.v[ 	]+v4,\(a0\),v12
++[ 	]+[0-9a-f]+:[ 	]+84c55207[ 	]+vluxseg5ei16.v[ 	]+v4,\(a0\),v12,v0.t
++[ 	]+[0-9a-f]+:[ 	]+86c55227[ 	]+vsuxseg5ei16.v[ 	]+v4,\(a0\),v12
++[ 	]+[0-9a-f]+:[ 	]+86c55227[ 	]+vsuxseg5ei16.v[ 	]+v4,\(a0\),v12
++[ 	]+[0-9a-f]+:[ 	]+84c55227[ 	]+vsuxseg5ei16.v[ 	]+v4,\(a0\),v12,v0.t
++[ 	]+[0-9a-f]+:[ 	]+a6c55207[ 	]+vluxseg6ei16.v[ 	]+v4,\(a0\),v12
++[ 	]+[0-9a-f]+:[ 	]+a6c55207[ 	]+vluxseg6ei16.v[ 	]+v4,\(a0\),v12
++[ 	]+[0-9a-f]+:[ 	]+a4c55207[ 	]+vluxseg6ei16.v[ 	]+v4,\(a0\),v12,v0.t
++[ 	]+[0-9a-f]+:[ 	]+a6c55227[ 	]+vsuxseg6ei16.v[ 	]+v4,\(a0\),v12
++[ 	]+[0-9a-f]+:[ 	]+a6c55227[ 	]+vsuxseg6ei16.v[ 	]+v4,\(a0\),v12
++[ 	]+[0-9a-f]+:[ 	]+a4c55227[ 	]+vsuxseg6ei16.v[ 	]+v4,\(a0\),v12,v0.t
++[ 	]+[0-9a-f]+:[ 	]+c6c55207[ 	]+vluxseg7ei16.v[ 	]+v4,\(a0\),v12
++[ 	]+[0-9a-f]+:[ 	]+c6c55207[ 	]+vluxseg7ei16.v[ 	]+v4,\(a0\),v12
++[ 	]+[0-9a-f]+:[ 	]+c4c55207[ 	]+vluxseg7ei16.v[ 	]+v4,\(a0\),v12,v0.t
++[ 	]+[0-9a-f]+:[ 	]+c6c55227[ 	]+vsuxseg7ei16.v[ 	]+v4,\(a0\),v12
++[ 	]+[0-9a-f]+:[ 	]+c6c55227[ 	]+vsuxseg7ei16.v[ 	]+v4,\(a0\),v12
++[ 	]+[0-9a-f]+:[ 	]+c4c55227[ 	]+vsuxseg7ei16.v[ 	]+v4,\(a0\),v12,v0.t
++[ 	]+[0-9a-f]+:[ 	]+e6c55207[ 	]+vluxseg8ei16.v[ 	]+v4,\(a0\),v12
++[ 	]+[0-9a-f]+:[ 	]+e6c55207[ 	]+vluxseg8ei16.v[ 	]+v4,\(a0\),v12
++[ 	]+[0-9a-f]+:[ 	]+e4c55207[ 	]+vluxseg8ei16.v[ 	]+v4,\(a0\),v12,v0.t
++[ 	]+[0-9a-f]+:[ 	]+e6c55227[ 	]+vsuxseg8ei16.v[ 	]+v4,\(a0\),v12
++[ 	]+[0-9a-f]+:[ 	]+e6c55227[ 	]+vsuxseg8ei16.v[ 	]+v4,\(a0\),v12
++[ 	]+[0-9a-f]+:[ 	]+e4c55227[ 	]+vsuxseg8ei16.v[ 	]+v4,\(a0\),v12,v0.t
++[ 	]+[0-9a-f]+:[ 	]+26c56207[ 	]+vluxseg2ei32.v[ 	]+v4,\(a0\),v12
++[ 	]+[0-9a-f]+:[ 	]+26c56207[ 	]+vluxseg2ei32.v[ 	]+v4,\(a0\),v12
++[ 	]+[0-9a-f]+:[ 	]+24c56207[ 	]+vluxseg2ei32.v[ 	]+v4,\(a0\),v12,v0.t
++[ 	]+[0-9a-f]+:[ 	]+26c56227[ 	]+vsuxseg2ei32.v[ 	]+v4,\(a0\),v12
++[ 	]+[0-9a-f]+:[ 	]+26c56227[ 	]+vsuxseg2ei32.v[ 	]+v4,\(a0\),v12
++[ 	]+[0-9a-f]+:[ 	]+24c56227[ 	]+vsuxseg2ei32.v[ 	]+v4,\(a0\),v12,v0.t
++[ 	]+[0-9a-f]+:[ 	]+46c56207[ 	]+vluxseg3ei32.v[ 	]+v4,\(a0\),v12
++[ 	]+[0-9a-f]+:[ 	]+46c56207[ 	]+vluxseg3ei32.v[ 	]+v4,\(a0\),v12
++[ 	]+[0-9a-f]+:[ 	]+44c56207[ 	]+vluxseg3ei32.v[ 	]+v4,\(a0\),v12,v0.t
++[ 	]+[0-9a-f]+:[ 	]+46c56227[ 	]+vsuxseg3ei32.v[ 	]+v4,\(a0\),v12
++[ 	]+[0-9a-f]+:[ 	]+46c56227[ 	]+vsuxseg3ei32.v[ 	]+v4,\(a0\),v12
++[ 	]+[0-9a-f]+:[ 	]+44c56227[ 	]+vsuxseg3ei32.v[ 	]+v4,\(a0\),v12,v0.t
++[ 	]+[0-9a-f]+:[ 	]+66c56207[ 	]+vluxseg4ei32.v[ 	]+v4,\(a0\),v12
++[ 	]+[0-9a-f]+:[ 	]+66c56207[ 	]+vluxseg4ei32.v[ 	]+v4,\(a0\),v12
++[ 	]+[0-9a-f]+:[ 	]+64c56207[ 	]+vluxseg4ei32.v[ 	]+v4,\(a0\),v12,v0.t
++[ 	]+[0-9a-f]+:[ 	]+66c56227[ 	]+vsuxseg4ei32.v[ 	]+v4,\(a0\),v12
++[ 	]+[0-9a-f]+:[ 	]+66c56227[ 	]+vsuxseg4ei32.v[ 	]+v4,\(a0\),v12
++[ 	]+[0-9a-f]+:[ 	]+64c56227[ 	]+vsuxseg4ei32.v[ 	]+v4,\(a0\),v12,v0.t
++[ 	]+[0-9a-f]+:[ 	]+86c56207[ 	]+vluxseg5ei32.v[ 	]+v4,\(a0\),v12
++[ 	]+[0-9a-f]+:[ 	]+86c56207[ 	]+vluxseg5ei32.v[ 	]+v4,\(a0\),v12
++[ 	]+[0-9a-f]+:[ 	]+84c56207[ 	]+vluxseg5ei32.v[ 	]+v4,\(a0\),v12,v0.t
++[ 	]+[0-9a-f]+:[ 	]+86c56227[ 	]+vsuxseg5ei32.v[ 	]+v4,\(a0\),v12
++[ 	]+[0-9a-f]+:[ 	]+86c56227[ 	]+vsuxseg5ei32.v[ 	]+v4,\(a0\),v12
++[ 	]+[0-9a-f]+:[ 	]+84c56227[ 	]+vsuxseg5ei32.v[ 	]+v4,\(a0\),v12,v0.t
++[ 	]+[0-9a-f]+:[ 	]+a6c56207[ 	]+vluxseg6ei32.v[ 	]+v4,\(a0\),v12
++[ 	]+[0-9a-f]+:[ 	]+a6c56207[ 	]+vluxseg6ei32.v[ 	]+v4,\(a0\),v12
++[ 	]+[0-9a-f]+:[ 	]+a4c56207[ 	]+vluxseg6ei32.v[ 	]+v4,\(a0\),v12,v0.t
++[ 	]+[0-9a-f]+:[ 	]+a6c56227[ 	]+vsuxseg6ei32.v[ 	]+v4,\(a0\),v12
++[ 	]+[0-9a-f]+:[ 	]+a6c56227[ 	]+vsuxseg6ei32.v[ 	]+v4,\(a0\),v12
++[ 	]+[0-9a-f]+:[ 	]+a4c56227[ 	]+vsuxseg6ei32.v[ 	]+v4,\(a0\),v12,v0.t
++[ 	]+[0-9a-f]+:[ 	]+c6c56207[ 	]+vluxseg7ei32.v[ 	]+v4,\(a0\),v12
++[ 	]+[0-9a-f]+:[ 	]+c6c56207[ 	]+vluxseg7ei32.v[ 	]+v4,\(a0\),v12
++[ 	]+[0-9a-f]+:[ 	]+c4c56207[ 	]+vluxseg7ei32.v[ 	]+v4,\(a0\),v12,v0.t
++[ 	]+[0-9a-f]+:[ 	]+c6c56227[ 	]+vsuxseg7ei32.v[ 	]+v4,\(a0\),v12
++[ 	]+[0-9a-f]+:[ 	]+c6c56227[ 	]+vsuxseg7ei32.v[ 	]+v4,\(a0\),v12
++[ 	]+[0-9a-f]+:[ 	]+c4c56227[ 	]+vsuxseg7ei32.v[ 	]+v4,\(a0\),v12,v0.t
++[ 	]+[0-9a-f]+:[ 	]+e6c56207[ 	]+vluxseg8ei32.v[ 	]+v4,\(a0\),v12
++[ 	]+[0-9a-f]+:[ 	]+e6c56207[ 	]+vluxseg8ei32.v[ 	]+v4,\(a0\),v12
++[ 	]+[0-9a-f]+:[ 	]+e4c56207[ 	]+vluxseg8ei32.v[ 	]+v4,\(a0\),v12,v0.t
++[ 	]+[0-9a-f]+:[ 	]+e6c56227[ 	]+vsuxseg8ei32.v[ 	]+v4,\(a0\),v12
++[ 	]+[0-9a-f]+:[ 	]+e6c56227[ 	]+vsuxseg8ei32.v[ 	]+v4,\(a0\),v12
++[ 	]+[0-9a-f]+:[ 	]+e4c56227[ 	]+vsuxseg8ei32.v[ 	]+v4,\(a0\),v12,v0.t
++[ 	]+[0-9a-f]+:[ 	]+26c57207[ 	]+vluxseg2ei64.v[ 	]+v4,\(a0\),v12
++[ 	]+[0-9a-f]+:[ 	]+26c57207[ 	]+vluxseg2ei64.v[ 	]+v4,\(a0\),v12
++[ 	]+[0-9a-f]+:[ 	]+24c57207[ 	]+vluxseg2ei64.v[ 	]+v4,\(a0\),v12,v0.t
++[ 	]+[0-9a-f]+:[ 	]+26c57227[ 	]+vsuxseg2ei64.v[ 	]+v4,\(a0\),v12
++[ 	]+[0-9a-f]+:[ 	]+26c57227[ 	]+vsuxseg2ei64.v[ 	]+v4,\(a0\),v12
++[ 	]+[0-9a-f]+:[ 	]+24c57227[ 	]+vsuxseg2ei64.v[ 	]+v4,\(a0\),v12,v0.t
++[ 	]+[0-9a-f]+:[ 	]+46c57207[ 	]+vluxseg3ei64.v[ 	]+v4,\(a0\),v12
++[ 	]+[0-9a-f]+:[ 	]+46c57207[ 	]+vluxseg3ei64.v[ 	]+v4,\(a0\),v12
++[ 	]+[0-9a-f]+:[ 	]+44c57207[ 	]+vluxseg3ei64.v[ 	]+v4,\(a0\),v12,v0.t
++[ 	]+[0-9a-f]+:[ 	]+46c57227[ 	]+vsuxseg3ei64.v[ 	]+v4,\(a0\),v12
++[ 	]+[0-9a-f]+:[ 	]+46c57227[ 	]+vsuxseg3ei64.v[ 	]+v4,\(a0\),v12
++[ 	]+[0-9a-f]+:[ 	]+44c57227[ 	]+vsuxseg3ei64.v[ 	]+v4,\(a0\),v12,v0.t
++[ 	]+[0-9a-f]+:[ 	]+66c57207[ 	]+vluxseg4ei64.v[ 	]+v4,\(a0\),v12
++[ 	]+[0-9a-f]+:[ 	]+66c57207[ 	]+vluxseg4ei64.v[ 	]+v4,\(a0\),v12
++[ 	]+[0-9a-f]+:[ 	]+64c57207[ 	]+vluxseg4ei64.v[ 	]+v4,\(a0\),v12,v0.t
++[ 	]+[0-9a-f]+:[ 	]+66c57227[ 	]+vsuxseg4ei64.v[ 	]+v4,\(a0\),v12
++[ 	]+[0-9a-f]+:[ 	]+66c57227[ 	]+vsuxseg4ei64.v[ 	]+v4,\(a0\),v12
++[ 	]+[0-9a-f]+:[ 	]+64c57227[ 	]+vsuxseg4ei64.v[ 	]+v4,\(a0\),v12,v0.t
++[ 	]+[0-9a-f]+:[ 	]+86c57207[ 	]+vluxseg5ei64.v[ 	]+v4,\(a0\),v12
++[ 	]+[0-9a-f]+:[ 	]+86c57207[ 	]+vluxseg5ei64.v[ 	]+v4,\(a0\),v12
++[ 	]+[0-9a-f]+:[ 	]+84c57207[ 	]+vluxseg5ei64.v[ 	]+v4,\(a0\),v12,v0.t
++[ 	]+[0-9a-f]+:[ 	]+86c57227[ 	]+vsuxseg5ei64.v[ 	]+v4,\(a0\),v12
++[ 	]+[0-9a-f]+:[ 	]+86c57227[ 	]+vsuxseg5ei64.v[ 	]+v4,\(a0\),v12
++[ 	]+[0-9a-f]+:[ 	]+84c57227[ 	]+vsuxseg5ei64.v[ 	]+v4,\(a0\),v12,v0.t
++[ 	]+[0-9a-f]+:[ 	]+a6c57207[ 	]+vluxseg6ei64.v[ 	]+v4,\(a0\),v12
++[ 	]+[0-9a-f]+:[ 	]+a6c57207[ 	]+vluxseg6ei64.v[ 	]+v4,\(a0\),v12
++[ 	]+[0-9a-f]+:[ 	]+a4c57207[ 	]+vluxseg6ei64.v[ 	]+v4,\(a0\),v12,v0.t
++[ 	]+[0-9a-f]+:[ 	]+a6c57227[ 	]+vsuxseg6ei64.v[ 	]+v4,\(a0\),v12
++[ 	]+[0-9a-f]+:[ 	]+a6c57227[ 	]+vsuxseg6ei64.v[ 	]+v4,\(a0\),v12
++[ 	]+[0-9a-f]+:[ 	]+a4c57227[ 	]+vsuxseg6ei64.v[ 	]+v4,\(a0\),v12,v0.t
++[ 	]+[0-9a-f]+:[ 	]+c6c57207[ 	]+vluxseg7ei64.v[ 	]+v4,\(a0\),v12
++[ 	]+[0-9a-f]+:[ 	]+c6c57207[ 	]+vluxseg7ei64.v[ 	]+v4,\(a0\),v12
++[ 	]+[0-9a-f]+:[ 	]+c4c57207[ 	]+vluxseg7ei64.v[ 	]+v4,\(a0\),v12,v0.t
++[ 	]+[0-9a-f]+:[ 	]+c6c57227[ 	]+vsuxseg7ei64.v[ 	]+v4,\(a0\),v12
++[ 	]+[0-9a-f]+:[ 	]+c6c57227[ 	]+vsuxseg7ei64.v[ 	]+v4,\(a0\),v12
++[ 	]+[0-9a-f]+:[ 	]+c4c57227[ 	]+vsuxseg7ei64.v[ 	]+v4,\(a0\),v12,v0.t
++[ 	]+[0-9a-f]+:[ 	]+e6c57207[ 	]+vluxseg8ei64.v[ 	]+v4,\(a0\),v12
++[ 	]+[0-9a-f]+:[ 	]+e6c57207[ 	]+vluxseg8ei64.v[ 	]+v4,\(a0\),v12
++[ 	]+[0-9a-f]+:[ 	]+e4c57207[ 	]+vluxseg8ei64.v[ 	]+v4,\(a0\),v12,v0.t
++[ 	]+[0-9a-f]+:[ 	]+e6c57227[ 	]+vsuxseg8ei64.v[ 	]+v4,\(a0\),v12
++[ 	]+[0-9a-f]+:[ 	]+e6c57227[ 	]+vsuxseg8ei64.v[ 	]+v4,\(a0\),v12
++[ 	]+[0-9a-f]+:[ 	]+e4c57227[ 	]+vsuxseg8ei64.v[ 	]+v4,\(a0\),v12,v0.t
++[ 	]+[0-9a-f]+:[ 	]+36c50207[ 	]+vluxseg2ei128.v[ 	]+v4,\(a0\),v12
++[ 	]+[0-9a-f]+:[ 	]+36c50207[ 	]+vluxseg2ei128.v[ 	]+v4,\(a0\),v12
++[ 	]+[0-9a-f]+:[ 	]+34c50207[ 	]+vluxseg2ei128.v[ 	]+v4,\(a0\),v12,v0.t
++[ 	]+[0-9a-f]+:[ 	]+36c50227[ 	]+vsuxseg2ei128.v[ 	]+v4,\(a0\),v12
++[ 	]+[0-9a-f]+:[ 	]+36c50227[ 	]+vsuxseg2ei128.v[ 	]+v4,\(a0\),v12
++[ 	]+[0-9a-f]+:[ 	]+34c50227[ 	]+vsuxseg2ei128.v[ 	]+v4,\(a0\),v12,v0.t
++[ 	]+[0-9a-f]+:[ 	]+56c50207[ 	]+vluxseg3ei128.v[ 	]+v4,\(a0\),v12
++[ 	]+[0-9a-f]+:[ 	]+56c50207[ 	]+vluxseg3ei128.v[ 	]+v4,\(a0\),v12
++[ 	]+[0-9a-f]+:[ 	]+54c50207[ 	]+vluxseg3ei128.v[ 	]+v4,\(a0\),v12,v0.t
++[ 	]+[0-9a-f]+:[ 	]+56c50227[ 	]+vsuxseg3ei128.v[ 	]+v4,\(a0\),v12
++[ 	]+[0-9a-f]+:[ 	]+56c50227[ 	]+vsuxseg3ei128.v[ 	]+v4,\(a0\),v12
++[ 	]+[0-9a-f]+:[ 	]+54c50227[ 	]+vsuxseg3ei128.v[ 	]+v4,\(a0\),v12,v0.t
++[ 	]+[0-9a-f]+:[ 	]+76c50207[ 	]+vluxseg4ei128.v[ 	]+v4,\(a0\),v12
++[ 	]+[0-9a-f]+:[ 	]+76c50207[ 	]+vluxseg4ei128.v[ 	]+v4,\(a0\),v12
++[ 	]+[0-9a-f]+:[ 	]+74c50207[ 	]+vluxseg4ei128.v[ 	]+v4,\(a0\),v12,v0.t
++[ 	]+[0-9a-f]+:[ 	]+76c50227[ 	]+vsuxseg4ei128.v[ 	]+v4,\(a0\),v12
++[ 	]+[0-9a-f]+:[ 	]+76c50227[ 	]+vsuxseg4ei128.v[ 	]+v4,\(a0\),v12
++[ 	]+[0-9a-f]+:[ 	]+74c50227[ 	]+vsuxseg4ei128.v[ 	]+v4,\(a0\),v12,v0.t
++[ 	]+[0-9a-f]+:[ 	]+96c50207[ 	]+vluxseg5ei128.v[ 	]+v4,\(a0\),v12
++[ 	]+[0-9a-f]+:[ 	]+96c50207[ 	]+vluxseg5ei128.v[ 	]+v4,\(a0\),v12
++[ 	]+[0-9a-f]+:[ 	]+94c50207[ 	]+vluxseg5ei128.v[ 	]+v4,\(a0\),v12,v0.t
++[ 	]+[0-9a-f]+:[ 	]+96c50227[ 	]+vsuxseg5ei128.v[ 	]+v4,\(a0\),v12
++[ 	]+[0-9a-f]+:[ 	]+96c50227[ 	]+vsuxseg5ei128.v[ 	]+v4,\(a0\),v12
++[ 	]+[0-9a-f]+:[ 	]+94c50227[ 	]+vsuxseg5ei128.v[ 	]+v4,\(a0\),v12,v0.t
++[ 	]+[0-9a-f]+:[ 	]+b6c50207[ 	]+vluxseg6ei128.v[ 	]+v4,\(a0\),v12
++[ 	]+[0-9a-f]+:[ 	]+b6c50207[ 	]+vluxseg6ei128.v[ 	]+v4,\(a0\),v12
++[ 	]+[0-9a-f]+:[ 	]+b4c50207[ 	]+vluxseg6ei128.v[ 	]+v4,\(a0\),v12,v0.t
++[ 	]+[0-9a-f]+:[ 	]+b6c50227[ 	]+vsuxseg6ei128.v[ 	]+v4,\(a0\),v12
++[ 	]+[0-9a-f]+:[ 	]+b6c50227[ 	]+vsuxseg6ei128.v[ 	]+v4,\(a0\),v12
++[ 	]+[0-9a-f]+:[ 	]+b4c50227[ 	]+vsuxseg6ei128.v[ 	]+v4,\(a0\),v12,v0.t
++[ 	]+[0-9a-f]+:[ 	]+d6c50207[ 	]+vluxseg7ei128.v[ 	]+v4,\(a0\),v12
++[ 	]+[0-9a-f]+:[ 	]+d6c50207[ 	]+vluxseg7ei128.v[ 	]+v4,\(a0\),v12
++[ 	]+[0-9a-f]+:[ 	]+d4c50207[ 	]+vluxseg7ei128.v[ 	]+v4,\(a0\),v12,v0.t
++[ 	]+[0-9a-f]+:[ 	]+d6c50227[ 	]+vsuxseg7ei128.v[ 	]+v4,\(a0\),v12
++[ 	]+[0-9a-f]+:[ 	]+d6c50227[ 	]+vsuxseg7ei128.v[ 	]+v4,\(a0\),v12
++[ 	]+[0-9a-f]+:[ 	]+d4c50227[ 	]+vsuxseg7ei128.v[ 	]+v4,\(a0\),v12,v0.t
++[ 	]+[0-9a-f]+:[ 	]+f6c50207[ 	]+vluxseg8ei128.v[ 	]+v4,\(a0\),v12
++[ 	]+[0-9a-f]+:[ 	]+f6c50207[ 	]+vluxseg8ei128.v[ 	]+v4,\(a0\),v12
++[ 	]+[0-9a-f]+:[ 	]+f4c50207[ 	]+vluxseg8ei128.v[ 	]+v4,\(a0\),v12,v0.t
++[ 	]+[0-9a-f]+:[ 	]+f6c50227[ 	]+vsuxseg8ei128.v[ 	]+v4,\(a0\),v12
++[ 	]+[0-9a-f]+:[ 	]+f6c50227[ 	]+vsuxseg8ei128.v[ 	]+v4,\(a0\),v12
++[ 	]+[0-9a-f]+:[ 	]+f4c50227[ 	]+vsuxseg8ei128.v[ 	]+v4,\(a0\),v12,v0.t
++[ 	]+[0-9a-f]+:[ 	]+36c55207[ 	]+vluxseg2ei256.v[ 	]+v4,\(a0\),v12
++[ 	]+[0-9a-f]+:[ 	]+36c55207[ 	]+vluxseg2ei256.v[ 	]+v4,\(a0\),v12
++[ 	]+[0-9a-f]+:[ 	]+34c55207[ 	]+vluxseg2ei256.v[ 	]+v4,\(a0\),v12,v0.t
++[ 	]+[0-9a-f]+:[ 	]+36c55227[ 	]+vsuxseg2ei256.v[ 	]+v4,\(a0\),v12
++[ 	]+[0-9a-f]+:[ 	]+36c55227[ 	]+vsuxseg2ei256.v[ 	]+v4,\(a0\),v12
++[ 	]+[0-9a-f]+:[ 	]+34c55227[ 	]+vsuxseg2ei256.v[ 	]+v4,\(a0\),v12,v0.t
++[ 	]+[0-9a-f]+:[ 	]+56c55207[ 	]+vluxseg3ei256.v[ 	]+v4,\(a0\),v12
++[ 	]+[0-9a-f]+:[ 	]+56c55207[ 	]+vluxseg3ei256.v[ 	]+v4,\(a0\),v12
++[ 	]+[0-9a-f]+:[ 	]+54c55207[ 	]+vluxseg3ei256.v[ 	]+v4,\(a0\),v12,v0.t
++[ 	]+[0-9a-f]+:[ 	]+56c55227[ 	]+vsuxseg3ei256.v[ 	]+v4,\(a0\),v12
++[ 	]+[0-9a-f]+:[ 	]+56c55227[ 	]+vsuxseg3ei256.v[ 	]+v4,\(a0\),v12
++[ 	]+[0-9a-f]+:[ 	]+54c55227[ 	]+vsuxseg3ei256.v[ 	]+v4,\(a0\),v12,v0.t
++[ 	]+[0-9a-f]+:[ 	]+76c55207[ 	]+vluxseg4ei256.v[ 	]+v4,\(a0\),v12
++[ 	]+[0-9a-f]+:[ 	]+76c55207[ 	]+vluxseg4ei256.v[ 	]+v4,\(a0\),v12
++[ 	]+[0-9a-f]+:[ 	]+74c55207[ 	]+vluxseg4ei256.v[ 	]+v4,\(a0\),v12,v0.t
++[ 	]+[0-9a-f]+:[ 	]+76c55227[ 	]+vsuxseg4ei256.v[ 	]+v4,\(a0\),v12
++[ 	]+[0-9a-f]+:[ 	]+76c55227[ 	]+vsuxseg4ei256.v[ 	]+v4,\(a0\),v12
++[ 	]+[0-9a-f]+:[ 	]+74c55227[ 	]+vsuxseg4ei256.v[ 	]+v4,\(a0\),v12,v0.t
++[ 	]+[0-9a-f]+:[ 	]+96c55207[ 	]+vluxseg5ei256.v[ 	]+v4,\(a0\),v12
++[ 	]+[0-9a-f]+:[ 	]+96c55207[ 	]+vluxseg5ei256.v[ 	]+v4,\(a0\),v12
++[ 	]+[0-9a-f]+:[ 	]+94c55207[ 	]+vluxseg5ei256.v[ 	]+v4,\(a0\),v12,v0.t
++[ 	]+[0-9a-f]+:[ 	]+96c55227[ 	]+vsuxseg5ei256.v[ 	]+v4,\(a0\),v12
++[ 	]+[0-9a-f]+:[ 	]+96c55227[ 	]+vsuxseg5ei256.v[ 	]+v4,\(a0\),v12
++[ 	]+[0-9a-f]+:[ 	]+94c55227[ 	]+vsuxseg5ei256.v[ 	]+v4,\(a0\),v12,v0.t
++[ 	]+[0-9a-f]+:[ 	]+b6c55207[ 	]+vluxseg6ei256.v[ 	]+v4,\(a0\),v12
++[ 	]+[0-9a-f]+:[ 	]+b6c55207[ 	]+vluxseg6ei256.v[ 	]+v4,\(a0\),v12
++[ 	]+[0-9a-f]+:[ 	]+b4c55207[ 	]+vluxseg6ei256.v[ 	]+v4,\(a0\),v12,v0.t
++[ 	]+[0-9a-f]+:[ 	]+b6c55227[ 	]+vsuxseg6ei256.v[ 	]+v4,\(a0\),v12
++[ 	]+[0-9a-f]+:[ 	]+b6c55227[ 	]+vsuxseg6ei256.v[ 	]+v4,\(a0\),v12
++[ 	]+[0-9a-f]+:[ 	]+b4c55227[ 	]+vsuxseg6ei256.v[ 	]+v4,\(a0\),v12,v0.t
++[ 	]+[0-9a-f]+:[ 	]+d6c55207[ 	]+vluxseg7ei256.v[ 	]+v4,\(a0\),v12
++[ 	]+[0-9a-f]+:[ 	]+d6c55207[ 	]+vluxseg7ei256.v[ 	]+v4,\(a0\),v12
++[ 	]+[0-9a-f]+:[ 	]+d4c55207[ 	]+vluxseg7ei256.v[ 	]+v4,\(a0\),v12,v0.t
++[ 	]+[0-9a-f]+:[ 	]+d6c55227[ 	]+vsuxseg7ei256.v[ 	]+v4,\(a0\),v12
++[ 	]+[0-9a-f]+:[ 	]+d6c55227[ 	]+vsuxseg7ei256.v[ 	]+v4,\(a0\),v12
++[ 	]+[0-9a-f]+:[ 	]+d4c55227[ 	]+vsuxseg7ei256.v[ 	]+v4,\(a0\),v12,v0.t
++[ 	]+[0-9a-f]+:[ 	]+f6c55207[ 	]+vluxseg8ei256.v[ 	]+v4,\(a0\),v12
++[ 	]+[0-9a-f]+:[ 	]+f6c55207[ 	]+vluxseg8ei256.v[ 	]+v4,\(a0\),v12
++[ 	]+[0-9a-f]+:[ 	]+f4c55207[ 	]+vluxseg8ei256.v[ 	]+v4,\(a0\),v12,v0.t
++[ 	]+[0-9a-f]+:[ 	]+f6c55227[ 	]+vsuxseg8ei256.v[ 	]+v4,\(a0\),v12
++[ 	]+[0-9a-f]+:[ 	]+f6c55227[ 	]+vsuxseg8ei256.v[ 	]+v4,\(a0\),v12
++[ 	]+[0-9a-f]+:[ 	]+f4c55227[ 	]+vsuxseg8ei256.v[ 	]+v4,\(a0\),v12,v0.t
++[ 	]+[0-9a-f]+:[ 	]+36c56207[ 	]+vluxseg2ei512.v[ 	]+v4,\(a0\),v12
++[ 	]+[0-9a-f]+:[ 	]+36c56207[ 	]+vluxseg2ei512.v[ 	]+v4,\(a0\),v12
++[ 	]+[0-9a-f]+:[ 	]+34c56207[ 	]+vluxseg2ei512.v[ 	]+v4,\(a0\),v12,v0.t
++[ 	]+[0-9a-f]+:[ 	]+36c56227[ 	]+vsuxseg2ei512.v[ 	]+v4,\(a0\),v12
++[ 	]+[0-9a-f]+:[ 	]+36c56227[ 	]+vsuxseg2ei512.v[ 	]+v4,\(a0\),v12
++[ 	]+[0-9a-f]+:[ 	]+34c56227[ 	]+vsuxseg2ei512.v[ 	]+v4,\(a0\),v12,v0.t
++[ 	]+[0-9a-f]+:[ 	]+56c56207[ 	]+vluxseg3ei512.v[ 	]+v4,\(a0\),v12
++[ 	]+[0-9a-f]+:[ 	]+56c56207[ 	]+vluxseg3ei512.v[ 	]+v4,\(a0\),v12
++[ 	]+[0-9a-f]+:[ 	]+54c56207[ 	]+vluxseg3ei512.v[ 	]+v4,\(a0\),v12,v0.t
++[ 	]+[0-9a-f]+:[ 	]+56c56227[ 	]+vsuxseg3ei512.v[ 	]+v4,\(a0\),v12
++[ 	]+[0-9a-f]+:[ 	]+56c56227[ 	]+vsuxseg3ei512.v[ 	]+v4,\(a0\),v12
++[ 	]+[0-9a-f]+:[ 	]+54c56227[ 	]+vsuxseg3ei512.v[ 	]+v4,\(a0\),v12,v0.t
++[ 	]+[0-9a-f]+:[ 	]+76c56207[ 	]+vluxseg4ei512.v[ 	]+v4,\(a0\),v12
++[ 	]+[0-9a-f]+:[ 	]+76c56207[ 	]+vluxseg4ei512.v[ 	]+v4,\(a0\),v12
++[ 	]+[0-9a-f]+:[ 	]+74c56207[ 	]+vluxseg4ei512.v[ 	]+v4,\(a0\),v12,v0.t
++[ 	]+[0-9a-f]+:[ 	]+76c56227[ 	]+vsuxseg4ei512.v[ 	]+v4,\(a0\),v12
++[ 	]+[0-9a-f]+:[ 	]+76c56227[ 	]+vsuxseg4ei512.v[ 	]+v4,\(a0\),v12
++[ 	]+[0-9a-f]+:[ 	]+74c56227[ 	]+vsuxseg4ei512.v[ 	]+v4,\(a0\),v12,v0.t
++[ 	]+[0-9a-f]+:[ 	]+96c56207[ 	]+vluxseg5ei512.v[ 	]+v4,\(a0\),v12
++[ 	]+[0-9a-f]+:[ 	]+96c56207[ 	]+vluxseg5ei512.v[ 	]+v4,\(a0\),v12
++[ 	]+[0-9a-f]+:[ 	]+94c56207[ 	]+vluxseg5ei512.v[ 	]+v4,\(a0\),v12,v0.t
++[ 	]+[0-9a-f]+:[ 	]+96c56227[ 	]+vsuxseg5ei512.v[ 	]+v4,\(a0\),v12
++[ 	]+[0-9a-f]+:[ 	]+96c56227[ 	]+vsuxseg5ei512.v[ 	]+v4,\(a0\),v12
++[ 	]+[0-9a-f]+:[ 	]+94c56227[ 	]+vsuxseg5ei512.v[ 	]+v4,\(a0\),v12,v0.t
++[ 	]+[0-9a-f]+:[ 	]+b6c56207[ 	]+vluxseg6ei512.v[ 	]+v4,\(a0\),v12
++[ 	]+[0-9a-f]+:[ 	]+b6c56207[ 	]+vluxseg6ei512.v[ 	]+v4,\(a0\),v12
++[ 	]+[0-9a-f]+:[ 	]+b4c56207[ 	]+vluxseg6ei512.v[ 	]+v4,\(a0\),v12,v0.t
++[ 	]+[0-9a-f]+:[ 	]+b6c56227[ 	]+vsuxseg6ei512.v[ 	]+v4,\(a0\),v12
++[ 	]+[0-9a-f]+:[ 	]+b6c56227[ 	]+vsuxseg6ei512.v[ 	]+v4,\(a0\),v12
++[ 	]+[0-9a-f]+:[ 	]+b4c56227[ 	]+vsuxseg6ei512.v[ 	]+v4,\(a0\),v12,v0.t
++[ 	]+[0-9a-f]+:[ 	]+d6c56207[ 	]+vluxseg7ei512.v[ 	]+v4,\(a0\),v12
++[ 	]+[0-9a-f]+:[ 	]+d6c56207[ 	]+vluxseg7ei512.v[ 	]+v4,\(a0\),v12
++[ 	]+[0-9a-f]+:[ 	]+d4c56207[ 	]+vluxseg7ei512.v[ 	]+v4,\(a0\),v12,v0.t
++[ 	]+[0-9a-f]+:[ 	]+d6c56227[ 	]+vsuxseg7ei512.v[ 	]+v4,\(a0\),v12
++[ 	]+[0-9a-f]+:[ 	]+d6c56227[ 	]+vsuxseg7ei512.v[ 	]+v4,\(a0\),v12
++[ 	]+[0-9a-f]+:[ 	]+d4c56227[ 	]+vsuxseg7ei512.v[ 	]+v4,\(a0\),v12,v0.t
++[ 	]+[0-9a-f]+:[ 	]+f6c56207[ 	]+vluxseg8ei512.v[ 	]+v4,\(a0\),v12
++[ 	]+[0-9a-f]+:[ 	]+f6c56207[ 	]+vluxseg8ei512.v[ 	]+v4,\(a0\),v12
++[ 	]+[0-9a-f]+:[ 	]+f4c56207[ 	]+vluxseg8ei512.v[ 	]+v4,\(a0\),v12,v0.t
++[ 	]+[0-9a-f]+:[ 	]+f6c56227[ 	]+vsuxseg8ei512.v[ 	]+v4,\(a0\),v12
++[ 	]+[0-9a-f]+:[ 	]+f6c56227[ 	]+vsuxseg8ei512.v[ 	]+v4,\(a0\),v12
++[ 	]+[0-9a-f]+:[ 	]+f4c56227[ 	]+vsuxseg8ei512.v[ 	]+v4,\(a0\),v12,v0.t
++[ 	]+[0-9a-f]+:[ 	]+36c57207[ 	]+vluxseg2ei1024.v[ 	]+v4,\(a0\),v12
++[ 	]+[0-9a-f]+:[ 	]+36c57207[ 	]+vluxseg2ei1024.v[ 	]+v4,\(a0\),v12
++[ 	]+[0-9a-f]+:[ 	]+34c57207[ 	]+vluxseg2ei1024.v[ 	]+v4,\(a0\),v12,v0.t
++[ 	]+[0-9a-f]+:[ 	]+36c57227[ 	]+vsuxseg2ei1024.v[ 	]+v4,\(a0\),v12
++[ 	]+[0-9a-f]+:[ 	]+36c57227[ 	]+vsuxseg2ei1024.v[ 	]+v4,\(a0\),v12
++[ 	]+[0-9a-f]+:[ 	]+34c57227[ 	]+vsuxseg2ei1024.v[ 	]+v4,\(a0\),v12,v0.t
++[ 	]+[0-9a-f]+:[ 	]+56c57207[ 	]+vluxseg3ei1024.v[ 	]+v4,\(a0\),v12
++[ 	]+[0-9a-f]+:[ 	]+56c57207[ 	]+vluxseg3ei1024.v[ 	]+v4,\(a0\),v12
++[ 	]+[0-9a-f]+:[ 	]+54c57207[ 	]+vluxseg3ei1024.v[ 	]+v4,\(a0\),v12,v0.t
++[ 	]+[0-9a-f]+:[ 	]+56c57227[ 	]+vsuxseg3ei1024.v[ 	]+v4,\(a0\),v12
++[ 	]+[0-9a-f]+:[ 	]+56c57227[ 	]+vsuxseg3ei1024.v[ 	]+v4,\(a0\),v12
++[ 	]+[0-9a-f]+:[ 	]+54c57227[ 	]+vsuxseg3ei1024.v[ 	]+v4,\(a0\),v12,v0.t
++[ 	]+[0-9a-f]+:[ 	]+76c57207[ 	]+vluxseg4ei1024.v[ 	]+v4,\(a0\),v12
++[ 	]+[0-9a-f]+:[ 	]+76c57207[ 	]+vluxseg4ei1024.v[ 	]+v4,\(a0\),v12
++[ 	]+[0-9a-f]+:[ 	]+74c57207[ 	]+vluxseg4ei1024.v[ 	]+v4,\(a0\),v12,v0.t
++[ 	]+[0-9a-f]+:[ 	]+76c57227[ 	]+vsuxseg4ei1024.v[ 	]+v4,\(a0\),v12
++[ 	]+[0-9a-f]+:[ 	]+76c57227[ 	]+vsuxseg4ei1024.v[ 	]+v4,\(a0\),v12
++[ 	]+[0-9a-f]+:[ 	]+74c57227[ 	]+vsuxseg4ei1024.v[ 	]+v4,\(a0\),v12,v0.t
++[ 	]+[0-9a-f]+:[ 	]+96c57207[ 	]+vluxseg5ei1024.v[ 	]+v4,\(a0\),v12
++[ 	]+[0-9a-f]+:[ 	]+96c57207[ 	]+vluxseg5ei1024.v[ 	]+v4,\(a0\),v12
++[ 	]+[0-9a-f]+:[ 	]+94c57207[ 	]+vluxseg5ei1024.v[ 	]+v4,\(a0\),v12,v0.t
++[ 	]+[0-9a-f]+:[ 	]+96c57227[ 	]+vsuxseg5ei1024.v[ 	]+v4,\(a0\),v12
++[ 	]+[0-9a-f]+:[ 	]+96c57227[ 	]+vsuxseg5ei1024.v[ 	]+v4,\(a0\),v12
++[ 	]+[0-9a-f]+:[ 	]+94c57227[ 	]+vsuxseg5ei1024.v[ 	]+v4,\(a0\),v12,v0.t
++[ 	]+[0-9a-f]+:[ 	]+b6c57207[ 	]+vluxseg6ei1024.v[ 	]+v4,\(a0\),v12
++[ 	]+[0-9a-f]+:[ 	]+b6c57207[ 	]+vluxseg6ei1024.v[ 	]+v4,\(a0\),v12
++[ 	]+[0-9a-f]+:[ 	]+b4c57207[ 	]+vluxseg6ei1024.v[ 	]+v4,\(a0\),v12,v0.t
++[ 	]+[0-9a-f]+:[ 	]+b6c57227[ 	]+vsuxseg6ei1024.v[ 	]+v4,\(a0\),v12
++[ 	]+[0-9a-f]+:[ 	]+b6c57227[ 	]+vsuxseg6ei1024.v[ 	]+v4,\(a0\),v12
++[ 	]+[0-9a-f]+:[ 	]+b4c57227[ 	]+vsuxseg6ei1024.v[ 	]+v4,\(a0\),v12,v0.t
++[ 	]+[0-9a-f]+:[ 	]+d6c57207[ 	]+vluxseg7ei1024.v[ 	]+v4,\(a0\),v12
++[ 	]+[0-9a-f]+:[ 	]+d6c57207[ 	]+vluxseg7ei1024.v[ 	]+v4,\(a0\),v12
++[ 	]+[0-9a-f]+:[ 	]+d4c57207[ 	]+vluxseg7ei1024.v[ 	]+v4,\(a0\),v12,v0.t
++[ 	]+[0-9a-f]+:[ 	]+d6c57227[ 	]+vsuxseg7ei1024.v[ 	]+v4,\(a0\),v12
++[ 	]+[0-9a-f]+:[ 	]+d6c57227[ 	]+vsuxseg7ei1024.v[ 	]+v4,\(a0\),v12
++[ 	]+[0-9a-f]+:[ 	]+d4c57227[ 	]+vsuxseg7ei1024.v[ 	]+v4,\(a0\),v12,v0.t
++[ 	]+[0-9a-f]+:[ 	]+f6c57207[ 	]+vluxseg8ei1024.v[ 	]+v4,\(a0\),v12
++[ 	]+[0-9a-f]+:[ 	]+f6c57207[ 	]+vluxseg8ei1024.v[ 	]+v4,\(a0\),v12
++[ 	]+[0-9a-f]+:[ 	]+f4c57207[ 	]+vluxseg8ei1024.v[ 	]+v4,\(a0\),v12,v0.t
++[ 	]+[0-9a-f]+:[ 	]+f6c57227[ 	]+vsuxseg8ei1024.v[ 	]+v4,\(a0\),v12
++[ 	]+[0-9a-f]+:[ 	]+f6c57227[ 	]+vsuxseg8ei1024.v[ 	]+v4,\(a0\),v12
++[ 	]+[0-9a-f]+:[ 	]+f4c57227[ 	]+vsuxseg8ei1024.v[ 	]+v4,\(a0\),v12,v0.t
+ [ 	]+[0-9a-f]+:[ 	]+23050207[ 	]+vlseg2e8ff.v[ 	]+v4,\(a0\)
+ [ 	]+[0-9a-f]+:[ 	]+23050207[ 	]+vlseg2e8ff.v[ 	]+v4,\(a0\)
+ [ 	]+[0-9a-f]+:[ 	]+21050207[ 	]+vlseg2e8ff.v[ 	]+v4,\(a0\),v0.t
+diff --git a/gas/testsuite/gas/riscv/vector-insns.s b/gas/testsuite/gas/riscv/vector-insns.s
+index b78604025a..5431863af9 100644
+--- a/gas/testsuite/gas/riscv/vector-insns.s
++++ b/gas/testsuite/gas/riscv/vector-insns.s
+@@ -130,42 +130,54 @@
+ 	vsse1024.v v4, 0(a0), a1
+ 	vsse1024.v v4, (a0), a1, v0.t
+ 
+-	vlxei8.v v4, (a0), v12
+-	vlxei8.v v4, 0(a0), v12
+-	vlxei8.v v4, (a0), v12, v0.t
+-	vsxei8.v v4, (a0), v12
+-	vsxei8.v v4, 0(a0), v12
+-	vsxei8.v v4, (a0), v12, v0.t
++	vloxei8.v v4, (a0), v12
++	vloxei8.v v4, 0(a0), v12
++	vloxei8.v v4, (a0), v12, v0.t
++	vsoxei8.v v4, (a0), v12
++	vsoxei8.v v4, 0(a0), v12
++	vsoxei8.v v4, (a0), v12, v0.t
++	vluxei8.v v4, (a0), v12
++	vluxei8.v v4, 0(a0), v12
++	vluxei8.v v4, (a0), v12, v0.t
+ 	vsuxei8.v v4, (a0), v12
+ 	vsuxei8.v v4, 0(a0), v12
+ 	vsuxei8.v v4, (a0), v12, v0.t
+ 
+-	vlxei16.v v4, (a0), v12
+-	vlxei16.v v4, 0(a0), v12
+-	vlxei16.v v4, (a0), v12, v0.t
+-	vsxei16.v v4, (a0), v12
+-	vsxei16.v v4, 0(a0), v12
+-	vsxei16.v v4, (a0), v12, v0.t
++	vloxei16.v v4, (a0), v12
++	vloxei16.v v4, 0(a0), v12
++	vloxei16.v v4, (a0), v12, v0.t
++	vsoxei16.v v4, (a0), v12
++	vsoxei16.v v4, 0(a0), v12
++	vsoxei16.v v4, (a0), v12, v0.t
++	vluxei16.v v4, (a0), v12
++	vluxei16.v v4, 0(a0), v12
++	vluxei16.v v4, (a0), v12, v0.t
+ 	vsuxei16.v v4, (a0), v12
+ 	vsuxei16.v v4, 0(a0), v12
+ 	vsuxei16.v v4, (a0), v12, v0.t
+ 
+-	vlxei32.v v4, (a0), v12
+-	vlxei32.v v4, 0(a0), v12
+-	vlxei32.v v4, (a0), v12, v0.t
+-	vsxei32.v v4, (a0), v12
+-	vsxei32.v v4, 0(a0), v12
+-	vsxei32.v v4, (a0), v12, v0.t
++	vloxei32.v v4, (a0), v12
++	vloxei32.v v4, 0(a0), v12
++	vloxei32.v v4, (a0), v12, v0.t
++	vsoxei32.v v4, (a0), v12
++	vsoxei32.v v4, 0(a0), v12
++	vsoxei32.v v4, (a0), v12, v0.t
++	vluxei32.v v4, (a0), v12
++	vluxei32.v v4, 0(a0), v12
++	vluxei32.v v4, (a0), v12, v0.t
+ 	vsuxei32.v v4, (a0), v12
+ 	vsuxei32.v v4, 0(a0), v12
+ 	vsuxei32.v v4, (a0), v12, v0.t
+ 
+-	vlxei64.v v4, (a0), v12
+-	vlxei64.v v4, 0(a0), v12
+-	vlxei64.v v4, (a0), v12, v0.t
+-	vsxei64.v v4, (a0), v12
+-	vsxei64.v v4, 0(a0), v12
+-	vsxei64.v v4, (a0), v12, v0.t
++	vloxei64.v v4, (a0), v12
++	vloxei64.v v4, 0(a0), v12
++	vloxei64.v v4, (a0), v12, v0.t
++	vsoxei64.v v4, (a0), v12
++	vsoxei64.v v4, 0(a0), v12
++	vsoxei64.v v4, (a0), v12, v0.t
++	vluxei64.v v4, (a0), v12
++	vluxei64.v v4, 0(a0), v12
++	vluxei64.v v4, (a0), v12, v0.t
+ 	vsuxei64.v v4, (a0), v12
+ 	vsuxei64.v v4, 0(a0), v12
+ 	vsuxei64.v v4, (a0), v12, v0.t
+@@ -986,397 +998,789 @@
+ 	vssseg8e1024.v v4, 0(a0), a1
+ 	vssseg8e1024.v v4, (a0), a1, v0.t
+ 
+-	vlxseg2ei8.v v4, (a0), v12
+-	vlxseg2ei8.v v4, 0(a0), v12
+-	vlxseg2ei8.v v4, (a0), v12, v0.t
+-	vsxseg2ei8.v v4, (a0), v12
+-	vsxseg2ei8.v v4, 0(a0), v12
+-	vsxseg2ei8.v v4, (a0), v12, v0.t
+-
+-	vlxseg3ei8.v v4, (a0), v12
+-	vlxseg3ei8.v v4, 0(a0), v12
+-	vlxseg3ei8.v v4, (a0), v12, v0.t
+-	vsxseg3ei8.v v4, (a0), v12
+-	vsxseg3ei8.v v4, 0(a0), v12
+-	vsxseg3ei8.v v4, (a0), v12, v0.t
+-
+-	vlxseg4ei8.v v4, (a0), v12
+-	vlxseg4ei8.v v4, 0(a0), v12
+-	vlxseg4ei8.v v4, (a0), v12, v0.t
+-	vsxseg4ei8.v v4, (a0), v12
+-	vsxseg4ei8.v v4, 0(a0), v12
+-	vsxseg4ei8.v v4, (a0), v12, v0.t
+-
+-	vlxseg5ei8.v v4, (a0), v12
+-	vlxseg5ei8.v v4, 0(a0), v12
+-	vlxseg5ei8.v v4, (a0), v12, v0.t
+-	vsxseg5ei8.v v4, (a0), v12
+-	vsxseg5ei8.v v4, 0(a0), v12
+-	vsxseg5ei8.v v4, (a0), v12, v0.t
+-
+-	vlxseg6ei8.v v4, (a0), v12
+-	vlxseg6ei8.v v4, 0(a0), v12
+-	vlxseg6ei8.v v4, (a0), v12, v0.t
+-	vsxseg6ei8.v v4, (a0), v12
+-	vsxseg6ei8.v v4, 0(a0), v12
+-	vsxseg6ei8.v v4, (a0), v12, v0.t
+-
+-	vlxseg7ei8.v v4, (a0), v12
+-	vlxseg7ei8.v v4, 0(a0), v12
+-	vlxseg7ei8.v v4, (a0), v12, v0.t
+-	vsxseg7ei8.v v4, (a0), v12
+-	vsxseg7ei8.v v4, 0(a0), v12
+-	vsxseg7ei8.v v4, (a0), v12, v0.t
+-
+-	vlxseg8ei8.v v4, (a0), v12
+-	vlxseg8ei8.v v4, 0(a0), v12
+-	vlxseg8ei8.v v4, (a0), v12, v0.t
+-	vsxseg8ei8.v v4, (a0), v12
+-	vsxseg8ei8.v v4, 0(a0), v12
+-	vsxseg8ei8.v v4, (a0), v12, v0.t
+-
+-	vlxseg2ei16.v v4, (a0), v12
+-	vlxseg2ei16.v v4, 0(a0), v12
+-	vlxseg2ei16.v v4, (a0), v12, v0.t
+-	vsxseg2ei16.v v4, (a0), v12
+-	vsxseg2ei16.v v4, 0(a0), v12
+-	vsxseg2ei16.v v4, (a0), v12, v0.t
+-
+-	vlxseg3ei16.v v4, (a0), v12
+-	vlxseg3ei16.v v4, 0(a0), v12
+-	vlxseg3ei16.v v4, (a0), v12, v0.t
+-	vsxseg3ei16.v v4, (a0), v12
+-	vsxseg3ei16.v v4, 0(a0), v12
+-	vsxseg3ei16.v v4, (a0), v12, v0.t
+-
+-	vlxseg4ei16.v v4, (a0), v12
+-	vlxseg4ei16.v v4, 0(a0), v12
+-	vlxseg4ei16.v v4, (a0), v12, v0.t
+-	vsxseg4ei16.v v4, (a0), v12
+-	vsxseg4ei16.v v4, 0(a0), v12
+-	vsxseg4ei16.v v4, (a0), v12, v0.t
+-
+-	vlxseg5ei16.v v4, (a0), v12
+-	vlxseg5ei16.v v4, 0(a0), v12
+-	vlxseg5ei16.v v4, (a0), v12, v0.t
+-	vsxseg5ei16.v v4, (a0), v12
+-	vsxseg5ei16.v v4, 0(a0), v12
+-	vsxseg5ei16.v v4, (a0), v12, v0.t
+-
+-	vlxseg6ei16.v v4, (a0), v12
+-	vlxseg6ei16.v v4, 0(a0), v12
+-	vlxseg6ei16.v v4, (a0), v12, v0.t
+-	vsxseg6ei16.v v4, (a0), v12
+-	vsxseg6ei16.v v4, 0(a0), v12
+-	vsxseg6ei16.v v4, (a0), v12, v0.t
+-
+-	vlxseg7ei16.v v4, (a0), v12
+-	vlxseg7ei16.v v4, 0(a0), v12
+-	vlxseg7ei16.v v4, (a0), v12, v0.t
+-	vsxseg7ei16.v v4, (a0), v12
+-	vsxseg7ei16.v v4, 0(a0), v12
+-	vsxseg7ei16.v v4, (a0), v12, v0.t
+-
+-	vlxseg8ei16.v v4, (a0), v12
+-	vlxseg8ei16.v v4, 0(a0), v12
+-	vlxseg8ei16.v v4, (a0), v12, v0.t
+-	vsxseg8ei16.v v4, (a0), v12
+-	vsxseg8ei16.v v4, 0(a0), v12
+-	vsxseg8ei16.v v4, (a0), v12, v0.t
+-
+-	vlxseg2ei32.v v4, (a0), v12
+-	vlxseg2ei32.v v4, 0(a0), v12
+-	vlxseg2ei32.v v4, (a0), v12, v0.t
+-	vsxseg2ei32.v v4, (a0), v12
+-	vsxseg2ei32.v v4, 0(a0), v12
+-	vsxseg2ei32.v v4, (a0), v12, v0.t
+-
+-	vlxseg3ei32.v v4, (a0), v12
+-	vlxseg3ei32.v v4, 0(a0), v12
+-	vlxseg3ei32.v v4, (a0), v12, v0.t
+-	vsxseg3ei32.v v4, (a0), v12
+-	vsxseg3ei32.v v4, 0(a0), v12
+-	vsxseg3ei32.v v4, (a0), v12, v0.t
+-
+-	vlxseg4ei32.v v4, (a0), v12
+-	vlxseg4ei32.v v4, 0(a0), v12
+-	vlxseg4ei32.v v4, (a0), v12, v0.t
+-	vsxseg4ei32.v v4, (a0), v12
+-	vsxseg4ei32.v v4, 0(a0), v12
+-	vsxseg4ei32.v v4, (a0), v12, v0.t
+-
+-	vlxseg5ei32.v v4, (a0), v12
+-	vlxseg5ei32.v v4, 0(a0), v12
+-	vlxseg5ei32.v v4, (a0), v12, v0.t
+-	vsxseg5ei32.v v4, (a0), v12
+-	vsxseg5ei32.v v4, 0(a0), v12
+-	vsxseg5ei32.v v4, (a0), v12, v0.t
+-
+-	vlxseg6ei32.v v4, (a0), v12
+-	vlxseg6ei32.v v4, 0(a0), v12
+-	vlxseg6ei32.v v4, (a0), v12, v0.t
+-	vsxseg6ei32.v v4, (a0), v12
+-	vsxseg6ei32.v v4, 0(a0), v12
+-	vsxseg6ei32.v v4, (a0), v12, v0.t
+-
+-	vlxseg7ei32.v v4, (a0), v12
+-	vlxseg7ei32.v v4, 0(a0), v12
+-	vlxseg7ei32.v v4, (a0), v12, v0.t
+-	vsxseg7ei32.v v4, (a0), v12
+-	vsxseg7ei32.v v4, 0(a0), v12
+-	vsxseg7ei32.v v4, (a0), v12, v0.t
+-
+-	vlxseg8ei32.v v4, (a0), v12
+-	vlxseg8ei32.v v4, 0(a0), v12
+-	vlxseg8ei32.v v4, (a0), v12, v0.t
+-	vsxseg8ei32.v v4, (a0), v12
+-	vsxseg8ei32.v v4, 0(a0), v12
+-	vsxseg8ei32.v v4, (a0), v12, v0.t
+-
+-	vlxseg2ei64.v v4, (a0), v12
+-	vlxseg2ei64.v v4, 0(a0), v12
+-	vlxseg2ei64.v v4, (a0), v12, v0.t
+-	vsxseg2ei64.v v4, (a0), v12
+-	vsxseg2ei64.v v4, 0(a0), v12
+-	vsxseg2ei64.v v4, (a0), v12, v0.t
+-
+-	vlxseg3ei64.v v4, (a0), v12
+-	vlxseg3ei64.v v4, 0(a0), v12
+-	vlxseg3ei64.v v4, (a0), v12, v0.t
+-	vsxseg3ei64.v v4, (a0), v12
+-	vsxseg3ei64.v v4, 0(a0), v12
+-	vsxseg3ei64.v v4, (a0), v12, v0.t
+-
+-	vlxseg4ei64.v v4, (a0), v12
+-	vlxseg4ei64.v v4, 0(a0), v12
+-	vlxseg4ei64.v v4, (a0), v12, v0.t
+-	vsxseg4ei64.v v4, (a0), v12
+-	vsxseg4ei64.v v4, 0(a0), v12
+-	vsxseg4ei64.v v4, (a0), v12, v0.t
+-
+-	vlxseg5ei64.v v4, (a0), v12
+-	vlxseg5ei64.v v4, 0(a0), v12
+-	vlxseg5ei64.v v4, (a0), v12, v0.t
+-	vsxseg5ei64.v v4, (a0), v12
+-	vsxseg5ei64.v v4, 0(a0), v12
+-	vsxseg5ei64.v v4, (a0), v12, v0.t
+-
+-	vlxseg6ei64.v v4, (a0), v12
+-	vlxseg6ei64.v v4, 0(a0), v12
+-	vlxseg6ei64.v v4, (a0), v12, v0.t
+-	vsxseg6ei64.v v4, (a0), v12
+-	vsxseg6ei64.v v4, 0(a0), v12
+-	vsxseg6ei64.v v4, (a0), v12, v0.t
+-
+-	vlxseg7ei64.v v4, (a0), v12
+-	vlxseg7ei64.v v4, 0(a0), v12
+-	vlxseg7ei64.v v4, (a0), v12, v0.t
+-	vsxseg7ei64.v v4, (a0), v12
+-	vsxseg7ei64.v v4, 0(a0), v12
+-	vsxseg7ei64.v v4, (a0), v12, v0.t
+-
+-	vlxseg8ei64.v v4, (a0), v12
+-	vlxseg8ei64.v v4, 0(a0), v12
+-	vlxseg8ei64.v v4, (a0), v12, v0.t
+-	vsxseg8ei64.v v4, (a0), v12
+-	vsxseg8ei64.v v4, 0(a0), v12
+-	vsxseg8ei64.v v4, (a0), v12, v0.t
+-
+-	vlxseg2ei128.v v4, (a0), v12
+-	vlxseg2ei128.v v4, 0(a0), v12
+-	vlxseg2ei128.v v4, (a0), v12, v0.t
+-	vsxseg2ei128.v v4, (a0), v12
+-	vsxseg2ei128.v v4, 0(a0), v12
+-	vsxseg2ei128.v v4, (a0), v12, v0.t
+-
+-	vlxseg3ei128.v v4, (a0), v12
+-	vlxseg3ei128.v v4, 0(a0), v12
+-	vlxseg3ei128.v v4, (a0), v12, v0.t
+-	vsxseg3ei128.v v4, (a0), v12
+-	vsxseg3ei128.v v4, 0(a0), v12
+-	vsxseg3ei128.v v4, (a0), v12, v0.t
+-
+-	vlxseg4ei128.v v4, (a0), v12
+-	vlxseg4ei128.v v4, 0(a0), v12
+-	vlxseg4ei128.v v4, (a0), v12, v0.t
+-	vsxseg4ei128.v v4, (a0), v12
+-	vsxseg4ei128.v v4, 0(a0), v12
+-	vsxseg4ei128.v v4, (a0), v12, v0.t
+-
+-	vlxseg5ei128.v v4, (a0), v12
+-	vlxseg5ei128.v v4, 0(a0), v12
+-	vlxseg5ei128.v v4, (a0), v12, v0.t
+-	vsxseg5ei128.v v4, (a0), v12
+-	vsxseg5ei128.v v4, 0(a0), v12
+-	vsxseg5ei128.v v4, (a0), v12, v0.t
+-
+-	vlxseg6ei128.v v4, (a0), v12
+-	vlxseg6ei128.v v4, 0(a0), v12
+-	vlxseg6ei128.v v4, (a0), v12, v0.t
+-	vsxseg6ei128.v v4, (a0), v12
+-	vsxseg6ei128.v v4, 0(a0), v12
+-	vsxseg6ei128.v v4, (a0), v12, v0.t
+-
+-	vlxseg7ei128.v v4, (a0), v12
+-	vlxseg7ei128.v v4, 0(a0), v12
+-	vlxseg7ei128.v v4, (a0), v12, v0.t
+-	vsxseg7ei128.v v4, (a0), v12
+-	vsxseg7ei128.v v4, 0(a0), v12
+-	vsxseg7ei128.v v4, (a0), v12, v0.t
+-
+-	vlxseg8ei128.v v4, (a0), v12
+-	vlxseg8ei128.v v4, 0(a0), v12
+-	vlxseg8ei128.v v4, (a0), v12, v0.t
+-	vsxseg8ei128.v v4, (a0), v12
+-	vsxseg8ei128.v v4, 0(a0), v12
+-	vsxseg8ei128.v v4, (a0), v12, v0.t
+-
+-	vlxseg2ei256.v v4, (a0), v12
+-	vlxseg2ei256.v v4, 0(a0), v12
+-	vlxseg2ei256.v v4, (a0), v12, v0.t
+-	vsxseg2ei256.v v4, (a0), v12
+-	vsxseg2ei256.v v4, 0(a0), v12
+-	vsxseg2ei256.v v4, (a0), v12, v0.t
+-
+-	vlxseg3ei256.v v4, (a0), v12
+-	vlxseg3ei256.v v4, 0(a0), v12
+-	vlxseg3ei256.v v4, (a0), v12, v0.t
+-	vsxseg3ei256.v v4, (a0), v12
+-	vsxseg3ei256.v v4, 0(a0), v12
+-	vsxseg3ei256.v v4, (a0), v12, v0.t
+-
+-	vlxseg4ei256.v v4, (a0), v12
+-	vlxseg4ei256.v v4, 0(a0), v12
+-	vlxseg4ei256.v v4, (a0), v12, v0.t
+-	vsxseg4ei256.v v4, (a0), v12
+-	vsxseg4ei256.v v4, 0(a0), v12
+-	vsxseg4ei256.v v4, (a0), v12, v0.t
+-
+-	vlxseg5ei256.v v4, (a0), v12
+-	vlxseg5ei256.v v4, 0(a0), v12
+-	vlxseg5ei256.v v4, (a0), v12, v0.t
+-	vsxseg5ei256.v v4, (a0), v12
+-	vsxseg5ei256.v v4, 0(a0), v12
+-	vsxseg5ei256.v v4, (a0), v12, v0.t
+-
+-	vlxseg6ei256.v v4, (a0), v12
+-	vlxseg6ei256.v v4, 0(a0), v12
+-	vlxseg6ei256.v v4, (a0), v12, v0.t
+-	vsxseg6ei256.v v4, (a0), v12
+-	vsxseg6ei256.v v4, 0(a0), v12
+-	vsxseg6ei256.v v4, (a0), v12, v0.t
+-
+-	vlxseg7ei256.v v4, (a0), v12
+-	vlxseg7ei256.v v4, 0(a0), v12
+-	vlxseg7ei256.v v4, (a0), v12, v0.t
+-	vsxseg7ei256.v v4, (a0), v12
+-	vsxseg7ei256.v v4, 0(a0), v12
+-	vsxseg7ei256.v v4, (a0), v12, v0.t
+-
+-	vlxseg8ei256.v v4, (a0), v12
+-	vlxseg8ei256.v v4, 0(a0), v12
+-	vlxseg8ei256.v v4, (a0), v12, v0.t
+-	vsxseg8ei256.v v4, (a0), v12
+-	vsxseg8ei256.v v4, 0(a0), v12
+-	vsxseg8ei256.v v4, (a0), v12, v0.t
+-
+-	vlxseg2ei512.v v4, (a0), v12
+-	vlxseg2ei512.v v4, 0(a0), v12
+-	vlxseg2ei512.v v4, (a0), v12, v0.t
+-	vsxseg2ei512.v v4, (a0), v12
+-	vsxseg2ei512.v v4, 0(a0), v12
+-	vsxseg2ei512.v v4, (a0), v12, v0.t
+-
+-	vlxseg3ei512.v v4, (a0), v12
+-	vlxseg3ei512.v v4, 0(a0), v12
+-	vlxseg3ei512.v v4, (a0), v12, v0.t
+-	vsxseg3ei512.v v4, (a0), v12
+-	vsxseg3ei512.v v4, 0(a0), v12
+-	vsxseg3ei512.v v4, (a0), v12, v0.t
+-
+-	vlxseg4ei512.v v4, (a0), v12
+-	vlxseg4ei512.v v4, 0(a0), v12
+-	vlxseg4ei512.v v4, (a0), v12, v0.t
+-	vsxseg4ei512.v v4, (a0), v12
+-	vsxseg4ei512.v v4, 0(a0), v12
+-	vsxseg4ei512.v v4, (a0), v12, v0.t
+-
+-	vlxseg5ei512.v v4, (a0), v12
+-	vlxseg5ei512.v v4, 0(a0), v12
+-	vlxseg5ei512.v v4, (a0), v12, v0.t
+-	vsxseg5ei512.v v4, (a0), v12
+-	vsxseg5ei512.v v4, 0(a0), v12
+-	vsxseg5ei512.v v4, (a0), v12, v0.t
+-
+-	vlxseg6ei512.v v4, (a0), v12
+-	vlxseg6ei512.v v4, 0(a0), v12
+-	vlxseg6ei512.v v4, (a0), v12, v0.t
+-	vsxseg6ei512.v v4, (a0), v12
+-	vsxseg6ei512.v v4, 0(a0), v12
+-	vsxseg6ei512.v v4, (a0), v12, v0.t
+-
+-	vlxseg7ei512.v v4, (a0), v12
+-	vlxseg7ei512.v v4, 0(a0), v12
+-	vlxseg7ei512.v v4, (a0), v12, v0.t
+-	vsxseg7ei512.v v4, (a0), v12
+-	vsxseg7ei512.v v4, 0(a0), v12
+-	vsxseg7ei512.v v4, (a0), v12, v0.t
+-
+-	vlxseg8ei512.v v4, (a0), v12
+-	vlxseg8ei512.v v4, 0(a0), v12
+-	vlxseg8ei512.v v4, (a0), v12, v0.t
+-	vsxseg8ei512.v v4, (a0), v12
+-	vsxseg8ei512.v v4, 0(a0), v12
+-	vsxseg8ei512.v v4, (a0), v12, v0.t
+-
+-	vlxseg2ei1024.v v4, (a0), v12
+-	vlxseg2ei1024.v v4, 0(a0), v12
+-	vlxseg2ei1024.v v4, (a0), v12, v0.t
+-	vsxseg2ei1024.v v4, (a0), v12
+-	vsxseg2ei1024.v v4, 0(a0), v12
+-	vsxseg2ei1024.v v4, (a0), v12, v0.t
+-
+-	vlxseg3ei1024.v v4, (a0), v12
+-	vlxseg3ei1024.v v4, 0(a0), v12
+-	vlxseg3ei1024.v v4, (a0), v12, v0.t
+-	vsxseg3ei1024.v v4, (a0), v12
+-	vsxseg3ei1024.v v4, 0(a0), v12
+-	vsxseg3ei1024.v v4, (a0), v12, v0.t
+-
+-	vlxseg4ei1024.v v4, (a0), v12
+-	vlxseg4ei1024.v v4, 0(a0), v12
+-	vlxseg4ei1024.v v4, (a0), v12, v0.t
+-	vsxseg4ei1024.v v4, (a0), v12
+-	vsxseg4ei1024.v v4, 0(a0), v12
+-	vsxseg4ei1024.v v4, (a0), v12, v0.t
+-
+-	vlxseg5ei1024.v v4, (a0), v12
+-	vlxseg5ei1024.v v4, 0(a0), v12
+-	vlxseg5ei1024.v v4, (a0), v12, v0.t
+-	vsxseg5ei1024.v v4, (a0), v12
+-	vsxseg5ei1024.v v4, 0(a0), v12
+-	vsxseg5ei1024.v v4, (a0), v12, v0.t
+-
+-	vlxseg6ei1024.v v4, (a0), v12
+-	vlxseg6ei1024.v v4, 0(a0), v12
+-	vlxseg6ei1024.v v4, (a0), v12, v0.t
+-	vsxseg6ei1024.v v4, (a0), v12
+-	vsxseg6ei1024.v v4, 0(a0), v12
+-	vsxseg6ei1024.v v4, (a0), v12, v0.t
+-
+-	vlxseg7ei1024.v v4, (a0), v12
+-	vlxseg7ei1024.v v4, 0(a0), v12
+-	vlxseg7ei1024.v v4, (a0), v12, v0.t
+-	vsxseg7ei1024.v v4, (a0), v12
+-	vsxseg7ei1024.v v4, 0(a0), v12
+-	vsxseg7ei1024.v v4, (a0), v12, v0.t
+-
+-	vlxseg8ei1024.v v4, (a0), v12
+-	vlxseg8ei1024.v v4, 0(a0), v12
+-	vlxseg8ei1024.v v4, (a0), v12, v0.t
+-	vsxseg8ei1024.v v4, (a0), v12
+-	vsxseg8ei1024.v v4, 0(a0), v12
+-	vsxseg8ei1024.v v4, (a0), v12, v0.t
++	vloxseg2ei8.v v4, (a0), v12
++	vloxseg2ei8.v v4, 0(a0), v12
++	vloxseg2ei8.v v4, (a0), v12, v0.t
++	vsoxseg2ei8.v v4, (a0), v12
++	vsoxseg2ei8.v v4, 0(a0), v12
++	vsoxseg2ei8.v v4, (a0), v12, v0.t
++
++	vloxseg3ei8.v v4, (a0), v12
++	vloxseg3ei8.v v4, 0(a0), v12
++	vloxseg3ei8.v v4, (a0), v12, v0.t
++	vsoxseg3ei8.v v4, (a0), v12
++	vsoxseg3ei8.v v4, 0(a0), v12
++	vsoxseg3ei8.v v4, (a0), v12, v0.t
++
++	vloxseg4ei8.v v4, (a0), v12
++	vloxseg4ei8.v v4, 0(a0), v12
++	vloxseg4ei8.v v4, (a0), v12, v0.t
++	vsoxseg4ei8.v v4, (a0), v12
++	vsoxseg4ei8.v v4, 0(a0), v12
++	vsoxseg4ei8.v v4, (a0), v12, v0.t
++
++	vloxseg5ei8.v v4, (a0), v12
++	vloxseg5ei8.v v4, 0(a0), v12
++	vloxseg5ei8.v v4, (a0), v12, v0.t
++	vsoxseg5ei8.v v4, (a0), v12
++	vsoxseg5ei8.v v4, 0(a0), v12
++	vsoxseg5ei8.v v4, (a0), v12, v0.t
++
++	vloxseg6ei8.v v4, (a0), v12
++	vloxseg6ei8.v v4, 0(a0), v12
++	vloxseg6ei8.v v4, (a0), v12, v0.t
++	vsoxseg6ei8.v v4, (a0), v12
++	vsoxseg6ei8.v v4, 0(a0), v12
++	vsoxseg6ei8.v v4, (a0), v12, v0.t
++
++	vloxseg7ei8.v v4, (a0), v12
++	vloxseg7ei8.v v4, 0(a0), v12
++	vloxseg7ei8.v v4, (a0), v12, v0.t
++	vsoxseg7ei8.v v4, (a0), v12
++	vsoxseg7ei8.v v4, 0(a0), v12
++	vsoxseg7ei8.v v4, (a0), v12, v0.t
++
++	vloxseg8ei8.v v4, (a0), v12
++	vloxseg8ei8.v v4, 0(a0), v12
++	vloxseg8ei8.v v4, (a0), v12, v0.t
++	vsoxseg8ei8.v v4, (a0), v12
++	vsoxseg8ei8.v v4, 0(a0), v12
++	vsoxseg8ei8.v v4, (a0), v12, v0.t
++
++	vloxseg2ei16.v v4, (a0), v12
++	vloxseg2ei16.v v4, 0(a0), v12
++	vloxseg2ei16.v v4, (a0), v12, v0.t
++	vsoxseg2ei16.v v4, (a0), v12
++	vsoxseg2ei16.v v4, 0(a0), v12
++	vsoxseg2ei16.v v4, (a0), v12, v0.t
++
++	vloxseg3ei16.v v4, (a0), v12
++	vloxseg3ei16.v v4, 0(a0), v12
++	vloxseg3ei16.v v4, (a0), v12, v0.t
++	vsoxseg3ei16.v v4, (a0), v12
++	vsoxseg3ei16.v v4, 0(a0), v12
++	vsoxseg3ei16.v v4, (a0), v12, v0.t
++
++	vloxseg4ei16.v v4, (a0), v12
++	vloxseg4ei16.v v4, 0(a0), v12
++	vloxseg4ei16.v v4, (a0), v12, v0.t
++	vsoxseg4ei16.v v4, (a0), v12
++	vsoxseg4ei16.v v4, 0(a0), v12
++	vsoxseg4ei16.v v4, (a0), v12, v0.t
++
++	vloxseg5ei16.v v4, (a0), v12
++	vloxseg5ei16.v v4, 0(a0), v12
++	vloxseg5ei16.v v4, (a0), v12, v0.t
++	vsoxseg5ei16.v v4, (a0), v12
++	vsoxseg5ei16.v v4, 0(a0), v12
++	vsoxseg5ei16.v v4, (a0), v12, v0.t
++
++	vloxseg6ei16.v v4, (a0), v12
++	vloxseg6ei16.v v4, 0(a0), v12
++	vloxseg6ei16.v v4, (a0), v12, v0.t
++	vsoxseg6ei16.v v4, (a0), v12
++	vsoxseg6ei16.v v4, 0(a0), v12
++	vsoxseg6ei16.v v4, (a0), v12, v0.t
++
++	vloxseg7ei16.v v4, (a0), v12
++	vloxseg7ei16.v v4, 0(a0), v12
++	vloxseg7ei16.v v4, (a0), v12, v0.t
++	vsoxseg7ei16.v v4, (a0), v12
++	vsoxseg7ei16.v v4, 0(a0), v12
++	vsoxseg7ei16.v v4, (a0), v12, v0.t
++
++	vloxseg8ei16.v v4, (a0), v12
++	vloxseg8ei16.v v4, 0(a0), v12
++	vloxseg8ei16.v v4, (a0), v12, v0.t
++	vsoxseg8ei16.v v4, (a0), v12
++	vsoxseg8ei16.v v4, 0(a0), v12
++	vsoxseg8ei16.v v4, (a0), v12, v0.t
++
++	vloxseg2ei32.v v4, (a0), v12
++	vloxseg2ei32.v v4, 0(a0), v12
++	vloxseg2ei32.v v4, (a0), v12, v0.t
++	vsoxseg2ei32.v v4, (a0), v12
++	vsoxseg2ei32.v v4, 0(a0), v12
++	vsoxseg2ei32.v v4, (a0), v12, v0.t
++
++	vloxseg3ei32.v v4, (a0), v12
++	vloxseg3ei32.v v4, 0(a0), v12
++	vloxseg3ei32.v v4, (a0), v12, v0.t
++	vsoxseg3ei32.v v4, (a0), v12
++	vsoxseg3ei32.v v4, 0(a0), v12
++	vsoxseg3ei32.v v4, (a0), v12, v0.t
++
++	vloxseg4ei32.v v4, (a0), v12
++	vloxseg4ei32.v v4, 0(a0), v12
++	vloxseg4ei32.v v4, (a0), v12, v0.t
++	vsoxseg4ei32.v v4, (a0), v12
++	vsoxseg4ei32.v v4, 0(a0), v12
++	vsoxseg4ei32.v v4, (a0), v12, v0.t
++
++	vloxseg5ei32.v v4, (a0), v12
++	vloxseg5ei32.v v4, 0(a0), v12
++	vloxseg5ei32.v v4, (a0), v12, v0.t
++	vsoxseg5ei32.v v4, (a0), v12
++	vsoxseg5ei32.v v4, 0(a0), v12
++	vsoxseg5ei32.v v4, (a0), v12, v0.t
++
++	vloxseg6ei32.v v4, (a0), v12
++	vloxseg6ei32.v v4, 0(a0), v12
++	vloxseg6ei32.v v4, (a0), v12, v0.t
++	vsoxseg6ei32.v v4, (a0), v12
++	vsoxseg6ei32.v v4, 0(a0), v12
++	vsoxseg6ei32.v v4, (a0), v12, v0.t
++
++	vloxseg7ei32.v v4, (a0), v12
++	vloxseg7ei32.v v4, 0(a0), v12
++	vloxseg7ei32.v v4, (a0), v12, v0.t
++	vsoxseg7ei32.v v4, (a0), v12
++	vsoxseg7ei32.v v4, 0(a0), v12
++	vsoxseg7ei32.v v4, (a0), v12, v0.t
++
++	vloxseg8ei32.v v4, (a0), v12
++	vloxseg8ei32.v v4, 0(a0), v12
++	vloxseg8ei32.v v4, (a0), v12, v0.t
++	vsoxseg8ei32.v v4, (a0), v12
++	vsoxseg8ei32.v v4, 0(a0), v12
++	vsoxseg8ei32.v v4, (a0), v12, v0.t
++
++	vloxseg2ei64.v v4, (a0), v12
++	vloxseg2ei64.v v4, 0(a0), v12
++	vloxseg2ei64.v v4, (a0), v12, v0.t
++	vsoxseg2ei64.v v4, (a0), v12
++	vsoxseg2ei64.v v4, 0(a0), v12
++	vsoxseg2ei64.v v4, (a0), v12, v0.t
++
++	vloxseg3ei64.v v4, (a0), v12
++	vloxseg3ei64.v v4, 0(a0), v12
++	vloxseg3ei64.v v4, (a0), v12, v0.t
++	vsoxseg3ei64.v v4, (a0), v12
++	vsoxseg3ei64.v v4, 0(a0), v12
++	vsoxseg3ei64.v v4, (a0), v12, v0.t
++
++	vloxseg4ei64.v v4, (a0), v12
++	vloxseg4ei64.v v4, 0(a0), v12
++	vloxseg4ei64.v v4, (a0), v12, v0.t
++	vsoxseg4ei64.v v4, (a0), v12
++	vsoxseg4ei64.v v4, 0(a0), v12
++	vsoxseg4ei64.v v4, (a0), v12, v0.t
++
++	vloxseg5ei64.v v4, (a0), v12
++	vloxseg5ei64.v v4, 0(a0), v12
++	vloxseg5ei64.v v4, (a0), v12, v0.t
++	vsoxseg5ei64.v v4, (a0), v12
++	vsoxseg5ei64.v v4, 0(a0), v12
++	vsoxseg5ei64.v v4, (a0), v12, v0.t
++
++	vloxseg6ei64.v v4, (a0), v12
++	vloxseg6ei64.v v4, 0(a0), v12
++	vloxseg6ei64.v v4, (a0), v12, v0.t
++	vsoxseg6ei64.v v4, (a0), v12
++	vsoxseg6ei64.v v4, 0(a0), v12
++	vsoxseg6ei64.v v4, (a0), v12, v0.t
++
++	vloxseg7ei64.v v4, (a0), v12
++	vloxseg7ei64.v v4, 0(a0), v12
++	vloxseg7ei64.v v4, (a0), v12, v0.t
++	vsoxseg7ei64.v v4, (a0), v12
++	vsoxseg7ei64.v v4, 0(a0), v12
++	vsoxseg7ei64.v v4, (a0), v12, v0.t
++
++	vloxseg8ei64.v v4, (a0), v12
++	vloxseg8ei64.v v4, 0(a0), v12
++	vloxseg8ei64.v v4, (a0), v12, v0.t
++	vsoxseg8ei64.v v4, (a0), v12
++	vsoxseg8ei64.v v4, 0(a0), v12
++	vsoxseg8ei64.v v4, (a0), v12, v0.t
++
++	vloxseg2ei128.v v4, (a0), v12
++	vloxseg2ei128.v v4, 0(a0), v12
++	vloxseg2ei128.v v4, (a0), v12, v0.t
++	vsoxseg2ei128.v v4, (a0), v12
++	vsoxseg2ei128.v v4, 0(a0), v12
++	vsoxseg2ei128.v v4, (a0), v12, v0.t
++
++	vloxseg3ei128.v v4, (a0), v12
++	vloxseg3ei128.v v4, 0(a0), v12
++	vloxseg3ei128.v v4, (a0), v12, v0.t
++	vsoxseg3ei128.v v4, (a0), v12
++	vsoxseg3ei128.v v4, 0(a0), v12
++	vsoxseg3ei128.v v4, (a0), v12, v0.t
++
++	vloxseg4ei128.v v4, (a0), v12
++	vloxseg4ei128.v v4, 0(a0), v12
++	vloxseg4ei128.v v4, (a0), v12, v0.t
++	vsoxseg4ei128.v v4, (a0), v12
++	vsoxseg4ei128.v v4, 0(a0), v12
++	vsoxseg4ei128.v v4, (a0), v12, v0.t
++
++	vloxseg5ei128.v v4, (a0), v12
++	vloxseg5ei128.v v4, 0(a0), v12
++	vloxseg5ei128.v v4, (a0), v12, v0.t
++	vsoxseg5ei128.v v4, (a0), v12
++	vsoxseg5ei128.v v4, 0(a0), v12
++	vsoxseg5ei128.v v4, (a0), v12, v0.t
++
++	vloxseg6ei128.v v4, (a0), v12
++	vloxseg6ei128.v v4, 0(a0), v12
++	vloxseg6ei128.v v4, (a0), v12, v0.t
++	vsoxseg6ei128.v v4, (a0), v12
++	vsoxseg6ei128.v v4, 0(a0), v12
++	vsoxseg6ei128.v v4, (a0), v12, v0.t
++
++	vloxseg7ei128.v v4, (a0), v12
++	vloxseg7ei128.v v4, 0(a0), v12
++	vloxseg7ei128.v v4, (a0), v12, v0.t
++	vsoxseg7ei128.v v4, (a0), v12
++	vsoxseg7ei128.v v4, 0(a0), v12
++	vsoxseg7ei128.v v4, (a0), v12, v0.t
++
++	vloxseg8ei128.v v4, (a0), v12
++	vloxseg8ei128.v v4, 0(a0), v12
++	vloxseg8ei128.v v4, (a0), v12, v0.t
++	vsoxseg8ei128.v v4, (a0), v12
++	vsoxseg8ei128.v v4, 0(a0), v12
++	vsoxseg8ei128.v v4, (a0), v12, v0.t
++
++	vloxseg2ei256.v v4, (a0), v12
++	vloxseg2ei256.v v4, 0(a0), v12
++	vloxseg2ei256.v v4, (a0), v12, v0.t
++	vsoxseg2ei256.v v4, (a0), v12
++	vsoxseg2ei256.v v4, 0(a0), v12
++	vsoxseg2ei256.v v4, (a0), v12, v0.t
++
++	vloxseg3ei256.v v4, (a0), v12
++	vloxseg3ei256.v v4, 0(a0), v12
++	vloxseg3ei256.v v4, (a0), v12, v0.t
++	vsoxseg3ei256.v v4, (a0), v12
++	vsoxseg3ei256.v v4, 0(a0), v12
++	vsoxseg3ei256.v v4, (a0), v12, v0.t
++
++	vloxseg4ei256.v v4, (a0), v12
++	vloxseg4ei256.v v4, 0(a0), v12
++	vloxseg4ei256.v v4, (a0), v12, v0.t
++	vsoxseg4ei256.v v4, (a0), v12
++	vsoxseg4ei256.v v4, 0(a0), v12
++	vsoxseg4ei256.v v4, (a0), v12, v0.t
++
++	vloxseg5ei256.v v4, (a0), v12
++	vloxseg5ei256.v v4, 0(a0), v12
++	vloxseg5ei256.v v4, (a0), v12, v0.t
++	vsoxseg5ei256.v v4, (a0), v12
++	vsoxseg5ei256.v v4, 0(a0), v12
++	vsoxseg5ei256.v v4, (a0), v12, v0.t
++
++	vloxseg6ei256.v v4, (a0), v12
++	vloxseg6ei256.v v4, 0(a0), v12
++	vloxseg6ei256.v v4, (a0), v12, v0.t
++	vsoxseg6ei256.v v4, (a0), v12
++	vsoxseg6ei256.v v4, 0(a0), v12
++	vsoxseg6ei256.v v4, (a0), v12, v0.t
++
++	vloxseg7ei256.v v4, (a0), v12
++	vloxseg7ei256.v v4, 0(a0), v12
++	vloxseg7ei256.v v4, (a0), v12, v0.t
++	vsoxseg7ei256.v v4, (a0), v12
++	vsoxseg7ei256.v v4, 0(a0), v12
++	vsoxseg7ei256.v v4, (a0), v12, v0.t
++
++	vloxseg8ei256.v v4, (a0), v12
++	vloxseg8ei256.v v4, 0(a0), v12
++	vloxseg8ei256.v v4, (a0), v12, v0.t
++	vsoxseg8ei256.v v4, (a0), v12
++	vsoxseg8ei256.v v4, 0(a0), v12
++	vsoxseg8ei256.v v4, (a0), v12, v0.t
++
++	vloxseg2ei512.v v4, (a0), v12
++	vloxseg2ei512.v v4, 0(a0), v12
++	vloxseg2ei512.v v4, (a0), v12, v0.t
++	vsoxseg2ei512.v v4, (a0), v12
++	vsoxseg2ei512.v v4, 0(a0), v12
++	vsoxseg2ei512.v v4, (a0), v12, v0.t
++
++	vloxseg3ei512.v v4, (a0), v12
++	vloxseg3ei512.v v4, 0(a0), v12
++	vloxseg3ei512.v v4, (a0), v12, v0.t
++	vsoxseg3ei512.v v4, (a0), v12
++	vsoxseg3ei512.v v4, 0(a0), v12
++	vsoxseg3ei512.v v4, (a0), v12, v0.t
++
++	vloxseg4ei512.v v4, (a0), v12
++	vloxseg4ei512.v v4, 0(a0), v12
++	vloxseg4ei512.v v4, (a0), v12, v0.t
++	vsoxseg4ei512.v v4, (a0), v12
++	vsoxseg4ei512.v v4, 0(a0), v12
++	vsoxseg4ei512.v v4, (a0), v12, v0.t
++
++	vloxseg5ei512.v v4, (a0), v12
++	vloxseg5ei512.v v4, 0(a0), v12
++	vloxseg5ei512.v v4, (a0), v12, v0.t
++	vsoxseg5ei512.v v4, (a0), v12
++	vsoxseg5ei512.v v4, 0(a0), v12
++	vsoxseg5ei512.v v4, (a0), v12, v0.t
++
++	vloxseg6ei512.v v4, (a0), v12
++	vloxseg6ei512.v v4, 0(a0), v12
++	vloxseg6ei512.v v4, (a0), v12, v0.t
++	vsoxseg6ei512.v v4, (a0), v12
++	vsoxseg6ei512.v v4, 0(a0), v12
++	vsoxseg6ei512.v v4, (a0), v12, v0.t
++
++	vloxseg7ei512.v v4, (a0), v12
++	vloxseg7ei512.v v4, 0(a0), v12
++	vloxseg7ei512.v v4, (a0), v12, v0.t
++	vsoxseg7ei512.v v4, (a0), v12
++	vsoxseg7ei512.v v4, 0(a0), v12
++	vsoxseg7ei512.v v4, (a0), v12, v0.t
++
++	vloxseg8ei512.v v4, (a0), v12
++	vloxseg8ei512.v v4, 0(a0), v12
++	vloxseg8ei512.v v4, (a0), v12, v0.t
++	vsoxseg8ei512.v v4, (a0), v12
++	vsoxseg8ei512.v v4, 0(a0), v12
++	vsoxseg8ei512.v v4, (a0), v12, v0.t
++
++	vloxseg2ei1024.v v4, (a0), v12
++	vloxseg2ei1024.v v4, 0(a0), v12
++	vloxseg2ei1024.v v4, (a0), v12, v0.t
++	vsoxseg2ei1024.v v4, (a0), v12
++	vsoxseg2ei1024.v v4, 0(a0), v12
++	vsoxseg2ei1024.v v4, (a0), v12, v0.t
++
++	vloxseg3ei1024.v v4, (a0), v12
++	vloxseg3ei1024.v v4, 0(a0), v12
++	vloxseg3ei1024.v v4, (a0), v12, v0.t
++	vsoxseg3ei1024.v v4, (a0), v12
++	vsoxseg3ei1024.v v4, 0(a0), v12
++	vsoxseg3ei1024.v v4, (a0), v12, v0.t
++
++	vloxseg4ei1024.v v4, (a0), v12
++	vloxseg4ei1024.v v4, 0(a0), v12
++	vloxseg4ei1024.v v4, (a0), v12, v0.t
++	vsoxseg4ei1024.v v4, (a0), v12
++	vsoxseg4ei1024.v v4, 0(a0), v12
++	vsoxseg4ei1024.v v4, (a0), v12, v0.t
++
++	vloxseg5ei1024.v v4, (a0), v12
++	vloxseg5ei1024.v v4, 0(a0), v12
++	vloxseg5ei1024.v v4, (a0), v12, v0.t
++	vsoxseg5ei1024.v v4, (a0), v12
++	vsoxseg5ei1024.v v4, 0(a0), v12
++	vsoxseg5ei1024.v v4, (a0), v12, v0.t
++
++	vloxseg6ei1024.v v4, (a0), v12
++	vloxseg6ei1024.v v4, 0(a0), v12
++	vloxseg6ei1024.v v4, (a0), v12, v0.t
++	vsoxseg6ei1024.v v4, (a0), v12
++	vsoxseg6ei1024.v v4, 0(a0), v12
++	vsoxseg6ei1024.v v4, (a0), v12, v0.t
++
++	vloxseg7ei1024.v v4, (a0), v12
++	vloxseg7ei1024.v v4, 0(a0), v12
++	vloxseg7ei1024.v v4, (a0), v12, v0.t
++	vsoxseg7ei1024.v v4, (a0), v12
++	vsoxseg7ei1024.v v4, 0(a0), v12
++	vsoxseg7ei1024.v v4, (a0), v12, v0.t
++
++	vloxseg8ei1024.v v4, (a0), v12
++	vloxseg8ei1024.v v4, 0(a0), v12
++	vloxseg8ei1024.v v4, (a0), v12, v0.t
++	vsoxseg8ei1024.v v4, (a0), v12
++	vsoxseg8ei1024.v v4, 0(a0), v12
++	vsoxseg8ei1024.v v4, (a0), v12, v0.t
++
++	vluxseg2ei8.v v4, (a0), v12
++	vluxseg2ei8.v v4, 0(a0), v12
++	vluxseg2ei8.v v4, (a0), v12, v0.t
++	vsuxseg2ei8.v v4, (a0), v12
++	vsuxseg2ei8.v v4, 0(a0), v12
++	vsuxseg2ei8.v v4, (a0), v12, v0.t
++
++	vluxseg3ei8.v v4, (a0), v12
++	vluxseg3ei8.v v4, 0(a0), v12
++	vluxseg3ei8.v v4, (a0), v12, v0.t
++	vsuxseg3ei8.v v4, (a0), v12
++	vsuxseg3ei8.v v4, 0(a0), v12
++	vsuxseg3ei8.v v4, (a0), v12, v0.t
++
++	vluxseg4ei8.v v4, (a0), v12
++	vluxseg4ei8.v v4, 0(a0), v12
++	vluxseg4ei8.v v4, (a0), v12, v0.t
++	vsuxseg4ei8.v v4, (a0), v12
++	vsuxseg4ei8.v v4, 0(a0), v12
++	vsuxseg4ei8.v v4, (a0), v12, v0.t
++
++	vluxseg5ei8.v v4, (a0), v12
++	vluxseg5ei8.v v4, 0(a0), v12
++	vluxseg5ei8.v v4, (a0), v12, v0.t
++	vsuxseg5ei8.v v4, (a0), v12
++	vsuxseg5ei8.v v4, 0(a0), v12
++	vsuxseg5ei8.v v4, (a0), v12, v0.t
++
++	vluxseg6ei8.v v4, (a0), v12
++	vluxseg6ei8.v v4, 0(a0), v12
++	vluxseg6ei8.v v4, (a0), v12, v0.t
++	vsuxseg6ei8.v v4, (a0), v12
++	vsuxseg6ei8.v v4, 0(a0), v12
++	vsuxseg6ei8.v v4, (a0), v12, v0.t
++
++	vluxseg7ei8.v v4, (a0), v12
++	vluxseg7ei8.v v4, 0(a0), v12
++	vluxseg7ei8.v v4, (a0), v12, v0.t
++	vsuxseg7ei8.v v4, (a0), v12
++	vsuxseg7ei8.v v4, 0(a0), v12
++	vsuxseg7ei8.v v4, (a0), v12, v0.t
++
++	vluxseg8ei8.v v4, (a0), v12
++	vluxseg8ei8.v v4, 0(a0), v12
++	vluxseg8ei8.v v4, (a0), v12, v0.t
++	vsuxseg8ei8.v v4, (a0), v12
++	vsuxseg8ei8.v v4, 0(a0), v12
++	vsuxseg8ei8.v v4, (a0), v12, v0.t
++
++	vluxseg2ei16.v v4, (a0), v12
++	vluxseg2ei16.v v4, 0(a0), v12
++	vluxseg2ei16.v v4, (a0), v12, v0.t
++	vsuxseg2ei16.v v4, (a0), v12
++	vsuxseg2ei16.v v4, 0(a0), v12
++	vsuxseg2ei16.v v4, (a0), v12, v0.t
++
++	vluxseg3ei16.v v4, (a0), v12
++	vluxseg3ei16.v v4, 0(a0), v12
++	vluxseg3ei16.v v4, (a0), v12, v0.t
++	vsuxseg3ei16.v v4, (a0), v12
++	vsuxseg3ei16.v v4, 0(a0), v12
++	vsuxseg3ei16.v v4, (a0), v12, v0.t
++
++	vluxseg4ei16.v v4, (a0), v12
++	vluxseg4ei16.v v4, 0(a0), v12
++	vluxseg4ei16.v v4, (a0), v12, v0.t
++	vsuxseg4ei16.v v4, (a0), v12
++	vsuxseg4ei16.v v4, 0(a0), v12
++	vsuxseg4ei16.v v4, (a0), v12, v0.t
++
++	vluxseg5ei16.v v4, (a0), v12
++	vluxseg5ei16.v v4, 0(a0), v12
++	vluxseg5ei16.v v4, (a0), v12, v0.t
++	vsuxseg5ei16.v v4, (a0), v12
++	vsuxseg5ei16.v v4, 0(a0), v12
++	vsuxseg5ei16.v v4, (a0), v12, v0.t
++
++	vluxseg6ei16.v v4, (a0), v12
++	vluxseg6ei16.v v4, 0(a0), v12
++	vluxseg6ei16.v v4, (a0), v12, v0.t
++	vsuxseg6ei16.v v4, (a0), v12
++	vsuxseg6ei16.v v4, 0(a0), v12
++	vsuxseg6ei16.v v4, (a0), v12, v0.t
++
++	vluxseg7ei16.v v4, (a0), v12
++	vluxseg7ei16.v v4, 0(a0), v12
++	vluxseg7ei16.v v4, (a0), v12, v0.t
++	vsuxseg7ei16.v v4, (a0), v12
++	vsuxseg7ei16.v v4, 0(a0), v12
++	vsuxseg7ei16.v v4, (a0), v12, v0.t
++
++	vluxseg8ei16.v v4, (a0), v12
++	vluxseg8ei16.v v4, 0(a0), v12
++	vluxseg8ei16.v v4, (a0), v12, v0.t
++	vsuxseg8ei16.v v4, (a0), v12
++	vsuxseg8ei16.v v4, 0(a0), v12
++	vsuxseg8ei16.v v4, (a0), v12, v0.t
++
++	vluxseg2ei32.v v4, (a0), v12
++	vluxseg2ei32.v v4, 0(a0), v12
++	vluxseg2ei32.v v4, (a0), v12, v0.t
++	vsuxseg2ei32.v v4, (a0), v12
++	vsuxseg2ei32.v v4, 0(a0), v12
++	vsuxseg2ei32.v v4, (a0), v12, v0.t
++
++	vluxseg3ei32.v v4, (a0), v12
++	vluxseg3ei32.v v4, 0(a0), v12
++	vluxseg3ei32.v v4, (a0), v12, v0.t
++	vsuxseg3ei32.v v4, (a0), v12
++	vsuxseg3ei32.v v4, 0(a0), v12
++	vsuxseg3ei32.v v4, (a0), v12, v0.t
++
++	vluxseg4ei32.v v4, (a0), v12
++	vluxseg4ei32.v v4, 0(a0), v12
++	vluxseg4ei32.v v4, (a0), v12, v0.t
++	vsuxseg4ei32.v v4, (a0), v12
++	vsuxseg4ei32.v v4, 0(a0), v12
++	vsuxseg4ei32.v v4, (a0), v12, v0.t
++
++	vluxseg5ei32.v v4, (a0), v12
++	vluxseg5ei32.v v4, 0(a0), v12
++	vluxseg5ei32.v v4, (a0), v12, v0.t
++	vsuxseg5ei32.v v4, (a0), v12
++	vsuxseg5ei32.v v4, 0(a0), v12
++	vsuxseg5ei32.v v4, (a0), v12, v0.t
++
++	vluxseg6ei32.v v4, (a0), v12
++	vluxseg6ei32.v v4, 0(a0), v12
++	vluxseg6ei32.v v4, (a0), v12, v0.t
++	vsuxseg6ei32.v v4, (a0), v12
++	vsuxseg6ei32.v v4, 0(a0), v12
++	vsuxseg6ei32.v v4, (a0), v12, v0.t
++
++	vluxseg7ei32.v v4, (a0), v12
++	vluxseg7ei32.v v4, 0(a0), v12
++	vluxseg7ei32.v v4, (a0), v12, v0.t
++	vsuxseg7ei32.v v4, (a0), v12
++	vsuxseg7ei32.v v4, 0(a0), v12
++	vsuxseg7ei32.v v4, (a0), v12, v0.t
++
++	vluxseg8ei32.v v4, (a0), v12
++	vluxseg8ei32.v v4, 0(a0), v12
++	vluxseg8ei32.v v4, (a0), v12, v0.t
++	vsuxseg8ei32.v v4, (a0), v12
++	vsuxseg8ei32.v v4, 0(a0), v12
++	vsuxseg8ei32.v v4, (a0), v12, v0.t
++
++	vluxseg2ei64.v v4, (a0), v12
++	vluxseg2ei64.v v4, 0(a0), v12
++	vluxseg2ei64.v v4, (a0), v12, v0.t
++	vsuxseg2ei64.v v4, (a0), v12
++	vsuxseg2ei64.v v4, 0(a0), v12
++	vsuxseg2ei64.v v4, (a0), v12, v0.t
++
++	vluxseg3ei64.v v4, (a0), v12
++	vluxseg3ei64.v v4, 0(a0), v12
++	vluxseg3ei64.v v4, (a0), v12, v0.t
++	vsuxseg3ei64.v v4, (a0), v12
++	vsuxseg3ei64.v v4, 0(a0), v12
++	vsuxseg3ei64.v v4, (a0), v12, v0.t
++
++	vluxseg4ei64.v v4, (a0), v12
++	vluxseg4ei64.v v4, 0(a0), v12
++	vluxseg4ei64.v v4, (a0), v12, v0.t
++	vsuxseg4ei64.v v4, (a0), v12
++	vsuxseg4ei64.v v4, 0(a0), v12
++	vsuxseg4ei64.v v4, (a0), v12, v0.t
++
++	vluxseg5ei64.v v4, (a0), v12
++	vluxseg5ei64.v v4, 0(a0), v12
++	vluxseg5ei64.v v4, (a0), v12, v0.t
++	vsuxseg5ei64.v v4, (a0), v12
++	vsuxseg5ei64.v v4, 0(a0), v12
++	vsuxseg5ei64.v v4, (a0), v12, v0.t
++
++	vluxseg6ei64.v v4, (a0), v12
++	vluxseg6ei64.v v4, 0(a0), v12
++	vluxseg6ei64.v v4, (a0), v12, v0.t
++	vsuxseg6ei64.v v4, (a0), v12
++	vsuxseg6ei64.v v4, 0(a0), v12
++	vsuxseg6ei64.v v4, (a0), v12, v0.t
++
++	vluxseg7ei64.v v4, (a0), v12
++	vluxseg7ei64.v v4, 0(a0), v12
++	vluxseg7ei64.v v4, (a0), v12, v0.t
++	vsuxseg7ei64.v v4, (a0), v12
++	vsuxseg7ei64.v v4, 0(a0), v12
++	vsuxseg7ei64.v v4, (a0), v12, v0.t
++
++	vluxseg8ei64.v v4, (a0), v12
++	vluxseg8ei64.v v4, 0(a0), v12
++	vluxseg8ei64.v v4, (a0), v12, v0.t
++	vsuxseg8ei64.v v4, (a0), v12
++	vsuxseg8ei64.v v4, 0(a0), v12
++	vsuxseg8ei64.v v4, (a0), v12, v0.t
++
++	vluxseg2ei128.v v4, (a0), v12
++	vluxseg2ei128.v v4, 0(a0), v12
++	vluxseg2ei128.v v4, (a0), v12, v0.t
++	vsuxseg2ei128.v v4, (a0), v12
++	vsuxseg2ei128.v v4, 0(a0), v12
++	vsuxseg2ei128.v v4, (a0), v12, v0.t
++
++	vluxseg3ei128.v v4, (a0), v12
++	vluxseg3ei128.v v4, 0(a0), v12
++	vluxseg3ei128.v v4, (a0), v12, v0.t
++	vsuxseg3ei128.v v4, (a0), v12
++	vsuxseg3ei128.v v4, 0(a0), v12
++	vsuxseg3ei128.v v4, (a0), v12, v0.t
++
++	vluxseg4ei128.v v4, (a0), v12
++	vluxseg4ei128.v v4, 0(a0), v12
++	vluxseg4ei128.v v4, (a0), v12, v0.t
++	vsuxseg4ei128.v v4, (a0), v12
++	vsuxseg4ei128.v v4, 0(a0), v12
++	vsuxseg4ei128.v v4, (a0), v12, v0.t
++
++	vluxseg5ei128.v v4, (a0), v12
++	vluxseg5ei128.v v4, 0(a0), v12
++	vluxseg5ei128.v v4, (a0), v12, v0.t
++	vsuxseg5ei128.v v4, (a0), v12
++	vsuxseg5ei128.v v4, 0(a0), v12
++	vsuxseg5ei128.v v4, (a0), v12, v0.t
++
++	vluxseg6ei128.v v4, (a0), v12
++	vluxseg6ei128.v v4, 0(a0), v12
++	vluxseg6ei128.v v4, (a0), v12, v0.t
++	vsuxseg6ei128.v v4, (a0), v12
++	vsuxseg6ei128.v v4, 0(a0), v12
++	vsuxseg6ei128.v v4, (a0), v12, v0.t
++
++	vluxseg7ei128.v v4, (a0), v12
++	vluxseg7ei128.v v4, 0(a0), v12
++	vluxseg7ei128.v v4, (a0), v12, v0.t
++	vsuxseg7ei128.v v4, (a0), v12
++	vsuxseg7ei128.v v4, 0(a0), v12
++	vsuxseg7ei128.v v4, (a0), v12, v0.t
++
++	vluxseg8ei128.v v4, (a0), v12
++	vluxseg8ei128.v v4, 0(a0), v12
++	vluxseg8ei128.v v4, (a0), v12, v0.t
++	vsuxseg8ei128.v v4, (a0), v12
++	vsuxseg8ei128.v v4, 0(a0), v12
++	vsuxseg8ei128.v v4, (a0), v12, v0.t
++
++	vluxseg2ei256.v v4, (a0), v12
++	vluxseg2ei256.v v4, 0(a0), v12
++	vluxseg2ei256.v v4, (a0), v12, v0.t
++	vsuxseg2ei256.v v4, (a0), v12
++	vsuxseg2ei256.v v4, 0(a0), v12
++	vsuxseg2ei256.v v4, (a0), v12, v0.t
++
++	vluxseg3ei256.v v4, (a0), v12
++	vluxseg3ei256.v v4, 0(a0), v12
++	vluxseg3ei256.v v4, (a0), v12, v0.t
++	vsuxseg3ei256.v v4, (a0), v12
++	vsuxseg3ei256.v v4, 0(a0), v12
++	vsuxseg3ei256.v v4, (a0), v12, v0.t
++
++	vluxseg4ei256.v v4, (a0), v12
++	vluxseg4ei256.v v4, 0(a0), v12
++	vluxseg4ei256.v v4, (a0), v12, v0.t
++	vsuxseg4ei256.v v4, (a0), v12
++	vsuxseg4ei256.v v4, 0(a0), v12
++	vsuxseg4ei256.v v4, (a0), v12, v0.t
++
++	vluxseg5ei256.v v4, (a0), v12
++	vluxseg5ei256.v v4, 0(a0), v12
++	vluxseg5ei256.v v4, (a0), v12, v0.t
++	vsuxseg5ei256.v v4, (a0), v12
++	vsuxseg5ei256.v v4, 0(a0), v12
++	vsuxseg5ei256.v v4, (a0), v12, v0.t
++
++	vluxseg6ei256.v v4, (a0), v12
++	vluxseg6ei256.v v4, 0(a0), v12
++	vluxseg6ei256.v v4, (a0), v12, v0.t
++	vsuxseg6ei256.v v4, (a0), v12
++	vsuxseg6ei256.v v4, 0(a0), v12
++	vsuxseg6ei256.v v4, (a0), v12, v0.t
++
++	vluxseg7ei256.v v4, (a0), v12
++	vluxseg7ei256.v v4, 0(a0), v12
++	vluxseg7ei256.v v4, (a0), v12, v0.t
++	vsuxseg7ei256.v v4, (a0), v12
++	vsuxseg7ei256.v v4, 0(a0), v12
++	vsuxseg7ei256.v v4, (a0), v12, v0.t
++
++	vluxseg8ei256.v v4, (a0), v12
++	vluxseg8ei256.v v4, 0(a0), v12
++	vluxseg8ei256.v v4, (a0), v12, v0.t
++	vsuxseg8ei256.v v4, (a0), v12
++	vsuxseg8ei256.v v4, 0(a0), v12
++	vsuxseg8ei256.v v4, (a0), v12, v0.t
++
++	vluxseg2ei512.v v4, (a0), v12
++	vluxseg2ei512.v v4, 0(a0), v12
++	vluxseg2ei512.v v4, (a0), v12, v0.t
++	vsuxseg2ei512.v v4, (a0), v12
++	vsuxseg2ei512.v v4, 0(a0), v12
++	vsuxseg2ei512.v v4, (a0), v12, v0.t
++
++	vluxseg3ei512.v v4, (a0), v12
++	vluxseg3ei512.v v4, 0(a0), v12
++	vluxseg3ei512.v v4, (a0), v12, v0.t
++	vsuxseg3ei512.v v4, (a0), v12
++	vsuxseg3ei512.v v4, 0(a0), v12
++	vsuxseg3ei512.v v4, (a0), v12, v0.t
++
++	vluxseg4ei512.v v4, (a0), v12
++	vluxseg4ei512.v v4, 0(a0), v12
++	vluxseg4ei512.v v4, (a0), v12, v0.t
++	vsuxseg4ei512.v v4, (a0), v12
++	vsuxseg4ei512.v v4, 0(a0), v12
++	vsuxseg4ei512.v v4, (a0), v12, v0.t
++
++	vluxseg5ei512.v v4, (a0), v12
++	vluxseg5ei512.v v4, 0(a0), v12
++	vluxseg5ei512.v v4, (a0), v12, v0.t
++	vsuxseg5ei512.v v4, (a0), v12
++	vsuxseg5ei512.v v4, 0(a0), v12
++	vsuxseg5ei512.v v4, (a0), v12, v0.t
++
++	vluxseg6ei512.v v4, (a0), v12
++	vluxseg6ei512.v v4, 0(a0), v12
++	vluxseg6ei512.v v4, (a0), v12, v0.t
++	vsuxseg6ei512.v v4, (a0), v12
++	vsuxseg6ei512.v v4, 0(a0), v12
++	vsuxseg6ei512.v v4, (a0), v12, v0.t
++
++	vluxseg7ei512.v v4, (a0), v12
++	vluxseg7ei512.v v4, 0(a0), v12
++	vluxseg7ei512.v v4, (a0), v12, v0.t
++	vsuxseg7ei512.v v4, (a0), v12
++	vsuxseg7ei512.v v4, 0(a0), v12
++	vsuxseg7ei512.v v4, (a0), v12, v0.t
++
++	vluxseg8ei512.v v4, (a0), v12
++	vluxseg8ei512.v v4, 0(a0), v12
++	vluxseg8ei512.v v4, (a0), v12, v0.t
++	vsuxseg8ei512.v v4, (a0), v12
++	vsuxseg8ei512.v v4, 0(a0), v12
++	vsuxseg8ei512.v v4, (a0), v12, v0.t
++
++	vluxseg2ei1024.v v4, (a0), v12
++	vluxseg2ei1024.v v4, 0(a0), v12
++	vluxseg2ei1024.v v4, (a0), v12, v0.t
++	vsuxseg2ei1024.v v4, (a0), v12
++	vsuxseg2ei1024.v v4, 0(a0), v12
++	vsuxseg2ei1024.v v4, (a0), v12, v0.t
++
++	vluxseg3ei1024.v v4, (a0), v12
++	vluxseg3ei1024.v v4, 0(a0), v12
++	vluxseg3ei1024.v v4, (a0), v12, v0.t
++	vsuxseg3ei1024.v v4, (a0), v12
++	vsuxseg3ei1024.v v4, 0(a0), v12
++	vsuxseg3ei1024.v v4, (a0), v12, v0.t
++
++	vluxseg4ei1024.v v4, (a0), v12
++	vluxseg4ei1024.v v4, 0(a0), v12
++	vluxseg4ei1024.v v4, (a0), v12, v0.t
++	vsuxseg4ei1024.v v4, (a0), v12
++	vsuxseg4ei1024.v v4, 0(a0), v12
++	vsuxseg4ei1024.v v4, (a0), v12, v0.t
++
++	vluxseg5ei1024.v v4, (a0), v12
++	vluxseg5ei1024.v v4, 0(a0), v12
++	vluxseg5ei1024.v v4, (a0), v12, v0.t
++	vsuxseg5ei1024.v v4, (a0), v12
++	vsuxseg5ei1024.v v4, 0(a0), v12
++	vsuxseg5ei1024.v v4, (a0), v12, v0.t
++
++	vluxseg6ei1024.v v4, (a0), v12
++	vluxseg6ei1024.v v4, 0(a0), v12
++	vluxseg6ei1024.v v4, (a0), v12, v0.t
++	vsuxseg6ei1024.v v4, (a0), v12
++	vsuxseg6ei1024.v v4, 0(a0), v12
++	vsuxseg6ei1024.v v4, (a0), v12, v0.t
++
++	vluxseg7ei1024.v v4, (a0), v12
++	vluxseg7ei1024.v v4, 0(a0), v12
++	vluxseg7ei1024.v v4, (a0), v12, v0.t
++	vsuxseg7ei1024.v v4, (a0), v12
++	vsuxseg7ei1024.v v4, 0(a0), v12
++	vsuxseg7ei1024.v v4, (a0), v12, v0.t
++
++	vluxseg8ei1024.v v4, (a0), v12
++	vluxseg8ei1024.v v4, 0(a0), v12
++	vluxseg8ei1024.v v4, (a0), v12, v0.t
++	vsuxseg8ei1024.v v4, (a0), v12
++	vsuxseg8ei1024.v v4, 0(a0), v12
++	vsuxseg8ei1024.v v4, (a0), v12, v0.t
+ 
+ 	vlseg2e8ff.v v4, (a0)
+ 	vlseg2e8ff.v v4, 0(a0)
+diff --git a/include/opcode/riscv-opc.h b/include/opcode/riscv-opc.h
+index 743060ca18..d74d3d5044 100644
+--- a/include/opcode/riscv-opc.h
++++ b/include/opcode/riscv-opc.h
+@@ -630,16 +630,16 @@
+ 
+ /* Temporary Load/store encoding info
+ MOP load
+-00 unit-stride	VLE<EEW>, VLE<EEW>FF, VL<nf>RE<EEW> (nf = 1, 2, 4, 8)
+-01 reserved
+-10 strided	VLSE<EEW>
+-11 indexed	VLXEI<EEW>
++00 unit-stride		LE<EEW>, VLE<EEW>FF, VL<nf>RE<EEW> (nf = 1, 2, 4, 8)
++01 indexed-unordered	VLUXEI<EEW>
++10 strided		VLSE<EEW>
++11 indexed-ordered	VLOXEI<EEW>
+ 
+ MOP store
+ 00 unit-stride		VSE<EEW>, VS<nf>R (nf = 1, 2, 4, 8)
+ 01 indexed-unordered	VSUXEI<EEW>
+ 10 strided		VSSE<EEW>
+-11 indexed-ordered	VSXEI<EEW>
++11 indexed-ordered	VSOXEI<EEW>
+ 
+ VM 0 masked
+ VM 1 unmasked
+@@ -680,8 +680,9 @@ NF MEW MOP VM LUMOP/RS2 RS1 WIDTH VD opcode
+ 000 - 00 x 00000 xxxxx --- xxxxx 0100111 VSE<EEW>
+ 000 - 10 x xxxxx xxxxx --- xxxxx 0000111 VLSE<EEW>
+ 000 - 10 x xxxxx xxxxx --- xxxxx 0100111 VSSE<EEW>
+-000 0 11 x xxxxx xxxxx --- xxxxx 0000111 VLXE<EEW>I
+-000 0 11 x xxxxx xxxxx --- xxxxx 0100111 VSXE<EEW>I
++000 0 11 x xxxxx xxxxx --- xxxxx 0000111 VLOXE<EEW>I
++000 0 11 x xxxxx xxxxx --- xxxxx 0100111 VSOXE<EEW>I
++000 0 01 x xxxxx xxxxx --- xxxxx 0000111 VLUXE<EEW>I
+ 000 0 01 x xxxxx xxxxx --- xxxxx 0100111 VSUXE<EEW>I
+ 000 - 00 x 10000 xxxxx --- xxxxx 0000111 VLE<EEW>FF
+ xxx - 00 1 01000 xxxxx --- xxxxx 0000111 VL<nf>RE<EEW>, nf = 1,2,4,8
+@@ -691,8 +692,10 @@ xxx - 00 x 00000 xxxxx --- xxxxx 0000111 VLSEG<nf>E<EEW>
+ xxx - 00 x 00000 xxxxx --- xxxxx 0100111 VSSEG<nf>E<EEW>
+ xxx - 10 x 00000 xxxxx --- xxxxx 0000111 VLSSEG<nf>E<EEW>
+ xxx - 10 x 00000 xxxxx --- xxxxx 0100111 VSSSEG<nf>E<EEW>
+-xxx - 11 x 00000 xxxxx --- xxxxx 0000111 VLXSEG<nf>E<EEW>I
+-xxx - 11 x 00000 xxxxx --- xxxxx 0100111 VSXSEG<nf>E<EEW>I
++xxx - 11 x 00000 xxxxx --- xxxxx 0000111 VLOXSEG<nf>E<EEW>I
++xxx - 11 x 00000 xxxxx --- xxxxx 0100111 VSOXSEG<nf>E<EEW>I
++xxx - 01 x 00000 xxxxx --- xxxxx 0000111 VLUXSEG<nf>E<EEW>I
++xxx - 01 x 00000 xxxxx --- xxxxx 0100111 VSUXSEG<nf>E<EEW>I
+ xxx - 00 x 10000 xxxxx --- xxxxx 0000111 VLSEG<nf>E<EEW>FF
+ */
+ 
+@@ -764,23 +767,32 @@ xxx - 00 x 10000 xxxxx --- xxxxx 0000111 VLSEG<nf>E<EEW>FF
+ #define MATCH_VSSE1024V 0x18007027
+ #define MASK_VSSE1024V  0xfc00707f
+ 
+-#define MATCH_VLXEI8V    0x0c000007
+-#define MASK_VLXEI8V     0xfc00707f
+-#define MATCH_VLXEI16V   0x0c005007
+-#define MASK_VLXEI16V    0xfc00707f
+-#define MATCH_VLXEI32V   0x0c006007
+-#define MASK_VLXEI32V    0xfc00707f
+-#define MATCH_VLXEI64V   0x0c007007
+-#define MASK_VLXEI64V    0xfc00707f
+-
+-#define MATCH_VSXEI8V    0x0c000027
+-#define MASK_VSXEI8V     0xfc00707f
+-#define MATCH_VSXEI16V   0x0c005027
+-#define MASK_VSXEI16V    0xfc00707f
+-#define MATCH_VSXEI32V   0x0c006027
+-#define MASK_VSXEI32V    0xfc00707f
+-#define MATCH_VSXEI64V   0x0c007027
+-#define MASK_VSXEI64V    0xfc00707f
++#define MATCH_VLOXEI8V    0x0c000007
++#define MASK_VLOXEI8V     0xfc00707f
++#define MATCH_VLOXEI16V   0x0c005007
++#define MASK_VLOXEI16V    0xfc00707f
++#define MATCH_VLOXEI32V   0x0c006007
++#define MASK_VLOXEI32V    0xfc00707f
++#define MATCH_VLOXEI64V   0x0c007007
++#define MASK_VLOXEI64V    0xfc00707f
++
++#define MATCH_VSOXEI8V    0x0c000027
++#define MASK_VSOXEI8V     0xfc00707f
++#define MATCH_VSOXEI16V   0x0c005027
++#define MASK_VSOXEI16V    0xfc00707f
++#define MATCH_VSOXEI32V   0x0c006027
++#define MASK_VSOXEI32V    0xfc00707f
++#define MATCH_VSOXEI64V   0x0c007027
++#define MASK_VSOXEI64V    0xfc00707f
++
++#define MATCH_VLUXEI8V    0x04000007
++#define MASK_VLUXEI8V     0xfc00707f
++#define MATCH_VLUXEI16V   0x04005007
++#define MASK_VLUXEI16V    0xfc00707f
++#define MATCH_VLUXEI32V   0x04006007
++#define MASK_VLUXEI32V    0xfc00707f
++#define MATCH_VLUXEI64V   0x04007007
++#define MASK_VLUXEI64V    0xfc00707f
+ 
+ #define MATCH_VSUXEI8V    0x04000027
+ #define MASK_VSUXEI8V     0xfc00707f
+@@ -1272,237 +1284,469 @@ xxx - 00 x 10000 xxxxx --- xxxxx 0000111 VLSEG<nf>E<EEW>FF
+ #define MATCH_VSSSEG8E1024V  0xf8007027
+ #define MASK_VSSSEG8E1024V   0xfc00707f
+ 
+-#define MATCH_VLXSEG2EI8V  0x2c000007
+-#define MASK_VLXSEG2EI8V   0xfc00707f
+-#define MATCH_VSXSEG2EI8V  0x2c000027
+-#define MASK_VSXSEG2EI8V   0xfc00707f
+-#define MATCH_VLXSEG3EI8V  0x4c000007
+-#define MASK_VLXSEG3EI8V   0xfc00707f
+-#define MATCH_VSXSEG3EI8V  0x4c000027
+-#define MASK_VSXSEG3EI8V   0xfc00707f
+-#define MATCH_VLXSEG4EI8V  0x6c000007
+-#define MASK_VLXSEG4EI8V   0xfc00707f
+-#define MATCH_VSXSEG4EI8V  0x6c000027
+-#define MASK_VSXSEG4EI8V   0xfc00707f
+-#define MATCH_VLXSEG5EI8V  0x8c000007
+-#define MASK_VLXSEG5EI8V   0xfc00707f
+-#define MATCH_VSXSEG5EI8V  0x8c000027
+-#define MASK_VSXSEG5EI8V   0xfc00707f
+-#define MATCH_VLXSEG6EI8V  0xac000007
+-#define MASK_VLXSEG6EI8V   0xfc00707f
+-#define MATCH_VSXSEG6EI8V  0xac000027
+-#define MASK_VSXSEG6EI8V   0xfc00707f
+-#define MATCH_VLXSEG7EI8V  0xcc000007
+-#define MASK_VLXSEG7EI8V   0xfc00707f
+-#define MATCH_VSXSEG7EI8V  0xcc000027
+-#define MASK_VSXSEG7EI8V   0xfc00707f
+-#define MATCH_VLXSEG8EI8V  0xec000007
+-#define MASK_VLXSEG8EI8V   0xfc00707f
+-#define MATCH_VSXSEG8EI8V  0xec000027
+-#define MASK_VSXSEG8EI8V   0xfc00707f
+-
+-#define MATCH_VLXSEG2EI16V  0x2c005007
+-#define MASK_VLXSEG2EI16V   0xfc00707f
+-#define MATCH_VSXSEG2EI16V  0x2c005027
+-#define MASK_VSXSEG2EI16V   0xfc00707f
+-#define MATCH_VLXSEG3EI16V  0x4c005007
+-#define MASK_VLXSEG3EI16V   0xfc00707f
+-#define MATCH_VSXSEG3EI16V  0x4c005027
+-#define MASK_VSXSEG3EI16V   0xfc00707f
+-#define MATCH_VLXSEG4EI16V  0x6c005007
+-#define MASK_VLXSEG4EI16V   0xfc00707f
+-#define MATCH_VSXSEG4EI16V  0x6c005027
+-#define MASK_VSXSEG4EI16V   0xfc00707f
+-#define MATCH_VLXSEG5EI16V  0x8c005007
+-#define MASK_VLXSEG5EI16V   0xfc00707f
+-#define MATCH_VSXSEG5EI16V  0x8c005027
+-#define MASK_VSXSEG5EI16V   0xfc00707f
+-#define MATCH_VLXSEG6EI16V  0xac005007
+-#define MASK_VLXSEG6EI16V   0xfc00707f
+-#define MATCH_VSXSEG6EI16V  0xac005027
+-#define MASK_VSXSEG6EI16V   0xfc00707f
+-#define MATCH_VLXSEG7EI16V  0xcc005007
+-#define MASK_VLXSEG7EI16V   0xfc00707f
+-#define MATCH_VSXSEG7EI16V  0xcc005027
+-#define MASK_VSXSEG7EI16V   0xfc00707f
+-#define MATCH_VLXSEG8EI16V  0xec005007
+-#define MASK_VLXSEG8EI16V   0xfc00707f
+-#define MATCH_VSXSEG8EI16V  0xec005027
+-#define MASK_VSXSEG8EI16V   0xfc00707f
+-
+-#define MATCH_VLXSEG2EI32V  0x2c006007
+-#define MASK_VLXSEG2EI32V   0xfc00707f
+-#define MATCH_VSXSEG2EI32V  0x2c006027
+-#define MASK_VSXSEG2EI32V   0xfc00707f
+-#define MATCH_VLXSEG3EI32V  0x4c006007
+-#define MASK_VLXSEG3EI32V   0xfc00707f
+-#define MATCH_VSXSEG3EI32V  0x4c006027
+-#define MASK_VSXSEG3EI32V   0xfc00707f
+-#define MATCH_VLXSEG4EI32V  0x6c006007
+-#define MASK_VLXSEG4EI32V   0xfc00707f
+-#define MATCH_VSXSEG4EI32V  0x6c006027
+-#define MASK_VSXSEG4EI32V   0xfc00707f
+-#define MATCH_VLXSEG5EI32V  0x8c006007
+-#define MASK_VLXSEG5EI32V   0xfc00707f
+-#define MATCH_VSXSEG5EI32V  0x8c006027
+-#define MASK_VSXSEG5EI32V   0xfc00707f
+-#define MATCH_VLXSEG6EI32V  0xac006007
+-#define MASK_VLXSEG6EI32V   0xfc00707f
+-#define MATCH_VSXSEG6EI32V  0xac006027
+-#define MASK_VSXSEG6EI32V   0xfc00707f
+-#define MATCH_VLXSEG7EI32V  0xcc006007
+-#define MASK_VLXSEG7EI32V   0xfc00707f
+-#define MATCH_VSXSEG7EI32V  0xcc006027
+-#define MASK_VSXSEG7EI32V   0xfc00707f
+-#define MATCH_VLXSEG8EI32V  0xec006007
+-#define MASK_VLXSEG8EI32V   0xfc00707f
+-#define MATCH_VSXSEG8EI32V  0xec006027
+-#define MASK_VSXSEG8EI32V   0xfc00707f
+-
+-#define MATCH_VLXSEG2EI64V  0x2c007007
+-#define MASK_VLXSEG2EI64V   0xfc00707f
+-#define MATCH_VSXSEG2EI64V  0x2c007027
+-#define MASK_VSXSEG2EI64V   0xfc00707f
+-#define MATCH_VLXSEG3EI64V  0x4c007007
+-#define MASK_VLXSEG3EI64V   0xfc00707f
+-#define MATCH_VSXSEG3EI64V  0x4c007027
+-#define MASK_VSXSEG3EI64V   0xfc00707f
+-#define MATCH_VLXSEG4EI64V  0x6c007007
+-#define MASK_VLXSEG4EI64V   0xfc00707f
+-#define MATCH_VSXSEG4EI64V  0x6c007027
+-#define MASK_VSXSEG4EI64V   0xfc00707f
+-#define MATCH_VLXSEG5EI64V  0x8c007007
+-#define MASK_VLXSEG5EI64V   0xfc00707f
+-#define MATCH_VSXSEG5EI64V  0x8c007027
+-#define MASK_VSXSEG5EI64V   0xfc00707f
+-#define MATCH_VLXSEG6EI64V  0xac007007
+-#define MASK_VLXSEG6EI64V   0xfc00707f
+-#define MATCH_VSXSEG6EI64V  0xac007027
+-#define MASK_VSXSEG6EI64V   0xfc00707f
+-#define MATCH_VLXSEG7EI64V  0xcc007007
+-#define MASK_VLXSEG7EI64V   0xfc00707f
+-#define MATCH_VSXSEG7EI64V  0xcc007027
+-#define MASK_VSXSEG7EI64V   0xfc00707f
+-#define MATCH_VLXSEG8EI64V  0xec007007
+-#define MASK_VLXSEG8EI64V   0xfc00707f
+-#define MATCH_VSXSEG8EI64V  0xec007027
+-#define MASK_VSXSEG8EI64V   0xfc00707f
+-
+-#define MATCH_VLXSEG2EI128V  0x3c000007
+-#define MASK_VLXSEG2EI128V   0xfc00707f
+-#define MATCH_VSXSEG2EI128V  0x3c000027
+-#define MASK_VSXSEG2EI128V   0xfc00707f
+-#define MATCH_VLXSEG3EI128V  0x5c000007
+-#define MASK_VLXSEG3EI128V   0xfc00707f
+-#define MATCH_VSXSEG3EI128V  0x5c000027
+-#define MASK_VSXSEG3EI128V   0xfc00707f
+-#define MATCH_VLXSEG4EI128V  0x7c000007
+-#define MASK_VLXSEG4EI128V   0xfc00707f
+-#define MATCH_VSXSEG4EI128V  0x7c000027
+-#define MASK_VSXSEG4EI128V   0xfc00707f
+-#define MATCH_VLXSEG5EI128V  0x9c000007
+-#define MASK_VLXSEG5EI128V   0xfc00707f
+-#define MATCH_VSXSEG5EI128V  0x9c000027
+-#define MASK_VSXSEG5EI128V   0xfc00707f
+-#define MATCH_VLXSEG6EI128V  0xbc000007
+-#define MASK_VLXSEG6EI128V   0xfc00707f
+-#define MATCH_VSXSEG6EI128V  0xbc000027
+-#define MASK_VSXSEG6EI128V   0xfc00707f
+-#define MATCH_VLXSEG7EI128V  0xdc000007
+-#define MASK_VLXSEG7EI128V   0xfc00707f
+-#define MATCH_VSXSEG7EI128V  0xdc000027
+-#define MASK_VSXSEG7EI128V   0xfc00707f
+-#define MATCH_VLXSEG8EI128V  0xfc000007
+-#define MASK_VLXSEG8EI128V   0xfc00707f
+-#define MATCH_VSXSEG8EI128V  0xfc000027
+-#define MASK_VSXSEG8EI128V   0xfc00707f
+-
+-#define MATCH_VLXSEG2EI256V  0x3c005007
+-#define MASK_VLXSEG2EI256V   0xfc00707f
+-#define MATCH_VSXSEG2EI256V  0x3c005027
+-#define MASK_VSXSEG2EI256V   0xfc00707f
+-#define MATCH_VLXSEG3EI256V  0x5c005007
+-#define MASK_VLXSEG3EI256V   0xfc00707f
+-#define MATCH_VSXSEG3EI256V  0x5c005027
+-#define MASK_VSXSEG3EI256V   0xfc00707f
+-#define MATCH_VLXSEG4EI256V  0x7c005007
+-#define MASK_VLXSEG4EI256V   0xfc00707f
+-#define MATCH_VSXSEG4EI256V  0x7c005027
+-#define MASK_VSXSEG4EI256V   0xfc00707f
+-#define MATCH_VLXSEG5EI256V  0x9c005007
+-#define MASK_VLXSEG5EI256V   0xfc00707f
+-#define MATCH_VSXSEG5EI256V  0x9c005027
+-#define MASK_VSXSEG5EI256V   0xfc00707f
+-#define MATCH_VLXSEG6EI256V  0xbc005007
+-#define MASK_VLXSEG6EI256V   0xfc00707f
+-#define MATCH_VSXSEG6EI256V  0xbc005027
+-#define MASK_VSXSEG6EI256V   0xfc00707f
+-#define MATCH_VLXSEG7EI256V  0xdc005007
+-#define MASK_VLXSEG7EI256V   0xfc00707f
+-#define MATCH_VSXSEG7EI256V  0xdc005027
+-#define MASK_VSXSEG7EI256V   0xfc00707f
+-#define MATCH_VLXSEG8EI256V  0xfc005007
+-#define MASK_VLXSEG8EI256V   0xfc00707f
+-#define MATCH_VSXSEG8EI256V  0xfc005027
+-#define MASK_VSXSEG8EI256V   0xfc00707f
+-
+-#define MATCH_VLXSEG2EI512V  0x3c006007
+-#define MASK_VLXSEG2EI512V   0xfc00707f
+-#define MATCH_VSXSEG2EI512V  0x3c006027
+-#define MASK_VSXSEG2EI512V   0xfc00707f
+-#define MATCH_VLXSEG3EI512V  0x5c006007
+-#define MASK_VLXSEG3EI512V   0xfc00707f
+-#define MATCH_VSXSEG3EI512V  0x5c006027
+-#define MASK_VSXSEG3EI512V   0xfc00707f
+-#define MATCH_VLXSEG4EI512V  0x7c006007
+-#define MASK_VLXSEG4EI512V   0xfc00707f
+-#define MATCH_VSXSEG4EI512V  0x7c006027
+-#define MASK_VSXSEG4EI512V   0xfc00707f
+-#define MATCH_VLXSEG5EI512V  0x9c006007
+-#define MASK_VLXSEG5EI512V   0xfc00707f
+-#define MATCH_VSXSEG5EI512V  0x9c006027
+-#define MASK_VSXSEG5EI512V   0xfc00707f
+-#define MATCH_VLXSEG6EI512V  0xbc006007
+-#define MASK_VLXSEG6EI512V   0xfc00707f
+-#define MATCH_VSXSEG6EI512V  0xbc006027
+-#define MASK_VSXSEG6EI512V   0xfc00707f
+-#define MATCH_VLXSEG7EI512V  0xdc006007
+-#define MASK_VLXSEG7EI512V   0xfc00707f
+-#define MATCH_VSXSEG7EI512V  0xdc006027
+-#define MASK_VSXSEG7EI512V   0xfc00707f
+-#define MATCH_VLXSEG8EI512V  0xfc006007
+-#define MASK_VLXSEG8EI512V   0xfc00707f
+-#define MATCH_VSXSEG8EI512V  0xfc006027
+-#define MASK_VSXSEG8EI512V   0xfc00707f
+-
+-#define MATCH_VLXSEG2EI1024V  0x3c007007
+-#define MASK_VLXSEG2EI1024V   0xfc00707f
+-#define MATCH_VSXSEG2EI1024V  0x3c007027
+-#define MASK_VSXSEG2EI1024V   0xfc00707f
+-#define MATCH_VLXSEG3EI1024V  0x5c007007
+-#define MASK_VLXSEG3EI1024V   0xfc00707f
+-#define MATCH_VSXSEG3EI1024V  0x5c007027
+-#define MASK_VSXSEG3EI1024V   0xfc00707f
+-#define MATCH_VLXSEG4EI1024V  0x7c007007
+-#define MASK_VLXSEG4EI1024V   0xfc00707f
+-#define MATCH_VSXSEG4EI1024V  0x7c007027
+-#define MASK_VSXSEG4EI1024V   0xfc00707f
+-#define MATCH_VLXSEG5EI1024V  0x9c007007
+-#define MASK_VLXSEG5EI1024V   0xfc00707f
+-#define MATCH_VSXSEG5EI1024V  0x9c007027
+-#define MASK_VSXSEG5EI1024V   0xfc00707f
+-#define MATCH_VLXSEG6EI1024V  0xbc007007
+-#define MASK_VLXSEG6EI1024V   0xfc00707f
+-#define MATCH_VSXSEG6EI1024V  0xbc007027
+-#define MASK_VSXSEG6EI1024V   0xfc00707f
+-#define MATCH_VLXSEG7EI1024V  0xdc007007
+-#define MASK_VLXSEG7EI1024V   0xfc00707f
+-#define MATCH_VSXSEG7EI1024V  0xdc007027
+-#define MASK_VSXSEG7EI1024V   0xfc00707f
+-#define MATCH_VLXSEG8EI1024V  0xfc007007
+-#define MASK_VLXSEG8EI1024V   0xfc00707f
+-#define MATCH_VSXSEG8EI1024V  0xfc007027
+-#define MASK_VSXSEG8EI1024V   0xfc00707f
++#define MATCH_VLOXSEG2EI8V  0x2c000007
++#define MASK_VLOXSEG2EI8V   0xfc00707f
++#define MATCH_VSOXSEG2EI8V  0x2c000027
++#define MASK_VSOXSEG2EI8V   0xfc00707f
++#define MATCH_VLOXSEG3EI8V  0x4c000007
++#define MASK_VLOXSEG3EI8V   0xfc00707f
++#define MATCH_VSOXSEG3EI8V  0x4c000027
++#define MASK_VSOXSEG3EI8V   0xfc00707f
++#define MATCH_VLOXSEG4EI8V  0x6c000007
++#define MASK_VLOXSEG4EI8V   0xfc00707f
++#define MATCH_VSOXSEG4EI8V  0x6c000027
++#define MASK_VSOXSEG4EI8V   0xfc00707f
++#define MATCH_VLOXSEG5EI8V  0x8c000007
++#define MASK_VLOXSEG5EI8V   0xfc00707f
++#define MATCH_VSOXSEG5EI8V  0x8c000027
++#define MASK_VSOXSEG5EI8V   0xfc00707f
++#define MATCH_VLOXSEG6EI8V  0xac000007
++#define MASK_VLOXSEG6EI8V   0xfc00707f
++#define MATCH_VSOXSEG6EI8V  0xac000027
++#define MASK_VSOXSEG6EI8V   0xfc00707f
++#define MATCH_VLOXSEG7EI8V  0xcc000007
++#define MASK_VLOXSEG7EI8V   0xfc00707f
++#define MATCH_VSOXSEG7EI8V  0xcc000027
++#define MASK_VSOXSEG7EI8V   0xfc00707f
++#define MATCH_VLOXSEG8EI8V  0xec000007
++#define MASK_VLOXSEG8EI8V   0xfc00707f
++#define MATCH_VSOXSEG8EI8V  0xec000027
++#define MASK_VSOXSEG8EI8V   0xfc00707f
++
++#define MATCH_VLUXSEG2EI8V  0x24000007
++#define MASK_VLUXSEG2EI8V   0xfc00707f
++#define MATCH_VSUXSEG2EI8V  0x24000027
++#define MASK_VSUXSEG2EI8V   0xfc00707f
++#define MATCH_VLUXSEG3EI8V  0x44000007
++#define MASK_VLUXSEG3EI8V   0xfc00707f
++#define MATCH_VSUXSEG3EI8V  0x44000027
++#define MASK_VSUXSEG3EI8V   0xfc00707f
++#define MATCH_VLUXSEG4EI8V  0x64000007
++#define MASK_VLUXSEG4EI8V   0xfc00707f
++#define MATCH_VSUXSEG4EI8V  0x64000027
++#define MASK_VSUXSEG4EI8V   0xfc00707f
++#define MATCH_VLUXSEG5EI8V  0x84000007
++#define MASK_VLUXSEG5EI8V   0xfc00707f
++#define MATCH_VSUXSEG5EI8V  0x84000027
++#define MASK_VSUXSEG5EI8V   0xfc00707f
++#define MATCH_VLUXSEG6EI8V  0xa4000007
++#define MASK_VLUXSEG6EI8V   0xfc00707f
++#define MATCH_VSUXSEG6EI8V  0xa4000027
++#define MASK_VSUXSEG6EI8V   0xfc00707f
++#define MATCH_VLUXSEG7EI8V  0xc4000007
++#define MASK_VLUXSEG7EI8V   0xfc00707f
++#define MATCH_VSUXSEG7EI8V  0xc4000027
++#define MASK_VSUXSEG7EI8V   0xfc00707f
++#define MATCH_VLUXSEG8EI8V  0xe4000007
++#define MASK_VLUXSEG8EI8V   0xfc00707f
++#define MATCH_VSUXSEG8EI8V  0xe4000027
++#define MASK_VSUXSEG8EI8V   0xfc00707f
++
++#define MATCH_VLOXSEG2EI16V  0x2c005007
++#define MASK_VLOXSEG2EI16V   0xfc00707f
++#define MATCH_VSOXSEG2EI16V  0x2c005027
++#define MASK_VSOXSEG2EI16V   0xfc00707f
++#define MATCH_VLOXSEG3EI16V  0x4c005007
++#define MASK_VLOXSEG3EI16V   0xfc00707f
++#define MATCH_VSOXSEG3EI16V  0x4c005027
++#define MASK_VSOXSEG3EI16V   0xfc00707f
++#define MATCH_VLOXSEG4EI16V  0x6c005007
++#define MASK_VLOXSEG4EI16V   0xfc00707f
++#define MATCH_VSOXSEG4EI16V  0x6c005027
++#define MASK_VSOXSEG4EI16V   0xfc00707f
++#define MATCH_VLOXSEG5EI16V  0x8c005007
++#define MASK_VLOXSEG5EI16V   0xfc00707f
++#define MATCH_VSOXSEG5EI16V  0x8c005027
++#define MASK_VSOXSEG5EI16V   0xfc00707f
++#define MATCH_VLOXSEG6EI16V  0xac005007
++#define MASK_VLOXSEG6EI16V   0xfc00707f
++#define MATCH_VSOXSEG6EI16V  0xac005027
++#define MASK_VSOXSEG6EI16V   0xfc00707f
++#define MATCH_VLOXSEG7EI16V  0xcc005007
++#define MASK_VLOXSEG7EI16V   0xfc00707f
++#define MATCH_VSOXSEG7EI16V  0xcc005027
++#define MASK_VSOXSEG7EI16V   0xfc00707f
++#define MATCH_VLOXSEG8EI16V  0xec005007
++#define MASK_VLOXSEG8EI16V   0xfc00707f
++#define MATCH_VSOXSEG8EI16V  0xec005027
++#define MASK_VSOXSEG8EI16V   0xfc00707f
++
++#define MATCH_VLUXSEG2EI16V  0x24005007
++#define MASK_VLUXSEG2EI16V   0xfc00707f
++#define MATCH_VSUXSEG2EI16V  0x24005027
++#define MASK_VSUXSEG2EI16V   0xfc00707f
++#define MATCH_VLUXSEG3EI16V  0x44005007
++#define MASK_VLUXSEG3EI16V   0xfc00707f
++#define MATCH_VSUXSEG3EI16V  0x44005027
++#define MASK_VSUXSEG3EI16V   0xfc00707f
++#define MATCH_VLUXSEG4EI16V  0x64005007
++#define MASK_VLUXSEG4EI16V   0xfc00707f
++#define MATCH_VSUXSEG4EI16V  0x64005027
++#define MASK_VSUXSEG4EI16V   0xfc00707f
++#define MATCH_VLUXSEG5EI16V  0x84005007
++#define MASK_VLUXSEG5EI16V   0xfc00707f
++#define MATCH_VSUXSEG5EI16V  0x84005027
++#define MASK_VSUXSEG5EI16V   0xfc00707f
++#define MATCH_VLUXSEG6EI16V  0xa4005007
++#define MASK_VLUXSEG6EI16V   0xfc00707f
++#define MATCH_VSUXSEG6EI16V  0xa4005027
++#define MASK_VSUXSEG6EI16V   0xfc00707f
++#define MATCH_VLUXSEG7EI16V  0xc4005007
++#define MASK_VLUXSEG7EI16V   0xfc00707f
++#define MATCH_VSUXSEG7EI16V  0xc4005027
++#define MASK_VSUXSEG7EI16V   0xfc00707f
++#define MATCH_VLUXSEG8EI16V  0xe4005007
++#define MASK_VLUXSEG8EI16V   0xfc00707f
++#define MATCH_VSUXSEG8EI16V  0xe4005027
++#define MASK_VSUXSEG8EI16V   0xfc00707f
++
++#define MATCH_VLOXSEG2EI32V  0x2c006007
++#define MASK_VLOXSEG2EI32V   0xfc00707f
++#define MATCH_VSOXSEG2EI32V  0x2c006027
++#define MASK_VSOXSEG2EI32V   0xfc00707f
++#define MATCH_VLOXSEG3EI32V  0x4c006007
++#define MASK_VLOXSEG3EI32V   0xfc00707f
++#define MATCH_VSOXSEG3EI32V  0x4c006027
++#define MASK_VSOXSEG3EI32V   0xfc00707f
++#define MATCH_VLOXSEG4EI32V  0x6c006007
++#define MASK_VLOXSEG4EI32V   0xfc00707f
++#define MATCH_VSOXSEG4EI32V  0x6c006027
++#define MASK_VSOXSEG4EI32V   0xfc00707f
++#define MATCH_VLOXSEG5EI32V  0x8c006007
++#define MASK_VLOXSEG5EI32V   0xfc00707f
++#define MATCH_VSOXSEG5EI32V  0x8c006027
++#define MASK_VSOXSEG5EI32V   0xfc00707f
++#define MATCH_VLOXSEG6EI32V  0xac006007
++#define MASK_VLOXSEG6EI32V   0xfc00707f
++#define MATCH_VSOXSEG6EI32V  0xac006027
++#define MASK_VSOXSEG6EI32V   0xfc00707f
++#define MATCH_VLOXSEG7EI32V  0xcc006007
++#define MASK_VLOXSEG7EI32V   0xfc00707f
++#define MATCH_VSOXSEG7EI32V  0xcc006027
++#define MASK_VSOXSEG7EI32V   0xfc00707f
++#define MATCH_VLOXSEG8EI32V  0xec006007
++#define MASK_VLOXSEG8EI32V   0xfc00707f
++#define MATCH_VSOXSEG8EI32V  0xec006027
++#define MASK_VSOXSEG8EI32V   0xfc00707f
++
++#define MATCH_VLUXSEG2EI32V  0x24006007
++#define MASK_VLUXSEG2EI32V   0xfc00707f
++#define MATCH_VSUXSEG2EI32V  0x24006027
++#define MASK_VSUXSEG2EI32V   0xfc00707f
++#define MATCH_VLUXSEG3EI32V  0x44006007
++#define MASK_VLUXSEG3EI32V   0xfc00707f
++#define MATCH_VSUXSEG3EI32V  0x44006027
++#define MASK_VSUXSEG3EI32V   0xfc00707f
++#define MATCH_VLUXSEG4EI32V  0x64006007
++#define MASK_VLUXSEG4EI32V   0xfc00707f
++#define MATCH_VSUXSEG4EI32V  0x64006027
++#define MASK_VSUXSEG4EI32V   0xfc00707f
++#define MATCH_VLUXSEG5EI32V  0x84006007
++#define MASK_VLUXSEG5EI32V   0xfc00707f
++#define MATCH_VSUXSEG5EI32V  0x84006027
++#define MASK_VSUXSEG5EI32V   0xfc00707f
++#define MATCH_VLUXSEG6EI32V  0xa4006007
++#define MASK_VLUXSEG6EI32V   0xfc00707f
++#define MATCH_VSUXSEG6EI32V  0xa4006027
++#define MASK_VSUXSEG6EI32V   0xfc00707f
++#define MATCH_VLUXSEG7EI32V  0xc4006007
++#define MASK_VLUXSEG7EI32V   0xfc00707f
++#define MATCH_VSUXSEG7EI32V  0xc4006027
++#define MASK_VSUXSEG7EI32V   0xfc00707f
++#define MATCH_VLUXSEG8EI32V  0xe4006007
++#define MASK_VLUXSEG8EI32V   0xfc00707f
++#define MATCH_VSUXSEG8EI32V  0xe4006027
++#define MASK_VSUXSEG8EI32V   0xfc00707f
++
++#define MATCH_VLOXSEG2EI64V  0x2c007007
++#define MASK_VLOXSEG2EI64V   0xfc00707f
++#define MATCH_VSOXSEG2EI64V  0x2c007027
++#define MASK_VSOXSEG2EI64V   0xfc00707f
++#define MATCH_VLOXSEG3EI64V  0x4c007007
++#define MASK_VLOXSEG3EI64V   0xfc00707f
++#define MATCH_VSOXSEG3EI64V  0x4c007027
++#define MASK_VSOXSEG3EI64V   0xfc00707f
++#define MATCH_VLOXSEG4EI64V  0x6c007007
++#define MASK_VLOXSEG4EI64V   0xfc00707f
++#define MATCH_VSOXSEG4EI64V  0x6c007027
++#define MASK_VSOXSEG4EI64V   0xfc00707f
++#define MATCH_VLOXSEG5EI64V  0x8c007007
++#define MASK_VLOXSEG5EI64V   0xfc00707f
++#define MATCH_VSOXSEG5EI64V  0x8c007027
++#define MASK_VSOXSEG5EI64V   0xfc00707f
++#define MATCH_VLOXSEG6EI64V  0xac007007
++#define MASK_VLOXSEG6EI64V   0xfc00707f
++#define MATCH_VSOXSEG6EI64V  0xac007027
++#define MASK_VSOXSEG6EI64V   0xfc00707f
++#define MATCH_VLOXSEG7EI64V  0xcc007007
++#define MASK_VLOXSEG7EI64V   0xfc00707f
++#define MATCH_VSOXSEG7EI64V  0xcc007027
++#define MASK_VSOXSEG7EI64V   0xfc00707f
++#define MATCH_VLOXSEG8EI64V  0xec007007
++#define MASK_VLOXSEG8EI64V   0xfc00707f
++#define MATCH_VSOXSEG8EI64V  0xec007027
++#define MASK_VSOXSEG8EI64V   0xfc00707f
++
++#define MATCH_VLUXSEG2EI64V  0x24007007
++#define MASK_VLUXSEG2EI64V   0xfc00707f
++#define MATCH_VSUXSEG2EI64V  0x24007027
++#define MASK_VSUXSEG2EI64V   0xfc00707f
++#define MATCH_VLUXSEG3EI64V  0x44007007
++#define MASK_VLUXSEG3EI64V   0xfc00707f
++#define MATCH_VSUXSEG3EI64V  0x44007027
++#define MASK_VSUXSEG3EI64V   0xfc00707f
++#define MATCH_VLUXSEG4EI64V  0x64007007
++#define MASK_VLUXSEG4EI64V   0xfc00707f
++#define MATCH_VSUXSEG4EI64V  0x64007027
++#define MASK_VSUXSEG4EI64V   0xfc00707f
++#define MATCH_VLUXSEG5EI64V  0x84007007
++#define MASK_VLUXSEG5EI64V   0xfc00707f
++#define MATCH_VSUXSEG5EI64V  0x84007027
++#define MASK_VSUXSEG5EI64V   0xfc00707f
++#define MATCH_VLUXSEG6EI64V  0xa4007007
++#define MASK_VLUXSEG6EI64V   0xfc00707f
++#define MATCH_VSUXSEG6EI64V  0xa4007027
++#define MASK_VSUXSEG6EI64V   0xfc00707f
++#define MATCH_VLUXSEG7EI64V  0xc4007007
++#define MASK_VLUXSEG7EI64V   0xfc00707f
++#define MATCH_VSUXSEG7EI64V  0xc4007027
++#define MASK_VSUXSEG7EI64V   0xfc00707f
++#define MATCH_VLUXSEG8EI64V  0xe4007007
++#define MASK_VLUXSEG8EI64V   0xfc00707f
++#define MATCH_VSUXSEG8EI64V  0xe4007027
++#define MASK_VSUXSEG8EI64V   0xfc00707f
++
++#define MATCH_VLOXSEG2EI128V  0x3c000007
++#define MASK_VLOXSEG2EI128V   0xfc00707f
++#define MATCH_VSOXSEG2EI128V  0x3c000027
++#define MASK_VSOXSEG2EI128V   0xfc00707f
++#define MATCH_VLOXSEG3EI128V  0x5c000007
++#define MASK_VLOXSEG3EI128V   0xfc00707f
++#define MATCH_VSOXSEG3EI128V  0x5c000027
++#define MASK_VSOXSEG3EI128V   0xfc00707f
++#define MATCH_VLOXSEG4EI128V  0x7c000007
++#define MASK_VLOXSEG4EI128V   0xfc00707f
++#define MATCH_VSOXSEG4EI128V  0x7c000027
++#define MASK_VSOXSEG4EI128V   0xfc00707f
++#define MATCH_VLOXSEG5EI128V  0x9c000007
++#define MASK_VLOXSEG5EI128V   0xfc00707f
++#define MATCH_VSOXSEG5EI128V  0x9c000027
++#define MASK_VSOXSEG5EI128V   0xfc00707f
++#define MATCH_VLOXSEG6EI128V  0xbc000007
++#define MASK_VLOXSEG6EI128V   0xfc00707f
++#define MATCH_VSOXSEG6EI128V  0xbc000027
++#define MASK_VSOXSEG6EI128V   0xfc00707f
++#define MATCH_VLOXSEG7EI128V  0xdc000007
++#define MASK_VLOXSEG7EI128V   0xfc00707f
++#define MATCH_VSOXSEG7EI128V  0xdc000027
++#define MASK_VSOXSEG7EI128V   0xfc00707f
++#define MATCH_VLOXSEG8EI128V  0xfc000007
++#define MASK_VLOXSEG8EI128V   0xfc00707f
++#define MATCH_VSOXSEG8EI128V  0xfc000027
++#define MASK_VSOXSEG8EI128V   0xfc00707f
++
++#define MATCH_VLUXSEG2EI128V  0x34000007
++#define MASK_VLUXSEG2EI128V   0xfc00707f
++#define MATCH_VSUXSEG2EI128V  0x34000027
++#define MASK_VSUXSEG2EI128V   0xfc00707f
++#define MATCH_VLUXSEG3EI128V  0x54000007
++#define MASK_VLUXSEG3EI128V   0xfc00707f
++#define MATCH_VSUXSEG3EI128V  0x54000027
++#define MASK_VSUXSEG3EI128V   0xfc00707f
++#define MATCH_VLUXSEG4EI128V  0x74000007
++#define MASK_VLUXSEG4EI128V   0xfc00707f
++#define MATCH_VSUXSEG4EI128V  0x74000027
++#define MASK_VSUXSEG4EI128V   0xfc00707f
++#define MATCH_VLUXSEG5EI128V  0x94000007
++#define MASK_VLUXSEG5EI128V   0xfc00707f
++#define MATCH_VSUXSEG5EI128V  0x94000027
++#define MASK_VSUXSEG5EI128V   0xfc00707f
++#define MATCH_VLUXSEG6EI128V  0xb4000007
++#define MASK_VLUXSEG6EI128V   0xfc00707f
++#define MATCH_VSUXSEG6EI128V  0xb4000027
++#define MASK_VSUXSEG6EI128V   0xfc00707f
++#define MATCH_VLUXSEG7EI128V  0xd4000007
++#define MASK_VLUXSEG7EI128V   0xfc00707f
++#define MATCH_VSUXSEG7EI128V  0xd4000027
++#define MASK_VSUXSEG7EI128V   0xfc00707f
++#define MATCH_VLUXSEG8EI128V  0xf4000007
++#define MASK_VLUXSEG8EI128V   0xfc00707f
++#define MATCH_VSUXSEG8EI128V  0xf4000027
++#define MASK_VSUXSEG8EI128V   0xfc00707f
++
++#define MATCH_VLOXSEG2EI256V  0x3c005007
++#define MASK_VLOXSEG2EI256V   0xfc00707f
++#define MATCH_VSOXSEG2EI256V  0x3c005027
++#define MASK_VSOXSEG2EI256V   0xfc00707f
++#define MATCH_VLOXSEG3EI256V  0x5c005007
++#define MASK_VLOXSEG3EI256V   0xfc00707f
++#define MATCH_VSOXSEG3EI256V  0x5c005027
++#define MASK_VSOXSEG3EI256V   0xfc00707f
++#define MATCH_VLOXSEG4EI256V  0x7c005007
++#define MASK_VLOXSEG4EI256V   0xfc00707f
++#define MATCH_VSOXSEG4EI256V  0x7c005027
++#define MASK_VSOXSEG4EI256V   0xfc00707f
++#define MATCH_VLOXSEG5EI256V  0x9c005007
++#define MASK_VLOXSEG5EI256V   0xfc00707f
++#define MATCH_VSOXSEG5EI256V  0x9c005027
++#define MASK_VSOXSEG5EI256V   0xfc00707f
++#define MATCH_VLOXSEG6EI256V  0xbc005007
++#define MASK_VLOXSEG6EI256V   0xfc00707f
++#define MATCH_VSOXSEG6EI256V  0xbc005027
++#define MASK_VSOXSEG6EI256V   0xfc00707f
++#define MATCH_VLOXSEG7EI256V  0xdc005007
++#define MASK_VLOXSEG7EI256V   0xfc00707f
++#define MATCH_VSOXSEG7EI256V  0xdc005027
++#define MASK_VSOXSEG7EI256V   0xfc00707f
++#define MATCH_VLOXSEG8EI256V  0xfc005007
++#define MASK_VLOXSEG8EI256V   0xfc00707f
++#define MATCH_VSOXSEG8EI256V  0xfc005027
++#define MASK_VSOXSEG8EI256V   0xfc00707f
++
++#define MATCH_VLUXSEG2EI256V  0x34005007
++#define MASK_VLUXSEG2EI256V   0xfc00707f
++#define MATCH_VSUXSEG2EI256V  0x34005027
++#define MASK_VSUXSEG2EI256V   0xfc00707f
++#define MATCH_VLUXSEG3EI256V  0x54005007
++#define MASK_VLUXSEG3EI256V   0xfc00707f
++#define MATCH_VSUXSEG3EI256V  0x54005027
++#define MASK_VSUXSEG3EI256V   0xfc00707f
++#define MATCH_VLUXSEG4EI256V  0x74005007
++#define MASK_VLUXSEG4EI256V   0xfc00707f
++#define MATCH_VSUXSEG4EI256V  0x74005027
++#define MASK_VSUXSEG4EI256V   0xfc00707f
++#define MATCH_VLUXSEG5EI256V  0x94005007
++#define MASK_VLUXSEG5EI256V   0xfc00707f
++#define MATCH_VSUXSEG5EI256V  0x94005027
++#define MASK_VSUXSEG5EI256V   0xfc00707f
++#define MATCH_VLUXSEG6EI256V  0xb4005007
++#define MASK_VLUXSEG6EI256V   0xfc00707f
++#define MATCH_VSUXSEG6EI256V  0xb4005027
++#define MASK_VSUXSEG6EI256V   0xfc00707f
++#define MATCH_VLUXSEG7EI256V  0xd4005007
++#define MASK_VLUXSEG7EI256V   0xfc00707f
++#define MATCH_VSUXSEG7EI256V  0xd4005027
++#define MASK_VSUXSEG7EI256V   0xfc00707f
++#define MATCH_VLUXSEG8EI256V  0xf4005007
++#define MASK_VLUXSEG8EI256V   0xfc00707f
++#define MATCH_VSUXSEG8EI256V  0xf4005027
++#define MASK_VSUXSEG8EI256V   0xfc00707f
++
++#define MATCH_VLOXSEG2EI512V  0x3c006007
++#define MASK_VLOXSEG2EI512V   0xfc00707f
++#define MATCH_VSOXSEG2EI512V  0x3c006027
++#define MASK_VSOXSEG2EI512V   0xfc00707f
++#define MATCH_VLOXSEG3EI512V  0x5c006007
++#define MASK_VLOXSEG3EI512V   0xfc00707f
++#define MATCH_VSOXSEG3EI512V  0x5c006027
++#define MASK_VSOXSEG3EI512V   0xfc00707f
++#define MATCH_VLOXSEG4EI512V  0x7c006007
++#define MASK_VLOXSEG4EI512V   0xfc00707f
++#define MATCH_VSOXSEG4EI512V  0x7c006027
++#define MASK_VSOXSEG4EI512V   0xfc00707f
++#define MATCH_VLOXSEG5EI512V  0x9c006007
++#define MASK_VLOXSEG5EI512V   0xfc00707f
++#define MATCH_VSOXSEG5EI512V  0x9c006027
++#define MASK_VSOXSEG5EI512V   0xfc00707f
++#define MATCH_VLOXSEG6EI512V  0xbc006007
++#define MASK_VLOXSEG6EI512V   0xfc00707f
++#define MATCH_VSOXSEG6EI512V  0xbc006027
++#define MASK_VSOXSEG6EI512V   0xfc00707f
++#define MATCH_VLOXSEG7EI512V  0xdc006007
++#define MASK_VLOXSEG7EI512V   0xfc00707f
++#define MATCH_VSOXSEG7EI512V  0xdc006027
++#define MASK_VSOXSEG7EI512V   0xfc00707f
++#define MATCH_VLOXSEG8EI512V  0xfc006007
++#define MASK_VLOXSEG8EI512V   0xfc00707f
++#define MATCH_VSOXSEG8EI512V  0xfc006027
++#define MASK_VSOXSEG8EI512V   0xfc00707f
++
++#define MATCH_VLUXSEG2EI512V  0x34006007
++#define MASK_VLUXSEG2EI512V   0xfc00707f
++#define MATCH_VSUXSEG2EI512V  0x34006027
++#define MASK_VSUXSEG2EI512V   0xfc00707f
++#define MATCH_VLUXSEG3EI512V  0x54006007
++#define MASK_VLUXSEG3EI512V   0xfc00707f
++#define MATCH_VSUXSEG3EI512V  0x54006027
++#define MASK_VSUXSEG3EI512V   0xfc00707f
++#define MATCH_VLUXSEG4EI512V  0x74006007
++#define MASK_VLUXSEG4EI512V   0xfc00707f
++#define MATCH_VSUXSEG4EI512V  0x74006027
++#define MASK_VSUXSEG4EI512V   0xfc00707f
++#define MATCH_VLUXSEG5EI512V  0x94006007
++#define MASK_VLUXSEG5EI512V   0xfc00707f
++#define MATCH_VSUXSEG5EI512V  0x94006027
++#define MASK_VSUXSEG5EI512V   0xfc00707f
++#define MATCH_VLUXSEG6EI512V  0xb4006007
++#define MASK_VLUXSEG6EI512V   0xfc00707f
++#define MATCH_VSUXSEG6EI512V  0xb4006027
++#define MASK_VSUXSEG6EI512V   0xfc00707f
++#define MATCH_VLUXSEG7EI512V  0xd4006007
++#define MASK_VLUXSEG7EI512V   0xfc00707f
++#define MATCH_VSUXSEG7EI512V  0xd4006027
++#define MASK_VSUXSEG7EI512V   0xfc00707f
++#define MATCH_VLUXSEG8EI512V  0xf4006007
++#define MASK_VLUXSEG8EI512V   0xfc00707f
++#define MATCH_VSUXSEG8EI512V  0xf4006027
++#define MASK_VSUXSEG8EI512V   0xfc00707f
++
++#define MATCH_VLOXSEG2EI1024V  0x3c007007
++#define MASK_VLOXSEG2EI1024V   0xfc00707f
++#define MATCH_VSOXSEG2EI1024V  0x3c007027
++#define MASK_VSOXSEG2EI1024V   0xfc00707f
++#define MATCH_VLOXSEG3EI1024V  0x5c007007
++#define MASK_VLOXSEG3EI1024V   0xfc00707f
++#define MATCH_VSOXSEG3EI1024V  0x5c007027
++#define MASK_VSOXSEG3EI1024V   0xfc00707f
++#define MATCH_VLOXSEG4EI1024V  0x7c007007
++#define MASK_VLOXSEG4EI1024V   0xfc00707f
++#define MATCH_VSOXSEG4EI1024V  0x7c007027
++#define MASK_VSOXSEG4EI1024V   0xfc00707f
++#define MATCH_VLOXSEG5EI1024V  0x9c007007
++#define MASK_VLOXSEG5EI1024V   0xfc00707f
++#define MATCH_VSOXSEG5EI1024V  0x9c007027
++#define MASK_VSOXSEG5EI1024V   0xfc00707f
++#define MATCH_VLOXSEG6EI1024V  0xbc007007
++#define MASK_VLOXSEG6EI1024V   0xfc00707f
++#define MATCH_VSOXSEG6EI1024V  0xbc007027
++#define MASK_VSOXSEG6EI1024V   0xfc00707f
++#define MATCH_VLOXSEG7EI1024V  0xdc007007
++#define MASK_VLOXSEG7EI1024V   0xfc00707f
++#define MATCH_VSOXSEG7EI1024V  0xdc007027
++#define MASK_VSOXSEG7EI1024V   0xfc00707f
++#define MATCH_VLOXSEG8EI1024V  0xfc007007
++#define MASK_VLOXSEG8EI1024V   0xfc00707f
++#define MATCH_VSOXSEG8EI1024V  0xfc007027
++#define MASK_VSOXSEG8EI1024V   0xfc00707f
++
++#define MATCH_VLUXSEG2EI1024V  0x34007007
++#define MASK_VLUXSEG2EI1024V   0xfc00707f
++#define MATCH_VSUXSEG2EI1024V  0x34007027
++#define MASK_VSUXSEG2EI1024V   0xfc00707f
++#define MATCH_VLUXSEG3EI1024V  0x54007007
++#define MASK_VLUXSEG3EI1024V   0xfc00707f
++#define MATCH_VSUXSEG3EI1024V  0x54007027
++#define MASK_VSUXSEG3EI1024V   0xfc00707f
++#define MATCH_VLUXSEG4EI1024V  0x74007007
++#define MASK_VLUXSEG4EI1024V   0xfc00707f
++#define MATCH_VSUXSEG4EI1024V  0x74007027
++#define MASK_VSUXSEG4EI1024V   0xfc00707f
++#define MATCH_VLUXSEG5EI1024V  0x94007007
++#define MASK_VLUXSEG5EI1024V   0xfc00707f
++#define MATCH_VSUXSEG5EI1024V  0x94007027
++#define MASK_VSUXSEG5EI1024V   0xfc00707f
++#define MATCH_VLUXSEG6EI1024V  0xb4007007
++#define MASK_VLUXSEG6EI1024V   0xfc00707f
++#define MATCH_VSUXSEG6EI1024V  0xb4007027
++#define MASK_VSUXSEG6EI1024V   0xfc00707f
++#define MATCH_VLUXSEG7EI1024V  0xd4007007
++#define MASK_VLUXSEG7EI1024V   0xfc00707f
++#define MATCH_VSUXSEG7EI1024V  0xd4007027
++#define MASK_VSUXSEG7EI1024V   0xfc00707f
++#define MATCH_VLUXSEG8EI1024V  0xf4007007
++#define MASK_VLUXSEG8EI1024V   0xfc00707f
++#define MATCH_VSUXSEG8EI1024V  0xf4007027
++#define MASK_VSUXSEG8EI1024V   0xfc00707f
+ 
+ #define MATCH_VLSEG2E8FFV  0x21000007
+ #define MASK_VLSEG2E8FFV   0xfdf0707f
+diff --git a/opcodes/riscv-opc.c b/opcodes/riscv-opc.c
+index e0383d08e9..076aea5f91 100644
+--- a/opcodes/riscv-opc.c
++++ b/opcodes/riscv-opc.c
+@@ -1307,15 +1307,20 @@ const struct riscv_opcode riscv_opcodes[] =
+ {"vsse512.v",  0, INSN_CLASS_V,  "Vd,0(s),tVm", MATCH_VSSE512V, MASK_VSSE512V, match_vd_neq_vm, INSN_DREF },
+ {"vsse1024.v", 0, INSN_CLASS_V,  "Vd,0(s),tVm", MATCH_VSSE1024V, MASK_VSSE1024V, match_vd_neq_vm, INSN_DREF },
+ 
+-{"vlxei8.v",   0, INSN_CLASS_V,  "Vd,0(s),VtVm", MATCH_VLXEI8V, MASK_VLXEI8V, match_vd_neq_vm, INSN_DREF },
+-{"vlxei16.v",  0, INSN_CLASS_V,  "Vd,0(s),VtVm", MATCH_VLXEI16V, MASK_VLXEI16V, match_vd_neq_vm, INSN_DREF },
+-{"vlxei32.v",  0, INSN_CLASS_V,  "Vd,0(s),VtVm", MATCH_VLXEI32V, MASK_VLXEI32V, match_vd_neq_vm, INSN_DREF },
+-{"vlxei64.v",  0, INSN_CLASS_V,  "Vd,0(s),VtVm", MATCH_VLXEI64V, MASK_VLXEI64V, match_vd_neq_vm, INSN_DREF },
++{"vloxei8.v",   0, INSN_CLASS_V,  "Vd,0(s),VtVm", MATCH_VLOXEI8V, MASK_VLOXEI8V, match_vd_neq_vm, INSN_DREF },
++{"vloxei16.v",  0, INSN_CLASS_V,  "Vd,0(s),VtVm", MATCH_VLOXEI16V, MASK_VLOXEI16V, match_vd_neq_vm, INSN_DREF },
++{"vloxei32.v",  0, INSN_CLASS_V,  "Vd,0(s),VtVm", MATCH_VLOXEI32V, MASK_VLOXEI32V, match_vd_neq_vm, INSN_DREF },
++{"vloxei64.v",  0, INSN_CLASS_V,  "Vd,0(s),VtVm", MATCH_VLOXEI64V, MASK_VLOXEI64V, match_vd_neq_vm, INSN_DREF },
+ 
+-{"vsxei8.v",   0, INSN_CLASS_V,  "Vd,0(s),VtVm", MATCH_VSXEI8V, MASK_VSXEI8V, match_vd_neq_vm, INSN_DREF },
+-{"vsxei16.v",  0, INSN_CLASS_V,  "Vd,0(s),VtVm", MATCH_VSXEI16V, MASK_VSXEI16V, match_vd_neq_vm, INSN_DREF },
+-{"vsxei32.v",  0, INSN_CLASS_V,  "Vd,0(s),VtVm", MATCH_VSXEI32V, MASK_VSXEI32V, match_vd_neq_vm, INSN_DREF },
+-{"vsxei64.v",  0, INSN_CLASS_V,  "Vd,0(s),VtVm", MATCH_VSXEI64V, MASK_VSXEI64V, match_vd_neq_vm, INSN_DREF },
++{"vsoxei8.v",   0, INSN_CLASS_V,  "Vd,0(s),VtVm", MATCH_VSOXEI8V, MASK_VSOXEI8V, match_vd_neq_vm, INSN_DREF },
++{"vsoxei16.v",  0, INSN_CLASS_V,  "Vd,0(s),VtVm", MATCH_VSOXEI16V, MASK_VSOXEI16V, match_vd_neq_vm, INSN_DREF },
++{"vsoxei32.v",  0, INSN_CLASS_V,  "Vd,0(s),VtVm", MATCH_VSOXEI32V, MASK_VSOXEI32V, match_vd_neq_vm, INSN_DREF },
++{"vsoxei64.v",  0, INSN_CLASS_V,  "Vd,0(s),VtVm", MATCH_VSOXEI64V, MASK_VSOXEI64V, match_vd_neq_vm, INSN_DREF },
++
++{"vluxei8.v",   0, INSN_CLASS_V,  "Vd,0(s),VtVm", MATCH_VLUXEI8V, MASK_VLUXEI8V, match_vd_neq_vm, INSN_DREF },
++{"vluxei16.v",  0, INSN_CLASS_V,  "Vd,0(s),VtVm", MATCH_VLUXEI16V, MASK_VLUXEI16V, match_vd_neq_vm, INSN_DREF },
++{"vluxei32.v",  0, INSN_CLASS_V,  "Vd,0(s),VtVm", MATCH_VLUXEI32V, MASK_VLUXEI32V, match_vd_neq_vm, INSN_DREF },
++{"vluxei64.v",  0, INSN_CLASS_V,  "Vd,0(s),VtVm", MATCH_VLUXEI64V, MASK_VLUXEI64V, match_vd_neq_vm, INSN_DREF },
+ 
+ {"vsuxei8.v",   0, INSN_CLASS_V,  "Vd,0(s),VtVm", MATCH_VSUXEI8V, MASK_VSUXEI8V, match_vd_neq_vm, INSN_DREF },
+ {"vsuxei16.v",  0, INSN_CLASS_V,  "Vd,0(s),VtVm", MATCH_VSUXEI16V, MASK_VSUXEI16V, match_vd_neq_vm, INSN_DREF },
+@@ -1571,125 +1576,245 @@ const struct riscv_opcode riscv_opcodes[] =
+ {"vlsseg8e1024.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),tVm", MATCH_VLSSEG8E1024V, MASK_VLSSEG8E1024V, match_vd_neq_vm, INSN_DREF },
+ {"vssseg8e1024.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),tVm", MATCH_VSSSEG8E1024V, MASK_VSSSEG8E1024V, match_vd_neq_vm, INSN_DREF },
+ 
+-{"vlxseg2ei8.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),VtVm", MATCH_VLXSEG2EI8V, MASK_VLXSEG2EI8V, match_vd_neq_vs2_neq_vm, INSN_DREF },
+-{"vsxseg2ei8.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),VtVm", MATCH_VSXSEG2EI8V, MASK_VSXSEG2EI8V, match_vd_neq_vs2_neq_vm, INSN_DREF },
+-{"vlxseg3ei8.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),VtVm", MATCH_VLXSEG3EI8V, MASK_VLXSEG3EI8V, match_vd_neq_vs2_neq_vm, INSN_DREF },
+-{"vsxseg3ei8.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),VtVm", MATCH_VSXSEG3EI8V, MASK_VSXSEG3EI8V, match_vd_neq_vs2_neq_vm, INSN_DREF },
+-{"vlxseg4ei8.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),VtVm", MATCH_VLXSEG4EI8V, MASK_VLXSEG4EI8V, match_vd_neq_vs2_neq_vm, INSN_DREF },
+-{"vsxseg4ei8.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),VtVm", MATCH_VSXSEG4EI8V, MASK_VSXSEG4EI8V, match_vd_neq_vs2_neq_vm, INSN_DREF },
+-{"vlxseg5ei8.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),VtVm", MATCH_VLXSEG5EI8V, MASK_VLXSEG5EI8V, match_vd_neq_vs2_neq_vm, INSN_DREF },
+-{"vsxseg5ei8.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),VtVm", MATCH_VSXSEG5EI8V, MASK_VSXSEG5EI8V, match_vd_neq_vs2_neq_vm, INSN_DREF },
+-{"vlxseg6ei8.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),VtVm", MATCH_VLXSEG6EI8V, MASK_VLXSEG6EI8V, match_vd_neq_vs2_neq_vm, INSN_DREF },
+-{"vsxseg6ei8.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),VtVm", MATCH_VSXSEG6EI8V, MASK_VSXSEG6EI8V, match_vd_neq_vs2_neq_vm, INSN_DREF },
+-{"vlxseg7ei8.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),VtVm", MATCH_VLXSEG7EI8V, MASK_VLXSEG7EI8V, match_vd_neq_vs2_neq_vm, INSN_DREF },
+-{"vsxseg7ei8.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),VtVm", MATCH_VSXSEG7EI8V, MASK_VSXSEG7EI8V, match_vd_neq_vs2_neq_vm, INSN_DREF },
+-{"vlxseg8ei8.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),VtVm", MATCH_VLXSEG8EI8V, MASK_VLXSEG8EI8V, match_vd_neq_vs2_neq_vm, INSN_DREF },
+-{"vsxseg8ei8.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),VtVm", MATCH_VSXSEG8EI8V, MASK_VSXSEG8EI8V, match_vd_neq_vs2_neq_vm, INSN_DREF },
+-
+-{"vlxseg2ei16.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),VtVm", MATCH_VLXSEG2EI16V, MASK_VLXSEG2EI16V, match_vd_neq_vs2_neq_vm, INSN_DREF },
+-{"vsxseg2ei16.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),VtVm", MATCH_VSXSEG2EI16V, MASK_VSXSEG2EI16V, match_vd_neq_vs2_neq_vm, INSN_DREF },
+-{"vlxseg3ei16.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),VtVm", MATCH_VLXSEG3EI16V, MASK_VLXSEG3EI16V, match_vd_neq_vs2_neq_vm, INSN_DREF },
+-{"vsxseg3ei16.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),VtVm", MATCH_VSXSEG3EI16V, MASK_VSXSEG3EI16V, match_vd_neq_vs2_neq_vm, INSN_DREF },
+-{"vlxseg4ei16.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),VtVm", MATCH_VLXSEG4EI16V, MASK_VLXSEG4EI16V, match_vd_neq_vs2_neq_vm, INSN_DREF },
+-{"vsxseg4ei16.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),VtVm", MATCH_VSXSEG4EI16V, MASK_VSXSEG4EI16V, match_vd_neq_vs2_neq_vm, INSN_DREF },
+-{"vlxseg5ei16.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),VtVm", MATCH_VLXSEG5EI16V, MASK_VLXSEG5EI16V, match_vd_neq_vs2_neq_vm, INSN_DREF },
+-{"vsxseg5ei16.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),VtVm", MATCH_VSXSEG5EI16V, MASK_VSXSEG5EI16V, match_vd_neq_vs2_neq_vm, INSN_DREF },
+-{"vlxseg6ei16.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),VtVm", MATCH_VLXSEG6EI16V, MASK_VLXSEG6EI16V, match_vd_neq_vs2_neq_vm, INSN_DREF },
+-{"vsxseg6ei16.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),VtVm", MATCH_VSXSEG6EI16V, MASK_VSXSEG6EI16V, match_vd_neq_vs2_neq_vm, INSN_DREF },
+-{"vlxseg7ei16.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),VtVm", MATCH_VLXSEG7EI16V, MASK_VLXSEG7EI16V, match_vd_neq_vs2_neq_vm, INSN_DREF },
+-{"vsxseg7ei16.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),VtVm", MATCH_VSXSEG7EI16V, MASK_VSXSEG7EI16V, match_vd_neq_vs2_neq_vm, INSN_DREF },
+-{"vlxseg8ei16.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),VtVm", MATCH_VLXSEG8EI16V, MASK_VLXSEG8EI16V, match_vd_neq_vs2_neq_vm, INSN_DREF },
+-{"vsxseg8ei16.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),VtVm", MATCH_VSXSEG8EI16V, MASK_VSXSEG8EI16V, match_vd_neq_vs2_neq_vm, INSN_DREF },
+-
+-{"vlxseg2ei32.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),VtVm", MATCH_VLXSEG2EI32V, MASK_VLXSEG2EI32V, match_vd_neq_vs2_neq_vm, INSN_DREF },
+-{"vsxseg2ei32.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),VtVm", MATCH_VSXSEG2EI32V, MASK_VSXSEG2EI32V, match_vd_neq_vs2_neq_vm, INSN_DREF },
+-{"vlxseg3ei32.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),VtVm", MATCH_VLXSEG3EI32V, MASK_VLXSEG3EI32V, match_vd_neq_vs2_neq_vm, INSN_DREF },
+-{"vsxseg3ei32.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),VtVm", MATCH_VSXSEG3EI32V, MASK_VSXSEG3EI32V, match_vd_neq_vs2_neq_vm, INSN_DREF },
+-{"vlxseg4ei32.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),VtVm", MATCH_VLXSEG4EI32V, MASK_VLXSEG4EI32V, match_vd_neq_vs2_neq_vm, INSN_DREF },
+-{"vsxseg4ei32.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),VtVm", MATCH_VSXSEG4EI32V, MASK_VSXSEG4EI32V, match_vd_neq_vs2_neq_vm, INSN_DREF },
+-{"vlxseg5ei32.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),VtVm", MATCH_VLXSEG5EI32V, MASK_VLXSEG5EI32V, match_vd_neq_vs2_neq_vm, INSN_DREF },
+-{"vsxseg5ei32.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),VtVm", MATCH_VSXSEG5EI32V, MASK_VSXSEG5EI32V, match_vd_neq_vs2_neq_vm, INSN_DREF },
+-{"vlxseg6ei32.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),VtVm", MATCH_VLXSEG6EI32V, MASK_VLXSEG6EI32V, match_vd_neq_vs2_neq_vm, INSN_DREF },
+-{"vsxseg6ei32.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),VtVm", MATCH_VSXSEG6EI32V, MASK_VSXSEG6EI32V, match_vd_neq_vs2_neq_vm, INSN_DREF },
+-{"vlxseg7ei32.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),VtVm", MATCH_VLXSEG7EI32V, MASK_VLXSEG7EI32V, match_vd_neq_vs2_neq_vm, INSN_DREF },
+-{"vsxseg7ei32.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),VtVm", MATCH_VSXSEG7EI32V, MASK_VSXSEG7EI32V, match_vd_neq_vs2_neq_vm, INSN_DREF },
+-{"vlxseg8ei32.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),VtVm", MATCH_VLXSEG8EI32V, MASK_VLXSEG8EI32V, match_vd_neq_vs2_neq_vm, INSN_DREF },
+-{"vsxseg8ei32.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),VtVm", MATCH_VSXSEG8EI32V, MASK_VSXSEG8EI32V, match_vd_neq_vs2_neq_vm, INSN_DREF },
+-
+-{"vlxseg2ei64.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),VtVm", MATCH_VLXSEG2EI64V, MASK_VLXSEG2EI64V, match_vd_neq_vs2_neq_vm, INSN_DREF },
+-{"vsxseg2ei64.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),VtVm", MATCH_VSXSEG2EI64V, MASK_VSXSEG2EI64V, match_vd_neq_vs2_neq_vm, INSN_DREF },
+-{"vlxseg3ei64.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),VtVm", MATCH_VLXSEG3EI64V, MASK_VLXSEG3EI64V, match_vd_neq_vs2_neq_vm, INSN_DREF },
+-{"vsxseg3ei64.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),VtVm", MATCH_VSXSEG3EI64V, MASK_VSXSEG3EI64V, match_vd_neq_vs2_neq_vm, INSN_DREF },
+-{"vlxseg4ei64.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),VtVm", MATCH_VLXSEG4EI64V, MASK_VLXSEG4EI64V, match_vd_neq_vs2_neq_vm, INSN_DREF },
+-{"vsxseg4ei64.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),VtVm", MATCH_VSXSEG4EI64V, MASK_VSXSEG4EI64V, match_vd_neq_vs2_neq_vm, INSN_DREF },
+-{"vlxseg5ei64.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),VtVm", MATCH_VLXSEG5EI64V, MASK_VLXSEG5EI64V, match_vd_neq_vs2_neq_vm, INSN_DREF },
+-{"vsxseg5ei64.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),VtVm", MATCH_VSXSEG5EI64V, MASK_VSXSEG5EI64V, match_vd_neq_vs2_neq_vm, INSN_DREF },
+-{"vlxseg6ei64.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),VtVm", MATCH_VLXSEG6EI64V, MASK_VLXSEG6EI64V, match_vd_neq_vs2_neq_vm, INSN_DREF },
+-{"vsxseg6ei64.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),VtVm", MATCH_VSXSEG6EI64V, MASK_VSXSEG6EI64V, match_vd_neq_vs2_neq_vm, INSN_DREF },
+-{"vlxseg7ei64.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),VtVm", MATCH_VLXSEG7EI64V, MASK_VLXSEG7EI64V, match_vd_neq_vs2_neq_vm, INSN_DREF },
+-{"vsxseg7ei64.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),VtVm", MATCH_VSXSEG7EI64V, MASK_VSXSEG7EI64V, match_vd_neq_vs2_neq_vm, INSN_DREF },
+-{"vlxseg8ei64.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),VtVm", MATCH_VLXSEG8EI64V, MASK_VLXSEG8EI64V, match_vd_neq_vs2_neq_vm, INSN_DREF },
+-{"vsxseg8ei64.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),VtVm", MATCH_VSXSEG8EI64V, MASK_VSXSEG8EI64V, match_vd_neq_vs2_neq_vm, INSN_DREF },
+-
+-{"vlxseg2ei128.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),VtVm", MATCH_VLXSEG2EI128V, MASK_VLXSEG2EI128V, match_vd_neq_vs2_neq_vm, INSN_DREF },
+-{"vsxseg2ei128.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),VtVm", MATCH_VSXSEG2EI128V, MASK_VSXSEG2EI128V, match_vd_neq_vs2_neq_vm, INSN_DREF },
+-{"vlxseg3ei128.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),VtVm", MATCH_VLXSEG3EI128V, MASK_VLXSEG3EI128V, match_vd_neq_vs2_neq_vm, INSN_DREF },
+-{"vsxseg3ei128.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),VtVm", MATCH_VSXSEG3EI128V, MASK_VSXSEG3EI128V, match_vd_neq_vs2_neq_vm, INSN_DREF },
+-{"vlxseg4ei128.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),VtVm", MATCH_VLXSEG4EI128V, MASK_VLXSEG4EI128V, match_vd_neq_vs2_neq_vm, INSN_DREF },
+-{"vsxseg4ei128.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),VtVm", MATCH_VSXSEG4EI128V, MASK_VSXSEG4EI128V, match_vd_neq_vs2_neq_vm, INSN_DREF },
+-{"vlxseg5ei128.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),VtVm", MATCH_VLXSEG5EI128V, MASK_VLXSEG5EI128V, match_vd_neq_vs2_neq_vm, INSN_DREF },
+-{"vsxseg5ei128.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),VtVm", MATCH_VSXSEG5EI128V, MASK_VSXSEG5EI128V, match_vd_neq_vs2_neq_vm, INSN_DREF },
+-{"vlxseg6ei128.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),VtVm", MATCH_VLXSEG6EI128V, MASK_VLXSEG6EI128V, match_vd_neq_vs2_neq_vm, INSN_DREF },
+-{"vsxseg6ei128.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),VtVm", MATCH_VSXSEG6EI128V, MASK_VSXSEG6EI128V, match_vd_neq_vs2_neq_vm, INSN_DREF },
+-{"vlxseg7ei128.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),VtVm", MATCH_VLXSEG7EI128V, MASK_VLXSEG7EI128V, match_vd_neq_vs2_neq_vm, INSN_DREF },
+-{"vsxseg7ei128.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),VtVm", MATCH_VSXSEG7EI128V, MASK_VSXSEG7EI128V, match_vd_neq_vs2_neq_vm, INSN_DREF },
+-{"vlxseg8ei128.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),VtVm", MATCH_VLXSEG8EI128V, MASK_VLXSEG8EI128V, match_vd_neq_vs2_neq_vm, INSN_DREF },
+-{"vsxseg8ei128.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),VtVm", MATCH_VSXSEG8EI128V, MASK_VSXSEG8EI128V, match_vd_neq_vs2_neq_vm, INSN_DREF },
+-
+-{"vlxseg2ei256.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),VtVm", MATCH_VLXSEG2EI256V, MASK_VLXSEG2EI256V, match_vd_neq_vs2_neq_vm, INSN_DREF },
+-{"vsxseg2ei256.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),VtVm", MATCH_VSXSEG2EI256V, MASK_VSXSEG2EI256V, match_vd_neq_vs2_neq_vm, INSN_DREF },
+-{"vlxseg3ei256.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),VtVm", MATCH_VLXSEG3EI256V, MASK_VLXSEG3EI256V, match_vd_neq_vs2_neq_vm, INSN_DREF },
+-{"vsxseg3ei256.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),VtVm", MATCH_VSXSEG3EI256V, MASK_VSXSEG3EI256V, match_vd_neq_vs2_neq_vm, INSN_DREF },
+-{"vlxseg4ei256.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),VtVm", MATCH_VLXSEG4EI256V, MASK_VLXSEG4EI256V, match_vd_neq_vs2_neq_vm, INSN_DREF },
+-{"vsxseg4ei256.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),VtVm", MATCH_VSXSEG4EI256V, MASK_VSXSEG4EI256V, match_vd_neq_vs2_neq_vm, INSN_DREF },
+-{"vlxseg5ei256.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),VtVm", MATCH_VLXSEG5EI256V, MASK_VLXSEG5EI256V, match_vd_neq_vs2_neq_vm, INSN_DREF },
+-{"vsxseg5ei256.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),VtVm", MATCH_VSXSEG5EI256V, MASK_VSXSEG5EI256V, match_vd_neq_vs2_neq_vm, INSN_DREF },
+-{"vlxseg6ei256.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),VtVm", MATCH_VLXSEG6EI256V, MASK_VLXSEG6EI256V, match_vd_neq_vs2_neq_vm, INSN_DREF },
+-{"vsxseg6ei256.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),VtVm", MATCH_VSXSEG6EI256V, MASK_VSXSEG6EI256V, match_vd_neq_vs2_neq_vm, INSN_DREF },
+-{"vlxseg7ei256.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),VtVm", MATCH_VLXSEG7EI256V, MASK_VLXSEG7EI256V, match_vd_neq_vs2_neq_vm, INSN_DREF },
+-{"vsxseg7ei256.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),VtVm", MATCH_VSXSEG7EI256V, MASK_VSXSEG7EI256V, match_vd_neq_vs2_neq_vm, INSN_DREF },
+-{"vlxseg8ei256.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),VtVm", MATCH_VLXSEG8EI256V, MASK_VLXSEG8EI256V, match_vd_neq_vs2_neq_vm, INSN_DREF },
+-{"vsxseg8ei256.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),VtVm", MATCH_VSXSEG8EI256V, MASK_VSXSEG8EI256V, match_vd_neq_vs2_neq_vm, INSN_DREF },
+-
+-{"vlxseg2ei512.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),VtVm", MATCH_VLXSEG2EI512V, MASK_VLXSEG2EI512V, match_vd_neq_vs2_neq_vm, INSN_DREF },
+-{"vsxseg2ei512.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),VtVm", MATCH_VSXSEG2EI512V, MASK_VSXSEG2EI512V, match_vd_neq_vs2_neq_vm, INSN_DREF },
+-{"vlxseg3ei512.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),VtVm", MATCH_VLXSEG3EI512V, MASK_VLXSEG3EI512V, match_vd_neq_vs2_neq_vm, INSN_DREF },
+-{"vsxseg3ei512.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),VtVm", MATCH_VSXSEG3EI512V, MASK_VSXSEG3EI512V, match_vd_neq_vs2_neq_vm, INSN_DREF },
+-{"vlxseg4ei512.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),VtVm", MATCH_VLXSEG4EI512V, MASK_VLXSEG4EI512V, match_vd_neq_vs2_neq_vm, INSN_DREF },
+-{"vsxseg4ei512.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),VtVm", MATCH_VSXSEG4EI512V, MASK_VSXSEG4EI512V, match_vd_neq_vs2_neq_vm, INSN_DREF },
+-{"vlxseg5ei512.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),VtVm", MATCH_VLXSEG5EI512V, MASK_VLXSEG5EI512V, match_vd_neq_vs2_neq_vm, INSN_DREF },
+-{"vsxseg5ei512.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),VtVm", MATCH_VSXSEG5EI512V, MASK_VSXSEG5EI512V, match_vd_neq_vs2_neq_vm, INSN_DREF },
+-{"vlxseg6ei512.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),VtVm", MATCH_VLXSEG6EI512V, MASK_VLXSEG6EI512V, match_vd_neq_vs2_neq_vm, INSN_DREF },
+-{"vsxseg6ei512.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),VtVm", MATCH_VSXSEG6EI512V, MASK_VSXSEG6EI512V, match_vd_neq_vs2_neq_vm, INSN_DREF },
+-{"vlxseg7ei512.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),VtVm", MATCH_VLXSEG7EI512V, MASK_VLXSEG7EI512V, match_vd_neq_vs2_neq_vm, INSN_DREF },
+-{"vsxseg7ei512.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),VtVm", MATCH_VSXSEG7EI512V, MASK_VSXSEG7EI512V, match_vd_neq_vs2_neq_vm, INSN_DREF },
+-{"vlxseg8ei512.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),VtVm", MATCH_VLXSEG8EI512V, MASK_VLXSEG8EI512V, match_vd_neq_vs2_neq_vm, INSN_DREF },
+-{"vsxseg8ei512.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),VtVm", MATCH_VSXSEG8EI512V, MASK_VSXSEG8EI512V, match_vd_neq_vs2_neq_vm, INSN_DREF },
+-
+-{"vlxseg2ei1024.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),VtVm", MATCH_VLXSEG2EI1024V, MASK_VLXSEG2EI1024V, match_vd_neq_vs2_neq_vm, INSN_DREF },
+-{"vsxseg2ei1024.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),VtVm", MATCH_VSXSEG2EI1024V, MASK_VSXSEG2EI1024V, match_vd_neq_vs2_neq_vm, INSN_DREF },
+-{"vlxseg3ei1024.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),VtVm", MATCH_VLXSEG3EI1024V, MASK_VLXSEG3EI1024V, match_vd_neq_vs2_neq_vm, INSN_DREF },
+-{"vsxseg3ei1024.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),VtVm", MATCH_VSXSEG3EI1024V, MASK_VSXSEG3EI1024V, match_vd_neq_vs2_neq_vm, INSN_DREF },
+-{"vlxseg4ei1024.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),VtVm", MATCH_VLXSEG4EI1024V, MASK_VLXSEG4EI1024V, match_vd_neq_vs2_neq_vm, INSN_DREF },
+-{"vsxseg4ei1024.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),VtVm", MATCH_VSXSEG4EI1024V, MASK_VSXSEG4EI1024V, match_vd_neq_vs2_neq_vm, INSN_DREF },
+-{"vlxseg5ei1024.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),VtVm", MATCH_VLXSEG5EI1024V, MASK_VLXSEG5EI1024V, match_vd_neq_vs2_neq_vm, INSN_DREF },
+-{"vsxseg5ei1024.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),VtVm", MATCH_VSXSEG5EI1024V, MASK_VSXSEG5EI1024V, match_vd_neq_vs2_neq_vm, INSN_DREF },
+-{"vlxseg6ei1024.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),VtVm", MATCH_VLXSEG6EI1024V, MASK_VLXSEG6EI1024V, match_vd_neq_vs2_neq_vm, INSN_DREF },
+-{"vsxseg6ei1024.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),VtVm", MATCH_VSXSEG6EI1024V, MASK_VSXSEG6EI1024V, match_vd_neq_vs2_neq_vm, INSN_DREF },
+-{"vlxseg7ei1024.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),VtVm", MATCH_VLXSEG7EI1024V, MASK_VLXSEG7EI1024V, match_vd_neq_vs2_neq_vm, INSN_DREF },
+-{"vsxseg7ei1024.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),VtVm", MATCH_VSXSEG7EI1024V, MASK_VSXSEG7EI1024V, match_vd_neq_vs2_neq_vm, INSN_DREF },
+-{"vlxseg8ei1024.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),VtVm", MATCH_VLXSEG8EI1024V, MASK_VLXSEG8EI1024V, match_vd_neq_vs2_neq_vm, INSN_DREF },
+-{"vsxseg8ei1024.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),VtVm", MATCH_VSXSEG8EI1024V, MASK_VSXSEG8EI1024V, match_vd_neq_vs2_neq_vm, INSN_DREF },
++{"vloxseg2ei8.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),VtVm", MATCH_VLOXSEG2EI8V, MASK_VLOXSEG2EI8V, match_vd_neq_vs2_neq_vm, INSN_DREF },
++{"vsoxseg2ei8.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),VtVm", MATCH_VSOXSEG2EI8V, MASK_VSOXSEG2EI8V, match_vd_neq_vs2_neq_vm, INSN_DREF },
++{"vloxseg3ei8.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),VtVm", MATCH_VLOXSEG3EI8V, MASK_VLOXSEG3EI8V, match_vd_neq_vs2_neq_vm, INSN_DREF },
++{"vsoxseg3ei8.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),VtVm", MATCH_VSOXSEG3EI8V, MASK_VSOXSEG3EI8V, match_vd_neq_vs2_neq_vm, INSN_DREF },
++{"vloxseg4ei8.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),VtVm", MATCH_VLOXSEG4EI8V, MASK_VLOXSEG4EI8V, match_vd_neq_vs2_neq_vm, INSN_DREF },
++{"vsoxseg4ei8.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),VtVm", MATCH_VSOXSEG4EI8V, MASK_VSOXSEG4EI8V, match_vd_neq_vs2_neq_vm, INSN_DREF },
++{"vloxseg5ei8.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),VtVm", MATCH_VLOXSEG5EI8V, MASK_VLOXSEG5EI8V, match_vd_neq_vs2_neq_vm, INSN_DREF },
++{"vsoxseg5ei8.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),VtVm", MATCH_VSOXSEG5EI8V, MASK_VSOXSEG5EI8V, match_vd_neq_vs2_neq_vm, INSN_DREF },
++{"vloxseg6ei8.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),VtVm", MATCH_VLOXSEG6EI8V, MASK_VLOXSEG6EI8V, match_vd_neq_vs2_neq_vm, INSN_DREF },
++{"vsoxseg6ei8.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),VtVm", MATCH_VSOXSEG6EI8V, MASK_VSOXSEG6EI8V, match_vd_neq_vs2_neq_vm, INSN_DREF },
++{"vloxseg7ei8.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),VtVm", MATCH_VLOXSEG7EI8V, MASK_VLOXSEG7EI8V, match_vd_neq_vs2_neq_vm, INSN_DREF },
++{"vsoxseg7ei8.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),VtVm", MATCH_VSOXSEG7EI8V, MASK_VSOXSEG7EI8V, match_vd_neq_vs2_neq_vm, INSN_DREF },
++{"vloxseg8ei8.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),VtVm", MATCH_VLOXSEG8EI8V, MASK_VLOXSEG8EI8V, match_vd_neq_vs2_neq_vm, INSN_DREF },
++{"vsoxseg8ei8.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),VtVm", MATCH_VSOXSEG8EI8V, MASK_VSOXSEG8EI8V, match_vd_neq_vs2_neq_vm, INSN_DREF },
++
++{"vloxseg2ei16.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),VtVm", MATCH_VLOXSEG2EI16V, MASK_VLOXSEG2EI16V, match_vd_neq_vs2_neq_vm, INSN_DREF },
++{"vsoxseg2ei16.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),VtVm", MATCH_VSOXSEG2EI16V, MASK_VSOXSEG2EI16V, match_vd_neq_vs2_neq_vm, INSN_DREF },
++{"vloxseg3ei16.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),VtVm", MATCH_VLOXSEG3EI16V, MASK_VLOXSEG3EI16V, match_vd_neq_vs2_neq_vm, INSN_DREF },
++{"vsoxseg3ei16.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),VtVm", MATCH_VSOXSEG3EI16V, MASK_VSOXSEG3EI16V, match_vd_neq_vs2_neq_vm, INSN_DREF },
++{"vloxseg4ei16.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),VtVm", MATCH_VLOXSEG4EI16V, MASK_VLOXSEG4EI16V, match_vd_neq_vs2_neq_vm, INSN_DREF },
++{"vsoxseg4ei16.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),VtVm", MATCH_VSOXSEG4EI16V, MASK_VSOXSEG4EI16V, match_vd_neq_vs2_neq_vm, INSN_DREF },
++{"vloxseg5ei16.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),VtVm", MATCH_VLOXSEG5EI16V, MASK_VLOXSEG5EI16V, match_vd_neq_vs2_neq_vm, INSN_DREF },
++{"vsoxseg5ei16.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),VtVm", MATCH_VSOXSEG5EI16V, MASK_VSOXSEG5EI16V, match_vd_neq_vs2_neq_vm, INSN_DREF },
++{"vloxseg6ei16.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),VtVm", MATCH_VLOXSEG6EI16V, MASK_VLOXSEG6EI16V, match_vd_neq_vs2_neq_vm, INSN_DREF },
++{"vsoxseg6ei16.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),VtVm", MATCH_VSOXSEG6EI16V, MASK_VSOXSEG6EI16V, match_vd_neq_vs2_neq_vm, INSN_DREF },
++{"vloxseg7ei16.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),VtVm", MATCH_VLOXSEG7EI16V, MASK_VLOXSEG7EI16V, match_vd_neq_vs2_neq_vm, INSN_DREF },
++{"vsoxseg7ei16.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),VtVm", MATCH_VSOXSEG7EI16V, MASK_VSOXSEG7EI16V, match_vd_neq_vs2_neq_vm, INSN_DREF },
++{"vloxseg8ei16.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),VtVm", MATCH_VLOXSEG8EI16V, MASK_VLOXSEG8EI16V, match_vd_neq_vs2_neq_vm, INSN_DREF },
++{"vsoxseg8ei16.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),VtVm", MATCH_VSOXSEG8EI16V, MASK_VSOXSEG8EI16V, match_vd_neq_vs2_neq_vm, INSN_DREF },
++
++{"vloxseg2ei32.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),VtVm", MATCH_VLOXSEG2EI32V, MASK_VLOXSEG2EI32V, match_vd_neq_vs2_neq_vm, INSN_DREF },
++{"vsoxseg2ei32.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),VtVm", MATCH_VSOXSEG2EI32V, MASK_VSOXSEG2EI32V, match_vd_neq_vs2_neq_vm, INSN_DREF },
++{"vloxseg3ei32.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),VtVm", MATCH_VLOXSEG3EI32V, MASK_VLOXSEG3EI32V, match_vd_neq_vs2_neq_vm, INSN_DREF },
++{"vsoxseg3ei32.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),VtVm", MATCH_VSOXSEG3EI32V, MASK_VSOXSEG3EI32V, match_vd_neq_vs2_neq_vm, INSN_DREF },
++{"vloxseg4ei32.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),VtVm", MATCH_VLOXSEG4EI32V, MASK_VLOXSEG4EI32V, match_vd_neq_vs2_neq_vm, INSN_DREF },
++{"vsoxseg4ei32.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),VtVm", MATCH_VSOXSEG4EI32V, MASK_VSOXSEG4EI32V, match_vd_neq_vs2_neq_vm, INSN_DREF },
++{"vloxseg5ei32.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),VtVm", MATCH_VLOXSEG5EI32V, MASK_VLOXSEG5EI32V, match_vd_neq_vs2_neq_vm, INSN_DREF },
++{"vsoxseg5ei32.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),VtVm", MATCH_VSOXSEG5EI32V, MASK_VSOXSEG5EI32V, match_vd_neq_vs2_neq_vm, INSN_DREF },
++{"vloxseg6ei32.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),VtVm", MATCH_VLOXSEG6EI32V, MASK_VLOXSEG6EI32V, match_vd_neq_vs2_neq_vm, INSN_DREF },
++{"vsoxseg6ei32.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),VtVm", MATCH_VSOXSEG6EI32V, MASK_VSOXSEG6EI32V, match_vd_neq_vs2_neq_vm, INSN_DREF },
++{"vloxseg7ei32.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),VtVm", MATCH_VLOXSEG7EI32V, MASK_VLOXSEG7EI32V, match_vd_neq_vs2_neq_vm, INSN_DREF },
++{"vsoxseg7ei32.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),VtVm", MATCH_VSOXSEG7EI32V, MASK_VSOXSEG7EI32V, match_vd_neq_vs2_neq_vm, INSN_DREF },
++{"vloxseg8ei32.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),VtVm", MATCH_VLOXSEG8EI32V, MASK_VLOXSEG8EI32V, match_vd_neq_vs2_neq_vm, INSN_DREF },
++{"vsoxseg8ei32.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),VtVm", MATCH_VSOXSEG8EI32V, MASK_VSOXSEG8EI32V, match_vd_neq_vs2_neq_vm, INSN_DREF },
++
++{"vloxseg2ei64.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),VtVm", MATCH_VLOXSEG2EI64V, MASK_VLOXSEG2EI64V, match_vd_neq_vs2_neq_vm, INSN_DREF },
++{"vsoxseg2ei64.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),VtVm", MATCH_VSOXSEG2EI64V, MASK_VSOXSEG2EI64V, match_vd_neq_vs2_neq_vm, INSN_DREF },
++{"vloxseg3ei64.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),VtVm", MATCH_VLOXSEG3EI64V, MASK_VLOXSEG3EI64V, match_vd_neq_vs2_neq_vm, INSN_DREF },
++{"vsoxseg3ei64.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),VtVm", MATCH_VSOXSEG3EI64V, MASK_VSOXSEG3EI64V, match_vd_neq_vs2_neq_vm, INSN_DREF },
++{"vloxseg4ei64.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),VtVm", MATCH_VLOXSEG4EI64V, MASK_VLOXSEG4EI64V, match_vd_neq_vs2_neq_vm, INSN_DREF },
++{"vsoxseg4ei64.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),VtVm", MATCH_VSOXSEG4EI64V, MASK_VSOXSEG4EI64V, match_vd_neq_vs2_neq_vm, INSN_DREF },
++{"vloxseg5ei64.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),VtVm", MATCH_VLOXSEG5EI64V, MASK_VLOXSEG5EI64V, match_vd_neq_vs2_neq_vm, INSN_DREF },
++{"vsoxseg5ei64.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),VtVm", MATCH_VSOXSEG5EI64V, MASK_VSOXSEG5EI64V, match_vd_neq_vs2_neq_vm, INSN_DREF },
++{"vloxseg6ei64.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),VtVm", MATCH_VLOXSEG6EI64V, MASK_VLOXSEG6EI64V, match_vd_neq_vs2_neq_vm, INSN_DREF },
++{"vsoxseg6ei64.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),VtVm", MATCH_VSOXSEG6EI64V, MASK_VSOXSEG6EI64V, match_vd_neq_vs2_neq_vm, INSN_DREF },
++{"vloxseg7ei64.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),VtVm", MATCH_VLOXSEG7EI64V, MASK_VLOXSEG7EI64V, match_vd_neq_vs2_neq_vm, INSN_DREF },
++{"vsoxseg7ei64.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),VtVm", MATCH_VSOXSEG7EI64V, MASK_VSOXSEG7EI64V, match_vd_neq_vs2_neq_vm, INSN_DREF },
++{"vloxseg8ei64.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),VtVm", MATCH_VLOXSEG8EI64V, MASK_VLOXSEG8EI64V, match_vd_neq_vs2_neq_vm, INSN_DREF },
++{"vsoxseg8ei64.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),VtVm", MATCH_VSOXSEG8EI64V, MASK_VSOXSEG8EI64V, match_vd_neq_vs2_neq_vm, INSN_DREF },
++
++{"vloxseg2ei128.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),VtVm", MATCH_VLOXSEG2EI128V, MASK_VLOXSEG2EI128V, match_vd_neq_vs2_neq_vm, INSN_DREF },
++{"vsoxseg2ei128.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),VtVm", MATCH_VSOXSEG2EI128V, MASK_VSOXSEG2EI128V, match_vd_neq_vs2_neq_vm, INSN_DREF },
++{"vloxseg3ei128.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),VtVm", MATCH_VLOXSEG3EI128V, MASK_VLOXSEG3EI128V, match_vd_neq_vs2_neq_vm, INSN_DREF },
++{"vsoxseg3ei128.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),VtVm", MATCH_VSOXSEG3EI128V, MASK_VSOXSEG3EI128V, match_vd_neq_vs2_neq_vm, INSN_DREF },
++{"vloxseg4ei128.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),VtVm", MATCH_VLOXSEG4EI128V, MASK_VLOXSEG4EI128V, match_vd_neq_vs2_neq_vm, INSN_DREF },
++{"vsoxseg4ei128.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),VtVm", MATCH_VSOXSEG4EI128V, MASK_VSOXSEG4EI128V, match_vd_neq_vs2_neq_vm, INSN_DREF },
++{"vloxseg5ei128.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),VtVm", MATCH_VLOXSEG5EI128V, MASK_VLOXSEG5EI128V, match_vd_neq_vs2_neq_vm, INSN_DREF },
++{"vsoxseg5ei128.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),VtVm", MATCH_VSOXSEG5EI128V, MASK_VSOXSEG5EI128V, match_vd_neq_vs2_neq_vm, INSN_DREF },
++{"vloxseg6ei128.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),VtVm", MATCH_VLOXSEG6EI128V, MASK_VLOXSEG6EI128V, match_vd_neq_vs2_neq_vm, INSN_DREF },
++{"vsoxseg6ei128.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),VtVm", MATCH_VSOXSEG6EI128V, MASK_VSOXSEG6EI128V, match_vd_neq_vs2_neq_vm, INSN_DREF },
++{"vloxseg7ei128.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),VtVm", MATCH_VLOXSEG7EI128V, MASK_VLOXSEG7EI128V, match_vd_neq_vs2_neq_vm, INSN_DREF },
++{"vsoxseg7ei128.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),VtVm", MATCH_VSOXSEG7EI128V, MASK_VSOXSEG7EI128V, match_vd_neq_vs2_neq_vm, INSN_DREF },
++{"vloxseg8ei128.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),VtVm", MATCH_VLOXSEG8EI128V, MASK_VLOXSEG8EI128V, match_vd_neq_vs2_neq_vm, INSN_DREF },
++{"vsoxseg8ei128.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),VtVm", MATCH_VSOXSEG8EI128V, MASK_VSOXSEG8EI128V, match_vd_neq_vs2_neq_vm, INSN_DREF },
++
++{"vloxseg2ei256.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),VtVm", MATCH_VLOXSEG2EI256V, MASK_VLOXSEG2EI256V, match_vd_neq_vs2_neq_vm, INSN_DREF },
++{"vsoxseg2ei256.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),VtVm", MATCH_VSOXSEG2EI256V, MASK_VSOXSEG2EI256V, match_vd_neq_vs2_neq_vm, INSN_DREF },
++{"vloxseg3ei256.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),VtVm", MATCH_VLOXSEG3EI256V, MASK_VLOXSEG3EI256V, match_vd_neq_vs2_neq_vm, INSN_DREF },
++{"vsoxseg3ei256.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),VtVm", MATCH_VSOXSEG3EI256V, MASK_VSOXSEG3EI256V, match_vd_neq_vs2_neq_vm, INSN_DREF },
++{"vloxseg4ei256.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),VtVm", MATCH_VLOXSEG4EI256V, MASK_VLOXSEG4EI256V, match_vd_neq_vs2_neq_vm, INSN_DREF },
++{"vsoxseg4ei256.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),VtVm", MATCH_VSOXSEG4EI256V, MASK_VSOXSEG4EI256V, match_vd_neq_vs2_neq_vm, INSN_DREF },
++{"vloxseg5ei256.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),VtVm", MATCH_VLOXSEG5EI256V, MASK_VLOXSEG5EI256V, match_vd_neq_vs2_neq_vm, INSN_DREF },
++{"vsoxseg5ei256.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),VtVm", MATCH_VSOXSEG5EI256V, MASK_VSOXSEG5EI256V, match_vd_neq_vs2_neq_vm, INSN_DREF },
++{"vloxseg6ei256.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),VtVm", MATCH_VLOXSEG6EI256V, MASK_VLOXSEG6EI256V, match_vd_neq_vs2_neq_vm, INSN_DREF },
++{"vsoxseg6ei256.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),VtVm", MATCH_VSOXSEG6EI256V, MASK_VSOXSEG6EI256V, match_vd_neq_vs2_neq_vm, INSN_DREF },
++{"vloxseg7ei256.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),VtVm", MATCH_VLOXSEG7EI256V, MASK_VLOXSEG7EI256V, match_vd_neq_vs2_neq_vm, INSN_DREF },
++{"vsoxseg7ei256.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),VtVm", MATCH_VSOXSEG7EI256V, MASK_VSOXSEG7EI256V, match_vd_neq_vs2_neq_vm, INSN_DREF },
++{"vloxseg8ei256.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),VtVm", MATCH_VLOXSEG8EI256V, MASK_VLOXSEG8EI256V, match_vd_neq_vs2_neq_vm, INSN_DREF },
++{"vsoxseg8ei256.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),VtVm", MATCH_VSOXSEG8EI256V, MASK_VSOXSEG8EI256V, match_vd_neq_vs2_neq_vm, INSN_DREF },
++
++{"vloxseg2ei512.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),VtVm", MATCH_VLOXSEG2EI512V, MASK_VLOXSEG2EI512V, match_vd_neq_vs2_neq_vm, INSN_DREF },
++{"vsoxseg2ei512.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),VtVm", MATCH_VSOXSEG2EI512V, MASK_VSOXSEG2EI512V, match_vd_neq_vs2_neq_vm, INSN_DREF },
++{"vloxseg3ei512.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),VtVm", MATCH_VLOXSEG3EI512V, MASK_VLOXSEG3EI512V, match_vd_neq_vs2_neq_vm, INSN_DREF },
++{"vsoxseg3ei512.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),VtVm", MATCH_VSOXSEG3EI512V, MASK_VSOXSEG3EI512V, match_vd_neq_vs2_neq_vm, INSN_DREF },
++{"vloxseg4ei512.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),VtVm", MATCH_VLOXSEG4EI512V, MASK_VLOXSEG4EI512V, match_vd_neq_vs2_neq_vm, INSN_DREF },
++{"vsoxseg4ei512.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),VtVm", MATCH_VSOXSEG4EI512V, MASK_VSOXSEG4EI512V, match_vd_neq_vs2_neq_vm, INSN_DREF },
++{"vloxseg5ei512.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),VtVm", MATCH_VLOXSEG5EI512V, MASK_VLOXSEG5EI512V, match_vd_neq_vs2_neq_vm, INSN_DREF },
++{"vsoxseg5ei512.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),VtVm", MATCH_VSOXSEG5EI512V, MASK_VSOXSEG5EI512V, match_vd_neq_vs2_neq_vm, INSN_DREF },
++{"vloxseg6ei512.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),VtVm", MATCH_VLOXSEG6EI512V, MASK_VLOXSEG6EI512V, match_vd_neq_vs2_neq_vm, INSN_DREF },
++{"vsoxseg6ei512.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),VtVm", MATCH_VSOXSEG6EI512V, MASK_VSOXSEG6EI512V, match_vd_neq_vs2_neq_vm, INSN_DREF },
++{"vloxseg7ei512.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),VtVm", MATCH_VLOXSEG7EI512V, MASK_VLOXSEG7EI512V, match_vd_neq_vs2_neq_vm, INSN_DREF },
++{"vsoxseg7ei512.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),VtVm", MATCH_VSOXSEG7EI512V, MASK_VSOXSEG7EI512V, match_vd_neq_vs2_neq_vm, INSN_DREF },
++{"vloxseg8ei512.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),VtVm", MATCH_VLOXSEG8EI512V, MASK_VLOXSEG8EI512V, match_vd_neq_vs2_neq_vm, INSN_DREF },
++{"vsoxseg8ei512.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),VtVm", MATCH_VSOXSEG8EI512V, MASK_VSOXSEG8EI512V, match_vd_neq_vs2_neq_vm, INSN_DREF },
++
++{"vloxseg2ei1024.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),VtVm", MATCH_VLOXSEG2EI1024V, MASK_VLOXSEG2EI1024V, match_vd_neq_vs2_neq_vm, INSN_DREF },
++{"vsoxseg2ei1024.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),VtVm", MATCH_VSOXSEG2EI1024V, MASK_VSOXSEG2EI1024V, match_vd_neq_vs2_neq_vm, INSN_DREF },
++{"vloxseg3ei1024.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),VtVm", MATCH_VLOXSEG3EI1024V, MASK_VLOXSEG3EI1024V, match_vd_neq_vs2_neq_vm, INSN_DREF },
++{"vsoxseg3ei1024.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),VtVm", MATCH_VSOXSEG3EI1024V, MASK_VSOXSEG3EI1024V, match_vd_neq_vs2_neq_vm, INSN_DREF },
++{"vloxseg4ei1024.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),VtVm", MATCH_VLOXSEG4EI1024V, MASK_VLOXSEG4EI1024V, match_vd_neq_vs2_neq_vm, INSN_DREF },
++{"vsoxseg4ei1024.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),VtVm", MATCH_VSOXSEG4EI1024V, MASK_VSOXSEG4EI1024V, match_vd_neq_vs2_neq_vm, INSN_DREF },
++{"vloxseg5ei1024.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),VtVm", MATCH_VLOXSEG5EI1024V, MASK_VLOXSEG5EI1024V, match_vd_neq_vs2_neq_vm, INSN_DREF },
++{"vsoxseg5ei1024.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),VtVm", MATCH_VSOXSEG5EI1024V, MASK_VSOXSEG5EI1024V, match_vd_neq_vs2_neq_vm, INSN_DREF },
++{"vloxseg6ei1024.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),VtVm", MATCH_VLOXSEG6EI1024V, MASK_VLOXSEG6EI1024V, match_vd_neq_vs2_neq_vm, INSN_DREF },
++{"vsoxseg6ei1024.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),VtVm", MATCH_VSOXSEG6EI1024V, MASK_VSOXSEG6EI1024V, match_vd_neq_vs2_neq_vm, INSN_DREF },
++{"vloxseg7ei1024.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),VtVm", MATCH_VLOXSEG7EI1024V, MASK_VLOXSEG7EI1024V, match_vd_neq_vs2_neq_vm, INSN_DREF },
++{"vsoxseg7ei1024.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),VtVm", MATCH_VSOXSEG7EI1024V, MASK_VSOXSEG7EI1024V, match_vd_neq_vs2_neq_vm, INSN_DREF },
++{"vloxseg8ei1024.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),VtVm", MATCH_VLOXSEG8EI1024V, MASK_VLOXSEG8EI1024V, match_vd_neq_vs2_neq_vm, INSN_DREF },
++{"vsoxseg8ei1024.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),VtVm", MATCH_VSOXSEG8EI1024V, MASK_VSOXSEG8EI1024V, match_vd_neq_vs2_neq_vm, INSN_DREF },
++
++{"vluxseg2ei8.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),VtVm", MATCH_VLUXSEG2EI8V, MASK_VLUXSEG2EI8V, match_vd_neq_vs2_neq_vm, INSN_DREF },
++{"vsuxseg2ei8.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),VtVm", MATCH_VSUXSEG2EI8V, MASK_VSUXSEG2EI8V, match_vd_neq_vs2_neq_vm, INSN_DREF },
++{"vluxseg3ei8.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),VtVm", MATCH_VLUXSEG3EI8V, MASK_VLUXSEG3EI8V, match_vd_neq_vs2_neq_vm, INSN_DREF },
++{"vsuxseg3ei8.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),VtVm", MATCH_VSUXSEG3EI8V, MASK_VSUXSEG3EI8V, match_vd_neq_vs2_neq_vm, INSN_DREF },
++{"vluxseg4ei8.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),VtVm", MATCH_VLUXSEG4EI8V, MASK_VLUXSEG4EI8V, match_vd_neq_vs2_neq_vm, INSN_DREF },
++{"vsuxseg4ei8.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),VtVm", MATCH_VSUXSEG4EI8V, MASK_VSUXSEG4EI8V, match_vd_neq_vs2_neq_vm, INSN_DREF },
++{"vluxseg5ei8.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),VtVm", MATCH_VLUXSEG5EI8V, MASK_VLUXSEG5EI8V, match_vd_neq_vs2_neq_vm, INSN_DREF },
++{"vsuxseg5ei8.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),VtVm", MATCH_VSUXSEG5EI8V, MASK_VSUXSEG5EI8V, match_vd_neq_vs2_neq_vm, INSN_DREF },
++{"vluxseg6ei8.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),VtVm", MATCH_VLUXSEG6EI8V, MASK_VLUXSEG6EI8V, match_vd_neq_vs2_neq_vm, INSN_DREF },
++{"vsuxseg6ei8.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),VtVm", MATCH_VSUXSEG6EI8V, MASK_VSUXSEG6EI8V, match_vd_neq_vs2_neq_vm, INSN_DREF },
++{"vluxseg7ei8.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),VtVm", MATCH_VLUXSEG7EI8V, MASK_VLUXSEG7EI8V, match_vd_neq_vs2_neq_vm, INSN_DREF },
++{"vsuxseg7ei8.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),VtVm", MATCH_VSUXSEG7EI8V, MASK_VSUXSEG7EI8V, match_vd_neq_vs2_neq_vm, INSN_DREF },
++{"vluxseg8ei8.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),VtVm", MATCH_VLUXSEG8EI8V, MASK_VLUXSEG8EI8V, match_vd_neq_vs2_neq_vm, INSN_DREF },
++{"vsuxseg8ei8.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),VtVm", MATCH_VSUXSEG8EI8V, MASK_VSUXSEG8EI8V, match_vd_neq_vs2_neq_vm, INSN_DREF },
++
++{"vluxseg2ei16.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),VtVm", MATCH_VLUXSEG2EI16V, MASK_VLUXSEG2EI16V, match_vd_neq_vs2_neq_vm, INSN_DREF },
++{"vsuxseg2ei16.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),VtVm", MATCH_VSUXSEG2EI16V, MASK_VSUXSEG2EI16V, match_vd_neq_vs2_neq_vm, INSN_DREF },
++{"vluxseg3ei16.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),VtVm", MATCH_VLUXSEG3EI16V, MASK_VLUXSEG3EI16V, match_vd_neq_vs2_neq_vm, INSN_DREF },
++{"vsuxseg3ei16.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),VtVm", MATCH_VSUXSEG3EI16V, MASK_VSUXSEG3EI16V, match_vd_neq_vs2_neq_vm, INSN_DREF },
++{"vluxseg4ei16.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),VtVm", MATCH_VLUXSEG4EI16V, MASK_VLUXSEG4EI16V, match_vd_neq_vs2_neq_vm, INSN_DREF },
++{"vsuxseg4ei16.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),VtVm", MATCH_VSUXSEG4EI16V, MASK_VSUXSEG4EI16V, match_vd_neq_vs2_neq_vm, INSN_DREF },
++{"vluxseg5ei16.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),VtVm", MATCH_VLUXSEG5EI16V, MASK_VLUXSEG5EI16V, match_vd_neq_vs2_neq_vm, INSN_DREF },
++{"vsuxseg5ei16.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),VtVm", MATCH_VSUXSEG5EI16V, MASK_VSUXSEG5EI16V, match_vd_neq_vs2_neq_vm, INSN_DREF },
++{"vluxseg6ei16.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),VtVm", MATCH_VLUXSEG6EI16V, MASK_VLUXSEG6EI16V, match_vd_neq_vs2_neq_vm, INSN_DREF },
++{"vsuxseg6ei16.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),VtVm", MATCH_VSUXSEG6EI16V, MASK_VSUXSEG6EI16V, match_vd_neq_vs2_neq_vm, INSN_DREF },
++{"vluxseg7ei16.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),VtVm", MATCH_VLUXSEG7EI16V, MASK_VLUXSEG7EI16V, match_vd_neq_vs2_neq_vm, INSN_DREF },
++{"vsuxseg7ei16.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),VtVm", MATCH_VSUXSEG7EI16V, MASK_VSUXSEG7EI16V, match_vd_neq_vs2_neq_vm, INSN_DREF },
++{"vluxseg8ei16.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),VtVm", MATCH_VLUXSEG8EI16V, MASK_VLUXSEG8EI16V, match_vd_neq_vs2_neq_vm, INSN_DREF },
++{"vsuxseg8ei16.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),VtVm", MATCH_VSUXSEG8EI16V, MASK_VSUXSEG8EI16V, match_vd_neq_vs2_neq_vm, INSN_DREF },
++
++{"vluxseg2ei32.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),VtVm", MATCH_VLUXSEG2EI32V, MASK_VLUXSEG2EI32V, match_vd_neq_vs2_neq_vm, INSN_DREF },
++{"vsuxseg2ei32.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),VtVm", MATCH_VSUXSEG2EI32V, MASK_VSUXSEG2EI32V, match_vd_neq_vs2_neq_vm, INSN_DREF },
++{"vluxseg3ei32.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),VtVm", MATCH_VLUXSEG3EI32V, MASK_VLUXSEG3EI32V, match_vd_neq_vs2_neq_vm, INSN_DREF },
++{"vsuxseg3ei32.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),VtVm", MATCH_VSUXSEG3EI32V, MASK_VSUXSEG3EI32V, match_vd_neq_vs2_neq_vm, INSN_DREF },
++{"vluxseg4ei32.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),VtVm", MATCH_VLUXSEG4EI32V, MASK_VLUXSEG4EI32V, match_vd_neq_vs2_neq_vm, INSN_DREF },
++{"vsuxseg4ei32.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),VtVm", MATCH_VSUXSEG4EI32V, MASK_VSUXSEG4EI32V, match_vd_neq_vs2_neq_vm, INSN_DREF },
++{"vluxseg5ei32.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),VtVm", MATCH_VLUXSEG5EI32V, MASK_VLUXSEG5EI32V, match_vd_neq_vs2_neq_vm, INSN_DREF },
++{"vsuxseg5ei32.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),VtVm", MATCH_VSUXSEG5EI32V, MASK_VSUXSEG5EI32V, match_vd_neq_vs2_neq_vm, INSN_DREF },
++{"vluxseg6ei32.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),VtVm", MATCH_VLUXSEG6EI32V, MASK_VLUXSEG6EI32V, match_vd_neq_vs2_neq_vm, INSN_DREF },
++{"vsuxseg6ei32.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),VtVm", MATCH_VSUXSEG6EI32V, MASK_VSUXSEG6EI32V, match_vd_neq_vs2_neq_vm, INSN_DREF },
++{"vluxseg7ei32.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),VtVm", MATCH_VLUXSEG7EI32V, MASK_VLUXSEG7EI32V, match_vd_neq_vs2_neq_vm, INSN_DREF },
++{"vsuxseg7ei32.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),VtVm", MATCH_VSUXSEG7EI32V, MASK_VSUXSEG7EI32V, match_vd_neq_vs2_neq_vm, INSN_DREF },
++{"vluxseg8ei32.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),VtVm", MATCH_VLUXSEG8EI32V, MASK_VLUXSEG8EI32V, match_vd_neq_vs2_neq_vm, INSN_DREF },
++{"vsuxseg8ei32.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),VtVm", MATCH_VSUXSEG8EI32V, MASK_VSUXSEG8EI32V, match_vd_neq_vs2_neq_vm, INSN_DREF },
++
++{"vluxseg2ei64.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),VtVm", MATCH_VLUXSEG2EI64V, MASK_VLUXSEG2EI64V, match_vd_neq_vs2_neq_vm, INSN_DREF },
++{"vsuxseg2ei64.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),VtVm", MATCH_VSUXSEG2EI64V, MASK_VSUXSEG2EI64V, match_vd_neq_vs2_neq_vm, INSN_DREF },
++{"vluxseg3ei64.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),VtVm", MATCH_VLUXSEG3EI64V, MASK_VLUXSEG3EI64V, match_vd_neq_vs2_neq_vm, INSN_DREF },
++{"vsuxseg3ei64.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),VtVm", MATCH_VSUXSEG3EI64V, MASK_VSUXSEG3EI64V, match_vd_neq_vs2_neq_vm, INSN_DREF },
++{"vluxseg4ei64.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),VtVm", MATCH_VLUXSEG4EI64V, MASK_VLUXSEG4EI64V, match_vd_neq_vs2_neq_vm, INSN_DREF },
++{"vsuxseg4ei64.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),VtVm", MATCH_VSUXSEG4EI64V, MASK_VSUXSEG4EI64V, match_vd_neq_vs2_neq_vm, INSN_DREF },
++{"vluxseg5ei64.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),VtVm", MATCH_VLUXSEG5EI64V, MASK_VLUXSEG5EI64V, match_vd_neq_vs2_neq_vm, INSN_DREF },
++{"vsuxseg5ei64.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),VtVm", MATCH_VSUXSEG5EI64V, MASK_VSUXSEG5EI64V, match_vd_neq_vs2_neq_vm, INSN_DREF },
++{"vluxseg6ei64.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),VtVm", MATCH_VLUXSEG6EI64V, MASK_VLUXSEG6EI64V, match_vd_neq_vs2_neq_vm, INSN_DREF },
++{"vsuxseg6ei64.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),VtVm", MATCH_VSUXSEG6EI64V, MASK_VSUXSEG6EI64V, match_vd_neq_vs2_neq_vm, INSN_DREF },
++{"vluxseg7ei64.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),VtVm", MATCH_VLUXSEG7EI64V, MASK_VLUXSEG7EI64V, match_vd_neq_vs2_neq_vm, INSN_DREF },
++{"vsuxseg7ei64.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),VtVm", MATCH_VSUXSEG7EI64V, MASK_VSUXSEG7EI64V, match_vd_neq_vs2_neq_vm, INSN_DREF },
++{"vluxseg8ei64.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),VtVm", MATCH_VLUXSEG8EI64V, MASK_VLUXSEG8EI64V, match_vd_neq_vs2_neq_vm, INSN_DREF },
++{"vsuxseg8ei64.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),VtVm", MATCH_VSUXSEG8EI64V, MASK_VSUXSEG8EI64V, match_vd_neq_vs2_neq_vm, INSN_DREF },
++
++{"vluxseg2ei128.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),VtVm", MATCH_VLUXSEG2EI128V, MASK_VLUXSEG2EI128V, match_vd_neq_vs2_neq_vm, INSN_DREF },
++{"vsuxseg2ei128.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),VtVm", MATCH_VSUXSEG2EI128V, MASK_VSUXSEG2EI128V, match_vd_neq_vs2_neq_vm, INSN_DREF },
++{"vluxseg3ei128.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),VtVm", MATCH_VLUXSEG3EI128V, MASK_VLUXSEG3EI128V, match_vd_neq_vs2_neq_vm, INSN_DREF },
++{"vsuxseg3ei128.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),VtVm", MATCH_VSUXSEG3EI128V, MASK_VSUXSEG3EI128V, match_vd_neq_vs2_neq_vm, INSN_DREF },
++{"vluxseg4ei128.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),VtVm", MATCH_VLUXSEG4EI128V, MASK_VLUXSEG4EI128V, match_vd_neq_vs2_neq_vm, INSN_DREF },
++{"vsuxseg4ei128.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),VtVm", MATCH_VSUXSEG4EI128V, MASK_VSUXSEG4EI128V, match_vd_neq_vs2_neq_vm, INSN_DREF },
++{"vluxseg5ei128.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),VtVm", MATCH_VLUXSEG5EI128V, MASK_VLUXSEG5EI128V, match_vd_neq_vs2_neq_vm, INSN_DREF },
++{"vsuxseg5ei128.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),VtVm", MATCH_VSUXSEG5EI128V, MASK_VSUXSEG5EI128V, match_vd_neq_vs2_neq_vm, INSN_DREF },
++{"vluxseg6ei128.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),VtVm", MATCH_VLUXSEG6EI128V, MASK_VLUXSEG6EI128V, match_vd_neq_vs2_neq_vm, INSN_DREF },
++{"vsuxseg6ei128.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),VtVm", MATCH_VSUXSEG6EI128V, MASK_VSUXSEG6EI128V, match_vd_neq_vs2_neq_vm, INSN_DREF },
++{"vluxseg7ei128.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),VtVm", MATCH_VLUXSEG7EI128V, MASK_VLUXSEG7EI128V, match_vd_neq_vs2_neq_vm, INSN_DREF },
++{"vsuxseg7ei128.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),VtVm", MATCH_VSUXSEG7EI128V, MASK_VSUXSEG7EI128V, match_vd_neq_vs2_neq_vm, INSN_DREF },
++{"vluxseg8ei128.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),VtVm", MATCH_VLUXSEG8EI128V, MASK_VLUXSEG8EI128V, match_vd_neq_vs2_neq_vm, INSN_DREF },
++{"vsuxseg8ei128.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),VtVm", MATCH_VSUXSEG8EI128V, MASK_VSUXSEG8EI128V, match_vd_neq_vs2_neq_vm, INSN_DREF },
++
++{"vluxseg2ei256.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),VtVm", MATCH_VLUXSEG2EI256V, MASK_VLUXSEG2EI256V, match_vd_neq_vs2_neq_vm, INSN_DREF },
++{"vsuxseg2ei256.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),VtVm", MATCH_VSUXSEG2EI256V, MASK_VSUXSEG2EI256V, match_vd_neq_vs2_neq_vm, INSN_DREF },
++{"vluxseg3ei256.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),VtVm", MATCH_VLUXSEG3EI256V, MASK_VLUXSEG3EI256V, match_vd_neq_vs2_neq_vm, INSN_DREF },
++{"vsuxseg3ei256.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),VtVm", MATCH_VSUXSEG3EI256V, MASK_VSUXSEG3EI256V, match_vd_neq_vs2_neq_vm, INSN_DREF },
++{"vluxseg4ei256.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),VtVm", MATCH_VLUXSEG4EI256V, MASK_VLUXSEG4EI256V, match_vd_neq_vs2_neq_vm, INSN_DREF },
++{"vsuxseg4ei256.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),VtVm", MATCH_VSUXSEG4EI256V, MASK_VSUXSEG4EI256V, match_vd_neq_vs2_neq_vm, INSN_DREF },
++{"vluxseg5ei256.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),VtVm", MATCH_VLUXSEG5EI256V, MASK_VLUXSEG5EI256V, match_vd_neq_vs2_neq_vm, INSN_DREF },
++{"vsuxseg5ei256.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),VtVm", MATCH_VSUXSEG5EI256V, MASK_VSUXSEG5EI256V, match_vd_neq_vs2_neq_vm, INSN_DREF },
++{"vluxseg6ei256.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),VtVm", MATCH_VLUXSEG6EI256V, MASK_VLUXSEG6EI256V, match_vd_neq_vs2_neq_vm, INSN_DREF },
++{"vsuxseg6ei256.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),VtVm", MATCH_VSUXSEG6EI256V, MASK_VSUXSEG6EI256V, match_vd_neq_vs2_neq_vm, INSN_DREF },
++{"vluxseg7ei256.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),VtVm", MATCH_VLUXSEG7EI256V, MASK_VLUXSEG7EI256V, match_vd_neq_vs2_neq_vm, INSN_DREF },
++{"vsuxseg7ei256.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),VtVm", MATCH_VSUXSEG7EI256V, MASK_VSUXSEG7EI256V, match_vd_neq_vs2_neq_vm, INSN_DREF },
++{"vluxseg8ei256.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),VtVm", MATCH_VLUXSEG8EI256V, MASK_VLUXSEG8EI256V, match_vd_neq_vs2_neq_vm, INSN_DREF },
++{"vsuxseg8ei256.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),VtVm", MATCH_VSUXSEG8EI256V, MASK_VSUXSEG8EI256V, match_vd_neq_vs2_neq_vm, INSN_DREF },
++
++{"vluxseg2ei512.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),VtVm", MATCH_VLUXSEG2EI512V, MASK_VLUXSEG2EI512V, match_vd_neq_vs2_neq_vm, INSN_DREF },
++{"vsuxseg2ei512.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),VtVm", MATCH_VSUXSEG2EI512V, MASK_VSUXSEG2EI512V, match_vd_neq_vs2_neq_vm, INSN_DREF },
++{"vluxseg3ei512.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),VtVm", MATCH_VLUXSEG3EI512V, MASK_VLUXSEG3EI512V, match_vd_neq_vs2_neq_vm, INSN_DREF },
++{"vsuxseg3ei512.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),VtVm", MATCH_VSUXSEG3EI512V, MASK_VSUXSEG3EI512V, match_vd_neq_vs2_neq_vm, INSN_DREF },
++{"vluxseg4ei512.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),VtVm", MATCH_VLUXSEG4EI512V, MASK_VLUXSEG4EI512V, match_vd_neq_vs2_neq_vm, INSN_DREF },
++{"vsuxseg4ei512.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),VtVm", MATCH_VSUXSEG4EI512V, MASK_VSUXSEG4EI512V, match_vd_neq_vs2_neq_vm, INSN_DREF },
++{"vluxseg5ei512.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),VtVm", MATCH_VLUXSEG5EI512V, MASK_VLUXSEG5EI512V, match_vd_neq_vs2_neq_vm, INSN_DREF },
++{"vsuxseg5ei512.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),VtVm", MATCH_VSUXSEG5EI512V, MASK_VSUXSEG5EI512V, match_vd_neq_vs2_neq_vm, INSN_DREF },
++{"vluxseg6ei512.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),VtVm", MATCH_VLUXSEG6EI512V, MASK_VLUXSEG6EI512V, match_vd_neq_vs2_neq_vm, INSN_DREF },
++{"vsuxseg6ei512.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),VtVm", MATCH_VSUXSEG6EI512V, MASK_VSUXSEG6EI512V, match_vd_neq_vs2_neq_vm, INSN_DREF },
++{"vluxseg7ei512.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),VtVm", MATCH_VLUXSEG7EI512V, MASK_VLUXSEG7EI512V, match_vd_neq_vs2_neq_vm, INSN_DREF },
++{"vsuxseg7ei512.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),VtVm", MATCH_VSUXSEG7EI512V, MASK_VSUXSEG7EI512V, match_vd_neq_vs2_neq_vm, INSN_DREF },
++{"vluxseg8ei512.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),VtVm", MATCH_VLUXSEG8EI512V, MASK_VLUXSEG8EI512V, match_vd_neq_vs2_neq_vm, INSN_DREF },
++{"vsuxseg8ei512.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),VtVm", MATCH_VSUXSEG8EI512V, MASK_VSUXSEG8EI512V, match_vd_neq_vs2_neq_vm, INSN_DREF },
++
++{"vluxseg2ei1024.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),VtVm", MATCH_VLUXSEG2EI1024V, MASK_VLUXSEG2EI1024V, match_vd_neq_vs2_neq_vm, INSN_DREF },
++{"vsuxseg2ei1024.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),VtVm", MATCH_VSUXSEG2EI1024V, MASK_VSUXSEG2EI1024V, match_vd_neq_vs2_neq_vm, INSN_DREF },
++{"vluxseg3ei1024.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),VtVm", MATCH_VLUXSEG3EI1024V, MASK_VLUXSEG3EI1024V, match_vd_neq_vs2_neq_vm, INSN_DREF },
++{"vsuxseg3ei1024.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),VtVm", MATCH_VSUXSEG3EI1024V, MASK_VSUXSEG3EI1024V, match_vd_neq_vs2_neq_vm, INSN_DREF },
++{"vluxseg4ei1024.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),VtVm", MATCH_VLUXSEG4EI1024V, MASK_VLUXSEG4EI1024V, match_vd_neq_vs2_neq_vm, INSN_DREF },
++{"vsuxseg4ei1024.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),VtVm", MATCH_VSUXSEG4EI1024V, MASK_VSUXSEG4EI1024V, match_vd_neq_vs2_neq_vm, INSN_DREF },
++{"vluxseg5ei1024.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),VtVm", MATCH_VLUXSEG5EI1024V, MASK_VLUXSEG5EI1024V, match_vd_neq_vs2_neq_vm, INSN_DREF },
++{"vsuxseg5ei1024.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),VtVm", MATCH_VSUXSEG5EI1024V, MASK_VSUXSEG5EI1024V, match_vd_neq_vs2_neq_vm, INSN_DREF },
++{"vluxseg6ei1024.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),VtVm", MATCH_VLUXSEG6EI1024V, MASK_VLUXSEG6EI1024V, match_vd_neq_vs2_neq_vm, INSN_DREF },
++{"vsuxseg6ei1024.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),VtVm", MATCH_VSUXSEG6EI1024V, MASK_VSUXSEG6EI1024V, match_vd_neq_vs2_neq_vm, INSN_DREF },
++{"vluxseg7ei1024.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),VtVm", MATCH_VLUXSEG7EI1024V, MASK_VLUXSEG7EI1024V, match_vd_neq_vs2_neq_vm, INSN_DREF },
++{"vsuxseg7ei1024.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),VtVm", MATCH_VSUXSEG7EI1024V, MASK_VSUXSEG7EI1024V, match_vd_neq_vs2_neq_vm, INSN_DREF },
++{"vluxseg8ei1024.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),VtVm", MATCH_VLUXSEG8EI1024V, MASK_VLUXSEG8EI1024V, match_vd_neq_vs2_neq_vm, INSN_DREF },
++{"vsuxseg8ei1024.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),VtVm", MATCH_VSUXSEG8EI1024V, MASK_VSUXSEG8EI1024V, match_vd_neq_vs2_neq_vm, INSN_DREF },
+ 
+ {"vlseg2e8ff.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s)Vm", MATCH_VLSEG2E8FFV, MASK_VLSEG2E8FFV, match_vd_neq_vm, INSN_DREF },
+ {"vlseg3e8ff.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s)Vm", MATCH_VLSEG3E8FFV, MASK_VLSEG3E8FFV, match_vd_neq_vm, INSN_DREF },
+-- 
+2.33.0
+

+ 112 - 0
recipes-devtools/gdb/files/0033-RISC-V-Rename-vncvt.x.x.v-to-vncvt.x.x.w.patch

@@ -0,0 +1,112 @@
+From 661ff3b85995c4bd23f90074270685d1eb79ca4e Mon Sep 17 00:00:00 2001
+From: Nelson Chu <nelson.chu@sifive.com>
+Date: Mon, 7 Dec 2020 01:46:08 -0800
+Subject: [PATCH 33/48] RISC-V: Rename vncvt.x.x.v to vncvt.x.x.w.
+
+---
+ .../gas/riscv/vector-insns-fail-arith-narrow.l         |  8 ++++----
+ .../gas/riscv/vector-insns-fail-arith-narrow.s         | 10 +++++-----
+ gas/testsuite/gas/riscv/vector-insns.d                 |  4 ++--
+ gas/testsuite/gas/riscv/vector-insns.s                 |  4 ++--
+ include/opcode/riscv-opc.h                             |  4 ++--
+ opcodes/riscv-opc.c                                    |  2 +-
+ 6 files changed, 16 insertions(+), 16 deletions(-)
+
+diff --git a/gas/testsuite/gas/riscv/vector-insns-fail-arith-narrow.l b/gas/testsuite/gas/riscv/vector-insns-fail-arith-narrow.l
+index defca03d6d..3a3634cd09 100644
+--- a/gas/testsuite/gas/riscv/vector-insns-fail-arith-narrow.l
++++ b/gas/testsuite/gas/riscv/vector-insns-fail-arith-narrow.l
+@@ -1,8 +1,8 @@
+ .*: Assembler messages:
+-.*Error: illegal operands vd cannot overlap vs2 `vncvt.x.x.v v2,v2'
+-.*Error: illegal operands vd must be multiple of 2 `vncvt.x.x.v v2,v3'
+-.*Error: illegal operands vd cannot overlap vs2 `vncvt.x.x.v v3,v2'
+-.*Error: illegal operands vd cannot overlap vm `vncvt.x.x.v v0,v2,v0.t'
++.*Error: illegal operands vd cannot overlap vs2 `vncvt.x.x.w v2,v2'
++.*Error: illegal operands vd must be multiple of 2 `vncvt.x.x.w v2,v3'
++.*Error: illegal operands vd cannot overlap vs2 `vncvt.x.x.w v3,v2'
++.*Error: illegal operands vd cannot overlap vm `vncvt.x.x.w v0,v2,v0.t'
+ .*Error: illegal operands vd cannot overlap vs2 `vnsrl.wv v2,v2,v4'
+ .*Error: illegal operands vd must be multiple of 2 `vnsrl.wv v2,v3,v4'
+ .*Error: illegal operands vd cannot overlap vs2 `vnsrl.wv v3,v2,v4'
+diff --git a/gas/testsuite/gas/riscv/vector-insns-fail-arith-narrow.s b/gas/testsuite/gas/riscv/vector-insns-fail-arith-narrow.s
+index a843d076ff..73b96ef800 100644
+--- a/gas/testsuite/gas/riscv/vector-insns-fail-arith-narrow.s
++++ b/gas/testsuite/gas/riscv/vector-insns-fail-arith-narrow.s
+@@ -1,10 +1,10 @@
+ # Vector Narrowing Integer Right Shift Instructions
+ 
+-	# vncvt.x.x.v vd,vs,vm = vnsrl.wx vd,vs,x0,vm
+-	vncvt.x.x.v v2, v2		# vd overlap vs2
+-	vncvt.x.x.v v2, v3		# vs2 should be multiple of 2
+-	vncvt.x.x.v v3, v2		# vd overlap vs2
+-	vncvt.x.x.v v0, v2, v0.t	# vd overlap vm
++	# vncvt.x.x.w vd,vs,vm = vnsrl.wx vd,vs,x0,vm
++	vncvt.x.x.w v2, v2		# vd overlap vs2
++	vncvt.x.x.w v2, v3		# vs2 should be multiple of 2
++	vncvt.x.x.w v3, v2		# vd overlap vs2
++	vncvt.x.x.w v0, v2, v0.t	# vd overlap vm
+ 
+ 	vnsrl.wv v2, v2, v4		# vd overlap vs2
+ 	vnsrl.wv v2, v3, v4		# vs2 should be multiple of 2
+diff --git a/gas/testsuite/gas/riscv/vector-insns.d b/gas/testsuite/gas/riscv/vector-insns.d
+index d8a8aa6d09..865ec7644e 100644
+--- a/gas/testsuite/gas/riscv/vector-insns.d
++++ b/gas/testsuite/gas/riscv/vector-insns.d
+@@ -2210,8 +2210,8 @@ Disassembly of section .text:
+ [ 	]+[0-9a-f]+:[ 	]+a485c257[ 	]+vsra.vx[ 	]+v4,v8,a1,v0.t
+ [ 	]+[0-9a-f]+:[ 	]+a480b257[ 	]+vsra.vi[ 	]+v4,v8,1,v0.t
+ [ 	]+[0-9a-f]+:[ 	]+a48fb257[ 	]+vsra.vi[ 	]+v4,v8,31,v0.t
+-[ 	]+[0-9a-f]+:[ 	]+b2804257[ 	]+vncvt.x.x.v[ 	]+v4,v8
+-[ 	]+[0-9a-f]+:[ 	]+b0804257[ 	]+vncvt.x.x.v[ 	]+v4,v8,v0.t
++[ 	]+[0-9a-f]+:[ 	]+b2804257[ 	]+vncvt.x.x.w[ 	]+v4,v8
++[ 	]+[0-9a-f]+:[ 	]+b0804257[ 	]+vncvt.x.x.w[ 	]+v4,v8,v0.t
+ [ 	]+[0-9a-f]+:[ 	]+b2860257[ 	]+vnsrl.wv[ 	]+v4,v8,v12
+ [ 	]+[0-9a-f]+:[ 	]+b285c257[ 	]+vnsrl.wx[ 	]+v4,v8,a1
+ [ 	]+[0-9a-f]+:[ 	]+b280b257[ 	]+vnsrl.wi[ 	]+v4,v8,1
+diff --git a/gas/testsuite/gas/riscv/vector-insns.s b/gas/testsuite/gas/riscv/vector-insns.s
+index 5431863af9..204088151e 100644
+--- a/gas/testsuite/gas/riscv/vector-insns.s
++++ b/gas/testsuite/gas/riscv/vector-insns.s
+@@ -2551,8 +2551,8 @@
+ 	vsra.vi v4, v8, 31, v0.t
+ 
+ 	# Aliases
+-	vncvt.x.x.v v4, v8
+-	vncvt.x.x.v v4, v8, v0.t
++	vncvt.x.x.w v4, v8
++	vncvt.x.x.w v4, v8, v0.t
+ 
+ 	vnsrl.wv v4, v8, v12
+ 	vnsrl.wx v4, v8, a1
+diff --git a/include/opcode/riscv-opc.h b/include/opcode/riscv-opc.h
+index d74d3d5044..2355f14b73 100644
+--- a/include/opcode/riscv-opc.h
++++ b/include/opcode/riscv-opc.h
+@@ -2474,8 +2474,8 @@ funct6 VM  VS2  VS1/RS1/IMM funct3 VD   opcode
+ #define MATCH_VSRAVI 0xa4003057
+ #define MASK_VSRAVI  0xfc00707f
+ 
+-#define MATCH_VNCVTXXV 0xb0004057
+-#define MASK_VNCVTXXV  0xfc0ff07f
++#define MATCH_VNCVTXXW 0xb0004057
++#define MASK_VNCVTXXW  0xfc0ff07f
+ 
+ #define MATCH_VNSRLWV  0xb0000057
+ #define MASK_VNSRLWV   0xfc00707f
+diff --git a/opcodes/riscv-opc.c b/opcodes/riscv-opc.c
+index 076aea5f91..7b258ee982 100644
+--- a/opcodes/riscv-opc.c
++++ b/opcodes/riscv-opc.c
+@@ -2040,7 +2040,7 @@ const struct riscv_opcode riscv_opcodes[] =
+ {"vsra.vx",    0, INSN_CLASS_V,  "Vd,Vt,sVm", MATCH_VSRAVX, MASK_VSRAVX, match_vd_neq_vm, 0 },
+ {"vsra.vi",    0, INSN_CLASS_V,  "Vd,Vt,VjVm", MATCH_VSRAVI, MASK_VSRAVI, match_vd_neq_vm, 0 },
+ 
+-{"vncvt.x.x.v",0, INSN_CLASS_V,  "Vd,VtVm", MATCH_VNCVTXXV, MASK_VNCVTXXV, match_narrow_vd_neq_vs2_neq_vm, INSN_ALIAS },
++{"vncvt.x.x.w",0, INSN_CLASS_V,  "Vd,VtVm", MATCH_VNCVTXXW, MASK_VNCVTXXW, match_narrow_vd_neq_vs2_neq_vm, INSN_ALIAS },
+ 
+ {"vnsrl.wv",   0, INSN_CLASS_V,  "Vd,Vt,VsVm", MATCH_VNSRLWV, MASK_VNSRLWV, match_narrow_vd_neq_vs2_neq_vm, 0 },
+ {"vnsrl.wx",   0, INSN_CLASS_V,  "Vd,Vt,sVm", MATCH_VNSRLWX, MASK_VNSRLWX, match_narrow_vd_neq_vs2_neq_vm, 0 },
+-- 
+2.33.0
+

+ 120 - 0
recipes-devtools/gdb/files/0034-SiFive-Support-SiFive-CLIC-CSRs.patch

@@ -0,0 +1,120 @@
+From c85da1a9c3aaf77bc803e06404594d6f38845da3 Mon Sep 17 00:00:00 2001
+From: Jim Wilson <jimw@sifive.com>
+Date: Thu, 21 Feb 2019 19:21:23 -0800
+Subject: [PATCH 34/48] SiFive: Support SiFive CLIC CSRs.
+
+---
+ gas/config/tc-riscv.c                            | 1 +
+ gas/testsuite/gas/riscv/priv-reg-version-1p10.d  | 4 ++++
+ gas/testsuite/gas/riscv/priv-reg-version-1p11.d  | 4 ++++
+ gas/testsuite/gas/riscv/priv-reg-version-1p9p1.d | 4 ++++
+ gas/testsuite/gas/riscv/priv-reg.s               | 6 ++++++
+ include/opcode/riscv-opc.h                       | 8 ++++++++
+ include/opcode/riscv.h                           | 3 ++-
+ 7 files changed, 29 insertions(+), 1 deletion(-)
+
+diff --git a/gas/config/tc-riscv.c b/gas/config/tc-riscv.c
+index 57d2908fcd..44e9358dd7 100644
+--- a/gas/config/tc-riscv.c
++++ b/gas/config/tc-riscv.c
+@@ -729,6 +729,7 @@ riscv_csr_address (const char *csr_name,
+       need_check_version = FALSE;
+       break;
+     case CSR_CLASS_DEBUG:
++    case CSR_CLASS_CLIC:
+       need_check_version = FALSE;
+       break;
+     default:
+diff --git a/gas/testsuite/gas/riscv/priv-reg-version-1p10.d b/gas/testsuite/gas/riscv/priv-reg-version-1p10.d
+index 0a023ea5a2..2db8d2021e 100644
+--- a/gas/testsuite/gas/riscv/priv-reg-version-1p10.d
++++ b/gas/testsuite/gas/riscv/priv-reg-version-1p10.d
+@@ -272,3 +272,7 @@ Disassembly of section .text:
+ [     	]+[0-9a-f]+:[  	]+7a102573[    	]+csrr[        	]+a0,tdata1
+ [     	]+[0-9a-f]+:[  	]+7a302573[    	]+csrr[        	]+a0,tdata3
+ [     	]+[0-9a-f]+:[  	]+7a302573[    	]+csrr[        	]+a0,tdata3
++[     	]+[0-9a-f]+:[  	]+30702573[    	]+csrr[        	]+a0,mtvt
++[     	]+[0-9a-f]+:[  	]+34502573[    	]+csrr[        	]+a0,mnxti
++[     	]+[0-9a-f]+:[  	]+34602573[    	]+csrr[        	]+a0,mintstatus
++[     	]+[0-9a-f]+:[  	]+34811173[    	]+csrrw[        	]+sp,mscratchcsw,sp
+diff --git a/gas/testsuite/gas/riscv/priv-reg-version-1p11.d b/gas/testsuite/gas/riscv/priv-reg-version-1p11.d
+index 5956b0d9fd..77ed98891c 100644
+--- a/gas/testsuite/gas/riscv/priv-reg-version-1p11.d
++++ b/gas/testsuite/gas/riscv/priv-reg-version-1p11.d
+@@ -272,3 +272,7 @@ Disassembly of section .text:
+ [     	]+[0-9a-f]+:[  	]+7a102573[    	]+csrr[        	]+a0,tdata1
+ [     	]+[0-9a-f]+:[  	]+7a302573[    	]+csrr[        	]+a0,tdata3
+ [     	]+[0-9a-f]+:[  	]+7a302573[    	]+csrr[        	]+a0,tdata3
++[     	]+[0-9a-f]+:[  	]+30702573[    	]+csrr[        	]+a0,mtvt
++[     	]+[0-9a-f]+:[  	]+34502573[    	]+csrr[        	]+a0,mnxti
++[     	]+[0-9a-f]+:[  	]+34602573[    	]+csrr[        	]+a0,mintstatus
++[     	]+[0-9a-f]+:[  	]+34811173[    	]+csrrw[        	]+sp,mscratchcsw,sp
+diff --git a/gas/testsuite/gas/riscv/priv-reg-version-1p9p1.d b/gas/testsuite/gas/riscv/priv-reg-version-1p9p1.d
+index 3fea56d947..7e1515f8be 100644
+--- a/gas/testsuite/gas/riscv/priv-reg-version-1p9p1.d
++++ b/gas/testsuite/gas/riscv/priv-reg-version-1p9p1.d
+@@ -272,3 +272,7 @@ Disassembly of section .text:
+ [     	]+[0-9a-f]+:[  	]+7a102573[    	]+csrr[        	]+a0,tdata1
+ [     	]+[0-9a-f]+:[  	]+7a302573[    	]+csrr[        	]+a0,tdata3
+ [     	]+[0-9a-f]+:[  	]+7a302573[    	]+csrr[        	]+a0,tdata3
++[     	]+[0-9a-f]+:[  	]+30702573[    	]+csrr[        	]+a0,mtvt
++[     	]+[0-9a-f]+:[  	]+34502573[    	]+csrr[        	]+a0,mnxti
++[     	]+[0-9a-f]+:[  	]+34602573[    	]+csrr[        	]+a0,mintstatus
++[     	]+[0-9a-f]+:[  	]+34811173[    	]+csrrw[        	]+sp,mscratchcsw,sp
+diff --git a/gas/testsuite/gas/riscv/priv-reg.s b/gas/testsuite/gas/riscv/priv-reg.s
+index 8f625054c1..bce7d00b81 100644
+--- a/gas/testsuite/gas/riscv/priv-reg.s
++++ b/gas/testsuite/gas/riscv/priv-reg.s
+@@ -291,3 +291,9 @@
+ 	csr etrigger		# 0x7a1, alias to tdata1
+ 	csr textra32		# 0x7a3, alias to tdata3
+ 	csr textra64		# 0x7a3, alias to tdata3
++
++	# CLIC registers
++	csr mtvt
++	csr mnxti
++	csr mintstatus
++	csrrw sp,mscratchcsw,sp
+diff --git a/include/opcode/riscv-opc.h b/include/opcode/riscv-opc.h
+index 2355f14b73..66e3f8f652 100644
+--- a/include/opcode/riscv-opc.h
++++ b/include/opcode/riscv-opc.h
+@@ -3348,6 +3348,10 @@ funct6 VM  VS2  VS1/RS1/IMM funct3 VD   opcode
+ #define CSR_TCONTROL 0x7a5
+ #define CSR_MCONTEXT 0x7a8
+ #define CSR_SCONTEXT 0x7aa
++#define CSR_MTVT 0x307
++#define CSR_MNXTI 0x345
++#define CSR_MINTSTATUS 0x346
++#define CSR_MSCRATCHCSW 0x348
+ #endif /* RISCV_ENCODING_H.  */
+ #ifdef DECLARE_INSN
+ DECLARE_INSN(slli_rv32, MATCH_SLLI_RV32, MASK_SLLI_RV32)
+@@ -3926,6 +3930,10 @@ DECLARE_CSR(tinfo, CSR_TINFO, CSR_CLASS_DEBUG, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_C
+ DECLARE_CSR(tcontrol, CSR_TCONTROL, CSR_CLASS_DEBUG, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE)
+ DECLARE_CSR(mcontext, CSR_MCONTEXT, CSR_CLASS_DEBUG, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE)
+ DECLARE_CSR(scontext, CSR_SCONTEXT, CSR_CLASS_DEBUG, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE)
++DECLARE_CSR(mtvt, CSR_MTVT, CSR_CLASS_CLIC, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE)
++DECLARE_CSR(mnxti, CSR_MNXTI, CSR_CLASS_CLIC, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE)
++DECLARE_CSR(mintstatus, CSR_MINTSTATUS, CSR_CLASS_CLIC, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE)
++DECLARE_CSR(mscratchcsw, CSR_MSCRATCHCSW, CSR_CLASS_CLIC, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE)
+ #endif /* DECLARE_CSR.  */
+ #ifdef DECLARE_CSR_ALIAS
+ DECLARE_CSR_ALIAS(ubadaddr, CSR_UTVAL, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_1P10)
+diff --git a/include/opcode/riscv.h b/include/opcode/riscv.h
+index 31bdcf95a9..2e1a665c6b 100644
+--- a/include/opcode/riscv.h
++++ b/include/opcode/riscv.h
+@@ -460,7 +460,8 @@ enum riscv_csr_class
+   CSR_CLASS_I_32,      /* rv32 only */
+   CSR_CLASS_F,         /* f-ext only */
+   CSR_CLASS_V,         /* v-ext only */
+-  CSR_CLASS_DEBUG      /* debug CSR */
++  CSR_CLASS_DEBUG,     /* debug CSR */
++  CSR_CLASS_CLIC       /* clic CSR */
+ };
+ 
+ /* The current supported privilege spec versions.  */
+-- 
+2.33.0
+

+ 105 - 0
recipes-devtools/gdb/files/0035-SiFive-Support-SiFive-specific-cache-control-instruc.patch

@@ -0,0 +1,105 @@
+From 2f7ac1fcdd1dda2c8a097ccf34e9c49482b8b781 Mon Sep 17 00:00:00 2001
+From: Nelson Chu <nelson.chu@sifive.com>
+Date: Fri, 31 Jan 2020 14:47:51 +0800
+Subject: [PATCH 35/48] SiFive: Support SiFive specific cache control
+ instructions.
+
+There are three cache control instructions,
+1. CFLUSH.D.L1   RS1
+2. CDISCARD.D.L1 RS1
+3. CFLUSH.I.L1
+
+These instructions use the same funct3 0x0 [14:12].  CFLUSH.D.L1 use 0xfc000073
+opcode (0xfc0 [31:20] + 0x0 [11:7] + SYSTEM OP [6:2] + 0x3 [1:0]) with optional
+rs1.  CDISCARD.D.L1 use 0xfc200073 opcode (0xfc2 [31:20], ...) with optional
+rs1.  CFLUSH.I.L1 use 0xfc100073 opcode.
+---
+ gas/testsuite/gas/riscv/cache-control.d | 15 +++++++++++++++
+ gas/testsuite/gas/riscv/cache-control.s |  7 +++++++
+ include/opcode/riscv-opc.h              | 10 ++++++++++
+ opcodes/riscv-opc.c                     |  5 +++++
+ 4 files changed, 37 insertions(+)
+ create mode 100644 gas/testsuite/gas/riscv/cache-control.d
+ create mode 100644 gas/testsuite/gas/riscv/cache-control.s
+
+diff --git a/gas/testsuite/gas/riscv/cache-control.d b/gas/testsuite/gas/riscv/cache-control.d
+new file mode 100644
+index 0000000000..b3c3be4a4d
+--- /dev/null
++++ b/gas/testsuite/gas/riscv/cache-control.d
+@@ -0,0 +1,15 @@
++#as: -march=rv32i
++#objdump: -dr
++
++.*:[ 	]+file format .*
++
++
++Disassembly of section .text:
++
++0+000 <.text>:
++[ 	]+0:[ 	]+fc050073[ 	]+cflush.d.l1[ 	]+a0
++[ 	]+4:[ 	]+fc250073[ 	]+cdiscard.d.l1[ 	]+a0
++[ 	]+8:[ 	]+fc100073[ 	]+cflush.i.l1
++[ 	]+c:[ 	]+fc050073[ 	]+cflush.d.l1[ 	]+a0
++[ 	]+10:[ 	]+fc250073[ 	]+cdiscard.d.l1[ 	]+a0
++[ 	]+14:[ 	]+fc100073[ 	]+cflush.i.l1
+diff --git a/gas/testsuite/gas/riscv/cache-control.s b/gas/testsuite/gas/riscv/cache-control.s
+new file mode 100644
+index 0000000000..354bca169a
+--- /dev/null
++++ b/gas/testsuite/gas/riscv/cache-control.s
+@@ -0,0 +1,7 @@
++	.insn i 0x73, 0, x0, x10, -0x40
++	.insn i 0x73, 0, x0, x10, -0x3E
++	.insn i 0x73, 0, x0, x0,  -0x3F
++
++	cflush.d.l1   x10
++	cdiscard.d.l1 x10
++	cflush.i.l1
+diff --git a/include/opcode/riscv-opc.h b/include/opcode/riscv-opc.h
+index 66e3f8f652..545bda3ed4 100644
+--- a/include/opcode/riscv-opc.h
++++ b/include/opcode/riscv-opc.h
+@@ -3094,6 +3094,13 @@ funct6 VM  VS2  VS1/RS1/IMM funct3 VD   opcode
+ #define MASK_CUSTOM3_RD_RS1  0x707f
+ #define MATCH_CUSTOM3_RD_RS1_RS2 0x707b
+ #define MASK_CUSTOM3_RD_RS1_RS2  0x707f
++/* SiFive specific cache control instruction.  */
++#define MATCH_CFLUSH_D_L1   0xfc000073
++#define MASK_CFLUSH_D_L1    0xfff07fff
++#define MATCH_CDISCARD_D_L1 0xfc200073
++#define MASK_CDISCARD_D_L1  0xfff07fff
++#define MATCH_CFLUSH_I_L1   0xfc100073
++#define MASK_CFLUSH_I_L1    0xffffffff
+ /* Privileged CSR addresses (v1.11).  */
+ #define CSR_USTATUS 0x0
+ #define CSR_UIE 0x4
+@@ -3673,6 +3680,9 @@ DECLARE_INSN(custom3_rs1_rs2, MATCH_CUSTOM3_RS1_RS2, MASK_CUSTOM3_RS1_RS2)
+ DECLARE_INSN(custom3_rd, MATCH_CUSTOM3_RD, MASK_CUSTOM3_RD)
+ DECLARE_INSN(custom3_rd_rs1, MATCH_CUSTOM3_RD_RS1, MASK_CUSTOM3_RD_RS1)
+ DECLARE_INSN(custom3_rd_rs1_rs2, MATCH_CUSTOM3_RD_RS1_RS2, MASK_CUSTOM3_RD_RS1_RS2)
++DECLARE_INSN(cflush_d_l1, MATCH_CFLUSH_D_L1, MASK_CFLUSH_D_L1)
++DECLARE_INSN(cdiscard_d_l1, MATCH_CDISCARD_D_L1, MASK_CDISCARD_D_L1)
++DECLARE_INSN(cflush_i_l1, MATCH_CFLUSH_I_L1, MASK_CFLUSH_I_L1)
+ #endif /* DECLARE_INSN.  */
+ #ifdef DECLARE_CSR
+ /* Privileged.  */
+diff --git a/opcodes/riscv-opc.c b/opcodes/riscv-opc.c
+index 7b258ee982..778c5d2f45 100644
+--- a/opcodes/riscv-opc.c
++++ b/opcodes/riscv-opc.c
+@@ -1267,6 +1267,11 @@ const struct riscv_opcode riscv_opcodes[] =
+ {"sfence.vma", 0, INSN_CLASS_I,   "s,t",  MATCH_SFENCE_VMA, MASK_SFENCE_VMA, match_opcode, 0 },
+ {"wfi",        0, INSN_CLASS_I,   "",     MATCH_WFI, MASK_WFI, match_opcode, 0 },
+ 
++/* SiFive specific cache control instruction.  */
++{"cflush.d.l1",   0, INSN_CLASS_I,   "s",  MATCH_CFLUSH_D_L1, MASK_CFLUSH_D_L1, match_opcode, 0 },
++{"cdiscard.d.l1", 0, INSN_CLASS_I,   "s",  MATCH_CDISCARD_D_L1, MASK_CDISCARD_D_L1, match_opcode, 0 },
++{"cflush.i.l1",   0, INSN_CLASS_I,   "",   MATCH_CFLUSH_I_L1, MASK_CFLUSH_I_L1, match_opcode, 0 },
++
+ /* RVV */
+ {"vsetvl",     0, INSN_CLASS_V,  "d,s,t", MATCH_VSETVL, MASK_VSETVL, match_opcode, 0},
+ {"vsetvli",    0, INSN_CLASS_V,  "d,s,Vc", MATCH_VSETVLI, MASK_VSETVLI, match_opcode, 0},
+-- 
+2.33.0
+

+ 995 - 0
recipes-devtools/gdb/files/0036-Initial-support-for-RISC-V-Bitmanip-Spec-0.92.patch

@@ -0,0 +1,995 @@
+From e69ed899f726c9d15c1afeab89de7a8fe2009156 Mon Sep 17 00:00:00 2001
+From: Clifford Wolf <clifford@clifford.at>
+Date: Sun, 11 Aug 2019 14:33:43 +0200
+Subject: [PATCH 36/48] Initial support for RISC-V Bitmanip Spec 0.92
+
+Signed-off-by: Clifford Wolf <clifford@clifford.at>
+---
+ gas/config/tc-riscv.c                         | 149 ++++++++
+ include/opcode/riscv-opc.h                    | 318 ++++++++++++++++++
+ include/opcode/riscv.h                        |  16 +
+ .../ld-riscv-elf/attr-dupl-arch-z-failed-01.d |   3 +
+ .../ld-riscv-elf/attr-dupl-arch-z-failed-01.s |   1 +
+ .../attr-merge-arch-z-failed-01.d             |   5 +
+ .../attr-merge-arch-z-failed-01a.s            |   1 +
+ .../attr-merge-arch-z-failed-01b.s            |   1 +
+ .../attr-order-arch-z-failed-01.d             |   3 +
+ .../attr-order-arch-z-failed-01.s             |   1 +
+ .../attr-order-arch-z-failed-02.d             |   3 +
+ .../attr-order-arch-z-failed-02.s             |   1 +
+ .../attr-tooshort-arch-z-failed-01.d          |   3 +
+ .../attr-tooshort-arch-z-failed-01.s          |   1 +
+ .../attr-unknown-arch-z-failed-01.d           |   3 +
+ .../attr-unknown-arch-z-failed-01.s           |   1 +
+ ld/testsuite/ld-riscv-elf/ld-riscv-elf.exp    |   6 +
+ opcodes/riscv-dis.c                           |   7 +
+ opcodes/riscv-opc.c                           | 214 ++++++++++++
+ 19 files changed, 737 insertions(+)
+ create mode 100644 ld/testsuite/ld-riscv-elf/attr-dupl-arch-z-failed-01.d
+ create mode 100644 ld/testsuite/ld-riscv-elf/attr-dupl-arch-z-failed-01.s
+ create mode 100644 ld/testsuite/ld-riscv-elf/attr-merge-arch-z-failed-01.d
+ create mode 100644 ld/testsuite/ld-riscv-elf/attr-merge-arch-z-failed-01a.s
+ create mode 100644 ld/testsuite/ld-riscv-elf/attr-merge-arch-z-failed-01b.s
+ create mode 100644 ld/testsuite/ld-riscv-elf/attr-order-arch-z-failed-01.d
+ create mode 100644 ld/testsuite/ld-riscv-elf/attr-order-arch-z-failed-01.s
+ create mode 100644 ld/testsuite/ld-riscv-elf/attr-order-arch-z-failed-02.d
+ create mode 100644 ld/testsuite/ld-riscv-elf/attr-order-arch-z-failed-02.s
+ create mode 100644 ld/testsuite/ld-riscv-elf/attr-tooshort-arch-z-failed-01.d
+ create mode 100644 ld/testsuite/ld-riscv-elf/attr-tooshort-arch-z-failed-01.s
+ create mode 100644 ld/testsuite/ld-riscv-elf/attr-unknown-arch-z-failed-01.d
+ create mode 100644 ld/testsuite/ld-riscv-elf/attr-unknown-arch-z-failed-01.s
+
+diff --git a/gas/config/tc-riscv.c b/gas/config/tc-riscv.c
+index 44e9358dd7..b53442b8b4 100644
+--- a/gas/config/tc-riscv.c
++++ b/gas/config/tc-riscv.c
+@@ -260,6 +260,40 @@ riscv_multi_subset_supports (enum riscv_insn_class insn_class)
+     case INSN_CLASS_V_AND_ZVQMAC:
+       return riscv_subset_supports ("v") && riscv_subset_supports ("zvqmac");
+ 
++    case INSN_CLASS_B_OR_ZBB:
++      return riscv_subset_supports ("b") || riscv_subset_supports ("zbb");
++
++    case INSN_CLASS_B_OR_ZBA:
++      return riscv_subset_supports ("b") || riscv_subset_supports ("zba");
++
++    case INSN_CLASS_B_OR_ZBC:
++      return riscv_subset_supports ("b") || riscv_subset_supports ("zbc");
++
++    case INSN_CLASS_B_OR_ZBE:
++      return riscv_subset_supports ("b") || riscv_subset_supports ("zbe");
++
++    case INSN_CLASS_B_OR_ZBF:
++      return riscv_subset_supports ("b") || riscv_subset_supports ("zbf");
++
++    case INSN_CLASS_B_OR_ZBM:
++      return riscv_subset_supports ("b") || riscv_subset_supports ("zbm");
++
++    case INSN_CLASS_B_OR_ZBP:
++      return riscv_subset_supports ("b") || riscv_subset_supports ("zbp");
++
++    case INSN_CLASS_B_OR_ZBR:
++      return riscv_subset_supports ("b") || riscv_subset_supports ("zbr");
++
++    case INSN_CLASS_B_OR_ZBS:
++      return riscv_subset_supports ("b") || riscv_subset_supports ("zbs");
++
++    case INSN_CLASS_B_OR_ZBT:
++      return riscv_subset_supports ("b") || riscv_subset_supports ("zbt");
++
++    case INSN_CLASS_B_OR_ZBB_OR_ZBP:
++      return riscv_subset_supports ("b") || riscv_subset_supports ("zbb")
++	|| riscv_subset_supports ("zbp");
++
+     default:
+       as_fatal ("Unreachable");
+       return FALSE;
+@@ -948,6 +982,7 @@ validate_riscv_insn (const struct riscv_opcode *opc, int length)
+       case '(': break;
+       case ')': break;
+       case '<': USE_BITS (OP_MASK_SHAMTW,	OP_SH_SHAMTW);	break;
++      case '|': USE_BITS (OP_MASK_SHAMTW,	OP_SH_SHAMTW);	break;
+       case '>':	USE_BITS (OP_MASK_SHAMT,	OP_SH_SHAMT);	break;
+       case 'A': break;
+       case 'D':	USE_BITS (OP_MASK_RD,		OP_SH_RD);	break;
+@@ -1250,6 +1285,15 @@ macro_build (expressionS *ep, const char *name, const char *fmt, ...)
+ 	  INSERT_OPERAND (RS2, insn, va_arg (args, int));
+ 	  continue;
+ 
++	case 'r':
++	  INSERT_OPERAND (RS3, insn, va_arg (args, int));
++	  continue;
++
++	case '<':
++	case '|':
++	  INSERT_OPERAND (SHAMTW, insn, va_arg (args, int));
++	  continue;
++
+ 	case '>':
+ 	  INSERT_OPERAND (SHAMT, insn, va_arg (args, int));
+ 	  continue;
+@@ -1465,6 +1509,86 @@ load_const (int reg, expressionS *ep)
+     }
+ }
+ 
++/* Immediate rotate left shift via right shift.  */
++
++static void
++rotate_left (int rd, int rs, unsigned shamt, unsigned this_xlen)
++{
++  shamt = (this_xlen-1) & -shamt;
++
++  if (this_xlen == xlen)
++    macro_build (NULL, "rori", "d,s,>", rd, rs, shamt);
++  else if (this_xlen == 32)
++    macro_build (NULL, "roriw", "d,s,<", rd, rs, shamt);
++  else
++    as_fatal (_("internal error: bad left shift xlen %d"), this_xlen);
++}
++
++static void
++funnel_left (int rd, int rs1, int rs3, unsigned shamt, unsigned this_xlen)
++{
++  shamt = (this_xlen-1) & -shamt;
++
++  if (this_xlen == xlen)
++    macro_build (NULL, "fsri", "d,s,r,>", rd, rs3, rs1, shamt);
++  else if (this_xlen == 32)
++    macro_build (NULL, "fsriw", "d,s,r,<", rd, rs3, rs1, shamt);
++  else
++    as_fatal (_("internal error: bad left shift xlen %d"), this_xlen);
++}
++
++static void
++perm (int rd, int rs1, const char *op)
++{
++  const char *insn = NULL;
++  const char *p = op;
++  int shamt = 0;
++  int shfl = 0;
++
++  switch (p[0])
++    {
++    case 'r': insn = "grevi";   shamt = xlen-1;   p += 3; break;
++    case 'o': insn = "gorci";   shamt = xlen-1;   p += 3; break;
++    case 'z': insn = "shfli";   shamt = xlen/2-1; p += 3; shfl = 1; break;
++    case 'u': insn = "unshfli"; shamt = xlen/2-1; p += 5; shfl = 1; break;
++    default: as_fatal (_("internal error: bad permutation pseudo-instruction %s"), op);
++    }
++
++  switch (p[0])
++    {
++    case '2': shamt &= shamt << 1; p += 1; break;
++    case '4': shamt &= shamt << 2; p += 1; break;
++    case '8': shamt &= shamt << 3; p += 1; break;
++    case '1': shamt &= shamt << 4; p += 2; break;
++    case '3': shamt &= shamt << 5; p += 2;
++    }
++
++  if (p[0])
++    {
++      if (shfl)
++        switch (p[1])
++          {
++          case 'w': shamt &= 15; break;
++          case 'h': shamt &=  7; break;
++          case 'b': shamt &=  3; break;
++          case 'n': shamt &=  1; break;
++          default: as_fatal (_("internal error: bad permutation pseudo-instruction %s"), op);
++          }
++      else
++        switch (p[1])
++          {
++          case 'w': shamt &= 31; break;
++          case 'h': shamt &= 15; break;
++          case 'b': shamt &=  7; break;
++          case 'n': shamt &=  3; break;
++          case 'p': shamt &=  1; break;
++          default: as_fatal (_("internal error: bad permutation pseudo-instruction %s"), op);
++          }
++    }
++
++  macro_build (NULL, insn, "d,s,>", rd, rs1, shamt);
++}
++
+ /* Expand RISC-V Vector macros into one of more instructions.  */
+ 
+ static void
+@@ -1563,6 +1687,8 @@ macro (struct riscv_cl_insn *ip, expressionS *imm_expr,
+   int rd = (ip->insn_opcode >> OP_SH_RD) & OP_MASK_RD;
+   int rs1 = (ip->insn_opcode >> OP_SH_RS1) & OP_MASK_RS1;
+   int rs2 = (ip->insn_opcode >> OP_SH_RS2) & OP_MASK_RS2;
++  int rs3 = (ip->insn_opcode >> OP_SH_RS3) & OP_MASK_RS3;
++  int shamt = (ip->insn_opcode >> OP_SH_SHAMT) & OP_MASK_SHAMT;
+   int mask = ip->insn_mo->mask;
+ 
+   switch (mask)
+@@ -1571,6 +1697,18 @@ macro (struct riscv_cl_insn *ip, expressionS *imm_expr,
+       load_const (rd, imm_expr);
+       break;
+ 
++    case M_RL:
++      rotate_left (rd, rs1, shamt, ip->insn_mo->xlen_requirement ? ip->insn_mo->xlen_requirement/2 : xlen);
++      break;
++
++    case M_FL:
++      funnel_left (rd, rs1, rs3, shamt, ip->insn_mo->xlen_requirement ? ip->insn_mo->xlen_requirement/2 : xlen);
++      break;
++
++    case M_PERM:
++      perm (rd, rs1, ip->insn_mo->name);
++      break;
++
+     case M_LA:
+     case M_LLA:
+       /* Load the address of a symbol into a register.  */
+@@ -2448,6 +2586,17 @@ riscv_ip (char *str, struct riscv_cl_insn *ip, expressionS *imm_expr,
+ 	      s = expr_end;
+ 	      continue;
+ 
++	    case '|':		/* Shift amount, 0 - (XLEN/2-1).  */
++	      my_getExpression (imm_expr, s);
++	      check_absolute_expr (ip, imm_expr, FALSE);
++	      if ((unsigned long) imm_expr->X_add_number >= xlen/2)
++		as_bad (_("Improper shift amount (%lu)"),
++			(unsigned long) imm_expr->X_add_number);
++	      INSERT_OPERAND (SHAMTW, *ip, imm_expr->X_add_number);
++	      imm_expr->X_op = O_absent;
++	      s = expr_end;
++	      continue;
++
+ 	    case '>':		/* Shift amount, 0 - (XLEN-1).  */
+ 	      my_getExpression (imm_expr, s);
+ 	      check_absolute_expr (ip, imm_expr, FALSE);
+diff --git a/include/opcode/riscv-opc.h b/include/opcode/riscv-opc.h
+index 545bda3ed4..426db0ca5f 100644
+--- a/include/opcode/riscv-opc.h
++++ b/include/opcode/riscv-opc.h
+@@ -189,6 +189,218 @@
+ #define MASK_REMW  0xfe00707f
+ #define MATCH_REMUW 0x200703b
+ #define MASK_REMUW  0xfe00707f
++#define MATCH_ANDN 0x40007033
++#define MASK_ANDN  0xfe00707f
++#define MATCH_ORN 0x40006033
++#define MASK_ORN  0xfe00707f
++#define MATCH_XNOR 0x40004033
++#define MASK_XNOR  0xfe00707f
++#define MATCH_SLO 0x20001033
++#define MASK_SLO  0xfe00707f
++#define MATCH_SRO 0x20005033
++#define MASK_SRO  0xfe00707f
++#define MATCH_ROL 0x60001033
++#define MASK_ROL  0xfe00707f
++#define MATCH_ROR 0x60005033
++#define MASK_ROR  0xfe00707f
++#define MATCH_SBCLR 0x48001033
++#define MASK_SBCLR  0xfe00707f
++#define MATCH_SBSET 0x28001033
++#define MASK_SBSET  0xfe00707f
++#define MATCH_SBINV 0x68001033
++#define MASK_SBINV  0xfe00707f
++#define MATCH_SBEXT 0x48005033
++#define MASK_SBEXT  0xfe00707f
++#define MATCH_GORC 0x28005033
++#define MASK_GORC  0xfe00707f
++#define MATCH_GREV 0x68005033
++#define MASK_GREV  0xfe00707f
++#define MATCH_SLOI 0x20001013
++#define MASK_SLOI  0xfc00707f
++#define MATCH_SROI 0x20005013
++#define MASK_SROI  0xfc00707f
++#define MATCH_RORI 0x60005013
++#define MASK_RORI  0xfc00707f
++#define MATCH_SBCLRI 0x48001013
++#define MASK_SBCLRI  0xfc00707f
++#define MATCH_SBSETI 0x28001013
++#define MASK_SBSETI  0xfc00707f
++#define MATCH_SBINVI 0x68001013
++#define MASK_SBINVI  0xfc00707f
++#define MATCH_SBEXTI 0x48005013
++#define MASK_SBEXTI  0xfc00707f
++#define MATCH_GORCI 0x28005013
++#define MASK_GORCI  0xfc00707f
++#define MATCH_GREVI 0x68005013
++#define MASK_GREVI  0xfc00707f
++#define MATCH_CMIX 0x6001033
++#define MASK_CMIX  0x600707f
++#define MATCH_CMOV 0x6005033
++#define MASK_CMOV  0x600707f
++#define MATCH_FSL 0x4001033
++#define MASK_FSL  0x600707f
++#define MATCH_FSR 0x4005033
++#define MASK_FSR  0x600707f
++#define MATCH_FSRI 0x4005013
++#define MASK_FSRI  0x400707f
++#define MATCH_CLZ 0x60001013
++#define MASK_CLZ  0xfff0707f
++#define MATCH_CTZ 0x60101013
++#define MASK_CTZ  0xfff0707f
++#define MATCH_PCNT 0x60201013
++#define MASK_PCNT  0xfff0707f
++#define MATCH_SEXT_B 0x60401013
++#define MASK_SEXT_B  0xfff0707f
++#define MATCH_SEXT_H 0x60501013
++#define MASK_SEXT_H  0xfff0707f
++#define MATCH_CRC32_B 0x61001013
++#define MASK_CRC32_B  0xfff0707f
++#define MATCH_CRC32_H 0x61101013
++#define MASK_CRC32_H  0xfff0707f
++#define MATCH_CRC32_W 0x61201013
++#define MASK_CRC32_W  0xfff0707f
++#define MATCH_CRC32C_B 0x61801013
++#define MASK_CRC32C_B  0xfff0707f
++#define MATCH_CRC32C_H 0x61901013
++#define MASK_CRC32C_H  0xfff0707f
++#define MATCH_CRC32C_W 0x61a01013
++#define MASK_CRC32C_W  0xfff0707f
++#define MATCH_SH1ADD 0x20002033
++#define MASK_SH1ADD  0xfe00707f
++#define MATCH_SH2ADD 0x20004033
++#define MASK_SH2ADD  0xfe00707f
++#define MATCH_SH3ADD 0x20006033
++#define MASK_SH3ADD  0xfe00707f
++#define MATCH_CLMUL 0xa001033
++#define MASK_CLMUL  0xfe00707f
++#define MATCH_CLMULR 0xa002033
++#define MASK_CLMULR  0xfe00707f
++#define MATCH_CLMULH 0xa003033
++#define MASK_CLMULH  0xfe00707f
++#define MATCH_MIN 0xa004033
++#define MASK_MIN  0xfe00707f
++#define MATCH_MAX 0xa005033
++#define MASK_MAX  0xfe00707f
++#define MATCH_MINU 0xa006033
++#define MASK_MINU  0xfe00707f
++#define MATCH_MAXU 0xa007033
++#define MASK_MAXU  0xfe00707f
++#define MATCH_SHFL 0x8001033
++#define MASK_SHFL  0xfe00707f
++#define MATCH_UNSHFL 0x8005033
++#define MASK_UNSHFL  0xfe00707f
++#define MATCH_BEXT 0x8006033
++#define MASK_BEXT  0xfe00707f
++#define MATCH_BDEP 0x48006033
++#define MASK_BDEP  0xfe00707f
++#define MATCH_PACK 0x8004033
++#define MASK_PACK  0xfe00707f
++#define MATCH_PACKU 0x48004033
++#define MASK_PACKU  0xfe00707f
++#define MATCH_PACKH 0x8007033
++#define MASK_PACKH  0xfe00707f
++#define MATCH_BFP 0x48007033
++#define MASK_BFP  0xfe00707f
++#define MATCH_SHFLI 0x8001013
++#define MASK_SHFLI  0xfe00707f
++#define MATCH_UNSHFLI 0x8005013
++#define MASK_UNSHFLI  0xfe00707f
++#define MATCH_BMATFLIP 0x60301013
++#define MASK_BMATFLIP  0xfff0707f
++#define MATCH_CRC32_D 0x61301013
++#define MASK_CRC32_D  0xfff0707f
++#define MATCH_CRC32C_D 0x61b01013
++#define MASK_CRC32C_D  0xfff0707f
++#define MATCH_BMATOR 0x8003033
++#define MASK_BMATOR  0xfe00707f
++#define MATCH_BMATXOR 0x48003033
++#define MASK_BMATXOR  0xfe00707f
++#define MATCH_ADDIWU 0x401b
++#define MASK_ADDIWU  0x707f
++#define MATCH_SLLIU_W 0x800101b
++#define MASK_SLLIU_W  0xfc00707f
++#define MATCH_ADDWU 0xa00003b
++#define MASK_ADDWU  0xfe00707f
++#define MATCH_SUBWU 0x4a00003b
++#define MASK_SUBWU  0xfe00707f
++#define MATCH_ADDU_W 0x800003b
++#define MASK_ADDU_W  0xfe00707f
++#define MATCH_SUBU_W 0x4800003b
++#define MASK_SUBU_W  0xfe00707f
++#define MATCH_SLOW 0x2000103b
++#define MASK_SLOW  0xfe00707f
++#define MATCH_SROW 0x2000503b
++#define MASK_SROW  0xfe00707f
++#define MATCH_ROLW 0x6000103b
++#define MASK_ROLW  0xfe00707f
++#define MATCH_RORW 0x6000503b
++#define MASK_RORW  0xfe00707f
++#define MATCH_SBCLRW 0x4800103b
++#define MASK_SBCLRW  0xfe00707f
++#define MATCH_SBSETW 0x2800103b
++#define MASK_SBSETW  0xfe00707f
++#define MATCH_SBINVW 0x6800103b
++#define MASK_SBINVW  0xfe00707f
++#define MATCH_SBEXTW 0x4800503b
++#define MASK_SBEXTW  0xfe00707f
++#define MATCH_GORCW 0x2800503b
++#define MASK_GORCW  0xfe00707f
++#define MATCH_GREVW 0x6800503b
++#define MASK_GREVW  0xfe00707f
++#define MATCH_SLOIW 0x2000101b
++#define MASK_SLOIW  0xfe00707f
++#define MATCH_SROIW 0x2000501b
++#define MASK_SROIW  0xfe00707f
++#define MATCH_RORIW 0x6000501b
++#define MASK_RORIW  0xfe00707f
++#define MATCH_SBCLRIW 0x4800101b
++#define MASK_SBCLRIW  0xfe00707f
++#define MATCH_SBSETIW 0x2800101b
++#define MASK_SBSETIW  0xfe00707f
++#define MATCH_SBINVIW 0x6800101b
++#define MASK_SBINVIW  0xfe00707f
++#define MATCH_GORCIW 0x2800501b
++#define MASK_GORCIW  0xfe00707f
++#define MATCH_GREVIW 0x6800501b
++#define MASK_GREVIW  0xfe00707f
++#define MATCH_FSLW 0x400103b
++#define MASK_FSLW  0x600707f
++#define MATCH_FSRW 0x400503b
++#define MASK_FSRW  0x600707f
++#define MATCH_FSRIW 0x400501b
++#define MASK_FSRIW  0x600707f
++#define MATCH_CLZW 0x6000101b
++#define MASK_CLZW  0xfff0707f
++#define MATCH_CTZW 0x6010101b
++#define MASK_CTZW  0xfff0707f
++#define MATCH_PCNTW 0x6020101b
++#define MASK_PCNTW  0xfff0707f
++#define MATCH_SH1ADDU_W 0x2000203b
++#define MASK_SH1ADDU_W  0xfe00707f
++#define MATCH_SH2ADDU_W 0x2000403b
++#define MASK_SH2ADDU_W  0xfe00707f
++#define MATCH_SH3ADDU_W 0x2000603b
++#define MASK_SH3ADDU_W  0xfe00707f
++#define MATCH_CLMULW 0xa00103b
++#define MASK_CLMULW  0xfe00707f
++#define MATCH_CLMULRW 0xa00203b
++#define MASK_CLMULRW  0xfe00707f
++#define MATCH_CLMULHW 0xa00303b
++#define MASK_CLMULHW  0xfe00707f
++#define MATCH_SHFLW 0x800103b
++#define MASK_SHFLW  0xfe00707f
++#define MATCH_UNSHFLW 0x800503b
++#define MASK_UNSHFLW  0xfe00707f
++#define MATCH_BEXTW 0x800603b
++#define MASK_BEXTW  0xfe00707f
++#define MATCH_BDEPW 0x4800603b
++#define MASK_BDEPW  0xfe00707f
++#define MATCH_PACKW 0x800403b
++#define MASK_PACKW  0xfe00707f
++#define MATCH_PACKUW 0x4800403b
++#define MASK_PACKUW  0xfe00707f
++#define MATCH_BFPW 0x4800703b
++#define MASK_BFPW  0xfe00707f
+ #define MATCH_AMOADD_W 0x202f
+ #define MASK_AMOADD_W  0xf800707f
+ #define MATCH_AMOXOR_W 0x2000202f
+@@ -3444,6 +3656,112 @@ DECLARE_INSN(divw, MATCH_DIVW, MASK_DIVW)
+ DECLARE_INSN(divuw, MATCH_DIVUW, MASK_DIVUW)
+ DECLARE_INSN(remw, MATCH_REMW, MASK_REMW)
+ DECLARE_INSN(remuw, MATCH_REMUW, MASK_REMUW)
++DECLARE_INSN(andn, MATCH_ANDN, MASK_ANDN)
++DECLARE_INSN(orn, MATCH_ORN, MASK_ORN)
++DECLARE_INSN(xnor, MATCH_XNOR, MASK_XNOR)
++DECLARE_INSN(slo, MATCH_SLO, MASK_SLO)
++DECLARE_INSN(sro, MATCH_SRO, MASK_SRO)
++DECLARE_INSN(rol, MATCH_ROL, MASK_ROL)
++DECLARE_INSN(ror, MATCH_ROR, MASK_ROR)
++DECLARE_INSN(sbclr, MATCH_SBCLR, MASK_SBCLR)
++DECLARE_INSN(sbset, MATCH_SBSET, MASK_SBSET)
++DECLARE_INSN(sbinv, MATCH_SBINV, MASK_SBINV)
++DECLARE_INSN(sbext, MATCH_SBEXT, MASK_SBEXT)
++DECLARE_INSN(gorc, MATCH_GORC, MASK_GORC)
++DECLARE_INSN(grev, MATCH_GREV, MASK_GREV)
++DECLARE_INSN(sloi, MATCH_SLOI, MASK_SLOI)
++DECLARE_INSN(sroi, MATCH_SROI, MASK_SROI)
++DECLARE_INSN(rori, MATCH_RORI, MASK_RORI)
++DECLARE_INSN(sbclri, MATCH_SBCLRI, MASK_SBCLRI)
++DECLARE_INSN(sbseti, MATCH_SBSETI, MASK_SBSETI)
++DECLARE_INSN(sbinvi, MATCH_SBINVI, MASK_SBINVI)
++DECLARE_INSN(sbexti, MATCH_SBEXTI, MASK_SBEXTI)
++DECLARE_INSN(gorci, MATCH_GORCI, MASK_GORCI)
++DECLARE_INSN(grevi, MATCH_GREVI, MASK_GREVI)
++DECLARE_INSN(cmix, MATCH_CMIX, MASK_CMIX)
++DECLARE_INSN(cmov, MATCH_CMOV, MASK_CMOV)
++DECLARE_INSN(fsl, MATCH_FSL, MASK_FSL)
++DECLARE_INSN(fsr, MATCH_FSR, MASK_FSR)
++DECLARE_INSN(fsri, MATCH_FSRI, MASK_FSRI)
++DECLARE_INSN(clz, MATCH_CLZ, MASK_CLZ)
++DECLARE_INSN(ctz, MATCH_CTZ, MASK_CTZ)
++DECLARE_INSN(pcnt, MATCH_PCNT, MASK_PCNT)
++DECLARE_INSN(sext_b, MATCH_SEXT_B, MASK_SEXT_B)
++DECLARE_INSN(sext_h, MATCH_SEXT_H, MASK_SEXT_H)
++DECLARE_INSN(crc32_b, MATCH_CRC32_B, MASK_CRC32_B)
++DECLARE_INSN(crc32_h, MATCH_CRC32_H, MASK_CRC32_H)
++DECLARE_INSN(crc32_w, MATCH_CRC32_W, MASK_CRC32_W)
++DECLARE_INSN(crc32c_b, MATCH_CRC32C_B, MASK_CRC32C_B)
++DECLARE_INSN(crc32c_h, MATCH_CRC32C_H, MASK_CRC32C_H)
++DECLARE_INSN(crc32c_w, MATCH_CRC32C_W, MASK_CRC32C_W)
++DECLARE_INSN(sh1add, MATCH_SH1ADD, MASK_SH1ADD)
++DECLARE_INSN(sh2add, MATCH_SH2ADD, MASK_SH2ADD)
++DECLARE_INSN(sh3add, MATCH_SH3ADD, MASK_SH3ADD)
++DECLARE_INSN(clmul, MATCH_CLMUL, MASK_CLMUL)
++DECLARE_INSN(clmulr, MATCH_CLMULR, MASK_CLMULR)
++DECLARE_INSN(clmulh, MATCH_CLMULH, MASK_CLMULH)
++DECLARE_INSN(min, MATCH_MIN, MASK_MIN)
++DECLARE_INSN(max, MATCH_MAX, MASK_MAX)
++DECLARE_INSN(minu, MATCH_MINU, MASK_MINU)
++DECLARE_INSN(maxu, MATCH_MAXU, MASK_MAXU)
++DECLARE_INSN(shfl, MATCH_SHFL, MASK_SHFL)
++DECLARE_INSN(unshfl, MATCH_UNSHFL, MASK_UNSHFL)
++DECLARE_INSN(bext, MATCH_BEXT, MASK_BEXT)
++DECLARE_INSN(bdep, MATCH_BDEP, MASK_BDEP)
++DECLARE_INSN(pack, MATCH_PACK, MASK_PACK)
++DECLARE_INSN(packu, MATCH_PACKU, MASK_PACKU)
++DECLARE_INSN(packh, MATCH_PACKH, MASK_PACKH)
++DECLARE_INSN(bfp, MATCH_BFP, MASK_BFP)
++DECLARE_INSN(shfli, MATCH_SHFLI, MASK_SHFLI)
++DECLARE_INSN(unshfli, MATCH_UNSHFLI, MASK_UNSHFLI)
++DECLARE_INSN(bmatflip, MATCH_BMATFLIP, MASK_BMATFLIP)
++DECLARE_INSN(crc32_d, MATCH_CRC32_D, MASK_CRC32_D)
++DECLARE_INSN(crc32c_d, MATCH_CRC32C_D, MASK_CRC32C_D)
++DECLARE_INSN(bmator, MATCH_BMATOR, MASK_BMATOR)
++DECLARE_INSN(bmatxor, MATCH_BMATXOR, MASK_BMATXOR)
++DECLARE_INSN(addiwu, MATCH_ADDIWU, MASK_ADDIWU)
++DECLARE_INSN(slliu_w, MATCH_SLLIU_W, MASK_SLLIU_W)
++DECLARE_INSN(addwu, MATCH_ADDWU, MASK_ADDWU)
++DECLARE_INSN(subwu, MATCH_SUBWU, MASK_SUBWU)
++DECLARE_INSN(addu_w, MATCH_ADDU_W, MASK_ADDU_W)
++DECLARE_INSN(subu_w, MATCH_SUBU_W, MASK_SUBU_W)
++DECLARE_INSN(slow, MATCH_SLOW, MASK_SLOW)
++DECLARE_INSN(srow, MATCH_SROW, MASK_SROW)
++DECLARE_INSN(rolw, MATCH_ROLW, MASK_ROLW)
++DECLARE_INSN(rorw, MATCH_RORW, MASK_RORW)
++DECLARE_INSN(sbclrw, MATCH_SBCLRW, MASK_SBCLRW)
++DECLARE_INSN(sbsetw, MATCH_SBSETW, MASK_SBSETW)
++DECLARE_INSN(sbinvw, MATCH_SBINVW, MASK_SBINVW)
++DECLARE_INSN(sbextw, MATCH_SBEXTW, MASK_SBEXTW)
++DECLARE_INSN(gorcw, MATCH_GORCW, MASK_GORCW)
++DECLARE_INSN(grevw, MATCH_GREVW, MASK_GREVW)
++DECLARE_INSN(sloiw, MATCH_SLOIW, MASK_SLOIW)
++DECLARE_INSN(sroiw, MATCH_SROIW, MASK_SROIW)
++DECLARE_INSN(roriw, MATCH_RORIW, MASK_RORIW)
++DECLARE_INSN(sbclriw, MATCH_SBCLRIW, MASK_SBCLRIW)
++DECLARE_INSN(sbsetiw, MATCH_SBSETIW, MASK_SBSETIW)
++DECLARE_INSN(sbinviw, MATCH_SBINVIW, MASK_SBINVIW)
++DECLARE_INSN(gorciw, MATCH_GORCIW, MASK_GORCIW)
++DECLARE_INSN(greviw, MATCH_GREVIW, MASK_GREVIW)
++DECLARE_INSN(fslw, MATCH_FSLW, MASK_FSLW)
++DECLARE_INSN(fsrw, MATCH_FSRW, MASK_FSRW)
++DECLARE_INSN(fsriw, MATCH_FSRIW, MASK_FSRIW)
++DECLARE_INSN(clzw, MATCH_CLZW, MASK_CLZW)
++DECLARE_INSN(ctzw, MATCH_CTZW, MASK_CTZW)
++DECLARE_INSN(pcntw, MATCH_PCNTW, MASK_PCNTW)
++DECLARE_INSN(sh1addu_w, MATCH_SH1ADDU_W, MASK_SH1ADDU_W)
++DECLARE_INSN(sh2addu_w, MATCH_SH2ADDU_W, MASK_SH2ADDU_W)
++DECLARE_INSN(sh3addu_w, MATCH_SH3ADDU_W, MASK_SH3ADDU_W)
++DECLARE_INSN(clmulw, MATCH_CLMULW, MASK_CLMULW)
++DECLARE_INSN(clmulrw, MATCH_CLMULRW, MASK_CLMULRW)
++DECLARE_INSN(clmulhw, MATCH_CLMULHW, MASK_CLMULHW)
++DECLARE_INSN(shflw, MATCH_SHFLW, MASK_SHFLW)
++DECLARE_INSN(unshflw, MATCH_UNSHFLW, MASK_UNSHFLW)
++DECLARE_INSN(bextw, MATCH_BEXTW, MASK_BEXTW)
++DECLARE_INSN(bdepw, MATCH_BDEPW, MASK_BDEPW)
++DECLARE_INSN(packw, MATCH_PACKW, MASK_PACKW)
++DECLARE_INSN(packuw, MATCH_PACKUW, MASK_PACKUW)
++DECLARE_INSN(bfpw, MATCH_BFPW, MASK_BFPW)
+ DECLARE_INSN(amoadd_w, MATCH_AMOADD_W, MASK_AMOADD_W)
+ DECLARE_INSN(amoxor_w, MATCH_AMOXOR_W, MASK_AMOXOR_W)
+ DECLARE_INSN(amoor_w, MATCH_AMOOR_W, MASK_AMOOR_W)
+diff --git a/include/opcode/riscv.h b/include/opcode/riscv.h
+index 2e1a665c6b..5303d14998 100644
+--- a/include/opcode/riscv.h
++++ b/include/opcode/riscv.h
+@@ -390,6 +390,19 @@ enum riscv_insn_class
+    INSN_CLASS_V_AND_ZVEDIV,
+    INSN_CLASS_V_OR_ZVLSSEG,
+    INSN_CLASS_V_AND_ZVQMAC,
++
++   INSN_CLASS_B,
++   INSN_CLASS_B_OR_ZBT,
++   INSN_CLASS_B_OR_ZBR,
++   INSN_CLASS_B_OR_ZBB,
++   INSN_CLASS_B_OR_ZBA,
++   INSN_CLASS_B_OR_ZBC,
++   INSN_CLASS_B_OR_ZBE,
++   INSN_CLASS_B_OR_ZBF,
++   INSN_CLASS_B_OR_ZBM,
++   INSN_CLASS_B_OR_ZBP,
++   INSN_CLASS_B_OR_ZBS,
++   INSN_CLASS_B_OR_ZBB_OR_ZBP
+   };
+ 
+ /* This structure holds information for a particular instruction.  */
+@@ -568,6 +581,9 @@ enum
+   M_LI,
+   M_VMSGE,
+   M_VMSGEU,
++  M_RL,
++  M_FL,
++  M_PERM,
+   M_NUM_MACROS
+ };
+ 
+diff --git a/ld/testsuite/ld-riscv-elf/attr-dupl-arch-z-failed-01.d b/ld/testsuite/ld-riscv-elf/attr-dupl-arch-z-failed-01.d
+new file mode 100644
+index 0000000000..20b4530f0a
+--- /dev/null
++++ b/ld/testsuite/ld-riscv-elf/attr-dupl-arch-z-failed-01.d
+@@ -0,0 +1,3 @@
++#source: attr-dupl-arch-z-failed-01.s
++#as: -march-attr
++#error: -march=rv32i2p0_zbc_zbc: Duplicate Z ISA extension: 'zbc'
+diff --git a/ld/testsuite/ld-riscv-elf/attr-dupl-arch-z-failed-01.s b/ld/testsuite/ld-riscv-elf/attr-dupl-arch-z-failed-01.s
+new file mode 100644
+index 0000000000..96d67e1833
+--- /dev/null
++++ b/ld/testsuite/ld-riscv-elf/attr-dupl-arch-z-failed-01.s
+@@ -0,0 +1 @@
++	.attribute arch, "rv32i2p0_zbc_zbc"
+diff --git a/ld/testsuite/ld-riscv-elf/attr-merge-arch-z-failed-01.d b/ld/testsuite/ld-riscv-elf/attr-merge-arch-z-failed-01.d
+new file mode 100644
+index 0000000000..d82c1c2868
+--- /dev/null
++++ b/ld/testsuite/ld-riscv-elf/attr-merge-arch-z-failed-01.d
+@@ -0,0 +1,5 @@
++#source: attr-merge-arch-z-failed-01a.s
++#source: attr-merge-arch-z-failed-01b.s
++#as: -march-attr
++#ld: -r -melf32lriscv
++#error: Mis-matched ISA version for 'zbb' extension. 2.1 vs 2.0
+diff --git a/ld/testsuite/ld-riscv-elf/attr-merge-arch-z-failed-01a.s b/ld/testsuite/ld-riscv-elf/attr-merge-arch-z-failed-01a.s
+new file mode 100644
+index 0000000000..6768e78c52
+--- /dev/null
++++ b/ld/testsuite/ld-riscv-elf/attr-merge-arch-z-failed-01a.s
+@@ -0,0 +1 @@
++	.attribute arch, "rv32i2p0_zbb2p0"
+diff --git a/ld/testsuite/ld-riscv-elf/attr-merge-arch-z-failed-01b.s b/ld/testsuite/ld-riscv-elf/attr-merge-arch-z-failed-01b.s
+new file mode 100644
+index 0000000000..4279973411
+--- /dev/null
++++ b/ld/testsuite/ld-riscv-elf/attr-merge-arch-z-failed-01b.s
+@@ -0,0 +1 @@
++	.attribute arch, "rv32i2p0_zbb2p1"
+diff --git a/ld/testsuite/ld-riscv-elf/attr-order-arch-z-failed-01.d b/ld/testsuite/ld-riscv-elf/attr-order-arch-z-failed-01.d
+new file mode 100644
+index 0000000000..809d8ba607
+--- /dev/null
++++ b/ld/testsuite/ld-riscv-elf/attr-order-arch-z-failed-01.d
+@@ -0,0 +1,3 @@
++#source: attr-order-arch-z-failed-01.s
++#as: -march-attr
++#error: -march=rv32i2p0_zbc_zbb: Z ISA extension not in alphabetical order: 'zbb' must come before 'zbc'.
+diff --git a/ld/testsuite/ld-riscv-elf/attr-order-arch-z-failed-01.s b/ld/testsuite/ld-riscv-elf/attr-order-arch-z-failed-01.s
+new file mode 100644
+index 0000000000..e31e3766ca
+--- /dev/null
++++ b/ld/testsuite/ld-riscv-elf/attr-order-arch-z-failed-01.s
+@@ -0,0 +1 @@
++	.attribute arch, "rv32i2p0_zbc_zbb"
+diff --git a/ld/testsuite/ld-riscv-elf/attr-order-arch-z-failed-02.d b/ld/testsuite/ld-riscv-elf/attr-order-arch-z-failed-02.d
+new file mode 100644
+index 0000000000..19a5482300
+--- /dev/null
++++ b/ld/testsuite/ld-riscv-elf/attr-order-arch-z-failed-02.d
+@@ -0,0 +1,3 @@
++#source: attr-order-arch-z-failed-02.s
++#as: -march-attr
++#error: -march=rv32i2p0_xsillyname_zbb: unexpected ISA string at end: zbb
+diff --git a/ld/testsuite/ld-riscv-elf/attr-order-arch-z-failed-02.s b/ld/testsuite/ld-riscv-elf/attr-order-arch-z-failed-02.s
+new file mode 100644
+index 0000000000..b1abe26891
+--- /dev/null
++++ b/ld/testsuite/ld-riscv-elf/attr-order-arch-z-failed-02.s
+@@ -0,0 +1 @@
++	.attribute arch, "rv32i2p0_xsillyname_zbb"
+diff --git a/ld/testsuite/ld-riscv-elf/attr-tooshort-arch-z-failed-01.d b/ld/testsuite/ld-riscv-elf/attr-tooshort-arch-z-failed-01.d
+new file mode 100644
+index 0000000000..4a6885db5e
+--- /dev/null
++++ b/ld/testsuite/ld-riscv-elf/attr-tooshort-arch-z-failed-01.d
+@@ -0,0 +1,3 @@
++#source: attr-tooshort-arch-z-failed-01.s
++#as: -march-attr
++#error: -march=rv32i2p0_z: Literal 'z' is an invalid Z ISA extension specifier.
+diff --git a/ld/testsuite/ld-riscv-elf/attr-tooshort-arch-z-failed-01.s b/ld/testsuite/ld-riscv-elf/attr-tooshort-arch-z-failed-01.s
+new file mode 100644
+index 0000000000..7ca87fabf4
+--- /dev/null
++++ b/ld/testsuite/ld-riscv-elf/attr-tooshort-arch-z-failed-01.s
+@@ -0,0 +1 @@
++	.attribute arch, "rv32i2p0_z"
+diff --git a/ld/testsuite/ld-riscv-elf/attr-unknown-arch-z-failed-01.d b/ld/testsuite/ld-riscv-elf/attr-unknown-arch-z-failed-01.d
+new file mode 100644
+index 0000000000..343db87a41
+--- /dev/null
++++ b/ld/testsuite/ld-riscv-elf/attr-unknown-arch-z-failed-01.d
+@@ -0,0 +1,3 @@
++#source: attr-unknown-arch-z-failed-01.s
++#as: -march-attr
++#error: -march=rv32i2p0_zsillyname: Unknown Z ISA extension: 'zsillyname'
+diff --git a/ld/testsuite/ld-riscv-elf/attr-unknown-arch-z-failed-01.s b/ld/testsuite/ld-riscv-elf/attr-unknown-arch-z-failed-01.s
+new file mode 100644
+index 0000000000..6e16bef91d
+--- /dev/null
++++ b/ld/testsuite/ld-riscv-elf/attr-unknown-arch-z-failed-01.s
+@@ -0,0 +1 @@
++	.attribute arch, "rv32i2p0_zsillyname"
+diff --git a/ld/testsuite/ld-riscv-elf/ld-riscv-elf.exp b/ld/testsuite/ld-riscv-elf/ld-riscv-elf.exp
+index 2c008d4c35..4df5d740e1 100644
+--- a/ld/testsuite/ld-riscv-elf/ld-riscv-elf.exp
++++ b/ld/testsuite/ld-riscv-elf/ld-riscv-elf.exp
+@@ -47,6 +47,12 @@ if [istarget "riscv*-*-*"] {
+     run_dump_test "attr-merge-priv-spec-failed-04"
+     run_dump_test "attr-merge-priv-spec-failed-05"
+     run_dump_test "attr-merge-priv-spec-failed-06"
++    run_dump_test "attr-merge-arch-z-failed-01"
++    run_dump_test "attr-dupl-arch-z-failed-01"
++    run_dump_test "attr-order-arch-z-failed-01"
++    run_dump_test "attr-order-arch-z-failed-02"
++    run_dump_test "attr-tooshort-arch-z-failed-01"
++    run_dump_test "attr-unknown-arch-z-failed-01"
+     run_ld_link_tests {
+ 	{ "Weak reference 32" "-T weakref.ld -melf32lriscv" ""
+ 	    "-march=rv32i -mabi=ilp32" {weakref32.s}
+diff --git a/opcodes/riscv-dis.c b/opcodes/riscv-dis.c
+index 2b64cf1d08..bb57793c94 100644
+--- a/opcodes/riscv-dis.c
++++ b/opcodes/riscv-dis.c
+@@ -239,6 +239,7 @@ print_insn_args (const char *d, insn_t l, bfd_vma pc, disassemble_info *info)
+ 	    case '>':
+ 	      print (info->stream, "0x%x", (int)EXTRACT_RVC_IMM (l) & 0x3f);
+ 	      break;
++	    case '|':
+ 	    case '<':
+ 	      print (info->stream, "0x%x", (int)EXTRACT_RVC_IMM (l) & 0x1f);
+ 	      break;
+@@ -279,6 +280,11 @@ print_insn_args (const char *d, insn_t l, bfd_vma pc, disassemble_info *info)
+ 		 riscv_gpr_names[EXTRACT_OPERAND (RS2, l)]);
+ 	  break;
+ 
++	case 'r':
++	  print (info->stream, "%s",
++		 riscv_gpr_names[EXTRACT_OPERAND (RS3, l)]);
++	  break;
++
+ 	case 'u':
+ 	  print (info->stream, "0x%x",
+ 		 (unsigned)EXTRACT_UTYPE_IMM (l) >> RISCV_IMM_BITS);
+@@ -342,6 +348,7 @@ print_insn_args (const char *d, insn_t l, bfd_vma pc, disassemble_info *info)
+ 	  print (info->stream, "0x%x", (int)EXTRACT_OPERAND (SHAMT, l));
+ 	  break;
+ 
++	case '|':
+ 	case '<':
+ 	  print (info->stream, "0x%x", (int)EXTRACT_OPERAND (SHAMTW, l));
+ 	  break;
+diff --git a/opcodes/riscv-opc.c b/opcodes/riscv-opc.c
+index 778c5d2f45..1869f545cf 100644
+--- a/opcodes/riscv-opc.c
++++ b/opcodes/riscv-opc.c
+@@ -984,6 +984,220 @@ const struct riscv_opcode riscv_opcodes[] =
+ {"fcvt.h.lu", 64, INSN_CLASS_F_AND_ZFH,   "D,s",  MATCH_FCVT_H_LU | MASK_RM, MASK_FCVT_H_L | MASK_RM, match_opcode, 0 },
+ {"fcvt.h.lu", 64, INSN_CLASS_F_AND_ZFH,   "D,s,m",  MATCH_FCVT_H_LU, MASK_FCVT_H_LU, match_opcode, 0 },
+ 
++/* Bitmanip instruction subset */
++{"andn",      0, INSN_CLASS_B_OR_ZBB_OR_ZBP,   "d,s,t",  MATCH_ANDN, MASK_ANDN, match_opcode, 0 },
++{"orn",       0, INSN_CLASS_B_OR_ZBB_OR_ZBP,   "d,s,t",  MATCH_ORN, MASK_ORN, match_opcode, 0 },
++{"xnor",      0, INSN_CLASS_B_OR_ZBB_OR_ZBP,   "d,s,t",  MATCH_XNOR, MASK_XNOR, match_opcode, 0 },
++{"sloi",      0, INSN_CLASS_B_OR_ZBP,   "d,s,>",  MATCH_SLOI, MASK_SLOI, match_opcode, 0 },
++{"sroi",      0, INSN_CLASS_B_OR_ZBP,   "d,s,>",  MATCH_SROI, MASK_SROI, match_opcode, 0 },
++{"roli",      0, INSN_CLASS_B_OR_ZBB_OR_ZBP,   "d,s,>",  0, (int) M_RL, match_never, INSN_MACRO },
++{"rori",      0, INSN_CLASS_B_OR_ZBB_OR_ZBP,   "d,s,>",  MATCH_RORI, MASK_RORI, match_opcode, 0 },
++{"slo",       0, INSN_CLASS_B_OR_ZBP,   "d,s,t",  MATCH_SLO, MASK_SLO, match_opcode, 0 },
++{"slo",       0, INSN_CLASS_B_OR_ZBP,   "d,s,>",  MATCH_SLOI, MASK_SLOI, match_opcode, INSN_ALIAS },
++{"sro",       0, INSN_CLASS_B_OR_ZBP,   "d,s,t",  MATCH_SRO, MASK_SRO, match_opcode, 0 },
++{"sro",       0, INSN_CLASS_B_OR_ZBP,   "d,s,>",  MATCH_SROI, MASK_SROI, match_opcode, INSN_ALIAS },
++{"rol",       0, INSN_CLASS_B_OR_ZBB_OR_ZBP,   "d,s,t",  MATCH_ROL, MASK_ROL, match_opcode, 0 },
++{"rol",       0, INSN_CLASS_B_OR_ZBB_OR_ZBP,   "d,s,>",  0, (int) M_RL, match_never, INSN_MACRO },
++{"ror",       0, INSN_CLASS_B_OR_ZBB_OR_ZBP,   "d,s,t",  MATCH_ROR, MASK_ROR, match_opcode, 0 },
++{"ror",       0, INSN_CLASS_B_OR_ZBB_OR_ZBP,   "d,s,>",  MATCH_RORI, MASK_RORI, match_opcode, INSN_ALIAS },
++{"sbclri",    0, INSN_CLASS_B_OR_ZBS,   "d,s,>",  MATCH_SBCLRI, MASK_SBCLRI, match_opcode, 0 },
++{"sbseti",    0, INSN_CLASS_B_OR_ZBS,   "d,s,>",  MATCH_SBSETI, MASK_SBSETI, match_opcode, 0 },
++{"sbinvi",    0, INSN_CLASS_B_OR_ZBS,   "d,s,>",  MATCH_SBINVI, MASK_SBINVI, match_opcode, 0 },
++{"sbexti",    0, INSN_CLASS_B_OR_ZBS,   "d,s,>",  MATCH_SBEXTI, MASK_SBEXTI, match_opcode, 0 },
++{"gorci",     0, INSN_CLASS_B_OR_ZBP,   "d,s,>",  MATCH_GORCI, MASK_GORCI, match_opcode, 0 },
++{"grevi",     0, INSN_CLASS_B_OR_ZBP,   "d,s,>",  MATCH_GREVI, MASK_GREVI, match_opcode, 0 },
++{"sbclr",     0, INSN_CLASS_B_OR_ZBS,   "d,s,t",  MATCH_SBCLR, MASK_SBCLR, match_opcode, 0 },
++{"sbclr",     0, INSN_CLASS_B_OR_ZBS,   "d,s,>",  MATCH_SBCLRI, MASK_SBCLRI, match_opcode, INSN_ALIAS },
++{"sbset",     0, INSN_CLASS_B_OR_ZBS,   "d,s,t",  MATCH_SBSET, MASK_SBSET, match_opcode, 0 },
++{"sbset",     0, INSN_CLASS_B_OR_ZBS,   "d,s,>",  MATCH_SBSETI, MASK_SBSETI, match_opcode, INSN_ALIAS },
++{"sbinv",     0, INSN_CLASS_B_OR_ZBS,   "d,s,t",  MATCH_SBINV, MASK_SBINV, match_opcode, 0 },
++{"sbinv",     0, INSN_CLASS_B_OR_ZBS,   "d,s,>",  MATCH_SBINVI, MASK_SBINVI, match_opcode, INSN_ALIAS },
++{"sbext",     0, INSN_CLASS_B_OR_ZBS,   "d,s,t",  MATCH_SBEXT, MASK_SBEXT, match_opcode, 0 },
++{"sbext",     0, INSN_CLASS_B_OR_ZBS,   "d,s,>",  MATCH_SBEXTI, MASK_SBEXTI, match_opcode, INSN_ALIAS },
++{"gorc",      0, INSN_CLASS_B_OR_ZBP,   "d,s,t",  MATCH_GORC, MASK_GORC, match_opcode, 0 },
++{"gorc",      0, INSN_CLASS_B_OR_ZBP,   "d,s,>",  MATCH_GORCI, MASK_GORCI, match_opcode, INSN_ALIAS },
++{"grev",      0, INSN_CLASS_B_OR_ZBP,   "d,s,t",  MATCH_GREV, MASK_GREV, match_opcode, 0 },
++{"grev",      0, INSN_CLASS_B_OR_ZBP,   "d,s,>",  MATCH_GREVI, MASK_GREVI, match_opcode, INSN_ALIAS },
++{"cmix",      0, INSN_CLASS_B_OR_ZBT,   "d,t,s,r",  MATCH_CMIX, MASK_CMIX, match_opcode, 0 },
++{"cmov",      0, INSN_CLASS_B_OR_ZBT,   "d,t,s,r",  MATCH_CMOV, MASK_CMOV, match_opcode, 0 },
++{"fsli",      0, INSN_CLASS_B_OR_ZBT,   "d,s,r,>",  0, (int) M_FL, match_never, INSN_MACRO },
++{"fsri",      0, INSN_CLASS_B_OR_ZBT,   "d,s,r,>",  MATCH_FSRI, MASK_FSRI, match_opcode, 0 },
++{"fsl",       0, INSN_CLASS_B_OR_ZBT,   "d,s,r,t",  MATCH_FSL, MASK_FSL, match_opcode, 0 },
++{"fsl",       0, INSN_CLASS_B_OR_ZBT,   "d,s,r,>",  0, (int) M_FL, match_never, INSN_MACRO },
++{"fsr",       0, INSN_CLASS_B_OR_ZBT,   "d,s,r,t",  MATCH_FSR, MASK_FSR, match_opcode, 0 },
++{"fsr",       0, INSN_CLASS_B_OR_ZBT,   "d,s,r,>",  MATCH_FSRI, MASK_FSRI, match_opcode, INSN_ALIAS },
++{"clz",       0, INSN_CLASS_B_OR_ZBB,   "d,s",  MATCH_CLZ, MASK_CLZ, match_opcode, 0 },
++{"ctz",       0, INSN_CLASS_B_OR_ZBB,   "d,s",  MATCH_CTZ, MASK_CTZ, match_opcode, 0 },
++{"pcnt",      0, INSN_CLASS_B_OR_ZBB,   "d,s",  MATCH_PCNT, MASK_PCNT, match_opcode, 0 },
++{"sext.b",    0, INSN_CLASS_B_OR_ZBB,   "d,s",  MATCH_SEXT_B, MASK_SEXT_B, match_opcode, 0 },
++{"sext.h",    0, INSN_CLASS_B_OR_ZBB,   "d,s",  MATCH_SEXT_H, MASK_SEXT_H, match_opcode, 0 },
++{"bmatflip", 64, INSN_CLASS_B_OR_ZBM,   "d,s",  MATCH_BMATFLIP, MASK_BMATFLIP, match_opcode, 0 },
++{"crc32.b",   0, INSN_CLASS_B_OR_ZBR,   "d,s",  MATCH_CRC32_B, MASK_CRC32_B, match_opcode, 0 },
++{"crc32.h",   0, INSN_CLASS_B_OR_ZBR,   "d,s",  MATCH_CRC32_H, MASK_CRC32_H, match_opcode, 0 },
++{"crc32.w",   0, INSN_CLASS_B_OR_ZBR,   "d,s",  MATCH_CRC32_W, MASK_CRC32_W, match_opcode, 0 },
++{"crc32.d",  64, INSN_CLASS_B_OR_ZBR,   "d,s",  MATCH_CRC32_D, MASK_CRC32_D, match_opcode, 0 },
++{"crc32c.b",  0, INSN_CLASS_B_OR_ZBR,   "d,s",  MATCH_CRC32C_B, MASK_CRC32C_B, match_opcode, 0 },
++{"crc32c.h",  0, INSN_CLASS_B_OR_ZBR,   "d,s",  MATCH_CRC32C_H, MASK_CRC32C_H, match_opcode, 0 },
++{"crc32c.w",  0, INSN_CLASS_B_OR_ZBR,   "d,s",  MATCH_CRC32C_W, MASK_CRC32C_W, match_opcode, 0 },
++{"crc32c.d", 64, INSN_CLASS_B_OR_ZBR,   "d,s",  MATCH_CRC32C_D, MASK_CRC32C_D, match_opcode, 0 },
++{"sh1add",    0, INSN_CLASS_B_OR_ZBA,   "d,s,t",  MATCH_SH1ADD, MASK_SH1ADD, match_opcode, 0 },
++{"sh2add",    0, INSN_CLASS_B_OR_ZBA,   "d,s,t",  MATCH_SH2ADD, MASK_SH2ADD, match_opcode, 0 },
++{"sh3add",    0, INSN_CLASS_B_OR_ZBA,   "d,s,t",  MATCH_SH3ADD, MASK_SH3ADD, match_opcode, 0 },
++{"clmul",     0, INSN_CLASS_B_OR_ZBC,   "d,s,t",  MATCH_CLMUL, MASK_CLMUL, match_opcode, 0 },
++{"clmulh",    0, INSN_CLASS_B_OR_ZBC,   "d,s,t",  MATCH_CLMULH, MASK_CLMULH, match_opcode, 0 },
++{"clmulr",    0, INSN_CLASS_B_OR_ZBC,   "d,s,t",  MATCH_CLMULR, MASK_CLMULR, match_opcode, 0 },
++{"min",       0, INSN_CLASS_B_OR_ZBB,   "d,s,t",  MATCH_MIN, MASK_MIN, match_opcode, 0 },
++{"max",       0, INSN_CLASS_B_OR_ZBB,   "d,s,t",  MATCH_MAX, MASK_MAX, match_opcode, 0 },
++{"minu",      0, INSN_CLASS_B_OR_ZBB,   "d,s,t",  MATCH_MINU, MASK_MINU, match_opcode, 0 },
++{"maxu",      0, INSN_CLASS_B_OR_ZBB,   "d,s,t",  MATCH_MAXU, MASK_MAXU, match_opcode, 0 },
++{"shfli",     0, INSN_CLASS_B_OR_ZBP,   "d,s,|",  MATCH_SHFLI, MASK_SHFLI, match_opcode, 0 },
++{"unshfli",   0, INSN_CLASS_B_OR_ZBP,   "d,s,|",  MATCH_UNSHFLI, MASK_UNSHFLI, match_opcode, 0 },
++{"shfl",      0, INSN_CLASS_B_OR_ZBP,   "d,s,t",  MATCH_SHFL, MASK_SHFL, match_opcode, 0 },
++{"shfl",      0, INSN_CLASS_B_OR_ZBP,   "d,s,|",  MATCH_SHFLI, MASK_SHFLI, match_opcode, INSN_ALIAS },
++{"unshfl",    0, INSN_CLASS_B_OR_ZBP,   "d,s,t",  MATCH_UNSHFL, MASK_UNSHFL, match_opcode, 0 },
++{"unshfl",    0, INSN_CLASS_B_OR_ZBP,   "d,s,|",  MATCH_UNSHFLI, MASK_UNSHFLI, match_opcode, INSN_ALIAS },
++{"bdep",      0, INSN_CLASS_B_OR_ZBE,   "d,s,t",  MATCH_BDEP, MASK_BDEP, match_opcode, 0 },
++{"bext",      0, INSN_CLASS_B_OR_ZBE,   "d,s,t",  MATCH_BEXT, MASK_BEXT, match_opcode, 0 },
++{"pack",      0, INSN_CLASS_B_OR_ZBB_OR_ZBP,   "d,s,t",  MATCH_PACK, MASK_PACK, match_opcode, 0 },
++{"packu",     0, INSN_CLASS_B_OR_ZBB_OR_ZBP,   "d,s,t",  MATCH_PACKU, MASK_PACKU, match_opcode, 0 },
++{"packh",     0, INSN_CLASS_B_OR_ZBB_OR_ZBP,   "d,s,t",  MATCH_PACKH, MASK_PACKH, match_opcode, 0 },
++{"bmator",   64, INSN_CLASS_B_OR_ZBM,   "d,s,t",  MATCH_BMATOR, MASK_BMATOR, match_opcode, 0 },
++{"bmatxor",  64, INSN_CLASS_B_OR_ZBM,   "d,s,t",  MATCH_BMATXOR, MASK_BMATXOR, match_opcode, 0 },
++{"bfp",       0, INSN_CLASS_B_OR_ZBF,   "d,s,t",  MATCH_BFP, MASK_BFP, match_opcode, 0 },
++{"addiwu",   64, INSN_CLASS_B_OR_ZBB,   "d,s,j",  MATCH_ADDIWU, MASK_ADDIWU, match_opcode, 0 },
++{"slliu.w",  64, INSN_CLASS_B_OR_ZBB,   "d,s,>",  MATCH_SLLIU_W, MASK_SLLIU_W, match_opcode, 0 },
++{"addwu",    64, INSN_CLASS_B_OR_ZBB,   "d,s,t",  MATCH_ADDWU, MASK_ADDWU, match_opcode, 0 },
++{"subwu",    64, INSN_CLASS_B_OR_ZBB,   "d,s,t",  MATCH_SUBWU, MASK_SUBWU, match_opcode, 0 },
++{"addu.w",   64, INSN_CLASS_B_OR_ZBB,   "d,s,t",  MATCH_ADDU_W, MASK_ADDU_W, match_opcode, 0 },
++{"subu.w",   64, INSN_CLASS_B_OR_ZBB,   "d,s,t",  MATCH_SUBU_W, MASK_SUBU_W, match_opcode, 0 },
++{"sloiw",    64, INSN_CLASS_B_OR_ZBP,   "d,s,<",  MATCH_SLOIW, MASK_SLOIW, match_opcode, 0 },
++{"sroiw",    64, INSN_CLASS_B_OR_ZBP,   "d,s,<",  MATCH_SROIW, MASK_SROIW, match_opcode, 0 },
++{"roliw",    64, INSN_CLASS_B_OR_ZBB_OR_ZBP,   "d,s,<",  0, (int) M_RL, match_never, INSN_MACRO },
++{"roriw",    64, INSN_CLASS_B_OR_ZBB_OR_ZBP,   "d,s,<",  MATCH_RORIW, MASK_RORIW, match_opcode, 0 },
++{"slow",     64, INSN_CLASS_B_OR_ZBP,   "d,s,t",  MATCH_SLOW, MASK_SLOW, match_opcode, 0 },
++{"slow",     64, INSN_CLASS_B_OR_ZBP,   "d,s,<",  MATCH_SLOIW, MASK_SLOIW, match_opcode, INSN_ALIAS },
++{"srow",     64, INSN_CLASS_B_OR_ZBP,   "d,s,t",  MATCH_SROW, MASK_SROW, match_opcode, 0 },
++{"srow",     64, INSN_CLASS_B_OR_ZBP,   "d,s,<",  MATCH_SROIW, MASK_SROIW, match_opcode, INSN_ALIAS },
++{"rolw",     64, INSN_CLASS_B_OR_ZBB_OR_ZBP,   "d,s,t",  MATCH_ROLW, MASK_ROLW, match_opcode, 0 },
++{"rolw",     64, INSN_CLASS_B_OR_ZBB_OR_ZBP,   "d,s,<",  0, (int) M_RL, match_never, INSN_MACRO },
++{"rorw",     64, INSN_CLASS_B_OR_ZBB_OR_ZBP,   "d,s,t",  MATCH_RORW, MASK_RORW, match_opcode, 0 },
++{"rorw",     64, INSN_CLASS_B_OR_ZBB_OR_ZBP,   "d,s,<",  MATCH_RORIW, MASK_RORIW, match_opcode, INSN_ALIAS },
++{"sbclriw",  64, INSN_CLASS_B_OR_ZBS,   "d,s,<",  MATCH_SBCLRIW, MASK_SBCLRIW, match_opcode, 0 },
++{"sbsetiw",  64, INSN_CLASS_B_OR_ZBS,   "d,s,<",  MATCH_SBSETIW, MASK_SBSETIW, match_opcode, 0 },
++{"sbinviw",  64, INSN_CLASS_B_OR_ZBS,   "d,s,<",  MATCH_SBINVIW, MASK_SBINVIW, match_opcode, 0 },
++{"gorciw",   64, INSN_CLASS_B_OR_ZBP,   "d,s,<",  MATCH_GORCIW, MASK_GORCIW, match_opcode, 0 },
++{"greviw",   64, INSN_CLASS_B_OR_ZBP,   "d,s,<",  MATCH_GREVIW, MASK_GREVIW, match_opcode, 0 },
++{"sbclrw",   64, INSN_CLASS_B_OR_ZBS,   "d,s,t",  MATCH_SBCLRW, MASK_SBCLRW, match_opcode, 0 },
++{"sbclrw",   64, INSN_CLASS_B_OR_ZBS,   "d,s,<",  MATCH_SBCLRIW, MASK_SBCLRIW, match_opcode, INSN_ALIAS },
++{"sbsetw",   64, INSN_CLASS_B_OR_ZBS,   "d,s,t",  MATCH_SBSETW, MASK_SBSETW, match_opcode, 0 },
++{"sbsetw",   64, INSN_CLASS_B_OR_ZBS,   "d,s,<",  MATCH_SBSETIW, MASK_SBSETIW, match_opcode, INSN_ALIAS },
++{"sbinvw",   64, INSN_CLASS_B_OR_ZBS,   "d,s,t",  MATCH_SBINVW, MASK_SBINVW, match_opcode, 0 },
++{"sbinvw",   64, INSN_CLASS_B_OR_ZBS,   "d,s,<",  MATCH_SBINVIW, MASK_SBINVIW, match_opcode, INSN_ALIAS },
++{"sbextw",   64, INSN_CLASS_B_OR_ZBS,   "d,s,t",  MATCH_SBEXTW, MASK_SBEXTW, match_opcode, 0 },
++{"gorcw",    64, INSN_CLASS_B_OR_ZBP,   "d,s,t",  MATCH_GORCW, MASK_GORCW, match_opcode, 0 },
++{"gorcw",    64, INSN_CLASS_B_OR_ZBP,   "d,s,<",  MATCH_GORCIW, MASK_GORCIW, match_opcode, INSN_ALIAS },
++{"grevw",    64, INSN_CLASS_B_OR_ZBP,   "d,s,t",  MATCH_GREVW, MASK_GREVW, match_opcode, 0 },
++{"grevw",    64, INSN_CLASS_B_OR_ZBP,   "d,s,<",  MATCH_GREVIW, MASK_GREVIW, match_opcode, INSN_ALIAS },
++{"fsliw",    64, INSN_CLASS_B_OR_ZBT,   "d,s,r,<",  0, (int) M_FL, match_never, INSN_MACRO },
++{"fsriw",    64, INSN_CLASS_B_OR_ZBT,   "d,s,r,<",  MATCH_FSRIW, MASK_FSRIW, match_opcode, 0 },
++{"fslw",     64, INSN_CLASS_B_OR_ZBT,   "d,s,r,t",  MATCH_FSLW, MASK_FSLW, match_opcode, 0 },
++{"fslw",     64, INSN_CLASS_B_OR_ZBT,   "d,s,r,<",  0, (int) M_FL, match_never, INSN_MACRO },
++{"fsrw",     64, INSN_CLASS_B_OR_ZBT,   "d,s,r,t",  MATCH_FSRW, MASK_FSRW, match_opcode, 0 },
++{"fsrw",     64, INSN_CLASS_B_OR_ZBT,   "d,s,r,<",  MATCH_FSRIW, MASK_FSRIW, match_opcode, INSN_ALIAS },
++{"clzw",     64, INSN_CLASS_B_OR_ZBB,   "d,s",  MATCH_CLZW, MASK_CLZW, match_opcode, 0 },
++{"ctzw",     64, INSN_CLASS_B_OR_ZBB,   "d,s",  MATCH_CTZW, MASK_CTZW, match_opcode, 0 },
++{"pcntw",    64, INSN_CLASS_B_OR_ZBB,   "d,s",  MATCH_PCNTW, MASK_PCNTW, match_opcode, 0 },
++{"sh1addu.w",64, INSN_CLASS_B_OR_ZBA,   "d,s,t",  MATCH_SH1ADDU_W, MASK_SH1ADDU_W, match_opcode, 0 },
++{"sh2addu.w",64, INSN_CLASS_B_OR_ZBA,   "d,s,t",  MATCH_SH2ADDU_W, MASK_SH2ADDU_W, match_opcode, 0 },
++{"sh3addu.w",64, INSN_CLASS_B_OR_ZBA,   "d,s,t",  MATCH_SH3ADDU_W, MASK_SH3ADDU_W, match_opcode, 0 },
++{"clmulw",   64, INSN_CLASS_B_OR_ZBC,   "d,s,t",  MATCH_CLMULW, MASK_CLMULW, match_opcode, 0 },
++{"clmulhw",  64, INSN_CLASS_B_OR_ZBC,   "d,s,t",  MATCH_CLMULHW, MASK_CLMULHW, match_opcode, 0 },
++{"clmulrw",  64, INSN_CLASS_B_OR_ZBC,   "d,s,t",  MATCH_CLMULRW, MASK_CLMULRW, match_opcode, 0 },
++{"shflw",    64, INSN_CLASS_B_OR_ZBP,   "d,s,t",  MATCH_SHFLW, MASK_SHFLW, match_opcode, 0 },
++{"unshflw",  64, INSN_CLASS_B_OR_ZBP,   "d,s,t",  MATCH_UNSHFLW, MASK_UNSHFLW, match_opcode, 0 },
++{"bdepw",    64, INSN_CLASS_B_OR_ZBE,   "d,s,t",  MATCH_BDEPW, MASK_BDEPW, match_opcode, 0 },
++{"bextw",    64, INSN_CLASS_B_OR_ZBE,   "d,s,t",  MATCH_BEXTW, MASK_BEXTW, match_opcode, 0 },
++{"packw",    64, INSN_CLASS_B_OR_ZBB_OR_ZBP,   "d,s,t",  MATCH_PACKW, MASK_PACKW, match_opcode, 0 },
++{"packuw",   64, INSN_CLASS_B_OR_ZBB_OR_ZBP,   "d,s,t",  MATCH_PACKUW, MASK_PACKUW, match_opcode, 0 },
++{"bfpw",     64, INSN_CLASS_B_OR_ZBF,   "d,s,t",  MATCH_BFPW, MASK_BFPW, match_opcode, 0 },
++
++/* Bitmanip pseudo-instructions */
++{"rev.p",     0, INSN_CLASS_B_OR_ZBB_OR_ZBP,   "d,s",  0, (int) M_PERM, match_never, INSN_MACRO },
++{"rev2.n",    0, INSN_CLASS_B_OR_ZBB_OR_ZBP,   "d,s",  0, (int) M_PERM, match_never, INSN_MACRO },
++{"rev.n",     0, INSN_CLASS_B_OR_ZBB_OR_ZBP,   "d,s",  0, (int) M_PERM, match_never, INSN_MACRO },
++{"rev4.b",    0, INSN_CLASS_B_OR_ZBB_OR_ZBP,   "d,s",  0, (int) M_PERM, match_never, INSN_MACRO },
++{"rev2.b",    0, INSN_CLASS_B_OR_ZBB_OR_ZBP,   "d,s",  0, (int) M_PERM, match_never, INSN_MACRO },
++{"rev.b",     0, INSN_CLASS_B_OR_ZBB_OR_ZBP,   "d,s",  0, (int) M_PERM, match_never, INSN_MACRO },
++{"rev8.h",    0, INSN_CLASS_B_OR_ZBB_OR_ZBP,   "d,s",  0, (int) M_PERM, match_never, INSN_MACRO },
++{"rev4.h",    0, INSN_CLASS_B_OR_ZBB_OR_ZBP,   "d,s",  0, (int) M_PERM, match_never, INSN_MACRO },
++{"rev2.h",    0, INSN_CLASS_B_OR_ZBB_OR_ZBP,   "d,s",  0, (int) M_PERM, match_never, INSN_MACRO },
++{"rev.h",     0, INSN_CLASS_B_OR_ZBB_OR_ZBP,   "d,s",  0, (int) M_PERM, match_never, INSN_MACRO },
++{"rev16.w",  64, INSN_CLASS_B_OR_ZBB_OR_ZBP,   "d,s",  0, (int) M_PERM, match_never, INSN_MACRO },
++{"rev8.w",   64, INSN_CLASS_B_OR_ZBB_OR_ZBP,   "d,s",  0, (int) M_PERM, match_never, INSN_MACRO },
++{"rev4.w",   64, INSN_CLASS_B_OR_ZBB_OR_ZBP,   "d,s",  0, (int) M_PERM, match_never, INSN_MACRO },
++{"rev2.w",   64, INSN_CLASS_B_OR_ZBB_OR_ZBP,   "d,s",  0, (int) M_PERM, match_never, INSN_MACRO },
++{"rev.w",    64, INSN_CLASS_B_OR_ZBB_OR_ZBP,   "d,s",  0, (int) M_PERM, match_never, INSN_MACRO },
++{"rev32",    64, INSN_CLASS_B_OR_ZBB_OR_ZBP,   "d,s",  0, (int) M_PERM, match_never, INSN_MACRO },
++{"rev16",     0, INSN_CLASS_B_OR_ZBB_OR_ZBP,   "d,s",  0, (int) M_PERM, match_never, INSN_MACRO },
++{"rev8",      0, INSN_CLASS_B_OR_ZBB_OR_ZBP,   "d,s",  0, (int) M_PERM, match_never, INSN_MACRO },
++{"rev4",      0, INSN_CLASS_B_OR_ZBB_OR_ZBP,   "d,s",  0, (int) M_PERM, match_never, INSN_MACRO },
++{"rev2",      0, INSN_CLASS_B_OR_ZBB_OR_ZBP,   "d,s",  0, (int) M_PERM, match_never, INSN_MACRO },
++{"rev",       0, INSN_CLASS_B_OR_ZBB_OR_ZBP,   "d,s",  0, (int) M_PERM, match_never, INSN_MACRO },
++
++{"orc.p",     0, INSN_CLASS_B_OR_ZBB_OR_ZBP,   "d,s",  0, (int) M_PERM, match_never, INSN_MACRO },
++{"orc2.n",    0, INSN_CLASS_B_OR_ZBB_OR_ZBP,   "d,s",  0, (int) M_PERM, match_never, INSN_MACRO },
++{"orc.n",     0, INSN_CLASS_B_OR_ZBB_OR_ZBP,   "d,s",  0, (int) M_PERM, match_never, INSN_MACRO },
++{"orc4.b",    0, INSN_CLASS_B_OR_ZBB_OR_ZBP,   "d,s",  0, (int) M_PERM, match_never, INSN_MACRO },
++{"orc2.b",    0, INSN_CLASS_B_OR_ZBB_OR_ZBP,   "d,s",  0, (int) M_PERM, match_never, INSN_MACRO },
++{"orc.b",     0, INSN_CLASS_B_OR_ZBB_OR_ZBP,   "d,s",  0, (int) M_PERM, match_never, INSN_MACRO },
++{"orc8.h",    0, INSN_CLASS_B_OR_ZBB_OR_ZBP,   "d,s",  0, (int) M_PERM, match_never, INSN_MACRO },
++{"orc4.h",    0, INSN_CLASS_B_OR_ZBB_OR_ZBP,   "d,s",  0, (int) M_PERM, match_never, INSN_MACRO },
++{"orc2.h",    0, INSN_CLASS_B_OR_ZBB_OR_ZBP,   "d,s",  0, (int) M_PERM, match_never, INSN_MACRO },
++{"orc.h",     0, INSN_CLASS_B_OR_ZBB_OR_ZBP,   "d,s",  0, (int) M_PERM, match_never, INSN_MACRO },
++{"orc16.w",  64, INSN_CLASS_B_OR_ZBB_OR_ZBP,   "d,s",  0, (int) M_PERM, match_never, INSN_MACRO },
++{"orc8.w",   64, INSN_CLASS_B_OR_ZBB_OR_ZBP,   "d,s",  0, (int) M_PERM, match_never, INSN_MACRO },
++{"orc4.w",   64, INSN_CLASS_B_OR_ZBB_OR_ZBP,   "d,s",  0, (int) M_PERM, match_never, INSN_MACRO },
++{"orc2.w",   64, INSN_CLASS_B_OR_ZBB_OR_ZBP,   "d,s",  0, (int) M_PERM, match_never, INSN_MACRO },
++{"orc.w",    64, INSN_CLASS_B_OR_ZBB_OR_ZBP,   "d,s",  0, (int) M_PERM, match_never, INSN_MACRO },
++{"orc32",    64, INSN_CLASS_B_OR_ZBB_OR_ZBP,   "d,s",  0, (int) M_PERM, match_never, INSN_MACRO },
++{"orc16",     0, INSN_CLASS_B_OR_ZBB_OR_ZBP,   "d,s",  0, (int) M_PERM, match_never, INSN_MACRO },
++{"orc8",      0, INSN_CLASS_B_OR_ZBB_OR_ZBP,   "d,s",  0, (int) M_PERM, match_never, INSN_MACRO },
++{"orc4",      0, INSN_CLASS_B_OR_ZBB_OR_ZBP,   "d,s",  0, (int) M_PERM, match_never, INSN_MACRO },
++{"orc2",      0, INSN_CLASS_B_OR_ZBB_OR_ZBP,   "d,s",  0, (int) M_PERM, match_never, INSN_MACRO },
++{"orc",       0, INSN_CLASS_B_OR_ZBB_OR_ZBP,   "d,s",  0, (int) M_PERM, match_never, INSN_MACRO },
++
++{"zip.n",     0, INSN_CLASS_B_OR_ZBP,   "d,s",  0, (int) M_PERM, match_never, INSN_MACRO },
++{"zip2.b",    0, INSN_CLASS_B_OR_ZBP,   "d,s",  0, (int) M_PERM, match_never, INSN_MACRO },
++{"zip.b",     0, INSN_CLASS_B_OR_ZBP,   "d,s",  0, (int) M_PERM, match_never, INSN_MACRO },
++{"zip4.h",    0, INSN_CLASS_B_OR_ZBP,   "d,s",  0, (int) M_PERM, match_never, INSN_MACRO },
++{"zip2.h",    0, INSN_CLASS_B_OR_ZBP,   "d,s",  0, (int) M_PERM, match_never, INSN_MACRO },
++{"zip.h",     0, INSN_CLASS_B_OR_ZBP,   "d,s",  0, (int) M_PERM, match_never, INSN_MACRO },
++{"zip8.w",   64, INSN_CLASS_B_OR_ZBP,   "d,s",  0, (int) M_PERM, match_never, INSN_MACRO },
++{"zip4.w",   64, INSN_CLASS_B_OR_ZBP,   "d,s",  0, (int) M_PERM, match_never, INSN_MACRO },
++{"zip2.w",   64, INSN_CLASS_B_OR_ZBP,   "d,s",  0, (int) M_PERM, match_never, INSN_MACRO },
++{"zip.w",    64, INSN_CLASS_B_OR_ZBP,   "d,s",  0, (int) M_PERM, match_never, INSN_MACRO },
++{"zip16",    64, INSN_CLASS_B_OR_ZBP,   "d,s",  0, (int) M_PERM, match_never, INSN_MACRO },
++{"zip8",      0, INSN_CLASS_B_OR_ZBP,   "d,s",  0, (int) M_PERM, match_never, INSN_MACRO },
++{"zip4",      0, INSN_CLASS_B_OR_ZBP,   "d,s",  0, (int) M_PERM, match_never, INSN_MACRO },
++{"zip2",      0, INSN_CLASS_B_OR_ZBP,   "d,s",  0, (int) M_PERM, match_never, INSN_MACRO },
++{"zip",       0, INSN_CLASS_B_OR_ZBP,   "d,s",  0, (int) M_PERM, match_never, INSN_MACRO },
++
++{"unzip.n",   0, INSN_CLASS_B_OR_ZBP,   "d,s",  0, (int) M_PERM, match_never, INSN_MACRO },
++{"unzip2.b",  0, INSN_CLASS_B_OR_ZBP,   "d,s",  0, (int) M_PERM, match_never, INSN_MACRO },
++{"unzip.b",   0, INSN_CLASS_B_OR_ZBP,   "d,s",  0, (int) M_PERM, match_never, INSN_MACRO },
++{"unzip4.h",  0, INSN_CLASS_B_OR_ZBP,   "d,s",  0, (int) M_PERM, match_never, INSN_MACRO },
++{"unzip2.h",  0, INSN_CLASS_B_OR_ZBP,   "d,s",  0, (int) M_PERM, match_never, INSN_MACRO },
++{"unzip.h",   0, INSN_CLASS_B_OR_ZBP,   "d,s",  0, (int) M_PERM, match_never, INSN_MACRO },
++{"unzip8.w", 64, INSN_CLASS_B_OR_ZBP,   "d,s",  0, (int) M_PERM, match_never, INSN_MACRO },
++{"unzip4.w", 64, INSN_CLASS_B_OR_ZBP,   "d,s",  0, (int) M_PERM, match_never, INSN_MACRO },
++{"unzip2.w", 64, INSN_CLASS_B_OR_ZBP,   "d,s",  0, (int) M_PERM, match_never, INSN_MACRO },
++{"unzip.w",  64, INSN_CLASS_B_OR_ZBP,   "d,s",  0, (int) M_PERM, match_never, INSN_MACRO },
++{"unzip16",  64, INSN_CLASS_B_OR_ZBP,   "d,s",  0, (int) M_PERM, match_never, INSN_MACRO },
++{"unzip8",    0, INSN_CLASS_B_OR_ZBP,   "d,s",  0, (int) M_PERM, match_never, INSN_MACRO },
++{"unzip4",    0, INSN_CLASS_B_OR_ZBP,   "d,s",  0, (int) M_PERM, match_never, INSN_MACRO },
++{"unzip2",    0, INSN_CLASS_B_OR_ZBP,   "d,s",  0, (int) M_PERM, match_never, INSN_MACRO },
++{"unzip",     0, INSN_CLASS_B_OR_ZBP,   "d,s",  0, (int) M_PERM, match_never, INSN_MACRO },
++
+ /* Single-precision floating-point instruction subset */
+ {"frcsr",     0, INSN_CLASS_F,   "d",  MATCH_FRCSR, MASK_FRCSR, match_opcode, INSN_ALIAS },
+ {"frsr",      0, INSN_CLASS_F,   "d",  MATCH_FRCSR, MASK_FRCSR, match_opcode, INSN_ALIAS },
+-- 
+2.33.0
+

+ 70 - 0
recipes-devtools/gdb/files/0037-RISC-V-Support-sub-extensions-of-B-for-march-parser.patch

@@ -0,0 +1,70 @@
+From 9a13033a9799982d53f47f853f8322ce6ed8246e Mon Sep 17 00:00:00 2001
+From: Kito Cheng <kito.cheng@sifive.com>
+Date: Tue, 3 Nov 2020 01:28:01 -0800
+Subject: [PATCH 37/48] RISC-V: Support sub-extensions of B for -march parser
+
+---
+ bfd/elfxx-riscv.c                                 |  1 +
+ gas/testsuite/gas/riscv/attribute-15-unratified.d |  4 ++--
+ opcodes/riscv-opc.c                               | 13 +++++++++++++
+ 3 files changed, 16 insertions(+), 2 deletions(-)
+
+diff --git a/bfd/elfxx-riscv.c b/bfd/elfxx-riscv.c
+index 67dbc2e682..75add5be1c 100644
+--- a/bfd/elfxx-riscv.c
++++ b/bfd/elfxx-riscv.c
+@@ -1567,6 +1567,7 @@ riscv_parse_prefixed_ext (riscv_parse_subset_t *rps,
+ static const char * const riscv_std_z_ext_strtab[] =
+ {
+   "zicsr", "zifencei", "zfh",
++  "zba", "zbb", "zbc", "zbe", "zbf", "zbm", "zbp", "zbr", "zbs", "zbt",
+   "zvamo", "zvediv", "zvlsseg", "zvqmac",
+   NULL
+ };
+diff --git a/gas/testsuite/gas/riscv/attribute-15-unratified.d b/gas/testsuite/gas/riscv/attribute-15-unratified.d
+index 09d64edbe6..4645762bd6 100644
+--- a/gas/testsuite/gas/riscv/attribute-15-unratified.d
++++ b/gas/testsuite/gas/riscv/attribute-15-unratified.d
+@@ -1,6 +1,6 @@
+-#as: -march-attr -march=rv32ifv_zvamo_zvediv_zvlsseg_zvqmac
++#as: -march-attr -march=rv32ibv_zfh_zba_zbb_zbc_zbe_zbf_zbm_zbp_zbr_zbs_zbt_zvamo_zvediv_zvlsseg_zvqmac
+ #readelf: -A
+ #source: empty.s
+ Attribute Section: riscv
+ File Attributes
+-  Tag_RISCV_arch: ".*_v1p0_zvamo1p0_zvediv1p0_zvlsseg1p0_zvqmac1p0"
++  Tag_RISCV_arch: ".*_b0p92_v1p0_zfh0p1_zba0p92_zbb0p92_zbc0p92_zbe0p92_zbf0p92_zbm0p92_zbp0p92_zbr0p92_zbs0p92_zbt0p92_zvamo1p0_zvediv1p0_zvlsseg1p0_zvqmac1p0"
+diff --git a/opcodes/riscv-opc.c b/opcodes/riscv-opc.c
+index 1869f545cf..bf36ada39c 100644
+--- a/opcodes/riscv-opc.c
++++ b/opcodes/riscv-opc.c
+@@ -2758,6 +2758,8 @@ const struct riscv_ext_version riscv_ext_version_table[] =
+ {"c", ISA_SPEC_CLASS_20190608, 2, 0},
+ {"c", ISA_SPEC_CLASS_2P2,      2, 0},
+ 
++{"b", ISA_SPEC_CLASS_NONE,     0, 92},
++
+ {"v", ISA_SPEC_CLASS_NONE,     1, 0},
+ 
+ {"zicsr", ISA_SPEC_CLASS_20191213, 2, 0},
+@@ -2768,6 +2770,17 @@ const struct riscv_ext_version riscv_ext_version_table[] =
+ 
+ {"zfh", ISA_SPEC_CLASS_NONE, 0, 1},
+ 
++{"zba", ISA_SPEC_CLASS_NONE, 0, 92},
++{"zbb", ISA_SPEC_CLASS_NONE, 0, 92},
++{"zbc", ISA_SPEC_CLASS_NONE, 0, 92},
++{"zbe", ISA_SPEC_CLASS_NONE, 0, 92},
++{"zbf", ISA_SPEC_CLASS_NONE, 0, 92},
++{"zbm", ISA_SPEC_CLASS_NONE, 0, 92},
++{"zbp", ISA_SPEC_CLASS_NONE, 0, 92},
++{"zbr", ISA_SPEC_CLASS_NONE, 0, 92},
++{"zbs", ISA_SPEC_CLASS_NONE, 0, 92},
++{"zbt", ISA_SPEC_CLASS_NONE, 0, 92},
++
+ {"zvamo",   ISA_SPEC_CLASS_NONE, 1, 0},
+ {"zvediv",  ISA_SPEC_CLASS_NONE, 1, 0},
+ {"zvlsseg", ISA_SPEC_CLASS_NONE, 1, 0},
+-- 
+2.33.0
+

+ 130 - 0
recipes-devtools/gdb/files/0038-RISC-V-Remove-ld-testcases-which-should-be-better-to.patch

@@ -0,0 +1,130 @@
+From 31eeed0afbce4c38d140b48cda1c379d18a67bef Mon Sep 17 00:00:00 2001
+From: Nelson Chu <nelson.chu@sifive.com>
+Date: Thu, 3 Dec 2020 16:17:40 +0800
+Subject: [PATCH 38/48] RISC-V: Remove ld testcases which should be better to
+ put into gas.
+
+---
+ ld/testsuite/ld-riscv-elf/attr-dupl-arch-z-failed-01.d     | 3 ---
+ ld/testsuite/ld-riscv-elf/attr-dupl-arch-z-failed-01.s     | 1 -
+ ld/testsuite/ld-riscv-elf/attr-order-arch-z-failed-01.d    | 3 ---
+ ld/testsuite/ld-riscv-elf/attr-order-arch-z-failed-01.s    | 1 -
+ ld/testsuite/ld-riscv-elf/attr-order-arch-z-failed-02.d    | 3 ---
+ ld/testsuite/ld-riscv-elf/attr-order-arch-z-failed-02.s    | 1 -
+ ld/testsuite/ld-riscv-elf/attr-tooshort-arch-z-failed-01.d | 3 ---
+ ld/testsuite/ld-riscv-elf/attr-tooshort-arch-z-failed-01.s | 1 -
+ ld/testsuite/ld-riscv-elf/attr-unknown-arch-z-failed-01.d  | 3 ---
+ ld/testsuite/ld-riscv-elf/attr-unknown-arch-z-failed-01.s  | 1 -
+ ld/testsuite/ld-riscv-elf/ld-riscv-elf.exp                 | 6 ------
+ 11 files changed, 26 deletions(-)
+ delete mode 100644 ld/testsuite/ld-riscv-elf/attr-dupl-arch-z-failed-01.d
+ delete mode 100644 ld/testsuite/ld-riscv-elf/attr-dupl-arch-z-failed-01.s
+ delete mode 100644 ld/testsuite/ld-riscv-elf/attr-order-arch-z-failed-01.d
+ delete mode 100644 ld/testsuite/ld-riscv-elf/attr-order-arch-z-failed-01.s
+ delete mode 100644 ld/testsuite/ld-riscv-elf/attr-order-arch-z-failed-02.d
+ delete mode 100644 ld/testsuite/ld-riscv-elf/attr-order-arch-z-failed-02.s
+ delete mode 100644 ld/testsuite/ld-riscv-elf/attr-tooshort-arch-z-failed-01.d
+ delete mode 100644 ld/testsuite/ld-riscv-elf/attr-tooshort-arch-z-failed-01.s
+ delete mode 100644 ld/testsuite/ld-riscv-elf/attr-unknown-arch-z-failed-01.d
+ delete mode 100644 ld/testsuite/ld-riscv-elf/attr-unknown-arch-z-failed-01.s
+
+diff --git a/ld/testsuite/ld-riscv-elf/attr-dupl-arch-z-failed-01.d b/ld/testsuite/ld-riscv-elf/attr-dupl-arch-z-failed-01.d
+deleted file mode 100644
+index 20b4530f0a..0000000000
+--- a/ld/testsuite/ld-riscv-elf/attr-dupl-arch-z-failed-01.d
++++ /dev/null
+@@ -1,3 +0,0 @@
+-#source: attr-dupl-arch-z-failed-01.s
+-#as: -march-attr
+-#error: -march=rv32i2p0_zbc_zbc: Duplicate Z ISA extension: 'zbc'
+diff --git a/ld/testsuite/ld-riscv-elf/attr-dupl-arch-z-failed-01.s b/ld/testsuite/ld-riscv-elf/attr-dupl-arch-z-failed-01.s
+deleted file mode 100644
+index 96d67e1833..0000000000
+--- a/ld/testsuite/ld-riscv-elf/attr-dupl-arch-z-failed-01.s
++++ /dev/null
+@@ -1 +0,0 @@
+-	.attribute arch, "rv32i2p0_zbc_zbc"
+diff --git a/ld/testsuite/ld-riscv-elf/attr-order-arch-z-failed-01.d b/ld/testsuite/ld-riscv-elf/attr-order-arch-z-failed-01.d
+deleted file mode 100644
+index 809d8ba607..0000000000
+--- a/ld/testsuite/ld-riscv-elf/attr-order-arch-z-failed-01.d
++++ /dev/null
+@@ -1,3 +0,0 @@
+-#source: attr-order-arch-z-failed-01.s
+-#as: -march-attr
+-#error: -march=rv32i2p0_zbc_zbb: Z ISA extension not in alphabetical order: 'zbb' must come before 'zbc'.
+diff --git a/ld/testsuite/ld-riscv-elf/attr-order-arch-z-failed-01.s b/ld/testsuite/ld-riscv-elf/attr-order-arch-z-failed-01.s
+deleted file mode 100644
+index e31e3766ca..0000000000
+--- a/ld/testsuite/ld-riscv-elf/attr-order-arch-z-failed-01.s
++++ /dev/null
+@@ -1 +0,0 @@
+-	.attribute arch, "rv32i2p0_zbc_zbb"
+diff --git a/ld/testsuite/ld-riscv-elf/attr-order-arch-z-failed-02.d b/ld/testsuite/ld-riscv-elf/attr-order-arch-z-failed-02.d
+deleted file mode 100644
+index 19a5482300..0000000000
+--- a/ld/testsuite/ld-riscv-elf/attr-order-arch-z-failed-02.d
++++ /dev/null
+@@ -1,3 +0,0 @@
+-#source: attr-order-arch-z-failed-02.s
+-#as: -march-attr
+-#error: -march=rv32i2p0_xsillyname_zbb: unexpected ISA string at end: zbb
+diff --git a/ld/testsuite/ld-riscv-elf/attr-order-arch-z-failed-02.s b/ld/testsuite/ld-riscv-elf/attr-order-arch-z-failed-02.s
+deleted file mode 100644
+index b1abe26891..0000000000
+--- a/ld/testsuite/ld-riscv-elf/attr-order-arch-z-failed-02.s
++++ /dev/null
+@@ -1 +0,0 @@
+-	.attribute arch, "rv32i2p0_xsillyname_zbb"
+diff --git a/ld/testsuite/ld-riscv-elf/attr-tooshort-arch-z-failed-01.d b/ld/testsuite/ld-riscv-elf/attr-tooshort-arch-z-failed-01.d
+deleted file mode 100644
+index 4a6885db5e..0000000000
+--- a/ld/testsuite/ld-riscv-elf/attr-tooshort-arch-z-failed-01.d
++++ /dev/null
+@@ -1,3 +0,0 @@
+-#source: attr-tooshort-arch-z-failed-01.s
+-#as: -march-attr
+-#error: -march=rv32i2p0_z: Literal 'z' is an invalid Z ISA extension specifier.
+diff --git a/ld/testsuite/ld-riscv-elf/attr-tooshort-arch-z-failed-01.s b/ld/testsuite/ld-riscv-elf/attr-tooshort-arch-z-failed-01.s
+deleted file mode 100644
+index 7ca87fabf4..0000000000
+--- a/ld/testsuite/ld-riscv-elf/attr-tooshort-arch-z-failed-01.s
++++ /dev/null
+@@ -1 +0,0 @@
+-	.attribute arch, "rv32i2p0_z"
+diff --git a/ld/testsuite/ld-riscv-elf/attr-unknown-arch-z-failed-01.d b/ld/testsuite/ld-riscv-elf/attr-unknown-arch-z-failed-01.d
+deleted file mode 100644
+index 343db87a41..0000000000
+--- a/ld/testsuite/ld-riscv-elf/attr-unknown-arch-z-failed-01.d
++++ /dev/null
+@@ -1,3 +0,0 @@
+-#source: attr-unknown-arch-z-failed-01.s
+-#as: -march-attr
+-#error: -march=rv32i2p0_zsillyname: Unknown Z ISA extension: 'zsillyname'
+diff --git a/ld/testsuite/ld-riscv-elf/attr-unknown-arch-z-failed-01.s b/ld/testsuite/ld-riscv-elf/attr-unknown-arch-z-failed-01.s
+deleted file mode 100644
+index 6e16bef91d..0000000000
+--- a/ld/testsuite/ld-riscv-elf/attr-unknown-arch-z-failed-01.s
++++ /dev/null
+@@ -1 +0,0 @@
+-	.attribute arch, "rv32i2p0_zsillyname"
+diff --git a/ld/testsuite/ld-riscv-elf/ld-riscv-elf.exp b/ld/testsuite/ld-riscv-elf/ld-riscv-elf.exp
+index 4df5d740e1..2c008d4c35 100644
+--- a/ld/testsuite/ld-riscv-elf/ld-riscv-elf.exp
++++ b/ld/testsuite/ld-riscv-elf/ld-riscv-elf.exp
+@@ -47,12 +47,6 @@ if [istarget "riscv*-*-*"] {
+     run_dump_test "attr-merge-priv-spec-failed-04"
+     run_dump_test "attr-merge-priv-spec-failed-05"
+     run_dump_test "attr-merge-priv-spec-failed-06"
+-    run_dump_test "attr-merge-arch-z-failed-01"
+-    run_dump_test "attr-dupl-arch-z-failed-01"
+-    run_dump_test "attr-order-arch-z-failed-01"
+-    run_dump_test "attr-order-arch-z-failed-02"
+-    run_dump_test "attr-tooshort-arch-z-failed-01"
+-    run_dump_test "attr-unknown-arch-z-failed-01"
+     run_ld_link_tests {
+ 	{ "Weak reference 32" "-T weakref.ld -melf32lriscv" ""
+ 	    "-march=rv32i -mabi=ilp32" {weakref32.s}
+-- 
+2.33.0
+

+ 152 - 0
recipes-devtools/gdb/files/0039-RISC-V-Added-Removed-Updated-instructions-to-the-ris.patch

@@ -0,0 +1,152 @@
+From 9f3047973b9f80b2b95989c86762502e456e59cf Mon Sep 17 00:00:00 2001
+From: Nelson Chu <nelson.chu@sifive.com>
+Date: Thu, 3 Dec 2020 15:35:49 +0800
+Subject: [PATCH 39/48] RISC-V: Added/Removed/Updated instructions to the
+ riscv-bitmanip-20201107.
+
+* Added xperm.[nbhw] instructions.
+* Regularized min vs. minu encoding to match slt vs. sltu (swap minu and max).
+* Removed add[i]wu, subwu and clmul[rh]w.
+---
+ include/opcode/riscv-opc.h | 34 ++++++++++++++--------------------
+ opcodes/riscv-opc.c        | 10 ++++------
+ 2 files changed, 18 insertions(+), 26 deletions(-)
+
+diff --git a/include/opcode/riscv-opc.h b/include/opcode/riscv-opc.h
+index 426db0ca5f..500be26f0f 100644
+--- a/include/opcode/riscv-opc.h
++++ b/include/opcode/riscv-opc.h
+@@ -279,9 +279,9 @@
+ #define MASK_CLMULH  0xfe00707f
+ #define MATCH_MIN 0xa004033
+ #define MASK_MIN  0xfe00707f
+-#define MATCH_MAX 0xa005033
++#define MATCH_MAX 0xa006033
+ #define MASK_MAX  0xfe00707f
+-#define MATCH_MINU 0xa006033
++#define MATCH_MINU 0xa005033
+ #define MASK_MINU  0xfe00707f
+ #define MATCH_MAXU 0xa007033
+ #define MASK_MAXU  0xfe00707f
+@@ -289,6 +289,12 @@
+ #define MASK_SHFL  0xfe00707f
+ #define MATCH_UNSHFL 0x8005033
+ #define MASK_UNSHFL  0xfe00707f
++#define MATCH_XPERMN 0x28002033
++#define MASK_XPERMN 0xfe00707f
++#define MATCH_XPERMB 0x28004033
++#define MASK_XPERMB 0xfe00707f
++#define MATCH_XPERMH 0x28006033
++#define MASK_XPERMH 0xfe00707f
+ #define MATCH_BEXT 0x8006033
+ #define MASK_BEXT  0xfe00707f
+ #define MATCH_BDEP 0x48006033
+@@ -315,14 +321,8 @@
+ #define MASK_BMATOR  0xfe00707f
+ #define MATCH_BMATXOR 0x48003033
+ #define MASK_BMATXOR  0xfe00707f
+-#define MATCH_ADDIWU 0x401b
+-#define MASK_ADDIWU  0x707f
+ #define MATCH_SLLIU_W 0x800101b
+ #define MASK_SLLIU_W  0xfc00707f
+-#define MATCH_ADDWU 0xa00003b
+-#define MASK_ADDWU  0xfe00707f
+-#define MATCH_SUBWU 0x4a00003b
+-#define MASK_SUBWU  0xfe00707f
+ #define MATCH_ADDU_W 0x800003b
+ #define MASK_ADDU_W  0xfe00707f
+ #define MATCH_SUBU_W 0x4800003b
+@@ -381,16 +381,12 @@
+ #define MASK_SH2ADDU_W  0xfe00707f
+ #define MATCH_SH3ADDU_W 0x2000603b
+ #define MASK_SH3ADDU_W  0xfe00707f
+-#define MATCH_CLMULW 0xa00103b
+-#define MASK_CLMULW  0xfe00707f
+-#define MATCH_CLMULRW 0xa00203b
+-#define MASK_CLMULRW  0xfe00707f
+-#define MATCH_CLMULHW 0xa00303b
+-#define MASK_CLMULHW  0xfe00707f
+ #define MATCH_SHFLW 0x800103b
+ #define MASK_SHFLW  0xfe00707f
+ #define MATCH_UNSHFLW 0x800503b
+ #define MASK_UNSHFLW  0xfe00707f
++#define MATCH_XPERMW 0x28000033
++#define MASK_XPERMW 0xfe00707f
+ #define MATCH_BEXTW 0x800603b
+ #define MASK_BEXTW  0xfe00707f
+ #define MATCH_BDEPW 0x4800603b
+@@ -3706,6 +3702,9 @@ DECLARE_INSN(minu, MATCH_MINU, MASK_MINU)
+ DECLARE_INSN(maxu, MATCH_MAXU, MASK_MAXU)
+ DECLARE_INSN(shfl, MATCH_SHFL, MASK_SHFL)
+ DECLARE_INSN(unshfl, MATCH_UNSHFL, MASK_UNSHFL)
++DECLARE_INSN(xperm_n, MATCH_XPERMN, MASK_XPERMN)
++DECLARE_INSN(xperm_b, MATCH_XPERMB, MASK_XPERMB)
++DECLARE_INSN(xperm_h, MATCH_XPERMH, MASK_XPERMH)
+ DECLARE_INSN(bext, MATCH_BEXT, MASK_BEXT)
+ DECLARE_INSN(bdep, MATCH_BDEP, MASK_BDEP)
+ DECLARE_INSN(pack, MATCH_PACK, MASK_PACK)
+@@ -3719,10 +3718,7 @@ DECLARE_INSN(crc32_d, MATCH_CRC32_D, MASK_CRC32_D)
+ DECLARE_INSN(crc32c_d, MATCH_CRC32C_D, MASK_CRC32C_D)
+ DECLARE_INSN(bmator, MATCH_BMATOR, MASK_BMATOR)
+ DECLARE_INSN(bmatxor, MATCH_BMATXOR, MASK_BMATXOR)
+-DECLARE_INSN(addiwu, MATCH_ADDIWU, MASK_ADDIWU)
+ DECLARE_INSN(slliu_w, MATCH_SLLIU_W, MASK_SLLIU_W)
+-DECLARE_INSN(addwu, MATCH_ADDWU, MASK_ADDWU)
+-DECLARE_INSN(subwu, MATCH_SUBWU, MASK_SUBWU)
+ DECLARE_INSN(addu_w, MATCH_ADDU_W, MASK_ADDU_W)
+ DECLARE_INSN(subu_w, MATCH_SUBU_W, MASK_SUBU_W)
+ DECLARE_INSN(slow, MATCH_SLOW, MASK_SLOW)
+@@ -3752,11 +3748,9 @@ DECLARE_INSN(pcntw, MATCH_PCNTW, MASK_PCNTW)
+ DECLARE_INSN(sh1addu_w, MATCH_SH1ADDU_W, MASK_SH1ADDU_W)
+ DECLARE_INSN(sh2addu_w, MATCH_SH2ADDU_W, MASK_SH2ADDU_W)
+ DECLARE_INSN(sh3addu_w, MATCH_SH3ADDU_W, MASK_SH3ADDU_W)
+-DECLARE_INSN(clmulw, MATCH_CLMULW, MASK_CLMULW)
+-DECLARE_INSN(clmulrw, MATCH_CLMULRW, MASK_CLMULRW)
+-DECLARE_INSN(clmulhw, MATCH_CLMULHW, MASK_CLMULHW)
+ DECLARE_INSN(shflw, MATCH_SHFLW, MASK_SHFLW)
+ DECLARE_INSN(unshflw, MATCH_UNSHFLW, MASK_UNSHFLW)
++DECLARE_INSN(xperm_w, MATCH_XPERMW, MASK_XPERMW)
+ DECLARE_INSN(bextw, MATCH_BEXTW, MASK_BEXTW)
+ DECLARE_INSN(bdepw, MATCH_BDEPW, MASK_BDEPW)
+ DECLARE_INSN(packw, MATCH_PACKW, MASK_PACKW)
+diff --git a/opcodes/riscv-opc.c b/opcodes/riscv-opc.c
+index bf36ada39c..f55e1281ed 100644
+--- a/opcodes/riscv-opc.c
++++ b/opcodes/riscv-opc.c
+@@ -1056,6 +1056,9 @@ const struct riscv_opcode riscv_opcodes[] =
+ {"shfl",      0, INSN_CLASS_B_OR_ZBP,   "d,s,|",  MATCH_SHFLI, MASK_SHFLI, match_opcode, INSN_ALIAS },
+ {"unshfl",    0, INSN_CLASS_B_OR_ZBP,   "d,s,t",  MATCH_UNSHFL, MASK_UNSHFL, match_opcode, 0 },
+ {"unshfl",    0, INSN_CLASS_B_OR_ZBP,   "d,s,|",  MATCH_UNSHFLI, MASK_UNSHFLI, match_opcode, INSN_ALIAS },
++{"xperm.n",   0, INSN_CLASS_B_OR_ZBP,   "d,s,t",  MATCH_XPERMN, MASK_XPERMN, match_opcode, 0 },
++{"xperm.b",   0, INSN_CLASS_B_OR_ZBP,   "d,s,t",  MATCH_XPERMB, MASK_XPERMB, match_opcode, 0 },
++{"xperm.h",   0, INSN_CLASS_B_OR_ZBP,   "d,s,t",  MATCH_XPERMH, MASK_XPERMH, match_opcode, 0 },
+ {"bdep",      0, INSN_CLASS_B_OR_ZBE,   "d,s,t",  MATCH_BDEP, MASK_BDEP, match_opcode, 0 },
+ {"bext",      0, INSN_CLASS_B_OR_ZBE,   "d,s,t",  MATCH_BEXT, MASK_BEXT, match_opcode, 0 },
+ {"pack",      0, INSN_CLASS_B_OR_ZBB_OR_ZBP,   "d,s,t",  MATCH_PACK, MASK_PACK, match_opcode, 0 },
+@@ -1064,10 +1067,7 @@ const struct riscv_opcode riscv_opcodes[] =
+ {"bmator",   64, INSN_CLASS_B_OR_ZBM,   "d,s,t",  MATCH_BMATOR, MASK_BMATOR, match_opcode, 0 },
+ {"bmatxor",  64, INSN_CLASS_B_OR_ZBM,   "d,s,t",  MATCH_BMATXOR, MASK_BMATXOR, match_opcode, 0 },
+ {"bfp",       0, INSN_CLASS_B_OR_ZBF,   "d,s,t",  MATCH_BFP, MASK_BFP, match_opcode, 0 },
+-{"addiwu",   64, INSN_CLASS_B_OR_ZBB,   "d,s,j",  MATCH_ADDIWU, MASK_ADDIWU, match_opcode, 0 },
+ {"slliu.w",  64, INSN_CLASS_B_OR_ZBB,   "d,s,>",  MATCH_SLLIU_W, MASK_SLLIU_W, match_opcode, 0 },
+-{"addwu",    64, INSN_CLASS_B_OR_ZBB,   "d,s,t",  MATCH_ADDWU, MASK_ADDWU, match_opcode, 0 },
+-{"subwu",    64, INSN_CLASS_B_OR_ZBB,   "d,s,t",  MATCH_SUBWU, MASK_SUBWU, match_opcode, 0 },
+ {"addu.w",   64, INSN_CLASS_B_OR_ZBB,   "d,s,t",  MATCH_ADDU_W, MASK_ADDU_W, match_opcode, 0 },
+ {"subu.w",   64, INSN_CLASS_B_OR_ZBB,   "d,s,t",  MATCH_SUBU_W, MASK_SUBU_W, match_opcode, 0 },
+ {"sloiw",    64, INSN_CLASS_B_OR_ZBP,   "d,s,<",  MATCH_SLOIW, MASK_SLOIW, match_opcode, 0 },
+@@ -1110,11 +1110,9 @@ const struct riscv_opcode riscv_opcodes[] =
+ {"sh1addu.w",64, INSN_CLASS_B_OR_ZBA,   "d,s,t",  MATCH_SH1ADDU_W, MASK_SH1ADDU_W, match_opcode, 0 },
+ {"sh2addu.w",64, INSN_CLASS_B_OR_ZBA,   "d,s,t",  MATCH_SH2ADDU_W, MASK_SH2ADDU_W, match_opcode, 0 },
+ {"sh3addu.w",64, INSN_CLASS_B_OR_ZBA,   "d,s,t",  MATCH_SH3ADDU_W, MASK_SH3ADDU_W, match_opcode, 0 },
+-{"clmulw",   64, INSN_CLASS_B_OR_ZBC,   "d,s,t",  MATCH_CLMULW, MASK_CLMULW, match_opcode, 0 },
+-{"clmulhw",  64, INSN_CLASS_B_OR_ZBC,   "d,s,t",  MATCH_CLMULHW, MASK_CLMULHW, match_opcode, 0 },
+-{"clmulrw",  64, INSN_CLASS_B_OR_ZBC,   "d,s,t",  MATCH_CLMULRW, MASK_CLMULRW, match_opcode, 0 },
+ {"shflw",    64, INSN_CLASS_B_OR_ZBP,   "d,s,t",  MATCH_SHFLW, MASK_SHFLW, match_opcode, 0 },
+ {"unshflw",  64, INSN_CLASS_B_OR_ZBP,   "d,s,t",  MATCH_UNSHFLW, MASK_UNSHFLW, match_opcode, 0 },
++{"xperm.w",  64, INSN_CLASS_B_OR_ZBP,   "d,s,t",  MATCH_XPERMW, MASK_XPERMW, match_opcode, 0 },
+ {"bdepw",    64, INSN_CLASS_B_OR_ZBE,   "d,s,t",  MATCH_BDEPW, MASK_BDEPW, match_opcode, 0 },
+ {"bextw",    64, INSN_CLASS_B_OR_ZBE,   "d,s,t",  MATCH_BEXTW, MASK_BEXTW, match_opcode, 0 },
+ {"packw",    64, INSN_CLASS_B_OR_ZBB_OR_ZBP,   "d,s,t",  MATCH_PACKW, MASK_PACKW, match_opcode, 0 },
+-- 
+2.33.0
+

+ 128 - 0
recipes-devtools/gdb/files/0040-RISC-V-Add-missing-zext.-hw-pseudo-instructions.patch

@@ -0,0 +1,128 @@
+From 6d82557fb262e1b17d523ee34a76f8216918ff26 Mon Sep 17 00:00:00 2001
+From: Nelson Chu <nelson.chu@sifive.com>
+Date: Thu, 3 Dec 2020 17:47:35 +0800
+Subject: [PATCH 40/48] RISC-V: Add missing zext.[hw] pseudo instructions.
+
+I only add the zext pseudo which will be converted to the physical
+b-ext instrcution.  As for the zext.b, it should be controlled by i-ext,
+and be added to FSF binutils directly, not here.
+---
+ gas/testsuite/gas/riscv/zext-32.d         | 11 +++++++++++
+ gas/testsuite/gas/riscv/zext-64.d         | 12 ++++++++++++
+ gas/testsuite/gas/riscv/zext-noalias-32.d | 11 +++++++++++
+ gas/testsuite/gas/riscv/zext-noalias-64.d | 12 ++++++++++++
+ gas/testsuite/gas/riscv/zext.s            |  6 ++++++
+ opcodes/riscv-opc.c                       |  3 +++
+ 6 files changed, 55 insertions(+)
+ create mode 100644 gas/testsuite/gas/riscv/zext-32.d
+ create mode 100644 gas/testsuite/gas/riscv/zext-64.d
+ create mode 100644 gas/testsuite/gas/riscv/zext-noalias-32.d
+ create mode 100644 gas/testsuite/gas/riscv/zext-noalias-64.d
+ create mode 100644 gas/testsuite/gas/riscv/zext.s
+
+diff --git a/gas/testsuite/gas/riscv/zext-32.d b/gas/testsuite/gas/riscv/zext-32.d
+new file mode 100644
+index 0000000000..9111177941
+--- /dev/null
++++ b/gas/testsuite/gas/riscv/zext-32.d
+@@ -0,0 +1,11 @@
++#as: -march=rv32ib
++#source: zext.s
++#objdump: -d
++
++.*:[ 	]+file format .*
++
++
++Disassembly of section .text:
++
++0+000 <target>:
++[ 	]+0:[ 	]+0805c533[ 	]+zext.h[ 	]+a0,a1
+diff --git a/gas/testsuite/gas/riscv/zext-64.d b/gas/testsuite/gas/riscv/zext-64.d
+new file mode 100644
+index 0000000000..3b0955a00f
+--- /dev/null
++++ b/gas/testsuite/gas/riscv/zext-64.d
+@@ -0,0 +1,12 @@
++#as: -march=rv64ib -defsym __64_bit__=1
++#source: zext.s
++#objdump: -d
++
++.*:[ 	]+file format .*
++
++
++Disassembly of section .text:
++
++0+000 <target>:
++[ 	]+0:[ 	]+0805c53b[ 	]+zext.h[ 	]+a0,a1
++[ 	]+4:[ 	]+0805853b[ 	]+zext.w[ 	]+a0,a1
+diff --git a/gas/testsuite/gas/riscv/zext-noalias-32.d b/gas/testsuite/gas/riscv/zext-noalias-32.d
+new file mode 100644
+index 0000000000..bdecbc2fc2
+--- /dev/null
++++ b/gas/testsuite/gas/riscv/zext-noalias-32.d
+@@ -0,0 +1,11 @@
++#as: -march=rv32ib
++#source: zext.s
++#objdump: -d -Mno-aliases
++
++.*:[ 	]+file format .*
++
++
++Disassembly of section .text:
++
++0+000 <target>:
++[ 	]+0:[ 	]+0805c533[ 	]+pack[ 	]+a0,a1,zero
+diff --git a/gas/testsuite/gas/riscv/zext-noalias-64.d b/gas/testsuite/gas/riscv/zext-noalias-64.d
+new file mode 100644
+index 0000000000..8dfd77bf43
+--- /dev/null
++++ b/gas/testsuite/gas/riscv/zext-noalias-64.d
+@@ -0,0 +1,12 @@
++#as: -march=rv64ib -defsym __64_bit__=1
++#source: zext.s
++#objdump: -d -Mno-aliases
++
++.*:[ 	]+file format .*
++
++
++Disassembly of section .text:
++
++0+000 <target>:
++[ 	]+0:[ 	]+0805c53b[ 	]+packw[ 	]+a0,a1,zero
++[ 	]+4:[ 	]+0805853b[ 	]+addu.w[ 	]+a0,a1,zero
+diff --git a/gas/testsuite/gas/riscv/zext.s b/gas/testsuite/gas/riscv/zext.s
+new file mode 100644
+index 0000000000..e2e127d949
+--- /dev/null
++++ b/gas/testsuite/gas/riscv/zext.s
+@@ -0,0 +1,6 @@
++target:
++	zext.h	a0, a1
++
++.ifdef __64_bit__
++	zext.w  a0, a1
++.endif
+diff --git a/opcodes/riscv-opc.c b/opcodes/riscv-opc.c
+index f55e1281ed..dbabc5c2f6 100644
+--- a/opcodes/riscv-opc.c
++++ b/opcodes/riscv-opc.c
+@@ -1061,6 +1061,8 @@ const struct riscv_opcode riscv_opcodes[] =
+ {"xperm.h",   0, INSN_CLASS_B_OR_ZBP,   "d,s,t",  MATCH_XPERMH, MASK_XPERMH, match_opcode, 0 },
+ {"bdep",      0, INSN_CLASS_B_OR_ZBE,   "d,s,t",  MATCH_BDEP, MASK_BDEP, match_opcode, 0 },
+ {"bext",      0, INSN_CLASS_B_OR_ZBE,   "d,s,t",  MATCH_BEXT, MASK_BEXT, match_opcode, 0 },
++{"zext.h",   32, INSN_CLASS_B_OR_ZBB_OR_ZBP,   "d,s",  MATCH_PACK, MASK_PACK | MASK_RS2, match_opcode, INSN_ALIAS },
++{"zext.h",   64, INSN_CLASS_B_OR_ZBB_OR_ZBP,   "d,s",  MATCH_PACKW, MASK_PACKW | MASK_RS2, match_opcode, INSN_ALIAS },
+ {"pack",      0, INSN_CLASS_B_OR_ZBB_OR_ZBP,   "d,s,t",  MATCH_PACK, MASK_PACK, match_opcode, 0 },
+ {"packu",     0, INSN_CLASS_B_OR_ZBB_OR_ZBP,   "d,s,t",  MATCH_PACKU, MASK_PACKU, match_opcode, 0 },
+ {"packh",     0, INSN_CLASS_B_OR_ZBB_OR_ZBP,   "d,s,t",  MATCH_PACKH, MASK_PACKH, match_opcode, 0 },
+@@ -1068,6 +1070,7 @@ const struct riscv_opcode riscv_opcodes[] =
+ {"bmatxor",  64, INSN_CLASS_B_OR_ZBM,   "d,s,t",  MATCH_BMATXOR, MASK_BMATXOR, match_opcode, 0 },
+ {"bfp",       0, INSN_CLASS_B_OR_ZBF,   "d,s,t",  MATCH_BFP, MASK_BFP, match_opcode, 0 },
+ {"slliu.w",  64, INSN_CLASS_B_OR_ZBB,   "d,s,>",  MATCH_SLLIU_W, MASK_SLLIU_W, match_opcode, 0 },
++{"zext.w",   64, INSN_CLASS_B_OR_ZBB_OR_ZBP,   "d,s",  MATCH_ADDU_W, MASK_ADDU_W | MASK_RS2, match_opcode, INSN_ALIAS },
+ {"addu.w",   64, INSN_CLASS_B_OR_ZBB,   "d,s,t",  MATCH_ADDU_W, MASK_ADDU_W, match_opcode, 0 },
+ {"subu.w",   64, INSN_CLASS_B_OR_ZBB,   "d,s,t",  MATCH_SUBU_W, MASK_SUBU_W, match_opcode, 0 },
+ {"sloiw",    64, INSN_CLASS_B_OR_ZBP,   "d,s,<",  MATCH_SLOIW, MASK_SLOIW, match_opcode, 0 },
+-- 
+2.33.0
+

+ 552 - 0
recipes-devtools/gdb/files/0041-RISC-V-Re-define-zba-zbb-zbc-and-zbs-extensions.patch

@@ -0,0 +1,552 @@
+From f6a5298d5c929a9d30fa56ddc14d686892f9bafc Mon Sep 17 00:00:00 2001
+From: Nelson Chu <nelson.chu@sifive.com>
+Date: Mon, 7 Dec 2020 16:25:05 +0800
+Subject: [PATCH 41/48] RISC-V: Re-define zba, zbb, zbc and zbs extensions.
+
+Andrew had re-defined zba, zbb, zbc and zbs on the tech-bitmanip mail list.
+Other instructions and sub-extensions are still discussing, so I change their
+type to INSN_CLASS_B, to keep the encodings and implementations, but we
+do need to re-define them in the future.
+
+Besides, B includes all of the zb*, except zbr and zbt.
+---
+ gas/config/tc-riscv.c  |  38 ++--
+ include/opcode/riscv.h |  14 +-
+ opcodes/riscv-opc.c    | 409 +++++++++++++++++++++--------------------
+ 3 files changed, 232 insertions(+), 229 deletions(-)
+
+diff --git a/gas/config/tc-riscv.c b/gas/config/tc-riscv.c
+index b53442b8b4..b1b86a7afb 100644
+--- a/gas/config/tc-riscv.c
++++ b/gas/config/tc-riscv.c
+@@ -260,39 +260,35 @@ riscv_multi_subset_supports (enum riscv_insn_class insn_class)
+     case INSN_CLASS_V_AND_ZVQMAC:
+       return riscv_subset_supports ("v") && riscv_subset_supports ("zvqmac");
+ 
+-    case INSN_CLASS_B_OR_ZBB:
+-      return riscv_subset_supports ("b") || riscv_subset_supports ("zbb");
+-
++    /* Sure.  */
+     case INSN_CLASS_B_OR_ZBA:
+       return riscv_subset_supports ("b") || riscv_subset_supports ("zba");
+-
++    case INSN_CLASS_B_OR_ZBB:
++      return riscv_subset_supports ("b") || riscv_subset_supports ("zbb");
+     case INSN_CLASS_B_OR_ZBC:
+       return riscv_subset_supports ("b") || riscv_subset_supports ("zbc");
+-
++    case INSN_CLASS_B_OR_ZBS:
++      return riscv_subset_supports ("b") || riscv_subset_supports ("zbs");
++    case INSN_CLASS_B_OR_ZBA_OR_ZBB:
++      return (riscv_subset_supports ("b")
++	      || riscv_subset_supports ("zba")
++	      || riscv_subset_supports ("zbb"));
++
++    /* Not sure.  */
++    case INSN_CLASS_B:
++      return riscv_subset_supports ("b");
+     case INSN_CLASS_B_OR_ZBE:
+       return riscv_subset_supports ("b") || riscv_subset_supports ("zbe");
+-
+     case INSN_CLASS_B_OR_ZBF:
+       return riscv_subset_supports ("b") || riscv_subset_supports ("zbf");
+-
+     case INSN_CLASS_B_OR_ZBM:
+       return riscv_subset_supports ("b") || riscv_subset_supports ("zbm");
+-
+     case INSN_CLASS_B_OR_ZBP:
+       return riscv_subset_supports ("b") || riscv_subset_supports ("zbp");
+-
+-    case INSN_CLASS_B_OR_ZBR:
+-      return riscv_subset_supports ("b") || riscv_subset_supports ("zbr");
+-
+-    case INSN_CLASS_B_OR_ZBS:
+-      return riscv_subset_supports ("b") || riscv_subset_supports ("zbs");
+-
+-    case INSN_CLASS_B_OR_ZBT:
+-      return riscv_subset_supports ("b") || riscv_subset_supports ("zbt");
+-
+-    case INSN_CLASS_B_OR_ZBB_OR_ZBP:
+-      return riscv_subset_supports ("b") || riscv_subset_supports ("zbb")
+-	|| riscv_subset_supports ("zbp");
++    case INSN_CLASS_ZBR:
++      return riscv_subset_supports ("zbr");
++    case INSN_CLASS_ZBT:
++      return riscv_subset_supports ("zbt");
+ 
+     default:
+       as_fatal ("Unreachable");
+diff --git a/include/opcode/riscv.h b/include/opcode/riscv.h
+index 5303d14998..a23a2a8002 100644
+--- a/include/opcode/riscv.h
++++ b/include/opcode/riscv.h
+@@ -379,6 +379,7 @@ enum riscv_insn_class
+    INSN_CLASS_F,
+    INSN_CLASS_D,
+    INSN_CLASS_Q,
++   INSN_CLASS_B,
+    INSN_CLASS_V,
+    INSN_CLASS_F_AND_C,
+    INSN_CLASS_F_AND_ZFH,
+@@ -390,19 +391,18 @@ enum riscv_insn_class
+    INSN_CLASS_V_AND_ZVEDIV,
+    INSN_CLASS_V_OR_ZVLSSEG,
+    INSN_CLASS_V_AND_ZVQMAC,
+-
+-   INSN_CLASS_B,
+-   INSN_CLASS_B_OR_ZBT,
+-   INSN_CLASS_B_OR_ZBR,
+-   INSN_CLASS_B_OR_ZBB,
+    INSN_CLASS_B_OR_ZBA,
++   INSN_CLASS_B_OR_ZBB,
+    INSN_CLASS_B_OR_ZBC,
++   INSN_CLASS_B_OR_ZBS,
++   INSN_CLASS_B_OR_ZBA_OR_ZBB,
++
+    INSN_CLASS_B_OR_ZBE,
+    INSN_CLASS_B_OR_ZBF,
+    INSN_CLASS_B_OR_ZBM,
+    INSN_CLASS_B_OR_ZBP,
+-   INSN_CLASS_B_OR_ZBS,
+-   INSN_CLASS_B_OR_ZBB_OR_ZBP
++   INSN_CLASS_ZBR,
++   INSN_CLASS_ZBT,
+   };
+ 
+ /* This structure holds information for a particular instruction.  */
+diff --git a/opcodes/riscv-opc.c b/opcodes/riscv-opc.c
+index dbabc5c2f6..86cfcabec9 100644
+--- a/opcodes/riscv-opc.c
++++ b/opcodes/riscv-opc.c
+@@ -984,220 +984,227 @@ const struct riscv_opcode riscv_opcodes[] =
+ {"fcvt.h.lu", 64, INSN_CLASS_F_AND_ZFH,   "D,s",  MATCH_FCVT_H_LU | MASK_RM, MASK_FCVT_H_L | MASK_RM, match_opcode, 0 },
+ {"fcvt.h.lu", 64, INSN_CLASS_F_AND_ZFH,   "D,s,m",  MATCH_FCVT_H_LU, MASK_FCVT_H_LU, match_opcode, 0 },
+ 
+-/* Bitmanip instruction subset */
+-{"andn",      0, INSN_CLASS_B_OR_ZBB_OR_ZBP,   "d,s,t",  MATCH_ANDN, MASK_ANDN, match_opcode, 0 },
+-{"orn",       0, INSN_CLASS_B_OR_ZBB_OR_ZBP,   "d,s,t",  MATCH_ORN, MASK_ORN, match_opcode, 0 },
+-{"xnor",      0, INSN_CLASS_B_OR_ZBB_OR_ZBP,   "d,s,t",  MATCH_XNOR, MASK_XNOR, match_opcode, 0 },
+-{"sloi",      0, INSN_CLASS_B_OR_ZBP,   "d,s,>",  MATCH_SLOI, MASK_SLOI, match_opcode, 0 },
+-{"sroi",      0, INSN_CLASS_B_OR_ZBP,   "d,s,>",  MATCH_SROI, MASK_SROI, match_opcode, 0 },
+-{"roli",      0, INSN_CLASS_B_OR_ZBB_OR_ZBP,   "d,s,>",  0, (int) M_RL, match_never, INSN_MACRO },
+-{"rori",      0, INSN_CLASS_B_OR_ZBB_OR_ZBP,   "d,s,>",  MATCH_RORI, MASK_RORI, match_opcode, 0 },
+-{"slo",       0, INSN_CLASS_B_OR_ZBP,   "d,s,t",  MATCH_SLO, MASK_SLO, match_opcode, 0 },
+-{"slo",       0, INSN_CLASS_B_OR_ZBP,   "d,s,>",  MATCH_SLOI, MASK_SLOI, match_opcode, INSN_ALIAS },
+-{"sro",       0, INSN_CLASS_B_OR_ZBP,   "d,s,t",  MATCH_SRO, MASK_SRO, match_opcode, 0 },
+-{"sro",       0, INSN_CLASS_B_OR_ZBP,   "d,s,>",  MATCH_SROI, MASK_SROI, match_opcode, INSN_ALIAS },
+-{"rol",       0, INSN_CLASS_B_OR_ZBB_OR_ZBP,   "d,s,t",  MATCH_ROL, MASK_ROL, match_opcode, 0 },
+-{"rol",       0, INSN_CLASS_B_OR_ZBB_OR_ZBP,   "d,s,>",  0, (int) M_RL, match_never, INSN_MACRO },
+-{"ror",       0, INSN_CLASS_B_OR_ZBB_OR_ZBP,   "d,s,t",  MATCH_ROR, MASK_ROR, match_opcode, 0 },
+-{"ror",       0, INSN_CLASS_B_OR_ZBB_OR_ZBP,   "d,s,>",  MATCH_RORI, MASK_RORI, match_opcode, INSN_ALIAS },
+-{"sbclri",    0, INSN_CLASS_B_OR_ZBS,   "d,s,>",  MATCH_SBCLRI, MASK_SBCLRI, match_opcode, 0 },
+-{"sbseti",    0, INSN_CLASS_B_OR_ZBS,   "d,s,>",  MATCH_SBSETI, MASK_SBSETI, match_opcode, 0 },
+-{"sbinvi",    0, INSN_CLASS_B_OR_ZBS,   "d,s,>",  MATCH_SBINVI, MASK_SBINVI, match_opcode, 0 },
+-{"sbexti",    0, INSN_CLASS_B_OR_ZBS,   "d,s,>",  MATCH_SBEXTI, MASK_SBEXTI, match_opcode, 0 },
+-{"gorci",     0, INSN_CLASS_B_OR_ZBP,   "d,s,>",  MATCH_GORCI, MASK_GORCI, match_opcode, 0 },
+-{"grevi",     0, INSN_CLASS_B_OR_ZBP,   "d,s,>",  MATCH_GREVI, MASK_GREVI, match_opcode, 0 },
+-{"sbclr",     0, INSN_CLASS_B_OR_ZBS,   "d,s,t",  MATCH_SBCLR, MASK_SBCLR, match_opcode, 0 },
+-{"sbclr",     0, INSN_CLASS_B_OR_ZBS,   "d,s,>",  MATCH_SBCLRI, MASK_SBCLRI, match_opcode, INSN_ALIAS },
+-{"sbset",     0, INSN_CLASS_B_OR_ZBS,   "d,s,t",  MATCH_SBSET, MASK_SBSET, match_opcode, 0 },
+-{"sbset",     0, INSN_CLASS_B_OR_ZBS,   "d,s,>",  MATCH_SBSETI, MASK_SBSETI, match_opcode, INSN_ALIAS },
+-{"sbinv",     0, INSN_CLASS_B_OR_ZBS,   "d,s,t",  MATCH_SBINV, MASK_SBINV, match_opcode, 0 },
+-{"sbinv",     0, INSN_CLASS_B_OR_ZBS,   "d,s,>",  MATCH_SBINVI, MASK_SBINVI, match_opcode, INSN_ALIAS },
+-{"sbext",     0, INSN_CLASS_B_OR_ZBS,   "d,s,t",  MATCH_SBEXT, MASK_SBEXT, match_opcode, 0 },
+-{"sbext",     0, INSN_CLASS_B_OR_ZBS,   "d,s,>",  MATCH_SBEXTI, MASK_SBEXTI, match_opcode, INSN_ALIAS },
+-{"gorc",      0, INSN_CLASS_B_OR_ZBP,   "d,s,t",  MATCH_GORC, MASK_GORC, match_opcode, 0 },
+-{"gorc",      0, INSN_CLASS_B_OR_ZBP,   "d,s,>",  MATCH_GORCI, MASK_GORCI, match_opcode, INSN_ALIAS },
+-{"grev",      0, INSN_CLASS_B_OR_ZBP,   "d,s,t",  MATCH_GREV, MASK_GREV, match_opcode, 0 },
+-{"grev",      0, INSN_CLASS_B_OR_ZBP,   "d,s,>",  MATCH_GREVI, MASK_GREVI, match_opcode, INSN_ALIAS },
+-{"cmix",      0, INSN_CLASS_B_OR_ZBT,   "d,t,s,r",  MATCH_CMIX, MASK_CMIX, match_opcode, 0 },
+-{"cmov",      0, INSN_CLASS_B_OR_ZBT,   "d,t,s,r",  MATCH_CMOV, MASK_CMOV, match_opcode, 0 },
+-{"fsli",      0, INSN_CLASS_B_OR_ZBT,   "d,s,r,>",  0, (int) M_FL, match_never, INSN_MACRO },
+-{"fsri",      0, INSN_CLASS_B_OR_ZBT,   "d,s,r,>",  MATCH_FSRI, MASK_FSRI, match_opcode, 0 },
+-{"fsl",       0, INSN_CLASS_B_OR_ZBT,   "d,s,r,t",  MATCH_FSL, MASK_FSL, match_opcode, 0 },
+-{"fsl",       0, INSN_CLASS_B_OR_ZBT,   "d,s,r,>",  0, (int) M_FL, match_never, INSN_MACRO },
+-{"fsr",       0, INSN_CLASS_B_OR_ZBT,   "d,s,r,t",  MATCH_FSR, MASK_FSR, match_opcode, 0 },
+-{"fsr",       0, INSN_CLASS_B_OR_ZBT,   "d,s,r,>",  MATCH_FSRI, MASK_FSRI, match_opcode, INSN_ALIAS },
++/* Bitmanip instruction subset - for sure  */
++{"sh1add",    0, INSN_CLASS_B_OR_ZBA,   "d,s,t",  MATCH_SH1ADD, MASK_SH1ADD, match_opcode, 0 },
++{"sh2add",    0, INSN_CLASS_B_OR_ZBA,   "d,s,t",  MATCH_SH2ADD, MASK_SH2ADD, match_opcode, 0 },
++{"sh3add",    0, INSN_CLASS_B_OR_ZBA,   "d,s,t",  MATCH_SH3ADD, MASK_SH3ADD, match_opcode, 0 },
++{"slliu.w",  64, INSN_CLASS_B_OR_ZBA,   "d,s,>",  MATCH_SLLIU_W, MASK_SLLIU_W, match_opcode, 0 },
++{"zext.w",   64, INSN_CLASS_B_OR_ZBA_OR_ZBB,   "d,s",  MATCH_ADDU_W, MASK_ADDU_W | MASK_RS2, match_opcode, INSN_ALIAS },
++{"addu.w",   64, INSN_CLASS_B_OR_ZBA,   "d,s,t",  MATCH_ADDU_W, MASK_ADDU_W, match_opcode, 0 },
++{"sh1addu.w",64, INSN_CLASS_B_OR_ZBA,   "d,s,t",  MATCH_SH1ADDU_W, MASK_SH1ADDU_W, match_opcode, 0 },
++{"sh2addu.w",64, INSN_CLASS_B_OR_ZBA,   "d,s,t",  MATCH_SH2ADDU_W, MASK_SH2ADDU_W, match_opcode, 0 },
++{"sh3addu.w",64, INSN_CLASS_B_OR_ZBA,   "d,s,t",  MATCH_SH3ADDU_W, MASK_SH3ADDU_W, match_opcode, 0 },
++
+ {"clz",       0, INSN_CLASS_B_OR_ZBB,   "d,s",  MATCH_CLZ, MASK_CLZ, match_opcode, 0 },
+ {"ctz",       0, INSN_CLASS_B_OR_ZBB,   "d,s",  MATCH_CTZ, MASK_CTZ, match_opcode, 0 },
+ {"pcnt",      0, INSN_CLASS_B_OR_ZBB,   "d,s",  MATCH_PCNT, MASK_PCNT, match_opcode, 0 },
++{"min",       0, INSN_CLASS_B_OR_ZBB,   "d,s,t",  MATCH_MIN, MASK_MIN, match_opcode, 0 },
++{"max",       0, INSN_CLASS_B_OR_ZBB,   "d,s,t",  MATCH_MAX, MASK_MAX, match_opcode, 0 },
++{"minu",      0, INSN_CLASS_B_OR_ZBB,   "d,s,t",  MATCH_MINU, MASK_MINU, match_opcode, 0 },
++{"maxu",      0, INSN_CLASS_B_OR_ZBB,   "d,s,t",  MATCH_MAXU, MASK_MAXU, match_opcode, 0 },
++{"andn",      0, INSN_CLASS_B_OR_ZBB,   "d,s,t",  MATCH_ANDN, MASK_ANDN, match_opcode, 0 },
++{"orn",       0, INSN_CLASS_B_OR_ZBB,   "d,s,t",  MATCH_ORN, MASK_ORN, match_opcode, 0 },
++{"xnor",      0, INSN_CLASS_B_OR_ZBB,   "d,s,t",  MATCH_XNOR, MASK_XNOR, match_opcode, 0 },
++{"roli",      0, INSN_CLASS_B_OR_ZBB,   "d,s,>",  0, (int) M_RL, match_never, INSN_MACRO },	/* rori  */
++{"rol",       0, INSN_CLASS_B_OR_ZBB,   "d,s,t",  MATCH_ROL, MASK_ROL, match_opcode, 0 },
++{"rol",       0, INSN_CLASS_B_OR_ZBB,   "d,s,>",  0, (int) M_RL, match_never, INSN_MACRO },	/* rori  */
++{"rori",      0, INSN_CLASS_B_OR_ZBB,   "d,s,>",  MATCH_RORI, MASK_RORI, match_opcode, 0 },
++{"ror",       0, INSN_CLASS_B_OR_ZBB,   "d,s,t",  MATCH_ROR, MASK_ROR, match_opcode, 0 },
++{"ror",       0, INSN_CLASS_B_OR_ZBB,   "d,s,>",  MATCH_RORI, MASK_RORI, match_opcode, INSN_ALIAS },
+ {"sext.b",    0, INSN_CLASS_B_OR_ZBB,   "d,s",  MATCH_SEXT_B, MASK_SEXT_B, match_opcode, 0 },
+ {"sext.h",    0, INSN_CLASS_B_OR_ZBB,   "d,s",  MATCH_SEXT_H, MASK_SEXT_H, match_opcode, 0 },
+-{"bmatflip", 64, INSN_CLASS_B_OR_ZBM,   "d,s",  MATCH_BMATFLIP, MASK_BMATFLIP, match_opcode, 0 },
+-{"crc32.b",   0, INSN_CLASS_B_OR_ZBR,   "d,s",  MATCH_CRC32_B, MASK_CRC32_B, match_opcode, 0 },
+-{"crc32.h",   0, INSN_CLASS_B_OR_ZBR,   "d,s",  MATCH_CRC32_H, MASK_CRC32_H, match_opcode, 0 },
+-{"crc32.w",   0, INSN_CLASS_B_OR_ZBR,   "d,s",  MATCH_CRC32_W, MASK_CRC32_W, match_opcode, 0 },
+-{"crc32.d",  64, INSN_CLASS_B_OR_ZBR,   "d,s",  MATCH_CRC32_D, MASK_CRC32_D, match_opcode, 0 },
+-{"crc32c.b",  0, INSN_CLASS_B_OR_ZBR,   "d,s",  MATCH_CRC32C_B, MASK_CRC32C_B, match_opcode, 0 },
+-{"crc32c.h",  0, INSN_CLASS_B_OR_ZBR,   "d,s",  MATCH_CRC32C_H, MASK_CRC32C_H, match_opcode, 0 },
+-{"crc32c.w",  0, INSN_CLASS_B_OR_ZBR,   "d,s",  MATCH_CRC32C_W, MASK_CRC32C_W, match_opcode, 0 },
+-{"crc32c.d", 64, INSN_CLASS_B_OR_ZBR,   "d,s",  MATCH_CRC32C_D, MASK_CRC32C_D, match_opcode, 0 },
+-{"sh1add",    0, INSN_CLASS_B_OR_ZBA,   "d,s,t",  MATCH_SH1ADD, MASK_SH1ADD, match_opcode, 0 },
+-{"sh2add",    0, INSN_CLASS_B_OR_ZBA,   "d,s,t",  MATCH_SH2ADD, MASK_SH2ADD, match_opcode, 0 },
+-{"sh3add",    0, INSN_CLASS_B_OR_ZBA,   "d,s,t",  MATCH_SH3ADD, MASK_SH3ADD, match_opcode, 0 },
++{"zext.h",   32, INSN_CLASS_B_OR_ZBB,   "d,s",  MATCH_PACK, MASK_PACK | MASK_RS2, match_opcode, INSN_ALIAS },	/* pack with rs2=x0  */
++{"zext.h",   64, INSN_CLASS_B_OR_ZBB,   "d,s",  MATCH_PACKW, MASK_PACKW | MASK_RS2, match_opcode, INSN_ALIAS },	/* packw with rs2=x0  */
++{"clzw",     64, INSN_CLASS_B_OR_ZBB,   "d,s",  MATCH_CLZW, MASK_CLZW, match_opcode, 0 },
++{"ctzw",     64, INSN_CLASS_B_OR_ZBB,   "d,s",  MATCH_CTZW, MASK_CTZW, match_opcode, 0 },
++{"pcntw",    64, INSN_CLASS_B_OR_ZBB,   "d,s",  MATCH_PCNTW, MASK_PCNTW, match_opcode, 0 },
++{"roliw",    64, INSN_CLASS_B_OR_ZBB,   "d,s,<",  0, (int) M_RL, match_never, INSN_MACRO },	/* roriw  */
++{"rolw",     64, INSN_CLASS_B_OR_ZBB,   "d,s,t",  MATCH_ROLW, MASK_ROLW, match_opcode, 0 },
++{"rolw",     64, INSN_CLASS_B_OR_ZBB,   "d,s,<",  0, (int) M_RL, match_never, INSN_MACRO },	/* roriw  */
++{"roriw",    64, INSN_CLASS_B_OR_ZBB,   "d,s,<",  MATCH_RORIW, MASK_RORIW, match_opcode, 0 },
++{"rorw",     64, INSN_CLASS_B_OR_ZBB,   "d,s,t",  MATCH_RORW, MASK_RORW, match_opcode, 0 },
++{"rorw",     64, INSN_CLASS_B_OR_ZBB,   "d,s,<",  MATCH_RORIW, MASK_RORIW, match_opcode, INSN_ALIAS },
++{"rev8",      0, INSN_CLASS_B_OR_ZBB,   "d,s",  0, (int) M_PERM, match_never, INSN_MACRO },
++{"orc.b",     0, INSN_CLASS_B_OR_ZBB,   "d,s",  0, (int) M_PERM, match_never, INSN_MACRO },
++
+ {"clmul",     0, INSN_CLASS_B_OR_ZBC,   "d,s,t",  MATCH_CLMUL, MASK_CLMUL, match_opcode, 0 },
+ {"clmulh",    0, INSN_CLASS_B_OR_ZBC,   "d,s,t",  MATCH_CLMULH, MASK_CLMULH, match_opcode, 0 },
+ {"clmulr",    0, INSN_CLASS_B_OR_ZBC,   "d,s,t",  MATCH_CLMULR, MASK_CLMULR, match_opcode, 0 },
+-{"min",       0, INSN_CLASS_B_OR_ZBB,   "d,s,t",  MATCH_MIN, MASK_MIN, match_opcode, 0 },
+-{"max",       0, INSN_CLASS_B_OR_ZBB,   "d,s,t",  MATCH_MAX, MASK_MAX, match_opcode, 0 },
+-{"minu",      0, INSN_CLASS_B_OR_ZBB,   "d,s,t",  MATCH_MINU, MASK_MINU, match_opcode, 0 },
+-{"maxu",      0, INSN_CLASS_B_OR_ZBB,   "d,s,t",  MATCH_MAXU, MASK_MAXU, match_opcode, 0 },
+-{"shfli",     0, INSN_CLASS_B_OR_ZBP,   "d,s,|",  MATCH_SHFLI, MASK_SHFLI, match_opcode, 0 },
+-{"unshfli",   0, INSN_CLASS_B_OR_ZBP,   "d,s,|",  MATCH_UNSHFLI, MASK_UNSHFLI, match_opcode, 0 },
+-{"shfl",      0, INSN_CLASS_B_OR_ZBP,   "d,s,t",  MATCH_SHFL, MASK_SHFL, match_opcode, 0 },
+-{"shfl",      0, INSN_CLASS_B_OR_ZBP,   "d,s,|",  MATCH_SHFLI, MASK_SHFLI, match_opcode, INSN_ALIAS },
+-{"unshfl",    0, INSN_CLASS_B_OR_ZBP,   "d,s,t",  MATCH_UNSHFL, MASK_UNSHFL, match_opcode, 0 },
+-{"unshfl",    0, INSN_CLASS_B_OR_ZBP,   "d,s,|",  MATCH_UNSHFLI, MASK_UNSHFLI, match_opcode, INSN_ALIAS },
+-{"xperm.n",   0, INSN_CLASS_B_OR_ZBP,   "d,s,t",  MATCH_XPERMN, MASK_XPERMN, match_opcode, 0 },
+-{"xperm.b",   0, INSN_CLASS_B_OR_ZBP,   "d,s,t",  MATCH_XPERMB, MASK_XPERMB, match_opcode, 0 },
+-{"xperm.h",   0, INSN_CLASS_B_OR_ZBP,   "d,s,t",  MATCH_XPERMH, MASK_XPERMH, match_opcode, 0 },
+-{"bdep",      0, INSN_CLASS_B_OR_ZBE,   "d,s,t",  MATCH_BDEP, MASK_BDEP, match_opcode, 0 },
+-{"bext",      0, INSN_CLASS_B_OR_ZBE,   "d,s,t",  MATCH_BEXT, MASK_BEXT, match_opcode, 0 },
+-{"zext.h",   32, INSN_CLASS_B_OR_ZBB_OR_ZBP,   "d,s",  MATCH_PACK, MASK_PACK | MASK_RS2, match_opcode, INSN_ALIAS },
+-{"zext.h",   64, INSN_CLASS_B_OR_ZBB_OR_ZBP,   "d,s",  MATCH_PACKW, MASK_PACKW | MASK_RS2, match_opcode, INSN_ALIAS },
+-{"pack",      0, INSN_CLASS_B_OR_ZBB_OR_ZBP,   "d,s,t",  MATCH_PACK, MASK_PACK, match_opcode, 0 },
+-{"packu",     0, INSN_CLASS_B_OR_ZBB_OR_ZBP,   "d,s,t",  MATCH_PACKU, MASK_PACKU, match_opcode, 0 },
+-{"packh",     0, INSN_CLASS_B_OR_ZBB_OR_ZBP,   "d,s,t",  MATCH_PACKH, MASK_PACKH, match_opcode, 0 },
+-{"bmator",   64, INSN_CLASS_B_OR_ZBM,   "d,s,t",  MATCH_BMATOR, MASK_BMATOR, match_opcode, 0 },
+-{"bmatxor",  64, INSN_CLASS_B_OR_ZBM,   "d,s,t",  MATCH_BMATXOR, MASK_BMATXOR, match_opcode, 0 },
+-{"bfp",       0, INSN_CLASS_B_OR_ZBF,   "d,s,t",  MATCH_BFP, MASK_BFP, match_opcode, 0 },
+-{"slliu.w",  64, INSN_CLASS_B_OR_ZBB,   "d,s,>",  MATCH_SLLIU_W, MASK_SLLIU_W, match_opcode, 0 },
+-{"zext.w",   64, INSN_CLASS_B_OR_ZBB_OR_ZBP,   "d,s",  MATCH_ADDU_W, MASK_ADDU_W | MASK_RS2, match_opcode, INSN_ALIAS },
+-{"addu.w",   64, INSN_CLASS_B_OR_ZBB,   "d,s,t",  MATCH_ADDU_W, MASK_ADDU_W, match_opcode, 0 },
+-{"subu.w",   64, INSN_CLASS_B_OR_ZBB,   "d,s,t",  MATCH_SUBU_W, MASK_SUBU_W, match_opcode, 0 },
+-{"sloiw",    64, INSN_CLASS_B_OR_ZBP,   "d,s,<",  MATCH_SLOIW, MASK_SLOIW, match_opcode, 0 },
+-{"sroiw",    64, INSN_CLASS_B_OR_ZBP,   "d,s,<",  MATCH_SROIW, MASK_SROIW, match_opcode, 0 },
+-{"roliw",    64, INSN_CLASS_B_OR_ZBB_OR_ZBP,   "d,s,<",  0, (int) M_RL, match_never, INSN_MACRO },
+-{"roriw",    64, INSN_CLASS_B_OR_ZBB_OR_ZBP,   "d,s,<",  MATCH_RORIW, MASK_RORIW, match_opcode, 0 },
+-{"slow",     64, INSN_CLASS_B_OR_ZBP,   "d,s,t",  MATCH_SLOW, MASK_SLOW, match_opcode, 0 },
+-{"slow",     64, INSN_CLASS_B_OR_ZBP,   "d,s,<",  MATCH_SLOIW, MASK_SLOIW, match_opcode, INSN_ALIAS },
+-{"srow",     64, INSN_CLASS_B_OR_ZBP,   "d,s,t",  MATCH_SROW, MASK_SROW, match_opcode, 0 },
+-{"srow",     64, INSN_CLASS_B_OR_ZBP,   "d,s,<",  MATCH_SROIW, MASK_SROIW, match_opcode, INSN_ALIAS },
+-{"rolw",     64, INSN_CLASS_B_OR_ZBB_OR_ZBP,   "d,s,t",  MATCH_ROLW, MASK_ROLW, match_opcode, 0 },
+-{"rolw",     64, INSN_CLASS_B_OR_ZBB_OR_ZBP,   "d,s,<",  0, (int) M_RL, match_never, INSN_MACRO },
+-{"rorw",     64, INSN_CLASS_B_OR_ZBB_OR_ZBP,   "d,s,t",  MATCH_RORW, MASK_RORW, match_opcode, 0 },
+-{"rorw",     64, INSN_CLASS_B_OR_ZBB_OR_ZBP,   "d,s,<",  MATCH_RORIW, MASK_RORIW, match_opcode, INSN_ALIAS },
+-{"sbclriw",  64, INSN_CLASS_B_OR_ZBS,   "d,s,<",  MATCH_SBCLRIW, MASK_SBCLRIW, match_opcode, 0 },
++
++{"sbseti",    0, INSN_CLASS_B_OR_ZBS,   "d,s,>",  MATCH_SBSETI, MASK_SBSETI, match_opcode, 0 },
++{"sbset",     0, INSN_CLASS_B_OR_ZBS,   "d,s,t",  MATCH_SBSET, MASK_SBSET, match_opcode, 0 },
++{"sbset",     0, INSN_CLASS_B_OR_ZBS,   "d,s,>",  MATCH_SBSETI, MASK_SBSETI, match_opcode, INSN_ALIAS },
++{"sbclri",    0, INSN_CLASS_B_OR_ZBS,   "d,s,>",  MATCH_SBCLRI, MASK_SBCLRI, match_opcode, 0 },
++{"sbclr",     0, INSN_CLASS_B_OR_ZBS,   "d,s,t",  MATCH_SBCLR, MASK_SBCLR, match_opcode, 0 },
++{"sbclr",     0, INSN_CLASS_B_OR_ZBS,   "d,s,>",  MATCH_SBCLRI, MASK_SBCLRI, match_opcode, INSN_ALIAS },
++{"sbinvi",    0, INSN_CLASS_B_OR_ZBS,   "d,s,>",  MATCH_SBINVI, MASK_SBINVI, match_opcode, 0 },
++{"sbinv",     0, INSN_CLASS_B_OR_ZBS,   "d,s,t",  MATCH_SBINV, MASK_SBINV, match_opcode, 0 },
++{"sbinv",     0, INSN_CLASS_B_OR_ZBS,   "d,s,>",  MATCH_SBINVI, MASK_SBINVI, match_opcode, INSN_ALIAS },
++{"sbexti",    0, INSN_CLASS_B_OR_ZBS,   "d,s,>",  MATCH_SBEXTI, MASK_SBEXTI, match_opcode, 0 },
++{"sbext",     0, INSN_CLASS_B_OR_ZBS,   "d,s,t",  MATCH_SBEXT, MASK_SBEXT, match_opcode, 0 },
++{"sbext",     0, INSN_CLASS_B_OR_ZBS,   "d,s,>",  MATCH_SBEXTI, MASK_SBEXTI, match_opcode, INSN_ALIAS },
+ {"sbsetiw",  64, INSN_CLASS_B_OR_ZBS,   "d,s,<",  MATCH_SBSETIW, MASK_SBSETIW, match_opcode, 0 },
+-{"sbinviw",  64, INSN_CLASS_B_OR_ZBS,   "d,s,<",  MATCH_SBINVIW, MASK_SBINVIW, match_opcode, 0 },
+-{"gorciw",   64, INSN_CLASS_B_OR_ZBP,   "d,s,<",  MATCH_GORCIW, MASK_GORCIW, match_opcode, 0 },
+-{"greviw",   64, INSN_CLASS_B_OR_ZBP,   "d,s,<",  MATCH_GREVIW, MASK_GREVIW, match_opcode, 0 },
+-{"sbclrw",   64, INSN_CLASS_B_OR_ZBS,   "d,s,t",  MATCH_SBCLRW, MASK_SBCLRW, match_opcode, 0 },
+-{"sbclrw",   64, INSN_CLASS_B_OR_ZBS,   "d,s,<",  MATCH_SBCLRIW, MASK_SBCLRIW, match_opcode, INSN_ALIAS },
+ {"sbsetw",   64, INSN_CLASS_B_OR_ZBS,   "d,s,t",  MATCH_SBSETW, MASK_SBSETW, match_opcode, 0 },
+ {"sbsetw",   64, INSN_CLASS_B_OR_ZBS,   "d,s,<",  MATCH_SBSETIW, MASK_SBSETIW, match_opcode, INSN_ALIAS },
++{"sbclriw",  64, INSN_CLASS_B_OR_ZBS,   "d,s,<",  MATCH_SBCLRIW, MASK_SBCLRIW, match_opcode, 0 },
++{"sbclrw",   64, INSN_CLASS_B_OR_ZBS,   "d,s,t",  MATCH_SBCLRW, MASK_SBCLRW, match_opcode, 0 },
++{"sbclrw",   64, INSN_CLASS_B_OR_ZBS,   "d,s,<",  MATCH_SBCLRIW, MASK_SBCLRIW, match_opcode, INSN_ALIAS },
++{"sbinviw",  64, INSN_CLASS_B_OR_ZBS,   "d,s,<",  MATCH_SBINVIW, MASK_SBINVIW, match_opcode, 0 },
+ {"sbinvw",   64, INSN_CLASS_B_OR_ZBS,   "d,s,t",  MATCH_SBINVW, MASK_SBINVW, match_opcode, 0 },
+ {"sbinvw",   64, INSN_CLASS_B_OR_ZBS,   "d,s,<",  MATCH_SBINVIW, MASK_SBINVIW, match_opcode, INSN_ALIAS },
+-{"sbextw",   64, INSN_CLASS_B_OR_ZBS,   "d,s,t",  MATCH_SBEXTW, MASK_SBEXTW, match_opcode, 0 },
+-{"gorcw",    64, INSN_CLASS_B_OR_ZBP,   "d,s,t",  MATCH_GORCW, MASK_GORCW, match_opcode, 0 },
+-{"gorcw",    64, INSN_CLASS_B_OR_ZBP,   "d,s,<",  MATCH_GORCIW, MASK_GORCIW, match_opcode, INSN_ALIAS },
+-{"grevw",    64, INSN_CLASS_B_OR_ZBP,   "d,s,t",  MATCH_GREVW, MASK_GREVW, match_opcode, 0 },
+-{"grevw",    64, INSN_CLASS_B_OR_ZBP,   "d,s,<",  MATCH_GREVIW, MASK_GREVIW, match_opcode, INSN_ALIAS },
+-{"fsliw",    64, INSN_CLASS_B_OR_ZBT,   "d,s,r,<",  0, (int) M_FL, match_never, INSN_MACRO },
+-{"fsriw",    64, INSN_CLASS_B_OR_ZBT,   "d,s,r,<",  MATCH_FSRIW, MASK_FSRIW, match_opcode, 0 },
+-{"fslw",     64, INSN_CLASS_B_OR_ZBT,   "d,s,r,t",  MATCH_FSLW, MASK_FSLW, match_opcode, 0 },
+-{"fslw",     64, INSN_CLASS_B_OR_ZBT,   "d,s,r,<",  0, (int) M_FL, match_never, INSN_MACRO },
+-{"fsrw",     64, INSN_CLASS_B_OR_ZBT,   "d,s,r,t",  MATCH_FSRW, MASK_FSRW, match_opcode, 0 },
+-{"fsrw",     64, INSN_CLASS_B_OR_ZBT,   "d,s,r,<",  MATCH_FSRIW, MASK_FSRIW, match_opcode, INSN_ALIAS },
+-{"clzw",     64, INSN_CLASS_B_OR_ZBB,   "d,s",  MATCH_CLZW, MASK_CLZW, match_opcode, 0 },
+-{"ctzw",     64, INSN_CLASS_B_OR_ZBB,   "d,s",  MATCH_CTZW, MASK_CTZW, match_opcode, 0 },
+-{"pcntw",    64, INSN_CLASS_B_OR_ZBB,   "d,s",  MATCH_PCNTW, MASK_PCNTW, match_opcode, 0 },
+-{"sh1addu.w",64, INSN_CLASS_B_OR_ZBA,   "d,s,t",  MATCH_SH1ADDU_W, MASK_SH1ADDU_W, match_opcode, 0 },
+-{"sh2addu.w",64, INSN_CLASS_B_OR_ZBA,   "d,s,t",  MATCH_SH2ADDU_W, MASK_SH2ADDU_W, match_opcode, 0 },
+-{"sh3addu.w",64, INSN_CLASS_B_OR_ZBA,   "d,s,t",  MATCH_SH3ADDU_W, MASK_SH3ADDU_W, match_opcode, 0 },
+-{"shflw",    64, INSN_CLASS_B_OR_ZBP,   "d,s,t",  MATCH_SHFLW, MASK_SHFLW, match_opcode, 0 },
+-{"unshflw",  64, INSN_CLASS_B_OR_ZBP,   "d,s,t",  MATCH_UNSHFLW, MASK_UNSHFLW, match_opcode, 0 },
+-{"xperm.w",  64, INSN_CLASS_B_OR_ZBP,   "d,s,t",  MATCH_XPERMW, MASK_XPERMW, match_opcode, 0 },
+-{"bdepw",    64, INSN_CLASS_B_OR_ZBE,   "d,s,t",  MATCH_BDEPW, MASK_BDEPW, match_opcode, 0 },
+-{"bextw",    64, INSN_CLASS_B_OR_ZBE,   "d,s,t",  MATCH_BEXTW, MASK_BEXTW, match_opcode, 0 },
+-{"packw",    64, INSN_CLASS_B_OR_ZBB_OR_ZBP,   "d,s,t",  MATCH_PACKW, MASK_PACKW, match_opcode, 0 },
+-{"packuw",   64, INSN_CLASS_B_OR_ZBB_OR_ZBP,   "d,s,t",  MATCH_PACKUW, MASK_PACKUW, match_opcode, 0 },
+-{"bfpw",     64, INSN_CLASS_B_OR_ZBF,   "d,s,t",  MATCH_BFPW, MASK_BFPW, match_opcode, 0 },
+-
+-/* Bitmanip pseudo-instructions */
+-{"rev.p",     0, INSN_CLASS_B_OR_ZBB_OR_ZBP,   "d,s",  0, (int) M_PERM, match_never, INSN_MACRO },
+-{"rev2.n",    0, INSN_CLASS_B_OR_ZBB_OR_ZBP,   "d,s",  0, (int) M_PERM, match_never, INSN_MACRO },
+-{"rev.n",     0, INSN_CLASS_B_OR_ZBB_OR_ZBP,   "d,s",  0, (int) M_PERM, match_never, INSN_MACRO },
+-{"rev4.b",    0, INSN_CLASS_B_OR_ZBB_OR_ZBP,   "d,s",  0, (int) M_PERM, match_never, INSN_MACRO },
+-{"rev2.b",    0, INSN_CLASS_B_OR_ZBB_OR_ZBP,   "d,s",  0, (int) M_PERM, match_never, INSN_MACRO },
+-{"rev.b",     0, INSN_CLASS_B_OR_ZBB_OR_ZBP,   "d,s",  0, (int) M_PERM, match_never, INSN_MACRO },
+-{"rev8.h",    0, INSN_CLASS_B_OR_ZBB_OR_ZBP,   "d,s",  0, (int) M_PERM, match_never, INSN_MACRO },
+-{"rev4.h",    0, INSN_CLASS_B_OR_ZBB_OR_ZBP,   "d,s",  0, (int) M_PERM, match_never, INSN_MACRO },
+-{"rev2.h",    0, INSN_CLASS_B_OR_ZBB_OR_ZBP,   "d,s",  0, (int) M_PERM, match_never, INSN_MACRO },
+-{"rev.h",     0, INSN_CLASS_B_OR_ZBB_OR_ZBP,   "d,s",  0, (int) M_PERM, match_never, INSN_MACRO },
+-{"rev16.w",  64, INSN_CLASS_B_OR_ZBB_OR_ZBP,   "d,s",  0, (int) M_PERM, match_never, INSN_MACRO },
+-{"rev8.w",   64, INSN_CLASS_B_OR_ZBB_OR_ZBP,   "d,s",  0, (int) M_PERM, match_never, INSN_MACRO },
+-{"rev4.w",   64, INSN_CLASS_B_OR_ZBB_OR_ZBP,   "d,s",  0, (int) M_PERM, match_never, INSN_MACRO },
+-{"rev2.w",   64, INSN_CLASS_B_OR_ZBB_OR_ZBP,   "d,s",  0, (int) M_PERM, match_never, INSN_MACRO },
+-{"rev.w",    64, INSN_CLASS_B_OR_ZBB_OR_ZBP,   "d,s",  0, (int) M_PERM, match_never, INSN_MACRO },
+-{"rev32",    64, INSN_CLASS_B_OR_ZBB_OR_ZBP,   "d,s",  0, (int) M_PERM, match_never, INSN_MACRO },
+-{"rev16",     0, INSN_CLASS_B_OR_ZBB_OR_ZBP,   "d,s",  0, (int) M_PERM, match_never, INSN_MACRO },
+-{"rev8",      0, INSN_CLASS_B_OR_ZBB_OR_ZBP,   "d,s",  0, (int) M_PERM, match_never, INSN_MACRO },
+-{"rev4",      0, INSN_CLASS_B_OR_ZBB_OR_ZBP,   "d,s",  0, (int) M_PERM, match_never, INSN_MACRO },
+-{"rev2",      0, INSN_CLASS_B_OR_ZBB_OR_ZBP,   "d,s",  0, (int) M_PERM, match_never, INSN_MACRO },
+-{"rev",       0, INSN_CLASS_B_OR_ZBB_OR_ZBP,   "d,s",  0, (int) M_PERM, match_never, INSN_MACRO },
+-
+-{"orc.p",     0, INSN_CLASS_B_OR_ZBB_OR_ZBP,   "d,s",  0, (int) M_PERM, match_never, INSN_MACRO },
+-{"orc2.n",    0, INSN_CLASS_B_OR_ZBB_OR_ZBP,   "d,s",  0, (int) M_PERM, match_never, INSN_MACRO },
+-{"orc.n",     0, INSN_CLASS_B_OR_ZBB_OR_ZBP,   "d,s",  0, (int) M_PERM, match_never, INSN_MACRO },
+-{"orc4.b",    0, INSN_CLASS_B_OR_ZBB_OR_ZBP,   "d,s",  0, (int) M_PERM, match_never, INSN_MACRO },
+-{"orc2.b",    0, INSN_CLASS_B_OR_ZBB_OR_ZBP,   "d,s",  0, (int) M_PERM, match_never, INSN_MACRO },
+-{"orc.b",     0, INSN_CLASS_B_OR_ZBB_OR_ZBP,   "d,s",  0, (int) M_PERM, match_never, INSN_MACRO },
+-{"orc8.h",    0, INSN_CLASS_B_OR_ZBB_OR_ZBP,   "d,s",  0, (int) M_PERM, match_never, INSN_MACRO },
+-{"orc4.h",    0, INSN_CLASS_B_OR_ZBB_OR_ZBP,   "d,s",  0, (int) M_PERM, match_never, INSN_MACRO },
+-{"orc2.h",    0, INSN_CLASS_B_OR_ZBB_OR_ZBP,   "d,s",  0, (int) M_PERM, match_never, INSN_MACRO },
+-{"orc.h",     0, INSN_CLASS_B_OR_ZBB_OR_ZBP,   "d,s",  0, (int) M_PERM, match_never, INSN_MACRO },
+-{"orc16.w",  64, INSN_CLASS_B_OR_ZBB_OR_ZBP,   "d,s",  0, (int) M_PERM, match_never, INSN_MACRO },
+-{"orc8.w",   64, INSN_CLASS_B_OR_ZBB_OR_ZBP,   "d,s",  0, (int) M_PERM, match_never, INSN_MACRO },
+-{"orc4.w",   64, INSN_CLASS_B_OR_ZBB_OR_ZBP,   "d,s",  0, (int) M_PERM, match_never, INSN_MACRO },
+-{"orc2.w",   64, INSN_CLASS_B_OR_ZBB_OR_ZBP,   "d,s",  0, (int) M_PERM, match_never, INSN_MACRO },
+-{"orc.w",    64, INSN_CLASS_B_OR_ZBB_OR_ZBP,   "d,s",  0, (int) M_PERM, match_never, INSN_MACRO },
+-{"orc32",    64, INSN_CLASS_B_OR_ZBB_OR_ZBP,   "d,s",  0, (int) M_PERM, match_never, INSN_MACRO },
+-{"orc16",     0, INSN_CLASS_B_OR_ZBB_OR_ZBP,   "d,s",  0, (int) M_PERM, match_never, INSN_MACRO },
+-{"orc8",      0, INSN_CLASS_B_OR_ZBB_OR_ZBP,   "d,s",  0, (int) M_PERM, match_never, INSN_MACRO },
+-{"orc4",      0, INSN_CLASS_B_OR_ZBB_OR_ZBP,   "d,s",  0, (int) M_PERM, match_never, INSN_MACRO },
+-{"orc2",      0, INSN_CLASS_B_OR_ZBB_OR_ZBP,   "d,s",  0, (int) M_PERM, match_never, INSN_MACRO },
+-{"orc",       0, INSN_CLASS_B_OR_ZBB_OR_ZBP,   "d,s",  0, (int) M_PERM, match_never, INSN_MACRO },
+-
+-{"zip.n",     0, INSN_CLASS_B_OR_ZBP,   "d,s",  0, (int) M_PERM, match_never, INSN_MACRO },
+-{"zip2.b",    0, INSN_CLASS_B_OR_ZBP,   "d,s",  0, (int) M_PERM, match_never, INSN_MACRO },
+-{"zip.b",     0, INSN_CLASS_B_OR_ZBP,   "d,s",  0, (int) M_PERM, match_never, INSN_MACRO },
+-{"zip4.h",    0, INSN_CLASS_B_OR_ZBP,   "d,s",  0, (int) M_PERM, match_never, INSN_MACRO },
+-{"zip2.h",    0, INSN_CLASS_B_OR_ZBP,   "d,s",  0, (int) M_PERM, match_never, INSN_MACRO },
+-{"zip.h",     0, INSN_CLASS_B_OR_ZBP,   "d,s",  0, (int) M_PERM, match_never, INSN_MACRO },
+-{"zip8.w",   64, INSN_CLASS_B_OR_ZBP,   "d,s",  0, (int) M_PERM, match_never, INSN_MACRO },
+-{"zip4.w",   64, INSN_CLASS_B_OR_ZBP,   "d,s",  0, (int) M_PERM, match_never, INSN_MACRO },
+-{"zip2.w",   64, INSN_CLASS_B_OR_ZBP,   "d,s",  0, (int) M_PERM, match_never, INSN_MACRO },
+-{"zip.w",    64, INSN_CLASS_B_OR_ZBP,   "d,s",  0, (int) M_PERM, match_never, INSN_MACRO },
+-{"zip16",    64, INSN_CLASS_B_OR_ZBP,   "d,s",  0, (int) M_PERM, match_never, INSN_MACRO },
+-{"zip8",      0, INSN_CLASS_B_OR_ZBP,   "d,s",  0, (int) M_PERM, match_never, INSN_MACRO },
+-{"zip4",      0, INSN_CLASS_B_OR_ZBP,   "d,s",  0, (int) M_PERM, match_never, INSN_MACRO },
+-{"zip2",      0, INSN_CLASS_B_OR_ZBP,   "d,s",  0, (int) M_PERM, match_never, INSN_MACRO },
+-{"zip",       0, INSN_CLASS_B_OR_ZBP,   "d,s",  0, (int) M_PERM, match_never, INSN_MACRO },
+-
+-{"unzip.n",   0, INSN_CLASS_B_OR_ZBP,   "d,s",  0, (int) M_PERM, match_never, INSN_MACRO },
+-{"unzip2.b",  0, INSN_CLASS_B_OR_ZBP,   "d,s",  0, (int) M_PERM, match_never, INSN_MACRO },
+-{"unzip.b",   0, INSN_CLASS_B_OR_ZBP,   "d,s",  0, (int) M_PERM, match_never, INSN_MACRO },
+-{"unzip4.h",  0, INSN_CLASS_B_OR_ZBP,   "d,s",  0, (int) M_PERM, match_never, INSN_MACRO },
+-{"unzip2.h",  0, INSN_CLASS_B_OR_ZBP,   "d,s",  0, (int) M_PERM, match_never, INSN_MACRO },
+-{"unzip.h",   0, INSN_CLASS_B_OR_ZBP,   "d,s",  0, (int) M_PERM, match_never, INSN_MACRO },
+-{"unzip8.w", 64, INSN_CLASS_B_OR_ZBP,   "d,s",  0, (int) M_PERM, match_never, INSN_MACRO },
+-{"unzip4.w", 64, INSN_CLASS_B_OR_ZBP,   "d,s",  0, (int) M_PERM, match_never, INSN_MACRO },
+-{"unzip2.w", 64, INSN_CLASS_B_OR_ZBP,   "d,s",  0, (int) M_PERM, match_never, INSN_MACRO },
+-{"unzip.w",  64, INSN_CLASS_B_OR_ZBP,   "d,s",  0, (int) M_PERM, match_never, INSN_MACRO },
+-{"unzip16",  64, INSN_CLASS_B_OR_ZBP,   "d,s",  0, (int) M_PERM, match_never, INSN_MACRO },
+-{"unzip8",    0, INSN_CLASS_B_OR_ZBP,   "d,s",  0, (int) M_PERM, match_never, INSN_MACRO },
+-{"unzip4",    0, INSN_CLASS_B_OR_ZBP,   "d,s",  0, (int) M_PERM, match_never, INSN_MACRO },
+-{"unzip2",    0, INSN_CLASS_B_OR_ZBP,   "d,s",  0, (int) M_PERM, match_never, INSN_MACRO },
+-{"unzip",     0, INSN_CLASS_B_OR_ZBP,   "d,s",  0, (int) M_PERM, match_never, INSN_MACRO },
++{"sbextw",   64, INSN_CLASS_B_OR_ZBS,   "d,s,t",  MATCH_SBEXTW, MASK_SBEXTW, match_opcode, 0 },	/* No sbextiw  */
++
++/* Bitmanip instruction subset - unsure  */
++{"sloi",      0, INSN_CLASS_B,   "d,s,>",  MATCH_SLOI, MASK_SLOI, match_opcode, 0 },
++{"sroi",      0, INSN_CLASS_B,   "d,s,>",  MATCH_SROI, MASK_SROI, match_opcode, 0 },
++{"slo",       0, INSN_CLASS_B,   "d,s,t",  MATCH_SLO, MASK_SLO, match_opcode, 0 },
++{"slo",       0, INSN_CLASS_B,   "d,s,>",  MATCH_SLOI, MASK_SLOI, match_opcode, INSN_ALIAS },
++{"sro",       0, INSN_CLASS_B,   "d,s,t",  MATCH_SRO, MASK_SRO, match_opcode, 0 },
++{"sro",       0, INSN_CLASS_B,   "d,s,>",  MATCH_SROI, MASK_SROI, match_opcode, INSN_ALIAS },
++{"gorci",     0, INSN_CLASS_B,   "d,s,>",  MATCH_GORCI, MASK_GORCI, match_opcode, 0 },
++{"grevi",     0, INSN_CLASS_B,   "d,s,>",  MATCH_GREVI, MASK_GREVI, match_opcode, 0 },
++{"gorc",      0, INSN_CLASS_B,   "d,s,t",  MATCH_GORC, MASK_GORC, match_opcode, 0 },
++{"gorc",      0, INSN_CLASS_B,   "d,s,>",  MATCH_GORCI, MASK_GORCI, match_opcode, INSN_ALIAS },
++{"grev",      0, INSN_CLASS_B,   "d,s,t",  MATCH_GREV, MASK_GREV, match_opcode, 0 },
++{"grev",      0, INSN_CLASS_B,   "d,s,>",  MATCH_GREVI, MASK_GREVI, match_opcode, INSN_ALIAS },
++{"bmatflip", 64, INSN_CLASS_B,   "d,s",  MATCH_BMATFLIP, MASK_BMATFLIP, match_opcode, 0 },
++{"shfli",     0, INSN_CLASS_B,   "d,s,|",  MATCH_SHFLI, MASK_SHFLI, match_opcode, 0 },
++{"unshfli",   0, INSN_CLASS_B,   "d,s,|",  MATCH_UNSHFLI, MASK_UNSHFLI, match_opcode, 0 },
++{"shfl",      0, INSN_CLASS_B,   "d,s,t",  MATCH_SHFL, MASK_SHFL, match_opcode, 0 },
++{"shfl",      0, INSN_CLASS_B,   "d,s,|",  MATCH_SHFLI, MASK_SHFLI, match_opcode, INSN_ALIAS },
++{"unshfl",    0, INSN_CLASS_B,   "d,s,t",  MATCH_UNSHFL, MASK_UNSHFL, match_opcode, 0 },
++{"unshfl",    0, INSN_CLASS_B,   "d,s,|",  MATCH_UNSHFLI, MASK_UNSHFLI, match_opcode, INSN_ALIAS },
++{"xperm.n",   0, INSN_CLASS_B,   "d,s,t",  MATCH_XPERMN, MASK_XPERMN, match_opcode, 0 },
++{"xperm.b",   0, INSN_CLASS_B,   "d,s,t",  MATCH_XPERMB, MASK_XPERMB, match_opcode, 0 },
++{"xperm.h",   0, INSN_CLASS_B,   "d,s,t",  MATCH_XPERMH, MASK_XPERMH, match_opcode, 0 },
++{"bdep",      0, INSN_CLASS_B,   "d,s,t",  MATCH_BDEP, MASK_BDEP, match_opcode, 0 },
++{"bext",      0, INSN_CLASS_B,   "d,s,t",  MATCH_BEXT, MASK_BEXT, match_opcode, 0 },
++{"pack",      0, INSN_CLASS_B,   "d,s,t",  MATCH_PACK, MASK_PACK, match_opcode, 0 },
++{"packu",     0, INSN_CLASS_B,   "d,s,t",  MATCH_PACKU, MASK_PACKU, match_opcode, 0 },
++{"packh",     0, INSN_CLASS_B,   "d,s,t",  MATCH_PACKH, MASK_PACKH, match_opcode, 0 },
++{"bmator",   64, INSN_CLASS_B,   "d,s,t",  MATCH_BMATOR, MASK_BMATOR, match_opcode, 0 },
++{"bmatxor",  64, INSN_CLASS_B,   "d,s,t",  MATCH_BMATXOR, MASK_BMATXOR, match_opcode, 0 },
++{"bfp",       0, INSN_CLASS_B,   "d,s,t",  MATCH_BFP, MASK_BFP, match_opcode, 0 },
++{"subu.w",   64, INSN_CLASS_B,   "d,s,t",  MATCH_SUBU_W, MASK_SUBU_W, match_opcode, 0 },
++{"sloiw",    64, INSN_CLASS_B,   "d,s,<",  MATCH_SLOIW, MASK_SLOIW, match_opcode, 0 },
++{"sroiw",    64, INSN_CLASS_B,   "d,s,<",  MATCH_SROIW, MASK_SROIW, match_opcode, 0 },
++{"slow",     64, INSN_CLASS_B,   "d,s,t",  MATCH_SLOW, MASK_SLOW, match_opcode, 0 },
++{"slow",     64, INSN_CLASS_B,   "d,s,<",  MATCH_SLOIW, MASK_SLOIW, match_opcode, INSN_ALIAS },
++{"srow",     64, INSN_CLASS_B,   "d,s,t",  MATCH_SROW, MASK_SROW, match_opcode, 0 },
++{"srow",     64, INSN_CLASS_B,   "d,s,<",  MATCH_SROIW, MASK_SROIW, match_opcode, INSN_ALIAS },
++{"gorciw",   64, INSN_CLASS_B,   "d,s,<",  MATCH_GORCIW, MASK_GORCIW, match_opcode, 0 },
++{"greviw",   64, INSN_CLASS_B,   "d,s,<",  MATCH_GREVIW, MASK_GREVIW, match_opcode, 0 },
++{"gorcw",    64, INSN_CLASS_B,   "d,s,t",  MATCH_GORCW, MASK_GORCW, match_opcode, 0 },
++{"gorcw",    64, INSN_CLASS_B,   "d,s,<",  MATCH_GORCIW, MASK_GORCIW, match_opcode, INSN_ALIAS },
++{"grevw",    64, INSN_CLASS_B,   "d,s,t",  MATCH_GREVW, MASK_GREVW, match_opcode, 0 },
++{"grevw",    64, INSN_CLASS_B,   "d,s,<",  MATCH_GREVIW, MASK_GREVIW, match_opcode, INSN_ALIAS },
++{"shflw",    64, INSN_CLASS_B,   "d,s,t",  MATCH_SHFLW, MASK_SHFLW, match_opcode, 0 },
++{"unshflw",  64, INSN_CLASS_B,   "d,s,t",  MATCH_UNSHFLW, MASK_UNSHFLW, match_opcode, 0 },
++{"xperm.w",  64, INSN_CLASS_B,   "d,s,t",  MATCH_XPERMW, MASK_XPERMW, match_opcode, 0 },
++{"bdepw",    64, INSN_CLASS_B,   "d,s,t",  MATCH_BDEPW, MASK_BDEPW, match_opcode, 0 },
++{"bextw",    64, INSN_CLASS_B,   "d,s,t",  MATCH_BEXTW, MASK_BEXTW, match_opcode, 0 },
++{"packw",    64, INSN_CLASS_B,   "d,s,t",  MATCH_PACKW, MASK_PACKW, match_opcode, 0 },
++{"packuw",   64, INSN_CLASS_B,   "d,s,t",  MATCH_PACKUW, MASK_PACKUW, match_opcode, 0 },
++{"bfpw",     64, INSN_CLASS_B,   "d,s,t",  MATCH_BFPW, MASK_BFPW, match_opcode, 0 },
++
++{"cmix",      0, INSN_CLASS_ZBT,   "d,t,s,r",  MATCH_CMIX, MASK_CMIX, match_opcode, 0 },
++{"cmov",      0, INSN_CLASS_ZBT,   "d,t,s,r",  MATCH_CMOV, MASK_CMOV, match_opcode, 0 },
++{"fsli",      0, INSN_CLASS_ZBT,   "d,s,r,>",  0, (int) M_FL, match_never, INSN_MACRO },	/* fsri  */
++{"fsl",       0, INSN_CLASS_ZBT,   "d,s,r,t",  MATCH_FSL, MASK_FSL, match_opcode, 0 },
++{"fsl",       0, INSN_CLASS_ZBT,   "d,s,r,>",  0, (int) M_FL, match_never, INSN_MACRO },	/* fsri  */
++{"fsri",      0, INSN_CLASS_ZBT,   "d,s,r,>",  MATCH_FSRI, MASK_FSRI, match_opcode, 0 },
++{"fsr",       0, INSN_CLASS_ZBT,   "d,s,r,t",  MATCH_FSR, MASK_FSR, match_opcode, 0 },
++{"fsr",       0, INSN_CLASS_ZBT,   "d,s,r,>",  MATCH_FSRI, MASK_FSRI, match_opcode, INSN_ALIAS },
++{"fsliw",    64, INSN_CLASS_ZBT,   "d,s,r,<",  0, (int) M_FL, match_never, INSN_MACRO },	/* fsriw  */
++{"fslw",     64, INSN_CLASS_ZBT,   "d,s,r,t",  MATCH_FSLW, MASK_FSLW, match_opcode, 0 },
++{"fslw",     64, INSN_CLASS_ZBT,   "d,s,r,<",  0, (int) M_FL, match_never, INSN_MACRO },	/* fsriw  */
++{"fsriw",    64, INSN_CLASS_ZBT,   "d,s,r,<",  MATCH_FSRIW, MASK_FSRIW, match_opcode, 0 },
++{"fsrw",     64, INSN_CLASS_ZBT,   "d,s,r,t",  MATCH_FSRW, MASK_FSRW, match_opcode, 0 },
++{"fsrw",     64, INSN_CLASS_ZBT,   "d,s,r,<",  MATCH_FSRIW, MASK_FSRIW, match_opcode, INSN_ALIAS },
++
++{"crc32.b",   0, INSN_CLASS_ZBR,   "d,s",  MATCH_CRC32_B, MASK_CRC32_B, match_opcode, 0 },
++{"crc32.h",   0, INSN_CLASS_ZBR,   "d,s",  MATCH_CRC32_H, MASK_CRC32_H, match_opcode, 0 },
++{"crc32.w",   0, INSN_CLASS_ZBR,   "d,s",  MATCH_CRC32_W, MASK_CRC32_W, match_opcode, 0 },
++{"crc32c.b",  0, INSN_CLASS_ZBR,   "d,s",  MATCH_CRC32C_B, MASK_CRC32C_B, match_opcode, 0 },
++{"crc32c.h",  0, INSN_CLASS_ZBR,   "d,s",  MATCH_CRC32C_H, MASK_CRC32C_H, match_opcode, 0 },
++{"crc32c.w",  0, INSN_CLASS_ZBR,   "d,s",  MATCH_CRC32C_W, MASK_CRC32C_W, match_opcode, 0 },
++{"crc32.d",  64, INSN_CLASS_ZBR,   "d,s",  MATCH_CRC32_D, MASK_CRC32_D, match_opcode, 0 },
++{"crc32c.d", 64, INSN_CLASS_ZBR,   "d,s",  MATCH_CRC32C_D, MASK_CRC32C_D, match_opcode, 0 },
++
++/* Bitmanip pseudo-instructions  */
++{"rev.p",     0, INSN_CLASS_B,   "d,s",  0, (int) M_PERM, match_never, INSN_MACRO },
++{"rev2.n",    0, INSN_CLASS_B,   "d,s",  0, (int) M_PERM, match_never, INSN_MACRO },
++{"rev.n",     0, INSN_CLASS_B,   "d,s",  0, (int) M_PERM, match_never, INSN_MACRO },
++{"rev4.b",    0, INSN_CLASS_B,   "d,s",  0, (int) M_PERM, match_never, INSN_MACRO },
++{"rev2.b",    0, INSN_CLASS_B,   "d,s",  0, (int) M_PERM, match_never, INSN_MACRO },
++{"rev.b",     0, INSN_CLASS_B,   "d,s",  0, (int) M_PERM, match_never, INSN_MACRO },
++{"rev8.h",    0, INSN_CLASS_B,   "d,s",  0, (int) M_PERM, match_never, INSN_MACRO },
++{"rev4.h",    0, INSN_CLASS_B,   "d,s",  0, (int) M_PERM, match_never, INSN_MACRO },
++{"rev2.h",    0, INSN_CLASS_B,   "d,s",  0, (int) M_PERM, match_never, INSN_MACRO },
++{"rev.h",     0, INSN_CLASS_B,   "d,s",  0, (int) M_PERM, match_never, INSN_MACRO },
++{"rev16.w",  64, INSN_CLASS_B,   "d,s",  0, (int) M_PERM, match_never, INSN_MACRO },
++{"rev8.w",   64, INSN_CLASS_B,   "d,s",  0, (int) M_PERM, match_never, INSN_MACRO },
++{"rev4.w",   64, INSN_CLASS_B,   "d,s",  0, (int) M_PERM, match_never, INSN_MACRO },
++{"rev2.w",   64, INSN_CLASS_B,   "d,s",  0, (int) M_PERM, match_never, INSN_MACRO },
++{"rev.w",    64, INSN_CLASS_B,   "d,s",  0, (int) M_PERM, match_never, INSN_MACRO },
++{"rev32",    64, INSN_CLASS_B,   "d,s",  0, (int) M_PERM, match_never, INSN_MACRO },
++{"rev16",     0, INSN_CLASS_B,   "d,s",  0, (int) M_PERM, match_never, INSN_MACRO },
++{"rev4",      0, INSN_CLASS_B,   "d,s",  0, (int) M_PERM, match_never, INSN_MACRO },
++{"rev2",      0, INSN_CLASS_B,   "d,s",  0, (int) M_PERM, match_never, INSN_MACRO },
++{"rev",       0, INSN_CLASS_B,   "d,s",  0, (int) M_PERM, match_never, INSN_MACRO },
++
++{"orc.p",     0, INSN_CLASS_B,   "d,s",  0, (int) M_PERM, match_never, INSN_MACRO },
++{"orc2.n",    0, INSN_CLASS_B,   "d,s",  0, (int) M_PERM, match_never, INSN_MACRO },
++{"orc.n",     0, INSN_CLASS_B,   "d,s",  0, (int) M_PERM, match_never, INSN_MACRO },
++{"orc4.b",    0, INSN_CLASS_B,   "d,s",  0, (int) M_PERM, match_never, INSN_MACRO },
++{"orc2.b",    0, INSN_CLASS_B,   "d,s",  0, (int) M_PERM, match_never, INSN_MACRO },
++{"orc8.h",    0, INSN_CLASS_B,   "d,s",  0, (int) M_PERM, match_never, INSN_MACRO },
++{"orc4.h",    0, INSN_CLASS_B,   "d,s",  0, (int) M_PERM, match_never, INSN_MACRO },
++{"orc2.h",    0, INSN_CLASS_B,   "d,s",  0, (int) M_PERM, match_never, INSN_MACRO },
++{"orc.h",     0, INSN_CLASS_B,   "d,s",  0, (int) M_PERM, match_never, INSN_MACRO },
++{"orc16.w",  64, INSN_CLASS_B,   "d,s",  0, (int) M_PERM, match_never, INSN_MACRO },
++{"orc8.w",   64, INSN_CLASS_B,   "d,s",  0, (int) M_PERM, match_never, INSN_MACRO },
++{"orc4.w",   64, INSN_CLASS_B,   "d,s",  0, (int) M_PERM, match_never, INSN_MACRO },
++{"orc2.w",   64, INSN_CLASS_B,   "d,s",  0, (int) M_PERM, match_never, INSN_MACRO },
++{"orc.w",    64, INSN_CLASS_B,   "d,s",  0, (int) M_PERM, match_never, INSN_MACRO },
++{"orc32",    64, INSN_CLASS_B,   "d,s",  0, (int) M_PERM, match_never, INSN_MACRO },
++{"orc16",     0, INSN_CLASS_B,   "d,s",  0, (int) M_PERM, match_never, INSN_MACRO },
++{"orc8",      0, INSN_CLASS_B,   "d,s",  0, (int) M_PERM, match_never, INSN_MACRO },
++{"orc4",      0, INSN_CLASS_B,   "d,s",  0, (int) M_PERM, match_never, INSN_MACRO },
++{"orc2",      0, INSN_CLASS_B,   "d,s",  0, (int) M_PERM, match_never, INSN_MACRO },
++{"orc",       0, INSN_CLASS_B,   "d,s",  0, (int) M_PERM, match_never, INSN_MACRO },
++
++{"zip.n",     0, INSN_CLASS_B,   "d,s",  0, (int) M_PERM, match_never, INSN_MACRO },
++{"zip2.b",    0, INSN_CLASS_B,   "d,s",  0, (int) M_PERM, match_never, INSN_MACRO },
++{"zip.b",     0, INSN_CLASS_B,   "d,s",  0, (int) M_PERM, match_never, INSN_MACRO },
++{"zip4.h",    0, INSN_CLASS_B,   "d,s",  0, (int) M_PERM, match_never, INSN_MACRO },
++{"zip2.h",    0, INSN_CLASS_B,   "d,s",  0, (int) M_PERM, match_never, INSN_MACRO },
++{"zip.h",     0, INSN_CLASS_B,   "d,s",  0, (int) M_PERM, match_never, INSN_MACRO },
++{"zip8.w",   64, INSN_CLASS_B,   "d,s",  0, (int) M_PERM, match_never, INSN_MACRO },
++{"zip4.w",   64, INSN_CLASS_B,   "d,s",  0, (int) M_PERM, match_never, INSN_MACRO },
++{"zip2.w",   64, INSN_CLASS_B,   "d,s",  0, (int) M_PERM, match_never, INSN_MACRO },
++{"zip.w",    64, INSN_CLASS_B,   "d,s",  0, (int) M_PERM, match_never, INSN_MACRO },
++{"zip16",    64, INSN_CLASS_B,   "d,s",  0, (int) M_PERM, match_never, INSN_MACRO },
++{"zip8",      0, INSN_CLASS_B,   "d,s",  0, (int) M_PERM, match_never, INSN_MACRO },
++{"zip4",      0, INSN_CLASS_B,   "d,s",  0, (int) M_PERM, match_never, INSN_MACRO },
++{"zip2",      0, INSN_CLASS_B,   "d,s",  0, (int) M_PERM, match_never, INSN_MACRO },
++{"zip",       0, INSN_CLASS_B,   "d,s",  0, (int) M_PERM, match_never, INSN_MACRO },
++
++{"unzip.n",   0, INSN_CLASS_B,   "d,s",  0, (int) M_PERM, match_never, INSN_MACRO },
++{"unzip2.b",  0, INSN_CLASS_B,   "d,s",  0, (int) M_PERM, match_never, INSN_MACRO },
++{"unzip.b",   0, INSN_CLASS_B,   "d,s",  0, (int) M_PERM, match_never, INSN_MACRO },
++{"unzip4.h",  0, INSN_CLASS_B,   "d,s",  0, (int) M_PERM, match_never, INSN_MACRO },
++{"unzip2.h",  0, INSN_CLASS_B,   "d,s",  0, (int) M_PERM, match_never, INSN_MACRO },
++{"unzip.h",   0, INSN_CLASS_B,   "d,s",  0, (int) M_PERM, match_never, INSN_MACRO },
++{"unzip8.w", 64, INSN_CLASS_B,   "d,s",  0, (int) M_PERM, match_never, INSN_MACRO },
++{"unzip4.w", 64, INSN_CLASS_B,   "d,s",  0, (int) M_PERM, match_never, INSN_MACRO },
++{"unzip2.w", 64, INSN_CLASS_B,   "d,s",  0, (int) M_PERM, match_never, INSN_MACRO },
++{"unzip.w",  64, INSN_CLASS_B,   "d,s",  0, (int) M_PERM, match_never, INSN_MACRO },
++{"unzip16",  64, INSN_CLASS_B,   "d,s",  0, (int) M_PERM, match_never, INSN_MACRO },
++{"unzip8",    0, INSN_CLASS_B,   "d,s",  0, (int) M_PERM, match_never, INSN_MACRO },
++{"unzip4",    0, INSN_CLASS_B,   "d,s",  0, (int) M_PERM, match_never, INSN_MACRO },
++{"unzip2",    0, INSN_CLASS_B,   "d,s",  0, (int) M_PERM, match_never, INSN_MACRO },
++{"unzip",     0, INSN_CLASS_B,   "d,s",  0, (int) M_PERM, match_never, INSN_MACRO },
+ 
+ /* Single-precision floating-point instruction subset */
+ {"frcsr",     0, INSN_CLASS_F,   "d",  MATCH_FRCSR, MASK_FRCSR, match_opcode, INSN_ALIAS },
+-- 
+2.33.0
+

+ 792 - 0
recipes-devtools/gdb/files/0042-RISC-V-Define-pseudo-rev-orc-zip-unzip-as-alias-inst.patch

@@ -0,0 +1,792 @@
+From 61090f05eb983ce302df091fb118103daa6dbb4e Mon Sep 17 00:00:00 2001
+From: Nelson Chu <nelson.chu@sifive.com>
+Date: Fri, 11 Dec 2020 12:42:36 +0800
+Subject: [PATCH 42/48] RISC-V: Define pseudo rev/orc/zip/unzip as alias
+ instructions.
+
+Generally, we usually use INSN_MACRO to expand a pseudo into multiple
+instructions; But if the pseudos are one to one mapping, then they are
+more like alias instructions, and can use INSN_ALIAS to handle them.
+One of the benefits of INSN_ALIAS is that - we can dump the their pseudo
+names directly, and it is more friendly to users.
+---
+ gas/config/tc-riscv.c                         |  56 ----
+ .../gas/riscv/bitmanip-insns-pseudo-32.d      |  60 +++++
+ .../gas/riscv/bitmanip-insns-pseudo-64.d      |  82 ++++++
+ .../riscv/bitmanip-insns-pseudo-noalias-32.d  |  60 +++++
+ .../riscv/bitmanip-insns-pseudo-noalias-64.d  |  82 ++++++
+ .../gas/riscv/bitmanip-insns-pseudo.s         |  81 ++++++
+ include/opcode/riscv.h                        |   1 -
+ opcodes/riscv-opc.c                           | 249 ++++++++++++------
+ 8 files changed, 537 insertions(+), 134 deletions(-)
+ create mode 100644 gas/testsuite/gas/riscv/bitmanip-insns-pseudo-32.d
+ create mode 100644 gas/testsuite/gas/riscv/bitmanip-insns-pseudo-64.d
+ create mode 100644 gas/testsuite/gas/riscv/bitmanip-insns-pseudo-noalias-32.d
+ create mode 100644 gas/testsuite/gas/riscv/bitmanip-insns-pseudo-noalias-64.d
+ create mode 100644 gas/testsuite/gas/riscv/bitmanip-insns-pseudo.s
+
+diff --git a/gas/config/tc-riscv.c b/gas/config/tc-riscv.c
+index b1b86a7afb..2a5ac9c861 100644
+--- a/gas/config/tc-riscv.c
++++ b/gas/config/tc-riscv.c
+@@ -1533,58 +1533,6 @@ funnel_left (int rd, int rs1, int rs3, unsigned shamt, unsigned this_xlen)
+     as_fatal (_("internal error: bad left shift xlen %d"), this_xlen);
+ }
+ 
+-static void
+-perm (int rd, int rs1, const char *op)
+-{
+-  const char *insn = NULL;
+-  const char *p = op;
+-  int shamt = 0;
+-  int shfl = 0;
+-
+-  switch (p[0])
+-    {
+-    case 'r': insn = "grevi";   shamt = xlen-1;   p += 3; break;
+-    case 'o': insn = "gorci";   shamt = xlen-1;   p += 3; break;
+-    case 'z': insn = "shfli";   shamt = xlen/2-1; p += 3; shfl = 1; break;
+-    case 'u': insn = "unshfli"; shamt = xlen/2-1; p += 5; shfl = 1; break;
+-    default: as_fatal (_("internal error: bad permutation pseudo-instruction %s"), op);
+-    }
+-
+-  switch (p[0])
+-    {
+-    case '2': shamt &= shamt << 1; p += 1; break;
+-    case '4': shamt &= shamt << 2; p += 1; break;
+-    case '8': shamt &= shamt << 3; p += 1; break;
+-    case '1': shamt &= shamt << 4; p += 2; break;
+-    case '3': shamt &= shamt << 5; p += 2;
+-    }
+-
+-  if (p[0])
+-    {
+-      if (shfl)
+-        switch (p[1])
+-          {
+-          case 'w': shamt &= 15; break;
+-          case 'h': shamt &=  7; break;
+-          case 'b': shamt &=  3; break;
+-          case 'n': shamt &=  1; break;
+-          default: as_fatal (_("internal error: bad permutation pseudo-instruction %s"), op);
+-          }
+-      else
+-        switch (p[1])
+-          {
+-          case 'w': shamt &= 31; break;
+-          case 'h': shamt &= 15; break;
+-          case 'b': shamt &=  7; break;
+-          case 'n': shamt &=  3; break;
+-          case 'p': shamt &=  1; break;
+-          default: as_fatal (_("internal error: bad permutation pseudo-instruction %s"), op);
+-          }
+-    }
+-
+-  macro_build (NULL, insn, "d,s,>", rd, rs1, shamt);
+-}
+-
+ /* Expand RISC-V Vector macros into one of more instructions.  */
+ 
+ static void
+@@ -1701,10 +1649,6 @@ macro (struct riscv_cl_insn *ip, expressionS *imm_expr,
+       funnel_left (rd, rs1, rs3, shamt, ip->insn_mo->xlen_requirement ? ip->insn_mo->xlen_requirement/2 : xlen);
+       break;
+ 
+-    case M_PERM:
+-      perm (rd, rs1, ip->insn_mo->name);
+-      break;
+-
+     case M_LA:
+     case M_LLA:
+       /* Load the address of a symbol into a register.  */
+diff --git a/gas/testsuite/gas/riscv/bitmanip-insns-pseudo-32.d b/gas/testsuite/gas/riscv/bitmanip-insns-pseudo-32.d
+new file mode 100644
+index 0000000000..2f24a19efc
+--- /dev/null
++++ b/gas/testsuite/gas/riscv/bitmanip-insns-pseudo-32.d
+@@ -0,0 +1,60 @@
++#as: -march=rv32ib
++#source: bitmanip-insns-pseudo.s
++#objdump: -dr
++
++.*:[ 	]+file format .*
++
++
++Disassembly of section .text:
++
++0+000 <.text>:
++[ 	]+[0-9a-f]+:[ 	]+6815d513[ 	]+rev.p[ 	]+a0,a1
++[ 	]+[0-9a-f]+:[ 	]+6825d513[ 	]+rev2.n[ 	]+a0,a1
++[ 	]+[0-9a-f]+:[ 	]+6835d513[ 	]+rev.n[ 	]+a0,a1
++[ 	]+[0-9a-f]+:[ 	]+6845d513[ 	]+rev4.b[ 	]+a0,a1
++[ 	]+[0-9a-f]+:[ 	]+6865d513[ 	]+rev2.b[ 	]+a0,a1
++[ 	]+[0-9a-f]+:[ 	]+6875d513[ 	]+rev.b[ 	]+a0,a1
++[ 	]+[0-9a-f]+:[ 	]+6885d513[ 	]+rev8.h[ 	]+a0,a1
++[ 	]+[0-9a-f]+:[ 	]+68c5d513[ 	]+rev4.h[ 	]+a0,a1
++[ 	]+[0-9a-f]+:[ 	]+68e5d513[ 	]+rev2.h[ 	]+a0,a1
++[ 	]+[0-9a-f]+:[ 	]+68f5d513[ 	]+rev.h[ 	]+a0,a1
++[ 	]+[0-9a-f]+:[ 	]+6905d513[ 	]+rev16[ 	]+a0,a1
++[ 	]+[0-9a-f]+:[ 	]+6985d513[ 	]+rev8[ 	]+a0,a1
++[ 	]+[0-9a-f]+:[ 	]+69c5d513[ 	]+rev4[ 	]+a0,a1
++[ 	]+[0-9a-f]+:[ 	]+69e5d513[ 	]+rev2[ 	]+a0,a1
++[ 	]+[0-9a-f]+:[ 	]+69f5d513[ 	]+rev[ 	]+a0,a1
++[ 	]+[0-9a-f]+:[ 	]+2815d513[ 	]+orc.p[ 	]+a0,a1
++[ 	]+[0-9a-f]+:[ 	]+2825d513[ 	]+orc2.n[ 	]+a0,a1
++[ 	]+[0-9a-f]+:[ 	]+2835d513[ 	]+orc.n[ 	]+a0,a1
++[ 	]+[0-9a-f]+:[ 	]+2845d513[ 	]+orc4.b[ 	]+a0,a1
++[ 	]+[0-9a-f]+:[ 	]+2865d513[ 	]+orc2.b[ 	]+a0,a1
++[ 	]+[0-9a-f]+:[ 	]+2875d513[ 	]+orc.b[ 	]+a0,a1
++[ 	]+[0-9a-f]+:[ 	]+2885d513[ 	]+orc8.h[ 	]+a0,a1
++[ 	]+[0-9a-f]+:[ 	]+28c5d513[ 	]+orc4.h[ 	]+a0,a1
++[ 	]+[0-9a-f]+:[ 	]+28e5d513[ 	]+orc2.h[ 	]+a0,a1
++[ 	]+[0-9a-f]+:[ 	]+28f5d513[ 	]+orc.h[ 	]+a0,a1
++[ 	]+[0-9a-f]+:[ 	]+2905d513[ 	]+orc16[ 	]+a0,a1
++[ 	]+[0-9a-f]+:[ 	]+2985d513[ 	]+orc8[ 	]+a0,a1
++[ 	]+[0-9a-f]+:[ 	]+29c5d513[ 	]+orc4[ 	]+a0,a1
++[ 	]+[0-9a-f]+:[ 	]+29e5d513[ 	]+orc2[ 	]+a0,a1
++[ 	]+[0-9a-f]+:[ 	]+29f5d513[ 	]+orc[ 	]+a0,a1
++[ 	]+[0-9a-f]+:[ 	]+08159513[ 	]+zip.n[ 	]+a0,a1
++[ 	]+[0-9a-f]+:[ 	]+08259513[ 	]+zip2.b[ 	]+a0,a1
++[ 	]+[0-9a-f]+:[ 	]+08359513[ 	]+zip.b[ 	]+a0,a1
++[ 	]+[0-9a-f]+:[ 	]+08459513[ 	]+zip4.h[ 	]+a0,a1
++[ 	]+[0-9a-f]+:[ 	]+08659513[ 	]+zip2.h[ 	]+a0,a1
++[ 	]+[0-9a-f]+:[ 	]+08759513[ 	]+zip.h[ 	]+a0,a1
++[ 	]+[0-9a-f]+:[ 	]+08859513[ 	]+zip8[ 	]+a0,a1
++[ 	]+[0-9a-f]+:[ 	]+08c59513[ 	]+zip4[ 	]+a0,a1
++[ 	]+[0-9a-f]+:[ 	]+08e59513[ 	]+zip2[ 	]+a0,a1
++[ 	]+[0-9a-f]+:[ 	]+08f59513[ 	]+zip[ 	]+a0,a1
++[ 	]+[0-9a-f]+:[ 	]+0815d513[ 	]+unzip.n[ 	]+a0,a1
++[ 	]+[0-9a-f]+:[ 	]+0825d513[ 	]+unzip2.b[ 	]+a0,a1
++[ 	]+[0-9a-f]+:[ 	]+0835d513[ 	]+unzip.b[ 	]+a0,a1
++[ 	]+[0-9a-f]+:[ 	]+0845d513[ 	]+unzip4.h[ 	]+a0,a1
++[ 	]+[0-9a-f]+:[ 	]+0865d513[ 	]+unzip2.h[ 	]+a0,a1
++[ 	]+[0-9a-f]+:[ 	]+0875d513[ 	]+unzip.h[ 	]+a0,a1
++[ 	]+[0-9a-f]+:[ 	]+0885d513[ 	]+unzip8[ 	]+a0,a1
++[ 	]+[0-9a-f]+:[ 	]+08c5d513[ 	]+unzip4[ 	]+a0,a1
++[ 	]+[0-9a-f]+:[ 	]+08e5d513[ 	]+unzip2[ 	]+a0,a1
++[ 	]+[0-9a-f]+:[ 	]+08f5d513[ 	]+unzip[ 	]+a0,a1
+diff --git a/gas/testsuite/gas/riscv/bitmanip-insns-pseudo-64.d b/gas/testsuite/gas/riscv/bitmanip-insns-pseudo-64.d
+new file mode 100644
+index 0000000000..6c27edac80
+--- /dev/null
++++ b/gas/testsuite/gas/riscv/bitmanip-insns-pseudo-64.d
+@@ -0,0 +1,82 @@
++#as: -march=rv64ib -defsym __64_bit__=1
++#source: bitmanip-insns-pseudo.s
++#objdump: -dr
++
++.*:[ 	]+file format .*
++
++
++Disassembly of section .text:
++
++0+000 <.text>:
++[ 	]+[0-9a-f]+:[ 	]+6815d513[ 	]+rev.p[ 	]+a0,a1
++[ 	]+[0-9a-f]+:[ 	]+6825d513[ 	]+rev2.n[ 	]+a0,a1
++[ 	]+[0-9a-f]+:[ 	]+6835d513[ 	]+rev.n[ 	]+a0,a1
++[ 	]+[0-9a-f]+:[ 	]+6845d513[ 	]+rev4.b[ 	]+a0,a1
++[ 	]+[0-9a-f]+:[ 	]+6865d513[ 	]+rev2.b[ 	]+a0,a1
++[ 	]+[0-9a-f]+:[ 	]+6875d513[ 	]+rev.b[ 	]+a0,a1
++[ 	]+[0-9a-f]+:[ 	]+6885d513[ 	]+rev8.h[ 	]+a0,a1
++[ 	]+[0-9a-f]+:[ 	]+68c5d513[ 	]+rev4.h[ 	]+a0,a1
++[ 	]+[0-9a-f]+:[ 	]+68e5d513[ 	]+rev2.h[ 	]+a0,a1
++[ 	]+[0-9a-f]+:[ 	]+68f5d513[ 	]+rev.h[ 	]+a0,a1
++[ 	]+[0-9a-f]+:[ 	]+6b05d513[ 	]+rev16[ 	]+a0,a1
++[ 	]+[0-9a-f]+:[ 	]+6b85d513[ 	]+rev8[ 	]+a0,a1
++[ 	]+[0-9a-f]+:[ 	]+6bc5d513[ 	]+rev4[ 	]+a0,a1
++[ 	]+[0-9a-f]+:[ 	]+6be5d513[ 	]+rev2[ 	]+a0,a1
++[ 	]+[0-9a-f]+:[ 	]+6bf5d513[ 	]+rev[ 	]+a0,a1
++[ 	]+[0-9a-f]+:[ 	]+2815d513[ 	]+orc.p[ 	]+a0,a1
++[ 	]+[0-9a-f]+:[ 	]+2825d513[ 	]+orc2.n[ 	]+a0,a1
++[ 	]+[0-9a-f]+:[ 	]+2835d513[ 	]+orc.n[ 	]+a0,a1
++[ 	]+[0-9a-f]+:[ 	]+2845d513[ 	]+orc4.b[ 	]+a0,a1
++[ 	]+[0-9a-f]+:[ 	]+2865d513[ 	]+orc2.b[ 	]+a0,a1
++[ 	]+[0-9a-f]+:[ 	]+2875d513[ 	]+orc.b[ 	]+a0,a1
++[ 	]+[0-9a-f]+:[ 	]+2885d513[ 	]+orc8.h[ 	]+a0,a1
++[ 	]+[0-9a-f]+:[ 	]+28c5d513[ 	]+orc4.h[ 	]+a0,a1
++[ 	]+[0-9a-f]+:[ 	]+28e5d513[ 	]+orc2.h[ 	]+a0,a1
++[ 	]+[0-9a-f]+:[ 	]+28f5d513[ 	]+orc.h[ 	]+a0,a1
++[ 	]+[0-9a-f]+:[ 	]+2b05d513[ 	]+orc16[ 	]+a0,a1
++[ 	]+[0-9a-f]+:[ 	]+2b85d513[ 	]+orc8[ 	]+a0,a1
++[ 	]+[0-9a-f]+:[ 	]+2bc5d513[ 	]+orc4[ 	]+a0,a1
++[ 	]+[0-9a-f]+:[ 	]+2be5d513[ 	]+orc2[ 	]+a0,a1
++[ 	]+[0-9a-f]+:[ 	]+2bf5d513[ 	]+orc[ 	]+a0,a1
++[ 	]+[0-9a-f]+:[ 	]+08159513[ 	]+zip.n[ 	]+a0,a1
++[ 	]+[0-9a-f]+:[ 	]+08259513[ 	]+zip2.b[ 	]+a0,a1
++[ 	]+[0-9a-f]+:[ 	]+08359513[ 	]+zip.b[ 	]+a0,a1
++[ 	]+[0-9a-f]+:[ 	]+08459513[ 	]+zip4.h[ 	]+a0,a1
++[ 	]+[0-9a-f]+:[ 	]+08659513[ 	]+zip2.h[ 	]+a0,a1
++[ 	]+[0-9a-f]+:[ 	]+08759513[ 	]+zip.h[ 	]+a0,a1
++[ 	]+[0-9a-f]+:[ 	]+09859513[ 	]+zip8[ 	]+a0,a1
++[ 	]+[0-9a-f]+:[ 	]+09c59513[ 	]+zip4[ 	]+a0,a1
++[ 	]+[0-9a-f]+:[ 	]+09e59513[ 	]+zip2[ 	]+a0,a1
++[ 	]+[0-9a-f]+:[ 	]+09f59513[ 	]+zip[ 	]+a0,a1
++[ 	]+[0-9a-f]+:[ 	]+0815d513[ 	]+unzip.n[ 	]+a0,a1
++[ 	]+[0-9a-f]+:[ 	]+0825d513[ 	]+unzip2.b[ 	]+a0,a1
++[ 	]+[0-9a-f]+:[ 	]+0835d513[ 	]+unzip.b[ 	]+a0,a1
++[ 	]+[0-9a-f]+:[ 	]+0845d513[ 	]+unzip4.h[ 	]+a0,a1
++[ 	]+[0-9a-f]+:[ 	]+0865d513[ 	]+unzip2.h[ 	]+a0,a1
++[ 	]+[0-9a-f]+:[ 	]+0875d513[ 	]+unzip.h[ 	]+a0,a1
++[ 	]+[0-9a-f]+:[ 	]+0985d513[ 	]+unzip8[ 	]+a0,a1
++[ 	]+[0-9a-f]+:[ 	]+09c5d513[ 	]+unzip4[ 	]+a0,a1
++[ 	]+[0-9a-f]+:[ 	]+09e5d513[ 	]+unzip2[ 	]+a0,a1
++[ 	]+[0-9a-f]+:[ 	]+09f5d513[ 	]+unzip[ 	]+a0,a1
++[ 	]+[0-9a-f]+:[ 	]+6905d513[ 	]+rev16.w[ 	]+a0,a1
++[ 	]+[0-9a-f]+:[ 	]+6985d513[ 	]+rev8.w[ 	]+a0,a1
++[ 	]+[0-9a-f]+:[ 	]+69c5d513[ 	]+rev4.w[ 	]+a0,a1
++[ 	]+[0-9a-f]+:[ 	]+69e5d513[ 	]+rev2.w[ 	]+a0,a1
++[ 	]+[0-9a-f]+:[ 	]+69f5d513[ 	]+rev.w[ 	]+a0,a1
++[ 	]+[0-9a-f]+:[ 	]+6a05d513[ 	]+rev32[ 	]+a0,a1
++[ 	]+[0-9a-f]+:[ 	]+2905d513[ 	]+orc16.w[ 	]+a0,a1
++[ 	]+[0-9a-f]+:[ 	]+2985d513[ 	]+orc8.w[ 	]+a0,a1
++[ 	]+[0-9a-f]+:[ 	]+29c5d513[ 	]+orc4.w[ 	]+a0,a1
++[ 	]+[0-9a-f]+:[ 	]+29e5d513[ 	]+orc2.w[ 	]+a0,a1
++[ 	]+[0-9a-f]+:[ 	]+29f5d513[ 	]+orc.w[ 	]+a0,a1
++[ 	]+[0-9a-f]+:[ 	]+2a05d513[ 	]+orc32[ 	]+a0,a1
++[ 	]+[0-9a-f]+:[ 	]+08859513[ 	]+zip8.w[ 	]+a0,a1
++[ 	]+[0-9a-f]+:[ 	]+08c59513[ 	]+zip4.w[ 	]+a0,a1
++[ 	]+[0-9a-f]+:[ 	]+08e59513[ 	]+zip2.w[ 	]+a0,a1
++[ 	]+[0-9a-f]+:[ 	]+08f59513[ 	]+zip.w[ 	]+a0,a1
++[ 	]+[0-9a-f]+:[ 	]+09059513[ 	]+zip16[ 	]+a0,a1
++[ 	]+[0-9a-f]+:[ 	]+0885d513[ 	]+unzip8.w[ 	]+a0,a1
++[ 	]+[0-9a-f]+:[ 	]+08c5d513[ 	]+unzip4.w[ 	]+a0,a1
++[ 	]+[0-9a-f]+:[ 	]+08e5d513[ 	]+unzip2.w[ 	]+a0,a1
++[ 	]+[0-9a-f]+:[ 	]+08f5d513[ 	]+unzip.w[ 	]+a0,a1
++[ 	]+[0-9a-f]+:[ 	]+0905d513[ 	]+unzip16[ 	]+a0,a1
+diff --git a/gas/testsuite/gas/riscv/bitmanip-insns-pseudo-noalias-32.d b/gas/testsuite/gas/riscv/bitmanip-insns-pseudo-noalias-32.d
+new file mode 100644
+index 0000000000..c2dde4cfaa
+--- /dev/null
++++ b/gas/testsuite/gas/riscv/bitmanip-insns-pseudo-noalias-32.d
+@@ -0,0 +1,60 @@
++#as: -march=rv32ib
++#source: bitmanip-insns-pseudo.s
++#objdump: -dr -Mno-aliases
++
++.*:[ 	]+file format .*
++
++
++Disassembly of section .text:
++
++0+000 <.text>:
++[ 	]+[0-9a-f]+:[ 	]+6815d513[ 	]+grevi[ 	]+a0,a1,0x1
++[ 	]+[0-9a-f]+:[ 	]+6825d513[ 	]+grevi[ 	]+a0,a1,0x2
++[ 	]+[0-9a-f]+:[ 	]+6835d513[ 	]+grevi[ 	]+a0,a1,0x3
++[ 	]+[0-9a-f]+:[ 	]+6845d513[ 	]+grevi[ 	]+a0,a1,0x4
++[ 	]+[0-9a-f]+:[ 	]+6865d513[ 	]+grevi[ 	]+a0,a1,0x6
++[ 	]+[0-9a-f]+:[ 	]+6875d513[ 	]+grevi[ 	]+a0,a1,0x7
++[ 	]+[0-9a-f]+:[ 	]+6885d513[ 	]+grevi[ 	]+a0,a1,0x8
++[ 	]+[0-9a-f]+:[ 	]+68c5d513[ 	]+grevi[ 	]+a0,a1,0xc
++[ 	]+[0-9a-f]+:[ 	]+68e5d513[ 	]+grevi[ 	]+a0,a1,0xe
++[ 	]+[0-9a-f]+:[ 	]+68f5d513[ 	]+grevi[ 	]+a0,a1,0xf
++[ 	]+[0-9a-f]+:[ 	]+6905d513[ 	]+grevi[ 	]+a0,a1,0x10
++[ 	]+[0-9a-f]+:[ 	]+6985d513[ 	]+grevi[ 	]+a0,a1,0x18
++[ 	]+[0-9a-f]+:[ 	]+69c5d513[ 	]+grevi[ 	]+a0,a1,0x1c
++[ 	]+[0-9a-f]+:[ 	]+69e5d513[ 	]+grevi[ 	]+a0,a1,0x1e
++[ 	]+[0-9a-f]+:[ 	]+69f5d513[ 	]+grevi[ 	]+a0,a1,0x1f
++[ 	]+[0-9a-f]+:[ 	]+2815d513[ 	]+gorci[ 	]+a0,a1,0x1
++[ 	]+[0-9a-f]+:[ 	]+2825d513[ 	]+gorci[ 	]+a0,a1,0x2
++[ 	]+[0-9a-f]+:[ 	]+2835d513[ 	]+gorci[ 	]+a0,a1,0x3
++[ 	]+[0-9a-f]+:[ 	]+2845d513[ 	]+gorci[ 	]+a0,a1,0x4
++[ 	]+[0-9a-f]+:[ 	]+2865d513[ 	]+gorci[ 	]+a0,a1,0x6
++[ 	]+[0-9a-f]+:[ 	]+2875d513[ 	]+gorci[ 	]+a0,a1,0x7
++[ 	]+[0-9a-f]+:[ 	]+2885d513[ 	]+gorci[ 	]+a0,a1,0x8
++[ 	]+[0-9a-f]+:[ 	]+28c5d513[ 	]+gorci[ 	]+a0,a1,0xc
++[ 	]+[0-9a-f]+:[ 	]+28e5d513[ 	]+gorci[ 	]+a0,a1,0xe
++[ 	]+[0-9a-f]+:[ 	]+28f5d513[ 	]+gorci[ 	]+a0,a1,0xf
++[ 	]+[0-9a-f]+:[ 	]+2905d513[ 	]+gorci[ 	]+a0,a1,0x10
++[ 	]+[0-9a-f]+:[ 	]+2985d513[ 	]+gorci[ 	]+a0,a1,0x18
++[ 	]+[0-9a-f]+:[ 	]+29c5d513[ 	]+gorci[ 	]+a0,a1,0x1c
++[ 	]+[0-9a-f]+:[ 	]+29e5d513[ 	]+gorci[ 	]+a0,a1,0x1e
++[ 	]+[0-9a-f]+:[ 	]+29f5d513[ 	]+gorci[ 	]+a0,a1,0x1f
++[ 	]+[0-9a-f]+:[ 	]+08159513[ 	]+shfli[ 	]+a0,a1,0x1
++[ 	]+[0-9a-f]+:[ 	]+08259513[ 	]+shfli[ 	]+a0,a1,0x2
++[ 	]+[0-9a-f]+:[ 	]+08359513[ 	]+shfli[ 	]+a0,a1,0x3
++[ 	]+[0-9a-f]+:[ 	]+08459513[ 	]+shfli[ 	]+a0,a1,0x4
++[ 	]+[0-9a-f]+:[ 	]+08659513[ 	]+shfli[ 	]+a0,a1,0x6
++[ 	]+[0-9a-f]+:[ 	]+08759513[ 	]+shfli[ 	]+a0,a1,0x7
++[ 	]+[0-9a-f]+:[ 	]+08859513[ 	]+shfli[ 	]+a0,a1,0x8
++[ 	]+[0-9a-f]+:[ 	]+08c59513[ 	]+shfli[ 	]+a0,a1,0xc
++[ 	]+[0-9a-f]+:[ 	]+08e59513[ 	]+shfli[ 	]+a0,a1,0xe
++[ 	]+[0-9a-f]+:[ 	]+08f59513[ 	]+shfli[ 	]+a0,a1,0xf
++[ 	]+[0-9a-f]+:[ 	]+0815d513[ 	]+unshfli[ 	]+a0,a1,0x1
++[ 	]+[0-9a-f]+:[ 	]+0825d513[ 	]+unshfli[ 	]+a0,a1,0x2
++[ 	]+[0-9a-f]+:[ 	]+0835d513[ 	]+unshfli[ 	]+a0,a1,0x3
++[ 	]+[0-9a-f]+:[ 	]+0845d513[ 	]+unshfli[ 	]+a0,a1,0x4
++[ 	]+[0-9a-f]+:[ 	]+0865d513[ 	]+unshfli[ 	]+a0,a1,0x6
++[ 	]+[0-9a-f]+:[ 	]+0875d513[ 	]+unshfli[ 	]+a0,a1,0x7
++[ 	]+[0-9a-f]+:[ 	]+0885d513[ 	]+unshfli[ 	]+a0,a1,0x8
++[ 	]+[0-9a-f]+:[ 	]+08c5d513[ 	]+unshfli[ 	]+a0,a1,0xc
++[ 	]+[0-9a-f]+:[ 	]+08e5d513[ 	]+unshfli[ 	]+a0,a1,0xe
++[ 	]+[0-9a-f]+:[ 	]+08f5d513[ 	]+unshfli[ 	]+a0,a1,0xf
+diff --git a/gas/testsuite/gas/riscv/bitmanip-insns-pseudo-noalias-64.d b/gas/testsuite/gas/riscv/bitmanip-insns-pseudo-noalias-64.d
+new file mode 100644
+index 0000000000..abdbbcaed5
+--- /dev/null
++++ b/gas/testsuite/gas/riscv/bitmanip-insns-pseudo-noalias-64.d
+@@ -0,0 +1,82 @@
++#as: -march=rv64ib -defsym __64_bit__=1
++#source: bitmanip-insns-pseudo.s
++#objdump: -dr -Mno-aliases
++
++.*:[ 	]+file format .*
++
++
++Disassembly of section .text:
++
++0+000 <.text>:
++[ 	]+[0-9a-f]+:[ 	]+6815d513[ 	]+grevi[ 	]+a0,a1,0x1
++[ 	]+[0-9a-f]+:[ 	]+6825d513[ 	]+grevi[ 	]+a0,a1,0x2
++[ 	]+[0-9a-f]+:[ 	]+6835d513[ 	]+grevi[ 	]+a0,a1,0x3
++[ 	]+[0-9a-f]+:[ 	]+6845d513[ 	]+grevi[ 	]+a0,a1,0x4
++[ 	]+[0-9a-f]+:[ 	]+6865d513[ 	]+grevi[ 	]+a0,a1,0x6
++[ 	]+[0-9a-f]+:[ 	]+6875d513[ 	]+grevi[ 	]+a0,a1,0x7
++[ 	]+[0-9a-f]+:[ 	]+6885d513[ 	]+grevi[ 	]+a0,a1,0x8
++[ 	]+[0-9a-f]+:[ 	]+68c5d513[ 	]+grevi[ 	]+a0,a1,0xc
++[ 	]+[0-9a-f]+:[ 	]+68e5d513[ 	]+grevi[ 	]+a0,a1,0xe
++[ 	]+[0-9a-f]+:[ 	]+68f5d513[ 	]+grevi[ 	]+a0,a1,0xf
++[ 	]+[0-9a-f]+:[ 	]+6b05d513[ 	]+grevi[ 	]+a0,a1,0x30
++[ 	]+[0-9a-f]+:[ 	]+6b85d513[ 	]+grevi[ 	]+a0,a1,0x38
++[ 	]+[0-9a-f]+:[ 	]+6bc5d513[ 	]+grevi[ 	]+a0,a1,0x3c
++[ 	]+[0-9a-f]+:[ 	]+6be5d513[ 	]+grevi[ 	]+a0,a1,0x3e
++[ 	]+[0-9a-f]+:[ 	]+6bf5d513[ 	]+grevi[ 	]+a0,a1,0x3f
++[ 	]+[0-9a-f]+:[ 	]+2815d513[ 	]+gorci[ 	]+a0,a1,0x1
++[ 	]+[0-9a-f]+:[ 	]+2825d513[ 	]+gorci[ 	]+a0,a1,0x2
++[ 	]+[0-9a-f]+:[ 	]+2835d513[ 	]+gorci[ 	]+a0,a1,0x3
++[ 	]+[0-9a-f]+:[ 	]+2845d513[ 	]+gorci[ 	]+a0,a1,0x4
++[ 	]+[0-9a-f]+:[ 	]+2865d513[ 	]+gorci[ 	]+a0,a1,0x6
++[ 	]+[0-9a-f]+:[ 	]+2875d513[ 	]+gorci[ 	]+a0,a1,0x7
++[ 	]+[0-9a-f]+:[ 	]+2885d513[ 	]+gorci[ 	]+a0,a1,0x8
++[ 	]+[0-9a-f]+:[ 	]+28c5d513[ 	]+gorci[ 	]+a0,a1,0xc
++[ 	]+[0-9a-f]+:[ 	]+28e5d513[ 	]+gorci[ 	]+a0,a1,0xe
++[ 	]+[0-9a-f]+:[ 	]+28f5d513[ 	]+gorci[ 	]+a0,a1,0xf
++[ 	]+[0-9a-f]+:[ 	]+2b05d513[ 	]+gorci[ 	]+a0,a1,0x30
++[ 	]+[0-9a-f]+:[ 	]+2b85d513[ 	]+gorci[ 	]+a0,a1,0x38
++[ 	]+[0-9a-f]+:[ 	]+2bc5d513[ 	]+gorci[ 	]+a0,a1,0x3c
++[ 	]+[0-9a-f]+:[ 	]+2be5d513[ 	]+gorci[ 	]+a0,a1,0x3e
++[ 	]+[0-9a-f]+:[ 	]+2bf5d513[ 	]+gorci[ 	]+a0,a1,0x3f
++[ 	]+[0-9a-f]+:[ 	]+08159513[ 	]+shfli[ 	]+a0,a1,0x1
++[ 	]+[0-9a-f]+:[ 	]+08259513[ 	]+shfli[ 	]+a0,a1,0x2
++[ 	]+[0-9a-f]+:[ 	]+08359513[ 	]+shfli[ 	]+a0,a1,0x3
++[ 	]+[0-9a-f]+:[ 	]+08459513[ 	]+shfli[ 	]+a0,a1,0x4
++[ 	]+[0-9a-f]+:[ 	]+08659513[ 	]+shfli[ 	]+a0,a1,0x6
++[ 	]+[0-9a-f]+:[ 	]+08759513[ 	]+shfli[ 	]+a0,a1,0x7
++[ 	]+[0-9a-f]+:[ 	]+09859513[ 	]+shfli[ 	]+a0,a1,0x18
++[ 	]+[0-9a-f]+:[ 	]+09c59513[ 	]+shfli[ 	]+a0,a1,0x1c
++[ 	]+[0-9a-f]+:[ 	]+09e59513[ 	]+shfli[ 	]+a0,a1,0x1e
++[ 	]+[0-9a-f]+:[ 	]+09f59513[ 	]+shfli[ 	]+a0,a1,0x1f
++[ 	]+[0-9a-f]+:[ 	]+0815d513[ 	]+unshfli[ 	]+a0,a1,0x1
++[ 	]+[0-9a-f]+:[ 	]+0825d513[ 	]+unshfli[ 	]+a0,a1,0x2
++[ 	]+[0-9a-f]+:[ 	]+0835d513[ 	]+unshfli[ 	]+a0,a1,0x3
++[ 	]+[0-9a-f]+:[ 	]+0845d513[ 	]+unshfli[ 	]+a0,a1,0x4
++[ 	]+[0-9a-f]+:[ 	]+0865d513[ 	]+unshfli[ 	]+a0,a1,0x6
++[ 	]+[0-9a-f]+:[ 	]+0875d513[ 	]+unshfli[ 	]+a0,a1,0x7
++[ 	]+[0-9a-f]+:[ 	]+0985d513[ 	]+unshfli[ 	]+a0,a1,0x18
++[ 	]+[0-9a-f]+:[ 	]+09c5d513[ 	]+unshfli[ 	]+a0,a1,0x1c
++[ 	]+[0-9a-f]+:[ 	]+09e5d513[ 	]+unshfli[ 	]+a0,a1,0x1e
++[ 	]+[0-9a-f]+:[ 	]+09f5d513[ 	]+unshfli[ 	]+a0,a1,0x1f
++[ 	]+[0-9a-f]+:[ 	]+6905d513[ 	]+grevi[ 	]+a0,a1,0x10
++[ 	]+[0-9a-f]+:[ 	]+6985d513[ 	]+grevi[ 	]+a0,a1,0x18
++[ 	]+[0-9a-f]+:[ 	]+69c5d513[ 	]+grevi[ 	]+a0,a1,0x1c
++[ 	]+[0-9a-f]+:[ 	]+69e5d513[ 	]+grevi[ 	]+a0,a1,0x1e
++[ 	]+[0-9a-f]+:[ 	]+69f5d513[ 	]+grevi[ 	]+a0,a1,0x1f
++[ 	]+[0-9a-f]+:[ 	]+6a05d513[ 	]+grevi[ 	]+a0,a1,0x20
++[ 	]+[0-9a-f]+:[ 	]+2905d513[ 	]+gorci[ 	]+a0,a1,0x10
++[ 	]+[0-9a-f]+:[ 	]+2985d513[ 	]+gorci[ 	]+a0,a1,0x18
++[ 	]+[0-9a-f]+:[ 	]+29c5d513[ 	]+gorci[ 	]+a0,a1,0x1c
++[ 	]+[0-9a-f]+:[ 	]+29e5d513[ 	]+gorci[ 	]+a0,a1,0x1e
++[ 	]+[0-9a-f]+:[ 	]+29f5d513[ 	]+gorci[ 	]+a0,a1,0x1f
++[ 	]+[0-9a-f]+:[ 	]+2a05d513[ 	]+gorci[ 	]+a0,a1,0x20
++[ 	]+[0-9a-f]+:[ 	]+08859513[ 	]+shfli[ 	]+a0,a1,0x8
++[ 	]+[0-9a-f]+:[ 	]+08c59513[ 	]+shfli[ 	]+a0,a1,0xc
++[ 	]+[0-9a-f]+:[ 	]+08e59513[ 	]+shfli[ 	]+a0,a1,0xe
++[ 	]+[0-9a-f]+:[ 	]+08f59513[ 	]+shfli[ 	]+a0,a1,0xf
++[ 	]+[0-9a-f]+:[ 	]+09059513[ 	]+shfli[ 	]+a0,a1,0x10
++[ 	]+[0-9a-f]+:[ 	]+0885d513[ 	]+unshfli[ 	]+a0,a1,0x8
++[ 	]+[0-9a-f]+:[ 	]+08c5d513[ 	]+unshfli[ 	]+a0,a1,0xc
++[ 	]+[0-9a-f]+:[ 	]+08e5d513[ 	]+unshfli[ 	]+a0,a1,0xe
++[ 	]+[0-9a-f]+:[ 	]+08f5d513[ 	]+unshfli[ 	]+a0,a1,0xf
++[ 	]+[0-9a-f]+:[ 	]+0905d513[ 	]+unshfli[ 	]+a0,a1,0x10
+diff --git a/gas/testsuite/gas/riscv/bitmanip-insns-pseudo.s b/gas/testsuite/gas/riscv/bitmanip-insns-pseudo.s
+new file mode 100644
+index 0000000000..37adb96a77
+--- /dev/null
++++ b/gas/testsuite/gas/riscv/bitmanip-insns-pseudo.s
+@@ -0,0 +1,81 @@
++	rev.p	a0, a1
++	rev2.n	a0, a1
++	rev.n	a0, a1
++	rev4.b	a0, a1
++	rev2.b	a0, a1
++	rev.b	a0, a1
++	rev8.h	a0, a1
++	rev4.h	a0, a1
++	rev2.h	a0, a1
++	rev.h	a0, a1
++	rev16	a0, a1
++	rev8	a0, a1
++	rev4	a0, a1
++	rev2	a0, a1
++	rev	a0, a1
++
++	orc.p	a0, a1
++	orc2.n	a0, a1
++	orc.n	a0, a1
++	orc4.b	a0, a1
++	orc2.b	a0, a1
++	orc.b	a0, a1
++	orc8.h	a0, a1
++	orc4.h	a0, a1
++	orc2.h	a0, a1
++	orc.h	a0, a1
++	orc16	a0, a1
++	orc8	a0, a1
++	orc4	a0, a1
++	orc2	a0, a1
++	orc	a0, a1
++
++	zip.n	a0, a1
++	zip2.b	a0, a1
++	zip.b	a0, a1
++	zip4.h	a0, a1
++	zip2.h	a0, a1
++	zip.h	a0, a1
++	zip8	a0, a1
++	zip4	a0, a1
++	zip2	a0, a1
++	zip	a0, a1
++
++	unzip.n		a0, a1
++	unzip2.b	a0, a1
++	unzip.b		a0, a1
++	unzip4.h	a0, a1
++	unzip2.h	a0, a1
++	unzip.h		a0, a1
++	unzip8		a0, a1
++	unzip4		a0, a1
++	unzip2		a0, a1
++	unzip		a0, a1
++
++.ifdef __64_bit__
++	rev16.w	a0, a1
++	rev8.w	a0, a1
++	rev4.w	a0, a1
++	rev2.w	a0, a1
++	rev.w	a0, a1
++	rev32	a0, a1
++
++	orc16.w	a0, a1
++	orc8.w	a0, a1
++	orc4.w	a0, a1
++	orc2.w	a0, a1
++	orc.w	a0, a1
++	orc32	a0, a1
++
++	zip8.w	a0, a1
++	zip4.w	a0, a1
++	zip2.w	a0, a1
++	zip.w	a0, a1
++	zip16	a0, a1
++
++	unzip8.w	a0, a1
++	unzip4.w	a0, a1
++	unzip2.w	a0, a1
++	unzip.w		a0, a1
++	unzip16		a0, a1
++.endif
+diff --git a/include/opcode/riscv.h b/include/opcode/riscv.h
+index a23a2a8002..9af4f6514c 100644
+--- a/include/opcode/riscv.h
++++ b/include/opcode/riscv.h
+@@ -583,7 +583,6 @@ enum
+   M_VMSGEU,
+   M_RL,
+   M_FL,
+-  M_PERM,
+   M_NUM_MACROS
+ };
+ 
+diff --git a/opcodes/riscv-opc.c b/opcodes/riscv-opc.c
+index 86cfcabec9..5d49912e2e 100644
+--- a/opcodes/riscv-opc.c
++++ b/opcodes/riscv-opc.c
+@@ -69,6 +69,51 @@ const char * const riscv_vecm_names_numeric[NVECM] =
+   "v0.t"
+ };
+ 
++/* The MATCH/MASK immediate macros for rvb pseudo instructions.  */
++
++#define MASK_RVB_IMM (OP_MASK_SHAMT << OP_SH_SHAMT)
++
++#define ENCODE_PERM_IMM(xlen, prefix, suffix) \
++  (ENCODE_ITYPE_IMM ((((xlen) - 1) & (((xlen) - 1) << (prefix)) & (suffix))))
++
++#define MATCH_PERM_IMM(xlen)    (ENCODE_PERM_IMM ((xlen), 0, -1))
++#define MATCH_PERM2_IMM(xlen)   (ENCODE_PERM_IMM ((xlen), 1, -1))
++#define MATCH_PERM4_IMM(xlen)   (ENCODE_PERM_IMM ((xlen), 2, -1))
++#define MATCH_PERM8_IMM(xlen)   (ENCODE_PERM_IMM ((xlen), 3, -1))
++#define MATCH_PERM16_IMM(xlen)  (ENCODE_PERM_IMM ((xlen), 4, -1))
++#define MATCH_PERM32_IMM(xlen)  (ENCODE_PERM_IMM ((xlen), 5, -1))
++#define MATCH_PERMP_IMM(xlen)   (ENCODE_PERM_IMM ((xlen), 0, 0x1))
++#define MATCH_PERMN_IMM(xlen)   (ENCODE_PERM_IMM ((xlen), 0, 0x3))
++#define MATCH_PERMB_IMM(xlen)   (ENCODE_PERM_IMM ((xlen), 0, 0x7))
++#define MATCH_PERMH_IMM(xlen)   (ENCODE_PERM_IMM ((xlen), 0, 0xf))
++#define MATCH_PERMW_IMM(xlen)   (ENCODE_PERM_IMM ((xlen), 0, 0x1f))
++#define MATCH_PERM2N_IMM(xlen)  (ENCODE_PERM_IMM ((xlen), 1, 0x3))
++#define MATCH_PERM2B_IMM(xlen)  (ENCODE_PERM_IMM ((xlen), 1, 0x7))
++#define MATCH_PERM4B_IMM(xlen)  (ENCODE_PERM_IMM ((xlen), 2, 0x7))
++#define MATCH_PERM2H_IMM(xlen)  (ENCODE_PERM_IMM ((xlen), 1, 0xf))
++#define MATCH_PERM4H_IMM(xlen)  (ENCODE_PERM_IMM ((xlen), 2, 0xf))
++#define MATCH_PERM8H_IMM(xlen)  (ENCODE_PERM_IMM ((xlen), 3, 0xf))
++#define MATCH_PERM2W_IMM(xlen)  (ENCODE_PERM_IMM ((xlen), 1, 0x1f))
++#define MATCH_PERM4W_IMM(xlen)  (ENCODE_PERM_IMM ((xlen), 2, 0x1f))
++#define MATCH_PERM8W_IMM(xlen)  (ENCODE_PERM_IMM ((xlen), 3, 0x1f))
++#define MATCH_PERM16W_IMM(xlen) (ENCODE_PERM_IMM ((xlen), 4, 0x1f))
++
++#define MATCH_PERM_SHFL_IMM(xlen)    (ENCODE_PERM_IMM ((xlen/2), 0, -1))
++#define MATCH_PERM2_SHFL_IMM(xlen)   (ENCODE_PERM_IMM ((xlen/2), 1, -1))
++#define MATCH_PERM4_SHFL_IMM(xlen)   (ENCODE_PERM_IMM ((xlen/2), 2, -1))
++#define MATCH_PERM8_SHFL_IMM(xlen)   (ENCODE_PERM_IMM ((xlen/2), 3, -1))
++#define MATCH_PERM16_SHFL_IMM(xlen)  (ENCODE_PERM_IMM ((xlen/2), 4, -1))
++#define MATCH_PERMN_SHFL_IMM(xlen)   (ENCODE_PERM_IMM ((xlen/2), 0, 0x1))
++#define MATCH_PERMB_SHFL_IMM(xlen)   (ENCODE_PERM_IMM ((xlen/2), 0, 0x3))
++#define MATCH_PERMH_SHFL_IMM(xlen)   (ENCODE_PERM_IMM ((xlen/2), 0, 0x7))
++#define MATCH_PERMW_SHFL_IMM(xlen)   (ENCODE_PERM_IMM ((xlen/2), 0, 0xf))
++#define MATCH_PERM2B_SHFL_IMM(xlen)  (ENCODE_PERM_IMM ((xlen/2), 1, 0x3))
++#define MATCH_PERM2H_SHFL_IMM(xlen)  (ENCODE_PERM_IMM ((xlen/2), 1, 0x7))
++#define MATCH_PERM4H_SHFL_IMM(xlen)  (ENCODE_PERM_IMM ((xlen/2), 2, 0x7))
++#define MATCH_PERM2W_SHFL_IMM(xlen)  (ENCODE_PERM_IMM ((xlen/2), 1, 0xf))
++#define MATCH_PERM4W_SHFL_IMM(xlen)  (ENCODE_PERM_IMM ((xlen/2), 2, 0xf))
++#define MATCH_PERM8W_SHFL_IMM(xlen)  (ENCODE_PERM_IMM ((xlen/2), 3, 0xf))
++
+ /* The order of overloaded instructions matters.  Label arguments and
+    register arguments look the same. Instructions that can have either
+    for arguments must apear in the correct order in this table for the
+@@ -984,6 +1029,133 @@ const struct riscv_opcode riscv_opcodes[] =
+ {"fcvt.h.lu", 64, INSN_CLASS_F_AND_ZFH,   "D,s",  MATCH_FCVT_H_LU | MASK_RM, MASK_FCVT_H_L | MASK_RM, match_opcode, 0 },
+ {"fcvt.h.lu", 64, INSN_CLASS_F_AND_ZFH,   "D,s,m",  MATCH_FCVT_H_LU, MASK_FCVT_H_LU, match_opcode, 0 },
+ 
++/* Bitmanip pseudo-instructions.  */
++{"rev.p",    32, INSN_CLASS_B,   "d,s",  MATCH_GREVI | MATCH_PERMP_IMM (32), MASK_GREVI | MASK_RVB_IMM, match_opcode, INSN_ALIAS },
++{"rev.p",    64, INSN_CLASS_B,   "d,s",  MATCH_GREVI | MATCH_PERMP_IMM (64), MASK_GREVI | MASK_RVB_IMM, match_opcode, INSN_ALIAS },
++{"rev2.n",   32, INSN_CLASS_B,   "d,s",  MATCH_GREVI | MATCH_PERM2N_IMM (32), MASK_GREVI | MASK_RVB_IMM, match_opcode, INSN_ALIAS },
++{"rev2.n",   64, INSN_CLASS_B,   "d,s",  MATCH_GREVI | MATCH_PERM2N_IMM (64), MASK_GREVI | MASK_RVB_IMM, match_opcode, INSN_ALIAS },
++{"rev.n",    32, INSN_CLASS_B,   "d,s",  MATCH_GREVI | MATCH_PERMN_IMM (32), MASK_GREVI | MASK_RVB_IMM, match_opcode, INSN_ALIAS },
++{"rev.n",    64, INSN_CLASS_B,   "d,s",  MATCH_GREVI | MATCH_PERMN_IMM (64), MASK_GREVI | MASK_RVB_IMM, match_opcode, INSN_ALIAS },
++{"rev4.b",   32, INSN_CLASS_B,   "d,s",  MATCH_GREVI | MATCH_PERM4B_IMM (32), MASK_GREVI | MASK_RVB_IMM, match_opcode, INSN_ALIAS },
++{"rev4.b",   64, INSN_CLASS_B,   "d,s",  MATCH_GREVI | MATCH_PERM4B_IMM (64), MASK_GREVI | MASK_RVB_IMM, match_opcode, INSN_ALIAS },
++{"rev2.b",   32, INSN_CLASS_B,   "d,s",  MATCH_GREVI | MATCH_PERM2B_IMM (32), MASK_GREVI | MASK_RVB_IMM, match_opcode, INSN_ALIAS },
++{"rev2.b",   64, INSN_CLASS_B,   "d,s",  MATCH_GREVI | MATCH_PERM2B_IMM (64), MASK_GREVI | MASK_RVB_IMM, match_opcode, INSN_ALIAS },
++{"rev.b",    32, INSN_CLASS_B,   "d,s",  MATCH_GREVI | MATCH_PERMB_IMM (32), MASK_GREVI | MASK_RVB_IMM, match_opcode, INSN_ALIAS },
++{"rev.b",    64, INSN_CLASS_B,   "d,s",  MATCH_GREVI | MATCH_PERMB_IMM (64), MASK_GREVI | MASK_RVB_IMM, match_opcode, INSN_ALIAS },
++{"rev8.h",   32, INSN_CLASS_B,   "d,s",  MATCH_GREVI | MATCH_PERM8H_IMM (32), MASK_GREVI | MASK_RVB_IMM, match_opcode, INSN_ALIAS },
++{"rev8.h",   64, INSN_CLASS_B,   "d,s",  MATCH_GREVI | MATCH_PERM8H_IMM (64), MASK_GREVI | MASK_RVB_IMM, match_opcode, INSN_ALIAS },
++{"rev4.h",   32, INSN_CLASS_B,   "d,s",  MATCH_GREVI | MATCH_PERM4H_IMM (32), MASK_GREVI | MASK_RVB_IMM, match_opcode, INSN_ALIAS },
++{"rev4.h",   64, INSN_CLASS_B,   "d,s",  MATCH_GREVI | MATCH_PERM4H_IMM (64), MASK_GREVI | MASK_RVB_IMM, match_opcode, INSN_ALIAS },
++{"rev2.h",   32, INSN_CLASS_B,   "d,s",  MATCH_GREVI | MATCH_PERM2H_IMM (32), MASK_GREVI | MASK_RVB_IMM, match_opcode, INSN_ALIAS },
++{"rev2.h",   64, INSN_CLASS_B,   "d,s",  MATCH_GREVI | MATCH_PERM2H_IMM (64), MASK_GREVI | MASK_RVB_IMM, match_opcode, INSN_ALIAS },
++{"rev.h",    32, INSN_CLASS_B,   "d,s",  MATCH_GREVI | MATCH_PERMH_IMM (32), MASK_GREVI | MASK_RVB_IMM, match_opcode, INSN_ALIAS },
++{"rev.h",    64, INSN_CLASS_B,   "d,s",  MATCH_GREVI | MATCH_PERMH_IMM (64), MASK_GREVI | MASK_RVB_IMM, match_opcode, INSN_ALIAS },
++{"rev16",    32, INSN_CLASS_B,   "d,s",  MATCH_GREVI | MATCH_PERM16_IMM (32), MASK_GREVI | MASK_RVB_IMM, match_opcode, INSN_ALIAS },
++{"rev16",    64, INSN_CLASS_B,   "d,s",  MATCH_GREVI | MATCH_PERM16_IMM (64), MASK_GREVI | MASK_RVB_IMM, match_opcode, INSN_ALIAS },
++{"rev8",     32, INSN_CLASS_B_OR_ZBB,   "d,s",  MATCH_GREVI | MATCH_PERM8_IMM (32), MASK_GREVI | MASK_RVB_IMM, match_opcode, INSN_ALIAS },
++{"rev8",     64, INSN_CLASS_B_OR_ZBB,   "d,s",  MATCH_GREVI | MATCH_PERM8_IMM (64), MASK_GREVI | MASK_RVB_IMM, match_opcode, INSN_ALIAS },
++{"rev4",     32, INSN_CLASS_B,   "d,s",  MATCH_GREVI | MATCH_PERM4_IMM (32), MASK_GREVI | MASK_RVB_IMM, match_opcode, INSN_ALIAS },
++{"rev4",     64, INSN_CLASS_B,   "d,s",  MATCH_GREVI | MATCH_PERM4_IMM (64), MASK_GREVI | MASK_RVB_IMM, match_opcode, INSN_ALIAS },
++{"rev2",     32, INSN_CLASS_B,   "d,s",  MATCH_GREVI | MATCH_PERM2_IMM (32), MASK_GREVI | MASK_RVB_IMM, match_opcode, INSN_ALIAS },
++{"rev2",     64, INSN_CLASS_B,   "d,s",  MATCH_GREVI | MATCH_PERM2_IMM (64), MASK_GREVI | MASK_RVB_IMM, match_opcode, INSN_ALIAS },
++{"rev",      32, INSN_CLASS_B,   "d,s",  MATCH_GREVI | MATCH_PERM_IMM (32), MASK_GREVI | MASK_RVB_IMM, match_opcode, INSN_ALIAS },
++{"rev",      64, INSN_CLASS_B,   "d,s",  MATCH_GREVI | MATCH_PERM_IMM (64), MASK_GREVI | MASK_RVB_IMM, match_opcode, INSN_ALIAS },
++{"rev16.w",  64, INSN_CLASS_B,   "d,s",  MATCH_GREVI | MATCH_PERM16W_IMM (64), MASK_GREVI | MASK_RVB_IMM, match_opcode, INSN_ALIAS },
++{"rev8.w",   64, INSN_CLASS_B,   "d,s",  MATCH_GREVI | MATCH_PERM8W_IMM (64), MASK_GREVI | MASK_RVB_IMM, match_opcode, INSN_ALIAS },
++{"rev4.w",   64, INSN_CLASS_B,   "d,s",  MATCH_GREVI | MATCH_PERM4W_IMM (64), MASK_GREVI | MASK_RVB_IMM, match_opcode, INSN_ALIAS },
++{"rev2.w",   64, INSN_CLASS_B,   "d,s",  MATCH_GREVI | MATCH_PERM2W_IMM (64), MASK_GREVI | MASK_RVB_IMM, match_opcode, INSN_ALIAS },
++{"rev.w",    64, INSN_CLASS_B,   "d,s",  MATCH_GREVI | MATCH_PERMW_IMM (64), MASK_GREVI | MASK_RVB_IMM, match_opcode, INSN_ALIAS },
++{"rev32",    64, INSN_CLASS_B,   "d,s",  MATCH_GREVI | MATCH_PERM32_IMM (64), MASK_GREVI | MASK_RVB_IMM, match_opcode, INSN_ALIAS },
++
++{"orc.p",    32, INSN_CLASS_B,   "d,s",  MATCH_GORCI | MATCH_PERMP_IMM (32), MASK_GORCI | MASK_RVB_IMM, match_opcode, INSN_ALIAS },
++{"orc.p",    64, INSN_CLASS_B,   "d,s",  MATCH_GORCI | MATCH_PERMP_IMM (64), MASK_GORCI | MASK_RVB_IMM, match_opcode, INSN_ALIAS },
++{"orc2.n",   32, INSN_CLASS_B,   "d,s",  MATCH_GORCI | MATCH_PERM2N_IMM (32), MASK_GORCI | MASK_RVB_IMM, match_opcode, INSN_ALIAS },
++{"orc2.n",   64, INSN_CLASS_B,   "d,s",  MATCH_GORCI | MATCH_PERM2N_IMM (64), MASK_GORCI | MASK_RVB_IMM, match_opcode, INSN_ALIAS },
++{"orc.n",    32, INSN_CLASS_B,   "d,s",  MATCH_GORCI | MATCH_PERMN_IMM (32), MASK_GORCI | MASK_RVB_IMM, match_opcode, INSN_ALIAS },
++{"orc.n",    64, INSN_CLASS_B,   "d,s",  MATCH_GORCI | MATCH_PERMN_IMM (64), MASK_GORCI | MASK_RVB_IMM, match_opcode, INSN_ALIAS },
++{"orc4.b",   32, INSN_CLASS_B,   "d,s",  MATCH_GORCI | MATCH_PERM4B_IMM (32), MASK_GORCI | MASK_RVB_IMM, match_opcode, INSN_ALIAS },
++{"orc4.b",   64, INSN_CLASS_B,   "d,s",  MATCH_GORCI | MATCH_PERM4B_IMM (64), MASK_GORCI | MASK_RVB_IMM, match_opcode, INSN_ALIAS },
++{"orc2.b",   32, INSN_CLASS_B,   "d,s",  MATCH_GORCI | MATCH_PERM2B_IMM (32), MASK_GORCI | MASK_RVB_IMM, match_opcode, INSN_ALIAS },
++{"orc2.b",   64, INSN_CLASS_B,   "d,s",  MATCH_GORCI | MATCH_PERM2B_IMM (64), MASK_GORCI | MASK_RVB_IMM, match_opcode, INSN_ALIAS },
++{"orc.b",    32, INSN_CLASS_B_OR_ZBB,   "d,s",  MATCH_GORCI | MATCH_PERMB_IMM (32), MASK_GORCI | MASK_RVB_IMM, match_opcode, INSN_ALIAS },
++{"orc.b",    64, INSN_CLASS_B_OR_ZBB,   "d,s",  MATCH_GORCI | MATCH_PERMB_IMM (64), MASK_GORCI | MASK_RVB_IMM, match_opcode, INSN_ALIAS },
++{"orc8.h",   32, INSN_CLASS_B,   "d,s",  MATCH_GORCI | MATCH_PERM8H_IMM (32), MASK_GORCI | MASK_RVB_IMM, match_opcode, INSN_ALIAS },
++{"orc8.h",   64, INSN_CLASS_B,   "d,s",  MATCH_GORCI | MATCH_PERM8H_IMM (64), MASK_GORCI | MASK_RVB_IMM, match_opcode, INSN_ALIAS },
++{"orc4.h",   32, INSN_CLASS_B,   "d,s",  MATCH_GORCI | MATCH_PERM4H_IMM (32), MASK_GORCI | MASK_RVB_IMM, match_opcode, INSN_ALIAS },
++{"orc4.h",   64, INSN_CLASS_B,   "d,s",  MATCH_GORCI | MATCH_PERM4H_IMM (64), MASK_GORCI | MASK_RVB_IMM, match_opcode, INSN_ALIAS },
++{"orc2.h",   32, INSN_CLASS_B,   "d,s",  MATCH_GORCI | MATCH_PERM2H_IMM (32), MASK_GORCI | MASK_RVB_IMM, match_opcode, INSN_ALIAS },
++{"orc2.h",   64, INSN_CLASS_B,   "d,s",  MATCH_GORCI | MATCH_PERM2H_IMM (64), MASK_GORCI | MASK_RVB_IMM, match_opcode, INSN_ALIAS },
++{"orc.h",    32, INSN_CLASS_B,   "d,s",  MATCH_GORCI | MATCH_PERMH_IMM (32), MASK_GORCI | MASK_RVB_IMM, match_opcode, INSN_ALIAS },
++{"orc.h",    64, INSN_CLASS_B,   "d,s",  MATCH_GORCI | MATCH_PERMH_IMM (64), MASK_GORCI | MASK_RVB_IMM, match_opcode, INSN_ALIAS },
++{"orc16",    32, INSN_CLASS_B,   "d,s",  MATCH_GORCI | MATCH_PERM16_IMM (32), MASK_GORCI | MASK_RVB_IMM, match_opcode, INSN_ALIAS },
++{"orc16",    64, INSN_CLASS_B,   "d,s",  MATCH_GORCI | MATCH_PERM16_IMM (64), MASK_GORCI | MASK_RVB_IMM, match_opcode, INSN_ALIAS },
++{"orc8",     32, INSN_CLASS_B,   "d,s",  MATCH_GORCI | MATCH_PERM8_IMM (32), MASK_GORCI | MASK_RVB_IMM, match_opcode, INSN_ALIAS },
++{"orc8",     64, INSN_CLASS_B,   "d,s",  MATCH_GORCI | MATCH_PERM8_IMM (64), MASK_GORCI | MASK_RVB_IMM, match_opcode, INSN_ALIAS },
++{"orc4",     32, INSN_CLASS_B,   "d,s",  MATCH_GORCI | MATCH_PERM4_IMM (32), MASK_GORCI | MASK_RVB_IMM, match_opcode, INSN_ALIAS },
++{"orc4",     64, INSN_CLASS_B,   "d,s",  MATCH_GORCI | MATCH_PERM4_IMM (64), MASK_GORCI | MASK_RVB_IMM, match_opcode, INSN_ALIAS },
++{"orc2",     32, INSN_CLASS_B,   "d,s",  MATCH_GORCI | MATCH_PERM2_IMM (32), MASK_GORCI | MASK_RVB_IMM, match_opcode, INSN_ALIAS },
++{"orc2",     64, INSN_CLASS_B,   "d,s",  MATCH_GORCI | MATCH_PERM2_IMM (64), MASK_GORCI | MASK_RVB_IMM, match_opcode, INSN_ALIAS },
++{"orc",      32, INSN_CLASS_B,   "d,s",  MATCH_GORCI | MATCH_PERM_IMM (32), MASK_GORCI | MASK_RVB_IMM, match_opcode, INSN_ALIAS },
++{"orc",      64, INSN_CLASS_B,   "d,s",  MATCH_GORCI | MATCH_PERM_IMM (64), MASK_GORCI | MASK_RVB_IMM, match_opcode, INSN_ALIAS },
++{"orc16.w",  64, INSN_CLASS_B,   "d,s",  MATCH_GORCI | MATCH_PERM16W_IMM (64), MASK_GORCI | MASK_RVB_IMM, match_opcode, INSN_ALIAS },
++{"orc8.w",   64, INSN_CLASS_B,   "d,s",  MATCH_GORCI | MATCH_PERM8W_IMM (64), MASK_GORCI | MASK_RVB_IMM, match_opcode, INSN_ALIAS },
++{"orc4.w",   64, INSN_CLASS_B,   "d,s",  MATCH_GORCI | MATCH_PERM4W_IMM (64), MASK_GORCI | MASK_RVB_IMM, match_opcode, INSN_ALIAS },
++{"orc2.w",   64, INSN_CLASS_B,   "d,s",  MATCH_GORCI | MATCH_PERM2W_IMM (64), MASK_GORCI | MASK_RVB_IMM, match_opcode, INSN_ALIAS },
++{"orc.w",    64, INSN_CLASS_B,   "d,s",  MATCH_GORCI | MATCH_PERMW_IMM (64), MASK_GORCI | MASK_RVB_IMM, match_opcode, INSN_ALIAS },
++{"orc32",    64, INSN_CLASS_B,   "d,s",  MATCH_GORCI | MATCH_PERM32_IMM (64), MASK_GORCI | MASK_RVB_IMM, match_opcode, INSN_ALIAS },
++
++{"zip.n",    32, INSN_CLASS_B,   "d,s",  MATCH_SHFLI | MATCH_PERMN_SHFL_IMM (32), MASK_SHFLI | MASK_RVB_IMM, match_opcode, INSN_ALIAS },
++{"zip.n",    64, INSN_CLASS_B,   "d,s",  MATCH_SHFLI | MATCH_PERMN_SHFL_IMM (64), MASK_SHFLI | MASK_RVB_IMM, match_opcode, INSN_ALIAS },
++{"zip2.b",   32, INSN_CLASS_B,   "d,s",  MATCH_SHFLI | MATCH_PERM2B_SHFL_IMM (32), MASK_SHFLI | MASK_RVB_IMM, match_opcode, INSN_ALIAS },
++{"zip2.b",   64, INSN_CLASS_B,   "d,s",  MATCH_SHFLI | MATCH_PERM2B_SHFL_IMM (64), MASK_SHFLI | MASK_RVB_IMM, match_opcode, INSN_ALIAS },
++{"zip.b",    32, INSN_CLASS_B,   "d,s",  MATCH_SHFLI | MATCH_PERMB_SHFL_IMM (32), MASK_SHFLI | MASK_RVB_IMM, match_opcode, INSN_ALIAS },
++{"zip.b",    64, INSN_CLASS_B,   "d,s",  MATCH_SHFLI | MATCH_PERMB_SHFL_IMM (64), MASK_SHFLI | MASK_RVB_IMM, match_opcode, INSN_ALIAS },
++{"zip4.h",   32, INSN_CLASS_B,   "d,s",  MATCH_SHFLI | MATCH_PERM4H_SHFL_IMM (32), MASK_SHFLI | MASK_RVB_IMM, match_opcode, INSN_ALIAS },
++{"zip4.h",   64, INSN_CLASS_B,   "d,s",  MATCH_SHFLI | MATCH_PERM4H_SHFL_IMM (64), MASK_SHFLI | MASK_RVB_IMM, match_opcode, INSN_ALIAS },
++{"zip2.h",   32, INSN_CLASS_B,   "d,s",  MATCH_SHFLI | MATCH_PERM2H_SHFL_IMM (32), MASK_SHFLI | MASK_RVB_IMM, match_opcode, INSN_ALIAS },
++{"zip2.h",   64, INSN_CLASS_B,   "d,s",  MATCH_SHFLI | MATCH_PERM2H_SHFL_IMM (64), MASK_SHFLI | MASK_RVB_IMM, match_opcode, INSN_ALIAS },
++{"zip.h",    32, INSN_CLASS_B,   "d,s",  MATCH_SHFLI | MATCH_PERMH_SHFL_IMM (32), MASK_SHFLI | MASK_RVB_IMM, match_opcode, INSN_ALIAS },
++{"zip.h",    64, INSN_CLASS_B,   "d,s",  MATCH_SHFLI | MATCH_PERMH_SHFL_IMM (64), MASK_SHFLI | MASK_RVB_IMM, match_opcode, INSN_ALIAS },
++{"zip8",     32, INSN_CLASS_B,   "d,s",  MATCH_SHFLI | MATCH_PERM8_SHFL_IMM (32), MASK_SHFLI | MASK_RVB_IMM, match_opcode, INSN_ALIAS },
++{"zip8",     64, INSN_CLASS_B,   "d,s",  MATCH_SHFLI | MATCH_PERM8_SHFL_IMM (64), MASK_SHFLI | MASK_RVB_IMM, match_opcode, INSN_ALIAS },
++{"zip4",     32, INSN_CLASS_B,   "d,s",  MATCH_SHFLI | MATCH_PERM4_SHFL_IMM (32), MASK_SHFLI | MASK_RVB_IMM, match_opcode, INSN_ALIAS },
++{"zip4",     64, INSN_CLASS_B,   "d,s",  MATCH_SHFLI | MATCH_PERM4_SHFL_IMM (64), MASK_SHFLI | MASK_RVB_IMM, match_opcode, INSN_ALIAS },
++{"zip2",     32, INSN_CLASS_B,   "d,s",  MATCH_SHFLI | MATCH_PERM2_SHFL_IMM (32), MASK_SHFLI | MASK_RVB_IMM, match_opcode, INSN_ALIAS },
++{"zip2",     64, INSN_CLASS_B,   "d,s",  MATCH_SHFLI | MATCH_PERM2_SHFL_IMM (64), MASK_SHFLI | MASK_RVB_IMM, match_opcode, INSN_ALIAS },
++{"zip",      32, INSN_CLASS_B,   "d,s",  MATCH_SHFLI | MATCH_PERM_SHFL_IMM (32), MASK_SHFLI | MASK_RVB_IMM, match_opcode, INSN_ALIAS },
++{"zip",      64, INSN_CLASS_B,   "d,s",  MATCH_SHFLI | MATCH_PERM_SHFL_IMM (64), MASK_SHFLI | MASK_RVB_IMM, match_opcode, INSN_ALIAS },
++{"zip8.w",   64, INSN_CLASS_B,   "d,s",  MATCH_SHFLI | MATCH_PERM8W_SHFL_IMM (64), MASK_SHFLI | MASK_RVB_IMM, match_opcode, INSN_ALIAS },
++{"zip4.w",   64, INSN_CLASS_B,   "d,s",  MATCH_SHFLI | MATCH_PERM4W_SHFL_IMM (64), MASK_SHFLI | MASK_RVB_IMM, match_opcode, INSN_ALIAS },
++{"zip2.w",   64, INSN_CLASS_B,   "d,s",  MATCH_SHFLI | MATCH_PERM2W_SHFL_IMM (64), MASK_SHFLI | MASK_RVB_IMM, match_opcode, INSN_ALIAS },
++{"zip.w",    64, INSN_CLASS_B,   "d,s",  MATCH_SHFLI | MATCH_PERMW_SHFL_IMM (64), MASK_SHFLI | MASK_RVB_IMM, match_opcode, INSN_ALIAS },
++{"zip16",    64, INSN_CLASS_B,   "d,s",  MATCH_SHFLI | MATCH_PERM16_SHFL_IMM (64), MASK_SHFLI | MASK_RVB_IMM, match_opcode, INSN_ALIAS },
++
++{"unzip.n",  32, INSN_CLASS_B,   "d,s",  MATCH_UNSHFLI | MATCH_PERMN_SHFL_IMM (32), MASK_UNSHFLI | MASK_RVB_IMM, match_opcode, INSN_ALIAS },
++{"unzip.n",  64, INSN_CLASS_B,   "d,s",  MATCH_UNSHFLI | MATCH_PERMN_SHFL_IMM (64), MASK_UNSHFLI | MASK_RVB_IMM, match_opcode, INSN_ALIAS },
++{"unzip2.b", 32, INSN_CLASS_B,   "d,s",  MATCH_UNSHFLI | MATCH_PERM2B_SHFL_IMM (32), MASK_UNSHFLI | MASK_RVB_IMM, match_opcode, INSN_ALIAS },
++{"unzip2.b", 64, INSN_CLASS_B,   "d,s",  MATCH_UNSHFLI | MATCH_PERM2B_SHFL_IMM (64), MASK_UNSHFLI | MASK_RVB_IMM, match_opcode, INSN_ALIAS },
++{"unzip.b",  32, INSN_CLASS_B,   "d,s",  MATCH_UNSHFLI | MATCH_PERMB_SHFL_IMM (32), MASK_UNSHFLI | MASK_RVB_IMM, match_opcode, INSN_ALIAS },
++{"unzip.b",  64, INSN_CLASS_B,   "d,s",  MATCH_UNSHFLI | MATCH_PERMB_SHFL_IMM (64), MASK_UNSHFLI | MASK_RVB_IMM, match_opcode, INSN_ALIAS },
++{"unzip4.h", 32, INSN_CLASS_B,   "d,s",  MATCH_UNSHFLI | MATCH_PERM4H_SHFL_IMM (32), MASK_UNSHFLI | MASK_RVB_IMM, match_opcode, INSN_ALIAS },
++{"unzip4.h", 64, INSN_CLASS_B,   "d,s",  MATCH_UNSHFLI | MATCH_PERM4H_SHFL_IMM (64), MASK_UNSHFLI | MASK_RVB_IMM, match_opcode, INSN_ALIAS },
++{"unzip2.h", 32, INSN_CLASS_B,   "d,s",  MATCH_UNSHFLI | MATCH_PERM2H_SHFL_IMM (32), MASK_UNSHFLI | MASK_RVB_IMM, match_opcode, INSN_ALIAS },
++{"unzip2.h", 64, INSN_CLASS_B,   "d,s",  MATCH_UNSHFLI | MATCH_PERM2H_SHFL_IMM (64), MASK_UNSHFLI | MASK_RVB_IMM, match_opcode, INSN_ALIAS },
++{"unzip.h",  32, INSN_CLASS_B,   "d,s",  MATCH_UNSHFLI | MATCH_PERMH_SHFL_IMM (32), MASK_UNSHFLI | MASK_RVB_IMM, match_opcode, INSN_ALIAS },
++{"unzip.h",  64, INSN_CLASS_B,   "d,s",  MATCH_UNSHFLI | MATCH_PERMH_SHFL_IMM (64), MASK_UNSHFLI | MASK_RVB_IMM, match_opcode, INSN_ALIAS },
++{"unzip8",   32, INSN_CLASS_B,   "d,s",  MATCH_UNSHFLI | MATCH_PERM8_SHFL_IMM (32), MASK_UNSHFLI | MASK_RVB_IMM, match_opcode, INSN_ALIAS },
++{"unzip8",   64, INSN_CLASS_B,   "d,s",  MATCH_UNSHFLI | MATCH_PERM8_SHFL_IMM (64), MASK_UNSHFLI | MASK_RVB_IMM, match_opcode, INSN_ALIAS },
++{"unzip4",   32, INSN_CLASS_B,   "d,s",  MATCH_UNSHFLI | MATCH_PERM4_SHFL_IMM (32), MASK_UNSHFLI | MASK_RVB_IMM, match_opcode, INSN_ALIAS },
++{"unzip4",   64, INSN_CLASS_B,   "d,s",  MATCH_UNSHFLI | MATCH_PERM4_SHFL_IMM (64), MASK_UNSHFLI | MASK_RVB_IMM, match_opcode, INSN_ALIAS },
++{"unzip2",   32, INSN_CLASS_B,   "d,s",  MATCH_UNSHFLI | MATCH_PERM2_SHFL_IMM (32), MASK_UNSHFLI | MASK_RVB_IMM, match_opcode, INSN_ALIAS },
++{"unzip2",   64, INSN_CLASS_B,   "d,s",  MATCH_UNSHFLI | MATCH_PERM2_SHFL_IMM (64), MASK_UNSHFLI | MASK_RVB_IMM, match_opcode, INSN_ALIAS },
++{"unzip",    32, INSN_CLASS_B,   "d,s",  MATCH_UNSHFLI | MATCH_PERM_SHFL_IMM (32), MASK_UNSHFLI | MASK_RVB_IMM, match_opcode, INSN_ALIAS },
++{"unzip",    64, INSN_CLASS_B,   "d,s",  MATCH_UNSHFLI | MATCH_PERM_SHFL_IMM (64), MASK_UNSHFLI | MASK_RVB_IMM, match_opcode, INSN_ALIAS },
++{"unzip8.w", 64, INSN_CLASS_B,   "d,s",  MATCH_UNSHFLI | MATCH_PERM8W_SHFL_IMM (64), MASK_UNSHFLI | MASK_RVB_IMM, match_opcode, INSN_ALIAS },
++{"unzip4.w", 64, INSN_CLASS_B,   "d,s",  MATCH_UNSHFLI | MATCH_PERM4W_SHFL_IMM (64), MASK_UNSHFLI | MASK_RVB_IMM, match_opcode, INSN_ALIAS },
++{"unzip2.w", 64, INSN_CLASS_B,   "d,s",  MATCH_UNSHFLI | MATCH_PERM2W_SHFL_IMM (64), MASK_UNSHFLI | MASK_RVB_IMM, match_opcode, INSN_ALIAS },
++{"unzip.w",  64, INSN_CLASS_B,   "d,s",  MATCH_UNSHFLI | MATCH_PERMW_SHFL_IMM (64), MASK_UNSHFLI | MASK_RVB_IMM, match_opcode, INSN_ALIAS },
++{"unzip16",  64, INSN_CLASS_B,   "d,s",  MATCH_UNSHFLI | MATCH_PERM16_SHFL_IMM (64), MASK_UNSHFLI | MASK_RVB_IMM, match_opcode, INSN_ALIAS },
++
+ /* Bitmanip instruction subset - for sure  */
+ {"sh1add",    0, INSN_CLASS_B_OR_ZBA,   "d,s,t",  MATCH_SH1ADD, MASK_SH1ADD, match_opcode, 0 },
+ {"sh2add",    0, INSN_CLASS_B_OR_ZBA,   "d,s,t",  MATCH_SH2ADD, MASK_SH2ADD, match_opcode, 0 },
+@@ -1024,8 +1196,6 @@ const struct riscv_opcode riscv_opcodes[] =
+ {"roriw",    64, INSN_CLASS_B_OR_ZBB,   "d,s,<",  MATCH_RORIW, MASK_RORIW, match_opcode, 0 },
+ {"rorw",     64, INSN_CLASS_B_OR_ZBB,   "d,s,t",  MATCH_RORW, MASK_RORW, match_opcode, 0 },
+ {"rorw",     64, INSN_CLASS_B_OR_ZBB,   "d,s,<",  MATCH_RORIW, MASK_RORIW, match_opcode, INSN_ALIAS },
+-{"rev8",      0, INSN_CLASS_B_OR_ZBB,   "d,s",  0, (int) M_PERM, match_never, INSN_MACRO },
+-{"orc.b",     0, INSN_CLASS_B_OR_ZBB,   "d,s",  0, (int) M_PERM, match_never, INSN_MACRO },
+ 
+ {"clmul",     0, INSN_CLASS_B_OR_ZBC,   "d,s,t",  MATCH_CLMUL, MASK_CLMUL, match_opcode, 0 },
+ {"clmulh",    0, INSN_CLASS_B_OR_ZBC,   "d,s,t",  MATCH_CLMULH, MASK_CLMULH, match_opcode, 0 },
+@@ -1131,81 +1301,6 @@ const struct riscv_opcode riscv_opcodes[] =
+ {"crc32.d",  64, INSN_CLASS_ZBR,   "d,s",  MATCH_CRC32_D, MASK_CRC32_D, match_opcode, 0 },
+ {"crc32c.d", 64, INSN_CLASS_ZBR,   "d,s",  MATCH_CRC32C_D, MASK_CRC32C_D, match_opcode, 0 },
+ 
+-/* Bitmanip pseudo-instructions  */
+-{"rev.p",     0, INSN_CLASS_B,   "d,s",  0, (int) M_PERM, match_never, INSN_MACRO },
+-{"rev2.n",    0, INSN_CLASS_B,   "d,s",  0, (int) M_PERM, match_never, INSN_MACRO },
+-{"rev.n",     0, INSN_CLASS_B,   "d,s",  0, (int) M_PERM, match_never, INSN_MACRO },
+-{"rev4.b",    0, INSN_CLASS_B,   "d,s",  0, (int) M_PERM, match_never, INSN_MACRO },
+-{"rev2.b",    0, INSN_CLASS_B,   "d,s",  0, (int) M_PERM, match_never, INSN_MACRO },
+-{"rev.b",     0, INSN_CLASS_B,   "d,s",  0, (int) M_PERM, match_never, INSN_MACRO },
+-{"rev8.h",    0, INSN_CLASS_B,   "d,s",  0, (int) M_PERM, match_never, INSN_MACRO },
+-{"rev4.h",    0, INSN_CLASS_B,   "d,s",  0, (int) M_PERM, match_never, INSN_MACRO },
+-{"rev2.h",    0, INSN_CLASS_B,   "d,s",  0, (int) M_PERM, match_never, INSN_MACRO },
+-{"rev.h",     0, INSN_CLASS_B,   "d,s",  0, (int) M_PERM, match_never, INSN_MACRO },
+-{"rev16.w",  64, INSN_CLASS_B,   "d,s",  0, (int) M_PERM, match_never, INSN_MACRO },
+-{"rev8.w",   64, INSN_CLASS_B,   "d,s",  0, (int) M_PERM, match_never, INSN_MACRO },
+-{"rev4.w",   64, INSN_CLASS_B,   "d,s",  0, (int) M_PERM, match_never, INSN_MACRO },
+-{"rev2.w",   64, INSN_CLASS_B,   "d,s",  0, (int) M_PERM, match_never, INSN_MACRO },
+-{"rev.w",    64, INSN_CLASS_B,   "d,s",  0, (int) M_PERM, match_never, INSN_MACRO },
+-{"rev32",    64, INSN_CLASS_B,   "d,s",  0, (int) M_PERM, match_never, INSN_MACRO },
+-{"rev16",     0, INSN_CLASS_B,   "d,s",  0, (int) M_PERM, match_never, INSN_MACRO },
+-{"rev4",      0, INSN_CLASS_B,   "d,s",  0, (int) M_PERM, match_never, INSN_MACRO },
+-{"rev2",      0, INSN_CLASS_B,   "d,s",  0, (int) M_PERM, match_never, INSN_MACRO },
+-{"rev",       0, INSN_CLASS_B,   "d,s",  0, (int) M_PERM, match_never, INSN_MACRO },
+-
+-{"orc.p",     0, INSN_CLASS_B,   "d,s",  0, (int) M_PERM, match_never, INSN_MACRO },
+-{"orc2.n",    0, INSN_CLASS_B,   "d,s",  0, (int) M_PERM, match_never, INSN_MACRO },
+-{"orc.n",     0, INSN_CLASS_B,   "d,s",  0, (int) M_PERM, match_never, INSN_MACRO },
+-{"orc4.b",    0, INSN_CLASS_B,   "d,s",  0, (int) M_PERM, match_never, INSN_MACRO },
+-{"orc2.b",    0, INSN_CLASS_B,   "d,s",  0, (int) M_PERM, match_never, INSN_MACRO },
+-{"orc8.h",    0, INSN_CLASS_B,   "d,s",  0, (int) M_PERM, match_never, INSN_MACRO },
+-{"orc4.h",    0, INSN_CLASS_B,   "d,s",  0, (int) M_PERM, match_never, INSN_MACRO },
+-{"orc2.h",    0, INSN_CLASS_B,   "d,s",  0, (int) M_PERM, match_never, INSN_MACRO },
+-{"orc.h",     0, INSN_CLASS_B,   "d,s",  0, (int) M_PERM, match_never, INSN_MACRO },
+-{"orc16.w",  64, INSN_CLASS_B,   "d,s",  0, (int) M_PERM, match_never, INSN_MACRO },
+-{"orc8.w",   64, INSN_CLASS_B,   "d,s",  0, (int) M_PERM, match_never, INSN_MACRO },
+-{"orc4.w",   64, INSN_CLASS_B,   "d,s",  0, (int) M_PERM, match_never, INSN_MACRO },
+-{"orc2.w",   64, INSN_CLASS_B,   "d,s",  0, (int) M_PERM, match_never, INSN_MACRO },
+-{"orc.w",    64, INSN_CLASS_B,   "d,s",  0, (int) M_PERM, match_never, INSN_MACRO },
+-{"orc32",    64, INSN_CLASS_B,   "d,s",  0, (int) M_PERM, match_never, INSN_MACRO },
+-{"orc16",     0, INSN_CLASS_B,   "d,s",  0, (int) M_PERM, match_never, INSN_MACRO },
+-{"orc8",      0, INSN_CLASS_B,   "d,s",  0, (int) M_PERM, match_never, INSN_MACRO },
+-{"orc4",      0, INSN_CLASS_B,   "d,s",  0, (int) M_PERM, match_never, INSN_MACRO },
+-{"orc2",      0, INSN_CLASS_B,   "d,s",  0, (int) M_PERM, match_never, INSN_MACRO },
+-{"orc",       0, INSN_CLASS_B,   "d,s",  0, (int) M_PERM, match_never, INSN_MACRO },
+-
+-{"zip.n",     0, INSN_CLASS_B,   "d,s",  0, (int) M_PERM, match_never, INSN_MACRO },
+-{"zip2.b",    0, INSN_CLASS_B,   "d,s",  0, (int) M_PERM, match_never, INSN_MACRO },
+-{"zip.b",     0, INSN_CLASS_B,   "d,s",  0, (int) M_PERM, match_never, INSN_MACRO },
+-{"zip4.h",    0, INSN_CLASS_B,   "d,s",  0, (int) M_PERM, match_never, INSN_MACRO },
+-{"zip2.h",    0, INSN_CLASS_B,   "d,s",  0, (int) M_PERM, match_never, INSN_MACRO },
+-{"zip.h",     0, INSN_CLASS_B,   "d,s",  0, (int) M_PERM, match_never, INSN_MACRO },
+-{"zip8.w",   64, INSN_CLASS_B,   "d,s",  0, (int) M_PERM, match_never, INSN_MACRO },
+-{"zip4.w",   64, INSN_CLASS_B,   "d,s",  0, (int) M_PERM, match_never, INSN_MACRO },
+-{"zip2.w",   64, INSN_CLASS_B,   "d,s",  0, (int) M_PERM, match_never, INSN_MACRO },
+-{"zip.w",    64, INSN_CLASS_B,   "d,s",  0, (int) M_PERM, match_never, INSN_MACRO },
+-{"zip16",    64, INSN_CLASS_B,   "d,s",  0, (int) M_PERM, match_never, INSN_MACRO },
+-{"zip8",      0, INSN_CLASS_B,   "d,s",  0, (int) M_PERM, match_never, INSN_MACRO },
+-{"zip4",      0, INSN_CLASS_B,   "d,s",  0, (int) M_PERM, match_never, INSN_MACRO },
+-{"zip2",      0, INSN_CLASS_B,   "d,s",  0, (int) M_PERM, match_never, INSN_MACRO },
+-{"zip",       0, INSN_CLASS_B,   "d,s",  0, (int) M_PERM, match_never, INSN_MACRO },
+-
+-{"unzip.n",   0, INSN_CLASS_B,   "d,s",  0, (int) M_PERM, match_never, INSN_MACRO },
+-{"unzip2.b",  0, INSN_CLASS_B,   "d,s",  0, (int) M_PERM, match_never, INSN_MACRO },
+-{"unzip.b",   0, INSN_CLASS_B,   "d,s",  0, (int) M_PERM, match_never, INSN_MACRO },
+-{"unzip4.h",  0, INSN_CLASS_B,   "d,s",  0, (int) M_PERM, match_never, INSN_MACRO },
+-{"unzip2.h",  0, INSN_CLASS_B,   "d,s",  0, (int) M_PERM, match_never, INSN_MACRO },
+-{"unzip.h",   0, INSN_CLASS_B,   "d,s",  0, (int) M_PERM, match_never, INSN_MACRO },
+-{"unzip8.w", 64, INSN_CLASS_B,   "d,s",  0, (int) M_PERM, match_never, INSN_MACRO },
+-{"unzip4.w", 64, INSN_CLASS_B,   "d,s",  0, (int) M_PERM, match_never, INSN_MACRO },
+-{"unzip2.w", 64, INSN_CLASS_B,   "d,s",  0, (int) M_PERM, match_never, INSN_MACRO },
+-{"unzip.w",  64, INSN_CLASS_B,   "d,s",  0, (int) M_PERM, match_never, INSN_MACRO },
+-{"unzip16",  64, INSN_CLASS_B,   "d,s",  0, (int) M_PERM, match_never, INSN_MACRO },
+-{"unzip8",    0, INSN_CLASS_B,   "d,s",  0, (int) M_PERM, match_never, INSN_MACRO },
+-{"unzip4",    0, INSN_CLASS_B,   "d,s",  0, (int) M_PERM, match_never, INSN_MACRO },
+-{"unzip2",    0, INSN_CLASS_B,   "d,s",  0, (int) M_PERM, match_never, INSN_MACRO },
+-{"unzip",     0, INSN_CLASS_B,   "d,s",  0, (int) M_PERM, match_never, INSN_MACRO },
+-
+ /* Single-precision floating-point instruction subset */
+ {"frcsr",     0, INSN_CLASS_F,   "d",  MATCH_FRCSR, MASK_FRCSR, match_opcode, INSN_ALIAS },
+ {"frsr",      0, INSN_CLASS_F,   "d",  MATCH_FRCSR, MASK_FRCSR, match_opcode, INSN_ALIAS },
+-- 
+2.33.0
+

+ 383 - 0
recipes-devtools/gdb/files/0043-RISC-V-Add-testcases-for-ZBA-and-ZBB-instructions.patch

@@ -0,0 +1,383 @@
+From 3acfa79228946abd469562071baeb79720222229 Mon Sep 17 00:00:00 2001
+From: Nelson Chu <nelson.chu@sifive.com>
+Date: Mon, 14 Dec 2020 14:04:59 +0800
+Subject: [PATCH 43/48] RISC-V: Add testcases for ZBA and ZBB instructions.
+
+---
+ gas/testsuite/gas/riscv/bitmanip-insns-32.d   | 35 +++++++++++
+ gas/testsuite/gas/riscv/bitmanip-insns-64.d   | 58 +++++++++++++++++++
+ .../gas/riscv/bitmanip-insns-pseudo-32.d      |  1 +
+ .../gas/riscv/bitmanip-insns-pseudo-64.d      |  2 +
+ .../riscv/bitmanip-insns-pseudo-noalias-32.d  |  1 +
+ .../riscv/bitmanip-insns-pseudo-noalias-64.d  |  2 +
+ .../gas/riscv/bitmanip-insns-pseudo.s         |  8 ++-
+ gas/testsuite/gas/riscv/bitmanip-insns.s      | 57 ++++++++++++++++++
+ gas/testsuite/gas/riscv/zext-32.d             | 11 ----
+ gas/testsuite/gas/riscv/zext-64.d             | 12 ----
+ gas/testsuite/gas/riscv/zext-noalias-32.d     | 11 ----
+ gas/testsuite/gas/riscv/zext-noalias-64.d     | 12 ----
+ gas/testsuite/gas/riscv/zext.s                |  6 --
+ 13 files changed, 162 insertions(+), 54 deletions(-)
+ create mode 100644 gas/testsuite/gas/riscv/bitmanip-insns-32.d
+ create mode 100644 gas/testsuite/gas/riscv/bitmanip-insns-64.d
+ create mode 100644 gas/testsuite/gas/riscv/bitmanip-insns.s
+ delete mode 100644 gas/testsuite/gas/riscv/zext-32.d
+ delete mode 100644 gas/testsuite/gas/riscv/zext-64.d
+ delete mode 100644 gas/testsuite/gas/riscv/zext-noalias-32.d
+ delete mode 100644 gas/testsuite/gas/riscv/zext-noalias-64.d
+ delete mode 100644 gas/testsuite/gas/riscv/zext.s
+
+diff --git a/gas/testsuite/gas/riscv/bitmanip-insns-32.d b/gas/testsuite/gas/riscv/bitmanip-insns-32.d
+new file mode 100644
+index 0000000000..bda9d603af
+--- /dev/null
++++ b/gas/testsuite/gas/riscv/bitmanip-insns-32.d
+@@ -0,0 +1,35 @@
++#as: -march=rv32i_zba_zbb
++#source: bitmanip-insns.s
++#objdump: -dr
++
++.*:[ 	]+file format .*
++
++
++Disassembly of section .text:
++
++0+000 <.text>:
++[ 	]+[0-9a-f]+:[ 	]+20c5a533[ 	]+sh1add[ 	]+a0,a1,a2
++[ 	]+[0-9a-f]+:[ 	]+20c5c533[ 	]+sh2add[ 	]+a0,a1,a2
++[ 	]+[0-9a-f]+:[ 	]+20c5e533[ 	]+sh3add[ 	]+a0,a1,a2
++[ 	]+[0-9a-f]+:[ 	]+60059513[ 	]+clz[ 	]+a0,a1
++[ 	]+[0-9a-f]+:[ 	]+60159513[ 	]+ctz[ 	]+a0,a1
++[ 	]+[0-9a-f]+:[ 	]+60259513[ 	]+pcnt[ 	]+a0,a1
++[ 	]+[0-9a-f]+:[ 	]+0ac5c533[ 	]+min[ 	]+a0,a1,a2
++[ 	]+[0-9a-f]+:[ 	]+0ac5e533[ 	]+max[ 	]+a0,a1,a2
++[ 	]+[0-9a-f]+:[ 	]+0ac5d533[ 	]+minu[ 	]+a0,a1,a2
++[ 	]+[0-9a-f]+:[ 	]+0ac5f533[ 	]+maxu[ 	]+a0,a1,a2
++[ 	]+[0-9a-f]+:[ 	]+40c5f533[ 	]+andn[ 	]+a0,a1,a2
++[ 	]+[0-9a-f]+:[ 	]+40c5e533[ 	]+orn[ 	]+a0,a1,a2
++[ 	]+[0-9a-f]+:[ 	]+00c5c533[ 	]+xor[ 	]+a0,a1,a2
++[ 	]+[0-9a-f]+:[ 	]+61f5d513[ 	]+rori[ 	]+a0,a1,0x1f
++[ 	]+[0-9a-f]+:[ 	]+6015d513[ 	]+rori[ 	]+a0,a1,0x1
++[ 	]+[0-9a-f]+:[ 	]+60c59533[ 	]+rol[ 	]+a0,a1,a2
++[ 	]+[0-9a-f]+:[ 	]+61f5d513[ 	]+rori[ 	]+a0,a1,0x1f
++[ 	]+[0-9a-f]+:[ 	]+6015d513[ 	]+rori[ 	]+a0,a1,0x1
++[ 	]+[0-9a-f]+:[ 	]+6015d513[ 	]+rori[ 	]+a0,a1,0x1
++[ 	]+[0-9a-f]+:[ 	]+61f5d513[ 	]+rori[ 	]+a0,a1,0x1f
++[ 	]+[0-9a-f]+:[ 	]+60c5d533[ 	]+ror[ 	]+a0,a1,a2
++[ 	]+[0-9a-f]+:[ 	]+6015d513[ 	]+rori[ 	]+a0,a1,0x1
++[ 	]+[0-9a-f]+:[ 	]+61f5d513[ 	]+rori[ 	]+a0,a1,0x1f
++[ 	]+[0-9a-f]+:[ 	]+60459513[ 	]+sext.b[ 	]+a0,a1
++[ 	]+[0-9a-f]+:[ 	]+60559513[ 	]+sext.h[ 	]+a0,a1
+diff --git a/gas/testsuite/gas/riscv/bitmanip-insns-64.d b/gas/testsuite/gas/riscv/bitmanip-insns-64.d
+new file mode 100644
+index 0000000000..843bb319be
+--- /dev/null
++++ b/gas/testsuite/gas/riscv/bitmanip-insns-64.d
+@@ -0,0 +1,58 @@
++#as: -march=rv64i_zba_zbb -defsym __64_bit__=1
++#source: bitmanip-insns.s
++#objdump: -dr
++
++.*:[ 	]+file format .*
++
++
++Disassembly of section .text:
++
++0+000 <.text>:
++[ 	]+[0-9a-f]+:[ 	]+20c5a533[ 	]+sh1add[ 	]+a0,a1,a2
++[ 	]+[0-9a-f]+:[ 	]+20c5c533[ 	]+sh2add[ 	]+a0,a1,a2
++[ 	]+[0-9a-f]+:[ 	]+20c5e533[ 	]+sh3add[ 	]+a0,a1,a2
++[ 	]+[0-9a-f]+:[ 	]+0815951b[ 	]+slliu.w[ 	]+a0,a1,0x1
++[ 	]+[0-9a-f]+:[ 	]+0bf5951b[ 	]+slliu.w[ 	]+a0,a1,0x3f
++[ 	]+[0-9a-f]+:[ 	]+08c5853b[ 	]+addu.w[ 	]+a0,a1,a2
++[ 	]+[0-9a-f]+:[ 	]+20c5a53b[ 	]+sh1addu.w[ 	]+a0,a1,a2
++[ 	]+[0-9a-f]+:[ 	]+20c5c53b[ 	]+sh2addu.w[ 	]+a0,a1,a2
++[ 	]+[0-9a-f]+:[ 	]+20c5e53b[ 	]+sh3addu.w[ 	]+a0,a1,a2
++[ 	]+[0-9a-f]+:[ 	]+60059513[ 	]+clz[ 	]+a0,a1
++[ 	]+[0-9a-f]+:[ 	]+60159513[ 	]+ctz[ 	]+a0,a1
++[ 	]+[0-9a-f]+:[ 	]+60259513[ 	]+pcnt[ 	]+a0,a1
++[ 	]+[0-9a-f]+:[ 	]+0ac5c533[ 	]+min[ 	]+a0,a1,a2
++[ 	]+[0-9a-f]+:[ 	]+0ac5e533[ 	]+max[ 	]+a0,a1,a2
++[ 	]+[0-9a-f]+:[ 	]+0ac5d533[ 	]+minu[ 	]+a0,a1,a2
++[ 	]+[0-9a-f]+:[ 	]+0ac5f533[ 	]+maxu[ 	]+a0,a1,a2
++[ 	]+[0-9a-f]+:[ 	]+40c5f533[ 	]+andn[ 	]+a0,a1,a2
++[ 	]+[0-9a-f]+:[ 	]+40c5e533[ 	]+orn[ 	]+a0,a1,a2
++[ 	]+[0-9a-f]+:[ 	]+00c5c533[ 	]+xor[ 	]+a0,a1,a2
++[ 	]+[0-9a-f]+:[ 	]+63f5d513[ 	]+rori[ 	]+a0,a1,0x3f
++[ 	]+[0-9a-f]+:[ 	]+6215d513[ 	]+rori[ 	]+a0,a1,0x21
++[ 	]+[0-9a-f]+:[ 	]+60c59533[ 	]+rol[ 	]+a0,a1,a2
++[ 	]+[0-9a-f]+:[ 	]+63f5d513[ 	]+rori[ 	]+a0,a1,0x3f
++[ 	]+[0-9a-f]+:[ 	]+6215d513[ 	]+rori[ 	]+a0,a1,0x21
++[ 	]+[0-9a-f]+:[ 	]+6015d513[ 	]+rori[ 	]+a0,a1,0x1
++[ 	]+[0-9a-f]+:[ 	]+61f5d513[ 	]+rori[ 	]+a0,a1,0x1f
++[ 	]+[0-9a-f]+:[ 	]+60c5d533[ 	]+ror[ 	]+a0,a1,a2
++[ 	]+[0-9a-f]+:[ 	]+6015d513[ 	]+rori[ 	]+a0,a1,0x1
++[ 	]+[0-9a-f]+:[ 	]+61f5d513[ 	]+rori[ 	]+a0,a1,0x1f
++[ 	]+[0-9a-f]+:[ 	]+60459513[ 	]+sext.b[ 	]+a0,a1
++[ 	]+[0-9a-f]+:[ 	]+60559513[ 	]+sext.h[ 	]+a0,a1
++[ 	]+[0-9a-f]+:[ 	]+6005951b[ 	]+clzw[ 	]+a0,a1
++[ 	]+[0-9a-f]+:[ 	]+6015951b[ 	]+ctzw[ 	]+a0,a1
++[ 	]+[0-9a-f]+:[ 	]+6025951b[ 	]+pcntw[ 	]+a0,a1
++[ 	]+[0-9a-f]+:[ 	]+6015d513[ 	]+rori[ 	]+a0,a1,0x1
++[ 	]+[0-9a-f]+:[ 	]+6015d513[ 	]+rori[ 	]+a0,a1,0x1
++[ 	]+[0-9a-f]+:[ 	]+63f5d513[ 	]+rori[ 	]+a0,a1,0x3f
++[ 	]+[0-9a-f]+:[ 	]+63f5d513[ 	]+rori[ 	]+a0,a1,0x3f
++[ 	]+[0-9a-f]+:[ 	]+61f5d51b[ 	]+roriw[ 	]+a0,a1,0x1f
++[ 	]+[0-9a-f]+:[ 	]+6015d51b[ 	]+roriw[ 	]+a0,a1,0x1
++[ 	]+[0-9a-f]+:[ 	]+6015d51b[ 	]+roriw[ 	]+a0,a1,0x1
++[ 	]+[0-9a-f]+:[ 	]+61f5d51b[ 	]+roriw[ 	]+a0,a1,0x1f
++[ 	]+[0-9a-f]+:[ 	]+60c5953b[ 	]+rolw[ 	]+a0,a1,a2
++[ 	]+[0-9a-f]+:[ 	]+61f5d51b[ 	]+roriw[ 	]+a0,a1,0x1f
++[ 	]+[0-9a-f]+:[ 	]+6015d51b[ 	]+roriw[ 	]+a0,a1,0x1
++[ 	]+[0-9a-f]+:[ 	]+60c5d53b[ 	]+rorw[ 	]+a0,a1,a2
++[ 	]+[0-9a-f]+:[ 	]+6015d51b[ 	]+roriw[ 	]+a0,a1,0x1
++[ 	]+[0-9a-f]+:[ 	]+61f5d51b[ 	]+roriw[ 	]+a0,a1,0x1f
+diff --git a/gas/testsuite/gas/riscv/bitmanip-insns-pseudo-32.d b/gas/testsuite/gas/riscv/bitmanip-insns-pseudo-32.d
+index 2f24a19efc..b0cdb16efc 100644
+--- a/gas/testsuite/gas/riscv/bitmanip-insns-pseudo-32.d
++++ b/gas/testsuite/gas/riscv/bitmanip-insns-pseudo-32.d
+@@ -8,6 +8,7 @@
+ Disassembly of section .text:
+ 
+ 0+000 <.text>:
++[ 	]+[0-9a-f]+:[ 	]+0805c533[ 	]+zext.h[ 	]+a0,a1
+ [ 	]+[0-9a-f]+:[ 	]+6815d513[ 	]+rev.p[ 	]+a0,a1
+ [ 	]+[0-9a-f]+:[ 	]+6825d513[ 	]+rev2.n[ 	]+a0,a1
+ [ 	]+[0-9a-f]+:[ 	]+6835d513[ 	]+rev.n[ 	]+a0,a1
+diff --git a/gas/testsuite/gas/riscv/bitmanip-insns-pseudo-64.d b/gas/testsuite/gas/riscv/bitmanip-insns-pseudo-64.d
+index 6c27edac80..23b8b7b5a6 100644
+--- a/gas/testsuite/gas/riscv/bitmanip-insns-pseudo-64.d
++++ b/gas/testsuite/gas/riscv/bitmanip-insns-pseudo-64.d
+@@ -8,6 +8,7 @@
+ Disassembly of section .text:
+ 
+ 0+000 <.text>:
++[ 	]+[0-9a-f]+:[ 	]+0805c53b[ 	]+zext.h[ 	]+a0,a1
+ [ 	]+[0-9a-f]+:[ 	]+6815d513[ 	]+rev.p[ 	]+a0,a1
+ [ 	]+[0-9a-f]+:[ 	]+6825d513[ 	]+rev2.n[ 	]+a0,a1
+ [ 	]+[0-9a-f]+:[ 	]+6835d513[ 	]+rev.n[ 	]+a0,a1
+@@ -58,6 +59,7 @@ Disassembly of section .text:
+ [ 	]+[0-9a-f]+:[ 	]+09c5d513[ 	]+unzip4[ 	]+a0,a1
+ [ 	]+[0-9a-f]+:[ 	]+09e5d513[ 	]+unzip2[ 	]+a0,a1
+ [ 	]+[0-9a-f]+:[ 	]+09f5d513[ 	]+unzip[ 	]+a0,a1
++[ 	]+[0-9a-f]+:[ 	]+0805853b[ 	]+zext.w[ 	]+a0,a1
+ [ 	]+[0-9a-f]+:[ 	]+6905d513[ 	]+rev16.w[ 	]+a0,a1
+ [ 	]+[0-9a-f]+:[ 	]+6985d513[ 	]+rev8.w[ 	]+a0,a1
+ [ 	]+[0-9a-f]+:[ 	]+69c5d513[ 	]+rev4.w[ 	]+a0,a1
+diff --git a/gas/testsuite/gas/riscv/bitmanip-insns-pseudo-noalias-32.d b/gas/testsuite/gas/riscv/bitmanip-insns-pseudo-noalias-32.d
+index c2dde4cfaa..91190c8b6a 100644
+--- a/gas/testsuite/gas/riscv/bitmanip-insns-pseudo-noalias-32.d
++++ b/gas/testsuite/gas/riscv/bitmanip-insns-pseudo-noalias-32.d
+@@ -8,6 +8,7 @@
+ Disassembly of section .text:
+ 
+ 0+000 <.text>:
++[ 	]+[0-9a-f]+:[ 	]+0805c533[ 	]+pack[ 	]+a0,a1,zero
+ [ 	]+[0-9a-f]+:[ 	]+6815d513[ 	]+grevi[ 	]+a0,a1,0x1
+ [ 	]+[0-9a-f]+:[ 	]+6825d513[ 	]+grevi[ 	]+a0,a1,0x2
+ [ 	]+[0-9a-f]+:[ 	]+6835d513[ 	]+grevi[ 	]+a0,a1,0x3
+diff --git a/gas/testsuite/gas/riscv/bitmanip-insns-pseudo-noalias-64.d b/gas/testsuite/gas/riscv/bitmanip-insns-pseudo-noalias-64.d
+index abdbbcaed5..187c487e7c 100644
+--- a/gas/testsuite/gas/riscv/bitmanip-insns-pseudo-noalias-64.d
++++ b/gas/testsuite/gas/riscv/bitmanip-insns-pseudo-noalias-64.d
+@@ -8,6 +8,7 @@
+ Disassembly of section .text:
+ 
+ 0+000 <.text>:
++[ 	]+[0-9a-f]+:[ 	]+0805c53b[ 	]+packw[ 	]+a0,a1,zero
+ [ 	]+[0-9a-f]+:[ 	]+6815d513[ 	]+grevi[ 	]+a0,a1,0x1
+ [ 	]+[0-9a-f]+:[ 	]+6825d513[ 	]+grevi[ 	]+a0,a1,0x2
+ [ 	]+[0-9a-f]+:[ 	]+6835d513[ 	]+grevi[ 	]+a0,a1,0x3
+@@ -58,6 +59,7 @@ Disassembly of section .text:
+ [ 	]+[0-9a-f]+:[ 	]+09c5d513[ 	]+unshfli[ 	]+a0,a1,0x1c
+ [ 	]+[0-9a-f]+:[ 	]+09e5d513[ 	]+unshfli[ 	]+a0,a1,0x1e
+ [ 	]+[0-9a-f]+:[ 	]+09f5d513[ 	]+unshfli[ 	]+a0,a1,0x1f
++[ 	]+[0-9a-f]+:[ 	]+0805853b[ 	]+addu.w[ 	]+a0,a1,zero
+ [ 	]+[0-9a-f]+:[ 	]+6905d513[ 	]+grevi[ 	]+a0,a1,0x10
+ [ 	]+[0-9a-f]+:[ 	]+6985d513[ 	]+grevi[ 	]+a0,a1,0x18
+ [ 	]+[0-9a-f]+:[ 	]+69c5d513[ 	]+grevi[ 	]+a0,a1,0x1c
+diff --git a/gas/testsuite/gas/riscv/bitmanip-insns-pseudo.s b/gas/testsuite/gas/riscv/bitmanip-insns-pseudo.s
+index 37adb96a77..5dcebc0619 100644
+--- a/gas/testsuite/gas/riscv/bitmanip-insns-pseudo.s
++++ b/gas/testsuite/gas/riscv/bitmanip-insns-pseudo.s
+@@ -1,3 +1,5 @@
++	zext.h	a0, a1	/* ZBB  */
++
+ 	rev.p	a0, a1
+ 	rev2.n	a0, a1
+ 	rev.n	a0, a1
+@@ -9,7 +11,7 @@
+ 	rev2.h	a0, a1
+ 	rev.h	a0, a1
+ 	rev16	a0, a1
+-	rev8	a0, a1
++	rev8	a0, a1	/* ZBB  */
+ 	rev4	a0, a1
+ 	rev2	a0, a1
+ 	rev	a0, a1
+@@ -19,7 +21,7 @@
+ 	orc.n	a0, a1
+ 	orc4.b	a0, a1
+ 	orc2.b	a0, a1
+-	orc.b	a0, a1
++	orc.b	a0, a1	/* ZBB  */
+ 	orc8.h	a0, a1
+ 	orc4.h	a0, a1
+ 	orc2.h	a0, a1
+@@ -53,6 +55,8 @@
+ 	unzip		a0, a1
+ 
+ .ifdef __64_bit__
++	zext.w	a0, a1	/* ZBA or ZBB  */
++
+ 	rev16.w	a0, a1
+ 	rev8.w	a0, a1
+ 	rev4.w	a0, a1
+diff --git a/gas/testsuite/gas/riscv/bitmanip-insns.s b/gas/testsuite/gas/riscv/bitmanip-insns.s
+new file mode 100644
+index 0000000000..52e4b3afff
+--- /dev/null
++++ b/gas/testsuite/gas/riscv/bitmanip-insns.s
+@@ -0,0 +1,57 @@
++	# ZBA
++	sh1add	a0, a1, a2
++	sh2add	a0, a1, a2
++	sh3add	a0, a1, a2
++
++.ifdef __64_bit__
++	slliu.w		a0, a1, 1
++	slliu.w		a0, a1, 63
++	addu.w		a0, a1, a2
++	sh1addu.w	a0, a1, a2
++	sh2addu.w	a0, a1, a2
++	sh3addu.w	a0, a1, a2
++.endif
++
++	# ZBB
++	clz	a0, a1
++	ctz	a0, a1
++	pcnt	a0, a1
++	min	a0, a1, a2
++	max	a0, a1, a2
++	minu	a0, a1, a2
++	maxu	a0, a1, a2
++	andn	a0, a1, a2
++	orn	a0, a1, a2
++	xor	a0, a1, a2
++	roli	a0, a1, 1
++	roli	a0, a1, 31
++	rol	a0, a1, a2
++	rol	a0, a1, 1
++	rol	a0, a1, 31
++	rori	a0, a1, 1
++	rori	a0, a1, 31
++	ror	a0, a1, a2
++	ror	a0, a1, 1
++	ror	a0, a1, 31
++	sext.b	a0, a1
++	sext.h	a0, a1
++
++.ifdef __64_bit__
++	clzw	a0, a1
++	ctzw	a0, a1
++	pcntw	a0, a1
++	roli	a0, a1, 63
++	rol	a0, a1, 63
++	rori	a0, a1, 63
++	ror	a0, a1, 63
++	roliw	a0, a1, 1
++	roliw	a0, a1, 31
++	roriw	a0, a1, 1
++	roriw	a0, a1, 31
++	rolw	a0, a1, a2
++	rolw	a0, a1, 1
++	rolw	a0, a1, 31
++	rorw	a0, a1, a2
++	rorw	a0, a1, 1
++	rorw	a0, a1, 31
++.endif
+diff --git a/gas/testsuite/gas/riscv/zext-32.d b/gas/testsuite/gas/riscv/zext-32.d
+deleted file mode 100644
+index 9111177941..0000000000
+--- a/gas/testsuite/gas/riscv/zext-32.d
++++ /dev/null
+@@ -1,11 +0,0 @@
+-#as: -march=rv32ib
+-#source: zext.s
+-#objdump: -d
+-
+-.*:[ 	]+file format .*
+-
+-
+-Disassembly of section .text:
+-
+-0+000 <target>:
+-[ 	]+0:[ 	]+0805c533[ 	]+zext.h[ 	]+a0,a1
+diff --git a/gas/testsuite/gas/riscv/zext-64.d b/gas/testsuite/gas/riscv/zext-64.d
+deleted file mode 100644
+index 3b0955a00f..0000000000
+--- a/gas/testsuite/gas/riscv/zext-64.d
++++ /dev/null
+@@ -1,12 +0,0 @@
+-#as: -march=rv64ib -defsym __64_bit__=1
+-#source: zext.s
+-#objdump: -d
+-
+-.*:[ 	]+file format .*
+-
+-
+-Disassembly of section .text:
+-
+-0+000 <target>:
+-[ 	]+0:[ 	]+0805c53b[ 	]+zext.h[ 	]+a0,a1
+-[ 	]+4:[ 	]+0805853b[ 	]+zext.w[ 	]+a0,a1
+diff --git a/gas/testsuite/gas/riscv/zext-noalias-32.d b/gas/testsuite/gas/riscv/zext-noalias-32.d
+deleted file mode 100644
+index bdecbc2fc2..0000000000
+--- a/gas/testsuite/gas/riscv/zext-noalias-32.d
++++ /dev/null
+@@ -1,11 +0,0 @@
+-#as: -march=rv32ib
+-#source: zext.s
+-#objdump: -d -Mno-aliases
+-
+-.*:[ 	]+file format .*
+-
+-
+-Disassembly of section .text:
+-
+-0+000 <target>:
+-[ 	]+0:[ 	]+0805c533[ 	]+pack[ 	]+a0,a1,zero
+diff --git a/gas/testsuite/gas/riscv/zext-noalias-64.d b/gas/testsuite/gas/riscv/zext-noalias-64.d
+deleted file mode 100644
+index 8dfd77bf43..0000000000
+--- a/gas/testsuite/gas/riscv/zext-noalias-64.d
++++ /dev/null
+@@ -1,12 +0,0 @@
+-#as: -march=rv64ib -defsym __64_bit__=1
+-#source: zext.s
+-#objdump: -d -Mno-aliases
+-
+-.*:[ 	]+file format .*
+-
+-
+-Disassembly of section .text:
+-
+-0+000 <target>:
+-[ 	]+0:[ 	]+0805c53b[ 	]+packw[ 	]+a0,a1,zero
+-[ 	]+4:[ 	]+0805853b[ 	]+addu.w[ 	]+a0,a1,zero
+diff --git a/gas/testsuite/gas/riscv/zext.s b/gas/testsuite/gas/riscv/zext.s
+deleted file mode 100644
+index e2e127d949..0000000000
+--- a/gas/testsuite/gas/riscv/zext.s
++++ /dev/null
+@@ -1,6 +0,0 @@
+-target:
+-	zext.h	a0, a1
+-
+-.ifdef __64_bit__
+-	zext.w  a0, a1
+-.endif
+-- 
+2.33.0
+

+ 287 - 0
recipes-devtools/gdb/files/0044-RISC-V-Add-sext.-bh-and-zext.-bhw-pseudo-instruction.patch

@@ -0,0 +1,287 @@
+From 16266fab77ff6e3760a08f107c782b91e595b33e Mon Sep 17 00:00:00 2001
+From: Nelson Chu <nelson.chu@sifive.com>
+Date: Wed, 9 Dec 2020 13:53:22 +0800
+Subject: [PATCH 44/48] RISC-V: Add sext.[bh] and zext.[bhw] pseudo
+ instructions.
+
+https://github.com/riscv/riscv-asm-manual/pull/61
+
+We aleady have sext.w, so just add sext.b, sext.h, zext.b, zext.h
+and zext.w.  In a certain sense, zext.b is not a pseudo - It is an
+alias of andi.  Similarly, sext.b and sext.h are aliases of other
+rvb instructions, when we enable b extension; But they are pseudos
+when we just enable rvi.  However, this patch does not consider the
+rvb cases.  Besides, zext.w is only valid in rv64.
+
+gas/
+    * config/tc-riscv.c (riscv_ext): New function.  Use md_assemblef
+    to expand the zext and sext pseudos, to give them a chance to be
+    expanded into c-ext instructions.
+    (macro): Handle M_ZEXTH, M_ZEXTW, M_SEXTB and M_SEXTH.
+    * testsuite/gas/riscv/ext.s: New testcase.
+    * testsuite/gas/riscv/ext-32.d: Likewise.
+    * testsuite/gas/riscv/ext-64.d: Likewise.
+include/
+    * opcode/riscv.h (M_ZEXTH, M_ZEXTW, M_SEXTB, M_SEXTH.): Added.
+opcodes/
+    * riscv-opc.c (riscv_opcodes): Add sext.[bh] and zext.[bhw].
+---
+ gas/config/tc-riscv.c            | 33 +++++++++++++++++++++
+ gas/testsuite/gas/riscv/ext-32.d | 39 ++++++++++++++++++++++++
+ gas/testsuite/gas/riscv/ext-64.d | 51 ++++++++++++++++++++++++++++++++
+ gas/testsuite/gas/riscv/ext.s    | 38 ++++++++++++++++++++++++
+ include/opcode/riscv.h           |  4 +++
+ opcodes/riscv-opc.c              |  5 ++++
+ 6 files changed, 170 insertions(+)
+ create mode 100644 gas/testsuite/gas/riscv/ext-32.d
+ create mode 100644 gas/testsuite/gas/riscv/ext-64.d
+ create mode 100644 gas/testsuite/gas/riscv/ext.s
+
+diff --git a/gas/config/tc-riscv.c b/gas/config/tc-riscv.c
+index 2a5ac9c861..bee1186c3a 100644
+--- a/gas/config/tc-riscv.c
++++ b/gas/config/tc-riscv.c
+@@ -1623,6 +1623,23 @@ vector_macro (struct riscv_cl_insn *ip)
+     }
+ }
+ 
++/* Zero extend and sign extend byte/half-word/word.  */
++
++static void
++riscv_ext (int destreg, int srcreg, unsigned shift, bfd_boolean sign)
++{
++  if (sign)
++    {
++      md_assemblef ("slli x%d, x%d, 0x%x", destreg, srcreg, shift);
++      md_assemblef ("srai x%d, x%d, 0x%x", destreg, destreg, shift);
++    }
++  else
++    {
++      md_assemblef ("slli x%d, x%d, 0x%x", destreg, srcreg, shift);
++      md_assemblef ("srli x%d, x%d, 0x%x", destreg, destreg, shift);
++    }
++}
++
+ /* Expand RISC-V assembly macros into one or more instructions.  */
+ static void
+ macro (struct riscv_cl_insn *ip, expressionS *imm_expr,
+@@ -1769,6 +1786,22 @@ macro (struct riscv_cl_insn *ip, expressionS *imm_expr,
+       vector_macro (ip);
+       break;
+ 
++    case M_ZEXTH:
++      riscv_ext (rd, rs1, xlen - 16, FALSE);
++      break;
++
++    case M_ZEXTW:
++      riscv_ext (rd, rs1, xlen - 32, FALSE);
++      break;
++
++    case M_SEXTB:
++      riscv_ext (rd, rs1, xlen - 8, TRUE);
++      break;
++
++    case M_SEXTH:
++      riscv_ext (rd, rs1, xlen - 16, TRUE);
++      break;
++
+     default:
+       as_bad (_("Macro %s not implemented"), ip->insn_mo->name);
+       break;
+diff --git a/gas/testsuite/gas/riscv/ext-32.d b/gas/testsuite/gas/riscv/ext-32.d
+new file mode 100644
+index 0000000000..918c9c8a16
+--- /dev/null
++++ b/gas/testsuite/gas/riscv/ext-32.d
+@@ -0,0 +1,39 @@
++#as: -march=rv32i
++#source: ext.s
++#objdump: -d
++
++.*:[ 	]+file format .*
++
++
++Disassembly of section .text:
++
++0+000 <target>:
++[ 	]+0:[ 	]+0ff57513[ 	]+zext.b[ 	]+a0,a0
++[ 	]+4:[ 	]+01051513[ 	]+slli[ 	]+a0,a0,0x10
++[ 	]+8:[ 	]+01055513[ 	]+srli[ 	]+a0,a0,0x10
++[ 	]+c:[ 	]+01851513[ 	]+slli[ 	]+a0,a0,0x18
++[ 	]+10:[ 	]+41855513[ 	]+srai[ 	]+a0,a0,0x18
++[ 	]+14:[ 	]+01051513[ 	]+slli[ 	]+a0,a0,0x10
++[ 	]+18:[ 	]+41055513[ 	]+srai[ 	]+a0,a0,0x10
++[ 	]+1c:[ 	]+0ff67593[ 	]+zext.b[ 	]+a1,a2
++[ 	]+20:[ 	]+01061593[ 	]+slli[ 	]+a1,a2,0x10
++[ 	]+24:[ 	]+0105d593[ 	]+srli[ 	]+a1,a1,0x10
++[ 	]+28:[ 	]+01861593[ 	]+slli[ 	]+a1,a2,0x18
++[ 	]+2c:[ 	]+4185d593[ 	]+srai[ 	]+a1,a1,0x18
++[ 	]+30:[ 	]+01061593[ 	]+slli[ 	]+a1,a2,0x10
++[ 	]+34:[ 	]+4105d593[ 	]+srai[ 	]+a1,a1,0x10
++[ 	]+38:[ 	]+0ff57513[ 	]+zext.b[ 	]+a0,a0
++[ 	]+3c:[ 	]+0542[ 	]+slli[ 	]+a0,a0,0x10
++[ 	]+3e:[ 	]+8141[ 	]+srli[ 	]+a0,a0,0x10
++[ 	]+40:[ 	]+0562[ 	]+slli[ 	]+a0,a0,0x18
++[ 	]+42:[ 	]+8561[ 	]+srai[ 	]+a0,a0,0x18
++[ 	]+44:[ 	]+0542[ 	]+slli[ 	]+a0,a0,0x10
++[ 	]+46:[ 	]+8541[ 	]+srai[ 	]+a0,a0,0x10
++[ 	]+48:[ 	]+0ff67593[ 	]+zext.b[ 	]+a1,a2
++[ 	]+4c:[ 	]+01061593[ 	]+slli[ 	]+a1,a2,0x10
++[ 	]+50:[ 	]+81c1[ 	]+srli[ 	]+a1,a1,0x10
++[ 	]+52:[ 	]+01861593[ 	]+slli[ 	]+a1,a2,0x18
++[ 	]+56:[ 	]+85e1[ 	]+srai[ 	]+a1,a1,0x18
++[ 	]+58:[ 	]+01061593[ 	]+slli[ 	]+a1,a2,0x10
++[ 	]+5c:[ 	]+85c1[ 	]+srai[ 	]+a1,a1,0x10
++#...
+diff --git a/gas/testsuite/gas/riscv/ext-64.d b/gas/testsuite/gas/riscv/ext-64.d
+new file mode 100644
+index 0000000000..49d109b1db
+--- /dev/null
++++ b/gas/testsuite/gas/riscv/ext-64.d
+@@ -0,0 +1,51 @@
++#as: -march=rv64i -defsym __64_bit__=1
++#source: ext.s
++#objdump: -d
++
++.*:[ 	]+file format .*
++
++
++Disassembly of section .text:
++
++0+000 <target>:
++[ 	]+0:[ 	]+0ff57513[ 	]+zext.b[ 	]+a0,a0
++[ 	]+4:[ 	]+03051513[ 	]+slli[ 	]+a0,a0,0x30
++[ 	]+8:[ 	]+03055513[ 	]+srli[ 	]+a0,a0,0x30
++[ 	]+c:[ 	]+03851513[ 	]+slli[ 	]+a0,a0,0x38
++[ 	]+10:[ 	]+43855513[ 	]+srai[ 	]+a0,a0,0x38
++[ 	]+14:[ 	]+03051513[ 	]+slli[ 	]+a0,a0,0x30
++[ 	]+18:[ 	]+43055513[ 	]+srai[ 	]+a0,a0,0x30
++[ 	]+1c:[ 	]+0ff67593[ 	]+zext.b[ 	]+a1,a2
++[ 	]+20:[ 	]+03061593[ 	]+slli[ 	]+a1,a2,0x30
++[ 	]+24:[ 	]+0305d593[ 	]+srli[ 	]+a1,a1,0x30
++[ 	]+28:[ 	]+03861593[ 	]+slli[ 	]+a1,a2,0x38
++[ 	]+2c:[ 	]+4385d593[ 	]+srai[ 	]+a1,a1,0x38
++[ 	]+30:[ 	]+03061593[ 	]+slli[ 	]+a1,a2,0x30
++[ 	]+34:[ 	]+4305d593[ 	]+srai[ 	]+a1,a1,0x30
++[ 	]+38:[ 	]+02051513[ 	]+slli[ 	]+a0,a0,0x20
++[ 	]+3c:[ 	]+02055513[ 	]+srli[ 	]+a0,a0,0x20
++[ 	]+40:[ 	]+0005051b[ 	]+sext.w[ 	]+a0,a0
++[ 	]+44:[ 	]+02061593[ 	]+slli[ 	]+a1,a2,0x20
++[ 	]+48:[ 	]+0205d593[ 	]+srli[ 	]+a1,a1,0x20
++[ 	]+4c:[ 	]+0006059b[ 	]+sext.w[ 	]+a1,a2
++[ 	]+50:[ 	]+0ff57513[ 	]+zext.b[ 	]+a0,a0
++[ 	]+54:[ 	]+1542[ 	]+slli[ 	]+a0,a0,0x30
++[ 	]+56:[ 	]+9141[ 	]+srli[ 	]+a0,a0,0x30
++[ 	]+58:[ 	]+1562[ 	]+slli[ 	]+a0,a0,0x38
++[ 	]+5a:[ 	]+9561[ 	]+srai[ 	]+a0,a0,0x38
++[ 	]+5c:[ 	]+1542[ 	]+slli[ 	]+a0,a0,0x30
++[ 	]+5e:[ 	]+9541[ 	]+srai[ 	]+a0,a0,0x30
++[ 	]+60:[ 	]+0ff67593[ 	]+zext.b[ 	]+a1,a2
++[ 	]+64:[ 	]+03061593[ 	]+slli[ 	]+a1,a2,0x30
++[ 	]+68:[ 	]+91c1[ 	]+srli[ 	]+a1,a1,0x30
++[ 	]+6a:[ 	]+03861593[ 	]+slli[ 	]+a1,a2,0x38
++[ 	]+6e:[ 	]+95e1[ 	]+srai[ 	]+a1,a1,0x38
++[ 	]+70:[ 	]+03061593[ 	]+slli[ 	]+a1,a2,0x30
++[ 	]+74:[ 	]+95c1[ 	]+srai[ 	]+a1,a1,0x30
++[ 	]+76:[ 	]+1502[ 	]+slli[ 	]+a0,a0,0x20
++[ 	]+78:[ 	]+9101[ 	]+srli[ 	]+a0,a0,0x20
++[ 	]+7a:[ 	]+2501[ 	]+sext.w[ 	]+a0,a0
++[ 	]+7c:[ 	]+02061593[ 	]+slli[ 	]+a1,a2,0x20
++[ 	]+80:[ 	]+9181[ 	]+srli[ 	]+a1,a1,0x20
++[ 	]+82:[ 	]+0006059b[ 	]+sext.w[ 	]+a1,a2
++#...
+diff --git a/gas/testsuite/gas/riscv/ext.s b/gas/testsuite/gas/riscv/ext.s
+new file mode 100644
+index 0000000000..f95713422a
+--- /dev/null
++++ b/gas/testsuite/gas/riscv/ext.s
+@@ -0,0 +1,38 @@
++target:
++	.option norvc
++	zext.b	a0, a0
++	zext.h	a0, a0
++	sext.b	a0, a0
++	sext.h	a0, a0
++
++	zext.b	a1, a2
++	zext.h	a1, a2
++	sext.b	a1, a2
++	sext.h	a1, a2
++
++.ifdef __64_bit__
++	zext.w	a0, a0
++	sext.w	a0, a0
++
++	zext.w	a1, a2
++	sext.w	a1, a2
++.endif
++
++	.option rvc
++	zext.b	a0, a0
++	zext.h	a0, a0
++	sext.b	a0, a0
++	sext.h	a0, a0
++
++	zext.b	a1, a2
++	zext.h	a1, a2
++	sext.b	a1, a2
++	sext.h	a1, a2
++
++.ifdef __64_bit__
++	zext.w	a0, a0
++	sext.w	a0, a0
++
++	zext.w	a1, a2
++	sext.w	a1, a2
++.endif
+diff --git a/include/opcode/riscv.h b/include/opcode/riscv.h
+index 9af4f6514c..71498563c3 100644
+--- a/include/opcode/riscv.h
++++ b/include/opcode/riscv.h
+@@ -583,6 +583,10 @@ enum
+   M_VMSGEU,
+   M_RL,
+   M_FL,
++  M_ZEXTH,
++  M_ZEXTW,
++  M_SEXTB,
++  M_SEXTH,
+   M_NUM_MACROS
+ };
+ 
+diff --git a/opcodes/riscv-opc.c b/opcodes/riscv-opc.c
+index 5d49912e2e..5f0885b5c6 100644
+--- a/opcodes/riscv-opc.c
++++ b/opcodes/riscv-opc.c
+@@ -705,6 +705,7 @@ const struct riscv_opcode riscv_opcodes[] =
+ {"mv",          0, INSN_CLASS_I,   "d,s",  MATCH_ADDI, MASK_ADDI | MASK_IMM, match_opcode, INSN_ALIAS },
+ {"move",        0, INSN_CLASS_C,   "d,CV",  MATCH_C_MV, MASK_C_MV, match_c_add, INSN_ALIAS },
+ {"move",        0, INSN_CLASS_I,   "d,s",  MATCH_ADDI, MASK_ADDI | MASK_IMM, match_opcode, INSN_ALIAS },
++{"zext.b",      0, INSN_CLASS_I,   "d,s",  MATCH_ANDI | ENCODE_ITYPE_IMM (255), MASK_ANDI | MASK_IMM, match_opcode, INSN_ALIAS },
+ {"andi",        0, INSN_CLASS_C,   "Cs,Cw,Co",  MATCH_C_ANDI, MASK_C_ANDI, match_opcode, INSN_ALIAS },
+ {"andi",        0, INSN_CLASS_I,   "d,s,j",  MATCH_ANDI, MASK_ANDI, match_opcode, 0 },
+ {"and",         0, INSN_CLASS_C,   "Cs,Cw,Ct",  MATCH_C_AND, MASK_C_AND, match_opcode, INSN_ALIAS },
+@@ -1162,6 +1163,7 @@ const struct riscv_opcode riscv_opcodes[] =
+ {"sh3add",    0, INSN_CLASS_B_OR_ZBA,   "d,s,t",  MATCH_SH3ADD, MASK_SH3ADD, match_opcode, 0 },
+ {"slliu.w",  64, INSN_CLASS_B_OR_ZBA,   "d,s,>",  MATCH_SLLIU_W, MASK_SLLIU_W, match_opcode, 0 },
+ {"zext.w",   64, INSN_CLASS_B_OR_ZBA_OR_ZBB,   "d,s",  MATCH_ADDU_W, MASK_ADDU_W | MASK_RS2, match_opcode, INSN_ALIAS },
++{"zext.w",   64, INSN_CLASS_I,                 "d,s",  0, (int) M_ZEXTW,  match_never, INSN_MACRO },
+ {"addu.w",   64, INSN_CLASS_B_OR_ZBA,   "d,s,t",  MATCH_ADDU_W, MASK_ADDU_W, match_opcode, 0 },
+ {"sh1addu.w",64, INSN_CLASS_B_OR_ZBA,   "d,s,t",  MATCH_SH1ADDU_W, MASK_SH1ADDU_W, match_opcode, 0 },
+ {"sh2addu.w",64, INSN_CLASS_B_OR_ZBA,   "d,s,t",  MATCH_SH2ADDU_W, MASK_SH2ADDU_W, match_opcode, 0 },
+@@ -1184,9 +1186,12 @@ const struct riscv_opcode riscv_opcodes[] =
+ {"ror",       0, INSN_CLASS_B_OR_ZBB,   "d,s,t",  MATCH_ROR, MASK_ROR, match_opcode, 0 },
+ {"ror",       0, INSN_CLASS_B_OR_ZBB,   "d,s,>",  MATCH_RORI, MASK_RORI, match_opcode, INSN_ALIAS },
+ {"sext.b",    0, INSN_CLASS_B_OR_ZBB,   "d,s",  MATCH_SEXT_B, MASK_SEXT_B, match_opcode, 0 },
++{"sext.b",    0, INSN_CLASS_I,          "d,s",  0, (int) M_SEXTB,  match_never, INSN_MACRO },
+ {"sext.h",    0, INSN_CLASS_B_OR_ZBB,   "d,s",  MATCH_SEXT_H, MASK_SEXT_H, match_opcode, 0 },
++{"sext.h",    0, INSN_CLASS_I,          "d,s",  0, (int) M_SEXTH,  match_never, INSN_MACRO },
+ {"zext.h",   32, INSN_CLASS_B_OR_ZBB,   "d,s",  MATCH_PACK, MASK_PACK | MASK_RS2, match_opcode, INSN_ALIAS },	/* pack with rs2=x0  */
+ {"zext.h",   64, INSN_CLASS_B_OR_ZBB,   "d,s",  MATCH_PACKW, MASK_PACKW | MASK_RS2, match_opcode, INSN_ALIAS },	/* packw with rs2=x0  */
++{"zext.h",    0, INSN_CLASS_I,          "d,s",  0, (int) M_ZEXTH,  match_never, INSN_MACRO },
+ {"clzw",     64, INSN_CLASS_B_OR_ZBB,   "d,s",  MATCH_CLZW, MASK_CLZW, match_opcode, 0 },
+ {"ctzw",     64, INSN_CLASS_B_OR_ZBB,   "d,s",  MATCH_CTZW, MASK_CTZW, match_opcode, 0 },
+ {"pcntw",    64, INSN_CLASS_B_OR_ZBB,   "d,s",  MATCH_PCNTW, MASK_PCNTW, match_opcode, 0 },
+-- 
+2.33.0
+

+ 25 - 0
recipes-devtools/gdb/files/0045-Fix-sim-build-since-op-match_func-have-more-argument.patch

@@ -0,0 +1,25 @@
+From baabe8640ae726f4244ba08713bf2312a5ea1be3 Mon Sep 17 00:00:00 2001
+From: Nelson Chu <nelson.chu@sifive.com>
+Date: Mon, 21 Dec 2020 15:12:42 +0800
+Subject: [PATCH 45/48] Fix sim build since op->match_func have more arguments.
+
+---
+ sim/riscv/sim-main.c | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+diff --git a/sim/riscv/sim-main.c b/sim/riscv/sim-main.c
+index d773a35cb5..037e1641fb 100644
+--- a/sim/riscv/sim-main.c
++++ b/sim/riscv/sim-main.c
+@@ -2220,7 +2220,7 @@ void step_once (SIM_CPU *cpu)
+   for (; op->name; op++)
+     {
+       /* Does the opcode match?  */
+-      if (!(op->match_func) (op, iw))
++      if (!(op->match_func) (op, iw, 0, NULL))
+ 	continue;
+       /* Is this a pseudo-instruction?  */
+       if ((op->pinfo & INSN_ALIAS))
+-- 
+2.33.0
+

+ 163 - 0
recipes-devtools/gdb/files/0046-SiFive-Add-RNMI-CSRs-and-MNRET-instruction.patch

@@ -0,0 +1,163 @@
+From 1ac8c2ffcb4a0a98d0597e71f9313352bda11ee3 Mon Sep 17 00:00:00 2001
+From: Nelson Chu <nelson.chu@sifive.com>
+Date: Wed, 30 Dec 2020 11:29:45 +0800
+Subject: [PATCH 46/48] SiFive: Add RNMI CSRs and MNRET instruction.
+
+https://github.com/sifive/arch-specs/blob/master/nmi.adoc#rnmi-operation.
+
+There are four RNMI CSRs, mnscratch (0x350), mnepc (0x351), mncause (0x352)
+and mnstatus (0x353).  And there is a new instruction, MNRET, which has the
+same encoding as MRET, except the func12 is 0x702 (011100000010).
+---
+ gas/config/tc-riscv.c                            |  1 +
+ gas/testsuite/gas/riscv/priv-reg-version-1p10.d  |  4 ++++
+ gas/testsuite/gas/riscv/priv-reg-version-1p11.d  |  4 ++++
+ gas/testsuite/gas/riscv/priv-reg-version-1p9p1.d |  4 ++++
+ gas/testsuite/gas/riscv/priv-reg.s               |  6 ++++++
+ include/opcode/riscv-opc.h                       | 11 +++++++++++
+ include/opcode/riscv.h                           | 11 ++++++-----
+ opcodes/riscv-opc.c                              |  1 +
+ 8 files changed, 37 insertions(+), 5 deletions(-)
+
+diff --git a/gas/config/tc-riscv.c b/gas/config/tc-riscv.c
+index bee1186c3a..60b9a92d77 100644
+--- a/gas/config/tc-riscv.c
++++ b/gas/config/tc-riscv.c
+@@ -760,6 +760,7 @@ riscv_csr_address (const char *csr_name,
+       break;
+     case CSR_CLASS_DEBUG:
+     case CSR_CLASS_CLIC:
++    case CSR_CLASS_RNMI:
+       need_check_version = FALSE;
+       break;
+     default:
+diff --git a/gas/testsuite/gas/riscv/priv-reg-version-1p10.d b/gas/testsuite/gas/riscv/priv-reg-version-1p10.d
+index 2db8d2021e..61c75ee0fc 100644
+--- a/gas/testsuite/gas/riscv/priv-reg-version-1p10.d
++++ b/gas/testsuite/gas/riscv/priv-reg-version-1p10.d
+@@ -276,3 +276,7 @@ Disassembly of section .text:
+ [     	]+[0-9a-f]+:[  	]+34502573[    	]+csrr[        	]+a0,mnxti
+ [     	]+[0-9a-f]+:[  	]+34602573[    	]+csrr[        	]+a0,mintstatus
+ [     	]+[0-9a-f]+:[  	]+34811173[    	]+csrrw[        	]+sp,mscratchcsw,sp
++[     	]+[0-9a-f]+:[  	]+35002573[    	]+csrr[        	]+a0,mnscratch
++[     	]+[0-9a-f]+:[  	]+35102573[    	]+csrr[        	]+a0,mnepc
++[     	]+[0-9a-f]+:[  	]+35202573[    	]+csrr[        	]+a0,mncause
++[     	]+[0-9a-f]+:[  	]+35302573[    	]+csrr[        	]+a0,mnstatus
+diff --git a/gas/testsuite/gas/riscv/priv-reg-version-1p11.d b/gas/testsuite/gas/riscv/priv-reg-version-1p11.d
+index 77ed98891c..a92e95086b 100644
+--- a/gas/testsuite/gas/riscv/priv-reg-version-1p11.d
++++ b/gas/testsuite/gas/riscv/priv-reg-version-1p11.d
+@@ -276,3 +276,7 @@ Disassembly of section .text:
+ [     	]+[0-9a-f]+:[  	]+34502573[    	]+csrr[        	]+a0,mnxti
+ [     	]+[0-9a-f]+:[  	]+34602573[    	]+csrr[        	]+a0,mintstatus
+ [     	]+[0-9a-f]+:[  	]+34811173[    	]+csrrw[        	]+sp,mscratchcsw,sp
++[     	]+[0-9a-f]+:[  	]+35002573[    	]+csrr[        	]+a0,mnscratch
++[     	]+[0-9a-f]+:[  	]+35102573[    	]+csrr[        	]+a0,mnepc
++[     	]+[0-9a-f]+:[  	]+35202573[    	]+csrr[        	]+a0,mncause
++[     	]+[0-9a-f]+:[  	]+35302573[    	]+csrr[        	]+a0,mnstatus
+diff --git a/gas/testsuite/gas/riscv/priv-reg-version-1p9p1.d b/gas/testsuite/gas/riscv/priv-reg-version-1p9p1.d
+index 7e1515f8be..27b599aa86 100644
+--- a/gas/testsuite/gas/riscv/priv-reg-version-1p9p1.d
++++ b/gas/testsuite/gas/riscv/priv-reg-version-1p9p1.d
+@@ -276,3 +276,7 @@ Disassembly of section .text:
+ [     	]+[0-9a-f]+:[  	]+34502573[    	]+csrr[        	]+a0,mnxti
+ [     	]+[0-9a-f]+:[  	]+34602573[    	]+csrr[        	]+a0,mintstatus
+ [     	]+[0-9a-f]+:[  	]+34811173[    	]+csrrw[        	]+sp,mscratchcsw,sp
++[     	]+[0-9a-f]+:[  	]+35002573[    	]+csrr[        	]+a0,mnscratch
++[     	]+[0-9a-f]+:[  	]+35102573[    	]+csrr[        	]+a0,mnepc
++[     	]+[0-9a-f]+:[  	]+35202573[    	]+csrr[        	]+a0,mncause
++[     	]+[0-9a-f]+:[  	]+35302573[    	]+csrr[        	]+a0,mnstatus
+diff --git a/gas/testsuite/gas/riscv/priv-reg.s b/gas/testsuite/gas/riscv/priv-reg.s
+index bce7d00b81..035e06e255 100644
+--- a/gas/testsuite/gas/riscv/priv-reg.s
++++ b/gas/testsuite/gas/riscv/priv-reg.s
+@@ -297,3 +297,9 @@
+ 	csr mnxti
+ 	csr mintstatus
+ 	csrrw sp,mscratchcsw,sp
++
++	# RNMI registers
++	csr mnscratch
++	csr mnepc
++	csr mncause
++	csr mnstatus
+diff --git a/include/opcode/riscv-opc.h b/include/opcode/riscv-opc.h
+index 500be26f0f..1faa2a8a8a 100644
+--- a/include/opcode/riscv-opc.h
++++ b/include/opcode/riscv-opc.h
+@@ -453,6 +453,8 @@
+ #define MASK_HRET  0xffffffff
+ #define MATCH_MRET 0x30200073
+ #define MASK_MRET  0xffffffff
++#define MATCH_MNRET 0x70200073
++#define MASK_MNRET  0xffffffff
+ #define MATCH_DRET 0x7b200073
+ #define MASK_DRET  0xffffffff
+ #define MATCH_SFENCE_VM 0x10400073
+@@ -3567,6 +3569,10 @@ funct6 VM  VS2  VS1/RS1/IMM funct3 VD   opcode
+ #define CSR_MNXTI 0x345
+ #define CSR_MINTSTATUS 0x346
+ #define CSR_MSCRATCHCSW 0x348
++#define CSR_MNSCRATCH 0x350
++#define CSR_MNEPC 0x351
++#define CSR_MNCAUSE 0x352
++#define CSR_MNSTATUS 0x353
+ #endif /* RISCV_ENCODING_H.  */
+ #ifdef DECLARE_INSN
+ DECLARE_INSN(slli_rv32, MATCH_SLLI_RV32, MASK_SLLI_RV32)
+@@ -3784,6 +3790,7 @@ DECLARE_INSN(uret, MATCH_URET, MASK_URET)
+ DECLARE_INSN(sret, MATCH_SRET, MASK_SRET)
+ DECLARE_INSN(hret, MATCH_HRET, MASK_HRET)
+ DECLARE_INSN(mret, MATCH_MRET, MASK_MRET)
++DECLARE_INSN(mnret, MATCH_MNRET, MASK_MNRET)
+ DECLARE_INSN(dret, MATCH_DRET, MASK_DRET)
+ DECLARE_INSN(sfence_vm, MATCH_SFENCE_VM, MASK_SFENCE_VM)
+ DECLARE_INSN(sfence_vma, MATCH_SFENCE_VMA, MASK_SFENCE_VMA)
+@@ -4256,6 +4263,10 @@ DECLARE_CSR(mtvt, CSR_MTVT, CSR_CLASS_CLIC, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLAS
+ DECLARE_CSR(mnxti, CSR_MNXTI, CSR_CLASS_CLIC, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE)
+ DECLARE_CSR(mintstatus, CSR_MINTSTATUS, CSR_CLASS_CLIC, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE)
+ DECLARE_CSR(mscratchcsw, CSR_MSCRATCHCSW, CSR_CLASS_CLIC, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE)
++DECLARE_CSR(mnscratch, CSR_MNSCRATCH, CSR_CLASS_RNMI, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE)
++DECLARE_CSR(mnepc, CSR_MNEPC, CSR_CLASS_RNMI, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE)
++DECLARE_CSR(mncause, CSR_MNCAUSE, CSR_CLASS_RNMI, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE)
++DECLARE_CSR(mnstatus, CSR_MNSTATUS, CSR_CLASS_RNMI, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE)
+ #endif /* DECLARE_CSR.  */
+ #ifdef DECLARE_CSR_ALIAS
+ DECLARE_CSR_ALIAS(ubadaddr, CSR_UTVAL, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_1P10)
+diff --git a/include/opcode/riscv.h b/include/opcode/riscv.h
+index 71498563c3..02800fda64 100644
+--- a/include/opcode/riscv.h
++++ b/include/opcode/riscv.h
+@@ -470,11 +470,12 @@ enum riscv_csr_class
+   CSR_CLASS_NONE,
+ 
+   CSR_CLASS_I,
+-  CSR_CLASS_I_32,      /* rv32 only */
+-  CSR_CLASS_F,         /* f-ext only */
+-  CSR_CLASS_V,         /* v-ext only */
+-  CSR_CLASS_DEBUG,     /* debug CSR */
+-  CSR_CLASS_CLIC       /* clic CSR */
++  CSR_CLASS_I_32,	/* rv32 only  */
++  CSR_CLASS_F,		/* f-ext only  */
++  CSR_CLASS_V,		/* v-ext only  */
++  CSR_CLASS_DEBUG,	/* debug CSR  */
++  CSR_CLASS_CLIC,	/* clic CSR  */
++  CSR_CLASS_RNMI,	/* rnmi CSR  */
+ };
+ 
+ /* The current supported privilege spec versions.  */
+diff --git a/opcodes/riscv-opc.c b/opcodes/riscv-opc.c
+index 5f0885b5c6..5c07c0a2db 100644
+--- a/opcodes/riscv-opc.c
++++ b/opcodes/riscv-opc.c
+@@ -1581,6 +1581,7 @@ const struct riscv_opcode riscv_opcodes[] =
+ {"sret",       0, INSN_CLASS_I,   "",     MATCH_SRET, MASK_SRET, match_opcode, 0 },
+ {"hret",       0, INSN_CLASS_I,   "",     MATCH_HRET, MASK_HRET, match_opcode, 0 },
+ {"mret",       0, INSN_CLASS_I,   "",     MATCH_MRET, MASK_MRET, match_opcode, 0 },
++{"mnret",      0, INSN_CLASS_I,   "",     MATCH_MNRET, MASK_MNRET, match_opcode, 0 },
+ {"dret",       0, INSN_CLASS_I,   "",     MATCH_DRET, MASK_DRET, match_opcode, 0 },
+ {"sfence.vm",  0, INSN_CLASS_I,   "",     MATCH_SFENCE_VM, MASK_SFENCE_VM | MASK_RS1, match_opcode, 0 },
+ {"sfence.vm",  0, INSN_CLASS_I,   "s",    MATCH_SFENCE_VM, MASK_SFENCE_VM, match_opcode, 0 },
+-- 
+2.33.0
+

+ 1292 - 0
recipes-devtools/gdb/files/0047-RISC-V-Freeze-ZBA-ZBB-ZBC-to-0.93.patch

@@ -0,0 +1,1292 @@
+From c7b89dd10cf3e18c695533e214a51b3efe7dd992 Mon Sep 17 00:00:00 2001
+From: Nelson Chu <nelson.chu@sifive.com>
+Date: Thu, 7 Jan 2021 21:05:48 +0800
+Subject: [PATCH 47/48] RISC-V: Freeze ZBA/ZBB/ZBC to 0.93.
+
+Only enable the frozen ZBA/ZBB/ZBC, other ZB* can not be used but
+still keep their opcodes.  Rename ZBS from sb* to b* will cause
+encoding conflicts for bext/bextw (ZBE), so rename the conflict
+sbext/sbextw to bfext/bfextw.
+
+Besides, cleanup and make them the same as the upstream code.
+---
+ bfd/elfxx-riscv.c                             |   3 +-
+ gas/config/tc-riscv.c                         |  86 +------
+ .../gas/riscv/attribute-15-unratified.d       |   4 +-
+ gas/testsuite/gas/riscv/bitmanip-insns-32.d   |  26 ++-
+ gas/testsuite/gas/riscv/bitmanip-insns-64.d   |  53 ++---
+ .../gas/riscv/bitmanip-insns-pseudo-32.d      |  61 -----
+ .../gas/riscv/bitmanip-insns-pseudo-64.d      |  84 -------
+ .../riscv/bitmanip-insns-pseudo-noalias-32.d  |  61 -----
+ .../riscv/bitmanip-insns-pseudo-noalias-64.d  |  84 -------
+ gas/testsuite/gas/riscv/bitmanip-insns.s      |  57 ++---
+ include/opcode/riscv-opc.h                    | 138 +++++------
+ include/opcode/riscv.h                        |  21 +-
+ opcodes/riscv-opc.c                           | 220 ++++++++----------
+ 13 files changed, 256 insertions(+), 642 deletions(-)
+ delete mode 100644 gas/testsuite/gas/riscv/bitmanip-insns-pseudo-32.d
+ delete mode 100644 gas/testsuite/gas/riscv/bitmanip-insns-pseudo-64.d
+ delete mode 100644 gas/testsuite/gas/riscv/bitmanip-insns-pseudo-noalias-32.d
+ delete mode 100644 gas/testsuite/gas/riscv/bitmanip-insns-pseudo-noalias-64.d
+
+diff --git a/bfd/elfxx-riscv.c b/bfd/elfxx-riscv.c
+index 75add5be1c..af014b29cb 100644
+--- a/bfd/elfxx-riscv.c
++++ b/bfd/elfxx-riscv.c
+@@ -1566,8 +1566,7 @@ riscv_parse_prefixed_ext (riscv_parse_subset_t *rps,
+ 
+ static const char * const riscv_std_z_ext_strtab[] =
+ {
+-  "zicsr", "zifencei", "zfh",
+-  "zba", "zbb", "zbc", "zbe", "zbf", "zbm", "zbp", "zbr", "zbs", "zbt",
++  "zicsr", "zifencei", "zfh", "zba", "zbb", "zbc",
+   "zvamo", "zvediv", "zvlsseg", "zvqmac",
+   NULL
+ };
+diff --git a/gas/config/tc-riscv.c b/gas/config/tc-riscv.c
+index 60b9a92d77..25405ca30d 100644
+--- a/gas/config/tc-riscv.c
++++ b/gas/config/tc-riscv.c
+@@ -260,35 +260,14 @@ riscv_multi_subset_supports (enum riscv_insn_class insn_class)
+     case INSN_CLASS_V_AND_ZVQMAC:
+       return riscv_subset_supports ("v") && riscv_subset_supports ("zvqmac");
+ 
+-    /* Sure.  */
+-    case INSN_CLASS_B_OR_ZBA:
+-      return riscv_subset_supports ("b") || riscv_subset_supports ("zba");
+-    case INSN_CLASS_B_OR_ZBB:
+-      return riscv_subset_supports ("b") || riscv_subset_supports ("zbb");
+-    case INSN_CLASS_B_OR_ZBC:
+-      return riscv_subset_supports ("b") || riscv_subset_supports ("zbc");
+-    case INSN_CLASS_B_OR_ZBS:
+-      return riscv_subset_supports ("b") || riscv_subset_supports ("zbs");
+-    case INSN_CLASS_B_OR_ZBA_OR_ZBB:
+-      return (riscv_subset_supports ("b")
+-	      || riscv_subset_supports ("zba")
+-	      || riscv_subset_supports ("zbb"));
+-
+-    /* Not sure.  */
+-    case INSN_CLASS_B:
+-      return riscv_subset_supports ("b");
+-    case INSN_CLASS_B_OR_ZBE:
+-      return riscv_subset_supports ("b") || riscv_subset_supports ("zbe");
+-    case INSN_CLASS_B_OR_ZBF:
+-      return riscv_subset_supports ("b") || riscv_subset_supports ("zbf");
+-    case INSN_CLASS_B_OR_ZBM:
+-      return riscv_subset_supports ("b") || riscv_subset_supports ("zbm");
+-    case INSN_CLASS_B_OR_ZBP:
+-      return riscv_subset_supports ("b") || riscv_subset_supports ("zbp");
+-    case INSN_CLASS_ZBR:
+-      return riscv_subset_supports ("zbr");
+-    case INSN_CLASS_ZBT:
+-      return riscv_subset_supports ("zbt");
++    case INSN_CLASS_ZBA:
++      return riscv_subset_supports ("zba");
++    case INSN_CLASS_ZBB:
++      return riscv_subset_supports ("zbb");
++    case INSN_CLASS_ZBC:
++      return riscv_subset_supports ("zbc");
++    case INSN_CLASS_ZBA_OR_ZBB:
++      return riscv_subset_supports ("zba") || riscv_subset_supports ("zbb");
+ 
+     default:
+       as_fatal ("Unreachable");
+@@ -335,7 +314,7 @@ riscv_get_default_ext_version (const char *name,
+ 	 && ext->name
+ 	 && strcmp (ext->name, name) == 0)
+     {
+-      if (ext->isa_spec_class == ISA_SPEC_CLASS_NONE
++      if (ext->isa_spec_class == ISA_SPEC_CLASS_DRAFT
+ 	  || ext->isa_spec_class == default_isa_spec)
+ 	{
+ 	  *major_version = ext->major_version;
+@@ -1282,15 +1261,6 @@ macro_build (expressionS *ep, const char *name, const char *fmt, ...)
+ 	  INSERT_OPERAND (RS2, insn, va_arg (args, int));
+ 	  continue;
+ 
+-	case 'r':
+-	  INSERT_OPERAND (RS3, insn, va_arg (args, int));
+-	  continue;
+-
+-	case '<':
+-	case '|':
+-	  INSERT_OPERAND (SHAMTW, insn, va_arg (args, int));
+-	  continue;
+-
+ 	case '>':
+ 	  INSERT_OPERAND (SHAMT, insn, va_arg (args, int));
+ 	  continue;
+@@ -1506,34 +1476,6 @@ load_const (int reg, expressionS *ep)
+     }
+ }
+ 
+-/* Immediate rotate left shift via right shift.  */
+-
+-static void
+-rotate_left (int rd, int rs, unsigned shamt, unsigned this_xlen)
+-{
+-  shamt = (this_xlen-1) & -shamt;
+-
+-  if (this_xlen == xlen)
+-    macro_build (NULL, "rori", "d,s,>", rd, rs, shamt);
+-  else if (this_xlen == 32)
+-    macro_build (NULL, "roriw", "d,s,<", rd, rs, shamt);
+-  else
+-    as_fatal (_("internal error: bad left shift xlen %d"), this_xlen);
+-}
+-
+-static void
+-funnel_left (int rd, int rs1, int rs3, unsigned shamt, unsigned this_xlen)
+-{
+-  shamt = (this_xlen-1) & -shamt;
+-
+-  if (this_xlen == xlen)
+-    macro_build (NULL, "fsri", "d,s,r,>", rd, rs3, rs1, shamt);
+-  else if (this_xlen == 32)
+-    macro_build (NULL, "fsriw", "d,s,r,<", rd, rs3, rs1, shamt);
+-  else
+-    as_fatal (_("internal error: bad left shift xlen %d"), this_xlen);
+-}
+-
+ /* Expand RISC-V Vector macros into one of more instructions.  */
+ 
+ static void
+@@ -1649,8 +1591,6 @@ macro (struct riscv_cl_insn *ip, expressionS *imm_expr,
+   int rd = (ip->insn_opcode >> OP_SH_RD) & OP_MASK_RD;
+   int rs1 = (ip->insn_opcode >> OP_SH_RS1) & OP_MASK_RS1;
+   int rs2 = (ip->insn_opcode >> OP_SH_RS2) & OP_MASK_RS2;
+-  int rs3 = (ip->insn_opcode >> OP_SH_RS3) & OP_MASK_RS3;
+-  int shamt = (ip->insn_opcode >> OP_SH_SHAMT) & OP_MASK_SHAMT;
+   int mask = ip->insn_mo->mask;
+ 
+   switch (mask)
+@@ -1659,14 +1599,6 @@ macro (struct riscv_cl_insn *ip, expressionS *imm_expr,
+       load_const (rd, imm_expr);
+       break;
+ 
+-    case M_RL:
+-      rotate_left (rd, rs1, shamt, ip->insn_mo->xlen_requirement ? ip->insn_mo->xlen_requirement/2 : xlen);
+-      break;
+-
+-    case M_FL:
+-      funnel_left (rd, rs1, rs3, shamt, ip->insn_mo->xlen_requirement ? ip->insn_mo->xlen_requirement/2 : xlen);
+-      break;
+-
+     case M_LA:
+     case M_LLA:
+       /* Load the address of a symbol into a register.  */
+diff --git a/gas/testsuite/gas/riscv/attribute-15-unratified.d b/gas/testsuite/gas/riscv/attribute-15-unratified.d
+index 4645762bd6..3d6c68ec2c 100644
+--- a/gas/testsuite/gas/riscv/attribute-15-unratified.d
++++ b/gas/testsuite/gas/riscv/attribute-15-unratified.d
+@@ -1,6 +1,6 @@
+-#as: -march-attr -march=rv32ibv_zfh_zba_zbb_zbc_zbe_zbf_zbm_zbp_zbr_zbs_zbt_zvamo_zvediv_zvlsseg_zvqmac
++#as: -march-attr -march=rv32iv_zfh_zba_zbb_zbc_zvamo_zvediv_zvlsseg_zvqmac
+ #readelf: -A
+ #source: empty.s
+ Attribute Section: riscv
+ File Attributes
+-  Tag_RISCV_arch: ".*_b0p92_v1p0_zfh0p1_zba0p92_zbb0p92_zbc0p92_zbe0p92_zbf0p92_zbm0p92_zbp0p92_zbr0p92_zbs0p92_zbt0p92_zvamo1p0_zvediv1p0_zvlsseg1p0_zvqmac1p0"
++  Tag_RISCV_arch: ".*_v1p0_zfh0p1_zba0p93_zbb0p93_zbc0p93_zvamo1p0_zvediv1p0_zvlsseg1p0_zvqmac1p0"
+diff --git a/gas/testsuite/gas/riscv/bitmanip-insns-32.d b/gas/testsuite/gas/riscv/bitmanip-insns-32.d
+index bda9d603af..b218f96e94 100644
+--- a/gas/testsuite/gas/riscv/bitmanip-insns-32.d
++++ b/gas/testsuite/gas/riscv/bitmanip-insns-32.d
+@@ -1,6 +1,6 @@
+-#as: -march=rv32i_zba_zbb
++#as: -march=rv32i_zba_zbb_zbc
+ #source: bitmanip-insns.s
+-#objdump: -dr
++#objdump: -dr -Mno-aliases
+ 
+ .*:[ 	]+file format .*
+ 
+@@ -8,28 +8,30 @@
+ Disassembly of section .text:
+ 
+ 0+000 <.text>:
++[ 	]+[0-9a-f]+:[ 	]+0805c533[ 	]+zext.h[ 	]+a0,a1
++[ 	]+[0-9a-f]+:[ 	]+6985d513[ 	]+rev8[ 	]+a0,a1
++[ 	]+[0-9a-f]+:[ 	]+2875d513[ 	]+orc.b[ 	]+a0,a1
+ [ 	]+[0-9a-f]+:[ 	]+20c5a533[ 	]+sh1add[ 	]+a0,a1,a2
+ [ 	]+[0-9a-f]+:[ 	]+20c5c533[ 	]+sh2add[ 	]+a0,a1,a2
+ [ 	]+[0-9a-f]+:[ 	]+20c5e533[ 	]+sh3add[ 	]+a0,a1,a2
+ [ 	]+[0-9a-f]+:[ 	]+60059513[ 	]+clz[ 	]+a0,a1
+ [ 	]+[0-9a-f]+:[ 	]+60159513[ 	]+ctz[ 	]+a0,a1
+-[ 	]+[0-9a-f]+:[ 	]+60259513[ 	]+pcnt[ 	]+a0,a1
++[ 	]+[0-9a-f]+:[ 	]+60259513[ 	]+cpop[ 	]+a0,a1
+ [ 	]+[0-9a-f]+:[ 	]+0ac5c533[ 	]+min[ 	]+a0,a1,a2
+ [ 	]+[0-9a-f]+:[ 	]+0ac5e533[ 	]+max[ 	]+a0,a1,a2
+ [ 	]+[0-9a-f]+:[ 	]+0ac5d533[ 	]+minu[ 	]+a0,a1,a2
+ [ 	]+[0-9a-f]+:[ 	]+0ac5f533[ 	]+maxu[ 	]+a0,a1,a2
++[ 	]+[0-9a-f]+:[ 	]+60459513[ 	]+sext.b[ 	]+a0,a1
++[ 	]+[0-9a-f]+:[ 	]+60559513[ 	]+sext.h[ 	]+a0,a1
+ [ 	]+[0-9a-f]+:[ 	]+40c5f533[ 	]+andn[ 	]+a0,a1,a2
+ [ 	]+[0-9a-f]+:[ 	]+40c5e533[ 	]+orn[ 	]+a0,a1,a2
+ [ 	]+[0-9a-f]+:[ 	]+00c5c533[ 	]+xor[ 	]+a0,a1,a2
+-[ 	]+[0-9a-f]+:[ 	]+61f5d513[ 	]+rori[ 	]+a0,a1,0x1f
+-[ 	]+[0-9a-f]+:[ 	]+6015d513[ 	]+rori[ 	]+a0,a1,0x1
+-[ 	]+[0-9a-f]+:[ 	]+60c59533[ 	]+rol[ 	]+a0,a1,a2
+-[ 	]+[0-9a-f]+:[ 	]+61f5d513[ 	]+rori[ 	]+a0,a1,0x1f
+-[ 	]+[0-9a-f]+:[ 	]+6015d513[ 	]+rori[ 	]+a0,a1,0x1
+-[ 	]+[0-9a-f]+:[ 	]+6015d513[ 	]+rori[ 	]+a0,a1,0x1
++[ 	]+[0-9a-f]+:[ 	]+6005d513[ 	]+rori[ 	]+a0,a1,0x0
+ [ 	]+[0-9a-f]+:[ 	]+61f5d513[ 	]+rori[ 	]+a0,a1,0x1f
+ [ 	]+[0-9a-f]+:[ 	]+60c5d533[ 	]+ror[ 	]+a0,a1,a2
+-[ 	]+[0-9a-f]+:[ 	]+6015d513[ 	]+rori[ 	]+a0,a1,0x1
++[ 	]+[0-9a-f]+:[ 	]+6005d513[ 	]+rori[ 	]+a0,a1,0x0
+ [ 	]+[0-9a-f]+:[ 	]+61f5d513[ 	]+rori[ 	]+a0,a1,0x1f
+-[ 	]+[0-9a-f]+:[ 	]+60459513[ 	]+sext.b[ 	]+a0,a1
+-[ 	]+[0-9a-f]+:[ 	]+60559513[ 	]+sext.h[ 	]+a0,a1
++[ 	]+[0-9a-f]+:[ 	]+60c59533[ 	]+rol[ 	]+a0,a1,a2
++[ 	]+[0-9a-f]+:[ 	]+0ac59533[ 	]+clmul[ 	]+a0,a1,a2
++[ 	]+[0-9a-f]+:[ 	]+0ac5b533[ 	]+clmulh[ 	]+a0,a1,a2
++[ 	]+[0-9a-f]+:[ 	]+0ac5a533[ 	]+clmulr[ 	]+a0,a1,a2
+diff --git a/gas/testsuite/gas/riscv/bitmanip-insns-64.d b/gas/testsuite/gas/riscv/bitmanip-insns-64.d
+index 843bb319be..9914f3e557 100644
+--- a/gas/testsuite/gas/riscv/bitmanip-insns-64.d
++++ b/gas/testsuite/gas/riscv/bitmanip-insns-64.d
+@@ -1,6 +1,6 @@
+-#as: -march=rv64i_zba_zbb -defsym __64_bit__=1
++#as: -march=rv64i_zba_zbb_zbc -defsym __64_bit__=1
+ #source: bitmanip-insns.s
+-#objdump: -dr
++#objdump: -dr -Mno-aliases
+ 
+ .*:[ 	]+file format .*
+ 
+@@ -8,51 +8,48 @@
+ Disassembly of section .text:
+ 
+ 0+000 <.text>:
++[ 	]+[0-9a-f]+:[ 	]+0805c53b[ 	]+zext.h[ 	]+a0,a1
++[ 	]+[0-9a-f]+:[ 	]+6b85d513[ 	]+rev8[ 	]+a0,a1
++[ 	]+[0-9a-f]+:[ 	]+2875d513[ 	]+orc.b[ 	]+a0,a1
++[ 	]+[0-9a-f]+:[ 	]+0805853b[ 	]+add.uw[ 	]+a0,a1,zero
+ [ 	]+[0-9a-f]+:[ 	]+20c5a533[ 	]+sh1add[ 	]+a0,a1,a2
+ [ 	]+[0-9a-f]+:[ 	]+20c5c533[ 	]+sh2add[ 	]+a0,a1,a2
+ [ 	]+[0-9a-f]+:[ 	]+20c5e533[ 	]+sh3add[ 	]+a0,a1,a2
+-[ 	]+[0-9a-f]+:[ 	]+0815951b[ 	]+slliu.w[ 	]+a0,a1,0x1
+-[ 	]+[0-9a-f]+:[ 	]+0bf5951b[ 	]+slliu.w[ 	]+a0,a1,0x3f
+-[ 	]+[0-9a-f]+:[ 	]+08c5853b[ 	]+addu.w[ 	]+a0,a1,a2
+-[ 	]+[0-9a-f]+:[ 	]+20c5a53b[ 	]+sh1addu.w[ 	]+a0,a1,a2
+-[ 	]+[0-9a-f]+:[ 	]+20c5c53b[ 	]+sh2addu.w[ 	]+a0,a1,a2
+-[ 	]+[0-9a-f]+:[ 	]+20c5e53b[ 	]+sh3addu.w[ 	]+a0,a1,a2
++[ 	]+[0-9a-f]+:[ 	]+20c5a53b[ 	]+sh1add.uw[ 	]+a0,a1,a2
++[ 	]+[0-9a-f]+:[ 	]+20c5c53b[ 	]+sh2add.uw[ 	]+a0,a1,a2
++[ 	]+[0-9a-f]+:[ 	]+20c5e53b[ 	]+sh3add.uw[ 	]+a0,a1,a2
++[ 	]+[0-9a-f]+:[ 	]+08c5853b[ 	]+add.uw[ 	]+a0,a1,a2
++[ 	]+[0-9a-f]+:[ 	]+0805951b[ 	]+slli.uw[ 	]+a0,a1,0x0
++[ 	]+[0-9a-f]+:[ 	]+0bf5951b[ 	]+slli.uw[ 	]+a0,a1,0x3f
+ [ 	]+[0-9a-f]+:[ 	]+60059513[ 	]+clz[ 	]+a0,a1
+ [ 	]+[0-9a-f]+:[ 	]+60159513[ 	]+ctz[ 	]+a0,a1
+-[ 	]+[0-9a-f]+:[ 	]+60259513[ 	]+pcnt[ 	]+a0,a1
++[ 	]+[0-9a-f]+:[ 	]+60259513[ 	]+cpop[ 	]+a0,a1
+ [ 	]+[0-9a-f]+:[ 	]+0ac5c533[ 	]+min[ 	]+a0,a1,a2
+ [ 	]+[0-9a-f]+:[ 	]+0ac5e533[ 	]+max[ 	]+a0,a1,a2
+ [ 	]+[0-9a-f]+:[ 	]+0ac5d533[ 	]+minu[ 	]+a0,a1,a2
+ [ 	]+[0-9a-f]+:[ 	]+0ac5f533[ 	]+maxu[ 	]+a0,a1,a2
++[ 	]+[0-9a-f]+:[ 	]+60459513[ 	]+sext.b[ 	]+a0,a1
++[ 	]+[0-9a-f]+:[ 	]+60559513[ 	]+sext.h[ 	]+a0,a1
+ [ 	]+[0-9a-f]+:[ 	]+40c5f533[ 	]+andn[ 	]+a0,a1,a2
+ [ 	]+[0-9a-f]+:[ 	]+40c5e533[ 	]+orn[ 	]+a0,a1,a2
+ [ 	]+[0-9a-f]+:[ 	]+00c5c533[ 	]+xor[ 	]+a0,a1,a2
+-[ 	]+[0-9a-f]+:[ 	]+63f5d513[ 	]+rori[ 	]+a0,a1,0x3f
+-[ 	]+[0-9a-f]+:[ 	]+6215d513[ 	]+rori[ 	]+a0,a1,0x21
+-[ 	]+[0-9a-f]+:[ 	]+60c59533[ 	]+rol[ 	]+a0,a1,a2
+-[ 	]+[0-9a-f]+:[ 	]+63f5d513[ 	]+rori[ 	]+a0,a1,0x3f
+-[ 	]+[0-9a-f]+:[ 	]+6215d513[ 	]+rori[ 	]+a0,a1,0x21
+-[ 	]+[0-9a-f]+:[ 	]+6015d513[ 	]+rori[ 	]+a0,a1,0x1
++[ 	]+[0-9a-f]+:[ 	]+6005d513[ 	]+rori[ 	]+a0,a1,0x0
+ [ 	]+[0-9a-f]+:[ 	]+61f5d513[ 	]+rori[ 	]+a0,a1,0x1f
+ [ 	]+[0-9a-f]+:[ 	]+60c5d533[ 	]+ror[ 	]+a0,a1,a2
+-[ 	]+[0-9a-f]+:[ 	]+6015d513[ 	]+rori[ 	]+a0,a1,0x1
++[ 	]+[0-9a-f]+:[ 	]+6005d513[ 	]+rori[ 	]+a0,a1,0x0
+ [ 	]+[0-9a-f]+:[ 	]+61f5d513[ 	]+rori[ 	]+a0,a1,0x1f
+-[ 	]+[0-9a-f]+:[ 	]+60459513[ 	]+sext.b[ 	]+a0,a1
+-[ 	]+[0-9a-f]+:[ 	]+60559513[ 	]+sext.h[ 	]+a0,a1
++[ 	]+[0-9a-f]+:[ 	]+60c59533[ 	]+rol[ 	]+a0,a1,a2
+ [ 	]+[0-9a-f]+:[ 	]+6005951b[ 	]+clzw[ 	]+a0,a1
+ [ 	]+[0-9a-f]+:[ 	]+6015951b[ 	]+ctzw[ 	]+a0,a1
+-[ 	]+[0-9a-f]+:[ 	]+6025951b[ 	]+pcntw[ 	]+a0,a1
+-[ 	]+[0-9a-f]+:[ 	]+6015d513[ 	]+rori[ 	]+a0,a1,0x1
+-[ 	]+[0-9a-f]+:[ 	]+6015d513[ 	]+rori[ 	]+a0,a1,0x1
++[ 	]+[0-9a-f]+:[ 	]+6025951b[ 	]+cpopw[ 	]+a0,a1
+ [ 	]+[0-9a-f]+:[ 	]+63f5d513[ 	]+rori[ 	]+a0,a1,0x3f
+ [ 	]+[0-9a-f]+:[ 	]+63f5d513[ 	]+rori[ 	]+a0,a1,0x3f
++[ 	]+[0-9a-f]+:[ 	]+6005d51b[ 	]+roriw[ 	]+a0,a1,0x0
+ [ 	]+[0-9a-f]+:[ 	]+61f5d51b[ 	]+roriw[ 	]+a0,a1,0x1f
+-[ 	]+[0-9a-f]+:[ 	]+6015d51b[ 	]+roriw[ 	]+a0,a1,0x1
+-[ 	]+[0-9a-f]+:[ 	]+6015d51b[ 	]+roriw[ 	]+a0,a1,0x1
+-[ 	]+[0-9a-f]+:[ 	]+61f5d51b[ 	]+roriw[ 	]+a0,a1,0x1f
+-[ 	]+[0-9a-f]+:[ 	]+60c5953b[ 	]+rolw[ 	]+a0,a1,a2
+-[ 	]+[0-9a-f]+:[ 	]+61f5d51b[ 	]+roriw[ 	]+a0,a1,0x1f
+-[ 	]+[0-9a-f]+:[ 	]+6015d51b[ 	]+roriw[ 	]+a0,a1,0x1
+ [ 	]+[0-9a-f]+:[ 	]+60c5d53b[ 	]+rorw[ 	]+a0,a1,a2
+-[ 	]+[0-9a-f]+:[ 	]+6015d51b[ 	]+roriw[ 	]+a0,a1,0x1
++[ 	]+[0-9a-f]+:[ 	]+6005d51b[ 	]+roriw[ 	]+a0,a1,0x0
+ [ 	]+[0-9a-f]+:[ 	]+61f5d51b[ 	]+roriw[ 	]+a0,a1,0x1f
++[ 	]+[0-9a-f]+:[ 	]+60c5953b[ 	]+rolw[ 	]+a0,a1,a2
++[ 	]+[0-9a-f]+:[ 	]+0ac59533[ 	]+clmul[ 	]+a0,a1,a2
++[ 	]+[0-9a-f]+:[ 	]+0ac5b533[ 	]+clmulh[ 	]+a0,a1,a2
++[ 	]+[0-9a-f]+:[ 	]+0ac5a533[ 	]+clmulr[ 	]+a0,a1,a2
+diff --git a/gas/testsuite/gas/riscv/bitmanip-insns-pseudo-32.d b/gas/testsuite/gas/riscv/bitmanip-insns-pseudo-32.d
+deleted file mode 100644
+index b0cdb16efc..0000000000
+--- a/gas/testsuite/gas/riscv/bitmanip-insns-pseudo-32.d
++++ /dev/null
+@@ -1,61 +0,0 @@
+-#as: -march=rv32ib
+-#source: bitmanip-insns-pseudo.s
+-#objdump: -dr
+-
+-.*:[ 	]+file format .*
+-
+-
+-Disassembly of section .text:
+-
+-0+000 <.text>:
+-[ 	]+[0-9a-f]+:[ 	]+0805c533[ 	]+zext.h[ 	]+a0,a1
+-[ 	]+[0-9a-f]+:[ 	]+6815d513[ 	]+rev.p[ 	]+a0,a1
+-[ 	]+[0-9a-f]+:[ 	]+6825d513[ 	]+rev2.n[ 	]+a0,a1
+-[ 	]+[0-9a-f]+:[ 	]+6835d513[ 	]+rev.n[ 	]+a0,a1
+-[ 	]+[0-9a-f]+:[ 	]+6845d513[ 	]+rev4.b[ 	]+a0,a1
+-[ 	]+[0-9a-f]+:[ 	]+6865d513[ 	]+rev2.b[ 	]+a0,a1
+-[ 	]+[0-9a-f]+:[ 	]+6875d513[ 	]+rev.b[ 	]+a0,a1
+-[ 	]+[0-9a-f]+:[ 	]+6885d513[ 	]+rev8.h[ 	]+a0,a1
+-[ 	]+[0-9a-f]+:[ 	]+68c5d513[ 	]+rev4.h[ 	]+a0,a1
+-[ 	]+[0-9a-f]+:[ 	]+68e5d513[ 	]+rev2.h[ 	]+a0,a1
+-[ 	]+[0-9a-f]+:[ 	]+68f5d513[ 	]+rev.h[ 	]+a0,a1
+-[ 	]+[0-9a-f]+:[ 	]+6905d513[ 	]+rev16[ 	]+a0,a1
+-[ 	]+[0-9a-f]+:[ 	]+6985d513[ 	]+rev8[ 	]+a0,a1
+-[ 	]+[0-9a-f]+:[ 	]+69c5d513[ 	]+rev4[ 	]+a0,a1
+-[ 	]+[0-9a-f]+:[ 	]+69e5d513[ 	]+rev2[ 	]+a0,a1
+-[ 	]+[0-9a-f]+:[ 	]+69f5d513[ 	]+rev[ 	]+a0,a1
+-[ 	]+[0-9a-f]+:[ 	]+2815d513[ 	]+orc.p[ 	]+a0,a1
+-[ 	]+[0-9a-f]+:[ 	]+2825d513[ 	]+orc2.n[ 	]+a0,a1
+-[ 	]+[0-9a-f]+:[ 	]+2835d513[ 	]+orc.n[ 	]+a0,a1
+-[ 	]+[0-9a-f]+:[ 	]+2845d513[ 	]+orc4.b[ 	]+a0,a1
+-[ 	]+[0-9a-f]+:[ 	]+2865d513[ 	]+orc2.b[ 	]+a0,a1
+-[ 	]+[0-9a-f]+:[ 	]+2875d513[ 	]+orc.b[ 	]+a0,a1
+-[ 	]+[0-9a-f]+:[ 	]+2885d513[ 	]+orc8.h[ 	]+a0,a1
+-[ 	]+[0-9a-f]+:[ 	]+28c5d513[ 	]+orc4.h[ 	]+a0,a1
+-[ 	]+[0-9a-f]+:[ 	]+28e5d513[ 	]+orc2.h[ 	]+a0,a1
+-[ 	]+[0-9a-f]+:[ 	]+28f5d513[ 	]+orc.h[ 	]+a0,a1
+-[ 	]+[0-9a-f]+:[ 	]+2905d513[ 	]+orc16[ 	]+a0,a1
+-[ 	]+[0-9a-f]+:[ 	]+2985d513[ 	]+orc8[ 	]+a0,a1
+-[ 	]+[0-9a-f]+:[ 	]+29c5d513[ 	]+orc4[ 	]+a0,a1
+-[ 	]+[0-9a-f]+:[ 	]+29e5d513[ 	]+orc2[ 	]+a0,a1
+-[ 	]+[0-9a-f]+:[ 	]+29f5d513[ 	]+orc[ 	]+a0,a1
+-[ 	]+[0-9a-f]+:[ 	]+08159513[ 	]+zip.n[ 	]+a0,a1
+-[ 	]+[0-9a-f]+:[ 	]+08259513[ 	]+zip2.b[ 	]+a0,a1
+-[ 	]+[0-9a-f]+:[ 	]+08359513[ 	]+zip.b[ 	]+a0,a1
+-[ 	]+[0-9a-f]+:[ 	]+08459513[ 	]+zip4.h[ 	]+a0,a1
+-[ 	]+[0-9a-f]+:[ 	]+08659513[ 	]+zip2.h[ 	]+a0,a1
+-[ 	]+[0-9a-f]+:[ 	]+08759513[ 	]+zip.h[ 	]+a0,a1
+-[ 	]+[0-9a-f]+:[ 	]+08859513[ 	]+zip8[ 	]+a0,a1
+-[ 	]+[0-9a-f]+:[ 	]+08c59513[ 	]+zip4[ 	]+a0,a1
+-[ 	]+[0-9a-f]+:[ 	]+08e59513[ 	]+zip2[ 	]+a0,a1
+-[ 	]+[0-9a-f]+:[ 	]+08f59513[ 	]+zip[ 	]+a0,a1
+-[ 	]+[0-9a-f]+:[ 	]+0815d513[ 	]+unzip.n[ 	]+a0,a1
+-[ 	]+[0-9a-f]+:[ 	]+0825d513[ 	]+unzip2.b[ 	]+a0,a1
+-[ 	]+[0-9a-f]+:[ 	]+0835d513[ 	]+unzip.b[ 	]+a0,a1
+-[ 	]+[0-9a-f]+:[ 	]+0845d513[ 	]+unzip4.h[ 	]+a0,a1
+-[ 	]+[0-9a-f]+:[ 	]+0865d513[ 	]+unzip2.h[ 	]+a0,a1
+-[ 	]+[0-9a-f]+:[ 	]+0875d513[ 	]+unzip.h[ 	]+a0,a1
+-[ 	]+[0-9a-f]+:[ 	]+0885d513[ 	]+unzip8[ 	]+a0,a1
+-[ 	]+[0-9a-f]+:[ 	]+08c5d513[ 	]+unzip4[ 	]+a0,a1
+-[ 	]+[0-9a-f]+:[ 	]+08e5d513[ 	]+unzip2[ 	]+a0,a1
+-[ 	]+[0-9a-f]+:[ 	]+08f5d513[ 	]+unzip[ 	]+a0,a1
+diff --git a/gas/testsuite/gas/riscv/bitmanip-insns-pseudo-64.d b/gas/testsuite/gas/riscv/bitmanip-insns-pseudo-64.d
+deleted file mode 100644
+index 23b8b7b5a6..0000000000
+--- a/gas/testsuite/gas/riscv/bitmanip-insns-pseudo-64.d
++++ /dev/null
+@@ -1,84 +0,0 @@
+-#as: -march=rv64ib -defsym __64_bit__=1
+-#source: bitmanip-insns-pseudo.s
+-#objdump: -dr
+-
+-.*:[ 	]+file format .*
+-
+-
+-Disassembly of section .text:
+-
+-0+000 <.text>:
+-[ 	]+[0-9a-f]+:[ 	]+0805c53b[ 	]+zext.h[ 	]+a0,a1
+-[ 	]+[0-9a-f]+:[ 	]+6815d513[ 	]+rev.p[ 	]+a0,a1
+-[ 	]+[0-9a-f]+:[ 	]+6825d513[ 	]+rev2.n[ 	]+a0,a1
+-[ 	]+[0-9a-f]+:[ 	]+6835d513[ 	]+rev.n[ 	]+a0,a1
+-[ 	]+[0-9a-f]+:[ 	]+6845d513[ 	]+rev4.b[ 	]+a0,a1
+-[ 	]+[0-9a-f]+:[ 	]+6865d513[ 	]+rev2.b[ 	]+a0,a1
+-[ 	]+[0-9a-f]+:[ 	]+6875d513[ 	]+rev.b[ 	]+a0,a1
+-[ 	]+[0-9a-f]+:[ 	]+6885d513[ 	]+rev8.h[ 	]+a0,a1
+-[ 	]+[0-9a-f]+:[ 	]+68c5d513[ 	]+rev4.h[ 	]+a0,a1
+-[ 	]+[0-9a-f]+:[ 	]+68e5d513[ 	]+rev2.h[ 	]+a0,a1
+-[ 	]+[0-9a-f]+:[ 	]+68f5d513[ 	]+rev.h[ 	]+a0,a1
+-[ 	]+[0-9a-f]+:[ 	]+6b05d513[ 	]+rev16[ 	]+a0,a1
+-[ 	]+[0-9a-f]+:[ 	]+6b85d513[ 	]+rev8[ 	]+a0,a1
+-[ 	]+[0-9a-f]+:[ 	]+6bc5d513[ 	]+rev4[ 	]+a0,a1
+-[ 	]+[0-9a-f]+:[ 	]+6be5d513[ 	]+rev2[ 	]+a0,a1
+-[ 	]+[0-9a-f]+:[ 	]+6bf5d513[ 	]+rev[ 	]+a0,a1
+-[ 	]+[0-9a-f]+:[ 	]+2815d513[ 	]+orc.p[ 	]+a0,a1
+-[ 	]+[0-9a-f]+:[ 	]+2825d513[ 	]+orc2.n[ 	]+a0,a1
+-[ 	]+[0-9a-f]+:[ 	]+2835d513[ 	]+orc.n[ 	]+a0,a1
+-[ 	]+[0-9a-f]+:[ 	]+2845d513[ 	]+orc4.b[ 	]+a0,a1
+-[ 	]+[0-9a-f]+:[ 	]+2865d513[ 	]+orc2.b[ 	]+a0,a1
+-[ 	]+[0-9a-f]+:[ 	]+2875d513[ 	]+orc.b[ 	]+a0,a1
+-[ 	]+[0-9a-f]+:[ 	]+2885d513[ 	]+orc8.h[ 	]+a0,a1
+-[ 	]+[0-9a-f]+:[ 	]+28c5d513[ 	]+orc4.h[ 	]+a0,a1
+-[ 	]+[0-9a-f]+:[ 	]+28e5d513[ 	]+orc2.h[ 	]+a0,a1
+-[ 	]+[0-9a-f]+:[ 	]+28f5d513[ 	]+orc.h[ 	]+a0,a1
+-[ 	]+[0-9a-f]+:[ 	]+2b05d513[ 	]+orc16[ 	]+a0,a1
+-[ 	]+[0-9a-f]+:[ 	]+2b85d513[ 	]+orc8[ 	]+a0,a1
+-[ 	]+[0-9a-f]+:[ 	]+2bc5d513[ 	]+orc4[ 	]+a0,a1
+-[ 	]+[0-9a-f]+:[ 	]+2be5d513[ 	]+orc2[ 	]+a0,a1
+-[ 	]+[0-9a-f]+:[ 	]+2bf5d513[ 	]+orc[ 	]+a0,a1
+-[ 	]+[0-9a-f]+:[ 	]+08159513[ 	]+zip.n[ 	]+a0,a1
+-[ 	]+[0-9a-f]+:[ 	]+08259513[ 	]+zip2.b[ 	]+a0,a1
+-[ 	]+[0-9a-f]+:[ 	]+08359513[ 	]+zip.b[ 	]+a0,a1
+-[ 	]+[0-9a-f]+:[ 	]+08459513[ 	]+zip4.h[ 	]+a0,a1
+-[ 	]+[0-9a-f]+:[ 	]+08659513[ 	]+zip2.h[ 	]+a0,a1
+-[ 	]+[0-9a-f]+:[ 	]+08759513[ 	]+zip.h[ 	]+a0,a1
+-[ 	]+[0-9a-f]+:[ 	]+09859513[ 	]+zip8[ 	]+a0,a1
+-[ 	]+[0-9a-f]+:[ 	]+09c59513[ 	]+zip4[ 	]+a0,a1
+-[ 	]+[0-9a-f]+:[ 	]+09e59513[ 	]+zip2[ 	]+a0,a1
+-[ 	]+[0-9a-f]+:[ 	]+09f59513[ 	]+zip[ 	]+a0,a1
+-[ 	]+[0-9a-f]+:[ 	]+0815d513[ 	]+unzip.n[ 	]+a0,a1
+-[ 	]+[0-9a-f]+:[ 	]+0825d513[ 	]+unzip2.b[ 	]+a0,a1
+-[ 	]+[0-9a-f]+:[ 	]+0835d513[ 	]+unzip.b[ 	]+a0,a1
+-[ 	]+[0-9a-f]+:[ 	]+0845d513[ 	]+unzip4.h[ 	]+a0,a1
+-[ 	]+[0-9a-f]+:[ 	]+0865d513[ 	]+unzip2.h[ 	]+a0,a1
+-[ 	]+[0-9a-f]+:[ 	]+0875d513[ 	]+unzip.h[ 	]+a0,a1
+-[ 	]+[0-9a-f]+:[ 	]+0985d513[ 	]+unzip8[ 	]+a0,a1
+-[ 	]+[0-9a-f]+:[ 	]+09c5d513[ 	]+unzip4[ 	]+a0,a1
+-[ 	]+[0-9a-f]+:[ 	]+09e5d513[ 	]+unzip2[ 	]+a0,a1
+-[ 	]+[0-9a-f]+:[ 	]+09f5d513[ 	]+unzip[ 	]+a0,a1
+-[ 	]+[0-9a-f]+:[ 	]+0805853b[ 	]+zext.w[ 	]+a0,a1
+-[ 	]+[0-9a-f]+:[ 	]+6905d513[ 	]+rev16.w[ 	]+a0,a1
+-[ 	]+[0-9a-f]+:[ 	]+6985d513[ 	]+rev8.w[ 	]+a0,a1
+-[ 	]+[0-9a-f]+:[ 	]+69c5d513[ 	]+rev4.w[ 	]+a0,a1
+-[ 	]+[0-9a-f]+:[ 	]+69e5d513[ 	]+rev2.w[ 	]+a0,a1
+-[ 	]+[0-9a-f]+:[ 	]+69f5d513[ 	]+rev.w[ 	]+a0,a1
+-[ 	]+[0-9a-f]+:[ 	]+6a05d513[ 	]+rev32[ 	]+a0,a1
+-[ 	]+[0-9a-f]+:[ 	]+2905d513[ 	]+orc16.w[ 	]+a0,a1
+-[ 	]+[0-9a-f]+:[ 	]+2985d513[ 	]+orc8.w[ 	]+a0,a1
+-[ 	]+[0-9a-f]+:[ 	]+29c5d513[ 	]+orc4.w[ 	]+a0,a1
+-[ 	]+[0-9a-f]+:[ 	]+29e5d513[ 	]+orc2.w[ 	]+a0,a1
+-[ 	]+[0-9a-f]+:[ 	]+29f5d513[ 	]+orc.w[ 	]+a0,a1
+-[ 	]+[0-9a-f]+:[ 	]+2a05d513[ 	]+orc32[ 	]+a0,a1
+-[ 	]+[0-9a-f]+:[ 	]+08859513[ 	]+zip8.w[ 	]+a0,a1
+-[ 	]+[0-9a-f]+:[ 	]+08c59513[ 	]+zip4.w[ 	]+a0,a1
+-[ 	]+[0-9a-f]+:[ 	]+08e59513[ 	]+zip2.w[ 	]+a0,a1
+-[ 	]+[0-9a-f]+:[ 	]+08f59513[ 	]+zip.w[ 	]+a0,a1
+-[ 	]+[0-9a-f]+:[ 	]+09059513[ 	]+zip16[ 	]+a0,a1
+-[ 	]+[0-9a-f]+:[ 	]+0885d513[ 	]+unzip8.w[ 	]+a0,a1
+-[ 	]+[0-9a-f]+:[ 	]+08c5d513[ 	]+unzip4.w[ 	]+a0,a1
+-[ 	]+[0-9a-f]+:[ 	]+08e5d513[ 	]+unzip2.w[ 	]+a0,a1
+-[ 	]+[0-9a-f]+:[ 	]+08f5d513[ 	]+unzip.w[ 	]+a0,a1
+-[ 	]+[0-9a-f]+:[ 	]+0905d513[ 	]+unzip16[ 	]+a0,a1
+diff --git a/gas/testsuite/gas/riscv/bitmanip-insns-pseudo-noalias-32.d b/gas/testsuite/gas/riscv/bitmanip-insns-pseudo-noalias-32.d
+deleted file mode 100644
+index 91190c8b6a..0000000000
+--- a/gas/testsuite/gas/riscv/bitmanip-insns-pseudo-noalias-32.d
++++ /dev/null
+@@ -1,61 +0,0 @@
+-#as: -march=rv32ib
+-#source: bitmanip-insns-pseudo.s
+-#objdump: -dr -Mno-aliases
+-
+-.*:[ 	]+file format .*
+-
+-
+-Disassembly of section .text:
+-
+-0+000 <.text>:
+-[ 	]+[0-9a-f]+:[ 	]+0805c533[ 	]+pack[ 	]+a0,a1,zero
+-[ 	]+[0-9a-f]+:[ 	]+6815d513[ 	]+grevi[ 	]+a0,a1,0x1
+-[ 	]+[0-9a-f]+:[ 	]+6825d513[ 	]+grevi[ 	]+a0,a1,0x2
+-[ 	]+[0-9a-f]+:[ 	]+6835d513[ 	]+grevi[ 	]+a0,a1,0x3
+-[ 	]+[0-9a-f]+:[ 	]+6845d513[ 	]+grevi[ 	]+a0,a1,0x4
+-[ 	]+[0-9a-f]+:[ 	]+6865d513[ 	]+grevi[ 	]+a0,a1,0x6
+-[ 	]+[0-9a-f]+:[ 	]+6875d513[ 	]+grevi[ 	]+a0,a1,0x7
+-[ 	]+[0-9a-f]+:[ 	]+6885d513[ 	]+grevi[ 	]+a0,a1,0x8
+-[ 	]+[0-9a-f]+:[ 	]+68c5d513[ 	]+grevi[ 	]+a0,a1,0xc
+-[ 	]+[0-9a-f]+:[ 	]+68e5d513[ 	]+grevi[ 	]+a0,a1,0xe
+-[ 	]+[0-9a-f]+:[ 	]+68f5d513[ 	]+grevi[ 	]+a0,a1,0xf
+-[ 	]+[0-9a-f]+:[ 	]+6905d513[ 	]+grevi[ 	]+a0,a1,0x10
+-[ 	]+[0-9a-f]+:[ 	]+6985d513[ 	]+grevi[ 	]+a0,a1,0x18
+-[ 	]+[0-9a-f]+:[ 	]+69c5d513[ 	]+grevi[ 	]+a0,a1,0x1c
+-[ 	]+[0-9a-f]+:[ 	]+69e5d513[ 	]+grevi[ 	]+a0,a1,0x1e
+-[ 	]+[0-9a-f]+:[ 	]+69f5d513[ 	]+grevi[ 	]+a0,a1,0x1f
+-[ 	]+[0-9a-f]+:[ 	]+2815d513[ 	]+gorci[ 	]+a0,a1,0x1
+-[ 	]+[0-9a-f]+:[ 	]+2825d513[ 	]+gorci[ 	]+a0,a1,0x2
+-[ 	]+[0-9a-f]+:[ 	]+2835d513[ 	]+gorci[ 	]+a0,a1,0x3
+-[ 	]+[0-9a-f]+:[ 	]+2845d513[ 	]+gorci[ 	]+a0,a1,0x4
+-[ 	]+[0-9a-f]+:[ 	]+2865d513[ 	]+gorci[ 	]+a0,a1,0x6
+-[ 	]+[0-9a-f]+:[ 	]+2875d513[ 	]+gorci[ 	]+a0,a1,0x7
+-[ 	]+[0-9a-f]+:[ 	]+2885d513[ 	]+gorci[ 	]+a0,a1,0x8
+-[ 	]+[0-9a-f]+:[ 	]+28c5d513[ 	]+gorci[ 	]+a0,a1,0xc
+-[ 	]+[0-9a-f]+:[ 	]+28e5d513[ 	]+gorci[ 	]+a0,a1,0xe
+-[ 	]+[0-9a-f]+:[ 	]+28f5d513[ 	]+gorci[ 	]+a0,a1,0xf
+-[ 	]+[0-9a-f]+:[ 	]+2905d513[ 	]+gorci[ 	]+a0,a1,0x10
+-[ 	]+[0-9a-f]+:[ 	]+2985d513[ 	]+gorci[ 	]+a0,a1,0x18
+-[ 	]+[0-9a-f]+:[ 	]+29c5d513[ 	]+gorci[ 	]+a0,a1,0x1c
+-[ 	]+[0-9a-f]+:[ 	]+29e5d513[ 	]+gorci[ 	]+a0,a1,0x1e
+-[ 	]+[0-9a-f]+:[ 	]+29f5d513[ 	]+gorci[ 	]+a0,a1,0x1f
+-[ 	]+[0-9a-f]+:[ 	]+08159513[ 	]+shfli[ 	]+a0,a1,0x1
+-[ 	]+[0-9a-f]+:[ 	]+08259513[ 	]+shfli[ 	]+a0,a1,0x2
+-[ 	]+[0-9a-f]+:[ 	]+08359513[ 	]+shfli[ 	]+a0,a1,0x3
+-[ 	]+[0-9a-f]+:[ 	]+08459513[ 	]+shfli[ 	]+a0,a1,0x4
+-[ 	]+[0-9a-f]+:[ 	]+08659513[ 	]+shfli[ 	]+a0,a1,0x6
+-[ 	]+[0-9a-f]+:[ 	]+08759513[ 	]+shfli[ 	]+a0,a1,0x7
+-[ 	]+[0-9a-f]+:[ 	]+08859513[ 	]+shfli[ 	]+a0,a1,0x8
+-[ 	]+[0-9a-f]+:[ 	]+08c59513[ 	]+shfli[ 	]+a0,a1,0xc
+-[ 	]+[0-9a-f]+:[ 	]+08e59513[ 	]+shfli[ 	]+a0,a1,0xe
+-[ 	]+[0-9a-f]+:[ 	]+08f59513[ 	]+shfli[ 	]+a0,a1,0xf
+-[ 	]+[0-9a-f]+:[ 	]+0815d513[ 	]+unshfli[ 	]+a0,a1,0x1
+-[ 	]+[0-9a-f]+:[ 	]+0825d513[ 	]+unshfli[ 	]+a0,a1,0x2
+-[ 	]+[0-9a-f]+:[ 	]+0835d513[ 	]+unshfli[ 	]+a0,a1,0x3
+-[ 	]+[0-9a-f]+:[ 	]+0845d513[ 	]+unshfli[ 	]+a0,a1,0x4
+-[ 	]+[0-9a-f]+:[ 	]+0865d513[ 	]+unshfli[ 	]+a0,a1,0x6
+-[ 	]+[0-9a-f]+:[ 	]+0875d513[ 	]+unshfli[ 	]+a0,a1,0x7
+-[ 	]+[0-9a-f]+:[ 	]+0885d513[ 	]+unshfli[ 	]+a0,a1,0x8
+-[ 	]+[0-9a-f]+:[ 	]+08c5d513[ 	]+unshfli[ 	]+a0,a1,0xc
+-[ 	]+[0-9a-f]+:[ 	]+08e5d513[ 	]+unshfli[ 	]+a0,a1,0xe
+-[ 	]+[0-9a-f]+:[ 	]+08f5d513[ 	]+unshfli[ 	]+a0,a1,0xf
+diff --git a/gas/testsuite/gas/riscv/bitmanip-insns-pseudo-noalias-64.d b/gas/testsuite/gas/riscv/bitmanip-insns-pseudo-noalias-64.d
+deleted file mode 100644
+index 187c487e7c..0000000000
+--- a/gas/testsuite/gas/riscv/bitmanip-insns-pseudo-noalias-64.d
++++ /dev/null
+@@ -1,84 +0,0 @@
+-#as: -march=rv64ib -defsym __64_bit__=1
+-#source: bitmanip-insns-pseudo.s
+-#objdump: -dr -Mno-aliases
+-
+-.*:[ 	]+file format .*
+-
+-
+-Disassembly of section .text:
+-
+-0+000 <.text>:
+-[ 	]+[0-9a-f]+:[ 	]+0805c53b[ 	]+packw[ 	]+a0,a1,zero
+-[ 	]+[0-9a-f]+:[ 	]+6815d513[ 	]+grevi[ 	]+a0,a1,0x1
+-[ 	]+[0-9a-f]+:[ 	]+6825d513[ 	]+grevi[ 	]+a0,a1,0x2
+-[ 	]+[0-9a-f]+:[ 	]+6835d513[ 	]+grevi[ 	]+a0,a1,0x3
+-[ 	]+[0-9a-f]+:[ 	]+6845d513[ 	]+grevi[ 	]+a0,a1,0x4
+-[ 	]+[0-9a-f]+:[ 	]+6865d513[ 	]+grevi[ 	]+a0,a1,0x6
+-[ 	]+[0-9a-f]+:[ 	]+6875d513[ 	]+grevi[ 	]+a0,a1,0x7
+-[ 	]+[0-9a-f]+:[ 	]+6885d513[ 	]+grevi[ 	]+a0,a1,0x8
+-[ 	]+[0-9a-f]+:[ 	]+68c5d513[ 	]+grevi[ 	]+a0,a1,0xc
+-[ 	]+[0-9a-f]+:[ 	]+68e5d513[ 	]+grevi[ 	]+a0,a1,0xe
+-[ 	]+[0-9a-f]+:[ 	]+68f5d513[ 	]+grevi[ 	]+a0,a1,0xf
+-[ 	]+[0-9a-f]+:[ 	]+6b05d513[ 	]+grevi[ 	]+a0,a1,0x30
+-[ 	]+[0-9a-f]+:[ 	]+6b85d513[ 	]+grevi[ 	]+a0,a1,0x38
+-[ 	]+[0-9a-f]+:[ 	]+6bc5d513[ 	]+grevi[ 	]+a0,a1,0x3c
+-[ 	]+[0-9a-f]+:[ 	]+6be5d513[ 	]+grevi[ 	]+a0,a1,0x3e
+-[ 	]+[0-9a-f]+:[ 	]+6bf5d513[ 	]+grevi[ 	]+a0,a1,0x3f
+-[ 	]+[0-9a-f]+:[ 	]+2815d513[ 	]+gorci[ 	]+a0,a1,0x1
+-[ 	]+[0-9a-f]+:[ 	]+2825d513[ 	]+gorci[ 	]+a0,a1,0x2
+-[ 	]+[0-9a-f]+:[ 	]+2835d513[ 	]+gorci[ 	]+a0,a1,0x3
+-[ 	]+[0-9a-f]+:[ 	]+2845d513[ 	]+gorci[ 	]+a0,a1,0x4
+-[ 	]+[0-9a-f]+:[ 	]+2865d513[ 	]+gorci[ 	]+a0,a1,0x6
+-[ 	]+[0-9a-f]+:[ 	]+2875d513[ 	]+gorci[ 	]+a0,a1,0x7
+-[ 	]+[0-9a-f]+:[ 	]+2885d513[ 	]+gorci[ 	]+a0,a1,0x8
+-[ 	]+[0-9a-f]+:[ 	]+28c5d513[ 	]+gorci[ 	]+a0,a1,0xc
+-[ 	]+[0-9a-f]+:[ 	]+28e5d513[ 	]+gorci[ 	]+a0,a1,0xe
+-[ 	]+[0-9a-f]+:[ 	]+28f5d513[ 	]+gorci[ 	]+a0,a1,0xf
+-[ 	]+[0-9a-f]+:[ 	]+2b05d513[ 	]+gorci[ 	]+a0,a1,0x30
+-[ 	]+[0-9a-f]+:[ 	]+2b85d513[ 	]+gorci[ 	]+a0,a1,0x38
+-[ 	]+[0-9a-f]+:[ 	]+2bc5d513[ 	]+gorci[ 	]+a0,a1,0x3c
+-[ 	]+[0-9a-f]+:[ 	]+2be5d513[ 	]+gorci[ 	]+a0,a1,0x3e
+-[ 	]+[0-9a-f]+:[ 	]+2bf5d513[ 	]+gorci[ 	]+a0,a1,0x3f
+-[ 	]+[0-9a-f]+:[ 	]+08159513[ 	]+shfli[ 	]+a0,a1,0x1
+-[ 	]+[0-9a-f]+:[ 	]+08259513[ 	]+shfli[ 	]+a0,a1,0x2
+-[ 	]+[0-9a-f]+:[ 	]+08359513[ 	]+shfli[ 	]+a0,a1,0x3
+-[ 	]+[0-9a-f]+:[ 	]+08459513[ 	]+shfli[ 	]+a0,a1,0x4
+-[ 	]+[0-9a-f]+:[ 	]+08659513[ 	]+shfli[ 	]+a0,a1,0x6
+-[ 	]+[0-9a-f]+:[ 	]+08759513[ 	]+shfli[ 	]+a0,a1,0x7
+-[ 	]+[0-9a-f]+:[ 	]+09859513[ 	]+shfli[ 	]+a0,a1,0x18
+-[ 	]+[0-9a-f]+:[ 	]+09c59513[ 	]+shfli[ 	]+a0,a1,0x1c
+-[ 	]+[0-9a-f]+:[ 	]+09e59513[ 	]+shfli[ 	]+a0,a1,0x1e
+-[ 	]+[0-9a-f]+:[ 	]+09f59513[ 	]+shfli[ 	]+a0,a1,0x1f
+-[ 	]+[0-9a-f]+:[ 	]+0815d513[ 	]+unshfli[ 	]+a0,a1,0x1
+-[ 	]+[0-9a-f]+:[ 	]+0825d513[ 	]+unshfli[ 	]+a0,a1,0x2
+-[ 	]+[0-9a-f]+:[ 	]+0835d513[ 	]+unshfli[ 	]+a0,a1,0x3
+-[ 	]+[0-9a-f]+:[ 	]+0845d513[ 	]+unshfli[ 	]+a0,a1,0x4
+-[ 	]+[0-9a-f]+:[ 	]+0865d513[ 	]+unshfli[ 	]+a0,a1,0x6
+-[ 	]+[0-9a-f]+:[ 	]+0875d513[ 	]+unshfli[ 	]+a0,a1,0x7
+-[ 	]+[0-9a-f]+:[ 	]+0985d513[ 	]+unshfli[ 	]+a0,a1,0x18
+-[ 	]+[0-9a-f]+:[ 	]+09c5d513[ 	]+unshfli[ 	]+a0,a1,0x1c
+-[ 	]+[0-9a-f]+:[ 	]+09e5d513[ 	]+unshfli[ 	]+a0,a1,0x1e
+-[ 	]+[0-9a-f]+:[ 	]+09f5d513[ 	]+unshfli[ 	]+a0,a1,0x1f
+-[ 	]+[0-9a-f]+:[ 	]+0805853b[ 	]+addu.w[ 	]+a0,a1,zero
+-[ 	]+[0-9a-f]+:[ 	]+6905d513[ 	]+grevi[ 	]+a0,a1,0x10
+-[ 	]+[0-9a-f]+:[ 	]+6985d513[ 	]+grevi[ 	]+a0,a1,0x18
+-[ 	]+[0-9a-f]+:[ 	]+69c5d513[ 	]+grevi[ 	]+a0,a1,0x1c
+-[ 	]+[0-9a-f]+:[ 	]+69e5d513[ 	]+grevi[ 	]+a0,a1,0x1e
+-[ 	]+[0-9a-f]+:[ 	]+69f5d513[ 	]+grevi[ 	]+a0,a1,0x1f
+-[ 	]+[0-9a-f]+:[ 	]+6a05d513[ 	]+grevi[ 	]+a0,a1,0x20
+-[ 	]+[0-9a-f]+:[ 	]+2905d513[ 	]+gorci[ 	]+a0,a1,0x10
+-[ 	]+[0-9a-f]+:[ 	]+2985d513[ 	]+gorci[ 	]+a0,a1,0x18
+-[ 	]+[0-9a-f]+:[ 	]+29c5d513[ 	]+gorci[ 	]+a0,a1,0x1c
+-[ 	]+[0-9a-f]+:[ 	]+29e5d513[ 	]+gorci[ 	]+a0,a1,0x1e
+-[ 	]+[0-9a-f]+:[ 	]+29f5d513[ 	]+gorci[ 	]+a0,a1,0x1f
+-[ 	]+[0-9a-f]+:[ 	]+2a05d513[ 	]+gorci[ 	]+a0,a1,0x20
+-[ 	]+[0-9a-f]+:[ 	]+08859513[ 	]+shfli[ 	]+a0,a1,0x8
+-[ 	]+[0-9a-f]+:[ 	]+08c59513[ 	]+shfli[ 	]+a0,a1,0xc
+-[ 	]+[0-9a-f]+:[ 	]+08e59513[ 	]+shfli[ 	]+a0,a1,0xe
+-[ 	]+[0-9a-f]+:[ 	]+08f59513[ 	]+shfli[ 	]+a0,a1,0xf
+-[ 	]+[0-9a-f]+:[ 	]+09059513[ 	]+shfli[ 	]+a0,a1,0x10
+-[ 	]+[0-9a-f]+:[ 	]+0885d513[ 	]+unshfli[ 	]+a0,a1,0x8
+-[ 	]+[0-9a-f]+:[ 	]+08c5d513[ 	]+unshfli[ 	]+a0,a1,0xc
+-[ 	]+[0-9a-f]+:[ 	]+08e5d513[ 	]+unshfli[ 	]+a0,a1,0xe
+-[ 	]+[0-9a-f]+:[ 	]+08f5d513[ 	]+unshfli[ 	]+a0,a1,0xf
+-[ 	]+[0-9a-f]+:[ 	]+0905d513[ 	]+unshfli[ 	]+a0,a1,0x10
+diff --git a/gas/testsuite/gas/riscv/bitmanip-insns.s b/gas/testsuite/gas/riscv/bitmanip-insns.s
+index 52e4b3afff..b14e89c1d4 100644
+--- a/gas/testsuite/gas/riscv/bitmanip-insns.s
++++ b/gas/testsuite/gas/riscv/bitmanip-insns.s
+@@ -1,57 +1,58 @@
++	# pseudo/aliaese
++	zext.h	a0, a1
++	rev8	a0, a1
++	orc.b	a0, a1
++.ifdef __64_bit__
++	zext.w	a0, a1
++.endif
++
+ 	# ZBA
+ 	sh1add	a0, a1, a2
+ 	sh2add	a0, a1, a2
+ 	sh3add	a0, a1, a2
+-
+ .ifdef __64_bit__
+-	slliu.w		a0, a1, 1
+-	slliu.w		a0, a1, 63
+-	addu.w		a0, a1, a2
+-	sh1addu.w	a0, a1, a2
+-	sh2addu.w	a0, a1, a2
+-	sh3addu.w	a0, a1, a2
++	sh1add.uw	a0, a1, a2
++	sh2add.uw	a0, a1, a2
++	sh3add.uw	a0, a1, a2
++	add.uw		a0, a1, a2
++	slli.uw		a0, a1, 0
++	slli.uw		a0, a1, 63
+ .endif
+ 
+ 	# ZBB
+ 	clz	a0, a1
+ 	ctz	a0, a1
+-	pcnt	a0, a1
++	cpop	a0, a1
+ 	min	a0, a1, a2
+ 	max	a0, a1, a2
+ 	minu	a0, a1, a2
+ 	maxu	a0, a1, a2
++	sext.b	a0, a1
++	sext.h	a0, a1
+ 	andn	a0, a1, a2
+ 	orn	a0, a1, a2
+ 	xor	a0, a1, a2
+-	roli	a0, a1, 1
+-	roli	a0, a1, 31
+-	rol	a0, a1, a2
+-	rol	a0, a1, 1
+-	rol	a0, a1, 31
+-	rori	a0, a1, 1
++	rori	a0, a1, 0
+ 	rori	a0, a1, 31
+ 	ror	a0, a1, a2
+-	ror	a0, a1, 1
++	ror	a0, a1, 0
+ 	ror	a0, a1, 31
+-	sext.b	a0, a1
+-	sext.h	a0, a1
+-
++	rol	a0, a1, a2
+ .ifdef __64_bit__
+ 	clzw	a0, a1
+ 	ctzw	a0, a1
+-	pcntw	a0, a1
+-	roli	a0, a1, 63
+-	rol	a0, a1, 63
++	cpopw	a0, a1
+ 	rori	a0, a1, 63
+ 	ror	a0, a1, 63
+-	roliw	a0, a1, 1
+-	roliw	a0, a1, 31
+-	roriw	a0, a1, 1
++	roriw	a0, a1, 0
+ 	roriw	a0, a1, 31
+-	rolw	a0, a1, a2
+-	rolw	a0, a1, 1
+-	rolw	a0, a1, 31
+ 	rorw	a0, a1, a2
+-	rorw	a0, a1, 1
++	rorw	a0, a1, 0
+ 	rorw	a0, a1, 31
++	rolw	a0, a1, a2
+ .endif
++
++	# ZBC
++	clmul	a0, a1, a2
++	clmulh	a0, a1, a2
++	clmulr	a0, a1, a2
+diff --git a/include/opcode/riscv-opc.h b/include/opcode/riscv-opc.h
+index 1faa2a8a8a..d481d5e2e6 100644
+--- a/include/opcode/riscv-opc.h
++++ b/include/opcode/riscv-opc.h
+@@ -203,14 +203,14 @@
+ #define MASK_ROL  0xfe00707f
+ #define MATCH_ROR 0x60005033
+ #define MASK_ROR  0xfe00707f
+-#define MATCH_SBCLR 0x48001033
+-#define MASK_SBCLR  0xfe00707f
+-#define MATCH_SBSET 0x28001033
+-#define MASK_SBSET  0xfe00707f
+-#define MATCH_SBINV 0x68001033
+-#define MASK_SBINV  0xfe00707f
+-#define MATCH_SBEXT 0x48005033
+-#define MASK_SBEXT  0xfe00707f
++#define MATCH_BCLR 0x48001033
++#define MASK_BCLR  0xfe00707f
++#define MATCH_BSET 0x28001033
++#define MASK_BSET  0xfe00707f
++#define MATCH_BINV 0x68001033
++#define MASK_BINV  0xfe00707f
++#define MATCH_BFEXT 0x48005033
++#define MASK_BFEXT  0xfe00707f
+ #define MATCH_GORC 0x28005033
+ #define MASK_GORC  0xfe00707f
+ #define MATCH_GREV 0x68005033
+@@ -221,14 +221,14 @@
+ #define MASK_SROI  0xfc00707f
+ #define MATCH_RORI 0x60005013
+ #define MASK_RORI  0xfc00707f
+-#define MATCH_SBCLRI 0x48001013
+-#define MASK_SBCLRI  0xfc00707f
+-#define MATCH_SBSETI 0x28001013
+-#define MASK_SBSETI  0xfc00707f
+-#define MATCH_SBINVI 0x68001013
+-#define MASK_SBINVI  0xfc00707f
+-#define MATCH_SBEXTI 0x48005013
+-#define MASK_SBEXTI  0xfc00707f
++#define MATCH_BCLRI 0x48001013
++#define MASK_BCLRI  0xfc00707f
++#define MATCH_BSETI 0x28001013
++#define MASK_BSETI  0xfc00707f
++#define MATCH_BINVI 0x68001013
++#define MASK_BINVI  0xfc00707f
++#define MATCH_BEXTI 0x48005013
++#define MASK_BEXTI  0xfc00707f
+ #define MATCH_GORCI 0x28005013
+ #define MASK_GORCI  0xfc00707f
+ #define MATCH_GREVI 0x68005013
+@@ -247,8 +247,8 @@
+ #define MASK_CLZ  0xfff0707f
+ #define MATCH_CTZ 0x60101013
+ #define MASK_CTZ  0xfff0707f
+-#define MATCH_PCNT 0x60201013
+-#define MASK_PCNT  0xfff0707f
++#define MATCH_CPOP 0x60201013
++#define MASK_CPOP  0xfff0707f
+ #define MATCH_SEXT_B 0x60401013
+ #define MASK_SEXT_B  0xfff0707f
+ #define MATCH_SEXT_H 0x60501013
+@@ -321,12 +321,12 @@
+ #define MASK_BMATOR  0xfe00707f
+ #define MATCH_BMATXOR 0x48003033
+ #define MASK_BMATXOR  0xfe00707f
+-#define MATCH_SLLIU_W 0x800101b
+-#define MASK_SLLIU_W  0xfc00707f
+-#define MATCH_ADDU_W 0x800003b
+-#define MASK_ADDU_W  0xfe00707f
+-#define MATCH_SUBU_W 0x4800003b
+-#define MASK_SUBU_W  0xfe00707f
++#define MATCH_SLLI_UW 0x800101b
++#define MASK_SLLI_UW  0xfc00707f
++#define MATCH_ADD_UW 0x800003b
++#define MASK_ADD_UW  0xfe00707f
++#define MATCH_SUB_UW 0x4800003b
++#define MASK_SUB_UW  0xfe00707f
+ #define MATCH_SLOW 0x2000103b
+ #define MASK_SLOW  0xfe00707f
+ #define MATCH_SROW 0x2000503b
+@@ -335,14 +335,14 @@
+ #define MASK_ROLW  0xfe00707f
+ #define MATCH_RORW 0x6000503b
+ #define MASK_RORW  0xfe00707f
+-#define MATCH_SBCLRW 0x4800103b
+-#define MASK_SBCLRW  0xfe00707f
+-#define MATCH_SBSETW 0x2800103b
+-#define MASK_SBSETW  0xfe00707f
+-#define MATCH_SBINVW 0x6800103b
+-#define MASK_SBINVW  0xfe00707f
+-#define MATCH_SBEXTW 0x4800503b
+-#define MASK_SBEXTW  0xfe00707f
++#define MATCH_BCLRW 0x4800103b
++#define MASK_BCLRW  0xfe00707f
++#define MATCH_BSETW 0x2800103b
++#define MASK_BSETW  0xfe00707f
++#define MATCH_BINVW 0x6800103b
++#define MASK_BINVW  0xfe00707f
++#define MATCH_BFEXTW 0x4800503b
++#define MASK_BFEXTW  0xfe00707f
+ #define MATCH_GORCW 0x2800503b
+ #define MASK_GORCW  0xfe00707f
+ #define MATCH_GREVW 0x6800503b
+@@ -353,12 +353,12 @@
+ #define MASK_SROIW  0xfe00707f
+ #define MATCH_RORIW 0x6000501b
+ #define MASK_RORIW  0xfe00707f
+-#define MATCH_SBCLRIW 0x4800101b
+-#define MASK_SBCLRIW  0xfe00707f
+-#define MATCH_SBSETIW 0x2800101b
+-#define MASK_SBSETIW  0xfe00707f
+-#define MATCH_SBINVIW 0x6800101b
+-#define MASK_SBINVIW  0xfe00707f
++#define MATCH_BCLRIW 0x4800101b
++#define MASK_BCLRIW  0xfe00707f
++#define MATCH_BSETIW 0x2800101b
++#define MASK_BSETIW  0xfe00707f
++#define MATCH_BINVIW 0x6800101b
++#define MASK_BINVIW  0xfe00707f
+ #define MATCH_GORCIW 0x2800501b
+ #define MASK_GORCIW  0xfe00707f
+ #define MATCH_GREVIW 0x6800501b
+@@ -373,14 +373,14 @@
+ #define MASK_CLZW  0xfff0707f
+ #define MATCH_CTZW 0x6010101b
+ #define MASK_CTZW  0xfff0707f
+-#define MATCH_PCNTW 0x6020101b
+-#define MASK_PCNTW  0xfff0707f
+-#define MATCH_SH1ADDU_W 0x2000203b
+-#define MASK_SH1ADDU_W  0xfe00707f
+-#define MATCH_SH2ADDU_W 0x2000403b
+-#define MASK_SH2ADDU_W  0xfe00707f
+-#define MATCH_SH3ADDU_W 0x2000603b
+-#define MASK_SH3ADDU_W  0xfe00707f
++#define MATCH_CPOPW 0x6020101b
++#define MASK_CPOPW  0xfff0707f
++#define MATCH_SH1ADD_UW 0x2000203b
++#define MASK_SH1ADD_UW  0xfe00707f
++#define MATCH_SH2ADD_UW 0x2000403b
++#define MASK_SH2ADD_UW  0xfe00707f
++#define MATCH_SH3ADD_UW 0x2000603b
++#define MASK_SH3ADD_UW  0xfe00707f
+ #define MATCH_SHFLW 0x800103b
+ #define MASK_SHFLW  0xfe00707f
+ #define MATCH_UNSHFLW 0x800503b
+@@ -3665,19 +3665,19 @@ DECLARE_INSN(slo, MATCH_SLO, MASK_SLO)
+ DECLARE_INSN(sro, MATCH_SRO, MASK_SRO)
+ DECLARE_INSN(rol, MATCH_ROL, MASK_ROL)
+ DECLARE_INSN(ror, MATCH_ROR, MASK_ROR)
+-DECLARE_INSN(sbclr, MATCH_SBCLR, MASK_SBCLR)
+-DECLARE_INSN(sbset, MATCH_SBSET, MASK_SBSET)
+-DECLARE_INSN(sbinv, MATCH_SBINV, MASK_SBINV)
+-DECLARE_INSN(sbext, MATCH_SBEXT, MASK_SBEXT)
++DECLARE_INSN(bclr, MATCH_BCLR, MASK_BCLR)
++DECLARE_INSN(bset, MATCH_BSET, MASK_BSET)
++DECLARE_INSN(binv, MATCH_BINV, MASK_BINV)
++DECLARE_INSN(bfext, MATCH_BFEXT, MASK_BFEXT)
+ DECLARE_INSN(gorc, MATCH_GORC, MASK_GORC)
+ DECLARE_INSN(grev, MATCH_GREV, MASK_GREV)
+ DECLARE_INSN(sloi, MATCH_SLOI, MASK_SLOI)
+ DECLARE_INSN(sroi, MATCH_SROI, MASK_SROI)
+ DECLARE_INSN(rori, MATCH_RORI, MASK_RORI)
+-DECLARE_INSN(sbclri, MATCH_SBCLRI, MASK_SBCLRI)
+-DECLARE_INSN(sbseti, MATCH_SBSETI, MASK_SBSETI)
+-DECLARE_INSN(sbinvi, MATCH_SBINVI, MASK_SBINVI)
+-DECLARE_INSN(sbexti, MATCH_SBEXTI, MASK_SBEXTI)
++DECLARE_INSN(bclri, MATCH_BCLRI, MASK_BCLRI)
++DECLARE_INSN(bseti, MATCH_BSETI, MASK_BSETI)
++DECLARE_INSN(binvi, MATCH_BINVI, MASK_BINVI)
++DECLARE_INSN(bexti, MATCH_BEXTI, MASK_BEXTI)
+ DECLARE_INSN(gorci, MATCH_GORCI, MASK_GORCI)
+ DECLARE_INSN(grevi, MATCH_GREVI, MASK_GREVI)
+ DECLARE_INSN(cmix, MATCH_CMIX, MASK_CMIX)
+@@ -3687,7 +3687,7 @@ DECLARE_INSN(fsr, MATCH_FSR, MASK_FSR)
+ DECLARE_INSN(fsri, MATCH_FSRI, MASK_FSRI)
+ DECLARE_INSN(clz, MATCH_CLZ, MASK_CLZ)
+ DECLARE_INSN(ctz, MATCH_CTZ, MASK_CTZ)
+-DECLARE_INSN(pcnt, MATCH_PCNT, MASK_PCNT)
++DECLARE_INSN(cpop, MATCH_CPOP, MASK_CPOP)
+ DECLARE_INSN(sext_b, MATCH_SEXT_B, MASK_SEXT_B)
+ DECLARE_INSN(sext_h, MATCH_SEXT_H, MASK_SEXT_H)
+ DECLARE_INSN(crc32_b, MATCH_CRC32_B, MASK_CRC32_B)
+@@ -3724,25 +3724,25 @@ DECLARE_INSN(crc32_d, MATCH_CRC32_D, MASK_CRC32_D)
+ DECLARE_INSN(crc32c_d, MATCH_CRC32C_D, MASK_CRC32C_D)
+ DECLARE_INSN(bmator, MATCH_BMATOR, MASK_BMATOR)
+ DECLARE_INSN(bmatxor, MATCH_BMATXOR, MASK_BMATXOR)
+-DECLARE_INSN(slliu_w, MATCH_SLLIU_W, MASK_SLLIU_W)
+-DECLARE_INSN(addu_w, MATCH_ADDU_W, MASK_ADDU_W)
+-DECLARE_INSN(subu_w, MATCH_SUBU_W, MASK_SUBU_W)
++DECLARE_INSN(slli_uw, MATCH_SLLI_UW, MASK_SLLI_UW)
++DECLARE_INSN(add_uw, MATCH_ADD_UW, MASK_ADD_UW)
++DECLARE_INSN(sub_uw, MATCH_SUB_UW, MASK_SUB_UW)
+ DECLARE_INSN(slow, MATCH_SLOW, MASK_SLOW)
+ DECLARE_INSN(srow, MATCH_SROW, MASK_SROW)
+ DECLARE_INSN(rolw, MATCH_ROLW, MASK_ROLW)
+ DECLARE_INSN(rorw, MATCH_RORW, MASK_RORW)
+-DECLARE_INSN(sbclrw, MATCH_SBCLRW, MASK_SBCLRW)
+-DECLARE_INSN(sbsetw, MATCH_SBSETW, MASK_SBSETW)
+-DECLARE_INSN(sbinvw, MATCH_SBINVW, MASK_SBINVW)
+-DECLARE_INSN(sbextw, MATCH_SBEXTW, MASK_SBEXTW)
++DECLARE_INSN(bclrw, MATCH_BCLRW, MASK_BCLRW)
++DECLARE_INSN(bsetw, MATCH_BSETW, MASK_BSETW)
++DECLARE_INSN(binvw, MATCH_BINVW, MASK_BINVW)
++DECLARE_INSN(bfextw, MATCH_BFEXTW, MASK_BFEXTW)
+ DECLARE_INSN(gorcw, MATCH_GORCW, MASK_GORCW)
+ DECLARE_INSN(grevw, MATCH_GREVW, MASK_GREVW)
+ DECLARE_INSN(sloiw, MATCH_SLOIW, MASK_SLOIW)
+ DECLARE_INSN(sroiw, MATCH_SROIW, MASK_SROIW)
+ DECLARE_INSN(roriw, MATCH_RORIW, MASK_RORIW)
+-DECLARE_INSN(sbclriw, MATCH_SBCLRIW, MASK_SBCLRIW)
+-DECLARE_INSN(sbsetiw, MATCH_SBSETIW, MASK_SBSETIW)
+-DECLARE_INSN(sbinviw, MATCH_SBINVIW, MASK_SBINVIW)
++DECLARE_INSN(bclriw, MATCH_BCLRIW, MASK_BCLRIW)
++DECLARE_INSN(bsetiw, MATCH_BSETIW, MASK_BSETIW)
++DECLARE_INSN(binviw, MATCH_BINVIW, MASK_BINVIW)
+ DECLARE_INSN(gorciw, MATCH_GORCIW, MASK_GORCIW)
+ DECLARE_INSN(greviw, MATCH_GREVIW, MASK_GREVIW)
+ DECLARE_INSN(fslw, MATCH_FSLW, MASK_FSLW)
+@@ -3750,10 +3750,10 @@ DECLARE_INSN(fsrw, MATCH_FSRW, MASK_FSRW)
+ DECLARE_INSN(fsriw, MATCH_FSRIW, MASK_FSRIW)
+ DECLARE_INSN(clzw, MATCH_CLZW, MASK_CLZW)
+ DECLARE_INSN(ctzw, MATCH_CTZW, MASK_CTZW)
+-DECLARE_INSN(pcntw, MATCH_PCNTW, MASK_PCNTW)
+-DECLARE_INSN(sh1addu_w, MATCH_SH1ADDU_W, MASK_SH1ADDU_W)
+-DECLARE_INSN(sh2addu_w, MATCH_SH2ADDU_W, MASK_SH2ADDU_W)
+-DECLARE_INSN(sh3addu_w, MATCH_SH3ADDU_W, MASK_SH3ADDU_W)
++DECLARE_INSN(cpopw, MATCH_CPOPW, MASK_CPOPW)
++DECLARE_INSN(sh1add_uw, MATCH_SH1ADD_UW, MASK_SH1ADD_UW)
++DECLARE_INSN(sh2add_uw, MATCH_SH2ADD_UW, MASK_SH2ADD_UW)
++DECLARE_INSN(sh3add_uw, MATCH_SH3ADD_UW, MASK_SH3ADD_UW)
+ DECLARE_INSN(shflw, MATCH_SHFLW, MASK_SHFLW)
+ DECLARE_INSN(unshflw, MATCH_UNSHFLW, MASK_UNSHFLW)
+ DECLARE_INSN(xperm_w, MATCH_XPERMW, MASK_XPERMW)
+diff --git a/include/opcode/riscv.h b/include/opcode/riscv.h
+index 02800fda64..6ff292d794 100644
+--- a/include/opcode/riscv.h
++++ b/include/opcode/riscv.h
+@@ -391,18 +391,10 @@ enum riscv_insn_class
+    INSN_CLASS_V_AND_ZVEDIV,
+    INSN_CLASS_V_OR_ZVLSSEG,
+    INSN_CLASS_V_AND_ZVQMAC,
+-   INSN_CLASS_B_OR_ZBA,
+-   INSN_CLASS_B_OR_ZBB,
+-   INSN_CLASS_B_OR_ZBC,
+-   INSN_CLASS_B_OR_ZBS,
+-   INSN_CLASS_B_OR_ZBA_OR_ZBB,
+-
+-   INSN_CLASS_B_OR_ZBE,
+-   INSN_CLASS_B_OR_ZBF,
+-   INSN_CLASS_B_OR_ZBM,
+-   INSN_CLASS_B_OR_ZBP,
+-   INSN_CLASS_ZBR,
+-   INSN_CLASS_ZBT,
++   INSN_CLASS_ZBA,
++   INSN_CLASS_ZBB,
++   INSN_CLASS_ZBC,
++   INSN_CLASS_ZBA_OR_ZBB,
+   };
+ 
+ /* This structure holds information for a particular instruction.  */
+@@ -448,7 +440,8 @@ enum riscv_isa_spec_class
+ 
+   ISA_SPEC_CLASS_2P2,
+   ISA_SPEC_CLASS_20190608,
+-  ISA_SPEC_CLASS_20191213
++  ISA_SPEC_CLASS_20191213,
++  ISA_SPEC_CLASS_DRAFT
+ };
+ 
+ #define RISCV_UNKNOWN_VERSION -1
+@@ -582,8 +575,6 @@ enum
+   M_LI,
+   M_VMSGE,
+   M_VMSGEU,
+-  M_RL,
+-  M_FL,
+   M_ZEXTH,
+   M_ZEXTW,
+   M_SEXTB,
+diff --git a/opcodes/riscv-opc.c b/opcodes/riscv-opc.c
+index 5c07c0a2db..af408b041c 100644
+--- a/opcodes/riscv-opc.c
++++ b/opcodes/riscv-opc.c
+@@ -1053,8 +1053,6 @@ const struct riscv_opcode riscv_opcodes[] =
+ {"rev.h",    64, INSN_CLASS_B,   "d,s",  MATCH_GREVI | MATCH_PERMH_IMM (64), MASK_GREVI | MASK_RVB_IMM, match_opcode, INSN_ALIAS },
+ {"rev16",    32, INSN_CLASS_B,   "d,s",  MATCH_GREVI | MATCH_PERM16_IMM (32), MASK_GREVI | MASK_RVB_IMM, match_opcode, INSN_ALIAS },
+ {"rev16",    64, INSN_CLASS_B,   "d,s",  MATCH_GREVI | MATCH_PERM16_IMM (64), MASK_GREVI | MASK_RVB_IMM, match_opcode, INSN_ALIAS },
+-{"rev8",     32, INSN_CLASS_B_OR_ZBB,   "d,s",  MATCH_GREVI | MATCH_PERM8_IMM (32), MASK_GREVI | MASK_RVB_IMM, match_opcode, INSN_ALIAS },
+-{"rev8",     64, INSN_CLASS_B_OR_ZBB,   "d,s",  MATCH_GREVI | MATCH_PERM8_IMM (64), MASK_GREVI | MASK_RVB_IMM, match_opcode, INSN_ALIAS },
+ {"rev4",     32, INSN_CLASS_B,   "d,s",  MATCH_GREVI | MATCH_PERM4_IMM (32), MASK_GREVI | MASK_RVB_IMM, match_opcode, INSN_ALIAS },
+ {"rev4",     64, INSN_CLASS_B,   "d,s",  MATCH_GREVI | MATCH_PERM4_IMM (64), MASK_GREVI | MASK_RVB_IMM, match_opcode, INSN_ALIAS },
+ {"rev2",     32, INSN_CLASS_B,   "d,s",  MATCH_GREVI | MATCH_PERM2_IMM (32), MASK_GREVI | MASK_RVB_IMM, match_opcode, INSN_ALIAS },
+@@ -1078,8 +1076,6 @@ const struct riscv_opcode riscv_opcodes[] =
+ {"orc4.b",   64, INSN_CLASS_B,   "d,s",  MATCH_GORCI | MATCH_PERM4B_IMM (64), MASK_GORCI | MASK_RVB_IMM, match_opcode, INSN_ALIAS },
+ {"orc2.b",   32, INSN_CLASS_B,   "d,s",  MATCH_GORCI | MATCH_PERM2B_IMM (32), MASK_GORCI | MASK_RVB_IMM, match_opcode, INSN_ALIAS },
+ {"orc2.b",   64, INSN_CLASS_B,   "d,s",  MATCH_GORCI | MATCH_PERM2B_IMM (64), MASK_GORCI | MASK_RVB_IMM, match_opcode, INSN_ALIAS },
+-{"orc.b",    32, INSN_CLASS_B_OR_ZBB,   "d,s",  MATCH_GORCI | MATCH_PERMB_IMM (32), MASK_GORCI | MASK_RVB_IMM, match_opcode, INSN_ALIAS },
+-{"orc.b",    64, INSN_CLASS_B_OR_ZBB,   "d,s",  MATCH_GORCI | MATCH_PERMB_IMM (64), MASK_GORCI | MASK_RVB_IMM, match_opcode, INSN_ALIAS },
+ {"orc8.h",   32, INSN_CLASS_B,   "d,s",  MATCH_GORCI | MATCH_PERM8H_IMM (32), MASK_GORCI | MASK_RVB_IMM, match_opcode, INSN_ALIAS },
+ {"orc8.h",   64, INSN_CLASS_B,   "d,s",  MATCH_GORCI | MATCH_PERM8H_IMM (64), MASK_GORCI | MASK_RVB_IMM, match_opcode, INSN_ALIAS },
+ {"orc4.h",   32, INSN_CLASS_B,   "d,s",  MATCH_GORCI | MATCH_PERM4H_IMM (32), MASK_GORCI | MASK_RVB_IMM, match_opcode, INSN_ALIAS },
+@@ -1157,77 +1153,53 @@ const struct riscv_opcode riscv_opcodes[] =
+ {"unzip.w",  64, INSN_CLASS_B,   "d,s",  MATCH_UNSHFLI | MATCH_PERMW_SHFL_IMM (64), MASK_UNSHFLI | MASK_RVB_IMM, match_opcode, INSN_ALIAS },
+ {"unzip16",  64, INSN_CLASS_B,   "d,s",  MATCH_UNSHFLI | MATCH_PERM16_SHFL_IMM (64), MASK_UNSHFLI | MASK_RVB_IMM, match_opcode, INSN_ALIAS },
+ 
+-/* Bitmanip instruction subset - for sure  */
+-{"sh1add",    0, INSN_CLASS_B_OR_ZBA,   "d,s,t",  MATCH_SH1ADD, MASK_SH1ADD, match_opcode, 0 },
+-{"sh2add",    0, INSN_CLASS_B_OR_ZBA,   "d,s,t",  MATCH_SH2ADD, MASK_SH2ADD, match_opcode, 0 },
+-{"sh3add",    0, INSN_CLASS_B_OR_ZBA,   "d,s,t",  MATCH_SH3ADD, MASK_SH3ADD, match_opcode, 0 },
+-{"slliu.w",  64, INSN_CLASS_B_OR_ZBA,   "d,s,>",  MATCH_SLLIU_W, MASK_SLLIU_W, match_opcode, 0 },
+-{"zext.w",   64, INSN_CLASS_B_OR_ZBA_OR_ZBB,   "d,s",  MATCH_ADDU_W, MASK_ADDU_W | MASK_RS2, match_opcode, INSN_ALIAS },
+-{"zext.w",   64, INSN_CLASS_I,                 "d,s",  0, (int) M_ZEXTW,  match_never, INSN_MACRO },
+-{"addu.w",   64, INSN_CLASS_B_OR_ZBA,   "d,s,t",  MATCH_ADDU_W, MASK_ADDU_W, match_opcode, 0 },
+-{"sh1addu.w",64, INSN_CLASS_B_OR_ZBA,   "d,s,t",  MATCH_SH1ADDU_W, MASK_SH1ADDU_W, match_opcode, 0 },
+-{"sh2addu.w",64, INSN_CLASS_B_OR_ZBA,   "d,s,t",  MATCH_SH2ADDU_W, MASK_SH2ADDU_W, match_opcode, 0 },
+-{"sh3addu.w",64, INSN_CLASS_B_OR_ZBA,   "d,s,t",  MATCH_SH3ADDU_W, MASK_SH3ADDU_W, match_opcode, 0 },
+-
+-{"clz",       0, INSN_CLASS_B_OR_ZBB,   "d,s",  MATCH_CLZ, MASK_CLZ, match_opcode, 0 },
+-{"ctz",       0, INSN_CLASS_B_OR_ZBB,   "d,s",  MATCH_CTZ, MASK_CTZ, match_opcode, 0 },
+-{"pcnt",      0, INSN_CLASS_B_OR_ZBB,   "d,s",  MATCH_PCNT, MASK_PCNT, match_opcode, 0 },
+-{"min",       0, INSN_CLASS_B_OR_ZBB,   "d,s,t",  MATCH_MIN, MASK_MIN, match_opcode, 0 },
+-{"max",       0, INSN_CLASS_B_OR_ZBB,   "d,s,t",  MATCH_MAX, MASK_MAX, match_opcode, 0 },
+-{"minu",      0, INSN_CLASS_B_OR_ZBB,   "d,s,t",  MATCH_MINU, MASK_MINU, match_opcode, 0 },
+-{"maxu",      0, INSN_CLASS_B_OR_ZBB,   "d,s,t",  MATCH_MAXU, MASK_MAXU, match_opcode, 0 },
+-{"andn",      0, INSN_CLASS_B_OR_ZBB,   "d,s,t",  MATCH_ANDN, MASK_ANDN, match_opcode, 0 },
+-{"orn",       0, INSN_CLASS_B_OR_ZBB,   "d,s,t",  MATCH_ORN, MASK_ORN, match_opcode, 0 },
+-{"xnor",      0, INSN_CLASS_B_OR_ZBB,   "d,s,t",  MATCH_XNOR, MASK_XNOR, match_opcode, 0 },
+-{"roli",      0, INSN_CLASS_B_OR_ZBB,   "d,s,>",  0, (int) M_RL, match_never, INSN_MACRO },	/* rori  */
+-{"rol",       0, INSN_CLASS_B_OR_ZBB,   "d,s,t",  MATCH_ROL, MASK_ROL, match_opcode, 0 },
+-{"rol",       0, INSN_CLASS_B_OR_ZBB,   "d,s,>",  0, (int) M_RL, match_never, INSN_MACRO },	/* rori  */
+-{"rori",      0, INSN_CLASS_B_OR_ZBB,   "d,s,>",  MATCH_RORI, MASK_RORI, match_opcode, 0 },
+-{"ror",       0, INSN_CLASS_B_OR_ZBB,   "d,s,t",  MATCH_ROR, MASK_ROR, match_opcode, 0 },
+-{"ror",       0, INSN_CLASS_B_OR_ZBB,   "d,s,>",  MATCH_RORI, MASK_RORI, match_opcode, INSN_ALIAS },
+-{"sext.b",    0, INSN_CLASS_B_OR_ZBB,   "d,s",  MATCH_SEXT_B, MASK_SEXT_B, match_opcode, 0 },
+-{"sext.b",    0, INSN_CLASS_I,          "d,s",  0, (int) M_SEXTB,  match_never, INSN_MACRO },
+-{"sext.h",    0, INSN_CLASS_B_OR_ZBB,   "d,s",  MATCH_SEXT_H, MASK_SEXT_H, match_opcode, 0 },
+-{"sext.h",    0, INSN_CLASS_I,          "d,s",  0, (int) M_SEXTH,  match_never, INSN_MACRO },
+-{"zext.h",   32, INSN_CLASS_B_OR_ZBB,   "d,s",  MATCH_PACK, MASK_PACK | MASK_RS2, match_opcode, INSN_ALIAS },	/* pack with rs2=x0  */
+-{"zext.h",   64, INSN_CLASS_B_OR_ZBB,   "d,s",  MATCH_PACKW, MASK_PACKW | MASK_RS2, match_opcode, INSN_ALIAS },	/* packw with rs2=x0  */
+-{"zext.h",    0, INSN_CLASS_I,          "d,s",  0, (int) M_ZEXTH,  match_never, INSN_MACRO },
+-{"clzw",     64, INSN_CLASS_B_OR_ZBB,   "d,s",  MATCH_CLZW, MASK_CLZW, match_opcode, 0 },
+-{"ctzw",     64, INSN_CLASS_B_OR_ZBB,   "d,s",  MATCH_CTZW, MASK_CTZW, match_opcode, 0 },
+-{"pcntw",    64, INSN_CLASS_B_OR_ZBB,   "d,s",  MATCH_PCNTW, MASK_PCNTW, match_opcode, 0 },
+-{"roliw",    64, INSN_CLASS_B_OR_ZBB,   "d,s,<",  0, (int) M_RL, match_never, INSN_MACRO },	/* roriw  */
+-{"rolw",     64, INSN_CLASS_B_OR_ZBB,   "d,s,t",  MATCH_ROLW, MASK_ROLW, match_opcode, 0 },
+-{"rolw",     64, INSN_CLASS_B_OR_ZBB,   "d,s,<",  0, (int) M_RL, match_never, INSN_MACRO },	/* roriw  */
+-{"roriw",    64, INSN_CLASS_B_OR_ZBB,   "d,s,<",  MATCH_RORIW, MASK_RORIW, match_opcode, 0 },
+-{"rorw",     64, INSN_CLASS_B_OR_ZBB,   "d,s,t",  MATCH_RORW, MASK_RORW, match_opcode, 0 },
+-{"rorw",     64, INSN_CLASS_B_OR_ZBB,   "d,s,<",  MATCH_RORIW, MASK_RORIW, match_opcode, INSN_ALIAS },
+-
+-{"clmul",     0, INSN_CLASS_B_OR_ZBC,   "d,s,t",  MATCH_CLMUL, MASK_CLMUL, match_opcode, 0 },
+-{"clmulh",    0, INSN_CLASS_B_OR_ZBC,   "d,s,t",  MATCH_CLMULH, MASK_CLMULH, match_opcode, 0 },
+-{"clmulr",    0, INSN_CLASS_B_OR_ZBC,   "d,s,t",  MATCH_CLMULR, MASK_CLMULR, match_opcode, 0 },
+-
+-{"sbseti",    0, INSN_CLASS_B_OR_ZBS,   "d,s,>",  MATCH_SBSETI, MASK_SBSETI, match_opcode, 0 },
+-{"sbset",     0, INSN_CLASS_B_OR_ZBS,   "d,s,t",  MATCH_SBSET, MASK_SBSET, match_opcode, 0 },
+-{"sbset",     0, INSN_CLASS_B_OR_ZBS,   "d,s,>",  MATCH_SBSETI, MASK_SBSETI, match_opcode, INSN_ALIAS },
+-{"sbclri",    0, INSN_CLASS_B_OR_ZBS,   "d,s,>",  MATCH_SBCLRI, MASK_SBCLRI, match_opcode, 0 },
+-{"sbclr",     0, INSN_CLASS_B_OR_ZBS,   "d,s,t",  MATCH_SBCLR, MASK_SBCLR, match_opcode, 0 },
+-{"sbclr",     0, INSN_CLASS_B_OR_ZBS,   "d,s,>",  MATCH_SBCLRI, MASK_SBCLRI, match_opcode, INSN_ALIAS },
+-{"sbinvi",    0, INSN_CLASS_B_OR_ZBS,   "d,s,>",  MATCH_SBINVI, MASK_SBINVI, match_opcode, 0 },
+-{"sbinv",     0, INSN_CLASS_B_OR_ZBS,   "d,s,t",  MATCH_SBINV, MASK_SBINV, match_opcode, 0 },
+-{"sbinv",     0, INSN_CLASS_B_OR_ZBS,   "d,s,>",  MATCH_SBINVI, MASK_SBINVI, match_opcode, INSN_ALIAS },
+-{"sbexti",    0, INSN_CLASS_B_OR_ZBS,   "d,s,>",  MATCH_SBEXTI, MASK_SBEXTI, match_opcode, 0 },
+-{"sbext",     0, INSN_CLASS_B_OR_ZBS,   "d,s,t",  MATCH_SBEXT, MASK_SBEXT, match_opcode, 0 },
+-{"sbext",     0, INSN_CLASS_B_OR_ZBS,   "d,s,>",  MATCH_SBEXTI, MASK_SBEXTI, match_opcode, INSN_ALIAS },
+-{"sbsetiw",  64, INSN_CLASS_B_OR_ZBS,   "d,s,<",  MATCH_SBSETIW, MASK_SBSETIW, match_opcode, 0 },
+-{"sbsetw",   64, INSN_CLASS_B_OR_ZBS,   "d,s,t",  MATCH_SBSETW, MASK_SBSETW, match_opcode, 0 },
+-{"sbsetw",   64, INSN_CLASS_B_OR_ZBS,   "d,s,<",  MATCH_SBSETIW, MASK_SBSETIW, match_opcode, INSN_ALIAS },
+-{"sbclriw",  64, INSN_CLASS_B_OR_ZBS,   "d,s,<",  MATCH_SBCLRIW, MASK_SBCLRIW, match_opcode, 0 },
+-{"sbclrw",   64, INSN_CLASS_B_OR_ZBS,   "d,s,t",  MATCH_SBCLRW, MASK_SBCLRW, match_opcode, 0 },
+-{"sbclrw",   64, INSN_CLASS_B_OR_ZBS,   "d,s,<",  MATCH_SBCLRIW, MASK_SBCLRIW, match_opcode, INSN_ALIAS },
+-{"sbinviw",  64, INSN_CLASS_B_OR_ZBS,   "d,s,<",  MATCH_SBINVIW, MASK_SBINVIW, match_opcode, 0 },
+-{"sbinvw",   64, INSN_CLASS_B_OR_ZBS,   "d,s,t",  MATCH_SBINVW, MASK_SBINVW, match_opcode, 0 },
+-{"sbinvw",   64, INSN_CLASS_B_OR_ZBS,   "d,s,<",  MATCH_SBINVIW, MASK_SBINVIW, match_opcode, INSN_ALIAS },
+-{"sbextw",   64, INSN_CLASS_B_OR_ZBS,   "d,s,t",  MATCH_SBEXTW, MASK_SBEXTW, match_opcode, 0 },	/* No sbextiw  */
++/* Bitmanip instruction subset - ZBA/ZBB/ZBC  */
++{"sh1add",    0, INSN_CLASS_ZBA,   "d,s,t",  MATCH_SH1ADD, MASK_SH1ADD, match_opcode, 0 },
++{"sh2add",    0, INSN_CLASS_ZBA,   "d,s,t",  MATCH_SH2ADD, MASK_SH2ADD, match_opcode, 0 },
++{"sh3add",    0, INSN_CLASS_ZBA,   "d,s,t",  MATCH_SH3ADD, MASK_SH3ADD, match_opcode, 0 },
++{"sh1add.uw",64, INSN_CLASS_ZBA,   "d,s,t",  MATCH_SH1ADD_UW, MASK_SH1ADD_UW, match_opcode, 0 },
++{"sh2add.uw",64, INSN_CLASS_ZBA,   "d,s,t",  MATCH_SH2ADD_UW, MASK_SH2ADD_UW, match_opcode, 0 },
++{"sh3add.uw",64, INSN_CLASS_ZBA,   "d,s,t",  MATCH_SH3ADD_UW, MASK_SH3ADD_UW, match_opcode, 0 },
++{"zext.w",   64, INSN_CLASS_ZBA_OR_ZBB,   "d,s",  MATCH_ADD_UW, MASK_ADD_UW | MASK_RS2, match_opcode, INSN_ALIAS },
++{"zext.w",   64, INSN_CLASS_I,     "d,s",  0, (int) M_ZEXTW,  match_never, INSN_MACRO },
++{"add.uw",   64, INSN_CLASS_ZBA,   "d,s,t",  MATCH_ADD_UW, MASK_ADD_UW, match_opcode, 0 },
++{"slli.uw",  64, INSN_CLASS_ZBA,   "d,s,>",  MATCH_SLLI_UW, MASK_SLLI_UW, match_opcode, 0 },
++
++{"clz",       0, INSN_CLASS_ZBB,   "d,s",  MATCH_CLZ, MASK_CLZ, match_opcode, 0 },
++{"ctz",       0, INSN_CLASS_ZBB,   "d,s",  MATCH_CTZ, MASK_CTZ, match_opcode, 0 },
++{"cpop",      0, INSN_CLASS_ZBB,   "d,s",  MATCH_CPOP, MASK_CPOP, match_opcode, 0 },
++{"min",       0, INSN_CLASS_ZBB,   "d,s,t",  MATCH_MIN, MASK_MIN, match_opcode, 0 },
++{"max",       0, INSN_CLASS_ZBB,   "d,s,t",  MATCH_MAX, MASK_MAX, match_opcode, 0 },
++{"minu",      0, INSN_CLASS_ZBB,   "d,s,t",  MATCH_MINU, MASK_MINU, match_opcode, 0 },
++{"maxu",      0, INSN_CLASS_ZBB,   "d,s,t",  MATCH_MAXU, MASK_MAXU, match_opcode, 0 },
++{"sext.b",    0, INSN_CLASS_ZBB,   "d,s",  MATCH_SEXT_B, MASK_SEXT_B, match_opcode, 0 },
++{"sext.b",    0, INSN_CLASS_I,     "d,s",  0, (int) M_SEXTB,  match_never, INSN_MACRO },
++{"sext.h",    0, INSN_CLASS_ZBB,   "d,s",  MATCH_SEXT_H, MASK_SEXT_H, match_opcode, 0 },
++{"sext.h",    0, INSN_CLASS_I,     "d,s",  0, (int) M_SEXTH,  match_never, INSN_MACRO },
++{"zext.h",   32, INSN_CLASS_ZBB,   "d,s",  MATCH_PACK, MASK_PACK | MASK_RS2, match_opcode, 0 },
++{"zext.h",   64, INSN_CLASS_ZBB,   "d,s",  MATCH_PACKW, MASK_PACKW | MASK_RS2, match_opcode, 0 },
++{"zext.h",    0, INSN_CLASS_I,     "d,s",  0, (int) M_ZEXTH,  match_never, INSN_MACRO },
++{"andn",      0, INSN_CLASS_ZBB,   "d,s,t",  MATCH_ANDN, MASK_ANDN, match_opcode, 0 },
++{"orn",       0, INSN_CLASS_ZBB,   "d,s,t",  MATCH_ORN, MASK_ORN, match_opcode, 0 },
++{"xnor",      0, INSN_CLASS_ZBB,   "d,s,t",  MATCH_XNOR, MASK_XNOR, match_opcode, 0 },
++{"rori",      0, INSN_CLASS_ZBB,   "d,s,>",  MATCH_RORI, MASK_RORI, match_opcode, 0 },
++{"ror",       0, INSN_CLASS_ZBB,   "d,s,t",  MATCH_ROR, MASK_ROR, match_opcode, 0 },
++{"ror",       0, INSN_CLASS_ZBB,   "d,s,>",  MATCH_RORI, MASK_RORI, match_opcode, INSN_ALIAS },
++{"rol",       0, INSN_CLASS_ZBB,   "d,s,t",  MATCH_ROL, MASK_ROL, match_opcode, 0 },
++{"clzw",     64, INSN_CLASS_ZBB,   "d,s",  MATCH_CLZW, MASK_CLZW, match_opcode, 0 },
++{"ctzw",     64, INSN_CLASS_ZBB,   "d,s",  MATCH_CTZW, MASK_CTZW, match_opcode, 0 },
++{"cpopw",    64, INSN_CLASS_ZBB,   "d,s",  MATCH_CPOPW, MASK_CPOPW, match_opcode, 0 },
++{"roriw",    64, INSN_CLASS_ZBB,   "d,s,<",  MATCH_RORIW, MASK_RORIW, match_opcode, 0 },
++{"rorw",     64, INSN_CLASS_ZBB,   "d,s,t",  MATCH_RORW, MASK_RORW, match_opcode, 0 },
++{"rorw",     64, INSN_CLASS_ZBB,   "d,s,<",  MATCH_RORIW, MASK_RORIW, match_opcode, INSN_ALIAS },
++{"rolw",     64, INSN_CLASS_ZBB,   "d,s,t",  MATCH_ROLW, MASK_ROLW, match_opcode, 0 },
++{"rev8",     32, INSN_CLASS_ZBB,   "d,s",  MATCH_GREVI | ENCODE_ITYPE_IMM (0x18), MASK_GREVI | MASK_RVB_IMM, match_opcode, 0 },
++{"rev8",     64, INSN_CLASS_ZBB,   "d,s",  MATCH_GREVI | ENCODE_ITYPE_IMM (0x38), MASK_GREVI | MASK_RVB_IMM, match_opcode, 0 },
++{"orc.b",     0, INSN_CLASS_ZBB,   "d,s",  MATCH_GORCI | ENCODE_ITYPE_IMM (0x7), MASK_GORCI | MASK_RVB_IMM, match_opcode, 0 },
++
++{"clmul",     0, INSN_CLASS_ZBC,   "d,s,t",  MATCH_CLMUL, MASK_CLMUL, match_opcode, 0 },
++{"clmulh",    0, INSN_CLASS_ZBC,   "d,s,t",  MATCH_CLMULH, MASK_CLMULH, match_opcode, 0 },
++{"clmulr",    0, INSN_CLASS_ZBC,   "d,s,t",  MATCH_CLMULR, MASK_CLMULR, match_opcode, 0 },
+ 
+ /* Bitmanip instruction subset - unsure  */
+ {"sloi",      0, INSN_CLASS_B,   "d,s,>",  MATCH_SLOI, MASK_SLOI, match_opcode, 0 },
+@@ -1260,7 +1232,7 @@ const struct riscv_opcode riscv_opcodes[] =
+ {"bmator",   64, INSN_CLASS_B,   "d,s,t",  MATCH_BMATOR, MASK_BMATOR, match_opcode, 0 },
+ {"bmatxor",  64, INSN_CLASS_B,   "d,s,t",  MATCH_BMATXOR, MASK_BMATXOR, match_opcode, 0 },
+ {"bfp",       0, INSN_CLASS_B,   "d,s,t",  MATCH_BFP, MASK_BFP, match_opcode, 0 },
+-{"subu.w",   64, INSN_CLASS_B,   "d,s,t",  MATCH_SUBU_W, MASK_SUBU_W, match_opcode, 0 },
++{"sub.uw",   64, INSN_CLASS_B,   "d,s,t",  MATCH_SUB_UW, MASK_SUB_UW, match_opcode, 0 },
+ {"sloiw",    64, INSN_CLASS_B,   "d,s,<",  MATCH_SLOIW, MASK_SLOIW, match_opcode, 0 },
+ {"sroiw",    64, INSN_CLASS_B,   "d,s,<",  MATCH_SROIW, MASK_SROIW, match_opcode, 0 },
+ {"slow",     64, INSN_CLASS_B,   "d,s,t",  MATCH_SLOW, MASK_SLOW, match_opcode, 0 },
+@@ -1282,29 +1254,48 @@ const struct riscv_opcode riscv_opcodes[] =
+ {"packuw",   64, INSN_CLASS_B,   "d,s,t",  MATCH_PACKUW, MASK_PACKUW, match_opcode, 0 },
+ {"bfpw",     64, INSN_CLASS_B,   "d,s,t",  MATCH_BFPW, MASK_BFPW, match_opcode, 0 },
+ 
+-{"cmix",      0, INSN_CLASS_ZBT,   "d,t,s,r",  MATCH_CMIX, MASK_CMIX, match_opcode, 0 },
+-{"cmov",      0, INSN_CLASS_ZBT,   "d,t,s,r",  MATCH_CMOV, MASK_CMOV, match_opcode, 0 },
+-{"fsli",      0, INSN_CLASS_ZBT,   "d,s,r,>",  0, (int) M_FL, match_never, INSN_MACRO },	/* fsri  */
+-{"fsl",       0, INSN_CLASS_ZBT,   "d,s,r,t",  MATCH_FSL, MASK_FSL, match_opcode, 0 },
+-{"fsl",       0, INSN_CLASS_ZBT,   "d,s,r,>",  0, (int) M_FL, match_never, INSN_MACRO },	/* fsri  */
+-{"fsri",      0, INSN_CLASS_ZBT,   "d,s,r,>",  MATCH_FSRI, MASK_FSRI, match_opcode, 0 },
+-{"fsr",       0, INSN_CLASS_ZBT,   "d,s,r,t",  MATCH_FSR, MASK_FSR, match_opcode, 0 },
+-{"fsr",       0, INSN_CLASS_ZBT,   "d,s,r,>",  MATCH_FSRI, MASK_FSRI, match_opcode, INSN_ALIAS },
+-{"fsliw",    64, INSN_CLASS_ZBT,   "d,s,r,<",  0, (int) M_FL, match_never, INSN_MACRO },	/* fsriw  */
+-{"fslw",     64, INSN_CLASS_ZBT,   "d,s,r,t",  MATCH_FSLW, MASK_FSLW, match_opcode, 0 },
+-{"fslw",     64, INSN_CLASS_ZBT,   "d,s,r,<",  0, (int) M_FL, match_never, INSN_MACRO },	/* fsriw  */
+-{"fsriw",    64, INSN_CLASS_ZBT,   "d,s,r,<",  MATCH_FSRIW, MASK_FSRIW, match_opcode, 0 },
+-{"fsrw",     64, INSN_CLASS_ZBT,   "d,s,r,t",  MATCH_FSRW, MASK_FSRW, match_opcode, 0 },
+-{"fsrw",     64, INSN_CLASS_ZBT,   "d,s,r,<",  MATCH_FSRIW, MASK_FSRIW, match_opcode, INSN_ALIAS },
+-
+-{"crc32.b",   0, INSN_CLASS_ZBR,   "d,s",  MATCH_CRC32_B, MASK_CRC32_B, match_opcode, 0 },
+-{"crc32.h",   0, INSN_CLASS_ZBR,   "d,s",  MATCH_CRC32_H, MASK_CRC32_H, match_opcode, 0 },
+-{"crc32.w",   0, INSN_CLASS_ZBR,   "d,s",  MATCH_CRC32_W, MASK_CRC32_W, match_opcode, 0 },
+-{"crc32c.b",  0, INSN_CLASS_ZBR,   "d,s",  MATCH_CRC32C_B, MASK_CRC32C_B, match_opcode, 0 },
+-{"crc32c.h",  0, INSN_CLASS_ZBR,   "d,s",  MATCH_CRC32C_H, MASK_CRC32C_H, match_opcode, 0 },
+-{"crc32c.w",  0, INSN_CLASS_ZBR,   "d,s",  MATCH_CRC32C_W, MASK_CRC32C_W, match_opcode, 0 },
+-{"crc32.d",  64, INSN_CLASS_ZBR,   "d,s",  MATCH_CRC32_D, MASK_CRC32_D, match_opcode, 0 },
+-{"crc32c.d", 64, INSN_CLASS_ZBR,   "d,s",  MATCH_CRC32C_D, MASK_CRC32C_D, match_opcode, 0 },
++{"cmix",      0, INSN_CLASS_B,   "d,t,s,r",  MATCH_CMIX, MASK_CMIX, match_opcode, 0 },
++{"cmov",      0, INSN_CLASS_B,   "d,t,s,r",  MATCH_CMOV, MASK_CMOV, match_opcode, 0 },
++{"fsl",       0, INSN_CLASS_B,   "d,s,r,t",  MATCH_FSL, MASK_FSL, match_opcode, 0 },
++{"fsri",      0, INSN_CLASS_B,   "d,s,r,>",  MATCH_FSRI, MASK_FSRI, match_opcode, 0 },
++{"fsr",       0, INSN_CLASS_B,   "d,s,r,t",  MATCH_FSR, MASK_FSR, match_opcode, 0 },
++{"fsr",       0, INSN_CLASS_B,   "d,s,r,>",  MATCH_FSRI, MASK_FSRI, match_opcode, INSN_ALIAS },
++{"fslw",     64, INSN_CLASS_B,   "d,s,r,t",  MATCH_FSLW, MASK_FSLW, match_opcode, 0 },
++{"fsriw",    64, INSN_CLASS_B,  "d,s,r,<",  MATCH_FSRIW, MASK_FSRIW, match_opcode, 0 },
++{"fsrw",     64, INSN_CLASS_B,   "d,s,r,t",  MATCH_FSRW, MASK_FSRW, match_opcode, 0 },
++{"fsrw",     64, INSN_CLASS_B,   "d,s,r,<",  MATCH_FSRIW, MASK_FSRIW, match_opcode, INSN_ALIAS },
++
++{"bseti",    0, INSN_CLASS_B,   "d,s,>",  MATCH_BSETI, MASK_BSETI, match_opcode, 0 },
++{"bset",     0, INSN_CLASS_B,   "d,s,t",  MATCH_BSET, MASK_BSET, match_opcode, 0 },
++{"bset",     0, INSN_CLASS_B,   "d,s,>",  MATCH_BSETI, MASK_BSETI, match_opcode, INSN_ALIAS },
++{"bclri",    0, INSN_CLASS_B,   "d,s,>",  MATCH_BCLRI, MASK_BCLRI, match_opcode, 0 },
++{"bclr",     0, INSN_CLASS_B,   "d,s,t",  MATCH_BCLR, MASK_BCLR, match_opcode, 0 },
++{"bclr",     0, INSN_CLASS_B,   "d,s,>",  MATCH_BCLRI, MASK_BCLRI, match_opcode, INSN_ALIAS },
++{"binvi",    0, INSN_CLASS_B,   "d,s,>",  MATCH_BINVI, MASK_BINVI, match_opcode, 0 },
++{"binv",     0, INSN_CLASS_B,   "d,s,t",  MATCH_BINV, MASK_BINV, match_opcode, 0 },
++{"binv",     0, INSN_CLASS_B,   "d,s,>",  MATCH_BINVI, MASK_BINVI, match_opcode, INSN_ALIAS },
++{"bexti",    0, INSN_CLASS_B,   "d,s,>",  MATCH_BEXTI, MASK_BEXTI, match_opcode, 0 },
++{"bfext",    0, INSN_CLASS_B,   "d,s,t",  MATCH_BFEXT, MASK_BFEXT, match_opcode, 0 },
++{"bfext",    0, INSN_CLASS_B,   "d,s,>",  MATCH_BEXTI, MASK_BEXTI, match_opcode, INSN_ALIAS },
++{"bsetiw",  64, INSN_CLASS_B,   "d,s,<",  MATCH_BSETIW, MASK_BSETIW, match_opcode, 0 },
++{"bsetw",   64, INSN_CLASS_B,   "d,s,t",  MATCH_BSETW, MASK_BSETW, match_opcode, 0 },
++{"bsetw",   64, INSN_CLASS_B,   "d,s,<",  MATCH_BSETIW, MASK_BSETIW, match_opcode, INSN_ALIAS },
++{"bclriw",  64, INSN_CLASS_B,   "d,s,<",  MATCH_BCLRIW, MASK_BCLRIW, match_opcode, 0 },
++{"bclrw",   64, INSN_CLASS_B,   "d,s,t",  MATCH_BCLRW, MASK_BCLRW, match_opcode, 0 },
++{"bclrw",   64, INSN_CLASS_B,   "d,s,<",  MATCH_BCLRIW, MASK_BCLRIW, match_opcode, INSN_ALIAS },
++{"binviw",  64, INSN_CLASS_B,   "d,s,<",  MATCH_BINVIW, MASK_BINVIW, match_opcode, 0 },
++{"binvw",   64, INSN_CLASS_B,   "d,s,t",  MATCH_BINVW, MASK_BINVW, match_opcode, 0 },
++{"binvw",   64, INSN_CLASS_B,   "d,s,<",  MATCH_BINVIW, MASK_BINVIW, match_opcode, INSN_ALIAS },
++{"bfextw",  64, INSN_CLASS_B,   "d,s,t",  MATCH_BFEXTW, MASK_BFEXTW, match_opcode, 0 }, /* No sbextiw  */
++
++{"crc32.b",   0, INSN_CLASS_B,   "d,s",  MATCH_CRC32_B, MASK_CRC32_B, match_opcode, 0 },
++{"crc32.h",   0, INSN_CLASS_B,   "d,s",  MATCH_CRC32_H, MASK_CRC32_H, match_opcode, 0 },
++{"crc32.w",   0, INSN_CLASS_B,   "d,s",  MATCH_CRC32_W, MASK_CRC32_W, match_opcode, 0 },
++{"crc32c.b",  0, INSN_CLASS_B,   "d,s",  MATCH_CRC32C_B, MASK_CRC32C_B, match_opcode, 0 },
++{"crc32c.h",  0, INSN_CLASS_B,   "d,s",  MATCH_CRC32C_H, MASK_CRC32C_H, match_opcode, 0 },
++{"crc32c.w",  0, INSN_CLASS_B,   "d,s",  MATCH_CRC32C_W, MASK_CRC32C_W, match_opcode, 0 },
++{"crc32.d",  64, INSN_CLASS_B,   "d,s",  MATCH_CRC32_D, MASK_CRC32_D, match_opcode, 0 },
++{"crc32c.d", 64, INSN_CLASS_B,   "d,s",  MATCH_CRC32C_D, MASK_CRC32C_D, match_opcode, 0 },
+ 
+ /* Single-precision floating-point instruction subset */
+ {"frcsr",     0, INSN_CLASS_F,   "d",  MATCH_FRCSR, MASK_FRCSR, match_opcode, INSN_ALIAS },
+@@ -2867,9 +2858,7 @@ const struct riscv_ext_version riscv_ext_version_table[] =
+ {"c", ISA_SPEC_CLASS_20190608, 2, 0},
+ {"c", ISA_SPEC_CLASS_2P2,      2, 0},
+ 
+-{"b", ISA_SPEC_CLASS_NONE,     0, 92},
+-
+-{"v", ISA_SPEC_CLASS_NONE,     1, 0},
++{"v", ISA_SPEC_CLASS_DRAFT, 1, 0},
+ 
+ {"zicsr", ISA_SPEC_CLASS_20191213, 2, 0},
+ {"zicsr", ISA_SPEC_CLASS_20190608, 2, 0},
+@@ -2877,23 +2866,16 @@ const struct riscv_ext_version riscv_ext_version_table[] =
+ {"zifencei", ISA_SPEC_CLASS_20191213, 2, 0},
+ {"zifencei", ISA_SPEC_CLASS_20190608, 2, 0},
+ 
+-{"zfh", ISA_SPEC_CLASS_NONE, 0, 1},
+-
+-{"zba", ISA_SPEC_CLASS_NONE, 0, 92},
+-{"zbb", ISA_SPEC_CLASS_NONE, 0, 92},
+-{"zbc", ISA_SPEC_CLASS_NONE, 0, 92},
+-{"zbe", ISA_SPEC_CLASS_NONE, 0, 92},
+-{"zbf", ISA_SPEC_CLASS_NONE, 0, 92},
+-{"zbm", ISA_SPEC_CLASS_NONE, 0, 92},
+-{"zbp", ISA_SPEC_CLASS_NONE, 0, 92},
+-{"zbr", ISA_SPEC_CLASS_NONE, 0, 92},
+-{"zbs", ISA_SPEC_CLASS_NONE, 0, 92},
+-{"zbt", ISA_SPEC_CLASS_NONE, 0, 92},
+-
+-{"zvamo",   ISA_SPEC_CLASS_NONE, 1, 0},
+-{"zvediv",  ISA_SPEC_CLASS_NONE, 1, 0},
+-{"zvlsseg", ISA_SPEC_CLASS_NONE, 1, 0},
+-{"zvqmac",  ISA_SPEC_CLASS_NONE, 1, 0},
++{"zfh", ISA_SPEC_CLASS_DRAFT, 0, 1},
++
++{"zba", ISA_SPEC_CLASS_DRAFT, 0, 93},
++{"zbb", ISA_SPEC_CLASS_DRAFT, 0, 93},
++{"zbc", ISA_SPEC_CLASS_DRAFT, 0, 93},
++
++{"zvamo",   ISA_SPEC_CLASS_DRAFT, 1, 0},
++{"zvediv",  ISA_SPEC_CLASS_DRAFT, 1, 0},
++{"zvlsseg", ISA_SPEC_CLASS_DRAFT, 1, 0},
++{"zvqmac",  ISA_SPEC_CLASS_DRAFT, 1, 0},
+ 
+ /* Terminate the list.  */
+ {NULL, 0, 0, 0}
+-- 
+2.33.0
+

+ 28 - 0
recipes-devtools/gdb/files/0048-fix-incorrect-shfli-and-unshfli-opcode.patch

@@ -0,0 +1,28 @@
+From 121340d222814e74833c6cce8be887c20af20769 Mon Sep 17 00:00:00 2001
+From: "max.ma" <max.ma@starfivetech.com>
+Date: Wed, 30 Jun 2021 23:19:07 -0700
+Subject: [PATCH 48/48] fix incorrect shfli and unshfli opcode
+
+---
+ include/opcode/riscv-opc.h | 4 ++--
+ 1 file changed, 2 insertions(+), 2 deletions(-)
+
+diff --git a/include/opcode/riscv-opc.h b/include/opcode/riscv-opc.h
+index d481d5e2e6..12cc31ec45 100644
+--- a/include/opcode/riscv-opc.h
++++ b/include/opcode/riscv-opc.h
+@@ -308,9 +308,9 @@
+ #define MATCH_BFP 0x48007033
+ #define MASK_BFP  0xfe00707f
+ #define MATCH_SHFLI 0x8001013
+-#define MASK_SHFLI  0xfe00707f
++#define MASK_SHFLI  0xfc00707f
+ #define MATCH_UNSHFLI 0x8005013
+-#define MASK_UNSHFLI  0xfe00707f
++#define MASK_UNSHFLI  0xfc00707f
+ #define MATCH_BMATFLIP 0x60301013
+ #define MASK_BMATFLIP  0xfff0707f
+ #define MATCH_CRC32_D 0x61301013
+-- 
+2.33.0
+

+ 64 - 0
recipes-devtools/gdb/gdb_10.1.bbappend

@@ -0,0 +1,64 @@
+FILESEXTRAPATHS_prepend := "${THISDIR}/files:"
+
+SRCREV = "63a44e5923c859e99d3a8799fa8132b49a135241"
+BRANCH = "fsf-gdb-10.1-with-sim"
+
+S = "${WORKDIR}/git"
+
+SRC_URI = " git://github.com/riscv/riscv-binutils-gdb.git;branch=${BRANCH} \
+	file://0004-RISC-V-Minor-cleanup-and-testcases-improvement-for-a.patch \
+	file://0005-RISC-V-Don-t-allow-any-uppercase-letter-in-the-arch-.patch \
+	file://0006-RISC-V-Add-zifencei-and-prefixed-h-class-extensions.patch \
+	file://0007-RISC-V-Remove-the-unimplemented-extensions.patch \
+	file://0008-RISC-V-Improve-the-version-parsing-for-arch-string.patch \
+	file://0009-RISC-V-Support-to-add-implicit-extensions.patch \
+	file://0010-RISC-V-Support-to-add-implicit-extensions-for-G.patch \
+	file://0011-RISC-V-Fix-the-order-checking-for-Z-extension.patch \
+	file://0012-RISC-V-Support-RVV-according-to-vector-spec-v1.0-dra.patch \
+	file://0013-Extend-the-VL-nf-R-and-VS-nf-R-instruction-when-nf-i.patch \
+	file://0014-Remove-Vector-indexed-instruction-when-EEW-128.patch \
+	file://0015-Add-assembly-pseudo-instructions-vncvt.x.x.v.patch \
+	file://0016-Update-the-vector-spec-version-tag-Version-1.0-draft.patch \
+	file://0017-Added-reciprocal-and-reciprocal-square-root-estimate.patch \
+	file://0018-Added-element-width-hint-to-whole-register-loads-sto.patch \
+	file://0019-Update-the-vector-spec-version-tag-Version-1.0-draft.patch \
+	file://0020-Added-vrgatherei16-instruction.patch \
+	file://0021-Make-vlmul-bits-contiguous-in-vtype.patch \
+	file://0022-RISC-V-Clarify-the-supported-versions-for-the-unrati.patch \
+	file://0023-RISC-V-Convert-CSR-dwarf-numbers-to-gdb-register-num.patch \
+	file://0024-RISC-V-Update-the-vector-mask-constraints.patch \
+	file://0025-RISC-V-Add-the-missing-constraints-for-VL-nf-R-and-V.patch \
+	file://0026-RISC-V-Fix-the-constraints-for-vector-mask-and-compr.patch \
+	file://0027-RISC-V-Report-rvv-assembler-constraint-errors-in-det.patch \
+	file://0028-RISC-V-Support-Zfh-standard-extension-for-half-preci.patch \
+	file://0029-RISC-V-Support-.float16-directive-for-assembler.patch \
+	file://0030-Set-default-version-of-ZFH-to-0.1.patch \
+	file://0031-RISC-V-Add-assembly-pseudoinstructions-vneg.v-and-vf.patch \
+	file://0032-RISC-V-Added-ordered-unordered-vector-indexed-instru.patch \
+	file://0033-RISC-V-Rename-vncvt.x.x.v-to-vncvt.x.x.w.patch \
+	file://0034-SiFive-Support-SiFive-CLIC-CSRs.patch \
+	file://0035-SiFive-Support-SiFive-specific-cache-control-instruc.patch \
+	file://0036-Initial-support-for-RISC-V-Bitmanip-Spec-0.92.patch \
+	file://0037-RISC-V-Support-sub-extensions-of-B-for-march-parser.patch \
+	file://0038-RISC-V-Remove-ld-testcases-which-should-be-better-to.patch \
+	file://0039-RISC-V-Added-Removed-Updated-instructions-to-the-ris.patch \
+	file://0040-RISC-V-Add-missing-zext.-hw-pseudo-instructions.patch \
+	file://0041-RISC-V-Re-define-zba-zbb-zbc-and-zbs-extensions.patch \
+	file://0042-RISC-V-Define-pseudo-rev-orc-zip-unzip-as-alias-inst.patch \
+	file://0043-RISC-V-Add-testcases-for-ZBA-and-ZBB-instructions.patch \
+	file://0044-RISC-V-Add-sext.-bh-and-zext.-bhw-pseudo-instruction.patch \
+	file://0045-Fix-sim-build-since-op-match_func-have-more-argument.patch \
+	file://0046-SiFive-Add-RNMI-CSRs-and-MNRET-instruction.patch \
+	file://0047-RISC-V-Freeze-ZBA-ZBB-ZBC-to-0.93.patch \
+	file://0048-fix-incorrect-shfli-and-unshfli-opcode.patch \
+	file://0001-make-man-install-relative-to-DESTDIR.patch \
+	file://0002-mips-linux-nat-Define-_ABIO32-if-not-defined.patch \
+	file://0003-ppc-ptrace-Define-pt_regs-uapi_pt_regs-on-GLIBC-syst.patch \
+	file://0004-Add-support-for-Renesas-SH-sh4-architecture.patch \
+	file://0005-Dont-disable-libreadline.a-when-using-disable-static.patch \
+	file://0006-use-asm-sgidefs.h.patch \
+	file://0008-Change-order-of-CFLAGS.patch \
+	file://0009-resolve-restrict-keyword-conflict.patch \
+	file://0010-Fix-invalid-sigprocmask-call.patch \
+	file://0011-gdbserver-ctrl-c-handling.patch \
+"