0013-Extend-the-VL-nf-R-and-VS-nf-R-instruction-when-nf-i.patch 5.6 KB

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  1. From 3eca424ccd778b50ce4a0b862c79afcd57fc3a82 Mon Sep 17 00:00:00 2001
  2. From: Nelson Chu <nelson.chu@sifive.com>
  3. Date: Fri, 3 Jul 2020 12:54:09 +0800
  4. Subject: [PATCH 13/48] Extend the VL<nf>R and VS<nf>R instruction, when <nf>
  5. is 2, 4, 8.
  6. These instruction are added back in the risc-v vector spec,
  7. commit 0fec0e257cca5e389a0e1774e7d5aaac729b4ad2,
  8. Added clarifications on loads/stores.
  9. Note that the base V extension only enable the single register load/store
  10. variant with <nf> is 0. It is clear to me that how to enable other register
  11. load/store is <nf> is 2, 4, 8, so I will add the limitation when it is
  12. clarified.
  13. ---
  14. gas/testsuite/gas/riscv/vector-insns.d | 12 ++++++++++++
  15. gas/testsuite/gas/riscv/vector-insns.s | 13 +++++++++++++
  16. include/opcode/riscv-opc.h | 17 +++++++++++++++--
  17. opcodes/riscv-opc.c | 7 +++++++
  18. 4 files changed, 47 insertions(+), 2 deletions(-)
  19. diff --git a/gas/testsuite/gas/riscv/vector-insns.d b/gas/testsuite/gas/riscv/vector-insns.d
  20. index 5e7267c3f8..70366fb787 100644
  21. --- a/gas/testsuite/gas/riscv/vector-insns.d
  22. +++ b/gas/testsuite/gas/riscv/vector-insns.d
  23. @@ -1396,8 +1396,20 @@ Disassembly of section .text:
  24. [ ]+[0-9a-f]+:[ ]+f1057207[ ]+vlseg8e1024ff.v[ ]+v4,\(a0\),v0.t
  25. [ ]+[0-9a-f]+:[ ]+02850187[ ]+vl1r.v[ ]+v3,\(a0\)
  26. [ ]+[0-9a-f]+:[ ]+02850187[ ]+vl1r.v[ ]+v3,\(a0\)
  27. +[ ]+[0-9a-f]+:[ ]+22850107[ ]+vl2r.v[ ]+v2,\(a0\)
  28. +[ ]+[0-9a-f]+:[ ]+22850107[ ]+vl2r.v[ ]+v2,\(a0\)
  29. +[ ]+[0-9a-f]+:[ ]+62850207[ ]+vl4r.v[ ]+v4,\(a0\)
  30. +[ ]+[0-9a-f]+:[ ]+62850207[ ]+vl4r.v[ ]+v4,\(a0\)
  31. +[ ]+[0-9a-f]+:[ ]+e2850407[ ]+vl8r.v[ ]+v8,\(a0\)
  32. +[ ]+[0-9a-f]+:[ ]+e2850407[ ]+vl8r.v[ ]+v8,\(a0\)
  33. [ ]+[0-9a-f]+:[ ]+028581a7[ ]+vs1r.v[ ]+v3,\(a1\)
  34. [ ]+[0-9a-f]+:[ ]+028581a7[ ]+vs1r.v[ ]+v3,\(a1\)
  35. +[ ]+[0-9a-f]+:[ ]+22858127[ ]+vs2r.v[ ]+v2,\(a1\)
  36. +[ ]+[0-9a-f]+:[ ]+22858127[ ]+vs2r.v[ ]+v2,\(a1\)
  37. +[ ]+[0-9a-f]+:[ ]+62858227[ ]+vs4r.v[ ]+v4,\(a1\)
  38. +[ ]+[0-9a-f]+:[ ]+62858227[ ]+vs4r.v[ ]+v4,\(a1\)
  39. +[ ]+[0-9a-f]+:[ ]+e2858427[ ]+vs8r.v[ ]+v8,\(a1\)
  40. +[ ]+[0-9a-f]+:[ ]+e2858427[ ]+vs8r.v[ ]+v8,\(a1\)
  41. [ ]+[0-9a-f]+:[ ]+0685822f[ ]+vamoaddei8.v[ ]+v4,\(a1\),v8,v4
  42. [ ]+[0-9a-f]+:[ ]+0285822f[ ]+vamoaddei8.v[ ]+zero,\(a1\),v8,v4
  43. [ ]+[0-9a-f]+:[ ]+0485822f[ ]+vamoaddei8.v[ ]+v4,\(a1\),v8,v4,v0.t
  44. diff --git a/gas/testsuite/gas/riscv/vector-insns.s b/gas/testsuite/gas/riscv/vector-insns.s
  45. index 8b9a894418..edd94d7d29 100644
  46. --- a/gas/testsuite/gas/riscv/vector-insns.s
  47. +++ b/gas/testsuite/gas/riscv/vector-insns.s
  48. @@ -1644,8 +1644,21 @@
  49. vl1r.v v3, (a0)
  50. vl1r.v v3, 0(a0)
  51. + vl2r.v v2, (a0)
  52. + vl2r.v v2, 0(a0)
  53. + vl4r.v v4, (a0)
  54. + vl4r.v v4, 0(a0)
  55. + vl8r.v v8, (a0)
  56. + vl8r.v v8, 0(a0)
  57. +
  58. vs1r.v v3, (a1)
  59. vs1r.v v3, 0(a1)
  60. + vs2r.v v2, (a1)
  61. + vs2r.v v2, 0(a1)
  62. + vs4r.v v4, (a1)
  63. + vs4r.v v4, 0(a1)
  64. + vs8r.v v8, (a1)
  65. + vs8r.v v8, 0(a1)
  66. vamoaddei8.v v4, (a1), v8, v4
  67. vamoaddei8.v x0, (a1), v8, v4
  68. diff --git a/include/opcode/riscv-opc.h b/include/opcode/riscv-opc.h
  69. index 6ec4c2a33a..579bae2670 100644
  70. --- a/include/opcode/riscv-opc.h
  71. +++ b/include/opcode/riscv-opc.h
  72. @@ -611,8 +611,8 @@ NF MEW MOP VM LUMOP/RS2 RS1 WIDTH VD opcode
  73. 000 - 11 x xxxxx xxxxx --- xxxxx 0100111 VSXE<EEW>I
  74. 000 - 01 x xxxxx xxxxx --- xxxxx 0100111 VSUXE<EEW>I
  75. 000 - 00 x 10000 xxxxx --- xxxxx 0000111 VLE<EEW>FF
  76. -000 0 00 1 01000 xxxxx 000 xxxxx 0000111 VL<nf>R, nf = 1
  77. -000 0 00 1 01000 xxxxx 000 xxxxx 0100111 VS<nf>R, nf = 1
  78. +xxx 0 00 1 01000 xxxxx 000 xxxxx 0000111 VL<nf>R, nf = 1,2,4,8
  79. +xxx 0 00 1 01000 xxxxx 000 xxxxx 0100111 VS<nf>R, nf = 1,2,4,8
  80. xxx - 00 x 00000 xxxxx --- xxxxx 0000111 VLSEG<nf>E<EEW>
  81. xxx - 00 x 00000 xxxxx --- xxxxx 0100111 VSSEG<nf>E<EEW>
  82. @@ -1577,8 +1577,21 @@ xxx - 00 x 10000 xxxxx --- xxxxx 0000111 VLSEG<nf>E<EEW>FF
  83. #define MATCH_VL1RV 0x02800007
  84. #define MASK_VL1RV 0xfff0707f
  85. +#define MATCH_VL2RV 0x22800007
  86. +#define MASK_VL2RV 0xfff0707f
  87. +#define MATCH_VL4RV 0x62800007
  88. +#define MASK_VL4RV 0xfff0707f
  89. +#define MATCH_VL8RV 0xe2800007
  90. +#define MASK_VL8RV 0xfff0707f
  91. +
  92. #define MATCH_VS1RV 0x02800027
  93. #define MASK_VS1RV 0xfff0707f
  94. +#define MATCH_VS2RV 0x22800027
  95. +#define MASK_VS2RV 0xfff0707f
  96. +#define MATCH_VS4RV 0x62800027
  97. +#define MASK_VS4RV 0xfff0707f
  98. +#define MATCH_VS8RV 0xe2800027
  99. +#define MASK_VS8RV 0xfff0707f
  100. /* Temporary AMO encoding info
  101. diff --git a/opcodes/riscv-opc.c b/opcodes/riscv-opc.c
  102. index fcd87e2261..ce9b10e411 100644
  103. --- a/opcodes/riscv-opc.c
  104. +++ b/opcodes/riscv-opc.c
  105. @@ -1563,7 +1563,14 @@ const struct riscv_opcode riscv_opcodes[] =
  106. {"vlseg8e1024ff.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s)Vm", MATCH_VLSEG8E1024FFV, MASK_VLSEG8E1024FFV, match_vd_neq_vm, INSN_DREF },
  107. {"vl1r.v", 0, INSN_CLASS_V, "Vd,0(s)", MATCH_VL1RV, MASK_VL1RV, match_opcode, INSN_DREF },
  108. +{"vl2r.v", 0, INSN_CLASS_V, "Vd,0(s)", MATCH_VL2RV, MASK_VL2RV, match_opcode, INSN_DREF },
  109. +{"vl4r.v", 0, INSN_CLASS_V, "Vd,0(s)", MATCH_VL4RV, MASK_VL4RV, match_opcode, INSN_DREF },
  110. +{"vl8r.v", 0, INSN_CLASS_V, "Vd,0(s)", MATCH_VL8RV, MASK_VL8RV, match_opcode, INSN_DREF },
  111. +
  112. {"vs1r.v", 0, INSN_CLASS_V, "Vd,0(s)", MATCH_VS1RV, MASK_VS1RV, match_opcode, INSN_DREF },
  113. +{"vs2r.v", 0, INSN_CLASS_V, "Vd,0(s)", MATCH_VS2RV, MASK_VS2RV, match_opcode, INSN_DREF },
  114. +{"vs4r.v", 0, INSN_CLASS_V, "Vd,0(s)", MATCH_VS4RV, MASK_VS4RV, match_opcode, INSN_DREF },
  115. +{"vs8r.v", 0, INSN_CLASS_V, "Vd,0(s)", MATCH_VS8RV, MASK_VS8RV, match_opcode, INSN_DREF },
  116. {"vamoaddei8.v", 0, INSN_CLASS_V_OR_ZVAMO, "Ve,0(s),Vt,VfVm", MATCH_VAMOADDEI8V, MASK_VAMOADDEI8V, match_opcode, INSN_DREF},
  117. {"vamoswapei8.v", 0, INSN_CLASS_V_OR_ZVAMO, "Ve,0(s),Vt,VfVm", MATCH_VAMOSWAPEI8V, MASK_VAMOSWAPEI8V, match_opcode, INSN_DREF},
  118. --
  119. 2.33.0