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- From 1ac8c2ffcb4a0a98d0597e71f9313352bda11ee3 Mon Sep 17 00:00:00 2001
- From: Nelson Chu <nelson.chu@sifive.com>
- Date: Wed, 30 Dec 2020 11:29:45 +0800
- Subject: [PATCH 46/48] SiFive: Add RNMI CSRs and MNRET instruction.
- https://github.com/sifive/arch-specs/blob/master/nmi.adoc#rnmi-operation.
- There are four RNMI CSRs, mnscratch (0x350), mnepc (0x351), mncause (0x352)
- and mnstatus (0x353). And there is a new instruction, MNRET, which has the
- same encoding as MRET, except the func12 is 0x702 (011100000010).
- ---
- gas/config/tc-riscv.c | 1 +
- gas/testsuite/gas/riscv/priv-reg-version-1p10.d | 4 ++++
- gas/testsuite/gas/riscv/priv-reg-version-1p11.d | 4 ++++
- gas/testsuite/gas/riscv/priv-reg-version-1p9p1.d | 4 ++++
- gas/testsuite/gas/riscv/priv-reg.s | 6 ++++++
- include/opcode/riscv-opc.h | 11 +++++++++++
- include/opcode/riscv.h | 11 ++++++-----
- opcodes/riscv-opc.c | 1 +
- 8 files changed, 37 insertions(+), 5 deletions(-)
- diff --git a/gas/config/tc-riscv.c b/gas/config/tc-riscv.c
- index bee1186c3a..60b9a92d77 100644
- --- a/gas/config/tc-riscv.c
- +++ b/gas/config/tc-riscv.c
- @@ -760,6 +760,7 @@ riscv_csr_address (const char *csr_name,
- break;
- case CSR_CLASS_DEBUG:
- case CSR_CLASS_CLIC:
- + case CSR_CLASS_RNMI:
- need_check_version = FALSE;
- break;
- default:
- diff --git a/gas/testsuite/gas/riscv/priv-reg-version-1p10.d b/gas/testsuite/gas/riscv/priv-reg-version-1p10.d
- index 2db8d2021e..61c75ee0fc 100644
- --- a/gas/testsuite/gas/riscv/priv-reg-version-1p10.d
- +++ b/gas/testsuite/gas/riscv/priv-reg-version-1p10.d
- @@ -276,3 +276,7 @@ Disassembly of section .text:
- [ ]+[0-9a-f]+:[ ]+34502573[ ]+csrr[ ]+a0,mnxti
- [ ]+[0-9a-f]+:[ ]+34602573[ ]+csrr[ ]+a0,mintstatus
- [ ]+[0-9a-f]+:[ ]+34811173[ ]+csrrw[ ]+sp,mscratchcsw,sp
- +[ ]+[0-9a-f]+:[ ]+35002573[ ]+csrr[ ]+a0,mnscratch
- +[ ]+[0-9a-f]+:[ ]+35102573[ ]+csrr[ ]+a0,mnepc
- +[ ]+[0-9a-f]+:[ ]+35202573[ ]+csrr[ ]+a0,mncause
- +[ ]+[0-9a-f]+:[ ]+35302573[ ]+csrr[ ]+a0,mnstatus
- diff --git a/gas/testsuite/gas/riscv/priv-reg-version-1p11.d b/gas/testsuite/gas/riscv/priv-reg-version-1p11.d
- index 77ed98891c..a92e95086b 100644
- --- a/gas/testsuite/gas/riscv/priv-reg-version-1p11.d
- +++ b/gas/testsuite/gas/riscv/priv-reg-version-1p11.d
- @@ -276,3 +276,7 @@ Disassembly of section .text:
- [ ]+[0-9a-f]+:[ ]+34502573[ ]+csrr[ ]+a0,mnxti
- [ ]+[0-9a-f]+:[ ]+34602573[ ]+csrr[ ]+a0,mintstatus
- [ ]+[0-9a-f]+:[ ]+34811173[ ]+csrrw[ ]+sp,mscratchcsw,sp
- +[ ]+[0-9a-f]+:[ ]+35002573[ ]+csrr[ ]+a0,mnscratch
- +[ ]+[0-9a-f]+:[ ]+35102573[ ]+csrr[ ]+a0,mnepc
- +[ ]+[0-9a-f]+:[ ]+35202573[ ]+csrr[ ]+a0,mncause
- +[ ]+[0-9a-f]+:[ ]+35302573[ ]+csrr[ ]+a0,mnstatus
- diff --git a/gas/testsuite/gas/riscv/priv-reg-version-1p9p1.d b/gas/testsuite/gas/riscv/priv-reg-version-1p9p1.d
- index 7e1515f8be..27b599aa86 100644
- --- a/gas/testsuite/gas/riscv/priv-reg-version-1p9p1.d
- +++ b/gas/testsuite/gas/riscv/priv-reg-version-1p9p1.d
- @@ -276,3 +276,7 @@ Disassembly of section .text:
- [ ]+[0-9a-f]+:[ ]+34502573[ ]+csrr[ ]+a0,mnxti
- [ ]+[0-9a-f]+:[ ]+34602573[ ]+csrr[ ]+a0,mintstatus
- [ ]+[0-9a-f]+:[ ]+34811173[ ]+csrrw[ ]+sp,mscratchcsw,sp
- +[ ]+[0-9a-f]+:[ ]+35002573[ ]+csrr[ ]+a0,mnscratch
- +[ ]+[0-9a-f]+:[ ]+35102573[ ]+csrr[ ]+a0,mnepc
- +[ ]+[0-9a-f]+:[ ]+35202573[ ]+csrr[ ]+a0,mncause
- +[ ]+[0-9a-f]+:[ ]+35302573[ ]+csrr[ ]+a0,mnstatus
- diff --git a/gas/testsuite/gas/riscv/priv-reg.s b/gas/testsuite/gas/riscv/priv-reg.s
- index bce7d00b81..035e06e255 100644
- --- a/gas/testsuite/gas/riscv/priv-reg.s
- +++ b/gas/testsuite/gas/riscv/priv-reg.s
- @@ -297,3 +297,9 @@
- csr mnxti
- csr mintstatus
- csrrw sp,mscratchcsw,sp
- +
- + # RNMI registers
- + csr mnscratch
- + csr mnepc
- + csr mncause
- + csr mnstatus
- diff --git a/include/opcode/riscv-opc.h b/include/opcode/riscv-opc.h
- index 500be26f0f..1faa2a8a8a 100644
- --- a/include/opcode/riscv-opc.h
- +++ b/include/opcode/riscv-opc.h
- @@ -453,6 +453,8 @@
- #define MASK_HRET 0xffffffff
- #define MATCH_MRET 0x30200073
- #define MASK_MRET 0xffffffff
- +#define MATCH_MNRET 0x70200073
- +#define MASK_MNRET 0xffffffff
- #define MATCH_DRET 0x7b200073
- #define MASK_DRET 0xffffffff
- #define MATCH_SFENCE_VM 0x10400073
- @@ -3567,6 +3569,10 @@ funct6 VM VS2 VS1/RS1/IMM funct3 VD opcode
- #define CSR_MNXTI 0x345
- #define CSR_MINTSTATUS 0x346
- #define CSR_MSCRATCHCSW 0x348
- +#define CSR_MNSCRATCH 0x350
- +#define CSR_MNEPC 0x351
- +#define CSR_MNCAUSE 0x352
- +#define CSR_MNSTATUS 0x353
- #endif /* RISCV_ENCODING_H. */
- #ifdef DECLARE_INSN
- DECLARE_INSN(slli_rv32, MATCH_SLLI_RV32, MASK_SLLI_RV32)
- @@ -3784,6 +3790,7 @@ DECLARE_INSN(uret, MATCH_URET, MASK_URET)
- DECLARE_INSN(sret, MATCH_SRET, MASK_SRET)
- DECLARE_INSN(hret, MATCH_HRET, MASK_HRET)
- DECLARE_INSN(mret, MATCH_MRET, MASK_MRET)
- +DECLARE_INSN(mnret, MATCH_MNRET, MASK_MNRET)
- DECLARE_INSN(dret, MATCH_DRET, MASK_DRET)
- DECLARE_INSN(sfence_vm, MATCH_SFENCE_VM, MASK_SFENCE_VM)
- DECLARE_INSN(sfence_vma, MATCH_SFENCE_VMA, MASK_SFENCE_VMA)
- @@ -4256,6 +4263,10 @@ DECLARE_CSR(mtvt, CSR_MTVT, CSR_CLASS_CLIC, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLAS
- DECLARE_CSR(mnxti, CSR_MNXTI, CSR_CLASS_CLIC, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE)
- DECLARE_CSR(mintstatus, CSR_MINTSTATUS, CSR_CLASS_CLIC, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE)
- DECLARE_CSR(mscratchcsw, CSR_MSCRATCHCSW, CSR_CLASS_CLIC, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE)
- +DECLARE_CSR(mnscratch, CSR_MNSCRATCH, CSR_CLASS_RNMI, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE)
- +DECLARE_CSR(mnepc, CSR_MNEPC, CSR_CLASS_RNMI, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE)
- +DECLARE_CSR(mncause, CSR_MNCAUSE, CSR_CLASS_RNMI, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE)
- +DECLARE_CSR(mnstatus, CSR_MNSTATUS, CSR_CLASS_RNMI, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE)
- #endif /* DECLARE_CSR. */
- #ifdef DECLARE_CSR_ALIAS
- DECLARE_CSR_ALIAS(ubadaddr, CSR_UTVAL, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_1P10)
- diff --git a/include/opcode/riscv.h b/include/opcode/riscv.h
- index 71498563c3..02800fda64 100644
- --- a/include/opcode/riscv.h
- +++ b/include/opcode/riscv.h
- @@ -470,11 +470,12 @@ enum riscv_csr_class
- CSR_CLASS_NONE,
-
- CSR_CLASS_I,
- - CSR_CLASS_I_32, /* rv32 only */
- - CSR_CLASS_F, /* f-ext only */
- - CSR_CLASS_V, /* v-ext only */
- - CSR_CLASS_DEBUG, /* debug CSR */
- - CSR_CLASS_CLIC /* clic CSR */
- + CSR_CLASS_I_32, /* rv32 only */
- + CSR_CLASS_F, /* f-ext only */
- + CSR_CLASS_V, /* v-ext only */
- + CSR_CLASS_DEBUG, /* debug CSR */
- + CSR_CLASS_CLIC, /* clic CSR */
- + CSR_CLASS_RNMI, /* rnmi CSR */
- };
-
- /* The current supported privilege spec versions. */
- diff --git a/opcodes/riscv-opc.c b/opcodes/riscv-opc.c
- index 5f0885b5c6..5c07c0a2db 100644
- --- a/opcodes/riscv-opc.c
- +++ b/opcodes/riscv-opc.c
- @@ -1581,6 +1581,7 @@ const struct riscv_opcode riscv_opcodes[] =
- {"sret", 0, INSN_CLASS_I, "", MATCH_SRET, MASK_SRET, match_opcode, 0 },
- {"hret", 0, INSN_CLASS_I, "", MATCH_HRET, MASK_HRET, match_opcode, 0 },
- {"mret", 0, INSN_CLASS_I, "", MATCH_MRET, MASK_MRET, match_opcode, 0 },
- +{"mnret", 0, INSN_CLASS_I, "", MATCH_MNRET, MASK_MNRET, match_opcode, 0 },
- {"dret", 0, INSN_CLASS_I, "", MATCH_DRET, MASK_DRET, match_opcode, 0 },
- {"sfence.vm", 0, INSN_CLASS_I, "", MATCH_SFENCE_VM, MASK_SFENCE_VM | MASK_RS1, match_opcode, 0 },
- {"sfence.vm", 0, INSN_CLASS_I, "s", MATCH_SFENCE_VM, MASK_SFENCE_VM, match_opcode, 0 },
- --
- 2.33.0
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