0046-SiFive-Add-RNMI-CSRs-and-MNRET-instruction.patch 7.7 KB

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  1. From 1ac8c2ffcb4a0a98d0597e71f9313352bda11ee3 Mon Sep 17 00:00:00 2001
  2. From: Nelson Chu <nelson.chu@sifive.com>
  3. Date: Wed, 30 Dec 2020 11:29:45 +0800
  4. Subject: [PATCH 46/48] SiFive: Add RNMI CSRs and MNRET instruction.
  5. https://github.com/sifive/arch-specs/blob/master/nmi.adoc#rnmi-operation.
  6. There are four RNMI CSRs, mnscratch (0x350), mnepc (0x351), mncause (0x352)
  7. and mnstatus (0x353). And there is a new instruction, MNRET, which has the
  8. same encoding as MRET, except the func12 is 0x702 (011100000010).
  9. ---
  10. gas/config/tc-riscv.c | 1 +
  11. gas/testsuite/gas/riscv/priv-reg-version-1p10.d | 4 ++++
  12. gas/testsuite/gas/riscv/priv-reg-version-1p11.d | 4 ++++
  13. gas/testsuite/gas/riscv/priv-reg-version-1p9p1.d | 4 ++++
  14. gas/testsuite/gas/riscv/priv-reg.s | 6 ++++++
  15. include/opcode/riscv-opc.h | 11 +++++++++++
  16. include/opcode/riscv.h | 11 ++++++-----
  17. opcodes/riscv-opc.c | 1 +
  18. 8 files changed, 37 insertions(+), 5 deletions(-)
  19. diff --git a/gas/config/tc-riscv.c b/gas/config/tc-riscv.c
  20. index bee1186c3a..60b9a92d77 100644
  21. --- a/gas/config/tc-riscv.c
  22. +++ b/gas/config/tc-riscv.c
  23. @@ -760,6 +760,7 @@ riscv_csr_address (const char *csr_name,
  24. break;
  25. case CSR_CLASS_DEBUG:
  26. case CSR_CLASS_CLIC:
  27. + case CSR_CLASS_RNMI:
  28. need_check_version = FALSE;
  29. break;
  30. default:
  31. diff --git a/gas/testsuite/gas/riscv/priv-reg-version-1p10.d b/gas/testsuite/gas/riscv/priv-reg-version-1p10.d
  32. index 2db8d2021e..61c75ee0fc 100644
  33. --- a/gas/testsuite/gas/riscv/priv-reg-version-1p10.d
  34. +++ b/gas/testsuite/gas/riscv/priv-reg-version-1p10.d
  35. @@ -276,3 +276,7 @@ Disassembly of section .text:
  36. [ ]+[0-9a-f]+:[ ]+34502573[ ]+csrr[ ]+a0,mnxti
  37. [ ]+[0-9a-f]+:[ ]+34602573[ ]+csrr[ ]+a0,mintstatus
  38. [ ]+[0-9a-f]+:[ ]+34811173[ ]+csrrw[ ]+sp,mscratchcsw,sp
  39. +[ ]+[0-9a-f]+:[ ]+35002573[ ]+csrr[ ]+a0,mnscratch
  40. +[ ]+[0-9a-f]+:[ ]+35102573[ ]+csrr[ ]+a0,mnepc
  41. +[ ]+[0-9a-f]+:[ ]+35202573[ ]+csrr[ ]+a0,mncause
  42. +[ ]+[0-9a-f]+:[ ]+35302573[ ]+csrr[ ]+a0,mnstatus
  43. diff --git a/gas/testsuite/gas/riscv/priv-reg-version-1p11.d b/gas/testsuite/gas/riscv/priv-reg-version-1p11.d
  44. index 77ed98891c..a92e95086b 100644
  45. --- a/gas/testsuite/gas/riscv/priv-reg-version-1p11.d
  46. +++ b/gas/testsuite/gas/riscv/priv-reg-version-1p11.d
  47. @@ -276,3 +276,7 @@ Disassembly of section .text:
  48. [ ]+[0-9a-f]+:[ ]+34502573[ ]+csrr[ ]+a0,mnxti
  49. [ ]+[0-9a-f]+:[ ]+34602573[ ]+csrr[ ]+a0,mintstatus
  50. [ ]+[0-9a-f]+:[ ]+34811173[ ]+csrrw[ ]+sp,mscratchcsw,sp
  51. +[ ]+[0-9a-f]+:[ ]+35002573[ ]+csrr[ ]+a0,mnscratch
  52. +[ ]+[0-9a-f]+:[ ]+35102573[ ]+csrr[ ]+a0,mnepc
  53. +[ ]+[0-9a-f]+:[ ]+35202573[ ]+csrr[ ]+a0,mncause
  54. +[ ]+[0-9a-f]+:[ ]+35302573[ ]+csrr[ ]+a0,mnstatus
  55. diff --git a/gas/testsuite/gas/riscv/priv-reg-version-1p9p1.d b/gas/testsuite/gas/riscv/priv-reg-version-1p9p1.d
  56. index 7e1515f8be..27b599aa86 100644
  57. --- a/gas/testsuite/gas/riscv/priv-reg-version-1p9p1.d
  58. +++ b/gas/testsuite/gas/riscv/priv-reg-version-1p9p1.d
  59. @@ -276,3 +276,7 @@ Disassembly of section .text:
  60. [ ]+[0-9a-f]+:[ ]+34502573[ ]+csrr[ ]+a0,mnxti
  61. [ ]+[0-9a-f]+:[ ]+34602573[ ]+csrr[ ]+a0,mintstatus
  62. [ ]+[0-9a-f]+:[ ]+34811173[ ]+csrrw[ ]+sp,mscratchcsw,sp
  63. +[ ]+[0-9a-f]+:[ ]+35002573[ ]+csrr[ ]+a0,mnscratch
  64. +[ ]+[0-9a-f]+:[ ]+35102573[ ]+csrr[ ]+a0,mnepc
  65. +[ ]+[0-9a-f]+:[ ]+35202573[ ]+csrr[ ]+a0,mncause
  66. +[ ]+[0-9a-f]+:[ ]+35302573[ ]+csrr[ ]+a0,mnstatus
  67. diff --git a/gas/testsuite/gas/riscv/priv-reg.s b/gas/testsuite/gas/riscv/priv-reg.s
  68. index bce7d00b81..035e06e255 100644
  69. --- a/gas/testsuite/gas/riscv/priv-reg.s
  70. +++ b/gas/testsuite/gas/riscv/priv-reg.s
  71. @@ -297,3 +297,9 @@
  72. csr mnxti
  73. csr mintstatus
  74. csrrw sp,mscratchcsw,sp
  75. +
  76. + # RNMI registers
  77. + csr mnscratch
  78. + csr mnepc
  79. + csr mncause
  80. + csr mnstatus
  81. diff --git a/include/opcode/riscv-opc.h b/include/opcode/riscv-opc.h
  82. index 500be26f0f..1faa2a8a8a 100644
  83. --- a/include/opcode/riscv-opc.h
  84. +++ b/include/opcode/riscv-opc.h
  85. @@ -453,6 +453,8 @@
  86. #define MASK_HRET 0xffffffff
  87. #define MATCH_MRET 0x30200073
  88. #define MASK_MRET 0xffffffff
  89. +#define MATCH_MNRET 0x70200073
  90. +#define MASK_MNRET 0xffffffff
  91. #define MATCH_DRET 0x7b200073
  92. #define MASK_DRET 0xffffffff
  93. #define MATCH_SFENCE_VM 0x10400073
  94. @@ -3567,6 +3569,10 @@ funct6 VM VS2 VS1/RS1/IMM funct3 VD opcode
  95. #define CSR_MNXTI 0x345
  96. #define CSR_MINTSTATUS 0x346
  97. #define CSR_MSCRATCHCSW 0x348
  98. +#define CSR_MNSCRATCH 0x350
  99. +#define CSR_MNEPC 0x351
  100. +#define CSR_MNCAUSE 0x352
  101. +#define CSR_MNSTATUS 0x353
  102. #endif /* RISCV_ENCODING_H. */
  103. #ifdef DECLARE_INSN
  104. DECLARE_INSN(slli_rv32, MATCH_SLLI_RV32, MASK_SLLI_RV32)
  105. @@ -3784,6 +3790,7 @@ DECLARE_INSN(uret, MATCH_URET, MASK_URET)
  106. DECLARE_INSN(sret, MATCH_SRET, MASK_SRET)
  107. DECLARE_INSN(hret, MATCH_HRET, MASK_HRET)
  108. DECLARE_INSN(mret, MATCH_MRET, MASK_MRET)
  109. +DECLARE_INSN(mnret, MATCH_MNRET, MASK_MNRET)
  110. DECLARE_INSN(dret, MATCH_DRET, MASK_DRET)
  111. DECLARE_INSN(sfence_vm, MATCH_SFENCE_VM, MASK_SFENCE_VM)
  112. DECLARE_INSN(sfence_vma, MATCH_SFENCE_VMA, MASK_SFENCE_VMA)
  113. @@ -4256,6 +4263,10 @@ DECLARE_CSR(mtvt, CSR_MTVT, CSR_CLASS_CLIC, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLAS
  114. DECLARE_CSR(mnxti, CSR_MNXTI, CSR_CLASS_CLIC, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE)
  115. DECLARE_CSR(mintstatus, CSR_MINTSTATUS, CSR_CLASS_CLIC, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE)
  116. DECLARE_CSR(mscratchcsw, CSR_MSCRATCHCSW, CSR_CLASS_CLIC, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE)
  117. +DECLARE_CSR(mnscratch, CSR_MNSCRATCH, CSR_CLASS_RNMI, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE)
  118. +DECLARE_CSR(mnepc, CSR_MNEPC, CSR_CLASS_RNMI, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE)
  119. +DECLARE_CSR(mncause, CSR_MNCAUSE, CSR_CLASS_RNMI, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE)
  120. +DECLARE_CSR(mnstatus, CSR_MNSTATUS, CSR_CLASS_RNMI, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE)
  121. #endif /* DECLARE_CSR. */
  122. #ifdef DECLARE_CSR_ALIAS
  123. DECLARE_CSR_ALIAS(ubadaddr, CSR_UTVAL, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_1P10)
  124. diff --git a/include/opcode/riscv.h b/include/opcode/riscv.h
  125. index 71498563c3..02800fda64 100644
  126. --- a/include/opcode/riscv.h
  127. +++ b/include/opcode/riscv.h
  128. @@ -470,11 +470,12 @@ enum riscv_csr_class
  129. CSR_CLASS_NONE,
  130. CSR_CLASS_I,
  131. - CSR_CLASS_I_32, /* rv32 only */
  132. - CSR_CLASS_F, /* f-ext only */
  133. - CSR_CLASS_V, /* v-ext only */
  134. - CSR_CLASS_DEBUG, /* debug CSR */
  135. - CSR_CLASS_CLIC /* clic CSR */
  136. + CSR_CLASS_I_32, /* rv32 only */
  137. + CSR_CLASS_F, /* f-ext only */
  138. + CSR_CLASS_V, /* v-ext only */
  139. + CSR_CLASS_DEBUG, /* debug CSR */
  140. + CSR_CLASS_CLIC, /* clic CSR */
  141. + CSR_CLASS_RNMI, /* rnmi CSR */
  142. };
  143. /* The current supported privilege spec versions. */
  144. diff --git a/opcodes/riscv-opc.c b/opcodes/riscv-opc.c
  145. index 5f0885b5c6..5c07c0a2db 100644
  146. --- a/opcodes/riscv-opc.c
  147. +++ b/opcodes/riscv-opc.c
  148. @@ -1581,6 +1581,7 @@ const struct riscv_opcode riscv_opcodes[] =
  149. {"sret", 0, INSN_CLASS_I, "", MATCH_SRET, MASK_SRET, match_opcode, 0 },
  150. {"hret", 0, INSN_CLASS_I, "", MATCH_HRET, MASK_HRET, match_opcode, 0 },
  151. {"mret", 0, INSN_CLASS_I, "", MATCH_MRET, MASK_MRET, match_opcode, 0 },
  152. +{"mnret", 0, INSN_CLASS_I, "", MATCH_MNRET, MASK_MNRET, match_opcode, 0 },
  153. {"dret", 0, INSN_CLASS_I, "", MATCH_DRET, MASK_DRET, match_opcode, 0 },
  154. {"sfence.vm", 0, INSN_CLASS_I, "", MATCH_SFENCE_VM, MASK_SFENCE_VM | MASK_RS1, match_opcode, 0 },
  155. {"sfence.vm", 0, INSN_CLASS_I, "s", MATCH_SFENCE_VM, MASK_SFENCE_VM, match_opcode, 0 },
  156. --
  157. 2.33.0