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- From f9e8a9be0538c55b9bbe7a85b0cbce1a0d5cd574 Mon Sep 17 00:00:00 2001
- From: Nelson Chu <nelson.chu@sifive.com>
- Date: Mon, 6 Jul 2020 13:27:29 +0800
- Subject: [PATCH 14/48] Remove Vector indexed instruction when EEW >= 128.
- These instruction are removed in the risc-v vector spec,
- commit 0fec0e257cca5e389a0e1774e7d5aaac729b4ad2,
- Added clarifications on loads/stores.
- ---
- gas/testsuite/gas/riscv/vector-insns.d | 36 -----------------------
- gas/testsuite/gas/riscv/vector-insns.s | 40 --------------------------
- include/opcode/riscv-opc.h | 30 ++-----------------
- opcodes/riscv-opc.c | 12 --------
- 4 files changed, 3 insertions(+), 115 deletions(-)
- diff --git a/gas/testsuite/gas/riscv/vector-insns.d b/gas/testsuite/gas/riscv/vector-insns.d
- index 70366fb787..634ff2945c 100644
- --- a/gas/testsuite/gas/riscv/vector-insns.d
- +++ b/gas/testsuite/gas/riscv/vector-insns.d
- @@ -158,42 +158,6 @@ Disassembly of section .text:
- [ ]+[0-9a-f]+:[ ]+06c57227[ ]+vsuxei64.v[ ]+v4,\(a0\),v12
- [ ]+[0-9a-f]+:[ ]+06c57227[ ]+vsuxei64.v[ ]+v4,\(a0\),v12
- [ ]+[0-9a-f]+:[ ]+04c57227[ ]+vsuxei64.v[ ]+v4,\(a0\),v12,v0.t
- -[ ]+[0-9a-f]+:[ ]+1ec50207[ ]+vlxei128.v[ ]+v4,\(a0\),v12
- -[ ]+[0-9a-f]+:[ ]+1ec50207[ ]+vlxei128.v[ ]+v4,\(a0\),v12
- -[ ]+[0-9a-f]+:[ ]+1cc50207[ ]+vlxei128.v[ ]+v4,\(a0\),v12,v0.t
- -[ ]+[0-9a-f]+:[ ]+1ec50227[ ]+vsxei128.v[ ]+v4,\(a0\),v12
- -[ ]+[0-9a-f]+:[ ]+1ec50227[ ]+vsxei128.v[ ]+v4,\(a0\),v12
- -[ ]+[0-9a-f]+:[ ]+1cc50227[ ]+vsxei128.v[ ]+v4,\(a0\),v12,v0.t
- -[ ]+[0-9a-f]+:[ ]+16c50227[ ]+vsuxei128.v[ ]+v4,\(a0\),v12
- -[ ]+[0-9a-f]+:[ ]+16c50227[ ]+vsuxei128.v[ ]+v4,\(a0\),v12
- -[ ]+[0-9a-f]+:[ ]+14c50227[ ]+vsuxei128.v[ ]+v4,\(a0\),v12,v0.t
- -[ ]+[0-9a-f]+:[ ]+1ec55207[ ]+vlxei256.v[ ]+v4,\(a0\),v12
- -[ ]+[0-9a-f]+:[ ]+1ec55207[ ]+vlxei256.v[ ]+v4,\(a0\),v12
- -[ ]+[0-9a-f]+:[ ]+1cc55207[ ]+vlxei256.v[ ]+v4,\(a0\),v12,v0.t
- -[ ]+[0-9a-f]+:[ ]+1ec55227[ ]+vsxei256.v[ ]+v4,\(a0\),v12
- -[ ]+[0-9a-f]+:[ ]+1ec55227[ ]+vsxei256.v[ ]+v4,\(a0\),v12
- -[ ]+[0-9a-f]+:[ ]+1cc55227[ ]+vsxei256.v[ ]+v4,\(a0\),v12,v0.t
- -[ ]+[0-9a-f]+:[ ]+16c55227[ ]+vsuxei256.v[ ]+v4,\(a0\),v12
- -[ ]+[0-9a-f]+:[ ]+16c55227[ ]+vsuxei256.v[ ]+v4,\(a0\),v12
- -[ ]+[0-9a-f]+:[ ]+14c55227[ ]+vsuxei256.v[ ]+v4,\(a0\),v12,v0.t
- -[ ]+[0-9a-f]+:[ ]+1ec56207[ ]+vlxei512.v[ ]+v4,\(a0\),v12
- -[ ]+[0-9a-f]+:[ ]+1ec56207[ ]+vlxei512.v[ ]+v4,\(a0\),v12
- -[ ]+[0-9a-f]+:[ ]+1cc56207[ ]+vlxei512.v[ ]+v4,\(a0\),v12,v0.t
- -[ ]+[0-9a-f]+:[ ]+1ec56227[ ]+vsxei512.v[ ]+v4,\(a0\),v12
- -[ ]+[0-9a-f]+:[ ]+1ec56227[ ]+vsxei512.v[ ]+v4,\(a0\),v12
- -[ ]+[0-9a-f]+:[ ]+1cc56227[ ]+vsxei512.v[ ]+v4,\(a0\),v12,v0.t
- -[ ]+[0-9a-f]+:[ ]+16c56227[ ]+vsuxei512.v[ ]+v4,\(a0\),v12
- -[ ]+[0-9a-f]+:[ ]+16c56227[ ]+vsuxei512.v[ ]+v4,\(a0\),v12
- -[ ]+[0-9a-f]+:[ ]+14c56227[ ]+vsuxei512.v[ ]+v4,\(a0\),v12,v0.t
- -[ ]+[0-9a-f]+:[ ]+1ec57207[ ]+vlxei1024.v[ ]+v4,\(a0\),v12
- -[ ]+[0-9a-f]+:[ ]+1ec57207[ ]+vlxei1024.v[ ]+v4,\(a0\),v12
- -[ ]+[0-9a-f]+:[ ]+1cc57207[ ]+vlxei1024.v[ ]+v4,\(a0\),v12,v0.t
- -[ ]+[0-9a-f]+:[ ]+1ec57227[ ]+vsxei1024.v[ ]+v4,\(a0\),v12
- -[ ]+[0-9a-f]+:[ ]+1ec57227[ ]+vsxei1024.v[ ]+v4,\(a0\),v12
- -[ ]+[0-9a-f]+:[ ]+1cc57227[ ]+vsxei1024.v[ ]+v4,\(a0\),v12,v0.t
- -[ ]+[0-9a-f]+:[ ]+16c57227[ ]+vsuxei1024.v[ ]+v4,\(a0\),v12
- -[ ]+[0-9a-f]+:[ ]+16c57227[ ]+vsuxei1024.v[ ]+v4,\(a0\),v12
- -[ ]+[0-9a-f]+:[ ]+14c57227[ ]+vsuxei1024.v[ ]+v4,\(a0\),v12,v0.t
- [ ]+[0-9a-f]+:[ ]+03050207[ ]+vle8ff.v[ ]+v4,\(a0\)
- [ ]+[0-9a-f]+:[ ]+03050207[ ]+vle8ff.v[ ]+v4,\(a0\)
- [ ]+[0-9a-f]+:[ ]+01050207[ ]+vle8ff.v[ ]+v4,\(a0\),v0.t
- diff --git a/gas/testsuite/gas/riscv/vector-insns.s b/gas/testsuite/gas/riscv/vector-insns.s
- index edd94d7d29..e6cfcad9ba 100644
- --- a/gas/testsuite/gas/riscv/vector-insns.s
- +++ b/gas/testsuite/gas/riscv/vector-insns.s
- @@ -170,46 +170,6 @@
- vsuxei64.v v4, 0(a0), v12
- vsuxei64.v v4, (a0), v12, v0.t
-
- - vlxei128.v v4, (a0), v12
- - vlxei128.v v4, 0(a0), v12
- - vlxei128.v v4, (a0), v12, v0.t
- - vsxei128.v v4, (a0), v12
- - vsxei128.v v4, 0(a0), v12
- - vsxei128.v v4, (a0), v12, v0.t
- - vsuxei128.v v4, (a0), v12
- - vsuxei128.v v4, 0(a0), v12
- - vsuxei128.v v4, (a0), v12, v0.t
- -
- - vlxei256.v v4, (a0), v12
- - vlxei256.v v4, 0(a0), v12
- - vlxei256.v v4, (a0), v12, v0.t
- - vsxei256.v v4, (a0), v12
- - vsxei256.v v4, 0(a0), v12
- - vsxei256.v v4, (a0), v12, v0.t
- - vsuxei256.v v4, (a0), v12
- - vsuxei256.v v4, 0(a0), v12
- - vsuxei256.v v4, (a0), v12, v0.t
- -
- - vlxei512.v v4, (a0), v12
- - vlxei512.v v4, 0(a0), v12
- - vlxei512.v v4, (a0), v12, v0.t
- - vsxei512.v v4, (a0), v12
- - vsxei512.v v4, 0(a0), v12
- - vsxei512.v v4, (a0), v12, v0.t
- - vsuxei512.v v4, (a0), v12
- - vsuxei512.v v4, 0(a0), v12
- - vsuxei512.v v4, (a0), v12, v0.t
- -
- - vlxei1024.v v4, (a0), v12
- - vlxei1024.v v4, 0(a0), v12
- - vlxei1024.v v4, (a0), v12, v0.t
- - vsxei1024.v v4, (a0), v12
- - vsxei1024.v v4, 0(a0), v12
- - vsxei1024.v v4, (a0), v12, v0.t
- - vsuxei1024.v v4, (a0), v12
- - vsuxei1024.v v4, 0(a0), v12
- - vsuxei1024.v v4, (a0), v12, v0.t
- -
- vle8ff.v v4, (a0)
- vle8ff.v v4, 0(a0)
- vle8ff.v v4, (a0), v0.t
- diff --git a/include/opcode/riscv-opc.h b/include/opcode/riscv-opc.h
- index 579bae2670..e196e27736 100644
- --- a/include/opcode/riscv-opc.h
- +++ b/include/opcode/riscv-opc.h
- @@ -607,9 +607,9 @@ NF MEW MOP VM LUMOP/RS2 RS1 WIDTH VD opcode
- 000 - 00 x 00000 xxxxx --- xxxxx 0100111 VSE<EEW>
- 000 - 10 x xxxxx xxxxx --- xxxxx 0000111 VLSE<EEW>
- 000 - 10 x xxxxx xxxxx --- xxxxx 0100111 VSSE<EEW>
- -000 - 11 x xxxxx xxxxx --- xxxxx 0000111 VLXE<EEW>I
- -000 - 11 x xxxxx xxxxx --- xxxxx 0100111 VSXE<EEW>I
- -000 - 01 x xxxxx xxxxx --- xxxxx 0100111 VSUXE<EEW>I
- +000 0 11 x xxxxx xxxxx --- xxxxx 0000111 VLXE<EEW>I
- +000 0 11 x xxxxx xxxxx --- xxxxx 0100111 VSXE<EEW>I
- +000 0 01 x xxxxx xxxxx --- xxxxx 0100111 VSUXE<EEW>I
- 000 - 00 x 10000 xxxxx --- xxxxx 0000111 VLE<EEW>FF
- xxx 0 00 1 01000 xxxxx 000 xxxxx 0000111 VL<nf>R, nf = 1,2,4,8
- xxx 0 00 1 01000 xxxxx 000 xxxxx 0100111 VS<nf>R, nf = 1,2,4,8
- @@ -699,14 +699,6 @@ xxx - 00 x 10000 xxxxx --- xxxxx 0000111 VLSEG<nf>E<EEW>FF
- #define MASK_VLXEI32V 0xfc00707f
- #define MATCH_VLXEI64V 0x0c007007
- #define MASK_VLXEI64V 0xfc00707f
- -#define MATCH_VLXEI128V 0x1c000007
- -#define MASK_VLXEI128V 0xfc00707f
- -#define MATCH_VLXEI256V 0x1c005007
- -#define MASK_VLXEI256V 0xfc00707f
- -#define MATCH_VLXEI512V 0x1c006007
- -#define MASK_VLXEI512V 0xfc00707f
- -#define MATCH_VLXEI1024V 0x1c007007
- -#define MASK_VLXEI1024V 0xfc00707f
-
- #define MATCH_VSXEI8V 0x0c000027
- #define MASK_VSXEI8V 0xfc00707f
- @@ -716,14 +708,6 @@ xxx - 00 x 10000 xxxxx --- xxxxx 0000111 VLSEG<nf>E<EEW>FF
- #define MASK_VSXEI32V 0xfc00707f
- #define MATCH_VSXEI64V 0x0c007027
- #define MASK_VSXEI64V 0xfc00707f
- -#define MATCH_VSXEI128V 0x1c000027
- -#define MASK_VSXEI128V 0xfc00707f
- -#define MATCH_VSXEI256V 0x1c005027
- -#define MASK_VSXEI256V 0xfc00707f
- -#define MATCH_VSXEI512V 0x1c006027
- -#define MASK_VSXEI512V 0xfc00707f
- -#define MATCH_VSXEI1024V 0x1c007027
- -#define MASK_VSXEI1024V 0xfc00707f
-
- #define MATCH_VSUXEI8V 0x04000027
- #define MASK_VSUXEI8V 0xfc00707f
- @@ -733,14 +717,6 @@ xxx - 00 x 10000 xxxxx --- xxxxx 0000111 VLSEG<nf>E<EEW>FF
- #define MASK_VSUXEI32V 0xfc00707f
- #define MATCH_VSUXEI64V 0x04007027
- #define MASK_VSUXEI64V 0xfc00707f
- -#define MATCH_VSUXEI128V 0x14000027
- -#define MASK_VSUXEI128V 0xfc00707f
- -#define MATCH_VSUXEI256V 0x14005027
- -#define MASK_VSUXEI256V 0xfc00707f
- -#define MATCH_VSUXEI512V 0x14006027
- -#define MASK_VSUXEI512V 0xfc00707f
- -#define MATCH_VSUXEI1024V 0x14007027
- -#define MASK_VSUXEI1024V 0xfc00707f
-
- #define MATCH_VLE8FFV 0x01000007
- #define MASK_VLE8FFV 0xfdf0707f
- diff --git a/opcodes/riscv-opc.c b/opcodes/riscv-opc.c
- index ce9b10e411..475c65d7e5 100644
- --- a/opcodes/riscv-opc.c
- +++ b/opcodes/riscv-opc.c
- @@ -1106,28 +1106,16 @@ const struct riscv_opcode riscv_opcodes[] =
- {"vlxei16.v", 0, INSN_CLASS_V, "Vd,0(s),VtVm", MATCH_VLXEI16V, MASK_VLXEI16V, match_opcode, INSN_DREF },
- {"vlxei32.v", 0, INSN_CLASS_V, "Vd,0(s),VtVm", MATCH_VLXEI32V, MASK_VLXEI32V, match_opcode, INSN_DREF },
- {"vlxei64.v", 0, INSN_CLASS_V, "Vd,0(s),VtVm", MATCH_VLXEI64V, MASK_VLXEI64V, match_opcode, INSN_DREF },
- -{"vlxei128.v", 0, INSN_CLASS_V, "Vd,0(s),VtVm", MATCH_VLXEI128V, MASK_VLXEI128V, match_opcode, INSN_DREF },
- -{"vlxei256.v", 0, INSN_CLASS_V, "Vd,0(s),VtVm", MATCH_VLXEI256V, MASK_VLXEI256V, match_opcode, INSN_DREF },
- -{"vlxei512.v", 0, INSN_CLASS_V, "Vd,0(s),VtVm", MATCH_VLXEI512V, MASK_VLXEI512V, match_opcode, INSN_DREF },
- -{"vlxei1024.v",0, INSN_CLASS_V, "Vd,0(s),VtVm", MATCH_VLXEI1024V, MASK_VLXEI1024V, match_opcode, INSN_DREF },
-
- {"vsxei8.v", 0, INSN_CLASS_V, "Vd,0(s),VtVm", MATCH_VSXEI8V, MASK_VSXEI8V, match_opcode, INSN_DREF },
- {"vsxei16.v", 0, INSN_CLASS_V, "Vd,0(s),VtVm", MATCH_VSXEI16V, MASK_VSXEI16V, match_opcode, INSN_DREF },
- {"vsxei32.v", 0, INSN_CLASS_V, "Vd,0(s),VtVm", MATCH_VSXEI32V, MASK_VSXEI32V, match_opcode, INSN_DREF },
- {"vsxei64.v", 0, INSN_CLASS_V, "Vd,0(s),VtVm", MATCH_VSXEI64V, MASK_VSXEI64V, match_opcode, INSN_DREF },
- -{"vsxei128.v", 0, INSN_CLASS_V, "Vd,0(s),VtVm", MATCH_VSXEI128V, MASK_VSXEI128V, match_opcode, INSN_DREF },
- -{"vsxei256.v", 0, INSN_CLASS_V, "Vd,0(s),VtVm", MATCH_VSXEI256V, MASK_VSXEI256V, match_opcode, INSN_DREF },
- -{"vsxei512.v", 0, INSN_CLASS_V, "Vd,0(s),VtVm", MATCH_VSXEI512V, MASK_VSXEI512V, match_opcode, INSN_DREF },
- -{"vsxei1024.v",0, INSN_CLASS_V, "Vd,0(s),VtVm", MATCH_VSXEI1024V, MASK_VSXEI1024V, match_opcode, INSN_DREF },
-
- {"vsuxei8.v", 0, INSN_CLASS_V, "Vd,0(s),VtVm", MATCH_VSUXEI8V, MASK_VSUXEI8V, match_opcode, INSN_DREF },
- {"vsuxei16.v", 0, INSN_CLASS_V, "Vd,0(s),VtVm", MATCH_VSUXEI16V, MASK_VSUXEI16V, match_opcode, INSN_DREF },
- {"vsuxei32.v", 0, INSN_CLASS_V, "Vd,0(s),VtVm", MATCH_VSUXEI32V, MASK_VSUXEI32V, match_opcode, INSN_DREF },
- {"vsuxei64.v", 0, INSN_CLASS_V, "Vd,0(s),VtVm", MATCH_VSUXEI64V, MASK_VSUXEI64V, match_opcode, INSN_DREF },
- -{"vsuxei128.v", 0, INSN_CLASS_V, "Vd,0(s),VtVm", MATCH_VSUXEI128V, MASK_VSUXEI128V, match_opcode, INSN_DREF },
- -{"vsuxei256.v", 0, INSN_CLASS_V, "Vd,0(s),VtVm", MATCH_VSUXEI256V, MASK_VSUXEI256V, match_opcode, INSN_DREF },
- -{"vsuxei512.v", 0, INSN_CLASS_V, "Vd,0(s),VtVm", MATCH_VSUXEI512V, MASK_VSUXEI512V, match_opcode, INSN_DREF },
- -{"vsuxei1024.v",0, INSN_CLASS_V, "Vd,0(s),VtVm", MATCH_VSUXEI1024V, MASK_VSUXEI1024V, match_opcode, INSN_DREF },
-
- {"vle8ff.v", 0, INSN_CLASS_V, "Vd,0(s)Vm", MATCH_VLE8FFV, MASK_VLE8FFV, match_opcode, INSN_DREF },
- {"vle16ff.v", 0, INSN_CLASS_V, "Vd,0(s)Vm", MATCH_VLE16FFV, MASK_VLE16FFV, match_opcode, INSN_DREF },
- --
- 2.33.0
|