0014-Remove-Vector-indexed-instruction-when-EEW-128.patch 10 KB

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  1. From f9e8a9be0538c55b9bbe7a85b0cbce1a0d5cd574 Mon Sep 17 00:00:00 2001
  2. From: Nelson Chu <nelson.chu@sifive.com>
  3. Date: Mon, 6 Jul 2020 13:27:29 +0800
  4. Subject: [PATCH 14/48] Remove Vector indexed instruction when EEW >= 128.
  5. These instruction are removed in the risc-v vector spec,
  6. commit 0fec0e257cca5e389a0e1774e7d5aaac729b4ad2,
  7. Added clarifications on loads/stores.
  8. ---
  9. gas/testsuite/gas/riscv/vector-insns.d | 36 -----------------------
  10. gas/testsuite/gas/riscv/vector-insns.s | 40 --------------------------
  11. include/opcode/riscv-opc.h | 30 ++-----------------
  12. opcodes/riscv-opc.c | 12 --------
  13. 4 files changed, 3 insertions(+), 115 deletions(-)
  14. diff --git a/gas/testsuite/gas/riscv/vector-insns.d b/gas/testsuite/gas/riscv/vector-insns.d
  15. index 70366fb787..634ff2945c 100644
  16. --- a/gas/testsuite/gas/riscv/vector-insns.d
  17. +++ b/gas/testsuite/gas/riscv/vector-insns.d
  18. @@ -158,42 +158,6 @@ Disassembly of section .text:
  19. [ ]+[0-9a-f]+:[ ]+06c57227[ ]+vsuxei64.v[ ]+v4,\(a0\),v12
  20. [ ]+[0-9a-f]+:[ ]+06c57227[ ]+vsuxei64.v[ ]+v4,\(a0\),v12
  21. [ ]+[0-9a-f]+:[ ]+04c57227[ ]+vsuxei64.v[ ]+v4,\(a0\),v12,v0.t
  22. -[ ]+[0-9a-f]+:[ ]+1ec50207[ ]+vlxei128.v[ ]+v4,\(a0\),v12
  23. -[ ]+[0-9a-f]+:[ ]+1ec50207[ ]+vlxei128.v[ ]+v4,\(a0\),v12
  24. -[ ]+[0-9a-f]+:[ ]+1cc50207[ ]+vlxei128.v[ ]+v4,\(a0\),v12,v0.t
  25. -[ ]+[0-9a-f]+:[ ]+1ec50227[ ]+vsxei128.v[ ]+v4,\(a0\),v12
  26. -[ ]+[0-9a-f]+:[ ]+1ec50227[ ]+vsxei128.v[ ]+v4,\(a0\),v12
  27. -[ ]+[0-9a-f]+:[ ]+1cc50227[ ]+vsxei128.v[ ]+v4,\(a0\),v12,v0.t
  28. -[ ]+[0-9a-f]+:[ ]+16c50227[ ]+vsuxei128.v[ ]+v4,\(a0\),v12
  29. -[ ]+[0-9a-f]+:[ ]+16c50227[ ]+vsuxei128.v[ ]+v4,\(a0\),v12
  30. -[ ]+[0-9a-f]+:[ ]+14c50227[ ]+vsuxei128.v[ ]+v4,\(a0\),v12,v0.t
  31. -[ ]+[0-9a-f]+:[ ]+1ec55207[ ]+vlxei256.v[ ]+v4,\(a0\),v12
  32. -[ ]+[0-9a-f]+:[ ]+1ec55207[ ]+vlxei256.v[ ]+v4,\(a0\),v12
  33. -[ ]+[0-9a-f]+:[ ]+1cc55207[ ]+vlxei256.v[ ]+v4,\(a0\),v12,v0.t
  34. -[ ]+[0-9a-f]+:[ ]+1ec55227[ ]+vsxei256.v[ ]+v4,\(a0\),v12
  35. -[ ]+[0-9a-f]+:[ ]+1ec55227[ ]+vsxei256.v[ ]+v4,\(a0\),v12
  36. -[ ]+[0-9a-f]+:[ ]+1cc55227[ ]+vsxei256.v[ ]+v4,\(a0\),v12,v0.t
  37. -[ ]+[0-9a-f]+:[ ]+16c55227[ ]+vsuxei256.v[ ]+v4,\(a0\),v12
  38. -[ ]+[0-9a-f]+:[ ]+16c55227[ ]+vsuxei256.v[ ]+v4,\(a0\),v12
  39. -[ ]+[0-9a-f]+:[ ]+14c55227[ ]+vsuxei256.v[ ]+v4,\(a0\),v12,v0.t
  40. -[ ]+[0-9a-f]+:[ ]+1ec56207[ ]+vlxei512.v[ ]+v4,\(a0\),v12
  41. -[ ]+[0-9a-f]+:[ ]+1ec56207[ ]+vlxei512.v[ ]+v4,\(a0\),v12
  42. -[ ]+[0-9a-f]+:[ ]+1cc56207[ ]+vlxei512.v[ ]+v4,\(a0\),v12,v0.t
  43. -[ ]+[0-9a-f]+:[ ]+1ec56227[ ]+vsxei512.v[ ]+v4,\(a0\),v12
  44. -[ ]+[0-9a-f]+:[ ]+1ec56227[ ]+vsxei512.v[ ]+v4,\(a0\),v12
  45. -[ ]+[0-9a-f]+:[ ]+1cc56227[ ]+vsxei512.v[ ]+v4,\(a0\),v12,v0.t
  46. -[ ]+[0-9a-f]+:[ ]+16c56227[ ]+vsuxei512.v[ ]+v4,\(a0\),v12
  47. -[ ]+[0-9a-f]+:[ ]+16c56227[ ]+vsuxei512.v[ ]+v4,\(a0\),v12
  48. -[ ]+[0-9a-f]+:[ ]+14c56227[ ]+vsuxei512.v[ ]+v4,\(a0\),v12,v0.t
  49. -[ ]+[0-9a-f]+:[ ]+1ec57207[ ]+vlxei1024.v[ ]+v4,\(a0\),v12
  50. -[ ]+[0-9a-f]+:[ ]+1ec57207[ ]+vlxei1024.v[ ]+v4,\(a0\),v12
  51. -[ ]+[0-9a-f]+:[ ]+1cc57207[ ]+vlxei1024.v[ ]+v4,\(a0\),v12,v0.t
  52. -[ ]+[0-9a-f]+:[ ]+1ec57227[ ]+vsxei1024.v[ ]+v4,\(a0\),v12
  53. -[ ]+[0-9a-f]+:[ ]+1ec57227[ ]+vsxei1024.v[ ]+v4,\(a0\),v12
  54. -[ ]+[0-9a-f]+:[ ]+1cc57227[ ]+vsxei1024.v[ ]+v4,\(a0\),v12,v0.t
  55. -[ ]+[0-9a-f]+:[ ]+16c57227[ ]+vsuxei1024.v[ ]+v4,\(a0\),v12
  56. -[ ]+[0-9a-f]+:[ ]+16c57227[ ]+vsuxei1024.v[ ]+v4,\(a0\),v12
  57. -[ ]+[0-9a-f]+:[ ]+14c57227[ ]+vsuxei1024.v[ ]+v4,\(a0\),v12,v0.t
  58. [ ]+[0-9a-f]+:[ ]+03050207[ ]+vle8ff.v[ ]+v4,\(a0\)
  59. [ ]+[0-9a-f]+:[ ]+03050207[ ]+vle8ff.v[ ]+v4,\(a0\)
  60. [ ]+[0-9a-f]+:[ ]+01050207[ ]+vle8ff.v[ ]+v4,\(a0\),v0.t
  61. diff --git a/gas/testsuite/gas/riscv/vector-insns.s b/gas/testsuite/gas/riscv/vector-insns.s
  62. index edd94d7d29..e6cfcad9ba 100644
  63. --- a/gas/testsuite/gas/riscv/vector-insns.s
  64. +++ b/gas/testsuite/gas/riscv/vector-insns.s
  65. @@ -170,46 +170,6 @@
  66. vsuxei64.v v4, 0(a0), v12
  67. vsuxei64.v v4, (a0), v12, v0.t
  68. - vlxei128.v v4, (a0), v12
  69. - vlxei128.v v4, 0(a0), v12
  70. - vlxei128.v v4, (a0), v12, v0.t
  71. - vsxei128.v v4, (a0), v12
  72. - vsxei128.v v4, 0(a0), v12
  73. - vsxei128.v v4, (a0), v12, v0.t
  74. - vsuxei128.v v4, (a0), v12
  75. - vsuxei128.v v4, 0(a0), v12
  76. - vsuxei128.v v4, (a0), v12, v0.t
  77. -
  78. - vlxei256.v v4, (a0), v12
  79. - vlxei256.v v4, 0(a0), v12
  80. - vlxei256.v v4, (a0), v12, v0.t
  81. - vsxei256.v v4, (a0), v12
  82. - vsxei256.v v4, 0(a0), v12
  83. - vsxei256.v v4, (a0), v12, v0.t
  84. - vsuxei256.v v4, (a0), v12
  85. - vsuxei256.v v4, 0(a0), v12
  86. - vsuxei256.v v4, (a0), v12, v0.t
  87. -
  88. - vlxei512.v v4, (a0), v12
  89. - vlxei512.v v4, 0(a0), v12
  90. - vlxei512.v v4, (a0), v12, v0.t
  91. - vsxei512.v v4, (a0), v12
  92. - vsxei512.v v4, 0(a0), v12
  93. - vsxei512.v v4, (a0), v12, v0.t
  94. - vsuxei512.v v4, (a0), v12
  95. - vsuxei512.v v4, 0(a0), v12
  96. - vsuxei512.v v4, (a0), v12, v0.t
  97. -
  98. - vlxei1024.v v4, (a0), v12
  99. - vlxei1024.v v4, 0(a0), v12
  100. - vlxei1024.v v4, (a0), v12, v0.t
  101. - vsxei1024.v v4, (a0), v12
  102. - vsxei1024.v v4, 0(a0), v12
  103. - vsxei1024.v v4, (a0), v12, v0.t
  104. - vsuxei1024.v v4, (a0), v12
  105. - vsuxei1024.v v4, 0(a0), v12
  106. - vsuxei1024.v v4, (a0), v12, v0.t
  107. -
  108. vle8ff.v v4, (a0)
  109. vle8ff.v v4, 0(a0)
  110. vle8ff.v v4, (a0), v0.t
  111. diff --git a/include/opcode/riscv-opc.h b/include/opcode/riscv-opc.h
  112. index 579bae2670..e196e27736 100644
  113. --- a/include/opcode/riscv-opc.h
  114. +++ b/include/opcode/riscv-opc.h
  115. @@ -607,9 +607,9 @@ NF MEW MOP VM LUMOP/RS2 RS1 WIDTH VD opcode
  116. 000 - 00 x 00000 xxxxx --- xxxxx 0100111 VSE<EEW>
  117. 000 - 10 x xxxxx xxxxx --- xxxxx 0000111 VLSE<EEW>
  118. 000 - 10 x xxxxx xxxxx --- xxxxx 0100111 VSSE<EEW>
  119. -000 - 11 x xxxxx xxxxx --- xxxxx 0000111 VLXE<EEW>I
  120. -000 - 11 x xxxxx xxxxx --- xxxxx 0100111 VSXE<EEW>I
  121. -000 - 01 x xxxxx xxxxx --- xxxxx 0100111 VSUXE<EEW>I
  122. +000 0 11 x xxxxx xxxxx --- xxxxx 0000111 VLXE<EEW>I
  123. +000 0 11 x xxxxx xxxxx --- xxxxx 0100111 VSXE<EEW>I
  124. +000 0 01 x xxxxx xxxxx --- xxxxx 0100111 VSUXE<EEW>I
  125. 000 - 00 x 10000 xxxxx --- xxxxx 0000111 VLE<EEW>FF
  126. xxx 0 00 1 01000 xxxxx 000 xxxxx 0000111 VL<nf>R, nf = 1,2,4,8
  127. xxx 0 00 1 01000 xxxxx 000 xxxxx 0100111 VS<nf>R, nf = 1,2,4,8
  128. @@ -699,14 +699,6 @@ xxx - 00 x 10000 xxxxx --- xxxxx 0000111 VLSEG<nf>E<EEW>FF
  129. #define MASK_VLXEI32V 0xfc00707f
  130. #define MATCH_VLXEI64V 0x0c007007
  131. #define MASK_VLXEI64V 0xfc00707f
  132. -#define MATCH_VLXEI128V 0x1c000007
  133. -#define MASK_VLXEI128V 0xfc00707f
  134. -#define MATCH_VLXEI256V 0x1c005007
  135. -#define MASK_VLXEI256V 0xfc00707f
  136. -#define MATCH_VLXEI512V 0x1c006007
  137. -#define MASK_VLXEI512V 0xfc00707f
  138. -#define MATCH_VLXEI1024V 0x1c007007
  139. -#define MASK_VLXEI1024V 0xfc00707f
  140. #define MATCH_VSXEI8V 0x0c000027
  141. #define MASK_VSXEI8V 0xfc00707f
  142. @@ -716,14 +708,6 @@ xxx - 00 x 10000 xxxxx --- xxxxx 0000111 VLSEG<nf>E<EEW>FF
  143. #define MASK_VSXEI32V 0xfc00707f
  144. #define MATCH_VSXEI64V 0x0c007027
  145. #define MASK_VSXEI64V 0xfc00707f
  146. -#define MATCH_VSXEI128V 0x1c000027
  147. -#define MASK_VSXEI128V 0xfc00707f
  148. -#define MATCH_VSXEI256V 0x1c005027
  149. -#define MASK_VSXEI256V 0xfc00707f
  150. -#define MATCH_VSXEI512V 0x1c006027
  151. -#define MASK_VSXEI512V 0xfc00707f
  152. -#define MATCH_VSXEI1024V 0x1c007027
  153. -#define MASK_VSXEI1024V 0xfc00707f
  154. #define MATCH_VSUXEI8V 0x04000027
  155. #define MASK_VSUXEI8V 0xfc00707f
  156. @@ -733,14 +717,6 @@ xxx - 00 x 10000 xxxxx --- xxxxx 0000111 VLSEG<nf>E<EEW>FF
  157. #define MASK_VSUXEI32V 0xfc00707f
  158. #define MATCH_VSUXEI64V 0x04007027
  159. #define MASK_VSUXEI64V 0xfc00707f
  160. -#define MATCH_VSUXEI128V 0x14000027
  161. -#define MASK_VSUXEI128V 0xfc00707f
  162. -#define MATCH_VSUXEI256V 0x14005027
  163. -#define MASK_VSUXEI256V 0xfc00707f
  164. -#define MATCH_VSUXEI512V 0x14006027
  165. -#define MASK_VSUXEI512V 0xfc00707f
  166. -#define MATCH_VSUXEI1024V 0x14007027
  167. -#define MASK_VSUXEI1024V 0xfc00707f
  168. #define MATCH_VLE8FFV 0x01000007
  169. #define MASK_VLE8FFV 0xfdf0707f
  170. diff --git a/opcodes/riscv-opc.c b/opcodes/riscv-opc.c
  171. index ce9b10e411..475c65d7e5 100644
  172. --- a/opcodes/riscv-opc.c
  173. +++ b/opcodes/riscv-opc.c
  174. @@ -1106,28 +1106,16 @@ const struct riscv_opcode riscv_opcodes[] =
  175. {"vlxei16.v", 0, INSN_CLASS_V, "Vd,0(s),VtVm", MATCH_VLXEI16V, MASK_VLXEI16V, match_opcode, INSN_DREF },
  176. {"vlxei32.v", 0, INSN_CLASS_V, "Vd,0(s),VtVm", MATCH_VLXEI32V, MASK_VLXEI32V, match_opcode, INSN_DREF },
  177. {"vlxei64.v", 0, INSN_CLASS_V, "Vd,0(s),VtVm", MATCH_VLXEI64V, MASK_VLXEI64V, match_opcode, INSN_DREF },
  178. -{"vlxei128.v", 0, INSN_CLASS_V, "Vd,0(s),VtVm", MATCH_VLXEI128V, MASK_VLXEI128V, match_opcode, INSN_DREF },
  179. -{"vlxei256.v", 0, INSN_CLASS_V, "Vd,0(s),VtVm", MATCH_VLXEI256V, MASK_VLXEI256V, match_opcode, INSN_DREF },
  180. -{"vlxei512.v", 0, INSN_CLASS_V, "Vd,0(s),VtVm", MATCH_VLXEI512V, MASK_VLXEI512V, match_opcode, INSN_DREF },
  181. -{"vlxei1024.v",0, INSN_CLASS_V, "Vd,0(s),VtVm", MATCH_VLXEI1024V, MASK_VLXEI1024V, match_opcode, INSN_DREF },
  182. {"vsxei8.v", 0, INSN_CLASS_V, "Vd,0(s),VtVm", MATCH_VSXEI8V, MASK_VSXEI8V, match_opcode, INSN_DREF },
  183. {"vsxei16.v", 0, INSN_CLASS_V, "Vd,0(s),VtVm", MATCH_VSXEI16V, MASK_VSXEI16V, match_opcode, INSN_DREF },
  184. {"vsxei32.v", 0, INSN_CLASS_V, "Vd,0(s),VtVm", MATCH_VSXEI32V, MASK_VSXEI32V, match_opcode, INSN_DREF },
  185. {"vsxei64.v", 0, INSN_CLASS_V, "Vd,0(s),VtVm", MATCH_VSXEI64V, MASK_VSXEI64V, match_opcode, INSN_DREF },
  186. -{"vsxei128.v", 0, INSN_CLASS_V, "Vd,0(s),VtVm", MATCH_VSXEI128V, MASK_VSXEI128V, match_opcode, INSN_DREF },
  187. -{"vsxei256.v", 0, INSN_CLASS_V, "Vd,0(s),VtVm", MATCH_VSXEI256V, MASK_VSXEI256V, match_opcode, INSN_DREF },
  188. -{"vsxei512.v", 0, INSN_CLASS_V, "Vd,0(s),VtVm", MATCH_VSXEI512V, MASK_VSXEI512V, match_opcode, INSN_DREF },
  189. -{"vsxei1024.v",0, INSN_CLASS_V, "Vd,0(s),VtVm", MATCH_VSXEI1024V, MASK_VSXEI1024V, match_opcode, INSN_DREF },
  190. {"vsuxei8.v", 0, INSN_CLASS_V, "Vd,0(s),VtVm", MATCH_VSUXEI8V, MASK_VSUXEI8V, match_opcode, INSN_DREF },
  191. {"vsuxei16.v", 0, INSN_CLASS_V, "Vd,0(s),VtVm", MATCH_VSUXEI16V, MASK_VSUXEI16V, match_opcode, INSN_DREF },
  192. {"vsuxei32.v", 0, INSN_CLASS_V, "Vd,0(s),VtVm", MATCH_VSUXEI32V, MASK_VSUXEI32V, match_opcode, INSN_DREF },
  193. {"vsuxei64.v", 0, INSN_CLASS_V, "Vd,0(s),VtVm", MATCH_VSUXEI64V, MASK_VSUXEI64V, match_opcode, INSN_DREF },
  194. -{"vsuxei128.v", 0, INSN_CLASS_V, "Vd,0(s),VtVm", MATCH_VSUXEI128V, MASK_VSUXEI128V, match_opcode, INSN_DREF },
  195. -{"vsuxei256.v", 0, INSN_CLASS_V, "Vd,0(s),VtVm", MATCH_VSUXEI256V, MASK_VSUXEI256V, match_opcode, INSN_DREF },
  196. -{"vsuxei512.v", 0, INSN_CLASS_V, "Vd,0(s),VtVm", MATCH_VSUXEI512V, MASK_VSUXEI512V, match_opcode, INSN_DREF },
  197. -{"vsuxei1024.v",0, INSN_CLASS_V, "Vd,0(s),VtVm", MATCH_VSUXEI1024V, MASK_VSUXEI1024V, match_opcode, INSN_DREF },
  198. {"vle8ff.v", 0, INSN_CLASS_V, "Vd,0(s)Vm", MATCH_VLE8FFV, MASK_VLE8FFV, match_opcode, INSN_DREF },
  199. {"vle16ff.v", 0, INSN_CLASS_V, "Vd,0(s)Vm", MATCH_VLE16FFV, MASK_VLE16FFV, match_opcode, INSN_DREF },
  200. --
  201. 2.33.0