0040-RISC-V-Add-missing-zext.-hw-pseudo-instructions.patch 4.8 KB

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  1. From 6d82557fb262e1b17d523ee34a76f8216918ff26 Mon Sep 17 00:00:00 2001
  2. From: Nelson Chu <nelson.chu@sifive.com>
  3. Date: Thu, 3 Dec 2020 17:47:35 +0800
  4. Subject: [PATCH 40/48] RISC-V: Add missing zext.[hw] pseudo instructions.
  5. I only add the zext pseudo which will be converted to the physical
  6. b-ext instrcution. As for the zext.b, it should be controlled by i-ext,
  7. and be added to FSF binutils directly, not here.
  8. ---
  9. gas/testsuite/gas/riscv/zext-32.d | 11 +++++++++++
  10. gas/testsuite/gas/riscv/zext-64.d | 12 ++++++++++++
  11. gas/testsuite/gas/riscv/zext-noalias-32.d | 11 +++++++++++
  12. gas/testsuite/gas/riscv/zext-noalias-64.d | 12 ++++++++++++
  13. gas/testsuite/gas/riscv/zext.s | 6 ++++++
  14. opcodes/riscv-opc.c | 3 +++
  15. 6 files changed, 55 insertions(+)
  16. create mode 100644 gas/testsuite/gas/riscv/zext-32.d
  17. create mode 100644 gas/testsuite/gas/riscv/zext-64.d
  18. create mode 100644 gas/testsuite/gas/riscv/zext-noalias-32.d
  19. create mode 100644 gas/testsuite/gas/riscv/zext-noalias-64.d
  20. create mode 100644 gas/testsuite/gas/riscv/zext.s
  21. diff --git a/gas/testsuite/gas/riscv/zext-32.d b/gas/testsuite/gas/riscv/zext-32.d
  22. new file mode 100644
  23. index 0000000000..9111177941
  24. --- /dev/null
  25. +++ b/gas/testsuite/gas/riscv/zext-32.d
  26. @@ -0,0 +1,11 @@
  27. +#as: -march=rv32ib
  28. +#source: zext.s
  29. +#objdump: -d
  30. +
  31. +.*:[ ]+file format .*
  32. +
  33. +
  34. +Disassembly of section .text:
  35. +
  36. +0+000 <target>:
  37. +[ ]+0:[ ]+0805c533[ ]+zext.h[ ]+a0,a1
  38. diff --git a/gas/testsuite/gas/riscv/zext-64.d b/gas/testsuite/gas/riscv/zext-64.d
  39. new file mode 100644
  40. index 0000000000..3b0955a00f
  41. --- /dev/null
  42. +++ b/gas/testsuite/gas/riscv/zext-64.d
  43. @@ -0,0 +1,12 @@
  44. +#as: -march=rv64ib -defsym __64_bit__=1
  45. +#source: zext.s
  46. +#objdump: -d
  47. +
  48. +.*:[ ]+file format .*
  49. +
  50. +
  51. +Disassembly of section .text:
  52. +
  53. +0+000 <target>:
  54. +[ ]+0:[ ]+0805c53b[ ]+zext.h[ ]+a0,a1
  55. +[ ]+4:[ ]+0805853b[ ]+zext.w[ ]+a0,a1
  56. diff --git a/gas/testsuite/gas/riscv/zext-noalias-32.d b/gas/testsuite/gas/riscv/zext-noalias-32.d
  57. new file mode 100644
  58. index 0000000000..bdecbc2fc2
  59. --- /dev/null
  60. +++ b/gas/testsuite/gas/riscv/zext-noalias-32.d
  61. @@ -0,0 +1,11 @@
  62. +#as: -march=rv32ib
  63. +#source: zext.s
  64. +#objdump: -d -Mno-aliases
  65. +
  66. +.*:[ ]+file format .*
  67. +
  68. +
  69. +Disassembly of section .text:
  70. +
  71. +0+000 <target>:
  72. +[ ]+0:[ ]+0805c533[ ]+pack[ ]+a0,a1,zero
  73. diff --git a/gas/testsuite/gas/riscv/zext-noalias-64.d b/gas/testsuite/gas/riscv/zext-noalias-64.d
  74. new file mode 100644
  75. index 0000000000..8dfd77bf43
  76. --- /dev/null
  77. +++ b/gas/testsuite/gas/riscv/zext-noalias-64.d
  78. @@ -0,0 +1,12 @@
  79. +#as: -march=rv64ib -defsym __64_bit__=1
  80. +#source: zext.s
  81. +#objdump: -d -Mno-aliases
  82. +
  83. +.*:[ ]+file format .*
  84. +
  85. +
  86. +Disassembly of section .text:
  87. +
  88. +0+000 <target>:
  89. +[ ]+0:[ ]+0805c53b[ ]+packw[ ]+a0,a1,zero
  90. +[ ]+4:[ ]+0805853b[ ]+addu.w[ ]+a0,a1,zero
  91. diff --git a/gas/testsuite/gas/riscv/zext.s b/gas/testsuite/gas/riscv/zext.s
  92. new file mode 100644
  93. index 0000000000..e2e127d949
  94. --- /dev/null
  95. +++ b/gas/testsuite/gas/riscv/zext.s
  96. @@ -0,0 +1,6 @@
  97. +target:
  98. + zext.h a0, a1
  99. +
  100. +.ifdef __64_bit__
  101. + zext.w a0, a1
  102. +.endif
  103. diff --git a/opcodes/riscv-opc.c b/opcodes/riscv-opc.c
  104. index f55e1281ed..dbabc5c2f6 100644
  105. --- a/opcodes/riscv-opc.c
  106. +++ b/opcodes/riscv-opc.c
  107. @@ -1061,6 +1061,8 @@ const struct riscv_opcode riscv_opcodes[] =
  108. {"xperm.h", 0, INSN_CLASS_B_OR_ZBP, "d,s,t", MATCH_XPERMH, MASK_XPERMH, match_opcode, 0 },
  109. {"bdep", 0, INSN_CLASS_B_OR_ZBE, "d,s,t", MATCH_BDEP, MASK_BDEP, match_opcode, 0 },
  110. {"bext", 0, INSN_CLASS_B_OR_ZBE, "d,s,t", MATCH_BEXT, MASK_BEXT, match_opcode, 0 },
  111. +{"zext.h", 32, INSN_CLASS_B_OR_ZBB_OR_ZBP, "d,s", MATCH_PACK, MASK_PACK | MASK_RS2, match_opcode, INSN_ALIAS },
  112. +{"zext.h", 64, INSN_CLASS_B_OR_ZBB_OR_ZBP, "d,s", MATCH_PACKW, MASK_PACKW | MASK_RS2, match_opcode, INSN_ALIAS },
  113. {"pack", 0, INSN_CLASS_B_OR_ZBB_OR_ZBP, "d,s,t", MATCH_PACK, MASK_PACK, match_opcode, 0 },
  114. {"packu", 0, INSN_CLASS_B_OR_ZBB_OR_ZBP, "d,s,t", MATCH_PACKU, MASK_PACKU, match_opcode, 0 },
  115. {"packh", 0, INSN_CLASS_B_OR_ZBB_OR_ZBP, "d,s,t", MATCH_PACKH, MASK_PACKH, match_opcode, 0 },
  116. @@ -1068,6 +1070,7 @@ const struct riscv_opcode riscv_opcodes[] =
  117. {"bmatxor", 64, INSN_CLASS_B_OR_ZBM, "d,s,t", MATCH_BMATXOR, MASK_BMATXOR, match_opcode, 0 },
  118. {"bfp", 0, INSN_CLASS_B_OR_ZBF, "d,s,t", MATCH_BFP, MASK_BFP, match_opcode, 0 },
  119. {"slliu.w", 64, INSN_CLASS_B_OR_ZBB, "d,s,>", MATCH_SLLIU_W, MASK_SLLIU_W, match_opcode, 0 },
  120. +{"zext.w", 64, INSN_CLASS_B_OR_ZBB_OR_ZBP, "d,s", MATCH_ADDU_W, MASK_ADDU_W | MASK_RS2, match_opcode, INSN_ALIAS },
  121. {"addu.w", 64, INSN_CLASS_B_OR_ZBB, "d,s,t", MATCH_ADDU_W, MASK_ADDU_W, match_opcode, 0 },
  122. {"subu.w", 64, INSN_CLASS_B_OR_ZBB, "d,s,t", MATCH_SUBU_W, MASK_SUBU_W, match_opcode, 0 },
  123. {"sloiw", 64, INSN_CLASS_B_OR_ZBP, "d,s,<", MATCH_SLOIW, MASK_SLOIW, match_opcode, 0 },
  124. --
  125. 2.33.0