0031-RISC-V-Add-assembly-pseudoinstructions-vneg.v-and-vf.patch 7.4 KB

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  1. From 786771070f564a133c536e05939eb51b546dc02d Mon Sep 17 00:00:00 2001
  2. From: Nelson Chu <nelson.chu@sifive.com>
  3. Date: Mon, 23 Nov 2020 11:34:34 +0800
  4. Subject: [PATCH 31/48] RISC-V: Add assembly pseudoinstructions, vneg.v and
  5. vfneg.v.
  6. vneg.v vd,vs = vrsub.vx vd,vs,x0
  7. vfneg.v vd,vs = vfsgnjn.vv vd,vs,vs
  8. ---
  9. .../riscv/vector-insns-fail-arith-floatp.l | 1 +
  10. .../riscv/vector-insns-fail-arith-floatp.s | 3 +++
  11. .../gas/riscv/vector-insns-fail-arith-int.l | 1 +
  12. .../gas/riscv/vector-insns-fail-arith-int.s | 3 +++
  13. gas/testsuite/gas/riscv/vector-insns.d | 4 +++
  14. gas/testsuite/gas/riscv/vector-insns.s | 6 +++++
  15. opcodes/riscv-opc.c | 25 +++++++++++++++++++
  16. 7 files changed, 43 insertions(+)
  17. diff --git a/gas/testsuite/gas/riscv/vector-insns-fail-arith-floatp.l b/gas/testsuite/gas/riscv/vector-insns-fail-arith-floatp.l
  18. index c55c7d24cd..bcc49a0908 100644
  19. --- a/gas/testsuite/gas/riscv/vector-insns-fail-arith-floatp.l
  20. +++ b/gas/testsuite/gas/riscv/vector-insns-fail-arith-floatp.l
  21. @@ -33,6 +33,7 @@
  22. .*Error: illegal operands vd cannot overlap vm `vfmin.vf v0,v4,fa1,v0.t'
  23. .*Error: illegal operands vd cannot overlap vm `vfmax.vv v0,v4,v8,v0.t'
  24. .*Error: illegal operands vd cannot overlap vm `vfmax.vf v0,v4,fa1,v0.t'
  25. +.*Error: illegal operands vd cannot overlap vm `vfneg.v v0,v4,v0.t'
  26. .*Error: illegal operands vd cannot overlap vm `vfsgnj.vv v0,v4,v8,v0.t'
  27. .*Error: illegal operands vd cannot overlap vm `vfsgnj.vf v0,v4,fa1,v0.t'
  28. .*Error: illegal operands vd cannot overlap vm `vfsgnjn.vv v0,v4,v8,v0.t'
  29. diff --git a/gas/testsuite/gas/riscv/vector-insns-fail-arith-floatp.s b/gas/testsuite/gas/riscv/vector-insns-fail-arith-floatp.s
  30. index 3231c35ada..a48b1a3fd3 100644
  31. --- a/gas/testsuite/gas/riscv/vector-insns-fail-arith-floatp.s
  32. +++ b/gas/testsuite/gas/riscv/vector-insns-fail-arith-floatp.s
  33. @@ -118,6 +118,9 @@
  34. # Vector Floating-Point Sign-Injection Instructions
  35. + vfneg.v v4, v4 # OK
  36. + vfneg.v v0, v4, v0.t # vd overlap vm
  37. +
  38. vfsgnj.vv v4, v4, v8 # OK
  39. vfsgnj.vv v8, v4, v8 # OK
  40. vfsgnj.vv v0, v4, v8, v0.t # vd overlap vm
  41. diff --git a/gas/testsuite/gas/riscv/vector-insns-fail-arith-int.l b/gas/testsuite/gas/riscv/vector-insns-fail-arith-int.l
  42. index 3b1d780fa4..5c9016dd4c 100644
  43. --- a/gas/testsuite/gas/riscv/vector-insns-fail-arith-int.l
  44. +++ b/gas/testsuite/gas/riscv/vector-insns-fail-arith-int.l
  45. @@ -1,4 +1,5 @@
  46. .*: Assembler messages:
  47. +.*Error: illegal operands vd cannot overlap vm `vneg.v v0,v4,v0.t'
  48. .*Error: illegal operands vd cannot overlap vm `vadd.vv v0,v4,v8,v0.t'
  49. .*Error: illegal operands vd cannot overlap vm `vadd.vx v0,v4,a1,v0.t'
  50. .*Error: illegal operands vd cannot overlap vm `vadd.vi v0,v4,15,v0.t'
  51. diff --git a/gas/testsuite/gas/riscv/vector-insns-fail-arith-int.s b/gas/testsuite/gas/riscv/vector-insns-fail-arith-int.s
  52. index e014125c29..6ce4e420c7 100644
  53. --- a/gas/testsuite/gas/riscv/vector-insns-fail-arith-int.s
  54. +++ b/gas/testsuite/gas/riscv/vector-insns-fail-arith-int.s
  55. @@ -1,5 +1,8 @@
  56. # Vector Single-Width Integer Add and Subtract
  57. + vneg.v v4, v4 # OK
  58. + vneg.v v0, v4, v0.t # vd overlap vm
  59. +
  60. vadd.vv v4, v4, v8 # OK
  61. vadd.vv v8, v4, v8 # OK
  62. vadd.vv v0, v4, v8, v0.t # vd overlap vm
  63. diff --git a/gas/testsuite/gas/riscv/vector-insns.d b/gas/testsuite/gas/riscv/vector-insns.d
  64. index 24a559cee5..29a38b3716 100644
  65. --- a/gas/testsuite/gas/riscv/vector-insns.d
  66. +++ b/gas/testsuite/gas/riscv/vector-insns.d
  67. @@ -1726,6 +1726,8 @@ Disassembly of section .text:
  68. [ ]+[0-9a-f]+:[ ]+e285f22f[ ]+vamomaxuei64.v[ ]+zero,\(a1\),v8,v4
  69. [ ]+[0-9a-f]+:[ ]+e485f22f[ ]+vamomaxuei64.v[ ]+v4,\(a1\),v8,v4,v0.t
  70. [ ]+[0-9a-f]+:[ ]+e085f22f[ ]+vamomaxuei64.v[ ]+zero,\(a1\),v8,v4,v0.t
  71. +[ ]+[0-9a-f]+:[ ]+0e804257[ ]+vneg.v[ ]+v4,v8
  72. +[ ]+[0-9a-f]+:[ ]+0c804257[ ]+vneg.v[ ]+v4,v8,v0.t
  73. [ ]+[0-9a-f]+:[ ]+02860257[ ]+vadd.vv[ ]+v4,v8,v12
  74. [ ]+[0-9a-f]+:[ ]+0285c257[ ]+vadd.vx[ ]+v4,v8,a1
  75. [ ]+[0-9a-f]+:[ ]+0287b257[ ]+vadd.vi[ ]+v4,v8,15
  76. @@ -2246,6 +2248,8 @@ Disassembly of section .text:
  77. [ ]+[0-9a-f]+:[ ]+10865257[ ]+vfmin.vf[ ]+v4,v8,fa2,v0.t
  78. [ ]+[0-9a-f]+:[ ]+18861257[ ]+vfmax.vv[ ]+v4,v8,v12,v0.t
  79. [ ]+[0-9a-f]+:[ ]+18865257[ ]+vfmax.vf[ ]+v4,v8,fa2,v0.t
  80. +[ ]+[0-9a-f]+:[ ]+26841257[ ]+vfneg.v[ ]+v4,v8
  81. +[ ]+[0-9a-f]+:[ ]+24841257[ ]+vfneg.v[ ]+v4,v8,v0.t
  82. [ ]+[0-9a-f]+:[ ]+22861257[ ]+vfsgnj.vv[ ]+v4,v8,v12
  83. [ ]+[0-9a-f]+:[ ]+22865257[ ]+vfsgnj.vf[ ]+v4,v8,fa2
  84. [ ]+[0-9a-f]+:[ ]+26861257[ ]+vfsgnjn.vv[ ]+v4,v8,v12
  85. diff --git a/gas/testsuite/gas/riscv/vector-insns.s b/gas/testsuite/gas/riscv/vector-insns.s
  86. index afec58c03b..b78604025a 100644
  87. --- a/gas/testsuite/gas/riscv/vector-insns.s
  88. +++ b/gas/testsuite/gas/riscv/vector-insns.s
  89. @@ -1999,6 +1999,9 @@
  90. vamomaxuei64.v v4, 0(a1), v8, v4, v0.t
  91. vamomaxuei64.v x0, 0(a1), v8, v4, v0.t
  92. + vneg.v v4, v8
  93. + vneg.v v4, v8, v0.t
  94. +
  95. vadd.vv v4, v8, v12
  96. vadd.vx v4, v8, a1
  97. vadd.vi v4, v8, 15
  98. @@ -2557,6 +2560,9 @@
  99. vfmax.vv v4, v8, v12, v0.t
  100. vfmax.vf v4, v8, fa2, v0.t
  101. + vfneg.v v4, v8
  102. + vfneg.v v4, v8, v0.t
  103. +
  104. vfsgnj.vv v4, v8, v12
  105. vfsgnj.vf v4, v8, fa2
  106. vfsgnjn.vv v4, v8, v12
  107. diff --git a/opcodes/riscv-opc.c b/opcodes/riscv-opc.c
  108. index af3d787fe6..e0383d08e9 100644
  109. --- a/opcodes/riscv-opc.c
  110. +++ b/opcodes/riscv-opc.c
  111. @@ -138,6 +138,27 @@ match_vs1_eq_vs2 (const struct riscv_opcode *op,
  112. return match_opcode (op, insn, 0, NULL) && vs1 == vs2;
  113. }
  114. +static int
  115. +match_vs1_eq_vs2_neq_vm (const struct riscv_opcode *op,
  116. + insn_t insn,
  117. + int constraints,
  118. + const char **error)
  119. +{
  120. + int vd = (insn & MASK_VD) >> OP_SH_VD;
  121. + int vs1 = (insn & MASK_VS1) >> OP_SH_VS1;
  122. + int vs2 = (insn & MASK_VS2) >> OP_SH_VS2;
  123. + int vm = (insn & MASK_VMASK) >> OP_SH_VMASK;
  124. +
  125. + if (!constraints || error == NULL)
  126. + return match_opcode (op, insn, 0, NULL) && vs1 == vs2;
  127. +
  128. + if (!vm && vm == vd)
  129. + *error = "illegal operands vd cannot overlap vm";
  130. + else
  131. + return match_opcode (op, insn, 0, NULL) && vs1 == vs2;
  132. + return 0;
  133. +}
  134. +
  135. static int
  136. match_vd_eq_vs1_eq_vs2 (const struct riscv_opcode *op,
  137. insn_t insn,
  138. @@ -1819,6 +1840,8 @@ const struct riscv_opcode riscv_opcodes[] =
  139. {"vamominuei64.v", 0, INSN_CLASS_V_OR_ZVAMO, "Ve,0(s),Vt,VfVm", MATCH_VAMOMINUEI64V, MASK_VAMOMINUEI64V, match_vd_neq_vm, INSN_DREF},
  140. {"vamomaxuei64.v", 0, INSN_CLASS_V_OR_ZVAMO, "Ve,0(s),Vt,VfVm", MATCH_VAMOMAXUEI64V, MASK_VAMOMAXUEI64V, match_vd_neq_vm, INSN_DREF},
  141. +{"vneg.v", 0, INSN_CLASS_V, "Vd,VtVm", MATCH_VRSUBVX, MASK_VRSUBVX | MASK_RS1, match_vd_neq_vm, INSN_ALIAS },
  142. +
  143. {"vadd.vv", 0, INSN_CLASS_V, "Vd,Vt,VsVm", MATCH_VADDVV, MASK_VADDVV, match_vd_neq_vm, 0 },
  144. {"vadd.vx", 0, INSN_CLASS_V, "Vd,Vt,sVm", MATCH_VADDVX, MASK_VADDVX, match_vd_neq_vm, 0 },
  145. {"vadd.vi", 0, INSN_CLASS_V, "Vd,Vt,ViVm", MATCH_VADDVI, MASK_VADDVI, match_vd_neq_vm, 0 },
  146. @@ -2103,6 +2126,8 @@ const struct riscv_opcode riscv_opcodes[] =
  147. {"vfmax.vv", 0, INSN_CLASS_V_AND_F, "Vd,Vt,VsVm", MATCH_VFMAXVV, MASK_VFMAXVV, match_vd_neq_vm, 0},
  148. {"vfmax.vf", 0, INSN_CLASS_V_AND_F, "Vd,Vt,SVm", MATCH_VFMAXVF, MASK_VFMAXVF, match_vd_neq_vm, 0},
  149. +{"vfneg.v", 0, INSN_CLASS_V_AND_F, "Vd,VuVm", MATCH_VFSGNJNVV, MASK_VFSGNJNVV, match_vs1_eq_vs2_neq_vm, INSN_ALIAS },
  150. +
  151. {"vfsgnj.vv", 0, INSN_CLASS_V_AND_F, "Vd,Vt,VsVm", MATCH_VFSGNJVV, MASK_VFSGNJVV, match_vd_neq_vm, 0},
  152. {"vfsgnj.vf", 0, INSN_CLASS_V_AND_F, "Vd,Vt,SVm", MATCH_VFSGNJVF, MASK_VFSGNJVF, match_vd_neq_vm, 0},
  153. {"vfsgnjn.vv", 0, INSN_CLASS_V_AND_F, "Vd,Vt,VsVm", MATCH_VFSGNJNVV, MASK_VFSGNJNVV, match_vd_neq_vm, 0},
  154. --
  155. 2.33.0