0021-Make-vlmul-bits-contiguous-in-vtype.patch 7.0 KB

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  1. From 3013bd5c37a680dfafd903b0bb06c5c8ad31ce7f Mon Sep 17 00:00:00 2001
  2. From: Nelson Chu <nelson.chu@sifive.com>
  3. Date: Wed, 22 Jul 2020 10:38:15 +0800
  4. Subject: [PATCH 21/48] Make vlmul bits contiguous in vtype.
  5. ---
  6. gas/config/tc-riscv.c | 6 +++---
  7. gas/testsuite/gas/riscv/insn.d | 4 ++--
  8. gas/testsuite/gas/riscv/vector-insns.d | 30 +++++++++++++-------------
  9. include/opcode/riscv.h | 21 ++++++------------
  10. opcodes/riscv-dis.c | 2 +-
  11. 5 files changed, 27 insertions(+), 36 deletions(-)
  12. diff --git a/gas/config/tc-riscv.c b/gas/config/tc-riscv.c
  13. index 222214d7e4..67353ab725 100644
  14. --- a/gas/config/tc-riscv.c
  15. +++ b/gas/config/tc-riscv.c
  16. @@ -1880,11 +1880,11 @@ my_getVsetvliExpression (expressionS *ep, char *str)
  17. if (vsew_found || vlmul_found || vediv_found || vta_found || vma_found)
  18. {
  19. ep->X_op = O_constant;
  20. - ep->X_add_number = (vediv_value << OP_SH_VEDIV)
  21. + ep->X_add_number = (vlmul_value << OP_SH_VLMUL)
  22. | (vsew_value << OP_SH_VSEW)
  23. | (vta_value << OP_SH_VTA)
  24. - | (vma_value << OP_SH_VMA) ;
  25. - INSERT_VLMUL (ep->X_add_number, vlmul_value);
  26. + | (vma_value << OP_SH_VMA)
  27. + | (vediv_value << OP_SH_VEDIV);
  28. expr_end = str;
  29. }
  30. else
  31. diff --git a/gas/testsuite/gas/riscv/insn.d b/gas/testsuite/gas/riscv/insn.d
  32. index 9d417b0794..e55f21c179 100644
  33. --- a/gas/testsuite/gas/riscv/insn.d
  34. +++ b/gas/testsuite/gas/riscv/insn.d
  35. @@ -122,8 +122,8 @@ Disassembly of section .text:
  36. [^:]+:[ ]+00d655d7[ ]+vfadd.vf[ ]+v11,v13,fa2,v0.t
  37. [^:]+:[ ]+38d665d7[ ]+vslide1up.vx[ ]+v11,v13,a2,v0.t
  38. [^:]+:[ ]+3cd665d7[ ]+vslide1down.vx[ ]+v11,v13,a2,v0.t
  39. -[^:]+:[ ]+00d675d7[ ]+vsetvli[ ]+a1,a2,e64,m2,tu,mu,d1
  40. -[^:]+:[ ]+00d675d7[ ]+vsetvli[ ]+a1,a2,e64,m2,tu,mu,d1
  41. +[^:]+:[ ]+00d675d7[ ]+vsetvli[ ]+a1,a2,e16,mf8,tu,mu,d1
  42. +[^:]+:[ ]+00d675d7[ ]+vsetvli[ ]+a1,a2,e16,mf8,tu,mu,d1
  43. [^:]+:[ ]+00d035d7[ ]+vadd.vi[ ]+v11,v13,0,v0.t
  44. [^:]+:[ ]+00d0b5d7[ ]+vadd.vi[ ]+v11,v13,1,v0.t
  45. [^:]+:[ ]+00d7b5d7[ ]+vadd.vi[ ]+v11,v13,15,v0.t
  46. diff --git a/gas/testsuite/gas/riscv/vector-insns.d b/gas/testsuite/gas/riscv/vector-insns.d
  47. index 8ac80fba1b..24a559cee5 100644
  48. --- a/gas/testsuite/gas/riscv/vector-insns.d
  49. +++ b/gas/testsuite/gas/riscv/vector-insns.d
  50. @@ -10,22 +10,22 @@ Disassembly of section .text:
  51. [ ]+[0-9a-f]+:[ ]+80c5f557[ ]+vsetvl[ ]+a0,a1,a2
  52. [ ]+[0-9a-f]+:[ ]+0005f557[ ]+vsetvli[ ]+a0,a1,e8,m1,tu,mu,d1
  53. [ ]+[0-9a-f]+:[ ]+7ff5f557[ ]+vsetvli[ ]+a0,a1,2047
  54. -[ ]+[0-9a-f]+:[ ]+2055f557[ ]+vsetvli[ ]+a0,a1,e16,m2,tu,mu,d4
  55. -[ ]+[0-9a-f]+:[ ]+3175f557[ ]+vsetvli[ ]+a0,a1,e256,m8,tu,mu,d8
  56. -[ ]+[0-9a-f]+:[ ]+31b5f557[ ]+vsetvli[ ]+a0,a1,e512,m8,tu,mu,d8
  57. -[ ]+[0-9a-f]+:[ ]+31f5f557[ ]+vsetvli[ ]+a0,a1,e1024,m8,tu,mu,d8
  58. -[ ]+[0-9a-f]+:[ ]+31c5f557[ ]+vsetvli[ ]+a0,a1,e1024,m1,tu,mu,d8
  59. +[ ]+[0-9a-f]+:[ ]+2095f557[ ]+vsetvli[ ]+a0,a1,e16,m2,tu,mu,d4
  60. +[ ]+[0-9a-f]+:[ ]+32b5f557[ ]+vsetvli[ ]+a0,a1,e256,m8,tu,mu,d8
  61. +[ ]+[0-9a-f]+:[ ]+3335f557[ ]+vsetvli[ ]+a0,a1,e512,m8,tu,mu,d8
  62. +[ ]+[0-9a-f]+:[ ]+33b5f557[ ]+vsetvli[ ]+a0,a1,e1024,m8,tu,mu,d8
  63. +[ ]+[0-9a-f]+:[ ]+3385f557[ ]+vsetvli[ ]+a0,a1,e1024,m1,tu,mu,d8
  64. [ ]+[0-9a-f]+:[ ]+33f5f557[ ]+vsetvli[ ]+a0,a1,e1024,mf2,tu,mu,d8
  65. -[ ]+[0-9a-f]+:[ ]+13a5f557[ ]+vsetvli[ ]+a0,a1,e512,mf4,tu,mu,d2
  66. -[ ]+[0-9a-f]+:[ ]+2355f557[ ]+vsetvli[ ]+a0,a1,e256,mf8,tu,mu,d4
  67. -[ ]+[0-9a-f]+:[ ]+2555f557[ ]+vsetvli[ ]+a0,a1,e256,m2,ta,mu,d4
  68. -[ ]+[0-9a-f]+:[ ]+2955f557[ ]+vsetvli[ ]+a0,a1,e256,m2,tu,ma,d4
  69. -[ ]+[0-9a-f]+:[ ]+2155f557[ ]+vsetvli[ ]+a0,a1,e256,m2,tu,mu,d4
  70. -[ ]+[0-9a-f]+:[ ]+2155f557[ ]+vsetvli[ ]+a0,a1,e256,m2,tu,mu,d4
  71. -[ ]+[0-9a-f]+:[ ]+2d55f557[ ]+vsetvli[ ]+a0,a1,e256,m2,ta,ma,d4
  72. -[ ]+[0-9a-f]+:[ ]+2955f557[ ]+vsetvli[ ]+a0,a1,e256,m2,tu,ma,d4
  73. -[ ]+[0-9a-f]+:[ ]+2555f557[ ]+vsetvli[ ]+a0,a1,e256,m2,ta,mu,d4
  74. -[ ]+[0-9a-f]+:[ ]+2155f557[ ]+vsetvli[ ]+a0,a1,e256,m2,tu,mu,d4
  75. +[ ]+[0-9a-f]+:[ ]+1365f557[ ]+vsetvli[ ]+a0,a1,e512,mf4,tu,mu,d2
  76. +[ ]+[0-9a-f]+:[ ]+22d5f557[ ]+vsetvli[ ]+a0,a1,e256,mf8,tu,mu,d4
  77. +[ ]+[0-9a-f]+:[ ]+2695f557[ ]+vsetvli[ ]+a0,a1,e256,m2,ta,mu,d4
  78. +[ ]+[0-9a-f]+:[ ]+2a95f557[ ]+vsetvli[ ]+a0,a1,e256,m2,tu,ma,d4
  79. +[ ]+[0-9a-f]+:[ ]+2295f557[ ]+vsetvli[ ]+a0,a1,e256,m2,tu,mu,d4
  80. +[ ]+[0-9a-f]+:[ ]+2295f557[ ]+vsetvli[ ]+a0,a1,e256,m2,tu,mu,d4
  81. +[ ]+[0-9a-f]+:[ ]+2e95f557[ ]+vsetvli[ ]+a0,a1,e256,m2,ta,ma,d4
  82. +[ ]+[0-9a-f]+:[ ]+2a95f557[ ]+vsetvli[ ]+a0,a1,e256,m2,tu,ma,d4
  83. +[ ]+[0-9a-f]+:[ ]+2695f557[ ]+vsetvli[ ]+a0,a1,e256,m2,ta,mu,d4
  84. +[ ]+[0-9a-f]+:[ ]+2295f557[ ]+vsetvli[ ]+a0,a1,e256,m2,tu,mu,d4
  85. [ ]+[0-9a-f]+:[ ]+02050207[ ]+vle8.v[ ]+v4,\(a0\)
  86. [ ]+[0-9a-f]+:[ ]+02050207[ ]+vle8.v[ ]+v4,\(a0\)
  87. [ ]+[0-9a-f]+:[ ]+00050207[ ]+vle8.v[ ]+v4,\(a0\),v0.t
  88. diff --git a/include/opcode/riscv.h b/include/opcode/riscv.h
  89. index 62049bdd23..b1d3c068db 100644
  90. --- a/include/opcode/riscv.h
  91. +++ b/include/opcode/riscv.h
  92. @@ -310,18 +310,18 @@ static const char * const riscv_vma[2] =
  93. #define OP_MASK_VFUNCT6 0x3f
  94. #define OP_SH_VFUNCT6 26
  95. -#define OP_MASK_VLMUL 0x23
  96. +#define OP_MASK_VLMUL 0x7
  97. #define OP_SH_VLMUL 0
  98. #define OP_MASK_VSEW 0x7
  99. -#define OP_SH_VSEW 2
  100. -#define OP_MASK_VEDIV 0x3
  101. -#define OP_SH_VEDIV 8
  102. -#define OP_MASK_VTYPE_RES 0x1
  103. -#define OP_SH_VTYPE_RES 10
  104. +#define OP_SH_VSEW 3
  105. #define OP_MASK_VTA 0x1
  106. #define OP_SH_VTA 6
  107. #define OP_MASK_VMA 0x1
  108. #define OP_SH_VMA 7
  109. +#define OP_MASK_VEDIV 0x3
  110. +#define OP_SH_VEDIV 8
  111. +#define OP_MASK_VTYPE_RES 0x1
  112. +#define OP_SH_VTYPE_RES 10
  113. #define OP_MASK_VWD 0x1
  114. #define OP_SH_VWD 26
  115. @@ -354,10 +354,6 @@ static const char * const riscv_vma[2] =
  116. (STRUCT) = (((STRUCT) & ~((insn_t)(MASK) << (SHIFT))) \
  117. | ((insn_t)((VALUE) & (MASK)) << (SHIFT)))
  118. -#define INSERT_VLMUL(STRUCT, VALUE) \
  119. - INSERT_BITS (STRUCT, (VALUE & 0x3), (OP_MASK_VLMUL & 0x3), 0), \
  120. - INSERT_BITS (STRUCT, (((VALUE & 0x4) >> 2) <<5), (OP_MASK_VLMUL & 0x20), 0)
  121. -
  122. /* Extract bits MASK << SHIFT from STRUCT and shift them right
  123. SHIFT places. */
  124. #define EXTRACT_BITS(STRUCT, MASK, SHIFT) \
  125. @@ -367,11 +363,6 @@ static const char * const riscv_vma[2] =
  126. #define EXTRACT_OPERAND(FIELD, INSN) \
  127. EXTRACT_BITS ((INSN), OP_MASK_##FIELD, OP_SH_##FIELD)
  128. -/* Extract the vlmul value from vsetvli instrucion. */
  129. -#define EXTRACT_VLMUL(INSN) \
  130. - (((EXTRACT_OPERAND (VLMUL, INSN) >> 5) << 2) \
  131. - | (EXTRACT_OPERAND (VLMUL, INSN) & 0x3))
  132. -
  133. /* The maximal number of subset can be required. */
  134. #define MAX_SUBSET_NUM 4
  135. diff --git a/opcodes/riscv-dis.c b/opcodes/riscv-dis.c
  136. index 25e0a93e88..875b69a1da 100644
  137. --- a/opcodes/riscv-dis.c
  138. +++ b/opcodes/riscv-dis.c
  139. @@ -439,7 +439,7 @@ print_insn_args (const char *d, insn_t l, bfd_vma pc, disassemble_info *info)
  140. case 'c':
  141. {
  142. int imm = EXTRACT_RVV_VC_IMM (l);
  143. - unsigned int imm_vlmul = EXTRACT_VLMUL (imm);
  144. + unsigned int imm_vlmul = EXTRACT_OPERAND (VLMUL, imm);
  145. unsigned int imm_vsew = EXTRACT_OPERAND (VSEW, imm);
  146. unsigned int imm_vediv = EXTRACT_OPERAND (VEDIV, imm);
  147. unsigned int imm_vta = EXTRACT_OPERAND (VTA, imm);
  148. --
  149. 2.33.0