0041-RISC-V-Re-define-zba-zbb-zbc-and-zbs-extensions.patch 42 KB

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  1. From f6a5298d5c929a9d30fa56ddc14d686892f9bafc Mon Sep 17 00:00:00 2001
  2. From: Nelson Chu <nelson.chu@sifive.com>
  3. Date: Mon, 7 Dec 2020 16:25:05 +0800
  4. Subject: [PATCH 41/48] RISC-V: Re-define zba, zbb, zbc and zbs extensions.
  5. Andrew had re-defined zba, zbb, zbc and zbs on the tech-bitmanip mail list.
  6. Other instructions and sub-extensions are still discussing, so I change their
  7. type to INSN_CLASS_B, to keep the encodings and implementations, but we
  8. do need to re-define them in the future.
  9. Besides, B includes all of the zb*, except zbr and zbt.
  10. ---
  11. gas/config/tc-riscv.c | 38 ++--
  12. include/opcode/riscv.h | 14 +-
  13. opcodes/riscv-opc.c | 409 +++++++++++++++++++++--------------------
  14. 3 files changed, 232 insertions(+), 229 deletions(-)
  15. diff --git a/gas/config/tc-riscv.c b/gas/config/tc-riscv.c
  16. index b53442b8b4..b1b86a7afb 100644
  17. --- a/gas/config/tc-riscv.c
  18. +++ b/gas/config/tc-riscv.c
  19. @@ -260,39 +260,35 @@ riscv_multi_subset_supports (enum riscv_insn_class insn_class)
  20. case INSN_CLASS_V_AND_ZVQMAC:
  21. return riscv_subset_supports ("v") && riscv_subset_supports ("zvqmac");
  22. - case INSN_CLASS_B_OR_ZBB:
  23. - return riscv_subset_supports ("b") || riscv_subset_supports ("zbb");
  24. -
  25. + /* Sure. */
  26. case INSN_CLASS_B_OR_ZBA:
  27. return riscv_subset_supports ("b") || riscv_subset_supports ("zba");
  28. -
  29. + case INSN_CLASS_B_OR_ZBB:
  30. + return riscv_subset_supports ("b") || riscv_subset_supports ("zbb");
  31. case INSN_CLASS_B_OR_ZBC:
  32. return riscv_subset_supports ("b") || riscv_subset_supports ("zbc");
  33. -
  34. + case INSN_CLASS_B_OR_ZBS:
  35. + return riscv_subset_supports ("b") || riscv_subset_supports ("zbs");
  36. + case INSN_CLASS_B_OR_ZBA_OR_ZBB:
  37. + return (riscv_subset_supports ("b")
  38. + || riscv_subset_supports ("zba")
  39. + || riscv_subset_supports ("zbb"));
  40. +
  41. + /* Not sure. */
  42. + case INSN_CLASS_B:
  43. + return riscv_subset_supports ("b");
  44. case INSN_CLASS_B_OR_ZBE:
  45. return riscv_subset_supports ("b") || riscv_subset_supports ("zbe");
  46. -
  47. case INSN_CLASS_B_OR_ZBF:
  48. return riscv_subset_supports ("b") || riscv_subset_supports ("zbf");
  49. -
  50. case INSN_CLASS_B_OR_ZBM:
  51. return riscv_subset_supports ("b") || riscv_subset_supports ("zbm");
  52. -
  53. case INSN_CLASS_B_OR_ZBP:
  54. return riscv_subset_supports ("b") || riscv_subset_supports ("zbp");
  55. -
  56. - case INSN_CLASS_B_OR_ZBR:
  57. - return riscv_subset_supports ("b") || riscv_subset_supports ("zbr");
  58. -
  59. - case INSN_CLASS_B_OR_ZBS:
  60. - return riscv_subset_supports ("b") || riscv_subset_supports ("zbs");
  61. -
  62. - case INSN_CLASS_B_OR_ZBT:
  63. - return riscv_subset_supports ("b") || riscv_subset_supports ("zbt");
  64. -
  65. - case INSN_CLASS_B_OR_ZBB_OR_ZBP:
  66. - return riscv_subset_supports ("b") || riscv_subset_supports ("zbb")
  67. - || riscv_subset_supports ("zbp");
  68. + case INSN_CLASS_ZBR:
  69. + return riscv_subset_supports ("zbr");
  70. + case INSN_CLASS_ZBT:
  71. + return riscv_subset_supports ("zbt");
  72. default:
  73. as_fatal ("Unreachable");
  74. diff --git a/include/opcode/riscv.h b/include/opcode/riscv.h
  75. index 5303d14998..a23a2a8002 100644
  76. --- a/include/opcode/riscv.h
  77. +++ b/include/opcode/riscv.h
  78. @@ -379,6 +379,7 @@ enum riscv_insn_class
  79. INSN_CLASS_F,
  80. INSN_CLASS_D,
  81. INSN_CLASS_Q,
  82. + INSN_CLASS_B,
  83. INSN_CLASS_V,
  84. INSN_CLASS_F_AND_C,
  85. INSN_CLASS_F_AND_ZFH,
  86. @@ -390,19 +391,18 @@ enum riscv_insn_class
  87. INSN_CLASS_V_AND_ZVEDIV,
  88. INSN_CLASS_V_OR_ZVLSSEG,
  89. INSN_CLASS_V_AND_ZVQMAC,
  90. -
  91. - INSN_CLASS_B,
  92. - INSN_CLASS_B_OR_ZBT,
  93. - INSN_CLASS_B_OR_ZBR,
  94. - INSN_CLASS_B_OR_ZBB,
  95. INSN_CLASS_B_OR_ZBA,
  96. + INSN_CLASS_B_OR_ZBB,
  97. INSN_CLASS_B_OR_ZBC,
  98. + INSN_CLASS_B_OR_ZBS,
  99. + INSN_CLASS_B_OR_ZBA_OR_ZBB,
  100. +
  101. INSN_CLASS_B_OR_ZBE,
  102. INSN_CLASS_B_OR_ZBF,
  103. INSN_CLASS_B_OR_ZBM,
  104. INSN_CLASS_B_OR_ZBP,
  105. - INSN_CLASS_B_OR_ZBS,
  106. - INSN_CLASS_B_OR_ZBB_OR_ZBP
  107. + INSN_CLASS_ZBR,
  108. + INSN_CLASS_ZBT,
  109. };
  110. /* This structure holds information for a particular instruction. */
  111. diff --git a/opcodes/riscv-opc.c b/opcodes/riscv-opc.c
  112. index dbabc5c2f6..86cfcabec9 100644
  113. --- a/opcodes/riscv-opc.c
  114. +++ b/opcodes/riscv-opc.c
  115. @@ -984,220 +984,227 @@ const struct riscv_opcode riscv_opcodes[] =
  116. {"fcvt.h.lu", 64, INSN_CLASS_F_AND_ZFH, "D,s", MATCH_FCVT_H_LU | MASK_RM, MASK_FCVT_H_L | MASK_RM, match_opcode, 0 },
  117. {"fcvt.h.lu", 64, INSN_CLASS_F_AND_ZFH, "D,s,m", MATCH_FCVT_H_LU, MASK_FCVT_H_LU, match_opcode, 0 },
  118. -/* Bitmanip instruction subset */
  119. -{"andn", 0, INSN_CLASS_B_OR_ZBB_OR_ZBP, "d,s,t", MATCH_ANDN, MASK_ANDN, match_opcode, 0 },
  120. -{"orn", 0, INSN_CLASS_B_OR_ZBB_OR_ZBP, "d,s,t", MATCH_ORN, MASK_ORN, match_opcode, 0 },
  121. -{"xnor", 0, INSN_CLASS_B_OR_ZBB_OR_ZBP, "d,s,t", MATCH_XNOR, MASK_XNOR, match_opcode, 0 },
  122. -{"sloi", 0, INSN_CLASS_B_OR_ZBP, "d,s,>", MATCH_SLOI, MASK_SLOI, match_opcode, 0 },
  123. -{"sroi", 0, INSN_CLASS_B_OR_ZBP, "d,s,>", MATCH_SROI, MASK_SROI, match_opcode, 0 },
  124. -{"roli", 0, INSN_CLASS_B_OR_ZBB_OR_ZBP, "d,s,>", 0, (int) M_RL, match_never, INSN_MACRO },
  125. -{"rori", 0, INSN_CLASS_B_OR_ZBB_OR_ZBP, "d,s,>", MATCH_RORI, MASK_RORI, match_opcode, 0 },
  126. -{"slo", 0, INSN_CLASS_B_OR_ZBP, "d,s,t", MATCH_SLO, MASK_SLO, match_opcode, 0 },
  127. -{"slo", 0, INSN_CLASS_B_OR_ZBP, "d,s,>", MATCH_SLOI, MASK_SLOI, match_opcode, INSN_ALIAS },
  128. -{"sro", 0, INSN_CLASS_B_OR_ZBP, "d,s,t", MATCH_SRO, MASK_SRO, match_opcode, 0 },
  129. -{"sro", 0, INSN_CLASS_B_OR_ZBP, "d,s,>", MATCH_SROI, MASK_SROI, match_opcode, INSN_ALIAS },
  130. -{"rol", 0, INSN_CLASS_B_OR_ZBB_OR_ZBP, "d,s,t", MATCH_ROL, MASK_ROL, match_opcode, 0 },
  131. -{"rol", 0, INSN_CLASS_B_OR_ZBB_OR_ZBP, "d,s,>", 0, (int) M_RL, match_never, INSN_MACRO },
  132. -{"ror", 0, INSN_CLASS_B_OR_ZBB_OR_ZBP, "d,s,t", MATCH_ROR, MASK_ROR, match_opcode, 0 },
  133. -{"ror", 0, INSN_CLASS_B_OR_ZBB_OR_ZBP, "d,s,>", MATCH_RORI, MASK_RORI, match_opcode, INSN_ALIAS },
  134. -{"sbclri", 0, INSN_CLASS_B_OR_ZBS, "d,s,>", MATCH_SBCLRI, MASK_SBCLRI, match_opcode, 0 },
  135. -{"sbseti", 0, INSN_CLASS_B_OR_ZBS, "d,s,>", MATCH_SBSETI, MASK_SBSETI, match_opcode, 0 },
  136. -{"sbinvi", 0, INSN_CLASS_B_OR_ZBS, "d,s,>", MATCH_SBINVI, MASK_SBINVI, match_opcode, 0 },
  137. -{"sbexti", 0, INSN_CLASS_B_OR_ZBS, "d,s,>", MATCH_SBEXTI, MASK_SBEXTI, match_opcode, 0 },
  138. -{"gorci", 0, INSN_CLASS_B_OR_ZBP, "d,s,>", MATCH_GORCI, MASK_GORCI, match_opcode, 0 },
  139. -{"grevi", 0, INSN_CLASS_B_OR_ZBP, "d,s,>", MATCH_GREVI, MASK_GREVI, match_opcode, 0 },
  140. -{"sbclr", 0, INSN_CLASS_B_OR_ZBS, "d,s,t", MATCH_SBCLR, MASK_SBCLR, match_opcode, 0 },
  141. -{"sbclr", 0, INSN_CLASS_B_OR_ZBS, "d,s,>", MATCH_SBCLRI, MASK_SBCLRI, match_opcode, INSN_ALIAS },
  142. -{"sbset", 0, INSN_CLASS_B_OR_ZBS, "d,s,t", MATCH_SBSET, MASK_SBSET, match_opcode, 0 },
  143. -{"sbset", 0, INSN_CLASS_B_OR_ZBS, "d,s,>", MATCH_SBSETI, MASK_SBSETI, match_opcode, INSN_ALIAS },
  144. -{"sbinv", 0, INSN_CLASS_B_OR_ZBS, "d,s,t", MATCH_SBINV, MASK_SBINV, match_opcode, 0 },
  145. -{"sbinv", 0, INSN_CLASS_B_OR_ZBS, "d,s,>", MATCH_SBINVI, MASK_SBINVI, match_opcode, INSN_ALIAS },
  146. -{"sbext", 0, INSN_CLASS_B_OR_ZBS, "d,s,t", MATCH_SBEXT, MASK_SBEXT, match_opcode, 0 },
  147. -{"sbext", 0, INSN_CLASS_B_OR_ZBS, "d,s,>", MATCH_SBEXTI, MASK_SBEXTI, match_opcode, INSN_ALIAS },
  148. -{"gorc", 0, INSN_CLASS_B_OR_ZBP, "d,s,t", MATCH_GORC, MASK_GORC, match_opcode, 0 },
  149. -{"gorc", 0, INSN_CLASS_B_OR_ZBP, "d,s,>", MATCH_GORCI, MASK_GORCI, match_opcode, INSN_ALIAS },
  150. -{"grev", 0, INSN_CLASS_B_OR_ZBP, "d,s,t", MATCH_GREV, MASK_GREV, match_opcode, 0 },
  151. -{"grev", 0, INSN_CLASS_B_OR_ZBP, "d,s,>", MATCH_GREVI, MASK_GREVI, match_opcode, INSN_ALIAS },
  152. -{"cmix", 0, INSN_CLASS_B_OR_ZBT, "d,t,s,r", MATCH_CMIX, MASK_CMIX, match_opcode, 0 },
  153. -{"cmov", 0, INSN_CLASS_B_OR_ZBT, "d,t,s,r", MATCH_CMOV, MASK_CMOV, match_opcode, 0 },
  154. -{"fsli", 0, INSN_CLASS_B_OR_ZBT, "d,s,r,>", 0, (int) M_FL, match_never, INSN_MACRO },
  155. -{"fsri", 0, INSN_CLASS_B_OR_ZBT, "d,s,r,>", MATCH_FSRI, MASK_FSRI, match_opcode, 0 },
  156. -{"fsl", 0, INSN_CLASS_B_OR_ZBT, "d,s,r,t", MATCH_FSL, MASK_FSL, match_opcode, 0 },
  157. -{"fsl", 0, INSN_CLASS_B_OR_ZBT, "d,s,r,>", 0, (int) M_FL, match_never, INSN_MACRO },
  158. -{"fsr", 0, INSN_CLASS_B_OR_ZBT, "d,s,r,t", MATCH_FSR, MASK_FSR, match_opcode, 0 },
  159. -{"fsr", 0, INSN_CLASS_B_OR_ZBT, "d,s,r,>", MATCH_FSRI, MASK_FSRI, match_opcode, INSN_ALIAS },
  160. +/* Bitmanip instruction subset - for sure */
  161. +{"sh1add", 0, INSN_CLASS_B_OR_ZBA, "d,s,t", MATCH_SH1ADD, MASK_SH1ADD, match_opcode, 0 },
  162. +{"sh2add", 0, INSN_CLASS_B_OR_ZBA, "d,s,t", MATCH_SH2ADD, MASK_SH2ADD, match_opcode, 0 },
  163. +{"sh3add", 0, INSN_CLASS_B_OR_ZBA, "d,s,t", MATCH_SH3ADD, MASK_SH3ADD, match_opcode, 0 },
  164. +{"slliu.w", 64, INSN_CLASS_B_OR_ZBA, "d,s,>", MATCH_SLLIU_W, MASK_SLLIU_W, match_opcode, 0 },
  165. +{"zext.w", 64, INSN_CLASS_B_OR_ZBA_OR_ZBB, "d,s", MATCH_ADDU_W, MASK_ADDU_W | MASK_RS2, match_opcode, INSN_ALIAS },
  166. +{"addu.w", 64, INSN_CLASS_B_OR_ZBA, "d,s,t", MATCH_ADDU_W, MASK_ADDU_W, match_opcode, 0 },
  167. +{"sh1addu.w",64, INSN_CLASS_B_OR_ZBA, "d,s,t", MATCH_SH1ADDU_W, MASK_SH1ADDU_W, match_opcode, 0 },
  168. +{"sh2addu.w",64, INSN_CLASS_B_OR_ZBA, "d,s,t", MATCH_SH2ADDU_W, MASK_SH2ADDU_W, match_opcode, 0 },
  169. +{"sh3addu.w",64, INSN_CLASS_B_OR_ZBA, "d,s,t", MATCH_SH3ADDU_W, MASK_SH3ADDU_W, match_opcode, 0 },
  170. +
  171. {"clz", 0, INSN_CLASS_B_OR_ZBB, "d,s", MATCH_CLZ, MASK_CLZ, match_opcode, 0 },
  172. {"ctz", 0, INSN_CLASS_B_OR_ZBB, "d,s", MATCH_CTZ, MASK_CTZ, match_opcode, 0 },
  173. {"pcnt", 0, INSN_CLASS_B_OR_ZBB, "d,s", MATCH_PCNT, MASK_PCNT, match_opcode, 0 },
  174. +{"min", 0, INSN_CLASS_B_OR_ZBB, "d,s,t", MATCH_MIN, MASK_MIN, match_opcode, 0 },
  175. +{"max", 0, INSN_CLASS_B_OR_ZBB, "d,s,t", MATCH_MAX, MASK_MAX, match_opcode, 0 },
  176. +{"minu", 0, INSN_CLASS_B_OR_ZBB, "d,s,t", MATCH_MINU, MASK_MINU, match_opcode, 0 },
  177. +{"maxu", 0, INSN_CLASS_B_OR_ZBB, "d,s,t", MATCH_MAXU, MASK_MAXU, match_opcode, 0 },
  178. +{"andn", 0, INSN_CLASS_B_OR_ZBB, "d,s,t", MATCH_ANDN, MASK_ANDN, match_opcode, 0 },
  179. +{"orn", 0, INSN_CLASS_B_OR_ZBB, "d,s,t", MATCH_ORN, MASK_ORN, match_opcode, 0 },
  180. +{"xnor", 0, INSN_CLASS_B_OR_ZBB, "d,s,t", MATCH_XNOR, MASK_XNOR, match_opcode, 0 },
  181. +{"roli", 0, INSN_CLASS_B_OR_ZBB, "d,s,>", 0, (int) M_RL, match_never, INSN_MACRO }, /* rori */
  182. +{"rol", 0, INSN_CLASS_B_OR_ZBB, "d,s,t", MATCH_ROL, MASK_ROL, match_opcode, 0 },
  183. +{"rol", 0, INSN_CLASS_B_OR_ZBB, "d,s,>", 0, (int) M_RL, match_never, INSN_MACRO }, /* rori */
  184. +{"rori", 0, INSN_CLASS_B_OR_ZBB, "d,s,>", MATCH_RORI, MASK_RORI, match_opcode, 0 },
  185. +{"ror", 0, INSN_CLASS_B_OR_ZBB, "d,s,t", MATCH_ROR, MASK_ROR, match_opcode, 0 },
  186. +{"ror", 0, INSN_CLASS_B_OR_ZBB, "d,s,>", MATCH_RORI, MASK_RORI, match_opcode, INSN_ALIAS },
  187. {"sext.b", 0, INSN_CLASS_B_OR_ZBB, "d,s", MATCH_SEXT_B, MASK_SEXT_B, match_opcode, 0 },
  188. {"sext.h", 0, INSN_CLASS_B_OR_ZBB, "d,s", MATCH_SEXT_H, MASK_SEXT_H, match_opcode, 0 },
  189. -{"bmatflip", 64, INSN_CLASS_B_OR_ZBM, "d,s", MATCH_BMATFLIP, MASK_BMATFLIP, match_opcode, 0 },
  190. -{"crc32.b", 0, INSN_CLASS_B_OR_ZBR, "d,s", MATCH_CRC32_B, MASK_CRC32_B, match_opcode, 0 },
  191. -{"crc32.h", 0, INSN_CLASS_B_OR_ZBR, "d,s", MATCH_CRC32_H, MASK_CRC32_H, match_opcode, 0 },
  192. -{"crc32.w", 0, INSN_CLASS_B_OR_ZBR, "d,s", MATCH_CRC32_W, MASK_CRC32_W, match_opcode, 0 },
  193. -{"crc32.d", 64, INSN_CLASS_B_OR_ZBR, "d,s", MATCH_CRC32_D, MASK_CRC32_D, match_opcode, 0 },
  194. -{"crc32c.b", 0, INSN_CLASS_B_OR_ZBR, "d,s", MATCH_CRC32C_B, MASK_CRC32C_B, match_opcode, 0 },
  195. -{"crc32c.h", 0, INSN_CLASS_B_OR_ZBR, "d,s", MATCH_CRC32C_H, MASK_CRC32C_H, match_opcode, 0 },
  196. -{"crc32c.w", 0, INSN_CLASS_B_OR_ZBR, "d,s", MATCH_CRC32C_W, MASK_CRC32C_W, match_opcode, 0 },
  197. -{"crc32c.d", 64, INSN_CLASS_B_OR_ZBR, "d,s", MATCH_CRC32C_D, MASK_CRC32C_D, match_opcode, 0 },
  198. -{"sh1add", 0, INSN_CLASS_B_OR_ZBA, "d,s,t", MATCH_SH1ADD, MASK_SH1ADD, match_opcode, 0 },
  199. -{"sh2add", 0, INSN_CLASS_B_OR_ZBA, "d,s,t", MATCH_SH2ADD, MASK_SH2ADD, match_opcode, 0 },
  200. -{"sh3add", 0, INSN_CLASS_B_OR_ZBA, "d,s,t", MATCH_SH3ADD, MASK_SH3ADD, match_opcode, 0 },
  201. +{"zext.h", 32, INSN_CLASS_B_OR_ZBB, "d,s", MATCH_PACK, MASK_PACK | MASK_RS2, match_opcode, INSN_ALIAS }, /* pack with rs2=x0 */
  202. +{"zext.h", 64, INSN_CLASS_B_OR_ZBB, "d,s", MATCH_PACKW, MASK_PACKW | MASK_RS2, match_opcode, INSN_ALIAS }, /* packw with rs2=x0 */
  203. +{"clzw", 64, INSN_CLASS_B_OR_ZBB, "d,s", MATCH_CLZW, MASK_CLZW, match_opcode, 0 },
  204. +{"ctzw", 64, INSN_CLASS_B_OR_ZBB, "d,s", MATCH_CTZW, MASK_CTZW, match_opcode, 0 },
  205. +{"pcntw", 64, INSN_CLASS_B_OR_ZBB, "d,s", MATCH_PCNTW, MASK_PCNTW, match_opcode, 0 },
  206. +{"roliw", 64, INSN_CLASS_B_OR_ZBB, "d,s,<", 0, (int) M_RL, match_never, INSN_MACRO }, /* roriw */
  207. +{"rolw", 64, INSN_CLASS_B_OR_ZBB, "d,s,t", MATCH_ROLW, MASK_ROLW, match_opcode, 0 },
  208. +{"rolw", 64, INSN_CLASS_B_OR_ZBB, "d,s,<", 0, (int) M_RL, match_never, INSN_MACRO }, /* roriw */
  209. +{"roriw", 64, INSN_CLASS_B_OR_ZBB, "d,s,<", MATCH_RORIW, MASK_RORIW, match_opcode, 0 },
  210. +{"rorw", 64, INSN_CLASS_B_OR_ZBB, "d,s,t", MATCH_RORW, MASK_RORW, match_opcode, 0 },
  211. +{"rorw", 64, INSN_CLASS_B_OR_ZBB, "d,s,<", MATCH_RORIW, MASK_RORIW, match_opcode, INSN_ALIAS },
  212. +{"rev8", 0, INSN_CLASS_B_OR_ZBB, "d,s", 0, (int) M_PERM, match_never, INSN_MACRO },
  213. +{"orc.b", 0, INSN_CLASS_B_OR_ZBB, "d,s", 0, (int) M_PERM, match_never, INSN_MACRO },
  214. +
  215. {"clmul", 0, INSN_CLASS_B_OR_ZBC, "d,s,t", MATCH_CLMUL, MASK_CLMUL, match_opcode, 0 },
  216. {"clmulh", 0, INSN_CLASS_B_OR_ZBC, "d,s,t", MATCH_CLMULH, MASK_CLMULH, match_opcode, 0 },
  217. {"clmulr", 0, INSN_CLASS_B_OR_ZBC, "d,s,t", MATCH_CLMULR, MASK_CLMULR, match_opcode, 0 },
  218. -{"min", 0, INSN_CLASS_B_OR_ZBB, "d,s,t", MATCH_MIN, MASK_MIN, match_opcode, 0 },
  219. -{"max", 0, INSN_CLASS_B_OR_ZBB, "d,s,t", MATCH_MAX, MASK_MAX, match_opcode, 0 },
  220. -{"minu", 0, INSN_CLASS_B_OR_ZBB, "d,s,t", MATCH_MINU, MASK_MINU, match_opcode, 0 },
  221. -{"maxu", 0, INSN_CLASS_B_OR_ZBB, "d,s,t", MATCH_MAXU, MASK_MAXU, match_opcode, 0 },
  222. -{"shfli", 0, INSN_CLASS_B_OR_ZBP, "d,s,|", MATCH_SHFLI, MASK_SHFLI, match_opcode, 0 },
  223. -{"unshfli", 0, INSN_CLASS_B_OR_ZBP, "d,s,|", MATCH_UNSHFLI, MASK_UNSHFLI, match_opcode, 0 },
  224. -{"shfl", 0, INSN_CLASS_B_OR_ZBP, "d,s,t", MATCH_SHFL, MASK_SHFL, match_opcode, 0 },
  225. -{"shfl", 0, INSN_CLASS_B_OR_ZBP, "d,s,|", MATCH_SHFLI, MASK_SHFLI, match_opcode, INSN_ALIAS },
  226. -{"unshfl", 0, INSN_CLASS_B_OR_ZBP, "d,s,t", MATCH_UNSHFL, MASK_UNSHFL, match_opcode, 0 },
  227. -{"unshfl", 0, INSN_CLASS_B_OR_ZBP, "d,s,|", MATCH_UNSHFLI, MASK_UNSHFLI, match_opcode, INSN_ALIAS },
  228. -{"xperm.n", 0, INSN_CLASS_B_OR_ZBP, "d,s,t", MATCH_XPERMN, MASK_XPERMN, match_opcode, 0 },
  229. -{"xperm.b", 0, INSN_CLASS_B_OR_ZBP, "d,s,t", MATCH_XPERMB, MASK_XPERMB, match_opcode, 0 },
  230. -{"xperm.h", 0, INSN_CLASS_B_OR_ZBP, "d,s,t", MATCH_XPERMH, MASK_XPERMH, match_opcode, 0 },
  231. -{"bdep", 0, INSN_CLASS_B_OR_ZBE, "d,s,t", MATCH_BDEP, MASK_BDEP, match_opcode, 0 },
  232. -{"bext", 0, INSN_CLASS_B_OR_ZBE, "d,s,t", MATCH_BEXT, MASK_BEXT, match_opcode, 0 },
  233. -{"zext.h", 32, INSN_CLASS_B_OR_ZBB_OR_ZBP, "d,s", MATCH_PACK, MASK_PACK | MASK_RS2, match_opcode, INSN_ALIAS },
  234. -{"zext.h", 64, INSN_CLASS_B_OR_ZBB_OR_ZBP, "d,s", MATCH_PACKW, MASK_PACKW | MASK_RS2, match_opcode, INSN_ALIAS },
  235. -{"pack", 0, INSN_CLASS_B_OR_ZBB_OR_ZBP, "d,s,t", MATCH_PACK, MASK_PACK, match_opcode, 0 },
  236. -{"packu", 0, INSN_CLASS_B_OR_ZBB_OR_ZBP, "d,s,t", MATCH_PACKU, MASK_PACKU, match_opcode, 0 },
  237. -{"packh", 0, INSN_CLASS_B_OR_ZBB_OR_ZBP, "d,s,t", MATCH_PACKH, MASK_PACKH, match_opcode, 0 },
  238. -{"bmator", 64, INSN_CLASS_B_OR_ZBM, "d,s,t", MATCH_BMATOR, MASK_BMATOR, match_opcode, 0 },
  239. -{"bmatxor", 64, INSN_CLASS_B_OR_ZBM, "d,s,t", MATCH_BMATXOR, MASK_BMATXOR, match_opcode, 0 },
  240. -{"bfp", 0, INSN_CLASS_B_OR_ZBF, "d,s,t", MATCH_BFP, MASK_BFP, match_opcode, 0 },
  241. -{"slliu.w", 64, INSN_CLASS_B_OR_ZBB, "d,s,>", MATCH_SLLIU_W, MASK_SLLIU_W, match_opcode, 0 },
  242. -{"zext.w", 64, INSN_CLASS_B_OR_ZBB_OR_ZBP, "d,s", MATCH_ADDU_W, MASK_ADDU_W | MASK_RS2, match_opcode, INSN_ALIAS },
  243. -{"addu.w", 64, INSN_CLASS_B_OR_ZBB, "d,s,t", MATCH_ADDU_W, MASK_ADDU_W, match_opcode, 0 },
  244. -{"subu.w", 64, INSN_CLASS_B_OR_ZBB, "d,s,t", MATCH_SUBU_W, MASK_SUBU_W, match_opcode, 0 },
  245. -{"sloiw", 64, INSN_CLASS_B_OR_ZBP, "d,s,<", MATCH_SLOIW, MASK_SLOIW, match_opcode, 0 },
  246. -{"sroiw", 64, INSN_CLASS_B_OR_ZBP, "d,s,<", MATCH_SROIW, MASK_SROIW, match_opcode, 0 },
  247. -{"roliw", 64, INSN_CLASS_B_OR_ZBB_OR_ZBP, "d,s,<", 0, (int) M_RL, match_never, INSN_MACRO },
  248. -{"roriw", 64, INSN_CLASS_B_OR_ZBB_OR_ZBP, "d,s,<", MATCH_RORIW, MASK_RORIW, match_opcode, 0 },
  249. -{"slow", 64, INSN_CLASS_B_OR_ZBP, "d,s,t", MATCH_SLOW, MASK_SLOW, match_opcode, 0 },
  250. -{"slow", 64, INSN_CLASS_B_OR_ZBP, "d,s,<", MATCH_SLOIW, MASK_SLOIW, match_opcode, INSN_ALIAS },
  251. -{"srow", 64, INSN_CLASS_B_OR_ZBP, "d,s,t", MATCH_SROW, MASK_SROW, match_opcode, 0 },
  252. -{"srow", 64, INSN_CLASS_B_OR_ZBP, "d,s,<", MATCH_SROIW, MASK_SROIW, match_opcode, INSN_ALIAS },
  253. -{"rolw", 64, INSN_CLASS_B_OR_ZBB_OR_ZBP, "d,s,t", MATCH_ROLW, MASK_ROLW, match_opcode, 0 },
  254. -{"rolw", 64, INSN_CLASS_B_OR_ZBB_OR_ZBP, "d,s,<", 0, (int) M_RL, match_never, INSN_MACRO },
  255. -{"rorw", 64, INSN_CLASS_B_OR_ZBB_OR_ZBP, "d,s,t", MATCH_RORW, MASK_RORW, match_opcode, 0 },
  256. -{"rorw", 64, INSN_CLASS_B_OR_ZBB_OR_ZBP, "d,s,<", MATCH_RORIW, MASK_RORIW, match_opcode, INSN_ALIAS },
  257. -{"sbclriw", 64, INSN_CLASS_B_OR_ZBS, "d,s,<", MATCH_SBCLRIW, MASK_SBCLRIW, match_opcode, 0 },
  258. +
  259. +{"sbseti", 0, INSN_CLASS_B_OR_ZBS, "d,s,>", MATCH_SBSETI, MASK_SBSETI, match_opcode, 0 },
  260. +{"sbset", 0, INSN_CLASS_B_OR_ZBS, "d,s,t", MATCH_SBSET, MASK_SBSET, match_opcode, 0 },
  261. +{"sbset", 0, INSN_CLASS_B_OR_ZBS, "d,s,>", MATCH_SBSETI, MASK_SBSETI, match_opcode, INSN_ALIAS },
  262. +{"sbclri", 0, INSN_CLASS_B_OR_ZBS, "d,s,>", MATCH_SBCLRI, MASK_SBCLRI, match_opcode, 0 },
  263. +{"sbclr", 0, INSN_CLASS_B_OR_ZBS, "d,s,t", MATCH_SBCLR, MASK_SBCLR, match_opcode, 0 },
  264. +{"sbclr", 0, INSN_CLASS_B_OR_ZBS, "d,s,>", MATCH_SBCLRI, MASK_SBCLRI, match_opcode, INSN_ALIAS },
  265. +{"sbinvi", 0, INSN_CLASS_B_OR_ZBS, "d,s,>", MATCH_SBINVI, MASK_SBINVI, match_opcode, 0 },
  266. +{"sbinv", 0, INSN_CLASS_B_OR_ZBS, "d,s,t", MATCH_SBINV, MASK_SBINV, match_opcode, 0 },
  267. +{"sbinv", 0, INSN_CLASS_B_OR_ZBS, "d,s,>", MATCH_SBINVI, MASK_SBINVI, match_opcode, INSN_ALIAS },
  268. +{"sbexti", 0, INSN_CLASS_B_OR_ZBS, "d,s,>", MATCH_SBEXTI, MASK_SBEXTI, match_opcode, 0 },
  269. +{"sbext", 0, INSN_CLASS_B_OR_ZBS, "d,s,t", MATCH_SBEXT, MASK_SBEXT, match_opcode, 0 },
  270. +{"sbext", 0, INSN_CLASS_B_OR_ZBS, "d,s,>", MATCH_SBEXTI, MASK_SBEXTI, match_opcode, INSN_ALIAS },
  271. {"sbsetiw", 64, INSN_CLASS_B_OR_ZBS, "d,s,<", MATCH_SBSETIW, MASK_SBSETIW, match_opcode, 0 },
  272. -{"sbinviw", 64, INSN_CLASS_B_OR_ZBS, "d,s,<", MATCH_SBINVIW, MASK_SBINVIW, match_opcode, 0 },
  273. -{"gorciw", 64, INSN_CLASS_B_OR_ZBP, "d,s,<", MATCH_GORCIW, MASK_GORCIW, match_opcode, 0 },
  274. -{"greviw", 64, INSN_CLASS_B_OR_ZBP, "d,s,<", MATCH_GREVIW, MASK_GREVIW, match_opcode, 0 },
  275. -{"sbclrw", 64, INSN_CLASS_B_OR_ZBS, "d,s,t", MATCH_SBCLRW, MASK_SBCLRW, match_opcode, 0 },
  276. -{"sbclrw", 64, INSN_CLASS_B_OR_ZBS, "d,s,<", MATCH_SBCLRIW, MASK_SBCLRIW, match_opcode, INSN_ALIAS },
  277. {"sbsetw", 64, INSN_CLASS_B_OR_ZBS, "d,s,t", MATCH_SBSETW, MASK_SBSETW, match_opcode, 0 },
  278. {"sbsetw", 64, INSN_CLASS_B_OR_ZBS, "d,s,<", MATCH_SBSETIW, MASK_SBSETIW, match_opcode, INSN_ALIAS },
  279. +{"sbclriw", 64, INSN_CLASS_B_OR_ZBS, "d,s,<", MATCH_SBCLRIW, MASK_SBCLRIW, match_opcode, 0 },
  280. +{"sbclrw", 64, INSN_CLASS_B_OR_ZBS, "d,s,t", MATCH_SBCLRW, MASK_SBCLRW, match_opcode, 0 },
  281. +{"sbclrw", 64, INSN_CLASS_B_OR_ZBS, "d,s,<", MATCH_SBCLRIW, MASK_SBCLRIW, match_opcode, INSN_ALIAS },
  282. +{"sbinviw", 64, INSN_CLASS_B_OR_ZBS, "d,s,<", MATCH_SBINVIW, MASK_SBINVIW, match_opcode, 0 },
  283. {"sbinvw", 64, INSN_CLASS_B_OR_ZBS, "d,s,t", MATCH_SBINVW, MASK_SBINVW, match_opcode, 0 },
  284. {"sbinvw", 64, INSN_CLASS_B_OR_ZBS, "d,s,<", MATCH_SBINVIW, MASK_SBINVIW, match_opcode, INSN_ALIAS },
  285. -{"sbextw", 64, INSN_CLASS_B_OR_ZBS, "d,s,t", MATCH_SBEXTW, MASK_SBEXTW, match_opcode, 0 },
  286. -{"gorcw", 64, INSN_CLASS_B_OR_ZBP, "d,s,t", MATCH_GORCW, MASK_GORCW, match_opcode, 0 },
  287. -{"gorcw", 64, INSN_CLASS_B_OR_ZBP, "d,s,<", MATCH_GORCIW, MASK_GORCIW, match_opcode, INSN_ALIAS },
  288. -{"grevw", 64, INSN_CLASS_B_OR_ZBP, "d,s,t", MATCH_GREVW, MASK_GREVW, match_opcode, 0 },
  289. -{"grevw", 64, INSN_CLASS_B_OR_ZBP, "d,s,<", MATCH_GREVIW, MASK_GREVIW, match_opcode, INSN_ALIAS },
  290. -{"fsliw", 64, INSN_CLASS_B_OR_ZBT, "d,s,r,<", 0, (int) M_FL, match_never, INSN_MACRO },
  291. -{"fsriw", 64, INSN_CLASS_B_OR_ZBT, "d,s,r,<", MATCH_FSRIW, MASK_FSRIW, match_opcode, 0 },
  292. -{"fslw", 64, INSN_CLASS_B_OR_ZBT, "d,s,r,t", MATCH_FSLW, MASK_FSLW, match_opcode, 0 },
  293. -{"fslw", 64, INSN_CLASS_B_OR_ZBT, "d,s,r,<", 0, (int) M_FL, match_never, INSN_MACRO },
  294. -{"fsrw", 64, INSN_CLASS_B_OR_ZBT, "d,s,r,t", MATCH_FSRW, MASK_FSRW, match_opcode, 0 },
  295. -{"fsrw", 64, INSN_CLASS_B_OR_ZBT, "d,s,r,<", MATCH_FSRIW, MASK_FSRIW, match_opcode, INSN_ALIAS },
  296. -{"clzw", 64, INSN_CLASS_B_OR_ZBB, "d,s", MATCH_CLZW, MASK_CLZW, match_opcode, 0 },
  297. -{"ctzw", 64, INSN_CLASS_B_OR_ZBB, "d,s", MATCH_CTZW, MASK_CTZW, match_opcode, 0 },
  298. -{"pcntw", 64, INSN_CLASS_B_OR_ZBB, "d,s", MATCH_PCNTW, MASK_PCNTW, match_opcode, 0 },
  299. -{"sh1addu.w",64, INSN_CLASS_B_OR_ZBA, "d,s,t", MATCH_SH1ADDU_W, MASK_SH1ADDU_W, match_opcode, 0 },
  300. -{"sh2addu.w",64, INSN_CLASS_B_OR_ZBA, "d,s,t", MATCH_SH2ADDU_W, MASK_SH2ADDU_W, match_opcode, 0 },
  301. -{"sh3addu.w",64, INSN_CLASS_B_OR_ZBA, "d,s,t", MATCH_SH3ADDU_W, MASK_SH3ADDU_W, match_opcode, 0 },
  302. -{"shflw", 64, INSN_CLASS_B_OR_ZBP, "d,s,t", MATCH_SHFLW, MASK_SHFLW, match_opcode, 0 },
  303. -{"unshflw", 64, INSN_CLASS_B_OR_ZBP, "d,s,t", MATCH_UNSHFLW, MASK_UNSHFLW, match_opcode, 0 },
  304. -{"xperm.w", 64, INSN_CLASS_B_OR_ZBP, "d,s,t", MATCH_XPERMW, MASK_XPERMW, match_opcode, 0 },
  305. -{"bdepw", 64, INSN_CLASS_B_OR_ZBE, "d,s,t", MATCH_BDEPW, MASK_BDEPW, match_opcode, 0 },
  306. -{"bextw", 64, INSN_CLASS_B_OR_ZBE, "d,s,t", MATCH_BEXTW, MASK_BEXTW, match_opcode, 0 },
  307. -{"packw", 64, INSN_CLASS_B_OR_ZBB_OR_ZBP, "d,s,t", MATCH_PACKW, MASK_PACKW, match_opcode, 0 },
  308. -{"packuw", 64, INSN_CLASS_B_OR_ZBB_OR_ZBP, "d,s,t", MATCH_PACKUW, MASK_PACKUW, match_opcode, 0 },
  309. -{"bfpw", 64, INSN_CLASS_B_OR_ZBF, "d,s,t", MATCH_BFPW, MASK_BFPW, match_opcode, 0 },
  310. -
  311. -/* Bitmanip pseudo-instructions */
  312. -{"rev.p", 0, INSN_CLASS_B_OR_ZBB_OR_ZBP, "d,s", 0, (int) M_PERM, match_never, INSN_MACRO },
  313. -{"rev2.n", 0, INSN_CLASS_B_OR_ZBB_OR_ZBP, "d,s", 0, (int) M_PERM, match_never, INSN_MACRO },
  314. -{"rev.n", 0, INSN_CLASS_B_OR_ZBB_OR_ZBP, "d,s", 0, (int) M_PERM, match_never, INSN_MACRO },
  315. -{"rev4.b", 0, INSN_CLASS_B_OR_ZBB_OR_ZBP, "d,s", 0, (int) M_PERM, match_never, INSN_MACRO },
  316. -{"rev2.b", 0, INSN_CLASS_B_OR_ZBB_OR_ZBP, "d,s", 0, (int) M_PERM, match_never, INSN_MACRO },
  317. -{"rev.b", 0, INSN_CLASS_B_OR_ZBB_OR_ZBP, "d,s", 0, (int) M_PERM, match_never, INSN_MACRO },
  318. -{"rev8.h", 0, INSN_CLASS_B_OR_ZBB_OR_ZBP, "d,s", 0, (int) M_PERM, match_never, INSN_MACRO },
  319. -{"rev4.h", 0, INSN_CLASS_B_OR_ZBB_OR_ZBP, "d,s", 0, (int) M_PERM, match_never, INSN_MACRO },
  320. -{"rev2.h", 0, INSN_CLASS_B_OR_ZBB_OR_ZBP, "d,s", 0, (int) M_PERM, match_never, INSN_MACRO },
  321. -{"rev.h", 0, INSN_CLASS_B_OR_ZBB_OR_ZBP, "d,s", 0, (int) M_PERM, match_never, INSN_MACRO },
  322. -{"rev16.w", 64, INSN_CLASS_B_OR_ZBB_OR_ZBP, "d,s", 0, (int) M_PERM, match_never, INSN_MACRO },
  323. -{"rev8.w", 64, INSN_CLASS_B_OR_ZBB_OR_ZBP, "d,s", 0, (int) M_PERM, match_never, INSN_MACRO },
  324. -{"rev4.w", 64, INSN_CLASS_B_OR_ZBB_OR_ZBP, "d,s", 0, (int) M_PERM, match_never, INSN_MACRO },
  325. -{"rev2.w", 64, INSN_CLASS_B_OR_ZBB_OR_ZBP, "d,s", 0, (int) M_PERM, match_never, INSN_MACRO },
  326. -{"rev.w", 64, INSN_CLASS_B_OR_ZBB_OR_ZBP, "d,s", 0, (int) M_PERM, match_never, INSN_MACRO },
  327. -{"rev32", 64, INSN_CLASS_B_OR_ZBB_OR_ZBP, "d,s", 0, (int) M_PERM, match_never, INSN_MACRO },
  328. -{"rev16", 0, INSN_CLASS_B_OR_ZBB_OR_ZBP, "d,s", 0, (int) M_PERM, match_never, INSN_MACRO },
  329. -{"rev8", 0, INSN_CLASS_B_OR_ZBB_OR_ZBP, "d,s", 0, (int) M_PERM, match_never, INSN_MACRO },
  330. -{"rev4", 0, INSN_CLASS_B_OR_ZBB_OR_ZBP, "d,s", 0, (int) M_PERM, match_never, INSN_MACRO },
  331. -{"rev2", 0, INSN_CLASS_B_OR_ZBB_OR_ZBP, "d,s", 0, (int) M_PERM, match_never, INSN_MACRO },
  332. -{"rev", 0, INSN_CLASS_B_OR_ZBB_OR_ZBP, "d,s", 0, (int) M_PERM, match_never, INSN_MACRO },
  333. -
  334. -{"orc.p", 0, INSN_CLASS_B_OR_ZBB_OR_ZBP, "d,s", 0, (int) M_PERM, match_never, INSN_MACRO },
  335. -{"orc2.n", 0, INSN_CLASS_B_OR_ZBB_OR_ZBP, "d,s", 0, (int) M_PERM, match_never, INSN_MACRO },
  336. -{"orc.n", 0, INSN_CLASS_B_OR_ZBB_OR_ZBP, "d,s", 0, (int) M_PERM, match_never, INSN_MACRO },
  337. -{"orc4.b", 0, INSN_CLASS_B_OR_ZBB_OR_ZBP, "d,s", 0, (int) M_PERM, match_never, INSN_MACRO },
  338. -{"orc2.b", 0, INSN_CLASS_B_OR_ZBB_OR_ZBP, "d,s", 0, (int) M_PERM, match_never, INSN_MACRO },
  339. -{"orc.b", 0, INSN_CLASS_B_OR_ZBB_OR_ZBP, "d,s", 0, (int) M_PERM, match_never, INSN_MACRO },
  340. -{"orc8.h", 0, INSN_CLASS_B_OR_ZBB_OR_ZBP, "d,s", 0, (int) M_PERM, match_never, INSN_MACRO },
  341. -{"orc4.h", 0, INSN_CLASS_B_OR_ZBB_OR_ZBP, "d,s", 0, (int) M_PERM, match_never, INSN_MACRO },
  342. -{"orc2.h", 0, INSN_CLASS_B_OR_ZBB_OR_ZBP, "d,s", 0, (int) M_PERM, match_never, INSN_MACRO },
  343. -{"orc.h", 0, INSN_CLASS_B_OR_ZBB_OR_ZBP, "d,s", 0, (int) M_PERM, match_never, INSN_MACRO },
  344. -{"orc16.w", 64, INSN_CLASS_B_OR_ZBB_OR_ZBP, "d,s", 0, (int) M_PERM, match_never, INSN_MACRO },
  345. -{"orc8.w", 64, INSN_CLASS_B_OR_ZBB_OR_ZBP, "d,s", 0, (int) M_PERM, match_never, INSN_MACRO },
  346. -{"orc4.w", 64, INSN_CLASS_B_OR_ZBB_OR_ZBP, "d,s", 0, (int) M_PERM, match_never, INSN_MACRO },
  347. -{"orc2.w", 64, INSN_CLASS_B_OR_ZBB_OR_ZBP, "d,s", 0, (int) M_PERM, match_never, INSN_MACRO },
  348. -{"orc.w", 64, INSN_CLASS_B_OR_ZBB_OR_ZBP, "d,s", 0, (int) M_PERM, match_never, INSN_MACRO },
  349. -{"orc32", 64, INSN_CLASS_B_OR_ZBB_OR_ZBP, "d,s", 0, (int) M_PERM, match_never, INSN_MACRO },
  350. -{"orc16", 0, INSN_CLASS_B_OR_ZBB_OR_ZBP, "d,s", 0, (int) M_PERM, match_never, INSN_MACRO },
  351. -{"orc8", 0, INSN_CLASS_B_OR_ZBB_OR_ZBP, "d,s", 0, (int) M_PERM, match_never, INSN_MACRO },
  352. -{"orc4", 0, INSN_CLASS_B_OR_ZBB_OR_ZBP, "d,s", 0, (int) M_PERM, match_never, INSN_MACRO },
  353. -{"orc2", 0, INSN_CLASS_B_OR_ZBB_OR_ZBP, "d,s", 0, (int) M_PERM, match_never, INSN_MACRO },
  354. -{"orc", 0, INSN_CLASS_B_OR_ZBB_OR_ZBP, "d,s", 0, (int) M_PERM, match_never, INSN_MACRO },
  355. -
  356. -{"zip.n", 0, INSN_CLASS_B_OR_ZBP, "d,s", 0, (int) M_PERM, match_never, INSN_MACRO },
  357. -{"zip2.b", 0, INSN_CLASS_B_OR_ZBP, "d,s", 0, (int) M_PERM, match_never, INSN_MACRO },
  358. -{"zip.b", 0, INSN_CLASS_B_OR_ZBP, "d,s", 0, (int) M_PERM, match_never, INSN_MACRO },
  359. -{"zip4.h", 0, INSN_CLASS_B_OR_ZBP, "d,s", 0, (int) M_PERM, match_never, INSN_MACRO },
  360. -{"zip2.h", 0, INSN_CLASS_B_OR_ZBP, "d,s", 0, (int) M_PERM, match_never, INSN_MACRO },
  361. -{"zip.h", 0, INSN_CLASS_B_OR_ZBP, "d,s", 0, (int) M_PERM, match_never, INSN_MACRO },
  362. -{"zip8.w", 64, INSN_CLASS_B_OR_ZBP, "d,s", 0, (int) M_PERM, match_never, INSN_MACRO },
  363. -{"zip4.w", 64, INSN_CLASS_B_OR_ZBP, "d,s", 0, (int) M_PERM, match_never, INSN_MACRO },
  364. -{"zip2.w", 64, INSN_CLASS_B_OR_ZBP, "d,s", 0, (int) M_PERM, match_never, INSN_MACRO },
  365. -{"zip.w", 64, INSN_CLASS_B_OR_ZBP, "d,s", 0, (int) M_PERM, match_never, INSN_MACRO },
  366. -{"zip16", 64, INSN_CLASS_B_OR_ZBP, "d,s", 0, (int) M_PERM, match_never, INSN_MACRO },
  367. -{"zip8", 0, INSN_CLASS_B_OR_ZBP, "d,s", 0, (int) M_PERM, match_never, INSN_MACRO },
  368. -{"zip4", 0, INSN_CLASS_B_OR_ZBP, "d,s", 0, (int) M_PERM, match_never, INSN_MACRO },
  369. -{"zip2", 0, INSN_CLASS_B_OR_ZBP, "d,s", 0, (int) M_PERM, match_never, INSN_MACRO },
  370. -{"zip", 0, INSN_CLASS_B_OR_ZBP, "d,s", 0, (int) M_PERM, match_never, INSN_MACRO },
  371. -
  372. -{"unzip.n", 0, INSN_CLASS_B_OR_ZBP, "d,s", 0, (int) M_PERM, match_never, INSN_MACRO },
  373. -{"unzip2.b", 0, INSN_CLASS_B_OR_ZBP, "d,s", 0, (int) M_PERM, match_never, INSN_MACRO },
  374. -{"unzip.b", 0, INSN_CLASS_B_OR_ZBP, "d,s", 0, (int) M_PERM, match_never, INSN_MACRO },
  375. -{"unzip4.h", 0, INSN_CLASS_B_OR_ZBP, "d,s", 0, (int) M_PERM, match_never, INSN_MACRO },
  376. -{"unzip2.h", 0, INSN_CLASS_B_OR_ZBP, "d,s", 0, (int) M_PERM, match_never, INSN_MACRO },
  377. -{"unzip.h", 0, INSN_CLASS_B_OR_ZBP, "d,s", 0, (int) M_PERM, match_never, INSN_MACRO },
  378. -{"unzip8.w", 64, INSN_CLASS_B_OR_ZBP, "d,s", 0, (int) M_PERM, match_never, INSN_MACRO },
  379. -{"unzip4.w", 64, INSN_CLASS_B_OR_ZBP, "d,s", 0, (int) M_PERM, match_never, INSN_MACRO },
  380. -{"unzip2.w", 64, INSN_CLASS_B_OR_ZBP, "d,s", 0, (int) M_PERM, match_never, INSN_MACRO },
  381. -{"unzip.w", 64, INSN_CLASS_B_OR_ZBP, "d,s", 0, (int) M_PERM, match_never, INSN_MACRO },
  382. -{"unzip16", 64, INSN_CLASS_B_OR_ZBP, "d,s", 0, (int) M_PERM, match_never, INSN_MACRO },
  383. -{"unzip8", 0, INSN_CLASS_B_OR_ZBP, "d,s", 0, (int) M_PERM, match_never, INSN_MACRO },
  384. -{"unzip4", 0, INSN_CLASS_B_OR_ZBP, "d,s", 0, (int) M_PERM, match_never, INSN_MACRO },
  385. -{"unzip2", 0, INSN_CLASS_B_OR_ZBP, "d,s", 0, (int) M_PERM, match_never, INSN_MACRO },
  386. -{"unzip", 0, INSN_CLASS_B_OR_ZBP, "d,s", 0, (int) M_PERM, match_never, INSN_MACRO },
  387. +{"sbextw", 64, INSN_CLASS_B_OR_ZBS, "d,s,t", MATCH_SBEXTW, MASK_SBEXTW, match_opcode, 0 }, /* No sbextiw */
  388. +
  389. +/* Bitmanip instruction subset - unsure */
  390. +{"sloi", 0, INSN_CLASS_B, "d,s,>", MATCH_SLOI, MASK_SLOI, match_opcode, 0 },
  391. +{"sroi", 0, INSN_CLASS_B, "d,s,>", MATCH_SROI, MASK_SROI, match_opcode, 0 },
  392. +{"slo", 0, INSN_CLASS_B, "d,s,t", MATCH_SLO, MASK_SLO, match_opcode, 0 },
  393. +{"slo", 0, INSN_CLASS_B, "d,s,>", MATCH_SLOI, MASK_SLOI, match_opcode, INSN_ALIAS },
  394. +{"sro", 0, INSN_CLASS_B, "d,s,t", MATCH_SRO, MASK_SRO, match_opcode, 0 },
  395. +{"sro", 0, INSN_CLASS_B, "d,s,>", MATCH_SROI, MASK_SROI, match_opcode, INSN_ALIAS },
  396. +{"gorci", 0, INSN_CLASS_B, "d,s,>", MATCH_GORCI, MASK_GORCI, match_opcode, 0 },
  397. +{"grevi", 0, INSN_CLASS_B, "d,s,>", MATCH_GREVI, MASK_GREVI, match_opcode, 0 },
  398. +{"gorc", 0, INSN_CLASS_B, "d,s,t", MATCH_GORC, MASK_GORC, match_opcode, 0 },
  399. +{"gorc", 0, INSN_CLASS_B, "d,s,>", MATCH_GORCI, MASK_GORCI, match_opcode, INSN_ALIAS },
  400. +{"grev", 0, INSN_CLASS_B, "d,s,t", MATCH_GREV, MASK_GREV, match_opcode, 0 },
  401. +{"grev", 0, INSN_CLASS_B, "d,s,>", MATCH_GREVI, MASK_GREVI, match_opcode, INSN_ALIAS },
  402. +{"bmatflip", 64, INSN_CLASS_B, "d,s", MATCH_BMATFLIP, MASK_BMATFLIP, match_opcode, 0 },
  403. +{"shfli", 0, INSN_CLASS_B, "d,s,|", MATCH_SHFLI, MASK_SHFLI, match_opcode, 0 },
  404. +{"unshfli", 0, INSN_CLASS_B, "d,s,|", MATCH_UNSHFLI, MASK_UNSHFLI, match_opcode, 0 },
  405. +{"shfl", 0, INSN_CLASS_B, "d,s,t", MATCH_SHFL, MASK_SHFL, match_opcode, 0 },
  406. +{"shfl", 0, INSN_CLASS_B, "d,s,|", MATCH_SHFLI, MASK_SHFLI, match_opcode, INSN_ALIAS },
  407. +{"unshfl", 0, INSN_CLASS_B, "d,s,t", MATCH_UNSHFL, MASK_UNSHFL, match_opcode, 0 },
  408. +{"unshfl", 0, INSN_CLASS_B, "d,s,|", MATCH_UNSHFLI, MASK_UNSHFLI, match_opcode, INSN_ALIAS },
  409. +{"xperm.n", 0, INSN_CLASS_B, "d,s,t", MATCH_XPERMN, MASK_XPERMN, match_opcode, 0 },
  410. +{"xperm.b", 0, INSN_CLASS_B, "d,s,t", MATCH_XPERMB, MASK_XPERMB, match_opcode, 0 },
  411. +{"xperm.h", 0, INSN_CLASS_B, "d,s,t", MATCH_XPERMH, MASK_XPERMH, match_opcode, 0 },
  412. +{"bdep", 0, INSN_CLASS_B, "d,s,t", MATCH_BDEP, MASK_BDEP, match_opcode, 0 },
  413. +{"bext", 0, INSN_CLASS_B, "d,s,t", MATCH_BEXT, MASK_BEXT, match_opcode, 0 },
  414. +{"pack", 0, INSN_CLASS_B, "d,s,t", MATCH_PACK, MASK_PACK, match_opcode, 0 },
  415. +{"packu", 0, INSN_CLASS_B, "d,s,t", MATCH_PACKU, MASK_PACKU, match_opcode, 0 },
  416. +{"packh", 0, INSN_CLASS_B, "d,s,t", MATCH_PACKH, MASK_PACKH, match_opcode, 0 },
  417. +{"bmator", 64, INSN_CLASS_B, "d,s,t", MATCH_BMATOR, MASK_BMATOR, match_opcode, 0 },
  418. +{"bmatxor", 64, INSN_CLASS_B, "d,s,t", MATCH_BMATXOR, MASK_BMATXOR, match_opcode, 0 },
  419. +{"bfp", 0, INSN_CLASS_B, "d,s,t", MATCH_BFP, MASK_BFP, match_opcode, 0 },
  420. +{"subu.w", 64, INSN_CLASS_B, "d,s,t", MATCH_SUBU_W, MASK_SUBU_W, match_opcode, 0 },
  421. +{"sloiw", 64, INSN_CLASS_B, "d,s,<", MATCH_SLOIW, MASK_SLOIW, match_opcode, 0 },
  422. +{"sroiw", 64, INSN_CLASS_B, "d,s,<", MATCH_SROIW, MASK_SROIW, match_opcode, 0 },
  423. +{"slow", 64, INSN_CLASS_B, "d,s,t", MATCH_SLOW, MASK_SLOW, match_opcode, 0 },
  424. +{"slow", 64, INSN_CLASS_B, "d,s,<", MATCH_SLOIW, MASK_SLOIW, match_opcode, INSN_ALIAS },
  425. +{"srow", 64, INSN_CLASS_B, "d,s,t", MATCH_SROW, MASK_SROW, match_opcode, 0 },
  426. +{"srow", 64, INSN_CLASS_B, "d,s,<", MATCH_SROIW, MASK_SROIW, match_opcode, INSN_ALIAS },
  427. +{"gorciw", 64, INSN_CLASS_B, "d,s,<", MATCH_GORCIW, MASK_GORCIW, match_opcode, 0 },
  428. +{"greviw", 64, INSN_CLASS_B, "d,s,<", MATCH_GREVIW, MASK_GREVIW, match_opcode, 0 },
  429. +{"gorcw", 64, INSN_CLASS_B, "d,s,t", MATCH_GORCW, MASK_GORCW, match_opcode, 0 },
  430. +{"gorcw", 64, INSN_CLASS_B, "d,s,<", MATCH_GORCIW, MASK_GORCIW, match_opcode, INSN_ALIAS },
  431. +{"grevw", 64, INSN_CLASS_B, "d,s,t", MATCH_GREVW, MASK_GREVW, match_opcode, 0 },
  432. +{"grevw", 64, INSN_CLASS_B, "d,s,<", MATCH_GREVIW, MASK_GREVIW, match_opcode, INSN_ALIAS },
  433. +{"shflw", 64, INSN_CLASS_B, "d,s,t", MATCH_SHFLW, MASK_SHFLW, match_opcode, 0 },
  434. +{"unshflw", 64, INSN_CLASS_B, "d,s,t", MATCH_UNSHFLW, MASK_UNSHFLW, match_opcode, 0 },
  435. +{"xperm.w", 64, INSN_CLASS_B, "d,s,t", MATCH_XPERMW, MASK_XPERMW, match_opcode, 0 },
  436. +{"bdepw", 64, INSN_CLASS_B, "d,s,t", MATCH_BDEPW, MASK_BDEPW, match_opcode, 0 },
  437. +{"bextw", 64, INSN_CLASS_B, "d,s,t", MATCH_BEXTW, MASK_BEXTW, match_opcode, 0 },
  438. +{"packw", 64, INSN_CLASS_B, "d,s,t", MATCH_PACKW, MASK_PACKW, match_opcode, 0 },
  439. +{"packuw", 64, INSN_CLASS_B, "d,s,t", MATCH_PACKUW, MASK_PACKUW, match_opcode, 0 },
  440. +{"bfpw", 64, INSN_CLASS_B, "d,s,t", MATCH_BFPW, MASK_BFPW, match_opcode, 0 },
  441. +
  442. +{"cmix", 0, INSN_CLASS_ZBT, "d,t,s,r", MATCH_CMIX, MASK_CMIX, match_opcode, 0 },
  443. +{"cmov", 0, INSN_CLASS_ZBT, "d,t,s,r", MATCH_CMOV, MASK_CMOV, match_opcode, 0 },
  444. +{"fsli", 0, INSN_CLASS_ZBT, "d,s,r,>", 0, (int) M_FL, match_never, INSN_MACRO }, /* fsri */
  445. +{"fsl", 0, INSN_CLASS_ZBT, "d,s,r,t", MATCH_FSL, MASK_FSL, match_opcode, 0 },
  446. +{"fsl", 0, INSN_CLASS_ZBT, "d,s,r,>", 0, (int) M_FL, match_never, INSN_MACRO }, /* fsri */
  447. +{"fsri", 0, INSN_CLASS_ZBT, "d,s,r,>", MATCH_FSRI, MASK_FSRI, match_opcode, 0 },
  448. +{"fsr", 0, INSN_CLASS_ZBT, "d,s,r,t", MATCH_FSR, MASK_FSR, match_opcode, 0 },
  449. +{"fsr", 0, INSN_CLASS_ZBT, "d,s,r,>", MATCH_FSRI, MASK_FSRI, match_opcode, INSN_ALIAS },
  450. +{"fsliw", 64, INSN_CLASS_ZBT, "d,s,r,<", 0, (int) M_FL, match_never, INSN_MACRO }, /* fsriw */
  451. +{"fslw", 64, INSN_CLASS_ZBT, "d,s,r,t", MATCH_FSLW, MASK_FSLW, match_opcode, 0 },
  452. +{"fslw", 64, INSN_CLASS_ZBT, "d,s,r,<", 0, (int) M_FL, match_never, INSN_MACRO }, /* fsriw */
  453. +{"fsriw", 64, INSN_CLASS_ZBT, "d,s,r,<", MATCH_FSRIW, MASK_FSRIW, match_opcode, 0 },
  454. +{"fsrw", 64, INSN_CLASS_ZBT, "d,s,r,t", MATCH_FSRW, MASK_FSRW, match_opcode, 0 },
  455. +{"fsrw", 64, INSN_CLASS_ZBT, "d,s,r,<", MATCH_FSRIW, MASK_FSRIW, match_opcode, INSN_ALIAS },
  456. +
  457. +{"crc32.b", 0, INSN_CLASS_ZBR, "d,s", MATCH_CRC32_B, MASK_CRC32_B, match_opcode, 0 },
  458. +{"crc32.h", 0, INSN_CLASS_ZBR, "d,s", MATCH_CRC32_H, MASK_CRC32_H, match_opcode, 0 },
  459. +{"crc32.w", 0, INSN_CLASS_ZBR, "d,s", MATCH_CRC32_W, MASK_CRC32_W, match_opcode, 0 },
  460. +{"crc32c.b", 0, INSN_CLASS_ZBR, "d,s", MATCH_CRC32C_B, MASK_CRC32C_B, match_opcode, 0 },
  461. +{"crc32c.h", 0, INSN_CLASS_ZBR, "d,s", MATCH_CRC32C_H, MASK_CRC32C_H, match_opcode, 0 },
  462. +{"crc32c.w", 0, INSN_CLASS_ZBR, "d,s", MATCH_CRC32C_W, MASK_CRC32C_W, match_opcode, 0 },
  463. +{"crc32.d", 64, INSN_CLASS_ZBR, "d,s", MATCH_CRC32_D, MASK_CRC32_D, match_opcode, 0 },
  464. +{"crc32c.d", 64, INSN_CLASS_ZBR, "d,s", MATCH_CRC32C_D, MASK_CRC32C_D, match_opcode, 0 },
  465. +
  466. +/* Bitmanip pseudo-instructions */
  467. +{"rev.p", 0, INSN_CLASS_B, "d,s", 0, (int) M_PERM, match_never, INSN_MACRO },
  468. +{"rev2.n", 0, INSN_CLASS_B, "d,s", 0, (int) M_PERM, match_never, INSN_MACRO },
  469. +{"rev.n", 0, INSN_CLASS_B, "d,s", 0, (int) M_PERM, match_never, INSN_MACRO },
  470. +{"rev4.b", 0, INSN_CLASS_B, "d,s", 0, (int) M_PERM, match_never, INSN_MACRO },
  471. +{"rev2.b", 0, INSN_CLASS_B, "d,s", 0, (int) M_PERM, match_never, INSN_MACRO },
  472. +{"rev.b", 0, INSN_CLASS_B, "d,s", 0, (int) M_PERM, match_never, INSN_MACRO },
  473. +{"rev8.h", 0, INSN_CLASS_B, "d,s", 0, (int) M_PERM, match_never, INSN_MACRO },
  474. +{"rev4.h", 0, INSN_CLASS_B, "d,s", 0, (int) M_PERM, match_never, INSN_MACRO },
  475. +{"rev2.h", 0, INSN_CLASS_B, "d,s", 0, (int) M_PERM, match_never, INSN_MACRO },
  476. +{"rev.h", 0, INSN_CLASS_B, "d,s", 0, (int) M_PERM, match_never, INSN_MACRO },
  477. +{"rev16.w", 64, INSN_CLASS_B, "d,s", 0, (int) M_PERM, match_never, INSN_MACRO },
  478. +{"rev8.w", 64, INSN_CLASS_B, "d,s", 0, (int) M_PERM, match_never, INSN_MACRO },
  479. +{"rev4.w", 64, INSN_CLASS_B, "d,s", 0, (int) M_PERM, match_never, INSN_MACRO },
  480. +{"rev2.w", 64, INSN_CLASS_B, "d,s", 0, (int) M_PERM, match_never, INSN_MACRO },
  481. +{"rev.w", 64, INSN_CLASS_B, "d,s", 0, (int) M_PERM, match_never, INSN_MACRO },
  482. +{"rev32", 64, INSN_CLASS_B, "d,s", 0, (int) M_PERM, match_never, INSN_MACRO },
  483. +{"rev16", 0, INSN_CLASS_B, "d,s", 0, (int) M_PERM, match_never, INSN_MACRO },
  484. +{"rev4", 0, INSN_CLASS_B, "d,s", 0, (int) M_PERM, match_never, INSN_MACRO },
  485. +{"rev2", 0, INSN_CLASS_B, "d,s", 0, (int) M_PERM, match_never, INSN_MACRO },
  486. +{"rev", 0, INSN_CLASS_B, "d,s", 0, (int) M_PERM, match_never, INSN_MACRO },
  487. +
  488. +{"orc.p", 0, INSN_CLASS_B, "d,s", 0, (int) M_PERM, match_never, INSN_MACRO },
  489. +{"orc2.n", 0, INSN_CLASS_B, "d,s", 0, (int) M_PERM, match_never, INSN_MACRO },
  490. +{"orc.n", 0, INSN_CLASS_B, "d,s", 0, (int) M_PERM, match_never, INSN_MACRO },
  491. +{"orc4.b", 0, INSN_CLASS_B, "d,s", 0, (int) M_PERM, match_never, INSN_MACRO },
  492. +{"orc2.b", 0, INSN_CLASS_B, "d,s", 0, (int) M_PERM, match_never, INSN_MACRO },
  493. +{"orc8.h", 0, INSN_CLASS_B, "d,s", 0, (int) M_PERM, match_never, INSN_MACRO },
  494. +{"orc4.h", 0, INSN_CLASS_B, "d,s", 0, (int) M_PERM, match_never, INSN_MACRO },
  495. +{"orc2.h", 0, INSN_CLASS_B, "d,s", 0, (int) M_PERM, match_never, INSN_MACRO },
  496. +{"orc.h", 0, INSN_CLASS_B, "d,s", 0, (int) M_PERM, match_never, INSN_MACRO },
  497. +{"orc16.w", 64, INSN_CLASS_B, "d,s", 0, (int) M_PERM, match_never, INSN_MACRO },
  498. +{"orc8.w", 64, INSN_CLASS_B, "d,s", 0, (int) M_PERM, match_never, INSN_MACRO },
  499. +{"orc4.w", 64, INSN_CLASS_B, "d,s", 0, (int) M_PERM, match_never, INSN_MACRO },
  500. +{"orc2.w", 64, INSN_CLASS_B, "d,s", 0, (int) M_PERM, match_never, INSN_MACRO },
  501. +{"orc.w", 64, INSN_CLASS_B, "d,s", 0, (int) M_PERM, match_never, INSN_MACRO },
  502. +{"orc32", 64, INSN_CLASS_B, "d,s", 0, (int) M_PERM, match_never, INSN_MACRO },
  503. +{"orc16", 0, INSN_CLASS_B, "d,s", 0, (int) M_PERM, match_never, INSN_MACRO },
  504. +{"orc8", 0, INSN_CLASS_B, "d,s", 0, (int) M_PERM, match_never, INSN_MACRO },
  505. +{"orc4", 0, INSN_CLASS_B, "d,s", 0, (int) M_PERM, match_never, INSN_MACRO },
  506. +{"orc2", 0, INSN_CLASS_B, "d,s", 0, (int) M_PERM, match_never, INSN_MACRO },
  507. +{"orc", 0, INSN_CLASS_B, "d,s", 0, (int) M_PERM, match_never, INSN_MACRO },
  508. +
  509. +{"zip.n", 0, INSN_CLASS_B, "d,s", 0, (int) M_PERM, match_never, INSN_MACRO },
  510. +{"zip2.b", 0, INSN_CLASS_B, "d,s", 0, (int) M_PERM, match_never, INSN_MACRO },
  511. +{"zip.b", 0, INSN_CLASS_B, "d,s", 0, (int) M_PERM, match_never, INSN_MACRO },
  512. +{"zip4.h", 0, INSN_CLASS_B, "d,s", 0, (int) M_PERM, match_never, INSN_MACRO },
  513. +{"zip2.h", 0, INSN_CLASS_B, "d,s", 0, (int) M_PERM, match_never, INSN_MACRO },
  514. +{"zip.h", 0, INSN_CLASS_B, "d,s", 0, (int) M_PERM, match_never, INSN_MACRO },
  515. +{"zip8.w", 64, INSN_CLASS_B, "d,s", 0, (int) M_PERM, match_never, INSN_MACRO },
  516. +{"zip4.w", 64, INSN_CLASS_B, "d,s", 0, (int) M_PERM, match_never, INSN_MACRO },
  517. +{"zip2.w", 64, INSN_CLASS_B, "d,s", 0, (int) M_PERM, match_never, INSN_MACRO },
  518. +{"zip.w", 64, INSN_CLASS_B, "d,s", 0, (int) M_PERM, match_never, INSN_MACRO },
  519. +{"zip16", 64, INSN_CLASS_B, "d,s", 0, (int) M_PERM, match_never, INSN_MACRO },
  520. +{"zip8", 0, INSN_CLASS_B, "d,s", 0, (int) M_PERM, match_never, INSN_MACRO },
  521. +{"zip4", 0, INSN_CLASS_B, "d,s", 0, (int) M_PERM, match_never, INSN_MACRO },
  522. +{"zip2", 0, INSN_CLASS_B, "d,s", 0, (int) M_PERM, match_never, INSN_MACRO },
  523. +{"zip", 0, INSN_CLASS_B, "d,s", 0, (int) M_PERM, match_never, INSN_MACRO },
  524. +
  525. +{"unzip.n", 0, INSN_CLASS_B, "d,s", 0, (int) M_PERM, match_never, INSN_MACRO },
  526. +{"unzip2.b", 0, INSN_CLASS_B, "d,s", 0, (int) M_PERM, match_never, INSN_MACRO },
  527. +{"unzip.b", 0, INSN_CLASS_B, "d,s", 0, (int) M_PERM, match_never, INSN_MACRO },
  528. +{"unzip4.h", 0, INSN_CLASS_B, "d,s", 0, (int) M_PERM, match_never, INSN_MACRO },
  529. +{"unzip2.h", 0, INSN_CLASS_B, "d,s", 0, (int) M_PERM, match_never, INSN_MACRO },
  530. +{"unzip.h", 0, INSN_CLASS_B, "d,s", 0, (int) M_PERM, match_never, INSN_MACRO },
  531. +{"unzip8.w", 64, INSN_CLASS_B, "d,s", 0, (int) M_PERM, match_never, INSN_MACRO },
  532. +{"unzip4.w", 64, INSN_CLASS_B, "d,s", 0, (int) M_PERM, match_never, INSN_MACRO },
  533. +{"unzip2.w", 64, INSN_CLASS_B, "d,s", 0, (int) M_PERM, match_never, INSN_MACRO },
  534. +{"unzip.w", 64, INSN_CLASS_B, "d,s", 0, (int) M_PERM, match_never, INSN_MACRO },
  535. +{"unzip16", 64, INSN_CLASS_B, "d,s", 0, (int) M_PERM, match_never, INSN_MACRO },
  536. +{"unzip8", 0, INSN_CLASS_B, "d,s", 0, (int) M_PERM, match_never, INSN_MACRO },
  537. +{"unzip4", 0, INSN_CLASS_B, "d,s", 0, (int) M_PERM, match_never, INSN_MACRO },
  538. +{"unzip2", 0, INSN_CLASS_B, "d,s", 0, (int) M_PERM, match_never, INSN_MACRO },
  539. +{"unzip", 0, INSN_CLASS_B, "d,s", 0, (int) M_PERM, match_never, INSN_MACRO },
  540. /* Single-precision floating-point instruction subset */
  541. {"frcsr", 0, INSN_CLASS_F, "d", MATCH_FRCSR, MASK_FRCSR, match_opcode, INSN_ALIAS },
  542. --
  543. 2.33.0