0018-Added-element-width-hint-to-whole-register-loads-sto.patch 16 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233234235236237238239240241242243244245246247248249250251252253254255256257258259260261262263264265266267268269270271272273274275276277278279280281282283284285286287288289290291292293294295296297298299300301302303304305306307308309310311312313314315316317318319320321322323324325326327328329330331332333334335336337338339340341342343344345346347348349350351352353354355356357358359360361362363364365366367368369370371372373374375376377
  1. From 33636301c48d21eaf665355c124af357ef5777c2 Mon Sep 17 00:00:00 2001
  2. From: Nelson Chu <nelson.chu@sifive.com>
  3. Date: Mon, 6 Jul 2020 22:34:19 +0800
  4. Subject: [PATCH 18/48] Added element width hint to whole register
  5. loads/stores.
  6. Add load instructions which have an EEW encoded in the `mew` and `width`.
  7. ---
  8. gas/testsuite/gas/riscv/vector-insns.d | 64 +++++++++++++++++
  9. gas/testsuite/gas/riscv/vector-insns.s | 67 ++++++++++++++++++
  10. include/opcode/riscv-opc.h | 98 +++++++++++++++++++++-----
  11. opcodes/riscv-opc.c | 43 +++++++++--
  12. 4 files changed, 249 insertions(+), 23 deletions(-)
  13. diff --git a/gas/testsuite/gas/riscv/vector-insns.d b/gas/testsuite/gas/riscv/vector-insns.d
  14. index 8909e822a0..e53d2f3242 100644
  15. --- a/gas/testsuite/gas/riscv/vector-insns.d
  16. +++ b/gas/testsuite/gas/riscv/vector-insns.d
  17. @@ -1360,12 +1360,76 @@ Disassembly of section .text:
  18. [ ]+[0-9a-f]+:[ ]+f1057207[ ]+vlseg8e1024ff.v[ ]+v4,\(a0\),v0.t
  19. [ ]+[0-9a-f]+:[ ]+02850187[ ]+vl1r.v[ ]+v3,\(a0\)
  20. [ ]+[0-9a-f]+:[ ]+02850187[ ]+vl1r.v[ ]+v3,\(a0\)
  21. +[ ]+[0-9a-f]+:[ ]+02850187[ ]+vl1r.v[ ]+v3,\(a0\)
  22. +[ ]+[0-9a-f]+:[ ]+02850187[ ]+vl1r.v[ ]+v3,\(a0\)
  23. +[ ]+[0-9a-f]+:[ ]+02855187[ ]+vl1re16.v[ ]+v3,\(a0\)
  24. +[ ]+[0-9a-f]+:[ ]+02855187[ ]+vl1re16.v[ ]+v3,\(a0\)
  25. +[ ]+[0-9a-f]+:[ ]+02856187[ ]+vl1re32.v[ ]+v3,\(a0\)
  26. +[ ]+[0-9a-f]+:[ ]+02856187[ ]+vl1re32.v[ ]+v3,\(a0\)
  27. +[ ]+[0-9a-f]+:[ ]+02857187[ ]+vl1re64.v[ ]+v3,\(a0\)
  28. +[ ]+[0-9a-f]+:[ ]+02857187[ ]+vl1re64.v[ ]+v3,\(a0\)
  29. +[ ]+[0-9a-f]+:[ ]+12850187[ ]+vl1re128.v[ ]+v3,\(a0\)
  30. +[ ]+[0-9a-f]+:[ ]+12850187[ ]+vl1re128.v[ ]+v3,\(a0\)
  31. +[ ]+[0-9a-f]+:[ ]+12855187[ ]+vl1re256.v[ ]+v3,\(a0\)
  32. +[ ]+[0-9a-f]+:[ ]+12855187[ ]+vl1re256.v[ ]+v3,\(a0\)
  33. +[ ]+[0-9a-f]+:[ ]+12856187[ ]+vl1re512.v[ ]+v3,\(a0\)
  34. +[ ]+[0-9a-f]+:[ ]+12856187[ ]+vl1re512.v[ ]+v3,\(a0\)
  35. +[ ]+[0-9a-f]+:[ ]+12857187[ ]+vl1re1024.v[ ]+v3,\(a0\)
  36. +[ ]+[0-9a-f]+:[ ]+12857187[ ]+vl1re1024.v[ ]+v3,\(a0\)
  37. +[ ]+[0-9a-f]+:[ ]+22850107[ ]+vl2r.v[ ]+v2,\(a0\)
  38. +[ ]+[0-9a-f]+:[ ]+22850107[ ]+vl2r.v[ ]+v2,\(a0\)
  39. [ ]+[0-9a-f]+:[ ]+22850107[ ]+vl2r.v[ ]+v2,\(a0\)
  40. [ ]+[0-9a-f]+:[ ]+22850107[ ]+vl2r.v[ ]+v2,\(a0\)
  41. +[ ]+[0-9a-f]+:[ ]+22855107[ ]+vl2re16.v[ ]+v2,\(a0\)
  42. +[ ]+[0-9a-f]+:[ ]+22855107[ ]+vl2re16.v[ ]+v2,\(a0\)
  43. +[ ]+[0-9a-f]+:[ ]+22856107[ ]+vl2re32.v[ ]+v2,\(a0\)
  44. +[ ]+[0-9a-f]+:[ ]+22856107[ ]+vl2re32.v[ ]+v2,\(a0\)
  45. +[ ]+[0-9a-f]+:[ ]+22857107[ ]+vl2re64.v[ ]+v2,\(a0\)
  46. +[ ]+[0-9a-f]+:[ ]+22857107[ ]+vl2re64.v[ ]+v2,\(a0\)
  47. +[ ]+[0-9a-f]+:[ ]+32850107[ ]+vl2re128.v[ ]+v2,\(a0\)
  48. +[ ]+[0-9a-f]+:[ ]+32850107[ ]+vl2re128.v[ ]+v2,\(a0\)
  49. +[ ]+[0-9a-f]+:[ ]+32855107[ ]+vl2re256.v[ ]+v2,\(a0\)
  50. +[ ]+[0-9a-f]+:[ ]+32855107[ ]+vl2re256.v[ ]+v2,\(a0\)
  51. +[ ]+[0-9a-f]+:[ ]+32856107[ ]+vl2re512.v[ ]+v2,\(a0\)
  52. +[ ]+[0-9a-f]+:[ ]+32856107[ ]+vl2re512.v[ ]+v2,\(a0\)
  53. +[ ]+[0-9a-f]+:[ ]+32857107[ ]+vl2re1024.v[ ]+v2,\(a0\)
  54. +[ ]+[0-9a-f]+:[ ]+32857107[ ]+vl2re1024.v[ ]+v2,\(a0\)
  55. [ ]+[0-9a-f]+:[ ]+62850207[ ]+vl4r.v[ ]+v4,\(a0\)
  56. [ ]+[0-9a-f]+:[ ]+62850207[ ]+vl4r.v[ ]+v4,\(a0\)
  57. +[ ]+[0-9a-f]+:[ ]+62850207[ ]+vl4r.v[ ]+v4,\(a0\)
  58. +[ ]+[0-9a-f]+:[ ]+62850207[ ]+vl4r.v[ ]+v4,\(a0\)
  59. +[ ]+[0-9a-f]+:[ ]+62855207[ ]+vl4re16.v[ ]+v4,\(a0\)
  60. +[ ]+[0-9a-f]+:[ ]+62855207[ ]+vl4re16.v[ ]+v4,\(a0\)
  61. +[ ]+[0-9a-f]+:[ ]+62856207[ ]+vl4re32.v[ ]+v4,\(a0\)
  62. +[ ]+[0-9a-f]+:[ ]+62856207[ ]+vl4re32.v[ ]+v4,\(a0\)
  63. +[ ]+[0-9a-f]+:[ ]+62857207[ ]+vl4re64.v[ ]+v4,\(a0\)
  64. +[ ]+[0-9a-f]+:[ ]+62857207[ ]+vl4re64.v[ ]+v4,\(a0\)
  65. +[ ]+[0-9a-f]+:[ ]+72850207[ ]+vl4re128.v[ ]+v4,\(a0\)
  66. +[ ]+[0-9a-f]+:[ ]+72850207[ ]+vl4re128.v[ ]+v4,\(a0\)
  67. +[ ]+[0-9a-f]+:[ ]+72855207[ ]+vl4re256.v[ ]+v4,\(a0\)
  68. +[ ]+[0-9a-f]+:[ ]+72855207[ ]+vl4re256.v[ ]+v4,\(a0\)
  69. +[ ]+[0-9a-f]+:[ ]+72856207[ ]+vl4re512.v[ ]+v4,\(a0\)
  70. +[ ]+[0-9a-f]+:[ ]+72856207[ ]+vl4re512.v[ ]+v4,\(a0\)
  71. +[ ]+[0-9a-f]+:[ ]+72857207[ ]+vl4re1024.v[ ]+v4,\(a0\)
  72. +[ ]+[0-9a-f]+:[ ]+72857207[ ]+vl4re1024.v[ ]+v4,\(a0\)
  73. +[ ]+[0-9a-f]+:[ ]+e2850407[ ]+vl8r.v[ ]+v8,\(a0\)
  74. +[ ]+[0-9a-f]+:[ ]+e2850407[ ]+vl8r.v[ ]+v8,\(a0\)
  75. [ ]+[0-9a-f]+:[ ]+e2850407[ ]+vl8r.v[ ]+v8,\(a0\)
  76. [ ]+[0-9a-f]+:[ ]+e2850407[ ]+vl8r.v[ ]+v8,\(a0\)
  77. +[ ]+[0-9a-f]+:[ ]+e2855407[ ]+vl8re16.v[ ]+v8,\(a0\)
  78. +[ ]+[0-9a-f]+:[ ]+e2855407[ ]+vl8re16.v[ ]+v8,\(a0\)
  79. +[ ]+[0-9a-f]+:[ ]+e2856407[ ]+vl8re32.v[ ]+v8,\(a0\)
  80. +[ ]+[0-9a-f]+:[ ]+e2856407[ ]+vl8re32.v[ ]+v8,\(a0\)
  81. +[ ]+[0-9a-f]+:[ ]+e2857407[ ]+vl8re64.v[ ]+v8,\(a0\)
  82. +[ ]+[0-9a-f]+:[ ]+e2857407[ ]+vl8re64.v[ ]+v8,\(a0\)
  83. +[ ]+[0-9a-f]+:[ ]+f2850407[ ]+vl8re128.v[ ]+v8,\(a0\)
  84. +[ ]+[0-9a-f]+:[ ]+f2850407[ ]+vl8re128.v[ ]+v8,\(a0\)
  85. +[ ]+[0-9a-f]+:[ ]+f2855407[ ]+vl8re256.v[ ]+v8,\(a0\)
  86. +[ ]+[0-9a-f]+:[ ]+f2855407[ ]+vl8re256.v[ ]+v8,\(a0\)
  87. +[ ]+[0-9a-f]+:[ ]+f2856407[ ]+vl8re512.v[ ]+v8,\(a0\)
  88. +[ ]+[0-9a-f]+:[ ]+f2856407[ ]+vl8re512.v[ ]+v8,\(a0\)
  89. +[ ]+[0-9a-f]+:[ ]+f2857407[ ]+vl8re1024.v[ ]+v8,\(a0\)
  90. +[ ]+[0-9a-f]+:[ ]+f2857407[ ]+vl8re1024.v[ ]+v8,\(a0\)
  91. [ ]+[0-9a-f]+:[ ]+028581a7[ ]+vs1r.v[ ]+v3,\(a1\)
  92. [ ]+[0-9a-f]+:[ ]+028581a7[ ]+vs1r.v[ ]+v3,\(a1\)
  93. [ ]+[0-9a-f]+:[ ]+22858127[ ]+vs2r.v[ ]+v2,\(a1\)
  94. diff --git a/gas/testsuite/gas/riscv/vector-insns.s b/gas/testsuite/gas/riscv/vector-insns.s
  95. index 39da92bab7..5046dd3bda 100644
  96. --- a/gas/testsuite/gas/riscv/vector-insns.s
  97. +++ b/gas/testsuite/gas/riscv/vector-insns.s
  98. @@ -1604,12 +1604,79 @@
  99. vl1r.v v3, (a0)
  100. vl1r.v v3, 0(a0)
  101. + vl1re8.v v3, (a0)
  102. + vl1re8.v v3, 0(a0)
  103. + vl1re16.v v3, (a0)
  104. + vl1re16.v v3, 0(a0)
  105. + vl1re32.v v3, (a0)
  106. + vl1re32.v v3, 0(a0)
  107. + vl1re64.v v3, (a0)
  108. + vl1re64.v v3, 0(a0)
  109. + vl1re128.v v3, (a0)
  110. + vl1re128.v v3, 0(a0)
  111. + vl1re256.v v3, (a0)
  112. + vl1re256.v v3, 0(a0)
  113. + vl1re512.v v3, (a0)
  114. + vl1re512.v v3, 0(a0)
  115. + vl1re1024.v v3, (a0)
  116. + vl1re1024.v v3, 0(a0)
  117. +
  118. vl2r.v v2, (a0)
  119. vl2r.v v2, 0(a0)
  120. + vl2re8.v v2, (a0)
  121. + vl2re8.v v2, 0(a0)
  122. + vl2re16.v v2, (a0)
  123. + vl2re16.v v2, 0(a0)
  124. + vl2re32.v v2, (a0)
  125. + vl2re32.v v2, 0(a0)
  126. + vl2re64.v v2, (a0)
  127. + vl2re64.v v2, 0(a0)
  128. + vl2re128.v v2, (a0)
  129. + vl2re128.v v2, 0(a0)
  130. + vl2re256.v v2, (a0)
  131. + vl2re256.v v2, 0(a0)
  132. + vl2re512.v v2, (a0)
  133. + vl2re512.v v2, 0(a0)
  134. + vl2re1024.v v2, (a0)
  135. + vl2re1024.v v2, 0(a0)
  136. +
  137. vl4r.v v4, (a0)
  138. vl4r.v v4, 0(a0)
  139. + vl4re8.v v4, (a0)
  140. + vl4re8.v v4, 0(a0)
  141. + vl4re16.v v4, (a0)
  142. + vl4re16.v v4, 0(a0)
  143. + vl4re32.v v4, (a0)
  144. + vl4re32.v v4, 0(a0)
  145. + vl4re64.v v4, (a0)
  146. + vl4re64.v v4, 0(a0)
  147. + vl4re128.v v4, (a0)
  148. + vl4re128.v v4, 0(a0)
  149. + vl4re256.v v4, (a0)
  150. + vl4re256.v v4, 0(a0)
  151. + vl4re512.v v4, (a0)
  152. + vl4re512.v v4, 0(a0)
  153. + vl4re1024.v v4, (a0)
  154. + vl4re1024.v v4, 0(a0)
  155. +
  156. vl8r.v v8, (a0)
  157. vl8r.v v8, 0(a0)
  158. + vl8re8.v v8, (a0)
  159. + vl8re8.v v8, 0(a0)
  160. + vl8re16.v v8, (a0)
  161. + vl8re16.v v8, 0(a0)
  162. + vl8re32.v v8, (a0)
  163. + vl8re32.v v8, 0(a0)
  164. + vl8re64.v v8, (a0)
  165. + vl8re64.v v8, 0(a0)
  166. + vl8re128.v v8, (a0)
  167. + vl8re128.v v8, 0(a0)
  168. + vl8re256.v v8, (a0)
  169. + vl8re256.v v8, 0(a0)
  170. + vl8re512.v v8, (a0)
  171. + vl8re512.v v8, 0(a0)
  172. + vl8re1024.v v8, (a0)
  173. + vl8re1024.v v8, 0(a0)
  174. vs1r.v v3, (a1)
  175. vs1r.v v3, 0(a1)
  176. diff --git a/include/opcode/riscv-opc.h b/include/opcode/riscv-opc.h
  177. index 2da0574cc0..a17a1e8ca3 100644
  178. --- a/include/opcode/riscv-opc.h
  179. +++ b/include/opcode/riscv-opc.h
  180. @@ -558,13 +558,13 @@
  181. /* Temporary Load/store encoding info
  182. MOP load
  183. -00 unit-stride VLE<EEW>, VLE<EEW>FF, VL<nf>RV (nf = 1)
  184. +00 unit-stride VLE<EEW>, VLE<EEW>FF, VL<nf>RE<EEW> (nf = 1, 2, 4, 8)
  185. 01 reserved
  186. 10 strided VLSE<EEW>
  187. 11 indexed VLXEI<EEW>
  188. MOP store
  189. -00 unit-stride VSE<EEW>, VS<nf>RV (nf = 1)
  190. +00 unit-stride VSE<EEW>, VS<nf>R (nf = 1, 2, 4, 8)
  191. 01 indexed-unordered VSUXEI<EEW>
  192. 10 strided VSSE<EEW>
  193. 11 indexed-ordered VSXEI<EEW>
  194. @@ -587,20 +587,21 @@ SUMOP
  195. 01xxx reserved, x!=0
  196. 1xxxx reserved
  197. +EEW =
  198. MEW WIDTH
  199. - ---
  200. x 001 FLH/FSH
  201. x 010 FLW/FSW
  202. x 011 FLD/FSW
  203. x 100 FLQ/FSQ
  204. -0 000 VLxE8/VSxE8
  205. -0 101 VLxE16/VSxE16
  206. -0 110 VLxE32/VSxE32
  207. -0 111 VLxE64/VSxE64
  208. -1 000 VLxE128/VSxE128
  209. -1 101 VLxE256/VSxE256
  210. -1 110 VLxE512/VSxE512
  211. -1 111 VLxE1024/VSxE1024
  212. +0 000 VLxE8/VSxE8, VLxEI8/VSxEI8, VL<nf>RE8, VS<nf>R
  213. +0 101 VLxE16/VSxE16, VLxEI16/VSxEI16, VL<nf>RE16
  214. +0 110 VLxE32/VSxE32, VLxEI32/VSxEI32, VL<nf>RE32
  215. +0 111 VLxE64/VSxE64, VLxEI64/VSxEI64, VL<nf>RE64
  216. +1 000 VLxE128/VSxE128, VL<nf>RE128
  217. +1 101 VLxE256/VSxE256, VL<nf>RE256
  218. +1 110 VLxE512/VSxE512, VL<nf>RE512
  219. +1 111 VLxE1024/VSxE1024, VL<nf>RE1024
  220. NF MEW MOP VM LUMOP/RS2 RS1 WIDTH VD opcode
  221. 000 - 00 x 00000 xxxxx --- xxxxx 0000111 VLE<EEW>
  222. @@ -611,7 +612,7 @@ NF MEW MOP VM LUMOP/RS2 RS1 WIDTH VD opcode
  223. 000 0 11 x xxxxx xxxxx --- xxxxx 0100111 VSXE<EEW>I
  224. 000 0 01 x xxxxx xxxxx --- xxxxx 0100111 VSUXE<EEW>I
  225. 000 - 00 x 10000 xxxxx --- xxxxx 0000111 VLE<EEW>FF
  226. -xxx 0 00 1 01000 xxxxx 000 xxxxx 0000111 VL<nf>R, nf = 1,2,4,8
  227. +xxx - 00 1 01000 xxxxx --- xxxxx 0000111 VL<nf>RE<EEW>, nf = 1,2,4,8
  228. xxx 0 00 1 01000 xxxxx 000 xxxxx 0100111 VS<nf>R, nf = 1,2,4,8
  229. xxx - 00 x 00000 xxxxx --- xxxxx 0000111 VLSEG<nf>E<EEW>
  230. @@ -1551,14 +1552,73 @@ xxx - 00 x 10000 xxxxx --- xxxxx 0000111 VLSEG<nf>E<EEW>FF
  231. #define MATCH_VLSEG8E1024FFV 0xf1007007
  232. #define MASK_VLSEG8E1024FFV 0xfdf0707f
  233. -#define MATCH_VL1RV 0x02800007
  234. -#define MASK_VL1RV 0xfff0707f
  235. -#define MATCH_VL2RV 0x22800007
  236. -#define MASK_VL2RV 0xfff0707f
  237. -#define MATCH_VL4RV 0x62800007
  238. -#define MASK_VL4RV 0xfff0707f
  239. -#define MATCH_VL8RV 0xe2800007
  240. -#define MASK_VL8RV 0xfff0707f
  241. +#define MATCH_VL1RE8V 0x02800007
  242. +#define MASK_VL1RE8V 0xfff0707f
  243. +#define MATCH_VL1RE16V 0x02805007
  244. +#define MASK_VL1RE16V 0xfff0707f
  245. +#define MATCH_VL1RE32V 0x02806007
  246. +#define MASK_VL1RE32V 0xfff0707f
  247. +#define MATCH_VL1RE64V 0x02807007
  248. +#define MASK_VL1RE64V 0xfff0707f
  249. +#define MATCH_VL1RE128V 0x12800007
  250. +#define MASK_VL1RE128V 0xfff0707f
  251. +#define MATCH_VL1RE256V 0x12805007
  252. +#define MASK_VL1RE256V 0xfff0707f
  253. +#define MATCH_VL1RE512V 0x12806007
  254. +#define MASK_VL1RE512V 0xfff0707f
  255. +#define MATCH_VL1RE1024V 0x12807007
  256. +#define MASK_VL1RE1024V 0xfff0707f
  257. +
  258. +#define MATCH_VL2RE8V 0x22800007
  259. +#define MASK_VL2RE8V 0xfff0707f
  260. +#define MATCH_VL2RE16V 0x22805007
  261. +#define MASK_VL2RE16V 0xfff0707f
  262. +#define MATCH_VL2RE32V 0x22806007
  263. +#define MASK_VL2RE32V 0xfff0707f
  264. +#define MATCH_VL2RE64V 0x22807007
  265. +#define MASK_VL2RE64V 0xfff0707f
  266. +#define MATCH_VL2RE128V 0x32800007
  267. +#define MASK_VL2RE128V 0xfff0707f
  268. +#define MATCH_VL2RE256V 0x32805007
  269. +#define MASK_VL2RE256V 0xfff0707f
  270. +#define MATCH_VL2RE512V 0x32806007
  271. +#define MASK_VL2RE512V 0xfff0707f
  272. +#define MATCH_VL2RE1024V 0x32807007
  273. +#define MASK_VL2RE1024V 0xfff0707f
  274. +
  275. +#define MATCH_VL4RE8V 0x62800007
  276. +#define MASK_VL4RE8V 0xfff0707f
  277. +#define MATCH_VL4RE16V 0x62805007
  278. +#define MASK_VL4RE16V 0xfff0707f
  279. +#define MATCH_VL4RE32V 0x62806007
  280. +#define MASK_VL4RE32V 0xfff0707f
  281. +#define MATCH_VL4RE64V 0x62807007
  282. +#define MASK_VL4RE64V 0xfff0707f
  283. +#define MATCH_VL4RE128V 0x72800007
  284. +#define MASK_VL4RE128V 0xfff0707f
  285. +#define MATCH_VL4RE256V 0x72805007
  286. +#define MASK_VL4RE256V 0xfff0707f
  287. +#define MATCH_VL4RE512V 0x72806007
  288. +#define MASK_VL4RE512V 0xfff0707f
  289. +#define MATCH_VL4RE1024V 0x72807007
  290. +#define MASK_VL4RE1024V 0xfff0707f
  291. +
  292. +#define MATCH_VL8RE8V 0xe2800007
  293. +#define MASK_VL8RE8V 0xfff0707f
  294. +#define MATCH_VL8RE16V 0xe2805007
  295. +#define MASK_VL8RE16V 0xfff0707f
  296. +#define MATCH_VL8RE32V 0xe2806007
  297. +#define MASK_VL8RE32V 0xfff0707f
  298. +#define MATCH_VL8RE64V 0xe2807007
  299. +#define MASK_VL8RE64V 0xfff0707f
  300. +#define MATCH_VL8RE128V 0xf2800007
  301. +#define MASK_VL8RE128V 0xfff0707f
  302. +#define MATCH_VL8RE256V 0xf2805007
  303. +#define MASK_VL8RE256V 0xfff0707f
  304. +#define MATCH_VL8RE512V 0xf2806007
  305. +#define MASK_VL8RE512V 0xfff0707f
  306. +#define MATCH_VL8RE1024V 0xf2807007
  307. +#define MASK_VL8RE1024V 0xfff0707f
  308. #define MATCH_VS1RV 0x02800027
  309. #define MASK_VS1RV 0xfff0707f
  310. diff --git a/opcodes/riscv-opc.c b/opcodes/riscv-opc.c
  311. index cb89f59208..208d3ce31b 100644
  312. --- a/opcodes/riscv-opc.c
  313. +++ b/opcodes/riscv-opc.c
  314. @@ -1550,10 +1550,45 @@ const struct riscv_opcode riscv_opcodes[] =
  315. {"vlseg7e1024ff.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s)Vm", MATCH_VLSEG7E1024FFV, MASK_VLSEG7E1024FFV, match_vd_neq_vm, INSN_DREF },
  316. {"vlseg8e1024ff.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s)Vm", MATCH_VLSEG8E1024FFV, MASK_VLSEG8E1024FFV, match_vd_neq_vm, INSN_DREF },
  317. -{"vl1r.v", 0, INSN_CLASS_V, "Vd,0(s)", MATCH_VL1RV, MASK_VL1RV, match_opcode, INSN_DREF },
  318. -{"vl2r.v", 0, INSN_CLASS_V, "Vd,0(s)", MATCH_VL2RV, MASK_VL2RV, match_opcode, INSN_DREF },
  319. -{"vl4r.v", 0, INSN_CLASS_V, "Vd,0(s)", MATCH_VL4RV, MASK_VL4RV, match_opcode, INSN_DREF },
  320. -{"vl8r.v", 0, INSN_CLASS_V, "Vd,0(s)", MATCH_VL8RV, MASK_VL8RV, match_opcode, INSN_DREF },
  321. +{"vl1r.v", 0, INSN_CLASS_V, "Vd,0(s)", MATCH_VL1RE8V, MASK_VL1RE8V, match_opcode, INSN_DREF|INSN_ALIAS },
  322. +{"vl1re8.v", 0, INSN_CLASS_V, "Vd,0(s)", MATCH_VL1RE8V, MASK_VL1RE8V, match_opcode, INSN_DREF },
  323. +{"vl1re16.v", 0, INSN_CLASS_V, "Vd,0(s)", MATCH_VL1RE16V, MASK_VL1RE16V, match_opcode, INSN_DREF },
  324. +{"vl1re32.v", 0, INSN_CLASS_V, "Vd,0(s)", MATCH_VL1RE32V, MASK_VL1RE32V, match_opcode, INSN_DREF },
  325. +{"vl1re64.v", 0, INSN_CLASS_V, "Vd,0(s)", MATCH_VL1RE64V, MASK_VL1RE64V, match_opcode, INSN_DREF },
  326. +{"vl1re128.v", 0, INSN_CLASS_V, "Vd,0(s)", MATCH_VL1RE128V, MASK_VL1RE128V, match_opcode, INSN_DREF },
  327. +{"vl1re256.v", 0, INSN_CLASS_V, "Vd,0(s)", MATCH_VL1RE256V, MASK_VL1RE256V, match_opcode, INSN_DREF },
  328. +{"vl1re512.v", 0, INSN_CLASS_V, "Vd,0(s)", MATCH_VL1RE512V, MASK_VL1RE512V, match_opcode, INSN_DREF },
  329. +{"vl1re1024.v", 0, INSN_CLASS_V, "Vd,0(s)", MATCH_VL1RE1024V, MASK_VL1RE1024V, match_opcode, INSN_DREF },
  330. +
  331. +{"vl2r.v", 0, INSN_CLASS_V, "Vd,0(s)", MATCH_VL2RE8V, MASK_VL2RE8V, match_opcode, INSN_DREF|INSN_ALIAS },
  332. +{"vl2re8.v", 0, INSN_CLASS_V, "Vd,0(s)", MATCH_VL2RE8V, MASK_VL2RE8V, match_opcode, INSN_DREF },
  333. +{"vl2re16.v", 0, INSN_CLASS_V, "Vd,0(s)", MATCH_VL2RE16V, MASK_VL2RE16V, match_opcode, INSN_DREF },
  334. +{"vl2re32.v", 0, INSN_CLASS_V, "Vd,0(s)", MATCH_VL2RE32V, MASK_VL2RE32V, match_opcode, INSN_DREF },
  335. +{"vl2re64.v", 0, INSN_CLASS_V, "Vd,0(s)", MATCH_VL2RE64V, MASK_VL2RE64V, match_opcode, INSN_DREF },
  336. +{"vl2re128.v", 0, INSN_CLASS_V, "Vd,0(s)", MATCH_VL2RE128V, MASK_VL2RE128V, match_opcode, INSN_DREF },
  337. +{"vl2re256.v", 0, INSN_CLASS_V, "Vd,0(s)", MATCH_VL2RE256V, MASK_VL2RE256V, match_opcode, INSN_DREF },
  338. +{"vl2re512.v", 0, INSN_CLASS_V, "Vd,0(s)", MATCH_VL2RE512V, MASK_VL2RE512V, match_opcode, INSN_DREF },
  339. +{"vl2re1024.v", 0, INSN_CLASS_V, "Vd,0(s)", MATCH_VL2RE1024V, MASK_VL2RE1024V, match_opcode, INSN_DREF },
  340. +
  341. +{"vl4r.v", 0, INSN_CLASS_V, "Vd,0(s)", MATCH_VL4RE8V, MASK_VL4RE8V, match_opcode, INSN_DREF|INSN_ALIAS },
  342. +{"vl4re8.v", 0, INSN_CLASS_V, "Vd,0(s)", MATCH_VL4RE8V, MASK_VL4RE8V, match_opcode, INSN_DREF },
  343. +{"vl4re16.v", 0, INSN_CLASS_V, "Vd,0(s)", MATCH_VL4RE16V, MASK_VL4RE16V, match_opcode, INSN_DREF },
  344. +{"vl4re32.v", 0, INSN_CLASS_V, "Vd,0(s)", MATCH_VL4RE32V, MASK_VL4RE32V, match_opcode, INSN_DREF },
  345. +{"vl4re64.v", 0, INSN_CLASS_V, "Vd,0(s)", MATCH_VL4RE64V, MASK_VL4RE64V, match_opcode, INSN_DREF },
  346. +{"vl4re128.v", 0, INSN_CLASS_V, "Vd,0(s)", MATCH_VL4RE128V, MASK_VL4RE128V, match_opcode, INSN_DREF },
  347. +{"vl4re256.v", 0, INSN_CLASS_V, "Vd,0(s)", MATCH_VL4RE256V, MASK_VL4RE256V, match_opcode, INSN_DREF },
  348. +{"vl4re512.v", 0, INSN_CLASS_V, "Vd,0(s)", MATCH_VL4RE512V, MASK_VL4RE512V, match_opcode, INSN_DREF },
  349. +{"vl4re1024.v", 0, INSN_CLASS_V, "Vd,0(s)", MATCH_VL4RE1024V, MASK_VL4RE1024V, match_opcode, INSN_DREF },
  350. +
  351. +{"vl8r.v", 0, INSN_CLASS_V, "Vd,0(s)", MATCH_VL8RE8V, MASK_VL8RE8V, match_opcode, INSN_DREF|INSN_ALIAS },
  352. +{"vl8re8.v", 0, INSN_CLASS_V, "Vd,0(s)", MATCH_VL8RE8V, MASK_VL8RE8V, match_opcode, INSN_DREF },
  353. +{"vl8re16.v", 0, INSN_CLASS_V, "Vd,0(s)", MATCH_VL8RE16V, MASK_VL8RE16V, match_opcode, INSN_DREF },
  354. +{"vl8re32.v", 0, INSN_CLASS_V, "Vd,0(s)", MATCH_VL8RE32V, MASK_VL8RE32V, match_opcode, INSN_DREF },
  355. +{"vl8re64.v", 0, INSN_CLASS_V, "Vd,0(s)", MATCH_VL8RE64V, MASK_VL8RE64V, match_opcode, INSN_DREF },
  356. +{"vl8re128.v", 0, INSN_CLASS_V, "Vd,0(s)", MATCH_VL8RE128V, MASK_VL8RE128V, match_opcode, INSN_DREF },
  357. +{"vl8re256.v", 0, INSN_CLASS_V, "Vd,0(s)", MATCH_VL8RE256V, MASK_VL8RE256V, match_opcode, INSN_DREF },
  358. +{"vl8re512.v", 0, INSN_CLASS_V, "Vd,0(s)", MATCH_VL8RE512V, MASK_VL8RE512V, match_opcode, INSN_DREF },
  359. +{"vl8re1024.v", 0, INSN_CLASS_V, "Vd,0(s)", MATCH_VL8RE1024V, MASK_VL8RE1024V, match_opcode, INSN_DREF },
  360. {"vs1r.v", 0, INSN_CLASS_V, "Vd,0(s)", MATCH_VS1RV, MASK_VS1RV, match_opcode, INSN_DREF },
  361. {"vs2r.v", 0, INSN_CLASS_V, "Vd,0(s)", MATCH_VS2RV, MASK_VS2RV, match_opcode, INSN_DREF },
  362. --
  363. 2.33.0