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- From 33636301c48d21eaf665355c124af357ef5777c2 Mon Sep 17 00:00:00 2001
- From: Nelson Chu <nelson.chu@sifive.com>
- Date: Mon, 6 Jul 2020 22:34:19 +0800
- Subject: [PATCH 18/48] Added element width hint to whole register
- loads/stores.
- Add load instructions which have an EEW encoded in the `mew` and `width`.
- ---
- gas/testsuite/gas/riscv/vector-insns.d | 64 +++++++++++++++++
- gas/testsuite/gas/riscv/vector-insns.s | 67 ++++++++++++++++++
- include/opcode/riscv-opc.h | 98 +++++++++++++++++++++-----
- opcodes/riscv-opc.c | 43 +++++++++--
- 4 files changed, 249 insertions(+), 23 deletions(-)
- diff --git a/gas/testsuite/gas/riscv/vector-insns.d b/gas/testsuite/gas/riscv/vector-insns.d
- index 8909e822a0..e53d2f3242 100644
- --- a/gas/testsuite/gas/riscv/vector-insns.d
- +++ b/gas/testsuite/gas/riscv/vector-insns.d
- @@ -1360,12 +1360,76 @@ Disassembly of section .text:
- [ ]+[0-9a-f]+:[ ]+f1057207[ ]+vlseg8e1024ff.v[ ]+v4,\(a0\),v0.t
- [ ]+[0-9a-f]+:[ ]+02850187[ ]+vl1r.v[ ]+v3,\(a0\)
- [ ]+[0-9a-f]+:[ ]+02850187[ ]+vl1r.v[ ]+v3,\(a0\)
- +[ ]+[0-9a-f]+:[ ]+02850187[ ]+vl1r.v[ ]+v3,\(a0\)
- +[ ]+[0-9a-f]+:[ ]+02850187[ ]+vl1r.v[ ]+v3,\(a0\)
- +[ ]+[0-9a-f]+:[ ]+02855187[ ]+vl1re16.v[ ]+v3,\(a0\)
- +[ ]+[0-9a-f]+:[ ]+02855187[ ]+vl1re16.v[ ]+v3,\(a0\)
- +[ ]+[0-9a-f]+:[ ]+02856187[ ]+vl1re32.v[ ]+v3,\(a0\)
- +[ ]+[0-9a-f]+:[ ]+02856187[ ]+vl1re32.v[ ]+v3,\(a0\)
- +[ ]+[0-9a-f]+:[ ]+02857187[ ]+vl1re64.v[ ]+v3,\(a0\)
- +[ ]+[0-9a-f]+:[ ]+02857187[ ]+vl1re64.v[ ]+v3,\(a0\)
- +[ ]+[0-9a-f]+:[ ]+12850187[ ]+vl1re128.v[ ]+v3,\(a0\)
- +[ ]+[0-9a-f]+:[ ]+12850187[ ]+vl1re128.v[ ]+v3,\(a0\)
- +[ ]+[0-9a-f]+:[ ]+12855187[ ]+vl1re256.v[ ]+v3,\(a0\)
- +[ ]+[0-9a-f]+:[ ]+12855187[ ]+vl1re256.v[ ]+v3,\(a0\)
- +[ ]+[0-9a-f]+:[ ]+12856187[ ]+vl1re512.v[ ]+v3,\(a0\)
- +[ ]+[0-9a-f]+:[ ]+12856187[ ]+vl1re512.v[ ]+v3,\(a0\)
- +[ ]+[0-9a-f]+:[ ]+12857187[ ]+vl1re1024.v[ ]+v3,\(a0\)
- +[ ]+[0-9a-f]+:[ ]+12857187[ ]+vl1re1024.v[ ]+v3,\(a0\)
- +[ ]+[0-9a-f]+:[ ]+22850107[ ]+vl2r.v[ ]+v2,\(a0\)
- +[ ]+[0-9a-f]+:[ ]+22850107[ ]+vl2r.v[ ]+v2,\(a0\)
- [ ]+[0-9a-f]+:[ ]+22850107[ ]+vl2r.v[ ]+v2,\(a0\)
- [ ]+[0-9a-f]+:[ ]+22850107[ ]+vl2r.v[ ]+v2,\(a0\)
- +[ ]+[0-9a-f]+:[ ]+22855107[ ]+vl2re16.v[ ]+v2,\(a0\)
- +[ ]+[0-9a-f]+:[ ]+22855107[ ]+vl2re16.v[ ]+v2,\(a0\)
- +[ ]+[0-9a-f]+:[ ]+22856107[ ]+vl2re32.v[ ]+v2,\(a0\)
- +[ ]+[0-9a-f]+:[ ]+22856107[ ]+vl2re32.v[ ]+v2,\(a0\)
- +[ ]+[0-9a-f]+:[ ]+22857107[ ]+vl2re64.v[ ]+v2,\(a0\)
- +[ ]+[0-9a-f]+:[ ]+22857107[ ]+vl2re64.v[ ]+v2,\(a0\)
- +[ ]+[0-9a-f]+:[ ]+32850107[ ]+vl2re128.v[ ]+v2,\(a0\)
- +[ ]+[0-9a-f]+:[ ]+32850107[ ]+vl2re128.v[ ]+v2,\(a0\)
- +[ ]+[0-9a-f]+:[ ]+32855107[ ]+vl2re256.v[ ]+v2,\(a0\)
- +[ ]+[0-9a-f]+:[ ]+32855107[ ]+vl2re256.v[ ]+v2,\(a0\)
- +[ ]+[0-9a-f]+:[ ]+32856107[ ]+vl2re512.v[ ]+v2,\(a0\)
- +[ ]+[0-9a-f]+:[ ]+32856107[ ]+vl2re512.v[ ]+v2,\(a0\)
- +[ ]+[0-9a-f]+:[ ]+32857107[ ]+vl2re1024.v[ ]+v2,\(a0\)
- +[ ]+[0-9a-f]+:[ ]+32857107[ ]+vl2re1024.v[ ]+v2,\(a0\)
- [ ]+[0-9a-f]+:[ ]+62850207[ ]+vl4r.v[ ]+v4,\(a0\)
- [ ]+[0-9a-f]+:[ ]+62850207[ ]+vl4r.v[ ]+v4,\(a0\)
- +[ ]+[0-9a-f]+:[ ]+62850207[ ]+vl4r.v[ ]+v4,\(a0\)
- +[ ]+[0-9a-f]+:[ ]+62850207[ ]+vl4r.v[ ]+v4,\(a0\)
- +[ ]+[0-9a-f]+:[ ]+62855207[ ]+vl4re16.v[ ]+v4,\(a0\)
- +[ ]+[0-9a-f]+:[ ]+62855207[ ]+vl4re16.v[ ]+v4,\(a0\)
- +[ ]+[0-9a-f]+:[ ]+62856207[ ]+vl4re32.v[ ]+v4,\(a0\)
- +[ ]+[0-9a-f]+:[ ]+62856207[ ]+vl4re32.v[ ]+v4,\(a0\)
- +[ ]+[0-9a-f]+:[ ]+62857207[ ]+vl4re64.v[ ]+v4,\(a0\)
- +[ ]+[0-9a-f]+:[ ]+62857207[ ]+vl4re64.v[ ]+v4,\(a0\)
- +[ ]+[0-9a-f]+:[ ]+72850207[ ]+vl4re128.v[ ]+v4,\(a0\)
- +[ ]+[0-9a-f]+:[ ]+72850207[ ]+vl4re128.v[ ]+v4,\(a0\)
- +[ ]+[0-9a-f]+:[ ]+72855207[ ]+vl4re256.v[ ]+v4,\(a0\)
- +[ ]+[0-9a-f]+:[ ]+72855207[ ]+vl4re256.v[ ]+v4,\(a0\)
- +[ ]+[0-9a-f]+:[ ]+72856207[ ]+vl4re512.v[ ]+v4,\(a0\)
- +[ ]+[0-9a-f]+:[ ]+72856207[ ]+vl4re512.v[ ]+v4,\(a0\)
- +[ ]+[0-9a-f]+:[ ]+72857207[ ]+vl4re1024.v[ ]+v4,\(a0\)
- +[ ]+[0-9a-f]+:[ ]+72857207[ ]+vl4re1024.v[ ]+v4,\(a0\)
- +[ ]+[0-9a-f]+:[ ]+e2850407[ ]+vl8r.v[ ]+v8,\(a0\)
- +[ ]+[0-9a-f]+:[ ]+e2850407[ ]+vl8r.v[ ]+v8,\(a0\)
- [ ]+[0-9a-f]+:[ ]+e2850407[ ]+vl8r.v[ ]+v8,\(a0\)
- [ ]+[0-9a-f]+:[ ]+e2850407[ ]+vl8r.v[ ]+v8,\(a0\)
- +[ ]+[0-9a-f]+:[ ]+e2855407[ ]+vl8re16.v[ ]+v8,\(a0\)
- +[ ]+[0-9a-f]+:[ ]+e2855407[ ]+vl8re16.v[ ]+v8,\(a0\)
- +[ ]+[0-9a-f]+:[ ]+e2856407[ ]+vl8re32.v[ ]+v8,\(a0\)
- +[ ]+[0-9a-f]+:[ ]+e2856407[ ]+vl8re32.v[ ]+v8,\(a0\)
- +[ ]+[0-9a-f]+:[ ]+e2857407[ ]+vl8re64.v[ ]+v8,\(a0\)
- +[ ]+[0-9a-f]+:[ ]+e2857407[ ]+vl8re64.v[ ]+v8,\(a0\)
- +[ ]+[0-9a-f]+:[ ]+f2850407[ ]+vl8re128.v[ ]+v8,\(a0\)
- +[ ]+[0-9a-f]+:[ ]+f2850407[ ]+vl8re128.v[ ]+v8,\(a0\)
- +[ ]+[0-9a-f]+:[ ]+f2855407[ ]+vl8re256.v[ ]+v8,\(a0\)
- +[ ]+[0-9a-f]+:[ ]+f2855407[ ]+vl8re256.v[ ]+v8,\(a0\)
- +[ ]+[0-9a-f]+:[ ]+f2856407[ ]+vl8re512.v[ ]+v8,\(a0\)
- +[ ]+[0-9a-f]+:[ ]+f2856407[ ]+vl8re512.v[ ]+v8,\(a0\)
- +[ ]+[0-9a-f]+:[ ]+f2857407[ ]+vl8re1024.v[ ]+v8,\(a0\)
- +[ ]+[0-9a-f]+:[ ]+f2857407[ ]+vl8re1024.v[ ]+v8,\(a0\)
- [ ]+[0-9a-f]+:[ ]+028581a7[ ]+vs1r.v[ ]+v3,\(a1\)
- [ ]+[0-9a-f]+:[ ]+028581a7[ ]+vs1r.v[ ]+v3,\(a1\)
- [ ]+[0-9a-f]+:[ ]+22858127[ ]+vs2r.v[ ]+v2,\(a1\)
- diff --git a/gas/testsuite/gas/riscv/vector-insns.s b/gas/testsuite/gas/riscv/vector-insns.s
- index 39da92bab7..5046dd3bda 100644
- --- a/gas/testsuite/gas/riscv/vector-insns.s
- +++ b/gas/testsuite/gas/riscv/vector-insns.s
- @@ -1604,12 +1604,79 @@
-
- vl1r.v v3, (a0)
- vl1r.v v3, 0(a0)
- + vl1re8.v v3, (a0)
- + vl1re8.v v3, 0(a0)
- + vl1re16.v v3, (a0)
- + vl1re16.v v3, 0(a0)
- + vl1re32.v v3, (a0)
- + vl1re32.v v3, 0(a0)
- + vl1re64.v v3, (a0)
- + vl1re64.v v3, 0(a0)
- + vl1re128.v v3, (a0)
- + vl1re128.v v3, 0(a0)
- + vl1re256.v v3, (a0)
- + vl1re256.v v3, 0(a0)
- + vl1re512.v v3, (a0)
- + vl1re512.v v3, 0(a0)
- + vl1re1024.v v3, (a0)
- + vl1re1024.v v3, 0(a0)
- +
- vl2r.v v2, (a0)
- vl2r.v v2, 0(a0)
- + vl2re8.v v2, (a0)
- + vl2re8.v v2, 0(a0)
- + vl2re16.v v2, (a0)
- + vl2re16.v v2, 0(a0)
- + vl2re32.v v2, (a0)
- + vl2re32.v v2, 0(a0)
- + vl2re64.v v2, (a0)
- + vl2re64.v v2, 0(a0)
- + vl2re128.v v2, (a0)
- + vl2re128.v v2, 0(a0)
- + vl2re256.v v2, (a0)
- + vl2re256.v v2, 0(a0)
- + vl2re512.v v2, (a0)
- + vl2re512.v v2, 0(a0)
- + vl2re1024.v v2, (a0)
- + vl2re1024.v v2, 0(a0)
- +
- vl4r.v v4, (a0)
- vl4r.v v4, 0(a0)
- + vl4re8.v v4, (a0)
- + vl4re8.v v4, 0(a0)
- + vl4re16.v v4, (a0)
- + vl4re16.v v4, 0(a0)
- + vl4re32.v v4, (a0)
- + vl4re32.v v4, 0(a0)
- + vl4re64.v v4, (a0)
- + vl4re64.v v4, 0(a0)
- + vl4re128.v v4, (a0)
- + vl4re128.v v4, 0(a0)
- + vl4re256.v v4, (a0)
- + vl4re256.v v4, 0(a0)
- + vl4re512.v v4, (a0)
- + vl4re512.v v4, 0(a0)
- + vl4re1024.v v4, (a0)
- + vl4re1024.v v4, 0(a0)
- +
- vl8r.v v8, (a0)
- vl8r.v v8, 0(a0)
- + vl8re8.v v8, (a0)
- + vl8re8.v v8, 0(a0)
- + vl8re16.v v8, (a0)
- + vl8re16.v v8, 0(a0)
- + vl8re32.v v8, (a0)
- + vl8re32.v v8, 0(a0)
- + vl8re64.v v8, (a0)
- + vl8re64.v v8, 0(a0)
- + vl8re128.v v8, (a0)
- + vl8re128.v v8, 0(a0)
- + vl8re256.v v8, (a0)
- + vl8re256.v v8, 0(a0)
- + vl8re512.v v8, (a0)
- + vl8re512.v v8, 0(a0)
- + vl8re1024.v v8, (a0)
- + vl8re1024.v v8, 0(a0)
-
- vs1r.v v3, (a1)
- vs1r.v v3, 0(a1)
- diff --git a/include/opcode/riscv-opc.h b/include/opcode/riscv-opc.h
- index 2da0574cc0..a17a1e8ca3 100644
- --- a/include/opcode/riscv-opc.h
- +++ b/include/opcode/riscv-opc.h
- @@ -558,13 +558,13 @@
-
- /* Temporary Load/store encoding info
- MOP load
- -00 unit-stride VLE<EEW>, VLE<EEW>FF, VL<nf>RV (nf = 1)
- +00 unit-stride VLE<EEW>, VLE<EEW>FF, VL<nf>RE<EEW> (nf = 1, 2, 4, 8)
- 01 reserved
- 10 strided VLSE<EEW>
- 11 indexed VLXEI<EEW>
-
- MOP store
- -00 unit-stride VSE<EEW>, VS<nf>RV (nf = 1)
- +00 unit-stride VSE<EEW>, VS<nf>R (nf = 1, 2, 4, 8)
- 01 indexed-unordered VSUXEI<EEW>
- 10 strided VSSE<EEW>
- 11 indexed-ordered VSXEI<EEW>
- @@ -587,20 +587,21 @@ SUMOP
- 01xxx reserved, x!=0
- 1xxxx reserved
-
- +EEW =
- MEW WIDTH
- - ---
- x 001 FLH/FSH
- x 010 FLW/FSW
- x 011 FLD/FSW
- x 100 FLQ/FSQ
- -0 000 VLxE8/VSxE8
- -0 101 VLxE16/VSxE16
- -0 110 VLxE32/VSxE32
- -0 111 VLxE64/VSxE64
- -1 000 VLxE128/VSxE128
- -1 101 VLxE256/VSxE256
- -1 110 VLxE512/VSxE512
- -1 111 VLxE1024/VSxE1024
- +0 000 VLxE8/VSxE8, VLxEI8/VSxEI8, VL<nf>RE8, VS<nf>R
- +0 101 VLxE16/VSxE16, VLxEI16/VSxEI16, VL<nf>RE16
- +0 110 VLxE32/VSxE32, VLxEI32/VSxEI32, VL<nf>RE32
- +0 111 VLxE64/VSxE64, VLxEI64/VSxEI64, VL<nf>RE64
- +1 000 VLxE128/VSxE128, VL<nf>RE128
- +1 101 VLxE256/VSxE256, VL<nf>RE256
- +1 110 VLxE512/VSxE512, VL<nf>RE512
- +1 111 VLxE1024/VSxE1024, VL<nf>RE1024
-
- NF MEW MOP VM LUMOP/RS2 RS1 WIDTH VD opcode
- 000 - 00 x 00000 xxxxx --- xxxxx 0000111 VLE<EEW>
- @@ -611,7 +612,7 @@ NF MEW MOP VM LUMOP/RS2 RS1 WIDTH VD opcode
- 000 0 11 x xxxxx xxxxx --- xxxxx 0100111 VSXE<EEW>I
- 000 0 01 x xxxxx xxxxx --- xxxxx 0100111 VSUXE<EEW>I
- 000 - 00 x 10000 xxxxx --- xxxxx 0000111 VLE<EEW>FF
- -xxx 0 00 1 01000 xxxxx 000 xxxxx 0000111 VL<nf>R, nf = 1,2,4,8
- +xxx - 00 1 01000 xxxxx --- xxxxx 0000111 VL<nf>RE<EEW>, nf = 1,2,4,8
- xxx 0 00 1 01000 xxxxx 000 xxxxx 0100111 VS<nf>R, nf = 1,2,4,8
-
- xxx - 00 x 00000 xxxxx --- xxxxx 0000111 VLSEG<nf>E<EEW>
- @@ -1551,14 +1552,73 @@ xxx - 00 x 10000 xxxxx --- xxxxx 0000111 VLSEG<nf>E<EEW>FF
- #define MATCH_VLSEG8E1024FFV 0xf1007007
- #define MASK_VLSEG8E1024FFV 0xfdf0707f
-
- -#define MATCH_VL1RV 0x02800007
- -#define MASK_VL1RV 0xfff0707f
- -#define MATCH_VL2RV 0x22800007
- -#define MASK_VL2RV 0xfff0707f
- -#define MATCH_VL4RV 0x62800007
- -#define MASK_VL4RV 0xfff0707f
- -#define MATCH_VL8RV 0xe2800007
- -#define MASK_VL8RV 0xfff0707f
- +#define MATCH_VL1RE8V 0x02800007
- +#define MASK_VL1RE8V 0xfff0707f
- +#define MATCH_VL1RE16V 0x02805007
- +#define MASK_VL1RE16V 0xfff0707f
- +#define MATCH_VL1RE32V 0x02806007
- +#define MASK_VL1RE32V 0xfff0707f
- +#define MATCH_VL1RE64V 0x02807007
- +#define MASK_VL1RE64V 0xfff0707f
- +#define MATCH_VL1RE128V 0x12800007
- +#define MASK_VL1RE128V 0xfff0707f
- +#define MATCH_VL1RE256V 0x12805007
- +#define MASK_VL1RE256V 0xfff0707f
- +#define MATCH_VL1RE512V 0x12806007
- +#define MASK_VL1RE512V 0xfff0707f
- +#define MATCH_VL1RE1024V 0x12807007
- +#define MASK_VL1RE1024V 0xfff0707f
- +
- +#define MATCH_VL2RE8V 0x22800007
- +#define MASK_VL2RE8V 0xfff0707f
- +#define MATCH_VL2RE16V 0x22805007
- +#define MASK_VL2RE16V 0xfff0707f
- +#define MATCH_VL2RE32V 0x22806007
- +#define MASK_VL2RE32V 0xfff0707f
- +#define MATCH_VL2RE64V 0x22807007
- +#define MASK_VL2RE64V 0xfff0707f
- +#define MATCH_VL2RE128V 0x32800007
- +#define MASK_VL2RE128V 0xfff0707f
- +#define MATCH_VL2RE256V 0x32805007
- +#define MASK_VL2RE256V 0xfff0707f
- +#define MATCH_VL2RE512V 0x32806007
- +#define MASK_VL2RE512V 0xfff0707f
- +#define MATCH_VL2RE1024V 0x32807007
- +#define MASK_VL2RE1024V 0xfff0707f
- +
- +#define MATCH_VL4RE8V 0x62800007
- +#define MASK_VL4RE8V 0xfff0707f
- +#define MATCH_VL4RE16V 0x62805007
- +#define MASK_VL4RE16V 0xfff0707f
- +#define MATCH_VL4RE32V 0x62806007
- +#define MASK_VL4RE32V 0xfff0707f
- +#define MATCH_VL4RE64V 0x62807007
- +#define MASK_VL4RE64V 0xfff0707f
- +#define MATCH_VL4RE128V 0x72800007
- +#define MASK_VL4RE128V 0xfff0707f
- +#define MATCH_VL4RE256V 0x72805007
- +#define MASK_VL4RE256V 0xfff0707f
- +#define MATCH_VL4RE512V 0x72806007
- +#define MASK_VL4RE512V 0xfff0707f
- +#define MATCH_VL4RE1024V 0x72807007
- +#define MASK_VL4RE1024V 0xfff0707f
- +
- +#define MATCH_VL8RE8V 0xe2800007
- +#define MASK_VL8RE8V 0xfff0707f
- +#define MATCH_VL8RE16V 0xe2805007
- +#define MASK_VL8RE16V 0xfff0707f
- +#define MATCH_VL8RE32V 0xe2806007
- +#define MASK_VL8RE32V 0xfff0707f
- +#define MATCH_VL8RE64V 0xe2807007
- +#define MASK_VL8RE64V 0xfff0707f
- +#define MATCH_VL8RE128V 0xf2800007
- +#define MASK_VL8RE128V 0xfff0707f
- +#define MATCH_VL8RE256V 0xf2805007
- +#define MASK_VL8RE256V 0xfff0707f
- +#define MATCH_VL8RE512V 0xf2806007
- +#define MASK_VL8RE512V 0xfff0707f
- +#define MATCH_VL8RE1024V 0xf2807007
- +#define MASK_VL8RE1024V 0xfff0707f
-
- #define MATCH_VS1RV 0x02800027
- #define MASK_VS1RV 0xfff0707f
- diff --git a/opcodes/riscv-opc.c b/opcodes/riscv-opc.c
- index cb89f59208..208d3ce31b 100644
- --- a/opcodes/riscv-opc.c
- +++ b/opcodes/riscv-opc.c
- @@ -1550,10 +1550,45 @@ const struct riscv_opcode riscv_opcodes[] =
- {"vlseg7e1024ff.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s)Vm", MATCH_VLSEG7E1024FFV, MASK_VLSEG7E1024FFV, match_vd_neq_vm, INSN_DREF },
- {"vlseg8e1024ff.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s)Vm", MATCH_VLSEG8E1024FFV, MASK_VLSEG8E1024FFV, match_vd_neq_vm, INSN_DREF },
-
- -{"vl1r.v", 0, INSN_CLASS_V, "Vd,0(s)", MATCH_VL1RV, MASK_VL1RV, match_opcode, INSN_DREF },
- -{"vl2r.v", 0, INSN_CLASS_V, "Vd,0(s)", MATCH_VL2RV, MASK_VL2RV, match_opcode, INSN_DREF },
- -{"vl4r.v", 0, INSN_CLASS_V, "Vd,0(s)", MATCH_VL4RV, MASK_VL4RV, match_opcode, INSN_DREF },
- -{"vl8r.v", 0, INSN_CLASS_V, "Vd,0(s)", MATCH_VL8RV, MASK_VL8RV, match_opcode, INSN_DREF },
- +{"vl1r.v", 0, INSN_CLASS_V, "Vd,0(s)", MATCH_VL1RE8V, MASK_VL1RE8V, match_opcode, INSN_DREF|INSN_ALIAS },
- +{"vl1re8.v", 0, INSN_CLASS_V, "Vd,0(s)", MATCH_VL1RE8V, MASK_VL1RE8V, match_opcode, INSN_DREF },
- +{"vl1re16.v", 0, INSN_CLASS_V, "Vd,0(s)", MATCH_VL1RE16V, MASK_VL1RE16V, match_opcode, INSN_DREF },
- +{"vl1re32.v", 0, INSN_CLASS_V, "Vd,0(s)", MATCH_VL1RE32V, MASK_VL1RE32V, match_opcode, INSN_DREF },
- +{"vl1re64.v", 0, INSN_CLASS_V, "Vd,0(s)", MATCH_VL1RE64V, MASK_VL1RE64V, match_opcode, INSN_DREF },
- +{"vl1re128.v", 0, INSN_CLASS_V, "Vd,0(s)", MATCH_VL1RE128V, MASK_VL1RE128V, match_opcode, INSN_DREF },
- +{"vl1re256.v", 0, INSN_CLASS_V, "Vd,0(s)", MATCH_VL1RE256V, MASK_VL1RE256V, match_opcode, INSN_DREF },
- +{"vl1re512.v", 0, INSN_CLASS_V, "Vd,0(s)", MATCH_VL1RE512V, MASK_VL1RE512V, match_opcode, INSN_DREF },
- +{"vl1re1024.v", 0, INSN_CLASS_V, "Vd,0(s)", MATCH_VL1RE1024V, MASK_VL1RE1024V, match_opcode, INSN_DREF },
- +
- +{"vl2r.v", 0, INSN_CLASS_V, "Vd,0(s)", MATCH_VL2RE8V, MASK_VL2RE8V, match_opcode, INSN_DREF|INSN_ALIAS },
- +{"vl2re8.v", 0, INSN_CLASS_V, "Vd,0(s)", MATCH_VL2RE8V, MASK_VL2RE8V, match_opcode, INSN_DREF },
- +{"vl2re16.v", 0, INSN_CLASS_V, "Vd,0(s)", MATCH_VL2RE16V, MASK_VL2RE16V, match_opcode, INSN_DREF },
- +{"vl2re32.v", 0, INSN_CLASS_V, "Vd,0(s)", MATCH_VL2RE32V, MASK_VL2RE32V, match_opcode, INSN_DREF },
- +{"vl2re64.v", 0, INSN_CLASS_V, "Vd,0(s)", MATCH_VL2RE64V, MASK_VL2RE64V, match_opcode, INSN_DREF },
- +{"vl2re128.v", 0, INSN_CLASS_V, "Vd,0(s)", MATCH_VL2RE128V, MASK_VL2RE128V, match_opcode, INSN_DREF },
- +{"vl2re256.v", 0, INSN_CLASS_V, "Vd,0(s)", MATCH_VL2RE256V, MASK_VL2RE256V, match_opcode, INSN_DREF },
- +{"vl2re512.v", 0, INSN_CLASS_V, "Vd,0(s)", MATCH_VL2RE512V, MASK_VL2RE512V, match_opcode, INSN_DREF },
- +{"vl2re1024.v", 0, INSN_CLASS_V, "Vd,0(s)", MATCH_VL2RE1024V, MASK_VL2RE1024V, match_opcode, INSN_DREF },
- +
- +{"vl4r.v", 0, INSN_CLASS_V, "Vd,0(s)", MATCH_VL4RE8V, MASK_VL4RE8V, match_opcode, INSN_DREF|INSN_ALIAS },
- +{"vl4re8.v", 0, INSN_CLASS_V, "Vd,0(s)", MATCH_VL4RE8V, MASK_VL4RE8V, match_opcode, INSN_DREF },
- +{"vl4re16.v", 0, INSN_CLASS_V, "Vd,0(s)", MATCH_VL4RE16V, MASK_VL4RE16V, match_opcode, INSN_DREF },
- +{"vl4re32.v", 0, INSN_CLASS_V, "Vd,0(s)", MATCH_VL4RE32V, MASK_VL4RE32V, match_opcode, INSN_DREF },
- +{"vl4re64.v", 0, INSN_CLASS_V, "Vd,0(s)", MATCH_VL4RE64V, MASK_VL4RE64V, match_opcode, INSN_DREF },
- +{"vl4re128.v", 0, INSN_CLASS_V, "Vd,0(s)", MATCH_VL4RE128V, MASK_VL4RE128V, match_opcode, INSN_DREF },
- +{"vl4re256.v", 0, INSN_CLASS_V, "Vd,0(s)", MATCH_VL4RE256V, MASK_VL4RE256V, match_opcode, INSN_DREF },
- +{"vl4re512.v", 0, INSN_CLASS_V, "Vd,0(s)", MATCH_VL4RE512V, MASK_VL4RE512V, match_opcode, INSN_DREF },
- +{"vl4re1024.v", 0, INSN_CLASS_V, "Vd,0(s)", MATCH_VL4RE1024V, MASK_VL4RE1024V, match_opcode, INSN_DREF },
- +
- +{"vl8r.v", 0, INSN_CLASS_V, "Vd,0(s)", MATCH_VL8RE8V, MASK_VL8RE8V, match_opcode, INSN_DREF|INSN_ALIAS },
- +{"vl8re8.v", 0, INSN_CLASS_V, "Vd,0(s)", MATCH_VL8RE8V, MASK_VL8RE8V, match_opcode, INSN_DREF },
- +{"vl8re16.v", 0, INSN_CLASS_V, "Vd,0(s)", MATCH_VL8RE16V, MASK_VL8RE16V, match_opcode, INSN_DREF },
- +{"vl8re32.v", 0, INSN_CLASS_V, "Vd,0(s)", MATCH_VL8RE32V, MASK_VL8RE32V, match_opcode, INSN_DREF },
- +{"vl8re64.v", 0, INSN_CLASS_V, "Vd,0(s)", MATCH_VL8RE64V, MASK_VL8RE64V, match_opcode, INSN_DREF },
- +{"vl8re128.v", 0, INSN_CLASS_V, "Vd,0(s)", MATCH_VL8RE128V, MASK_VL8RE128V, match_opcode, INSN_DREF },
- +{"vl8re256.v", 0, INSN_CLASS_V, "Vd,0(s)", MATCH_VL8RE256V, MASK_VL8RE256V, match_opcode, INSN_DREF },
- +{"vl8re512.v", 0, INSN_CLASS_V, "Vd,0(s)", MATCH_VL8RE512V, MASK_VL8RE512V, match_opcode, INSN_DREF },
- +{"vl8re1024.v", 0, INSN_CLASS_V, "Vd,0(s)", MATCH_VL8RE1024V, MASK_VL8RE1024V, match_opcode, INSN_DREF },
-
- {"vs1r.v", 0, INSN_CLASS_V, "Vd,0(s)", MATCH_VS1RV, MASK_VS1RV, match_opcode, INSN_DREF },
- {"vs2r.v", 0, INSN_CLASS_V, "Vd,0(s)", MATCH_VS2RV, MASK_VS2RV, match_opcode, INSN_DREF },
- --
- 2.33.0
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