0036-Initial-support-for-RISC-V-Bitmanip-Spec-0.92.patch 49 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233234235236237238239240241242243244245246247248249250251252253254255256257258259260261262263264265266267268269270271272273274275276277278279280281282283284285286287288289290291292293294295296297298299300301302303304305306307308309310311312313314315316317318319320321322323324325326327328329330331332333334335336337338339340341342343344345346347348349350351352353354355356357358359360361362363364365366367368369370371372373374375376377378379380381382383384385386387388389390391392393394395396397398399400401402403404405406407408409410411412413414415416417418419420421422423424425426427428429430431432433434435436437438439440441442443444445446447448449450451452453454455456457458459460461462463464465466467468469470471472473474475476477478479480481482483484485486487488489490491492493494495496497498499500501502503504505506507508509510511512513514515516517518519520521522523524525526527528529530531532533534535536537538539540541542543544545546547548549550551552553554555556557558559560561562563564565566567568569570571572573574575576577578579580581582583584585586587588589590591592593594595596597598599600601602603604605606607608609610611612613614615616617618619620621622623624625626627628629630631632633634635636637638639640641642643644645646647648649650651652653654655656657658659660661662663664665666667668669670671672673674675676677678679680681682683684685686687688689690691692693694695696697698699700701702703704705706707708709710711712713714715716717718719720721722723724725726727728729730731732733734735736737738739740741742743744745746747748749750751752753754755756757758759760761762763764765766767768769770771772773774775776777778779780781782783784785786787788789790791792793794795796797798799800801802803804805806807808809810811812813814815816817818819820821822823824825826827828829830831832833834835836837838839840841842843844845846847848849850851852853854855856857858859860861862863864865866867868869870871872873874875876877878879880881882883884885886887888889890891892893894895896897898899900901902903904905906907908909910911912913914915916917918919920921922923924925926927928929930931932933934935936937938939940941942943944945946947948949950951952953954955956957958959960961962963964965966967968969970971972973974975976977978979980981982983984985986987988989990991992993994995
  1. From e69ed899f726c9d15c1afeab89de7a8fe2009156 Mon Sep 17 00:00:00 2001
  2. From: Clifford Wolf <clifford@clifford.at>
  3. Date: Sun, 11 Aug 2019 14:33:43 +0200
  4. Subject: [PATCH 36/48] Initial support for RISC-V Bitmanip Spec 0.92
  5. Signed-off-by: Clifford Wolf <clifford@clifford.at>
  6. ---
  7. gas/config/tc-riscv.c | 149 ++++++++
  8. include/opcode/riscv-opc.h | 318 ++++++++++++++++++
  9. include/opcode/riscv.h | 16 +
  10. .../ld-riscv-elf/attr-dupl-arch-z-failed-01.d | 3 +
  11. .../ld-riscv-elf/attr-dupl-arch-z-failed-01.s | 1 +
  12. .../attr-merge-arch-z-failed-01.d | 5 +
  13. .../attr-merge-arch-z-failed-01a.s | 1 +
  14. .../attr-merge-arch-z-failed-01b.s | 1 +
  15. .../attr-order-arch-z-failed-01.d | 3 +
  16. .../attr-order-arch-z-failed-01.s | 1 +
  17. .../attr-order-arch-z-failed-02.d | 3 +
  18. .../attr-order-arch-z-failed-02.s | 1 +
  19. .../attr-tooshort-arch-z-failed-01.d | 3 +
  20. .../attr-tooshort-arch-z-failed-01.s | 1 +
  21. .../attr-unknown-arch-z-failed-01.d | 3 +
  22. .../attr-unknown-arch-z-failed-01.s | 1 +
  23. ld/testsuite/ld-riscv-elf/ld-riscv-elf.exp | 6 +
  24. opcodes/riscv-dis.c | 7 +
  25. opcodes/riscv-opc.c | 214 ++++++++++++
  26. 19 files changed, 737 insertions(+)
  27. create mode 100644 ld/testsuite/ld-riscv-elf/attr-dupl-arch-z-failed-01.d
  28. create mode 100644 ld/testsuite/ld-riscv-elf/attr-dupl-arch-z-failed-01.s
  29. create mode 100644 ld/testsuite/ld-riscv-elf/attr-merge-arch-z-failed-01.d
  30. create mode 100644 ld/testsuite/ld-riscv-elf/attr-merge-arch-z-failed-01a.s
  31. create mode 100644 ld/testsuite/ld-riscv-elf/attr-merge-arch-z-failed-01b.s
  32. create mode 100644 ld/testsuite/ld-riscv-elf/attr-order-arch-z-failed-01.d
  33. create mode 100644 ld/testsuite/ld-riscv-elf/attr-order-arch-z-failed-01.s
  34. create mode 100644 ld/testsuite/ld-riscv-elf/attr-order-arch-z-failed-02.d
  35. create mode 100644 ld/testsuite/ld-riscv-elf/attr-order-arch-z-failed-02.s
  36. create mode 100644 ld/testsuite/ld-riscv-elf/attr-tooshort-arch-z-failed-01.d
  37. create mode 100644 ld/testsuite/ld-riscv-elf/attr-tooshort-arch-z-failed-01.s
  38. create mode 100644 ld/testsuite/ld-riscv-elf/attr-unknown-arch-z-failed-01.d
  39. create mode 100644 ld/testsuite/ld-riscv-elf/attr-unknown-arch-z-failed-01.s
  40. diff --git a/gas/config/tc-riscv.c b/gas/config/tc-riscv.c
  41. index 44e9358dd7..b53442b8b4 100644
  42. --- a/gas/config/tc-riscv.c
  43. +++ b/gas/config/tc-riscv.c
  44. @@ -260,6 +260,40 @@ riscv_multi_subset_supports (enum riscv_insn_class insn_class)
  45. case INSN_CLASS_V_AND_ZVQMAC:
  46. return riscv_subset_supports ("v") && riscv_subset_supports ("zvqmac");
  47. + case INSN_CLASS_B_OR_ZBB:
  48. + return riscv_subset_supports ("b") || riscv_subset_supports ("zbb");
  49. +
  50. + case INSN_CLASS_B_OR_ZBA:
  51. + return riscv_subset_supports ("b") || riscv_subset_supports ("zba");
  52. +
  53. + case INSN_CLASS_B_OR_ZBC:
  54. + return riscv_subset_supports ("b") || riscv_subset_supports ("zbc");
  55. +
  56. + case INSN_CLASS_B_OR_ZBE:
  57. + return riscv_subset_supports ("b") || riscv_subset_supports ("zbe");
  58. +
  59. + case INSN_CLASS_B_OR_ZBF:
  60. + return riscv_subset_supports ("b") || riscv_subset_supports ("zbf");
  61. +
  62. + case INSN_CLASS_B_OR_ZBM:
  63. + return riscv_subset_supports ("b") || riscv_subset_supports ("zbm");
  64. +
  65. + case INSN_CLASS_B_OR_ZBP:
  66. + return riscv_subset_supports ("b") || riscv_subset_supports ("zbp");
  67. +
  68. + case INSN_CLASS_B_OR_ZBR:
  69. + return riscv_subset_supports ("b") || riscv_subset_supports ("zbr");
  70. +
  71. + case INSN_CLASS_B_OR_ZBS:
  72. + return riscv_subset_supports ("b") || riscv_subset_supports ("zbs");
  73. +
  74. + case INSN_CLASS_B_OR_ZBT:
  75. + return riscv_subset_supports ("b") || riscv_subset_supports ("zbt");
  76. +
  77. + case INSN_CLASS_B_OR_ZBB_OR_ZBP:
  78. + return riscv_subset_supports ("b") || riscv_subset_supports ("zbb")
  79. + || riscv_subset_supports ("zbp");
  80. +
  81. default:
  82. as_fatal ("Unreachable");
  83. return FALSE;
  84. @@ -948,6 +982,7 @@ validate_riscv_insn (const struct riscv_opcode *opc, int length)
  85. case '(': break;
  86. case ')': break;
  87. case '<': USE_BITS (OP_MASK_SHAMTW, OP_SH_SHAMTW); break;
  88. + case '|': USE_BITS (OP_MASK_SHAMTW, OP_SH_SHAMTW); break;
  89. case '>': USE_BITS (OP_MASK_SHAMT, OP_SH_SHAMT); break;
  90. case 'A': break;
  91. case 'D': USE_BITS (OP_MASK_RD, OP_SH_RD); break;
  92. @@ -1250,6 +1285,15 @@ macro_build (expressionS *ep, const char *name, const char *fmt, ...)
  93. INSERT_OPERAND (RS2, insn, va_arg (args, int));
  94. continue;
  95. + case 'r':
  96. + INSERT_OPERAND (RS3, insn, va_arg (args, int));
  97. + continue;
  98. +
  99. + case '<':
  100. + case '|':
  101. + INSERT_OPERAND (SHAMTW, insn, va_arg (args, int));
  102. + continue;
  103. +
  104. case '>':
  105. INSERT_OPERAND (SHAMT, insn, va_arg (args, int));
  106. continue;
  107. @@ -1465,6 +1509,86 @@ load_const (int reg, expressionS *ep)
  108. }
  109. }
  110. +/* Immediate rotate left shift via right shift. */
  111. +
  112. +static void
  113. +rotate_left (int rd, int rs, unsigned shamt, unsigned this_xlen)
  114. +{
  115. + shamt = (this_xlen-1) & -shamt;
  116. +
  117. + if (this_xlen == xlen)
  118. + macro_build (NULL, "rori", "d,s,>", rd, rs, shamt);
  119. + else if (this_xlen == 32)
  120. + macro_build (NULL, "roriw", "d,s,<", rd, rs, shamt);
  121. + else
  122. + as_fatal (_("internal error: bad left shift xlen %d"), this_xlen);
  123. +}
  124. +
  125. +static void
  126. +funnel_left (int rd, int rs1, int rs3, unsigned shamt, unsigned this_xlen)
  127. +{
  128. + shamt = (this_xlen-1) & -shamt;
  129. +
  130. + if (this_xlen == xlen)
  131. + macro_build (NULL, "fsri", "d,s,r,>", rd, rs3, rs1, shamt);
  132. + else if (this_xlen == 32)
  133. + macro_build (NULL, "fsriw", "d,s,r,<", rd, rs3, rs1, shamt);
  134. + else
  135. + as_fatal (_("internal error: bad left shift xlen %d"), this_xlen);
  136. +}
  137. +
  138. +static void
  139. +perm (int rd, int rs1, const char *op)
  140. +{
  141. + const char *insn = NULL;
  142. + const char *p = op;
  143. + int shamt = 0;
  144. + int shfl = 0;
  145. +
  146. + switch (p[0])
  147. + {
  148. + case 'r': insn = "grevi"; shamt = xlen-1; p += 3; break;
  149. + case 'o': insn = "gorci"; shamt = xlen-1; p += 3; break;
  150. + case 'z': insn = "shfli"; shamt = xlen/2-1; p += 3; shfl = 1; break;
  151. + case 'u': insn = "unshfli"; shamt = xlen/2-1; p += 5; shfl = 1; break;
  152. + default: as_fatal (_("internal error: bad permutation pseudo-instruction %s"), op);
  153. + }
  154. +
  155. + switch (p[0])
  156. + {
  157. + case '2': shamt &= shamt << 1; p += 1; break;
  158. + case '4': shamt &= shamt << 2; p += 1; break;
  159. + case '8': shamt &= shamt << 3; p += 1; break;
  160. + case '1': shamt &= shamt << 4; p += 2; break;
  161. + case '3': shamt &= shamt << 5; p += 2;
  162. + }
  163. +
  164. + if (p[0])
  165. + {
  166. + if (shfl)
  167. + switch (p[1])
  168. + {
  169. + case 'w': shamt &= 15; break;
  170. + case 'h': shamt &= 7; break;
  171. + case 'b': shamt &= 3; break;
  172. + case 'n': shamt &= 1; break;
  173. + default: as_fatal (_("internal error: bad permutation pseudo-instruction %s"), op);
  174. + }
  175. + else
  176. + switch (p[1])
  177. + {
  178. + case 'w': shamt &= 31; break;
  179. + case 'h': shamt &= 15; break;
  180. + case 'b': shamt &= 7; break;
  181. + case 'n': shamt &= 3; break;
  182. + case 'p': shamt &= 1; break;
  183. + default: as_fatal (_("internal error: bad permutation pseudo-instruction %s"), op);
  184. + }
  185. + }
  186. +
  187. + macro_build (NULL, insn, "d,s,>", rd, rs1, shamt);
  188. +}
  189. +
  190. /* Expand RISC-V Vector macros into one of more instructions. */
  191. static void
  192. @@ -1563,6 +1687,8 @@ macro (struct riscv_cl_insn *ip, expressionS *imm_expr,
  193. int rd = (ip->insn_opcode >> OP_SH_RD) & OP_MASK_RD;
  194. int rs1 = (ip->insn_opcode >> OP_SH_RS1) & OP_MASK_RS1;
  195. int rs2 = (ip->insn_opcode >> OP_SH_RS2) & OP_MASK_RS2;
  196. + int rs3 = (ip->insn_opcode >> OP_SH_RS3) & OP_MASK_RS3;
  197. + int shamt = (ip->insn_opcode >> OP_SH_SHAMT) & OP_MASK_SHAMT;
  198. int mask = ip->insn_mo->mask;
  199. switch (mask)
  200. @@ -1571,6 +1697,18 @@ macro (struct riscv_cl_insn *ip, expressionS *imm_expr,
  201. load_const (rd, imm_expr);
  202. break;
  203. + case M_RL:
  204. + rotate_left (rd, rs1, shamt, ip->insn_mo->xlen_requirement ? ip->insn_mo->xlen_requirement/2 : xlen);
  205. + break;
  206. +
  207. + case M_FL:
  208. + funnel_left (rd, rs1, rs3, shamt, ip->insn_mo->xlen_requirement ? ip->insn_mo->xlen_requirement/2 : xlen);
  209. + break;
  210. +
  211. + case M_PERM:
  212. + perm (rd, rs1, ip->insn_mo->name);
  213. + break;
  214. +
  215. case M_LA:
  216. case M_LLA:
  217. /* Load the address of a symbol into a register. */
  218. @@ -2448,6 +2586,17 @@ riscv_ip (char *str, struct riscv_cl_insn *ip, expressionS *imm_expr,
  219. s = expr_end;
  220. continue;
  221. + case '|': /* Shift amount, 0 - (XLEN/2-1). */
  222. + my_getExpression (imm_expr, s);
  223. + check_absolute_expr (ip, imm_expr, FALSE);
  224. + if ((unsigned long) imm_expr->X_add_number >= xlen/2)
  225. + as_bad (_("Improper shift amount (%lu)"),
  226. + (unsigned long) imm_expr->X_add_number);
  227. + INSERT_OPERAND (SHAMTW, *ip, imm_expr->X_add_number);
  228. + imm_expr->X_op = O_absent;
  229. + s = expr_end;
  230. + continue;
  231. +
  232. case '>': /* Shift amount, 0 - (XLEN-1). */
  233. my_getExpression (imm_expr, s);
  234. check_absolute_expr (ip, imm_expr, FALSE);
  235. diff --git a/include/opcode/riscv-opc.h b/include/opcode/riscv-opc.h
  236. index 545bda3ed4..426db0ca5f 100644
  237. --- a/include/opcode/riscv-opc.h
  238. +++ b/include/opcode/riscv-opc.h
  239. @@ -189,6 +189,218 @@
  240. #define MASK_REMW 0xfe00707f
  241. #define MATCH_REMUW 0x200703b
  242. #define MASK_REMUW 0xfe00707f
  243. +#define MATCH_ANDN 0x40007033
  244. +#define MASK_ANDN 0xfe00707f
  245. +#define MATCH_ORN 0x40006033
  246. +#define MASK_ORN 0xfe00707f
  247. +#define MATCH_XNOR 0x40004033
  248. +#define MASK_XNOR 0xfe00707f
  249. +#define MATCH_SLO 0x20001033
  250. +#define MASK_SLO 0xfe00707f
  251. +#define MATCH_SRO 0x20005033
  252. +#define MASK_SRO 0xfe00707f
  253. +#define MATCH_ROL 0x60001033
  254. +#define MASK_ROL 0xfe00707f
  255. +#define MATCH_ROR 0x60005033
  256. +#define MASK_ROR 0xfe00707f
  257. +#define MATCH_SBCLR 0x48001033
  258. +#define MASK_SBCLR 0xfe00707f
  259. +#define MATCH_SBSET 0x28001033
  260. +#define MASK_SBSET 0xfe00707f
  261. +#define MATCH_SBINV 0x68001033
  262. +#define MASK_SBINV 0xfe00707f
  263. +#define MATCH_SBEXT 0x48005033
  264. +#define MASK_SBEXT 0xfe00707f
  265. +#define MATCH_GORC 0x28005033
  266. +#define MASK_GORC 0xfe00707f
  267. +#define MATCH_GREV 0x68005033
  268. +#define MASK_GREV 0xfe00707f
  269. +#define MATCH_SLOI 0x20001013
  270. +#define MASK_SLOI 0xfc00707f
  271. +#define MATCH_SROI 0x20005013
  272. +#define MASK_SROI 0xfc00707f
  273. +#define MATCH_RORI 0x60005013
  274. +#define MASK_RORI 0xfc00707f
  275. +#define MATCH_SBCLRI 0x48001013
  276. +#define MASK_SBCLRI 0xfc00707f
  277. +#define MATCH_SBSETI 0x28001013
  278. +#define MASK_SBSETI 0xfc00707f
  279. +#define MATCH_SBINVI 0x68001013
  280. +#define MASK_SBINVI 0xfc00707f
  281. +#define MATCH_SBEXTI 0x48005013
  282. +#define MASK_SBEXTI 0xfc00707f
  283. +#define MATCH_GORCI 0x28005013
  284. +#define MASK_GORCI 0xfc00707f
  285. +#define MATCH_GREVI 0x68005013
  286. +#define MASK_GREVI 0xfc00707f
  287. +#define MATCH_CMIX 0x6001033
  288. +#define MASK_CMIX 0x600707f
  289. +#define MATCH_CMOV 0x6005033
  290. +#define MASK_CMOV 0x600707f
  291. +#define MATCH_FSL 0x4001033
  292. +#define MASK_FSL 0x600707f
  293. +#define MATCH_FSR 0x4005033
  294. +#define MASK_FSR 0x600707f
  295. +#define MATCH_FSRI 0x4005013
  296. +#define MASK_FSRI 0x400707f
  297. +#define MATCH_CLZ 0x60001013
  298. +#define MASK_CLZ 0xfff0707f
  299. +#define MATCH_CTZ 0x60101013
  300. +#define MASK_CTZ 0xfff0707f
  301. +#define MATCH_PCNT 0x60201013
  302. +#define MASK_PCNT 0xfff0707f
  303. +#define MATCH_SEXT_B 0x60401013
  304. +#define MASK_SEXT_B 0xfff0707f
  305. +#define MATCH_SEXT_H 0x60501013
  306. +#define MASK_SEXT_H 0xfff0707f
  307. +#define MATCH_CRC32_B 0x61001013
  308. +#define MASK_CRC32_B 0xfff0707f
  309. +#define MATCH_CRC32_H 0x61101013
  310. +#define MASK_CRC32_H 0xfff0707f
  311. +#define MATCH_CRC32_W 0x61201013
  312. +#define MASK_CRC32_W 0xfff0707f
  313. +#define MATCH_CRC32C_B 0x61801013
  314. +#define MASK_CRC32C_B 0xfff0707f
  315. +#define MATCH_CRC32C_H 0x61901013
  316. +#define MASK_CRC32C_H 0xfff0707f
  317. +#define MATCH_CRC32C_W 0x61a01013
  318. +#define MASK_CRC32C_W 0xfff0707f
  319. +#define MATCH_SH1ADD 0x20002033
  320. +#define MASK_SH1ADD 0xfe00707f
  321. +#define MATCH_SH2ADD 0x20004033
  322. +#define MASK_SH2ADD 0xfe00707f
  323. +#define MATCH_SH3ADD 0x20006033
  324. +#define MASK_SH3ADD 0xfe00707f
  325. +#define MATCH_CLMUL 0xa001033
  326. +#define MASK_CLMUL 0xfe00707f
  327. +#define MATCH_CLMULR 0xa002033
  328. +#define MASK_CLMULR 0xfe00707f
  329. +#define MATCH_CLMULH 0xa003033
  330. +#define MASK_CLMULH 0xfe00707f
  331. +#define MATCH_MIN 0xa004033
  332. +#define MASK_MIN 0xfe00707f
  333. +#define MATCH_MAX 0xa005033
  334. +#define MASK_MAX 0xfe00707f
  335. +#define MATCH_MINU 0xa006033
  336. +#define MASK_MINU 0xfe00707f
  337. +#define MATCH_MAXU 0xa007033
  338. +#define MASK_MAXU 0xfe00707f
  339. +#define MATCH_SHFL 0x8001033
  340. +#define MASK_SHFL 0xfe00707f
  341. +#define MATCH_UNSHFL 0x8005033
  342. +#define MASK_UNSHFL 0xfe00707f
  343. +#define MATCH_BEXT 0x8006033
  344. +#define MASK_BEXT 0xfe00707f
  345. +#define MATCH_BDEP 0x48006033
  346. +#define MASK_BDEP 0xfe00707f
  347. +#define MATCH_PACK 0x8004033
  348. +#define MASK_PACK 0xfe00707f
  349. +#define MATCH_PACKU 0x48004033
  350. +#define MASK_PACKU 0xfe00707f
  351. +#define MATCH_PACKH 0x8007033
  352. +#define MASK_PACKH 0xfe00707f
  353. +#define MATCH_BFP 0x48007033
  354. +#define MASK_BFP 0xfe00707f
  355. +#define MATCH_SHFLI 0x8001013
  356. +#define MASK_SHFLI 0xfe00707f
  357. +#define MATCH_UNSHFLI 0x8005013
  358. +#define MASK_UNSHFLI 0xfe00707f
  359. +#define MATCH_BMATFLIP 0x60301013
  360. +#define MASK_BMATFLIP 0xfff0707f
  361. +#define MATCH_CRC32_D 0x61301013
  362. +#define MASK_CRC32_D 0xfff0707f
  363. +#define MATCH_CRC32C_D 0x61b01013
  364. +#define MASK_CRC32C_D 0xfff0707f
  365. +#define MATCH_BMATOR 0x8003033
  366. +#define MASK_BMATOR 0xfe00707f
  367. +#define MATCH_BMATXOR 0x48003033
  368. +#define MASK_BMATXOR 0xfe00707f
  369. +#define MATCH_ADDIWU 0x401b
  370. +#define MASK_ADDIWU 0x707f
  371. +#define MATCH_SLLIU_W 0x800101b
  372. +#define MASK_SLLIU_W 0xfc00707f
  373. +#define MATCH_ADDWU 0xa00003b
  374. +#define MASK_ADDWU 0xfe00707f
  375. +#define MATCH_SUBWU 0x4a00003b
  376. +#define MASK_SUBWU 0xfe00707f
  377. +#define MATCH_ADDU_W 0x800003b
  378. +#define MASK_ADDU_W 0xfe00707f
  379. +#define MATCH_SUBU_W 0x4800003b
  380. +#define MASK_SUBU_W 0xfe00707f
  381. +#define MATCH_SLOW 0x2000103b
  382. +#define MASK_SLOW 0xfe00707f
  383. +#define MATCH_SROW 0x2000503b
  384. +#define MASK_SROW 0xfe00707f
  385. +#define MATCH_ROLW 0x6000103b
  386. +#define MASK_ROLW 0xfe00707f
  387. +#define MATCH_RORW 0x6000503b
  388. +#define MASK_RORW 0xfe00707f
  389. +#define MATCH_SBCLRW 0x4800103b
  390. +#define MASK_SBCLRW 0xfe00707f
  391. +#define MATCH_SBSETW 0x2800103b
  392. +#define MASK_SBSETW 0xfe00707f
  393. +#define MATCH_SBINVW 0x6800103b
  394. +#define MASK_SBINVW 0xfe00707f
  395. +#define MATCH_SBEXTW 0x4800503b
  396. +#define MASK_SBEXTW 0xfe00707f
  397. +#define MATCH_GORCW 0x2800503b
  398. +#define MASK_GORCW 0xfe00707f
  399. +#define MATCH_GREVW 0x6800503b
  400. +#define MASK_GREVW 0xfe00707f
  401. +#define MATCH_SLOIW 0x2000101b
  402. +#define MASK_SLOIW 0xfe00707f
  403. +#define MATCH_SROIW 0x2000501b
  404. +#define MASK_SROIW 0xfe00707f
  405. +#define MATCH_RORIW 0x6000501b
  406. +#define MASK_RORIW 0xfe00707f
  407. +#define MATCH_SBCLRIW 0x4800101b
  408. +#define MASK_SBCLRIW 0xfe00707f
  409. +#define MATCH_SBSETIW 0x2800101b
  410. +#define MASK_SBSETIW 0xfe00707f
  411. +#define MATCH_SBINVIW 0x6800101b
  412. +#define MASK_SBINVIW 0xfe00707f
  413. +#define MATCH_GORCIW 0x2800501b
  414. +#define MASK_GORCIW 0xfe00707f
  415. +#define MATCH_GREVIW 0x6800501b
  416. +#define MASK_GREVIW 0xfe00707f
  417. +#define MATCH_FSLW 0x400103b
  418. +#define MASK_FSLW 0x600707f
  419. +#define MATCH_FSRW 0x400503b
  420. +#define MASK_FSRW 0x600707f
  421. +#define MATCH_FSRIW 0x400501b
  422. +#define MASK_FSRIW 0x600707f
  423. +#define MATCH_CLZW 0x6000101b
  424. +#define MASK_CLZW 0xfff0707f
  425. +#define MATCH_CTZW 0x6010101b
  426. +#define MASK_CTZW 0xfff0707f
  427. +#define MATCH_PCNTW 0x6020101b
  428. +#define MASK_PCNTW 0xfff0707f
  429. +#define MATCH_SH1ADDU_W 0x2000203b
  430. +#define MASK_SH1ADDU_W 0xfe00707f
  431. +#define MATCH_SH2ADDU_W 0x2000403b
  432. +#define MASK_SH2ADDU_W 0xfe00707f
  433. +#define MATCH_SH3ADDU_W 0x2000603b
  434. +#define MASK_SH3ADDU_W 0xfe00707f
  435. +#define MATCH_CLMULW 0xa00103b
  436. +#define MASK_CLMULW 0xfe00707f
  437. +#define MATCH_CLMULRW 0xa00203b
  438. +#define MASK_CLMULRW 0xfe00707f
  439. +#define MATCH_CLMULHW 0xa00303b
  440. +#define MASK_CLMULHW 0xfe00707f
  441. +#define MATCH_SHFLW 0x800103b
  442. +#define MASK_SHFLW 0xfe00707f
  443. +#define MATCH_UNSHFLW 0x800503b
  444. +#define MASK_UNSHFLW 0xfe00707f
  445. +#define MATCH_BEXTW 0x800603b
  446. +#define MASK_BEXTW 0xfe00707f
  447. +#define MATCH_BDEPW 0x4800603b
  448. +#define MASK_BDEPW 0xfe00707f
  449. +#define MATCH_PACKW 0x800403b
  450. +#define MASK_PACKW 0xfe00707f
  451. +#define MATCH_PACKUW 0x4800403b
  452. +#define MASK_PACKUW 0xfe00707f
  453. +#define MATCH_BFPW 0x4800703b
  454. +#define MASK_BFPW 0xfe00707f
  455. #define MATCH_AMOADD_W 0x202f
  456. #define MASK_AMOADD_W 0xf800707f
  457. #define MATCH_AMOXOR_W 0x2000202f
  458. @@ -3444,6 +3656,112 @@ DECLARE_INSN(divw, MATCH_DIVW, MASK_DIVW)
  459. DECLARE_INSN(divuw, MATCH_DIVUW, MASK_DIVUW)
  460. DECLARE_INSN(remw, MATCH_REMW, MASK_REMW)
  461. DECLARE_INSN(remuw, MATCH_REMUW, MASK_REMUW)
  462. +DECLARE_INSN(andn, MATCH_ANDN, MASK_ANDN)
  463. +DECLARE_INSN(orn, MATCH_ORN, MASK_ORN)
  464. +DECLARE_INSN(xnor, MATCH_XNOR, MASK_XNOR)
  465. +DECLARE_INSN(slo, MATCH_SLO, MASK_SLO)
  466. +DECLARE_INSN(sro, MATCH_SRO, MASK_SRO)
  467. +DECLARE_INSN(rol, MATCH_ROL, MASK_ROL)
  468. +DECLARE_INSN(ror, MATCH_ROR, MASK_ROR)
  469. +DECLARE_INSN(sbclr, MATCH_SBCLR, MASK_SBCLR)
  470. +DECLARE_INSN(sbset, MATCH_SBSET, MASK_SBSET)
  471. +DECLARE_INSN(sbinv, MATCH_SBINV, MASK_SBINV)
  472. +DECLARE_INSN(sbext, MATCH_SBEXT, MASK_SBEXT)
  473. +DECLARE_INSN(gorc, MATCH_GORC, MASK_GORC)
  474. +DECLARE_INSN(grev, MATCH_GREV, MASK_GREV)
  475. +DECLARE_INSN(sloi, MATCH_SLOI, MASK_SLOI)
  476. +DECLARE_INSN(sroi, MATCH_SROI, MASK_SROI)
  477. +DECLARE_INSN(rori, MATCH_RORI, MASK_RORI)
  478. +DECLARE_INSN(sbclri, MATCH_SBCLRI, MASK_SBCLRI)
  479. +DECLARE_INSN(sbseti, MATCH_SBSETI, MASK_SBSETI)
  480. +DECLARE_INSN(sbinvi, MATCH_SBINVI, MASK_SBINVI)
  481. +DECLARE_INSN(sbexti, MATCH_SBEXTI, MASK_SBEXTI)
  482. +DECLARE_INSN(gorci, MATCH_GORCI, MASK_GORCI)
  483. +DECLARE_INSN(grevi, MATCH_GREVI, MASK_GREVI)
  484. +DECLARE_INSN(cmix, MATCH_CMIX, MASK_CMIX)
  485. +DECLARE_INSN(cmov, MATCH_CMOV, MASK_CMOV)
  486. +DECLARE_INSN(fsl, MATCH_FSL, MASK_FSL)
  487. +DECLARE_INSN(fsr, MATCH_FSR, MASK_FSR)
  488. +DECLARE_INSN(fsri, MATCH_FSRI, MASK_FSRI)
  489. +DECLARE_INSN(clz, MATCH_CLZ, MASK_CLZ)
  490. +DECLARE_INSN(ctz, MATCH_CTZ, MASK_CTZ)
  491. +DECLARE_INSN(pcnt, MATCH_PCNT, MASK_PCNT)
  492. +DECLARE_INSN(sext_b, MATCH_SEXT_B, MASK_SEXT_B)
  493. +DECLARE_INSN(sext_h, MATCH_SEXT_H, MASK_SEXT_H)
  494. +DECLARE_INSN(crc32_b, MATCH_CRC32_B, MASK_CRC32_B)
  495. +DECLARE_INSN(crc32_h, MATCH_CRC32_H, MASK_CRC32_H)
  496. +DECLARE_INSN(crc32_w, MATCH_CRC32_W, MASK_CRC32_W)
  497. +DECLARE_INSN(crc32c_b, MATCH_CRC32C_B, MASK_CRC32C_B)
  498. +DECLARE_INSN(crc32c_h, MATCH_CRC32C_H, MASK_CRC32C_H)
  499. +DECLARE_INSN(crc32c_w, MATCH_CRC32C_W, MASK_CRC32C_W)
  500. +DECLARE_INSN(sh1add, MATCH_SH1ADD, MASK_SH1ADD)
  501. +DECLARE_INSN(sh2add, MATCH_SH2ADD, MASK_SH2ADD)
  502. +DECLARE_INSN(sh3add, MATCH_SH3ADD, MASK_SH3ADD)
  503. +DECLARE_INSN(clmul, MATCH_CLMUL, MASK_CLMUL)
  504. +DECLARE_INSN(clmulr, MATCH_CLMULR, MASK_CLMULR)
  505. +DECLARE_INSN(clmulh, MATCH_CLMULH, MASK_CLMULH)
  506. +DECLARE_INSN(min, MATCH_MIN, MASK_MIN)
  507. +DECLARE_INSN(max, MATCH_MAX, MASK_MAX)
  508. +DECLARE_INSN(minu, MATCH_MINU, MASK_MINU)
  509. +DECLARE_INSN(maxu, MATCH_MAXU, MASK_MAXU)
  510. +DECLARE_INSN(shfl, MATCH_SHFL, MASK_SHFL)
  511. +DECLARE_INSN(unshfl, MATCH_UNSHFL, MASK_UNSHFL)
  512. +DECLARE_INSN(bext, MATCH_BEXT, MASK_BEXT)
  513. +DECLARE_INSN(bdep, MATCH_BDEP, MASK_BDEP)
  514. +DECLARE_INSN(pack, MATCH_PACK, MASK_PACK)
  515. +DECLARE_INSN(packu, MATCH_PACKU, MASK_PACKU)
  516. +DECLARE_INSN(packh, MATCH_PACKH, MASK_PACKH)
  517. +DECLARE_INSN(bfp, MATCH_BFP, MASK_BFP)
  518. +DECLARE_INSN(shfli, MATCH_SHFLI, MASK_SHFLI)
  519. +DECLARE_INSN(unshfli, MATCH_UNSHFLI, MASK_UNSHFLI)
  520. +DECLARE_INSN(bmatflip, MATCH_BMATFLIP, MASK_BMATFLIP)
  521. +DECLARE_INSN(crc32_d, MATCH_CRC32_D, MASK_CRC32_D)
  522. +DECLARE_INSN(crc32c_d, MATCH_CRC32C_D, MASK_CRC32C_D)
  523. +DECLARE_INSN(bmator, MATCH_BMATOR, MASK_BMATOR)
  524. +DECLARE_INSN(bmatxor, MATCH_BMATXOR, MASK_BMATXOR)
  525. +DECLARE_INSN(addiwu, MATCH_ADDIWU, MASK_ADDIWU)
  526. +DECLARE_INSN(slliu_w, MATCH_SLLIU_W, MASK_SLLIU_W)
  527. +DECLARE_INSN(addwu, MATCH_ADDWU, MASK_ADDWU)
  528. +DECLARE_INSN(subwu, MATCH_SUBWU, MASK_SUBWU)
  529. +DECLARE_INSN(addu_w, MATCH_ADDU_W, MASK_ADDU_W)
  530. +DECLARE_INSN(subu_w, MATCH_SUBU_W, MASK_SUBU_W)
  531. +DECLARE_INSN(slow, MATCH_SLOW, MASK_SLOW)
  532. +DECLARE_INSN(srow, MATCH_SROW, MASK_SROW)
  533. +DECLARE_INSN(rolw, MATCH_ROLW, MASK_ROLW)
  534. +DECLARE_INSN(rorw, MATCH_RORW, MASK_RORW)
  535. +DECLARE_INSN(sbclrw, MATCH_SBCLRW, MASK_SBCLRW)
  536. +DECLARE_INSN(sbsetw, MATCH_SBSETW, MASK_SBSETW)
  537. +DECLARE_INSN(sbinvw, MATCH_SBINVW, MASK_SBINVW)
  538. +DECLARE_INSN(sbextw, MATCH_SBEXTW, MASK_SBEXTW)
  539. +DECLARE_INSN(gorcw, MATCH_GORCW, MASK_GORCW)
  540. +DECLARE_INSN(grevw, MATCH_GREVW, MASK_GREVW)
  541. +DECLARE_INSN(sloiw, MATCH_SLOIW, MASK_SLOIW)
  542. +DECLARE_INSN(sroiw, MATCH_SROIW, MASK_SROIW)
  543. +DECLARE_INSN(roriw, MATCH_RORIW, MASK_RORIW)
  544. +DECLARE_INSN(sbclriw, MATCH_SBCLRIW, MASK_SBCLRIW)
  545. +DECLARE_INSN(sbsetiw, MATCH_SBSETIW, MASK_SBSETIW)
  546. +DECLARE_INSN(sbinviw, MATCH_SBINVIW, MASK_SBINVIW)
  547. +DECLARE_INSN(gorciw, MATCH_GORCIW, MASK_GORCIW)
  548. +DECLARE_INSN(greviw, MATCH_GREVIW, MASK_GREVIW)
  549. +DECLARE_INSN(fslw, MATCH_FSLW, MASK_FSLW)
  550. +DECLARE_INSN(fsrw, MATCH_FSRW, MASK_FSRW)
  551. +DECLARE_INSN(fsriw, MATCH_FSRIW, MASK_FSRIW)
  552. +DECLARE_INSN(clzw, MATCH_CLZW, MASK_CLZW)
  553. +DECLARE_INSN(ctzw, MATCH_CTZW, MASK_CTZW)
  554. +DECLARE_INSN(pcntw, MATCH_PCNTW, MASK_PCNTW)
  555. +DECLARE_INSN(sh1addu_w, MATCH_SH1ADDU_W, MASK_SH1ADDU_W)
  556. +DECLARE_INSN(sh2addu_w, MATCH_SH2ADDU_W, MASK_SH2ADDU_W)
  557. +DECLARE_INSN(sh3addu_w, MATCH_SH3ADDU_W, MASK_SH3ADDU_W)
  558. +DECLARE_INSN(clmulw, MATCH_CLMULW, MASK_CLMULW)
  559. +DECLARE_INSN(clmulrw, MATCH_CLMULRW, MASK_CLMULRW)
  560. +DECLARE_INSN(clmulhw, MATCH_CLMULHW, MASK_CLMULHW)
  561. +DECLARE_INSN(shflw, MATCH_SHFLW, MASK_SHFLW)
  562. +DECLARE_INSN(unshflw, MATCH_UNSHFLW, MASK_UNSHFLW)
  563. +DECLARE_INSN(bextw, MATCH_BEXTW, MASK_BEXTW)
  564. +DECLARE_INSN(bdepw, MATCH_BDEPW, MASK_BDEPW)
  565. +DECLARE_INSN(packw, MATCH_PACKW, MASK_PACKW)
  566. +DECLARE_INSN(packuw, MATCH_PACKUW, MASK_PACKUW)
  567. +DECLARE_INSN(bfpw, MATCH_BFPW, MASK_BFPW)
  568. DECLARE_INSN(amoadd_w, MATCH_AMOADD_W, MASK_AMOADD_W)
  569. DECLARE_INSN(amoxor_w, MATCH_AMOXOR_W, MASK_AMOXOR_W)
  570. DECLARE_INSN(amoor_w, MATCH_AMOOR_W, MASK_AMOOR_W)
  571. diff --git a/include/opcode/riscv.h b/include/opcode/riscv.h
  572. index 2e1a665c6b..5303d14998 100644
  573. --- a/include/opcode/riscv.h
  574. +++ b/include/opcode/riscv.h
  575. @@ -390,6 +390,19 @@ enum riscv_insn_class
  576. INSN_CLASS_V_AND_ZVEDIV,
  577. INSN_CLASS_V_OR_ZVLSSEG,
  578. INSN_CLASS_V_AND_ZVQMAC,
  579. +
  580. + INSN_CLASS_B,
  581. + INSN_CLASS_B_OR_ZBT,
  582. + INSN_CLASS_B_OR_ZBR,
  583. + INSN_CLASS_B_OR_ZBB,
  584. + INSN_CLASS_B_OR_ZBA,
  585. + INSN_CLASS_B_OR_ZBC,
  586. + INSN_CLASS_B_OR_ZBE,
  587. + INSN_CLASS_B_OR_ZBF,
  588. + INSN_CLASS_B_OR_ZBM,
  589. + INSN_CLASS_B_OR_ZBP,
  590. + INSN_CLASS_B_OR_ZBS,
  591. + INSN_CLASS_B_OR_ZBB_OR_ZBP
  592. };
  593. /* This structure holds information for a particular instruction. */
  594. @@ -568,6 +581,9 @@ enum
  595. M_LI,
  596. M_VMSGE,
  597. M_VMSGEU,
  598. + M_RL,
  599. + M_FL,
  600. + M_PERM,
  601. M_NUM_MACROS
  602. };
  603. diff --git a/ld/testsuite/ld-riscv-elf/attr-dupl-arch-z-failed-01.d b/ld/testsuite/ld-riscv-elf/attr-dupl-arch-z-failed-01.d
  604. new file mode 100644
  605. index 0000000000..20b4530f0a
  606. --- /dev/null
  607. +++ b/ld/testsuite/ld-riscv-elf/attr-dupl-arch-z-failed-01.d
  608. @@ -0,0 +1,3 @@
  609. +#source: attr-dupl-arch-z-failed-01.s
  610. +#as: -march-attr
  611. +#error: -march=rv32i2p0_zbc_zbc: Duplicate Z ISA extension: 'zbc'
  612. diff --git a/ld/testsuite/ld-riscv-elf/attr-dupl-arch-z-failed-01.s b/ld/testsuite/ld-riscv-elf/attr-dupl-arch-z-failed-01.s
  613. new file mode 100644
  614. index 0000000000..96d67e1833
  615. --- /dev/null
  616. +++ b/ld/testsuite/ld-riscv-elf/attr-dupl-arch-z-failed-01.s
  617. @@ -0,0 +1 @@
  618. + .attribute arch, "rv32i2p0_zbc_zbc"
  619. diff --git a/ld/testsuite/ld-riscv-elf/attr-merge-arch-z-failed-01.d b/ld/testsuite/ld-riscv-elf/attr-merge-arch-z-failed-01.d
  620. new file mode 100644
  621. index 0000000000..d82c1c2868
  622. --- /dev/null
  623. +++ b/ld/testsuite/ld-riscv-elf/attr-merge-arch-z-failed-01.d
  624. @@ -0,0 +1,5 @@
  625. +#source: attr-merge-arch-z-failed-01a.s
  626. +#source: attr-merge-arch-z-failed-01b.s
  627. +#as: -march-attr
  628. +#ld: -r -melf32lriscv
  629. +#error: Mis-matched ISA version for 'zbb' extension. 2.1 vs 2.0
  630. diff --git a/ld/testsuite/ld-riscv-elf/attr-merge-arch-z-failed-01a.s b/ld/testsuite/ld-riscv-elf/attr-merge-arch-z-failed-01a.s
  631. new file mode 100644
  632. index 0000000000..6768e78c52
  633. --- /dev/null
  634. +++ b/ld/testsuite/ld-riscv-elf/attr-merge-arch-z-failed-01a.s
  635. @@ -0,0 +1 @@
  636. + .attribute arch, "rv32i2p0_zbb2p0"
  637. diff --git a/ld/testsuite/ld-riscv-elf/attr-merge-arch-z-failed-01b.s b/ld/testsuite/ld-riscv-elf/attr-merge-arch-z-failed-01b.s
  638. new file mode 100644
  639. index 0000000000..4279973411
  640. --- /dev/null
  641. +++ b/ld/testsuite/ld-riscv-elf/attr-merge-arch-z-failed-01b.s
  642. @@ -0,0 +1 @@
  643. + .attribute arch, "rv32i2p0_zbb2p1"
  644. diff --git a/ld/testsuite/ld-riscv-elf/attr-order-arch-z-failed-01.d b/ld/testsuite/ld-riscv-elf/attr-order-arch-z-failed-01.d
  645. new file mode 100644
  646. index 0000000000..809d8ba607
  647. --- /dev/null
  648. +++ b/ld/testsuite/ld-riscv-elf/attr-order-arch-z-failed-01.d
  649. @@ -0,0 +1,3 @@
  650. +#source: attr-order-arch-z-failed-01.s
  651. +#as: -march-attr
  652. +#error: -march=rv32i2p0_zbc_zbb: Z ISA extension not in alphabetical order: 'zbb' must come before 'zbc'.
  653. diff --git a/ld/testsuite/ld-riscv-elf/attr-order-arch-z-failed-01.s b/ld/testsuite/ld-riscv-elf/attr-order-arch-z-failed-01.s
  654. new file mode 100644
  655. index 0000000000..e31e3766ca
  656. --- /dev/null
  657. +++ b/ld/testsuite/ld-riscv-elf/attr-order-arch-z-failed-01.s
  658. @@ -0,0 +1 @@
  659. + .attribute arch, "rv32i2p0_zbc_zbb"
  660. diff --git a/ld/testsuite/ld-riscv-elf/attr-order-arch-z-failed-02.d b/ld/testsuite/ld-riscv-elf/attr-order-arch-z-failed-02.d
  661. new file mode 100644
  662. index 0000000000..19a5482300
  663. --- /dev/null
  664. +++ b/ld/testsuite/ld-riscv-elf/attr-order-arch-z-failed-02.d
  665. @@ -0,0 +1,3 @@
  666. +#source: attr-order-arch-z-failed-02.s
  667. +#as: -march-attr
  668. +#error: -march=rv32i2p0_xsillyname_zbb: unexpected ISA string at end: zbb
  669. diff --git a/ld/testsuite/ld-riscv-elf/attr-order-arch-z-failed-02.s b/ld/testsuite/ld-riscv-elf/attr-order-arch-z-failed-02.s
  670. new file mode 100644
  671. index 0000000000..b1abe26891
  672. --- /dev/null
  673. +++ b/ld/testsuite/ld-riscv-elf/attr-order-arch-z-failed-02.s
  674. @@ -0,0 +1 @@
  675. + .attribute arch, "rv32i2p0_xsillyname_zbb"
  676. diff --git a/ld/testsuite/ld-riscv-elf/attr-tooshort-arch-z-failed-01.d b/ld/testsuite/ld-riscv-elf/attr-tooshort-arch-z-failed-01.d
  677. new file mode 100644
  678. index 0000000000..4a6885db5e
  679. --- /dev/null
  680. +++ b/ld/testsuite/ld-riscv-elf/attr-tooshort-arch-z-failed-01.d
  681. @@ -0,0 +1,3 @@
  682. +#source: attr-tooshort-arch-z-failed-01.s
  683. +#as: -march-attr
  684. +#error: -march=rv32i2p0_z: Literal 'z' is an invalid Z ISA extension specifier.
  685. diff --git a/ld/testsuite/ld-riscv-elf/attr-tooshort-arch-z-failed-01.s b/ld/testsuite/ld-riscv-elf/attr-tooshort-arch-z-failed-01.s
  686. new file mode 100644
  687. index 0000000000..7ca87fabf4
  688. --- /dev/null
  689. +++ b/ld/testsuite/ld-riscv-elf/attr-tooshort-arch-z-failed-01.s
  690. @@ -0,0 +1 @@
  691. + .attribute arch, "rv32i2p0_z"
  692. diff --git a/ld/testsuite/ld-riscv-elf/attr-unknown-arch-z-failed-01.d b/ld/testsuite/ld-riscv-elf/attr-unknown-arch-z-failed-01.d
  693. new file mode 100644
  694. index 0000000000..343db87a41
  695. --- /dev/null
  696. +++ b/ld/testsuite/ld-riscv-elf/attr-unknown-arch-z-failed-01.d
  697. @@ -0,0 +1,3 @@
  698. +#source: attr-unknown-arch-z-failed-01.s
  699. +#as: -march-attr
  700. +#error: -march=rv32i2p0_zsillyname: Unknown Z ISA extension: 'zsillyname'
  701. diff --git a/ld/testsuite/ld-riscv-elf/attr-unknown-arch-z-failed-01.s b/ld/testsuite/ld-riscv-elf/attr-unknown-arch-z-failed-01.s
  702. new file mode 100644
  703. index 0000000000..6e16bef91d
  704. --- /dev/null
  705. +++ b/ld/testsuite/ld-riscv-elf/attr-unknown-arch-z-failed-01.s
  706. @@ -0,0 +1 @@
  707. + .attribute arch, "rv32i2p0_zsillyname"
  708. diff --git a/ld/testsuite/ld-riscv-elf/ld-riscv-elf.exp b/ld/testsuite/ld-riscv-elf/ld-riscv-elf.exp
  709. index 2c008d4c35..4df5d740e1 100644
  710. --- a/ld/testsuite/ld-riscv-elf/ld-riscv-elf.exp
  711. +++ b/ld/testsuite/ld-riscv-elf/ld-riscv-elf.exp
  712. @@ -47,6 +47,12 @@ if [istarget "riscv*-*-*"] {
  713. run_dump_test "attr-merge-priv-spec-failed-04"
  714. run_dump_test "attr-merge-priv-spec-failed-05"
  715. run_dump_test "attr-merge-priv-spec-failed-06"
  716. + run_dump_test "attr-merge-arch-z-failed-01"
  717. + run_dump_test "attr-dupl-arch-z-failed-01"
  718. + run_dump_test "attr-order-arch-z-failed-01"
  719. + run_dump_test "attr-order-arch-z-failed-02"
  720. + run_dump_test "attr-tooshort-arch-z-failed-01"
  721. + run_dump_test "attr-unknown-arch-z-failed-01"
  722. run_ld_link_tests {
  723. { "Weak reference 32" "-T weakref.ld -melf32lriscv" ""
  724. "-march=rv32i -mabi=ilp32" {weakref32.s}
  725. diff --git a/opcodes/riscv-dis.c b/opcodes/riscv-dis.c
  726. index 2b64cf1d08..bb57793c94 100644
  727. --- a/opcodes/riscv-dis.c
  728. +++ b/opcodes/riscv-dis.c
  729. @@ -239,6 +239,7 @@ print_insn_args (const char *d, insn_t l, bfd_vma pc, disassemble_info *info)
  730. case '>':
  731. print (info->stream, "0x%x", (int)EXTRACT_RVC_IMM (l) & 0x3f);
  732. break;
  733. + case '|':
  734. case '<':
  735. print (info->stream, "0x%x", (int)EXTRACT_RVC_IMM (l) & 0x1f);
  736. break;
  737. @@ -279,6 +280,11 @@ print_insn_args (const char *d, insn_t l, bfd_vma pc, disassemble_info *info)
  738. riscv_gpr_names[EXTRACT_OPERAND (RS2, l)]);
  739. break;
  740. + case 'r':
  741. + print (info->stream, "%s",
  742. + riscv_gpr_names[EXTRACT_OPERAND (RS3, l)]);
  743. + break;
  744. +
  745. case 'u':
  746. print (info->stream, "0x%x",
  747. (unsigned)EXTRACT_UTYPE_IMM (l) >> RISCV_IMM_BITS);
  748. @@ -342,6 +348,7 @@ print_insn_args (const char *d, insn_t l, bfd_vma pc, disassemble_info *info)
  749. print (info->stream, "0x%x", (int)EXTRACT_OPERAND (SHAMT, l));
  750. break;
  751. + case '|':
  752. case '<':
  753. print (info->stream, "0x%x", (int)EXTRACT_OPERAND (SHAMTW, l));
  754. break;
  755. diff --git a/opcodes/riscv-opc.c b/opcodes/riscv-opc.c
  756. index 778c5d2f45..1869f545cf 100644
  757. --- a/opcodes/riscv-opc.c
  758. +++ b/opcodes/riscv-opc.c
  759. @@ -984,6 +984,220 @@ const struct riscv_opcode riscv_opcodes[] =
  760. {"fcvt.h.lu", 64, INSN_CLASS_F_AND_ZFH, "D,s", MATCH_FCVT_H_LU | MASK_RM, MASK_FCVT_H_L | MASK_RM, match_opcode, 0 },
  761. {"fcvt.h.lu", 64, INSN_CLASS_F_AND_ZFH, "D,s,m", MATCH_FCVT_H_LU, MASK_FCVT_H_LU, match_opcode, 0 },
  762. +/* Bitmanip instruction subset */
  763. +{"andn", 0, INSN_CLASS_B_OR_ZBB_OR_ZBP, "d,s,t", MATCH_ANDN, MASK_ANDN, match_opcode, 0 },
  764. +{"orn", 0, INSN_CLASS_B_OR_ZBB_OR_ZBP, "d,s,t", MATCH_ORN, MASK_ORN, match_opcode, 0 },
  765. +{"xnor", 0, INSN_CLASS_B_OR_ZBB_OR_ZBP, "d,s,t", MATCH_XNOR, MASK_XNOR, match_opcode, 0 },
  766. +{"sloi", 0, INSN_CLASS_B_OR_ZBP, "d,s,>", MATCH_SLOI, MASK_SLOI, match_opcode, 0 },
  767. +{"sroi", 0, INSN_CLASS_B_OR_ZBP, "d,s,>", MATCH_SROI, MASK_SROI, match_opcode, 0 },
  768. +{"roli", 0, INSN_CLASS_B_OR_ZBB_OR_ZBP, "d,s,>", 0, (int) M_RL, match_never, INSN_MACRO },
  769. +{"rori", 0, INSN_CLASS_B_OR_ZBB_OR_ZBP, "d,s,>", MATCH_RORI, MASK_RORI, match_opcode, 0 },
  770. +{"slo", 0, INSN_CLASS_B_OR_ZBP, "d,s,t", MATCH_SLO, MASK_SLO, match_opcode, 0 },
  771. +{"slo", 0, INSN_CLASS_B_OR_ZBP, "d,s,>", MATCH_SLOI, MASK_SLOI, match_opcode, INSN_ALIAS },
  772. +{"sro", 0, INSN_CLASS_B_OR_ZBP, "d,s,t", MATCH_SRO, MASK_SRO, match_opcode, 0 },
  773. +{"sro", 0, INSN_CLASS_B_OR_ZBP, "d,s,>", MATCH_SROI, MASK_SROI, match_opcode, INSN_ALIAS },
  774. +{"rol", 0, INSN_CLASS_B_OR_ZBB_OR_ZBP, "d,s,t", MATCH_ROL, MASK_ROL, match_opcode, 0 },
  775. +{"rol", 0, INSN_CLASS_B_OR_ZBB_OR_ZBP, "d,s,>", 0, (int) M_RL, match_never, INSN_MACRO },
  776. +{"ror", 0, INSN_CLASS_B_OR_ZBB_OR_ZBP, "d,s,t", MATCH_ROR, MASK_ROR, match_opcode, 0 },
  777. +{"ror", 0, INSN_CLASS_B_OR_ZBB_OR_ZBP, "d,s,>", MATCH_RORI, MASK_RORI, match_opcode, INSN_ALIAS },
  778. +{"sbclri", 0, INSN_CLASS_B_OR_ZBS, "d,s,>", MATCH_SBCLRI, MASK_SBCLRI, match_opcode, 0 },
  779. +{"sbseti", 0, INSN_CLASS_B_OR_ZBS, "d,s,>", MATCH_SBSETI, MASK_SBSETI, match_opcode, 0 },
  780. +{"sbinvi", 0, INSN_CLASS_B_OR_ZBS, "d,s,>", MATCH_SBINVI, MASK_SBINVI, match_opcode, 0 },
  781. +{"sbexti", 0, INSN_CLASS_B_OR_ZBS, "d,s,>", MATCH_SBEXTI, MASK_SBEXTI, match_opcode, 0 },
  782. +{"gorci", 0, INSN_CLASS_B_OR_ZBP, "d,s,>", MATCH_GORCI, MASK_GORCI, match_opcode, 0 },
  783. +{"grevi", 0, INSN_CLASS_B_OR_ZBP, "d,s,>", MATCH_GREVI, MASK_GREVI, match_opcode, 0 },
  784. +{"sbclr", 0, INSN_CLASS_B_OR_ZBS, "d,s,t", MATCH_SBCLR, MASK_SBCLR, match_opcode, 0 },
  785. +{"sbclr", 0, INSN_CLASS_B_OR_ZBS, "d,s,>", MATCH_SBCLRI, MASK_SBCLRI, match_opcode, INSN_ALIAS },
  786. +{"sbset", 0, INSN_CLASS_B_OR_ZBS, "d,s,t", MATCH_SBSET, MASK_SBSET, match_opcode, 0 },
  787. +{"sbset", 0, INSN_CLASS_B_OR_ZBS, "d,s,>", MATCH_SBSETI, MASK_SBSETI, match_opcode, INSN_ALIAS },
  788. +{"sbinv", 0, INSN_CLASS_B_OR_ZBS, "d,s,t", MATCH_SBINV, MASK_SBINV, match_opcode, 0 },
  789. +{"sbinv", 0, INSN_CLASS_B_OR_ZBS, "d,s,>", MATCH_SBINVI, MASK_SBINVI, match_opcode, INSN_ALIAS },
  790. +{"sbext", 0, INSN_CLASS_B_OR_ZBS, "d,s,t", MATCH_SBEXT, MASK_SBEXT, match_opcode, 0 },
  791. +{"sbext", 0, INSN_CLASS_B_OR_ZBS, "d,s,>", MATCH_SBEXTI, MASK_SBEXTI, match_opcode, INSN_ALIAS },
  792. +{"gorc", 0, INSN_CLASS_B_OR_ZBP, "d,s,t", MATCH_GORC, MASK_GORC, match_opcode, 0 },
  793. +{"gorc", 0, INSN_CLASS_B_OR_ZBP, "d,s,>", MATCH_GORCI, MASK_GORCI, match_opcode, INSN_ALIAS },
  794. +{"grev", 0, INSN_CLASS_B_OR_ZBP, "d,s,t", MATCH_GREV, MASK_GREV, match_opcode, 0 },
  795. +{"grev", 0, INSN_CLASS_B_OR_ZBP, "d,s,>", MATCH_GREVI, MASK_GREVI, match_opcode, INSN_ALIAS },
  796. +{"cmix", 0, INSN_CLASS_B_OR_ZBT, "d,t,s,r", MATCH_CMIX, MASK_CMIX, match_opcode, 0 },
  797. +{"cmov", 0, INSN_CLASS_B_OR_ZBT, "d,t,s,r", MATCH_CMOV, MASK_CMOV, match_opcode, 0 },
  798. +{"fsli", 0, INSN_CLASS_B_OR_ZBT, "d,s,r,>", 0, (int) M_FL, match_never, INSN_MACRO },
  799. +{"fsri", 0, INSN_CLASS_B_OR_ZBT, "d,s,r,>", MATCH_FSRI, MASK_FSRI, match_opcode, 0 },
  800. +{"fsl", 0, INSN_CLASS_B_OR_ZBT, "d,s,r,t", MATCH_FSL, MASK_FSL, match_opcode, 0 },
  801. +{"fsl", 0, INSN_CLASS_B_OR_ZBT, "d,s,r,>", 0, (int) M_FL, match_never, INSN_MACRO },
  802. +{"fsr", 0, INSN_CLASS_B_OR_ZBT, "d,s,r,t", MATCH_FSR, MASK_FSR, match_opcode, 0 },
  803. +{"fsr", 0, INSN_CLASS_B_OR_ZBT, "d,s,r,>", MATCH_FSRI, MASK_FSRI, match_opcode, INSN_ALIAS },
  804. +{"clz", 0, INSN_CLASS_B_OR_ZBB, "d,s", MATCH_CLZ, MASK_CLZ, match_opcode, 0 },
  805. +{"ctz", 0, INSN_CLASS_B_OR_ZBB, "d,s", MATCH_CTZ, MASK_CTZ, match_opcode, 0 },
  806. +{"pcnt", 0, INSN_CLASS_B_OR_ZBB, "d,s", MATCH_PCNT, MASK_PCNT, match_opcode, 0 },
  807. +{"sext.b", 0, INSN_CLASS_B_OR_ZBB, "d,s", MATCH_SEXT_B, MASK_SEXT_B, match_opcode, 0 },
  808. +{"sext.h", 0, INSN_CLASS_B_OR_ZBB, "d,s", MATCH_SEXT_H, MASK_SEXT_H, match_opcode, 0 },
  809. +{"bmatflip", 64, INSN_CLASS_B_OR_ZBM, "d,s", MATCH_BMATFLIP, MASK_BMATFLIP, match_opcode, 0 },
  810. +{"crc32.b", 0, INSN_CLASS_B_OR_ZBR, "d,s", MATCH_CRC32_B, MASK_CRC32_B, match_opcode, 0 },
  811. +{"crc32.h", 0, INSN_CLASS_B_OR_ZBR, "d,s", MATCH_CRC32_H, MASK_CRC32_H, match_opcode, 0 },
  812. +{"crc32.w", 0, INSN_CLASS_B_OR_ZBR, "d,s", MATCH_CRC32_W, MASK_CRC32_W, match_opcode, 0 },
  813. +{"crc32.d", 64, INSN_CLASS_B_OR_ZBR, "d,s", MATCH_CRC32_D, MASK_CRC32_D, match_opcode, 0 },
  814. +{"crc32c.b", 0, INSN_CLASS_B_OR_ZBR, "d,s", MATCH_CRC32C_B, MASK_CRC32C_B, match_opcode, 0 },
  815. +{"crc32c.h", 0, INSN_CLASS_B_OR_ZBR, "d,s", MATCH_CRC32C_H, MASK_CRC32C_H, match_opcode, 0 },
  816. +{"crc32c.w", 0, INSN_CLASS_B_OR_ZBR, "d,s", MATCH_CRC32C_W, MASK_CRC32C_W, match_opcode, 0 },
  817. +{"crc32c.d", 64, INSN_CLASS_B_OR_ZBR, "d,s", MATCH_CRC32C_D, MASK_CRC32C_D, match_opcode, 0 },
  818. +{"sh1add", 0, INSN_CLASS_B_OR_ZBA, "d,s,t", MATCH_SH1ADD, MASK_SH1ADD, match_opcode, 0 },
  819. +{"sh2add", 0, INSN_CLASS_B_OR_ZBA, "d,s,t", MATCH_SH2ADD, MASK_SH2ADD, match_opcode, 0 },
  820. +{"sh3add", 0, INSN_CLASS_B_OR_ZBA, "d,s,t", MATCH_SH3ADD, MASK_SH3ADD, match_opcode, 0 },
  821. +{"clmul", 0, INSN_CLASS_B_OR_ZBC, "d,s,t", MATCH_CLMUL, MASK_CLMUL, match_opcode, 0 },
  822. +{"clmulh", 0, INSN_CLASS_B_OR_ZBC, "d,s,t", MATCH_CLMULH, MASK_CLMULH, match_opcode, 0 },
  823. +{"clmulr", 0, INSN_CLASS_B_OR_ZBC, "d,s,t", MATCH_CLMULR, MASK_CLMULR, match_opcode, 0 },
  824. +{"min", 0, INSN_CLASS_B_OR_ZBB, "d,s,t", MATCH_MIN, MASK_MIN, match_opcode, 0 },
  825. +{"max", 0, INSN_CLASS_B_OR_ZBB, "d,s,t", MATCH_MAX, MASK_MAX, match_opcode, 0 },
  826. +{"minu", 0, INSN_CLASS_B_OR_ZBB, "d,s,t", MATCH_MINU, MASK_MINU, match_opcode, 0 },
  827. +{"maxu", 0, INSN_CLASS_B_OR_ZBB, "d,s,t", MATCH_MAXU, MASK_MAXU, match_opcode, 0 },
  828. +{"shfli", 0, INSN_CLASS_B_OR_ZBP, "d,s,|", MATCH_SHFLI, MASK_SHFLI, match_opcode, 0 },
  829. +{"unshfli", 0, INSN_CLASS_B_OR_ZBP, "d,s,|", MATCH_UNSHFLI, MASK_UNSHFLI, match_opcode, 0 },
  830. +{"shfl", 0, INSN_CLASS_B_OR_ZBP, "d,s,t", MATCH_SHFL, MASK_SHFL, match_opcode, 0 },
  831. +{"shfl", 0, INSN_CLASS_B_OR_ZBP, "d,s,|", MATCH_SHFLI, MASK_SHFLI, match_opcode, INSN_ALIAS },
  832. +{"unshfl", 0, INSN_CLASS_B_OR_ZBP, "d,s,t", MATCH_UNSHFL, MASK_UNSHFL, match_opcode, 0 },
  833. +{"unshfl", 0, INSN_CLASS_B_OR_ZBP, "d,s,|", MATCH_UNSHFLI, MASK_UNSHFLI, match_opcode, INSN_ALIAS },
  834. +{"bdep", 0, INSN_CLASS_B_OR_ZBE, "d,s,t", MATCH_BDEP, MASK_BDEP, match_opcode, 0 },
  835. +{"bext", 0, INSN_CLASS_B_OR_ZBE, "d,s,t", MATCH_BEXT, MASK_BEXT, match_opcode, 0 },
  836. +{"pack", 0, INSN_CLASS_B_OR_ZBB_OR_ZBP, "d,s,t", MATCH_PACK, MASK_PACK, match_opcode, 0 },
  837. +{"packu", 0, INSN_CLASS_B_OR_ZBB_OR_ZBP, "d,s,t", MATCH_PACKU, MASK_PACKU, match_opcode, 0 },
  838. +{"packh", 0, INSN_CLASS_B_OR_ZBB_OR_ZBP, "d,s,t", MATCH_PACKH, MASK_PACKH, match_opcode, 0 },
  839. +{"bmator", 64, INSN_CLASS_B_OR_ZBM, "d,s,t", MATCH_BMATOR, MASK_BMATOR, match_opcode, 0 },
  840. +{"bmatxor", 64, INSN_CLASS_B_OR_ZBM, "d,s,t", MATCH_BMATXOR, MASK_BMATXOR, match_opcode, 0 },
  841. +{"bfp", 0, INSN_CLASS_B_OR_ZBF, "d,s,t", MATCH_BFP, MASK_BFP, match_opcode, 0 },
  842. +{"addiwu", 64, INSN_CLASS_B_OR_ZBB, "d,s,j", MATCH_ADDIWU, MASK_ADDIWU, match_opcode, 0 },
  843. +{"slliu.w", 64, INSN_CLASS_B_OR_ZBB, "d,s,>", MATCH_SLLIU_W, MASK_SLLIU_W, match_opcode, 0 },
  844. +{"addwu", 64, INSN_CLASS_B_OR_ZBB, "d,s,t", MATCH_ADDWU, MASK_ADDWU, match_opcode, 0 },
  845. +{"subwu", 64, INSN_CLASS_B_OR_ZBB, "d,s,t", MATCH_SUBWU, MASK_SUBWU, match_opcode, 0 },
  846. +{"addu.w", 64, INSN_CLASS_B_OR_ZBB, "d,s,t", MATCH_ADDU_W, MASK_ADDU_W, match_opcode, 0 },
  847. +{"subu.w", 64, INSN_CLASS_B_OR_ZBB, "d,s,t", MATCH_SUBU_W, MASK_SUBU_W, match_opcode, 0 },
  848. +{"sloiw", 64, INSN_CLASS_B_OR_ZBP, "d,s,<", MATCH_SLOIW, MASK_SLOIW, match_opcode, 0 },
  849. +{"sroiw", 64, INSN_CLASS_B_OR_ZBP, "d,s,<", MATCH_SROIW, MASK_SROIW, match_opcode, 0 },
  850. +{"roliw", 64, INSN_CLASS_B_OR_ZBB_OR_ZBP, "d,s,<", 0, (int) M_RL, match_never, INSN_MACRO },
  851. +{"roriw", 64, INSN_CLASS_B_OR_ZBB_OR_ZBP, "d,s,<", MATCH_RORIW, MASK_RORIW, match_opcode, 0 },
  852. +{"slow", 64, INSN_CLASS_B_OR_ZBP, "d,s,t", MATCH_SLOW, MASK_SLOW, match_opcode, 0 },
  853. +{"slow", 64, INSN_CLASS_B_OR_ZBP, "d,s,<", MATCH_SLOIW, MASK_SLOIW, match_opcode, INSN_ALIAS },
  854. +{"srow", 64, INSN_CLASS_B_OR_ZBP, "d,s,t", MATCH_SROW, MASK_SROW, match_opcode, 0 },
  855. +{"srow", 64, INSN_CLASS_B_OR_ZBP, "d,s,<", MATCH_SROIW, MASK_SROIW, match_opcode, INSN_ALIAS },
  856. +{"rolw", 64, INSN_CLASS_B_OR_ZBB_OR_ZBP, "d,s,t", MATCH_ROLW, MASK_ROLW, match_opcode, 0 },
  857. +{"rolw", 64, INSN_CLASS_B_OR_ZBB_OR_ZBP, "d,s,<", 0, (int) M_RL, match_never, INSN_MACRO },
  858. +{"rorw", 64, INSN_CLASS_B_OR_ZBB_OR_ZBP, "d,s,t", MATCH_RORW, MASK_RORW, match_opcode, 0 },
  859. +{"rorw", 64, INSN_CLASS_B_OR_ZBB_OR_ZBP, "d,s,<", MATCH_RORIW, MASK_RORIW, match_opcode, INSN_ALIAS },
  860. +{"sbclriw", 64, INSN_CLASS_B_OR_ZBS, "d,s,<", MATCH_SBCLRIW, MASK_SBCLRIW, match_opcode, 0 },
  861. +{"sbsetiw", 64, INSN_CLASS_B_OR_ZBS, "d,s,<", MATCH_SBSETIW, MASK_SBSETIW, match_opcode, 0 },
  862. +{"sbinviw", 64, INSN_CLASS_B_OR_ZBS, "d,s,<", MATCH_SBINVIW, MASK_SBINVIW, match_opcode, 0 },
  863. +{"gorciw", 64, INSN_CLASS_B_OR_ZBP, "d,s,<", MATCH_GORCIW, MASK_GORCIW, match_opcode, 0 },
  864. +{"greviw", 64, INSN_CLASS_B_OR_ZBP, "d,s,<", MATCH_GREVIW, MASK_GREVIW, match_opcode, 0 },
  865. +{"sbclrw", 64, INSN_CLASS_B_OR_ZBS, "d,s,t", MATCH_SBCLRW, MASK_SBCLRW, match_opcode, 0 },
  866. +{"sbclrw", 64, INSN_CLASS_B_OR_ZBS, "d,s,<", MATCH_SBCLRIW, MASK_SBCLRIW, match_opcode, INSN_ALIAS },
  867. +{"sbsetw", 64, INSN_CLASS_B_OR_ZBS, "d,s,t", MATCH_SBSETW, MASK_SBSETW, match_opcode, 0 },
  868. +{"sbsetw", 64, INSN_CLASS_B_OR_ZBS, "d,s,<", MATCH_SBSETIW, MASK_SBSETIW, match_opcode, INSN_ALIAS },
  869. +{"sbinvw", 64, INSN_CLASS_B_OR_ZBS, "d,s,t", MATCH_SBINVW, MASK_SBINVW, match_opcode, 0 },
  870. +{"sbinvw", 64, INSN_CLASS_B_OR_ZBS, "d,s,<", MATCH_SBINVIW, MASK_SBINVIW, match_opcode, INSN_ALIAS },
  871. +{"sbextw", 64, INSN_CLASS_B_OR_ZBS, "d,s,t", MATCH_SBEXTW, MASK_SBEXTW, match_opcode, 0 },
  872. +{"gorcw", 64, INSN_CLASS_B_OR_ZBP, "d,s,t", MATCH_GORCW, MASK_GORCW, match_opcode, 0 },
  873. +{"gorcw", 64, INSN_CLASS_B_OR_ZBP, "d,s,<", MATCH_GORCIW, MASK_GORCIW, match_opcode, INSN_ALIAS },
  874. +{"grevw", 64, INSN_CLASS_B_OR_ZBP, "d,s,t", MATCH_GREVW, MASK_GREVW, match_opcode, 0 },
  875. +{"grevw", 64, INSN_CLASS_B_OR_ZBP, "d,s,<", MATCH_GREVIW, MASK_GREVIW, match_opcode, INSN_ALIAS },
  876. +{"fsliw", 64, INSN_CLASS_B_OR_ZBT, "d,s,r,<", 0, (int) M_FL, match_never, INSN_MACRO },
  877. +{"fsriw", 64, INSN_CLASS_B_OR_ZBT, "d,s,r,<", MATCH_FSRIW, MASK_FSRIW, match_opcode, 0 },
  878. +{"fslw", 64, INSN_CLASS_B_OR_ZBT, "d,s,r,t", MATCH_FSLW, MASK_FSLW, match_opcode, 0 },
  879. +{"fslw", 64, INSN_CLASS_B_OR_ZBT, "d,s,r,<", 0, (int) M_FL, match_never, INSN_MACRO },
  880. +{"fsrw", 64, INSN_CLASS_B_OR_ZBT, "d,s,r,t", MATCH_FSRW, MASK_FSRW, match_opcode, 0 },
  881. +{"fsrw", 64, INSN_CLASS_B_OR_ZBT, "d,s,r,<", MATCH_FSRIW, MASK_FSRIW, match_opcode, INSN_ALIAS },
  882. +{"clzw", 64, INSN_CLASS_B_OR_ZBB, "d,s", MATCH_CLZW, MASK_CLZW, match_opcode, 0 },
  883. +{"ctzw", 64, INSN_CLASS_B_OR_ZBB, "d,s", MATCH_CTZW, MASK_CTZW, match_opcode, 0 },
  884. +{"pcntw", 64, INSN_CLASS_B_OR_ZBB, "d,s", MATCH_PCNTW, MASK_PCNTW, match_opcode, 0 },
  885. +{"sh1addu.w",64, INSN_CLASS_B_OR_ZBA, "d,s,t", MATCH_SH1ADDU_W, MASK_SH1ADDU_W, match_opcode, 0 },
  886. +{"sh2addu.w",64, INSN_CLASS_B_OR_ZBA, "d,s,t", MATCH_SH2ADDU_W, MASK_SH2ADDU_W, match_opcode, 0 },
  887. +{"sh3addu.w",64, INSN_CLASS_B_OR_ZBA, "d,s,t", MATCH_SH3ADDU_W, MASK_SH3ADDU_W, match_opcode, 0 },
  888. +{"clmulw", 64, INSN_CLASS_B_OR_ZBC, "d,s,t", MATCH_CLMULW, MASK_CLMULW, match_opcode, 0 },
  889. +{"clmulhw", 64, INSN_CLASS_B_OR_ZBC, "d,s,t", MATCH_CLMULHW, MASK_CLMULHW, match_opcode, 0 },
  890. +{"clmulrw", 64, INSN_CLASS_B_OR_ZBC, "d,s,t", MATCH_CLMULRW, MASK_CLMULRW, match_opcode, 0 },
  891. +{"shflw", 64, INSN_CLASS_B_OR_ZBP, "d,s,t", MATCH_SHFLW, MASK_SHFLW, match_opcode, 0 },
  892. +{"unshflw", 64, INSN_CLASS_B_OR_ZBP, "d,s,t", MATCH_UNSHFLW, MASK_UNSHFLW, match_opcode, 0 },
  893. +{"bdepw", 64, INSN_CLASS_B_OR_ZBE, "d,s,t", MATCH_BDEPW, MASK_BDEPW, match_opcode, 0 },
  894. +{"bextw", 64, INSN_CLASS_B_OR_ZBE, "d,s,t", MATCH_BEXTW, MASK_BEXTW, match_opcode, 0 },
  895. +{"packw", 64, INSN_CLASS_B_OR_ZBB_OR_ZBP, "d,s,t", MATCH_PACKW, MASK_PACKW, match_opcode, 0 },
  896. +{"packuw", 64, INSN_CLASS_B_OR_ZBB_OR_ZBP, "d,s,t", MATCH_PACKUW, MASK_PACKUW, match_opcode, 0 },
  897. +{"bfpw", 64, INSN_CLASS_B_OR_ZBF, "d,s,t", MATCH_BFPW, MASK_BFPW, match_opcode, 0 },
  898. +
  899. +/* Bitmanip pseudo-instructions */
  900. +{"rev.p", 0, INSN_CLASS_B_OR_ZBB_OR_ZBP, "d,s", 0, (int) M_PERM, match_never, INSN_MACRO },
  901. +{"rev2.n", 0, INSN_CLASS_B_OR_ZBB_OR_ZBP, "d,s", 0, (int) M_PERM, match_never, INSN_MACRO },
  902. +{"rev.n", 0, INSN_CLASS_B_OR_ZBB_OR_ZBP, "d,s", 0, (int) M_PERM, match_never, INSN_MACRO },
  903. +{"rev4.b", 0, INSN_CLASS_B_OR_ZBB_OR_ZBP, "d,s", 0, (int) M_PERM, match_never, INSN_MACRO },
  904. +{"rev2.b", 0, INSN_CLASS_B_OR_ZBB_OR_ZBP, "d,s", 0, (int) M_PERM, match_never, INSN_MACRO },
  905. +{"rev.b", 0, INSN_CLASS_B_OR_ZBB_OR_ZBP, "d,s", 0, (int) M_PERM, match_never, INSN_MACRO },
  906. +{"rev8.h", 0, INSN_CLASS_B_OR_ZBB_OR_ZBP, "d,s", 0, (int) M_PERM, match_never, INSN_MACRO },
  907. +{"rev4.h", 0, INSN_CLASS_B_OR_ZBB_OR_ZBP, "d,s", 0, (int) M_PERM, match_never, INSN_MACRO },
  908. +{"rev2.h", 0, INSN_CLASS_B_OR_ZBB_OR_ZBP, "d,s", 0, (int) M_PERM, match_never, INSN_MACRO },
  909. +{"rev.h", 0, INSN_CLASS_B_OR_ZBB_OR_ZBP, "d,s", 0, (int) M_PERM, match_never, INSN_MACRO },
  910. +{"rev16.w", 64, INSN_CLASS_B_OR_ZBB_OR_ZBP, "d,s", 0, (int) M_PERM, match_never, INSN_MACRO },
  911. +{"rev8.w", 64, INSN_CLASS_B_OR_ZBB_OR_ZBP, "d,s", 0, (int) M_PERM, match_never, INSN_MACRO },
  912. +{"rev4.w", 64, INSN_CLASS_B_OR_ZBB_OR_ZBP, "d,s", 0, (int) M_PERM, match_never, INSN_MACRO },
  913. +{"rev2.w", 64, INSN_CLASS_B_OR_ZBB_OR_ZBP, "d,s", 0, (int) M_PERM, match_never, INSN_MACRO },
  914. +{"rev.w", 64, INSN_CLASS_B_OR_ZBB_OR_ZBP, "d,s", 0, (int) M_PERM, match_never, INSN_MACRO },
  915. +{"rev32", 64, INSN_CLASS_B_OR_ZBB_OR_ZBP, "d,s", 0, (int) M_PERM, match_never, INSN_MACRO },
  916. +{"rev16", 0, INSN_CLASS_B_OR_ZBB_OR_ZBP, "d,s", 0, (int) M_PERM, match_never, INSN_MACRO },
  917. +{"rev8", 0, INSN_CLASS_B_OR_ZBB_OR_ZBP, "d,s", 0, (int) M_PERM, match_never, INSN_MACRO },
  918. +{"rev4", 0, INSN_CLASS_B_OR_ZBB_OR_ZBP, "d,s", 0, (int) M_PERM, match_never, INSN_MACRO },
  919. +{"rev2", 0, INSN_CLASS_B_OR_ZBB_OR_ZBP, "d,s", 0, (int) M_PERM, match_never, INSN_MACRO },
  920. +{"rev", 0, INSN_CLASS_B_OR_ZBB_OR_ZBP, "d,s", 0, (int) M_PERM, match_never, INSN_MACRO },
  921. +
  922. +{"orc.p", 0, INSN_CLASS_B_OR_ZBB_OR_ZBP, "d,s", 0, (int) M_PERM, match_never, INSN_MACRO },
  923. +{"orc2.n", 0, INSN_CLASS_B_OR_ZBB_OR_ZBP, "d,s", 0, (int) M_PERM, match_never, INSN_MACRO },
  924. +{"orc.n", 0, INSN_CLASS_B_OR_ZBB_OR_ZBP, "d,s", 0, (int) M_PERM, match_never, INSN_MACRO },
  925. +{"orc4.b", 0, INSN_CLASS_B_OR_ZBB_OR_ZBP, "d,s", 0, (int) M_PERM, match_never, INSN_MACRO },
  926. +{"orc2.b", 0, INSN_CLASS_B_OR_ZBB_OR_ZBP, "d,s", 0, (int) M_PERM, match_never, INSN_MACRO },
  927. +{"orc.b", 0, INSN_CLASS_B_OR_ZBB_OR_ZBP, "d,s", 0, (int) M_PERM, match_never, INSN_MACRO },
  928. +{"orc8.h", 0, INSN_CLASS_B_OR_ZBB_OR_ZBP, "d,s", 0, (int) M_PERM, match_never, INSN_MACRO },
  929. +{"orc4.h", 0, INSN_CLASS_B_OR_ZBB_OR_ZBP, "d,s", 0, (int) M_PERM, match_never, INSN_MACRO },
  930. +{"orc2.h", 0, INSN_CLASS_B_OR_ZBB_OR_ZBP, "d,s", 0, (int) M_PERM, match_never, INSN_MACRO },
  931. +{"orc.h", 0, INSN_CLASS_B_OR_ZBB_OR_ZBP, "d,s", 0, (int) M_PERM, match_never, INSN_MACRO },
  932. +{"orc16.w", 64, INSN_CLASS_B_OR_ZBB_OR_ZBP, "d,s", 0, (int) M_PERM, match_never, INSN_MACRO },
  933. +{"orc8.w", 64, INSN_CLASS_B_OR_ZBB_OR_ZBP, "d,s", 0, (int) M_PERM, match_never, INSN_MACRO },
  934. +{"orc4.w", 64, INSN_CLASS_B_OR_ZBB_OR_ZBP, "d,s", 0, (int) M_PERM, match_never, INSN_MACRO },
  935. +{"orc2.w", 64, INSN_CLASS_B_OR_ZBB_OR_ZBP, "d,s", 0, (int) M_PERM, match_never, INSN_MACRO },
  936. +{"orc.w", 64, INSN_CLASS_B_OR_ZBB_OR_ZBP, "d,s", 0, (int) M_PERM, match_never, INSN_MACRO },
  937. +{"orc32", 64, INSN_CLASS_B_OR_ZBB_OR_ZBP, "d,s", 0, (int) M_PERM, match_never, INSN_MACRO },
  938. +{"orc16", 0, INSN_CLASS_B_OR_ZBB_OR_ZBP, "d,s", 0, (int) M_PERM, match_never, INSN_MACRO },
  939. +{"orc8", 0, INSN_CLASS_B_OR_ZBB_OR_ZBP, "d,s", 0, (int) M_PERM, match_never, INSN_MACRO },
  940. +{"orc4", 0, INSN_CLASS_B_OR_ZBB_OR_ZBP, "d,s", 0, (int) M_PERM, match_never, INSN_MACRO },
  941. +{"orc2", 0, INSN_CLASS_B_OR_ZBB_OR_ZBP, "d,s", 0, (int) M_PERM, match_never, INSN_MACRO },
  942. +{"orc", 0, INSN_CLASS_B_OR_ZBB_OR_ZBP, "d,s", 0, (int) M_PERM, match_never, INSN_MACRO },
  943. +
  944. +{"zip.n", 0, INSN_CLASS_B_OR_ZBP, "d,s", 0, (int) M_PERM, match_never, INSN_MACRO },
  945. +{"zip2.b", 0, INSN_CLASS_B_OR_ZBP, "d,s", 0, (int) M_PERM, match_never, INSN_MACRO },
  946. +{"zip.b", 0, INSN_CLASS_B_OR_ZBP, "d,s", 0, (int) M_PERM, match_never, INSN_MACRO },
  947. +{"zip4.h", 0, INSN_CLASS_B_OR_ZBP, "d,s", 0, (int) M_PERM, match_never, INSN_MACRO },
  948. +{"zip2.h", 0, INSN_CLASS_B_OR_ZBP, "d,s", 0, (int) M_PERM, match_never, INSN_MACRO },
  949. +{"zip.h", 0, INSN_CLASS_B_OR_ZBP, "d,s", 0, (int) M_PERM, match_never, INSN_MACRO },
  950. +{"zip8.w", 64, INSN_CLASS_B_OR_ZBP, "d,s", 0, (int) M_PERM, match_never, INSN_MACRO },
  951. +{"zip4.w", 64, INSN_CLASS_B_OR_ZBP, "d,s", 0, (int) M_PERM, match_never, INSN_MACRO },
  952. +{"zip2.w", 64, INSN_CLASS_B_OR_ZBP, "d,s", 0, (int) M_PERM, match_never, INSN_MACRO },
  953. +{"zip.w", 64, INSN_CLASS_B_OR_ZBP, "d,s", 0, (int) M_PERM, match_never, INSN_MACRO },
  954. +{"zip16", 64, INSN_CLASS_B_OR_ZBP, "d,s", 0, (int) M_PERM, match_never, INSN_MACRO },
  955. +{"zip8", 0, INSN_CLASS_B_OR_ZBP, "d,s", 0, (int) M_PERM, match_never, INSN_MACRO },
  956. +{"zip4", 0, INSN_CLASS_B_OR_ZBP, "d,s", 0, (int) M_PERM, match_never, INSN_MACRO },
  957. +{"zip2", 0, INSN_CLASS_B_OR_ZBP, "d,s", 0, (int) M_PERM, match_never, INSN_MACRO },
  958. +{"zip", 0, INSN_CLASS_B_OR_ZBP, "d,s", 0, (int) M_PERM, match_never, INSN_MACRO },
  959. +
  960. +{"unzip.n", 0, INSN_CLASS_B_OR_ZBP, "d,s", 0, (int) M_PERM, match_never, INSN_MACRO },
  961. +{"unzip2.b", 0, INSN_CLASS_B_OR_ZBP, "d,s", 0, (int) M_PERM, match_never, INSN_MACRO },
  962. +{"unzip.b", 0, INSN_CLASS_B_OR_ZBP, "d,s", 0, (int) M_PERM, match_never, INSN_MACRO },
  963. +{"unzip4.h", 0, INSN_CLASS_B_OR_ZBP, "d,s", 0, (int) M_PERM, match_never, INSN_MACRO },
  964. +{"unzip2.h", 0, INSN_CLASS_B_OR_ZBP, "d,s", 0, (int) M_PERM, match_never, INSN_MACRO },
  965. +{"unzip.h", 0, INSN_CLASS_B_OR_ZBP, "d,s", 0, (int) M_PERM, match_never, INSN_MACRO },
  966. +{"unzip8.w", 64, INSN_CLASS_B_OR_ZBP, "d,s", 0, (int) M_PERM, match_never, INSN_MACRO },
  967. +{"unzip4.w", 64, INSN_CLASS_B_OR_ZBP, "d,s", 0, (int) M_PERM, match_never, INSN_MACRO },
  968. +{"unzip2.w", 64, INSN_CLASS_B_OR_ZBP, "d,s", 0, (int) M_PERM, match_never, INSN_MACRO },
  969. +{"unzip.w", 64, INSN_CLASS_B_OR_ZBP, "d,s", 0, (int) M_PERM, match_never, INSN_MACRO },
  970. +{"unzip16", 64, INSN_CLASS_B_OR_ZBP, "d,s", 0, (int) M_PERM, match_never, INSN_MACRO },
  971. +{"unzip8", 0, INSN_CLASS_B_OR_ZBP, "d,s", 0, (int) M_PERM, match_never, INSN_MACRO },
  972. +{"unzip4", 0, INSN_CLASS_B_OR_ZBP, "d,s", 0, (int) M_PERM, match_never, INSN_MACRO },
  973. +{"unzip2", 0, INSN_CLASS_B_OR_ZBP, "d,s", 0, (int) M_PERM, match_never, INSN_MACRO },
  974. +{"unzip", 0, INSN_CLASS_B_OR_ZBP, "d,s", 0, (int) M_PERM, match_never, INSN_MACRO },
  975. +
  976. /* Single-precision floating-point instruction subset */
  977. {"frcsr", 0, INSN_CLASS_F, "d", MATCH_FRCSR, MASK_FRCSR, match_opcode, INSN_ALIAS },
  978. {"frsr", 0, INSN_CLASS_F, "d", MATCH_FRCSR, MASK_FRCSR, match_opcode, INSN_ALIAS },
  979. --
  980. 2.33.0