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+From 2824e8fad46464ac663d078f95ebcb4e69184c6f Mon Sep 17 00:00:00 2001
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+From: "eric.tang" <eric.tang@starfivetech.com>
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+Date: Fri, 4 Jun 2021 14:26:05 +0800
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+Subject: [PATCH 05/28] support Dubhe V extension
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+
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+Signed-off-by: eric.tang <eric.tang@starfivetech.com>
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+---
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+ gas/testsuite/gas/riscv/insn.d | 47 +-
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+ gas/testsuite/gas/riscv/insn.s | 64 +
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+ gas/testsuite/gas/riscv/v-zero-imm.d | 17 +
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+ gas/testsuite/gas/riscv/v-zero-imm.s | 8 +
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+ .../riscv/vector-insns-fail-arith-floatp.d | 3 +
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+ .../riscv/vector-insns-fail-arith-floatp.l | 39 +
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+ .../riscv/vector-insns-fail-arith-floatp.s | 123 ++
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+ .../gas/riscv/vector-insns-fail-arith-int.d | 3 +
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+ .../gas/riscv/vector-insns-fail-arith-int.l | 62 +
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+ .../gas/riscv/vector-insns-fail-arith-int.s | 187 ++
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+ .../gas/riscv/vector-insns-fail-load-store.d | 3 +
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+ .../gas/riscv/vector-insns-fail-load-store.l | 25 +
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+ .../gas/riscv/vector-insns-fail-load-store.s | 43 +
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+ .../gas/riscv/vector-insns-fail-permutation.d | 3 +
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+ .../gas/riscv/vector-insns-fail-permutation.l | 19 +
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+ .../gas/riscv/vector-insns-fail-permutation.s | 37 +
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+ .../gas/riscv/vector-insns-fail-unsupport.d | 3 +
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+ .../gas/riscv/vector-insns-fail-unsupport.l | 1469 ++++++++++++++
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+ .../gas/riscv/vector-insns-fail-unsupport.s | 1679 +++++++++++++++++
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+ .../gas/riscv/vector-insns-vmsgtvx.d | 29 +
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+ .../gas/riscv/vector-insns-vmsgtvx.s | 9 +
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+ gas/testsuite/gas/riscv/vector-insns.d | 476 +++++
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+ gas/testsuite/gas/riscv/vector-insns.s | 521 +++++
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+ opcodes/riscv-opc.c | 535 +-----
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+ 24 files changed, 4869 insertions(+), 535 deletions(-)
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+ create mode 100644 gas/testsuite/gas/riscv/v-zero-imm.d
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+ create mode 100644 gas/testsuite/gas/riscv/v-zero-imm.s
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+ create mode 100644 gas/testsuite/gas/riscv/vector-insns-fail-arith-floatp.d
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+ create mode 100644 gas/testsuite/gas/riscv/vector-insns-fail-arith-floatp.l
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+ create mode 100644 gas/testsuite/gas/riscv/vector-insns-fail-arith-floatp.s
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+ create mode 100644 gas/testsuite/gas/riscv/vector-insns-fail-arith-int.d
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+ create mode 100644 gas/testsuite/gas/riscv/vector-insns-fail-arith-int.l
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+ create mode 100644 gas/testsuite/gas/riscv/vector-insns-fail-arith-int.s
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+ create mode 100644 gas/testsuite/gas/riscv/vector-insns-fail-load-store.d
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+ create mode 100644 gas/testsuite/gas/riscv/vector-insns-fail-load-store.l
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+ create mode 100644 gas/testsuite/gas/riscv/vector-insns-fail-load-store.s
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+ create mode 100644 gas/testsuite/gas/riscv/vector-insns-fail-permutation.d
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+ create mode 100644 gas/testsuite/gas/riscv/vector-insns-fail-permutation.l
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+ create mode 100644 gas/testsuite/gas/riscv/vector-insns-fail-permutation.s
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+ create mode 100644 gas/testsuite/gas/riscv/vector-insns-fail-unsupport.d
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+ create mode 100644 gas/testsuite/gas/riscv/vector-insns-fail-unsupport.l
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+ create mode 100644 gas/testsuite/gas/riscv/vector-insns-fail-unsupport.s
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+ create mode 100644 gas/testsuite/gas/riscv/vector-insns-vmsgtvx.d
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+ create mode 100644 gas/testsuite/gas/riscv/vector-insns-vmsgtvx.s
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+ create mode 100644 gas/testsuite/gas/riscv/vector-insns.d
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+ create mode 100644 gas/testsuite/gas/riscv/vector-insns.s
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+
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+diff --git a/gas/testsuite/gas/riscv/insn.d b/gas/testsuite/gas/riscv/insn.d
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+index 8f0badfce1..e7a17b11d5 100644
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+--- a/gas/testsuite/gas/riscv/insn.d
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++++ b/gas/testsuite/gas/riscv/insn.d
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+@@ -1,4 +1,4 @@
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+-#as: -march=rv32ifc
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++#as: -march=rv32ifcv0p10
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+ #objdump: -dr
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+
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+ .*:[ ]+file format .*
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+@@ -63,3 +63,48 @@ Disassembly of section .text:
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+ [^:]+:[ ]+00c58533[ ]+add[ ]+a0,a1,a2
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+ [^:]+:[ ]+00c58533[ ]+add[ ]+a0,a1,a2
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+ [^:]+:[ ]+00c58533[ ]+add[ ]+a0,a1,a2
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++[^:]+:[ ]+08d67587[ ]+vlse64.v[ ]+v11,\(a2\),a3,v0.t
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++[^:]+:[ ]+08d67587[ ]+vlse64.v[ ]+v11,\(a2\),a3,v0.t
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++[^:]+:[ ]+08d67587[ ]+vlse64.v[ ]+v11,\(a2\),a3,v0.t
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++[^:]+:[ ]+08d67587[ ]+vlse64.v[ ]+v11,\(a2\),a3,v0.t
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++[^:]+:[ ]+08d67587[ ]+vlse64.v[ ]+v11,\(a2\),a3,v0.t
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++[^:]+:[ ]+0ad67587[ ]+vlse64.v[ ]+v11,\(a2\),a3
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++[^:]+:[ ]+0ad67587[ ]+vlse64.v[ ]+v11,\(a2\),a3
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++[^:]+:[ ]+0ad67587[ ]+vlse64.v[ ]+v11,\(a2\),a3
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++[^:]+:[ ]+0ad67587[ ]+vlse64.v[ ]+v11,\(a2\),a3
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++[^:]+:[ ]+0ad67587[ ]+vlse64.v[ ]+v11,\(a2\),a3
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++[^:]+:[ ]+08d675a7[ ]+vsse64.v[ ]+v11,\(a2\),a3,v0.t
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++[^:]+:[ ]+08d675a7[ ]+vsse64.v[ ]+v11,\(a2\),a3,v0.t
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++[^:]+:[ ]+08d675a7[ ]+vsse64.v[ ]+v11,\(a2\),a3,v0.t
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++[^:]+:[ ]+08d675a7[ ]+vsse64.v[ ]+v11,\(a2\),a3,v0.t
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++[^:]+:[ ]+08d675a7[ ]+vsse64.v[ ]+v11,\(a2\),a3,v0.t
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++[^:]+:[ ]+0ad675a7[ ]+vsse64.v[ ]+v11,\(a2\),a3
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++[^:]+:[ ]+0ad675a7[ ]+vsse64.v[ ]+v11,\(a2\),a3
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++[^:]+:[ ]+0ad675a7[ ]+vsse64.v[ ]+v11,\(a2\),a3
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++[^:]+:[ ]+0ad675a7[ ]+vsse64.v[ ]+v11,\(a2\),a3
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++[^:]+:[ ]+0ad675a7[ ]+vsse64.v[ ]+v11,\(a2\),a3
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++[^:]+:[ ]+00067587[ ]+vle64.v[ ]+v11,\(a2\),v0.t
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++[^:]+:[ ]+000675a7[ ]+vse64.v[ ]+v11,\(a2\),v0.t
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++[^:]+:[ ]+00d605d7[ ]+vadd.vv[ ]+v11,v13,v12,v0.t
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++[^:]+:[ ]+00d605d7[ ]+vadd.vv[ ]+v11,v13,v12,v0.t
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++[^:]+:[ ]+00d605d7[ ]+vadd.vv[ ]+v11,v13,v12,v0.t
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++[^:]+:[ ]+00d605d7[ ]+vadd.vv[ ]+v11,v13,v12,v0.t
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++[^:]+:[ ]+00d605d7[ ]+vadd.vv[ ]+v11,v13,v12,v0.t
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++[^:]+:[ ]+00d605d7[ ]+vadd.vv[ ]+v11,v13,v12,v0.t
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++[^:]+:[ ]+00d605d7[ ]+vadd.vv[ ]+v11,v13,v12,v0.t
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++[^:]+:[ ]+00d615d7[ ]+vfadd.vv[ ]+v11,v13,v12,v0.t
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++[^:]+:[ ]+00d615d7[ ]+vfadd.vv[ ]+v11,v13,v12,v0.t
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++[^:]+:[ ]+00d645d7[ ]+vadd.vx[ ]+v11,v13,a2,v0.t
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++[^:]+:[ ]+00d645d7[ ]+vadd.vx[ ]+v11,v13,a2,v0.t
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++[^:]+:[ ]+00d655d7[ ]+vfadd.vf[ ]+v11,v13,fa2,v0.t
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++[^:]+:[ ]+00d655d7[ ]+vfadd.vf[ ]+v11,v13,fa2,v0.t
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++[^:]+:[ ]+38d665d7[ ]+vslide1up.vx[ ]+v11,v13,a2,v0.t
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++[^:]+:[ ]+3cd665d7[ ]+vslide1down.vx[ ]+v11,v13,a2,v0.t
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++[^:]+:[ ]+00d675d7[ ]+vsetvli[ ]+a1,a2,e16,mf8,tu,mu
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++[^:]+:[ ]+00d675d7[ ]+vsetvli[ ]+a1,a2,e16,mf8,tu,mu
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++[^:]+:[ ]+00d035d7[ ]+vadd.vi[ ]+v11,v13,0,v0.t
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++[^:]+:[ ]+00d0b5d7[ ]+vadd.vi[ ]+v11,v13,1,v0.t
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++[^:]+:[ ]+00d7b5d7[ ]+vadd.vi[ ]+v11,v13,15,v0.t
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++[^:]+:[ ]+00d835d7[ ]+vadd.vi[ ]+v11,v13,-16,v0.t
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++[^:]+:[ ]+00df35d7[ ]+vadd.vi[ ]+v11,v13,-2,v0.t
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++[^:]+:[ ]+00dfb5d7[ ]+vadd.vi[ ]+v11,v13,-1,v0.t
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+diff --git a/gas/testsuite/gas/riscv/insn.s b/gas/testsuite/gas/riscv/insn.s
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+index 6c08f49d43..5f2f75e88b 100644
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+--- a/gas/testsuite/gas/riscv/insn.s
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++++ b/gas/testsuite/gas/riscv/insn.s
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+@@ -47,3 +47,67 @@ target:
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+ .insn r 0x33, 0, 0, fa0, a1, fa2
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+ .insn r 0x33, 0, 0, a0, fa1, fa2
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+ .insn r 0x33, 0, 0, fa0, fa1, fa2
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++
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++# vamo
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++# F3: width[14:12]
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++# F7: amoop[31:27] + wd[26] + vm[25]
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++
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++# vmem
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++# F3: width[14:12]
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++# F7: nf[31:29] + mop[28:26] + vm[25]
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++
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++ .insn r LOAD_FP, 0x7, 0x4, v11, a2, a3
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++ .insn r LOAD_FP, 0x7, 0x4, v11, a2, a3
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++ .insn r LOAD_FP, 0x7, 0x4, v11, fa2, a3
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++ .insn r LOAD_FP, 0x7, 0x4, v11, a2, fa3
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++ .insn r LOAD_FP, 0x7, 0x4, v11, fa2, fa3
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++ .insn r 0x7, 0x7, 0x5, a1, v12, a3
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++ .insn r 0x7, 0x7, 0x5, fa1, v12, a3
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++ .insn r 0x7, 0x7, 0x5, a1, v12, fa3
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++ .insn r 0x7, 0x7, 0x5, fa1, v12, fa3
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++ .insn r 0x7, 0x7, 0x5, a1, a2, v13
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++ .insn r STORE_FP, 0x7, 0x4, fa1, a2, v13
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++ .insn r STORE_FP, 0x7, 0x4, a1, fa2, v13
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++ .insn r STORE_FP, 0x7, 0x4, fa1, fa2, v13
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++ .insn r STORE_FP, 0x7, 0x4, a1, v12, v13
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++ .insn r STORE_FP, 0x7, 0x4, fa1, v12, v13
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++ .insn r 0x27, 0x7, 0x5, v11, a2, v13
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++ .insn r 0x27, 0x7, 0x5, v11, fa2, v13
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++ .insn r 0x27, 0x7, 0x5, v11, v12, a3
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++ .insn r 0x27, 0x7, 0x5, v11, v12, fa3
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++ .insn r 0x27, 0x7, 0x5, v11, v12, v13
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++ # unit-stride
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++ .insn r LOAD_FP, 0x7, 0x0, v11, a2, x0
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++ #.insn r LOAD_FP, 0x7, 0x1, v11, a2, x16
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++ .insn r STORE_FP, 0x7, 0x0, v11, a2, x0
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++
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++# valu and vcfg
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++# F3: funct3[14:12]
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++# F7: F6[31:26] + vm[25]
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++
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++ .insn r 0x57, 0x0, 0x0, v11, a2, a3
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++ .insn r 0x57, 0x0, 0x0, v11, fa2, a3
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++ .insn r 0x57, 0x0, 0x0, v11, a2, fa3
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++ .insn r 0x57, 0x0, 0x0, v11, fa2, fa3
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++ .insn r 0x57, 0x0, 0x0, a1, v12, a3
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++ .insn r 0x57, 0x0, 0x0, fa1, v12, a3
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++ .insn r 0x57, 0x0, 0x0, a1, v12, fa3
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++ .insn r 0x57, 0x1, 0x0, fa1, v12, fa3
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++ .insn r 0x57, 0x1, 0x0, a1, a2, v13
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++ #.insn r 0x57, 0x2, 0x0, fa1, a2, v13
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++ #.insn r 0x57, 0x2, 0x0, a1, fa2, v13
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++ .insn r 0x57, 0x4, 0x0, fa1, fa2, v13
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++ .insn r 0x57, 0x4, 0x0, a1, v12, v13
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++ .insn r 0x57, 0x5, 0x0, fa1, v12, v13
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++ .insn r 0x57, 0x5, 0x0, v11, a2, v13
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++ .insn r 0x57, 0x6, 0x1c, v11, fa2, v13
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++ .insn r 0x57, 0x6, 0x1e, v11, v12, a3
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++ .insn r 0x57, 0x7, 0x0, v11, v12, fa3
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++ .insn r 0x57, 0x7, 0x0, v11, v12, v13
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++ # OPIVI
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++ .insn r 0x57, 0x3, 0x0, v11, x0, a3
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++ .insn r 0x57, 0x3, 0x0, v11, x1, a3
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++ .insn r 0x57, 0x3, 0x0, v11, x15, a3
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++ .insn r 0x57, 0x3, 0x0, v11, x16, a3
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++ .insn r 0x57, 0x3, 0x0, v11, x30, a3
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++ .insn r 0x57, 0x3, 0x0, v11, x31, a3
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+diff --git a/gas/testsuite/gas/riscv/v-zero-imm.d b/gas/testsuite/gas/riscv/v-zero-imm.d
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+new file mode 100644
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+index 0000000000..b95c068a17
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+--- /dev/null
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++++ b/gas/testsuite/gas/riscv/v-zero-imm.d
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+@@ -0,0 +1,17 @@
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++#as: -march=rv32ifv0p10
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++#objdump: -dr
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++
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++.*:[ ]+file format .*
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++
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++
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++Disassembly of section .text:
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++
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++0+000 <.text>:
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++[ ]+[0-9a-f]+:[ ]+768fb257[ ]+vmsle.vi[ ]+v4,v8,-1
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++[ ]+[0-9a-f]+:[ ]+748fb257[ ]+vmsle.vi[ ]+v4,v8,-1,v0.t
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++[ ]+[0-9a-f]+:[ ]+66840257[ ]+vmsne.vv[ ]+v4,v8,v8
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++[ ]+[0-9a-f]+:[ ]+64840257[ ]+vmsne.vv[ ]+v4,v8,v8,v0.t
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++[ ]+[0-9a-f]+:[ ]+7e8fb257[ ]+vmsgt.vi[ ]+v4,v8,-1
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++[ ]+[0-9a-f]+:[ ]+7c8fb257[ ]+vmsgt.vi[ ]+v4,v8,-1,v0.t
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++[ ]+[0-9a-f]+:[ ]+62840257[ ]+vmseq.vv[ ]+v4,v8,v8
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++[ ]+[0-9a-f]+:[ ]+60840257[ ]+vmseq.vv[ ]+v4,v8,v8,v0.t
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+diff --git a/gas/testsuite/gas/riscv/v-zero-imm.s b/gas/testsuite/gas/riscv/v-zero-imm.s
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+new file mode 100644
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+index 0000000000..98b7063880
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+--- /dev/null
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++++ b/gas/testsuite/gas/riscv/v-zero-imm.s
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+@@ -0,0 +1,8 @@
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++ vmslt.vi v4, v8, 0
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++ vmslt.vi v4, v8, 0, v0.t
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++ vmsltu.vi v4, v8, 0
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++ vmsltu.vi v4, v8, 0, v0.t
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++ vmsge.vi v4, v8, 0
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++ vmsge.vi v4, v8, 0, v0.t
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++ vmsgeu.vi v4, v8, 0
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++ vmsgeu.vi v4, v8, 0, v0.t
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+diff --git a/gas/testsuite/gas/riscv/vector-insns-fail-arith-floatp.d b/gas/testsuite/gas/riscv/vector-insns-fail-arith-floatp.d
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+new file mode 100644
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+index 0000000000..d192761c06
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+--- /dev/null
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++++ b/gas/testsuite/gas/riscv/vector-insns-fail-arith-floatp.d
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+@@ -0,0 +1,3 @@
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++#as: -march=rv32ifv0p10
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++#source: vector-insns-fail-arith-floatp.s
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++#error_output: vector-insns-fail-arith-floatp.l
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+diff --git a/gas/testsuite/gas/riscv/vector-insns-fail-arith-floatp.l b/gas/testsuite/gas/riscv/vector-insns-fail-arith-floatp.l
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+new file mode 100644
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+index 0000000000..b211327275
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+--- /dev/null
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|
++++ b/gas/testsuite/gas/riscv/vector-insns-fail-arith-floatp.l
|
|
|
+@@ -0,0 +1,39 @@
|
|
|
++.*: Assembler messages:
|
|
|
++.*Error: illegal operands `vfadd.vv v0,v4,v8,v0.t'
|
|
|
++.*Error: illegal operands `vfadd.vf v0,v4,fa1,v0.t'
|
|
|
++.*Error: illegal operands `vfsub.vv v0,v4,v8,v0.t'
|
|
|
++.*Error: illegal operands `vfsub.vf v0,v4,fa1,v0.t'
|
|
|
++.*Error: illegal operands `vfrsub.vf v0,v4,fa1,v0.t'
|
|
|
++.*Error: illegal operands `vfmul.vv v0,v4,v8,v0.t'
|
|
|
++.*Error: illegal operands `vfmul.vf v0,v4,fa1,v0.t'
|
|
|
++.*Error: illegal operands `vfdiv.vv v0,v4,v8,v0.t'
|
|
|
++.*Error: illegal operands `vfdiv.vf v0,v4,fa1,v0.t'
|
|
|
++.*Error: illegal operands `vfrdiv.vf v0,v4,fa1,v0.t'
|
|
|
++.*Error: illegal operands `vfmacc.vv v0,v4,v8,v0.t'
|
|
|
++.*Error: illegal operands `vfmacc.vf v0,fa1,v4,v0.t'
|
|
|
++.*Error: illegal operands `vfnmacc.vv v0,v4,v8,v0.t'
|
|
|
++.*Error: illegal operands `vfnmacc.vf v0,fa1,v4,v0.t'
|
|
|
++.*Error: illegal operands `vfmsac.vv v0,v4,v8,v0.t'
|
|
|
++.*Error: illegal operands `vfmsac.vf v0,fa1,v4,v0.t'
|
|
|
++.*Error: illegal operands `vfnmsac.vv v0,v4,v8,v0.t'
|
|
|
++.*Error: illegal operands `vfnmsac.vf v0,fa1,v4,v0.t'
|
|
|
++.*Error: illegal operands `vfmadd.vv v0,v4,v8,v0.t'
|
|
|
++.*Error: illegal operands `vfmadd.vf v0,fa1,v4,v0.t'
|
|
|
++.*Error: illegal operands `vfnmadd.vv v0,v4,v8,v0.t'
|
|
|
++.*Error: illegal operands `vfnmadd.vf v0,fa1,v4,v0.t'
|
|
|
++.*Error: illegal operands `vfmsub.vv v0,v4,v8,v0.t'
|
|
|
++.*Error: illegal operands `vfmsub.vf v0,fa1,v4,v0.t'
|
|
|
++.*Error: illegal operands `vfnmsub.vv v0,v4,v8,v0.t'
|
|
|
++.*Error: illegal operands `vfnmsub.vf v0,fa1,v4,v0.t'
|
|
|
++.*Error: illegal operands `vfmin.vv v0,v4,v8,v0.t'
|
|
|
++.*Error: illegal operands `vfmin.vf v0,v4,fa1,v0.t'
|
|
|
++.*Error: illegal operands `vfmax.vv v0,v4,v8,v0.t'
|
|
|
++.*Error: illegal operands `vfmax.vf v0,v4,fa1,v0.t'
|
|
|
++.*Error: illegal operands `vfneg.v v0,v4,v0.t'
|
|
|
++.*Error: illegal operands `vfabs.v v0,v4,v0.t'
|
|
|
++.*Error: illegal operands `vfsgnj.vv v0,v4,v8,v0.t'
|
|
|
++.*Error: illegal operands `vfsgnj.vf v0,v4,fa1,v0.t'
|
|
|
++.*Error: illegal operands `vfsgnjn.vv v0,v4,v8,v0.t'
|
|
|
++.*Error: illegal operands `vfsgnjn.vf v0,v4,fa1,v0.t'
|
|
|
++.*Error: illegal operands `vfsgnjx.vv v0,v4,v8,v0.t'
|
|
|
++.*Error: illegal operands `vfsgnjx.vf v0,v4,fa1,v0.t'
|
|
|
+diff --git a/gas/testsuite/gas/riscv/vector-insns-fail-arith-floatp.s b/gas/testsuite/gas/riscv/vector-insns-fail-arith-floatp.s
|
|
|
+new file mode 100644
|
|
|
+index 0000000000..28e1d35db7
|
|
|
+--- /dev/null
|
|
|
++++ b/gas/testsuite/gas/riscv/vector-insns-fail-arith-floatp.s
|
|
|
+@@ -0,0 +1,123 @@
|
|
|
++# Vector Single-Width Floating-Point Add/Subtract Instructions
|
|
|
++
|
|
|
++ vfadd.vv v4, v4, v8 # OK
|
|
|
++ vfadd.vv v8, v4, v8 # OK
|
|
|
++ vfadd.vv v0, v4, v8, v0.t # vd overlap vm
|
|
|
++ vfadd.vf v4, v4, fa1 # OK
|
|
|
++ vfadd.vf v0, v4, fa1, v0.t # vd overlap vm
|
|
|
++
|
|
|
++ vfsub.vv v4, v4, v8
|
|
|
++ vfsub.vv v8, v4, v8
|
|
|
++ vfsub.vv v0, v4, v8, v0.t
|
|
|
++ vfsub.vf v4, v4, fa1
|
|
|
++ vfsub.vf v0, v4, fa1, v0.t
|
|
|
++
|
|
|
++ vfrsub.vf v4, v4, fa1 # OK
|
|
|
++ vfrsub.vf v0, v4, fa1, v0.t # vd overlap vm
|
|
|
++
|
|
|
++# Vector Single-Width Floating-Point Multiply/Divide Instructions
|
|
|
++
|
|
|
++ vfmul.vv v4, v4, v8 # OK
|
|
|
++ vfmul.vv v8, v4, v8 # OK
|
|
|
++ vfmul.vv v0, v4, v8, v0.t # vd overlap vm
|
|
|
++ vfmul.vf v4, v4, fa1 # OK
|
|
|
++ vfmul.vf v0, v4, fa1, v0.t # vd overlap vm
|
|
|
++
|
|
|
++ vfdiv.vv v4, v4, v8
|
|
|
++ vfdiv.vv v8, v4, v8
|
|
|
++ vfdiv.vv v0, v4, v8, v0.t
|
|
|
++ vfdiv.vf v4, v4, fa1
|
|
|
++ vfdiv.vf v0, v4, fa1, v0.t
|
|
|
++
|
|
|
++ vfrdiv.vf v4, v4, fa1 # OK
|
|
|
++ vfrdiv.vf v0, v4, fa1, v0.t # vd overlap vm
|
|
|
++
|
|
|
++# Vector Single-Width Floating-Point Fused Multiply-Add Instructions
|
|
|
++
|
|
|
++ vfmacc.vv v4, v4, v8 # OK
|
|
|
++ vfmacc.vv v8, v4, v8 # OK
|
|
|
++ vfmacc.vv v0, v4, v8, v0.t # vd overlap vm
|
|
|
++ vfmacc.vf v4, fa1, v4 # OK
|
|
|
++ vfmacc.vf v0, fa1, v4, v0.t # vd overlap vm
|
|
|
++
|
|
|
++ vfnmacc.vv v4, v4, v8
|
|
|
++ vfnmacc.vv v8, v4, v8
|
|
|
++ vfnmacc.vv v0, v4, v8, v0.t
|
|
|
++ vfnmacc.vf v4, fa1, v4
|
|
|
++ vfnmacc.vf v0, fa1, v4, v0.t
|
|
|
++
|
|
|
++ vfmsac.vv v4, v4, v8
|
|
|
++ vfmsac.vv v8, v4, v8
|
|
|
++ vfmsac.vv v0, v4, v8, v0.t
|
|
|
++ vfmsac.vf v4, fa1, v4
|
|
|
++ vfmsac.vf v0, fa1, v4, v0.t
|
|
|
++
|
|
|
++ vfnmsac.vv v4, v4, v8
|
|
|
++ vfnmsac.vv v8, v4, v8
|
|
|
++ vfnmsac.vv v0, v4, v8, v0.t
|
|
|
++ vfnmsac.vf v4, fa1, v4
|
|
|
++ vfnmsac.vf v0, fa1, v4, v0.t
|
|
|
++
|
|
|
++ vfmadd.vv v4, v4, v8
|
|
|
++ vfmadd.vv v8, v4, v8
|
|
|
++ vfmadd.vv v0, v4, v8, v0.t
|
|
|
++ vfmadd.vf v4, fa1, v4
|
|
|
++ vfmadd.vf v0, fa1, v4, v0.t
|
|
|
++
|
|
|
++ vfnmadd.vv v4, v4, v8
|
|
|
++ vfnmadd.vv v8, v4, v8
|
|
|
++ vfnmadd.vv v0, v4, v8, v0.t
|
|
|
++ vfnmadd.vf v4, fa1, v4
|
|
|
++ vfnmadd.vf v0, fa1, v4, v0.t
|
|
|
++
|
|
|
++ vfmsub.vv v4, v4, v8
|
|
|
++ vfmsub.vv v8, v4, v8
|
|
|
++ vfmsub.vv v0, v4, v8, v0.t
|
|
|
++ vfmsub.vf v4, fa1, v4
|
|
|
++ vfmsub.vf v0, fa1, v4, v0.t
|
|
|
++
|
|
|
++ vfnmsub.vv v4, v4, v8
|
|
|
++ vfnmsub.vv v8, v4, v8
|
|
|
++ vfnmsub.vv v0, v4, v8, v0.t
|
|
|
++ vfnmsub.vf v4, fa1, v4
|
|
|
++ vfnmsub.vf v0, fa1, v4, v0.t
|
|
|
++
|
|
|
++# Vector Floating-Point MIN/MAX Instructions
|
|
|
++
|
|
|
++ vfmin.vv v4, v4, v8 # OK
|
|
|
++ vfmin.vv v8, v4, v8 # OK
|
|
|
++ vfmin.vv v0, v4, v8, v0.t # vd overlap vm
|
|
|
++ vfmin.vf v4, v4, fa1 # OK
|
|
|
++ vfmin.vf v0, v4, fa1, v0.t # vd overlap vm
|
|
|
++
|
|
|
++ vfmax.vv v4, v4, v8
|
|
|
++ vfmax.vv v8, v4, v8
|
|
|
++ vfmax.vv v0, v4, v8, v0.t
|
|
|
++ vfmax.vf v4, v4, fa1
|
|
|
++ vfmax.vf v0, v4, fa1, v0.t
|
|
|
++
|
|
|
++# Vector Floating-Point Sign-Injection Instructions
|
|
|
++
|
|
|
++ vfneg.v v4, v4 # OK
|
|
|
++ vfneg.v v0, v4, v0.t # vd overlap vm
|
|
|
++ vfabs.v v4, v4 # OK
|
|
|
++ vfabs.v v0, v4, v0.t # vd overlap vm
|
|
|
++
|
|
|
++ vfsgnj.vv v4, v4, v8 # OK
|
|
|
++ vfsgnj.vv v8, v4, v8 # OK
|
|
|
++ vfsgnj.vv v0, v4, v8, v0.t # vd overlap vm
|
|
|
++ vfsgnj.vf v4, v4, fa1 # OK
|
|
|
++ vfsgnj.vf v0, v4, fa1, v0.t # vd overlap vm
|
|
|
++
|
|
|
++ vfsgnjn.vv v4, v4, v8
|
|
|
++ vfsgnjn.vv v8, v4, v8
|
|
|
++ vfsgnjn.vv v0, v4, v8, v0.t
|
|
|
++ vfsgnjn.vf v4, v4, fa1
|
|
|
++ vfsgnjn.vf v0, v4, fa1, v0.t
|
|
|
++
|
|
|
++ vfsgnjx.vv v4, v4, v8
|
|
|
++ vfsgnjx.vv v8, v4, v8
|
|
|
++ vfsgnjx.vv v0, v4, v8, v0.t
|
|
|
++ vfsgnjx.vf v4, v4, fa1
|
|
|
++ vfsgnjx.vf v0, v4, fa1, v0.t
|
|
|
++
|
|
|
+diff --git a/gas/testsuite/gas/riscv/vector-insns-fail-arith-int.d b/gas/testsuite/gas/riscv/vector-insns-fail-arith-int.d
|
|
|
+new file mode 100644
|
|
|
+index 0000000000..746f8d1964
|
|
|
+--- /dev/null
|
|
|
++++ b/gas/testsuite/gas/riscv/vector-insns-fail-arith-int.d
|
|
|
+@@ -0,0 +1,3 @@
|
|
|
++#as: -march=rv32iv0p10
|
|
|
++#source: vector-insns-fail-arith-int.s
|
|
|
++#error_output: vector-insns-fail-arith-int.l
|
|
|
+diff --git a/gas/testsuite/gas/riscv/vector-insns-fail-arith-int.l b/gas/testsuite/gas/riscv/vector-insns-fail-arith-int.l
|
|
|
+new file mode 100644
|
|
|
+index 0000000000..40f4f7717e
|
|
|
+--- /dev/null
|
|
|
++++ b/gas/testsuite/gas/riscv/vector-insns-fail-arith-int.l
|
|
|
+@@ -0,0 +1,62 @@
|
|
|
++.*: Assembler messages:
|
|
|
++.*Error: illegal operands `vneg.v v0,v4,v0.t'
|
|
|
++.*Error: illegal operands `vadd.vv v0,v4,v8,v0.t'
|
|
|
++.*Error: illegal operands `vadd.vx v0,v4,a1,v0.t'
|
|
|
++.*Error: illegal operands `vadd.vi v0,v4,15,v0.t'
|
|
|
++.*Error: illegal operands `vsub.vv v0,v4,v8,v0.t'
|
|
|
++.*Error: illegal operands `vsub.vx v0,v4,a1,v0.t'
|
|
|
++.*Error: illegal operands `vrsub.vx v0,v4,a1,v0.t'
|
|
|
++.*Error: illegal operands `vrsub.vi v0,v4,15,v0.t'
|
|
|
++.*Error: illegal operands `vzext.vf2 v0,v4,v0.t'
|
|
|
++.*Error: illegal operands `vsext.vf2 v0,v4,v0.t'
|
|
|
++.*Error: illegal operands `vzext.vf4 v0,v4,v0.t'
|
|
|
++.*Error: illegal operands `vsext.vf4 v0,v4,v0.t'
|
|
|
++.*Error: illegal operands `vzext.vf8 v0,v4,v0.t'
|
|
|
++.*Error: illegal operands `vsext.vf8 v0,v4,v0.t'
|
|
|
++.*Error: illegal operands `vadc.vvm v0,v4,v8,v0'
|
|
|
++.*Error: illegal operands `vadc.vxm v0,v4,a1,v0'
|
|
|
++.*Error: illegal operands `vadc.vim v0,v4,15,v0'
|
|
|
++.*Error: illegal operands `vsbc.vvm v0,v4,v8,v0'
|
|
|
++.*Error: illegal operands `vsbc.vxm v0,v4,a1,v0'
|
|
|
++.*Error: illegal operands `vnot.v v0,v4,v0.t'
|
|
|
++.*Error: illegal operands `vand.vv v0,v4,v8,v0.t'
|
|
|
++.*Error: illegal operands `vand.vx v0,v4,a1,v0.t'
|
|
|
++.*Error: illegal operands `vand.vi v0,v4,15,v0.t'
|
|
|
++.*Error: illegal operands `vor.vv v0,v4,v8,v0.t'
|
|
|
++.*Error: illegal operands `vor.vx v0,v4,a1,v0.t'
|
|
|
++.*Error: illegal operands `vor.vi v0,v4,15,v0.t'
|
|
|
++.*Error: illegal operands `vxor.vv v0,v4,v8,v0.t'
|
|
|
++.*Error: illegal operands `vxor.vx v0,v4,a1,v0.t'
|
|
|
++.*Error: illegal operands `vxor.vi v0,v4,15,v0.t'
|
|
|
++.*Error: illegal operands `vminu.vv v0,v4,v8,v0.t'
|
|
|
++.*Error: illegal operands `vminu.vx v0,v4,a1,v0.t'
|
|
|
++.*Error: illegal operands `vmin.vv v0,v4,v8,v0.t'
|
|
|
++.*Error: illegal operands `vmin.vx v0,v4,a1,v0.t'
|
|
|
++.*Error: illegal operands `vmaxu.vv v0,v4,v8,v0.t'
|
|
|
++.*Error: illegal operands `vmaxu.vx v0,v4,a1,v0.t'
|
|
|
++.*Error: illegal operands `vmax.vv v0,v4,v8,v0.t'
|
|
|
++.*Error: illegal operands `vmax.vx v0,v4,a1,v0.t'
|
|
|
++.*Error: illegal operands `vmul.vv v0,v4,v8,v0.t'
|
|
|
++.*Error: illegal operands `vmul.vx v0,v4,a1,v0.t'
|
|
|
++.*Error: illegal operands `vmulh.vv v0,v4,v8,v0.t'
|
|
|
++.*Error: illegal operands `vmulh.vx v0,v4,a1,v0.t'
|
|
|
++.*Error: illegal operands `vmulhu.vv v0,v4,v8,v0.t'
|
|
|
++.*Error: illegal operands `vmulhu.vx v0,v4,a1,v0.t'
|
|
|
++.*Error: illegal operands `vmulhsu.vv v0,v4,v8,v0.t'
|
|
|
++.*Error: illegal operands `vmulhsu.vx v0,v4,a1,v0.t'
|
|
|
++.*Error: illegal operands `vdivu.vv v0,v4,v8,v0.t'
|
|
|
++.*Error: illegal operands `vdivu.vx v0,v4,a1,v0.t'
|
|
|
++.*Error: illegal operands `vdiv.vv v0,v4,v8,v0.t'
|
|
|
++.*Error: illegal operands `vdiv.vx v0,v4,a1,v0.t'
|
|
|
++.*Error: illegal operands `vremu.vv v0,v4,v8,v0.t'
|
|
|
++.*Error: illegal operands `vremu.vx v0,v4,a1,v0.t'
|
|
|
++.*Error: illegal operands `vrem.vv v0,v4,v8,v0.t'
|
|
|
++.*Error: illegal operands `vrem.vx v0,v4,a1,v0.t'
|
|
|
++.*Error: illegal operands `vmacc.vv v0,v4,v8,v0.t'
|
|
|
++.*Error: illegal operands `vmacc.vx v0,a1,v4,v0.t'
|
|
|
++.*Error: illegal operands `vnmsac.vv v0,v4,v8,v0.t'
|
|
|
++.*Error: illegal operands `vnmsac.vx v0,a1,v4,v0.t'
|
|
|
++.*Error: illegal operands `vmadd.vv v0,v4,v8,v0.t'
|
|
|
++.*Error: illegal operands `vmadd.vx v0,a1,v4,v0.t'
|
|
|
++.*Error: illegal operands `vnmsub.vv v0,v4,v8,v0.t'
|
|
|
++.*Error: illegal operands `vnmsub.vx v0,a1,v4,v0.t'
|
|
|
+diff --git a/gas/testsuite/gas/riscv/vector-insns-fail-arith-int.s b/gas/testsuite/gas/riscv/vector-insns-fail-arith-int.s
|
|
|
+new file mode 100644
|
|
|
+index 0000000000..af0d1737ff
|
|
|
+--- /dev/null
|
|
|
++++ b/gas/testsuite/gas/riscv/vector-insns-fail-arith-int.s
|
|
|
+@@ -0,0 +1,187 @@
|
|
|
++# Vector Single-Width Integer Add and Subtract
|
|
|
++
|
|
|
++ vneg.v v4, v4 # OK
|
|
|
++ vneg.v v0, v4, v0.t # vd overlap vm
|
|
|
++
|
|
|
++ vadd.vv v4, v4, v8 # OK
|
|
|
++ vadd.vv v8, v4, v8 # OK
|
|
|
++ vadd.vv v0, v4, v8, v0.t # vd overlap vm
|
|
|
++ vadd.vx v4, v4, a1 # OK
|
|
|
++ vadd.vx v0, v4, a1, v0.t # vd overlap vm
|
|
|
++ vadd.vi v4, v4, 15 # OK
|
|
|
++ vadd.vi v0, v4, 15, v0.t # vd overlap vm
|
|
|
++
|
|
|
++ vsub.vv v4, v4, v8 # OK
|
|
|
++ vsub.vv v8, v4, v8 # OK
|
|
|
++ vsub.vv v0, v4, v8, v0.t # vd overlap vm
|
|
|
++ vsub.vx v4, v4, a1 # OK
|
|
|
++ vsub.vx v0, v4, a1, v0.t # vd overlap vm
|
|
|
++
|
|
|
++ vrsub.vx v4, v4, a1 # OK
|
|
|
++ vrsub.vx v0, v4, a1, v0.t # vd overlap vm
|
|
|
++ vrsub.vi v4, v4, 15 # OK
|
|
|
++ vrsub.vi v0, v4, 15, v0.t # vd overlap vm
|
|
|
++
|
|
|
++# Vector Integer Extension
|
|
|
++
|
|
|
++ vzext.vf2 v4, v4 # OK
|
|
|
++ vzext.vf2 v0, v4, v0.t # vd overlap vm
|
|
|
++ vsext.vf2 v4, v4
|
|
|
++ vsext.vf2 v0, v4, v0.t
|
|
|
++ vzext.vf4 v4, v4
|
|
|
++ vzext.vf4 v0, v4, v0.t
|
|
|
++ vsext.vf4 v4, v4
|
|
|
++ vsext.vf4 v0, v4, v0.t
|
|
|
++ vzext.vf8 v4, v4
|
|
|
++ vzext.vf8 v0, v4, v0.t
|
|
|
++ vsext.vf8 v4, v4
|
|
|
++ vsext.vf8 v0, v4, v0.t
|
|
|
++
|
|
|
++# Vector Integer Add-with-Carry / Subtract-with-Borrow Instructions
|
|
|
++
|
|
|
++ vadc.vvm v4, v4, v8, v0 # OK
|
|
|
++ vadc.vvm v8, v4, v8, v0 # OK
|
|
|
++ vadc.vvm v0, v4, v8, v0 # vd overlap vm
|
|
|
++ vadc.vxm v4, v4, a1, v0 # OK
|
|
|
++ vadc.vxm v0, v4, a1, v0 # vd overlap vm
|
|
|
++ vadc.vim v4, v4, 15, v0 # OK
|
|
|
++ vadc.vim v0, v4, 15, v0 # vd overlap vm
|
|
|
++
|
|
|
++ vsbc.vvm v4, v4, v8, v0 # OK
|
|
|
++ vsbc.vvm v8, v4, v8, v0 # OK
|
|
|
++ vsbc.vvm v0, v4, v8, v0 # vd overlap vm
|
|
|
++ vsbc.vxm v4, v4, a1, v0 # OK
|
|
|
++ vsbc.vxm v0, v4, a1, v0 # vd overlap vm
|
|
|
++
|
|
|
++# Vector Bitwise Logical Instructions
|
|
|
++
|
|
|
++ vnot.v v4, v4 # OK
|
|
|
++ vnot.v v0, v4, v0.t # vd overlap vm
|
|
|
++
|
|
|
++ vand.vv v4, v4, v8 # OK
|
|
|
++ vand.vv v8, v4, v8 # OK
|
|
|
++ vand.vv v0, v4, v8, v0.t # vd overlap vm
|
|
|
++ vand.vx v4, v4, a1 # OK
|
|
|
++ vand.vx v0, v4, a1, v0.t # vd overlap vm
|
|
|
++ vand.vi v4, v4, 15 # OK
|
|
|
++ vand.vi v0, v4, 15, v0.t # vd overlap vm
|
|
|
++
|
|
|
++ vor.vv v4, v4, v8
|
|
|
++ vor.vv v8, v4, v8
|
|
|
++ vor.vv v0, v4, v8, v0.t
|
|
|
++ vor.vx v4, v4, a1
|
|
|
++ vor.vx v0, v4, a1, v0.t
|
|
|
++ vor.vi v4, v4, 15
|
|
|
++ vor.vi v0, v4, 15, v0.t
|
|
|
++
|
|
|
++ vxor.vv v4, v4, v8
|
|
|
++ vxor.vv v8, v4, v8
|
|
|
++ vxor.vv v0, v4, v8, v0.t
|
|
|
++ vxor.vx v4, v4, a1
|
|
|
++ vxor.vx v0, v4, a1, v0.t
|
|
|
++ vxor.vi v4, v4, 15
|
|
|
++ vxor.vi v0, v4, 15, v0.t
|
|
|
++
|
|
|
++# Vector Integer Min/Max Instructions
|
|
|
++
|
|
|
++ vminu.vv v4, v4, v8 # OK
|
|
|
++ vminu.vv v8, v4, v8 # OK
|
|
|
++ vminu.vv v0, v4, v8, v0.t # vd overlap vm
|
|
|
++ vminu.vx v4, v4, a1 # OK
|
|
|
++ vminu.vx v0, v4, a1, v0.t # vd overlap vm
|
|
|
++
|
|
|
++ vmin.vv v4, v4, v8
|
|
|
++ vmin.vv v8, v4, v8
|
|
|
++ vmin.vv v0, v4, v8, v0.t
|
|
|
++ vmin.vx v4, v4, a1
|
|
|
++ vmin.vx v0, v4, a1, v0.t
|
|
|
++
|
|
|
++ vmaxu.vv v4, v4, v8
|
|
|
++ vmaxu.vv v8, v4, v8
|
|
|
++ vmaxu.vv v0, v4, v8, v0.t
|
|
|
++ vmaxu.vx v4, v4, a1
|
|
|
++ vmaxu.vx v0, v4, a1, v0.t
|
|
|
++
|
|
|
++ vmax.vv v4, v4, v8
|
|
|
++ vmax.vv v8, v4, v8
|
|
|
++ vmax.vv v0, v4, v8, v0.t
|
|
|
++ vmax.vx v4, v4, a1
|
|
|
++ vmax.vx v0, v4, a1, v0.t
|
|
|
++
|
|
|
++# Vector Single-Width Integer Multiply Instructions
|
|
|
++
|
|
|
++ vmul.vv v4, v4, v8 # OK
|
|
|
++ vmul.vv v8, v4, v8 # OK
|
|
|
++ vmul.vv v0, v4, v8, v0.t # vd overlap vm
|
|
|
++ vmul.vx v4, v4, a1 # OK
|
|
|
++ vmul.vx v0, v4, a1, v0.t # vd overlap vm
|
|
|
++
|
|
|
++ vmulh.vv v4, v4, v8
|
|
|
++ vmulh.vv v8, v4, v8
|
|
|
++ vmulh.vv v0, v4, v8, v0.t
|
|
|
++ vmulh.vx v4, v4, a1
|
|
|
++ vmulh.vx v0, v4, a1, v0.t
|
|
|
++
|
|
|
++ vmulhu.vv v4, v4, v8
|
|
|
++ vmulhu.vv v8, v4, v8
|
|
|
++ vmulhu.vv v0, v4, v8, v0.t
|
|
|
++ vmulhu.vx v4, v4, a1
|
|
|
++ vmulhu.vx v0, v4, a1, v0.t
|
|
|
++
|
|
|
++ vmulhsu.vv v4, v4, v8
|
|
|
++ vmulhsu.vv v8, v4, v8
|
|
|
++ vmulhsu.vv v0, v4, v8, v0.t
|
|
|
++ vmulhsu.vx v4, v4, a1
|
|
|
++ vmulhsu.vx v0, v4, a1, v0.t
|
|
|
++
|
|
|
++# Vector Integer Divide Instructions
|
|
|
++
|
|
|
++ vdivu.vv v4, v4, v8 # OK
|
|
|
++ vdivu.vv v8, v4, v8 # OK
|
|
|
++ vdivu.vv v0, v4, v8, v0.t # vd overlap vm
|
|
|
++ vdivu.vx v4, v4, a1 # OK
|
|
|
++ vdivu.vx v0, v4, a1, v0.t # vd overlap vm
|
|
|
++
|
|
|
++ vdiv.vv v4, v4, v8
|
|
|
++ vdiv.vv v8, v4, v8
|
|
|
++ vdiv.vv v0, v4, v8, v0.t
|
|
|
++ vdiv.vx v4, v4, a1
|
|
|
++ vdiv.vx v0, v4, a1, v0.t
|
|
|
++
|
|
|
++ vremu.vv v4, v4, v8
|
|
|
++ vremu.vv v8, v4, v8
|
|
|
++ vremu.vv v0, v4, v8, v0.t
|
|
|
++ vremu.vx v4, v4, a1
|
|
|
++ vremu.vx v0, v4, a1, v0.t
|
|
|
++
|
|
|
++ vrem.vv v4, v4, v8
|
|
|
++ vrem.vv v8, v4, v8
|
|
|
++ vrem.vv v0, v4, v8, v0.t
|
|
|
++ vrem.vx v4, v4, a1
|
|
|
++ vrem.vx v0, v4, a1, v0.t
|
|
|
++
|
|
|
++# Vector Single-Width Integer Multiply-Add Instructions
|
|
|
++
|
|
|
++ vmacc.vv v4, v4, v8 # OK
|
|
|
++ vmacc.vv v8, v4, v8 # OK
|
|
|
++ vmacc.vv v0, v4, v8, v0.t # vd overlap vm
|
|
|
++ vmacc.vx v4, a1, v4 # OK
|
|
|
++ vmacc.vx v0, a1, v4, v0.t # vd overlap vm
|
|
|
++
|
|
|
++ vnmsac.vv v4, v4, v8
|
|
|
++ vnmsac.vv v8, v4, v8
|
|
|
++ vnmsac.vv v0, v4, v8, v0.t
|
|
|
++ vnmsac.vx v4, a1, v4
|
|
|
++ vnmsac.vx v0, a1, v4, v0.t
|
|
|
++
|
|
|
++ vmadd.vv v4, v4, v8
|
|
|
++ vmadd.vv v8, v4, v8
|
|
|
++ vmadd.vv v0, v4, v8, v0.t
|
|
|
++ vmadd.vx v4, a1, v4
|
|
|
++ vmadd.vx v0, a1, v4, v0.t
|
|
|
++
|
|
|
++ vnmsub.vv v4, v4, v8
|
|
|
++ vnmsub.vv v8, v4, v8
|
|
|
++ vnmsub.vv v0, v4, v8, v0.t
|
|
|
++ vnmsub.vx v4, a1, v4
|
|
|
++ vnmsub.vx v0, a1, v4, v0.t
|
|
|
+diff --git a/gas/testsuite/gas/riscv/vector-insns-fail-load-store.d b/gas/testsuite/gas/riscv/vector-insns-fail-load-store.d
|
|
|
+new file mode 100644
|
|
|
+index 0000000000..7d3d6bfe78
|
|
|
+--- /dev/null
|
|
|
++++ b/gas/testsuite/gas/riscv/vector-insns-fail-load-store.d
|
|
|
+@@ -0,0 +1,3 @@
|
|
|
++#as: -march=rv32iv0p10
|
|
|
++#source: vector-insns-fail-load-store.s
|
|
|
++#error_output: vector-insns-fail-load-store.l
|
|
|
+diff --git a/gas/testsuite/gas/riscv/vector-insns-fail-load-store.l b/gas/testsuite/gas/riscv/vector-insns-fail-load-store.l
|
|
|
+new file mode 100644
|
|
|
+index 0000000000..47259a3a7e
|
|
|
+--- /dev/null
|
|
|
++++ b/gas/testsuite/gas/riscv/vector-insns-fail-load-store.l
|
|
|
+@@ -0,0 +1,25 @@
|
|
|
++.*: Assembler messages:
|
|
|
++.*Error: illegal operands `vle8.v v0,\(a0\),v0.t'
|
|
|
++.*Error: illegal operands `vle16.v v0,\(a0\),v0.t'
|
|
|
++.*Error: illegal operands `vle32.v v0,\(a0\),v0.t'
|
|
|
++.*Error: illegal operands `vle64.v v0,\(a0\),v0.t'
|
|
|
++.*Error: illegal operands `vse8.v v0,\(a0\),v0.t'
|
|
|
++.*Error: illegal operands `vse16.v v0,\(a0\),v0.t'
|
|
|
++.*Error: illegal operands `vse32.v v0,\(a0\),v0.t'
|
|
|
++.*Error: illegal operands `vse64.v v0,\(a0\),v0.t'
|
|
|
++.*Error: illegal operands `vlse8.v v0,\(a0\),a1,v0.t'
|
|
|
++.*Error: illegal operands `vlse16.v v0,\(a0\),a1,v0.t'
|
|
|
++.*Error: illegal operands `vlse32.v v0,\(a0\),a1,v0.t'
|
|
|
++.*Error: illegal operands `vlse64.v v0,\(a0\),a1,v0.t'
|
|
|
++.*Error: illegal operands `vsse8.v v0,\(a0\),a1,v0.t'
|
|
|
++.*Error: illegal operands `vsse16.v v0,\(a0\),a1,v0.t'
|
|
|
++.*Error: illegal operands `vsse32.v v0,\(a0\),a1,v0.t'
|
|
|
++.*Error: illegal operands `vsse64.v v0,\(a0\),a1,v0.t'
|
|
|
++.*Error: illegal operands `vloxei8.v v0,\(a0\),v4,v0.t'
|
|
|
++.*Error: illegal operands `vloxei16.v v0,\(a0\),v4,v0.t'
|
|
|
++.*Error: illegal operands `vloxei32.v v0,\(a0\),v4,v0.t'
|
|
|
++.*Error: illegal operands `vloxei64.v v0,\(a0\),v4,v0.t'
|
|
|
++.*Error: illegal operands `vsoxei8.v v0,\(a0\),v4,v0.t'
|
|
|
++.*Error: illegal operands `vsoxei16.v v0,\(a0\),v4,v0.t'
|
|
|
++.*Error: illegal operands `vsoxei32.v v0,\(a0\),v4,v0.t'
|
|
|
++.*Error: illegal operands `vsoxei64.v v0,\(a0\),v4,v0.t'
|
|
|
+diff --git a/gas/testsuite/gas/riscv/vector-insns-fail-load-store.s b/gas/testsuite/gas/riscv/vector-insns-fail-load-store.s
|
|
|
+new file mode 100644
|
|
|
+index 0000000000..ce3b9ec013
|
|
|
+--- /dev/null
|
|
|
++++ b/gas/testsuite/gas/riscv/vector-insns-fail-load-store.s
|
|
|
+@@ -0,0 +1,43 @@
|
|
|
++# Vector Unit-Stride Loads and Stores
|
|
|
++
|
|
|
++ vle8.v v0, (a0), v0.t # vd overlap vm
|
|
|
++ vle16.v v0, (a0), v0.t
|
|
|
++ vle32.v v0, (a0), v0.t
|
|
|
++ vle64.v v0, (a0), v0.t
|
|
|
++
|
|
|
++ vse8.v v0, (a0), v0.t # vd overlap vm
|
|
|
++ vse16.v v0, (a0), v0.t
|
|
|
++ vse32.v v0, (a0), v0.t
|
|
|
++ vse64.v v0, (a0), v0.t
|
|
|
++
|
|
|
++# Vector Strided Loads and Stores
|
|
|
++
|
|
|
++ vlse8.v v0, (a0), a1, v0.t # vd overlap vm
|
|
|
++ vlse16.v v0, (a0), a1, v0.t
|
|
|
++ vlse32.v v0, (a0), a1, v0.t
|
|
|
++ vlse64.v v0, (a0), a1, v0.t
|
|
|
++
|
|
|
++ vsse8.v v0, (a0), a1, v0.t
|
|
|
++ vsse16.v v0, (a0), a1, v0.t
|
|
|
++ vsse32.v v0, (a0), a1, v0.t
|
|
|
++ vsse64.v v0, (a0), a1, v0.t
|
|
|
++
|
|
|
++# Vector Ordered Indexed Loads and Stores
|
|
|
++
|
|
|
++ vloxei8.v v4, (a0), v4 # OK
|
|
|
++ vloxei8.v v0, (a0), v4, v0.t # vd overlap vm
|
|
|
++ vloxei16.v v4, (a0), v4
|
|
|
++ vloxei16.v v0, (a0), v4, v0.t
|
|
|
++ vloxei32.v v4, (a0), v4
|
|
|
++ vloxei32.v v0, (a0), v4, v0.t
|
|
|
++ vloxei64.v v4, (a0), v4
|
|
|
++ vloxei64.v v0, (a0), v4, v0.t
|
|
|
++
|
|
|
++ vsoxei8.v v4, (a0), v4
|
|
|
++ vsoxei8.v v0, (a0), v4, v0.t
|
|
|
++ vsoxei16.v v4, (a0), v4
|
|
|
++ vsoxei16.v v0, (a0), v4, v0.t
|
|
|
++ vsoxei32.v v4, (a0), v4
|
|
|
++ vsoxei32.v v0, (a0), v4, v0.t
|
|
|
++ vsoxei64.v v4, (a0), v4
|
|
|
++ vsoxei64.v v0, (a0), v4, v0.t
|
|
|
+diff --git a/gas/testsuite/gas/riscv/vector-insns-fail-permutation.d b/gas/testsuite/gas/riscv/vector-insns-fail-permutation.d
|
|
|
+new file mode 100644
|
|
|
+index 0000000000..ebdd2b1051
|
|
|
+--- /dev/null
|
|
|
++++ b/gas/testsuite/gas/riscv/vector-insns-fail-permutation.d
|
|
|
+@@ -0,0 +1,3 @@
|
|
|
++#as: -march=rv32ifv0p10
|
|
|
++#source: vector-insns-fail-permutation.s
|
|
|
++#error_output: vector-insns-fail-permutation.l
|
|
|
+diff --git a/gas/testsuite/gas/riscv/vector-insns-fail-permutation.l b/gas/testsuite/gas/riscv/vector-insns-fail-permutation.l
|
|
|
+new file mode 100644
|
|
|
+index 0000000000..682f1cd9a4
|
|
|
+--- /dev/null
|
|
|
++++ b/gas/testsuite/gas/riscv/vector-insns-fail-permutation.l
|
|
|
+@@ -0,0 +1,19 @@
|
|
|
++.*: Assembler messages:
|
|
|
++.*Error: illegal operands `vslideup.vx v4,v4,a1'
|
|
|
++.*Error: illegal operands `vslideup.vx v0,v4,a1,v0.t'
|
|
|
++.*Error: illegal operands `vslideup.vi v4,v4,31'
|
|
|
++.*Error: illegal operands `vslideup.vi v0,v4,31,v0.t'
|
|
|
++.*Error: illegal operands `vslidedown.vx v0,v4,a1,v0.t'
|
|
|
++.*Error: illegal operands `vslidedown.vi v0,v4,31,v0.t'
|
|
|
++.*Error: illegal operands `vslide1up.vx v4,v4,a1'
|
|
|
++.*Error: illegal operands `vslide1up.vx v0,v4,a1,v0.t'
|
|
|
++.*Error: illegal operands `vfslide1up.vf v4,v4,fa1'
|
|
|
++.*Error: illegal operands `vfslide1up.vf v0,v4,fa1,v0.t'
|
|
|
++.*Error: illegal operands `vslide1down.vx v0,v4,a1,v0.t'
|
|
|
++.*Error: illegal operands `vfslide1down.vf v0,v4,fa1,v0.t'
|
|
|
++.*Error: illegal operands `vrgather.vx v4,v4,a1'
|
|
|
++.*Error: illegal operands `vrgather.vx v0,v4,a1,v0.t'
|
|
|
++.*Error: illegal operands `vrgather.vi v4,v4,31'
|
|
|
++.*Error: illegal operands `vrgather.vi v0,v4,31,v0.t'
|
|
|
++.*Error: illegal operands `vcompress.vm v4,v4,v8'
|
|
|
++.*Error: illegal operands `vcompress.vm v8,v4,v8'
|
|
|
+diff --git a/gas/testsuite/gas/riscv/vector-insns-fail-permutation.s b/gas/testsuite/gas/riscv/vector-insns-fail-permutation.s
|
|
|
+new file mode 100644
|
|
|
+index 0000000000..834bee925b
|
|
|
+--- /dev/null
|
|
|
++++ b/gas/testsuite/gas/riscv/vector-insns-fail-permutation.s
|
|
|
+@@ -0,0 +1,37 @@
|
|
|
++# Vector Slideup Instructions
|
|
|
++
|
|
|
++ vslideup.vx v4, v4, a1 # vd overlap vs2
|
|
|
++ vslideup.vx v0, v4, a1, v0.t # vd overlap vm
|
|
|
++ vslideup.vi v4, v4, 31 # vd overlap vs2
|
|
|
++ vslideup.vi v0, v4, 31, v0.t # vd overlap vm
|
|
|
++
|
|
|
++ vslidedown.vx v4, v4, a1 # OK
|
|
|
++ vslidedown.vx v0, v4, a1, v0.t # vd overlap vm
|
|
|
++ vslidedown.vi v4, v4, 31 # OK
|
|
|
++ vslidedown.vi v0, v4, 31, v0.t # vd overlap vm
|
|
|
++
|
|
|
++ vslide1up.vx v4, v4, a1 # vd overlap vs2
|
|
|
++ vslide1up.vx v0, v4, a1, v0.t # vd overlap vm
|
|
|
++ vfslide1up.vf v4, v4, fa1 # vd overlap vs2
|
|
|
++ vfslide1up.vf v0, v4, fa1, v0.t # vd overlap vm
|
|
|
++
|
|
|
++ vslide1down.vx v4, v4, a1 # OK
|
|
|
++ vslide1down.vx v0, v4, a1, v0.t # vd overlap vm
|
|
|
++ vfslide1down.vf v4, v4, fa1 # OK
|
|
|
++ vfslide1down.vf v0, v4, fa1, v0.t # vd overlap vm
|
|
|
++
|
|
|
++# Vector Register Gather Instructions
|
|
|
++
|
|
|
++ vrgather.vv v4, v4, v8 # vd overlap vs2
|
|
|
++ vrgather.vv v8, v4, v8 # vd overlap vs1
|
|
|
++ vrgather.vv v0, v4, v8, v0.t # vd overlap vm
|
|
|
++ vrgather.vx v4, v4, a1 # vd overlap vs2
|
|
|
++ vrgather.vx v0, v4, a1, v0.t # vd overlap vm
|
|
|
++ vrgather.vi v4, v4, 31 # vd overlap vs2
|
|
|
++ vrgather.vi v0, v4, 31, v0.t # vd overlap vm
|
|
|
++
|
|
|
++# Vector Compress Instruction
|
|
|
++
|
|
|
++ vcompress.vm v4, v4, v8 # vd overlap vs2
|
|
|
++ vcompress.vm v8, v4, v8 # vd overlap vs1
|
|
|
++
|
|
|
+diff --git a/gas/testsuite/gas/riscv/vector-insns-fail-unsupport.d b/gas/testsuite/gas/riscv/vector-insns-fail-unsupport.d
|
|
|
+new file mode 100644
|
|
|
+index 0000000000..cca6928e7d
|
|
|
+--- /dev/null
|
|
|
++++ b/gas/testsuite/gas/riscv/vector-insns-fail-unsupport.d
|
|
|
+@@ -0,0 +1,3 @@
|
|
|
++#as: -march=rv32iv0p10
|
|
|
++#source: vector-insns-fail-unsupport.s
|
|
|
++#error_output: vector-insns-fail-unsupport.l
|
|
|
+diff --git a/gas/testsuite/gas/riscv/vector-insns-fail-unsupport.l b/gas/testsuite/gas/riscv/vector-insns-fail-unsupport.l
|
|
|
+new file mode 100644
|
|
|
+index 0000000000..ae2230cb9e
|
|
|
+--- /dev/null
|
|
|
++++ b/gas/testsuite/gas/riscv/vector-insns-fail-unsupport.l
|
|
|
+@@ -0,0 +1,1469 @@
|
|
|
++.*: Assembler messages:
|
|
|
++.*: Error: unrecognized opcode `vsetivli a0,0xb,0'
|
|
|
++.*: Error: unrecognized opcode `vsetivli a0,0xb,0x3ff'
|
|
|
++.*: Error: unrecognized opcode `vsetivli a0,0xb,e16,m2'
|
|
|
++.*: Error: unrecognized opcode `vsetivli a0,0xb,e256,m8'
|
|
|
++.*: Error: unrecognized opcode `vsetivli a0,0xb,e512,m8'
|
|
|
++.*: Error: unrecognized opcode `vsetivli a0,0xb,e1024,m8'
|
|
|
++.*: Error: unrecognized opcode `vsetivli a0,0xb,e1024,m1'
|
|
|
++.*: Error: unrecognized opcode `vsetivli a0,0xb,e1024,mf2'
|
|
|
++.*: Error: unrecognized opcode `vsetivli a0,0xb,e512,mf4'
|
|
|
++.*: Error: unrecognized opcode `vsetivli a0,0xb,e256,mf8'
|
|
|
++.*: Error: unrecognized opcode `vsetivli a0,0xb,e256,m2,ta'
|
|
|
++.*: Error: unrecognized opcode `vsetivli a0,0xb,e256,m2,ma'
|
|
|
++.*: Error: unrecognized opcode `vsetivli a0,0xb,e256,m2,tu'
|
|
|
++.*: Error: unrecognized opcode `vsetivli a0,0xb,e256,m2,mu'
|
|
|
++.*: Error: unrecognized opcode `vsetivli a0,0xb,e256,m2,ta,ma'
|
|
|
++.*: Error: unrecognized opcode `vsetivli a0,0xb,e256,m2,tu,ma'
|
|
|
++.*: Error: unrecognized opcode `vsetivli a0,0xb,e256,m2,ta,mu'
|
|
|
++.*: Error: unrecognized opcode `vsetivli a0,0xb,e256,m2,tu,mu'
|
|
|
++.*: Error: unrecognized opcode `vle1.v v4,\(a0\)'
|
|
|
++.*: Error: unrecognized opcode `vle1.v v4,0\(a0\)'
|
|
|
++.*: Error: unrecognized opcode `vse1.v v4,\(a0\)'
|
|
|
++.*: Error: unrecognized opcode `vse1.v v4,0\(a0\)'
|
|
|
++.*: Error: unrecognized opcode `vluxei8.v v4,\(a0\),v12'
|
|
|
++.*: Error: unrecognized opcode `vluxei8.v v4,0\(a0\),v12'
|
|
|
++.*: Error: unrecognized opcode `vluxei8.v v4,\(a0\),v12,v0.t'
|
|
|
++.*: Error: unrecognized opcode `vsuxei8.v v4,\(a0\),v12'
|
|
|
++.*: Error: unrecognized opcode `vsuxei8.v v4,0\(a0\),v12'
|
|
|
++.*: Error: unrecognized opcode `vsuxei8.v v4,\(a0\),v12,v0.t'
|
|
|
++.*: Error: unrecognized opcode `vluxei16.v v4,\(a0\),v12'
|
|
|
++.*: Error: unrecognized opcode `vluxei16.v v4,0\(a0\),v12'
|
|
|
++.*: Error: unrecognized opcode `vluxei16.v v4,\(a0\),v12,v0.t'
|
|
|
++.*: Error: unrecognized opcode `vsuxei16.v v4,\(a0\),v12'
|
|
|
++.*: Error: unrecognized opcode `vsuxei16.v v4,0\(a0\),v12'
|
|
|
++.*: Error: unrecognized opcode `vsuxei16.v v4,\(a0\),v12,v0.t'
|
|
|
++.*: Error: unrecognized opcode `vluxei32.v v4,\(a0\),v12'
|
|
|
++.*: Error: unrecognized opcode `vluxei32.v v4,0\(a0\),v12'
|
|
|
++.*: Error: unrecognized opcode `vluxei32.v v4,\(a0\),v12,v0.t'
|
|
|
++.*: Error: unrecognized opcode `vsuxei32.v v4,\(a0\),v12'
|
|
|
++.*: Error: unrecognized opcode `vsuxei32.v v4,0\(a0\),v12'
|
|
|
++.*: Error: unrecognized opcode `vsuxei32.v v4,\(a0\),v12,v0.t'
|
|
|
++.*: Error: unrecognized opcode `vluxei64.v v4,\(a0\),v12'
|
|
|
++.*: Error: unrecognized opcode `vluxei64.v v4,0\(a0\),v12'
|
|
|
++.*: Error: unrecognized opcode `vluxei64.v v4,\(a0\),v12,v0.t'
|
|
|
++.*: Error: unrecognized opcode `vsuxei64.v v4,\(a0\),v12'
|
|
|
++.*: Error: unrecognized opcode `vsuxei64.v v4,0\(a0\),v12'
|
|
|
++.*: Error: unrecognized opcode `vsuxei64.v v4,\(a0\),v12,v0.t'
|
|
|
++.*: Error: unrecognized opcode `vle8ff.v v4,\(a0\)'
|
|
|
++.*: Error: unrecognized opcode `vle8ff.v v4,0\(a0\)'
|
|
|
++.*: Error: unrecognized opcode `vle8ff.v v4,\(a0\),v0.t'
|
|
|
++.*: Error: unrecognized opcode `vle16ff.v v4,\(a0\)'
|
|
|
++.*: Error: unrecognized opcode `vle16ff.v v4,0\(a0\)'
|
|
|
++.*: Error: unrecognized opcode `vle16ff.v v4,\(a0\),v0.t'
|
|
|
++.*: Error: unrecognized opcode `vle32ff.v v4,\(a0\)'
|
|
|
++.*: Error: unrecognized opcode `vle32ff.v v4,0\(a0\)'
|
|
|
++.*: Error: unrecognized opcode `vle32ff.v v4,\(a0\),v0.t'
|
|
|
++.*: Error: unrecognized opcode `vle64ff.v v4,\(a0\)'
|
|
|
++.*: Error: unrecognized opcode `vle64ff.v v4,0\(a0\)'
|
|
|
++.*: Error: unrecognized opcode `vle64ff.v v4,\(a0\),v0.t'
|
|
|
++.*: Error: unrecognized opcode `vlseg2e8.v v4,\(a0\)'
|
|
|
++.*: Error: unrecognized opcode `vlseg2e8.v v4,0\(a0\)'
|
|
|
++.*: Error: unrecognized opcode `vlseg2e8.v v4,\(a0\),v0.t'
|
|
|
++.*: Error: unrecognized opcode `vsseg2e8.v v4,\(a0\)'
|
|
|
++.*: Error: unrecognized opcode `vsseg2e8.v v4,0\(a0\)'
|
|
|
++.*: Error: unrecognized opcode `vsseg2e8.v v4,\(a0\),v0.t'
|
|
|
++.*: Error: unrecognized opcode `vlseg3e8.v v4,\(a0\)'
|
|
|
++.*: Error: unrecognized opcode `vlseg3e8.v v4,0\(a0\)'
|
|
|
++.*: Error: unrecognized opcode `vlseg3e8.v v4,\(a0\),v0.t'
|
|
|
++.*: Error: unrecognized opcode `vsseg3e8.v v4,\(a0\)'
|
|
|
++.*: Error: unrecognized opcode `vsseg3e8.v v4,0\(a0\)'
|
|
|
++.*: Error: unrecognized opcode `vsseg3e8.v v4,\(a0\),v0.t'
|
|
|
++.*: Error: unrecognized opcode `vlseg4e8.v v4,\(a0\)'
|
|
|
++.*: Error: unrecognized opcode `vlseg4e8.v v4,0\(a0\)'
|
|
|
++.*: Error: unrecognized opcode `vlseg4e8.v v4,\(a0\),v0.t'
|
|
|
++.*: Error: unrecognized opcode `vsseg4e8.v v4,\(a0\)'
|
|
|
++.*: Error: unrecognized opcode `vsseg4e8.v v4,0\(a0\)'
|
|
|
++.*: Error: unrecognized opcode `vsseg4e8.v v4,\(a0\),v0.t'
|
|
|
++.*: Error: unrecognized opcode `vlseg5e8.v v4,\(a0\)'
|
|
|
++.*: Error: unrecognized opcode `vlseg5e8.v v4,0\(a0\)'
|
|
|
++.*: Error: unrecognized opcode `vlseg5e8.v v4,\(a0\),v0.t'
|
|
|
++.*: Error: unrecognized opcode `vsseg5e8.v v4,\(a0\)'
|
|
|
++.*: Error: unrecognized opcode `vsseg5e8.v v4,0\(a0\)'
|
|
|
++.*: Error: unrecognized opcode `vsseg5e8.v v4,\(a0\),v0.t'
|
|
|
++.*: Error: unrecognized opcode `vlseg6e8.v v4,\(a0\)'
|
|
|
++.*: Error: unrecognized opcode `vlseg6e8.v v4,0\(a0\)'
|
|
|
++.*: Error: unrecognized opcode `vlseg6e8.v v4,\(a0\),v0.t'
|
|
|
++.*: Error: unrecognized opcode `vsseg6e8.v v4,\(a0\)'
|
|
|
++.*: Error: unrecognized opcode `vsseg6e8.v v4,0\(a0\)'
|
|
|
++.*: Error: unrecognized opcode `vsseg6e8.v v4,\(a0\),v0.t'
|
|
|
++.*: Error: unrecognized opcode `vlseg7e8.v v4,\(a0\)'
|
|
|
++.*: Error: unrecognized opcode `vlseg7e8.v v4,0\(a0\)'
|
|
|
++.*: Error: unrecognized opcode `vlseg7e8.v v4,\(a0\),v0.t'
|
|
|
++.*: Error: unrecognized opcode `vsseg7e8.v v4,\(a0\)'
|
|
|
++.*: Error: unrecognized opcode `vsseg7e8.v v4,0\(a0\)'
|
|
|
++.*: Error: unrecognized opcode `vsseg7e8.v v4,\(a0\),v0.t'
|
|
|
++.*: Error: unrecognized opcode `vlseg8e8.v v4,\(a0\)'
|
|
|
++.*: Error: unrecognized opcode `vlseg8e8.v v4,0\(a0\)'
|
|
|
++.*: Error: unrecognized opcode `vlseg8e8.v v4,\(a0\),v0.t'
|
|
|
++.*: Error: unrecognized opcode `vsseg8e8.v v4,\(a0\)'
|
|
|
++.*: Error: unrecognized opcode `vsseg8e8.v v4,0\(a0\)'
|
|
|
++.*: Error: unrecognized opcode `vsseg8e8.v v4,\(a0\),v0.t'
|
|
|
++.*: Error: unrecognized opcode `vlseg2e16.v v4,\(a0\)'
|
|
|
++.*: Error: unrecognized opcode `vlseg2e16.v v4,0\(a0\)'
|
|
|
++.*: Error: unrecognized opcode `vlseg2e16.v v4,\(a0\),v0.t'
|
|
|
++.*: Error: unrecognized opcode `vsseg2e16.v v4,\(a0\)'
|
|
|
++.*: Error: unrecognized opcode `vsseg2e16.v v4,0\(a0\)'
|
|
|
++.*: Error: unrecognized opcode `vsseg2e16.v v4,\(a0\),v0.t'
|
|
|
++.*: Error: unrecognized opcode `vlseg3e16.v v4,\(a0\)'
|
|
|
++.*: Error: unrecognized opcode `vlseg3e16.v v4,0\(a0\)'
|
|
|
++.*: Error: unrecognized opcode `vlseg3e16.v v4,\(a0\),v0.t'
|
|
|
++.*: Error: unrecognized opcode `vsseg3e16.v v4,\(a0\)'
|
|
|
++.*: Error: unrecognized opcode `vsseg3e16.v v4,0\(a0\)'
|
|
|
++.*: Error: unrecognized opcode `vsseg3e16.v v4,\(a0\),v0.t'
|
|
|
++.*: Error: unrecognized opcode `vlseg4e16.v v4,\(a0\)'
|
|
|
++.*: Error: unrecognized opcode `vlseg4e16.v v4,0\(a0\)'
|
|
|
++.*: Error: unrecognized opcode `vlseg4e16.v v4,\(a0\),v0.t'
|
|
|
++.*: Error: unrecognized opcode `vsseg4e16.v v4,\(a0\)'
|
|
|
++.*: Error: unrecognized opcode `vsseg4e16.v v4,0\(a0\)'
|
|
|
++.*: Error: unrecognized opcode `vsseg4e16.v v4,\(a0\),v0.t'
|
|
|
++.*: Error: unrecognized opcode `vlseg5e16.v v4,\(a0\)'
|
|
|
++.*: Error: unrecognized opcode `vlseg5e16.v v4,0\(a0\)'
|
|
|
++.*: Error: unrecognized opcode `vlseg5e16.v v4,\(a0\),v0.t'
|
|
|
++.*: Error: unrecognized opcode `vsseg5e16.v v4,\(a0\)'
|
|
|
++.*: Error: unrecognized opcode `vsseg5e16.v v4,0\(a0\)'
|
|
|
++.*: Error: unrecognized opcode `vsseg5e16.v v4,\(a0\),v0.t'
|
|
|
++.*: Error: unrecognized opcode `vlseg6e16.v v4,\(a0\)'
|
|
|
++.*: Error: unrecognized opcode `vlseg6e16.v v4,0\(a0\)'
|
|
|
++.*: Error: unrecognized opcode `vlseg6e16.v v4,\(a0\),v0.t'
|
|
|
++.*: Error: unrecognized opcode `vsseg6e16.v v4,\(a0\)'
|
|
|
++.*: Error: unrecognized opcode `vsseg6e16.v v4,0\(a0\)'
|
|
|
++.*: Error: unrecognized opcode `vsseg6e16.v v4,\(a0\),v0.t'
|
|
|
++.*: Error: unrecognized opcode `vlseg7e16.v v4,\(a0\)'
|
|
|
++.*: Error: unrecognized opcode `vlseg7e16.v v4,0\(a0\)'
|
|
|
++.*: Error: unrecognized opcode `vlseg7e16.v v4,\(a0\),v0.t'
|
|
|
++.*: Error: unrecognized opcode `vsseg7e16.v v4,\(a0\)'
|
|
|
++.*: Error: unrecognized opcode `vsseg7e16.v v4,0\(a0\)'
|
|
|
++.*: Error: unrecognized opcode `vsseg7e16.v v4,\(a0\),v0.t'
|
|
|
++.*: Error: unrecognized opcode `vlseg8e16.v v4,\(a0\)'
|
|
|
++.*: Error: unrecognized opcode `vlseg8e16.v v4,0\(a0\)'
|
|
|
++.*: Error: unrecognized opcode `vlseg8e16.v v4,\(a0\),v0.t'
|
|
|
++.*: Error: unrecognized opcode `vsseg8e16.v v4,\(a0\)'
|
|
|
++.*: Error: unrecognized opcode `vsseg8e16.v v4,0\(a0\)'
|
|
|
++.*: Error: unrecognized opcode `vsseg8e16.v v4,\(a0\),v0.t'
|
|
|
++.*: Error: unrecognized opcode `vlseg2e32.v v4,\(a0\)'
|
|
|
++.*: Error: unrecognized opcode `vlseg2e32.v v4,0\(a0\)'
|
|
|
++.*: Error: unrecognized opcode `vlseg2e32.v v4,\(a0\),v0.t'
|
|
|
++.*: Error: unrecognized opcode `vsseg2e32.v v4,\(a0\)'
|
|
|
++.*: Error: unrecognized opcode `vsseg2e32.v v4,0\(a0\)'
|
|
|
++.*: Error: unrecognized opcode `vsseg2e32.v v4,\(a0\),v0.t'
|
|
|
++.*: Error: unrecognized opcode `vlseg3e32.v v4,\(a0\)'
|
|
|
++.*: Error: unrecognized opcode `vlseg3e32.v v4,0\(a0\)'
|
|
|
++.*: Error: unrecognized opcode `vlseg3e32.v v4,\(a0\),v0.t'
|
|
|
++.*: Error: unrecognized opcode `vsseg3e32.v v4,\(a0\)'
|
|
|
++.*: Error: unrecognized opcode `vsseg3e32.v v4,0\(a0\)'
|
|
|
++.*: Error: unrecognized opcode `vsseg3e32.v v4,\(a0\),v0.t'
|
|
|
++.*: Error: unrecognized opcode `vlseg4e32.v v4,\(a0\)'
|
|
|
++.*: Error: unrecognized opcode `vlseg4e32.v v4,0\(a0\)'
|
|
|
++.*: Error: unrecognized opcode `vlseg4e32.v v4,\(a0\),v0.t'
|
|
|
++.*: Error: unrecognized opcode `vsseg4e32.v v4,\(a0\)'
|
|
|
++.*: Error: unrecognized opcode `vsseg4e32.v v4,0\(a0\)'
|
|
|
++.*: Error: unrecognized opcode `vsseg4e32.v v4,\(a0\),v0.t'
|
|
|
++.*: Error: unrecognized opcode `vlseg5e32.v v4,\(a0\)'
|
|
|
++.*: Error: unrecognized opcode `vlseg5e32.v v4,0\(a0\)'
|
|
|
++.*: Error: unrecognized opcode `vlseg5e32.v v4,\(a0\),v0.t'
|
|
|
++.*: Error: unrecognized opcode `vsseg5e32.v v4,\(a0\)'
|
|
|
++.*: Error: unrecognized opcode `vsseg5e32.v v4,0\(a0\)'
|
|
|
++.*: Error: unrecognized opcode `vsseg5e32.v v4,\(a0\),v0.t'
|
|
|
++.*: Error: unrecognized opcode `vlseg6e32.v v4,\(a0\)'
|
|
|
++.*: Error: unrecognized opcode `vlseg6e32.v v4,0\(a0\)'
|
|
|
++.*: Error: unrecognized opcode `vlseg6e32.v v4,\(a0\),v0.t'
|
|
|
++.*: Error: unrecognized opcode `vsseg6e32.v v4,\(a0\)'
|
|
|
++.*: Error: unrecognized opcode `vsseg6e32.v v4,0\(a0\)'
|
|
|
++.*: Error: unrecognized opcode `vsseg6e32.v v4,\(a0\),v0.t'
|
|
|
++.*: Error: unrecognized opcode `vlseg7e32.v v4,\(a0\)'
|
|
|
++.*: Error: unrecognized opcode `vlseg7e32.v v4,0\(a0\)'
|
|
|
++.*: Error: unrecognized opcode `vlseg7e32.v v4,\(a0\),v0.t'
|
|
|
++.*: Error: unrecognized opcode `vsseg7e32.v v4,\(a0\)'
|
|
|
++.*: Error: unrecognized opcode `vsseg7e32.v v4,0\(a0\)'
|
|
|
++.*: Error: unrecognized opcode `vsseg7e32.v v4,\(a0\),v0.t'
|
|
|
++.*: Error: unrecognized opcode `vlseg8e32.v v4,\(a0\)'
|
|
|
++.*: Error: unrecognized opcode `vlseg8e32.v v4,0\(a0\)'
|
|
|
++.*: Error: unrecognized opcode `vlseg8e32.v v4,\(a0\),v0.t'
|
|
|
++.*: Error: unrecognized opcode `vsseg8e32.v v4,\(a0\)'
|
|
|
++.*: Error: unrecognized opcode `vsseg8e32.v v4,0\(a0\)'
|
|
|
++.*: Error: unrecognized opcode `vsseg8e32.v v4,\(a0\),v0.t'
|
|
|
++.*: Error: unrecognized opcode `vlseg2e64.v v4,\(a0\)'
|
|
|
++.*: Error: unrecognized opcode `vlseg2e64.v v4,0\(a0\)'
|
|
|
++.*: Error: unrecognized opcode `vlseg2e64.v v4,\(a0\),v0.t'
|
|
|
++.*: Error: unrecognized opcode `vsseg2e64.v v4,\(a0\)'
|
|
|
++.*: Error: unrecognized opcode `vsseg2e64.v v4,0\(a0\)'
|
|
|
++.*: Error: unrecognized opcode `vsseg2e64.v v4,\(a0\),v0.t'
|
|
|
++.*: Error: unrecognized opcode `vlseg3e64.v v4,\(a0\)'
|
|
|
++.*: Error: unrecognized opcode `vlseg3e64.v v4,0\(a0\)'
|
|
|
++.*: Error: unrecognized opcode `vlseg3e64.v v4,\(a0\),v0.t'
|
|
|
++.*: Error: unrecognized opcode `vsseg3e64.v v4,\(a0\)'
|
|
|
++.*: Error: unrecognized opcode `vsseg3e64.v v4,0\(a0\)'
|
|
|
++.*: Error: unrecognized opcode `vsseg3e64.v v4,\(a0\),v0.t'
|
|
|
++.*: Error: unrecognized opcode `vlseg4e64.v v4,\(a0\)'
|
|
|
++.*: Error: unrecognized opcode `vlseg4e64.v v4,0\(a0\)'
|
|
|
++.*: Error: unrecognized opcode `vlseg4e64.v v4,\(a0\),v0.t'
|
|
|
++.*: Error: unrecognized opcode `vsseg4e64.v v4,\(a0\)'
|
|
|
++.*: Error: unrecognized opcode `vsseg4e64.v v4,0\(a0\)'
|
|
|
++.*: Error: unrecognized opcode `vsseg4e64.v v4,\(a0\),v0.t'
|
|
|
++.*: Error: unrecognized opcode `vlseg5e64.v v4,\(a0\)'
|
|
|
++.*: Error: unrecognized opcode `vlseg5e64.v v4,0\(a0\)'
|
|
|
++.*: Error: unrecognized opcode `vlseg5e64.v v4,\(a0\),v0.t'
|
|
|
++.*: Error: unrecognized opcode `vsseg5e64.v v4,\(a0\)'
|
|
|
++.*: Error: unrecognized opcode `vsseg5e64.v v4,0\(a0\)'
|
|
|
++.*: Error: unrecognized opcode `vsseg5e64.v v4,\(a0\),v0.t'
|
|
|
++.*: Error: unrecognized opcode `vlseg6e64.v v4,\(a0\)'
|
|
|
++.*: Error: unrecognized opcode `vlseg6e64.v v4,0\(a0\)'
|
|
|
++.*: Error: unrecognized opcode `vlseg6e64.v v4,\(a0\),v0.t'
|
|
|
++.*: Error: unrecognized opcode `vsseg6e64.v v4,\(a0\)'
|
|
|
++.*: Error: unrecognized opcode `vsseg6e64.v v4,0\(a0\)'
|
|
|
++.*: Error: unrecognized opcode `vsseg6e64.v v4,\(a0\),v0.t'
|
|
|
++.*: Error: unrecognized opcode `vlseg7e64.v v4,\(a0\)'
|
|
|
++.*: Error: unrecognized opcode `vlseg7e64.v v4,0\(a0\)'
|
|
|
++.*: Error: unrecognized opcode `vlseg7e64.v v4,\(a0\),v0.t'
|
|
|
++.*: Error: unrecognized opcode `vsseg7e64.v v4,\(a0\)'
|
|
|
++.*: Error: unrecognized opcode `vsseg7e64.v v4,0\(a0\)'
|
|
|
++.*: Error: unrecognized opcode `vsseg7e64.v v4,\(a0\),v0.t'
|
|
|
++.*: Error: unrecognized opcode `vlseg8e64.v v4,\(a0\)'
|
|
|
++.*: Error: unrecognized opcode `vlseg8e64.v v4,0\(a0\)'
|
|
|
++.*: Error: unrecognized opcode `vlseg8e64.v v4,\(a0\),v0.t'
|
|
|
++.*: Error: unrecognized opcode `vsseg8e64.v v4,\(a0\)'
|
|
|
++.*: Error: unrecognized opcode `vsseg8e64.v v4,0\(a0\)'
|
|
|
++.*: Error: unrecognized opcode `vsseg8e64.v v4,\(a0\),v0.t'
|
|
|
++.*: Error: unrecognized opcode `vlsseg2e8.v v4,\(a0\),a1'
|
|
|
++.*: Error: unrecognized opcode `vlsseg2e8.v v4,0\(a0\),a1'
|
|
|
++.*: Error: unrecognized opcode `vlsseg2e8.v v4,\(a0\),a1,v0.t'
|
|
|
++.*: Error: unrecognized opcode `vssseg2e8.v v4,\(a0\),a1'
|
|
|
++.*: Error: unrecognized opcode `vssseg2e8.v v4,0\(a0\),a1'
|
|
|
++.*: Error: unrecognized opcode `vssseg2e8.v v4,\(a0\),a1,v0.t'
|
|
|
++.*: Error: unrecognized opcode `vlsseg3e8.v v4,\(a0\),a1'
|
|
|
++.*: Error: unrecognized opcode `vlsseg3e8.v v4,0\(a0\),a1'
|
|
|
++.*: Error: unrecognized opcode `vlsseg3e8.v v4,\(a0\),a1,v0.t'
|
|
|
++.*: Error: unrecognized opcode `vssseg3e8.v v4,\(a0\),a1'
|
|
|
++.*: Error: unrecognized opcode `vssseg3e8.v v4,0\(a0\),a1'
|
|
|
++.*: Error: unrecognized opcode `vssseg3e8.v v4,\(a0\),a1,v0.t'
|
|
|
++.*: Error: unrecognized opcode `vlsseg4e8.v v4,\(a0\),a1'
|
|
|
++.*: Error: unrecognized opcode `vlsseg4e8.v v4,0\(a0\),a1'
|
|
|
++.*: Error: unrecognized opcode `vlsseg4e8.v v4,\(a0\),a1,v0.t'
|
|
|
++.*: Error: unrecognized opcode `vssseg4e8.v v4,\(a0\),a1'
|
|
|
++.*: Error: unrecognized opcode `vssseg4e8.v v4,0\(a0\),a1'
|
|
|
++.*: Error: unrecognized opcode `vssseg4e8.v v4,\(a0\),a1,v0.t'
|
|
|
++.*: Error: unrecognized opcode `vlsseg5e8.v v4,\(a0\),a1'
|
|
|
++.*: Error: unrecognized opcode `vlsseg5e8.v v4,0\(a0\),a1'
|
|
|
++.*: Error: unrecognized opcode `vlsseg5e8.v v4,\(a0\),a1,v0.t'
|
|
|
++.*: Error: unrecognized opcode `vssseg5e8.v v4,\(a0\),a1'
|
|
|
++.*: Error: unrecognized opcode `vssseg5e8.v v4,0\(a0\),a1'
|
|
|
++.*: Error: unrecognized opcode `vssseg5e8.v v4,\(a0\),a1,v0.t'
|
|
|
++.*: Error: unrecognized opcode `vlsseg6e8.v v4,\(a0\),a1'
|
|
|
++.*: Error: unrecognized opcode `vlsseg6e8.v v4,0\(a0\),a1'
|
|
|
++.*: Error: unrecognized opcode `vlsseg6e8.v v4,\(a0\),a1,v0.t'
|
|
|
++.*: Error: unrecognized opcode `vssseg6e8.v v4,\(a0\),a1'
|
|
|
++.*: Error: unrecognized opcode `vssseg6e8.v v4,0\(a0\),a1'
|
|
|
++.*: Error: unrecognized opcode `vssseg6e8.v v4,\(a0\),a1,v0.t'
|
|
|
++.*: Error: unrecognized opcode `vlsseg7e8.v v4,\(a0\),a1'
|
|
|
++.*: Error: unrecognized opcode `vlsseg7e8.v v4,0\(a0\),a1'
|
|
|
++.*: Error: unrecognized opcode `vlsseg7e8.v v4,\(a0\),a1,v0.t'
|
|
|
++.*: Error: unrecognized opcode `vssseg7e8.v v4,\(a0\),a1'
|
|
|
++.*: Error: unrecognized opcode `vssseg7e8.v v4,0\(a0\),a1'
|
|
|
++.*: Error: unrecognized opcode `vssseg7e8.v v4,\(a0\),a1,v0.t'
|
|
|
++.*: Error: unrecognized opcode `vlsseg8e8.v v4,\(a0\),a1'
|
|
|
++.*: Error: unrecognized opcode `vlsseg8e8.v v4,0\(a0\),a1'
|
|
|
++.*: Error: unrecognized opcode `vlsseg8e8.v v4,\(a0\),a1,v0.t'
|
|
|
++.*: Error: unrecognized opcode `vssseg8e8.v v4,\(a0\),a1'
|
|
|
++.*: Error: unrecognized opcode `vssseg8e8.v v4,0\(a0\),a1'
|
|
|
++.*: Error: unrecognized opcode `vssseg8e8.v v4,\(a0\),a1,v0.t'
|
|
|
++.*: Error: unrecognized opcode `vlsseg2e16.v v4,\(a0\),a1'
|
|
|
++.*: Error: unrecognized opcode `vlsseg2e16.v v4,0\(a0\),a1'
|
|
|
++.*: Error: unrecognized opcode `vlsseg2e16.v v4,\(a0\),a1,v0.t'
|
|
|
++.*: Error: unrecognized opcode `vssseg2e16.v v4,\(a0\),a1'
|
|
|
++.*: Error: unrecognized opcode `vssseg2e16.v v4,0\(a0\),a1'
|
|
|
++.*: Error: unrecognized opcode `vssseg2e16.v v4,\(a0\),a1,v0.t'
|
|
|
++.*: Error: unrecognized opcode `vlsseg3e16.v v4,\(a0\),a1'
|
|
|
++.*: Error: unrecognized opcode `vlsseg3e16.v v4,0\(a0\),a1'
|
|
|
++.*: Error: unrecognized opcode `vlsseg3e16.v v4,\(a0\),a1,v0.t'
|
|
|
++.*: Error: unrecognized opcode `vssseg3e16.v v4,\(a0\),a1'
|
|
|
++.*: Error: unrecognized opcode `vssseg3e16.v v4,0\(a0\),a1'
|
|
|
++.*: Error: unrecognized opcode `vssseg3e16.v v4,\(a0\),a1,v0.t'
|
|
|
++.*: Error: unrecognized opcode `vlsseg4e16.v v4,\(a0\),a1'
|
|
|
++.*: Error: unrecognized opcode `vlsseg4e16.v v4,0\(a0\),a1'
|
|
|
++.*: Error: unrecognized opcode `vlsseg4e16.v v4,\(a0\),a1,v0.t'
|
|
|
++.*: Error: unrecognized opcode `vssseg4e16.v v4,\(a0\),a1'
|
|
|
++.*: Error: unrecognized opcode `vssseg4e16.v v4,0\(a0\),a1'
|
|
|
++.*: Error: unrecognized opcode `vssseg4e16.v v4,\(a0\),a1,v0.t'
|
|
|
++.*: Error: unrecognized opcode `vlsseg5e16.v v4,\(a0\),a1'
|
|
|
++.*: Error: unrecognized opcode `vlsseg5e16.v v4,0\(a0\),a1'
|
|
|
++.*: Error: unrecognized opcode `vlsseg5e16.v v4,\(a0\),a1,v0.t'
|
|
|
++.*: Error: unrecognized opcode `vssseg5e16.v v4,\(a0\),a1'
|
|
|
++.*: Error: unrecognized opcode `vssseg5e16.v v4,0\(a0\),a1'
|
|
|
++.*: Error: unrecognized opcode `vssseg5e16.v v4,\(a0\),a1,v0.t'
|
|
|
++.*: Error: unrecognized opcode `vlsseg6e16.v v4,\(a0\),a1'
|
|
|
++.*: Error: unrecognized opcode `vlsseg6e16.v v4,0\(a0\),a1'
|
|
|
++.*: Error: unrecognized opcode `vlsseg6e16.v v4,\(a0\),a1,v0.t'
|
|
|
++.*: Error: unrecognized opcode `vssseg6e16.v v4,\(a0\),a1'
|
|
|
++.*: Error: unrecognized opcode `vssseg6e16.v v4,0\(a0\),a1'
|
|
|
++.*: Error: unrecognized opcode `vssseg6e16.v v4,\(a0\),a1,v0.t'
|
|
|
++.*: Error: unrecognized opcode `vlsseg7e16.v v4,\(a0\),a1'
|
|
|
++.*: Error: unrecognized opcode `vlsseg7e16.v v4,0\(a0\),a1'
|
|
|
++.*: Error: unrecognized opcode `vlsseg7e16.v v4,\(a0\),a1,v0.t'
|
|
|
++.*: Error: unrecognized opcode `vssseg7e16.v v4,\(a0\),a1'
|
|
|
++.*: Error: unrecognized opcode `vssseg7e16.v v4,0\(a0\),a1'
|
|
|
++.*: Error: unrecognized opcode `vssseg7e16.v v4,\(a0\),a1,v0.t'
|
|
|
++.*: Error: unrecognized opcode `vlsseg8e16.v v4,\(a0\),a1'
|
|
|
++.*: Error: unrecognized opcode `vlsseg8e16.v v4,0\(a0\),a1'
|
|
|
++.*: Error: unrecognized opcode `vlsseg8e16.v v4,\(a0\),a1,v0.t'
|
|
|
++.*: Error: unrecognized opcode `vssseg8e16.v v4,\(a0\),a1'
|
|
|
++.*: Error: unrecognized opcode `vssseg8e16.v v4,0\(a0\),a1'
|
|
|
++.*: Error: unrecognized opcode `vssseg8e16.v v4,\(a0\),a1,v0.t'
|
|
|
++.*: Error: unrecognized opcode `vlsseg2e32.v v4,\(a0\),a1'
|
|
|
++.*: Error: unrecognized opcode `vlsseg2e32.v v4,0\(a0\),a1'
|
|
|
++.*: Error: unrecognized opcode `vlsseg2e32.v v4,\(a0\),a1,v0.t'
|
|
|
++.*: Error: unrecognized opcode `vssseg2e32.v v4,\(a0\),a1'
|
|
|
++.*: Error: unrecognized opcode `vssseg2e32.v v4,0\(a0\),a1'
|
|
|
++.*: Error: unrecognized opcode `vssseg2e32.v v4,\(a0\),a1,v0.t'
|
|
|
++.*: Error: unrecognized opcode `vlsseg3e32.v v4,\(a0\),a1'
|
|
|
++.*: Error: unrecognized opcode `vlsseg3e32.v v4,0\(a0\),a1'
|
|
|
++.*: Error: unrecognized opcode `vlsseg3e32.v v4,\(a0\),a1,v0.t'
|
|
|
++.*: Error: unrecognized opcode `vssseg3e32.v v4,\(a0\),a1'
|
|
|
++.*: Error: unrecognized opcode `vssseg3e32.v v4,0\(a0\),a1'
|
|
|
++.*: Error: unrecognized opcode `vssseg3e32.v v4,\(a0\),a1,v0.t'
|
|
|
++.*: Error: unrecognized opcode `vlsseg4e32.v v4,\(a0\),a1'
|
|
|
++.*: Error: unrecognized opcode `vlsseg4e32.v v4,0\(a0\),a1'
|
|
|
++.*: Error: unrecognized opcode `vlsseg4e32.v v4,\(a0\),a1,v0.t'
|
|
|
++.*: Error: unrecognized opcode `vssseg4e32.v v4,\(a0\),a1'
|
|
|
++.*: Error: unrecognized opcode `vssseg4e32.v v4,0\(a0\),a1'
|
|
|
++.*: Error: unrecognized opcode `vssseg4e32.v v4,\(a0\),a1,v0.t'
|
|
|
++.*: Error: unrecognized opcode `vlsseg5e32.v v4,\(a0\),a1'
|
|
|
++.*: Error: unrecognized opcode `vlsseg5e32.v v4,0\(a0\),a1'
|
|
|
++.*: Error: unrecognized opcode `vlsseg5e32.v v4,\(a0\),a1,v0.t'
|
|
|
++.*: Error: unrecognized opcode `vssseg5e32.v v4,\(a0\),a1'
|
|
|
++.*: Error: unrecognized opcode `vssseg5e32.v v4,0\(a0\),a1'
|
|
|
++.*: Error: unrecognized opcode `vssseg5e32.v v4,\(a0\),a1,v0.t'
|
|
|
++.*: Error: unrecognized opcode `vlsseg6e32.v v4,\(a0\),a1'
|
|
|
++.*: Error: unrecognized opcode `vlsseg6e32.v v4,0\(a0\),a1'
|
|
|
++.*: Error: unrecognized opcode `vlsseg6e32.v v4,\(a0\),a1,v0.t'
|
|
|
++.*: Error: unrecognized opcode `vssseg6e32.v v4,\(a0\),a1'
|
|
|
++.*: Error: unrecognized opcode `vssseg6e32.v v4,0\(a0\),a1'
|
|
|
++.*: Error: unrecognized opcode `vssseg6e32.v v4,\(a0\),a1,v0.t'
|
|
|
++.*: Error: unrecognized opcode `vlsseg7e32.v v4,\(a0\),a1'
|
|
|
++.*: Error: unrecognized opcode `vlsseg7e32.v v4,0\(a0\),a1'
|
|
|
++.*: Error: unrecognized opcode `vlsseg7e32.v v4,\(a0\),a1,v0.t'
|
|
|
++.*: Error: unrecognized opcode `vssseg7e32.v v4,\(a0\),a1'
|
|
|
++.*: Error: unrecognized opcode `vssseg7e32.v v4,0\(a0\),a1'
|
|
|
++.*: Error: unrecognized opcode `vssseg7e32.v v4,\(a0\),a1,v0.t'
|
|
|
++.*: Error: unrecognized opcode `vlsseg8e32.v v4,\(a0\),a1'
|
|
|
++.*: Error: unrecognized opcode `vlsseg8e32.v v4,0\(a0\),a1'
|
|
|
++.*: Error: unrecognized opcode `vlsseg8e32.v v4,\(a0\),a1,v0.t'
|
|
|
++.*: Error: unrecognized opcode `vssseg8e32.v v4,\(a0\),a1'
|
|
|
++.*: Error: unrecognized opcode `vssseg8e32.v v4,0\(a0\),a1'
|
|
|
++.*: Error: unrecognized opcode `vssseg8e32.v v4,\(a0\),a1,v0.t'
|
|
|
++.*: Error: unrecognized opcode `vlsseg2e64.v v4,\(a0\),a1'
|
|
|
++.*: Error: unrecognized opcode `vlsseg2e64.v v4,0\(a0\),a1'
|
|
|
++.*: Error: unrecognized opcode `vlsseg2e64.v v4,\(a0\),a1,v0.t'
|
|
|
++.*: Error: unrecognized opcode `vssseg2e64.v v4,\(a0\),a1'
|
|
|
++.*: Error: unrecognized opcode `vssseg2e64.v v4,0\(a0\),a1'
|
|
|
++.*: Error: unrecognized opcode `vssseg2e64.v v4,\(a0\),a1,v0.t'
|
|
|
++.*: Error: unrecognized opcode `vlsseg3e64.v v4,\(a0\),a1'
|
|
|
++.*: Error: unrecognized opcode `vlsseg3e64.v v4,0\(a0\),a1'
|
|
|
++.*: Error: unrecognized opcode `vlsseg3e64.v v4,\(a0\),a1,v0.t'
|
|
|
++.*: Error: unrecognized opcode `vssseg3e64.v v4,\(a0\),a1'
|
|
|
++.*: Error: unrecognized opcode `vssseg3e64.v v4,0\(a0\),a1'
|
|
|
++.*: Error: unrecognized opcode `vssseg3e64.v v4,\(a0\),a1,v0.t'
|
|
|
++.*: Error: unrecognized opcode `vlsseg4e64.v v4,\(a0\),a1'
|
|
|
++.*: Error: unrecognized opcode `vlsseg4e64.v v4,0\(a0\),a1'
|
|
|
++.*: Error: unrecognized opcode `vlsseg4e64.v v4,\(a0\),a1,v0.t'
|
|
|
++.*: Error: unrecognized opcode `vssseg4e64.v v4,\(a0\),a1'
|
|
|
++.*: Error: unrecognized opcode `vssseg4e64.v v4,0\(a0\),a1'
|
|
|
++.*: Error: unrecognized opcode `vssseg4e64.v v4,\(a0\),a1,v0.t'
|
|
|
++.*: Error: unrecognized opcode `vlsseg5e64.v v4,\(a0\),a1'
|
|
|
++.*: Error: unrecognized opcode `vlsseg5e64.v v4,0\(a0\),a1'
|
|
|
++.*: Error: unrecognized opcode `vlsseg5e64.v v4,\(a0\),a1,v0.t'
|
|
|
++.*: Error: unrecognized opcode `vssseg5e64.v v4,\(a0\),a1'
|
|
|
++.*: Error: unrecognized opcode `vssseg5e64.v v4,0\(a0\),a1'
|
|
|
++.*: Error: unrecognized opcode `vssseg5e64.v v4,\(a0\),a1,v0.t'
|
|
|
++.*: Error: unrecognized opcode `vlsseg6e64.v v4,\(a0\),a1'
|
|
|
++.*: Error: unrecognized opcode `vlsseg6e64.v v4,0\(a0\),a1'
|
|
|
++.*: Error: unrecognized opcode `vlsseg6e64.v v4,\(a0\),a1,v0.t'
|
|
|
++.*: Error: unrecognized opcode `vssseg6e64.v v4,\(a0\),a1'
|
|
|
++.*: Error: unrecognized opcode `vssseg6e64.v v4,0\(a0\),a1'
|
|
|
++.*: Error: unrecognized opcode `vssseg6e64.v v4,\(a0\),a1,v0.t'
|
|
|
++.*: Error: unrecognized opcode `vlsseg7e64.v v4,\(a0\),a1'
|
|
|
++.*: Error: unrecognized opcode `vlsseg7e64.v v4,0\(a0\),a1'
|
|
|
++.*: Error: unrecognized opcode `vlsseg7e64.v v4,\(a0\),a1,v0.t'
|
|
|
++.*: Error: unrecognized opcode `vssseg7e64.v v4,\(a0\),a1'
|
|
|
++.*: Error: unrecognized opcode `vssseg7e64.v v4,0\(a0\),a1'
|
|
|
++.*: Error: unrecognized opcode `vssseg7e64.v v4,\(a0\),a1,v0.t'
|
|
|
++.*: Error: unrecognized opcode `vlsseg8e64.v v4,\(a0\),a1'
|
|
|
++.*: Error: unrecognized opcode `vlsseg8e64.v v4,0\(a0\),a1'
|
|
|
++.*: Error: unrecognized opcode `vlsseg8e64.v v4,\(a0\),a1,v0.t'
|
|
|
++.*: Error: unrecognized opcode `vssseg8e64.v v4,\(a0\),a1'
|
|
|
++.*: Error: unrecognized opcode `vssseg8e64.v v4,0\(a0\),a1'
|
|
|
++.*: Error: unrecognized opcode `vssseg8e64.v v4,\(a0\),a1,v0.t'
|
|
|
++.*: Error: unrecognized opcode `vloxseg2ei8.v v4,\(a0\),v12'
|
|
|
++.*: Error: unrecognized opcode `vloxseg2ei8.v v4,0\(a0\),v12'
|
|
|
++.*: Error: unrecognized opcode `vloxseg2ei8.v v4,\(a0\),v12,v0.t'
|
|
|
++.*: Error: unrecognized opcode `vsoxseg2ei8.v v4,\(a0\),v12'
|
|
|
++.*: Error: unrecognized opcode `vsoxseg2ei8.v v4,0\(a0\),v12'
|
|
|
++.*: Error: unrecognized opcode `vsoxseg2ei8.v v4,\(a0\),v12,v0.t'
|
|
|
++.*: Error: unrecognized opcode `vloxseg3ei8.v v4,\(a0\),v12'
|
|
|
++.*: Error: unrecognized opcode `vloxseg3ei8.v v4,0\(a0\),v12'
|
|
|
++.*: Error: unrecognized opcode `vloxseg3ei8.v v4,\(a0\),v12,v0.t'
|
|
|
++.*: Error: unrecognized opcode `vsoxseg3ei8.v v4,\(a0\),v12'
|
|
|
++.*: Error: unrecognized opcode `vsoxseg3ei8.v v4,0\(a0\),v12'
|
|
|
++.*: Error: unrecognized opcode `vsoxseg3ei8.v v4,\(a0\),v12,v0.t'
|
|
|
++.*: Error: unrecognized opcode `vloxseg4ei8.v v4,\(a0\),v12'
|
|
|
++.*: Error: unrecognized opcode `vloxseg4ei8.v v4,0\(a0\),v12'
|
|
|
++.*: Error: unrecognized opcode `vloxseg4ei8.v v4,\(a0\),v12,v0.t'
|
|
|
++.*: Error: unrecognized opcode `vsoxseg4ei8.v v4,\(a0\),v12'
|
|
|
++.*: Error: unrecognized opcode `vsoxseg4ei8.v v4,0\(a0\),v12'
|
|
|
++.*: Error: unrecognized opcode `vsoxseg4ei8.v v4,\(a0\),v12,v0.t'
|
|
|
++.*: Error: unrecognized opcode `vloxseg5ei8.v v4,\(a0\),v12'
|
|
|
++.*: Error: unrecognized opcode `vloxseg5ei8.v v4,0\(a0\),v12'
|
|
|
++.*: Error: unrecognized opcode `vloxseg5ei8.v v4,\(a0\),v12,v0.t'
|
|
|
++.*: Error: unrecognized opcode `vsoxseg5ei8.v v4,\(a0\),v12'
|
|
|
++.*: Error: unrecognized opcode `vsoxseg5ei8.v v4,0\(a0\),v12'
|
|
|
++.*: Error: unrecognized opcode `vsoxseg5ei8.v v4,\(a0\),v12,v0.t'
|
|
|
++.*: Error: unrecognized opcode `vloxseg6ei8.v v4,\(a0\),v12'
|
|
|
++.*: Error: unrecognized opcode `vloxseg6ei8.v v4,0\(a0\),v12'
|
|
|
++.*: Error: unrecognized opcode `vloxseg6ei8.v v4,\(a0\),v12,v0.t'
|
|
|
++.*: Error: unrecognized opcode `vsoxseg6ei8.v v4,\(a0\),v12'
|
|
|
++.*: Error: unrecognized opcode `vsoxseg6ei8.v v4,0\(a0\),v12'
|
|
|
++.*: Error: unrecognized opcode `vsoxseg6ei8.v v4,\(a0\),v12,v0.t'
|
|
|
++.*: Error: unrecognized opcode `vloxseg7ei8.v v4,\(a0\),v12'
|
|
|
++.*: Error: unrecognized opcode `vloxseg7ei8.v v4,0\(a0\),v12'
|
|
|
++.*: Error: unrecognized opcode `vloxseg7ei8.v v4,\(a0\),v12,v0.t'
|
|
|
++.*: Error: unrecognized opcode `vsoxseg7ei8.v v4,\(a0\),v12'
|
|
|
++.*: Error: unrecognized opcode `vsoxseg7ei8.v v4,0\(a0\),v12'
|
|
|
++.*: Error: unrecognized opcode `vsoxseg7ei8.v v4,\(a0\),v12,v0.t'
|
|
|
++.*: Error: unrecognized opcode `vloxseg8ei8.v v4,\(a0\),v12'
|
|
|
++.*: Error: unrecognized opcode `vloxseg8ei8.v v4,0\(a0\),v12'
|
|
|
++.*: Error: unrecognized opcode `vloxseg8ei8.v v4,\(a0\),v12,v0.t'
|
|
|
++.*: Error: unrecognized opcode `vsoxseg8ei8.v v4,\(a0\),v12'
|
|
|
++.*: Error: unrecognized opcode `vsoxseg8ei8.v v4,0\(a0\),v12'
|
|
|
++.*: Error: unrecognized opcode `vsoxseg8ei8.v v4,\(a0\),v12,v0.t'
|
|
|
++.*: Error: unrecognized opcode `vloxseg2ei16.v v4,\(a0\),v12'
|
|
|
++.*: Error: unrecognized opcode `vloxseg2ei16.v v4,0\(a0\),v12'
|
|
|
++.*: Error: unrecognized opcode `vloxseg2ei16.v v4,\(a0\),v12,v0.t'
|
|
|
++.*: Error: unrecognized opcode `vsoxseg2ei16.v v4,\(a0\),v12'
|
|
|
++.*: Error: unrecognized opcode `vsoxseg2ei16.v v4,0\(a0\),v12'
|
|
|
++.*: Error: unrecognized opcode `vsoxseg2ei16.v v4,\(a0\),v12,v0.t'
|
|
|
++.*: Error: unrecognized opcode `vloxseg3ei16.v v4,\(a0\),v12'
|
|
|
++.*: Error: unrecognized opcode `vloxseg3ei16.v v4,0\(a0\),v12'
|
|
|
++.*: Error: unrecognized opcode `vloxseg3ei16.v v4,\(a0\),v12,v0.t'
|
|
|
++.*: Error: unrecognized opcode `vsoxseg3ei16.v v4,\(a0\),v12'
|
|
|
++.*: Error: unrecognized opcode `vsoxseg3ei16.v v4,0\(a0\),v12'
|
|
|
++.*: Error: unrecognized opcode `vsoxseg3ei16.v v4,\(a0\),v12,v0.t'
|
|
|
++.*: Error: unrecognized opcode `vloxseg4ei16.v v4,\(a0\),v12'
|
|
|
++.*: Error: unrecognized opcode `vloxseg4ei16.v v4,0\(a0\),v12'
|
|
|
++.*: Error: unrecognized opcode `vloxseg4ei16.v v4,\(a0\),v12,v0.t'
|
|
|
++.*: Error: unrecognized opcode `vsoxseg4ei16.v v4,\(a0\),v12'
|
|
|
++.*: Error: unrecognized opcode `vsoxseg4ei16.v v4,0\(a0\),v12'
|
|
|
++.*: Error: unrecognized opcode `vsoxseg4ei16.v v4,\(a0\),v12,v0.t'
|
|
|
++.*: Error: unrecognized opcode `vloxseg5ei16.v v4,\(a0\),v12'
|
|
|
++.*: Error: unrecognized opcode `vloxseg5ei16.v v4,0\(a0\),v12'
|
|
|
++.*: Error: unrecognized opcode `vloxseg5ei16.v v4,\(a0\),v12,v0.t'
|
|
|
++.*: Error: unrecognized opcode `vsoxseg5ei16.v v4,\(a0\),v12'
|
|
|
++.*: Error: unrecognized opcode `vsoxseg5ei16.v v4,0\(a0\),v12'
|
|
|
++.*: Error: unrecognized opcode `vsoxseg5ei16.v v4,\(a0\),v12,v0.t'
|
|
|
++.*: Error: unrecognized opcode `vloxseg6ei16.v v4,\(a0\),v12'
|
|
|
++.*: Error: unrecognized opcode `vloxseg6ei16.v v4,0\(a0\),v12'
|
|
|
++.*: Error: unrecognized opcode `vloxseg6ei16.v v4,\(a0\),v12,v0.t'
|
|
|
++.*: Error: unrecognized opcode `vsoxseg6ei16.v v4,\(a0\),v12'
|
|
|
++.*: Error: unrecognized opcode `vsoxseg6ei16.v v4,0\(a0\),v12'
|
|
|
++.*: Error: unrecognized opcode `vsoxseg6ei16.v v4,\(a0\),v12,v0.t'
|
|
|
++.*: Error: unrecognized opcode `vloxseg7ei16.v v4,\(a0\),v12'
|
|
|
++.*: Error: unrecognized opcode `vloxseg7ei16.v v4,0\(a0\),v12'
|
|
|
++.*: Error: unrecognized opcode `vloxseg7ei16.v v4,\(a0\),v12,v0.t'
|
|
|
++.*: Error: unrecognized opcode `vsoxseg7ei16.v v4,\(a0\),v12'
|
|
|
++.*: Error: unrecognized opcode `vsoxseg7ei16.v v4,0\(a0\),v12'
|
|
|
++.*: Error: unrecognized opcode `vsoxseg7ei16.v v4,\(a0\),v12,v0.t'
|
|
|
++.*: Error: unrecognized opcode `vloxseg8ei16.v v4,\(a0\),v12'
|
|
|
++.*: Error: unrecognized opcode `vloxseg8ei16.v v4,0\(a0\),v12'
|
|
|
++.*: Error: unrecognized opcode `vloxseg8ei16.v v4,\(a0\),v12,v0.t'
|
|
|
++.*: Error: unrecognized opcode `vsoxseg8ei16.v v4,\(a0\),v12'
|
|
|
++.*: Error: unrecognized opcode `vsoxseg8ei16.v v4,0\(a0\),v12'
|
|
|
++.*: Error: unrecognized opcode `vsoxseg8ei16.v v4,\(a0\),v12,v0.t'
|
|
|
++.*: Error: unrecognized opcode `vloxseg2ei32.v v4,\(a0\),v12'
|
|
|
++.*: Error: unrecognized opcode `vloxseg2ei32.v v4,0\(a0\),v12'
|
|
|
++.*: Error: unrecognized opcode `vloxseg2ei32.v v4,\(a0\),v12,v0.t'
|
|
|
++.*: Error: unrecognized opcode `vsoxseg2ei32.v v4,\(a0\),v12'
|
|
|
++.*: Error: unrecognized opcode `vsoxseg2ei32.v v4,0\(a0\),v12'
|
|
|
++.*: Error: unrecognized opcode `vsoxseg2ei32.v v4,\(a0\),v12,v0.t'
|
|
|
++.*: Error: unrecognized opcode `vloxseg3ei32.v v4,\(a0\),v12'
|
|
|
++.*: Error: unrecognized opcode `vloxseg3ei32.v v4,0\(a0\),v12'
|
|
|
++.*: Error: unrecognized opcode `vloxseg3ei32.v v4,\(a0\),v12,v0.t'
|
|
|
++.*: Error: unrecognized opcode `vsoxseg3ei32.v v4,\(a0\),v12'
|
|
|
++.*: Error: unrecognized opcode `vsoxseg3ei32.v v4,0\(a0\),v12'
|
|
|
++.*: Error: unrecognized opcode `vsoxseg3ei32.v v4,\(a0\),v12,v0.t'
|
|
|
++.*: Error: unrecognized opcode `vloxseg4ei32.v v4,\(a0\),v12'
|
|
|
++.*: Error: unrecognized opcode `vloxseg4ei32.v v4,0\(a0\),v12'
|
|
|
++.*: Error: unrecognized opcode `vloxseg4ei32.v v4,\(a0\),v12,v0.t'
|
|
|
++.*: Error: unrecognized opcode `vsoxseg4ei32.v v4,\(a0\),v12'
|
|
|
++.*: Error: unrecognized opcode `vsoxseg4ei32.v v4,0\(a0\),v12'
|
|
|
++.*: Error: unrecognized opcode `vsoxseg4ei32.v v4,\(a0\),v12,v0.t'
|
|
|
++.*: Error: unrecognized opcode `vloxseg5ei32.v v4,\(a0\),v12'
|
|
|
++.*: Error: unrecognized opcode `vloxseg5ei32.v v4,0\(a0\),v12'
|
|
|
++.*: Error: unrecognized opcode `vloxseg5ei32.v v4,\(a0\),v12,v0.t'
|
|
|
++.*: Error: unrecognized opcode `vsoxseg5ei32.v v4,\(a0\),v12'
|
|
|
++.*: Error: unrecognized opcode `vsoxseg5ei32.v v4,0\(a0\),v12'
|
|
|
++.*: Error: unrecognized opcode `vsoxseg5ei32.v v4,\(a0\),v12,v0.t'
|
|
|
++.*: Error: unrecognized opcode `vloxseg6ei32.v v4,\(a0\),v12'
|
|
|
++.*: Error: unrecognized opcode `vloxseg6ei32.v v4,0\(a0\),v12'
|
|
|
++.*: Error: unrecognized opcode `vloxseg6ei32.v v4,\(a0\),v12,v0.t'
|
|
|
++.*: Error: unrecognized opcode `vsoxseg6ei32.v v4,\(a0\),v12'
|
|
|
++.*: Error: unrecognized opcode `vsoxseg6ei32.v v4,0\(a0\),v12'
|
|
|
++.*: Error: unrecognized opcode `vsoxseg6ei32.v v4,\(a0\),v12,v0.t'
|
|
|
++.*: Error: unrecognized opcode `vloxseg7ei32.v v4,\(a0\),v12'
|
|
|
++.*: Error: unrecognized opcode `vloxseg7ei32.v v4,0\(a0\),v12'
|
|
|
++.*: Error: unrecognized opcode `vloxseg7ei32.v v4,\(a0\),v12,v0.t'
|
|
|
++.*: Error: unrecognized opcode `vsoxseg7ei32.v v4,\(a0\),v12'
|
|
|
++.*: Error: unrecognized opcode `vsoxseg7ei32.v v4,0\(a0\),v12'
|
|
|
++.*: Error: unrecognized opcode `vsoxseg7ei32.v v4,\(a0\),v12,v0.t'
|
|
|
++.*: Error: unrecognized opcode `vloxseg8ei32.v v4,\(a0\),v12'
|
|
|
++.*: Error: unrecognized opcode `vloxseg8ei32.v v4,0\(a0\),v12'
|
|
|
++.*: Error: unrecognized opcode `vloxseg8ei32.v v4,\(a0\),v12,v0.t'
|
|
|
++.*: Error: unrecognized opcode `vsoxseg8ei32.v v4,\(a0\),v12'
|
|
|
++.*: Error: unrecognized opcode `vsoxseg8ei32.v v4,0\(a0\),v12'
|
|
|
++.*: Error: unrecognized opcode `vsoxseg8ei32.v v4,\(a0\),v12,v0.t'
|
|
|
++.*: Error: unrecognized opcode `vloxseg2ei64.v v4,\(a0\),v12'
|
|
|
++.*: Error: unrecognized opcode `vloxseg2ei64.v v4,0\(a0\),v12'
|
|
|
++.*: Error: unrecognized opcode `vloxseg2ei64.v v4,\(a0\),v12,v0.t'
|
|
|
++.*: Error: unrecognized opcode `vsoxseg2ei64.v v4,\(a0\),v12'
|
|
|
++.*: Error: unrecognized opcode `vsoxseg2ei64.v v4,0\(a0\),v12'
|
|
|
++.*: Error: unrecognized opcode `vsoxseg2ei64.v v4,\(a0\),v12,v0.t'
|
|
|
++.*: Error: unrecognized opcode `vloxseg3ei64.v v4,\(a0\),v12'
|
|
|
++.*: Error: unrecognized opcode `vloxseg3ei64.v v4,0\(a0\),v12'
|
|
|
++.*: Error: unrecognized opcode `vloxseg3ei64.v v4,\(a0\),v12,v0.t'
|
|
|
++.*: Error: unrecognized opcode `vsoxseg3ei64.v v4,\(a0\),v12'
|
|
|
++.*: Error: unrecognized opcode `vsoxseg3ei64.v v4,0\(a0\),v12'
|
|
|
++.*: Error: unrecognized opcode `vsoxseg3ei64.v v4,\(a0\),v12,v0.t'
|
|
|
++.*: Error: unrecognized opcode `vloxseg4ei64.v v4,\(a0\),v12'
|
|
|
++.*: Error: unrecognized opcode `vloxseg4ei64.v v4,0\(a0\),v12'
|
|
|
++.*: Error: unrecognized opcode `vloxseg4ei64.v v4,\(a0\),v12,v0.t'
|
|
|
++.*: Error: unrecognized opcode `vsoxseg4ei64.v v4,\(a0\),v12'
|
|
|
++.*: Error: unrecognized opcode `vsoxseg4ei64.v v4,0\(a0\),v12'
|
|
|
++.*: Error: unrecognized opcode `vsoxseg4ei64.v v4,\(a0\),v12,v0.t'
|
|
|
++.*: Error: unrecognized opcode `vloxseg5ei64.v v4,\(a0\),v12'
|
|
|
++.*: Error: unrecognized opcode `vloxseg5ei64.v v4,0\(a0\),v12'
|
|
|
++.*: Error: unrecognized opcode `vloxseg5ei64.v v4,\(a0\),v12,v0.t'
|
|
|
++.*: Error: unrecognized opcode `vsoxseg5ei64.v v4,\(a0\),v12'
|
|
|
++.*: Error: unrecognized opcode `vsoxseg5ei64.v v4,0\(a0\),v12'
|
|
|
++.*: Error: unrecognized opcode `vsoxseg5ei64.v v4,\(a0\),v12,v0.t'
|
|
|
++.*: Error: unrecognized opcode `vloxseg6ei64.v v4,\(a0\),v12'
|
|
|
++.*: Error: unrecognized opcode `vloxseg6ei64.v v4,0\(a0\),v12'
|
|
|
++.*: Error: unrecognized opcode `vloxseg6ei64.v v4,\(a0\),v12,v0.t'
|
|
|
++.*: Error: unrecognized opcode `vsoxseg6ei64.v v4,\(a0\),v12'
|
|
|
++.*: Error: unrecognized opcode `vsoxseg6ei64.v v4,0\(a0\),v12'
|
|
|
++.*: Error: unrecognized opcode `vsoxseg6ei64.v v4,\(a0\),v12,v0.t'
|
|
|
++.*: Error: unrecognized opcode `vloxseg7ei64.v v4,\(a0\),v12'
|
|
|
++.*: Error: unrecognized opcode `vloxseg7ei64.v v4,0\(a0\),v12'
|
|
|
++.*: Error: unrecognized opcode `vloxseg7ei64.v v4,\(a0\),v12,v0.t'
|
|
|
++.*: Error: unrecognized opcode `vsoxseg7ei64.v v4,\(a0\),v12'
|
|
|
++.*: Error: unrecognized opcode `vsoxseg7ei64.v v4,0\(a0\),v12'
|
|
|
++.*: Error: unrecognized opcode `vsoxseg7ei64.v v4,\(a0\),v12,v0.t'
|
|
|
++.*: Error: unrecognized opcode `vloxseg8ei64.v v4,\(a0\),v12'
|
|
|
++.*: Error: unrecognized opcode `vloxseg8ei64.v v4,0\(a0\),v12'
|
|
|
++.*: Error: unrecognized opcode `vloxseg8ei64.v v4,\(a0\),v12,v0.t'
|
|
|
++.*: Error: unrecognized opcode `vsoxseg8ei64.v v4,\(a0\),v12'
|
|
|
++.*: Error: unrecognized opcode `vsoxseg8ei64.v v4,0\(a0\),v12'
|
|
|
++.*: Error: unrecognized opcode `vsoxseg8ei64.v v4,\(a0\),v12,v0.t'
|
|
|
++.*: Error: unrecognized opcode `vluxseg2ei8.v v4,\(a0\),v12'
|
|
|
++.*: Error: unrecognized opcode `vluxseg2ei8.v v4,0\(a0\),v12'
|
|
|
++.*: Error: unrecognized opcode `vluxseg2ei8.v v4,\(a0\),v12,v0.t'
|
|
|
++.*: Error: unrecognized opcode `vsuxseg2ei8.v v4,\(a0\),v12'
|
|
|
++.*: Error: unrecognized opcode `vsuxseg2ei8.v v4,0\(a0\),v12'
|
|
|
++.*: Error: unrecognized opcode `vsuxseg2ei8.v v4,\(a0\),v12,v0.t'
|
|
|
++.*: Error: unrecognized opcode `vluxseg3ei8.v v4,\(a0\),v12'
|
|
|
++.*: Error: unrecognized opcode `vluxseg3ei8.v v4,0\(a0\),v12'
|
|
|
++.*: Error: unrecognized opcode `vluxseg3ei8.v v4,\(a0\),v12,v0.t'
|
|
|
++.*: Error: unrecognized opcode `vsuxseg3ei8.v v4,\(a0\),v12'
|
|
|
++.*: Error: unrecognized opcode `vsuxseg3ei8.v v4,0\(a0\),v12'
|
|
|
++.*: Error: unrecognized opcode `vsuxseg3ei8.v v4,\(a0\),v12,v0.t'
|
|
|
++.*: Error: unrecognized opcode `vluxseg4ei8.v v4,\(a0\),v12'
|
|
|
++.*: Error: unrecognized opcode `vluxseg4ei8.v v4,0\(a0\),v12'
|
|
|
++.*: Error: unrecognized opcode `vluxseg4ei8.v v4,\(a0\),v12,v0.t'
|
|
|
++.*: Error: unrecognized opcode `vsuxseg4ei8.v v4,\(a0\),v12'
|
|
|
++.*: Error: unrecognized opcode `vsuxseg4ei8.v v4,0\(a0\),v12'
|
|
|
++.*: Error: unrecognized opcode `vsuxseg4ei8.v v4,\(a0\),v12,v0.t'
|
|
|
++.*: Error: unrecognized opcode `vluxseg5ei8.v v4,\(a0\),v12'
|
|
|
++.*: Error: unrecognized opcode `vluxseg5ei8.v v4,0\(a0\),v12'
|
|
|
++.*: Error: unrecognized opcode `vluxseg5ei8.v v4,\(a0\),v12,v0.t'
|
|
|
++.*: Error: unrecognized opcode `vsuxseg5ei8.v v4,\(a0\),v12'
|
|
|
++.*: Error: unrecognized opcode `vsuxseg5ei8.v v4,0\(a0\),v12'
|
|
|
++.*: Error: unrecognized opcode `vsuxseg5ei8.v v4,\(a0\),v12,v0.t'
|
|
|
++.*: Error: unrecognized opcode `vluxseg6ei8.v v4,\(a0\),v12'
|
|
|
++.*: Error: unrecognized opcode `vluxseg6ei8.v v4,0\(a0\),v12'
|
|
|
++.*: Error: unrecognized opcode `vluxseg6ei8.v v4,\(a0\),v12,v0.t'
|
|
|
++.*: Error: unrecognized opcode `vsuxseg6ei8.v v4,\(a0\),v12'
|
|
|
++.*: Error: unrecognized opcode `vsuxseg6ei8.v v4,0\(a0\),v12'
|
|
|
++.*: Error: unrecognized opcode `vsuxseg6ei8.v v4,\(a0\),v12,v0.t'
|
|
|
++.*: Error: unrecognized opcode `vluxseg7ei8.v v4,\(a0\),v12'
|
|
|
++.*: Error: unrecognized opcode `vluxseg7ei8.v v4,0\(a0\),v12'
|
|
|
++.*: Error: unrecognized opcode `vluxseg7ei8.v v4,\(a0\),v12,v0.t'
|
|
|
++.*: Error: unrecognized opcode `vsuxseg7ei8.v v4,\(a0\),v12'
|
|
|
++.*: Error: unrecognized opcode `vsuxseg7ei8.v v4,0\(a0\),v12'
|
|
|
++.*: Error: unrecognized opcode `vsuxseg7ei8.v v4,\(a0\),v12,v0.t'
|
|
|
++.*: Error: unrecognized opcode `vluxseg8ei8.v v4,\(a0\),v12'
|
|
|
++.*: Error: unrecognized opcode `vluxseg8ei8.v v4,0\(a0\),v12'
|
|
|
++.*: Error: unrecognized opcode `vluxseg8ei8.v v4,\(a0\),v12,v0.t'
|
|
|
++.*: Error: unrecognized opcode `vsuxseg8ei8.v v4,\(a0\),v12'
|
|
|
++.*: Error: unrecognized opcode `vsuxseg8ei8.v v4,0\(a0\),v12'
|
|
|
++.*: Error: unrecognized opcode `vsuxseg8ei8.v v4,\(a0\),v12,v0.t'
|
|
|
++.*: Error: unrecognized opcode `vluxseg2ei16.v v4,\(a0\),v12'
|
|
|
++.*: Error: unrecognized opcode `vluxseg2ei16.v v4,0\(a0\),v12'
|
|
|
++.*: Error: unrecognized opcode `vluxseg2ei16.v v4,\(a0\),v12,v0.t'
|
|
|
++.*: Error: unrecognized opcode `vsuxseg2ei16.v v4,\(a0\),v12'
|
|
|
++.*: Error: unrecognized opcode `vsuxseg2ei16.v v4,0\(a0\),v12'
|
|
|
++.*: Error: unrecognized opcode `vsuxseg2ei16.v v4,\(a0\),v12,v0.t'
|
|
|
++.*: Error: unrecognized opcode `vluxseg3ei16.v v4,\(a0\),v12'
|
|
|
++.*: Error: unrecognized opcode `vluxseg3ei16.v v4,0\(a0\),v12'
|
|
|
++.*: Error: unrecognized opcode `vluxseg3ei16.v v4,\(a0\),v12,v0.t'
|
|
|
++.*: Error: unrecognized opcode `vsuxseg3ei16.v v4,\(a0\),v12'
|
|
|
++.*: Error: unrecognized opcode `vsuxseg3ei16.v v4,0\(a0\),v12'
|
|
|
++.*: Error: unrecognized opcode `vsuxseg3ei16.v v4,\(a0\),v12,v0.t'
|
|
|
++.*: Error: unrecognized opcode `vluxseg4ei16.v v4,\(a0\),v12'
|
|
|
++.*: Error: unrecognized opcode `vluxseg4ei16.v v4,0\(a0\),v12'
|
|
|
++.*: Error: unrecognized opcode `vluxseg4ei16.v v4,\(a0\),v12,v0.t'
|
|
|
++.*: Error: unrecognized opcode `vsuxseg4ei16.v v4,\(a0\),v12'
|
|
|
++.*: Error: unrecognized opcode `vsuxseg4ei16.v v4,0\(a0\),v12'
|
|
|
++.*: Error: unrecognized opcode `vsuxseg4ei16.v v4,\(a0\),v12,v0.t'
|
|
|
++.*: Error: unrecognized opcode `vluxseg5ei16.v v4,\(a0\),v12'
|
|
|
++.*: Error: unrecognized opcode `vluxseg5ei16.v v4,0\(a0\),v12'
|
|
|
++.*: Error: unrecognized opcode `vluxseg5ei16.v v4,\(a0\),v12,v0.t'
|
|
|
++.*: Error: unrecognized opcode `vsuxseg5ei16.v v4,\(a0\),v12'
|
|
|
++.*: Error: unrecognized opcode `vsuxseg5ei16.v v4,0\(a0\),v12'
|
|
|
++.*: Error: unrecognized opcode `vsuxseg5ei16.v v4,\(a0\),v12,v0.t'
|
|
|
++.*: Error: unrecognized opcode `vluxseg6ei16.v v4,\(a0\),v12'
|
|
|
++.*: Error: unrecognized opcode `vluxseg6ei16.v v4,0\(a0\),v12'
|
|
|
++.*: Error: unrecognized opcode `vluxseg6ei16.v v4,\(a0\),v12,v0.t'
|
|
|
++.*: Error: unrecognized opcode `vsuxseg6ei16.v v4,\(a0\),v12'
|
|
|
++.*: Error: unrecognized opcode `vsuxseg6ei16.v v4,0\(a0\),v12'
|
|
|
++.*: Error: unrecognized opcode `vsuxseg6ei16.v v4,\(a0\),v12,v0.t'
|
|
|
++.*: Error: unrecognized opcode `vluxseg7ei16.v v4,\(a0\),v12'
|
|
|
++.*: Error: unrecognized opcode `vluxseg7ei16.v v4,0\(a0\),v12'
|
|
|
++.*: Error: unrecognized opcode `vluxseg7ei16.v v4,\(a0\),v12,v0.t'
|
|
|
++.*: Error: unrecognized opcode `vsuxseg7ei16.v v4,\(a0\),v12'
|
|
|
++.*: Error: unrecognized opcode `vsuxseg7ei16.v v4,0\(a0\),v12'
|
|
|
++.*: Error: unrecognized opcode `vsuxseg7ei16.v v4,\(a0\),v12,v0.t'
|
|
|
++.*: Error: unrecognized opcode `vluxseg8ei16.v v4,\(a0\),v12'
|
|
|
++.*: Error: unrecognized opcode `vluxseg8ei16.v v4,0\(a0\),v12'
|
|
|
++.*: Error: unrecognized opcode `vluxseg8ei16.v v4,\(a0\),v12,v0.t'
|
|
|
++.*: Error: unrecognized opcode `vsuxseg8ei16.v v4,\(a0\),v12'
|
|
|
++.*: Error: unrecognized opcode `vsuxseg8ei16.v v4,0\(a0\),v12'
|
|
|
++.*: Error: unrecognized opcode `vsuxseg8ei16.v v4,\(a0\),v12,v0.t'
|
|
|
++.*: Error: unrecognized opcode `vluxseg2ei32.v v4,\(a0\),v12'
|
|
|
++.*: Error: unrecognized opcode `vluxseg2ei32.v v4,0\(a0\),v12'
|
|
|
++.*: Error: unrecognized opcode `vluxseg2ei32.v v4,\(a0\),v12,v0.t'
|
|
|
++.*: Error: unrecognized opcode `vsuxseg2ei32.v v4,\(a0\),v12'
|
|
|
++.*: Error: unrecognized opcode `vsuxseg2ei32.v v4,0\(a0\),v12'
|
|
|
++.*: Error: unrecognized opcode `vsuxseg2ei32.v v4,\(a0\),v12,v0.t'
|
|
|
++.*: Error: unrecognized opcode `vluxseg3ei32.v v4,\(a0\),v12'
|
|
|
++.*: Error: unrecognized opcode `vluxseg3ei32.v v4,0\(a0\),v12'
|
|
|
++.*: Error: unrecognized opcode `vluxseg3ei32.v v4,\(a0\),v12,v0.t'
|
|
|
++.*: Error: unrecognized opcode `vsuxseg3ei32.v v4,\(a0\),v12'
|
|
|
++.*: Error: unrecognized opcode `vsuxseg3ei32.v v4,0\(a0\),v12'
|
|
|
++.*: Error: unrecognized opcode `vsuxseg3ei32.v v4,\(a0\),v12,v0.t'
|
|
|
++.*: Error: unrecognized opcode `vluxseg4ei32.v v4,\(a0\),v12'
|
|
|
++.*: Error: unrecognized opcode `vluxseg4ei32.v v4,0\(a0\),v12'
|
|
|
++.*: Error: unrecognized opcode `vluxseg4ei32.v v4,\(a0\),v12,v0.t'
|
|
|
++.*: Error: unrecognized opcode `vsuxseg4ei32.v v4,\(a0\),v12'
|
|
|
++.*: Error: unrecognized opcode `vsuxseg4ei32.v v4,0\(a0\),v12'
|
|
|
++.*: Error: unrecognized opcode `vsuxseg4ei32.v v4,\(a0\),v12,v0.t'
|
|
|
++.*: Error: unrecognized opcode `vluxseg5ei32.v v4,\(a0\),v12'
|
|
|
++.*: Error: unrecognized opcode `vluxseg5ei32.v v4,0\(a0\),v12'
|
|
|
++.*: Error: unrecognized opcode `vluxseg5ei32.v v4,\(a0\),v12,v0.t'
|
|
|
++.*: Error: unrecognized opcode `vsuxseg5ei32.v v4,\(a0\),v12'
|
|
|
++.*: Error: unrecognized opcode `vsuxseg5ei32.v v4,0\(a0\),v12'
|
|
|
++.*: Error: unrecognized opcode `vsuxseg5ei32.v v4,\(a0\),v12,v0.t'
|
|
|
++.*: Error: unrecognized opcode `vluxseg6ei32.v v4,\(a0\),v12'
|
|
|
++.*: Error: unrecognized opcode `vluxseg6ei32.v v4,0\(a0\),v12'
|
|
|
++.*: Error: unrecognized opcode `vluxseg6ei32.v v4,\(a0\),v12,v0.t'
|
|
|
++.*: Error: unrecognized opcode `vsuxseg6ei32.v v4,\(a0\),v12'
|
|
|
++.*: Error: unrecognized opcode `vsuxseg6ei32.v v4,0\(a0\),v12'
|
|
|
++.*: Error: unrecognized opcode `vsuxseg6ei32.v v4,\(a0\),v12,v0.t'
|
|
|
++.*: Error: unrecognized opcode `vluxseg7ei32.v v4,\(a0\),v12'
|
|
|
++.*: Error: unrecognized opcode `vluxseg7ei32.v v4,0\(a0\),v12'
|
|
|
++.*: Error: unrecognized opcode `vluxseg7ei32.v v4,\(a0\),v12,v0.t'
|
|
|
++.*: Error: unrecognized opcode `vsuxseg7ei32.v v4,\(a0\),v12'
|
|
|
++.*: Error: unrecognized opcode `vsuxseg7ei32.v v4,0\(a0\),v12'
|
|
|
++.*: Error: unrecognized opcode `vsuxseg7ei32.v v4,\(a0\),v12,v0.t'
|
|
|
++.*: Error: unrecognized opcode `vluxseg8ei32.v v4,\(a0\),v12'
|
|
|
++.*: Error: unrecognized opcode `vluxseg8ei32.v v4,0\(a0\),v12'
|
|
|
++.*: Error: unrecognized opcode `vluxseg8ei32.v v4,\(a0\),v12,v0.t'
|
|
|
++.*: Error: unrecognized opcode `vsuxseg8ei32.v v4,\(a0\),v12'
|
|
|
++.*: Error: unrecognized opcode `vsuxseg8ei32.v v4,0\(a0\),v12'
|
|
|
++.*: Error: unrecognized opcode `vsuxseg8ei32.v v4,\(a0\),v12,v0.t'
|
|
|
++.*: Error: unrecognized opcode `vluxseg2ei64.v v4,\(a0\),v12'
|
|
|
++.*: Error: unrecognized opcode `vluxseg2ei64.v v4,0\(a0\),v12'
|
|
|
++.*: Error: unrecognized opcode `vluxseg2ei64.v v4,\(a0\),v12,v0.t'
|
|
|
++.*: Error: unrecognized opcode `vsuxseg2ei64.v v4,\(a0\),v12'
|
|
|
++.*: Error: unrecognized opcode `vsuxseg2ei64.v v4,0\(a0\),v12'
|
|
|
++.*: Error: unrecognized opcode `vsuxseg2ei64.v v4,\(a0\),v12,v0.t'
|
|
|
++.*: Error: unrecognized opcode `vluxseg3ei64.v v4,\(a0\),v12'
|
|
|
++.*: Error: unrecognized opcode `vluxseg3ei64.v v4,0\(a0\),v12'
|
|
|
++.*: Error: unrecognized opcode `vluxseg3ei64.v v4,\(a0\),v12,v0.t'
|
|
|
++.*: Error: unrecognized opcode `vsuxseg3ei64.v v4,\(a0\),v12'
|
|
|
++.*: Error: unrecognized opcode `vsuxseg3ei64.v v4,0\(a0\),v12'
|
|
|
++.*: Error: unrecognized opcode `vsuxseg3ei64.v v4,\(a0\),v12,v0.t'
|
|
|
++.*: Error: unrecognized opcode `vluxseg4ei64.v v4,\(a0\),v12'
|
|
|
++.*: Error: unrecognized opcode `vluxseg4ei64.v v4,0\(a0\),v12'
|
|
|
++.*: Error: unrecognized opcode `vluxseg4ei64.v v4,\(a0\),v12,v0.t'
|
|
|
++.*: Error: unrecognized opcode `vsuxseg4ei64.v v4,\(a0\),v12'
|
|
|
++.*: Error: unrecognized opcode `vsuxseg4ei64.v v4,0\(a0\),v12'
|
|
|
++.*: Error: unrecognized opcode `vsuxseg4ei64.v v4,\(a0\),v12,v0.t'
|
|
|
++.*: Error: unrecognized opcode `vluxseg5ei64.v v4,\(a0\),v12'
|
|
|
++.*: Error: unrecognized opcode `vluxseg5ei64.v v4,0\(a0\),v12'
|
|
|
++.*: Error: unrecognized opcode `vluxseg5ei64.v v4,\(a0\),v12,v0.t'
|
|
|
++.*: Error: unrecognized opcode `vsuxseg5ei64.v v4,\(a0\),v12'
|
|
|
++.*: Error: unrecognized opcode `vsuxseg5ei64.v v4,0\(a0\),v12'
|
|
|
++.*: Error: unrecognized opcode `vsuxseg5ei64.v v4,\(a0\),v12,v0.t'
|
|
|
++.*: Error: unrecognized opcode `vluxseg6ei64.v v4,\(a0\),v12'
|
|
|
++.*: Error: unrecognized opcode `vluxseg6ei64.v v4,0\(a0\),v12'
|
|
|
++.*: Error: unrecognized opcode `vluxseg6ei64.v v4,\(a0\),v12,v0.t'
|
|
|
++.*: Error: unrecognized opcode `vsuxseg6ei64.v v4,\(a0\),v12'
|
|
|
++.*: Error: unrecognized opcode `vsuxseg6ei64.v v4,0\(a0\),v12'
|
|
|
++.*: Error: unrecognized opcode `vsuxseg6ei64.v v4,\(a0\),v12,v0.t'
|
|
|
++.*: Error: unrecognized opcode `vluxseg7ei64.v v4,\(a0\),v12'
|
|
|
++.*: Error: unrecognized opcode `vluxseg7ei64.v v4,0\(a0\),v12'
|
|
|
++.*: Error: unrecognized opcode `vluxseg7ei64.v v4,\(a0\),v12,v0.t'
|
|
|
++.*: Error: unrecognized opcode `vsuxseg7ei64.v v4,\(a0\),v12'
|
|
|
++.*: Error: unrecognized opcode `vsuxseg7ei64.v v4,0\(a0\),v12'
|
|
|
++.*: Error: unrecognized opcode `vsuxseg7ei64.v v4,\(a0\),v12,v0.t'
|
|
|
++.*: Error: unrecognized opcode `vluxseg8ei64.v v4,\(a0\),v12'
|
|
|
++.*: Error: unrecognized opcode `vluxseg8ei64.v v4,0\(a0\),v12'
|
|
|
++.*: Error: unrecognized opcode `vluxseg8ei64.v v4,\(a0\),v12,v0.t'
|
|
|
++.*: Error: unrecognized opcode `vsuxseg8ei64.v v4,\(a0\),v12'
|
|
|
++.*: Error: unrecognized opcode `vsuxseg8ei64.v v4,0\(a0\),v12'
|
|
|
++.*: Error: unrecognized opcode `vsuxseg8ei64.v v4,\(a0\),v12,v0.t'
|
|
|
++.*: Error: unrecognized opcode `vlseg2e8ff.v v4,\(a0\)'
|
|
|
++.*: Error: unrecognized opcode `vlseg2e8ff.v v4,0\(a0\)'
|
|
|
++.*: Error: unrecognized opcode `vlseg2e8ff.v v4,\(a0\),v0.t'
|
|
|
++.*: Error: unrecognized opcode `vlseg3e8ff.v v4,\(a0\)'
|
|
|
++.*: Error: unrecognized opcode `vlseg3e8ff.v v4,0\(a0\)'
|
|
|
++.*: Error: unrecognized opcode `vlseg3e8ff.v v4,\(a0\),v0.t'
|
|
|
++.*: Error: unrecognized opcode `vlseg4e8ff.v v4,\(a0\)'
|
|
|
++.*: Error: unrecognized opcode `vlseg4e8ff.v v4,0\(a0\)'
|
|
|
++.*: Error: unrecognized opcode `vlseg4e8ff.v v4,\(a0\),v0.t'
|
|
|
++.*: Error: unrecognized opcode `vlseg5e8ff.v v4,\(a0\)'
|
|
|
++.*: Error: unrecognized opcode `vlseg5e8ff.v v4,0\(a0\)'
|
|
|
++.*: Error: unrecognized opcode `vlseg5e8ff.v v4,\(a0\),v0.t'
|
|
|
++.*: Error: unrecognized opcode `vlseg6e8ff.v v4,\(a0\)'
|
|
|
++.*: Error: unrecognized opcode `vlseg6e8ff.v v4,0\(a0\)'
|
|
|
++.*: Error: unrecognized opcode `vlseg6e8ff.v v4,\(a0\),v0.t'
|
|
|
++.*: Error: unrecognized opcode `vlseg7e8ff.v v4,\(a0\)'
|
|
|
++.*: Error: unrecognized opcode `vlseg7e8ff.v v4,0\(a0\)'
|
|
|
++.*: Error: unrecognized opcode `vlseg7e8ff.v v4,\(a0\),v0.t'
|
|
|
++.*: Error: unrecognized opcode `vlseg8e8ff.v v4,\(a0\)'
|
|
|
++.*: Error: unrecognized opcode `vlseg8e8ff.v v4,0\(a0\)'
|
|
|
++.*: Error: unrecognized opcode `vlseg8e8ff.v v4,\(a0\),v0.t'
|
|
|
++.*: Error: unrecognized opcode `vlseg2e16ff.v v4,\(a0\)'
|
|
|
++.*: Error: unrecognized opcode `vlseg2e16ff.v v4,0\(a0\)'
|
|
|
++.*: Error: unrecognized opcode `vlseg2e16ff.v v4,\(a0\),v0.t'
|
|
|
++.*: Error: unrecognized opcode `vlseg3e16ff.v v4,\(a0\)'
|
|
|
++.*: Error: unrecognized opcode `vlseg3e16ff.v v4,0\(a0\)'
|
|
|
++.*: Error: unrecognized opcode `vlseg3e16ff.v v4,\(a0\),v0.t'
|
|
|
++.*: Error: unrecognized opcode `vlseg4e16ff.v v4,\(a0\)'
|
|
|
++.*: Error: unrecognized opcode `vlseg4e16ff.v v4,0\(a0\)'
|
|
|
++.*: Error: unrecognized opcode `vlseg4e16ff.v v4,\(a0\),v0.t'
|
|
|
++.*: Error: unrecognized opcode `vlseg5e16ff.v v4,\(a0\)'
|
|
|
++.*: Error: unrecognized opcode `vlseg5e16ff.v v4,0\(a0\)'
|
|
|
++.*: Error: unrecognized opcode `vlseg5e16ff.v v4,\(a0\),v0.t'
|
|
|
++.*: Error: unrecognized opcode `vlseg6e16ff.v v4,\(a0\)'
|
|
|
++.*: Error: unrecognized opcode `vlseg6e16ff.v v4,0\(a0\)'
|
|
|
++.*: Error: unrecognized opcode `vlseg6e16ff.v v4,\(a0\),v0.t'
|
|
|
++.*: Error: unrecognized opcode `vlseg7e16ff.v v4,\(a0\)'
|
|
|
++.*: Error: unrecognized opcode `vlseg7e16ff.v v4,0\(a0\)'
|
|
|
++.*: Error: unrecognized opcode `vlseg7e16ff.v v4,\(a0\),v0.t'
|
|
|
++.*: Error: unrecognized opcode `vlseg8e16ff.v v4,\(a0\)'
|
|
|
++.*: Error: unrecognized opcode `vlseg8e16ff.v v4,0\(a0\)'
|
|
|
++.*: Error: unrecognized opcode `vlseg8e16ff.v v4,\(a0\),v0.t'
|
|
|
++.*: Error: unrecognized opcode `vlseg2e32ff.v v4,\(a0\)'
|
|
|
++.*: Error: unrecognized opcode `vlseg2e32ff.v v4,0\(a0\)'
|
|
|
++.*: Error: unrecognized opcode `vlseg2e32ff.v v4,\(a0\),v0.t'
|
|
|
++.*: Error: unrecognized opcode `vlseg3e32ff.v v4,\(a0\)'
|
|
|
++.*: Error: unrecognized opcode `vlseg3e32ff.v v4,0\(a0\)'
|
|
|
++.*: Error: unrecognized opcode `vlseg3e32ff.v v4,\(a0\),v0.t'
|
|
|
++.*: Error: unrecognized opcode `vlseg4e32ff.v v4,\(a0\)'
|
|
|
++.*: Error: unrecognized opcode `vlseg4e32ff.v v4,0\(a0\)'
|
|
|
++.*: Error: unrecognized opcode `vlseg4e32ff.v v4,\(a0\),v0.t'
|
|
|
++.*: Error: unrecognized opcode `vlseg5e32ff.v v4,\(a0\)'
|
|
|
++.*: Error: unrecognized opcode `vlseg5e32ff.v v4,0\(a0\)'
|
|
|
++.*: Error: unrecognized opcode `vlseg5e32ff.v v4,\(a0\),v0.t'
|
|
|
++.*: Error: unrecognized opcode `vlseg6e32ff.v v4,\(a0\)'
|
|
|
++.*: Error: unrecognized opcode `vlseg6e32ff.v v4,0\(a0\)'
|
|
|
++.*: Error: unrecognized opcode `vlseg6e32ff.v v4,\(a0\),v0.t'
|
|
|
++.*: Error: unrecognized opcode `vlseg7e32ff.v v4,\(a0\)'
|
|
|
++.*: Error: unrecognized opcode `vlseg7e32ff.v v4,0\(a0\)'
|
|
|
++.*: Error: unrecognized opcode `vlseg7e32ff.v v4,\(a0\),v0.t'
|
|
|
++.*: Error: unrecognized opcode `vlseg8e32ff.v v4,\(a0\)'
|
|
|
++.*: Error: unrecognized opcode `vlseg8e32ff.v v4,0\(a0\)'
|
|
|
++.*: Error: unrecognized opcode `vlseg8e32ff.v v4,\(a0\),v0.t'
|
|
|
++.*: Error: unrecognized opcode `vlseg2e64ff.v v4,\(a0\)'
|
|
|
++.*: Error: unrecognized opcode `vlseg2e64ff.v v4,0\(a0\)'
|
|
|
++.*: Error: unrecognized opcode `vlseg2e64ff.v v4,\(a0\),v0.t'
|
|
|
++.*: Error: unrecognized opcode `vlseg3e64ff.v v4,\(a0\)'
|
|
|
++.*: Error: unrecognized opcode `vlseg3e64ff.v v4,0\(a0\)'
|
|
|
++.*: Error: unrecognized opcode `vlseg3e64ff.v v4,\(a0\),v0.t'
|
|
|
++.*: Error: unrecognized opcode `vlseg4e64ff.v v4,\(a0\)'
|
|
|
++.*: Error: unrecognized opcode `vlseg4e64ff.v v4,0\(a0\)'
|
|
|
++.*: Error: unrecognized opcode `vlseg4e64ff.v v4,\(a0\),v0.t'
|
|
|
++.*: Error: unrecognized opcode `vlseg5e64ff.v v4,\(a0\)'
|
|
|
++.*: Error: unrecognized opcode `vlseg5e64ff.v v4,0\(a0\)'
|
|
|
++.*: Error: unrecognized opcode `vlseg5e64ff.v v4,\(a0\),v0.t'
|
|
|
++.*: Error: unrecognized opcode `vlseg6e64ff.v v4,\(a0\)'
|
|
|
++.*: Error: unrecognized opcode `vlseg6e64ff.v v4,0\(a0\)'
|
|
|
++.*: Error: unrecognized opcode `vlseg6e64ff.v v4,\(a0\),v0.t'
|
|
|
++.*: Error: unrecognized opcode `vlseg7e64ff.v v4,\(a0\)'
|
|
|
++.*: Error: unrecognized opcode `vlseg7e64ff.v v4,0\(a0\)'
|
|
|
++.*: Error: unrecognized opcode `vlseg7e64ff.v v4,\(a0\),v0.t'
|
|
|
++.*: Error: unrecognized opcode `vlseg8e64ff.v v4,\(a0\)'
|
|
|
++.*: Error: unrecognized opcode `vlseg8e64ff.v v4,0\(a0\)'
|
|
|
++.*: Error: unrecognized opcode `vlseg8e64ff.v v4,\(a0\),v0.t'
|
|
|
++.*: Error: unrecognized opcode `vl1r.v v3,\(a0\)'
|
|
|
++.*: Error: unrecognized opcode `vl1r.v v3,0\(a0\)'
|
|
|
++.*: Error: unrecognized opcode `vl1re8.v v3,\(a0\)'
|
|
|
++.*: Error: unrecognized opcode `vl1re8.v v3,0\(a0\)'
|
|
|
++.*: Error: unrecognized opcode `vl1re16.v v3,\(a0\)'
|
|
|
++.*: Error: unrecognized opcode `vl1re16.v v3,0\(a0\)'
|
|
|
++.*: Error: unrecognized opcode `vl1re32.v v3,\(a0\)'
|
|
|
++.*: Error: unrecognized opcode `vl1re32.v v3,0\(a0\)'
|
|
|
++.*: Error: unrecognized opcode `vl1re64.v v3,\(a0\)'
|
|
|
++.*: Error: unrecognized opcode `vl1re64.v v3,0\(a0\)'
|
|
|
++.*: Error: unrecognized opcode `vl2r.v v2,\(a0\)'
|
|
|
++.*: Error: unrecognized opcode `vl2r.v v2,0\(a0\)'
|
|
|
++.*: Error: unrecognized opcode `vl2re8.v v2,\(a0\)'
|
|
|
++.*: Error: unrecognized opcode `vl2re8.v v2,0\(a0\)'
|
|
|
++.*: Error: unrecognized opcode `vl2re16.v v2,\(a0\)'
|
|
|
++.*: Error: unrecognized opcode `vl2re16.v v2,0\(a0\)'
|
|
|
++.*: Error: unrecognized opcode `vl2re32.v v2,\(a0\)'
|
|
|
++.*: Error: unrecognized opcode `vl2re32.v v2,0\(a0\)'
|
|
|
++.*: Error: unrecognized opcode `vl2re64.v v2,\(a0\)'
|
|
|
++.*: Error: unrecognized opcode `vl2re64.v v2,0\(a0\)'
|
|
|
++.*: Error: unrecognized opcode `vl4r.v v4,\(a0\)'
|
|
|
++.*: Error: unrecognized opcode `vl4r.v v4,0\(a0\)'
|
|
|
++.*: Error: unrecognized opcode `vl4re8.v v4,\(a0\)'
|
|
|
++.*: Error: unrecognized opcode `vl4re8.v v4,0\(a0\)'
|
|
|
++.*: Error: unrecognized opcode `vl4re16.v v4,\(a0\)'
|
|
|
++.*: Error: unrecognized opcode `vl4re16.v v4,0\(a0\)'
|
|
|
++.*: Error: unrecognized opcode `vl4re32.v v4,\(a0\)'
|
|
|
++.*: Error: unrecognized opcode `vl4re32.v v4,0\(a0\)'
|
|
|
++.*: Error: unrecognized opcode `vl4re64.v v4,\(a0\)'
|
|
|
++.*: Error: unrecognized opcode `vl4re64.v v4,0\(a0\)'
|
|
|
++.*: Error: unrecognized opcode `vl8r.v v8,\(a0\)'
|
|
|
++.*: Error: unrecognized opcode `vl8r.v v8,0\(a0\)'
|
|
|
++.*: Error: unrecognized opcode `vl8re8.v v8,\(a0\)'
|
|
|
++.*: Error: unrecognized opcode `vl8re8.v v8,0\(a0\)'
|
|
|
++.*: Error: unrecognized opcode `vl8re16.v v8,\(a0\)'
|
|
|
++.*: Error: unrecognized opcode `vl8re16.v v8,0\(a0\)'
|
|
|
++.*: Error: unrecognized opcode `vl8re32.v v8,\(a0\)'
|
|
|
++.*: Error: unrecognized opcode `vl8re32.v v8,0\(a0\)'
|
|
|
++.*: Error: unrecognized opcode `vl8re64.v v8,\(a0\)'
|
|
|
++.*: Error: unrecognized opcode `vl8re64.v v8,0\(a0\)'
|
|
|
++.*: Error: unrecognized opcode `vs1r.v v3,\(a1\)'
|
|
|
++.*: Error: unrecognized opcode `vs1r.v v3,0\(a1\)'
|
|
|
++.*: Error: unrecognized opcode `vs2r.v v2,\(a1\)'
|
|
|
++.*: Error: unrecognized opcode `vs2r.v v2,0\(a1\)'
|
|
|
++.*: Error: unrecognized opcode `vs4r.v v4,\(a1\)'
|
|
|
++.*: Error: unrecognized opcode `vs4r.v v4,0\(a1\)'
|
|
|
++.*: Error: unrecognized opcode `vs8r.v v8,\(a1\)'
|
|
|
++.*: Error: unrecognized opcode `vs8r.v v8,0\(a1\)'
|
|
|
++.*: Error: unrecognized opcode `vamoaddei8.v v4,\(a1\),v8,v4'
|
|
|
++.*: Error: unrecognized opcode `vamoaddei8.v x0,\(a1\),v8,v4'
|
|
|
++.*: Error: unrecognized opcode `vamoaddei8.v v4,\(a1\),v8,v4,v0.t'
|
|
|
++.*: Error: unrecognized opcode `vamoaddei8.v x0,\(a1\),v8,v4,v0.t'
|
|
|
++.*: Error: unrecognized opcode `vamoswapei8.v v4,\(a1\),v8,v4'
|
|
|
++.*: Error: unrecognized opcode `vamoswapei8.v x0,\(a1\),v8,v4'
|
|
|
++.*: Error: unrecognized opcode `vamoswapei8.v v4,\(a1\),v8,v4,v0.t'
|
|
|
++.*: Error: unrecognized opcode `vamoswapei8.v x0,\(a1\),v8,v4,v0.t'
|
|
|
++.*: Error: unrecognized opcode `vamoxorei8.v v4,\(a1\),v8,v4'
|
|
|
++.*: Error: unrecognized opcode `vamoxorei8.v x0,\(a1\),v8,v4'
|
|
|
++.*: Error: unrecognized opcode `vamoxorei8.v v4,\(a1\),v8,v4,v0.t'
|
|
|
++.*: Error: unrecognized opcode `vamoxorei8.v x0,\(a1\),v8,v4,v0.t'
|
|
|
++.*: Error: unrecognized opcode `vamoandei8.v v4,\(a1\),v8,v4'
|
|
|
++.*: Error: unrecognized opcode `vamoandei8.v x0,\(a1\),v8,v4'
|
|
|
++.*: Error: unrecognized opcode `vamoandei8.v v4,\(a1\),v8,v4,v0.t'
|
|
|
++.*: Error: unrecognized opcode `vamoandei8.v x0,\(a1\),v8,v4,v0.t'
|
|
|
++.*: Error: unrecognized opcode `vamoorei8.v v4,\(a1\),v8,v4'
|
|
|
++.*: Error: unrecognized opcode `vamoorei8.v x0,\(a1\),v8,v4'
|
|
|
++.*: Error: unrecognized opcode `vamoorei8.v v4,\(a1\),v8,v4,v0.t'
|
|
|
++.*: Error: unrecognized opcode `vamoorei8.v x0,\(a1\),v8,v4,v0.t'
|
|
|
++.*: Error: unrecognized opcode `vamominei8.v v4,\(a1\),v8,v4'
|
|
|
++.*: Error: unrecognized opcode `vamominei8.v x0,\(a1\),v8,v4'
|
|
|
++.*: Error: unrecognized opcode `vamominei8.v v4,\(a1\),v8,v4,v0.t'
|
|
|
++.*: Error: unrecognized opcode `vamominei8.v x0,\(a1\),v8,v4,v0.t'
|
|
|
++.*: Error: unrecognized opcode `vamomaxei8.v v4,\(a1\),v8,v4'
|
|
|
++.*: Error: unrecognized opcode `vamomaxei8.v x0,\(a1\),v8,v4'
|
|
|
++.*: Error: unrecognized opcode `vamomaxei8.v v4,\(a1\),v8,v4,v0.t'
|
|
|
++.*: Error: unrecognized opcode `vamomaxei8.v x0,\(a1\),v8,v4,v0.t'
|
|
|
++.*: Error: unrecognized opcode `vamominuei8.v v4,\(a1\),v8,v4'
|
|
|
++.*: Error: unrecognized opcode `vamominuei8.v x0,\(a1\),v8,v4'
|
|
|
++.*: Error: unrecognized opcode `vamominuei8.v v4,\(a1\),v8,v4,v0.t'
|
|
|
++.*: Error: unrecognized opcode `vamominuei8.v x0,\(a1\),v8,v4,v0.t'
|
|
|
++.*: Error: unrecognized opcode `vamomaxuei8.v v4,\(a1\),v8,v4'
|
|
|
++.*: Error: unrecognized opcode `vamomaxuei8.v x0,\(a1\),v8,v4'
|
|
|
++.*: Error: unrecognized opcode `vamomaxuei8.v v4,\(a1\),v8,v4,v0.t'
|
|
|
++.*: Error: unrecognized opcode `vamomaxuei8.v x0,\(a1\),v8,v4,v0.t'
|
|
|
++.*: Error: unrecognized opcode `vamoaddei8.v v4,0\(a1\),v8,v4'
|
|
|
++.*: Error: unrecognized opcode `vamoaddei8.v x0,0\(a1\),v8,v4'
|
|
|
++.*: Error: unrecognized opcode `vamoaddei8.v v4,0\(a1\),v8,v4,v0.t'
|
|
|
++.*: Error: unrecognized opcode `vamoaddei8.v x0,0\(a1\),v8,v4,v0.t'
|
|
|
++.*: Error: unrecognized opcode `vamoswapei8.v v4,0\(a1\),v8,v4'
|
|
|
++.*: Error: unrecognized opcode `vamoswapei8.v x0,0\(a1\),v8,v4'
|
|
|
++.*: Error: unrecognized opcode `vamoswapei8.v v4,0\(a1\),v8,v4,v0.t'
|
|
|
++.*: Error: unrecognized opcode `vamoswapei8.v x0,0\(a1\),v8,v4,v0.t'
|
|
|
++.*: Error: unrecognized opcode `vamoxorei8.v v4,0\(a1\),v8,v4'
|
|
|
++.*: Error: unrecognized opcode `vamoxorei8.v x0,0\(a1\),v8,v4'
|
|
|
++.*: Error: unrecognized opcode `vamoxorei8.v v4,0\(a1\),v8,v4,v0.t'
|
|
|
++.*: Error: unrecognized opcode `vamoxorei8.v x0,0\(a1\),v8,v4,v0.t'
|
|
|
++.*: Error: unrecognized opcode `vamoandei8.v v4,0\(a1\),v8,v4'
|
|
|
++.*: Error: unrecognized opcode `vamoandei8.v x0,0\(a1\),v8,v4'
|
|
|
++.*: Error: unrecognized opcode `vamoandei8.v v4,0\(a1\),v8,v4,v0.t'
|
|
|
++.*: Error: unrecognized opcode `vamoandei8.v x0,0\(a1\),v8,v4,v0.t'
|
|
|
++.*: Error: unrecognized opcode `vamoorei8.v v4,0\(a1\),v8,v4'
|
|
|
++.*: Error: unrecognized opcode `vamoorei8.v x0,0\(a1\),v8,v4'
|
|
|
++.*: Error: unrecognized opcode `vamoorei8.v v4,0\(a1\),v8,v4,v0.t'
|
|
|
++.*: Error: unrecognized opcode `vamoorei8.v x0,0\(a1\),v8,v4,v0.t'
|
|
|
++.*: Error: unrecognized opcode `vamominei8.v v4,0\(a1\),v8,v4'
|
|
|
++.*: Error: unrecognized opcode `vamominei8.v x0,0\(a1\),v8,v4'
|
|
|
++.*: Error: unrecognized opcode `vamominei8.v v4,0\(a1\),v8,v4,v0.t'
|
|
|
++.*: Error: unrecognized opcode `vamominei8.v x0,0\(a1\),v8,v4,v0.t'
|
|
|
++.*: Error: unrecognized opcode `vamomaxei8.v v4,0\(a1\),v8,v4'
|
|
|
++.*: Error: unrecognized opcode `vamomaxei8.v x0,0\(a1\),v8,v4'
|
|
|
++.*: Error: unrecognized opcode `vamomaxei8.v v4,0\(a1\),v8,v4,v0.t'
|
|
|
++.*: Error: unrecognized opcode `vamomaxei8.v x0,0\(a1\),v8,v4,v0.t'
|
|
|
++.*: Error: unrecognized opcode `vamominuei8.v v4,0\(a1\),v8,v4'
|
|
|
++.*: Error: unrecognized opcode `vamominuei8.v x0,0\(a1\),v8,v4'
|
|
|
++.*: Error: unrecognized opcode `vamominuei8.v v4,0\(a1\),v8,v4,v0.t'
|
|
|
++.*: Error: unrecognized opcode `vamominuei8.v x0,0\(a1\),v8,v4,v0.t'
|
|
|
++.*: Error: unrecognized opcode `vamomaxuei8.v v4,0\(a1\),v8,v4'
|
|
|
++.*: Error: unrecognized opcode `vamomaxuei8.v x0,0\(a1\),v8,v4'
|
|
|
++.*: Error: unrecognized opcode `vamomaxuei8.v v4,0\(a1\),v8,v4,v0.t'
|
|
|
++.*: Error: unrecognized opcode `vamomaxuei8.v x0,0\(a1\),v8,v4,v0.t'
|
|
|
++.*: Error: unrecognized opcode `vamoaddei16.v v4,\(a1\),v8,v4'
|
|
|
++.*: Error: unrecognized opcode `vamoaddei16.v x0,\(a1\),v8,v4'
|
|
|
++.*: Error: unrecognized opcode `vamoaddei16.v v4,\(a1\),v8,v4,v0.t'
|
|
|
++.*: Error: unrecognized opcode `vamoaddei16.v x0,\(a1\),v8,v4,v0.t'
|
|
|
++.*: Error: unrecognized opcode `vamoswapei16.v v4,\(a1\),v8,v4'
|
|
|
++.*: Error: unrecognized opcode `vamoswapei16.v x0,\(a1\),v8,v4'
|
|
|
++.*: Error: unrecognized opcode `vamoswapei16.v v4,\(a1\),v8,v4,v0.t'
|
|
|
++.*: Error: unrecognized opcode `vamoswapei16.v x0,\(a1\),v8,v4,v0.t'
|
|
|
++.*: Error: unrecognized opcode `vamoxorei16.v v4,\(a1\),v8,v4'
|
|
|
++.*: Error: unrecognized opcode `vamoxorei16.v x0,\(a1\),v8,v4'
|
|
|
++.*: Error: unrecognized opcode `vamoxorei16.v v4,\(a1\),v8,v4,v0.t'
|
|
|
++.*: Error: unrecognized opcode `vamoxorei16.v x0,\(a1\),v8,v4,v0.t'
|
|
|
++.*: Error: unrecognized opcode `vamoandei16.v v4,\(a1\),v8,v4'
|
|
|
++.*: Error: unrecognized opcode `vamoandei16.v x0,\(a1\),v8,v4'
|
|
|
++.*: Error: unrecognized opcode `vamoandei16.v v4,\(a1\),v8,v4,v0.t'
|
|
|
++.*: Error: unrecognized opcode `vamoandei16.v x0,\(a1\),v8,v4,v0.t'
|
|
|
++.*: Error: unrecognized opcode `vamoorei16.v v4,\(a1\),v8,v4'
|
|
|
++.*: Error: unrecognized opcode `vamoorei16.v x0,\(a1\),v8,v4'
|
|
|
++.*: Error: unrecognized opcode `vamoorei16.v v4,\(a1\),v8,v4,v0.t'
|
|
|
++.*: Error: unrecognized opcode `vamoorei16.v x0,\(a1\),v8,v4,v0.t'
|
|
|
++.*: Error: unrecognized opcode `vamominei16.v v4,\(a1\),v8,v4'
|
|
|
++.*: Error: unrecognized opcode `vamominei16.v x0,\(a1\),v8,v4'
|
|
|
++.*: Error: unrecognized opcode `vamominei16.v v4,\(a1\),v8,v4,v0.t'
|
|
|
++.*: Error: unrecognized opcode `vamominei16.v x0,\(a1\),v8,v4,v0.t'
|
|
|
++.*: Error: unrecognized opcode `vamomaxei16.v v4,\(a1\),v8,v4'
|
|
|
++.*: Error: unrecognized opcode `vamomaxei16.v x0,\(a1\),v8,v4'
|
|
|
++.*: Error: unrecognized opcode `vamomaxei16.v v4,\(a1\),v8,v4,v0.t'
|
|
|
++.*: Error: unrecognized opcode `vamomaxei16.v x0,\(a1\),v8,v4,v0.t'
|
|
|
++.*: Error: unrecognized opcode `vamominuei16.v v4,\(a1\),v8,v4'
|
|
|
++.*: Error: unrecognized opcode `vamominuei16.v x0,\(a1\),v8,v4'
|
|
|
++.*: Error: unrecognized opcode `vamominuei16.v v4,\(a1\),v8,v4,v0.t'
|
|
|
++.*: Error: unrecognized opcode `vamominuei16.v x0,\(a1\),v8,v4,v0.t'
|
|
|
++.*: Error: unrecognized opcode `vamomaxuei16.v v4,\(a1\),v8,v4'
|
|
|
++.*: Error: unrecognized opcode `vamomaxuei16.v x0,\(a1\),v8,v4'
|
|
|
++.*: Error: unrecognized opcode `vamomaxuei16.v v4,\(a1\),v8,v4,v0.t'
|
|
|
++.*: Error: unrecognized opcode `vamomaxuei16.v x0,\(a1\),v8,v4,v0.t'
|
|
|
++.*: Error: unrecognized opcode `vamoaddei16.v v4,0\(a1\),v8,v4'
|
|
|
++.*: Error: unrecognized opcode `vamoaddei16.v x0,0\(a1\),v8,v4'
|
|
|
++.*: Error: unrecognized opcode `vamoaddei16.v v4,0\(a1\),v8,v4,v0.t'
|
|
|
++.*: Error: unrecognized opcode `vamoaddei16.v x0,0\(a1\),v8,v4,v0.t'
|
|
|
++.*: Error: unrecognized opcode `vamoswapei16.v v4,0\(a1\),v8,v4'
|
|
|
++.*: Error: unrecognized opcode `vamoswapei16.v x0,0\(a1\),v8,v4'
|
|
|
++.*: Error: unrecognized opcode `vamoswapei16.v v4,0\(a1\),v8,v4,v0.t'
|
|
|
++.*: Error: unrecognized opcode `vamoswapei16.v x0,0\(a1\),v8,v4,v0.t'
|
|
|
++.*: Error: unrecognized opcode `vamoxorei16.v v4,0\(a1\),v8,v4'
|
|
|
++.*: Error: unrecognized opcode `vamoxorei16.v x0,0\(a1\),v8,v4'
|
|
|
++.*: Error: unrecognized opcode `vamoxorei16.v v4,0\(a1\),v8,v4,v0.t'
|
|
|
++.*: Error: unrecognized opcode `vamoxorei16.v x0,0\(a1\),v8,v4,v0.t'
|
|
|
++.*: Error: unrecognized opcode `vamoandei16.v v4,0\(a1\),v8,v4'
|
|
|
++.*: Error: unrecognized opcode `vamoandei16.v x0,0\(a1\),v8,v4'
|
|
|
++.*: Error: unrecognized opcode `vamoandei16.v v4,0\(a1\),v8,v4,v0.t'
|
|
|
++.*: Error: unrecognized opcode `vamoandei16.v x0,0\(a1\),v8,v4,v0.t'
|
|
|
++.*: Error: unrecognized opcode `vamoorei16.v v4,0\(a1\),v8,v4'
|
|
|
++.*: Error: unrecognized opcode `vamoorei16.v x0,0\(a1\),v8,v4'
|
|
|
++.*: Error: unrecognized opcode `vamoorei16.v v4,0\(a1\),v8,v4,v0.t'
|
|
|
++.*: Error: unrecognized opcode `vamoorei16.v x0,0\(a1\),v8,v4,v0.t'
|
|
|
++.*: Error: unrecognized opcode `vamominei16.v v4,0\(a1\),v8,v4'
|
|
|
++.*: Error: unrecognized opcode `vamominei16.v x0,0\(a1\),v8,v4'
|
|
|
++.*: Error: unrecognized opcode `vamominei16.v v4,0\(a1\),v8,v4,v0.t'
|
|
|
++.*: Error: unrecognized opcode `vamominei16.v x0,0\(a1\),v8,v4,v0.t'
|
|
|
++.*: Error: unrecognized opcode `vamomaxei16.v v4,0\(a1\),v8,v4'
|
|
|
++.*: Error: unrecognized opcode `vamomaxei16.v x0,0\(a1\),v8,v4'
|
|
|
++.*: Error: unrecognized opcode `vamomaxei16.v v4,0\(a1\),v8,v4,v0.t'
|
|
|
++.*: Error: unrecognized opcode `vamomaxei16.v x0,0\(a1\),v8,v4,v0.t'
|
|
|
++.*: Error: unrecognized opcode `vamominuei16.v v4,0\(a1\),v8,v4'
|
|
|
++.*: Error: unrecognized opcode `vamominuei16.v x0,0\(a1\),v8,v4'
|
|
|
++.*: Error: unrecognized opcode `vamominuei16.v v4,0\(a1\),v8,v4,v0.t'
|
|
|
++.*: Error: unrecognized opcode `vamominuei16.v x0,0\(a1\),v8,v4,v0.t'
|
|
|
++.*: Error: unrecognized opcode `vamomaxuei16.v v4,0\(a1\),v8,v4'
|
|
|
++.*: Error: unrecognized opcode `vamomaxuei16.v x0,0\(a1\),v8,v4'
|
|
|
++.*: Error: unrecognized opcode `vamomaxuei16.v v4,0\(a1\),v8,v4,v0.t'
|
|
|
++.*: Error: unrecognized opcode `vamomaxuei16.v x0,0\(a1\),v8,v4,v0.t'
|
|
|
++.*: Error: unrecognized opcode `vamoaddei32.v v4,\(a1\),v8,v4'
|
|
|
++.*: Error: unrecognized opcode `vamoaddei32.v x0,\(a1\),v8,v4'
|
|
|
++.*: Error: unrecognized opcode `vamoaddei32.v v4,\(a1\),v8,v4,v0.t'
|
|
|
++.*: Error: unrecognized opcode `vamoaddei32.v x0,\(a1\),v8,v4,v0.t'
|
|
|
++.*: Error: unrecognized opcode `vamoswapei32.v v4,\(a1\),v8,v4'
|
|
|
++.*: Error: unrecognized opcode `vamoswapei32.v x0,\(a1\),v8,v4'
|
|
|
++.*: Error: unrecognized opcode `vamoswapei32.v v4,\(a1\),v8,v4,v0.t'
|
|
|
++.*: Error: unrecognized opcode `vamoswapei32.v x0,\(a1\),v8,v4,v0.t'
|
|
|
++.*: Error: unrecognized opcode `vamoxorei32.v v4,\(a1\),v8,v4'
|
|
|
++.*: Error: unrecognized opcode `vamoxorei32.v x0,\(a1\),v8,v4'
|
|
|
++.*: Error: unrecognized opcode `vamoxorei32.v v4,\(a1\),v8,v4,v0.t'
|
|
|
++.*: Error: unrecognized opcode `vamoxorei32.v x0,\(a1\),v8,v4,v0.t'
|
|
|
++.*: Error: unrecognized opcode `vamoandei32.v v4,\(a1\),v8,v4'
|
|
|
++.*: Error: unrecognized opcode `vamoandei32.v x0,\(a1\),v8,v4'
|
|
|
++.*: Error: unrecognized opcode `vamoandei32.v v4,\(a1\),v8,v4,v0.t'
|
|
|
++.*: Error: unrecognized opcode `vamoandei32.v x0,\(a1\),v8,v4,v0.t'
|
|
|
++.*: Error: unrecognized opcode `vamoorei32.v v4,\(a1\),v8,v4'
|
|
|
++.*: Error: unrecognized opcode `vamoorei32.v x0,\(a1\),v8,v4'
|
|
|
++.*: Error: unrecognized opcode `vamoorei32.v v4,\(a1\),v8,v4,v0.t'
|
|
|
++.*: Error: unrecognized opcode `vamoorei32.v x0,\(a1\),v8,v4,v0.t'
|
|
|
++.*: Error: unrecognized opcode `vamominei32.v v4,\(a1\),v8,v4'
|
|
|
++.*: Error: unrecognized opcode `vamominei32.v x0,\(a1\),v8,v4'
|
|
|
++.*: Error: unrecognized opcode `vamominei32.v v4,\(a1\),v8,v4,v0.t'
|
|
|
++.*: Error: unrecognized opcode `vamominei32.v x0,\(a1\),v8,v4,v0.t'
|
|
|
++.*: Error: unrecognized opcode `vamomaxei32.v v4,\(a1\),v8,v4'
|
|
|
++.*: Error: unrecognized opcode `vamomaxei32.v x0,\(a1\),v8,v4'
|
|
|
++.*: Error: unrecognized opcode `vamomaxei32.v v4,\(a1\),v8,v4,v0.t'
|
|
|
++.*: Error: unrecognized opcode `vamomaxei32.v x0,\(a1\),v8,v4,v0.t'
|
|
|
++.*: Error: unrecognized opcode `vamominuei32.v v4,\(a1\),v8,v4'
|
|
|
++.*: Error: unrecognized opcode `vamominuei32.v x0,\(a1\),v8,v4'
|
|
|
++.*: Error: unrecognized opcode `vamominuei32.v v4,\(a1\),v8,v4,v0.t'
|
|
|
++.*: Error: unrecognized opcode `vamominuei32.v x0,\(a1\),v8,v4,v0.t'
|
|
|
++.*: Error: unrecognized opcode `vamomaxuei32.v v4,\(a1\),v8,v4'
|
|
|
++.*: Error: unrecognized opcode `vamomaxuei32.v x0,\(a1\),v8,v4'
|
|
|
++.*: Error: unrecognized opcode `vamomaxuei32.v v4,\(a1\),v8,v4,v0.t'
|
|
|
++.*: Error: unrecognized opcode `vamomaxuei32.v x0,\(a1\),v8,v4,v0.t'
|
|
|
++.*: Error: unrecognized opcode `vamoaddei32.v v4,0\(a1\),v8,v4'
|
|
|
++.*: Error: unrecognized opcode `vamoaddei32.v x0,0\(a1\),v8,v4'
|
|
|
++.*: Error: unrecognized opcode `vamoaddei32.v v4,0\(a1\),v8,v4,v0.t'
|
|
|
++.*: Error: unrecognized opcode `vamoaddei32.v x0,0\(a1\),v8,v4,v0.t'
|
|
|
++.*: Error: unrecognized opcode `vamoswapei32.v v4,0\(a1\),v8,v4'
|
|
|
++.*: Error: unrecognized opcode `vamoswapei32.v x0,0\(a1\),v8,v4'
|
|
|
++.*: Error: unrecognized opcode `vamoswapei32.v v4,0\(a1\),v8,v4,v0.t'
|
|
|
++.*: Error: unrecognized opcode `vamoswapei32.v x0,0\(a1\),v8,v4,v0.t'
|
|
|
++.*: Error: unrecognized opcode `vamoxorei32.v v4,0\(a1\),v8,v4'
|
|
|
++.*: Error: unrecognized opcode `vamoxorei32.v x0,0\(a1\),v8,v4'
|
|
|
++.*: Error: unrecognized opcode `vamoxorei32.v v4,0\(a1\),v8,v4,v0.t'
|
|
|
++.*: Error: unrecognized opcode `vamoxorei32.v x0,0\(a1\),v8,v4,v0.t'
|
|
|
++.*: Error: unrecognized opcode `vamoandei32.v v4,0\(a1\),v8,v4'
|
|
|
++.*: Error: unrecognized opcode `vamoandei32.v x0,0\(a1\),v8,v4'
|
|
|
++.*: Error: unrecognized opcode `vamoandei32.v v4,0\(a1\),v8,v4,v0.t'
|
|
|
++.*: Error: unrecognized opcode `vamoandei32.v x0,0\(a1\),v8,v4,v0.t'
|
|
|
++.*: Error: unrecognized opcode `vamoorei32.v v4,0\(a1\),v8,v4'
|
|
|
++.*: Error: unrecognized opcode `vamoorei32.v x0,0\(a1\),v8,v4'
|
|
|
++.*: Error: unrecognized opcode `vamoorei32.v v4,0\(a1\),v8,v4,v0.t'
|
|
|
++.*: Error: unrecognized opcode `vamoorei32.v x0,0\(a1\),v8,v4,v0.t'
|
|
|
++.*: Error: unrecognized opcode `vamominei32.v v4,0\(a1\),v8,v4'
|
|
|
++.*: Error: unrecognized opcode `vamominei32.v x0,0\(a1\),v8,v4'
|
|
|
++.*: Error: unrecognized opcode `vamominei32.v v4,0\(a1\),v8,v4,v0.t'
|
|
|
++.*: Error: unrecognized opcode `vamominei32.v x0,0\(a1\),v8,v4,v0.t'
|
|
|
++.*: Error: unrecognized opcode `vamomaxei32.v v4,0\(a1\),v8,v4'
|
|
|
++.*: Error: unrecognized opcode `vamomaxei32.v x0,0\(a1\),v8,v4'
|
|
|
++.*: Error: unrecognized opcode `vamomaxei32.v v4,0\(a1\),v8,v4,v0.t'
|
|
|
++.*: Error: unrecognized opcode `vamomaxei32.v x0,0\(a1\),v8,v4,v0.t'
|
|
|
++.*: Error: unrecognized opcode `vamominuei32.v v4,0\(a1\),v8,v4'
|
|
|
++.*: Error: unrecognized opcode `vamominuei32.v x0,0\(a1\),v8,v4'
|
|
|
++.*: Error: unrecognized opcode `vamominuei32.v v4,0\(a1\),v8,v4,v0.t'
|
|
|
++.*: Error: unrecognized opcode `vamominuei32.v x0,0\(a1\),v8,v4,v0.t'
|
|
|
++.*: Error: unrecognized opcode `vamomaxuei32.v v4,0\(a1\),v8,v4'
|
|
|
++.*: Error: unrecognized opcode `vamomaxuei32.v x0,0\(a1\),v8,v4'
|
|
|
++.*: Error: unrecognized opcode `vamomaxuei32.v v4,0\(a1\),v8,v4,v0.t'
|
|
|
++.*: Error: unrecognized opcode `vamomaxuei32.v x0,0\(a1\),v8,v4,v0.t'
|
|
|
++.*: Error: unrecognized opcode `vamoaddei64.v v4,\(a1\),v8,v4'
|
|
|
++.*: Error: unrecognized opcode `vamoaddei64.v x0,\(a1\),v8,v4'
|
|
|
++.*: Error: unrecognized opcode `vamoaddei64.v v4,\(a1\),v8,v4,v0.t'
|
|
|
++.*: Error: unrecognized opcode `vamoaddei64.v x0,\(a1\),v8,v4,v0.t'
|
|
|
++.*: Error: unrecognized opcode `vamoswapei64.v v4,\(a1\),v8,v4'
|
|
|
++.*: Error: unrecognized opcode `vamoswapei64.v x0,\(a1\),v8,v4'
|
|
|
++.*: Error: unrecognized opcode `vamoswapei64.v v4,\(a1\),v8,v4,v0.t'
|
|
|
++.*: Error: unrecognized opcode `vamoswapei64.v x0,\(a1\),v8,v4,v0.t'
|
|
|
++.*: Error: unrecognized opcode `vamoxorei64.v v4,\(a1\),v8,v4'
|
|
|
++.*: Error: unrecognized opcode `vamoxorei64.v x0,\(a1\),v8,v4'
|
|
|
++.*: Error: unrecognized opcode `vamoxorei64.v v4,\(a1\),v8,v4,v0.t'
|
|
|
++.*: Error: unrecognized opcode `vamoxorei64.v x0,\(a1\),v8,v4,v0.t'
|
|
|
++.*: Error: unrecognized opcode `vamoandei64.v v4,\(a1\),v8,v4'
|
|
|
++.*: Error: unrecognized opcode `vamoandei64.v x0,\(a1\),v8,v4'
|
|
|
++.*: Error: unrecognized opcode `vamoandei64.v v4,\(a1\),v8,v4,v0.t'
|
|
|
++.*: Error: unrecognized opcode `vamoandei64.v x0,\(a1\),v8,v4,v0.t'
|
|
|
++.*: Error: unrecognized opcode `vamoorei64.v v4,\(a1\),v8,v4'
|
|
|
++.*: Error: unrecognized opcode `vamoorei64.v x0,\(a1\),v8,v4'
|
|
|
++.*: Error: unrecognized opcode `vamoorei64.v v4,\(a1\),v8,v4,v0.t'
|
|
|
++.*: Error: unrecognized opcode `vamoorei64.v x0,\(a1\),v8,v4,v0.t'
|
|
|
++.*: Error: unrecognized opcode `vamominei64.v v4,\(a1\),v8,v4'
|
|
|
++.*: Error: unrecognized opcode `vamominei64.v x0,\(a1\),v8,v4'
|
|
|
++.*: Error: unrecognized opcode `vamominei64.v v4,\(a1\),v8,v4,v0.t'
|
|
|
++.*: Error: unrecognized opcode `vamominei64.v x0,\(a1\),v8,v4,v0.t'
|
|
|
++.*: Error: unrecognized opcode `vamomaxei64.v v4,\(a1\),v8,v4'
|
|
|
++.*: Error: unrecognized opcode `vamomaxei64.v x0,\(a1\),v8,v4'
|
|
|
++.*: Error: unrecognized opcode `vamomaxei64.v v4,\(a1\),v8,v4,v0.t'
|
|
|
++.*: Error: unrecognized opcode `vamomaxei64.v x0,\(a1\),v8,v4,v0.t'
|
|
|
++.*: Error: unrecognized opcode `vamominuei64.v v4,\(a1\),v8,v4'
|
|
|
++.*: Error: unrecognized opcode `vamominuei64.v x0,\(a1\),v8,v4'
|
|
|
++.*: Error: unrecognized opcode `vamominuei64.v v4,\(a1\),v8,v4,v0.t'
|
|
|
++.*: Error: unrecognized opcode `vamominuei64.v x0,\(a1\),v8,v4,v0.t'
|
|
|
++.*: Error: unrecognized opcode `vamomaxuei64.v v4,\(a1\),v8,v4'
|
|
|
++.*: Error: unrecognized opcode `vamomaxuei64.v x0,\(a1\),v8,v4'
|
|
|
++.*: Error: unrecognized opcode `vamomaxuei64.v v4,\(a1\),v8,v4,v0.t'
|
|
|
++.*: Error: unrecognized opcode `vamomaxuei64.v x0,\(a1\),v8,v4,v0.t'
|
|
|
++.*: Error: unrecognized opcode `vamoaddei64.v v4,0\(a1\),v8,v4'
|
|
|
++.*: Error: unrecognized opcode `vamoaddei64.v x0,0\(a1\),v8,v4'
|
|
|
++.*: Error: unrecognized opcode `vamoaddei64.v v4,0\(a1\),v8,v4,v0.t'
|
|
|
++.*: Error: unrecognized opcode `vamoaddei64.v x0,0\(a1\),v8,v4,v0.t'
|
|
|
++.*: Error: unrecognized opcode `vamoswapei64.v v4,0\(a1\),v8,v4'
|
|
|
++.*: Error: unrecognized opcode `vamoswapei64.v x0,0\(a1\),v8,v4'
|
|
|
++.*: Error: unrecognized opcode `vamoswapei64.v v4,0\(a1\),v8,v4,v0.t'
|
|
|
++.*: Error: unrecognized opcode `vamoswapei64.v x0,0\(a1\),v8,v4,v0.t'
|
|
|
++.*: Error: unrecognized opcode `vamoxorei64.v v4,0\(a1\),v8,v4'
|
|
|
++.*: Error: unrecognized opcode `vamoxorei64.v x0,0\(a1\),v8,v4'
|
|
|
++.*: Error: unrecognized opcode `vamoxorei64.v v4,0\(a1\),v8,v4,v0.t'
|
|
|
++.*: Error: unrecognized opcode `vamoxorei64.v x0,0\(a1\),v8,v4,v0.t'
|
|
|
++.*: Error: unrecognized opcode `vamoandei64.v v4,0\(a1\),v8,v4'
|
|
|
++.*: Error: unrecognized opcode `vamoandei64.v x0,0\(a1\),v8,v4'
|
|
|
++.*: Error: unrecognized opcode `vamoandei64.v v4,0\(a1\),v8,v4,v0.t'
|
|
|
++.*: Error: unrecognized opcode `vamoandei64.v x0,0\(a1\),v8,v4,v0.t'
|
|
|
++.*: Error: unrecognized opcode `vamoorei64.v v4,0\(a1\),v8,v4'
|
|
|
++.*: Error: unrecognized opcode `vamoorei64.v x0,0\(a1\),v8,v4'
|
|
|
++.*: Error: unrecognized opcode `vamoorei64.v v4,0\(a1\),v8,v4,v0.t'
|
|
|
++.*: Error: unrecognized opcode `vamoorei64.v x0,0\(a1\),v8,v4,v0.t'
|
|
|
++.*: Error: unrecognized opcode `vamominei64.v v4,0\(a1\),v8,v4'
|
|
|
++.*: Error: unrecognized opcode `vamominei64.v x0,0\(a1\),v8,v4'
|
|
|
++.*: Error: unrecognized opcode `vamominei64.v v4,0\(a1\),v8,v4,v0.t'
|
|
|
++.*: Error: unrecognized opcode `vamominei64.v x0,0\(a1\),v8,v4,v0.t'
|
|
|
++.*: Error: unrecognized opcode `vamomaxei64.v v4,0\(a1\),v8,v4'
|
|
|
++.*: Error: unrecognized opcode `vamomaxei64.v x0,0\(a1\),v8,v4'
|
|
|
++.*: Error: unrecognized opcode `vamomaxei64.v v4,0\(a1\),v8,v4,v0.t'
|
|
|
++.*: Error: unrecognized opcode `vamomaxei64.v x0,0\(a1\),v8,v4,v0.t'
|
|
|
++.*: Error: unrecognized opcode `vamominuei64.v v4,0\(a1\),v8,v4'
|
|
|
++.*: Error: unrecognized opcode `vamominuei64.v x0,0\(a1\),v8,v4'
|
|
|
++.*: Error: unrecognized opcode `vamominuei64.v v4,0\(a1\),v8,v4,v0.t'
|
|
|
++.*: Error: unrecognized opcode `vamominuei64.v x0,0\(a1\),v8,v4,v0.t'
|
|
|
++.*: Error: unrecognized opcode `vamomaxuei64.v v4,0\(a1\),v8,v4'
|
|
|
++.*: Error: unrecognized opcode `vamomaxuei64.v x0,0\(a1\),v8,v4'
|
|
|
++.*: Error: unrecognized opcode `vamomaxuei64.v v4,0\(a1\),v8,v4,v0.t'
|
|
|
++.*: Error: unrecognized opcode `vamomaxuei64.v x0,0\(a1\),v8,v4,v0.t'
|
|
|
++.*: Error: unrecognized opcode `vwcvt.x.x.v v4,v8'
|
|
|
++.*: Error: unrecognized opcode `vwcvtu.x.x.v v4,v8'
|
|
|
++.*: Error: unrecognized opcode `vwcvt.x.x.v v4,v8,v0.t'
|
|
|
++.*: Error: unrecognized opcode `vwcvtu.x.x.v v4,v8,v0.t'
|
|
|
++.*: Error: unrecognized opcode `vwaddu.vv v4,v8,v12'
|
|
|
++.*: Error: unrecognized opcode `vwaddu.vx v4,v8,a1'
|
|
|
++.*: Error: unrecognized opcode `vwaddu.vv v4,v8,v12,v0.t'
|
|
|
++.*: Error: unrecognized opcode `vwaddu.vx v4,v8,a1,v0.t'
|
|
|
++.*: Error: unrecognized opcode `vwsubu.vv v4,v8,v12'
|
|
|
++.*: Error: unrecognized opcode `vwsubu.vx v4,v8,a1'
|
|
|
++.*: Error: unrecognized opcode `vwsubu.vv v4,v8,v12,v0.t'
|
|
|
++.*: Error: unrecognized opcode `vwsubu.vx v4,v8,a1,v0.t'
|
|
|
++.*: Error: unrecognized opcode `vwadd.vv v4,v8,v12'
|
|
|
++.*: Error: unrecognized opcode `vwadd.vx v4,v8,a1'
|
|
|
++.*: Error: unrecognized opcode `vwadd.vv v4,v8,v12,v0.t'
|
|
|
++.*: Error: unrecognized opcode `vwadd.vx v4,v8,a1,v0.t'
|
|
|
++.*: Error: unrecognized opcode `vwsub.vv v4,v8,v12'
|
|
|
++.*: Error: unrecognized opcode `vwsub.vx v4,v8,a1'
|
|
|
++.*: Error: unrecognized opcode `vwsub.vv v4,v8,v12,v0.t'
|
|
|
++.*: Error: unrecognized opcode `vwsub.vx v4,v8,a1,v0.t'
|
|
|
++.*: Error: unrecognized opcode `vwaddu.wv v4,v8,v12'
|
|
|
++.*: Error: unrecognized opcode `vwaddu.wx v4,v8,a1'
|
|
|
++.*: Error: unrecognized opcode `vwaddu.wv v4,v8,v12,v0.t'
|
|
|
++.*: Error: unrecognized opcode `vwaddu.wx v4,v8,a1,v0.t'
|
|
|
++.*: Error: unrecognized opcode `vwsubu.wv v4,v8,v12'
|
|
|
++.*: Error: unrecognized opcode `vwsubu.wx v4,v8,a1'
|
|
|
++.*: Error: unrecognized opcode `vwsubu.wv v4,v8,v12,v0.t'
|
|
|
++.*: Error: unrecognized opcode `vwsubu.wx v4,v8,a1,v0.t'
|
|
|
++.*: Error: unrecognized opcode `vwadd.wv v4,v8,v12'
|
|
|
++.*: Error: unrecognized opcode `vwadd.wx v4,v8,a1'
|
|
|
++.*: Error: unrecognized opcode `vwadd.wv v4,v8,v12,v0.t'
|
|
|
++.*: Error: unrecognized opcode `vwadd.wx v4,v8,a1,v0.t'
|
|
|
++.*: Error: unrecognized opcode `vwsub.wv v4,v8,v12'
|
|
|
++.*: Error: unrecognized opcode `vwsub.wx v4,v8,a1'
|
|
|
++.*: Error: unrecognized opcode `vwsub.wv v4,v8,v12,v0.t'
|
|
|
++.*: Error: unrecognized opcode `vwsub.wx v4,v8,a1,v0.t'
|
|
|
++.*: Error: unrecognized opcode `vsll.vv v4,v8,v12'
|
|
|
++.*: Error: unrecognized opcode `vsll.vx v4,v8,a1'
|
|
|
++.*: Error: unrecognized opcode `vsll.vi v4,v8,1'
|
|
|
++.*: Error: unrecognized opcode `vsll.vi v4,v8,31'
|
|
|
++.*: Error: unrecognized opcode `vsll.vv v4,v8,v12,v0.t'
|
|
|
++.*: Error: unrecognized opcode `vsll.vx v4,v8,a1,v0.t'
|
|
|
++.*: Error: unrecognized opcode `vsll.vi v4,v8,1,v0.t'
|
|
|
++.*: Error: unrecognized opcode `vsll.vi v4,v8,31,v0.t'
|
|
|
++.*: Error: unrecognized opcode `vsrl.vv v4,v8,v12'
|
|
|
++.*: Error: unrecognized opcode `vsrl.vx v4,v8,a1'
|
|
|
++.*: Error: unrecognized opcode `vsrl.vi v4,v8,1'
|
|
|
++.*: Error: unrecognized opcode `vsrl.vi v4,v8,31'
|
|
|
++.*: Error: unrecognized opcode `vsrl.vv v4,v8,v12,v0.t'
|
|
|
++.*: Error: unrecognized opcode `vsrl.vx v4,v8,a1,v0.t'
|
|
|
++.*: Error: unrecognized opcode `vsrl.vi v4,v8,1,v0.t'
|
|
|
++.*: Error: unrecognized opcode `vsrl.vi v4,v8,31,v0.t'
|
|
|
++.*: Error: unrecognized opcode `vsra.vv v4,v8,v12'
|
|
|
++.*: Error: unrecognized opcode `vsra.vx v4,v8,a1'
|
|
|
++.*: Error: unrecognized opcode `vsra.vi v4,v8,1'
|
|
|
++.*: Error: unrecognized opcode `vsra.vi v4,v8,31'
|
|
|
++.*: Error: unrecognized opcode `vsra.vv v4,v8,v12,v0.t'
|
|
|
++.*: Error: unrecognized opcode `vsra.vx v4,v8,a1,v0.t'
|
|
|
++.*: Error: unrecognized opcode `vsra.vi v4,v8,1,v0.t'
|
|
|
++.*: Error: unrecognized opcode `vsra.vi v4,v8,31,v0.t'
|
|
|
++.*: Error: unrecognized opcode `vncvt.x.x.w v4,v8'
|
|
|
++.*: Error: unrecognized opcode `vncvt.x.x.w v4,v8,v0.t'
|
|
|
++.*: Error: unrecognized opcode `vnsrl.wv v4,v8,v12'
|
|
|
++.*: Error: unrecognized opcode `vnsrl.wx v4,v8,a1'
|
|
|
++.*: Error: unrecognized opcode `vnsrl.wi v4,v8,1'
|
|
|
++.*: Error: unrecognized opcode `vnsrl.wi v4,v8,31'
|
|
|
++.*: Error: unrecognized opcode `vnsrl.wv v4,v8,v12,v0.t'
|
|
|
++.*: Error: unrecognized opcode `vnsrl.wx v4,v8,a1,v0.t'
|
|
|
++.*: Error: unrecognized opcode `vnsrl.wi v4,v8,1,v0.t'
|
|
|
++.*: Error: unrecognized opcode `vnsrl.wi v4,v8,31,v0.t'
|
|
|
++.*: Error: unrecognized opcode `vnsra.wv v4,v8,v12'
|
|
|
++.*: Error: unrecognized opcode `vnsra.wx v4,v8,a1'
|
|
|
++.*: Error: unrecognized opcode `vnsra.wi v4,v8,1'
|
|
|
++.*: Error: unrecognized opcode `vnsra.wi v4,v8,31'
|
|
|
++.*: Error: unrecognized opcode `vnsra.wv v4,v8,v12,v0.t'
|
|
|
++.*: Error: unrecognized opcode `vnsra.wx v4,v8,a1,v0.t'
|
|
|
++.*: Error: unrecognized opcode `vnsra.wi v4,v8,1,v0.t'
|
|
|
++.*: Error: unrecognized opcode `vnsra.wi v4,v8,31,v0.t'
|
|
|
++.*: Error: unrecognized opcode `vwmul.vv v4,v8,v12'
|
|
|
++.*: Error: unrecognized opcode `vwmul.vx v4,v8,a1'
|
|
|
++.*: Error: unrecognized opcode `vwmul.vv v4,v8,v12,v0.t'
|
|
|
++.*: Error: unrecognized opcode `vwmul.vx v4,v8,a1,v0.t'
|
|
|
++.*: Error: unrecognized opcode `vwmulu.vv v4,v8,v12'
|
|
|
++.*: Error: unrecognized opcode `vwmulu.vx v4,v8,a1'
|
|
|
++.*: Error: unrecognized opcode `vwmulu.vv v4,v8,v12,v0.t'
|
|
|
++.*: Error: unrecognized opcode `vwmulu.vx v4,v8,a1,v0.t'
|
|
|
++.*: Error: unrecognized opcode `vwmulsu.vv v4,v8,v12'
|
|
|
++.*: Error: unrecognized opcode `vwmulsu.vx v4,v8,a1'
|
|
|
++.*: Error: unrecognized opcode `vwmulsu.vv v4,v8,v12,v0.t'
|
|
|
++.*: Error: unrecognized opcode `vwmulsu.vx v4,v8,a1,v0.t'
|
|
|
++.*: Error: unrecognized opcode `vwmaccu.vv v4,v12,v8'
|
|
|
++.*: Error: unrecognized opcode `vwmaccu.vx v4,a1,v8'
|
|
|
++.*: Error: unrecognized opcode `vwmaccu.vv v4,v12,v8,v0.t'
|
|
|
++.*: Error: unrecognized opcode `vwmaccu.vx v4,a1,v8,v0.t'
|
|
|
++.*: Error: unrecognized opcode `vwmacc.vv v4,v12,v8'
|
|
|
++.*: Error: unrecognized opcode `vwmacc.vx v4,a1,v8'
|
|
|
++.*: Error: unrecognized opcode `vwmacc.vv v4,v12,v8,v0.t'
|
|
|
++.*: Error: unrecognized opcode `vwmacc.vx v4,a1,v8,v0.t'
|
|
|
++.*: Error: unrecognized opcode `vwmaccsu.vv v4,v12,v8'
|
|
|
++.*: Error: unrecognized opcode `vwmaccsu.vx v4,a1,v8'
|
|
|
++.*: Error: unrecognized opcode `vwmaccsu.vv v4,v12,v8,v0.t'
|
|
|
++.*: Error: unrecognized opcode `vwmaccsu.vx v4,a1,v8,v0.t'
|
|
|
++.*: Error: unrecognized opcode `vwmaccus.vx v4,a1,v8'
|
|
|
++.*: Error: unrecognized opcode `vwmaccus.vx v4,a1,v8,v0.t'
|
|
|
++.*: Error: unrecognized opcode `vsaddu.vv v4,v8,v12'
|
|
|
++.*: Error: unrecognized opcode `vsaddu.vx v4,v8,a1'
|
|
|
++.*: Error: unrecognized opcode `vsaddu.vi v4,v8,15'
|
|
|
++.*: Error: unrecognized opcode `vsaddu.vi v4,v8,-16'
|
|
|
++.*: Error: unrecognized opcode `vsaddu.vv v4,v8,v12,v0.t'
|
|
|
++.*: Error: unrecognized opcode `vsaddu.vx v4,v8,a1,v0.t'
|
|
|
++.*: Error: unrecognized opcode `vsaddu.vi v4,v8,15,v0.t'
|
|
|
++.*: Error: unrecognized opcode `vsaddu.vi v4,v8,-16,v0.t'
|
|
|
++.*: Error: unrecognized opcode `vsadd.vv v4,v8,v12'
|
|
|
++.*: Error: unrecognized opcode `vsadd.vx v4,v8,a1'
|
|
|
++.*: Error: unrecognized opcode `vsadd.vi v4,v8,15'
|
|
|
++.*: Error: unrecognized opcode `vsadd.vi v4,v8,-16'
|
|
|
++.*: Error: unrecognized opcode `vsadd.vv v4,v8,v12,v0.t'
|
|
|
++.*: Error: unrecognized opcode `vsadd.vx v4,v8,a1,v0.t'
|
|
|
++.*: Error: unrecognized opcode `vsadd.vi v4,v8,15,v0.t'
|
|
|
++.*: Error: unrecognized opcode `vsadd.vi v4,v8,-16,v0.t'
|
|
|
++.*: Error: unrecognized opcode `vssubu.vv v4,v8,v12'
|
|
|
++.*: Error: unrecognized opcode `vssubu.vx v4,v8,a1'
|
|
|
++.*: Error: unrecognized opcode `vssubu.vv v4,v8,v12,v0.t'
|
|
|
++.*: Error: unrecognized opcode `vssubu.vx v4,v8,a1,v0.t'
|
|
|
++.*: Error: unrecognized opcode `vssub.vv v4,v8,v12'
|
|
|
++.*: Error: unrecognized opcode `vssub.vx v4,v8,a1'
|
|
|
++.*: Error: unrecognized opcode `vssub.vv v4,v8,v12,v0.t'
|
|
|
++.*: Error: unrecognized opcode `vssub.vx v4,v8,a1,v0.t'
|
|
|
++.*: Error: unrecognized opcode `vaaddu.vv v4,v8,v12'
|
|
|
++.*: Error: unrecognized opcode `vaaddu.vx v4,v8,a1'
|
|
|
++.*: Error: unrecognized opcode `vaaddu.vv v4,v8,v12,v0.t'
|
|
|
++.*: Error: unrecognized opcode `vaaddu.vx v4,v8,a1,v0.t'
|
|
|
++.*: Error: unrecognized opcode `vaadd.vv v4,v8,v12'
|
|
|
++.*: Error: unrecognized opcode `vaadd.vx v4,v8,a1'
|
|
|
++.*: Error: unrecognized opcode `vaadd.vv v4,v8,v12,v0.t'
|
|
|
++.*: Error: unrecognized opcode `vaadd.vx v4,v8,a1,v0.t'
|
|
|
++.*: Error: unrecognized opcode `vasubu.vv v4,v8,v12'
|
|
|
++.*: Error: unrecognized opcode `vasubu.vx v4,v8,a1'
|
|
|
++.*: Error: unrecognized opcode `vasubu.vv v4,v8,v12,v0.t'
|
|
|
++.*: Error: unrecognized opcode `vasubu.vx v4,v8,a1,v0.t'
|
|
|
++.*: Error: unrecognized opcode `vasub.vv v4,v8,v12'
|
|
|
++.*: Error: unrecognized opcode `vasub.vx v4,v8,a1'
|
|
|
++.*: Error: unrecognized opcode `vasub.vv v4,v8,v12,v0.t'
|
|
|
++.*: Error: unrecognized opcode `vasub.vx v4,v8,a1,v0.t'
|
|
|
++.*: Error: unrecognized opcode `vsmul.vv v4,v8,v12'
|
|
|
++.*: Error: unrecognized opcode `vsmul.vx v4,v8,a1'
|
|
|
++.*: Error: unrecognized opcode `vsmul.vv v4,v8,v12,v0.t'
|
|
|
++.*: Error: unrecognized opcode `vsmul.vx v4,v8,a1,v0.t'
|
|
|
++.*: Error: unrecognized opcode `vssrl.vv v4,v8,v12'
|
|
|
++.*: Error: unrecognized opcode `vssrl.vx v4,v8,a1'
|
|
|
++.*: Error: unrecognized opcode `vssrl.vi v4,v8,1'
|
|
|
++.*: Error: unrecognized opcode `vssrl.vi v4,v8,31'
|
|
|
++.*: Error: unrecognized opcode `vssrl.vv v4,v8,v12,v0.t'
|
|
|
++.*: Error: unrecognized opcode `vssrl.vx v4,v8,a1,v0.t'
|
|
|
++.*: Error: unrecognized opcode `vssrl.vi v4,v8,1,v0.t'
|
|
|
++.*: Error: unrecognized opcode `vssrl.vi v4,v8,31,v0.t'
|
|
|
++.*: Error: unrecognized opcode `vssra.vv v4,v8,v12'
|
|
|
++.*: Error: unrecognized opcode `vssra.vx v4,v8,a1'
|
|
|
++.*: Error: unrecognized opcode `vssra.vi v4,v8,1'
|
|
|
++.*: Error: unrecognized opcode `vssra.vi v4,v8,31'
|
|
|
++.*: Error: unrecognized opcode `vssra.vv v4,v8,v12,v0.t'
|
|
|
++.*: Error: unrecognized opcode `vssra.vx v4,v8,a1,v0.t'
|
|
|
++.*: Error: unrecognized opcode `vssra.vi v4,v8,1,v0.t'
|
|
|
++.*: Error: unrecognized opcode `vssra.vi v4,v8,31,v0.t'
|
|
|
++.*: Error: unrecognized opcode `vnclipu.wv v4,v8,v12'
|
|
|
++.*: Error: unrecognized opcode `vnclipu.wx v4,v8,a1'
|
|
|
++.*: Error: unrecognized opcode `vnclipu.wi v4,v8,1'
|
|
|
++.*: Error: unrecognized opcode `vnclipu.wi v4,v8,31'
|
|
|
++.*: Error: unrecognized opcode `vnclipu.wv v4,v8,v12,v0.t'
|
|
|
++.*: Error: unrecognized opcode `vnclipu.wx v4,v8,a1,v0.t'
|
|
|
++.*: Error: unrecognized opcode `vnclipu.wi v4,v8,1,v0.t'
|
|
|
++.*: Error: unrecognized opcode `vnclipu.wi v4,v8,31,v0.t'
|
|
|
++.*: Error: unrecognized opcode `vnclip.wv v4,v8,v12'
|
|
|
++.*: Error: unrecognized opcode `vnclip.wx v4,v8,a1'
|
|
|
++.*: Error: unrecognized opcode `vnclip.wi v4,v8,1'
|
|
|
++.*: Error: unrecognized opcode `vnclip.wi v4,v8,31'
|
|
|
++.*: Error: unrecognized opcode `vnclip.wv v4,v8,v12,v0.t'
|
|
|
++.*: Error: unrecognized opcode `vnclip.wx v4,v8,a1,v0.t'
|
|
|
++.*: Error: unrecognized opcode `vnclip.wi v4,v8,1,v0.t'
|
|
|
++.*: Error: unrecognized opcode `vnclip.wi v4,v8,31,v0.t'
|
|
|
++.*: Error: unrecognized opcode `vfwadd.vv v4,v8,v12'
|
|
|
++.*: Error: unrecognized opcode `vfwadd.vf v4,v8,fa2'
|
|
|
++.*: Error: unrecognized opcode `vfwadd.vv v4,v8,v12,v0.t'
|
|
|
++.*: Error: unrecognized opcode `vfwadd.vf v4,v8,fa2,v0.t'
|
|
|
++.*: Error: unrecognized opcode `vfwsub.vv v4,v8,v12'
|
|
|
++.*: Error: unrecognized opcode `vfwsub.vf v4,v8,fa2'
|
|
|
++.*: Error: unrecognized opcode `vfwsub.vv v4,v8,v12,v0.t'
|
|
|
++.*: Error: unrecognized opcode `vfwsub.vf v4,v8,fa2,v0.t'
|
|
|
++.*: Error: unrecognized opcode `vfwadd.wv v4,v8,v12'
|
|
|
++.*: Error: unrecognized opcode `vfwadd.wf v4,v8,fa2'
|
|
|
++.*: Error: unrecognized opcode `vfwadd.wv v4,v8,v12,v0.t'
|
|
|
++.*: Error: unrecognized opcode `vfwadd.wf v4,v8,fa2,v0.t'
|
|
|
++.*: Error: unrecognized opcode `vfwsub.wv v4,v8,v12'
|
|
|
++.*: Error: unrecognized opcode `vfwsub.wf v4,v8,fa2'
|
|
|
++.*: Error: unrecognized opcode `vfwsub.wv v4,v8,v12,v0.t'
|
|
|
++.*: Error: unrecognized opcode `vfwsub.wf v4,v8,fa2,v0.t'
|
|
|
++.*: Error: unrecognized opcode `vfwmul.vv v4,v8,v12'
|
|
|
++.*: Error: unrecognized opcode `vfwmul.vf v4,v8,fa2'
|
|
|
++.*: Error: unrecognized opcode `vfwmul.vv v4,v8,v12,v0.t'
|
|
|
++.*: Error: unrecognized opcode `vfwmul.vf v4,v8,fa2,v0.t'
|
|
|
++.*: Error: unrecognized opcode `vfwmacc.vv v4,v12,v8'
|
|
|
++.*: Error: unrecognized opcode `vfwmacc.vf v4,fa2,v8'
|
|
|
++.*: Error: unrecognized opcode `vfwnmacc.vv v4,v12,v8'
|
|
|
++.*: Error: unrecognized opcode `vfwnmacc.vf v4,fa2,v8'
|
|
|
++.*: Error: unrecognized opcode `vfwmsac.vv v4,v12,v8'
|
|
|
++.*: Error: unrecognized opcode `vfwmsac.vf v4,fa2,v8'
|
|
|
++.*: Error: unrecognized opcode `vfwnmsac.vv v4,v12,v8'
|
|
|
++.*: Error: unrecognized opcode `vfwnmsac.vf v4,fa2,v8'
|
|
|
++.*: Error: unrecognized opcode `vfwmacc.vv v4,v12,v8,v0.t'
|
|
|
++.*: Error: unrecognized opcode `vfwmacc.vf v4,fa2,v8,v0.t'
|
|
|
++.*: Error: unrecognized opcode `vfwnmacc.vv v4,v12,v8,v0.t'
|
|
|
++.*: Error: unrecognized opcode `vfwnmacc.vf v4,fa2,v8,v0.t'
|
|
|
++.*: Error: unrecognized opcode `vfwmsac.vv v4,v12,v8,v0.t'
|
|
|
++.*: Error: unrecognized opcode `vfwmsac.vf v4,fa2,v8,v0.t'
|
|
|
++.*: Error: unrecognized opcode `vfwnmsac.vv v4,v12,v8,v0.t'
|
|
|
++.*: Error: unrecognized opcode `vfwnmsac.vf v4,fa2,v8,v0.t'
|
|
|
++.*: Error: unrecognized opcode `vfsqrt.v v4,v8'
|
|
|
++.*: Error: unrecognized opcode `vfsqrt.v v4,v8,v0.t'
|
|
|
++.*: Error: unrecognized opcode `vfrsqrte7.v v4,v8'
|
|
|
++.*: Error: unrecognized opcode `vfrsqrte7.v v4,v8,v0.t'
|
|
|
++.*: Error: unrecognized opcode `vfrsqrt7.v v4,v8'
|
|
|
++.*: Error: unrecognized opcode `vfrsqrt7.v v4,v8,v0.t'
|
|
|
++.*: Error: unrecognized opcode `vfrece7.v v4,v8'
|
|
|
++.*: Error: unrecognized opcode `vfrece7.v v4,v8,v0.t'
|
|
|
++.*: Error: unrecognized opcode `vfrec7.v v4,v8'
|
|
|
++.*: Error: unrecognized opcode `vfrec7.v v4,v8,v0.t'
|
|
|
++.*: Error: unrecognized opcode `vfclass.v v4,v8'
|
|
|
++.*: Error: unrecognized opcode `vfclass.v v4,v8,v0.t'
|
|
|
++.*: Error: unrecognized opcode `vfcvt.xu.f.v v4,v8'
|
|
|
++.*: Error: unrecognized opcode `vfcvt.x.f.v v4,v8'
|
|
|
++.*: Error: unrecognized opcode `vfcvt.rtz.xu.f.v v4,v8'
|
|
|
++.*: Error: unrecognized opcode `vfcvt.rtz.x.f.v v4,v8'
|
|
|
++.*: Error: unrecognized opcode `vfcvt.f.xu.v v4,v8'
|
|
|
++.*: Error: unrecognized opcode `vfcvt.f.x.v v4,v8'
|
|
|
++.*: Error: unrecognized opcode `vfcvt.xu.f.v v4,v8,v0.t'
|
|
|
++.*: Error: unrecognized opcode `vfcvt.x.f.v v4,v8,v0.t'
|
|
|
++.*: Error: unrecognized opcode `vfcvt.rtz.xu.f.v v4,v8,v0.t'
|
|
|
++.*: Error: unrecognized opcode `vfcvt.rtz.x.f.v v4,v8,v0.t'
|
|
|
++.*: Error: unrecognized opcode `vfcvt.f.xu.v v4,v8,v0.t'
|
|
|
++.*: Error: unrecognized opcode `vfcvt.f.x.v v4,v8,v0.t'
|
|
|
++.*: Error: unrecognized opcode `vfwcvt.xu.f.v v4,v8'
|
|
|
++.*: Error: unrecognized opcode `vfwcvt.x.f.v v4,v8'
|
|
|
++.*: Error: unrecognized opcode `vfwcvt.rtz.xu.f.v v4,v8'
|
|
|
++.*: Error: unrecognized opcode `vfwcvt.rtz.x.f.v v4,v8'
|
|
|
++.*: Error: unrecognized opcode `vfwcvt.f.xu.v v4,v8'
|
|
|
++.*: Error: unrecognized opcode `vfwcvt.f.x.v v4,v8'
|
|
|
++.*: Error: unrecognized opcode `vfwcvt.f.f.v v4,v8'
|
|
|
++.*: Error: unrecognized opcode `vfwcvt.xu.f.v v4,v8,v0.t'
|
|
|
++.*: Error: unrecognized opcode `vfwcvt.x.f.v v4,v8,v0.t'
|
|
|
++.*: Error: unrecognized opcode `vfwcvt.rtz.xu.f.v v4,v8,v0.t'
|
|
|
++.*: Error: unrecognized opcode `vfwcvt.rtz.x.f.v v4,v8,v0.t'
|
|
|
++.*: Error: unrecognized opcode `vfwcvt.f.xu.v v4,v8,v0.t'
|
|
|
++.*: Error: unrecognized opcode `vfwcvt.f.x.v v4,v8,v0.t'
|
|
|
++.*: Error: unrecognized opcode `vfwcvt.f.f.v v4,v8,v0.t'
|
|
|
++.*: Error: unrecognized opcode `vfncvt.xu.f.w v4,v8'
|
|
|
++.*: Error: unrecognized opcode `vfncvt.x.f.w v4,v8'
|
|
|
++.*: Error: unrecognized opcode `vfncvt.rtz.xu.f.w v4,v8'
|
|
|
++.*: Error: unrecognized opcode `vfncvt.rtz.x.f.w v4,v8'
|
|
|
++.*: Error: unrecognized opcode `vfncvt.f.xu.w v4,v8'
|
|
|
++.*: Error: unrecognized opcode `vfncvt.f.x.w v4,v8'
|
|
|
++.*: Error: unrecognized opcode `vfncvt.f.f.w v4,v8'
|
|
|
++.*: Error: unrecognized opcode `vfncvt.rod.f.f.w v4,v8'
|
|
|
++.*: Error: unrecognized opcode `vfncvt.xu.f.w v4,v8,v0.t'
|
|
|
++.*: Error: unrecognized opcode `vfncvt.x.f.w v4,v8,v0.t'
|
|
|
++.*: Error: unrecognized opcode `vfncvt.rtz.xu.f.w v4,v8,v0.t'
|
|
|
++.*: Error: unrecognized opcode `vfncvt.rtz.x.f.w v4,v8,v0.t'
|
|
|
++.*: Error: unrecognized opcode `vfncvt.f.xu.w v4,v8,v0.t'
|
|
|
++.*: Error: unrecognized opcode `vfncvt.f.x.w v4,v8,v0.t'
|
|
|
++.*: Error: unrecognized opcode `vfncvt.f.f.w v4,v8,v0.t'
|
|
|
++.*: Error: unrecognized opcode `vfncvt.rod.f.f.w v4,v8,v0.t'
|
|
|
++.*: Error: unrecognized opcode `vredsum.vs v4,v8,v12'
|
|
|
++.*: Error: unrecognized opcode `vredmaxu.vs v4,v8,v8'
|
|
|
++.*: Error: unrecognized opcode `vredmax.vs v4,v8,v8'
|
|
|
++.*: Error: unrecognized opcode `vredminu.vs v4,v8,v8'
|
|
|
++.*: Error: unrecognized opcode `vredmin.vs v4,v8,v8'
|
|
|
++.*: Error: unrecognized opcode `vredand.vs v4,v8,v12'
|
|
|
++.*: Error: unrecognized opcode `vredor.vs v4,v8,v12'
|
|
|
++.*: Error: unrecognized opcode `vredxor.vs v4,v8,v12'
|
|
|
++.*: Error: unrecognized opcode `vredsum.vs v4,v8,v12,v0.t'
|
|
|
++.*: Error: unrecognized opcode `vredmaxu.vs v4,v8,v8,v0.t'
|
|
|
++.*: Error: unrecognized opcode `vredmax.vs v4,v8,v8,v0.t'
|
|
|
++.*: Error: unrecognized opcode `vredminu.vs v4,v8,v8,v0.t'
|
|
|
++.*: Error: unrecognized opcode `vredmin.vs v4,v8,v8,v0.t'
|
|
|
++.*: Error: unrecognized opcode `vredand.vs v4,v8,v12,v0.t'
|
|
|
++.*: Error: unrecognized opcode `vredor.vs v4,v8,v12,v0.t'
|
|
|
++.*: Error: unrecognized opcode `vredxor.vs v4,v8,v12,v0.t'
|
|
|
++.*: Error: unrecognized opcode `vwredsumu.vs v4,v8,v12'
|
|
|
++.*: Error: unrecognized opcode `vwredsum.vs v4,v8,v12'
|
|
|
++.*: Error: unrecognized opcode `vwredsumu.vs v4,v8,v12,v0.t'
|
|
|
++.*: Error: unrecognized opcode `vwredsum.vs v4,v8,v12,v0.t'
|
|
|
++.*: Error: unrecognized opcode `vfredosum.vs v4,v8,v12'
|
|
|
++.*: Error: unrecognized opcode `vfredsum.vs v4,v8,v12'
|
|
|
++.*: Error: unrecognized opcode `vfredmax.vs v4,v8,v12'
|
|
|
++.*: Error: unrecognized opcode `vfredmin.vs v4,v8,v12'
|
|
|
++.*: Error: unrecognized opcode `vfredosum.vs v4,v8,v12,v0.t'
|
|
|
++.*: Error: unrecognized opcode `vfredsum.vs v4,v8,v12,v0.t'
|
|
|
++.*: Error: unrecognized opcode `vfredmax.vs v4,v8,v12,v0.t'
|
|
|
++.*: Error: unrecognized opcode `vfredmin.vs v4,v8,v12,v0.t'
|
|
|
++.*: Error: unrecognized opcode `vfwredosum.vs v4,v8,v12'
|
|
|
++.*: Error: unrecognized opcode `vfwredsum.vs v4,v8,v12'
|
|
|
++.*: Error: unrecognized opcode `vfwredosum.vs v4,v8,v12,v0.t'
|
|
|
++.*: Error: unrecognized opcode `vfwredsum.vs v4,v8,v12,v0.t'
|
|
|
++.*: Error: unrecognized opcode `vmsbf.m v4,v8'
|
|
|
++.*: Error: unrecognized opcode `vmsif.m v4,v8'
|
|
|
++.*: Error: unrecognized opcode `vmsof.m v4,v8'
|
|
|
++.*: Error: unrecognized opcode `viota.m v4,v8'
|
|
|
++.*: Error: unrecognized opcode `vid.v v4'
|
|
|
++.*: Error: unrecognized opcode `vmsbf.m v4,v8,v0.t'
|
|
|
++.*: Error: unrecognized opcode `vmsif.m v4,v8,v0.t'
|
|
|
++.*: Error: unrecognized opcode `vmsof.m v4,v8,v0.t'
|
|
|
++.*: Error: unrecognized opcode `viota.m v4,v8,v0.t'
|
|
|
++.*: Error: unrecognized opcode `vid.v v4,v0.t'
|
|
|
++.*: Error: unrecognized opcode `vrgatherei16.vv v4,v8,v12'
|
|
|
++.*: Error: unrecognized opcode `vrgatherei16.vv v4,v8,v12,v0.t'
|
|
|
++.*: Error: unrecognized opcode `vmv1r.v v1,v2'
|
|
|
++.*: Error: unrecognized opcode `vmv2r.v v2,v4'
|
|
|
++.*: Error: unrecognized opcode `vmv4r.v v4,v8'
|
|
|
++.*: Error: unrecognized opcode `vmv8r.v v0,v8'
|
|
|
+diff --git a/gas/testsuite/gas/riscv/vector-insns-fail-unsupport.s b/gas/testsuite/gas/riscv/vector-insns-fail-unsupport.s
|
|
|
+new file mode 100644
|
|
|
+index 0000000000..0116ac2c06
|
|
|
+--- /dev/null
|
|
|
++++ b/gas/testsuite/gas/riscv/vector-insns-fail-unsupport.s
|
|
|
+@@ -0,0 +1,1679 @@
|
|
|
++
|
|
|
++ vsetivli a0, 0xb, 0
|
|
|
++ vsetivli a0, 0xb, 0x3ff
|
|
|
++ vsetivli a0, 0xb, e16, m2
|
|
|
++ vsetivli a0, 0xb, e256, m8
|
|
|
++ vsetivli a0, 0xb, e512, m8
|
|
|
++ vsetivli a0, 0xb, e1024, m8
|
|
|
++ vsetivli a0, 0xb, e1024, m1
|
|
|
++ vsetivli a0, 0xb, e1024, mf2
|
|
|
++ vsetivli a0, 0xb, e512, mf4
|
|
|
++ vsetivli a0, 0xb, e256, mf8
|
|
|
++ vsetivli a0, 0xb, e256, m2, ta
|
|
|
++ vsetivli a0, 0xb, e256, m2, ma
|
|
|
++ vsetivli a0, 0xb, e256, m2, tu
|
|
|
++ vsetivli a0, 0xb, e256, m2, mu
|
|
|
++ vsetivli a0, 0xb, e256, m2, ta, ma
|
|
|
++ vsetivli a0, 0xb, e256, m2, tu, ma
|
|
|
++ vsetivli a0, 0xb, e256, m2, ta, mu
|
|
|
++ vsetivli a0, 0xb, e256, m2, tu, mu
|
|
|
++
|
|
|
++ vle1.v v4, (a0)
|
|
|
++ vle1.v v4, 0(a0)
|
|
|
++ vse1.v v4, (a0)
|
|
|
++ vse1.v v4, 0(a0)
|
|
|
++
|
|
|
++
|
|
|
++ vluxei8.v v4, (a0), v12
|
|
|
++ vluxei8.v v4, 0(a0), v12
|
|
|
++ vluxei8.v v4, (a0), v12, v0.t
|
|
|
++ vsuxei8.v v4, (a0), v12
|
|
|
++ vsuxei8.v v4, 0(a0), v12
|
|
|
++ vsuxei8.v v4, (a0), v12, v0.t
|
|
|
++
|
|
|
++
|
|
|
++ vluxei16.v v4, (a0), v12
|
|
|
++ vluxei16.v v4, 0(a0), v12
|
|
|
++ vluxei16.v v4, (a0), v12, v0.t
|
|
|
++ vsuxei16.v v4, (a0), v12
|
|
|
++ vsuxei16.v v4, 0(a0), v12
|
|
|
++ vsuxei16.v v4, (a0), v12, v0.t
|
|
|
++
|
|
|
++
|
|
|
++ vluxei32.v v4, (a0), v12
|
|
|
++ vluxei32.v v4, 0(a0), v12
|
|
|
++ vluxei32.v v4, (a0), v12, v0.t
|
|
|
++ vsuxei32.v v4, (a0), v12
|
|
|
++ vsuxei32.v v4, 0(a0), v12
|
|
|
++ vsuxei32.v v4, (a0), v12, v0.t
|
|
|
++
|
|
|
++
|
|
|
++ vluxei64.v v4, (a0), v12
|
|
|
++ vluxei64.v v4, 0(a0), v12
|
|
|
++ vluxei64.v v4, (a0), v12, v0.t
|
|
|
++ vsuxei64.v v4, (a0), v12
|
|
|
++ vsuxei64.v v4, 0(a0), v12
|
|
|
++ vsuxei64.v v4, (a0), v12, v0.t
|
|
|
++
|
|
|
++ vle8ff.v v4, (a0)
|
|
|
++ vle8ff.v v4, 0(a0)
|
|
|
++ vle8ff.v v4, (a0), v0.t
|
|
|
++
|
|
|
++ vle16ff.v v4, (a0)
|
|
|
++ vle16ff.v v4, 0(a0)
|
|
|
++ vle16ff.v v4, (a0), v0.t
|
|
|
++
|
|
|
++ vle32ff.v v4, (a0)
|
|
|
++ vle32ff.v v4, 0(a0)
|
|
|
++ vle32ff.v v4, (a0), v0.t
|
|
|
++
|
|
|
++ vle64ff.v v4, (a0)
|
|
|
++ vle64ff.v v4, 0(a0)
|
|
|
++ vle64ff.v v4, (a0), v0.t
|
|
|
++
|
|
|
++ vlseg2e8.v v4, (a0)
|
|
|
++ vlseg2e8.v v4, 0(a0)
|
|
|
++ vlseg2e8.v v4, (a0), v0.t
|
|
|
++ vsseg2e8.v v4, (a0)
|
|
|
++ vsseg2e8.v v4, 0(a0)
|
|
|
++ vsseg2e8.v v4, (a0), v0.t
|
|
|
++
|
|
|
++ vlseg3e8.v v4, (a0)
|
|
|
++ vlseg3e8.v v4, 0(a0)
|
|
|
++ vlseg3e8.v v4, (a0), v0.t
|
|
|
++ vsseg3e8.v v4, (a0)
|
|
|
++ vsseg3e8.v v4, 0(a0)
|
|
|
++ vsseg3e8.v v4, (a0), v0.t
|
|
|
++
|
|
|
++ vlseg4e8.v v4, (a0)
|
|
|
++ vlseg4e8.v v4, 0(a0)
|
|
|
++ vlseg4e8.v v4, (a0), v0.t
|
|
|
++ vsseg4e8.v v4, (a0)
|
|
|
++ vsseg4e8.v v4, 0(a0)
|
|
|
++ vsseg4e8.v v4, (a0), v0.t
|
|
|
++
|
|
|
++ vlseg5e8.v v4, (a0)
|
|
|
++ vlseg5e8.v v4, 0(a0)
|
|
|
++ vlseg5e8.v v4, (a0), v0.t
|
|
|
++ vsseg5e8.v v4, (a0)
|
|
|
++ vsseg5e8.v v4, 0(a0)
|
|
|
++ vsseg5e8.v v4, (a0), v0.t
|
|
|
++
|
|
|
++ vlseg6e8.v v4, (a0)
|
|
|
++ vlseg6e8.v v4, 0(a0)
|
|
|
++ vlseg6e8.v v4, (a0), v0.t
|
|
|
++ vsseg6e8.v v4, (a0)
|
|
|
++ vsseg6e8.v v4, 0(a0)
|
|
|
++ vsseg6e8.v v4, (a0), v0.t
|
|
|
++
|
|
|
++ vlseg7e8.v v4, (a0)
|
|
|
++ vlseg7e8.v v4, 0(a0)
|
|
|
++ vlseg7e8.v v4, (a0), v0.t
|
|
|
++ vsseg7e8.v v4, (a0)
|
|
|
++ vsseg7e8.v v4, 0(a0)
|
|
|
++ vsseg7e8.v v4, (a0), v0.t
|
|
|
++
|
|
|
++ vlseg8e8.v v4, (a0)
|
|
|
++ vlseg8e8.v v4, 0(a0)
|
|
|
++ vlseg8e8.v v4, (a0), v0.t
|
|
|
++ vsseg8e8.v v4, (a0)
|
|
|
++ vsseg8e8.v v4, 0(a0)
|
|
|
++ vsseg8e8.v v4, (a0), v0.t
|
|
|
++
|
|
|
++ vlseg2e16.v v4, (a0)
|
|
|
++ vlseg2e16.v v4, 0(a0)
|
|
|
++ vlseg2e16.v v4, (a0), v0.t
|
|
|
++ vsseg2e16.v v4, (a0)
|
|
|
++ vsseg2e16.v v4, 0(a0)
|
|
|
++ vsseg2e16.v v4, (a0), v0.t
|
|
|
++
|
|
|
++ vlseg3e16.v v4, (a0)
|
|
|
++ vlseg3e16.v v4, 0(a0)
|
|
|
++ vlseg3e16.v v4, (a0), v0.t
|
|
|
++ vsseg3e16.v v4, (a0)
|
|
|
++ vsseg3e16.v v4, 0(a0)
|
|
|
++ vsseg3e16.v v4, (a0), v0.t
|
|
|
++
|
|
|
++ vlseg4e16.v v4, (a0)
|
|
|
++ vlseg4e16.v v4, 0(a0)
|
|
|
++ vlseg4e16.v v4, (a0), v0.t
|
|
|
++ vsseg4e16.v v4, (a0)
|
|
|
++ vsseg4e16.v v4, 0(a0)
|
|
|
++ vsseg4e16.v v4, (a0), v0.t
|
|
|
++
|
|
|
++ vlseg5e16.v v4, (a0)
|
|
|
++ vlseg5e16.v v4, 0(a0)
|
|
|
++ vlseg5e16.v v4, (a0), v0.t
|
|
|
++ vsseg5e16.v v4, (a0)
|
|
|
++ vsseg5e16.v v4, 0(a0)
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++ vsseg5e16.v v4, (a0), v0.t
|
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++
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++ vlseg6e16.v v4, (a0)
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++ vlseg6e16.v v4, 0(a0)
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++ vlseg6e16.v v4, (a0), v0.t
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++ vsseg6e16.v v4, (a0)
|
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++ vsseg6e16.v v4, 0(a0)
|
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++ vsseg6e16.v v4, (a0), v0.t
|
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++
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++ vlseg7e16.v v4, (a0)
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++ vlseg7e16.v v4, 0(a0)
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++ vlseg7e16.v v4, (a0), v0.t
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++ vsseg7e16.v v4, (a0)
|
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++ vsseg7e16.v v4, 0(a0)
|
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++ vsseg7e16.v v4, (a0), v0.t
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++
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++ vlseg8e16.v v4, (a0)
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++ vlseg8e16.v v4, 0(a0)
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++ vlseg8e16.v v4, (a0), v0.t
|
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++ vsseg8e16.v v4, (a0)
|
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++ vsseg8e16.v v4, 0(a0)
|
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++ vsseg8e16.v v4, (a0), v0.t
|
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++
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++ vlseg2e32.v v4, (a0)
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++ vlseg2e32.v v4, 0(a0)
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++ vlseg2e32.v v4, (a0), v0.t
|
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++ vsseg2e32.v v4, (a0)
|
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++ vsseg2e32.v v4, 0(a0)
|
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++ vsseg2e32.v v4, (a0), v0.t
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++
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++ vlseg3e32.v v4, (a0)
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++ vlseg3e32.v v4, 0(a0)
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++ vlseg3e32.v v4, (a0), v0.t
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++ vsseg3e32.v v4, (a0)
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++ vsseg3e32.v v4, 0(a0)
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++ vsseg3e32.v v4, (a0), v0.t
|
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++
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++ vlseg4e32.v v4, (a0)
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++ vlseg4e32.v v4, 0(a0)
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++ vlseg4e32.v v4, (a0), v0.t
|
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++ vsseg4e32.v v4, (a0)
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++ vsseg4e32.v v4, 0(a0)
|
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++ vsseg4e32.v v4, (a0), v0.t
|
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++
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++ vlseg5e32.v v4, (a0)
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++ vlseg5e32.v v4, 0(a0)
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++ vlseg5e32.v v4, (a0), v0.t
|
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++ vsseg5e32.v v4, (a0)
|
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++ vsseg5e32.v v4, 0(a0)
|
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++ vsseg5e32.v v4, (a0), v0.t
|
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++
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++ vlseg6e32.v v4, (a0)
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++ vlseg6e32.v v4, 0(a0)
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++ vlseg6e32.v v4, (a0), v0.t
|
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++ vsseg6e32.v v4, (a0)
|
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++ vsseg6e32.v v4, 0(a0)
|
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++ vsseg6e32.v v4, (a0), v0.t
|
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++
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++ vlseg7e32.v v4, (a0)
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++ vlseg7e32.v v4, 0(a0)
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++ vlseg7e32.v v4, (a0), v0.t
|
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++ vsseg7e32.v v4, (a0)
|
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++ vsseg7e32.v v4, 0(a0)
|
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++ vsseg7e32.v v4, (a0), v0.t
|
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++
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++ vlseg8e32.v v4, (a0)
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++ vlseg8e32.v v4, 0(a0)
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++ vlseg8e32.v v4, (a0), v0.t
|
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++ vsseg8e32.v v4, (a0)
|
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++ vsseg8e32.v v4, 0(a0)
|
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++ vsseg8e32.v v4, (a0), v0.t
|
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++
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++ vlseg2e64.v v4, (a0)
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++ vlseg2e64.v v4, 0(a0)
|
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++ vlseg2e64.v v4, (a0), v0.t
|
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++ vsseg2e64.v v4, (a0)
|
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++ vsseg2e64.v v4, 0(a0)
|
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++ vsseg2e64.v v4, (a0), v0.t
|
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++
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++ vlseg3e64.v v4, (a0)
|
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++ vlseg3e64.v v4, 0(a0)
|
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++ vlseg3e64.v v4, (a0), v0.t
|
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++ vsseg3e64.v v4, (a0)
|
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++ vsseg3e64.v v4, 0(a0)
|
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++ vsseg3e64.v v4, (a0), v0.t
|
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++
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++ vlseg4e64.v v4, (a0)
|
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++ vlseg4e64.v v4, 0(a0)
|
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++ vlseg4e64.v v4, (a0), v0.t
|
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++ vsseg4e64.v v4, (a0)
|
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++ vsseg4e64.v v4, 0(a0)
|
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++ vsseg4e64.v v4, (a0), v0.t
|
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++
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++ vlseg5e64.v v4, (a0)
|
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++ vlseg5e64.v v4, 0(a0)
|
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++ vlseg5e64.v v4, (a0), v0.t
|
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++ vsseg5e64.v v4, (a0)
|
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++ vsseg5e64.v v4, 0(a0)
|
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++ vsseg5e64.v v4, (a0), v0.t
|
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++
|
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++ vlseg6e64.v v4, (a0)
|
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++ vlseg6e64.v v4, 0(a0)
|
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++ vlseg6e64.v v4, (a0), v0.t
|
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++ vsseg6e64.v v4, (a0)
|
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++ vsseg6e64.v v4, 0(a0)
|
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++ vsseg6e64.v v4, (a0), v0.t
|
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++
|
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++ vlseg7e64.v v4, (a0)
|
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++ vlseg7e64.v v4, 0(a0)
|
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++ vlseg7e64.v v4, (a0), v0.t
|
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++ vsseg7e64.v v4, (a0)
|
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++ vsseg7e64.v v4, 0(a0)
|
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++ vsseg7e64.v v4, (a0), v0.t
|
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++
|
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++ vlseg8e64.v v4, (a0)
|
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++ vlseg8e64.v v4, 0(a0)
|
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++ vlseg8e64.v v4, (a0), v0.t
|
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++ vsseg8e64.v v4, (a0)
|
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++ vsseg8e64.v v4, 0(a0)
|
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++ vsseg8e64.v v4, (a0), v0.t
|
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++
|
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++ vlsseg2e8.v v4, (a0), a1
|
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++ vlsseg2e8.v v4, 0(a0), a1
|
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++ vlsseg2e8.v v4, (a0), a1, v0.t
|
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++ vssseg2e8.v v4, (a0), a1
|
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++ vssseg2e8.v v4, 0(a0), a1
|
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++ vssseg2e8.v v4, (a0), a1, v0.t
|
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++
|
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++ vlsseg3e8.v v4, (a0), a1
|
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++ vlsseg3e8.v v4, 0(a0), a1
|
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++ vlsseg3e8.v v4, (a0), a1, v0.t
|
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++ vssseg3e8.v v4, (a0), a1
|
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++ vssseg3e8.v v4, 0(a0), a1
|
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++ vssseg3e8.v v4, (a0), a1, v0.t
|
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++
|
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++ vlsseg4e8.v v4, (a0), a1
|
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++ vlsseg4e8.v v4, 0(a0), a1
|
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++ vlsseg4e8.v v4, (a0), a1, v0.t
|
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++ vssseg4e8.v v4, (a0), a1
|
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++ vssseg4e8.v v4, 0(a0), a1
|
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++ vssseg4e8.v v4, (a0), a1, v0.t
|
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++
|
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++ vlsseg5e8.v v4, (a0), a1
|
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++ vlsseg5e8.v v4, 0(a0), a1
|
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++ vlsseg5e8.v v4, (a0), a1, v0.t
|
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++ vssseg5e8.v v4, (a0), a1
|
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++ vssseg5e8.v v4, 0(a0), a1
|
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++ vssseg5e8.v v4, (a0), a1, v0.t
|
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++
|
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++ vlsseg6e8.v v4, (a0), a1
|
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++ vlsseg6e8.v v4, 0(a0), a1
|
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++ vlsseg6e8.v v4, (a0), a1, v0.t
|
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++ vssseg6e8.v v4, (a0), a1
|
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++ vssseg6e8.v v4, 0(a0), a1
|
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++ vssseg6e8.v v4, (a0), a1, v0.t
|
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++
|
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++ vlsseg7e8.v v4, (a0), a1
|
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++ vlsseg7e8.v v4, 0(a0), a1
|
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++ vlsseg7e8.v v4, (a0), a1, v0.t
|
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++ vssseg7e8.v v4, (a0), a1
|
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++ vssseg7e8.v v4, 0(a0), a1
|
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++ vssseg7e8.v v4, (a0), a1, v0.t
|
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++
|
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++ vlsseg8e8.v v4, (a0), a1
|
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++ vlsseg8e8.v v4, 0(a0), a1
|
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++ vlsseg8e8.v v4, (a0), a1, v0.t
|
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++ vssseg8e8.v v4, (a0), a1
|
|
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++ vssseg8e8.v v4, 0(a0), a1
|
|
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++ vssseg8e8.v v4, (a0), a1, v0.t
|
|
|
++
|
|
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++ vlsseg2e16.v v4, (a0), a1
|
|
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++ vlsseg2e16.v v4, 0(a0), a1
|
|
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++ vlsseg2e16.v v4, (a0), a1, v0.t
|
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++ vssseg2e16.v v4, (a0), a1
|
|
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++ vssseg2e16.v v4, 0(a0), a1
|
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++ vssseg2e16.v v4, (a0), a1, v0.t
|
|
|
++
|
|
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++ vlsseg3e16.v v4, (a0), a1
|
|
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++ vlsseg3e16.v v4, 0(a0), a1
|
|
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++ vlsseg3e16.v v4, (a0), a1, v0.t
|
|
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++ vssseg3e16.v v4, (a0), a1
|
|
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++ vssseg3e16.v v4, 0(a0), a1
|
|
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++ vssseg3e16.v v4, (a0), a1, v0.t
|
|
|
++
|
|
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++ vlsseg4e16.v v4, (a0), a1
|
|
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++ vlsseg4e16.v v4, 0(a0), a1
|
|
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++ vlsseg4e16.v v4, (a0), a1, v0.t
|
|
|
++ vssseg4e16.v v4, (a0), a1
|
|
|
++ vssseg4e16.v v4, 0(a0), a1
|
|
|
++ vssseg4e16.v v4, (a0), a1, v0.t
|
|
|
++
|
|
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++ vlsseg5e16.v v4, (a0), a1
|
|
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++ vlsseg5e16.v v4, 0(a0), a1
|
|
|
++ vlsseg5e16.v v4, (a0), a1, v0.t
|
|
|
++ vssseg5e16.v v4, (a0), a1
|
|
|
++ vssseg5e16.v v4, 0(a0), a1
|
|
|
++ vssseg5e16.v v4, (a0), a1, v0.t
|
|
|
++
|
|
|
++ vlsseg6e16.v v4, (a0), a1
|
|
|
++ vlsseg6e16.v v4, 0(a0), a1
|
|
|
++ vlsseg6e16.v v4, (a0), a1, v0.t
|
|
|
++ vssseg6e16.v v4, (a0), a1
|
|
|
++ vssseg6e16.v v4, 0(a0), a1
|
|
|
++ vssseg6e16.v v4, (a0), a1, v0.t
|
|
|
++
|
|
|
++ vlsseg7e16.v v4, (a0), a1
|
|
|
++ vlsseg7e16.v v4, 0(a0), a1
|
|
|
++ vlsseg7e16.v v4, (a0), a1, v0.t
|
|
|
++ vssseg7e16.v v4, (a0), a1
|
|
|
++ vssseg7e16.v v4, 0(a0), a1
|
|
|
++ vssseg7e16.v v4, (a0), a1, v0.t
|
|
|
++
|
|
|
++ vlsseg8e16.v v4, (a0), a1
|
|
|
++ vlsseg8e16.v v4, 0(a0), a1
|
|
|
++ vlsseg8e16.v v4, (a0), a1, v0.t
|
|
|
++ vssseg8e16.v v4, (a0), a1
|
|
|
++ vssseg8e16.v v4, 0(a0), a1
|
|
|
++ vssseg8e16.v v4, (a0), a1, v0.t
|
|
|
++
|
|
|
++ vlsseg2e32.v v4, (a0), a1
|
|
|
++ vlsseg2e32.v v4, 0(a0), a1
|
|
|
++ vlsseg2e32.v v4, (a0), a1, v0.t
|
|
|
++ vssseg2e32.v v4, (a0), a1
|
|
|
++ vssseg2e32.v v4, 0(a0), a1
|
|
|
++ vssseg2e32.v v4, (a0), a1, v0.t
|
|
|
++
|
|
|
++ vlsseg3e32.v v4, (a0), a1
|
|
|
++ vlsseg3e32.v v4, 0(a0), a1
|
|
|
++ vlsseg3e32.v v4, (a0), a1, v0.t
|
|
|
++ vssseg3e32.v v4, (a0), a1
|
|
|
++ vssseg3e32.v v4, 0(a0), a1
|
|
|
++ vssseg3e32.v v4, (a0), a1, v0.t
|
|
|
++
|
|
|
++ vlsseg4e32.v v4, (a0), a1
|
|
|
++ vlsseg4e32.v v4, 0(a0), a1
|
|
|
++ vlsseg4e32.v v4, (a0), a1, v0.t
|
|
|
++ vssseg4e32.v v4, (a0), a1
|
|
|
++ vssseg4e32.v v4, 0(a0), a1
|
|
|
++ vssseg4e32.v v4, (a0), a1, v0.t
|
|
|
++
|
|
|
++ vlsseg5e32.v v4, (a0), a1
|
|
|
++ vlsseg5e32.v v4, 0(a0), a1
|
|
|
++ vlsseg5e32.v v4, (a0), a1, v0.t
|
|
|
++ vssseg5e32.v v4, (a0), a1
|
|
|
++ vssseg5e32.v v4, 0(a0), a1
|
|
|
++ vssseg5e32.v v4, (a0), a1, v0.t
|
|
|
++
|
|
|
++ vlsseg6e32.v v4, (a0), a1
|
|
|
++ vlsseg6e32.v v4, 0(a0), a1
|
|
|
++ vlsseg6e32.v v4, (a0), a1, v0.t
|
|
|
++ vssseg6e32.v v4, (a0), a1
|
|
|
++ vssseg6e32.v v4, 0(a0), a1
|
|
|
++ vssseg6e32.v v4, (a0), a1, v0.t
|
|
|
++
|
|
|
++ vlsseg7e32.v v4, (a0), a1
|
|
|
++ vlsseg7e32.v v4, 0(a0), a1
|
|
|
++ vlsseg7e32.v v4, (a0), a1, v0.t
|
|
|
++ vssseg7e32.v v4, (a0), a1
|
|
|
++ vssseg7e32.v v4, 0(a0), a1
|
|
|
++ vssseg7e32.v v4, (a0), a1, v0.t
|
|
|
++
|
|
|
++ vlsseg8e32.v v4, (a0), a1
|
|
|
++ vlsseg8e32.v v4, 0(a0), a1
|
|
|
++ vlsseg8e32.v v4, (a0), a1, v0.t
|
|
|
++ vssseg8e32.v v4, (a0), a1
|
|
|
++ vssseg8e32.v v4, 0(a0), a1
|
|
|
++ vssseg8e32.v v4, (a0), a1, v0.t
|
|
|
++
|
|
|
++ vlsseg2e64.v v4, (a0), a1
|
|
|
++ vlsseg2e64.v v4, 0(a0), a1
|
|
|
++ vlsseg2e64.v v4, (a0), a1, v0.t
|
|
|
++ vssseg2e64.v v4, (a0), a1
|
|
|
++ vssseg2e64.v v4, 0(a0), a1
|
|
|
++ vssseg2e64.v v4, (a0), a1, v0.t
|
|
|
++
|
|
|
++ vlsseg3e64.v v4, (a0), a1
|
|
|
++ vlsseg3e64.v v4, 0(a0), a1
|
|
|
++ vlsseg3e64.v v4, (a0), a1, v0.t
|
|
|
++ vssseg3e64.v v4, (a0), a1
|
|
|
++ vssseg3e64.v v4, 0(a0), a1
|
|
|
++ vssseg3e64.v v4, (a0), a1, v0.t
|
|
|
++
|
|
|
++ vlsseg4e64.v v4, (a0), a1
|
|
|
++ vlsseg4e64.v v4, 0(a0), a1
|
|
|
++ vlsseg4e64.v v4, (a0), a1, v0.t
|
|
|
++ vssseg4e64.v v4, (a0), a1
|
|
|
++ vssseg4e64.v v4, 0(a0), a1
|
|
|
++ vssseg4e64.v v4, (a0), a1, v0.t
|
|
|
++
|
|
|
++ vlsseg5e64.v v4, (a0), a1
|
|
|
++ vlsseg5e64.v v4, 0(a0), a1
|
|
|
++ vlsseg5e64.v v4, (a0), a1, v0.t
|
|
|
++ vssseg5e64.v v4, (a0), a1
|
|
|
++ vssseg5e64.v v4, 0(a0), a1
|
|
|
++ vssseg5e64.v v4, (a0), a1, v0.t
|
|
|
++
|
|
|
++ vlsseg6e64.v v4, (a0), a1
|
|
|
++ vlsseg6e64.v v4, 0(a0), a1
|
|
|
++ vlsseg6e64.v v4, (a0), a1, v0.t
|
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++ vssseg6e64.v v4, (a0), a1
|
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++ vssseg6e64.v v4, 0(a0), a1
|
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++ vssseg6e64.v v4, (a0), a1, v0.t
|
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++
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++ vlsseg7e64.v v4, (a0), a1
|
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++ vlsseg7e64.v v4, 0(a0), a1
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++ vlsseg7e64.v v4, (a0), a1, v0.t
|
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++ vssseg7e64.v v4, (a0), a1
|
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++ vssseg7e64.v v4, 0(a0), a1
|
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++ vssseg7e64.v v4, (a0), a1, v0.t
|
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++
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++ vlsseg8e64.v v4, (a0), a1
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++ vlsseg8e64.v v4, 0(a0), a1
|
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++ vlsseg8e64.v v4, (a0), a1, v0.t
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++ vssseg8e64.v v4, (a0), a1
|
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++ vssseg8e64.v v4, 0(a0), a1
|
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++ vssseg8e64.v v4, (a0), a1, v0.t
|
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++
|
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++ vloxseg2ei8.v v4, (a0), v12
|
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++ vloxseg2ei8.v v4, 0(a0), v12
|
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++ vloxseg2ei8.v v4, (a0), v12, v0.t
|
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++ vsoxseg2ei8.v v4, (a0), v12
|
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++ vsoxseg2ei8.v v4, 0(a0), v12
|
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++ vsoxseg2ei8.v v4, (a0), v12, v0.t
|
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++
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++ vloxseg3ei8.v v4, (a0), v12
|
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++ vloxseg3ei8.v v4, 0(a0), v12
|
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++ vloxseg3ei8.v v4, (a0), v12, v0.t
|
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++ vsoxseg3ei8.v v4, (a0), v12
|
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++ vsoxseg3ei8.v v4, 0(a0), v12
|
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++ vsoxseg3ei8.v v4, (a0), v12, v0.t
|
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++
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++ vloxseg4ei8.v v4, (a0), v12
|
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++ vloxseg4ei8.v v4, 0(a0), v12
|
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++ vloxseg4ei8.v v4, (a0), v12, v0.t
|
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++ vsoxseg4ei8.v v4, (a0), v12
|
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++ vsoxseg4ei8.v v4, 0(a0), v12
|
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++ vsoxseg4ei8.v v4, (a0), v12, v0.t
|
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++
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++ vloxseg5ei8.v v4, (a0), v12
|
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++ vloxseg5ei8.v v4, 0(a0), v12
|
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++ vloxseg5ei8.v v4, (a0), v12, v0.t
|
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++ vsoxseg5ei8.v v4, (a0), v12
|
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++ vsoxseg5ei8.v v4, 0(a0), v12
|
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++ vsoxseg5ei8.v v4, (a0), v12, v0.t
|
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++
|
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++ vloxseg6ei8.v v4, (a0), v12
|
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++ vloxseg6ei8.v v4, 0(a0), v12
|
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++ vloxseg6ei8.v v4, (a0), v12, v0.t
|
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++ vsoxseg6ei8.v v4, (a0), v12
|
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++ vsoxseg6ei8.v v4, 0(a0), v12
|
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++ vsoxseg6ei8.v v4, (a0), v12, v0.t
|
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++
|
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++ vloxseg7ei8.v v4, (a0), v12
|
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++ vloxseg7ei8.v v4, 0(a0), v12
|
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++ vloxseg7ei8.v v4, (a0), v12, v0.t
|
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++ vsoxseg7ei8.v v4, (a0), v12
|
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++ vsoxseg7ei8.v v4, 0(a0), v12
|
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++ vsoxseg7ei8.v v4, (a0), v12, v0.t
|
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++
|
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++ vloxseg8ei8.v v4, (a0), v12
|
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++ vloxseg8ei8.v v4, 0(a0), v12
|
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++ vloxseg8ei8.v v4, (a0), v12, v0.t
|
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++ vsoxseg8ei8.v v4, (a0), v12
|
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++ vsoxseg8ei8.v v4, 0(a0), v12
|
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++ vsoxseg8ei8.v v4, (a0), v12, v0.t
|
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++
|
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++ vloxseg2ei16.v v4, (a0), v12
|
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++ vloxseg2ei16.v v4, 0(a0), v12
|
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++ vloxseg2ei16.v v4, (a0), v12, v0.t
|
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++ vsoxseg2ei16.v v4, (a0), v12
|
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++ vsoxseg2ei16.v v4, 0(a0), v12
|
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++ vsoxseg2ei16.v v4, (a0), v12, v0.t
|
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++
|
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++ vloxseg3ei16.v v4, (a0), v12
|
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++ vloxseg3ei16.v v4, 0(a0), v12
|
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++ vloxseg3ei16.v v4, (a0), v12, v0.t
|
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++ vsoxseg3ei16.v v4, (a0), v12
|
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++ vsoxseg3ei16.v v4, 0(a0), v12
|
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++ vsoxseg3ei16.v v4, (a0), v12, v0.t
|
|
|
++
|
|
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++ vloxseg4ei16.v v4, (a0), v12
|
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++ vloxseg4ei16.v v4, 0(a0), v12
|
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++ vloxseg4ei16.v v4, (a0), v12, v0.t
|
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++ vsoxseg4ei16.v v4, (a0), v12
|
|
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++ vsoxseg4ei16.v v4, 0(a0), v12
|
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++ vsoxseg4ei16.v v4, (a0), v12, v0.t
|
|
|
++
|
|
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++ vloxseg5ei16.v v4, (a0), v12
|
|
|
++ vloxseg5ei16.v v4, 0(a0), v12
|
|
|
++ vloxseg5ei16.v v4, (a0), v12, v0.t
|
|
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++ vsoxseg5ei16.v v4, (a0), v12
|
|
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++ vsoxseg5ei16.v v4, 0(a0), v12
|
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++ vsoxseg5ei16.v v4, (a0), v12, v0.t
|
|
|
++
|
|
|
++ vloxseg6ei16.v v4, (a0), v12
|
|
|
++ vloxseg6ei16.v v4, 0(a0), v12
|
|
|
++ vloxseg6ei16.v v4, (a0), v12, v0.t
|
|
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++ vsoxseg6ei16.v v4, (a0), v12
|
|
|
++ vsoxseg6ei16.v v4, 0(a0), v12
|
|
|
++ vsoxseg6ei16.v v4, (a0), v12, v0.t
|
|
|
++
|
|
|
++ vloxseg7ei16.v v4, (a0), v12
|
|
|
++ vloxseg7ei16.v v4, 0(a0), v12
|
|
|
++ vloxseg7ei16.v v4, (a0), v12, v0.t
|
|
|
++ vsoxseg7ei16.v v4, (a0), v12
|
|
|
++ vsoxseg7ei16.v v4, 0(a0), v12
|
|
|
++ vsoxseg7ei16.v v4, (a0), v12, v0.t
|
|
|
++
|
|
|
++ vloxseg8ei16.v v4, (a0), v12
|
|
|
++ vloxseg8ei16.v v4, 0(a0), v12
|
|
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++ vloxseg8ei16.v v4, (a0), v12, v0.t
|
|
|
++ vsoxseg8ei16.v v4, (a0), v12
|
|
|
++ vsoxseg8ei16.v v4, 0(a0), v12
|
|
|
++ vsoxseg8ei16.v v4, (a0), v12, v0.t
|
|
|
++
|
|
|
++ vloxseg2ei32.v v4, (a0), v12
|
|
|
++ vloxseg2ei32.v v4, 0(a0), v12
|
|
|
++ vloxseg2ei32.v v4, (a0), v12, v0.t
|
|
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++ vsoxseg2ei32.v v4, (a0), v12
|
|
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++ vsoxseg2ei32.v v4, 0(a0), v12
|
|
|
++ vsoxseg2ei32.v v4, (a0), v12, v0.t
|
|
|
++
|
|
|
++ vloxseg3ei32.v v4, (a0), v12
|
|
|
++ vloxseg3ei32.v v4, 0(a0), v12
|
|
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++ vloxseg3ei32.v v4, (a0), v12, v0.t
|
|
|
++ vsoxseg3ei32.v v4, (a0), v12
|
|
|
++ vsoxseg3ei32.v v4, 0(a0), v12
|
|
|
++ vsoxseg3ei32.v v4, (a0), v12, v0.t
|
|
|
++
|
|
|
++ vloxseg4ei32.v v4, (a0), v12
|
|
|
++ vloxseg4ei32.v v4, 0(a0), v12
|
|
|
++ vloxseg4ei32.v v4, (a0), v12, v0.t
|
|
|
++ vsoxseg4ei32.v v4, (a0), v12
|
|
|
++ vsoxseg4ei32.v v4, 0(a0), v12
|
|
|
++ vsoxseg4ei32.v v4, (a0), v12, v0.t
|
|
|
++
|
|
|
++ vloxseg5ei32.v v4, (a0), v12
|
|
|
++ vloxseg5ei32.v v4, 0(a0), v12
|
|
|
++ vloxseg5ei32.v v4, (a0), v12, v0.t
|
|
|
++ vsoxseg5ei32.v v4, (a0), v12
|
|
|
++ vsoxseg5ei32.v v4, 0(a0), v12
|
|
|
++ vsoxseg5ei32.v v4, (a0), v12, v0.t
|
|
|
++
|
|
|
++ vloxseg6ei32.v v4, (a0), v12
|
|
|
++ vloxseg6ei32.v v4, 0(a0), v12
|
|
|
++ vloxseg6ei32.v v4, (a0), v12, v0.t
|
|
|
++ vsoxseg6ei32.v v4, (a0), v12
|
|
|
++ vsoxseg6ei32.v v4, 0(a0), v12
|
|
|
++ vsoxseg6ei32.v v4, (a0), v12, v0.t
|
|
|
++
|
|
|
++ vloxseg7ei32.v v4, (a0), v12
|
|
|
++ vloxseg7ei32.v v4, 0(a0), v12
|
|
|
++ vloxseg7ei32.v v4, (a0), v12, v0.t
|
|
|
++ vsoxseg7ei32.v v4, (a0), v12
|
|
|
++ vsoxseg7ei32.v v4, 0(a0), v12
|
|
|
++ vsoxseg7ei32.v v4, (a0), v12, v0.t
|
|
|
++
|
|
|
++ vloxseg8ei32.v v4, (a0), v12
|
|
|
++ vloxseg8ei32.v v4, 0(a0), v12
|
|
|
++ vloxseg8ei32.v v4, (a0), v12, v0.t
|
|
|
++ vsoxseg8ei32.v v4, (a0), v12
|
|
|
++ vsoxseg8ei32.v v4, 0(a0), v12
|
|
|
++ vsoxseg8ei32.v v4, (a0), v12, v0.t
|
|
|
++
|
|
|
++ vloxseg2ei64.v v4, (a0), v12
|
|
|
++ vloxseg2ei64.v v4, 0(a0), v12
|
|
|
++ vloxseg2ei64.v v4, (a0), v12, v0.t
|
|
|
++ vsoxseg2ei64.v v4, (a0), v12
|
|
|
++ vsoxseg2ei64.v v4, 0(a0), v12
|
|
|
++ vsoxseg2ei64.v v4, (a0), v12, v0.t
|
|
|
++
|
|
|
++ vloxseg3ei64.v v4, (a0), v12
|
|
|
++ vloxseg3ei64.v v4, 0(a0), v12
|
|
|
++ vloxseg3ei64.v v4, (a0), v12, v0.t
|
|
|
++ vsoxseg3ei64.v v4, (a0), v12
|
|
|
++ vsoxseg3ei64.v v4, 0(a0), v12
|
|
|
++ vsoxseg3ei64.v v4, (a0), v12, v0.t
|
|
|
++
|
|
|
++ vloxseg4ei64.v v4, (a0), v12
|
|
|
++ vloxseg4ei64.v v4, 0(a0), v12
|
|
|
++ vloxseg4ei64.v v4, (a0), v12, v0.t
|
|
|
++ vsoxseg4ei64.v v4, (a0), v12
|
|
|
++ vsoxseg4ei64.v v4, 0(a0), v12
|
|
|
++ vsoxseg4ei64.v v4, (a0), v12, v0.t
|
|
|
++
|
|
|
++ vloxseg5ei64.v v4, (a0), v12
|
|
|
++ vloxseg5ei64.v v4, 0(a0), v12
|
|
|
++ vloxseg5ei64.v v4, (a0), v12, v0.t
|
|
|
++ vsoxseg5ei64.v v4, (a0), v12
|
|
|
++ vsoxseg5ei64.v v4, 0(a0), v12
|
|
|
++ vsoxseg5ei64.v v4, (a0), v12, v0.t
|
|
|
++
|
|
|
++ vloxseg6ei64.v v4, (a0), v12
|
|
|
++ vloxseg6ei64.v v4, 0(a0), v12
|
|
|
++ vloxseg6ei64.v v4, (a0), v12, v0.t
|
|
|
++ vsoxseg6ei64.v v4, (a0), v12
|
|
|
++ vsoxseg6ei64.v v4, 0(a0), v12
|
|
|
++ vsoxseg6ei64.v v4, (a0), v12, v0.t
|
|
|
++
|
|
|
++ vloxseg7ei64.v v4, (a0), v12
|
|
|
++ vloxseg7ei64.v v4, 0(a0), v12
|
|
|
++ vloxseg7ei64.v v4, (a0), v12, v0.t
|
|
|
++ vsoxseg7ei64.v v4, (a0), v12
|
|
|
++ vsoxseg7ei64.v v4, 0(a0), v12
|
|
|
++ vsoxseg7ei64.v v4, (a0), v12, v0.t
|
|
|
++
|
|
|
++ vloxseg8ei64.v v4, (a0), v12
|
|
|
++ vloxseg8ei64.v v4, 0(a0), v12
|
|
|
++ vloxseg8ei64.v v4, (a0), v12, v0.t
|
|
|
++ vsoxseg8ei64.v v4, (a0), v12
|
|
|
++ vsoxseg8ei64.v v4, 0(a0), v12
|
|
|
++ vsoxseg8ei64.v v4, (a0), v12, v0.t
|
|
|
++
|
|
|
++ vluxseg2ei8.v v4, (a0), v12
|
|
|
++ vluxseg2ei8.v v4, 0(a0), v12
|
|
|
++ vluxseg2ei8.v v4, (a0), v12, v0.t
|
|
|
++ vsuxseg2ei8.v v4, (a0), v12
|
|
|
++ vsuxseg2ei8.v v4, 0(a0), v12
|
|
|
++ vsuxseg2ei8.v v4, (a0), v12, v0.t
|
|
|
++
|
|
|
++ vluxseg3ei8.v v4, (a0), v12
|
|
|
++ vluxseg3ei8.v v4, 0(a0), v12
|
|
|
++ vluxseg3ei8.v v4, (a0), v12, v0.t
|
|
|
++ vsuxseg3ei8.v v4, (a0), v12
|
|
|
++ vsuxseg3ei8.v v4, 0(a0), v12
|
|
|
++ vsuxseg3ei8.v v4, (a0), v12, v0.t
|
|
|
++
|
|
|
++ vluxseg4ei8.v v4, (a0), v12
|
|
|
++ vluxseg4ei8.v v4, 0(a0), v12
|
|
|
++ vluxseg4ei8.v v4, (a0), v12, v0.t
|
|
|
++ vsuxseg4ei8.v v4, (a0), v12
|
|
|
++ vsuxseg4ei8.v v4, 0(a0), v12
|
|
|
++ vsuxseg4ei8.v v4, (a0), v12, v0.t
|
|
|
++
|
|
|
++ vluxseg5ei8.v v4, (a0), v12
|
|
|
++ vluxseg5ei8.v v4, 0(a0), v12
|
|
|
++ vluxseg5ei8.v v4, (a0), v12, v0.t
|
|
|
++ vsuxseg5ei8.v v4, (a0), v12
|
|
|
++ vsuxseg5ei8.v v4, 0(a0), v12
|
|
|
++ vsuxseg5ei8.v v4, (a0), v12, v0.t
|
|
|
++
|
|
|
++ vluxseg6ei8.v v4, (a0), v12
|
|
|
++ vluxseg6ei8.v v4, 0(a0), v12
|
|
|
++ vluxseg6ei8.v v4, (a0), v12, v0.t
|
|
|
++ vsuxseg6ei8.v v4, (a0), v12
|
|
|
++ vsuxseg6ei8.v v4, 0(a0), v12
|
|
|
++ vsuxseg6ei8.v v4, (a0), v12, v0.t
|
|
|
++
|
|
|
++ vluxseg7ei8.v v4, (a0), v12
|
|
|
++ vluxseg7ei8.v v4, 0(a0), v12
|
|
|
++ vluxseg7ei8.v v4, (a0), v12, v0.t
|
|
|
++ vsuxseg7ei8.v v4, (a0), v12
|
|
|
++ vsuxseg7ei8.v v4, 0(a0), v12
|
|
|
++ vsuxseg7ei8.v v4, (a0), v12, v0.t
|
|
|
++
|
|
|
++ vluxseg8ei8.v v4, (a0), v12
|
|
|
++ vluxseg8ei8.v v4, 0(a0), v12
|
|
|
++ vluxseg8ei8.v v4, (a0), v12, v0.t
|
|
|
++ vsuxseg8ei8.v v4, (a0), v12
|
|
|
++ vsuxseg8ei8.v v4, 0(a0), v12
|
|
|
++ vsuxseg8ei8.v v4, (a0), v12, v0.t
|
|
|
++
|
|
|
++ vluxseg2ei16.v v4, (a0), v12
|
|
|
++ vluxseg2ei16.v v4, 0(a0), v12
|
|
|
++ vluxseg2ei16.v v4, (a0), v12, v0.t
|
|
|
++ vsuxseg2ei16.v v4, (a0), v12
|
|
|
++ vsuxseg2ei16.v v4, 0(a0), v12
|
|
|
++ vsuxseg2ei16.v v4, (a0), v12, v0.t
|
|
|
++
|
|
|
++ vluxseg3ei16.v v4, (a0), v12
|
|
|
++ vluxseg3ei16.v v4, 0(a0), v12
|
|
|
++ vluxseg3ei16.v v4, (a0), v12, v0.t
|
|
|
++ vsuxseg3ei16.v v4, (a0), v12
|
|
|
++ vsuxseg3ei16.v v4, 0(a0), v12
|
|
|
++ vsuxseg3ei16.v v4, (a0), v12, v0.t
|
|
|
++
|
|
|
++ vluxseg4ei16.v v4, (a0), v12
|
|
|
++ vluxseg4ei16.v v4, 0(a0), v12
|
|
|
++ vluxseg4ei16.v v4, (a0), v12, v0.t
|
|
|
++ vsuxseg4ei16.v v4, (a0), v12
|
|
|
++ vsuxseg4ei16.v v4, 0(a0), v12
|
|
|
++ vsuxseg4ei16.v v4, (a0), v12, v0.t
|
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++
|
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++ vluxseg5ei16.v v4, (a0), v12
|
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++ vluxseg5ei16.v v4, 0(a0), v12
|
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++ vluxseg5ei16.v v4, (a0), v12, v0.t
|
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++ vsuxseg5ei16.v v4, (a0), v12
|
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++ vsuxseg5ei16.v v4, 0(a0), v12
|
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++ vsuxseg5ei16.v v4, (a0), v12, v0.t
|
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++
|
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++ vluxseg6ei16.v v4, (a0), v12
|
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++ vluxseg6ei16.v v4, 0(a0), v12
|
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++ vluxseg6ei16.v v4, (a0), v12, v0.t
|
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++ vsuxseg6ei16.v v4, (a0), v12
|
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++ vsuxseg6ei16.v v4, 0(a0), v12
|
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++ vsuxseg6ei16.v v4, (a0), v12, v0.t
|
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++
|
|
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++ vluxseg7ei16.v v4, (a0), v12
|
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++ vluxseg7ei16.v v4, 0(a0), v12
|
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++ vluxseg7ei16.v v4, (a0), v12, v0.t
|
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++ vsuxseg7ei16.v v4, (a0), v12
|
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++ vsuxseg7ei16.v v4, 0(a0), v12
|
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++ vsuxseg7ei16.v v4, (a0), v12, v0.t
|
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++
|
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++ vluxseg8ei16.v v4, (a0), v12
|
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++ vluxseg8ei16.v v4, 0(a0), v12
|
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++ vluxseg8ei16.v v4, (a0), v12, v0.t
|
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++ vsuxseg8ei16.v v4, (a0), v12
|
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++ vsuxseg8ei16.v v4, 0(a0), v12
|
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++ vsuxseg8ei16.v v4, (a0), v12, v0.t
|
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++
|
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++ vluxseg2ei32.v v4, (a0), v12
|
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++ vluxseg2ei32.v v4, 0(a0), v12
|
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++ vluxseg2ei32.v v4, (a0), v12, v0.t
|
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++ vsuxseg2ei32.v v4, (a0), v12
|
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++ vsuxseg2ei32.v v4, 0(a0), v12
|
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++ vsuxseg2ei32.v v4, (a0), v12, v0.t
|
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|
++
|
|
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++ vluxseg3ei32.v v4, (a0), v12
|
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++ vluxseg3ei32.v v4, 0(a0), v12
|
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++ vluxseg3ei32.v v4, (a0), v12, v0.t
|
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++ vsuxseg3ei32.v v4, (a0), v12
|
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++ vsuxseg3ei32.v v4, 0(a0), v12
|
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++ vsuxseg3ei32.v v4, (a0), v12, v0.t
|
|
|
++
|
|
|
++ vluxseg4ei32.v v4, (a0), v12
|
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++ vluxseg4ei32.v v4, 0(a0), v12
|
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|
++ vluxseg4ei32.v v4, (a0), v12, v0.t
|
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|
++ vsuxseg4ei32.v v4, (a0), v12
|
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|
++ vsuxseg4ei32.v v4, 0(a0), v12
|
|
|
++ vsuxseg4ei32.v v4, (a0), v12, v0.t
|
|
|
++
|
|
|
++ vluxseg5ei32.v v4, (a0), v12
|
|
|
++ vluxseg5ei32.v v4, 0(a0), v12
|
|
|
++ vluxseg5ei32.v v4, (a0), v12, v0.t
|
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|
++ vsuxseg5ei32.v v4, (a0), v12
|
|
|
++ vsuxseg5ei32.v v4, 0(a0), v12
|
|
|
++ vsuxseg5ei32.v v4, (a0), v12, v0.t
|
|
|
++
|
|
|
++ vluxseg6ei32.v v4, (a0), v12
|
|
|
++ vluxseg6ei32.v v4, 0(a0), v12
|
|
|
++ vluxseg6ei32.v v4, (a0), v12, v0.t
|
|
|
++ vsuxseg6ei32.v v4, (a0), v12
|
|
|
++ vsuxseg6ei32.v v4, 0(a0), v12
|
|
|
++ vsuxseg6ei32.v v4, (a0), v12, v0.t
|
|
|
++
|
|
|
++ vluxseg7ei32.v v4, (a0), v12
|
|
|
++ vluxseg7ei32.v v4, 0(a0), v12
|
|
|
++ vluxseg7ei32.v v4, (a0), v12, v0.t
|
|
|
++ vsuxseg7ei32.v v4, (a0), v12
|
|
|
++ vsuxseg7ei32.v v4, 0(a0), v12
|
|
|
++ vsuxseg7ei32.v v4, (a0), v12, v0.t
|
|
|
++
|
|
|
++ vluxseg8ei32.v v4, (a0), v12
|
|
|
++ vluxseg8ei32.v v4, 0(a0), v12
|
|
|
++ vluxseg8ei32.v v4, (a0), v12, v0.t
|
|
|
++ vsuxseg8ei32.v v4, (a0), v12
|
|
|
++ vsuxseg8ei32.v v4, 0(a0), v12
|
|
|
++ vsuxseg8ei32.v v4, (a0), v12, v0.t
|
|
|
++
|
|
|
++ vluxseg2ei64.v v4, (a0), v12
|
|
|
++ vluxseg2ei64.v v4, 0(a0), v12
|
|
|
++ vluxseg2ei64.v v4, (a0), v12, v0.t
|
|
|
++ vsuxseg2ei64.v v4, (a0), v12
|
|
|
++ vsuxseg2ei64.v v4, 0(a0), v12
|
|
|
++ vsuxseg2ei64.v v4, (a0), v12, v0.t
|
|
|
++
|
|
|
++ vluxseg3ei64.v v4, (a0), v12
|
|
|
++ vluxseg3ei64.v v4, 0(a0), v12
|
|
|
++ vluxseg3ei64.v v4, (a0), v12, v0.t
|
|
|
++ vsuxseg3ei64.v v4, (a0), v12
|
|
|
++ vsuxseg3ei64.v v4, 0(a0), v12
|
|
|
++ vsuxseg3ei64.v v4, (a0), v12, v0.t
|
|
|
++
|
|
|
++ vluxseg4ei64.v v4, (a0), v12
|
|
|
++ vluxseg4ei64.v v4, 0(a0), v12
|
|
|
++ vluxseg4ei64.v v4, (a0), v12, v0.t
|
|
|
++ vsuxseg4ei64.v v4, (a0), v12
|
|
|
++ vsuxseg4ei64.v v4, 0(a0), v12
|
|
|
++ vsuxseg4ei64.v v4, (a0), v12, v0.t
|
|
|
++
|
|
|
++ vluxseg5ei64.v v4, (a0), v12
|
|
|
++ vluxseg5ei64.v v4, 0(a0), v12
|
|
|
++ vluxseg5ei64.v v4, (a0), v12, v0.t
|
|
|
++ vsuxseg5ei64.v v4, (a0), v12
|
|
|
++ vsuxseg5ei64.v v4, 0(a0), v12
|
|
|
++ vsuxseg5ei64.v v4, (a0), v12, v0.t
|
|
|
++
|
|
|
++ vluxseg6ei64.v v4, (a0), v12
|
|
|
++ vluxseg6ei64.v v4, 0(a0), v12
|
|
|
++ vluxseg6ei64.v v4, (a0), v12, v0.t
|
|
|
++ vsuxseg6ei64.v v4, (a0), v12
|
|
|
++ vsuxseg6ei64.v v4, 0(a0), v12
|
|
|
++ vsuxseg6ei64.v v4, (a0), v12, v0.t
|
|
|
++
|
|
|
++ vluxseg7ei64.v v4, (a0), v12
|
|
|
++ vluxseg7ei64.v v4, 0(a0), v12
|
|
|
++ vluxseg7ei64.v v4, (a0), v12, v0.t
|
|
|
++ vsuxseg7ei64.v v4, (a0), v12
|
|
|
++ vsuxseg7ei64.v v4, 0(a0), v12
|
|
|
++ vsuxseg7ei64.v v4, (a0), v12, v0.t
|
|
|
++
|
|
|
++ vluxseg8ei64.v v4, (a0), v12
|
|
|
++ vluxseg8ei64.v v4, 0(a0), v12
|
|
|
++ vluxseg8ei64.v v4, (a0), v12, v0.t
|
|
|
++ vsuxseg8ei64.v v4, (a0), v12
|
|
|
++ vsuxseg8ei64.v v4, 0(a0), v12
|
|
|
++ vsuxseg8ei64.v v4, (a0), v12, v0.t
|
|
|
++
|
|
|
++ vlseg2e8ff.v v4, (a0)
|
|
|
++ vlseg2e8ff.v v4, 0(a0)
|
|
|
++ vlseg2e8ff.v v4, (a0), v0.t
|
|
|
++
|
|
|
++ vlseg3e8ff.v v4, (a0)
|
|
|
++ vlseg3e8ff.v v4, 0(a0)
|
|
|
++ vlseg3e8ff.v v4, (a0), v0.t
|
|
|
++
|
|
|
++ vlseg4e8ff.v v4, (a0)
|
|
|
++ vlseg4e8ff.v v4, 0(a0)
|
|
|
++ vlseg4e8ff.v v4, (a0), v0.t
|
|
|
++
|
|
|
++ vlseg5e8ff.v v4, (a0)
|
|
|
++ vlseg5e8ff.v v4, 0(a0)
|
|
|
++ vlseg5e8ff.v v4, (a0), v0.t
|
|
|
++
|
|
|
++ vlseg6e8ff.v v4, (a0)
|
|
|
++ vlseg6e8ff.v v4, 0(a0)
|
|
|
++ vlseg6e8ff.v v4, (a0), v0.t
|
|
|
++
|
|
|
++ vlseg7e8ff.v v4, (a0)
|
|
|
++ vlseg7e8ff.v v4, 0(a0)
|
|
|
++ vlseg7e8ff.v v4, (a0), v0.t
|
|
|
++
|
|
|
++ vlseg8e8ff.v v4, (a0)
|
|
|
++ vlseg8e8ff.v v4, 0(a0)
|
|
|
++ vlseg8e8ff.v v4, (a0), v0.t
|
|
|
++
|
|
|
++ vlseg2e16ff.v v4, (a0)
|
|
|
++ vlseg2e16ff.v v4, 0(a0)
|
|
|
++ vlseg2e16ff.v v4, (a0), v0.t
|
|
|
++
|
|
|
++ vlseg3e16ff.v v4, (a0)
|
|
|
++ vlseg3e16ff.v v4, 0(a0)
|
|
|
++ vlseg3e16ff.v v4, (a0), v0.t
|
|
|
++
|
|
|
++ vlseg4e16ff.v v4, (a0)
|
|
|
++ vlseg4e16ff.v v4, 0(a0)
|
|
|
++ vlseg4e16ff.v v4, (a0), v0.t
|
|
|
++
|
|
|
++ vlseg5e16ff.v v4, (a0)
|
|
|
++ vlseg5e16ff.v v4, 0(a0)
|
|
|
++ vlseg5e16ff.v v4, (a0), v0.t
|
|
|
++
|
|
|
++ vlseg6e16ff.v v4, (a0)
|
|
|
++ vlseg6e16ff.v v4, 0(a0)
|
|
|
++ vlseg6e16ff.v v4, (a0), v0.t
|
|
|
++
|
|
|
++ vlseg7e16ff.v v4, (a0)
|
|
|
++ vlseg7e16ff.v v4, 0(a0)
|
|
|
++ vlseg7e16ff.v v4, (a0), v0.t
|
|
|
++
|
|
|
++ vlseg8e16ff.v v4, (a0)
|
|
|
++ vlseg8e16ff.v v4, 0(a0)
|
|
|
++ vlseg8e16ff.v v4, (a0), v0.t
|
|
|
++
|
|
|
++ vlseg2e32ff.v v4, (a0)
|
|
|
++ vlseg2e32ff.v v4, 0(a0)
|
|
|
++ vlseg2e32ff.v v4, (a0), v0.t
|
|
|
++
|
|
|
++ vlseg3e32ff.v v4, (a0)
|
|
|
++ vlseg3e32ff.v v4, 0(a0)
|
|
|
++ vlseg3e32ff.v v4, (a0), v0.t
|
|
|
++
|
|
|
++ vlseg4e32ff.v v4, (a0)
|
|
|
++ vlseg4e32ff.v v4, 0(a0)
|
|
|
++ vlseg4e32ff.v v4, (a0), v0.t
|
|
|
++
|
|
|
++ vlseg5e32ff.v v4, (a0)
|
|
|
++ vlseg5e32ff.v v4, 0(a0)
|
|
|
++ vlseg5e32ff.v v4, (a0), v0.t
|
|
|
++
|
|
|
++ vlseg6e32ff.v v4, (a0)
|
|
|
++ vlseg6e32ff.v v4, 0(a0)
|
|
|
++ vlseg6e32ff.v v4, (a0), v0.t
|
|
|
++
|
|
|
++ vlseg7e32ff.v v4, (a0)
|
|
|
++ vlseg7e32ff.v v4, 0(a0)
|
|
|
++ vlseg7e32ff.v v4, (a0), v0.t
|
|
|
++
|
|
|
++ vlseg8e32ff.v v4, (a0)
|
|
|
++ vlseg8e32ff.v v4, 0(a0)
|
|
|
++ vlseg8e32ff.v v4, (a0), v0.t
|
|
|
++
|
|
|
++ vlseg2e64ff.v v4, (a0)
|
|
|
++ vlseg2e64ff.v v4, 0(a0)
|
|
|
++ vlseg2e64ff.v v4, (a0), v0.t
|
|
|
++
|
|
|
++ vlseg3e64ff.v v4, (a0)
|
|
|
++ vlseg3e64ff.v v4, 0(a0)
|
|
|
++ vlseg3e64ff.v v4, (a0), v0.t
|
|
|
++
|
|
|
++ vlseg4e64ff.v v4, (a0)
|
|
|
++ vlseg4e64ff.v v4, 0(a0)
|
|
|
++ vlseg4e64ff.v v4, (a0), v0.t
|
|
|
++
|
|
|
++ vlseg5e64ff.v v4, (a0)
|
|
|
++ vlseg5e64ff.v v4, 0(a0)
|
|
|
++ vlseg5e64ff.v v4, (a0), v0.t
|
|
|
++
|
|
|
++ vlseg6e64ff.v v4, (a0)
|
|
|
++ vlseg6e64ff.v v4, 0(a0)
|
|
|
++ vlseg6e64ff.v v4, (a0), v0.t
|
|
|
++
|
|
|
++ vlseg7e64ff.v v4, (a0)
|
|
|
++ vlseg7e64ff.v v4, 0(a0)
|
|
|
++ vlseg7e64ff.v v4, (a0), v0.t
|
|
|
++
|
|
|
++ vlseg8e64ff.v v4, (a0)
|
|
|
++ vlseg8e64ff.v v4, 0(a0)
|
|
|
++ vlseg8e64ff.v v4, (a0), v0.t
|
|
|
++
|
|
|
++ vl1r.v v3, (a0)
|
|
|
++ vl1r.v v3, 0(a0)
|
|
|
++ vl1re8.v v3, (a0)
|
|
|
++ vl1re8.v v3, 0(a0)
|
|
|
++ vl1re16.v v3, (a0)
|
|
|
++ vl1re16.v v3, 0(a0)
|
|
|
++ vl1re32.v v3, (a0)
|
|
|
++ vl1re32.v v3, 0(a0)
|
|
|
++ vl1re64.v v3, (a0)
|
|
|
++ vl1re64.v v3, 0(a0)
|
|
|
++
|
|
|
++ vl2r.v v2, (a0)
|
|
|
++ vl2r.v v2, 0(a0)
|
|
|
++ vl2re8.v v2, (a0)
|
|
|
++ vl2re8.v v2, 0(a0)
|
|
|
++ vl2re16.v v2, (a0)
|
|
|
++ vl2re16.v v2, 0(a0)
|
|
|
++ vl2re32.v v2, (a0)
|
|
|
++ vl2re32.v v2, 0(a0)
|
|
|
++ vl2re64.v v2, (a0)
|
|
|
++ vl2re64.v v2, 0(a0)
|
|
|
++
|
|
|
++ vl4r.v v4, (a0)
|
|
|
++ vl4r.v v4, 0(a0)
|
|
|
++ vl4re8.v v4, (a0)
|
|
|
++ vl4re8.v v4, 0(a0)
|
|
|
++ vl4re16.v v4, (a0)
|
|
|
++ vl4re16.v v4, 0(a0)
|
|
|
++ vl4re32.v v4, (a0)
|
|
|
++ vl4re32.v v4, 0(a0)
|
|
|
++ vl4re64.v v4, (a0)
|
|
|
++ vl4re64.v v4, 0(a0)
|
|
|
++
|
|
|
++ vl8r.v v8, (a0)
|
|
|
++ vl8r.v v8, 0(a0)
|
|
|
++ vl8re8.v v8, (a0)
|
|
|
++ vl8re8.v v8, 0(a0)
|
|
|
++ vl8re16.v v8, (a0)
|
|
|
++ vl8re16.v v8, 0(a0)
|
|
|
++ vl8re32.v v8, (a0)
|
|
|
++ vl8re32.v v8, 0(a0)
|
|
|
++ vl8re64.v v8, (a0)
|
|
|
++ vl8re64.v v8, 0(a0)
|
|
|
++
|
|
|
++ vs1r.v v3, (a1)
|
|
|
++ vs1r.v v3, 0(a1)
|
|
|
++ vs2r.v v2, (a1)
|
|
|
++ vs2r.v v2, 0(a1)
|
|
|
++ vs4r.v v4, (a1)
|
|
|
++ vs4r.v v4, 0(a1)
|
|
|
++ vs8r.v v8, (a1)
|
|
|
++ vs8r.v v8, 0(a1)
|
|
|
++
|
|
|
++ vamoaddei8.v v4, (a1), v8, v4
|
|
|
++ vamoaddei8.v x0, (a1), v8, v4
|
|
|
++ vamoaddei8.v v4, (a1), v8, v4, v0.t
|
|
|
++ vamoaddei8.v x0, (a1), v8, v4, v0.t
|
|
|
++ vamoswapei8.v v4, (a1), v8, v4
|
|
|
++ vamoswapei8.v x0, (a1), v8, v4
|
|
|
++ vamoswapei8.v v4, (a1), v8, v4, v0.t
|
|
|
++ vamoswapei8.v x0, (a1), v8, v4, v0.t
|
|
|
++
|
|
|
++ vamoxorei8.v v4, (a1), v8, v4
|
|
|
++ vamoxorei8.v x0, (a1), v8, v4
|
|
|
++ vamoxorei8.v v4, (a1), v8, v4, v0.t
|
|
|
++ vamoxorei8.v x0, (a1), v8, v4, v0.t
|
|
|
++ vamoandei8.v v4, (a1), v8, v4
|
|
|
++ vamoandei8.v x0, (a1), v8, v4
|
|
|
++ vamoandei8.v v4, (a1), v8, v4, v0.t
|
|
|
++ vamoandei8.v x0, (a1), v8, v4, v0.t
|
|
|
++ vamoorei8.v v4, (a1), v8, v4
|
|
|
++ vamoorei8.v x0, (a1), v8, v4
|
|
|
++ vamoorei8.v v4, (a1), v8, v4, v0.t
|
|
|
++ vamoorei8.v x0, (a1), v8, v4, v0.t
|
|
|
++
|
|
|
++ vamominei8.v v4, (a1), v8, v4
|
|
|
++ vamominei8.v x0, (a1), v8, v4
|
|
|
++ vamominei8.v v4, (a1), v8, v4, v0.t
|
|
|
++ vamominei8.v x0, (a1), v8, v4, v0.t
|
|
|
++ vamomaxei8.v v4, (a1), v8, v4
|
|
|
++ vamomaxei8.v x0, (a1), v8, v4
|
|
|
++ vamomaxei8.v v4, (a1), v8, v4, v0.t
|
|
|
++ vamomaxei8.v x0, (a1), v8, v4, v0.t
|
|
|
++ vamominuei8.v v4, (a1), v8, v4
|
|
|
++ vamominuei8.v x0, (a1), v8, v4
|
|
|
++ vamominuei8.v v4, (a1), v8, v4, v0.t
|
|
|
++ vamominuei8.v x0, (a1), v8, v4, v0.t
|
|
|
++ vamomaxuei8.v v4, (a1), v8, v4
|
|
|
++ vamomaxuei8.v x0, (a1), v8, v4
|
|
|
++ vamomaxuei8.v v4, (a1), v8, v4, v0.t
|
|
|
++ vamomaxuei8.v x0, (a1), v8, v4, v0.t
|
|
|
++
|
|
|
++ vamoaddei8.v v4, 0(a1), v8, v4
|
|
|
++ vamoaddei8.v x0, 0(a1), v8, v4
|
|
|
++ vamoaddei8.v v4, 0(a1), v8, v4, v0.t
|
|
|
++ vamoaddei8.v x0, 0(a1), v8, v4, v0.t
|
|
|
++ vamoswapei8.v v4, 0(a1), v8, v4
|
|
|
++ vamoswapei8.v x0, 0(a1), v8, v4
|
|
|
++ vamoswapei8.v v4, 0(a1), v8, v4, v0.t
|
|
|
++ vamoswapei8.v x0, 0(a1), v8, v4, v0.t
|
|
|
++
|
|
|
++ vamoxorei8.v v4, 0(a1), v8, v4
|
|
|
++ vamoxorei8.v x0, 0(a1), v8, v4
|
|
|
++ vamoxorei8.v v4, 0(a1), v8, v4, v0.t
|
|
|
++ vamoxorei8.v x0, 0(a1), v8, v4, v0.t
|
|
|
++ vamoandei8.v v4, 0(a1), v8, v4
|
|
|
++ vamoandei8.v x0, 0(a1), v8, v4
|
|
|
++ vamoandei8.v v4, 0(a1), v8, v4, v0.t
|
|
|
++ vamoandei8.v x0, 0(a1), v8, v4, v0.t
|
|
|
++ vamoorei8.v v4, 0(a1), v8, v4
|
|
|
++ vamoorei8.v x0, 0(a1), v8, v4
|
|
|
++ vamoorei8.v v4, 0(a1), v8, v4, v0.t
|
|
|
++ vamoorei8.v x0, 0(a1), v8, v4, v0.t
|
|
|
++
|
|
|
++ vamominei8.v v4, 0(a1), v8, v4
|
|
|
++ vamominei8.v x0, 0(a1), v8, v4
|
|
|
++ vamominei8.v v4, 0(a1), v8, v4, v0.t
|
|
|
++ vamominei8.v x0, 0(a1), v8, v4, v0.t
|
|
|
++ vamomaxei8.v v4, 0(a1), v8, v4
|
|
|
++ vamomaxei8.v x0, 0(a1), v8, v4
|
|
|
++ vamomaxei8.v v4, 0(a1), v8, v4, v0.t
|
|
|
++ vamomaxei8.v x0, 0(a1), v8, v4, v0.t
|
|
|
++ vamominuei8.v v4, 0(a1), v8, v4
|
|
|
++ vamominuei8.v x0, 0(a1), v8, v4
|
|
|
++ vamominuei8.v v4, 0(a1), v8, v4, v0.t
|
|
|
++ vamominuei8.v x0, 0(a1), v8, v4, v0.t
|
|
|
++ vamomaxuei8.v v4, 0(a1), v8, v4
|
|
|
++ vamomaxuei8.v x0, 0(a1), v8, v4
|
|
|
++ vamomaxuei8.v v4, 0(a1), v8, v4, v0.t
|
|
|
++ vamomaxuei8.v x0, 0(a1), v8, v4, v0.t
|
|
|
++
|
|
|
++ vamoaddei16.v v4, (a1), v8, v4
|
|
|
++ vamoaddei16.v x0, (a1), v8, v4
|
|
|
++ vamoaddei16.v v4, (a1), v8, v4, v0.t
|
|
|
++ vamoaddei16.v x0, (a1), v8, v4, v0.t
|
|
|
++ vamoswapei16.v v4, (a1), v8, v4
|
|
|
++ vamoswapei16.v x0, (a1), v8, v4
|
|
|
++ vamoswapei16.v v4, (a1), v8, v4, v0.t
|
|
|
++ vamoswapei16.v x0, (a1), v8, v4, v0.t
|
|
|
++
|
|
|
++ vamoxorei16.v v4, (a1), v8, v4
|
|
|
++ vamoxorei16.v x0, (a1), v8, v4
|
|
|
++ vamoxorei16.v v4, (a1), v8, v4, v0.t
|
|
|
++ vamoxorei16.v x0, (a1), v8, v4, v0.t
|
|
|
++ vamoandei16.v v4, (a1), v8, v4
|
|
|
++ vamoandei16.v x0, (a1), v8, v4
|
|
|
++ vamoandei16.v v4, (a1), v8, v4, v0.t
|
|
|
++ vamoandei16.v x0, (a1), v8, v4, v0.t
|
|
|
++ vamoorei16.v v4, (a1), v8, v4
|
|
|
++ vamoorei16.v x0, (a1), v8, v4
|
|
|
++ vamoorei16.v v4, (a1), v8, v4, v0.t
|
|
|
++ vamoorei16.v x0, (a1), v8, v4, v0.t
|
|
|
++
|
|
|
++ vamominei16.v v4, (a1), v8, v4
|
|
|
++ vamominei16.v x0, (a1), v8, v4
|
|
|
++ vamominei16.v v4, (a1), v8, v4, v0.t
|
|
|
++ vamominei16.v x0, (a1), v8, v4, v0.t
|
|
|
++ vamomaxei16.v v4, (a1), v8, v4
|
|
|
++ vamomaxei16.v x0, (a1), v8, v4
|
|
|
++ vamomaxei16.v v4, (a1), v8, v4, v0.t
|
|
|
++ vamomaxei16.v x0, (a1), v8, v4, v0.t
|
|
|
++ vamominuei16.v v4, (a1), v8, v4
|
|
|
++ vamominuei16.v x0, (a1), v8, v4
|
|
|
++ vamominuei16.v v4, (a1), v8, v4, v0.t
|
|
|
++ vamominuei16.v x0, (a1), v8, v4, v0.t
|
|
|
++ vamomaxuei16.v v4, (a1), v8, v4
|
|
|
++ vamomaxuei16.v x0, (a1), v8, v4
|
|
|
++ vamomaxuei16.v v4, (a1), v8, v4, v0.t
|
|
|
++ vamomaxuei16.v x0, (a1), v8, v4, v0.t
|
|
|
++
|
|
|
++ vamoaddei16.v v4, 0(a1), v8, v4
|
|
|
++ vamoaddei16.v x0, 0(a1), v8, v4
|
|
|
++ vamoaddei16.v v4, 0(a1), v8, v4, v0.t
|
|
|
++ vamoaddei16.v x0, 0(a1), v8, v4, v0.t
|
|
|
++ vamoswapei16.v v4, 0(a1), v8, v4
|
|
|
++ vamoswapei16.v x0, 0(a1), v8, v4
|
|
|
++ vamoswapei16.v v4, 0(a1), v8, v4, v0.t
|
|
|
++ vamoswapei16.v x0, 0(a1), v8, v4, v0.t
|
|
|
++
|
|
|
++ vamoxorei16.v v4, 0(a1), v8, v4
|
|
|
++ vamoxorei16.v x0, 0(a1), v8, v4
|
|
|
++ vamoxorei16.v v4, 0(a1), v8, v4, v0.t
|
|
|
++ vamoxorei16.v x0, 0(a1), v8, v4, v0.t
|
|
|
++ vamoandei16.v v4, 0(a1), v8, v4
|
|
|
++ vamoandei16.v x0, 0(a1), v8, v4
|
|
|
++ vamoandei16.v v4, 0(a1), v8, v4, v0.t
|
|
|
++ vamoandei16.v x0, 0(a1), v8, v4, v0.t
|
|
|
++ vamoorei16.v v4, 0(a1), v8, v4
|
|
|
++ vamoorei16.v x0, 0(a1), v8, v4
|
|
|
++ vamoorei16.v v4, 0(a1), v8, v4, v0.t
|
|
|
++ vamoorei16.v x0, 0(a1), v8, v4, v0.t
|
|
|
++
|
|
|
++ vamominei16.v v4, 0(a1), v8, v4
|
|
|
++ vamominei16.v x0, 0(a1), v8, v4
|
|
|
++ vamominei16.v v4, 0(a1), v8, v4, v0.t
|
|
|
++ vamominei16.v x0, 0(a1), v8, v4, v0.t
|
|
|
++ vamomaxei16.v v4, 0(a1), v8, v4
|
|
|
++ vamomaxei16.v x0, 0(a1), v8, v4
|
|
|
++ vamomaxei16.v v4, 0(a1), v8, v4, v0.t
|
|
|
++ vamomaxei16.v x0, 0(a1), v8, v4, v0.t
|
|
|
++ vamominuei16.v v4, 0(a1), v8, v4
|
|
|
++ vamominuei16.v x0, 0(a1), v8, v4
|
|
|
++ vamominuei16.v v4, 0(a1), v8, v4, v0.t
|
|
|
++ vamominuei16.v x0, 0(a1), v8, v4, v0.t
|
|
|
++ vamomaxuei16.v v4, 0(a1), v8, v4
|
|
|
++ vamomaxuei16.v x0, 0(a1), v8, v4
|
|
|
++ vamomaxuei16.v v4, 0(a1), v8, v4, v0.t
|
|
|
++ vamomaxuei16.v x0, 0(a1), v8, v4, v0.t
|
|
|
++
|
|
|
++ vamoaddei32.v v4, (a1), v8, v4
|
|
|
++ vamoaddei32.v x0, (a1), v8, v4
|
|
|
++ vamoaddei32.v v4, (a1), v8, v4, v0.t
|
|
|
++ vamoaddei32.v x0, (a1), v8, v4, v0.t
|
|
|
++ vamoswapei32.v v4, (a1), v8, v4
|
|
|
++ vamoswapei32.v x0, (a1), v8, v4
|
|
|
++ vamoswapei32.v v4, (a1), v8, v4, v0.t
|
|
|
++ vamoswapei32.v x0, (a1), v8, v4, v0.t
|
|
|
++
|
|
|
++ vamoxorei32.v v4, (a1), v8, v4
|
|
|
++ vamoxorei32.v x0, (a1), v8, v4
|
|
|
++ vamoxorei32.v v4, (a1), v8, v4, v0.t
|
|
|
++ vamoxorei32.v x0, (a1), v8, v4, v0.t
|
|
|
++ vamoandei32.v v4, (a1), v8, v4
|
|
|
++ vamoandei32.v x0, (a1), v8, v4
|
|
|
++ vamoandei32.v v4, (a1), v8, v4, v0.t
|
|
|
++ vamoandei32.v x0, (a1), v8, v4, v0.t
|
|
|
++ vamoorei32.v v4, (a1), v8, v4
|
|
|
++ vamoorei32.v x0, (a1), v8, v4
|
|
|
++ vamoorei32.v v4, (a1), v8, v4, v0.t
|
|
|
++ vamoorei32.v x0, (a1), v8, v4, v0.t
|
|
|
++
|
|
|
++ vamominei32.v v4, (a1), v8, v4
|
|
|
++ vamominei32.v x0, (a1), v8, v4
|
|
|
++ vamominei32.v v4, (a1), v8, v4, v0.t
|
|
|
++ vamominei32.v x0, (a1), v8, v4, v0.t
|
|
|
++ vamomaxei32.v v4, (a1), v8, v4
|
|
|
++ vamomaxei32.v x0, (a1), v8, v4
|
|
|
++ vamomaxei32.v v4, (a1), v8, v4, v0.t
|
|
|
++ vamomaxei32.v x0, (a1), v8, v4, v0.t
|
|
|
++ vamominuei32.v v4, (a1), v8, v4
|
|
|
++ vamominuei32.v x0, (a1), v8, v4
|
|
|
++ vamominuei32.v v4, (a1), v8, v4, v0.t
|
|
|
++ vamominuei32.v x0, (a1), v8, v4, v0.t
|
|
|
++ vamomaxuei32.v v4, (a1), v8, v4
|
|
|
++ vamomaxuei32.v x0, (a1), v8, v4
|
|
|
++ vamomaxuei32.v v4, (a1), v8, v4, v0.t
|
|
|
++ vamomaxuei32.v x0, (a1), v8, v4, v0.t
|
|
|
++
|
|
|
++ vamoaddei32.v v4, 0(a1), v8, v4
|
|
|
++ vamoaddei32.v x0, 0(a1), v8, v4
|
|
|
++ vamoaddei32.v v4, 0(a1), v8, v4, v0.t
|
|
|
++ vamoaddei32.v x0, 0(a1), v8, v4, v0.t
|
|
|
++ vamoswapei32.v v4, 0(a1), v8, v4
|
|
|
++ vamoswapei32.v x0, 0(a1), v8, v4
|
|
|
++ vamoswapei32.v v4, 0(a1), v8, v4, v0.t
|
|
|
++ vamoswapei32.v x0, 0(a1), v8, v4, v0.t
|
|
|
++
|
|
|
++ vamoxorei32.v v4, 0(a1), v8, v4
|
|
|
++ vamoxorei32.v x0, 0(a1), v8, v4
|
|
|
++ vamoxorei32.v v4, 0(a1), v8, v4, v0.t
|
|
|
++ vamoxorei32.v x0, 0(a1), v8, v4, v0.t
|
|
|
++ vamoandei32.v v4, 0(a1), v8, v4
|
|
|
++ vamoandei32.v x0, 0(a1), v8, v4
|
|
|
++ vamoandei32.v v4, 0(a1), v8, v4, v0.t
|
|
|
++ vamoandei32.v x0, 0(a1), v8, v4, v0.t
|
|
|
++ vamoorei32.v v4, 0(a1), v8, v4
|
|
|
++ vamoorei32.v x0, 0(a1), v8, v4
|
|
|
++ vamoorei32.v v4, 0(a1), v8, v4, v0.t
|
|
|
++ vamoorei32.v x0, 0(a1), v8, v4, v0.t
|
|
|
++
|
|
|
++ vamominei32.v v4, 0(a1), v8, v4
|
|
|
++ vamominei32.v x0, 0(a1), v8, v4
|
|
|
++ vamominei32.v v4, 0(a1), v8, v4, v0.t
|
|
|
++ vamominei32.v x0, 0(a1), v8, v4, v0.t
|
|
|
++ vamomaxei32.v v4, 0(a1), v8, v4
|
|
|
++ vamomaxei32.v x0, 0(a1), v8, v4
|
|
|
++ vamomaxei32.v v4, 0(a1), v8, v4, v0.t
|
|
|
++ vamomaxei32.v x0, 0(a1), v8, v4, v0.t
|
|
|
++ vamominuei32.v v4, 0(a1), v8, v4
|
|
|
++ vamominuei32.v x0, 0(a1), v8, v4
|
|
|
++ vamominuei32.v v4, 0(a1), v8, v4, v0.t
|
|
|
++ vamominuei32.v x0, 0(a1), v8, v4, v0.t
|
|
|
++ vamomaxuei32.v v4, 0(a1), v8, v4
|
|
|
++ vamomaxuei32.v x0, 0(a1), v8, v4
|
|
|
++ vamomaxuei32.v v4, 0(a1), v8, v4, v0.t
|
|
|
++ vamomaxuei32.v x0, 0(a1), v8, v4, v0.t
|
|
|
++
|
|
|
++ vamoaddei64.v v4, (a1), v8, v4
|
|
|
++ vamoaddei64.v x0, (a1), v8, v4
|
|
|
++ vamoaddei64.v v4, (a1), v8, v4, v0.t
|
|
|
++ vamoaddei64.v x0, (a1), v8, v4, v0.t
|
|
|
++ vamoswapei64.v v4, (a1), v8, v4
|
|
|
++ vamoswapei64.v x0, (a1), v8, v4
|
|
|
++ vamoswapei64.v v4, (a1), v8, v4, v0.t
|
|
|
++ vamoswapei64.v x0, (a1), v8, v4, v0.t
|
|
|
++
|
|
|
++ vamoxorei64.v v4, (a1), v8, v4
|
|
|
++ vamoxorei64.v x0, (a1), v8, v4
|
|
|
++ vamoxorei64.v v4, (a1), v8, v4, v0.t
|
|
|
++ vamoxorei64.v x0, (a1), v8, v4, v0.t
|
|
|
++ vamoandei64.v v4, (a1), v8, v4
|
|
|
++ vamoandei64.v x0, (a1), v8, v4
|
|
|
++ vamoandei64.v v4, (a1), v8, v4, v0.t
|
|
|
++ vamoandei64.v x0, (a1), v8, v4, v0.t
|
|
|
++ vamoorei64.v v4, (a1), v8, v4
|
|
|
++ vamoorei64.v x0, (a1), v8, v4
|
|
|
++ vamoorei64.v v4, (a1), v8, v4, v0.t
|
|
|
++ vamoorei64.v x0, (a1), v8, v4, v0.t
|
|
|
++
|
|
|
++ vamominei64.v v4, (a1), v8, v4
|
|
|
++ vamominei64.v x0, (a1), v8, v4
|
|
|
++ vamominei64.v v4, (a1), v8, v4, v0.t
|
|
|
++ vamominei64.v x0, (a1), v8, v4, v0.t
|
|
|
++ vamomaxei64.v v4, (a1), v8, v4
|
|
|
++ vamomaxei64.v x0, (a1), v8, v4
|
|
|
++ vamomaxei64.v v4, (a1), v8, v4, v0.t
|
|
|
++ vamomaxei64.v x0, (a1), v8, v4, v0.t
|
|
|
++ vamominuei64.v v4, (a1), v8, v4
|
|
|
++ vamominuei64.v x0, (a1), v8, v4
|
|
|
++ vamominuei64.v v4, (a1), v8, v4, v0.t
|
|
|
++ vamominuei64.v x0, (a1), v8, v4, v0.t
|
|
|
++ vamomaxuei64.v v4, (a1), v8, v4
|
|
|
++ vamomaxuei64.v x0, (a1), v8, v4
|
|
|
++ vamomaxuei64.v v4, (a1), v8, v4, v0.t
|
|
|
++ vamomaxuei64.v x0, (a1), v8, v4, v0.t
|
|
|
++
|
|
|
++ vamoaddei64.v v4, 0(a1), v8, v4
|
|
|
++ vamoaddei64.v x0, 0(a1), v8, v4
|
|
|
++ vamoaddei64.v v4, 0(a1), v8, v4, v0.t
|
|
|
++ vamoaddei64.v x0, 0(a1), v8, v4, v0.t
|
|
|
++ vamoswapei64.v v4, 0(a1), v8, v4
|
|
|
++ vamoswapei64.v x0, 0(a1), v8, v4
|
|
|
++ vamoswapei64.v v4, 0(a1), v8, v4, v0.t
|
|
|
++ vamoswapei64.v x0, 0(a1), v8, v4, v0.t
|
|
|
++
|
|
|
++ vamoxorei64.v v4, 0(a1), v8, v4
|
|
|
++ vamoxorei64.v x0, 0(a1), v8, v4
|
|
|
++ vamoxorei64.v v4, 0(a1), v8, v4, v0.t
|
|
|
++ vamoxorei64.v x0, 0(a1), v8, v4, v0.t
|
|
|
++ vamoandei64.v v4, 0(a1), v8, v4
|
|
|
++ vamoandei64.v x0, 0(a1), v8, v4
|
|
|
++ vamoandei64.v v4, 0(a1), v8, v4, v0.t
|
|
|
++ vamoandei64.v x0, 0(a1), v8, v4, v0.t
|
|
|
++ vamoorei64.v v4, 0(a1), v8, v4
|
|
|
++ vamoorei64.v x0, 0(a1), v8, v4
|
|
|
++ vamoorei64.v v4, 0(a1), v8, v4, v0.t
|
|
|
++ vamoorei64.v x0, 0(a1), v8, v4, v0.t
|
|
|
++
|
|
|
++ vamominei64.v v4, 0(a1), v8, v4
|
|
|
++ vamominei64.v x0, 0(a1), v8, v4
|
|
|
++ vamominei64.v v4, 0(a1), v8, v4, v0.t
|
|
|
++ vamominei64.v x0, 0(a1), v8, v4, v0.t
|
|
|
++ vamomaxei64.v v4, 0(a1), v8, v4
|
|
|
++ vamomaxei64.v x0, 0(a1), v8, v4
|
|
|
++ vamomaxei64.v v4, 0(a1), v8, v4, v0.t
|
|
|
++ vamomaxei64.v x0, 0(a1), v8, v4, v0.t
|
|
|
++ vamominuei64.v v4, 0(a1), v8, v4
|
|
|
++ vamominuei64.v x0, 0(a1), v8, v4
|
|
|
++ vamominuei64.v v4, 0(a1), v8, v4, v0.t
|
|
|
++ vamominuei64.v x0, 0(a1), v8, v4, v0.t
|
|
|
++ vamomaxuei64.v v4, 0(a1), v8, v4
|
|
|
++ vamomaxuei64.v x0, 0(a1), v8, v4
|
|
|
++ vamomaxuei64.v v4, 0(a1), v8, v4, v0.t
|
|
|
++ vamomaxuei64.v x0, 0(a1), v8, v4, v0.t
|
|
|
++ # Aliases
|
|
|
++ vwcvt.x.x.v v4, v8
|
|
|
++ vwcvtu.x.x.v v4, v8
|
|
|
++ vwcvt.x.x.v v4, v8, v0.t
|
|
|
++ vwcvtu.x.x.v v4, v8, v0.t
|
|
|
++
|
|
|
++ vwaddu.vv v4, v8, v12
|
|
|
++ vwaddu.vx v4, v8, a1
|
|
|
++ vwaddu.vv v4, v8, v12, v0.t
|
|
|
++ vwaddu.vx v4, v8, a1, v0.t
|
|
|
++ vwsubu.vv v4, v8, v12
|
|
|
++ vwsubu.vx v4, v8, a1
|
|
|
++ vwsubu.vv v4, v8, v12, v0.t
|
|
|
++ vwsubu.vx v4, v8, a1, v0.t
|
|
|
++ vwadd.vv v4, v8, v12
|
|
|
++ vwadd.vx v4, v8, a1
|
|
|
++ vwadd.vv v4, v8, v12, v0.t
|
|
|
++ vwadd.vx v4, v8, a1, v0.t
|
|
|
++ vwsub.vv v4, v8, v12
|
|
|
++ vwsub.vx v4, v8, a1
|
|
|
++ vwsub.vv v4, v8, v12, v0.t
|
|
|
++ vwsub.vx v4, v8, a1, v0.t
|
|
|
++ vwaddu.wv v4, v8, v12
|
|
|
++ vwaddu.wx v4, v8, a1
|
|
|
++ vwaddu.wv v4, v8, v12, v0.t
|
|
|
++ vwaddu.wx v4, v8, a1, v0.t
|
|
|
++ vwsubu.wv v4, v8, v12
|
|
|
++ vwsubu.wx v4, v8, a1
|
|
|
++ vwsubu.wv v4, v8, v12, v0.t
|
|
|
++ vwsubu.wx v4, v8, a1, v0.t
|
|
|
++ vwadd.wv v4, v8, v12
|
|
|
++ vwadd.wx v4, v8, a1
|
|
|
++ vwadd.wv v4, v8, v12, v0.t
|
|
|
++ vwadd.wx v4, v8, a1, v0.t
|
|
|
++ vwsub.wv v4, v8, v12
|
|
|
++ vwsub.wx v4, v8, a1
|
|
|
++ vwsub.wv v4, v8, v12, v0.t
|
|
|
++ vwsub.wx v4, v8, a1, v0.t
|
|
|
++
|
|
|
++ vsll.vv v4, v8, v12
|
|
|
++ vsll.vx v4, v8, a1
|
|
|
++ vsll.vi v4, v8, 1
|
|
|
++ vsll.vi v4, v8, 31
|
|
|
++ vsll.vv v4, v8, v12, v0.t
|
|
|
++ vsll.vx v4, v8, a1, v0.t
|
|
|
++ vsll.vi v4, v8, 1, v0.t
|
|
|
++ vsll.vi v4, v8, 31, v0.t
|
|
|
++ vsrl.vv v4, v8, v12
|
|
|
++ vsrl.vx v4, v8, a1
|
|
|
++ vsrl.vi v4, v8, 1
|
|
|
++ vsrl.vi v4, v8, 31
|
|
|
++ vsrl.vv v4, v8, v12, v0.t
|
|
|
++ vsrl.vx v4, v8, a1, v0.t
|
|
|
++ vsrl.vi v4, v8, 1, v0.t
|
|
|
++ vsrl.vi v4, v8, 31, v0.t
|
|
|
++ vsra.vv v4, v8, v12
|
|
|
++ vsra.vx v4, v8, a1
|
|
|
++ vsra.vi v4, v8, 1
|
|
|
++ vsra.vi v4, v8, 31
|
|
|
++ vsra.vv v4, v8, v12, v0.t
|
|
|
++ vsra.vx v4, v8, a1, v0.t
|
|
|
++ vsra.vi v4, v8, 1, v0.t
|
|
|
++ vsra.vi v4, v8, 31, v0.t
|
|
|
++
|
|
|
++ # Aliases
|
|
|
++ vncvt.x.x.w v4, v8
|
|
|
++ vncvt.x.x.w v4, v8, v0.t
|
|
|
++
|
|
|
++ vnsrl.wv v4, v8, v12
|
|
|
++ vnsrl.wx v4, v8, a1
|
|
|
++ vnsrl.wi v4, v8, 1
|
|
|
++ vnsrl.wi v4, v8, 31
|
|
|
++ vnsrl.wv v4, v8, v12, v0.t
|
|
|
++ vnsrl.wx v4, v8, a1, v0.t
|
|
|
++ vnsrl.wi v4, v8, 1, v0.t
|
|
|
++ vnsrl.wi v4, v8, 31, v0.t
|
|
|
++ vnsra.wv v4, v8, v12
|
|
|
++ vnsra.wx v4, v8, a1
|
|
|
++ vnsra.wi v4, v8, 1
|
|
|
++ vnsra.wi v4, v8, 31
|
|
|
++ vnsra.wv v4, v8, v12, v0.t
|
|
|
++ vnsra.wx v4, v8, a1, v0.t
|
|
|
++ vnsra.wi v4, v8, 1, v0.t
|
|
|
++ vnsra.wi v4, v8, 31, v0.t
|
|
|
++
|
|
|
++ vwmul.vv v4, v8, v12
|
|
|
++ vwmul.vx v4, v8, a1
|
|
|
++ vwmul.vv v4, v8, v12, v0.t
|
|
|
++ vwmul.vx v4, v8, a1, v0.t
|
|
|
++ vwmulu.vv v4, v8, v12
|
|
|
++ vwmulu.vx v4, v8, a1
|
|
|
++ vwmulu.vv v4, v8, v12, v0.t
|
|
|
++ vwmulu.vx v4, v8, a1, v0.t
|
|
|
++ vwmulsu.vv v4, v8, v12
|
|
|
++ vwmulsu.vx v4, v8, a1
|
|
|
++ vwmulsu.vv v4, v8, v12, v0.t
|
|
|
++ vwmulsu.vx v4, v8, a1, v0.t
|
|
|
++
|
|
|
++ vwmaccu.vv v4, v12, v8
|
|
|
++ vwmaccu.vx v4, a1, v8
|
|
|
++ vwmaccu.vv v4, v12, v8, v0.t
|
|
|
++ vwmaccu.vx v4, a1, v8, v0.t
|
|
|
++ vwmacc.vv v4, v12, v8
|
|
|
++ vwmacc.vx v4, a1, v8
|
|
|
++ vwmacc.vv v4, v12, v8, v0.t
|
|
|
++ vwmacc.vx v4, a1, v8, v0.t
|
|
|
++ vwmaccsu.vv v4, v12, v8
|
|
|
++ vwmaccsu.vx v4, a1, v8
|
|
|
++ vwmaccsu.vv v4, v12, v8, v0.t
|
|
|
++ vwmaccsu.vx v4, a1, v8, v0.t
|
|
|
++ vwmaccus.vx v4, a1, v8
|
|
|
++ vwmaccus.vx v4, a1, v8, v0.t
|
|
|
++
|
|
|
++ vsaddu.vv v4, v8, v12
|
|
|
++ vsaddu.vx v4, v8, a1
|
|
|
++ vsaddu.vi v4, v8, 15
|
|
|
++ vsaddu.vi v4, v8, -16
|
|
|
++ vsaddu.vv v4, v8, v12, v0.t
|
|
|
++ vsaddu.vx v4, v8, a1, v0.t
|
|
|
++ vsaddu.vi v4, v8, 15, v0.t
|
|
|
++ vsaddu.vi v4, v8, -16, v0.t
|
|
|
++ vsadd.vv v4, v8, v12
|
|
|
++ vsadd.vx v4, v8, a1
|
|
|
++ vsadd.vi v4, v8, 15
|
|
|
++ vsadd.vi v4, v8, -16
|
|
|
++ vsadd.vv v4, v8, v12, v0.t
|
|
|
++ vsadd.vx v4, v8, a1, v0.t
|
|
|
++ vsadd.vi v4, v8, 15, v0.t
|
|
|
++ vsadd.vi v4, v8, -16, v0.t
|
|
|
++ vssubu.vv v4, v8, v12
|
|
|
++ vssubu.vx v4, v8, a1
|
|
|
++ vssubu.vv v4, v8, v12, v0.t
|
|
|
++ vssubu.vx v4, v8, a1, v0.t
|
|
|
++ vssub.vv v4, v8, v12
|
|
|
++ vssub.vx v4, v8, a1
|
|
|
++ vssub.vv v4, v8, v12, v0.t
|
|
|
++ vssub.vx v4, v8, a1, v0.t
|
|
|
++
|
|
|
++ vaaddu.vv v4, v8, v12
|
|
|
++ vaaddu.vx v4, v8, a1
|
|
|
++ vaaddu.vv v4, v8, v12, v0.t
|
|
|
++ vaaddu.vx v4, v8, a1, v0.t
|
|
|
++ vaadd.vv v4, v8, v12
|
|
|
++ vaadd.vx v4, v8, a1
|
|
|
++ vaadd.vv v4, v8, v12, v0.t
|
|
|
++ vaadd.vx v4, v8, a1, v0.t
|
|
|
++ vasubu.vv v4, v8, v12
|
|
|
++ vasubu.vx v4, v8, a1
|
|
|
++ vasubu.vv v4, v8, v12, v0.t
|
|
|
++ vasubu.vx v4, v8, a1, v0.t
|
|
|
++ vasub.vv v4, v8, v12
|
|
|
++ vasub.vx v4, v8, a1
|
|
|
++ vasub.vv v4, v8, v12, v0.t
|
|
|
++ vasub.vx v4, v8, a1, v0.t
|
|
|
++
|
|
|
++ vsmul.vv v4, v8, v12
|
|
|
++ vsmul.vx v4, v8, a1
|
|
|
++ vsmul.vv v4, v8, v12, v0.t
|
|
|
++ vsmul.vx v4, v8, a1, v0.t
|
|
|
++
|
|
|
++ vssrl.vv v4, v8, v12
|
|
|
++ vssrl.vx v4, v8, a1
|
|
|
++ vssrl.vi v4, v8, 1
|
|
|
++ vssrl.vi v4, v8, 31
|
|
|
++ vssrl.vv v4, v8, v12, v0.t
|
|
|
++ vssrl.vx v4, v8, a1, v0.t
|
|
|
++ vssrl.vi v4, v8, 1, v0.t
|
|
|
++ vssrl.vi v4, v8, 31, v0.t
|
|
|
++ vssra.vv v4, v8, v12
|
|
|
++ vssra.vx v4, v8, a1
|
|
|
++ vssra.vi v4, v8, 1
|
|
|
++ vssra.vi v4, v8, 31
|
|
|
++ vssra.vv v4, v8, v12, v0.t
|
|
|
++ vssra.vx v4, v8, a1, v0.t
|
|
|
++ vssra.vi v4, v8, 1, v0.t
|
|
|
++ vssra.vi v4, v8, 31, v0.t
|
|
|
++
|
|
|
++ vnclipu.wv v4, v8, v12
|
|
|
++ vnclipu.wx v4, v8, a1
|
|
|
++ vnclipu.wi v4, v8, 1
|
|
|
++ vnclipu.wi v4, v8, 31
|
|
|
++ vnclipu.wv v4, v8, v12, v0.t
|
|
|
++ vnclipu.wx v4, v8, a1, v0.t
|
|
|
++ vnclipu.wi v4, v8, 1, v0.t
|
|
|
++ vnclipu.wi v4, v8, 31, v0.t
|
|
|
++ vnclip.wv v4, v8, v12
|
|
|
++ vnclip.wx v4, v8, a1
|
|
|
++ vnclip.wi v4, v8, 1
|
|
|
++ vnclip.wi v4, v8, 31
|
|
|
++ vnclip.wv v4, v8, v12, v0.t
|
|
|
++ vnclip.wx v4, v8, a1, v0.t
|
|
|
++ vnclip.wi v4, v8, 1, v0.t
|
|
|
++ vnclip.wi v4, v8, 31, v0.t
|
|
|
++
|
|
|
++ vfwadd.vv v4, v8, v12
|
|
|
++ vfwadd.vf v4, v8, fa2
|
|
|
++ vfwadd.vv v4, v8, v12, v0.t
|
|
|
++ vfwadd.vf v4, v8, fa2, v0.t
|
|
|
++ vfwsub.vv v4, v8, v12
|
|
|
++ vfwsub.vf v4, v8, fa2
|
|
|
++ vfwsub.vv v4, v8, v12, v0.t
|
|
|
++ vfwsub.vf v4, v8, fa2, v0.t
|
|
|
++ vfwadd.wv v4, v8, v12
|
|
|
++ vfwadd.wf v4, v8, fa2
|
|
|
++ vfwadd.wv v4, v8, v12, v0.t
|
|
|
++ vfwadd.wf v4, v8, fa2, v0.t
|
|
|
++ vfwsub.wv v4, v8, v12
|
|
|
++ vfwsub.wf v4, v8, fa2
|
|
|
++ vfwsub.wv v4, v8, v12, v0.t
|
|
|
++ vfwsub.wf v4, v8, fa2, v0.t
|
|
|
++
|
|
|
++ vfwmul.vv v4, v8, v12
|
|
|
++ vfwmul.vf v4, v8, fa2
|
|
|
++ vfwmul.vv v4, v8, v12, v0.t
|
|
|
++ vfwmul.vf v4, v8, fa2, v0.t
|
|
|
++
|
|
|
++ vfwmacc.vv v4, v12, v8
|
|
|
++ vfwmacc.vf v4, fa2, v8
|
|
|
++ vfwnmacc.vv v4, v12, v8
|
|
|
++ vfwnmacc.vf v4, fa2, v8
|
|
|
++ vfwmsac.vv v4, v12, v8
|
|
|
++ vfwmsac.vf v4, fa2, v8
|
|
|
++ vfwnmsac.vv v4, v12, v8
|
|
|
++ vfwnmsac.vf v4, fa2, v8
|
|
|
++ vfwmacc.vv v4, v12, v8, v0.t
|
|
|
++ vfwmacc.vf v4, fa2, v8, v0.t
|
|
|
++ vfwnmacc.vv v4, v12, v8, v0.t
|
|
|
++ vfwnmacc.vf v4, fa2, v8, v0.t
|
|
|
++ vfwmsac.vv v4, v12, v8, v0.t
|
|
|
++ vfwmsac.vf v4, fa2, v8, v0.t
|
|
|
++ vfwnmsac.vv v4, v12, v8, v0.t
|
|
|
++ vfwnmsac.vf v4, fa2, v8, v0.t
|
|
|
++
|
|
|
++ vfsqrt.v v4, v8
|
|
|
++ vfsqrt.v v4, v8, v0.t
|
|
|
++ vfrsqrte7.v v4, v8
|
|
|
++ vfrsqrte7.v v4, v8, v0.t
|
|
|
++ vfrsqrt7.v v4, v8
|
|
|
++ vfrsqrt7.v v4, v8, v0.t
|
|
|
++ vfrece7.v v4, v8
|
|
|
++ vfrece7.v v4, v8, v0.t
|
|
|
++ vfrec7.v v4, v8
|
|
|
++ vfrec7.v v4, v8, v0.t
|
|
|
++ vfclass.v v4, v8
|
|
|
++ vfclass.v v4, v8, v0.t
|
|
|
++
|
|
|
++ vfcvt.xu.f.v v4, v8
|
|
|
++ vfcvt.x.f.v v4, v8
|
|
|
++ vfcvt.rtz.xu.f.v v4, v8
|
|
|
++ vfcvt.rtz.x.f.v v4, v8
|
|
|
++ vfcvt.f.xu.v v4, v8
|
|
|
++ vfcvt.f.x.v v4, v8
|
|
|
++ vfcvt.xu.f.v v4, v8, v0.t
|
|
|
++ vfcvt.x.f.v v4, v8, v0.t
|
|
|
++ vfcvt.rtz.xu.f.v v4, v8, v0.t
|
|
|
++ vfcvt.rtz.x.f.v v4, v8, v0.t
|
|
|
++ vfcvt.f.xu.v v4, v8, v0.t
|
|
|
++ vfcvt.f.x.v v4, v8, v0.t
|
|
|
++
|
|
|
++ vfwcvt.xu.f.v v4, v8
|
|
|
++ vfwcvt.x.f.v v4, v8
|
|
|
++ vfwcvt.rtz.xu.f.v v4, v8
|
|
|
++ vfwcvt.rtz.x.f.v v4, v8
|
|
|
++ vfwcvt.f.xu.v v4, v8
|
|
|
++ vfwcvt.f.x.v v4, v8
|
|
|
++ vfwcvt.f.f.v v4, v8
|
|
|
++ vfwcvt.xu.f.v v4, v8, v0.t
|
|
|
++ vfwcvt.x.f.v v4, v8, v0.t
|
|
|
++ vfwcvt.rtz.xu.f.v v4, v8, v0.t
|
|
|
++ vfwcvt.rtz.x.f.v v4, v8, v0.t
|
|
|
++ vfwcvt.f.xu.v v4, v8, v0.t
|
|
|
++ vfwcvt.f.x.v v4, v8, v0.t
|
|
|
++ vfwcvt.f.f.v v4, v8, v0.t
|
|
|
++
|
|
|
++ vfncvt.xu.f.w v4, v8
|
|
|
++ vfncvt.x.f.w v4, v8
|
|
|
++ vfncvt.rtz.xu.f.w v4, v8
|
|
|
++ vfncvt.rtz.x.f.w v4, v8
|
|
|
++ vfncvt.f.xu.w v4, v8
|
|
|
++ vfncvt.f.x.w v4, v8
|
|
|
++ vfncvt.f.f.w v4, v8
|
|
|
++ vfncvt.rod.f.f.w v4, v8
|
|
|
++ vfncvt.xu.f.w v4, v8, v0.t
|
|
|
++ vfncvt.x.f.w v4, v8, v0.t
|
|
|
++ vfncvt.rtz.xu.f.w v4, v8, v0.t
|
|
|
++ vfncvt.rtz.x.f.w v4, v8, v0.t
|
|
|
++ vfncvt.f.xu.w v4, v8, v0.t
|
|
|
++ vfncvt.f.x.w v4, v8, v0.t
|
|
|
++ vfncvt.f.f.w v4, v8, v0.t
|
|
|
++ vfncvt.rod.f.f.w v4, v8, v0.t
|
|
|
++
|
|
|
++ vredsum.vs v4, v8, v12
|
|
|
++ vredmaxu.vs v4, v8, v8
|
|
|
++ vredmax.vs v4, v8, v8
|
|
|
++ vredminu.vs v4, v8, v8
|
|
|
++ vredmin.vs v4, v8, v8
|
|
|
++ vredand.vs v4, v8, v12
|
|
|
++ vredor.vs v4, v8, v12
|
|
|
++ vredxor.vs v4, v8, v12
|
|
|
++ vredsum.vs v4, v8, v12, v0.t
|
|
|
++ vredmaxu.vs v4, v8, v8, v0.t
|
|
|
++ vredmax.vs v4, v8, v8, v0.t
|
|
|
++ vredminu.vs v4, v8, v8, v0.t
|
|
|
++ vredmin.vs v4, v8, v8, v0.t
|
|
|
++ vredand.vs v4, v8, v12, v0.t
|
|
|
++ vredor.vs v4, v8, v12, v0.t
|
|
|
++ vredxor.vs v4, v8, v12, v0.t
|
|
|
++
|
|
|
++ vwredsumu.vs v4, v8, v12
|
|
|
++ vwredsum.vs v4, v8, v12
|
|
|
++ vwredsumu.vs v4, v8, v12, v0.t
|
|
|
++ vwredsum.vs v4, v8, v12, v0.t
|
|
|
++
|
|
|
++ vfredosum.vs v4, v8, v12
|
|
|
++ vfredsum.vs v4, v8, v12
|
|
|
++ vfredmax.vs v4, v8, v12
|
|
|
++ vfredmin.vs v4, v8, v12
|
|
|
++ vfredosum.vs v4, v8, v12, v0.t
|
|
|
++ vfredsum.vs v4, v8, v12, v0.t
|
|
|
++ vfredmax.vs v4, v8, v12, v0.t
|
|
|
++ vfredmin.vs v4, v8, v12, v0.t
|
|
|
++
|
|
|
++ vfwredosum.vs v4, v8, v12
|
|
|
++ vfwredsum.vs v4, v8, v12
|
|
|
++ vfwredosum.vs v4, v8, v12, v0.t
|
|
|
++ vfwredsum.vs v4, v8, v12, v0.t
|
|
|
++
|
|
|
++ vmsbf.m v4, v8
|
|
|
++ vmsif.m v4, v8
|
|
|
++ vmsof.m v4, v8
|
|
|
++ viota.m v4, v8
|
|
|
++ vid.v v4
|
|
|
++
|
|
|
++ vmsbf.m v4, v8, v0.t
|
|
|
++ vmsif.m v4, v8, v0.t
|
|
|
++ vmsof.m v4, v8, v0.t
|
|
|
++ viota.m v4, v8, v0.t
|
|
|
++ vid.v v4, v0.t
|
|
|
++
|
|
|
++ vrgatherei16.vv v4, v8, v12
|
|
|
++ vrgatherei16.vv v4, v8, v12, v0.t
|
|
|
++
|
|
|
++ vmv1r.v v1, v2
|
|
|
++ vmv2r.v v2, v4
|
|
|
++ vmv4r.v v4, v8
|
|
|
++ vmv8r.v v0, v8
|
|
|
+diff --git a/gas/testsuite/gas/riscv/vector-insns-vmsgtvx.d b/gas/testsuite/gas/riscv/vector-insns-vmsgtvx.d
|
|
|
+new file mode 100644
|
|
|
+index 0000000000..207a410c28
|
|
|
+--- /dev/null
|
|
|
++++ b/gas/testsuite/gas/riscv/vector-insns-vmsgtvx.d
|
|
|
+@@ -0,0 +1,29 @@
|
|
|
++#as: -march=rv32iv0p10
|
|
|
++#objdump: -dr
|
|
|
++
|
|
|
++.*:[ ]+file format .*
|
|
|
++
|
|
|
++
|
|
|
++Disassembly of section .text:
|
|
|
++
|
|
|
++0+000 <.text>:
|
|
|
++[ ]+[0-9a-f]+:[ ]+6e85c257[ ]+vmslt.vx[ ]+v4,v8,a1
|
|
|
++[ ]+[0-9a-f]+:[ ]+76422257[ ]+vmnot.m[ ]+v4,v4
|
|
|
++[ ]+[0-9a-f]+:[ ]+6cc64457[ ]+vmslt.vx[ ]+v8,v12,a2,v0.t
|
|
|
++[ ]+[0-9a-f]+:[ ]+6e802457[ ]+vmxor.mm[ ]+v8,v8,v0
|
|
|
++[ ]+[0-9a-f]+:[ ]+6c85c657[ ]+vmslt.vx[ ]+v12,v8,a1,v0.t
|
|
|
++[ ]+[0-9a-f]+:[ ]+62062057[ ]+vmandnot.mm[ ]+v0,v0,v12
|
|
|
++[ ]+[0-9a-f]+:[ ]+6c85c657[ ]+vmslt.vx[ ]+v12,v8,a1,v0.t
|
|
|
++[ ]+[0-9a-f]+:[ ]+62062657[ ]+vmandnot.mm[ ]+v12,v0,v12
|
|
|
++[ ]+[0-9a-f]+:[ ]+62402257[ ]+vmandnot.mm[ ]+v4,v4,v0
|
|
|
++[ ]+[0-9a-f]+:[ ]+6ac22257[ ]+vmor.mm[ ]+v4,v12,v4
|
|
|
++[ ]+[0-9a-f]+:[ ]+6a85c257[ ]+vmsltu.vx[ ]+v4,v8,a1
|
|
|
++[ ]+[0-9a-f]+:[ ]+76422257[ ]+vmnot.m[ ]+v4,v4
|
|
|
++[ ]+[0-9a-f]+:[ ]+68c64457[ ]+vmsltu.vx[ ]+v8,v12,a2,v0.t
|
|
|
++[ ]+[0-9a-f]+:[ ]+6e802457[ ]+vmxor.mm[ ]+v8,v8,v0
|
|
|
++[ ]+[0-9a-f]+:[ ]+6885c657[ ]+vmsltu.vx[ ]+v12,v8,a1,v0.t
|
|
|
++[ ]+[0-9a-f]+:[ ]+62062057[ ]+vmandnot.mm[ ]+v0,v0,v12
|
|
|
++[ ]+[0-9a-f]+:[ ]+6885c657[ ]+vmsltu.vx[ ]+v12,v8,a1,v0.t
|
|
|
++[ ]+[0-9a-f]+:[ ]+62062657[ ]+vmandnot.mm[ ]+v12,v0,v12
|
|
|
++[ ]+[0-9a-f]+:[ ]+62402257[ ]+vmandnot.mm[ ]+v4,v4,v0
|
|
|
++[ ]+[0-9a-f]+:[ ]+6ac22257[ ]+vmor.mm[ ]+v4,v12,v4
|
|
|
+diff --git a/gas/testsuite/gas/riscv/vector-insns-vmsgtvx.s b/gas/testsuite/gas/riscv/vector-insns-vmsgtvx.s
|
|
|
+new file mode 100644
|
|
|
+index 0000000000..afbb7ccb36
|
|
|
+--- /dev/null
|
|
|
++++ b/gas/testsuite/gas/riscv/vector-insns-vmsgtvx.s
|
|
|
+@@ -0,0 +1,9 @@
|
|
|
++ vmsge.vx v4, v8, a1 # unmasked va >= x
|
|
|
++ vmsge.vx v8, v12, a2, v0.t # masked va >= x, vd != v0
|
|
|
++ vmsge.vx v0, v8, a1, v0.t, v12 # masked va >= x, vd == v0
|
|
|
++ vmsge.vx v4, v8, a1, v0.t, v12 # masked va >= x, any vd
|
|
|
++
|
|
|
++ vmsgeu.vx v4, v8, a1 # unmasked va >= x
|
|
|
++ vmsgeu.vx v8, v12, a2, v0.t # masked va >= x, vd != v0
|
|
|
++ vmsgeu.vx v0, v8, a1, v0.t, v12 # masked va >= x, vd == v0
|
|
|
++ vmsgeu.vx v4, v8, a1, v0.t, v12 # masked va >= x, any vd
|
|
|
+diff --git a/gas/testsuite/gas/riscv/vector-insns.d b/gas/testsuite/gas/riscv/vector-insns.d
|
|
|
+new file mode 100644
|
|
|
+index 0000000000..fe6a95cba5
|
|
|
+--- /dev/null
|
|
|
++++ b/gas/testsuite/gas/riscv/vector-insns.d
|
|
|
+@@ -0,0 +1,476 @@
|
|
|
++#as: -march=rv32iafv0p10
|
|
|
++#objdump: -dr
|
|
|
++
|
|
|
++.*:[ ]+file format .*
|
|
|
++
|
|
|
++
|
|
|
++Disassembly of section .text:
|
|
|
++
|
|
|
++0+000 <.text>:
|
|
|
++[ ]+[0-9a-f]+:[ ]+80c5f557[ ]+vsetvl[ ]+a0,a1,a2
|
|
|
++[ ]+[0-9a-f]+:[ ]+0005f557[ ]+vsetvli[ ]+a0,a1,e8,m1,tu,mu
|
|
|
++[ ]+[0-9a-f]+:[ ]+7ff5f557[ ]+vsetvli[ ]+a0,a1,2047
|
|
|
++[ ]+[0-9a-f]+:[ ]+0095f557[ ]+vsetvli[ ]+a0,a1,e16,m2,tu,mu
|
|
|
++[ ]+[0-9a-f]+:[ ]+02b5f557[ ]+vsetvli[ ]+a0,a1,e256,m8,tu,mu
|
|
|
++[ ]+[0-9a-f]+:[ ]+0335f557[ ]+vsetvli[ ]+a0,a1,e512,m8,tu,mu
|
|
|
++[ ]+[0-9a-f]+:[ ]+03b5f557[ ]+vsetvli[ ]+a0,a1,e1024,m8,tu,mu
|
|
|
++[ ]+[0-9a-f]+:[ ]+0385f557[ ]+vsetvli[ ]+a0,a1,e1024,m1,tu,mu
|
|
|
++[ ]+[0-9a-f]+:[ ]+03f5f557[ ]+vsetvli[ ]+a0,a1,e1024,mf2,tu,mu
|
|
|
++[ ]+[0-9a-f]+:[ ]+0365f557[ ]+vsetvli[ ]+a0,a1,e512,mf4,tu,mu
|
|
|
++[ ]+[0-9a-f]+:[ ]+02d5f557[ ]+vsetvli[ ]+a0,a1,e256,mf8,tu,mu
|
|
|
++[ ]+[0-9a-f]+:[ ]+0695f557[ ]+vsetvli[ ]+a0,a1,e256,m2,ta,mu
|
|
|
++[ ]+[0-9a-f]+:[ ]+0a95f557[ ]+vsetvli[ ]+a0,a1,e256,m2,tu,ma
|
|
|
++[ ]+[0-9a-f]+:[ ]+0295f557[ ]+vsetvli[ ]+a0,a1,e256,m2,tu,mu
|
|
|
++[ ]+[0-9a-f]+:[ ]+0295f557[ ]+vsetvli[ ]+a0,a1,e256,m2,tu,mu
|
|
|
++[ ]+[0-9a-f]+:[ ]+0e95f557[ ]+vsetvli[ ]+a0,a1,e256,m2,ta,ma
|
|
|
++[ ]+[0-9a-f]+:[ ]+0a95f557[ ]+vsetvli[ ]+a0,a1,e256,m2,tu,ma
|
|
|
++[ ]+[0-9a-f]+:[ ]+0695f557[ ]+vsetvli[ ]+a0,a1,e256,m2,ta,mu
|
|
|
++[ ]+[0-9a-f]+:[ ]+0295f557[ ]+vsetvli[ ]+a0,a1,e256,m2,tu,mu
|
|
|
++[ ]+[0-9a-f]+:[ ]+02050207[ ]+vle8.v[ ]+v4,\(a0\)
|
|
|
++[ ]+[0-9a-f]+:[ ]+02050207[ ]+vle8.v[ ]+v4,\(a0\)
|
|
|
++[ ]+[0-9a-f]+:[ ]+00050207[ ]+vle8.v[ ]+v4,\(a0\),v0.t
|
|
|
++[ ]+[0-9a-f]+:[ ]+02050227[ ]+vse8.v[ ]+v4,\(a0\)
|
|
|
++[ ]+[0-9a-f]+:[ ]+02050227[ ]+vse8.v[ ]+v4,\(a0\)
|
|
|
++[ ]+[0-9a-f]+:[ ]+00050227[ ]+vse8.v[ ]+v4,\(a0\),v0.t
|
|
|
++[ ]+[0-9a-f]+:[ ]+02055207[ ]+vle16.v[ ]+v4,\(a0\)
|
|
|
++[ ]+[0-9a-f]+:[ ]+02055207[ ]+vle16.v[ ]+v4,\(a0\)
|
|
|
++[ ]+[0-9a-f]+:[ ]+00055207[ ]+vle16.v[ ]+v4,\(a0\),v0.t
|
|
|
++[ ]+[0-9a-f]+:[ ]+02055227[ ]+vse16.v[ ]+v4,\(a0\)
|
|
|
++[ ]+[0-9a-f]+:[ ]+02055227[ ]+vse16.v[ ]+v4,\(a0\)
|
|
|
++[ ]+[0-9a-f]+:[ ]+00055227[ ]+vse16.v[ ]+v4,\(a0\),v0.t
|
|
|
++[ ]+[0-9a-f]+:[ ]+02056207[ ]+vle32.v[ ]+v4,\(a0\)
|
|
|
++[ ]+[0-9a-f]+:[ ]+02056207[ ]+vle32.v[ ]+v4,\(a0\)
|
|
|
++[ ]+[0-9a-f]+:[ ]+00056207[ ]+vle32.v[ ]+v4,\(a0\),v0.t
|
|
|
++[ ]+[0-9a-f]+:[ ]+02056227[ ]+vse32.v[ ]+v4,\(a0\)
|
|
|
++[ ]+[0-9a-f]+:[ ]+02056227[ ]+vse32.v[ ]+v4,\(a0\)
|
|
|
++[ ]+[0-9a-f]+:[ ]+00056227[ ]+vse32.v[ ]+v4,\(a0\),v0.t
|
|
|
++[ ]+[0-9a-f]+:[ ]+02057207[ ]+vle64.v[ ]+v4,\(a0\)
|
|
|
++[ ]+[0-9a-f]+:[ ]+02057207[ ]+vle64.v[ ]+v4,\(a0\)
|
|
|
++[ ]+[0-9a-f]+:[ ]+00057207[ ]+vle64.v[ ]+v4,\(a0\),v0.t
|
|
|
++[ ]+[0-9a-f]+:[ ]+02057227[ ]+vse64.v[ ]+v4,\(a0\)
|
|
|
++[ ]+[0-9a-f]+:[ ]+02057227[ ]+vse64.v[ ]+v4,\(a0\)
|
|
|
++[ ]+[0-9a-f]+:[ ]+00057227[ ]+vse64.v[ ]+v4,\(a0\),v0.t
|
|
|
++[ ]+[0-9a-f]+:[ ]+0ab50207[ ]+vlse8.v[ ]+v4,\(a0\),a1
|
|
|
++[ ]+[0-9a-f]+:[ ]+0ab50207[ ]+vlse8.v[ ]+v4,\(a0\),a1
|
|
|
++[ ]+[0-9a-f]+:[ ]+08b50207[ ]+vlse8.v[ ]+v4,\(a0\),a1,v0.t
|
|
|
++[ ]+[0-9a-f]+:[ ]+0ab50227[ ]+vsse8.v[ ]+v4,\(a0\),a1
|
|
|
++[ ]+[0-9a-f]+:[ ]+0ab50227[ ]+vsse8.v[ ]+v4,\(a0\),a1
|
|
|
++[ ]+[0-9a-f]+:[ ]+08b50227[ ]+vsse8.v[ ]+v4,\(a0\),a1,v0.t
|
|
|
++[ ]+[0-9a-f]+:[ ]+0ab55207[ ]+vlse16.v[ ]+v4,\(a0\),a1
|
|
|
++[ ]+[0-9a-f]+:[ ]+0ab55207[ ]+vlse16.v[ ]+v4,\(a0\),a1
|
|
|
++[ ]+[0-9a-f]+:[ ]+08b55207[ ]+vlse16.v[ ]+v4,\(a0\),a1,v0.t
|
|
|
++[ ]+[0-9a-f]+:[ ]+0ab55227[ ]+vsse16.v[ ]+v4,\(a0\),a1
|
|
|
++[ ]+[0-9a-f]+:[ ]+0ab55227[ ]+vsse16.v[ ]+v4,\(a0\),a1
|
|
|
++[ ]+[0-9a-f]+:[ ]+08b55227[ ]+vsse16.v[ ]+v4,\(a0\),a1,v0.t
|
|
|
++[ ]+[0-9a-f]+:[ ]+0ab56207[ ]+vlse32.v[ ]+v4,\(a0\),a1
|
|
|
++[ ]+[0-9a-f]+:[ ]+0ab56207[ ]+vlse32.v[ ]+v4,\(a0\),a1
|
|
|
++[ ]+[0-9a-f]+:[ ]+08b56207[ ]+vlse32.v[ ]+v4,\(a0\),a1,v0.t
|
|
|
++[ ]+[0-9a-f]+:[ ]+0ab56227[ ]+vsse32.v[ ]+v4,\(a0\),a1
|
|
|
++[ ]+[0-9a-f]+:[ ]+0ab56227[ ]+vsse32.v[ ]+v4,\(a0\),a1
|
|
|
++[ ]+[0-9a-f]+:[ ]+08b56227[ ]+vsse32.v[ ]+v4,\(a0\),a1,v0.t
|
|
|
++[ ]+[0-9a-f]+:[ ]+0ab57207[ ]+vlse64.v[ ]+v4,\(a0\),a1
|
|
|
++[ ]+[0-9a-f]+:[ ]+0ab57207[ ]+vlse64.v[ ]+v4,\(a0\),a1
|
|
|
++[ ]+[0-9a-f]+:[ ]+08b57207[ ]+vlse64.v[ ]+v4,\(a0\),a1,v0.t
|
|
|
++[ ]+[0-9a-f]+:[ ]+0ab57227[ ]+vsse64.v[ ]+v4,\(a0\),a1
|
|
|
++[ ]+[0-9a-f]+:[ ]+0ab57227[ ]+vsse64.v[ ]+v4,\(a0\),a1
|
|
|
++[ ]+[0-9a-f]+:[ ]+08b57227[ ]+vsse64.v[ ]+v4,\(a0\),a1,v0.t
|
|
|
++[ ]+[0-9a-f]+:[ ]+0ec50207[ ]+vloxei8.v[ ]+v4,\(a0\),v12
|
|
|
++[ ]+[0-9a-f]+:[ ]+0ec50207[ ]+vloxei8.v[ ]+v4,\(a0\),v12
|
|
|
++[ ]+[0-9a-f]+:[ ]+0cc50207[ ]+vloxei8.v[ ]+v4,\(a0\),v12,v0.t
|
|
|
++[ ]+[0-9a-f]+:[ ]+0ec50227[ ]+vsoxei8.v[ ]+v4,\(a0\),v12
|
|
|
++[ ]+[0-9a-f]+:[ ]+0ec50227[ ]+vsoxei8.v[ ]+v4,\(a0\),v12
|
|
|
++[ ]+[0-9a-f]+:[ ]+0cc50227[ ]+vsoxei8.v[ ]+v4,\(a0\),v12,v0.t
|
|
|
++[ ]+[0-9a-f]+:[ ]+0ec55207[ ]+vloxei16.v[ ]+v4,\(a0\),v12
|
|
|
++[ ]+[0-9a-f]+:[ ]+0ec55207[ ]+vloxei16.v[ ]+v4,\(a0\),v12
|
|
|
++[ ]+[0-9a-f]+:[ ]+0cc55207[ ]+vloxei16.v[ ]+v4,\(a0\),v12,v0.t
|
|
|
++[ ]+[0-9a-f]+:[ ]+0ec55227[ ]+vsoxei16.v[ ]+v4,\(a0\),v12
|
|
|
++[ ]+[0-9a-f]+:[ ]+0ec55227[ ]+vsoxei16.v[ ]+v4,\(a0\),v12
|
|
|
++[ ]+[0-9a-f]+:[ ]+0cc55227[ ]+vsoxei16.v[ ]+v4,\(a0\),v12,v0.t
|
|
|
++[ ]+[0-9a-f]+:[ ]+0ec56207[ ]+vloxei32.v[ ]+v4,\(a0\),v12
|
|
|
++[ ]+[0-9a-f]+:[ ]+0ec56207[ ]+vloxei32.v[ ]+v4,\(a0\),v12
|
|
|
++[ ]+[0-9a-f]+:[ ]+0cc56207[ ]+vloxei32.v[ ]+v4,\(a0\),v12,v0.t
|
|
|
++[ ]+[0-9a-f]+:[ ]+0ec56227[ ]+vsoxei32.v[ ]+v4,\(a0\),v12
|
|
|
++[ ]+[0-9a-f]+:[ ]+0ec56227[ ]+vsoxei32.v[ ]+v4,\(a0\),v12
|
|
|
++[ ]+[0-9a-f]+:[ ]+0cc56227[ ]+vsoxei32.v[ ]+v4,\(a0\),v12,v0.t
|
|
|
++[ ]+[0-9a-f]+:[ ]+0ec57207[ ]+vloxei64.v[ ]+v4,\(a0\),v12
|
|
|
++[ ]+[0-9a-f]+:[ ]+0ec57207[ ]+vloxei64.v[ ]+v4,\(a0\),v12
|
|
|
++[ ]+[0-9a-f]+:[ ]+0cc57207[ ]+vloxei64.v[ ]+v4,\(a0\),v12,v0.t
|
|
|
++[ ]+[0-9a-f]+:[ ]+0ec57227[ ]+vsoxei64.v[ ]+v4,\(a0\),v12
|
|
|
++[ ]+[0-9a-f]+:[ ]+0ec57227[ ]+vsoxei64.v[ ]+v4,\(a0\),v12
|
|
|
++[ ]+[0-9a-f]+:[ ]+0cc57227[ ]+vsoxei64.v[ ]+v4,\(a0\),v12,v0.t
|
|
|
++[ ]+[0-9a-f]+:[ ]+0e804257[ ]+vneg.v[ ]+v4,v8
|
|
|
++[ ]+[0-9a-f]+:[ ]+0c804257[ ]+vneg.v[ ]+v4,v8,v0.t
|
|
|
++[ ]+[0-9a-f]+:[ ]+02860257[ ]+vadd.vv[ ]+v4,v8,v12
|
|
|
++[ ]+[0-9a-f]+:[ ]+0285c257[ ]+vadd.vx[ ]+v4,v8,a1
|
|
|
++[ ]+[0-9a-f]+:[ ]+0287b257[ ]+vadd.vi[ ]+v4,v8,15
|
|
|
++[ ]+[0-9a-f]+:[ ]+02883257[ ]+vadd.vi[ ]+v4,v8,-16
|
|
|
++[ ]+[0-9a-f]+:[ ]+00860257[ ]+vadd.vv[ ]+v4,v8,v12,v0.t
|
|
|
++[ ]+[0-9a-f]+:[ ]+0085c257[ ]+vadd.vx[ ]+v4,v8,a1,v0.t
|
|
|
++[ ]+[0-9a-f]+:[ ]+0087b257[ ]+vadd.vi[ ]+v4,v8,15,v0.t
|
|
|
++[ ]+[0-9a-f]+:[ ]+00883257[ ]+vadd.vi[ ]+v4,v8,-16,v0.t
|
|
|
++[ ]+[0-9a-f]+:[ ]+0a860257[ ]+vsub.vv[ ]+v4,v8,v12
|
|
|
++[ ]+[0-9a-f]+:[ ]+0a85c257[ ]+vsub.vx[ ]+v4,v8,a1
|
|
|
++[ ]+[0-9a-f]+:[ ]+0e85c257[ ]+vrsub.vx[ ]+v4,v8,a1
|
|
|
++[ ]+[0-9a-f]+:[ ]+0e87b257[ ]+vrsub.vi[ ]+v4,v8,15
|
|
|
++[ ]+[0-9a-f]+:[ ]+0e883257[ ]+vrsub.vi[ ]+v4,v8,-16
|
|
|
++[ ]+[0-9a-f]+:[ ]+08860257[ ]+vsub.vv[ ]+v4,v8,v12,v0.t
|
|
|
++[ ]+[0-9a-f]+:[ ]+0885c257[ ]+vsub.vx[ ]+v4,v8,a1,v0.t
|
|
|
++[ ]+[0-9a-f]+:[ ]+0c85c257[ ]+vrsub.vx[ ]+v4,v8,a1,v0.t
|
|
|
++[ ]+[0-9a-f]+:[ ]+0c87b257[ ]+vrsub.vi[ ]+v4,v8,15,v0.t
|
|
|
++[ ]+[0-9a-f]+:[ ]+0c883257[ ]+vrsub.vi[ ]+v4,v8,-16,v0.t
|
|
|
++[ ]+[0-9a-f]+:[ ]+4a832257[ ]+vzext.vf2[ ]+v4,v8
|
|
|
++[ ]+[0-9a-f]+:[ ]+48832257[ ]+vzext.vf2[ ]+v4,v8,v0.t
|
|
|
++[ ]+[0-9a-f]+:[ ]+4a83a257[ ]+vsext.vf2[ ]+v4,v8
|
|
|
++[ ]+[0-9a-f]+:[ ]+4883a257[ ]+vsext.vf2[ ]+v4,v8,v0.t
|
|
|
++[ ]+[0-9a-f]+:[ ]+4a822257[ ]+vzext.vf4[ ]+v4,v8
|
|
|
++[ ]+[0-9a-f]+:[ ]+48822257[ ]+vzext.vf4[ ]+v4,v8,v0.t
|
|
|
++[ ]+[0-9a-f]+:[ ]+4a82a257[ ]+vsext.vf4[ ]+v4,v8
|
|
|
++[ ]+[0-9a-f]+:[ ]+4882a257[ ]+vsext.vf4[ ]+v4,v8,v0.t
|
|
|
++[ ]+[0-9a-f]+:[ ]+4a812257[ ]+vzext.vf8[ ]+v4,v8
|
|
|
++[ ]+[0-9a-f]+:[ ]+48812257[ ]+vzext.vf8[ ]+v4,v8,v0.t
|
|
|
++[ ]+[0-9a-f]+:[ ]+4a81a257[ ]+vsext.vf8[ ]+v4,v8
|
|
|
++[ ]+[0-9a-f]+:[ ]+4881a257[ ]+vsext.vf8[ ]+v4,v8,v0.t
|
|
|
++[ ]+[0-9a-f]+:[ ]+40860257[ ]+vadc.vvm[ ]+v4,v8,v12,v0
|
|
|
++[ ]+[0-9a-f]+:[ ]+4085c257[ ]+vadc.vxm[ ]+v4,v8,a1,v0
|
|
|
++[ ]+[0-9a-f]+:[ ]+4087b257[ ]+vadc.vim[ ]+v4,v8,15,v0
|
|
|
++[ ]+[0-9a-f]+:[ ]+40883257[ ]+vadc.vim[ ]+v4,v8,-16,v0
|
|
|
++[ ]+[0-9a-f]+:[ ]+44860257[ ]+vmadc.vvm[ ]+v4,v8,v12,v0
|
|
|
++[ ]+[0-9a-f]+:[ ]+4485c257[ ]+vmadc.vxm[ ]+v4,v8,a1,v0
|
|
|
++[ ]+[0-9a-f]+:[ ]+4487b257[ ]+vmadc.vim[ ]+v4,v8,15,v0
|
|
|
++[ ]+[0-9a-f]+:[ ]+44883257[ ]+vmadc.vim[ ]+v4,v8,-16,v0
|
|
|
++[ ]+[0-9a-f]+:[ ]+46860257[ ]+vmadc.vv[ ]+v4,v8,v12
|
|
|
++[ ]+[0-9a-f]+:[ ]+4685c257[ ]+vmadc.vx[ ]+v4,v8,a1
|
|
|
++[ ]+[0-9a-f]+:[ ]+4687b257[ ]+vmadc.vi[ ]+v4,v8,15
|
|
|
++[ ]+[0-9a-f]+:[ ]+46883257[ ]+vmadc.vi[ ]+v4,v8,-16
|
|
|
++[ ]+[0-9a-f]+:[ ]+48860257[ ]+vsbc.vvm[ ]+v4,v8,v12,v0
|
|
|
++[ ]+[0-9a-f]+:[ ]+4885c257[ ]+vsbc.vxm[ ]+v4,v8,a1,v0
|
|
|
++[ ]+[0-9a-f]+:[ ]+4c860257[ ]+vmsbc.vvm[ ]+v4,v8,v12,v0
|
|
|
++[ ]+[0-9a-f]+:[ ]+4c85c257[ ]+vmsbc.vxm[ ]+v4,v8,a1,v0
|
|
|
++[ ]+[0-9a-f]+:[ ]+4e860257[ ]+vmsbc.vv[ ]+v4,v8,v12
|
|
|
++[ ]+[0-9a-f]+:[ ]+4e85c257[ ]+vmsbc.vx[ ]+v4,v8,a1
|
|
|
++[ ]+[0-9a-f]+:[ ]+2e8fb257[ ]+vnot.v[ ]+v4,v8
|
|
|
++[ ]+[0-9a-f]+:[ ]+2c8fb257[ ]+vnot.v[ ]+v4,v8,v0.t
|
|
|
++[ ]+[0-9a-f]+:[ ]+26860257[ ]+vand.vv[ ]+v4,v8,v12
|
|
|
++[ ]+[0-9a-f]+:[ ]+2685c257[ ]+vand.vx[ ]+v4,v8,a1
|
|
|
++[ ]+[0-9a-f]+:[ ]+2687b257[ ]+vand.vi[ ]+v4,v8,15
|
|
|
++[ ]+[0-9a-f]+:[ ]+26883257[ ]+vand.vi[ ]+v4,v8,-16
|
|
|
++[ ]+[0-9a-f]+:[ ]+24860257[ ]+vand.vv[ ]+v4,v8,v12,v0.t
|
|
|
++[ ]+[0-9a-f]+:[ ]+2485c257[ ]+vand.vx[ ]+v4,v8,a1,v0.t
|
|
|
++[ ]+[0-9a-f]+:[ ]+2487b257[ ]+vand.vi[ ]+v4,v8,15,v0.t
|
|
|
++[ ]+[0-9a-f]+:[ ]+24883257[ ]+vand.vi[ ]+v4,v8,-16,v0.t
|
|
|
++[ ]+[0-9a-f]+:[ ]+2a860257[ ]+vor.vv[ ]+v4,v8,v12
|
|
|
++[ ]+[0-9a-f]+:[ ]+2a85c257[ ]+vor.vx[ ]+v4,v8,a1
|
|
|
++[ ]+[0-9a-f]+:[ ]+2a87b257[ ]+vor.vi[ ]+v4,v8,15
|
|
|
++[ ]+[0-9a-f]+:[ ]+2a883257[ ]+vor.vi[ ]+v4,v8,-16
|
|
|
++[ ]+[0-9a-f]+:[ ]+28860257[ ]+vor.vv[ ]+v4,v8,v12,v0.t
|
|
|
++[ ]+[0-9a-f]+:[ ]+2885c257[ ]+vor.vx[ ]+v4,v8,a1,v0.t
|
|
|
++[ ]+[0-9a-f]+:[ ]+2887b257[ ]+vor.vi[ ]+v4,v8,15,v0.t
|
|
|
++[ ]+[0-9a-f]+:[ ]+28883257[ ]+vor.vi[ ]+v4,v8,-16,v0.t
|
|
|
++[ ]+[0-9a-f]+:[ ]+2e860257[ ]+vxor.vv[ ]+v4,v8,v12
|
|
|
++[ ]+[0-9a-f]+:[ ]+2e85c257[ ]+vxor.vx[ ]+v4,v8,a1
|
|
|
++[ ]+[0-9a-f]+:[ ]+2e87b257[ ]+vxor.vi[ ]+v4,v8,15
|
|
|
++[ ]+[0-9a-f]+:[ ]+2e883257[ ]+vxor.vi[ ]+v4,v8,-16
|
|
|
++[ ]+[0-9a-f]+:[ ]+2c860257[ ]+vxor.vv[ ]+v4,v8,v12,v0.t
|
|
|
++[ ]+[0-9a-f]+:[ ]+2c85c257[ ]+vxor.vx[ ]+v4,v8,a1,v0.t
|
|
|
++[ ]+[0-9a-f]+:[ ]+2c87b257[ ]+vxor.vi[ ]+v4,v8,15,v0.t
|
|
|
++[ ]+[0-9a-f]+:[ ]+2c883257[ ]+vxor.vi[ ]+v4,v8,-16,v0.t
|
|
|
++[ ]+[0-9a-f]+:[ ]+6ec40257[ ]+vmslt.vv[ ]+v4,v12,v8
|
|
|
++[ ]+[0-9a-f]+:[ ]+6ac40257[ ]+vmsltu.vv[ ]+v4,v12,v8
|
|
|
++[ ]+[0-9a-f]+:[ ]+76c40257[ ]+vmsle.vv[ ]+v4,v12,v8
|
|
|
++[ ]+[0-9a-f]+:[ ]+72c40257[ ]+vmsleu.vv[ ]+v4,v12,v8
|
|
|
++[ ]+[0-9a-f]+:[ ]+6cc40257[ ]+vmslt.vv[ ]+v4,v12,v8,v0.t
|
|
|
++[ ]+[0-9a-f]+:[ ]+68c40257[ ]+vmsltu.vv[ ]+v4,v12,v8,v0.t
|
|
|
++[ ]+[0-9a-f]+:[ ]+74c40257[ ]+vmsle.vv[ ]+v4,v12,v8,v0.t
|
|
|
++[ ]+[0-9a-f]+:[ ]+70c40257[ ]+vmsleu.vv[ ]+v4,v12,v8,v0.t
|
|
|
++[ ]+[0-9a-f]+:[ ]+7687b257[ ]+vmsle.vi[ ]+v4,v8,15
|
|
|
++[ ]+[0-9a-f]+:[ ]+76883257[ ]+vmsle.vi[ ]+v4,v8,-16
|
|
|
++[ ]+[0-9a-f]+:[ ]+7287b257[ ]+vmsleu.vi[ ]+v4,v8,15
|
|
|
++[ ]+[0-9a-f]+:[ ]+72883257[ ]+vmsleu.vi[ ]+v4,v8,-16
|
|
|
++[ ]+[0-9a-f]+:[ ]+7e87b257[ ]+vmsgt.vi[ ]+v4,v8,15
|
|
|
++[ ]+[0-9a-f]+:[ ]+7e883257[ ]+vmsgt.vi[ ]+v4,v8,-16
|
|
|
++[ ]+[0-9a-f]+:[ ]+7a87b257[ ]+vmsgtu.vi[ ]+v4,v8,15
|
|
|
++[ ]+[0-9a-f]+:[ ]+7a883257[ ]+vmsgtu.vi[ ]+v4,v8,-16
|
|
|
++[ ]+[0-9a-f]+:[ ]+7487b257[ ]+vmsle.vi[ ]+v4,v8,15,v0.t
|
|
|
++[ ]+[0-9a-f]+:[ ]+74883257[ ]+vmsle.vi[ ]+v4,v8,-16,v0.t
|
|
|
++[ ]+[0-9a-f]+:[ ]+7087b257[ ]+vmsleu.vi[ ]+v4,v8,15,v0.t
|
|
|
++[ ]+[0-9a-f]+:[ ]+70883257[ ]+vmsleu.vi[ ]+v4,v8,-16,v0.t
|
|
|
++[ ]+[0-9a-f]+:[ ]+7c87b257[ ]+vmsgt.vi[ ]+v4,v8,15,v0.t
|
|
|
++[ ]+[0-9a-f]+:[ ]+7c883257[ ]+vmsgt.vi[ ]+v4,v8,-16,v0.t
|
|
|
++[ ]+[0-9a-f]+:[ ]+7887b257[ ]+vmsgtu.vi[ ]+v4,v8,15,v0.t
|
|
|
++[ ]+[0-9a-f]+:[ ]+78883257[ ]+vmsgtu.vi[ ]+v4,v8,-16,v0.t
|
|
|
++[ ]+[0-9a-f]+:[ ]+62860257[ ]+vmseq.vv[ ]+v4,v8,v12
|
|
|
++[ ]+[0-9a-f]+:[ ]+6285c257[ ]+vmseq.vx[ ]+v4,v8,a1
|
|
|
++[ ]+[0-9a-f]+:[ ]+6287b257[ ]+vmseq.vi[ ]+v4,v8,15
|
|
|
++[ ]+[0-9a-f]+:[ ]+62883257[ ]+vmseq.vi[ ]+v4,v8,-16
|
|
|
++[ ]+[0-9a-f]+:[ ]+60860257[ ]+vmseq.vv[ ]+v4,v8,v12,v0.t
|
|
|
++[ ]+[0-9a-f]+:[ ]+6085c257[ ]+vmseq.vx[ ]+v4,v8,a1,v0.t
|
|
|
++[ ]+[0-9a-f]+:[ ]+6087b257[ ]+vmseq.vi[ ]+v4,v8,15,v0.t
|
|
|
++[ ]+[0-9a-f]+:[ ]+60883257[ ]+vmseq.vi[ ]+v4,v8,-16,v0.t
|
|
|
++[ ]+[0-9a-f]+:[ ]+66860257[ ]+vmsne.vv[ ]+v4,v8,v12
|
|
|
++[ ]+[0-9a-f]+:[ ]+6685c257[ ]+vmsne.vx[ ]+v4,v8,a1
|
|
|
++[ ]+[0-9a-f]+:[ ]+6687b257[ ]+vmsne.vi[ ]+v4,v8,15
|
|
|
++[ ]+[0-9a-f]+:[ ]+66883257[ ]+vmsne.vi[ ]+v4,v8,-16
|
|
|
++[ ]+[0-9a-f]+:[ ]+64860257[ ]+vmsne.vv[ ]+v4,v8,v12,v0.t
|
|
|
++[ ]+[0-9a-f]+:[ ]+6485c257[ ]+vmsne.vx[ ]+v4,v8,a1,v0.t
|
|
|
++[ ]+[0-9a-f]+:[ ]+6487b257[ ]+vmsne.vi[ ]+v4,v8,15,v0.t
|
|
|
++[ ]+[0-9a-f]+:[ ]+64883257[ ]+vmsne.vi[ ]+v4,v8,-16,v0.t
|
|
|
++[ ]+[0-9a-f]+:[ ]+6a860257[ ]+vmsltu.vv[ ]+v4,v8,v12
|
|
|
++[ ]+[0-9a-f]+:[ ]+6a85c257[ ]+vmsltu.vx[ ]+v4,v8,a1
|
|
|
++[ ]+[0-9a-f]+:[ ]+68860257[ ]+vmsltu.vv[ ]+v4,v8,v12,v0.t
|
|
|
++[ ]+[0-9a-f]+:[ ]+6885c257[ ]+vmsltu.vx[ ]+v4,v8,a1,v0.t
|
|
|
++[ ]+[0-9a-f]+:[ ]+6e860257[ ]+vmslt.vv[ ]+v4,v8,v12
|
|
|
++[ ]+[0-9a-f]+:[ ]+6e85c257[ ]+vmslt.vx[ ]+v4,v8,a1
|
|
|
++[ ]+[0-9a-f]+:[ ]+6c860257[ ]+vmslt.vv[ ]+v4,v8,v12,v0.t
|
|
|
++[ ]+[0-9a-f]+:[ ]+6c85c257[ ]+vmslt.vx[ ]+v4,v8,a1,v0.t
|
|
|
++[ ]+[0-9a-f]+:[ ]+72860257[ ]+vmsleu.vv[ ]+v4,v8,v12
|
|
|
++[ ]+[0-9a-f]+:[ ]+7285c257[ ]+vmsleu.vx[ ]+v4,v8,a1
|
|
|
++[ ]+[0-9a-f]+:[ ]+7287b257[ ]+vmsleu.vi[ ]+v4,v8,15
|
|
|
++[ ]+[0-9a-f]+:[ ]+72883257[ ]+vmsleu.vi[ ]+v4,v8,-16
|
|
|
++[ ]+[0-9a-f]+:[ ]+70860257[ ]+vmsleu.vv[ ]+v4,v8,v12,v0.t
|
|
|
++[ ]+[0-9a-f]+:[ ]+7085c257[ ]+vmsleu.vx[ ]+v4,v8,a1,v0.t
|
|
|
++[ ]+[0-9a-f]+:[ ]+7087b257[ ]+vmsleu.vi[ ]+v4,v8,15,v0.t
|
|
|
++[ ]+[0-9a-f]+:[ ]+70883257[ ]+vmsleu.vi[ ]+v4,v8,-16,v0.t
|
|
|
++[ ]+[0-9a-f]+:[ ]+76860257[ ]+vmsle.vv[ ]+v4,v8,v12
|
|
|
++[ ]+[0-9a-f]+:[ ]+7685c257[ ]+vmsle.vx[ ]+v4,v8,a1
|
|
|
++[ ]+[0-9a-f]+:[ ]+7687b257[ ]+vmsle.vi[ ]+v4,v8,15
|
|
|
++[ ]+[0-9a-f]+:[ ]+76883257[ ]+vmsle.vi[ ]+v4,v8,-16
|
|
|
++[ ]+[0-9a-f]+:[ ]+74860257[ ]+vmsle.vv[ ]+v4,v8,v12,v0.t
|
|
|
++[ ]+[0-9a-f]+:[ ]+7485c257[ ]+vmsle.vx[ ]+v4,v8,a1,v0.t
|
|
|
++[ ]+[0-9a-f]+:[ ]+7487b257[ ]+vmsle.vi[ ]+v4,v8,15,v0.t
|
|
|
++[ ]+[0-9a-f]+:[ ]+74883257[ ]+vmsle.vi[ ]+v4,v8,-16,v0.t
|
|
|
++[ ]+[0-9a-f]+:[ ]+7a85c257[ ]+vmsgtu.vx[ ]+v4,v8,a1
|
|
|
++[ ]+[0-9a-f]+:[ ]+7a87b257[ ]+vmsgtu.vi[ ]+v4,v8,15
|
|
|
++[ ]+[0-9a-f]+:[ ]+7a883257[ ]+vmsgtu.vi[ ]+v4,v8,-16
|
|
|
++[ ]+[0-9a-f]+:[ ]+7885c257[ ]+vmsgtu.vx[ ]+v4,v8,a1,v0.t
|
|
|
++[ ]+[0-9a-f]+:[ ]+7887b257[ ]+vmsgtu.vi[ ]+v4,v8,15,v0.t
|
|
|
++[ ]+[0-9a-f]+:[ ]+78883257[ ]+vmsgtu.vi[ ]+v4,v8,-16,v0.t
|
|
|
++[ ]+[0-9a-f]+:[ ]+7e85c257[ ]+vmsgt.vx[ ]+v4,v8,a1
|
|
|
++[ ]+[0-9a-f]+:[ ]+7e87b257[ ]+vmsgt.vi[ ]+v4,v8,15
|
|
|
++[ ]+[0-9a-f]+:[ ]+7e883257[ ]+vmsgt.vi[ ]+v4,v8,-16
|
|
|
++[ ]+[0-9a-f]+:[ ]+7c85c257[ ]+vmsgt.vx[ ]+v4,v8,a1,v0.t
|
|
|
++[ ]+[0-9a-f]+:[ ]+7c87b257[ ]+vmsgt.vi[ ]+v4,v8,15,v0.t
|
|
|
++[ ]+[0-9a-f]+:[ ]+7c883257[ ]+vmsgt.vi[ ]+v4,v8,-16,v0.t
|
|
|
++[ ]+[0-9a-f]+:[ ]+12860257[ ]+vminu.vv[ ]+v4,v8,v12
|
|
|
++[ ]+[0-9a-f]+:[ ]+1285c257[ ]+vminu.vx[ ]+v4,v8,a1
|
|
|
++[ ]+[0-9a-f]+:[ ]+10860257[ ]+vminu.vv[ ]+v4,v8,v12,v0.t
|
|
|
++[ ]+[0-9a-f]+:[ ]+1085c257[ ]+vminu.vx[ ]+v4,v8,a1,v0.t
|
|
|
++[ ]+[0-9a-f]+:[ ]+16860257[ ]+vmin.vv[ ]+v4,v8,v12
|
|
|
++[ ]+[0-9a-f]+:[ ]+1685c257[ ]+vmin.vx[ ]+v4,v8,a1
|
|
|
++[ ]+[0-9a-f]+:[ ]+14860257[ ]+vmin.vv[ ]+v4,v8,v12,v0.t
|
|
|
++[ ]+[0-9a-f]+:[ ]+1485c257[ ]+vmin.vx[ ]+v4,v8,a1,v0.t
|
|
|
++[ ]+[0-9a-f]+:[ ]+1a860257[ ]+vmaxu.vv[ ]+v4,v8,v12
|
|
|
++[ ]+[0-9a-f]+:[ ]+1a85c257[ ]+vmaxu.vx[ ]+v4,v8,a1
|
|
|
++[ ]+[0-9a-f]+:[ ]+18860257[ ]+vmaxu.vv[ ]+v4,v8,v12,v0.t
|
|
|
++[ ]+[0-9a-f]+:[ ]+1885c257[ ]+vmaxu.vx[ ]+v4,v8,a1,v0.t
|
|
|
++[ ]+[0-9a-f]+:[ ]+1e860257[ ]+vmax.vv[ ]+v4,v8,v12
|
|
|
++[ ]+[0-9a-f]+:[ ]+1e85c257[ ]+vmax.vx[ ]+v4,v8,a1
|
|
|
++[ ]+[0-9a-f]+:[ ]+1c860257[ ]+vmax.vv[ ]+v4,v8,v12,v0.t
|
|
|
++[ ]+[0-9a-f]+:[ ]+1c85c257[ ]+vmax.vx[ ]+v4,v8,a1,v0.t
|
|
|
++[ ]+[0-9a-f]+:[ ]+96862257[ ]+vmul.vv[ ]+v4,v8,v12
|
|
|
++[ ]+[0-9a-f]+:[ ]+9685e257[ ]+vmul.vx[ ]+v4,v8,a1
|
|
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++[ ]+[0-9a-f]+:[ ]+94862257[ ]+vmul.vv[ ]+v4,v8,v12,v0.t
|
|
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++[ ]+[0-9a-f]+:[ ]+9485e257[ ]+vmul.vx[ ]+v4,v8,a1,v0.t
|
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++[ ]+[0-9a-f]+:[ ]+9e862257[ ]+vmulh.vv[ ]+v4,v8,v12
|
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|
++[ ]+[0-9a-f]+:[ ]+9e85e257[ ]+vmulh.vx[ ]+v4,v8,a1
|
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++[ ]+[0-9a-f]+:[ ]+9c862257[ ]+vmulh.vv[ ]+v4,v8,v12,v0.t
|
|
|
++[ ]+[0-9a-f]+:[ ]+9c85e257[ ]+vmulh.vx[ ]+v4,v8,a1,v0.t
|
|
|
++[ ]+[0-9a-f]+:[ ]+92862257[ ]+vmulhu.vv[ ]+v4,v8,v12
|
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++[ ]+[0-9a-f]+:[ ]+9285e257[ ]+vmulhu.vx[ ]+v4,v8,a1
|
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|
++[ ]+[0-9a-f]+:[ ]+90862257[ ]+vmulhu.vv[ ]+v4,v8,v12,v0.t
|
|
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++[ ]+[0-9a-f]+:[ ]+9085e257[ ]+vmulhu.vx[ ]+v4,v8,a1,v0.t
|
|
|
++[ ]+[0-9a-f]+:[ ]+9a862257[ ]+vmulhsu.vv[ ]+v4,v8,v12
|
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|
++[ ]+[0-9a-f]+:[ ]+9a85e257[ ]+vmulhsu.vx[ ]+v4,v8,a1
|
|
|
++[ ]+[0-9a-f]+:[ ]+98862257[ ]+vmulhsu.vv[ ]+v4,v8,v12,v0.t
|
|
|
++[ ]+[0-9a-f]+:[ ]+9885e257[ ]+vmulhsu.vx[ ]+v4,v8,a1,v0.t
|
|
|
++[ ]+[0-9a-f]+:[ ]+b6862257[ ]+vmacc.vv[ ]+v4,v12,v8
|
|
|
++[ ]+[0-9a-f]+:[ ]+b685e257[ ]+vmacc.vx[ ]+v4,a1,v8
|
|
|
++[ ]+[0-9a-f]+:[ ]+b4862257[ ]+vmacc.vv[ ]+v4,v12,v8,v0.t
|
|
|
++[ ]+[0-9a-f]+:[ ]+b485e257[ ]+vmacc.vx[ ]+v4,a1,v8,v0.t
|
|
|
++[ ]+[0-9a-f]+:[ ]+be862257[ ]+vnmsac.vv[ ]+v4,v12,v8
|
|
|
++[ ]+[0-9a-f]+:[ ]+be85e257[ ]+vnmsac.vx[ ]+v4,a1,v8
|
|
|
++[ ]+[0-9a-f]+:[ ]+bc862257[ ]+vnmsac.vv[ ]+v4,v12,v8,v0.t
|
|
|
++[ ]+[0-9a-f]+:[ ]+bc85e257[ ]+vnmsac.vx[ ]+v4,a1,v8,v0.t
|
|
|
++[ ]+[0-9a-f]+:[ ]+a6862257[ ]+vmadd.vv[ ]+v4,v12,v8
|
|
|
++[ ]+[0-9a-f]+:[ ]+a685e257[ ]+vmadd.vx[ ]+v4,a1,v8
|
|
|
++[ ]+[0-9a-f]+:[ ]+a4862257[ ]+vmadd.vv[ ]+v4,v12,v8,v0.t
|
|
|
++[ ]+[0-9a-f]+:[ ]+a485e257[ ]+vmadd.vx[ ]+v4,a1,v8,v0.t
|
|
|
++[ ]+[0-9a-f]+:[ ]+ae862257[ ]+vnmsub.vv[ ]+v4,v12,v8
|
|
|
++[ ]+[0-9a-f]+:[ ]+ae85e257[ ]+vnmsub.vx[ ]+v4,a1,v8
|
|
|
++[ ]+[0-9a-f]+:[ ]+ac862257[ ]+vnmsub.vv[ ]+v4,v12,v8,v0.t
|
|
|
++[ ]+[0-9a-f]+:[ ]+ac85e257[ ]+vnmsub.vx[ ]+v4,a1,v8,v0.t
|
|
|
++[ ]+[0-9a-f]+:[ ]+82862257[ ]+vdivu.vv[ ]+v4,v8,v12
|
|
|
++[ ]+[0-9a-f]+:[ ]+8285e257[ ]+vdivu.vx[ ]+v4,v8,a1
|
|
|
++[ ]+[0-9a-f]+:[ ]+80862257[ ]+vdivu.vv[ ]+v4,v8,v12,v0.t
|
|
|
++[ ]+[0-9a-f]+:[ ]+8085e257[ ]+vdivu.vx[ ]+v4,v8,a1,v0.t
|
|
|
++[ ]+[0-9a-f]+:[ ]+86862257[ ]+vdiv.vv[ ]+v4,v8,v12
|
|
|
++[ ]+[0-9a-f]+:[ ]+8685e257[ ]+vdiv.vx[ ]+v4,v8,a1
|
|
|
++[ ]+[0-9a-f]+:[ ]+84862257[ ]+vdiv.vv[ ]+v4,v8,v12,v0.t
|
|
|
++[ ]+[0-9a-f]+:[ ]+8485e257[ ]+vdiv.vx[ ]+v4,v8,a1,v0.t
|
|
|
++[ ]+[0-9a-f]+:[ ]+8a862257[ ]+vremu.vv[ ]+v4,v8,v12
|
|
|
++[ ]+[0-9a-f]+:[ ]+8a85e257[ ]+vremu.vx[ ]+v4,v8,a1
|
|
|
++[ ]+[0-9a-f]+:[ ]+88862257[ ]+vremu.vv[ ]+v4,v8,v12,v0.t
|
|
|
++[ ]+[0-9a-f]+:[ ]+8885e257[ ]+vremu.vx[ ]+v4,v8,a1,v0.t
|
|
|
++[ ]+[0-9a-f]+:[ ]+8e862257[ ]+vrem.vv[ ]+v4,v8,v12
|
|
|
++[ ]+[0-9a-f]+:[ ]+8e85e257[ ]+vrem.vx[ ]+v4,v8,a1
|
|
|
++[ ]+[0-9a-f]+:[ ]+8c862257[ ]+vrem.vv[ ]+v4,v8,v12,v0.t
|
|
|
++[ ]+[0-9a-f]+:[ ]+8c85e257[ ]+vrem.vx[ ]+v4,v8,a1,v0.t
|
|
|
++[ ]+[0-9a-f]+:[ ]+5c860257[ ]+vmerge.vvm[ ]+v4,v8,v12,v0
|
|
|
++[ ]+[0-9a-f]+:[ ]+5c85c257[ ]+vmerge.vxm[ ]+v4,v8,a1,v0
|
|
|
++[ ]+[0-9a-f]+:[ ]+5c87b257[ ]+vmerge.vim[ ]+v4,v8,15,v0
|
|
|
++[ ]+[0-9a-f]+:[ ]+5c883257[ ]+vmerge.vim[ ]+v4,v8,-16,v0
|
|
|
++[ ]+[0-9a-f]+:[ ]+5e060457[ ]+vmv.v.v[ ]+v8,v12
|
|
|
++[ ]+[0-9a-f]+:[ ]+5e05c457[ ]+vmv.v.x[ ]+v8,a1
|
|
|
++[ ]+[0-9a-f]+:[ ]+5e07b457[ ]+vmv.v.i[ ]+v8,15
|
|
|
++[ ]+[0-9a-f]+:[ ]+5e083457[ ]+vmv.v.i[ ]+v8,-16
|
|
|
++[ ]+[0-9a-f]+:[ ]+02861257[ ]+vfadd.vv[ ]+v4,v8,v12
|
|
|
++[ ]+[0-9a-f]+:[ ]+02865257[ ]+vfadd.vf[ ]+v4,v8,fa2
|
|
|
++[ ]+[0-9a-f]+:[ ]+00861257[ ]+vfadd.vv[ ]+v4,v8,v12,v0.t
|
|
|
++[ ]+[0-9a-f]+:[ ]+00865257[ ]+vfadd.vf[ ]+v4,v8,fa2,v0.t
|
|
|
++[ ]+[0-9a-f]+:[ ]+0a861257[ ]+vfsub.vv[ ]+v4,v8,v12
|
|
|
++[ ]+[0-9a-f]+:[ ]+0a865257[ ]+vfsub.vf[ ]+v4,v8,fa2
|
|
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++[ ]+[0-9a-f]+:[ ]+08861257[ ]+vfsub.vv[ ]+v4,v8,v12,v0.t
|
|
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++[ ]+[0-9a-f]+:[ ]+08865257[ ]+vfsub.vf[ ]+v4,v8,fa2,v0.t
|
|
|
++[ ]+[0-9a-f]+:[ ]+9e865257[ ]+vfrsub.vf[ ]+v4,v8,fa2
|
|
|
++[ ]+[0-9a-f]+:[ ]+9c865257[ ]+vfrsub.vf[ ]+v4,v8,fa2,v0.t
|
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++[ ]+[0-9a-f]+:[ ]+92861257[ ]+vfmul.vv[ ]+v4,v8,v12
|
|
|
++[ ]+[0-9a-f]+:[ ]+92865257[ ]+vfmul.vf[ ]+v4,v8,fa2
|
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++[ ]+[0-9a-f]+:[ ]+90861257[ ]+vfmul.vv[ ]+v4,v8,v12,v0.t
|
|
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++[ ]+[0-9a-f]+:[ ]+90865257[ ]+vfmul.vf[ ]+v4,v8,fa2,v0.t
|
|
|
++[ ]+[0-9a-f]+:[ ]+82861257[ ]+vfdiv.vv[ ]+v4,v8,v12
|
|
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++[ ]+[0-9a-f]+:[ ]+82865257[ ]+vfdiv.vf[ ]+v4,v8,fa2
|
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++[ ]+[0-9a-f]+:[ ]+80861257[ ]+vfdiv.vv[ ]+v4,v8,v12,v0.t
|
|
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++[ ]+[0-9a-f]+:[ ]+80865257[ ]+vfdiv.vf[ ]+v4,v8,fa2,v0.t
|
|
|
++[ ]+[0-9a-f]+:[ ]+86865257[ ]+vfrdiv.vf[ ]+v4,v8,fa2
|
|
|
++[ ]+[0-9a-f]+:[ ]+84865257[ ]+vfrdiv.vf[ ]+v4,v8,fa2,v0.t
|
|
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++[ ]+[0-9a-f]+:[ ]+a2861257[ ]+vfmadd.vv[ ]+v4,v12,v8
|
|
|
++[ ]+[0-9a-f]+:[ ]+a2865257[ ]+vfmadd.vf[ ]+v4,fa2,v8
|
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++[ ]+[0-9a-f]+:[ ]+a6861257[ ]+vfnmadd.vv[ ]+v4,v12,v8
|
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++[ ]+[0-9a-f]+:[ ]+a6865257[ ]+vfnmadd.vf[ ]+v4,fa2,v8
|
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++[ ]+[0-9a-f]+:[ ]+aa861257[ ]+vfmsub.vv[ ]+v4,v12,v8
|
|
|
++[ ]+[0-9a-f]+:[ ]+aa865257[ ]+vfmsub.vf[ ]+v4,fa2,v8
|
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++[ ]+[0-9a-f]+:[ ]+ae861257[ ]+vfnmsub.vv[ ]+v4,v12,v8
|
|
|
++[ ]+[0-9a-f]+:[ ]+ae865257[ ]+vfnmsub.vf[ ]+v4,fa2,v8
|
|
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++[ ]+[0-9a-f]+:[ ]+a0861257[ ]+vfmadd.vv[ ]+v4,v12,v8,v0.t
|
|
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++[ ]+[0-9a-f]+:[ ]+a0865257[ ]+vfmadd.vf[ ]+v4,fa2,v8,v0.t
|
|
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++[ ]+[0-9a-f]+:[ ]+a4861257[ ]+vfnmadd.vv[ ]+v4,v12,v8,v0.t
|
|
|
++[ ]+[0-9a-f]+:[ ]+a4865257[ ]+vfnmadd.vf[ ]+v4,fa2,v8,v0.t
|
|
|
++[ ]+[0-9a-f]+:[ ]+a8861257[ ]+vfmsub.vv[ ]+v4,v12,v8,v0.t
|
|
|
++[ ]+[0-9a-f]+:[ ]+a8865257[ ]+vfmsub.vf[ ]+v4,fa2,v8,v0.t
|
|
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++[ ]+[0-9a-f]+:[ ]+ac861257[ ]+vfnmsub.vv[ ]+v4,v12,v8,v0.t
|
|
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++[ ]+[0-9a-f]+:[ ]+ac865257[ ]+vfnmsub.vf[ ]+v4,fa2,v8,v0.t
|
|
|
++[ ]+[0-9a-f]+:[ ]+b2861257[ ]+vfmacc.vv[ ]+v4,v12,v8
|
|
|
++[ ]+[0-9a-f]+:[ ]+b2865257[ ]+vfmacc.vf[ ]+v4,fa2,v8
|
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++[ ]+[0-9a-f]+:[ ]+b6861257[ ]+vfnmacc.vv[ ]+v4,v12,v8
|
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++[ ]+[0-9a-f]+:[ ]+b6865257[ ]+vfnmacc.vf[ ]+v4,fa2,v8
|
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++[ ]+[0-9a-f]+:[ ]+ba861257[ ]+vfmsac.vv[ ]+v4,v12,v8
|
|
|
++[ ]+[0-9a-f]+:[ ]+ba865257[ ]+vfmsac.vf[ ]+v4,fa2,v8
|
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++[ ]+[0-9a-f]+:[ ]+be861257[ ]+vfnmsac.vv[ ]+v4,v12,v8
|
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|
++[ ]+[0-9a-f]+:[ ]+be865257[ ]+vfnmsac.vf[ ]+v4,fa2,v8
|
|
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++[ ]+[0-9a-f]+:[ ]+b0861257[ ]+vfmacc.vv[ ]+v4,v12,v8,v0.t
|
|
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++[ ]+[0-9a-f]+:[ ]+b0865257[ ]+vfmacc.vf[ ]+v4,fa2,v8,v0.t
|
|
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++[ ]+[0-9a-f]+:[ ]+b4861257[ ]+vfnmacc.vv[ ]+v4,v12,v8,v0.t
|
|
|
++[ ]+[0-9a-f]+:[ ]+b4865257[ ]+vfnmacc.vf[ ]+v4,fa2,v8,v0.t
|
|
|
++[ ]+[0-9a-f]+:[ ]+b8861257[ ]+vfmsac.vv[ ]+v4,v12,v8,v0.t
|
|
|
++[ ]+[0-9a-f]+:[ ]+b8865257[ ]+vfmsac.vf[ ]+v4,fa2,v8,v0.t
|
|
|
++[ ]+[0-9a-f]+:[ ]+bc861257[ ]+vfnmsac.vv[ ]+v4,v12,v8,v0.t
|
|
|
++[ ]+[0-9a-f]+:[ ]+bc865257[ ]+vfnmsac.vf[ ]+v4,fa2,v8,v0.t
|
|
|
++[ ]+[0-9a-f]+:[ ]+12861257[ ]+vfmin.vv[ ]+v4,v8,v12
|
|
|
++[ ]+[0-9a-f]+:[ ]+12865257[ ]+vfmin.vf[ ]+v4,v8,fa2
|
|
|
++[ ]+[0-9a-f]+:[ ]+1a861257[ ]+vfmax.vv[ ]+v4,v8,v12
|
|
|
++[ ]+[0-9a-f]+:[ ]+1a865257[ ]+vfmax.vf[ ]+v4,v8,fa2
|
|
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++[ ]+[0-9a-f]+:[ ]+10861257[ ]+vfmin.vv[ ]+v4,v8,v12,v0.t
|
|
|
++[ ]+[0-9a-f]+:[ ]+10865257[ ]+vfmin.vf[ ]+v4,v8,fa2,v0.t
|
|
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++[ ]+[0-9a-f]+:[ ]+18861257[ ]+vfmax.vv[ ]+v4,v8,v12,v0.t
|
|
|
++[ ]+[0-9a-f]+:[ ]+18865257[ ]+vfmax.vf[ ]+v4,v8,fa2,v0.t
|
|
|
++[ ]+[0-9a-f]+:[ ]+26841257[ ]+vfneg.v[ ]+v4,v8
|
|
|
++[ ]+[0-9a-f]+:[ ]+24841257[ ]+vfneg.v[ ]+v4,v8,v0.t
|
|
|
++[ ]+[0-9a-f]+:[ ]+2a841257[ ]+vfabs.v[ ]+v4,v8
|
|
|
++[ ]+[0-9a-f]+:[ ]+28841257[ ]+vfabs.v[ ]+v4,v8,v0.t
|
|
|
++[ ]+[0-9a-f]+:[ ]+22861257[ ]+vfsgnj.vv[ ]+v4,v8,v12
|
|
|
++[ ]+[0-9a-f]+:[ ]+22865257[ ]+vfsgnj.vf[ ]+v4,v8,fa2
|
|
|
++[ ]+[0-9a-f]+:[ ]+26861257[ ]+vfsgnjn.vv[ ]+v4,v8,v12
|
|
|
++[ ]+[0-9a-f]+:[ ]+26865257[ ]+vfsgnjn.vf[ ]+v4,v8,fa2
|
|
|
++[ ]+[0-9a-f]+:[ ]+2a861257[ ]+vfsgnjx.vv[ ]+v4,v8,v12
|
|
|
++[ ]+[0-9a-f]+:[ ]+2a865257[ ]+vfsgnjx.vf[ ]+v4,v8,fa2
|
|
|
++[ ]+[0-9a-f]+:[ ]+20861257[ ]+vfsgnj.vv[ ]+v4,v8,v12,v0.t
|
|
|
++[ ]+[0-9a-f]+:[ ]+20865257[ ]+vfsgnj.vf[ ]+v4,v8,fa2,v0.t
|
|
|
++[ ]+[0-9a-f]+:[ ]+24861257[ ]+vfsgnjn.vv[ ]+v4,v8,v12,v0.t
|
|
|
++[ ]+[0-9a-f]+:[ ]+24865257[ ]+vfsgnjn.vf[ ]+v4,v8,fa2,v0.t
|
|
|
++[ ]+[0-9a-f]+:[ ]+28861257[ ]+vfsgnjx.vv[ ]+v4,v8,v12,v0.t
|
|
|
++[ ]+[0-9a-f]+:[ ]+28865257[ ]+vfsgnjx.vf[ ]+v4,v8,fa2,v0.t
|
|
|
++[ ]+[0-9a-f]+:[ ]+6ec41257[ ]+vmflt.vv[ ]+v4,v12,v8
|
|
|
++[ ]+[0-9a-f]+:[ ]+66c41257[ ]+vmfle.vv[ ]+v4,v12,v8
|
|
|
++[ ]+[0-9a-f]+:[ ]+6cc41257[ ]+vmflt.vv[ ]+v4,v12,v8,v0.t
|
|
|
++[ ]+[0-9a-f]+:[ ]+64c41257[ ]+vmfle.vv[ ]+v4,v12,v8,v0.t
|
|
|
++[ ]+[0-9a-f]+:[ ]+62861257[ ]+vmfeq.vv[ ]+v4,v8,v12
|
|
|
++[ ]+[0-9a-f]+:[ ]+62865257[ ]+vmfeq.vf[ ]+v4,v8,fa2
|
|
|
++[ ]+[0-9a-f]+:[ ]+72861257[ ]+vmfne.vv[ ]+v4,v8,v12
|
|
|
++[ ]+[0-9a-f]+:[ ]+72865257[ ]+vmfne.vf[ ]+v4,v8,fa2
|
|
|
++[ ]+[0-9a-f]+:[ ]+6e861257[ ]+vmflt.vv[ ]+v4,v8,v12
|
|
|
++[ ]+[0-9a-f]+:[ ]+6e865257[ ]+vmflt.vf[ ]+v4,v8,fa2
|
|
|
++[ ]+[0-9a-f]+:[ ]+66861257[ ]+vmfle.vv[ ]+v4,v8,v12
|
|
|
++[ ]+[0-9a-f]+:[ ]+66865257[ ]+vmfle.vf[ ]+v4,v8,fa2
|
|
|
++[ ]+[0-9a-f]+:[ ]+76865257[ ]+vmfgt.vf[ ]+v4,v8,fa2
|
|
|
++[ ]+[0-9a-f]+:[ ]+7e865257[ ]+vmfge.vf[ ]+v4,v8,fa2
|
|
|
++[ ]+[0-9a-f]+:[ ]+60861257[ ]+vmfeq.vv[ ]+v4,v8,v12,v0.t
|
|
|
++[ ]+[0-9a-f]+:[ ]+60865257[ ]+vmfeq.vf[ ]+v4,v8,fa2,v0.t
|
|
|
++[ ]+[0-9a-f]+:[ ]+70861257[ ]+vmfne.vv[ ]+v4,v8,v12,v0.t
|
|
|
++[ ]+[0-9a-f]+:[ ]+70865257[ ]+vmfne.vf[ ]+v4,v8,fa2,v0.t
|
|
|
++[ ]+[0-9a-f]+:[ ]+6c861257[ ]+vmflt.vv[ ]+v4,v8,v12,v0.t
|
|
|
++[ ]+[0-9a-f]+:[ ]+6c865257[ ]+vmflt.vf[ ]+v4,v8,fa2,v0.t
|
|
|
++[ ]+[0-9a-f]+:[ ]+64861257[ ]+vmfle.vv[ ]+v4,v8,v12,v0.t
|
|
|
++[ ]+[0-9a-f]+:[ ]+64865257[ ]+vmfle.vf[ ]+v4,v8,fa2,v0.t
|
|
|
++[ ]+[0-9a-f]+:[ ]+74865257[ ]+vmfgt.vf[ ]+v4,v8,fa2,v0.t
|
|
|
++[ ]+[0-9a-f]+:[ ]+7c865257[ ]+vmfge.vf[ ]+v4,v8,fa2,v0.t
|
|
|
++[ ]+[0-9a-f]+:[ ]+5c865257[ ]+vfmerge.vfm[ ]+v4,v8,fa2,v0
|
|
|
++[ ]+[0-9a-f]+:[ ]+5e05d257[ ]+vfmv.v.f[ ]+v4,fa1
|
|
|
++[ ]+[0-9a-f]+:[ ]+66842257[ ]+vmmv.m[ ]+v4,v8
|
|
|
++[ ]+[0-9a-f]+:[ ]+66842257[ ]+vmmv.m[ ]+v4,v8
|
|
|
++[ ]+[0-9a-f]+:[ ]+6e422257[ ]+vmclr.m[ ]+v4
|
|
|
++[ ]+[0-9a-f]+:[ ]+7e422257[ ]+vmset.m[ ]+v4
|
|
|
++[ ]+[0-9a-f]+:[ ]+76842257[ ]+vmnot.m[ ]+v4,v8
|
|
|
++[ ]+[0-9a-f]+:[ ]+66862257[ ]+vmand.mm[ ]+v4,v8,v12
|
|
|
++[ ]+[0-9a-f]+:[ ]+76862257[ ]+vmnand.mm[ ]+v4,v8,v12
|
|
|
++[ ]+[0-9a-f]+:[ ]+62862257[ ]+vmandnot.mm[ ]+v4,v8,v12
|
|
|
++[ ]+[0-9a-f]+:[ ]+6e862257[ ]+vmxor.mm[ ]+v4,v8,v12
|
|
|
++[ ]+[0-9a-f]+:[ ]+6a862257[ ]+vmor.mm[ ]+v4,v8,v12
|
|
|
++[ ]+[0-9a-f]+:[ ]+7a862257[ ]+vmnor.mm[ ]+v4,v8,v12
|
|
|
++[ ]+[0-9a-f]+:[ ]+72862257[ ]+vmornot.mm[ ]+v4,v8,v12
|
|
|
++[ ]+[0-9a-f]+:[ ]+7e862257[ ]+vmxnor.mm[ ]+v4,v8,v12
|
|
|
++[ ]+[0-9a-f]+:[ ]+42c82557[ ]+vpopc.m[ ]+a0,v12
|
|
|
++[ ]+[0-9a-f]+:[ ]+42c8a557[ ]+vfirst.m[ ]+a0,v12
|
|
|
++[ ]+[0-9a-f]+:[ ]+40c82557[ ]+vpopc.m[ ]+a0,v12,v0.t
|
|
|
++[ ]+[0-9a-f]+:[ ]+40c8a557[ ]+vfirst.m[ ]+a0,v12,v0.t
|
|
|
++[ ]+[0-9a-f]+:[ ]+42c02557[ ]+vmv.x.s[ ]+a0,v12
|
|
|
++[ ]+[0-9a-f]+:[ ]+42056257[ ]+vmv.s.x[ ]+v4,a0
|
|
|
++[ ]+[0-9a-f]+:[ ]+42801557[ ]+vfmv.f.s[ ]+fa0,v8
|
|
|
++[ ]+[0-9a-f]+:[ ]+4205d257[ ]+vfmv.s.f[ ]+v4,fa1
|
|
|
++[ ]+[0-9a-f]+:[ ]+3a85c257[ ]+vslideup.vx[ ]+v4,v8,a1
|
|
|
++[ ]+[0-9a-f]+:[ ]+3a803257[ ]+vslideup.vi[ ]+v4,v8,0
|
|
|
++[ ]+[0-9a-f]+:[ ]+3a8fb257[ ]+vslideup.vi[ ]+v4,v8,31
|
|
|
++[ ]+[0-9a-f]+:[ ]+3e85c257[ ]+vslidedown.vx[ ]+v4,v8,a1
|
|
|
++[ ]+[0-9a-f]+:[ ]+3e803257[ ]+vslidedown.vi[ ]+v4,v8,0
|
|
|
++[ ]+[0-9a-f]+:[ ]+3e8fb257[ ]+vslidedown.vi[ ]+v4,v8,31
|
|
|
++[ ]+[0-9a-f]+:[ ]+3885c257[ ]+vslideup.vx[ ]+v4,v8,a1,v0.t
|
|
|
++[ ]+[0-9a-f]+:[ ]+38803257[ ]+vslideup.vi[ ]+v4,v8,0,v0.t
|
|
|
++[ ]+[0-9a-f]+:[ ]+388fb257[ ]+vslideup.vi[ ]+v4,v8,31,v0.t
|
|
|
++[ ]+[0-9a-f]+:[ ]+3c85c257[ ]+vslidedown.vx[ ]+v4,v8,a1,v0.t
|
|
|
++[ ]+[0-9a-f]+:[ ]+3c803257[ ]+vslidedown.vi[ ]+v4,v8,0,v0.t
|
|
|
++[ ]+[0-9a-f]+:[ ]+3c8fb257[ ]+vslidedown.vi[ ]+v4,v8,31,v0.t
|
|
|
++[ ]+[0-9a-f]+:[ ]+3a85e257[ ]+vslide1up.vx[ ]+v4,v8,a1
|
|
|
++[ ]+[0-9a-f]+:[ ]+3e85e257[ ]+vslide1down.vx[ ]+v4,v8,a1
|
|
|
++[ ]+[0-9a-f]+:[ ]+3885e257[ ]+vslide1up.vx[ ]+v4,v8,a1,v0.t
|
|
|
++[ ]+[0-9a-f]+:[ ]+3c85e257[ ]+vslide1down.vx[ ]+v4,v8,a1,v0.t
|
|
|
++[ ]+[0-9a-f]+:[ ]+3a85d257[ ]+vfslide1up.vf[ ]+v4,v8,fa1
|
|
|
++[ ]+[0-9a-f]+:[ ]+3e85d257[ ]+vfslide1down.vf[ ]+v4,v8,fa1
|
|
|
++[ ]+[0-9a-f]+:[ ]+3885d257[ ]+vfslide1up.vf[ ]+v4,v8,fa1,v0.t
|
|
|
++[ ]+[0-9a-f]+:[ ]+3c85d257[ ]+vfslide1down.vf[ ]+v4,v8,fa1,v0.t
|
|
|
++[ ]+[0-9a-f]+:[ ]+32860257[ ]+vrgather.vv[ ]+v4,v8,v12
|
|
|
++[ ]+[0-9a-f]+:[ ]+3285c257[ ]+vrgather.vx[ ]+v4,v8,a1
|
|
|
++[ ]+[0-9a-f]+:[ ]+32803257[ ]+vrgather.vi[ ]+v4,v8,0
|
|
|
++[ ]+[0-9a-f]+:[ ]+328fb257[ ]+vrgather.vi[ ]+v4,v8,31
|
|
|
++[ ]+[0-9a-f]+:[ ]+30860257[ ]+vrgather.vv[ ]+v4,v8,v12,v0.t
|
|
|
++[ ]+[0-9a-f]+:[ ]+3085c257[ ]+vrgather.vx[ ]+v4,v8,a1,v0.t
|
|
|
++[ ]+[0-9a-f]+:[ ]+30803257[ ]+vrgather.vi[ ]+v4,v8,0,v0.t
|
|
|
++[ ]+[0-9a-f]+:[ ]+308fb257[ ]+vrgather.vi[ ]+v4,v8,31,v0.t
|
|
|
++[ ]+[0-9a-f]+:[ ]+5e862257[ ]+vcompress.vm[ ]+v4,v8,v12
|
|
|
+diff --git a/gas/testsuite/gas/riscv/vector-insns.s b/gas/testsuite/gas/riscv/vector-insns.s
|
|
|
+new file mode 100644
|
|
|
+index 0000000000..a6f906e416
|
|
|
+--- /dev/null
|
|
|
++++ b/gas/testsuite/gas/riscv/vector-insns.s
|
|
|
+@@ -0,0 +1,521 @@
|
|
|
++ vsetvl a0, a1, a2
|
|
|
++ vsetvli a0, a1, 0
|
|
|
++ vsetvli a0, a1, 0x7ff
|
|
|
++ vsetvli a0, a1, e16, m2
|
|
|
++ vsetvli a0, a1, e256, m8
|
|
|
++ vsetvli a0, a1, e512, m8
|
|
|
++ vsetvli a0, a1, e1024, m8
|
|
|
++ vsetvli a0, a1, e1024, m1
|
|
|
++ vsetvli a0, a1, e1024, mf2
|
|
|
++ vsetvli a0, a1, e512, mf4
|
|
|
++ vsetvli a0, a1, e256, mf8
|
|
|
++ vsetvli a0, a1, e256, m2, ta
|
|
|
++ vsetvli a0, a1, e256, m2, ma
|
|
|
++ vsetvli a0, a1, e256, m2, tu
|
|
|
++ vsetvli a0, a1, e256, m2, mu
|
|
|
++ vsetvli a0, a1, e256, m2, ta, ma
|
|
|
++ vsetvli a0, a1, e256, m2, tu, ma
|
|
|
++ vsetvli a0, a1, e256, m2, ta, mu
|
|
|
++ vsetvli a0, a1, e256, m2, tu, mu
|
|
|
++
|
|
|
++ vle8.v v4, (a0)
|
|
|
++ vle8.v v4, 0(a0)
|
|
|
++ vle8.v v4, (a0), v0.t
|
|
|
++ vse8.v v4, (a0)
|
|
|
++ vse8.v v4, 0(a0)
|
|
|
++ vse8.v v4, (a0), v0.t
|
|
|
++
|
|
|
++ vle16.v v4, (a0)
|
|
|
++ vle16.v v4, 0(a0)
|
|
|
++ vle16.v v4, (a0), v0.t
|
|
|
++ vse16.v v4, (a0)
|
|
|
++ vse16.v v4, 0(a0)
|
|
|
++ vse16.v v4, (a0), v0.t
|
|
|
++
|
|
|
++ vle32.v v4, (a0)
|
|
|
++ vle32.v v4, 0(a0)
|
|
|
++ vle32.v v4, (a0), v0.t
|
|
|
++ vse32.v v4, (a0)
|
|
|
++ vse32.v v4, 0(a0)
|
|
|
++ vse32.v v4, (a0), v0.t
|
|
|
++
|
|
|
++ vle64.v v4, (a0)
|
|
|
++ vle64.v v4, 0(a0)
|
|
|
++ vle64.v v4, (a0), v0.t
|
|
|
++ vse64.v v4, (a0)
|
|
|
++ vse64.v v4, 0(a0)
|
|
|
++ vse64.v v4, (a0), v0.t
|
|
|
++
|
|
|
++ vlse8.v v4, (a0), a1
|
|
|
++ vlse8.v v4, 0(a0), a1
|
|
|
++ vlse8.v v4, (a0), a1, v0.t
|
|
|
++ vsse8.v v4, (a0), a1
|
|
|
++ vsse8.v v4, 0(a0), a1
|
|
|
++ vsse8.v v4, (a0), a1, v0.t
|
|
|
++
|
|
|
++ vlse16.v v4, (a0), a1
|
|
|
++ vlse16.v v4, 0(a0), a1
|
|
|
++ vlse16.v v4, (a0), a1, v0.t
|
|
|
++ vsse16.v v4, (a0), a1
|
|
|
++ vsse16.v v4, 0(a0), a1
|
|
|
++ vsse16.v v4, (a0), a1, v0.t
|
|
|
++
|
|
|
++ vlse32.v v4, (a0), a1
|
|
|
++ vlse32.v v4, 0(a0), a1
|
|
|
++ vlse32.v v4, (a0), a1, v0.t
|
|
|
++ vsse32.v v4, (a0), a1
|
|
|
++ vsse32.v v4, 0(a0), a1
|
|
|
++ vsse32.v v4, (a0), a1, v0.t
|
|
|
++
|
|
|
++ vlse64.v v4, (a0), a1
|
|
|
++ vlse64.v v4, 0(a0), a1
|
|
|
++ vlse64.v v4, (a0), a1, v0.t
|
|
|
++ vsse64.v v4, (a0), a1
|
|
|
++ vsse64.v v4, 0(a0), a1
|
|
|
++ vsse64.v v4, (a0), a1, v0.t
|
|
|
++
|
|
|
++ vloxei8.v v4, (a0), v12
|
|
|
++ vloxei8.v v4, 0(a0), v12
|
|
|
++ vloxei8.v v4, (a0), v12, v0.t
|
|
|
++ vsoxei8.v v4, (a0), v12
|
|
|
++ vsoxei8.v v4, 0(a0), v12
|
|
|
++ vsoxei8.v v4, (a0), v12, v0.t
|
|
|
++
|
|
|
++ vloxei16.v v4, (a0), v12
|
|
|
++ vloxei16.v v4, 0(a0), v12
|
|
|
++ vloxei16.v v4, (a0), v12, v0.t
|
|
|
++ vsoxei16.v v4, (a0), v12
|
|
|
++ vsoxei16.v v4, 0(a0), v12
|
|
|
++ vsoxei16.v v4, (a0), v12, v0.t
|
|
|
++
|
|
|
++ vloxei32.v v4, (a0), v12
|
|
|
++ vloxei32.v v4, 0(a0), v12
|
|
|
++ vloxei32.v v4, (a0), v12, v0.t
|
|
|
++ vsoxei32.v v4, (a0), v12
|
|
|
++ vsoxei32.v v4, 0(a0), v12
|
|
|
++ vsoxei32.v v4, (a0), v12, v0.t
|
|
|
++
|
|
|
++ vloxei64.v v4, (a0), v12
|
|
|
++ vloxei64.v v4, 0(a0), v12
|
|
|
++ vloxei64.v v4, (a0), v12, v0.t
|
|
|
++ vsoxei64.v v4, (a0), v12
|
|
|
++ vsoxei64.v v4, 0(a0), v12
|
|
|
++ vsoxei64.v v4, (a0), v12, v0.t
|
|
|
++
|
|
|
++ vneg.v v4, v8
|
|
|
++ vneg.v v4, v8, v0.t
|
|
|
++
|
|
|
++ vadd.vv v4, v8, v12
|
|
|
++ vadd.vx v4, v8, a1
|
|
|
++ vadd.vi v4, v8, 15
|
|
|
++ vadd.vi v4, v8, -16
|
|
|
++ vadd.vv v4, v8, v12, v0.t
|
|
|
++ vadd.vx v4, v8, a1, v0.t
|
|
|
++ vadd.vi v4, v8, 15, v0.t
|
|
|
++ vadd.vi v4, v8, -16, v0.t
|
|
|
++ vsub.vv v4, v8, v12
|
|
|
++ vsub.vx v4, v8, a1
|
|
|
++ vrsub.vx v4, v8, a1
|
|
|
++ vrsub.vi v4, v8, 15
|
|
|
++ vrsub.vi v4, v8, -16
|
|
|
++ vsub.vv v4, v8, v12, v0.t
|
|
|
++ vsub.vx v4, v8, a1, v0.t
|
|
|
++ vrsub.vx v4, v8, a1, v0.t
|
|
|
++ vrsub.vi v4, v8, 15, v0.t
|
|
|
++ vrsub.vi v4, v8, -16, v0.t
|
|
|
++
|
|
|
++ # Aliases
|
|
|
++ vzext.vf2 v4, v8
|
|
|
++ vzext.vf2 v4, v8, v0.t
|
|
|
++ vsext.vf2 v4, v8
|
|
|
++ vsext.vf2 v4, v8, v0.t
|
|
|
++ vzext.vf4 v4, v8
|
|
|
++ vzext.vf4 v4, v8, v0.t
|
|
|
++ vsext.vf4 v4, v8
|
|
|
++ vsext.vf4 v4, v8, v0.t
|
|
|
++ vzext.vf8 v4, v8
|
|
|
++ vzext.vf8 v4, v8, v0.t
|
|
|
++ vsext.vf8 v4, v8
|
|
|
++ vsext.vf8 v4, v8, v0.t
|
|
|
++
|
|
|
++ vadc.vvm v4, v8, v12, v0
|
|
|
++ vadc.vxm v4, v8, a1, v0
|
|
|
++ vadc.vim v4, v8, 15, v0
|
|
|
++ vadc.vim v4, v8, -16, v0
|
|
|
++ vmadc.vvm v4, v8, v12, v0
|
|
|
++ vmadc.vxm v4, v8, a1, v0
|
|
|
++ vmadc.vim v4, v8, 15, v0
|
|
|
++ vmadc.vim v4, v8, -16, v0
|
|
|
++ vmadc.vv v4, v8, v12
|
|
|
++ vmadc.vx v4, v8, a1
|
|
|
++ vmadc.vi v4, v8, 15
|
|
|
++ vmadc.vi v4, v8, -16
|
|
|
++ vsbc.vvm v4, v8, v12, v0
|
|
|
++ vsbc.vxm v4, v8, a1, v0
|
|
|
++ vmsbc.vvm v4, v8, v12, v0
|
|
|
++ vmsbc.vxm v4, v8, a1, v0
|
|
|
++ vmsbc.vv v4, v8, v12
|
|
|
++ vmsbc.vx v4, v8, a1
|
|
|
++
|
|
|
++ # Aliases
|
|
|
++ vnot.v v4, v8
|
|
|
++ vnot.v v4, v8, v0.t
|
|
|
++
|
|
|
++ vand.vv v4, v8, v12
|
|
|
++ vand.vx v4, v8, a1
|
|
|
++ vand.vi v4, v8, 15
|
|
|
++ vand.vi v4, v8, -16
|
|
|
++ vand.vv v4, v8, v12, v0.t
|
|
|
++ vand.vx v4, v8, a1, v0.t
|
|
|
++ vand.vi v4, v8, 15, v0.t
|
|
|
++ vand.vi v4, v8, -16, v0.t
|
|
|
++ vor.vv v4, v8, v12
|
|
|
++ vor.vx v4, v8, a1
|
|
|
++ vor.vi v4, v8, 15
|
|
|
++ vor.vi v4, v8, -16
|
|
|
++ vor.vv v4, v8, v12, v0.t
|
|
|
++ vor.vx v4, v8, a1, v0.t
|
|
|
++ vor.vi v4, v8, 15, v0.t
|
|
|
++ vor.vi v4, v8, -16, v0.t
|
|
|
++ vxor.vv v4, v8, v12
|
|
|
++ vxor.vx v4, v8, a1
|
|
|
++ vxor.vi v4, v8, 15
|
|
|
++ vxor.vi v4, v8, -16
|
|
|
++ vxor.vv v4, v8, v12, v0.t
|
|
|
++ vxor.vx v4, v8, a1, v0.t
|
|
|
++ vxor.vi v4, v8, 15, v0.t
|
|
|
++ vxor.vi v4, v8, -16, v0.t
|
|
|
++
|
|
|
++ # Aliases
|
|
|
++ vmsgt.vv v4, v8, v12
|
|
|
++ vmsgtu.vv v4, v8, v12
|
|
|
++ vmsge.vv v4, v8, v12
|
|
|
++ vmsgeu.vv v4, v8, v12
|
|
|
++ vmsgt.vv v4, v8, v12, v0.t
|
|
|
++ vmsgtu.vv v4, v8, v12, v0.t
|
|
|
++ vmsge.vv v4, v8, v12, v0.t
|
|
|
++ vmsgeu.vv v4, v8, v12, v0.t
|
|
|
++ vmslt.vi v4, v8, 16
|
|
|
++ vmslt.vi v4, v8, -15
|
|
|
++ vmsltu.vi v4, v8, 16
|
|
|
++ vmsltu.vi v4, v8, -15
|
|
|
++ vmsge.vi v4, v8, 16
|
|
|
++ vmsge.vi v4, v8, -15
|
|
|
++ vmsgeu.vi v4, v8, 16
|
|
|
++ vmsgeu.vi v4, v8, -15
|
|
|
++ vmslt.vi v4, v8, 16, v0.t
|
|
|
++ vmslt.vi v4, v8, -15, v0.t
|
|
|
++ vmsltu.vi v4, v8, 16, v0.t
|
|
|
++ vmsltu.vi v4, v8, -15, v0.t
|
|
|
++ vmsge.vi v4, v8, 16, v0.t
|
|
|
++ vmsge.vi v4, v8, -15, v0.t
|
|
|
++ vmsgeu.vi v4, v8, 16, v0.t
|
|
|
++ vmsgeu.vi v4, v8, -15, v0.t
|
|
|
++
|
|
|
++ vmseq.vv v4, v8, v12
|
|
|
++ vmseq.vx v4, v8, a1
|
|
|
++ vmseq.vi v4, v8, 15
|
|
|
++ vmseq.vi v4, v8, -16
|
|
|
++ vmseq.vv v4, v8, v12, v0.t
|
|
|
++ vmseq.vx v4, v8, a1, v0.t
|
|
|
++ vmseq.vi v4, v8, 15, v0.t
|
|
|
++ vmseq.vi v4, v8, -16, v0.t
|
|
|
++ vmsne.vv v4, v8, v12
|
|
|
++ vmsne.vx v4, v8, a1
|
|
|
++ vmsne.vi v4, v8, 15
|
|
|
++ vmsne.vi v4, v8, -16
|
|
|
++ vmsne.vv v4, v8, v12, v0.t
|
|
|
++ vmsne.vx v4, v8, a1, v0.t
|
|
|
++ vmsne.vi v4, v8, 15, v0.t
|
|
|
++ vmsne.vi v4, v8, -16, v0.t
|
|
|
++ vmsltu.vv v4, v8, v12
|
|
|
++ vmsltu.vx v4, v8, a1
|
|
|
++ vmsltu.vv v4, v8, v12, v0.t
|
|
|
++ vmsltu.vx v4, v8, a1, v0.t
|
|
|
++ vmslt.vv v4, v8, v12
|
|
|
++ vmslt.vx v4, v8, a1
|
|
|
++ vmslt.vv v4, v8, v12, v0.t
|
|
|
++ vmslt.vx v4, v8, a1, v0.t
|
|
|
++ vmsleu.vv v4, v8, v12
|
|
|
++ vmsleu.vx v4, v8, a1
|
|
|
++ vmsleu.vi v4, v8, 15
|
|
|
++ vmsleu.vi v4, v8, -16
|
|
|
++ vmsleu.vv v4, v8, v12, v0.t
|
|
|
++ vmsleu.vx v4, v8, a1, v0.t
|
|
|
++ vmsleu.vi v4, v8, 15, v0.t
|
|
|
++ vmsleu.vi v4, v8, -16, v0.t
|
|
|
++ vmsle.vv v4, v8, v12
|
|
|
++ vmsle.vx v4, v8, a1
|
|
|
++ vmsle.vi v4, v8, 15
|
|
|
++ vmsle.vi v4, v8, -16
|
|
|
++ vmsle.vv v4, v8, v12, v0.t
|
|
|
++ vmsle.vx v4, v8, a1, v0.t
|
|
|
++ vmsle.vi v4, v8, 15, v0.t
|
|
|
++ vmsle.vi v4, v8, -16, v0.t
|
|
|
++ vmsgtu.vx v4, v8, a1
|
|
|
++ vmsgtu.vi v4, v8, 15
|
|
|
++ vmsgtu.vi v4, v8, -16
|
|
|
++ vmsgtu.vx v4, v8, a1, v0.t
|
|
|
++ vmsgtu.vi v4, v8, 15, v0.t
|
|
|
++ vmsgtu.vi v4, v8, -16, v0.t
|
|
|
++ vmsgt.vx v4, v8, a1
|
|
|
++ vmsgt.vi v4, v8, 15
|
|
|
++ vmsgt.vi v4, v8, -16
|
|
|
++ vmsgt.vx v4, v8, a1, v0.t
|
|
|
++ vmsgt.vi v4, v8, 15, v0.t
|
|
|
++ vmsgt.vi v4, v8, -16, v0.t
|
|
|
++
|
|
|
++ vminu.vv v4, v8, v12
|
|
|
++ vminu.vx v4, v8, a1
|
|
|
++ vminu.vv v4, v8, v12, v0.t
|
|
|
++ vminu.vx v4, v8, a1, v0.t
|
|
|
++ vmin.vv v4, v8, v12
|
|
|
++ vmin.vx v4, v8, a1
|
|
|
++ vmin.vv v4, v8, v12, v0.t
|
|
|
++ vmin.vx v4, v8, a1, v0.t
|
|
|
++ vmaxu.vv v4, v8, v12
|
|
|
++ vmaxu.vx v4, v8, a1
|
|
|
++ vmaxu.vv v4, v8, v12, v0.t
|
|
|
++ vmaxu.vx v4, v8, a1, v0.t
|
|
|
++ vmax.vv v4, v8, v12
|
|
|
++ vmax.vx v4, v8, a1
|
|
|
++ vmax.vv v4, v8, v12, v0.t
|
|
|
++ vmax.vx v4, v8, a1, v0.t
|
|
|
++
|
|
|
++ vmul.vv v4, v8, v12
|
|
|
++ vmul.vx v4, v8, a1
|
|
|
++ vmul.vv v4, v8, v12, v0.t
|
|
|
++ vmul.vx v4, v8, a1, v0.t
|
|
|
++ vmulh.vv v4, v8, v12
|
|
|
++ vmulh.vx v4, v8, a1
|
|
|
++ vmulh.vv v4, v8, v12, v0.t
|
|
|
++ vmulh.vx v4, v8, a1, v0.t
|
|
|
++ vmulhu.vv v4, v8, v12
|
|
|
++ vmulhu.vx v4, v8, a1
|
|
|
++ vmulhu.vv v4, v8, v12, v0.t
|
|
|
++ vmulhu.vx v4, v8, a1, v0.t
|
|
|
++ vmulhsu.vv v4, v8, v12
|
|
|
++ vmulhsu.vx v4, v8, a1
|
|
|
++ vmulhsu.vv v4, v8, v12, v0.t
|
|
|
++ vmulhsu.vx v4, v8, a1, v0.t
|
|
|
++
|
|
|
++ vmacc.vv v4, v12, v8
|
|
|
++ vmacc.vx v4, a1, v8
|
|
|
++ vmacc.vv v4, v12, v8, v0.t
|
|
|
++ vmacc.vx v4, a1, v8, v0.t
|
|
|
++ vnmsac.vv v4, v12, v8
|
|
|
++ vnmsac.vx v4, a1, v8
|
|
|
++ vnmsac.vv v4, v12, v8, v0.t
|
|
|
++ vnmsac.vx v4, a1, v8, v0.t
|
|
|
++ vmadd.vv v4, v12, v8
|
|
|
++ vmadd.vx v4, a1, v8
|
|
|
++ vmadd.vv v4, v12, v8, v0.t
|
|
|
++ vmadd.vx v4, a1, v8, v0.t
|
|
|
++ vnmsub.vv v4, v12, v8
|
|
|
++ vnmsub.vx v4, a1, v8
|
|
|
++ vnmsub.vv v4, v12, v8, v0.t
|
|
|
++ vnmsub.vx v4, a1, v8, v0.t
|
|
|
++
|
|
|
++ vdivu.vv v4, v8, v12
|
|
|
++ vdivu.vx v4, v8, a1
|
|
|
++ vdivu.vv v4, v8, v12, v0.t
|
|
|
++ vdivu.vx v4, v8, a1, v0.t
|
|
|
++ vdiv.vv v4, v8, v12
|
|
|
++ vdiv.vx v4, v8, a1
|
|
|
++ vdiv.vv v4, v8, v12, v0.t
|
|
|
++ vdiv.vx v4, v8, a1, v0.t
|
|
|
++ vremu.vv v4, v8, v12
|
|
|
++ vremu.vx v4, v8, a1
|
|
|
++ vremu.vv v4, v8, v12, v0.t
|
|
|
++ vremu.vx v4, v8, a1, v0.t
|
|
|
++ vrem.vv v4, v8, v12
|
|
|
++ vrem.vx v4, v8, a1
|
|
|
++ vrem.vv v4, v8, v12, v0.t
|
|
|
++ vrem.vx v4, v8, a1, v0.t
|
|
|
++
|
|
|
++ vmerge.vvm v4, v8, v12, v0
|
|
|
++ vmerge.vxm v4, v8, a1, v0
|
|
|
++ vmerge.vim v4, v8, 15, v0
|
|
|
++ vmerge.vim v4, v8, -16, v0
|
|
|
++
|
|
|
++ vmv.v.v v8, v12
|
|
|
++ vmv.v.x v8, a1
|
|
|
++ vmv.v.i v8, 15
|
|
|
++ vmv.v.i v8, -16
|
|
|
++
|
|
|
++
|
|
|
++
|
|
|
++ vfadd.vv v4, v8, v12
|
|
|
++ vfadd.vf v4, v8, fa2
|
|
|
++ vfadd.vv v4, v8, v12, v0.t
|
|
|
++ vfadd.vf v4, v8, fa2, v0.t
|
|
|
++ vfsub.vv v4, v8, v12
|
|
|
++ vfsub.vf v4, v8, fa2
|
|
|
++ vfsub.vv v4, v8, v12, v0.t
|
|
|
++ vfsub.vf v4, v8, fa2, v0.t
|
|
|
++ vfrsub.vf v4, v8, fa2
|
|
|
++ vfrsub.vf v4, v8, fa2, v0.t
|
|
|
++
|
|
|
++
|
|
|
++ vfmul.vv v4, v8, v12
|
|
|
++ vfmul.vf v4, v8, fa2
|
|
|
++ vfmul.vv v4, v8, v12, v0.t
|
|
|
++ vfmul.vf v4, v8, fa2, v0.t
|
|
|
++ vfdiv.vv v4, v8, v12
|
|
|
++ vfdiv.vf v4, v8, fa2
|
|
|
++ vfdiv.vv v4, v8, v12, v0.t
|
|
|
++ vfdiv.vf v4, v8, fa2, v0.t
|
|
|
++ vfrdiv.vf v4, v8, fa2
|
|
|
++ vfrdiv.vf v4, v8, fa2, v0.t
|
|
|
++
|
|
|
++ vfmadd.vv v4, v12, v8
|
|
|
++ vfmadd.vf v4, fa2, v8
|
|
|
++ vfnmadd.vv v4, v12, v8
|
|
|
++ vfnmadd.vf v4, fa2, v8
|
|
|
++ vfmsub.vv v4, v12, v8
|
|
|
++ vfmsub.vf v4, fa2, v8
|
|
|
++ vfnmsub.vv v4, v12, v8
|
|
|
++ vfnmsub.vf v4, fa2, v8
|
|
|
++ vfmadd.vv v4, v12, v8, v0.t
|
|
|
++ vfmadd.vf v4, fa2, v8, v0.t
|
|
|
++ vfnmadd.vv v4, v12, v8, v0.t
|
|
|
++ vfnmadd.vf v4, fa2, v8, v0.t
|
|
|
++ vfmsub.vv v4, v12, v8, v0.t
|
|
|
++ vfmsub.vf v4, fa2, v8, v0.t
|
|
|
++ vfnmsub.vv v4, v12, v8, v0.t
|
|
|
++ vfnmsub.vf v4, fa2, v8, v0.t
|
|
|
++ vfmacc.vv v4, v12, v8
|
|
|
++ vfmacc.vf v4, fa2, v8
|
|
|
++ vfnmacc.vv v4, v12, v8
|
|
|
++ vfnmacc.vf v4, fa2, v8
|
|
|
++ vfmsac.vv v4, v12, v8
|
|
|
++ vfmsac.vf v4, fa2, v8
|
|
|
++ vfnmsac.vv v4, v12, v8
|
|
|
++ vfnmsac.vf v4, fa2, v8
|
|
|
++ vfmacc.vv v4, v12, v8, v0.t
|
|
|
++ vfmacc.vf v4, fa2, v8, v0.t
|
|
|
++ vfnmacc.vv v4, v12, v8, v0.t
|
|
|
++ vfnmacc.vf v4, fa2, v8, v0.t
|
|
|
++ vfmsac.vv v4, v12, v8, v0.t
|
|
|
++ vfmsac.vf v4, fa2, v8, v0.t
|
|
|
++ vfnmsac.vv v4, v12, v8, v0.t
|
|
|
++ vfnmsac.vf v4, fa2, v8, v0.t
|
|
|
++
|
|
|
++ vfmin.vv v4, v8, v12
|
|
|
++ vfmin.vf v4, v8, fa2
|
|
|
++ vfmax.vv v4, v8, v12
|
|
|
++ vfmax.vf v4, v8, fa2
|
|
|
++ vfmin.vv v4, v8, v12, v0.t
|
|
|
++ vfmin.vf v4, v8, fa2, v0.t
|
|
|
++ vfmax.vv v4, v8, v12, v0.t
|
|
|
++ vfmax.vf v4, v8, fa2, v0.t
|
|
|
++
|
|
|
++ vfneg.v v4, v8
|
|
|
++ vfneg.v v4, v8, v0.t
|
|
|
++ vfabs.v v4, v8
|
|
|
++ vfabs.v v4, v8, v0.t
|
|
|
++
|
|
|
++ vfsgnj.vv v4, v8, v12
|
|
|
++ vfsgnj.vf v4, v8, fa2
|
|
|
++ vfsgnjn.vv v4, v8, v12
|
|
|
++ vfsgnjn.vf v4, v8, fa2
|
|
|
++ vfsgnjx.vv v4, v8, v12
|
|
|
++ vfsgnjx.vf v4, v8, fa2
|
|
|
++ vfsgnj.vv v4, v8, v12, v0.t
|
|
|
++ vfsgnj.vf v4, v8, fa2, v0.t
|
|
|
++ vfsgnjn.vv v4, v8, v12, v0.t
|
|
|
++ vfsgnjn.vf v4, v8, fa2, v0.t
|
|
|
++ vfsgnjx.vv v4, v8, v12, v0.t
|
|
|
++ vfsgnjx.vf v4, v8, fa2, v0.t
|
|
|
++
|
|
|
++ # Aliases
|
|
|
++ vmfgt.vv v4, v8, v12
|
|
|
++ vmfge.vv v4, v8, v12
|
|
|
++ vmfgt.vv v4, v8, v12, v0.t
|
|
|
++ vmfge.vv v4, v8, v12, v0.t
|
|
|
++
|
|
|
++ vmfeq.vv v4, v8, v12
|
|
|
++ vmfeq.vf v4, v8, fa2
|
|
|
++ vmfne.vv v4, v8, v12
|
|
|
++ vmfne.vf v4, v8, fa2
|
|
|
++ vmflt.vv v4, v8, v12
|
|
|
++ vmflt.vf v4, v8, fa2
|
|
|
++ vmfle.vv v4, v8, v12
|
|
|
++ vmfle.vf v4, v8, fa2
|
|
|
++ vmfgt.vf v4, v8, fa2
|
|
|
++ vmfge.vf v4, v8, fa2
|
|
|
++ vmfeq.vv v4, v8, v12, v0.t
|
|
|
++ vmfeq.vf v4, v8, fa2, v0.t
|
|
|
++ vmfne.vv v4, v8, v12, v0.t
|
|
|
++ vmfne.vf v4, v8, fa2, v0.t
|
|
|
++ vmflt.vv v4, v8, v12, v0.t
|
|
|
++ vmflt.vf v4, v8, fa2, v0.t
|
|
|
++ vmfle.vv v4, v8, v12, v0.t
|
|
|
++ vmfle.vf v4, v8, fa2, v0.t
|
|
|
++ vmfgt.vf v4, v8, fa2, v0.t
|
|
|
++ vmfge.vf v4, v8, fa2, v0.t
|
|
|
++
|
|
|
++ vfmerge.vfm v4, v8, fa2, v0
|
|
|
++ vfmv.v.f v4, fa1
|
|
|
++
|
|
|
++ # Aliases
|
|
|
++ vmcpy.m v4, v8
|
|
|
++ vmmv.m v4, v8
|
|
|
++ vmclr.m v4
|
|
|
++ vmset.m v4
|
|
|
++ vmnot.m v4, v8
|
|
|
++
|
|
|
++ vmand.mm v4, v8, v12
|
|
|
++ vmnand.mm v4, v8, v12
|
|
|
++ vmandnot.mm v4, v8, v12
|
|
|
++ vmxor.mm v4, v8, v12
|
|
|
++ vmor.mm v4, v8, v12
|
|
|
++ vmnor.mm v4, v8, v12
|
|
|
++ vmornot.mm v4, v8, v12
|
|
|
++ vmxnor.mm v4, v8, v12
|
|
|
++
|
|
|
++ vpopc.m a0, v12
|
|
|
++ vfirst.m a0, v12
|
|
|
++ vpopc.m a0, v12, v0.t
|
|
|
++ vfirst.m a0, v12, v0.t
|
|
|
++
|
|
|
++ vmv.x.s a0, v12
|
|
|
++ vmv.s.x v4, a0
|
|
|
++
|
|
|
++ vfmv.f.s fa0, v8
|
|
|
++ vfmv.s.f v4, fa1
|
|
|
++
|
|
|
++ vslideup.vx v4, v8, a1
|
|
|
++ vslideup.vi v4, v8, 0
|
|
|
++ vslideup.vi v4, v8, 31
|
|
|
++ vslidedown.vx v4, v8, a1
|
|
|
++ vslidedown.vi v4, v8, 0
|
|
|
++ vslidedown.vi v4, v8, 31
|
|
|
++ vslideup.vx v4, v8, a1, v0.t
|
|
|
++ vslideup.vi v4, v8, 0, v0.t
|
|
|
++ vslideup.vi v4, v8, 31, v0.t
|
|
|
++ vslidedown.vx v4, v8, a1, v0.t
|
|
|
++ vslidedown.vi v4, v8, 0, v0.t
|
|
|
++ vslidedown.vi v4, v8, 31, v0.t
|
|
|
++
|
|
|
++ vslide1up.vx v4, v8, a1
|
|
|
++ vslide1down.vx v4, v8, a1
|
|
|
++ vslide1up.vx v4, v8, a1, v0.t
|
|
|
++ vslide1down.vx v4, v8, a1, v0.t
|
|
|
++
|
|
|
++ vfslide1up.vf v4, v8, fa1
|
|
|
++ vfslide1down.vf v4, v8, fa1
|
|
|
++ vfslide1up.vf v4, v8, fa1, v0.t
|
|
|
++ vfslide1down.vf v4, v8, fa1, v0.t
|
|
|
++
|
|
|
++ vrgather.vv v4, v8, v12
|
|
|
++ vrgather.vx v4, v8, a1
|
|
|
++ vrgather.vi v4, v8, 0
|
|
|
++ vrgather.vi v4, v8, 31
|
|
|
++ vrgather.vv v4, v8, v12, v0.t
|
|
|
++ vrgather.vx v4, v8, a1, v0.t
|
|
|
++ vrgather.vi v4, v8, 0, v0.t
|
|
|
++ vrgather.vi v4, v8, 31, v0.t
|
|
|
++
|
|
|
++ vcompress.vm v4, v8, v12
|
|
|
++
|
|
|
+diff --git a/opcodes/riscv-opc.c b/opcodes/riscv-opc.c
|
|
|
+index b51e876977..df6b1659f8 100644
|
|
|
+--- a/opcodes/riscv-opc.c
|
|
|
++++ b/opcodes/riscv-opc.c
|
|
|
+@@ -1309,10 +1309,6 @@ const struct riscv_opcode riscv_opcodes[] =
|
|
|
+ /* RVV */
|
|
|
+ {"vsetvl", 0, INSN_CLASS_V, "d,s,t", MATCH_VSETVL, MASK_VSETVL, match_opcode, 0},
|
|
|
+ {"vsetvli", 0, INSN_CLASS_V, "d,s,Vc", MATCH_VSETVLI, MASK_VSETVLI, match_opcode, 0},
|
|
|
+-{"vsetivli", 0, INSN_CLASS_V, "d,Z,Vb", MATCH_VSETIVLI, MASK_VSETIVLI, match_opcode, 0},
|
|
|
+-
|
|
|
+-{"vle1.v", 0, INSN_CLASS_V, "Vd,0(s)", MATCH_VLE1V, MASK_VLE1V, match_opcode, INSN_DREF },
|
|
|
+-{"vse1.v", 0, INSN_CLASS_V, "Vd,0(s)", MATCH_VSE1V, MASK_VSE1V, match_opcode, INSN_DREF },
|
|
|
+
|
|
|
+ {"vle8.v", 0, INSN_CLASS_V, "Vd,0(s)Vm", MATCH_VLE8V, MASK_VLE8V, match_vd_neq_vm, INSN_DREF },
|
|
|
+ {"vle16.v", 0, INSN_CLASS_V, "Vd,0(s)Vm", MATCH_VLE16V, MASK_VLE16V, match_vd_neq_vm, INSN_DREF },
|
|
|
+@@ -1344,362 +1340,6 @@ const struct riscv_opcode riscv_opcodes[] =
|
|
|
+ {"vsoxei32.v", 0, INSN_CLASS_V, "Vd,0(s),VtVm", MATCH_VSOXEI32V, MASK_VSOXEI32V, match_vd_neq_vm, INSN_DREF },
|
|
|
+ {"vsoxei64.v", 0, INSN_CLASS_V, "Vd,0(s),VtVm", MATCH_VSOXEI64V, MASK_VSOXEI64V, match_vd_neq_vm, INSN_DREF },
|
|
|
+
|
|
|
+-{"vluxei8.v", 0, INSN_CLASS_V, "Vd,0(s),VtVm", MATCH_VLUXEI8V, MASK_VLUXEI8V, match_vd_neq_vm, INSN_DREF },
|
|
|
+-{"vluxei16.v", 0, INSN_CLASS_V, "Vd,0(s),VtVm", MATCH_VLUXEI16V, MASK_VLUXEI16V, match_vd_neq_vm, INSN_DREF },
|
|
|
+-{"vluxei32.v", 0, INSN_CLASS_V, "Vd,0(s),VtVm", MATCH_VLUXEI32V, MASK_VLUXEI32V, match_vd_neq_vm, INSN_DREF },
|
|
|
+-{"vluxei64.v", 0, INSN_CLASS_V, "Vd,0(s),VtVm", MATCH_VLUXEI64V, MASK_VLUXEI64V, match_vd_neq_vm, INSN_DREF },
|
|
|
+-
|
|
|
+-{"vsuxei8.v", 0, INSN_CLASS_V, "Vd,0(s),VtVm", MATCH_VSUXEI8V, MASK_VSUXEI8V, match_vd_neq_vm, INSN_DREF },
|
|
|
+-{"vsuxei16.v", 0, INSN_CLASS_V, "Vd,0(s),VtVm", MATCH_VSUXEI16V, MASK_VSUXEI16V, match_vd_neq_vm, INSN_DREF },
|
|
|
+-{"vsuxei32.v", 0, INSN_CLASS_V, "Vd,0(s),VtVm", MATCH_VSUXEI32V, MASK_VSUXEI32V, match_vd_neq_vm, INSN_DREF },
|
|
|
+-{"vsuxei64.v", 0, INSN_CLASS_V, "Vd,0(s),VtVm", MATCH_VSUXEI64V, MASK_VSUXEI64V, match_vd_neq_vm, INSN_DREF },
|
|
|
+-
|
|
|
+-{"vle8ff.v", 0, INSN_CLASS_V, "Vd,0(s)Vm", MATCH_VLE8FFV, MASK_VLE8FFV, match_vd_neq_vm, INSN_DREF },
|
|
|
+-{"vle16ff.v", 0, INSN_CLASS_V, "Vd,0(s)Vm", MATCH_VLE16FFV, MASK_VLE16FFV, match_vd_neq_vm, INSN_DREF },
|
|
|
+-{"vle32ff.v", 0, INSN_CLASS_V, "Vd,0(s)Vm", MATCH_VLE32FFV, MASK_VLE32FFV, match_vd_neq_vm, INSN_DREF },
|
|
|
+-{"vle64ff.v", 0, INSN_CLASS_V, "Vd,0(s)Vm", MATCH_VLE64FFV, MASK_VLE64FFV, match_vd_neq_vm, INSN_DREF },
|
|
|
+-
|
|
|
+-{"vlseg2e8.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s)Vm", MATCH_VLSEG2E8V, MASK_VLSEG2E8V, match_vd_neq_vm, INSN_DREF },
|
|
|
+-{"vsseg2e8.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s)Vm", MATCH_VSSEG2E8V, MASK_VSSEG2E8V, match_vd_neq_vm, INSN_DREF },
|
|
|
+-{"vlseg3e8.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s)Vm", MATCH_VLSEG3E8V, MASK_VLSEG3E8V, match_vd_neq_vm, INSN_DREF },
|
|
|
+-{"vsseg3e8.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s)Vm", MATCH_VSSEG3E8V, MASK_VSSEG3E8V, match_vd_neq_vm, INSN_DREF },
|
|
|
+-{"vlseg4e8.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s)Vm", MATCH_VLSEG4E8V, MASK_VLSEG4E8V, match_vd_neq_vm, INSN_DREF },
|
|
|
+-{"vsseg4e8.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s)Vm", MATCH_VSSEG4E8V, MASK_VSSEG4E8V, match_vd_neq_vm, INSN_DREF },
|
|
|
+-{"vlseg5e8.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s)Vm", MATCH_VLSEG5E8V, MASK_VLSEG5E8V, match_vd_neq_vm, INSN_DREF },
|
|
|
+-{"vsseg5e8.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s)Vm", MATCH_VSSEG5E8V, MASK_VSSEG5E8V, match_vd_neq_vm, INSN_DREF },
|
|
|
+-{"vlseg6e8.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s)Vm", MATCH_VLSEG6E8V, MASK_VLSEG6E8V, match_vd_neq_vm, INSN_DREF },
|
|
|
+-{"vsseg6e8.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s)Vm", MATCH_VSSEG6E8V, MASK_VSSEG6E8V, match_vd_neq_vm, INSN_DREF },
|
|
|
+-{"vlseg7e8.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s)Vm", MATCH_VLSEG7E8V, MASK_VLSEG7E8V, match_vd_neq_vm, INSN_DREF },
|
|
|
+-{"vsseg7e8.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s)Vm", MATCH_VSSEG7E8V, MASK_VSSEG7E8V, match_vd_neq_vm, INSN_DREF },
|
|
|
+-{"vlseg8e8.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s)Vm", MATCH_VLSEG8E8V, MASK_VLSEG8E8V, match_vd_neq_vm, INSN_DREF },
|
|
|
+-{"vsseg8e8.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s)Vm", MATCH_VSSEG8E8V, MASK_VSSEG8E8V, match_vd_neq_vm, INSN_DREF },
|
|
|
+-
|
|
|
+-{"vlseg2e16.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s)Vm", MATCH_VLSEG2E16V, MASK_VLSEG2E16V, match_vd_neq_vm, INSN_DREF },
|
|
|
+-{"vsseg2e16.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s)Vm", MATCH_VSSEG2E16V, MASK_VSSEG2E16V, match_vd_neq_vm, INSN_DREF },
|
|
|
+-{"vlseg3e16.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s)Vm", MATCH_VLSEG3E16V, MASK_VLSEG3E16V, match_vd_neq_vm, INSN_DREF },
|
|
|
+-{"vsseg3e16.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s)Vm", MATCH_VSSEG3E16V, MASK_VSSEG3E16V, match_vd_neq_vm, INSN_DREF },
|
|
|
+-{"vlseg4e16.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s)Vm", MATCH_VLSEG4E16V, MASK_VLSEG4E16V, match_vd_neq_vm, INSN_DREF },
|
|
|
+-{"vsseg4e16.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s)Vm", MATCH_VSSEG4E16V, MASK_VSSEG4E16V, match_vd_neq_vm, INSN_DREF },
|
|
|
+-{"vlseg5e16.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s)Vm", MATCH_VLSEG5E16V, MASK_VLSEG5E16V, match_vd_neq_vm, INSN_DREF },
|
|
|
+-{"vsseg5e16.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s)Vm", MATCH_VSSEG5E16V, MASK_VSSEG5E16V, match_vd_neq_vm, INSN_DREF },
|
|
|
+-{"vlseg6e16.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s)Vm", MATCH_VLSEG6E16V, MASK_VLSEG6E16V, match_vd_neq_vm, INSN_DREF },
|
|
|
+-{"vsseg6e16.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s)Vm", MATCH_VSSEG6E16V, MASK_VSSEG6E16V, match_vd_neq_vm, INSN_DREF },
|
|
|
+-{"vlseg7e16.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s)Vm", MATCH_VLSEG7E16V, MASK_VLSEG7E16V, match_vd_neq_vm, INSN_DREF },
|
|
|
+-{"vsseg7e16.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s)Vm", MATCH_VSSEG7E16V, MASK_VSSEG7E16V, match_vd_neq_vm, INSN_DREF },
|
|
|
+-{"vlseg8e16.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s)Vm", MATCH_VLSEG8E16V, MASK_VLSEG8E16V, match_vd_neq_vm, INSN_DREF },
|
|
|
+-{"vsseg8e16.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s)Vm", MATCH_VSSEG8E16V, MASK_VSSEG8E16V, match_vd_neq_vm, INSN_DREF },
|
|
|
+-
|
|
|
+-{"vlseg2e32.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s)Vm", MATCH_VLSEG2E32V, MASK_VLSEG2E32V, match_vd_neq_vm, INSN_DREF },
|
|
|
+-{"vsseg2e32.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s)Vm", MATCH_VSSEG2E32V, MASK_VSSEG2E32V, match_vd_neq_vm, INSN_DREF },
|
|
|
+-{"vlseg3e32.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s)Vm", MATCH_VLSEG3E32V, MASK_VLSEG3E32V, match_vd_neq_vm, INSN_DREF },
|
|
|
+-{"vsseg3e32.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s)Vm", MATCH_VSSEG3E32V, MASK_VSSEG3E32V, match_vd_neq_vm, INSN_DREF },
|
|
|
+-{"vlseg4e32.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s)Vm", MATCH_VLSEG4E32V, MASK_VLSEG4E32V, match_vd_neq_vm, INSN_DREF },
|
|
|
+-{"vsseg4e32.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s)Vm", MATCH_VSSEG4E32V, MASK_VSSEG4E32V, match_vd_neq_vm, INSN_DREF },
|
|
|
+-{"vlseg5e32.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s)Vm", MATCH_VLSEG5E32V, MASK_VLSEG5E32V, match_vd_neq_vm, INSN_DREF },
|
|
|
+-{"vsseg5e32.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s)Vm", MATCH_VSSEG5E32V, MASK_VSSEG5E32V, match_vd_neq_vm, INSN_DREF },
|
|
|
+-{"vlseg6e32.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s)Vm", MATCH_VLSEG6E32V, MASK_VLSEG6E32V, match_vd_neq_vm, INSN_DREF },
|
|
|
+-{"vsseg6e32.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s)Vm", MATCH_VSSEG6E32V, MASK_VSSEG6E32V, match_vd_neq_vm, INSN_DREF },
|
|
|
+-{"vlseg7e32.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s)Vm", MATCH_VLSEG7E32V, MASK_VLSEG7E32V, match_vd_neq_vm, INSN_DREF },
|
|
|
+-{"vsseg7e32.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s)Vm", MATCH_VSSEG7E32V, MASK_VSSEG7E32V, match_vd_neq_vm, INSN_DREF },
|
|
|
+-{"vlseg8e32.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s)Vm", MATCH_VLSEG8E32V, MASK_VLSEG8E32V, match_vd_neq_vm, INSN_DREF },
|
|
|
+-{"vsseg8e32.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s)Vm", MATCH_VSSEG8E32V, MASK_VSSEG8E32V, match_vd_neq_vm, INSN_DREF },
|
|
|
+-
|
|
|
+-{"vlseg2e64.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s)Vm", MATCH_VLSEG2E64V, MASK_VLSEG2E64V, match_vd_neq_vm, INSN_DREF },
|
|
|
+-{"vsseg2e64.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s)Vm", MATCH_VSSEG2E64V, MASK_VSSEG2E64V, match_vd_neq_vm, INSN_DREF },
|
|
|
+-{"vlseg3e64.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s)Vm", MATCH_VLSEG3E64V, MASK_VLSEG3E64V, match_vd_neq_vm, INSN_DREF },
|
|
|
+-{"vsseg3e64.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s)Vm", MATCH_VSSEG3E64V, MASK_VSSEG3E64V, match_vd_neq_vm, INSN_DREF },
|
|
|
+-{"vlseg4e64.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s)Vm", MATCH_VLSEG4E64V, MASK_VLSEG4E64V, match_vd_neq_vm, INSN_DREF },
|
|
|
+-{"vsseg4e64.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s)Vm", MATCH_VSSEG4E64V, MASK_VSSEG4E64V, match_vd_neq_vm, INSN_DREF },
|
|
|
+-{"vlseg5e64.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s)Vm", MATCH_VLSEG5E64V, MASK_VLSEG5E64V, match_vd_neq_vm, INSN_DREF },
|
|
|
+-{"vsseg5e64.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s)Vm", MATCH_VSSEG5E64V, MASK_VSSEG5E64V, match_vd_neq_vm, INSN_DREF },
|
|
|
+-{"vlseg6e64.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s)Vm", MATCH_VLSEG6E64V, MASK_VLSEG6E64V, match_vd_neq_vm, INSN_DREF },
|
|
|
+-{"vsseg6e64.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s)Vm", MATCH_VSSEG6E64V, MASK_VSSEG6E64V, match_vd_neq_vm, INSN_DREF },
|
|
|
+-{"vlseg7e64.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s)Vm", MATCH_VLSEG7E64V, MASK_VLSEG7E64V, match_vd_neq_vm, INSN_DREF },
|
|
|
+-{"vsseg7e64.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s)Vm", MATCH_VSSEG7E64V, MASK_VSSEG7E64V, match_vd_neq_vm, INSN_DREF },
|
|
|
+-{"vlseg8e64.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s)Vm", MATCH_VLSEG8E64V, MASK_VLSEG8E64V, match_vd_neq_vm, INSN_DREF },
|
|
|
+-{"vsseg8e64.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s)Vm", MATCH_VSSEG8E64V, MASK_VSSEG8E64V, match_vd_neq_vm, INSN_DREF },
|
|
|
+-
|
|
|
+-{"vlsseg2e8.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),tVm", MATCH_VLSSEG2E8V, MASK_VLSSEG2E8V, match_vd_neq_vm, INSN_DREF },
|
|
|
+-{"vssseg2e8.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),tVm", MATCH_VSSSEG2E8V, MASK_VSSSEG2E8V, match_vd_neq_vm, INSN_DREF },
|
|
|
+-{"vlsseg3e8.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),tVm", MATCH_VLSSEG3E8V, MASK_VLSSEG3E8V, match_vd_neq_vm, INSN_DREF },
|
|
|
+-{"vssseg3e8.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),tVm", MATCH_VSSSEG3E8V, MASK_VSSSEG3E8V, match_vd_neq_vm, INSN_DREF },
|
|
|
+-{"vlsseg4e8.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),tVm", MATCH_VLSSEG4E8V, MASK_VLSSEG4E8V, match_vd_neq_vm, INSN_DREF },
|
|
|
+-{"vssseg4e8.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),tVm", MATCH_VSSSEG4E8V, MASK_VSSSEG4E8V, match_vd_neq_vm, INSN_DREF },
|
|
|
+-{"vlsseg5e8.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),tVm", MATCH_VLSSEG5E8V, MASK_VLSSEG5E8V, match_vd_neq_vm, INSN_DREF },
|
|
|
+-{"vssseg5e8.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),tVm", MATCH_VSSSEG5E8V, MASK_VSSSEG5E8V, match_vd_neq_vm, INSN_DREF },
|
|
|
+-{"vlsseg6e8.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),tVm", MATCH_VLSSEG6E8V, MASK_VLSSEG6E8V, match_vd_neq_vm, INSN_DREF },
|
|
|
+-{"vssseg6e8.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),tVm", MATCH_VSSSEG6E8V, MASK_VSSSEG6E8V, match_vd_neq_vm, INSN_DREF },
|
|
|
+-{"vlsseg7e8.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),tVm", MATCH_VLSSEG7E8V, MASK_VLSSEG7E8V, match_vd_neq_vm, INSN_DREF },
|
|
|
+-{"vssseg7e8.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),tVm", MATCH_VSSSEG7E8V, MASK_VSSSEG7E8V, match_vd_neq_vm, INSN_DREF },
|
|
|
+-{"vlsseg8e8.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),tVm", MATCH_VLSSEG8E8V, MASK_VLSSEG8E8V, match_vd_neq_vm, INSN_DREF },
|
|
|
+-{"vssseg8e8.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),tVm", MATCH_VSSSEG8E8V, MASK_VSSSEG8E8V, match_vd_neq_vm, INSN_DREF },
|
|
|
+-
|
|
|
+-{"vlsseg2e16.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),tVm", MATCH_VLSSEG2E16V, MASK_VLSSEG2E16V, match_vd_neq_vm, INSN_DREF },
|
|
|
+-{"vssseg2e16.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),tVm", MATCH_VSSSEG2E16V, MASK_VSSSEG2E16V, match_vd_neq_vm, INSN_DREF },
|
|
|
+-{"vlsseg3e16.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),tVm", MATCH_VLSSEG3E16V, MASK_VLSSEG3E16V, match_vd_neq_vm, INSN_DREF },
|
|
|
+-{"vssseg3e16.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),tVm", MATCH_VSSSEG3E16V, MASK_VSSSEG3E16V, match_vd_neq_vm, INSN_DREF },
|
|
|
+-{"vlsseg4e16.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),tVm", MATCH_VLSSEG4E16V, MASK_VLSSEG4E16V, match_vd_neq_vm, INSN_DREF },
|
|
|
+-{"vssseg4e16.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),tVm", MATCH_VSSSEG4E16V, MASK_VSSSEG4E16V, match_vd_neq_vm, INSN_DREF },
|
|
|
+-{"vlsseg5e16.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),tVm", MATCH_VLSSEG5E16V, MASK_VLSSEG5E16V, match_vd_neq_vm, INSN_DREF },
|
|
|
+-{"vssseg5e16.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),tVm", MATCH_VSSSEG5E16V, MASK_VSSSEG5E16V, match_vd_neq_vm, INSN_DREF },
|
|
|
+-{"vlsseg6e16.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),tVm", MATCH_VLSSEG6E16V, MASK_VLSSEG6E16V, match_vd_neq_vm, INSN_DREF },
|
|
|
+-{"vssseg6e16.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),tVm", MATCH_VSSSEG6E16V, MASK_VSSSEG6E16V, match_vd_neq_vm, INSN_DREF },
|
|
|
+-{"vlsseg7e16.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),tVm", MATCH_VLSSEG7E16V, MASK_VLSSEG7E16V, match_vd_neq_vm, INSN_DREF },
|
|
|
+-{"vssseg7e16.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),tVm", MATCH_VSSSEG7E16V, MASK_VSSSEG7E16V, match_vd_neq_vm, INSN_DREF },
|
|
|
+-{"vlsseg8e16.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),tVm", MATCH_VLSSEG8E16V, MASK_VLSSEG8E16V, match_vd_neq_vm, INSN_DREF },
|
|
|
+-{"vssseg8e16.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),tVm", MATCH_VSSSEG8E16V, MASK_VSSSEG8E16V, match_vd_neq_vm, INSN_DREF },
|
|
|
+-
|
|
|
+-{"vlsseg2e32.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),tVm", MATCH_VLSSEG2E32V, MASK_VLSSEG2E32V, match_vd_neq_vm, INSN_DREF },
|
|
|
+-{"vssseg2e32.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),tVm", MATCH_VSSSEG2E32V, MASK_VSSSEG2E32V, match_vd_neq_vm, INSN_DREF },
|
|
|
+-{"vlsseg3e32.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),tVm", MATCH_VLSSEG3E32V, MASK_VLSSEG3E32V, match_vd_neq_vm, INSN_DREF },
|
|
|
+-{"vssseg3e32.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),tVm", MATCH_VSSSEG3E32V, MASK_VSSSEG3E32V, match_vd_neq_vm, INSN_DREF },
|
|
|
+-{"vlsseg4e32.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),tVm", MATCH_VLSSEG4E32V, MASK_VLSSEG4E32V, match_vd_neq_vm, INSN_DREF },
|
|
|
+-{"vssseg4e32.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),tVm", MATCH_VSSSEG4E32V, MASK_VSSSEG4E32V, match_vd_neq_vm, INSN_DREF },
|
|
|
+-{"vlsseg5e32.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),tVm", MATCH_VLSSEG5E32V, MASK_VLSSEG5E32V, match_vd_neq_vm, INSN_DREF },
|
|
|
+-{"vssseg5e32.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),tVm", MATCH_VSSSEG5E32V, MASK_VSSSEG5E32V, match_vd_neq_vm, INSN_DREF },
|
|
|
+-{"vlsseg6e32.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),tVm", MATCH_VLSSEG6E32V, MASK_VLSSEG6E32V, match_vd_neq_vm, INSN_DREF },
|
|
|
+-{"vssseg6e32.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),tVm", MATCH_VSSSEG6E32V, MASK_VSSSEG6E32V, match_vd_neq_vm, INSN_DREF },
|
|
|
+-{"vlsseg7e32.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),tVm", MATCH_VLSSEG7E32V, MASK_VLSSEG7E32V, match_vd_neq_vm, INSN_DREF },
|
|
|
+-{"vssseg7e32.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),tVm", MATCH_VSSSEG7E32V, MASK_VSSSEG7E32V, match_vd_neq_vm, INSN_DREF },
|
|
|
+-{"vlsseg8e32.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),tVm", MATCH_VLSSEG8E32V, MASK_VLSSEG8E32V, match_vd_neq_vm, INSN_DREF },
|
|
|
+-{"vssseg8e32.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),tVm", MATCH_VSSSEG8E32V, MASK_VSSSEG8E32V, match_vd_neq_vm, INSN_DREF },
|
|
|
+-
|
|
|
+-{"vlsseg2e64.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),tVm", MATCH_VLSSEG2E64V, MASK_VLSSEG2E64V, match_vd_neq_vm, INSN_DREF },
|
|
|
+-{"vssseg2e64.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),tVm", MATCH_VSSSEG2E64V, MASK_VSSSEG2E64V, match_vd_neq_vm, INSN_DREF },
|
|
|
+-{"vlsseg3e64.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),tVm", MATCH_VLSSEG3E64V, MASK_VLSSEG3E64V, match_vd_neq_vm, INSN_DREF },
|
|
|
+-{"vssseg3e64.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),tVm", MATCH_VSSSEG3E64V, MASK_VSSSEG3E64V, match_vd_neq_vm, INSN_DREF },
|
|
|
+-{"vlsseg4e64.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),tVm", MATCH_VLSSEG4E64V, MASK_VLSSEG4E64V, match_vd_neq_vm, INSN_DREF },
|
|
|
+-{"vssseg4e64.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),tVm", MATCH_VSSSEG4E64V, MASK_VSSSEG4E64V, match_vd_neq_vm, INSN_DREF },
|
|
|
+-{"vlsseg5e64.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),tVm", MATCH_VLSSEG5E64V, MASK_VLSSEG5E64V, match_vd_neq_vm, INSN_DREF },
|
|
|
+-{"vssseg5e64.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),tVm", MATCH_VSSSEG5E64V, MASK_VSSSEG5E64V, match_vd_neq_vm, INSN_DREF },
|
|
|
+-{"vlsseg6e64.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),tVm", MATCH_VLSSEG6E64V, MASK_VLSSEG6E64V, match_vd_neq_vm, INSN_DREF },
|
|
|
+-{"vssseg6e64.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),tVm", MATCH_VSSSEG6E64V, MASK_VSSSEG6E64V, match_vd_neq_vm, INSN_DREF },
|
|
|
+-{"vlsseg7e64.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),tVm", MATCH_VLSSEG7E64V, MASK_VLSSEG7E64V, match_vd_neq_vm, INSN_DREF },
|
|
|
+-{"vssseg7e64.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),tVm", MATCH_VSSSEG7E64V, MASK_VSSSEG7E64V, match_vd_neq_vm, INSN_DREF },
|
|
|
+-{"vlsseg8e64.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),tVm", MATCH_VLSSEG8E64V, MASK_VLSSEG8E64V, match_vd_neq_vm, INSN_DREF },
|
|
|
+-{"vssseg8e64.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),tVm", MATCH_VSSSEG8E64V, MASK_VSSSEG8E64V, match_vd_neq_vm, INSN_DREF },
|
|
|
+-
|
|
|
+-{"vloxseg2ei8.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),VtVm", MATCH_VLOXSEG2EI8V, MASK_VLOXSEG2EI8V, match_vd_neq_vs2_neq_vm, INSN_DREF },
|
|
|
+-{"vsoxseg2ei8.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),VtVm", MATCH_VSOXSEG2EI8V, MASK_VSOXSEG2EI8V, match_vd_neq_vs2_neq_vm, INSN_DREF },
|
|
|
+-{"vloxseg3ei8.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),VtVm", MATCH_VLOXSEG3EI8V, MASK_VLOXSEG3EI8V, match_vd_neq_vs2_neq_vm, INSN_DREF },
|
|
|
+-{"vsoxseg3ei8.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),VtVm", MATCH_VSOXSEG3EI8V, MASK_VSOXSEG3EI8V, match_vd_neq_vs2_neq_vm, INSN_DREF },
|
|
|
+-{"vloxseg4ei8.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),VtVm", MATCH_VLOXSEG4EI8V, MASK_VLOXSEG4EI8V, match_vd_neq_vs2_neq_vm, INSN_DREF },
|
|
|
+-{"vsoxseg4ei8.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),VtVm", MATCH_VSOXSEG4EI8V, MASK_VSOXSEG4EI8V, match_vd_neq_vs2_neq_vm, INSN_DREF },
|
|
|
+-{"vloxseg5ei8.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),VtVm", MATCH_VLOXSEG5EI8V, MASK_VLOXSEG5EI8V, match_vd_neq_vs2_neq_vm, INSN_DREF },
|
|
|
+-{"vsoxseg5ei8.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),VtVm", MATCH_VSOXSEG5EI8V, MASK_VSOXSEG5EI8V, match_vd_neq_vs2_neq_vm, INSN_DREF },
|
|
|
+-{"vloxseg6ei8.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),VtVm", MATCH_VLOXSEG6EI8V, MASK_VLOXSEG6EI8V, match_vd_neq_vs2_neq_vm, INSN_DREF },
|
|
|
+-{"vsoxseg6ei8.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),VtVm", MATCH_VSOXSEG6EI8V, MASK_VSOXSEG6EI8V, match_vd_neq_vs2_neq_vm, INSN_DREF },
|
|
|
+-{"vloxseg7ei8.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),VtVm", MATCH_VLOXSEG7EI8V, MASK_VLOXSEG7EI8V, match_vd_neq_vs2_neq_vm, INSN_DREF },
|
|
|
+-{"vsoxseg7ei8.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),VtVm", MATCH_VSOXSEG7EI8V, MASK_VSOXSEG7EI8V, match_vd_neq_vs2_neq_vm, INSN_DREF },
|
|
|
+-{"vloxseg8ei8.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),VtVm", MATCH_VLOXSEG8EI8V, MASK_VLOXSEG8EI8V, match_vd_neq_vs2_neq_vm, INSN_DREF },
|
|
|
+-{"vsoxseg8ei8.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),VtVm", MATCH_VSOXSEG8EI8V, MASK_VSOXSEG8EI8V, match_vd_neq_vs2_neq_vm, INSN_DREF },
|
|
|
+-
|
|
|
+-{"vloxseg2ei16.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),VtVm", MATCH_VLOXSEG2EI16V, MASK_VLOXSEG2EI16V, match_vd_neq_vs2_neq_vm, INSN_DREF },
|
|
|
+-{"vsoxseg2ei16.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),VtVm", MATCH_VSOXSEG2EI16V, MASK_VSOXSEG2EI16V, match_vd_neq_vs2_neq_vm, INSN_DREF },
|
|
|
+-{"vloxseg3ei16.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),VtVm", MATCH_VLOXSEG3EI16V, MASK_VLOXSEG3EI16V, match_vd_neq_vs2_neq_vm, INSN_DREF },
|
|
|
+-{"vsoxseg3ei16.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),VtVm", MATCH_VSOXSEG3EI16V, MASK_VSOXSEG3EI16V, match_vd_neq_vs2_neq_vm, INSN_DREF },
|
|
|
+-{"vloxseg4ei16.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),VtVm", MATCH_VLOXSEG4EI16V, MASK_VLOXSEG4EI16V, match_vd_neq_vs2_neq_vm, INSN_DREF },
|
|
|
+-{"vsoxseg4ei16.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),VtVm", MATCH_VSOXSEG4EI16V, MASK_VSOXSEG4EI16V, match_vd_neq_vs2_neq_vm, INSN_DREF },
|
|
|
+-{"vloxseg5ei16.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),VtVm", MATCH_VLOXSEG5EI16V, MASK_VLOXSEG5EI16V, match_vd_neq_vs2_neq_vm, INSN_DREF },
|
|
|
+-{"vsoxseg5ei16.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),VtVm", MATCH_VSOXSEG5EI16V, MASK_VSOXSEG5EI16V, match_vd_neq_vs2_neq_vm, INSN_DREF },
|
|
|
+-{"vloxseg6ei16.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),VtVm", MATCH_VLOXSEG6EI16V, MASK_VLOXSEG6EI16V, match_vd_neq_vs2_neq_vm, INSN_DREF },
|
|
|
+-{"vsoxseg6ei16.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),VtVm", MATCH_VSOXSEG6EI16V, MASK_VSOXSEG6EI16V, match_vd_neq_vs2_neq_vm, INSN_DREF },
|
|
|
+-{"vloxseg7ei16.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),VtVm", MATCH_VLOXSEG7EI16V, MASK_VLOXSEG7EI16V, match_vd_neq_vs2_neq_vm, INSN_DREF },
|
|
|
+-{"vsoxseg7ei16.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),VtVm", MATCH_VSOXSEG7EI16V, MASK_VSOXSEG7EI16V, match_vd_neq_vs2_neq_vm, INSN_DREF },
|
|
|
+-{"vloxseg8ei16.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),VtVm", MATCH_VLOXSEG8EI16V, MASK_VLOXSEG8EI16V, match_vd_neq_vs2_neq_vm, INSN_DREF },
|
|
|
+-{"vsoxseg8ei16.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),VtVm", MATCH_VSOXSEG8EI16V, MASK_VSOXSEG8EI16V, match_vd_neq_vs2_neq_vm, INSN_DREF },
|
|
|
+-
|
|
|
+-{"vloxseg2ei32.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),VtVm", MATCH_VLOXSEG2EI32V, MASK_VLOXSEG2EI32V, match_vd_neq_vs2_neq_vm, INSN_DREF },
|
|
|
+-{"vsoxseg2ei32.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),VtVm", MATCH_VSOXSEG2EI32V, MASK_VSOXSEG2EI32V, match_vd_neq_vs2_neq_vm, INSN_DREF },
|
|
|
+-{"vloxseg3ei32.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),VtVm", MATCH_VLOXSEG3EI32V, MASK_VLOXSEG3EI32V, match_vd_neq_vs2_neq_vm, INSN_DREF },
|
|
|
+-{"vsoxseg3ei32.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),VtVm", MATCH_VSOXSEG3EI32V, MASK_VSOXSEG3EI32V, match_vd_neq_vs2_neq_vm, INSN_DREF },
|
|
|
+-{"vloxseg4ei32.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),VtVm", MATCH_VLOXSEG4EI32V, MASK_VLOXSEG4EI32V, match_vd_neq_vs2_neq_vm, INSN_DREF },
|
|
|
+-{"vsoxseg4ei32.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),VtVm", MATCH_VSOXSEG4EI32V, MASK_VSOXSEG4EI32V, match_vd_neq_vs2_neq_vm, INSN_DREF },
|
|
|
+-{"vloxseg5ei32.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),VtVm", MATCH_VLOXSEG5EI32V, MASK_VLOXSEG5EI32V, match_vd_neq_vs2_neq_vm, INSN_DREF },
|
|
|
+-{"vsoxseg5ei32.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),VtVm", MATCH_VSOXSEG5EI32V, MASK_VSOXSEG5EI32V, match_vd_neq_vs2_neq_vm, INSN_DREF },
|
|
|
+-{"vloxseg6ei32.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),VtVm", MATCH_VLOXSEG6EI32V, MASK_VLOXSEG6EI32V, match_vd_neq_vs2_neq_vm, INSN_DREF },
|
|
|
+-{"vsoxseg6ei32.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),VtVm", MATCH_VSOXSEG6EI32V, MASK_VSOXSEG6EI32V, match_vd_neq_vs2_neq_vm, INSN_DREF },
|
|
|
+-{"vloxseg7ei32.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),VtVm", MATCH_VLOXSEG7EI32V, MASK_VLOXSEG7EI32V, match_vd_neq_vs2_neq_vm, INSN_DREF },
|
|
|
+-{"vsoxseg7ei32.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),VtVm", MATCH_VSOXSEG7EI32V, MASK_VSOXSEG7EI32V, match_vd_neq_vs2_neq_vm, INSN_DREF },
|
|
|
+-{"vloxseg8ei32.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),VtVm", MATCH_VLOXSEG8EI32V, MASK_VLOXSEG8EI32V, match_vd_neq_vs2_neq_vm, INSN_DREF },
|
|
|
+-{"vsoxseg8ei32.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),VtVm", MATCH_VSOXSEG8EI32V, MASK_VSOXSEG8EI32V, match_vd_neq_vs2_neq_vm, INSN_DREF },
|
|
|
+-
|
|
|
+-{"vloxseg2ei64.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),VtVm", MATCH_VLOXSEG2EI64V, MASK_VLOXSEG2EI64V, match_vd_neq_vs2_neq_vm, INSN_DREF },
|
|
|
+-{"vsoxseg2ei64.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),VtVm", MATCH_VSOXSEG2EI64V, MASK_VSOXSEG2EI64V, match_vd_neq_vs2_neq_vm, INSN_DREF },
|
|
|
+-{"vloxseg3ei64.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),VtVm", MATCH_VLOXSEG3EI64V, MASK_VLOXSEG3EI64V, match_vd_neq_vs2_neq_vm, INSN_DREF },
|
|
|
+-{"vsoxseg3ei64.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),VtVm", MATCH_VSOXSEG3EI64V, MASK_VSOXSEG3EI64V, match_vd_neq_vs2_neq_vm, INSN_DREF },
|
|
|
+-{"vloxseg4ei64.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),VtVm", MATCH_VLOXSEG4EI64V, MASK_VLOXSEG4EI64V, match_vd_neq_vs2_neq_vm, INSN_DREF },
|
|
|
+-{"vsoxseg4ei64.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),VtVm", MATCH_VSOXSEG4EI64V, MASK_VSOXSEG4EI64V, match_vd_neq_vs2_neq_vm, INSN_DREF },
|
|
|
+-{"vloxseg5ei64.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),VtVm", MATCH_VLOXSEG5EI64V, MASK_VLOXSEG5EI64V, match_vd_neq_vs2_neq_vm, INSN_DREF },
|
|
|
+-{"vsoxseg5ei64.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),VtVm", MATCH_VSOXSEG5EI64V, MASK_VSOXSEG5EI64V, match_vd_neq_vs2_neq_vm, INSN_DREF },
|
|
|
+-{"vloxseg6ei64.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),VtVm", MATCH_VLOXSEG6EI64V, MASK_VLOXSEG6EI64V, match_vd_neq_vs2_neq_vm, INSN_DREF },
|
|
|
+-{"vsoxseg6ei64.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),VtVm", MATCH_VSOXSEG6EI64V, MASK_VSOXSEG6EI64V, match_vd_neq_vs2_neq_vm, INSN_DREF },
|
|
|
+-{"vloxseg7ei64.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),VtVm", MATCH_VLOXSEG7EI64V, MASK_VLOXSEG7EI64V, match_vd_neq_vs2_neq_vm, INSN_DREF },
|
|
|
+-{"vsoxseg7ei64.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),VtVm", MATCH_VSOXSEG7EI64V, MASK_VSOXSEG7EI64V, match_vd_neq_vs2_neq_vm, INSN_DREF },
|
|
|
+-{"vloxseg8ei64.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),VtVm", MATCH_VLOXSEG8EI64V, MASK_VLOXSEG8EI64V, match_vd_neq_vs2_neq_vm, INSN_DREF },
|
|
|
+-{"vsoxseg8ei64.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),VtVm", MATCH_VSOXSEG8EI64V, MASK_VSOXSEG8EI64V, match_vd_neq_vs2_neq_vm, INSN_DREF },
|
|
|
+-
|
|
|
+-{"vluxseg2ei8.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),VtVm", MATCH_VLUXSEG2EI8V, MASK_VLUXSEG2EI8V, match_vd_neq_vs2_neq_vm, INSN_DREF },
|
|
|
+-{"vsuxseg2ei8.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),VtVm", MATCH_VSUXSEG2EI8V, MASK_VSUXSEG2EI8V, match_vd_neq_vs2_neq_vm, INSN_DREF },
|
|
|
+-{"vluxseg3ei8.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),VtVm", MATCH_VLUXSEG3EI8V, MASK_VLUXSEG3EI8V, match_vd_neq_vs2_neq_vm, INSN_DREF },
|
|
|
+-{"vsuxseg3ei8.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),VtVm", MATCH_VSUXSEG3EI8V, MASK_VSUXSEG3EI8V, match_vd_neq_vs2_neq_vm, INSN_DREF },
|
|
|
+-{"vluxseg4ei8.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),VtVm", MATCH_VLUXSEG4EI8V, MASK_VLUXSEG4EI8V, match_vd_neq_vs2_neq_vm, INSN_DREF },
|
|
|
+-{"vsuxseg4ei8.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),VtVm", MATCH_VSUXSEG4EI8V, MASK_VSUXSEG4EI8V, match_vd_neq_vs2_neq_vm, INSN_DREF },
|
|
|
+-{"vluxseg5ei8.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),VtVm", MATCH_VLUXSEG5EI8V, MASK_VLUXSEG5EI8V, match_vd_neq_vs2_neq_vm, INSN_DREF },
|
|
|
+-{"vsuxseg5ei8.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),VtVm", MATCH_VSUXSEG5EI8V, MASK_VSUXSEG5EI8V, match_vd_neq_vs2_neq_vm, INSN_DREF },
|
|
|
+-{"vluxseg6ei8.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),VtVm", MATCH_VLUXSEG6EI8V, MASK_VLUXSEG6EI8V, match_vd_neq_vs2_neq_vm, INSN_DREF },
|
|
|
+-{"vsuxseg6ei8.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),VtVm", MATCH_VSUXSEG6EI8V, MASK_VSUXSEG6EI8V, match_vd_neq_vs2_neq_vm, INSN_DREF },
|
|
|
+-{"vluxseg7ei8.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),VtVm", MATCH_VLUXSEG7EI8V, MASK_VLUXSEG7EI8V, match_vd_neq_vs2_neq_vm, INSN_DREF },
|
|
|
+-{"vsuxseg7ei8.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),VtVm", MATCH_VSUXSEG7EI8V, MASK_VSUXSEG7EI8V, match_vd_neq_vs2_neq_vm, INSN_DREF },
|
|
|
+-{"vluxseg8ei8.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),VtVm", MATCH_VLUXSEG8EI8V, MASK_VLUXSEG8EI8V, match_vd_neq_vs2_neq_vm, INSN_DREF },
|
|
|
+-{"vsuxseg8ei8.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),VtVm", MATCH_VSUXSEG8EI8V, MASK_VSUXSEG8EI8V, match_vd_neq_vs2_neq_vm, INSN_DREF },
|
|
|
+-
|
|
|
+-{"vluxseg2ei16.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),VtVm", MATCH_VLUXSEG2EI16V, MASK_VLUXSEG2EI16V, match_vd_neq_vs2_neq_vm, INSN_DREF },
|
|
|
+-{"vsuxseg2ei16.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),VtVm", MATCH_VSUXSEG2EI16V, MASK_VSUXSEG2EI16V, match_vd_neq_vs2_neq_vm, INSN_DREF },
|
|
|
+-{"vluxseg3ei16.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),VtVm", MATCH_VLUXSEG3EI16V, MASK_VLUXSEG3EI16V, match_vd_neq_vs2_neq_vm, INSN_DREF },
|
|
|
+-{"vsuxseg3ei16.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),VtVm", MATCH_VSUXSEG3EI16V, MASK_VSUXSEG3EI16V, match_vd_neq_vs2_neq_vm, INSN_DREF },
|
|
|
+-{"vluxseg4ei16.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),VtVm", MATCH_VLUXSEG4EI16V, MASK_VLUXSEG4EI16V, match_vd_neq_vs2_neq_vm, INSN_DREF },
|
|
|
+-{"vsuxseg4ei16.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),VtVm", MATCH_VSUXSEG4EI16V, MASK_VSUXSEG4EI16V, match_vd_neq_vs2_neq_vm, INSN_DREF },
|
|
|
+-{"vluxseg5ei16.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),VtVm", MATCH_VLUXSEG5EI16V, MASK_VLUXSEG5EI16V, match_vd_neq_vs2_neq_vm, INSN_DREF },
|
|
|
+-{"vsuxseg5ei16.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),VtVm", MATCH_VSUXSEG5EI16V, MASK_VSUXSEG5EI16V, match_vd_neq_vs2_neq_vm, INSN_DREF },
|
|
|
+-{"vluxseg6ei16.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),VtVm", MATCH_VLUXSEG6EI16V, MASK_VLUXSEG6EI16V, match_vd_neq_vs2_neq_vm, INSN_DREF },
|
|
|
+-{"vsuxseg6ei16.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),VtVm", MATCH_VSUXSEG6EI16V, MASK_VSUXSEG6EI16V, match_vd_neq_vs2_neq_vm, INSN_DREF },
|
|
|
+-{"vluxseg7ei16.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),VtVm", MATCH_VLUXSEG7EI16V, MASK_VLUXSEG7EI16V, match_vd_neq_vs2_neq_vm, INSN_DREF },
|
|
|
+-{"vsuxseg7ei16.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),VtVm", MATCH_VSUXSEG7EI16V, MASK_VSUXSEG7EI16V, match_vd_neq_vs2_neq_vm, INSN_DREF },
|
|
|
+-{"vluxseg8ei16.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),VtVm", MATCH_VLUXSEG8EI16V, MASK_VLUXSEG8EI16V, match_vd_neq_vs2_neq_vm, INSN_DREF },
|
|
|
+-{"vsuxseg8ei16.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),VtVm", MATCH_VSUXSEG8EI16V, MASK_VSUXSEG8EI16V, match_vd_neq_vs2_neq_vm, INSN_DREF },
|
|
|
+-
|
|
|
+-{"vluxseg2ei32.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),VtVm", MATCH_VLUXSEG2EI32V, MASK_VLUXSEG2EI32V, match_vd_neq_vs2_neq_vm, INSN_DREF },
|
|
|
+-{"vsuxseg2ei32.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),VtVm", MATCH_VSUXSEG2EI32V, MASK_VSUXSEG2EI32V, match_vd_neq_vs2_neq_vm, INSN_DREF },
|
|
|
+-{"vluxseg3ei32.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),VtVm", MATCH_VLUXSEG3EI32V, MASK_VLUXSEG3EI32V, match_vd_neq_vs2_neq_vm, INSN_DREF },
|
|
|
+-{"vsuxseg3ei32.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),VtVm", MATCH_VSUXSEG3EI32V, MASK_VSUXSEG3EI32V, match_vd_neq_vs2_neq_vm, INSN_DREF },
|
|
|
+-{"vluxseg4ei32.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),VtVm", MATCH_VLUXSEG4EI32V, MASK_VLUXSEG4EI32V, match_vd_neq_vs2_neq_vm, INSN_DREF },
|
|
|
+-{"vsuxseg4ei32.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),VtVm", MATCH_VSUXSEG4EI32V, MASK_VSUXSEG4EI32V, match_vd_neq_vs2_neq_vm, INSN_DREF },
|
|
|
+-{"vluxseg5ei32.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),VtVm", MATCH_VLUXSEG5EI32V, MASK_VLUXSEG5EI32V, match_vd_neq_vs2_neq_vm, INSN_DREF },
|
|
|
+-{"vsuxseg5ei32.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),VtVm", MATCH_VSUXSEG5EI32V, MASK_VSUXSEG5EI32V, match_vd_neq_vs2_neq_vm, INSN_DREF },
|
|
|
+-{"vluxseg6ei32.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),VtVm", MATCH_VLUXSEG6EI32V, MASK_VLUXSEG6EI32V, match_vd_neq_vs2_neq_vm, INSN_DREF },
|
|
|
+-{"vsuxseg6ei32.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),VtVm", MATCH_VSUXSEG6EI32V, MASK_VSUXSEG6EI32V, match_vd_neq_vs2_neq_vm, INSN_DREF },
|
|
|
+-{"vluxseg7ei32.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),VtVm", MATCH_VLUXSEG7EI32V, MASK_VLUXSEG7EI32V, match_vd_neq_vs2_neq_vm, INSN_DREF },
|
|
|
+-{"vsuxseg7ei32.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),VtVm", MATCH_VSUXSEG7EI32V, MASK_VSUXSEG7EI32V, match_vd_neq_vs2_neq_vm, INSN_DREF },
|
|
|
+-{"vluxseg8ei32.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),VtVm", MATCH_VLUXSEG8EI32V, MASK_VLUXSEG8EI32V, match_vd_neq_vs2_neq_vm, INSN_DREF },
|
|
|
+-{"vsuxseg8ei32.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),VtVm", MATCH_VSUXSEG8EI32V, MASK_VSUXSEG8EI32V, match_vd_neq_vs2_neq_vm, INSN_DREF },
|
|
|
+-
|
|
|
+-{"vluxseg2ei64.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),VtVm", MATCH_VLUXSEG2EI64V, MASK_VLUXSEG2EI64V, match_vd_neq_vs2_neq_vm, INSN_DREF },
|
|
|
+-{"vsuxseg2ei64.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),VtVm", MATCH_VSUXSEG2EI64V, MASK_VSUXSEG2EI64V, match_vd_neq_vs2_neq_vm, INSN_DREF },
|
|
|
+-{"vluxseg3ei64.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),VtVm", MATCH_VLUXSEG3EI64V, MASK_VLUXSEG3EI64V, match_vd_neq_vs2_neq_vm, INSN_DREF },
|
|
|
+-{"vsuxseg3ei64.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),VtVm", MATCH_VSUXSEG3EI64V, MASK_VSUXSEG3EI64V, match_vd_neq_vs2_neq_vm, INSN_DREF },
|
|
|
+-{"vluxseg4ei64.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),VtVm", MATCH_VLUXSEG4EI64V, MASK_VLUXSEG4EI64V, match_vd_neq_vs2_neq_vm, INSN_DREF },
|
|
|
+-{"vsuxseg4ei64.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),VtVm", MATCH_VSUXSEG4EI64V, MASK_VSUXSEG4EI64V, match_vd_neq_vs2_neq_vm, INSN_DREF },
|
|
|
+-{"vluxseg5ei64.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),VtVm", MATCH_VLUXSEG5EI64V, MASK_VLUXSEG5EI64V, match_vd_neq_vs2_neq_vm, INSN_DREF },
|
|
|
+-{"vsuxseg5ei64.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),VtVm", MATCH_VSUXSEG5EI64V, MASK_VSUXSEG5EI64V, match_vd_neq_vs2_neq_vm, INSN_DREF },
|
|
|
+-{"vluxseg6ei64.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),VtVm", MATCH_VLUXSEG6EI64V, MASK_VLUXSEG6EI64V, match_vd_neq_vs2_neq_vm, INSN_DREF },
|
|
|
+-{"vsuxseg6ei64.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),VtVm", MATCH_VSUXSEG6EI64V, MASK_VSUXSEG6EI64V, match_vd_neq_vs2_neq_vm, INSN_DREF },
|
|
|
+-{"vluxseg7ei64.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),VtVm", MATCH_VLUXSEG7EI64V, MASK_VLUXSEG7EI64V, match_vd_neq_vs2_neq_vm, INSN_DREF },
|
|
|
+-{"vsuxseg7ei64.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),VtVm", MATCH_VSUXSEG7EI64V, MASK_VSUXSEG7EI64V, match_vd_neq_vs2_neq_vm, INSN_DREF },
|
|
|
+-{"vluxseg8ei64.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),VtVm", MATCH_VLUXSEG8EI64V, MASK_VLUXSEG8EI64V, match_vd_neq_vs2_neq_vm, INSN_DREF },
|
|
|
+-{"vsuxseg8ei64.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),VtVm", MATCH_VSUXSEG8EI64V, MASK_VSUXSEG8EI64V, match_vd_neq_vs2_neq_vm, INSN_DREF },
|
|
|
+-
|
|
|
+-{"vlseg2e8ff.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s)Vm", MATCH_VLSEG2E8FFV, MASK_VLSEG2E8FFV, match_vd_neq_vm, INSN_DREF },
|
|
|
+-{"vlseg3e8ff.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s)Vm", MATCH_VLSEG3E8FFV, MASK_VLSEG3E8FFV, match_vd_neq_vm, INSN_DREF },
|
|
|
+-{"vlseg4e8ff.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s)Vm", MATCH_VLSEG4E8FFV, MASK_VLSEG4E8FFV, match_vd_neq_vm, INSN_DREF },
|
|
|
+-{"vlseg5e8ff.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s)Vm", MATCH_VLSEG5E8FFV, MASK_VLSEG5E8FFV, match_vd_neq_vm, INSN_DREF },
|
|
|
+-{"vlseg6e8ff.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s)Vm", MATCH_VLSEG6E8FFV, MASK_VLSEG6E8FFV, match_vd_neq_vm, INSN_DREF },
|
|
|
+-{"vlseg7e8ff.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s)Vm", MATCH_VLSEG7E8FFV, MASK_VLSEG7E8FFV, match_vd_neq_vm, INSN_DREF },
|
|
|
+-{"vlseg8e8ff.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s)Vm", MATCH_VLSEG8E8FFV, MASK_VLSEG8E8FFV, match_vd_neq_vm, INSN_DREF },
|
|
|
+-
|
|
|
+-{"vlseg2e16ff.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s)Vm", MATCH_VLSEG2E16FFV, MASK_VLSEG2E16FFV, match_vd_neq_vm, INSN_DREF },
|
|
|
+-{"vlseg3e16ff.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s)Vm", MATCH_VLSEG3E16FFV, MASK_VLSEG3E16FFV, match_vd_neq_vm, INSN_DREF },
|
|
|
+-{"vlseg4e16ff.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s)Vm", MATCH_VLSEG4E16FFV, MASK_VLSEG4E16FFV, match_vd_neq_vm, INSN_DREF },
|
|
|
+-{"vlseg5e16ff.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s)Vm", MATCH_VLSEG5E16FFV, MASK_VLSEG5E16FFV, match_vd_neq_vm, INSN_DREF },
|
|
|
+-{"vlseg6e16ff.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s)Vm", MATCH_VLSEG6E16FFV, MASK_VLSEG6E16FFV, match_vd_neq_vm, INSN_DREF },
|
|
|
+-{"vlseg7e16ff.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s)Vm", MATCH_VLSEG7E16FFV, MASK_VLSEG7E16FFV, match_vd_neq_vm, INSN_DREF },
|
|
|
+-{"vlseg8e16ff.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s)Vm", MATCH_VLSEG8E16FFV, MASK_VLSEG8E16FFV, match_vd_neq_vm, INSN_DREF },
|
|
|
+-
|
|
|
+-{"vlseg2e32ff.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s)Vm", MATCH_VLSEG2E32FFV, MASK_VLSEG2E32FFV, match_vd_neq_vm, INSN_DREF },
|
|
|
+-{"vlseg3e32ff.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s)Vm", MATCH_VLSEG3E32FFV, MASK_VLSEG3E32FFV, match_vd_neq_vm, INSN_DREF },
|
|
|
+-{"vlseg4e32ff.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s)Vm", MATCH_VLSEG4E32FFV, MASK_VLSEG4E32FFV, match_vd_neq_vm, INSN_DREF },
|
|
|
+-{"vlseg5e32ff.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s)Vm", MATCH_VLSEG5E32FFV, MASK_VLSEG5E32FFV, match_vd_neq_vm, INSN_DREF },
|
|
|
+-{"vlseg6e32ff.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s)Vm", MATCH_VLSEG6E32FFV, MASK_VLSEG6E32FFV, match_vd_neq_vm, INSN_DREF },
|
|
|
+-{"vlseg7e32ff.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s)Vm", MATCH_VLSEG7E32FFV, MASK_VLSEG7E32FFV, match_vd_neq_vm, INSN_DREF },
|
|
|
+-{"vlseg8e32ff.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s)Vm", MATCH_VLSEG8E32FFV, MASK_VLSEG8E32FFV, match_vd_neq_vm, INSN_DREF },
|
|
|
+-
|
|
|
+-{"vlseg2e64ff.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s)Vm", MATCH_VLSEG2E64FFV, MASK_VLSEG2E64FFV, match_vd_neq_vm, INSN_DREF },
|
|
|
+-{"vlseg3e64ff.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s)Vm", MATCH_VLSEG3E64FFV, MASK_VLSEG3E64FFV, match_vd_neq_vm, INSN_DREF },
|
|
|
+-{"vlseg4e64ff.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s)Vm", MATCH_VLSEG4E64FFV, MASK_VLSEG4E64FFV, match_vd_neq_vm, INSN_DREF },
|
|
|
+-{"vlseg5e64ff.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s)Vm", MATCH_VLSEG5E64FFV, MASK_VLSEG5E64FFV, match_vd_neq_vm, INSN_DREF },
|
|
|
+-{"vlseg6e64ff.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s)Vm", MATCH_VLSEG6E64FFV, MASK_VLSEG6E64FFV, match_vd_neq_vm, INSN_DREF },
|
|
|
+-{"vlseg7e64ff.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s)Vm", MATCH_VLSEG7E64FFV, MASK_VLSEG7E64FFV, match_vd_neq_vm, INSN_DREF },
|
|
|
+-{"vlseg8e64ff.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s)Vm", MATCH_VLSEG8E64FFV, MASK_VLSEG8E64FFV, match_vd_neq_vm, INSN_DREF },
|
|
|
+-
|
|
|
+-{"vl1r.v", 0, INSN_CLASS_V, "Vd,0(s)", MATCH_VL1RE8V, MASK_VL1RE8V, match_vls_nf_rv, INSN_DREF|INSN_ALIAS },
|
|
|
+-{"vl1re8.v", 0, INSN_CLASS_V, "Vd,0(s)", MATCH_VL1RE8V, MASK_VL1RE8V, match_vls_nf_rv, INSN_DREF },
|
|
|
+-{"vl1re16.v", 0, INSN_CLASS_V, "Vd,0(s)", MATCH_VL1RE16V, MASK_VL1RE16V, match_vls_nf_rv, INSN_DREF },
|
|
|
+-{"vl1re32.v", 0, INSN_CLASS_V, "Vd,0(s)", MATCH_VL1RE32V, MASK_VL1RE32V, match_vls_nf_rv, INSN_DREF },
|
|
|
+-{"vl1re64.v", 0, INSN_CLASS_V, "Vd,0(s)", MATCH_VL1RE64V, MASK_VL1RE64V, match_vls_nf_rv, INSN_DREF },
|
|
|
+-
|
|
|
+-{"vl2r.v", 0, INSN_CLASS_V, "Vd,0(s)", MATCH_VL2RE8V, MASK_VL2RE8V, match_vls_nf_rv, INSN_DREF|INSN_ALIAS },
|
|
|
+-{"vl2re8.v", 0, INSN_CLASS_V, "Vd,0(s)", MATCH_VL2RE8V, MASK_VL2RE8V, match_vls_nf_rv, INSN_DREF },
|
|
|
+-{"vl2re16.v", 0, INSN_CLASS_V, "Vd,0(s)", MATCH_VL2RE16V, MASK_VL2RE16V, match_vls_nf_rv, INSN_DREF },
|
|
|
+-{"vl2re32.v", 0, INSN_CLASS_V, "Vd,0(s)", MATCH_VL2RE32V, MASK_VL2RE32V, match_vls_nf_rv, INSN_DREF },
|
|
|
+-{"vl2re64.v", 0, INSN_CLASS_V, "Vd,0(s)", MATCH_VL2RE64V, MASK_VL2RE64V, match_vls_nf_rv, INSN_DREF },
|
|
|
+-
|
|
|
+-{"vl4r.v", 0, INSN_CLASS_V, "Vd,0(s)", MATCH_VL4RE8V, MASK_VL4RE8V, match_vls_nf_rv, INSN_DREF|INSN_ALIAS },
|
|
|
+-{"vl4re8.v", 0, INSN_CLASS_V, "Vd,0(s)", MATCH_VL4RE8V, MASK_VL4RE8V, match_vls_nf_rv, INSN_DREF },
|
|
|
+-{"vl4re16.v", 0, INSN_CLASS_V, "Vd,0(s)", MATCH_VL4RE16V, MASK_VL4RE16V, match_vls_nf_rv, INSN_DREF },
|
|
|
+-{"vl4re32.v", 0, INSN_CLASS_V, "Vd,0(s)", MATCH_VL4RE32V, MASK_VL4RE32V, match_vls_nf_rv, INSN_DREF },
|
|
|
+-{"vl4re64.v", 0, INSN_CLASS_V, "Vd,0(s)", MATCH_VL4RE64V, MASK_VL4RE64V, match_vls_nf_rv, INSN_DREF },
|
|
|
+-
|
|
|
+-{"vl8r.v", 0, INSN_CLASS_V, "Vd,0(s)", MATCH_VL8RE8V, MASK_VL8RE8V, match_vls_nf_rv, INSN_DREF|INSN_ALIAS },
|
|
|
+-{"vl8re8.v", 0, INSN_CLASS_V, "Vd,0(s)", MATCH_VL8RE8V, MASK_VL8RE8V, match_vls_nf_rv, INSN_DREF },
|
|
|
+-{"vl8re16.v", 0, INSN_CLASS_V, "Vd,0(s)", MATCH_VL8RE16V, MASK_VL8RE16V, match_vls_nf_rv, INSN_DREF },
|
|
|
+-{"vl8re32.v", 0, INSN_CLASS_V, "Vd,0(s)", MATCH_VL8RE32V, MASK_VL8RE32V, match_vls_nf_rv, INSN_DREF },
|
|
|
+-{"vl8re64.v", 0, INSN_CLASS_V, "Vd,0(s)", MATCH_VL8RE64V, MASK_VL8RE64V, match_vls_nf_rv, INSN_DREF },
|
|
|
+-
|
|
|
+-{"vs1r.v", 0, INSN_CLASS_V, "Vd,0(s)", MATCH_VS1RV, MASK_VS1RV, match_vls_nf_rv, INSN_DREF },
|
|
|
+-{"vs2r.v", 0, INSN_CLASS_V, "Vd,0(s)", MATCH_VS2RV, MASK_VS2RV, match_vls_nf_rv, INSN_DREF },
|
|
|
+-{"vs4r.v", 0, INSN_CLASS_V, "Vd,0(s)", MATCH_VS4RV, MASK_VS4RV, match_vls_nf_rv, INSN_DREF },
|
|
|
+-{"vs8r.v", 0, INSN_CLASS_V, "Vd,0(s)", MATCH_VS8RV, MASK_VS8RV, match_vls_nf_rv, INSN_DREF },
|
|
|
+-
|
|
|
+-{"vamoaddei8.v", 0, INSN_CLASS_V_OR_ZVAMO, "Ve,0(s),Vt,VfVm", MATCH_VAMOADDEI8V, MASK_VAMOADDEI8V, match_vd_neq_vm, INSN_DREF},
|
|
|
+-{"vamoswapei8.v", 0, INSN_CLASS_V_OR_ZVAMO, "Ve,0(s),Vt,VfVm", MATCH_VAMOSWAPEI8V, MASK_VAMOSWAPEI8V, match_vd_neq_vm, INSN_DREF},
|
|
|
+-{"vamoxorei8.v", 0, INSN_CLASS_V_OR_ZVAMO, "Ve,0(s),Vt,VfVm", MATCH_VAMOXOREI8V, MASK_VAMOXOREI8V, match_vd_neq_vm, INSN_DREF},
|
|
|
+-{"vamoandei8.v", 0, INSN_CLASS_V_OR_ZVAMO, "Ve,0(s),Vt,VfVm", MATCH_VAMOANDEI8V, MASK_VAMOANDEI8V, match_vd_neq_vm, INSN_DREF},
|
|
|
+-{"vamoorei8.v", 0, INSN_CLASS_V_OR_ZVAMO, "Ve,0(s),Vt,VfVm", MATCH_VAMOOREI8V, MASK_VAMOOREI8V, match_vd_neq_vm, INSN_DREF},
|
|
|
+-{"vamominei8.v", 0, INSN_CLASS_V_OR_ZVAMO, "Ve,0(s),Vt,VfVm", MATCH_VAMOMINEI8V, MASK_VAMOMINEI8V, match_vd_neq_vm, INSN_DREF},
|
|
|
+-{"vamomaxei8.v", 0, INSN_CLASS_V_OR_ZVAMO, "Ve,0(s),Vt,VfVm", MATCH_VAMOMAXEI8V, MASK_VAMOMAXEI8V, match_vd_neq_vm, INSN_DREF},
|
|
|
+-{"vamominuei8.v", 0, INSN_CLASS_V_OR_ZVAMO, "Ve,0(s),Vt,VfVm", MATCH_VAMOMINUEI8V, MASK_VAMOMINUEI8V, match_vd_neq_vm, INSN_DREF},
|
|
|
+-{"vamomaxuei8.v", 0, INSN_CLASS_V_OR_ZVAMO, "Ve,0(s),Vt,VfVm", MATCH_VAMOMAXUEI8V, MASK_VAMOMAXUEI8V, match_vd_neq_vm, INSN_DREF},
|
|
|
+-
|
|
|
+-{"vamoaddei16.v", 0, INSN_CLASS_V_OR_ZVAMO, "Ve,0(s),Vt,VfVm", MATCH_VAMOADDEI16V, MASK_VAMOADDEI16V, match_vd_neq_vm, INSN_DREF},
|
|
|
+-{"vamoswapei16.v", 0, INSN_CLASS_V_OR_ZVAMO, "Ve,0(s),Vt,VfVm", MATCH_VAMOSWAPEI16V, MASK_VAMOSWAPEI16V, match_vd_neq_vm, INSN_DREF},
|
|
|
+-{"vamoxorei16.v", 0, INSN_CLASS_V_OR_ZVAMO, "Ve,0(s),Vt,VfVm", MATCH_VAMOXOREI16V, MASK_VAMOXOREI16V, match_vd_neq_vm, INSN_DREF},
|
|
|
+-{"vamoandei16.v", 0, INSN_CLASS_V_OR_ZVAMO, "Ve,0(s),Vt,VfVm", MATCH_VAMOANDEI16V, MASK_VAMOANDEI16V, match_vd_neq_vm, INSN_DREF},
|
|
|
+-{"vamoorei16.v", 0, INSN_CLASS_V_OR_ZVAMO, "Ve,0(s),Vt,VfVm", MATCH_VAMOOREI16V, MASK_VAMOOREI16V, match_vd_neq_vm, INSN_DREF},
|
|
|
+-{"vamominei16.v", 0, INSN_CLASS_V_OR_ZVAMO, "Ve,0(s),Vt,VfVm", MATCH_VAMOMINEI16V, MASK_VAMOMINEI16V, match_vd_neq_vm, INSN_DREF},
|
|
|
+-{"vamomaxei16.v", 0, INSN_CLASS_V_OR_ZVAMO, "Ve,0(s),Vt,VfVm", MATCH_VAMOMAXEI16V, MASK_VAMOMAXEI16V, match_vd_neq_vm, INSN_DREF},
|
|
|
+-{"vamominuei16.v", 0, INSN_CLASS_V_OR_ZVAMO, "Ve,0(s),Vt,VfVm", MATCH_VAMOMINUEI16V, MASK_VAMOMINUEI16V, match_vd_neq_vm, INSN_DREF},
|
|
|
+-{"vamomaxuei16.v", 0, INSN_CLASS_V_OR_ZVAMO, "Ve,0(s),Vt,VfVm", MATCH_VAMOMAXUEI16V, MASK_VAMOMAXUEI16V, match_vd_neq_vm, INSN_DREF},
|
|
|
+-
|
|
|
+-{"vamoaddei32.v", 0, INSN_CLASS_V_OR_ZVAMO, "Ve,0(s),Vt,VfVm", MATCH_VAMOADDEI32V, MASK_VAMOADDEI32V, match_vd_neq_vm, INSN_DREF},
|
|
|
+-{"vamoswapei32.v", 0, INSN_CLASS_V_OR_ZVAMO, "Ve,0(s),Vt,VfVm", MATCH_VAMOSWAPEI32V, MASK_VAMOSWAPEI32V, match_vd_neq_vm, INSN_DREF},
|
|
|
+-{"vamoxorei32.v", 0, INSN_CLASS_V_OR_ZVAMO, "Ve,0(s),Vt,VfVm", MATCH_VAMOXOREI32V, MASK_VAMOXOREI32V, match_vd_neq_vm, INSN_DREF},
|
|
|
+-{"vamoandei32.v", 0, INSN_CLASS_V_OR_ZVAMO, "Ve,0(s),Vt,VfVm", MATCH_VAMOANDEI32V, MASK_VAMOANDEI32V, match_vd_neq_vm, INSN_DREF},
|
|
|
+-{"vamoorei32.v", 0, INSN_CLASS_V_OR_ZVAMO, "Ve,0(s),Vt,VfVm", MATCH_VAMOOREI32V, MASK_VAMOOREI32V, match_vd_neq_vm, INSN_DREF},
|
|
|
+-{"vamominei32.v", 0, INSN_CLASS_V_OR_ZVAMO, "Ve,0(s),Vt,VfVm", MATCH_VAMOMINEI32V, MASK_VAMOMINEI32V, match_vd_neq_vm, INSN_DREF},
|
|
|
+-{"vamomaxei32.v", 0, INSN_CLASS_V_OR_ZVAMO, "Ve,0(s),Vt,VfVm", MATCH_VAMOMAXEI32V, MASK_VAMOMAXEI32V, match_vd_neq_vm, INSN_DREF},
|
|
|
+-{"vamominuei32.v", 0, INSN_CLASS_V_OR_ZVAMO, "Ve,0(s),Vt,VfVm", MATCH_VAMOMINUEI32V, MASK_VAMOMINUEI32V, match_vd_neq_vm, INSN_DREF},
|
|
|
+-{"vamomaxuei32.v", 0, INSN_CLASS_V_OR_ZVAMO, "Ve,0(s),Vt,VfVm", MATCH_VAMOMAXUEI32V, MASK_VAMOMAXUEI32V, match_vd_neq_vm, INSN_DREF},
|
|
|
+-
|
|
|
+-{"vamoaddei64.v", 0, INSN_CLASS_V_OR_ZVAMO, "Ve,0(s),Vt,VfVm", MATCH_VAMOADDEI64V, MASK_VAMOADDEI64V, match_vd_neq_vm, INSN_DREF},
|
|
|
+-{"vamoswapei64.v", 0, INSN_CLASS_V_OR_ZVAMO, "Ve,0(s),Vt,VfVm", MATCH_VAMOSWAPEI64V, MASK_VAMOSWAPEI64V, match_vd_neq_vm, INSN_DREF},
|
|
|
+-{"vamoxorei64.v", 0, INSN_CLASS_V_OR_ZVAMO, "Ve,0(s),Vt,VfVm", MATCH_VAMOXOREI64V, MASK_VAMOXOREI64V, match_vd_neq_vm, INSN_DREF},
|
|
|
+-{"vamoandei64.v", 0, INSN_CLASS_V_OR_ZVAMO, "Ve,0(s),Vt,VfVm", MATCH_VAMOANDEI64V, MASK_VAMOANDEI64V, match_vd_neq_vm, INSN_DREF},
|
|
|
+-{"vamoorei64.v", 0, INSN_CLASS_V_OR_ZVAMO, "Ve,0(s),Vt,VfVm", MATCH_VAMOOREI64V, MASK_VAMOOREI64V, match_vd_neq_vm, INSN_DREF},
|
|
|
+-{"vamominei64.v", 0, INSN_CLASS_V_OR_ZVAMO, "Ve,0(s),Vt,VfVm", MATCH_VAMOMINEI64V, MASK_VAMOMINEI64V, match_vd_neq_vm, INSN_DREF},
|
|
|
+-{"vamomaxei64.v", 0, INSN_CLASS_V_OR_ZVAMO, "Ve,0(s),Vt,VfVm", MATCH_VAMOMAXEI64V, MASK_VAMOMAXEI64V, match_vd_neq_vm, INSN_DREF},
|
|
|
+-{"vamominuei64.v", 0, INSN_CLASS_V_OR_ZVAMO, "Ve,0(s),Vt,VfVm", MATCH_VAMOMINUEI64V, MASK_VAMOMINUEI64V, match_vd_neq_vm, INSN_DREF},
|
|
|
+-{"vamomaxuei64.v", 0, INSN_CLASS_V_OR_ZVAMO, "Ve,0(s),Vt,VfVm", MATCH_VAMOMAXUEI64V, MASK_VAMOMAXUEI64V, match_vd_neq_vm, INSN_DREF},
|
|
|
+-
|
|
|
+ {"vneg.v", 0, INSN_CLASS_V, "Vd,VtVm", MATCH_VRSUBVX, MASK_VRSUBVX | MASK_RS1, match_vd_neq_vm, INSN_ALIAS },
|
|
|
+
|
|
|
+ {"vadd.vv", 0, INSN_CLASS_V, "Vd,Vt,VsVm", MATCH_VADDVV, MASK_VADDVV, match_vd_neq_vm, 0 },
|
|
|
+@@ -1710,26 +1350,6 @@ const struct riscv_opcode riscv_opcodes[] =
|
|
|
+ {"vrsub.vx", 0, INSN_CLASS_V, "Vd,Vt,sVm", MATCH_VRSUBVX, MASK_VRSUBVX, match_vd_neq_vm, 0 },
|
|
|
+ {"vrsub.vi", 0, INSN_CLASS_V, "Vd,Vt,ViVm", MATCH_VRSUBVI, MASK_VRSUBVI, match_vd_neq_vm, 0 },
|
|
|
+
|
|
|
+-{"vwcvt.x.x.v", 0, INSN_CLASS_V, "Vd,VtVm", MATCH_VWCVTXXV, MASK_VWCVTXXV, match_widen_vd_neq_vs2_neq_vm, INSN_ALIAS },
|
|
|
+-{"vwcvtu.x.x.v", 0, INSN_CLASS_V, "Vd,VtVm", MATCH_VWCVTUXXV, MASK_VWCVTUXXV, match_widen_vd_neq_vs2_neq_vm, INSN_ALIAS },
|
|
|
+-
|
|
|
+-{"vwaddu.vv", 0, INSN_CLASS_V, "Vd,Vt,VsVm", MATCH_VWADDUVV, MASK_VWADDUVV, match_widen_vd_neq_vs1_neq_vs2_neq_vm, 0 },
|
|
|
+-{"vwaddu.vx", 0, INSN_CLASS_V, "Vd,Vt,sVm", MATCH_VWADDUVX, MASK_VWADDUVX, match_widen_vd_neq_vs2_neq_vm, 0 },
|
|
|
+-{"vwsubu.vv", 0, INSN_CLASS_V, "Vd,Vt,VsVm", MATCH_VWSUBUVV, MASK_VWSUBUVV, match_widen_vd_neq_vs1_neq_vs2_neq_vm, 0 },
|
|
|
+-{"vwsubu.vx", 0, INSN_CLASS_V, "Vd,Vt,sVm", MATCH_VWSUBUVX, MASK_VWSUBUVX, match_widen_vd_neq_vs2_neq_vm, 0 },
|
|
|
+-{"vwadd.vv", 0, INSN_CLASS_V, "Vd,Vt,VsVm", MATCH_VWADDVV, MASK_VWADDVV, match_widen_vd_neq_vs1_neq_vs2_neq_vm, 0 },
|
|
|
+-{"vwadd.vx", 0, INSN_CLASS_V, "Vd,Vt,sVm", MATCH_VWADDVX, MASK_VWADDVX, match_widen_vd_neq_vs2_neq_vm, 0 },
|
|
|
+-{"vwsub.vv", 0, INSN_CLASS_V, "Vd,Vt,VsVm", MATCH_VWSUBVV, MASK_VWSUBVV, match_widen_vd_neq_vs1_neq_vs2_neq_vm, 0 },
|
|
|
+-{"vwsub.vx", 0, INSN_CLASS_V, "Vd,Vt,sVm", MATCH_VWSUBVX, MASK_VWSUBVX, match_widen_vd_neq_vs2_neq_vm, 0 },
|
|
|
+-{"vwaddu.wv", 0, INSN_CLASS_V, "Vd,Vt,VsVm", MATCH_VWADDUWV, MASK_VWADDUWV, match_widen_vd_neq_vs1_neq_vm, 0 },
|
|
|
+-{"vwaddu.wx", 0, INSN_CLASS_V, "Vd,Vt,sVm", MATCH_VWADDUWX, MASK_VWADDUWX, match_widen_vd_neq_vm, 0 },
|
|
|
+-{"vwsubu.wv", 0, INSN_CLASS_V, "Vd,Vt,VsVm", MATCH_VWSUBUWV, MASK_VWSUBUWV, match_widen_vd_neq_vs1_neq_vm, 0 },
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|
|
+-{"vwsubu.wx", 0, INSN_CLASS_V, "Vd,Vt,sVm", MATCH_VWSUBUWX, MASK_VWSUBUWX, match_widen_vd_neq_vm, 0 },
|
|
|
+-{"vwadd.wv", 0, INSN_CLASS_V, "Vd,Vt,VsVm", MATCH_VWADDWV, MASK_VWADDWV, match_widen_vd_neq_vs1_neq_vm, 0 },
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|
|
+-{"vwadd.wx", 0, INSN_CLASS_V, "Vd,Vt,sVm", MATCH_VWADDWX, MASK_VWADDWX, match_widen_vd_neq_vm, 0 },
|
|
|
+-{"vwsub.wv", 0, INSN_CLASS_V, "Vd,Vt,VsVm", MATCH_VWSUBWV, MASK_VWSUBWV, match_widen_vd_neq_vs1_neq_vm, 0 },
|
|
|
+-{"vwsub.wx", 0, INSN_CLASS_V, "Vd,Vt,sVm", MATCH_VWSUBWX, MASK_VWSUBWX, match_widen_vd_neq_vm, 0 },
|
|
|
+-
|
|
|
+ {"vzext.vf2", 0, INSN_CLASS_V, "Vd,VtVm", MATCH_VZEXT_VF2, MASK_VZEXT_VF2, match_vd_neq_vm, 0 },
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|
|
+ {"vsext.vf2", 0, INSN_CLASS_V, "Vd,VtVm", MATCH_VSEXT_VF2, MASK_VSEXT_VF2, match_vd_neq_vm, 0 },
|
|
|
+ {"vzext.vf4", 0, INSN_CLASS_V, "Vd,VtVm", MATCH_VZEXT_VF4, MASK_VZEXT_VF4, match_vd_neq_vm, 0 },
|
|
|
+@@ -1765,25 +1385,6 @@ const struct riscv_opcode riscv_opcodes[] =
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|
+ {"vxor.vx", 0, INSN_CLASS_V, "Vd,Vt,sVm", MATCH_VXORVX, MASK_VXORVX, match_vd_neq_vm, 0 },
|
|
|
+ {"vxor.vi", 0, INSN_CLASS_V, "Vd,Vt,ViVm", MATCH_VXORVI, MASK_VXORVI, match_vd_neq_vm, 0 },
|
|
|
+
|
|
|
+-{"vsll.vv", 0, INSN_CLASS_V, "Vd,Vt,VsVm", MATCH_VSLLVV, MASK_VSLLVV, match_vd_neq_vm, 0 },
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|
|
+-{"vsll.vx", 0, INSN_CLASS_V, "Vd,Vt,sVm", MATCH_VSLLVX, MASK_VSLLVX, match_vd_neq_vm, 0 },
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|
+-{"vsll.vi", 0, INSN_CLASS_V, "Vd,Vt,VjVm", MATCH_VSLLVI, MASK_VSLLVI, match_vd_neq_vm, 0 },
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|
+-{"vsrl.vv", 0, INSN_CLASS_V, "Vd,Vt,VsVm", MATCH_VSRLVV, MASK_VSRLVV, match_vd_neq_vm, 0 },
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|
+-{"vsrl.vx", 0, INSN_CLASS_V, "Vd,Vt,sVm", MATCH_VSRLVX, MASK_VSRLVX, match_vd_neq_vm, 0 },
|
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|
+-{"vsrl.vi", 0, INSN_CLASS_V, "Vd,Vt,VjVm", MATCH_VSRLVI, MASK_VSRLVI, match_vd_neq_vm, 0 },
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|
+-{"vsra.vv", 0, INSN_CLASS_V, "Vd,Vt,VsVm", MATCH_VSRAVV, MASK_VSRAVV, match_vd_neq_vm, 0 },
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|
+-{"vsra.vx", 0, INSN_CLASS_V, "Vd,Vt,sVm", MATCH_VSRAVX, MASK_VSRAVX, match_vd_neq_vm, 0 },
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|
+-{"vsra.vi", 0, INSN_CLASS_V, "Vd,Vt,VjVm", MATCH_VSRAVI, MASK_VSRAVI, match_vd_neq_vm, 0 },
|
|
|
+-
|
|
|
+-{"vncvt.x.x.w",0, INSN_CLASS_V, "Vd,VtVm", MATCH_VNCVTXXW, MASK_VNCVTXXW, match_narrow_vd_neq_vs2_neq_vm, INSN_ALIAS },
|
|
|
+-
|
|
|
+-{"vnsrl.wv", 0, INSN_CLASS_V, "Vd,Vt,VsVm", MATCH_VNSRLWV, MASK_VNSRLWV, match_narrow_vd_neq_vs2_neq_vm, 0 },
|
|
|
+-{"vnsrl.wx", 0, INSN_CLASS_V, "Vd,Vt,sVm", MATCH_VNSRLWX, MASK_VNSRLWX, match_narrow_vd_neq_vs2_neq_vm, 0 },
|
|
|
+-{"vnsrl.wi", 0, INSN_CLASS_V, "Vd,Vt,VjVm", MATCH_VNSRLWI, MASK_VNSRLWI, match_narrow_vd_neq_vs2_neq_vm, 0 },
|
|
|
+-{"vnsra.wv", 0, INSN_CLASS_V, "Vd,Vt,VsVm", MATCH_VNSRAWV, MASK_VNSRAWV, match_narrow_vd_neq_vs2_neq_vm, 0 },
|
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|
+-{"vnsra.wx", 0, INSN_CLASS_V, "Vd,Vt,sVm", MATCH_VNSRAWX, MASK_VNSRAWX, match_narrow_vd_neq_vs2_neq_vm, 0 },
|
|
|
+-{"vnsra.wi", 0, INSN_CLASS_V, "Vd,Vt,VjVm", MATCH_VNSRAWI, MASK_VNSRAWI, match_narrow_vd_neq_vs2_neq_vm, 0 },
|
|
|
+-
|
|
|
+ {"vmseq.vv", 0, INSN_CLASS_V, "Vd,Vt,VsVm", MATCH_VMSEQVV, MASK_VMSEQVV, match_opcode, 0 },
|
|
|
+ {"vmseq.vx", 0, INSN_CLASS_V, "Vd,Vt,sVm", MATCH_VMSEQVX, MASK_VMSEQVX, match_opcode, 0 },
|
|
|
+ {"vmseq.vi", 0, INSN_CLASS_V, "Vd,Vt,ViVm", MATCH_VMSEQVI, MASK_VMSEQVI, match_opcode, 0 },
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|
|
+@@ -1840,13 +1441,6 @@ const struct riscv_opcode riscv_opcodes[] =
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|
|
+ {"vmulhsu.vv", 0, INSN_CLASS_V, "Vd,Vt,VsVm", MATCH_VMULHSUVV, MASK_VMULHSUVV, match_vd_neq_vm, 0 },
|
|
|
+ {"vmulhsu.vx", 0, INSN_CLASS_V, "Vd,Vt,sVm", MATCH_VMULHSUVX, MASK_VMULHSUVX, match_vd_neq_vm, 0 },
|
|
|
+
|
|
|
+-{"vwmul.vv", 0, INSN_CLASS_V, "Vd,Vt,VsVm", MATCH_VWMULVV, MASK_VWMULVV, match_widen_vd_neq_vs1_neq_vs2_neq_vm, 0 },
|
|
|
+-{"vwmul.vx", 0, INSN_CLASS_V, "Vd,Vt,sVm", MATCH_VWMULVX, MASK_VWMULVX, match_widen_vd_neq_vs2_neq_vm, 0 },
|
|
|
+-{"vwmulu.vv", 0, INSN_CLASS_V, "Vd,Vt,VsVm", MATCH_VWMULUVV, MASK_VWMULUVV, match_widen_vd_neq_vs1_neq_vs2_neq_vm, 0 },
|
|
|
+-{"vwmulu.vx", 0, INSN_CLASS_V, "Vd,Vt,sVm", MATCH_VWMULUVX, MASK_VWMULUVX, match_widen_vd_neq_vs2_neq_vm, 0 },
|
|
|
+-{"vwmulsu.vv", 0, INSN_CLASS_V, "Vd,Vt,VsVm", MATCH_VWMULSUVV, MASK_VWMULSUVV, match_widen_vd_neq_vs1_neq_vs2_neq_vm, 0 },
|
|
|
+-{"vwmulsu.vx", 0, INSN_CLASS_V, "Vd,Vt,sVm", MATCH_VWMULSUVX, MASK_VWMULSUVX, match_widen_vd_neq_vs2_neq_vm, 0 },
|
|
|
+-
|
|
|
+ {"vmacc.vv", 0, INSN_CLASS_V, "Vd,Vs,VtVm", MATCH_VMACCVV, MASK_VMACCVV, match_vd_neq_vm, 0},
|
|
|
+ {"vmacc.vx", 0, INSN_CLASS_V, "Vd,s,VtVm", MATCH_VMACCVX, MASK_VMACCVX, match_vd_neq_vm, 0},
|
|
|
+ {"vnmsac.vv", 0, INSN_CLASS_V, "Vd,Vs,VtVm", MATCH_VNMSACVV, MASK_VNMSACVV, match_vd_neq_vm, 0},
|
|
|
+@@ -1856,14 +1450,6 @@ const struct riscv_opcode riscv_opcodes[] =
|
|
|
+ {"vnmsub.vv", 0, INSN_CLASS_V, "Vd,Vs,VtVm", MATCH_VNMSUBVV, MASK_VNMSUBVV, match_vd_neq_vm, 0},
|
|
|
+ {"vnmsub.vx", 0, INSN_CLASS_V, "Vd,s,VtVm", MATCH_VNMSUBVX, MASK_VNMSUBVX, match_vd_neq_vm, 0},
|
|
|
+
|
|
|
+-{"vwmaccu.vv", 0, INSN_CLASS_V, "Vd,Vs,VtVm", MATCH_VWMACCUVV, MASK_VWMACCUVV, match_widen_vd_neq_vs1_neq_vs2_neq_vm, 0},
|
|
|
+-{"vwmaccu.vx", 0, INSN_CLASS_V, "Vd,s,VtVm", MATCH_VWMACCUVX, MASK_VWMACCUVX, match_widen_vd_neq_vs2_neq_vm, 0},
|
|
|
+-{"vwmacc.vv", 0, INSN_CLASS_V, "Vd,Vs,VtVm", MATCH_VWMACCVV, MASK_VWMACCVV, match_widen_vd_neq_vs1_neq_vs2_neq_vm, 0},
|
|
|
+-{"vwmacc.vx", 0, INSN_CLASS_V, "Vd,s,VtVm", MATCH_VWMACCVX, MASK_VWMACCVX, match_widen_vd_neq_vs2_neq_vm, 0},
|
|
|
+-{"vwmaccsu.vv", 0, INSN_CLASS_V, "Vd,Vs,VtVm", MATCH_VWMACCSUVV, MASK_VWMACCSUVV, match_widen_vd_neq_vs1_neq_vs2_neq_vm, 0},
|
|
|
+-{"vwmaccsu.vx", 0, INSN_CLASS_V, "Vd,s,VtVm", MATCH_VWMACCSUVX, MASK_VWMACCSUVX, match_widen_vd_neq_vs2_neq_vm, 0},
|
|
|
+-{"vwmaccus.vx", 0, INSN_CLASS_V, "Vd,s,VtVm", MATCH_VWMACCUSVX, MASK_VWMACCUSVX, match_widen_vd_neq_vs2_neq_vm, 0},
|
|
|
+-
|
|
|
+ {"vdivu.vv", 0, INSN_CLASS_V, "Vd,Vt,VsVm", MATCH_VDIVUVV, MASK_VDIVUVV, match_vd_neq_vm, 0 },
|
|
|
+ {"vdivu.vx", 0, INSN_CLASS_V, "Vd,Vt,sVm", MATCH_VDIVUVX, MASK_VDIVUVX, match_vd_neq_vm, 0 },
|
|
|
+ {"vdiv.vv", 0, INSN_CLASS_V, "Vd,Vt,VsVm", MATCH_VDIVVV, MASK_VDIVVV, match_vd_neq_vm, 0 },
|
|
|
+@@ -1881,67 +1467,18 @@ const struct riscv_opcode riscv_opcodes[] =
|
|
|
+ {"vmv.v.x", 0, INSN_CLASS_V, "Vd,s", MATCH_VMVVX, MASK_VMVVX, match_opcode, 0 },
|
|
|
+ {"vmv.v.i", 0, INSN_CLASS_V, "Vd,Vi", MATCH_VMVVI, MASK_VMVVI, match_opcode, 0 },
|
|
|
+
|
|
|
+-{"vsaddu.vv", 0, INSN_CLASS_V, "Vd,Vt,VsVm", MATCH_VSADDUVV, MASK_VSADDUVV, match_vd_neq_vm, 0 },
|
|
|
+-{"vsaddu.vx", 0, INSN_CLASS_V, "Vd,Vt,sVm", MATCH_VSADDUVX, MASK_VSADDUVX, match_vd_neq_vm, 0 },
|
|
|
+-{"vsaddu.vi", 0, INSN_CLASS_V, "Vd,Vt,ViVm", MATCH_VSADDUVI, MASK_VSADDUVI, match_vd_neq_vm, 0 },
|
|
|
+-{"vsadd.vv", 0, INSN_CLASS_V, "Vd,Vt,VsVm", MATCH_VSADDVV, MASK_VSADDVV, match_vd_neq_vm, 0 },
|
|
|
+-{"vsadd.vx", 0, INSN_CLASS_V, "Vd,Vt,sVm", MATCH_VSADDVX, MASK_VSADDVX, match_vd_neq_vm, 0 },
|
|
|
+-{"vsadd.vi", 0, INSN_CLASS_V, "Vd,Vt,ViVm", MATCH_VSADDVI, MASK_VSADDVI, match_vd_neq_vm, 0 },
|
|
|
+-{"vssubu.vv", 0, INSN_CLASS_V, "Vd,Vt,VsVm", MATCH_VSSUBUVV, MASK_VSSUBUVV, match_vd_neq_vm, 0 },
|
|
|
+-{"vssubu.vx", 0, INSN_CLASS_V, "Vd,Vt,sVm", MATCH_VSSUBUVX, MASK_VSSUBUVX, match_vd_neq_vm, 0 },
|
|
|
+-{"vssub.vv", 0, INSN_CLASS_V, "Vd,Vt,VsVm", MATCH_VSSUBVV, MASK_VSSUBVV, match_vd_neq_vm, 0 },
|
|
|
+-{"vssub.vx", 0, INSN_CLASS_V, "Vd,Vt,sVm", MATCH_VSSUBVX, MASK_VSSUBVX, match_vd_neq_vm, 0 },
|
|
|
+-
|
|
|
+-{"vaaddu.vv", 0, INSN_CLASS_V, "Vd,Vt,VsVm", MATCH_VAADDUVV, MASK_VAADDUVV, match_vd_neq_vm, 0 },
|
|
|
+-{"vaaddu.vx", 0, INSN_CLASS_V, "Vd,Vt,sVm", MATCH_VAADDUVX, MASK_VAADDUVX, match_vd_neq_vm, 0 },
|
|
|
+-{"vaadd.vv", 0, INSN_CLASS_V, "Vd,Vt,VsVm", MATCH_VAADDVV, MASK_VAADDVV, match_vd_neq_vm, 0 },
|
|
|
+-{"vaadd.vx", 0, INSN_CLASS_V, "Vd,Vt,sVm", MATCH_VAADDVX, MASK_VAADDVX, match_vd_neq_vm, 0 },
|
|
|
+-{"vasubu.vv", 0, INSN_CLASS_V, "Vd,Vt,VsVm", MATCH_VASUBUVV, MASK_VASUBUVV, match_vd_neq_vm, 0 },
|
|
|
+-{"vasubu.vx", 0, INSN_CLASS_V, "Vd,Vt,sVm", MATCH_VASUBUVX, MASK_VASUBUVX, match_vd_neq_vm, 0 },
|
|
|
+-{"vasub.vv", 0, INSN_CLASS_V, "Vd,Vt,VsVm", MATCH_VASUBVV, MASK_VASUBVV, match_vd_neq_vm, 0 },
|
|
|
+-{"vasub.vx", 0, INSN_CLASS_V, "Vd,Vt,sVm", MATCH_VASUBVX, MASK_VASUBVX, match_vd_neq_vm, 0 },
|
|
|
+-
|
|
|
+-{"vsmul.vv", 0, INSN_CLASS_V, "Vd,Vt,VsVm", MATCH_VSMULVV, MASK_VSMULVV, match_vd_neq_vm, 0 },
|
|
|
+-{"vsmul.vx", 0, INSN_CLASS_V, "Vd,Vt,sVm", MATCH_VSMULVX, MASK_VSMULVX, match_vd_neq_vm, 0 },
|
|
|
+-
|
|
|
+-{"vssrl.vv", 0, INSN_CLASS_V, "Vd,Vt,VsVm", MATCH_VSSRLVV, MASK_VSSRLVV, match_vd_neq_vm, 0 },
|
|
|
+-{"vssrl.vx", 0, INSN_CLASS_V, "Vd,Vt,sVm", MATCH_VSSRLVX, MASK_VSSRLVX, match_vd_neq_vm, 0 },
|
|
|
+-{"vssrl.vi", 0, INSN_CLASS_V, "Vd,Vt,VjVm", MATCH_VSSRLVI, MASK_VSSRLVI, match_vd_neq_vm, 0 },
|
|
|
+-{"vssra.vv", 0, INSN_CLASS_V, "Vd,Vt,VsVm", MATCH_VSSRAVV, MASK_VSSRAVV, match_vd_neq_vm, 0 },
|
|
|
+-{"vssra.vx", 0, INSN_CLASS_V, "Vd,Vt,sVm", MATCH_VSSRAVX, MASK_VSSRAVX, match_vd_neq_vm, 0 },
|
|
|
+-{"vssra.vi", 0, INSN_CLASS_V, "Vd,Vt,VjVm", MATCH_VSSRAVI, MASK_VSSRAVI, match_vd_neq_vm, 0 },
|
|
|
+-
|
|
|
+-{"vnclipu.wv", 0, INSN_CLASS_V, "Vd,Vt,VsVm", MATCH_VNCLIPUWV, MASK_VNCLIPUWV, match_narrow_vd_neq_vs2_neq_vm, 0 },
|
|
|
+-{"vnclipu.wx", 0, INSN_CLASS_V, "Vd,Vt,sVm", MATCH_VNCLIPUWX, MASK_VNCLIPUWX, match_narrow_vd_neq_vs2_neq_vm, 0 },
|
|
|
+-{"vnclipu.wi", 0, INSN_CLASS_V, "Vd,Vt,VjVm", MATCH_VNCLIPUWI, MASK_VNCLIPUWI, match_narrow_vd_neq_vs2_neq_vm, 0 },
|
|
|
+-{"vnclip.wv", 0, INSN_CLASS_V, "Vd,Vt,VsVm", MATCH_VNCLIPWV, MASK_VNCLIPWV, match_narrow_vd_neq_vs2_neq_vm, 0 },
|
|
|
+-{"vnclip.wx", 0, INSN_CLASS_V, "Vd,Vt,sVm", MATCH_VNCLIPWX, MASK_VNCLIPWX, match_narrow_vd_neq_vs2_neq_vm, 0 },
|
|
|
+-{"vnclip.wi", 0, INSN_CLASS_V, "Vd,Vt,VjVm", MATCH_VNCLIPWI, MASK_VNCLIPWI, match_narrow_vd_neq_vs2_neq_vm, 0 },
|
|
|
+-
|
|
|
+ {"vfadd.vv", 0, INSN_CLASS_V_AND_F, "Vd,Vt,VsVm", MATCH_VFADDVV, MASK_VFADDVV, match_vd_neq_vm, 0},
|
|
|
+ {"vfadd.vf", 0, INSN_CLASS_V_AND_F, "Vd,Vt,SVm", MATCH_VFADDVF, MASK_VFADDVF, match_vd_neq_vm, 0},
|
|
|
+ {"vfsub.vv", 0, INSN_CLASS_V_AND_F, "Vd,Vt,VsVm", MATCH_VFSUBVV, MASK_VFSUBVV, match_vd_neq_vm, 0},
|
|
|
+ {"vfsub.vf", 0, INSN_CLASS_V_AND_F, "Vd,Vt,SVm", MATCH_VFSUBVF, MASK_VFSUBVF, match_vd_neq_vm, 0},
|
|
|
+ {"vfrsub.vf", 0, INSN_CLASS_V_AND_F, "Vd,Vt,SVm", MATCH_VFRSUBVF, MASK_VFRSUBVF, match_vd_neq_vm, 0},
|
|
|
+
|
|
|
+-{"vfwadd.vv", 0, INSN_CLASS_V_AND_F, "Vd,Vt,VsVm", MATCH_VFWADDVV, MASK_VFWADDVV, match_widen_vd_neq_vs1_neq_vs2_neq_vm, 0},
|
|
|
+-{"vfwadd.vf", 0, INSN_CLASS_V_AND_F, "Vd,Vt,SVm", MATCH_VFWADDVF, MASK_VFWADDVF, match_widen_vd_neq_vs2_neq_vm, 0},
|
|
|
+-{"vfwsub.vv", 0, INSN_CLASS_V_AND_F, "Vd,Vt,VsVm", MATCH_VFWSUBVV, MASK_VFWSUBVV, match_widen_vd_neq_vs1_neq_vs2_neq_vm, 0},
|
|
|
+-{"vfwsub.vf", 0, INSN_CLASS_V_AND_F, "Vd,Vt,SVm", MATCH_VFWSUBVF, MASK_VFWSUBVF, match_widen_vd_neq_vs2_neq_vm, 0},
|
|
|
+-{"vfwadd.wv", 0, INSN_CLASS_V_AND_F, "Vd,Vt,VsVm", MATCH_VFWADDWV, MASK_VFWADDWV, match_widen_vd_neq_vs1_neq_vm, 0},
|
|
|
+-{"vfwadd.wf", 0, INSN_CLASS_V_AND_F, "Vd,Vt,SVm", MATCH_VFWADDWF, MASK_VFWADDWF, match_widen_vd_neq_vm, 0},
|
|
|
+-{"vfwsub.wv", 0, INSN_CLASS_V_AND_F, "Vd,Vt,VsVm", MATCH_VFWSUBWV, MASK_VFWSUBWV, match_widen_vd_neq_vs1_neq_vm, 0},
|
|
|
+-{"vfwsub.wf", 0, INSN_CLASS_V_AND_F, "Vd,Vt,SVm", MATCH_VFWSUBWF, MASK_VFWSUBWF, match_widen_vd_neq_vm, 0},
|
|
|
+-
|
|
|
+ {"vfmul.vv", 0, INSN_CLASS_V_AND_F, "Vd,Vt,VsVm", MATCH_VFMULVV, MASK_VFMULVV, match_vd_neq_vm, 0},
|
|
|
+ {"vfmul.vf", 0, INSN_CLASS_V_AND_F, "Vd,Vt,SVm", MATCH_VFMULVF, MASK_VFMULVF, match_vd_neq_vm, 0},
|
|
|
+ {"vfdiv.vv", 0, INSN_CLASS_V_AND_F, "Vd,Vt,VsVm", MATCH_VFDIVVV, MASK_VFDIVVV, match_vd_neq_vm, 0},
|
|
|
+ {"vfdiv.vf", 0, INSN_CLASS_V_AND_F, "Vd,Vt,SVm", MATCH_VFDIVVF, MASK_VFDIVVF, match_vd_neq_vm, 0},
|
|
|
+ {"vfrdiv.vf", 0, INSN_CLASS_V_AND_F, "Vd,Vt,SVm", MATCH_VFRDIVVF, MASK_VFRDIVVF, match_vd_neq_vm, 0},
|
|
|
+
|
|
|
+-{"vfwmul.vv", 0, INSN_CLASS_V_AND_F, "Vd,Vt,VsVm", MATCH_VFWMULVV, MASK_VFWMULVV, match_widen_vd_neq_vs1_neq_vs2_neq_vm, 0},
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|
+-{"vfwmul.vf", 0, INSN_CLASS_V_AND_F, "Vd,Vt,SVm", MATCH_VFWMULVF, MASK_VFWMULVF, match_widen_vd_neq_vs2_neq_vm, 0},
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|
|
+-
|
|
|
+ {"vfmadd.vv", 0, INSN_CLASS_V_AND_F, "Vd,Vs,VtVm", MATCH_VFMADDVV, MASK_VFMADDVV, match_vd_neq_vm, 0},
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|
+ {"vfmadd.vf", 0, INSN_CLASS_V_AND_F, "Vd,S,VtVm", MATCH_VFMADDVF, MASK_VFMADDVF, match_vd_neq_vm, 0},
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|
|
+ {"vfnmadd.vv", 0, INSN_CLASS_V_AND_F, "Vd,Vs,VtVm", MATCH_VFNMADDVV, MASK_VFNMADDVV, match_vd_neq_vm, 0},
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|
|
+@@ -1959,22 +1496,6 @@ const struct riscv_opcode riscv_opcodes[] =
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|
+ {"vfnmsac.vv", 0, INSN_CLASS_V_AND_F, "Vd,Vs,VtVm", MATCH_VFNMSACVV, MASK_VFNMSACVV, match_vd_neq_vm, 0},
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|
+ {"vfnmsac.vf", 0, INSN_CLASS_V_AND_F, "Vd,S,VtVm", MATCH_VFNMSACVF, MASK_VFNMSACVF, match_vd_neq_vm, 0},
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+
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|
+-{"vfwmacc.vv", 0, INSN_CLASS_V_AND_F, "Vd,Vs,VtVm", MATCH_VFWMACCVV, MASK_VFWMACCVV, match_widen_vd_neq_vs1_neq_vs2_neq_vm, 0},
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|
+-{"vfwmacc.vf", 0, INSN_CLASS_V_AND_F, "Vd,S,VtVm", MATCH_VFWMACCVF, MASK_VFWMACCVF, match_widen_vd_neq_vs2_neq_vm, 0},
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+-{"vfwnmacc.vv", 0, INSN_CLASS_V_AND_F, "Vd,Vs,VtVm", MATCH_VFWNMACCVV, MASK_VFWNMACCVV, match_widen_vd_neq_vs1_neq_vs2_neq_vm, 0},
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+-{"vfwnmacc.vf", 0, INSN_CLASS_V_AND_F, "Vd,S,VtVm", MATCH_VFWNMACCVF, MASK_VFWNMACCVF, match_widen_vd_neq_vs2_neq_vm, 0},
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+-{"vfwmsac.vv", 0, INSN_CLASS_V_AND_F, "Vd,Vs,VtVm", MATCH_VFWMSACVV, MASK_VFWMSACVV, match_widen_vd_neq_vs1_neq_vs2_neq_vm, 0},
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|
+-{"vfwmsac.vf", 0, INSN_CLASS_V_AND_F, "Vd,S,VtVm", MATCH_VFWMSACVF, MASK_VFWMSACVF, match_widen_vd_neq_vs2_neq_vm, 0},
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|
+-{"vfwnmsac.vv", 0, INSN_CLASS_V_AND_F, "Vd,Vs,VtVm", MATCH_VFWNMSACVV, MASK_VFWNMSACVV, match_widen_vd_neq_vs1_neq_vs2_neq_vm, 0},
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|
+-{"vfwnmsac.vf", 0, INSN_CLASS_V_AND_F, "Vd,S,VtVm", MATCH_VFWNMSACVF, MASK_VFWNMSACVF, match_widen_vd_neq_vs2_neq_vm, 0},
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+-
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|
|
+-{"vfsqrt.v", 0, INSN_CLASS_V_AND_F, "Vd,VtVm", MATCH_VFSQRTV, MASK_VFSQRTV, match_vd_neq_vm, 0},
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|
+-{"vfrsqrt7.v", 0, INSN_CLASS_V_AND_F, "Vd,VtVm", MATCH_VFRSQRT7V, MASK_VFRSQRT7V, match_vd_neq_vm, 0},
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|
+-{"vfrsqrte7.v",0, INSN_CLASS_V_AND_F, "Vd,VtVm", MATCH_VFRSQRT7V, MASK_VFRSQRT7V, match_vd_neq_vm, 0},
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|
|
+-{"vfrec7.v", 0, INSN_CLASS_V_AND_F, "Vd,VtVm", MATCH_VFREC7V, MASK_VFREC7V, match_vd_neq_vm, 0},
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|
+-{"vfrece7.v", 0, INSN_CLASS_V_AND_F, "Vd,VtVm", MATCH_VFREC7V, MASK_VFREC7V, match_vd_neq_vm, 0},
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|
|
+-{"vfclass.v", 0, INSN_CLASS_V_AND_F, "Vd,VtVm", MATCH_VFCLASSV, MASK_VFCLASSV, match_vd_neq_vm, 0},
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|
|
+-
|
|
|
+ {"vfmin.vv", 0, INSN_CLASS_V_AND_F, "Vd,Vt,VsVm", MATCH_VFMINVV, MASK_VFMINVV, match_vd_neq_vm, 0},
|
|
|
+ {"vfmin.vf", 0, INSN_CLASS_V_AND_F, "Vd,Vt,SVm", MATCH_VFMINVF, MASK_VFMINVF, match_vd_neq_vm, 0},
|
|
|
+ {"vfmax.vv", 0, INSN_CLASS_V_AND_F, "Vd,Vt,VsVm", MATCH_VFMAXVV, MASK_VFMAXVV, match_vd_neq_vm, 0},
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|
|
+@@ -2008,50 +1529,6 @@ const struct riscv_opcode riscv_opcodes[] =
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|
|
+ {"vfmerge.vfm",0, INSN_CLASS_V_AND_F, "Vd,Vt,S,V0", MATCH_VFMERGEVFM, MASK_VFMERGEVFM, match_opcode, 0},
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|
|
+ {"vfmv.v.f", 0, INSN_CLASS_V_AND_F, "Vd,S", MATCH_VFMVVF, MASK_VFMVVF, match_opcode, 0 },
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|
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+
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|
|
+-{"vfcvt.xu.f.v", 0, INSN_CLASS_V_AND_F, "Vd,VtVm", MATCH_VFCVTXUFV, MASK_VFCVTXUFV, match_vd_neq_vm, 0},
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|
|
+-{"vfcvt.x.f.v", 0, INSN_CLASS_V_AND_F, "Vd,VtVm", MATCH_VFCVTXFV, MASK_VFCVTXFV, match_vd_neq_vm, 0},
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|
|
+-{"vfcvt.rtz.xu.f.v", 0, INSN_CLASS_V_AND_F, "Vd,VtVm", MATCH_VFCVTRTZXUFV, MASK_VFCVTRTZXUFV, match_vd_neq_vm, 0},
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|
|
+-{"vfcvt.rtz.x.f.v", 0, INSN_CLASS_V_AND_F, "Vd,VtVm", MATCH_VFCVTRTZXFV, MASK_VFCVTRTZXFV, match_vd_neq_vm, 0},
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|
|
+-{"vfcvt.f.xu.v", 0, INSN_CLASS_V_AND_F, "Vd,VtVm", MATCH_VFCVTFXUV, MASK_VFCVTFXUV, match_vd_neq_vm, 0},
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|
+-{"vfcvt.f.x.v", 0, INSN_CLASS_V_AND_F, "Vd,VtVm", MATCH_VFCVTFXV, MASK_VFCVTFXV, match_vd_neq_vm, 0},
|
|
|
+-
|
|
|
+-{"vfwcvt.xu.f.v", 0, INSN_CLASS_V_AND_F, "Vd,VtVm", MATCH_VFWCVTXUFV, MASK_VFWCVTXUFV, match_widen_vd_neq_vs2_neq_vm, 0},
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|
|
+-{"vfwcvt.x.f.v", 0, INSN_CLASS_V_AND_F, "Vd,VtVm", MATCH_VFWCVTXFV, MASK_VFWCVTXFV, match_widen_vd_neq_vs2_neq_vm, 0},
|
|
|
+-{"vfwcvt.rtz.xu.f.v", 0, INSN_CLASS_V_AND_F, "Vd,VtVm", MATCH_VFWCVTRTZXUFV, MASK_VFWCVTRTZXUFV, match_widen_vd_neq_vs2_neq_vm, 0},
|
|
|
+-{"vfwcvt.rtz.x.f.v", 0, INSN_CLASS_V_AND_F, "Vd,VtVm", MATCH_VFWCVTRTZXFV, MASK_VFWCVTRTZXFV, match_widen_vd_neq_vs2_neq_vm, 0},
|
|
|
+-{"vfwcvt.f.xu.v", 0, INSN_CLASS_V_AND_F, "Vd,VtVm", MATCH_VFWCVTFXUV, MASK_VFWCVTFXUV, match_widen_vd_neq_vs2_neq_vm, 0},
|
|
|
+-{"vfwcvt.f.x.v", 0, INSN_CLASS_V_AND_F, "Vd,VtVm", MATCH_VFWCVTFXV, MASK_VFWCVTFXV, match_widen_vd_neq_vs2_neq_vm, 0},
|
|
|
+-{"vfwcvt.f.f.v", 0, INSN_CLASS_V_AND_F, "Vd,VtVm", MATCH_VFWCVTFFV, MASK_VFWCVTFFV, match_widen_vd_neq_vs2_neq_vm, 0},
|
|
|
+-
|
|
|
+-{"vfncvt.xu.f.w", 0, INSN_CLASS_V_AND_F, "Vd,VtVm", MATCH_VFNCVTXUFW, MASK_VFNCVTXUFW, match_narrow_vd_neq_vs2_neq_vm, 0},
|
|
|
+-{"vfncvt.x.f.w", 0, INSN_CLASS_V_AND_F, "Vd,VtVm", MATCH_VFNCVTXFW, MASK_VFNCVTXFW, match_narrow_vd_neq_vs2_neq_vm, 0},
|
|
|
+-{"vfncvt.rtz.xu.f.w", 0, INSN_CLASS_V_AND_F, "Vd,VtVm", MATCH_VFNCVTRTZXUFW, MASK_VFNCVTRTZXUFW, match_narrow_vd_neq_vs2_neq_vm, 0},
|
|
|
+-{"vfncvt.rtz.x.f.w", 0, INSN_CLASS_V_AND_F, "Vd,VtVm", MATCH_VFNCVTRTZXFW, MASK_VFNCVTRTZXFW, match_narrow_vd_neq_vs2_neq_vm, 0},
|
|
|
+-{"vfncvt.f.xu.w", 0, INSN_CLASS_V_AND_F, "Vd,VtVm", MATCH_VFNCVTFXUW, MASK_VFNCVTFXUW, match_narrow_vd_neq_vs2_neq_vm, 0},
|
|
|
+-{"vfncvt.f.x.w", 0, INSN_CLASS_V_AND_F, "Vd,VtVm", MATCH_VFNCVTFXW, MASK_VFNCVTFXW, match_narrow_vd_neq_vs2_neq_vm, 0},
|
|
|
+-{"vfncvt.f.f.w", 0, INSN_CLASS_V_AND_F, "Vd,VtVm", MATCH_VFNCVTFFW, MASK_VFNCVTFFW, match_narrow_vd_neq_vs2_neq_vm, 0},
|
|
|
+-{"vfncvt.rod.f.f.w", 0, INSN_CLASS_V_AND_F, "Vd,VtVm", MATCH_VFNCVTRODFFW, MASK_VFNCVTRODFFW, match_narrow_vd_neq_vs2_neq_vm, 0},
|
|
|
+-
|
|
|
+-{"vredsum.vs", 0, INSN_CLASS_V, "Vd,Vt,VsVm", MATCH_VREDSUMVS, MASK_VREDSUMVS, match_opcode, 0},
|
|
|
+-{"vredmaxu.vs",0, INSN_CLASS_V, "Vd,Vt,VsVm", MATCH_VREDMAXUVS, MASK_VREDMAXUVS, match_opcode, 0},
|
|
|
+-{"vredmax.vs", 0, INSN_CLASS_V, "Vd,Vt,VsVm", MATCH_VREDMAXVS, MASK_VREDMAXVS, match_opcode, 0},
|
|
|
+-{"vredminu.vs",0, INSN_CLASS_V, "Vd,Vt,VsVm", MATCH_VREDMINUVS, MASK_VREDMINUVS, match_opcode, 0},
|
|
|
+-{"vredmin.vs", 0, INSN_CLASS_V, "Vd,Vt,VsVm", MATCH_VREDMINVS, MASK_VREDMINVS, match_opcode, 0},
|
|
|
+-{"vredand.vs", 0, INSN_CLASS_V, "Vd,Vt,VsVm", MATCH_VREDANDVS, MASK_VREDANDVS, match_opcode, 0},
|
|
|
+-{"vredor.vs", 0, INSN_CLASS_V, "Vd,Vt,VsVm", MATCH_VREDORVS, MASK_VREDORVS, match_opcode, 0},
|
|
|
+-{"vredxor.vs", 0, INSN_CLASS_V, "Vd,Vt,VsVm", MATCH_VREDXORVS, MASK_VREDXORVS, match_opcode, 0},
|
|
|
+-
|
|
|
+-{"vwredsumu.vs",0, INSN_CLASS_V, "Vd,Vt,VsVm", MATCH_VWREDSUMUVS, MASK_VWREDSUMUVS, match_opcode, 0},
|
|
|
+-{"vwredsum.vs",0, INSN_CLASS_V, "Vd,Vt,VsVm", MATCH_VWREDSUMVS, MASK_VWREDSUMVS, match_opcode, 0},
|
|
|
+-
|
|
|
+-{"vfredosum.vs",0, INSN_CLASS_V_AND_F, "Vd,Vt,VsVm", MATCH_VFREDOSUMVS, MASK_VFREDOSUMVS, match_opcode, 0},
|
|
|
+-{"vfredsum.vs", 0, INSN_CLASS_V_AND_F, "Vd,Vt,VsVm", MATCH_VFREDSUMVS, MASK_VFREDSUMVS, match_opcode, 0},
|
|
|
+-{"vfredmax.vs", 0, INSN_CLASS_V_AND_F, "Vd,Vt,VsVm", MATCH_VFREDMAXVS, MASK_VFREDMAXVS, match_opcode, 0},
|
|
|
+-{"vfredmin.vs", 0, INSN_CLASS_V_AND_F, "Vd,Vt,VsVm", MATCH_VFREDMINVS, MASK_VFREDMINVS, match_opcode, 0},
|
|
|
+-
|
|
|
+-{"vfwredosum.vs",0, INSN_CLASS_V_AND_F, "Vd,Vt,VsVm", MATCH_VFWREDOSUMVS, MASK_VFWREDOSUMVS, match_opcode, 0},
|
|
|
+-{"vfwredsum.vs", 0, INSN_CLASS_V_AND_F, "Vd,Vt,VsVm", MATCH_VFWREDSUMVS, MASK_VFWREDSUMVS, match_opcode, 0},
|
|
|
+-
|
|
|
+ {"vmmv.m", 0, INSN_CLASS_V, "Vd,Vu", MATCH_VMANDMM, MASK_VMANDMM, match_vs1_eq_vs2, INSN_ALIAS},
|
|
|
+ {"vmcpy.m", 0, INSN_CLASS_V, "Vd,Vu", MATCH_VMANDMM, MASK_VMANDMM, match_vs1_eq_vs2, INSN_ALIAS},
|
|
|
+ {"vmclr.m", 0, INSN_CLASS_V, "Vv", MATCH_VMXORMM, MASK_VMXORMM, match_vd_eq_vs1_eq_vs2, INSN_ALIAS},
|
|
|
+@@ -2069,11 +1546,6 @@ const struct riscv_opcode riscv_opcodes[] =
|
|
|
+
|
|
|
+ {"vpopc.m", 0, INSN_CLASS_V, "d,VtVm", MATCH_VPOPCM, MASK_VPOPCM, match_opcode, 0},
|
|
|
+ {"vfirst.m", 0, INSN_CLASS_V, "d,VtVm", MATCH_VFIRSTM, MASK_VFIRSTM, match_opcode, 0},
|
|
|
+-{"vmsbf.m", 0, INSN_CLASS_V, "Vd,VtVm", MATCH_VMSBFM, MASK_VMSBFM, match_vd_neq_vs2_neq_vm, 0},
|
|
|
+-{"vmsif.m", 0, INSN_CLASS_V, "Vd,VtVm", MATCH_VMSIFM, MASK_VMSIFM, match_vd_neq_vs2_neq_vm, 0},
|
|
|
+-{"vmsof.m", 0, INSN_CLASS_V, "Vd,VtVm", MATCH_VMSOFM, MASK_VMSOFM, match_vd_neq_vs2_neq_vm, 0},
|
|
|
+-{"viota.m", 0, INSN_CLASS_V, "Vd,VtVm", MATCH_VIOTAM, MASK_VIOTAM, match_vd_neq_vs2_neq_vm, 0},
|
|
|
+-{"vid.v", 0, INSN_CLASS_V, "VdVm", MATCH_VIDV, MASK_VIDV, match_vd_neq_vm, 0},
|
|
|
+
|
|
|
+ {"vmv.x.s", 0, INSN_CLASS_V, "d,Vt", MATCH_VMVXS, MASK_VMVXS, match_opcode, 0},
|
|
|
+ {"vmv.s.x", 0, INSN_CLASS_V, "Vd,s", MATCH_VMVSX, MASK_VMVSX, match_opcode, 0},
|
|
|
+@@ -2094,15 +1566,10 @@ const struct riscv_opcode riscv_opcodes[] =
|
|
|
+ {"vrgather.vv", 0, INSN_CLASS_V, "Vd,Vt,VsVm", MATCH_VRGATHERVV, MASK_VRGATHERVV, match_vd_neq_vs1_neq_vs2_neq_vm, 0},
|
|
|
+ {"vrgather.vx", 0, INSN_CLASS_V, "Vd,Vt,sVm", MATCH_VRGATHERVX, MASK_VRGATHERVX, match_vd_neq_vs2_neq_vm, 0},
|
|
|
+ {"vrgather.vi", 0, INSN_CLASS_V, "Vd,Vt,VjVm", MATCH_VRGATHERVI, MASK_VRGATHERVI, match_vd_neq_vs2_neq_vm, 0},
|
|
|
+-{"vrgatherei16.vv",0, INSN_CLASS_V, "Vd,Vt,VsVm", MATCH_VRGATHEREI16VV, MASK_VRGATHEREI16VV, match_vd_neq_vs1_neq_vs2_neq_vm, 0},
|
|
|
+
|
|
|
+ {"vcompress.vm",0, INSN_CLASS_V, "Vd,Vt,Vs", MATCH_VCOMPRESSVM, MASK_VCOMPRESSVM, match_vd_neq_vs1_neq_vs2, 0},
|
|
|
+-
|
|
|
+-{"vmv1r.v", 0, INSN_CLASS_V, "Vd,Vt", MATCH_VMV1RV, MASK_VMV1RV, match_vmv_nf_rv, 0},
|
|
|
+-{"vmv2r.v", 0, INSN_CLASS_V, "Vd,Vt", MATCH_VMV2RV, MASK_VMV2RV, match_vmv_nf_rv, 0},
|
|
|
+-{"vmv4r.v", 0, INSN_CLASS_V, "Vd,Vt", MATCH_VMV4RV, MASK_VMV4RV, match_vmv_nf_rv, 0},
|
|
|
+-{"vmv8r.v", 0, INSN_CLASS_V, "Vd,Vt", MATCH_VMV8RV, MASK_VMV8RV, match_vmv_nf_rv, 0},
|
|
|
+ /* END RVV */
|
|
|
++
|
|
|
+ /* Terminate the list. */
|
|
|
+ {0, 0, INSN_CLASS_NONE, 0, 0, 0, 0, 0}
|
|
|
+ };
|
|
|
+--
|
|
|
+2.33.0
|
|
|
+
|