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dubhe: Update GCC and Binutils to B extension v0.94

Added patch files to update GCC and Binutils into B extension 0.94.

Signed-off-by: Jun Yuan Tan <junyuan.tan@starfivetech.com>
Jun Yuan Tan 2 년 전
부모
커밋
75116d3654
39개의 변경된 파일13664개의 추가작업 그리고 48개의 파일을 삭제
  1. 32 5
      recipes-devtools/binutils/binutils-cross-canadian_2.36.bbappend
  2. 32 5
      recipes-devtools/binutils/binutils-cross_2.36.bbappend
  3. 32 5
      recipes-devtools/binutils/binutils-crosssdk_2.36.bbappend
  4. 25 0
      recipes-devtools/binutils/binutils/0001-resolve-bug-1-unsupported-zvmo-extension.patch
  5. 1001 0
      recipes-devtools/binutils/binutils/0002-Add-support-for-B-extension.patch
  6. 4252 0
      recipes-devtools/binutils/binutils/0003-merge-rvv1.0-branch.patch
  7. 523 0
      recipes-devtools/binutils/binutils/0004-add-missed-sysroff-file.patch
  8. 5703 0
      recipes-devtools/binutils/binutils/0005-support-Dubhe-V-extension.patch
  9. 281 0
      recipes-devtools/binutils/binutils/0006-Add-pseudo-instructions-for-B-extension.patch
  10. 81 0
      recipes-devtools/binutils/binutils/0007-Rename-bdep-to-bdecompress.patch
  11. 76 0
      recipes-devtools/binutils/binutils/0008-RISCV-Add-support-for-bcompress.patch
  12. 25 0
      recipes-devtools/binutils/binutils/0009-RISCV-Coding-bug-Fix-for-FSRW.patch
  13. 25 0
      recipes-devtools/binutils/binutils/0010-RISCV-Coding-bug-Fix-for-FSRIW.patch
  14. 274 0
      recipes-devtools/binutils/binutils/0011-RISCV-Fix-coding-for-un-zip-2-4-8-16-n-b-h-w.patch
  15. 45 0
      recipes-devtools/binutils/binutils/0012-update-bitmap-version-number-from-0.93-to-0.94.patch
  16. 93 0
      recipes-devtools/binutils/binutils/0013-Fix-gas-test-cases.patch
  17. 36 0
      recipes-devtools/binutils/binutils/0014-resolve-crash-issue-when-objdump-encounter-unrecogni.patch
  18. 131 0
      recipes-devtools/binutils/binutils/0015-Remove-MASK_SHAMT2.patch
  19. 50 0
      recipes-devtools/binutils/binutils/0016-Fix-internal-error-undefined-modifier-r.patch
  20. 25 0
      recipes-devtools/binutils/binutils/0017-Fix-coding-for-Bcompressw.patch
  21. 25 0
      recipes-devtools/binutils/binutils/0018-Fix-zip2.b-testcase.patch
  22. 25 0
      recipes-devtools/binutils/binutils/0019-Fix-orc2.n-testcase.patch
  23. 25 0
      recipes-devtools/binutils/binutils/0020-Fix-rev2.n-test-case.patch
  24. 34 0
      recipes-devtools/binutils/binutils/0021-Fix-testcase-for-zip2.b-and-rev2.n.patch
  25. 27 0
      recipes-devtools/binutils/binutils/0022-Fix-r-operands-type-from-fpr-to-gpr.patch
  26. 99 0
      recipes-devtools/binutils/binutils/0023-support-vid-vmv1r-vl1r-vs1r-instruction.patch
  27. 214 0
      recipes-devtools/binutils/binutils/0024-add-vid-instruction-support.patch
  28. 34 0
      recipes-devtools/binutils/binutils/0025-Fix-all-issues-in-b-ext-64.d.patch
  29. 34 0
      recipes-devtools/binutils/binutils/0026-Apply-same-fix-on-b-ext.d.patch
  30. 47 0
      recipes-devtools/binutils/binutils/0027-remove-redundant-symbol.patch
  31. 87 0
      recipes-devtools/binutils/binutils/0028-solved-vector-insns-test-failed-n.patch
  32. 32 5
      recipes-devtools/binutils/binutils_2.36.bbappend
  33. 0 23
      recipes-devtools/gcc/files/0001-Fix-compilation-issue-when-building-multilib.patch
  34. 185 0
      recipes-devtools/gcc/files/0060-Initial-support-for-0.94-Bitmap.patch
  35. 47 0
      recipes-devtools/gcc/files/0061-Remove-unsupported-bext.w-in-gcc.patch
  36. 1 1
      recipes-devtools/gcc/gcc-cross-canadian_10.2.bbappend
  37. 1 1
      recipes-devtools/gcc/gcc-cross_10.2.bbappend
  38. 1 1
      recipes-devtools/gcc/gcc-crosssdk_10.2.bbappend
  39. 4 2
      recipes-devtools/gcc/gcc-source_10.2.bbappend

+ 32 - 5
recipes-devtools/binutils/binutils-cross-canadian_2.36.bbappend

@@ -1,11 +1,38 @@
-SRCBRANCH = "sifive-rvv-1.0.x-zfh-rvb"
+FILESEXTRAPATHS_prepend := "${THISDIR}/binutils:"
+SRCBRANCH = "riscv-binutils-2.36.1"
 
-SRCREV = "75d2236ce26a3048f52bbd5186602e27bd635e2b"
+SRCREV = "f35674005e609660f5f45005a9e095541ca4c5fe"
 
-BINUTILS_GIT_URI = "git://github.com/sifive/riscv-binutils-gdb.git;branch=${SRCBRANCH};protocol=git"
+BINUTILS_GIT_URI = "git://github.com/riscv/riscv-binutils-gdb.git;branch=${SRCBRANCH};protocol=git"
 
 SRC_URI = "\
       ${BINUTILS_GIT_URI} \
-      file://0005-Point-scripts-location-to-libdir.patch \
+      file://0001-resolve-bug-1-unsupported-zvmo-extension.patch \
+      file://0002-Add-support-for-B-extension.patch \
+      file://0003-merge-rvv1.0-branch.patch \
+      file://0005-support-Dubhe-V-extension.patch \
+      file://0005-Point-scripts-location-to-libdir.patch \ 
+      file://0006-Add-pseudo-instructions-for-B-extension.patch \
+      file://0007-Rename-bdep-to-bdecompress.patch \
+      file://0008-RISCV-Add-support-for-bcompress.patch \
+      file://0009-RISCV-Coding-bug-Fix-for-FSRW.patch \
+      file://0010-RISCV-Coding-bug-Fix-for-FSRIW.patch \
+      file://0011-RISCV-Fix-coding-for-un-zip-2-4-8-16-n-b-h-w.patch \
+      file://0012-update-bitmap-version-number-from-0.93-to-0.94.patch \
+      file://0013-Fix-gas-test-cases.patch \
+      file://0014-resolve-crash-issue-when-objdump-encounter-unrecogni.patch \
+      file://0015-Remove-MASK_SHAMT2.patch \
+      file://0016-Fix-internal-error-undefined-modifier-r.patch \
+      file://0017-Fix-coding-for-Bcompressw.patch \
+      file://0018-Fix-zip2.b-testcase.patch \
+      file://0019-Fix-orc2.n-testcase.patch \
+      file://0020-Fix-rev2.n-test-case.patch \
+      file://0021-Fix-testcase-for-zip2.b-and-rev2.n.patch \
+      file://0022-Fix-r-operands-type-from-fpr-to-gpr.patch \
+      file://0023-support-vid-vmv1r-vl1r-vs1r-instruction.patch \
+      file://0024-add-vid-instruction-support.patch \
+      file://0025-Fix-all-issues-in-b-ext-64.d.patch \
+      file://0026-Apply-same-fix-on-b-ext.d.patch \
+      file://0027-remove-redundant-symbol.patch \
+      file://0028-solved-vector-insns-test-failed-n.patch \
 "
-

+ 32 - 5
recipes-devtools/binutils/binutils-cross_2.36.bbappend

@@ -1,11 +1,38 @@
-SRCBRANCH = "sifive-rvv-1.0.x-zfh-rvb"
+FILESEXTRAPATHS_prepend := "${THISDIR}/binutils:"
+SRCBRANCH = "riscv-binutils-2.36.1"
 
-SRCREV = "75d2236ce26a3048f52bbd5186602e27bd635e2b"
+SRCREV = "f35674005e609660f5f45005a9e095541ca4c5fe"
 
-BINUTILS_GIT_URI = "git://github.com/sifive/riscv-binutils-gdb.git;branch=${SRCBRANCH};protocol=git"
+BINUTILS_GIT_URI = "git://github.com/riscv/riscv-binutils-gdb.git;branch=${SRCBRANCH};protocol=git"
 
 SRC_URI = "\
       ${BINUTILS_GIT_URI} \
-      file://0005-Point-scripts-location-to-libdir.patch \
+      file://0001-resolve-bug-1-unsupported-zvmo-extension.patch \
+      file://0002-Add-support-for-B-extension.patch \
+      file://0003-merge-rvv1.0-branch.patch \
+      file://0005-support-Dubhe-V-extension.patch \
+      file://0005-Point-scripts-location-to-libdir.patch \ 
+      file://0006-Add-pseudo-instructions-for-B-extension.patch \
+      file://0007-Rename-bdep-to-bdecompress.patch \
+      file://0008-RISCV-Add-support-for-bcompress.patch \
+      file://0009-RISCV-Coding-bug-Fix-for-FSRW.patch \
+      file://0010-RISCV-Coding-bug-Fix-for-FSRIW.patch \
+      file://0011-RISCV-Fix-coding-for-un-zip-2-4-8-16-n-b-h-w.patch \
+      file://0012-update-bitmap-version-number-from-0.93-to-0.94.patch \
+      file://0013-Fix-gas-test-cases.patch \
+      file://0014-resolve-crash-issue-when-objdump-encounter-unrecogni.patch \
+      file://0015-Remove-MASK_SHAMT2.patch \
+      file://0016-Fix-internal-error-undefined-modifier-r.patch \
+      file://0017-Fix-coding-for-Bcompressw.patch \
+      file://0018-Fix-zip2.b-testcase.patch \
+      file://0019-Fix-orc2.n-testcase.patch \
+      file://0020-Fix-rev2.n-test-case.patch \
+      file://0021-Fix-testcase-for-zip2.b-and-rev2.n.patch \
+      file://0022-Fix-r-operands-type-from-fpr-to-gpr.patch \
+      file://0023-support-vid-vmv1r-vl1r-vs1r-instruction.patch \
+      file://0024-add-vid-instruction-support.patch \
+      file://0025-Fix-all-issues-in-b-ext-64.d.patch \
+      file://0026-Apply-same-fix-on-b-ext.d.patch \
+      file://0027-remove-redundant-symbol.patch \
+      file://0028-solved-vector-insns-test-failed-n.patch \
 "
-

+ 32 - 5
recipes-devtools/binutils/binutils-crosssdk_2.36.bbappend

@@ -1,11 +1,38 @@
-SRCBRANCH = "sifive-rvv-1.0.x-zfh-rvb"
+FILESEXTRAPATHS_prepend := "${THISDIR}/binutils:"
+SRCBRANCH = "riscv-binutils-2.36.1"
 
-SRCREV = "75d2236ce26a3048f52bbd5186602e27bd635e2b"
+SRCREV = "f35674005e609660f5f45005a9e095541ca4c5fe"
 
-BINUTILS_GIT_URI = "git://github.com/sifive/riscv-binutils-gdb.git;branch=${SRCBRANCH};protocol=git"
+BINUTILS_GIT_URI = "git://github.com/riscv/riscv-binutils-gdb.git;branch=${SRCBRANCH};protocol=git"
 
 SRC_URI = "\
       ${BINUTILS_GIT_URI} \
-      file://0005-Point-scripts-location-to-libdir.patch \
+      file://0001-resolve-bug-1-unsupported-zvmo-extension.patch \
+      file://0002-Add-support-for-B-extension.patch \
+      file://0003-merge-rvv1.0-branch.patch \
+      file://0005-support-Dubhe-V-extension.patch \
+      file://0005-Point-scripts-location-to-libdir.patch \ 
+      file://0006-Add-pseudo-instructions-for-B-extension.patch \
+      file://0007-Rename-bdep-to-bdecompress.patch \
+      file://0008-RISCV-Add-support-for-bcompress.patch \
+      file://0009-RISCV-Coding-bug-Fix-for-FSRW.patch \
+      file://0010-RISCV-Coding-bug-Fix-for-FSRIW.patch \
+      file://0011-RISCV-Fix-coding-for-un-zip-2-4-8-16-n-b-h-w.patch \
+      file://0012-update-bitmap-version-number-from-0.93-to-0.94.patch \
+      file://0013-Fix-gas-test-cases.patch \
+      file://0014-resolve-crash-issue-when-objdump-encounter-unrecogni.patch \
+      file://0015-Remove-MASK_SHAMT2.patch \
+      file://0016-Fix-internal-error-undefined-modifier-r.patch \
+      file://0017-Fix-coding-for-Bcompressw.patch \
+      file://0018-Fix-zip2.b-testcase.patch \
+      file://0019-Fix-orc2.n-testcase.patch \
+      file://0020-Fix-rev2.n-test-case.patch \
+      file://0021-Fix-testcase-for-zip2.b-and-rev2.n.patch \
+      file://0022-Fix-r-operands-type-from-fpr-to-gpr.patch \
+      file://0023-support-vid-vmv1r-vl1r-vs1r-instruction.patch \
+      file://0024-add-vid-instruction-support.patch \
+      file://0025-Fix-all-issues-in-b-ext-64.d.patch \
+      file://0026-Apply-same-fix-on-b-ext.d.patch \
+      file://0027-remove-redundant-symbol.patch \
+      file://0028-solved-vector-insns-test-failed-n.patch \
 "
-

+ 25 - 0
recipes-devtools/binutils/binutils/0001-resolve-bug-1-unsupported-zvmo-extension.patch

@@ -0,0 +1,25 @@
+From 7578dbdb2be0b6183b36303d115521ebae28f2f6 Mon Sep 17 00:00:00 2001
+From: "max.ma" <max.ma@starfivetech.com>
+Date: Tue, 18 May 2021 18:05:37 -0700
+Subject: [PATCH 01/28] resolve bug#1: unsupported zvmo extension
+
+---
+ bfd/elfxx-riscv.c | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+diff --git a/bfd/elfxx-riscv.c b/bfd/elfxx-riscv.c
+index 97ad51f865..0d5bec4762 100644
+--- a/bfd/elfxx-riscv.c
++++ b/bfd/elfxx-riscv.c
+@@ -1597,7 +1597,7 @@ riscv_parse_prefixed_ext (riscv_parse_subset_t *rps,
+ 
+ static const char * const riscv_std_z_ext_strtab[] =
+ {
+-  "zicsr", "zifencei", "zihintpause", NULL
++  "zicsr", "zifencei", "zihintpause", "zvamo", "zvlsseg", NULL
+ };
+ 
+ static const char * const riscv_std_s_ext_strtab[] =
+-- 
+2.33.0
+

+ 1001 - 0
recipes-devtools/binutils/binutils/0002-Add-support-for-B-extension.patch

@@ -0,0 +1,1001 @@
+From 4bbe6648eb8c452a9dcd77895caf2c3f0d8771f7 Mon Sep 17 00:00:00 2001
+From: "max.ma" <max.ma@starfivetech.com>
+Date: Wed, 19 May 2021 02:19:34 -0700
+Subject: [PATCH 02/28] Add support for B extension
+
+---
+ bfd/elfxx-riscv.c                  |   2 +-
+ gas/config/tc-riscv.c              |  31 +++
+ gas/testsuite/gas/riscv/b-ext-64.d | 117 +++++++++++
+ gas/testsuite/gas/riscv/b-ext-64.s | 108 ++++++++++
+ gas/testsuite/gas/riscv/b-ext.d    |  74 +++++++
+ gas/testsuite/gas/riscv/b-ext.s    |  65 +++++++
+ include/opcode/riscv-opc.h         | 303 +++++++++++++++++++++++++++++
+ include/opcode/riscv.h             |  15 ++
+ opcodes/riscv-dis.c                |   4 +
+ opcodes/riscv-opc.c                | 139 +++++++++++++
+ 10 files changed, 857 insertions(+), 1 deletion(-)
+ create mode 100755 gas/testsuite/gas/riscv/b-ext-64.d
+ create mode 100755 gas/testsuite/gas/riscv/b-ext-64.s
+ create mode 100755 gas/testsuite/gas/riscv/b-ext.d
+ create mode 100755 gas/testsuite/gas/riscv/b-ext.s
+
+diff --git a/bfd/elfxx-riscv.c b/bfd/elfxx-riscv.c
+index 0d5bec4762..8c8af2386b 100644
+--- a/bfd/elfxx-riscv.c
++++ b/bfd/elfxx-riscv.c
+@@ -1597,7 +1597,7 @@ riscv_parse_prefixed_ext (riscv_parse_subset_t *rps,
+ 
+ static const char * const riscv_std_z_ext_strtab[] =
+ {
+-  "zicsr", "zifencei", "zihintpause", "zvamo", "zvlsseg", NULL
++  "zicsr", "zifencei", "zihintpause", "zba", "zbb", "zbc", "zbe", "zbf", "zbm", "zbp", "zbr", "zbs", "zbt", "zvamo", "zvlsseg",NULL
+ };
+ 
+ static const char * const riscv_std_s_ext_strtab[] =
+diff --git a/gas/config/tc-riscv.c b/gas/config/tc-riscv.c
+index 3322f17ccb..3e76e538c4 100644
+--- a/gas/config/tc-riscv.c
++++ b/gas/config/tc-riscv.c
+@@ -253,6 +253,37 @@ riscv_multi_subset_supports (enum riscv_insn_class insn_class)
+     case INSN_CLASS_ZIHINTPAUSE:
+       return riscv_subset_supports ("zihintpause");
+ 
++    case INSN_CLASS_ZBB:
++      return riscv_subset_supports ("zbb");
++    case INSN_CLASS_ZBA:
++      return riscv_subset_supports ("zba");
++    case INSN_CLASS_ZBC:
++      return riscv_subset_supports ("zbc");
++    case INSN_CLASS_ZBE:
++      return riscv_subset_supports ("zbe");
++    case INSN_CLASS_ZBF:
++      return riscv_subset_supports ("zbf");
++    case INSN_CLASS_ZBM:
++      return riscv_subset_supports ("zbm");
++    case INSN_CLASS_ZBP:
++      return riscv_subset_supports ("zbp");
++    case INSN_CLASS_ZBR:
++      return riscv_subset_supports ("zbr");
++    case INSN_CLASS_ZBS:
++      return riscv_subset_supports ("zbs");
++    case INSN_CLASS_ZBT:
++      return riscv_subset_supports ("zbt");
++    case INSN_CLASS_ZBB_OR_ZBP:
++      return (riscv_subset_supports ("zbb") || riscv_subset_supports ("zbp"));
++    case INSN_CLASS_ZBS_OR_ZBE:
++      return (riscv_subset_supports ("zbs") || riscv_subset_supports ("zbe"));
++    case INSN_CLASS_ZBP_OR_ZBM:
++      return (riscv_subset_supports ("zbp") || riscv_subset_supports ("zbm"));
++    case INSN_CLASS_ZBP_OR_ZBE_OR_ZBF:
++      return (riscv_subset_supports ("zbp") || riscv_subset_supports ("zbe") || riscv_subset_supports ("zbf"));
++    case INSN_CLASS_ZBP_OR_ZBE_OR_ZBF_OR_ZBM:
++      return (riscv_subset_supports ("zbp") || riscv_subset_supports ("zbe") || riscv_subset_supports ("zbf") || riscv_subset_supports ("zbm"));
++
+     default:
+       as_fatal ("Unreachable");
+       return FALSE;
+diff --git a/gas/testsuite/gas/riscv/b-ext-64.d b/gas/testsuite/gas/riscv/b-ext-64.d
+new file mode 100755
+index 0000000000..23da2e0d58
+--- /dev/null
++++ b/gas/testsuite/gas/riscv/b-ext-64.d
+@@ -0,0 +1,117 @@
++#as: -march=rv64i_zba_zbb_zbc_zbe_zbf_zbm_zbp_zbr_zbs_zbt
++#source: b-ext-64.s
++#objdump: -d
++
++.*:[ 	]+file format .*
++
++
++Disassembly of section .text:
++
++0+000 <target>:
++[ 	]+0:[ 	]+60051513[ 	]+clz[ 	]+a0,a0
++[ 	]+4:[ 	]+60151513[ 	]+ctz[ 	]+a0,a0
++[ 	]+8:[ 	]+60251513[ 	]+cpop[ 	]+a0,a0
++[ 	]+c:[ 	]+0ac5c533[ 	]+min[ 	]+a0,a1,a2
++[ 	]+10:[ 	]+0ac5d533[ 	]+minu[ 	]+a0,a1,a2
++[ 	]+14:[ 	]+0ac5e533[ 	]+max[ 	]+a0,a1,a2
++[ 	]+18:[ 	]+0ac5f533[ 	]+maxu[ 	]+a0,a1,a2
++[ 	]+1c:[ 	]+60451513[ 	]+sext.b[ 	]+a0,a0
++[ 	]+20:[ 	]+60551513[ 	]+sext.h[ 	]+a0,a0
++[ 	]+24:[ 	]+0805453b[ 	]+zext.h[ 	]+a0,a0
++[ 	]+28:[ 	]+40c5f533[ 	]+andn[ 	]+a0,a1,a2
++[ 	]+2c:[ 	]+40c5e533[ 	]+orn[ 	]+a0,a1,a2
++[ 	]+30:[ 	]+40c5c533[ 	]+xnor[ 	]+a0,a1,a2
++[ 	]+34:[ 	]+60c59533[ 	]+rol[ 	]+a0,a1,a2
++[ 	]+38:[ 	]+60c5d533[ 	]+ror[ 	]+a0,a1,a2
++[ 	]+3c:[ 	]+6025d513[ 	]+rori[ 	]+a0,a1,0x2
++[ 	]+40:[ 	]+6025d513[ 	]+rori[ 	]+a0,a1,0x2
++[ 	]+44:[ 	]+6b855513[ 	]+rev8[ 	]+a0,a0
++[ 	]+48:[ 	]+28755513[ 	]+orc.b[ 	]+a0,a0
++[ 	]+4c:[ 	]+20c5a533[ 	]+sh1add[ 	]+a0,a1,a2
++[ 	]+50:[ 	]+20c5c533[ 	]+sh2add[ 	]+a0,a1,a2
++[ 	]+54:[ 	]+20c5e533[ 	]+sh3add[ 	]+a0,a1,a2
++[ 	]+58:[ 	]+0ac59533[ 	]+clmul[ 	]+a0,a1,a2
++[ 	]+5c:[ 	]+0ac5b533[ 	]+clmulh[ 	]+a0,a1,a2
++[ 	]+60:[ 	]+0ac5a533[ 	]+clmulr[ 	]+a0,a1,a2
++[ 	]+64:[ 	]+6005151b[ 	]+clzw[ 	]+a0,a0
++[ 	]+68:[ 	]+6015151b[ 	]+ctzw[ 	]+a0,a0
++[ 	]+6c:[ 	]+6025151b[ 	]+cpopw[ 	]+a0,a0
++[ 	]+70:[ 	]+60c5953b[ 	]+rolw[ 	]+a0,a1,a2
++[ 	]+74:[ 	]+60c5d53b[ 	]+rorw[ 	]+a0,a1,a2
++[ 	]+78:[ 	]+6025d51b[ 	]+roriw[ 	]+a0,a1,0x2
++[ 	]+7c:[ 	]+6025d51b[ 	]+roriw[ 	]+a0,a1,0x2
++[ 	]+80:[ 	]+20c5a53b[ 	]+sh1add.uw[ 	]+a0,a1,a2
++[ 	]+84:[ 	]+20c5c53b[ 	]+sh2add.uw[ 	]+a0,a1,a2
++[ 	]+88:[ 	]+20c5e53b[ 	]+sh3add.uw[ 	]+a0,a1,a2
++[ 	]+8c:[ 	]+08c5853b[ 	]+add.uw[ 	]+a0,a1,a2
++[ 	]+90:[ 	]+0805853b[ 	]+zext.w[ 	]+a0,a1
++[ 	]+94:[ 	]+0825951b[ 	]+slli.uw[ 	]+a0,a1,0x2
++[ 	]+98:[ 	]+08c5c533[ 	]+pack[ 	]+a0,a1,a2
++[ 	]+9c:[ 	]+48c5c533[ 	]+packu[ 	]+a0,a1,a2
++[ 	]+a0:[ 	]+08c5f533[ 	]+packh[ 	]+a0,a1,a2
++[ 	]+a4:[ 	]+0825c53b[ 	]+packw[ 	]+a0,a1,0x2
++[ 	]+a8:[ 	]+4825c53b[ 	]+packuw[ 	]+a0,a1,0x2
++[ 	]+ac:[ 	]+68c5d533[ 	]+grev[ 	]+a0,a1,a2
++[ 	]+b0:[ 	]+6825d513[ 	]+grevi[ 	]+a0,a1,0x2
++[ 	]+b4:[ 	]+6825d53b[ 	]+grevw[ 	]+a0,a1,0x2
++[ 	]+b8:[ 	]+6825d51b[ 	]+greviw[ 	]+a0,a1,0x2
++[ 	]+bc:[ 	]+28c5d533[ 	]+gorc[ 	]+a0,a1,a2
++[ 	]+c0:[ 	]+2825d513[ 	]+gorci[ 	]+a0,a1,0x2
++[ 	]+c4:[ 	]+2825d53b[ 	]+gorcw[ 	]+a0,a1,0x2
++[ 	]+c8:[ 	]+2825d51b[ 	]+gorciw[ 	]+a0,a1,0x2
++[ 	]+cc:[ 	]+08c59533[ 	]+shfl[ 	]+a0,a1,a2
++[ 	]+d0:[ 	]+08259513[ 	]+shfli[ 	]+a0,a1,0x2
++[ 	]+d4:[ 	]+0825953b[ 	]+shflw[ 	]+a0,a1,0x2
++[ 	]+d8:[ 	]+08c5d533[ 	]+unshfl[ 	]+a0,a1,a2
++[ 	]+dc:[ 	]+0825d513[ 	]+unshfli[ 	]+a0,a1,0x2
++[ 	]+e0:[ 	]+0825d53b[ 	]+unshflw[ 	]+a0,a1,0x2
++[ 	]+e4:[ 	]+28c5a533[ 	]+xperm.n[ 	]+a0,a1,a2
++[ 	]+e8:[ 	]+28c5c533[ 	]+xperm.b[ 	]+a0,a1,a2
++[ 	]+ec:[ 	]+28c5e533[ 	]+xperm.h[ 	]+a0,a1,a2
++[ 	]+f0:[ 	]+28258533[ 	]+xperm.w[ 	]+a0,a1,0x2
++[ 	]+f4:[ 	]+28c59533[ 	]+bset[ 	]+a0,a1,a2
++[ 	]+f8:[ 	]+48c59533[ 	]+bclr[ 	]+a0,a1,a2
++[ 	]+fc:[ 	]+68c59533[ 	]+binv[ 	]+a0,a1,a2
++[ 	]+100:[ 	]+48c5d533[ 	]+bext[ 	]+a0,a1,a2
++[ 	]+104:[ 	]+48c5e533[ 	]+bdep[ 	]+a0,a1,a2
++[ 	]+108:[ 	]+28259513[ 	]+bseti[ 	]+a0,a1,0x2
++[ 	]+10c:[ 	]+48259513[ 	]+bclri[ 	]+a0,a1,0x2
++[ 	]+110:[ 	]+68259513[ 	]+binvi[ 	]+a0,a1,0x2
++[ 	]+114:[ 	]+4825d513[ 	]+bexti[ 	]+a0,a1,0x2
++[ 	]+118:[ 	]+28c5953b[ 	]+bsetw[ 	]+a0,a1,a2
++[ 	]+11c:[ 	]+48c5953b[ 	]+bclrw[ 	]+a0,a1,a2
++[ 	]+120:[ 	]+68c5953b[ 	]+binvw[ 	]+a0,a1,a2
++[ 	]+124:[ 	]+48c5d53b[ 	]+bextw[ 	]+a0,a1,a2
++[ 	]+128:[ 	]+4825e53b[ 	]+bdepw[ 	]+a0,a1,0x2
++[ 	]+12c:[ 	]+2825951b[ 	]+bsetiw[ 	]+a0,a1,0x2
++[ 	]+130:[ 	]+4825951b[ 	]+bclriw[ 	]+a0,a1,0x2
++[ 	]+134:[ 	]+6825951b[ 	]+binviw[ 	]+a0,a1,0x2
++[ 	]+138:[ 	]+20c59533[ 	]+slo[ 	]+a0,a1,a2
++[ 	]+13c:[ 	]+20c5d533[ 	]+sro[ 	]+a0,a1,a2
++[ 	]+140:[ 	]+20259513[ 	]+sloi[ 	]+a0,a1,0x2
++[ 	]+144:[ 	]+2025d513[ 	]+sroi[ 	]+a0,a1,0x2
++[ 	]+148:[ 	]+2025953b[ 	]+slow[ 	]+a0,a1,0x2
++[ 	]+14c:[ 	]+2025d53b[ 	]+srow[ 	]+a0,a1,0x2
++[ 	]+150:[ 	]+2025951b[ 	]+sloiw[ 	]+a0,a1,0x2
++[ 	]+154:[ 	]+2025d51b[ 	]+sroiw[ 	]+a0,a1,0x2
++[ 	]+158:[ 	]+48c5f533[ 	]+bfp[ 	]+a0,a1,a2
++[ 	]+15c:[ 	]+4825f53b[ 	]+bfpw[ 	]+a0,a1,0x2
++[ 	]+160:[ 	]+08c5b533[ 	]+bmator[ 	]+a0,a1,a2
++[ 	]+164:[ 	]+48c5b533[ 	]+bmatxor[ 	]+a0,a1,a2
++[ 	]+168:[ 	]+60351513[ 	]+bmatflip[ 	]+a0,a0
++[ 	]+16c:[ 	]+61051513[ 	]+crc32.b[ 	]+a0,a0
++[ 	]+170:[ 	]+61151513[ 	]+crc32.h[ 	]+a0,a0
++[ 	]+174:[ 	]+61251513[ 	]+crc32.w[ 	]+a0,a0
++[ 	]+178:[ 	]+61851513[ 	]+crc32c.b[ 	]+a0,a0
++[ 	]+17c:[ 	]+61951513[ 	]+crc32c.h[ 	]+a0,a0
++[ 	]+180:[ 	]+61a51513[ 	]+crc32c.w[ 	]+a0,a0
++[ 	]+184:[ 	]+61351513[ 	]+crc32.d[ 	]+a0,a0
++[ 	]+188:[ 	]+61b51513[ 	]+crc32c.d[ 	]+a0,a0
++[ 	]+18c:[ 	]+6ec59533[ 	]+cmix[ 	]+a0,a1,a2,a3
++[ 	]+190:[ 	]+6ec5d533[ 	]+cmov[ 	]+a0,a1,a2,a3
++[ 	]+194:[ 	]+6cc59533[ 	]+fsl[ 	]+a0,a1,a2,a3
++[ 	]+198:[ 	]+6cc5d533[ 	]+fsr[ 	]+a0,a1,a2,a3
++[ 	]+19c:[ 	]+6c25d513[ 	]+fsri[ 	]+a0,a1,0x2,a3
++[ 	]+1a0:[ 	]+6c25953b[ 	]+fslw[ 	]+a0,a1,0x2,a3
++[ 	]+1a4:[ 	]+6c25b53b[ 	]+fsrw[ 	]+a0,a1,0x2,a3
++[ 	]+1a8:[ 	]+6c25b51b[ 	]+fsriw[ 	]+a0,a1,0x2,a3
+diff --git a/gas/testsuite/gas/riscv/b-ext-64.s b/gas/testsuite/gas/riscv/b-ext-64.s
+new file mode 100755
+index 0000000000..176d617be5
+--- /dev/null
++++ b/gas/testsuite/gas/riscv/b-ext-64.s
+@@ -0,0 +1,108 @@
++target:
++	clz	a0, a0
++	ctz	a0, a0
++	cpop	a0, a0
++	min	a0, a1, a2
++	minu	a0, a1, a2
++	max	a0, a1, a2
++	maxu	a0, a1, a2
++	sext.b	a0, a0
++	sext.h	a0, a0
++	zext.h	a0, a0
++	andn	a0, a1, a2
++	orn	a0, a1, a2
++	xnor	a0, a1, a2
++	rol	a0, a1, a2
++	ror	a0, a1, a2
++	ror	a0, a1, 2
++	rori	a0, a1, 2
++	rev8	a0, a0
++	orc.b	a0, a0
++	sh1add	a0, a1, a2
++	sh2add	a0, a1, a2
++	sh3add	a0, a1, a2
++	clmul	a0, a1, a2
++	clmulh	a0, a1, a2
++	clmulr	a0, a1, a2
++	clzw	a0, a0
++	ctzw	a0, a0
++	cpopw	a0, a0
++	rolw	a0, a1, a2
++	rorw	a0, a1, a2
++	rorw	a0, a1, 2
++	roriw	a0, a1, 2
++	sh1add.uw	a0, a1, a2
++	sh2add.uw	a0, a1, a2
++	sh3add.uw	a0, a1, a2
++	add.uw	a0, a1, a2
++	zext.w	a0, a1
++	slli.uw	a0, a1, 2
++	pack	a0, a1, a2
++	packu	a0, a1, a2
++	packh	a0, a1, a2
++	packw	a0, a1, 2
++	packuw	a0, a1, 2
++	grev	a0, a1, a2
++	grevi	a0, a1, 2
++	grevw	a0, a1, 2
++	greviw	a0, a1, 2
++	gorc	a0, a1, a2
++	gorci	a0, a1, 2
++	gorcw	a0, a1, 2
++	gorciw	a0, a1, 2
++	shfl	a0, a1, a2
++	shfli	a0, a1, 2
++	shflw	a0, a1, 2
++	unshfl	a0, a1, a2
++	unshfli	a0, a1, 2
++	unshflw	a0, a1, 2
++	xperm.n	a0, a1, a2
++	xperm.b	a0, a1, a2
++	xperm.h	a0, a1, a2
++	xperm.w	a0, a1, 2
++	bset	a0, a1, a2
++	bclr	a0, a1, a2
++	binv	a0, a1, a2
++	bext	a0, a1, a2
++	bdep	a0, a1, a2
++	bseti	a0, a1, 2
++	bclri	a0, a1, 2
++	binvi	a0, a1, 2
++	bexti	a0, a1, 2
++	bsetw	a0, a1, a2
++	bclrw	a0, a1, a2
++	binvw	a0, a1, a2
++	bextw	a0, a1, a2
++	bdepw	a0, a1, 2
++	bsetiw	a0, a1, 2
++	bclriw	a0, a1, 2
++	binviw	a0, a1, 2
++	slo	a0, a1, a2
++	sro	a0, a1, a2
++	sloi	a0, a1, 2
++	sroi	a0, a1, 2
++	slow	a0, a1, 2
++	srow	a0, a1, 2
++	sloiw	a0, a1, 2
++	sroiw	a0, a1, 2
++	bfp	a0, a1, a2
++	bfpw	a0, a1, 2
++	bmator	a0, a1, a2
++	bmatxor	a0, a1, a2
++	bmatflip	a0, a0
++	crc32.b	a0, a0
++	crc32.h	a0, a0
++	crc32.w	a0, a0
++	crc32c.b	a0, a0
++	crc32c.h	a0, a0
++	crc32c.w	a0, a0
++	crc32.d	a0, a0
++	crc32c.d	a0, a0
++	cmix	a0, a1, a2, a3
++	cmov	a0, a1, a2, a3
++	fsl	a0, a1, a2, a3
++	fsr	a0, a1, a2, a3
++	fsri	a0, a1,  2, a3
++	fslw	a0, a1,  2, a3
++	fsrw	a0, a1,  2, a3
++	fsriw	a0, a1,  2, a3
+diff --git a/gas/testsuite/gas/riscv/b-ext.d b/gas/testsuite/gas/riscv/b-ext.d
+new file mode 100755
+index 0000000000..4df9e90693
+--- /dev/null
++++ b/gas/testsuite/gas/riscv/b-ext.d
+@@ -0,0 +1,74 @@
++#as: -march=rv32i_zba_zbb_zbc_zbe_zbf_zbm_zbp_zbr_zbs_zbt
++#source: b-ext.s
++#objdump: -d
++
++.*:[ 	]+file format .*
++
++
++Disassembly of section .text:
++
++0+000 <target>:
++[ 	]+0:[ 	]+60051513[ 	]+clz[ 	]+a0,a0
++[ 	]+4:[ 	]+60151513[ 	]+ctz[ 	]+a0,a0
++[ 	]+8:[ 	]+60251513[ 	]+cpop[ 	]+a0,a0
++[ 	]+c:[ 	]+0ac5c533[ 	]+min[ 	]+a0,a1,a2
++[ 	]+10:[ 	]+0ac5d533[ 	]+minu[ 	]+a0,a1,a2
++[ 	]+14:[ 	]+0ac5e533[ 	]+max[ 	]+a0,a1,a2
++[ 	]+18:[ 	]+0ac5f533[ 	]+maxu[ 	]+a0,a1,a2
++[ 	]+1c:[ 	]+60451513[ 	]+sext.b[ 	]+a0,a0
++[ 	]+20:[ 	]+60551513[ 	]+sext.h[ 	]+a0,a0
++[ 	]+24:[ 	]+08054533[ 	]+zext.h[ 	]+a0,a0
++[ 	]+28:[ 	]+40c5f533[ 	]+andn[ 	]+a0,a1,a2
++[ 	]+2c:[ 	]+40c5e533[ 	]+orn[ 	]+a0,a1,a2
++[ 	]+30:[ 	]+40c5c533[ 	]+xnor[ 	]+a0,a1,a2
++[ 	]+34:[ 	]+60c59533[ 	]+rol[ 	]+a0,a1,a2
++[ 	]+38:[ 	]+60c5d533[ 	]+ror[ 	]+a0,a1,a2
++[ 	]+3c:[ 	]+6025d513[ 	]+rori[ 	]+a0,a1,0x2
++[ 	]+40:[ 	]+6025d513[ 	]+rori[ 	]+a0,a1,0x2
++[ 	]+44:[ 	]+69855513[ 	]+rev8[ 	]+a0,a0
++[ 	]+48:[ 	]+28755513[ 	]+orc.b[ 	]+a0,a0
++[ 	]+4c:[ 	]+20c5a533[ 	]+sh1add[ 	]+a0,a1,a2
++[ 	]+50:[ 	]+20c5c533[ 	]+sh2add[ 	]+a0,a1,a2
++[ 	]+54:[ 	]+20c5e533[ 	]+sh3add[ 	]+a0,a1,a2
++[ 	]+58:[ 	]+0ac59533[ 	]+clmul[ 	]+a0,a1,a2
++[ 	]+5c:[ 	]+0ac5b533[ 	]+clmulh[ 	]+a0,a1,a2
++[ 	]+60:[ 	]+0ac5a533[ 	]+clmulr[ 	]+a0,a1,a2
++[ 	]+64:[ 	]+08c5c533[ 	]+pack[ 	]+a0,a1,a2
++[ 	]+68:[ 	]+48c5c533[ 	]+packu[ 	]+a0,a1,a2
++[ 	]+6c:[ 	]+08c5f533[ 	]+packh[ 	]+a0,a1,a2
++[ 	]+70:[ 	]+68c5d533[ 	]+grev[ 	]+a0,a1,a2
++[ 	]+74:[ 	]+6825d513[ 	]+grevi[ 	]+a0,a1,0x2
++[ 	]+78:[ 	]+28c5d533[ 	]+gorc[ 	]+a0,a1,a2
++[ 	]+7c:[ 	]+2825d513[ 	]+gorci[ 	]+a0,a1,0x2
++[ 	]+80:[ 	]+08c59533[ 	]+shfl[ 	]+a0,a1,a2
++[ 	]+84:[ 	]+08259513[ 	]+shfli[ 	]+a0,a1,0x2
++[ 	]+88:[ 	]+08c5d533[ 	]+unshfl[ 	]+a0,a1,a2
++[ 	]+8c:[ 	]+0825d513[ 	]+unshfli[ 	]+a0,a1,0x2
++[ 	]+90:[ 	]+28c5a533[ 	]+xperm.n[ 	]+a0,a1,a2
++[ 	]+94:[ 	]+28c5c533[ 	]+xperm.b[ 	]+a0,a1,a2
++[ 	]+98:[ 	]+28c5e533[ 	]+xperm.h[ 	]+a0,a1,a2
++[ 	]+9c:[ 	]+28c59533[ 	]+bset[ 	]+a0,a1,a2
++[ 	]+a0:[ 	]+48c59533[ 	]+bclr[ 	]+a0,a1,a2
++[ 	]+a4:[ 	]+68c59533[ 	]+binv[ 	]+a0,a1,a2
++[ 	]+a8:[ 	]+48c5d533[ 	]+bext[ 	]+a0,a1,a2
++[ 	]+ac:[ 	]+48c5e533[ 	]+bdep[ 	]+a0,a1,a2
++[ 	]+b0:[ 	]+28259513[ 	]+bseti[ 	]+a0,a1,0x2
++[ 	]+b4:[ 	]+48259513[ 	]+bclri[ 	]+a0,a1,0x2
++[ 	]+b8:[ 	]+68259513[ 	]+binvi[ 	]+a0,a1,0x2
++[ 	]+bc:[ 	]+4825d513[ 	]+bexti[ 	]+a0,a1,0x2
++[ 	]+c0:[ 	]+20c59533[ 	]+slo[ 	]+a0,a1,a2
++[ 	]+c4:[ 	]+20c5d533[ 	]+sro[ 	]+a0,a1,a2
++[ 	]+c8:[ 	]+20259513[ 	]+sloi[ 	]+a0,a1,0x2
++[ 	]+cc:[ 	]+2025d513[ 	]+sroi[ 	]+a0,a1,0x2
++[ 	]+d0:[ 	]+48c5f533[ 	]+bfp[ 	]+a0,a1,a2
++[ 	]+d4:[ 	]+61051513[ 	]+crc32.b[ 	]+a0,a0
++[ 	]+d8:[ 	]+61151513[ 	]+crc32.h[ 	]+a0,a0
++[ 	]+dc:[ 	]+61251513[ 	]+crc32.w[ 	]+a0,a0
++[ 	]+e0:[ 	]+61851513[ 	]+crc32c.b[ 	]+a0,a0
++[ 	]+e4:[ 	]+61951513[ 	]+crc32c.h[ 	]+a0,a0
++[ 	]+e8:[ 	]+61a51513[ 	]+crc32c.w[ 	]+a0,a0
++[ 	]+ec:[ 	]+6ec59533[ 	]+cmix[ 	]+a0,a1,a2,a3
++[ 	]+f0:[ 	]+6ec5d533[ 	]+cmov[ 	]+a0,a1,a2,a3
++[ 	]+f4:[ 	]+6cc59533[ 	]+fsl[ 	]+a0,a1,a2,a3
++[ 	]+f8:[ 	]+6cc5d533[ 	]+fsr[ 	]+a0,a1,a2,a3
++[ 	]+fc:[ 	]+6c25d513[ 	]+fsri[ 	]+a0,a1,0x2,a3
+diff --git a/gas/testsuite/gas/riscv/b-ext.s b/gas/testsuite/gas/riscv/b-ext.s
+new file mode 100755
+index 0000000000..429c005849
+--- /dev/null
++++ b/gas/testsuite/gas/riscv/b-ext.s
+@@ -0,0 +1,65 @@
++target:
++	clz	 a0, a0
++	ctz	 a0, a0
++	cpop	 a0, a0
++	min	 a0, a1, a2
++	minu	 a0, a1, a2
++	max	 a0, a1, a2
++	maxu	 a0, a1, a2
++	sext.b	 a0, a0
++	sext.h	 a0, a0
++	zext.h	 a0, a0
++	andn	 a0, a1, a2
++	orn	 a0, a1, a2
++	xnor	 a0, a1, a2
++	rol	 a0, a1, a2
++	ror	 a0, a1, a2
++	ror	 a0, a1, 2
++	rori	 a0, a1, 2
++	rev8	 a0, a0
++	orc.b	 a0, a0
++	sh1add	 a0, a1, a2
++	sh2add	 a0, a1, a2
++	sh3add	 a0, a1, a2
++	clmul	 a0, a1, a2
++	clmulh	 a0, a1, a2
++	clmulr	 a0, a1, a2
++	pack	 a0, a1, a2
++	packu	 a0, a1, a2
++	packh	 a0, a1, a2
++	grev	 a0, a1, a2
++	grevi	 a0, a1, 2
++	gorc	 a0, a1, a2
++	gorci	 a0, a1, 2
++	shfl	 a0, a1, a2
++	shfli	 a0, a1, 2
++	unshfl	 a0, a1, a2
++	unshfli	 a0, a1, 2
++	xperm.n	 a0, a1, a2
++	xperm.b	 a0, a1, a2
++	xperm.h	 a0, a1, a2
++	bset	 a0, a1, a2
++	bclr	 a0, a1, a2
++	binv	 a0, a1, a2
++	bext	 a0, a1, a2
++	bdep	 a0, a1, a2
++	bseti	 a0, a1, 2
++	bclri	 a0, a1, 2
++	binvi	 a0, a1, 2
++	bexti	 a0, a1, 2
++	slo	 a0, a1, a2
++	sro	 a0, a1, a2
++	sloi	 a0, a1, 2
++	sroi	 a0, a1, 2
++	bfp	 a0, a1, a2
++	crc32.b	 a0, a0
++	crc32.h	 a0, a0
++	crc32.w	 a0, a0
++	crc32c.b	 a0, a0
++	crc32c.h	 a0, a0
++	crc32c.w	 a0, a0
++	cmix	 a0, a1, a2, a3
++	cmov	 a0, a1, a2, a3
++	fsl	 a0, a1, a2, a3
++	fsr	 a0, a1, a2, a3
++	fsri	 a0, a1, 2, a3
+diff --git a/include/opcode/riscv-opc.h b/include/opcode/riscv-opc.h
+index b0e549a0f2..1a9e313fc3 100644
+--- a/include/opcode/riscv-opc.h
++++ b/include/opcode/riscv-opc.h
+@@ -113,6 +113,18 @@
+ #define MASK_SRL  0xfe00707f
+ #define MATCH_SRA 0x40005033
+ #define MASK_SRA  0xfe00707f
++#define MATCH_SLO 0x20001033
++#define MASK_SLO  0xfe00707f
++#define MATCH_SLOI 0x20001013
++#define MASK_SLOI  0xfc00707f
++#define MATCH_SLOW 0x2000103b
++#define MASK_SLOW  0xfe00707f
++#define MATCH_SRO 0x20005033
++#define MASK_SRO  0xfe00707f
++#define MATCH_SROI 0x20005013
++#define MASK_SROI  0xfc00707f
++#define MATCH_SROW 0x2000503b
++#define MASK_SROW  0xfe00707f
+ #define MATCH_OR 0x6033
+ #define MASK_OR  0xfe00707f
+ #define MATCH_AND 0x7033
+@@ -423,6 +435,196 @@
+ #define MASK_FCVT_Q_LU  0xfff0007f
+ #define MATCH_FMV_Q_X 0xf6000053
+ #define MASK_FMV_Q_X  0xfff0707f
++#define MATCH_CLZ 0x60001013
++#define MASK_CLZ  0xfff0707f
++#define MATCH_CTZ 0x60101013
++#define MASK_CTZ  0xfff0707f
++#define MATCH_CPOP 0x60201013
++#define MASK_CPOP  0xfff0707f
++#define MATCH_BMATFLIP 0x60301013
++#define MASK_BMATFLIP  0xfff0707f
++#define MATCH_CRC32_B 0x61001013
++#define MASK_CRC32_B  0xfff0707f
++#define MATCH_CRC32_H 0x61101013
++#define MASK_CRC32_H  0xfff0707f
++#define MATCH_CRC32_W 0x61201013
++#define MASK_CRC32_W  0xfff0707f
++#define MATCH_CRC32_D 0x61301013
++#define MASK_CRC32_D  0xfff0707f
++#define MATCH_CRC32C_B 0x61801013
++#define MASK_CRC32C_B  0xfff0707f
++#define MATCH_CRC32C_H 0x61901013
++#define MASK_CRC32C_H  0xfff0707f
++#define MATCH_CRC32C_W 0x61A01013
++#define MASK_CRC32C_W  0xfff0707f
++#define MATCH_CRC32C_D 0x61B01013
++#define MASK_CRC32C_D  0xfff0707f
++#define MATCH_MIN 0xa004033
++#define MASK_MIN  0xfe00707f
++#define MATCH_MINU 0xa005033
++#define MASK_MINU  0xfe00707f
++#define MATCH_MAX 0xa006033
++#define MASK_MAX  0xfe00707f
++#define MATCH_MAXU 0xa007033
++#define MASK_MAXU  0xfe00707f
++#define MATCH_SHFL 0x8001033
++#define MASK_SHFL  0xfe00707f
++#define MATCH_SHFLI 0x8001013
++#define MASK_SHFLI  0xfc00707f
++#define MATCH_UNSHFL 0x8005033
++#define MASK_UNSHFL  0xfe00707f
++#define MATCH_UNSHFLI 0x8005013
++#define MASK_UNSHFLI  0xfc00707f
++#define MATCH_BDEP 0x48006033
++#define MASK_BDEP  0xfe00707f
++#define MATCH_SEXT_B 0x60401013
++#define MASK_SEXT_B  0xfff0707f
++#define MATCH_SEXT_H 0x60501013
++#define MASK_SEXT_H  0xfff0707f
++#define MATCH_PACK 0x8004033
++#define MASK_PACK  0xfe00707f
++#define MATCH_PACKU 0x48004033
++#define MASK_PACKU  0xfe00707f
++#define MATCH_BMATOR 0x8003033
++#define MASK_BMATOR  0xfe00707f
++#define MATCH_BMATXOR 0x48003033
++#define MASK_BMATXOR  0xfe00707f
++#define MATCH_PACKH 0x8007033
++#define MASK_PACKH  0xfe00707f
++#define MATCH_BFP 0x48007033
++#define MASK_BFP  0xfe00707f
++#define MATCH_PACKW 0x800403b
++#define MASK_PACKW  0xfe00707f
++#define MATCH_PACKUW 0x4800403b
++#define MASK_PACKUW  0xfe00707f
++#define MATCH_ANDN 0x40007033
++#define MASK_ANDN  0xfe00707f
++#define MATCH_ORN 0x40006033
++#define MASK_ORN  0xfe00707f
++#define MATCH_XNOR 0x40004033
++#define MASK_XNOR  0xfe00707f
++#define MATCH_ROL 0x60001033
++#define MASK_ROL  0xfe00707f
++#define MATCH_ROR 0x60005033
++#define MASK_ROR  0xfe00707f
++#define MATCH_RORI 0x60005013
++#define MASK_RORI  0xfc00707f
++#define MATCH_BCLR 0x48001033
++#define MASK_BCLR  0xfe00707f
++#define MATCH_BCLRI 0x48001013
++#define MASK_BCLRI  0xfc00707f
++#define MATCH_BSET 0x28001033
++#define MASK_BSET  0xfe00707f
++#define MATCH_BSETI 0x28001013
++#define MASK_BSETI  0xfc00707f
++#define MATCH_BINV 0x68001033
++#define MASK_BINV  0xfe00707f
++#define MATCH_BINVI 0x68001013
++#define MASK_BINVI  0xfc00707f
++#define MATCH_BEXT 0x48005033
++#define MASK_BEXT  0xfe00707f
++#define MATCH_BEXTI 0x48005013
++#define MASK_BEXTI  0xfc00707f
++#define MATCH_GREV 0x68005033
++#define MASK_GREV  0xfe00707f
++#define MATCH_GREVI 0x68005013
++#define MASK_GREVI  0xfc00707f
++#define MATCH_GORC 0x28005033
++#define MASK_GORC  0xfe00707f
++#define MATCH_GORCI 0x28005013
++#define MASK_GORCI  0xfc00707f
++#define MATCH_CMIX 0x6001033
++#define MASK_CMIX  0x600707f
++#define MATCH_CMOV 0x6005033
++#define MASK_CMOV  0x600707f
++#define MATCH_FSL 0x4001033
++#define MASK_FSL  0x600707f
++#define MATCH_FSR 0x4005033
++#define MASK_FSR  0x600707f
++#define MATCH_FSRI 0x4005013
++#define MASK_FSRI  0x400707f
++#define MATCH_CLZW 0x6000101b
++#define MASK_CLZW  0xfff0707f
++#define MATCH_CTZW 0x6010101b
++#define MASK_CTZW  0xfff0707f
++#define MATCH_CPOPW 0x6020101b
++#define MASK_CPOPW  0xfff0707f
++#define MATCH_ROLW 0x6000103b
++#define MASK_ROLW  0xfe00707f
++#define MATCH_RORW 0x6000503b
++#define MASK_RORW  0xfe00707f
++#define MATCH_RORIW 0x6000501b
++#define MASK_RORIW  0xfe00707f
++#define MATCH_SH1ADD 0x20002033
++#define MASK_SH1ADD  0xfe00707f
++#define MATCH_SH2ADD 0x20004033
++#define MASK_SH2ADD  0xfe00707f
++#define MATCH_SH3ADD 0x20006033
++#define MASK_SH3ADD  0xfe00707f
++#define MATCH_SH1ADD_UW 0x2000203b
++#define MASK_SH1ADD_UW  0xfe00707f
++#define MATCH_SH2ADD_UW 0x2000403b
++#define MASK_SH2ADD_UW  0xfe00707f
++#define MATCH_SH3ADD_UW 0x2000603b
++#define MASK_SH3ADD_UW  0xfe00707f
++#define MATCH_BCLRW 0x4800103b
++#define MASK_BCLRW  0xfe00707f
++#define MATCH_BSETW 0x2800103b
++#define MASK_BSETW  0xfe00707f
++#define MATCH_BINVW 0x6800103b
++#define MASK_BINVW  0xfe00707f
++#define MATCH_BEXTW 0x4800503b
++#define MASK_BEXTW  0xfe00707f
++#define MATCH_GORCW 0x2800503b
++#define MASK_GORCW  0xfe00707f
++#define MATCH_GREVW 0x6800503b
++#define MASK_GREVW  0xfe00707f
++#define MATCH_SLOIW 0x2000101b
++#define MASK_SLOIW  0xfe00707f
++#define MATCH_SROIW 0x2000501b
++#define MASK_SROIW  0xfe00707f
++#define MATCH_BCLRIW 0x4800101b
++#define MASK_BCLRIW  0xfe00707f
++#define MATCH_BSETIW 0x2800101b
++#define MASK_BSETIW  0xfe00707f
++#define MATCH_BINVIW 0x6800101b
++#define MASK_BINVIW  0xfe00707f
++#define MATCH_GORCIW 0x2800501b
++#define MASK_GORCIW  0xfe00707f
++#define MATCH_GREVIW 0x6800501b
++#define MASK_GREVIW  0xfe00707f
++#define MATCH_FSLW 0x400103b
++#define MASK_FSLW  0x600707f
++#define MATCH_FSRW 0x400303b
++#define MASK_FSRW  0x600707f
++#define MATCH_FSRIW 0x400301b
++#define MASK_FSRIW  0x600707f
++#define MATCH_SHFLW 0x800103b
++#define MASK_SHFLW  0xfe00707f
++#define MATCH_UNSHFLW 0x800503b
++#define MASK_UNSHFLW  0xfe00707f
++#define MATCH_BDEPW 0x4800603b
++#define MASK_BDEPW  0xfe00707f
++#define MATCH_BFPW 0x4800703b
++#define MASK_BFPW  0xfe00707f
++#define MATCH_XPERM_N 0x28002033
++#define MASK_XPERM_N  0xfe00707f
++#define MATCH_XPERM_B 0x28004033
++#define MASK_XPERM_B  0xfe00707f
++#define MATCH_XPERM_H 0x28006033
++#define MASK_XPERM_H  0xfe00707f
++#define MATCH_XPERM_W 0x28000033
++#define MASK_XPERM_W  0xfe00707f
++#define MATCH_ADD_UW 0x800003b
++#define MASK_ADD_UW  0xfe00707f
++#define MATCH_SLLI_UW 0x800101b
++#define MASK_SLLI_UW  0xfc00707f
++#define MATCH_CLMUL 0xa001033
++#define MASK_CLMUL  0xfe00707f
++#define MATCH_CLMULH 0xa003033
++#define MASK_CLMULH  0xfe00707f
++#define MATCH_CLMULR 0xa002033
++#define MASK_CLMULR  0xfe00707f
+ #define MATCH_FLW 0x2007
+ #define MASK_FLW  0x707f
+ #define MATCH_FLD 0x3007
+@@ -1046,6 +1248,107 @@ DECLARE_INSN(fcvt_q_wu, MATCH_FCVT_Q_WU, MASK_FCVT_Q_WU)
+ DECLARE_INSN(fcvt_q_l, MATCH_FCVT_Q_L, MASK_FCVT_Q_L)
+ DECLARE_INSN(fcvt_q_lu, MATCH_FCVT_Q_LU, MASK_FCVT_Q_LU)
+ DECLARE_INSN(fmv_q_x, MATCH_FMV_Q_X, MASK_FMV_Q_X)
++DECLARE_INSN(clz, MATCH_CLZ, MASK_CLZ)
++DECLARE_INSN(ctz, MATCH_CTZ, MASK_CTZ)
++DECLARE_INSN(cpop, MATCH_CPOP, MASK_CPOP)
++DECLARE_INSN(min, MATCH_MIN, MASK_MIN)
++DECLARE_INSN(minu, MATCH_MINU, MASK_MINU)
++DECLARE_INSN(max, MATCH_MAX, MASK_MAX)
++DECLARE_INSN(maxu, MATCH_MAXU, MASK_MAXU)
++DECLARE_INSN(sext_b, MATCH_SEXT_B, MASK_SEXT_B)
++DECLARE_INSN(sext_h, MATCH_SEXT_H, MASK_SEXT_H)
++DECLARE_INSN(andn, MATCH_ANDN, MASK_ANDN)
++DECLARE_INSN(orn, MATCH_ORN, MASK_ORN)
++DECLARE_INSN(xnor, MATCH_XNOR, MASK_XNOR)
++DECLARE_INSN(rol, MATCH_ROL, MASK_ROL)
++DECLARE_INSN(ror, MATCH_ROR, MASK_ROR)
++DECLARE_INSN(rori, MATCH_RORI, MASK_RORI)
++DECLARE_INSN(clzw, MATCH_CLZW, MASK_CLZW)
++DECLARE_INSN(ctzw, MATCH_CTZW, MASK_CTZW)
++DECLARE_INSN(cpopw, MATCH_CPOPW, MASK_CPOPW)
++DECLARE_INSN(rolw, MATCH_ROLW, MASK_ROLW)
++DECLARE_INSN(rorw, MATCH_RORW, MASK_RORW)
++DECLARE_INSN(roriw, MATCH_RORIW, MASK_RORIW)
++DECLARE_INSN(sh1add, MATCH_SH1ADD, MASK_SH1ADD)
++DECLARE_INSN(sh2add, MATCH_SH2ADD, MASK_SH2ADD)
++DECLARE_INSN(sh3add, MATCH_SH3ADD, MASK_SH3ADD)
++DECLARE_INSN(sh1add_uw, MATCH_SH1ADD_UW, MASK_SH1ADD_UW)
++DECLARE_INSN(sh2add_uw, MATCH_SH2ADD_UW, MASK_SH2ADD_UW)
++DECLARE_INSN(sh3add_uw, MATCH_SH3ADD_UW, MASK_SH3ADD_UW)
++DECLARE_INSN(add_uw, MATCH_ADD_UW, MASK_ADD_UW)
++DECLARE_INSN(slli_uw, MATCH_SLLI_UW, MASK_SLLI_UW)
++DECLARE_INSN(clmul, MATCH_CLMUL, MASK_CLMUL)
++DECLARE_INSN(clmulh, MATCH_CLMULH, MASK_CLMULH)
++DECLARE_INSN(clmulr, MATCH_CLMULR, MASK_CLMULR)
++DECLARE_INSN(pack, MATCH_PACK, MASK_PACK)
++DECLARE_INSN(packu, MATCH_PACKU, MASK_PACKU)
++DECLARE_INSN(packh, MATCH_PACKH, MASK_PACKH)
++DECLARE_INSN(packw, MATCH_PACKW, MASK_PACKW)
++DECLARE_INSN(packuw, MATCH_PACKUW, MASK_PACKUW)
++DECLARE_INSN(grev, MATCH_GREV, MASK_GREV)
++DECLARE_INSN(grevi, MATCH_GREVI, MASK_GREVI)
++DECLARE_INSN(grevw, MATCH_GREVW, MASK_GREVW)
++DECLARE_INSN(greviw, MATCH_GREVIW, MASK_GREVIW)
++DECLARE_INSN(gorc, MATCH_GORC, MASK_GORC)
++DECLARE_INSN(gorci, MATCH_GORCI, MASK_GORCI)
++DECLARE_INSN(gorcw, MATCH_GORCW, MASK_GORCW)
++DECLARE_INSN(gorciw, MATCH_GORCIW, MASK_GORCIW)
++DECLARE_INSN(shfl, MATCH_SHFL, MASK_SHFL)
++DECLARE_INSN(shfli, MATCH_SHFLI, MASK_SHFLI)
++DECLARE_INSN(shflw, MATCH_SHFLW, MASK_SHFLW)
++DECLARE_INSN(unshfl, MATCH_UNSHFL, MASK_UNSHFL)
++DECLARE_INSN(unshfli, MATCH_UNSHFLI, MASK_UNSHFLI)
++DECLARE_INSN(unshflw, MATCH_UNSHFLW, MASK_UNSHFLW)
++DECLARE_INSN(xperm_n, MATCH_XPERM_N, MASK_XPERM_N)
++DECLARE_INSN(xperm_b, MATCH_XPERM_B, MASK_XPERM_B)
++DECLARE_INSN(xperm_h, MATCH_XPERM_H, MASK_XPERM_H)
++DECLARE_INSN(xperm_w, MATCH_XPERM_W, MASK_XPERM_W)
++DECLARE_INSN(bset, MATCH_BSET, MASK_BSET)
++DECLARE_INSN(bclr, MATCH_BCLR, MASK_BCLR)
++DECLARE_INSN(binv, MATCH_BINV, MASK_BINV)
++DECLARE_INSN(bext, MATCH_BEXT, MASK_BEXT)
++DECLARE_INSN(bdep, MATCH_BDEP, MASK_BDEP)
++DECLARE_INSN(bseti, MATCH_BSETI, MASK_BSETI)
++DECLARE_INSN(bclri, MATCH_BCLRI, MASK_BCLRI)
++DECLARE_INSN(binvi, MATCH_BINVI, MASK_BINVI)
++DECLARE_INSN(bexti, MATCH_BEXTI, MASK_BEXTI)
++DECLARE_INSN(bsetw, MATCH_BSETW, MASK_BSETW)
++DECLARE_INSN(bclrw, MATCH_BCLRW, MASK_BCLRW)
++DECLARE_INSN(binvw, MATCH_BINVW, MASK_BINVW)
++DECLARE_INSN(bextw, MATCH_BEXTW, MASK_BEXTW)
++DECLARE_INSN(bdepw, MATCH_BDEPW, MASK_BDEPW)
++DECLARE_INSN(bsetiw, MATCH_BSETIW, MASK_BSETIW)
++DECLARE_INSN(bclriw, MATCH_BCLRIW, MASK_BCLRIW)
++DECLARE_INSN(binviw, MATCH_BINVIW, MASK_BINVIW)
++DECLARE_INSN(slo, MATCH_SLO, MASK_SLO)
++DECLARE_INSN(sro, MATCH_SRO, MASK_SRO)
++DECLARE_INSN(sloi, MATCH_SLOI, MASK_SLOI)
++DECLARE_INSN(sroi, MATCH_SROI, MASK_SROI)
++DECLARE_INSN(slow, MATCH_SLOW, MASK_SLOW)
++DECLARE_INSN(srow, MATCH_SROW, MASK_SROW)
++DECLARE_INSN(sloiw, MATCH_SLOIW, MASK_SLOIW)
++DECLARE_INSN(sroiw, MATCH_SROIW, MASK_SROIW)
++DECLARE_INSN(bfp, MATCH_BFP, MASK_BFP)
++DECLARE_INSN(bfpw, MATCH_BFPW, MASK_BFPW)
++DECLARE_INSN(bmator, MATCH_BMATOR, MASK_BMATOR)
++DECLARE_INSN(bmatxor, MATCH_BMATXOR, MASK_BMATXOR)
++DECLARE_INSN(bmatflip, MATCH_BMATFLIP, MASK_BMATFLIP)
++DECLARE_INSN(crc32_b, MATCH_CRC32_B, MASK_CRC32_B)
++DECLARE_INSN(crc32_h, MATCH_CRC32_H, MASK_CRC32_H)
++DECLARE_INSN(crc32_w, MATCH_CRC32_W, MASK_CRC32_W)
++DECLARE_INSN(crc32c_b, MATCH_CRC32C_B, MASK_CRC32C_B)
++DECLARE_INSN(crc32c_h, MATCH_CRC32C_H, MASK_CRC32C_H)
++DECLARE_INSN(crc32c_w, MATCH_CRC32C_W, MASK_CRC32C_W)
++DECLARE_INSN(crc32_d, MATCH_CRC32_D, MASK_CRC32_D)
++DECLARE_INSN(crc32c_d, MATCH_CRC32C_D, MASK_CRC32C_D)
++DECLARE_INSN(cmix, MATCH_CMIX, MASK_CMIX)
++DECLARE_INSN(cmov, MATCH_CMOV, MASK_CMOV)
++DECLARE_INSN(fsl, MATCH_FSL, MASK_FSL)
++DECLARE_INSN(fsr, MATCH_FSR, MASK_FSR)
++DECLARE_INSN(fsri, MATCH_FSRI, MASK_FSRI)
++DECLARE_INSN(fslw, MATCH_FSLW, MASK_FSLW)
++DECLARE_INSN(fsrw, MATCH_FSRW, MASK_FSRW)
++DECLARE_INSN(fsriw, MATCH_FSRIW, MASK_FSRIW)
+ DECLARE_INSN(flw, MATCH_FLW, MASK_FLW)
+ DECLARE_INSN(fld, MATCH_FLD, MASK_FLD)
+ DECLARE_INSN(flq, MATCH_FLQ, MASK_FLQ)
+diff --git a/include/opcode/riscv.h b/include/opcode/riscv.h
+index caaaea5162..87d1aedb40 100644
+--- a/include/opcode/riscv.h
++++ b/include/opcode/riscv.h
+@@ -312,6 +312,21 @@ enum riscv_insn_class
+    INSN_CLASS_ZICSR,
+    INSN_CLASS_ZIFENCEI,
+    INSN_CLASS_ZIHINTPAUSE,
++   INSN_CLASS_ZBA,
++   INSN_CLASS_ZBB,
++   INSN_CLASS_ZBC,
++   INSN_CLASS_ZBP,
++   INSN_CLASS_ZBB_OR_ZBP,
++   INSN_CLASS_ZBS,
++   INSN_CLASS_ZBE,
++   INSN_CLASS_ZBS_OR_ZBE,
++   INSN_CLASS_ZBF,
++   INSN_CLASS_ZBM,
++   INSN_CLASS_ZBP_OR_ZBM,
++   INSN_CLASS_ZBR,
++   INSN_CLASS_ZBT,
++   INSN_CLASS_ZBP_OR_ZBE_OR_ZBF,
++   INSN_CLASS_ZBP_OR_ZBE_OR_ZBF_OR_ZBM,
+   };
+ 
+ /* This structure holds information for a particular instruction.  */
+diff --git a/opcodes/riscv-dis.c b/opcodes/riscv-dis.c
+index c3d9bb8745..a169d013c4 100644
+--- a/opcodes/riscv-dis.c
++++ b/opcodes/riscv-dis.c
+@@ -238,6 +238,10 @@ print_insn_args (const char *d, insn_t l, bfd_vma pc, disassemble_info *info)
+ 	      info->target = EXTRACT_RVC_J_IMM (l) + pc;
+ 	      (*info->print_address_func) (info->target, info);
+ 	      break;
++	    case 'r':
++	      print (info->stream, "%s",
++                     riscv_gpr_names[EXTRACT_OPERAND (RS3, l)]);
++              break;
+ 	    case 'u':
+ 	      print (info->stream, "0x%x",
+ 		     (int)(EXTRACT_RVC_IMM (l) & (RISCV_BIGIMM_REACH-1)));
+diff --git a/opcodes/riscv-opc.c b/opcodes/riscv-opc.c
+index a2ea66a723..d73c980acd 100644
+--- a/opcodes/riscv-opc.c
++++ b/opcodes/riscv-opc.c
+@@ -24,6 +24,11 @@
+ #include "opcode/riscv.h"
+ #include <stdio.h>
+ 
++#define MASK_SHAMT (OP_MASK_SHAMT << OP_SH_SHAMT)
++#define MATCH_SHAMT_REV8_32 (0b11000 << OP_SH_SHAMT)
++#define MATCH_SHAMT_REV8_64 (0b111000 << OP_SH_SHAMT)
++#define MATCH_SHAMT_ORC_B (0b00111 << OP_SH_SHAMT)
++
+ /* Register names used by gas and objdump.  */
+ 
+ const char * const riscv_gpr_names_numeric[NGPR] =
+@@ -786,6 +791,127 @@ const struct riscv_opcode riscv_opcodes[] =
+ {"sfence.vma", 0, INSN_CLASS_I,   "s,t",  MATCH_SFENCE_VMA, MASK_SFENCE_VMA, match_opcode, 0 },
+ {"wfi",        0, INSN_CLASS_I,   "",     MATCH_WFI, MASK_WFI, match_opcode, 0 },
+ 
++
++/* RVB instructions.  */
++{"clz",        0, INSN_CLASS_ZBB,  "d,s",      MATCH_CLZ, MASK_CLZ, match_opcode, 0 },
++{"ctz",        0, INSN_CLASS_ZBB,  "d,s",      MATCH_CTZ, MASK_CTZ, match_opcode, 0 },
++{"cpop",       0, INSN_CLASS_ZBB,  "d,s",      MATCH_CPOP, MASK_CPOP, match_opcode, 0 },
++{"min",        0, INSN_CLASS_ZBB,  "d,s,t",    MATCH_MIN, MASK_MIN, match_opcode, 0 },
++{"max",        0, INSN_CLASS_ZBB,  "d,s,t",    MATCH_MAX, MASK_MAX, match_opcode, 0 },
++{"minu",       0, INSN_CLASS_ZBB,  "d,s,t",    MATCH_MINU, MASK_MINU, match_opcode, 0 },
++{"maxu",       0, INSN_CLASS_ZBB,  "d,s,t",    MATCH_MAXU, MASK_MAXU, match_opcode, 0 },
++{"sext.b",     0, INSN_CLASS_ZBB,  "d,s",      MATCH_SEXT_B, MASK_SEXT_B, match_opcode, 0 },
++{"sext.b",     0, INSN_CLASS_I,    "d,s",      0, (int) M_SEXTB, match_never, INSN_MACRO },
++{"sext.h",     0, INSN_CLASS_ZBB,  "d,s",      MATCH_SEXT_H, MASK_SEXT_H, match_opcode, 0 },
++{"sext.h",     0, INSN_CLASS_I,    "d,s",      0, (int) M_SEXTH, match_never, INSN_MACRO },
++{"zext.h",    32, INSN_CLASS_ZBB,  "d,s",      MATCH_PACK, MASK_PACK | MASK_RS2, match_opcode, 0 },
++{"zext.h",    64, INSN_CLASS_ZBB,  "d,s",      MATCH_PACKW, MASK_PACKW | MASK_RS2, match_opcode, 0 },
++{"zext.h",     0, INSN_CLASS_I,    "d,s",      0, (int) M_ZEXTH, match_never, INSN_MACRO },
++{"andn",       0, INSN_CLASS_ZBB_OR_ZBP,  "d,s,t",    MATCH_ANDN, MASK_ANDN, match_opcode, 0 },
++{"orn",        0, INSN_CLASS_ZBB_OR_ZBP,  "d,s,t",    MATCH_ORN, MASK_ORN, match_opcode, 0 },
++{"xnor",       0, INSN_CLASS_ZBB_OR_ZBP,  "d,s,t",    MATCH_XNOR, MASK_XNOR, match_opcode, 0 },
++{"rol",        0, INSN_CLASS_ZBB_OR_ZBP,  "d,s,t",    MATCH_ROL, MASK_ROL, match_opcode, 0 },
++{"rori",       0, INSN_CLASS_ZBB_OR_ZBP,  "d,s,>",    MATCH_RORI, MASK_RORI, match_opcode, 0 },
++{"ror",        0, INSN_CLASS_ZBB_OR_ZBP,  "d,s,t",    MATCH_ROR, MASK_ROR, match_opcode, 0 },
++{"ror",        0, INSN_CLASS_ZBB_OR_ZBP,  "d,s,>",    MATCH_RORI, MASK_RORI, match_opcode, INSN_ALIAS },
++{"rev8",      32, INSN_CLASS_ZBB,  "d,s",      MATCH_GREVI|MATCH_SHAMT_REV8_32, MASK_GREVI|MASK_SHAMT, match_opcode, 0 },
++{"rev8",      64, INSN_CLASS_ZBB,  "d,s",      MATCH_GREVI|MATCH_SHAMT_REV8_64, MASK_GREVI|MASK_SHAMT, match_opcode, 0 },
++{"orc.b",      0, INSN_CLASS_ZBB,  "d,s",      MATCH_GORCI|MATCH_SHAMT_ORC_B, MASK_GORCI|MASK_SHAMT, match_opcode, 0 },
++{"clzw",      64, INSN_CLASS_ZBB,  "d,s",      MATCH_CLZW, MASK_CLZW, match_opcode, 0 },
++{"ctzw",      64, INSN_CLASS_ZBB,  "d,s",      MATCH_CTZW, MASK_CTZW, match_opcode, 0 },
++{"cpopw",     64, INSN_CLASS_ZBB,  "d,s",      MATCH_CPOPW, MASK_CPOPW, match_opcode, 0 },
++{"rolw",      64, INSN_CLASS_ZBB_OR_ZBP,  "d,s,t",    MATCH_ROLW, MASK_ROLW, match_opcode, 0 },
++{"roriw",     64, INSN_CLASS_ZBB_OR_ZBP,  "d,s,<",    MATCH_RORIW, MASK_RORIW, match_opcode, 0 },
++{"rorw",      64, INSN_CLASS_ZBB_OR_ZBP,  "d,s,t",    MATCH_RORW, MASK_RORW, match_opcode, 0 },
++{"rorw",      64, INSN_CLASS_ZBB_OR_ZBP,  "d,s,<",    MATCH_RORIW, MASK_RORIW, match_opcode, 0 },
++{"sh1add",     0, INSN_CLASS_ZBA,  "d,s,t",    MATCH_SH1ADD, MASK_SH1ADD, match_opcode, 0 },
++{"sh2add",     0, INSN_CLASS_ZBA,  "d,s,t",    MATCH_SH2ADD, MASK_SH2ADD, match_opcode, 0 },
++{"sh3add",     0, INSN_CLASS_ZBA,  "d,s,t",    MATCH_SH3ADD, MASK_SH3ADD, match_opcode, 0 },
++{"sh1add.uw", 64, INSN_CLASS_ZBA,  "d,s,t",    MATCH_SH1ADD_UW, MASK_SH1ADD_UW, match_opcode, 0 },
++{"sh2add.uw", 64, INSN_CLASS_ZBA,  "d,s,t",    MATCH_SH2ADD_UW, MASK_SH2ADD_UW, match_opcode, 0 },
++{"sh3add.uw", 64, INSN_CLASS_ZBA,  "d,s,t",    MATCH_SH3ADD_UW, MASK_SH3ADD_UW, match_opcode, 0 },
++{"zext.w",    64, INSN_CLASS_ZBA,  "d,s",      MATCH_ADD_UW, MASK_ADD_UW|MASK_RS2, match_opcode, INSN_ALIAS },
++{"zext.w",    64, INSN_CLASS_I,    "d,s",      0, (int) M_ZEXTW, match_never, INSN_MACRO },
++{"add.uw",    64, INSN_CLASS_ZBA,  "d,s,t",    MATCH_ADD_UW, MASK_ADD_UW, match_opcode, 0 },
++{"slli.uw",   64, INSN_CLASS_ZBA,  "d,s,>",    MATCH_SLLI_UW, MASK_SLLI_UW, match_opcode, 0 },
++{"clmul",      0, INSN_CLASS_ZBC,  "d,s,t",    MATCH_CLMUL, MASK_CLMUL, match_opcode, 0 },
++{"clmulh",     0, INSN_CLASS_ZBC,  "d,s,t",    MATCH_CLMULH, MASK_CLMULH, match_opcode, 0 },
++{"clmulr",     0, INSN_CLASS_ZBC,  "d,s,t",    MATCH_CLMULR, MASK_CLMULR, match_opcode, 0 },
++
++{"pack",       0, INSN_CLASS_ZBP_OR_ZBE_OR_ZBF_OR_ZBM,  "d,s,t",    MATCH_PACK, MASK_PACK, match_opcode, 0 },
++{"packu",      0, INSN_CLASS_ZBP_OR_ZBM,  "d,s,t",    MATCH_PACKU, MASK_PACKU, match_opcode, 0 },
++{"packh",      0, INSN_CLASS_ZBP_OR_ZBE_OR_ZBF,  "d,s,t",    MATCH_PACKH, MASK_PACKH, match_opcode, 0 },
++{"packw",     64, INSN_CLASS_ZBP_OR_ZBE_OR_ZBF,  "d,s,<",    MATCH_PACKW, MASK_PACKW, match_opcode, 0 },
++{"packuw",    64, INSN_CLASS_ZBP,  "d,s,<",    MATCH_PACKUW, MASK_PACKUW, match_opcode, 0 },
++{"grev",       0, INSN_CLASS_ZBP,  "d,s,t",    MATCH_GREV, MASK_GREV, match_opcode, 0 },
++{"grevi",      0, INSN_CLASS_ZBP,  "d,s,>",    MATCH_GREVI, MASK_GREVI, match_opcode, 0 },
++{"grevw",     64, INSN_CLASS_ZBP,  "d,s,<",    MATCH_GREVW, MASK_GREVW, match_opcode, 0 },
++{"greviw",    64, INSN_CLASS_ZBP,  "d,s,<",    MATCH_GREVIW, MASK_GREVIW, match_opcode, 0 },
++{"gorc",       0, INSN_CLASS_ZBP,  "d,s,t",    MATCH_GORC, MASK_GORC, match_opcode, 0 },
++{"gorci",      0, INSN_CLASS_ZBP,  "d,s,>",    MATCH_GORCI, MASK_GORCI, match_opcode, 0 },
++{"gorcw",     64, INSN_CLASS_ZBP,  "d,s,<",    MATCH_GORCW, MASK_GORCW, match_opcode, 0 },
++{"gorciw",    64, INSN_CLASS_ZBP,  "d,s,<",    MATCH_GORCIW, MASK_GORCIW, match_opcode, 0 },
++{"shfl",       0, INSN_CLASS_ZBP,  "d,s,t",    MATCH_SHFL, MASK_SHFL, match_opcode, 0 },
++{"shfli",      0, INSN_CLASS_ZBP,  "d,s,>",    MATCH_SHFLI, MASK_SHFLI, match_opcode, 0 },
++{"shflw",     64, INSN_CLASS_ZBP,  "d,s,<",    MATCH_SHFLW, MASK_SHFLW, match_opcode, 0 },
++{"unshfl",     0, INSN_CLASS_ZBP,  "d,s,t",    MATCH_UNSHFL, MASK_UNSHFL, match_opcode, 0 },
++{"unshfli",    0, INSN_CLASS_ZBP,  "d,s,>",    MATCH_UNSHFLI, MASK_UNSHFLI, match_opcode, 0 },
++{"unshflw",   64, INSN_CLASS_ZBP,  "d,s,<",    MATCH_UNSHFLW, MASK_UNSHFLW, match_opcode, 0 },
++{"xperm.n",    0, INSN_CLASS_ZBP,  "d,s,t",    MATCH_XPERM_N, MASK_XPERM_N, match_opcode, 0 },
++{"xperm.b",    0, INSN_CLASS_ZBP,  "d,s,t",    MATCH_XPERM_B, MASK_XPERM_B, match_opcode, 0 },
++{"xperm.h",    0, INSN_CLASS_ZBP,  "d,s,t",    MATCH_XPERM_H, MASK_XPERM_H, match_opcode, 0 },
++{"xperm.w",   64, INSN_CLASS_ZBP,  "d,s,<",    MATCH_XPERM_W, MASK_XPERM_W, match_opcode, 0 },
++
++{"bset",       0, INSN_CLASS_ZBS,  "d,s,t",    MATCH_BSET, MASK_BSET, match_opcode, 0 },
++{"bclr",       0, INSN_CLASS_ZBS,  "d,s,t",    MATCH_BCLR, MASK_BCLR, match_opcode, 0 },
++{"binv",       0, INSN_CLASS_ZBS,  "d,s,t",    MATCH_BINV, MASK_BINV, match_opcode, 0 },
++{"bext",       0, INSN_CLASS_ZBS_OR_ZBE,  "d,s,t",    MATCH_BEXT, MASK_BEXT, match_opcode, 0 },
++{"bdep",       0, INSN_CLASS_ZBE,  "d,s,t",    MATCH_BDEP, MASK_BDEP, match_opcode, 0 },
++{"bseti",      0, INSN_CLASS_ZBS,  "d,s,>",    MATCH_BSETI, MASK_BSETI, match_opcode, 0 },
++{"bclri",      0, INSN_CLASS_ZBS,  "d,s,>",    MATCH_BCLRI, MASK_BCLRI, match_opcode, 0 },
++{"binvi",      0, INSN_CLASS_ZBS,  "d,s,>",    MATCH_BINVI, MASK_BINVI, match_opcode, 0 },
++{"bexti",      0, INSN_CLASS_ZBS,  "d,s,>",    MATCH_BEXTI, MASK_BEXTI, match_opcode, 0 },
++{"bsetw",     64, INSN_CLASS_ZBS,  "d,s,t",    MATCH_BSETW, MASK_BSETW, match_opcode, 0 },
++{"bclrw",     64, INSN_CLASS_ZBS,  "d,s,t",    MATCH_BCLRW, MASK_BCLRW, match_opcode, 0 },
++{"binvw",     64, INSN_CLASS_ZBS,  "d,s,t",    MATCH_BINVW, MASK_BINVW, match_opcode, 0 },
++{"bextw",     64, INSN_CLASS_ZBS_OR_ZBE,  "d,s,t",    MATCH_BEXTW, MASK_BEXTW, match_opcode, 0 },
++{"bdepw",     64, INSN_CLASS_ZBE,  "d,s,<",    MATCH_BDEPW, MASK_BDEPW, match_opcode, 0 },
++{"bsetiw",    64, INSN_CLASS_ZBS,  "d,s,<",    MATCH_BSETIW, MASK_BSETIW, match_opcode, 0 },
++{"bclriw",    64, INSN_CLASS_ZBS,  "d,s,<",    MATCH_BCLRIW, MASK_BCLRIW, match_opcode, 0 },
++{"binviw",    64, INSN_CLASS_ZBS,  "d,s,<",    MATCH_BINVIW, MASK_BINVIW, match_opcode, 0 },
++{"slo",        0, INSN_CLASS_ZBS,  "d,s,t",    MATCH_SLO, MASK_SLO, match_opcode, 0 },
++{"sro",        0, INSN_CLASS_ZBS,  "d,s,t",    MATCH_SRO, MASK_SRO, match_opcode, 0 },
++{"sloi",       0, INSN_CLASS_ZBS,  "d,s,>",    MATCH_SLOI, MASK_SLOI, match_opcode, 0 },
++{"sroi",       0, INSN_CLASS_ZBS,  "d,s,>",    MATCH_SROI, MASK_SROI, match_opcode, 0 },
++{"slow",      64, INSN_CLASS_ZBS,  "d,s,<",    MATCH_SLOW, MASK_SLOW, match_opcode, 0 },
++{"srow",      64, INSN_CLASS_ZBS,  "d,s,<",    MATCH_SROW, MASK_SROW, match_opcode, 0 },
++{"sloiw",     64, INSN_CLASS_ZBS,  "d,s,<",    MATCH_SLOIW, MASK_SLOIW, match_opcode, 0 },
++{"sroiw",     64, INSN_CLASS_ZBS,  "d,s,<",    MATCH_SROIW, MASK_SROIW, match_opcode, 0 },
++
++{"bfp",        0, INSN_CLASS_ZBF,  "d,s,t",    MATCH_BFP, MASK_BFP, match_opcode, 0 },
++{"bfpw",      64, INSN_CLASS_ZBF,  "d,s,<",    MATCH_BFPW, MASK_BFPW, match_opcode, 0 },
++
++{"bmator",    64, INSN_CLASS_ZBM,  "d,s,t",    MATCH_BMATOR, MASK_BMATOR, match_opcode, 0 },
++{"bmatxor",   64, INSN_CLASS_ZBM,  "d,s,t",    MATCH_BMATXOR, MASK_BMATXOR, match_opcode, 0 },
++{"bmatflip",  64, INSN_CLASS_ZBM,  "d,s",      MATCH_BMATFLIP, MASK_BMATFLIP, match_opcode, 0 },
++
++{"crc32.b",    0, INSN_CLASS_ZBR,  "d,s",      MATCH_CRC32_B, MASK_CRC32_B, match_opcode, 0 },
++{"crc32.h",    0, INSN_CLASS_ZBR,  "d,s",      MATCH_CRC32_H, MASK_CRC32_H, match_opcode, 0 },
++{"crc32.w",    0, INSN_CLASS_ZBR,  "d,s",      MATCH_CRC32_W, MASK_CRC32_W, match_opcode, 0 },
++{"crc32c.b",   0, INSN_CLASS_ZBR,  "d,s",      MATCH_CRC32C_B, MASK_CRC32C_B, match_opcode, 0 },
++{"crc32c.h",   0, INSN_CLASS_ZBR,  "d,s",      MATCH_CRC32C_H, MASK_CRC32C_H, match_opcode, 0 },
++{"crc32c.w",   0, INSN_CLASS_ZBR,  "d,s",      MATCH_CRC32C_W, MASK_CRC32C_W, match_opcode, 0 },
++{"crc32.d",   64, INSN_CLASS_ZBR,  "d,s",      MATCH_CRC32_D, MASK_CRC32_D, match_opcode, 0 },
++{"crc32c.d",  64, INSN_CLASS_ZBR,  "d,s",      MATCH_CRC32C_D, MASK_CRC32C_D, match_opcode, 0 },
++
++{"cmix",       0, INSN_CLASS_ZBT,  "d,s,t,r",  MATCH_CMIX, MASK_CMIX, match_opcode, 0 },
++{"cmov",       0, INSN_CLASS_ZBT,  "d,s,t,r",  MATCH_CMOV, MASK_CMOV, match_opcode, 0 },
++{"fsl",        0, INSN_CLASS_ZBT,  "d,s,t,r",  MATCH_FSL, MASK_FSL, match_opcode, 0 },
++{"fsr",        0, INSN_CLASS_ZBT,  "d,s,t,r",  MATCH_FSR, MASK_FSR, match_opcode, 0 },
++{"fsri",       0, INSN_CLASS_ZBT,  "d,s,>,r",  MATCH_FSRI, MASK_FSRI, match_opcode, 0 },
++{"fslw",      64, INSN_CLASS_ZBT,  "d,s,<,r",  MATCH_FSLW, MASK_FSLW, match_opcode, 0 },
++{"fsrw",      64, INSN_CLASS_ZBT,  "d,s,<,r",  MATCH_FSRW, MASK_FSRW, match_opcode, 0 },
++{"fsriw",     64, INSN_CLASS_ZBT,  "d,s,<,r",  MATCH_FSRIW, MASK_FSRIW, match_opcode, 0 },
+ /* Terminate the list.  */
+ {0, 0, INSN_CLASS_NONE, 0, 0, 0, 0, 0}
+ };
+@@ -935,6 +1061,19 @@ const struct riscv_ext_version riscv_ext_version_table[] =
+ 
+ {"zihintpause", ISA_SPEC_CLASS_DRAFT, 1, 0},
+ 
++{"b",     ISA_SPEC_CLASS_DRAFT, 0, 93},
++{"zbb",   ISA_SPEC_CLASS_DRAFT, 0, 93},
++{"zba",   ISA_SPEC_CLASS_DRAFT, 0, 93},
++{"zbc",   ISA_SPEC_CLASS_DRAFT, 0, 93},
++{"zbe",   ISA_SPEC_CLASS_DRAFT, 0, 93},
++{"zbf",   ISA_SPEC_CLASS_DRAFT, 0, 93},
++{"zbm",   ISA_SPEC_CLASS_DRAFT, 0, 93},
++{"zbp",   ISA_SPEC_CLASS_DRAFT, 0, 93},
++{"zbr",   ISA_SPEC_CLASS_DRAFT, 0, 93},
++{"zbs",   ISA_SPEC_CLASS_DRAFT, 0, 93},
++{"zbt",   ISA_SPEC_CLASS_DRAFT, 0, 93},
++
++
+ /* Terminate the list.  */
+ {NULL, 0, 0, 0}
+ };
+-- 
+2.33.0
+

+ 4252 - 0
recipes-devtools/binutils/binutils/0003-merge-rvv1.0-branch.patch

@@ -0,0 +1,4252 @@
+From 8c25ceee37b496c1b89ca046d980d4c632450ada Mon Sep 17 00:00:00 2001
+From: "max.ma" <max.ma@starfivetech.com>
+Date: Wed, 2 Jun 2021 17:22:17 -0700
+Subject: [PATCH 03/28] merge rvv1.0 branch
+
+---
+ bfd/elfxx-riscv.c          |   34 +
+ gas/config/tc-riscv.c      |  418 ++++++++
+ gas/read.c                 |    5 +
+ include/opcode/riscv-opc.h | 1970 ++++++++++++++++++++++++++++++++++++
+ include/opcode/riscv.h     |   83 ++
+ opcodes/riscv-dis.c        |   84 ++
+ opcodes/riscv-opc.c        | 1221 +++++++++++++++++++++-
+ 7 files changed, 3811 insertions(+), 4 deletions(-)
+
+diff --git a/bfd/elfxx-riscv.c b/bfd/elfxx-riscv.c
+index 8c8af2386b..f257989b54 100644
+--- a/bfd/elfxx-riscv.c
++++ b/bfd/elfxx-riscv.c
+@@ -1771,6 +1771,40 @@ riscv_parse_add_implicit_subsets (riscv_parse_subset_t *rps)
+ 			      RISCV_UNKNOWN_VERSION,
+ 			      RISCV_UNKNOWN_VERSION, TRUE);
+     }
++
++  if ((riscv_lookup_subset (rps->subset_list, "b", &subset)))
++    {
++      riscv_parse_add_subset (rps, "zba",
++                              RISCV_UNKNOWN_VERSION,
++                              RISCV_UNKNOWN_VERSION, TRUE);
++      riscv_parse_add_subset (rps, "zbb",
++                              RISCV_UNKNOWN_VERSION,
++                              RISCV_UNKNOWN_VERSION, TRUE);
++      riscv_parse_add_subset (rps, "zbc",
++                              RISCV_UNKNOWN_VERSION,
++                              RISCV_UNKNOWN_VERSION, TRUE);
++      riscv_parse_add_subset (rps, "zbe",
++                              RISCV_UNKNOWN_VERSION,
++                              RISCV_UNKNOWN_VERSION, TRUE);
++      riscv_parse_add_subset (rps, "zbf",
++                              RISCV_UNKNOWN_VERSION,
++                              RISCV_UNKNOWN_VERSION, TRUE);
++      riscv_parse_add_subset (rps, "zbm",
++                              RISCV_UNKNOWN_VERSION,
++                              RISCV_UNKNOWN_VERSION, TRUE);
++      riscv_parse_add_subset (rps, "zbp",
++                              RISCV_UNKNOWN_VERSION,
++                              RISCV_UNKNOWN_VERSION, TRUE);
++      riscv_parse_add_subset (rps, "zbr",
++                              RISCV_UNKNOWN_VERSION,
++                              RISCV_UNKNOWN_VERSION, TRUE);
++      riscv_parse_add_subset (rps, "zbs",
++                              RISCV_UNKNOWN_VERSION,
++                              RISCV_UNKNOWN_VERSION, TRUE);
++      riscv_parse_add_subset (rps, "zbt",
++                              RISCV_UNKNOWN_VERSION,
++                              RISCV_UNKNOWN_VERSION, TRUE);
++    }
+ }
+ 
+ /* Function for parsing arch string.
+diff --git a/gas/config/tc-riscv.c b/gas/config/tc-riscv.c
+index 3e76e538c4..405ef3278a 100644
+--- a/gas/config/tc-riscv.c
++++ b/gas/config/tc-riscv.c
+@@ -253,6 +253,16 @@ riscv_multi_subset_supports (enum riscv_insn_class insn_class)
+     case INSN_CLASS_ZIHINTPAUSE:
+       return riscv_subset_supports ("zihintpause");
+ 
++    case INSN_CLASS_V: return riscv_subset_supports ("v");
++    case INSN_CLASS_V_AND_F:
++      return riscv_subset_supports ("v") && riscv_subset_supports ("f");
++    case INSN_CLASS_V_OR_ZVAMO:
++      return (riscv_subset_supports ("a")
++	      && (riscv_subset_supports ("v")
++		  || riscv_subset_supports ("zvamo")));
++    case INSN_CLASS_V_OR_ZVLSSEG:
++      return riscv_subset_supports ("v") || riscv_subset_supports ("zvlsseg");
++
+     case INSN_CLASS_ZBB:
+       return riscv_subset_supports ("zbb");
+     case INSN_CLASS_ZBA:
+@@ -693,6 +703,8 @@ enum reg_class
+ {
+   RCLASS_GPR,
+   RCLASS_FPR,
++  RCLASS_VECR,
++  RCLASS_VECM,
+   RCLASS_MAX,
+ 
+   RCLASS_CSR
+@@ -791,6 +803,12 @@ riscv_csr_address (const char *csr_name,
+       result = riscv_subset_supports ("f");
+       need_check_version = FALSE;
+       break;
++    case CSR_CLASS_V:
++      result = (riscv_subset_supports ("v")
++		|| riscv_subset_supports ("zvamo")
++		|| riscv_subset_supports ("zvlsseg"));
++      need_check_version = FALSE;
++      break;
+     case CSR_CLASS_DEBUG:
+       need_check_version = FALSE;
+       break;
+@@ -868,6 +886,11 @@ reg_lookup_internal (const char *s, enum reg_class class)
+   if (riscv_opts.rve && class == RCLASS_GPR && DECODE_REG_NUM (r) > 15)
+     return -1;
+ 
++  if (class == RCLASS_CSR
++      && riscv_opts.csr_check
++      && !reg_csr_lookup_internal (s))
++    return -1;
++
+   return DECODE_REG_NUM (r);
+ }
+ 
+@@ -1060,6 +1083,33 @@ validate_riscv_insn (const struct riscv_opcode *opc, int length)
+ 	     return FALSE;
+ 	  }
+ 	break;
++
++      case 'V': /* RVV */
++	switch (c = *p++)
++	  {
++	  case 'd':
++	  case 'f': USE_BITS (OP_MASK_VD, OP_SH_VD); break;
++	  case 'e': USE_BITS (OP_MASK_VWD, OP_SH_VWD); break;
++	  case 's': USE_BITS (OP_MASK_VS1, OP_SH_VS1); break;
++	  case 't': USE_BITS (OP_MASK_VS2, OP_SH_VS2); break;
++	  case 'u': USE_BITS (OP_MASK_VS1, OP_SH_VS1);
++		    USE_BITS (OP_MASK_VS2, OP_SH_VS2); break;
++	  case 'v': USE_BITS (OP_MASK_VD, OP_SH_VD);
++		    USE_BITS (OP_MASK_VS1, OP_SH_VS1);
++		    USE_BITS (OP_MASK_VS2, OP_SH_VS2); break;
++	  case '0': break;
++	  case 'b': used_bits |= ENCODE_RVV_VB_IMM (-1U); break;
++	  case 'c': used_bits |= ENCODE_RVV_VC_IMM (-1U); break;
++	  case 'i':
++	  case 'j':
++	  case 'k': USE_BITS (OP_MASK_VIMM, OP_SH_VIMM); break;
++	  case 'm': USE_BITS (OP_MASK_VMASK, OP_SH_VMASK); break;
++	  default:
++	    as_bad (_("internal: bad RISC-V opcode (unknown operand type `V%c'): %s %s"),
++		    c, opc->name, opc->args);
++	  }
++	break;
++
+       default:
+ 	as_bad (_("internal: bad RISC-V opcode "
+ 		  "(unknown operand type `%c'): %s %s"),
+@@ -1138,6 +1188,8 @@ md_begin (void)
+   hash_reg_names (RCLASS_GPR, riscv_gpr_names_abi, NGPR);
+   hash_reg_names (RCLASS_FPR, riscv_fpr_names_numeric, NFPR);
+   hash_reg_names (RCLASS_FPR, riscv_fpr_names_abi, NFPR);
++  hash_reg_names (RCLASS_VECR, riscv_vecr_names_numeric, NVECR);
++  hash_reg_names (RCLASS_VECM, riscv_vecm_names_numeric, NVECM);
+   /* Add "fp" as an alias for "s0".  */
+   hash_reg_name (RCLASS_GPR, "fp", 8);
+ 
+@@ -1301,6 +1353,42 @@ macro_build (expressionS *ep, const char *name, const char *fmt, ...)
+ 	  break;
+ 	case ',':
+ 	  continue;
++
++	case 'V': /* RVV */
++	  {
++	    switch (*fmt++)
++	      {
++	      case 'd':
++		INSERT_OPERAND (VD, insn, va_arg (args, int));
++		continue;
++
++	      case 's':
++		INSERT_OPERAND (VS1, insn, va_arg (args, int));
++		continue;
++
++	      case 't':
++		INSERT_OPERAND (VS2, insn, va_arg (args, int));
++		continue;
++
++	      case 'm':
++		{
++		  int reg = va_arg (args, int);
++		  if (reg == -1)
++		    {
++		      INSERT_OPERAND (VMASK, insn, 1);
++		      continue;
++		    }
++		  else if (reg == 0)
++		    {
++		      INSERT_OPERAND (VMASK, insn, 0);
++		      continue;
++		    }
++		}
++		/* fallthru */
++	      }
++	  }
++	  /* fallthru */
++
+ 	default:
+ 	  as_fatal (_("internal error: invalid macro"));
+ 	}
+@@ -1470,6 +1558,97 @@ load_const (int reg, expressionS *ep)
+     }
+ }
+ 
++/* Expand RISC-V Vector macros into one of more instructions.  */
++
++static void
++vector_macro (struct riscv_cl_insn *ip)
++{
++  int vd = (ip->insn_opcode >> OP_SH_VD) & OP_MASK_VD;
++  int vs1 = (ip->insn_opcode >> OP_SH_VS1) & OP_MASK_VS1;
++  int vs2 = (ip->insn_opcode >> OP_SH_VS2) & OP_MASK_VS2;
++  int vm = (ip->insn_opcode >> OP_SH_VMASK) & OP_MASK_VMASK;
++  int vtemp = (ip->insn_opcode >> OP_SH_VFUNCT6) & OP_MASK_VFUNCT6;
++  int mask = ip->insn_mo->mask;
++
++  switch (mask)
++    {
++    case M_VMSGE:
++      if (vm)
++	{
++	  /* Unmasked.  */
++	  macro_build (NULL, "vmslt.vx", "Vd,Vt,sVm", vd, vs2, vs1, -1);
++	  macro_build (NULL, "vmnand.mm", "Vd,Vt,Vs", vd, vd, vd);
++	  break;
++	}
++      if (vtemp != 0)
++	{
++	  /* Masked.  Have vtemp to avoid overlap constraints.  */
++	  if (vd == vm)
++	    {
++	      macro_build (NULL, "vmslt.vx", "Vd,Vt,s", vtemp, vs2, vs1);
++	      macro_build (NULL, "vmandnot.mm", "Vd,Vt,Vs", vd, vm, vtemp);
++	    }
++	  else
++	    {
++	      /* Preserve the value of vd if not updating by vm.  */
++	      macro_build (NULL, "vmslt.vx", "Vd,Vt,s", vtemp, vs2, vs1);
++	      macro_build (NULL, "vmandnot.mm", "Vd,Vt,Vs", vtemp, vm, vtemp);
++	      macro_build (NULL, "vmandnot.mm", "Vd,Vt,Vs", vd, vd, vm);
++	      macro_build (NULL, "vmor.mm", "Vd,Vt,Vs", vd, vtemp, vd);
++	    }
++	}
++      else if (vd != vm)
++	{
++	  /* Masked.  This may cause the vd overlaps vs2, when LMUL > 1.  */
++	  macro_build (NULL, "vmslt.vx", "Vd,Vt,sVm", vd, vs2, vs1, vm);
++	  macro_build (NULL, "vmxor.mm", "Vd,Vt,Vs", vd, vd, vm);
++	}
++      else
++	as_bad (_("must provide temp if destination overlaps mask"));
++      break;
++
++    case M_VMSGEU:
++      if (vm)
++	{
++	  /* Unmasked.  */
++	  macro_build (NULL, "vmsltu.vx", "Vd,Vt,sVm", vd, vs2, vs1, -1);
++	  macro_build (NULL, "vmnand.mm", "Vd,Vt,Vs", vd, vd, vd);
++	  break;
++	}
++      if (vtemp != 0)
++	{
++	  /* Masked.  Have vtemp to avoid overlap constraints.  */
++	  if (vd == vm)
++	    {
++	      macro_build (NULL, "vmsltu.vx", "Vd,Vt,s", vtemp, vs2, vs1);
++	      macro_build (NULL, "vmandnot.mm", "Vd,Vt,Vs", vd, vm, vtemp);
++	    }
++	  else
++	    {
++	      /* Preserve the value of vd if not updating by vm.  */
++	      macro_build (NULL, "vmsltu.vx", "Vd,Vt,s", vtemp, vs2, vs1);
++	      macro_build (NULL, "vmandnot.mm", "Vd,Vt,Vs", vtemp, vm, vtemp);
++	      macro_build (NULL, "vmandnot.mm", "Vd,Vt,Vs", vd, vd, vm);
++	      macro_build (NULL, "vmor.mm", "Vd,Vt,Vs", vd, vtemp, vd);
++	    }
++	}
++      else if (vd != vm)
++	{
++	  /* Masked.  This may cause the vd overlaps vs2, when LMUL > 1.  */
++	  macro_build (NULL, "vmsltu.vx", "Vd,Vt,sVm", vd, vs2, vs1, vm);
++	  macro_build (NULL, "vmxor.mm", "Vd,Vt,Vs", vd, vd, vm);
++	}
++      else
++	as_bad (_("must provide temp if destination overlaps mask"));
++      break;
++
++    default:
++      as_bad (_("Macro %s not implemented"), ip->insn_mo->name);
++      break;
++    }
++}
++
++
+ /* Zero extend and sign extend byte/half-word/word.  */
+ 
+ static void
+@@ -1565,6 +1744,11 @@ macro (struct riscv_cl_insn *ip, expressionS *imm_expr,
+ 		  BFD_RELOC_RISCV_PCREL_HI20, BFD_RELOC_RISCV_PCREL_LO12_I);
+       break;
+ 
++    case M_FLH:
++      pcrel_load (rd, rs1, imm_expr, "flh",
++		  BFD_RELOC_RISCV_PCREL_HI20, BFD_RELOC_RISCV_PCREL_LO12_I);
++      break;
++
+     case M_FLW:
+       pcrel_load (rd, rs1, imm_expr, "flw",
+ 		  BFD_RELOC_RISCV_PCREL_HI20, BFD_RELOC_RISCV_PCREL_LO12_I);
+@@ -1595,6 +1779,11 @@ macro (struct riscv_cl_insn *ip, expressionS *imm_expr,
+ 		   BFD_RELOC_RISCV_PCREL_HI20, BFD_RELOC_RISCV_PCREL_LO12_S);
+       break;
+ 
++    case M_FSH:
++      pcrel_store (rs2, rs1, imm_expr, "fsh",
++		   BFD_RELOC_RISCV_PCREL_HI20, BFD_RELOC_RISCV_PCREL_LO12_S);
++      break;
++
+     case M_FSW:
+       pcrel_store (rs2, rs1, imm_expr, "fsw",
+ 		   BFD_RELOC_RISCV_PCREL_HI20, BFD_RELOC_RISCV_PCREL_LO12_S);
+@@ -1625,6 +1814,11 @@ macro (struct riscv_cl_insn *ip, expressionS *imm_expr,
+       riscv_ext (rd, rs1, xlen - 16, TRUE);
+       break;
+ 
++    case M_VMSGE:
++    case M_VMSGEU:
++      vector_macro (ip);
++      break;
++
+     default:
+       as_bad (_("Macro %s not implemented"), ip->insn_mo->name);
+       break;
+@@ -1778,6 +1972,66 @@ my_getSmallExpression (expressionS *ep, bfd_reloc_code_real_type *reloc,
+   return reloc_index;
+ }
+ 
++/* Parse string STR as a vsetvli operand.  Store the expression in *EP.
++   On exit, EXPR_END points to the first character after the expression.  */
++
++static void
++my_getVsetvliExpression (expressionS *ep, char *str)
++{
++  unsigned int vsew_value = 0, vlmul_value = 0;
++  unsigned int vta_value = 0, vma_value = 0;
++  bfd_boolean vsew_found = FALSE, vlmul_found = FALSE;
++  bfd_boolean vta_found = FALSE, vma_found = FALSE;
++
++  if (arg_lookup (&str, riscv_vsew, ARRAY_SIZE (riscv_vsew), &vsew_value))
++    {
++      if (*str == ',')
++	++str;
++      if (vsew_found)
++	as_bad (_("multiple vsew constants"));
++      vsew_found = TRUE;
++    }
++  if (arg_lookup (&str, riscv_vlmul, ARRAY_SIZE (riscv_vlmul), &vlmul_value))
++    {
++      if (*str == ',')
++	++str;
++      if (vlmul_found)
++	as_bad (_("multiple vlmul constants"));
++      vlmul_found = TRUE;
++    }
++  if (arg_lookup (&str, riscv_vta, ARRAY_SIZE (riscv_vta), &vta_value))
++    {
++      if (*str == ',')
++	++str;
++      if (vta_found)
++	as_bad (_("multiple vta constants"));
++      vta_found = TRUE;
++    }
++  if (arg_lookup (&str, riscv_vma, ARRAY_SIZE (riscv_vma), &vma_value))
++    {
++      if (*str == ',')
++	++str;
++      if (vma_found)
++	as_bad (_("multiple vma constants"));
++      vma_found = TRUE;
++    }
++
++  if (vsew_found || vlmul_found || vta_found || vma_found)
++    {
++      ep->X_op = O_constant;
++      ep->X_add_number = (vlmul_value << OP_SH_VLMUL)
++			 | (vsew_value << OP_SH_VSEW)
++			 | (vta_value << OP_SH_VTA)
++			 | (vma_value << OP_SH_VMA);
++      expr_end = str;
++    }
++  else
++    {
++      my_getExpression (ep, str);
++      str = expr_end;
++    }
++}
++
+ /* Parse opcode name, could be an mnemonics or number.  */
+ static size_t
+ my_getOpcodeExpression (expressionS *ep, bfd_reloc_code_real_type *reloc,
+@@ -2641,6 +2895,170 @@ riscv_ip (char *str, struct riscv_cl_insn *ip, expressionS *imm_expr,
+ 	      imm_expr->X_op = O_absent;
+ 	      continue;
+ 
++	    case 'V': /* RVV */
++	      switch (*++args)
++		{
++		case 'd': /* VD */
++		  if (!reg_lookup (&s, RCLASS_VECR, &regno))
++		    break;
++		  INSERT_OPERAND (VD, *ip, regno);
++		  continue;
++
++		case 'e': /* AMO VD */
++		  if (reg_lookup (&s, RCLASS_GPR, &regno) && regno == 0)
++		    INSERT_OPERAND (VWD, *ip, 0);
++		  else if (reg_lookup (&s, RCLASS_VECR, &regno))
++		    {
++		      INSERT_OPERAND (VWD, *ip, 1);
++		      INSERT_OPERAND (VD, *ip, regno);
++		    }
++		  else
++		    break;
++		  continue;
++
++		case 'f': /* AMO VS3 */
++		  if (!reg_lookup (&s, RCLASS_VECR, &regno))
++		    break;
++		  if (!EXTRACT_OPERAND (VWD, ip->insn_opcode))
++		    INSERT_OPERAND (VD, *ip, regno);
++		  else
++		    {
++		      /* VS3 must match VD.  */
++		      if (EXTRACT_OPERAND (VD, ip->insn_opcode) != regno)
++			break;
++		    }
++		  continue;
++
++		case 's': /* VS1 */
++		  if (!reg_lookup (&s, RCLASS_VECR, &regno))
++		    break;
++		  INSERT_OPERAND (VS1, *ip, regno);
++		  continue;
++
++		case 't': /* VS2 */
++		  if (!reg_lookup (&s, RCLASS_VECR, &regno))
++		    break;
++		  INSERT_OPERAND (VS2, *ip, regno);
++		  continue;
++
++		case 'u': /* VS1 == VS2 */
++		  if (!reg_lookup (&s, RCLASS_VECR, &regno))
++		    break;
++		  INSERT_OPERAND (VS1, *ip, regno);
++		  INSERT_OPERAND (VS2, *ip, regno);
++		  continue;
++
++		case 'v': /* VD == VS1 == VS2 */
++		  if (!reg_lookup (&s, RCLASS_VECR, &regno))
++		    break;
++		  INSERT_OPERAND (VD, *ip, regno);
++		  INSERT_OPERAND (VS1, *ip, regno);
++		  INSERT_OPERAND (VS2, *ip, regno);
++		  continue;
++
++		/* The `V0` is carry-in register for v[m]adc and v[m]sbc,
++		   and is used to choose vs1/rs1/frs1/imm or vs2 for
++		   v[f]merge.  It use the same encoding as the vector mask
++		   register.  */
++		case '0':
++		  if (reg_lookup (&s, RCLASS_VECR, &regno) && regno == 0)
++		    continue;
++		  break;
++
++		case 'b': /* vtypei for vsetivli */
++		  my_getVsetvliExpression (imm_expr, s);
++		  check_absolute_expr (ip, imm_expr, FALSE);
++		  if (!VALID_RVV_VB_IMM (imm_expr->X_add_number))
++		    as_bad (_("bad value for vsetivli immediate field, "
++			      "value must be 0..1023"));
++		  ip->insn_opcode
++		    |= ENCODE_RVV_VB_IMM (imm_expr->X_add_number);
++		  imm_expr->X_op = O_absent;
++		  s = expr_end;
++		  continue;
++
++		case 'c': /* vtypei for vsetvli */
++		  my_getVsetvliExpression (imm_expr, s);
++		  check_absolute_expr (ip, imm_expr, FALSE);
++		  if (!VALID_RVV_VC_IMM (imm_expr->X_add_number))
++		    as_bad (_("bad value for vsetvli immediate field, "
++			      "value must be 0..2047"));
++		  ip->insn_opcode
++		    |= ENCODE_RVV_VC_IMM (imm_expr->X_add_number);
++		  imm_expr->X_op = O_absent;
++		  s = expr_end;
++		  continue;
++
++		case 'i': /* vector arith signed immediate */
++		  my_getExpression (imm_expr, s);
++		  check_absolute_expr (ip, imm_expr, FALSE);
++		  if (imm_expr->X_add_number > 15
++		      || imm_expr->X_add_number < -16)
++		    as_bad (_("bad value for vector immediate field, "
++			      "value must be -16...15"));
++		  INSERT_OPERAND (VIMM, *ip, imm_expr->X_add_number);
++		  imm_expr->X_op = O_absent;
++		  s = expr_end;
++		  continue;
++
++		case 'j': /* vector arith unsigned immediate */
++		  my_getExpression (imm_expr, s);
++		  check_absolute_expr (ip, imm_expr, FALSE);
++		  if (imm_expr->X_add_number < 0
++		      || imm_expr->X_add_number >= 32)
++		    as_bad (_("bad value for vector immediate field, "
++			      "value must be 0...31"));
++		  INSERT_OPERAND (VIMM, *ip, imm_expr->X_add_number);
++		  imm_expr->X_op = O_absent;
++		  s = expr_end;
++		  continue;
++
++		case 'k': /* vector arith signed immediate, minus 1 */
++		  my_getExpression (imm_expr, s);
++		  check_absolute_expr (ip, imm_expr, FALSE);
++		  if (imm_expr->X_add_number > 16
++		      || imm_expr->X_add_number < -15)
++		    as_bad (_("bad value for vector immediate field, "
++			      "value must be -15...16"));
++		  INSERT_OPERAND (VIMM, *ip, imm_expr->X_add_number - 1);
++		  imm_expr->X_op = O_absent;
++		  s = expr_end;
++		  continue;
++
++		case 'm': /* optional vector mask */
++		  if (*s == '\0')
++		    {
++		      INSERT_OPERAND (VMASK, *ip, 1);
++		      continue;
++		    }
++		  else if (*s == ',' && s++
++			   && reg_lookup (&s, RCLASS_VECM, &regno)
++			   && regno == 0)
++		    {
++		      INSERT_OPERAND (VMASK, *ip, 0);
++		      continue;
++		    }
++		  break;
++
++		  /* The following ones are only used in macros.  */
++		case 'M': /* required vector mask */
++		  if (reg_lookup (&s, RCLASS_VECM, &regno) && regno == 0)
++		    {
++		      INSERT_OPERAND (VMASK, *ip, 0);
++		      continue;
++		    }
++		  break;
++
++		case 'T': /* vector macro temporary register */
++		  if (!reg_lookup (&s, RCLASS_VECR, &regno) || regno == 0)
++		    break;
++		  /* Store it in the FUNCT6 field as we don't have anyplace
++		     else to store it.  */
++		  INSERT_OPERAND (VFUNCT6, *ip, regno);
++		  continue;
++		}
++	      break;
++
+ 	    default:
+ 	      as_fatal (_("internal error: bad argument type %c"), *args);
+ 	    }
+diff --git a/gas/read.c b/gas/read.c
+index be6e3e03d4..2d2acf9592 100644
+--- a/gas/read.c
++++ b/gas/read.c
+@@ -4827,6 +4827,11 @@ hex_float (int float_type, char *bytes)
+ 
+   switch (float_type)
+     {
++    case 'h':
++    case 'H':
++      length = 2;
++      break;
++
+     case 'f':
+     case 'F':
+     case 's':
+diff --git a/include/opcode/riscv-opc.h b/include/opcode/riscv-opc.h
+index 1a9e313fc3..5bb3803d03 100644
+--- a/include/opcode/riscv-opc.h
++++ b/include/opcode/riscv-opc.h
+@@ -323,6 +323,38 @@
+ #define MASK_FCVT_D_S  0xfff0007f
+ #define MATCH_FSQRT_D 0x5a000053
+ #define MASK_FSQRT_D  0xfff0007f
++#define MATCH_FADD_H 0x4000053
++#define MASK_FADD_H  0xfe00007f
++#define MATCH_FSUB_H 0xc000053
++#define MASK_FSUB_H  0xfe00007f
++#define MATCH_FMUL_H 0x14000053
++#define MASK_FMUL_H  0xfe00007f
++#define MATCH_FDIV_H 0x1c000053
++#define MASK_FDIV_H  0xfe00007f
++#define MATCH_FSGNJ_H 0x24000053
++#define MASK_FSGNJ_H  0xfe00707f
++#define MATCH_FSGNJN_H 0x24001053
++#define MASK_FSGNJN_H  0xfe00707f
++#define MATCH_FSGNJX_H 0x24002053
++#define MASK_FSGNJX_H  0xfe00707f
++#define MATCH_FMIN_H 0x2c000053
++#define MASK_FMIN_H  0xfe00707f
++#define MATCH_FMAX_H 0x2c001053
++#define MASK_FMAX_H  0xfe00707f
++#define MATCH_FCVT_S_H 0x40200053
++#define MASK_FCVT_S_H  0xfff0007f
++#define MATCH_FCVT_H_S 0x44000053
++#define MASK_FCVT_H_S  0xfff0007f
++#define MATCH_FCVT_D_H 0x42200053
++#define MASK_FCVT_D_H  0xfff0007f
++#define MATCH_FCVT_H_D 0x44100053
++#define MASK_FCVT_H_D  0xfff0007f
++#define MATCH_FCVT_Q_H 0x46300053
++#define MASK_FCVT_Q_H  0xfff0007f
++#define MATCH_FCVT_H_Q 0x44200053
++#define MASK_FCVT_H_Q  0xfff0007f
++#define MATCH_FSQRT_H 0x5c000053
++#define MASK_FSQRT_H  0xfff0007f
+ #define MATCH_FADD_Q 0x6000053
+ #define MASK_FADD_Q  0xfe00007f
+ #define MATCH_FSUB_Q 0xe000053
+@@ -363,6 +395,12 @@
+ #define MASK_FLT_D  0xfe00707f
+ #define MATCH_FEQ_D 0xa2002053
+ #define MASK_FEQ_D  0xfe00707f
++#define MATCH_FLE_H 0xa4000053
++#define MASK_FLE_H  0xfe00707f
++#define MATCH_FLT_H 0xa4001053
++#define MASK_FLT_H  0xfe00707f
++#define MATCH_FEQ_H 0xa4002053
++#define MASK_FEQ_H  0xfe00707f
+ #define MATCH_FLE_Q 0xa6000053
+ #define MASK_FLE_Q  0xfe00707f
+ #define MATCH_FLT_Q 0xa6001053
+@@ -393,6 +431,18 @@
+ #define MASK_FMV_X_D  0xfff0707f
+ #define MATCH_FCLASS_D 0xe2001053
+ #define MASK_FCLASS_D  0xfff0707f
++#define MATCH_FCVT_W_H 0xc4000053
++#define MASK_FCVT_W_H  0xfff0007f
++#define MATCH_FCVT_WU_H 0xc4100053
++#define MASK_FCVT_WU_H  0xfff0007f
++#define MATCH_FCVT_L_H 0xc4200053
++#define MASK_FCVT_L_H  0xfff0007f
++#define MATCH_FCVT_LU_H 0xc4300053
++#define MASK_FCVT_LU_H  0xfff0007f
++#define MATCH_FMV_X_H 0xe4000053
++#define MASK_FMV_X_H  0xfff0707f
++#define MATCH_FCLASS_H 0xe4001053
++#define MASK_FCLASS_H  0xfff0707f
+ #define MATCH_FCVT_W_Q 0xc6000053
+ #define MASK_FCVT_W_Q  0xfff0007f
+ #define MATCH_FCVT_WU_Q 0xc6100053
+@@ -425,6 +475,16 @@
+ #define MASK_FCVT_D_LU  0xfff0007f
+ #define MATCH_FMV_D_X 0xf2000053
+ #define MASK_FMV_D_X  0xfff0707f
++#define MATCH_FCVT_H_W 0xd4000053
++#define MASK_FCVT_H_W  0xfff0007f
++#define MATCH_FCVT_H_WU 0xd4100053
++#define MASK_FCVT_H_WU  0xfff0007f
++#define MATCH_FCVT_H_L 0xd4200053
++#define MASK_FCVT_H_L  0xfff0007f
++#define MATCH_FCVT_H_LU 0xd4300053
++#define MASK_FCVT_H_LU  0xfff0007f
++#define MATCH_FMV_H_X 0xf4000053
++#define MASK_FMV_H_X  0xfff0707f
+ #define MATCH_FCVT_Q_W 0xd6000053
+ #define MASK_FCVT_Q_W  0xfff0007f
+ #define MATCH_FCVT_Q_WU 0xd6100053
+@@ -625,12 +685,16 @@
+ #define MASK_CLMULH  0xfe00707f
+ #define MATCH_CLMULR 0xa002033
+ #define MASK_CLMULR  0xfe00707f
++#define MATCH_FLH 0x1007
++#define MASK_FLH  0x707f
+ #define MATCH_FLW 0x2007
+ #define MASK_FLW  0x707f
+ #define MATCH_FLD 0x3007
+ #define MASK_FLD  0x707f
+ #define MATCH_FLQ 0x4007
+ #define MASK_FLQ  0x707f
++#define MATCH_FSH 0x1027
++#define MASK_FSH  0x707f
+ #define MATCH_FSW 0x2027
+ #define MASK_FSW  0x707f
+ #define MATCH_FSD 0x3027
+@@ -653,6 +717,14 @@
+ #define MASK_FNMSUB_D  0x600007f
+ #define MATCH_FNMADD_D 0x200004f
+ #define MASK_FNMADD_D  0x600007f
++#define MATCH_FMADD_H 0x4000043
++#define MASK_FMADD_H  0x600007f
++#define MATCH_FMSUB_H 0x4000047
++#define MASK_FMSUB_H  0x600007f
++#define MATCH_FNMSUB_H 0x400004b
++#define MASK_FNMSUB_H  0x600007f
++#define MATCH_FNMADD_H 0x400004f
++#define MASK_FNMADD_H  0x600007f
+ #define MATCH_FMADD_Q 0x6000043
+ #define MASK_FMADD_Q  0x600007f
+ #define MATCH_FMSUB_Q 0x6000047
+@@ -751,6 +823,1854 @@
+ #define MASK_C_LDSP  0xe003
+ #define MATCH_C_SDSP 0xe002
+ #define MASK_C_SDSP  0xe003
++
++/* RVV */
++/* Version 1.0-draft-20210130.  */
++
++/* Temporary configuration-setting encoding info
++
++`-` means zimm
++
++31 30 zimm  RS2   RS1/uimm funct3 RD    opcode
++1  0  00000 xxxxx xxxxx    111    xxxxx 1010111 vsetvl
++1  1  ----- ----- xxxxx    111    xxxxx 1010111 vsetivli
++0  -  ----- ----- xxxxx    111    xxxxx 1010111 vsetvli
++*/
++
++#define MATCH_VSETVL   0x80007057
++#define MASK_VSETVL    0xfe00707f
++#define MATCH_VSETIVLI 0xc0007057
++#define MASK_VSETIVLI  0xc000707f
++#define MATCH_VSETVLI  0x00007057
++#define MASK_VSETVLI   0x8000707f
++
++/* Temporary Load/store encoding info
++
++MOP load
++00 unit-stride		LE<EEW>, VLE<EEW>FF, VL<nf>RE<EEW> (nf = 1, 2, 4, 8)
++01 indexed-unordered	VLUXEI<EEW>
++10 strided		VLSE<EEW>
++11 indexed-ordered	VLOXEI<EEW>
++
++MOP store
++00 unit-stride		VSE<EEW>, VS<nf>R (nf = 1, 2, 4, 8)
++01 indexed-unordered	VSUXEI<EEW>
++10 strided		VSSE<EEW>
++11 indexed-ordered	VSOXEI<EEW>
++
++VM 0 masked
++VM 1 unmasked
++
++LUMOP
++00000 unit-stride load
++01000 unit-stride, whole registers load
++01011 unit-stride, mask load, EEW = 1
++10000 unit-stride first-fault
++xxxxx other encodings reserved, x != 0
++
++SUMOP
++00000 unit-stride store
++01000 unit-stride, whole registers store
++01011 unit-stride, mask store, EEW = 1
++0xxxx other encodings reserved, x != 0
++
++`-` means EEW =
++MEW WIDTH
++x   001   FLH/FSH
++x   010   FLW/FSW
++x   011   FLD/FSW
++x   100   FLQ/FSQ
++0   000   VLxE8/VSxE8, VLxEI8/VSxEI8, VL<nf>RE8, VS<nf>R
++0   101   VLxE16/VSxE16, VLxEI16/VSxEI16, VL<nf>RE16
++0   110   VLxE32/VSxE32, VLxEI32/VSxEI32, VL<nf>RE32
++0   111   VLxE64/VSxE64, VLxEI64/VSxEI64, VL<nf>RE64
++1   000   Reserved (VLxE128/VSxE128, VL<nf>RE128)
++1   101   Reserved (VLxE256/VSxE256, VL<nf>RE256)
++1   110   Reserved (VLxE512/VSxE512, VL<nf>RE512)
++1   111   Reserved (VLxE1024/VSxE1024, VL<nf>RE1024)
++
++NF  MEW MOP VM LUMOP/RS2 RS1   WIDTH VD    opcode
++000 -   00  x  00000     xxxxx ---   xxxxx 0000111 VLE<EEW>
++000 -   00  x  00000     xxxxx ---   xxxxx 0100111 VSE<EEW>
++000 -   00  1  01011     xxxxx ---   xxxxx 0000111 VLE, EEW = 1
++000 -   00  1  01011     xxxxx ---   xxxxx 0100111 VSE, EEW = 1
++000 -   10  x  xxxxx     xxxxx ---   xxxxx 0000111 VLSE<EEW>
++000 -   10  x  xxxxx     xxxxx ---   xxxxx 0100111 VSSE<EEW>
++000 0   11  x  xxxxx     xxxxx ---   xxxxx 0000111 VLOXE<EEW>I
++000 0   11  x  xxxxx     xxxxx ---   xxxxx 0100111 VSOXE<EEW>I
++000 0   01  x  xxxxx     xxxxx ---   xxxxx 0000111 VLUXE<EEW>I
++000 0   01  x  xxxxx     xxxxx ---   xxxxx 0100111 VSUXE<EEW>I
++000 -   00  x  10000     xxxxx ---   xxxxx 0000111 VLE<EEW>FF
++xxx -   00  1  01000     xxxxx ---   xxxxx 0000111 VL<nf>RE<EEW>, nf = 1,2,4,8
++xxx 0   00  1  01000     xxxxx 000   xxxxx 0100111 VS<nf>R, nf = 1,2,4,8
++
++xxx -   00  x  00000     xxxxx ---   xxxxx 0000111 VLSEG<nf>E<EEW>
++xxx -   00  x  00000     xxxxx ---   xxxxx 0100111 VSSEG<nf>E<EEW>
++xxx -   10  x  00000     xxxxx ---   xxxxx 0000111 VLSSEG<nf>E<EEW>
++xxx -   10  x  00000     xxxxx ---   xxxxx 0100111 VSSSEG<nf>E<EEW>
++xxx -   11  x  00000     xxxxx ---   xxxxx 0000111 VLOXSEG<nf>E<EEW>I
++xxx -   11  x  00000     xxxxx ---   xxxxx 0100111 VSOXSEG<nf>E<EEW>I
++xxx -   01  x  00000     xxxxx ---   xxxxx 0000111 VLUXSEG<nf>E<EEW>I
++xxx -   01  x  00000     xxxxx ---   xxxxx 0100111 VSUXSEG<nf>E<EEW>I
++xxx -   00  x  10000     xxxxx ---   xxxxx 0000111 VLSEG<nf>E<EEW>FF
++*/
++
++#define MATCH_VLE1V    0x02b00007
++#define MASK_VLE1V     0xfff0707f
++#define MATCH_VSE1V    0x02b00027
++#define MASK_VSE1V     0xfff0707f
++
++#define MATCH_VLE8V    0x00000007
++#define MASK_VLE8V     0xfdf0707f
++#define MATCH_VLE16V   0x00005007
++#define MASK_VLE16V    0xfdf0707f
++#define MATCH_VLE32V   0x00006007
++#define MASK_VLE32V    0xfdf0707f
++#define MATCH_VLE64V   0x00007007
++#define MASK_VLE64V    0xfdf0707f
++
++#define MATCH_VSE8V    0x00000027
++#define MASK_VSE8V     0xfdf0707f
++#define MATCH_VSE16V   0x00005027
++#define MASK_VSE16V    0xfdf0707f
++#define MATCH_VSE32V   0x00006027
++#define MASK_VSE32V    0xfdf0707f
++#define MATCH_VSE64V   0x00007027
++#define MASK_VSE64V    0xfdf0707f
++
++#define MATCH_VLSE8V    0x08000007
++#define MASK_VLSE8V     0xfc00707f
++#define MATCH_VLSE16V   0x08005007
++#define MASK_VLSE16V    0xfc00707f
++#define MATCH_VLSE32V   0x08006007
++#define MASK_VLSE32V    0xfc00707f
++#define MATCH_VLSE64V   0x08007007
++#define MASK_VLSE64V    0xfc00707f
++
++#define MATCH_VSSE8V    0x08000027
++#define MASK_VSSE8V     0xfc00707f
++#define MATCH_VSSE16V   0x08005027
++#define MASK_VSSE16V    0xfc00707f
++#define MATCH_VSSE32V   0x08006027
++#define MASK_VSSE32V    0xfc00707f
++#define MATCH_VSSE64V   0x08007027
++#define MASK_VSSE64V    0xfc00707f
++
++#define MATCH_VLOXEI8V    0x0c000007
++#define MASK_VLOXEI8V     0xfc00707f
++#define MATCH_VLOXEI16V   0x0c005007
++#define MASK_VLOXEI16V    0xfc00707f
++#define MATCH_VLOXEI32V   0x0c006007
++#define MASK_VLOXEI32V    0xfc00707f
++#define MATCH_VLOXEI64V   0x0c007007
++#define MASK_VLOXEI64V    0xfc00707f
++
++#define MATCH_VSOXEI8V    0x0c000027
++#define MASK_VSOXEI8V     0xfc00707f
++#define MATCH_VSOXEI16V   0x0c005027
++#define MASK_VSOXEI16V    0xfc00707f
++#define MATCH_VSOXEI32V   0x0c006027
++#define MASK_VSOXEI32V    0xfc00707f
++#define MATCH_VSOXEI64V   0x0c007027
++#define MASK_VSOXEI64V    0xfc00707f
++
++#define MATCH_VLUXEI8V    0x04000007
++#define MASK_VLUXEI8V     0xfc00707f
++#define MATCH_VLUXEI16V   0x04005007
++#define MASK_VLUXEI16V    0xfc00707f
++#define MATCH_VLUXEI32V   0x04006007
++#define MASK_VLUXEI32V    0xfc00707f
++#define MATCH_VLUXEI64V   0x04007007
++#define MASK_VLUXEI64V    0xfc00707f
++
++#define MATCH_VSUXEI8V    0x04000027
++#define MASK_VSUXEI8V     0xfc00707f
++#define MATCH_VSUXEI16V   0x04005027
++#define MASK_VSUXEI16V    0xfc00707f
++#define MATCH_VSUXEI32V   0x04006027
++#define MASK_VSUXEI32V    0xfc00707f
++#define MATCH_VSUXEI64V   0x04007027
++#define MASK_VSUXEI64V    0xfc00707f
++
++#define MATCH_VLE8FFV    0x01000007
++#define MASK_VLE8FFV     0xfdf0707f
++#define MATCH_VLE16FFV   0x01005007
++#define MASK_VLE16FFV    0xfdf0707f
++#define MATCH_VLE32FFV   0x01006007
++#define MASK_VLE32FFV    0xfdf0707f
++#define MATCH_VLE64FFV   0x01007007
++#define MASK_VLE64FFV    0xfdf0707f
++
++#define MATCH_VLSEG2E8V  0x20000007
++#define MASK_VLSEG2E8V   0xfdf0707f
++#define MATCH_VSSEG2E8V  0x20000027
++#define MASK_VSSEG2E8V   0xfdf0707f
++#define MATCH_VLSEG3E8V  0x40000007
++#define MASK_VLSEG3E8V   0xfdf0707f
++#define MATCH_VSSEG3E8V  0x40000027
++#define MASK_VSSEG3E8V   0xfdf0707f
++#define MATCH_VLSEG4E8V  0x60000007
++#define MASK_VLSEG4E8V   0xfdf0707f
++#define MATCH_VSSEG4E8V  0x60000027
++#define MASK_VSSEG4E8V   0xfdf0707f
++#define MATCH_VLSEG5E8V  0x80000007
++#define MASK_VLSEG5E8V   0xfdf0707f
++#define MATCH_VSSEG5E8V  0x80000027
++#define MASK_VSSEG5E8V   0xfdf0707f
++#define MATCH_VLSEG6E8V  0xa0000007
++#define MASK_VLSEG6E8V   0xfdf0707f
++#define MATCH_VSSEG6E8V  0xa0000027
++#define MASK_VSSEG6E8V   0xfdf0707f
++#define MATCH_VLSEG7E8V  0xc0000007
++#define MASK_VLSEG7E8V   0xfdf0707f
++#define MATCH_VSSEG7E8V  0xc0000027
++#define MASK_VSSEG7E8V   0xfdf0707f
++#define MATCH_VLSEG8E8V  0xe0000007
++#define MASK_VLSEG8E8V   0xfdf0707f
++#define MATCH_VSSEG8E8V  0xe0000027
++#define MASK_VSSEG8E8V   0xfdf0707f
++
++#define MATCH_VLSEG2E16V  0x20005007
++#define MASK_VLSEG2E16V   0xfdf0707f
++#define MATCH_VSSEG2E16V  0x20005027
++#define MASK_VSSEG2E16V   0xfdf0707f
++#define MATCH_VLSEG3E16V  0x40005007
++#define MASK_VLSEG3E16V   0xfdf0707f
++#define MATCH_VSSEG3E16V  0x40005027
++#define MASK_VSSEG3E16V   0xfdf0707f
++#define MATCH_VLSEG4E16V  0x60005007
++#define MASK_VLSEG4E16V   0xfdf0707f
++#define MATCH_VSSEG4E16V  0x60005027
++#define MASK_VSSEG4E16V   0xfdf0707f
++#define MATCH_VLSEG5E16V  0x80005007
++#define MASK_VLSEG5E16V   0xfdf0707f
++#define MATCH_VSSEG5E16V  0x80005027
++#define MASK_VSSEG5E16V   0xfdf0707f
++#define MATCH_VLSEG6E16V  0xa0005007
++#define MASK_VLSEG6E16V   0xfdf0707f
++#define MATCH_VSSEG6E16V  0xa0005027
++#define MASK_VSSEG6E16V   0xfdf0707f
++#define MATCH_VLSEG7E16V  0xc0005007
++#define MASK_VLSEG7E16V   0xfdf0707f
++#define MATCH_VSSEG7E16V  0xc0005027
++#define MASK_VSSEG7E16V   0xfdf0707f
++#define MATCH_VLSEG8E16V  0xe0005007
++#define MASK_VLSEG8E16V   0xfdf0707f
++#define MATCH_VSSEG8E16V  0xe0005027
++#define MASK_VSSEG8E16V   0xfdf0707f
++
++#define MATCH_VLSEG2E32V  0x20006007
++#define MASK_VLSEG2E32V   0xfdf0707f
++#define MATCH_VSSEG2E32V  0x20006027
++#define MASK_VSSEG2E32V   0xfdf0707f
++#define MATCH_VLSEG3E32V  0x40006007
++#define MASK_VLSEG3E32V   0xfdf0707f
++#define MATCH_VSSEG3E32V  0x40006027
++#define MASK_VSSEG3E32V   0xfdf0707f
++#define MATCH_VLSEG4E32V  0x60006007
++#define MASK_VLSEG4E32V   0xfdf0707f
++#define MATCH_VSSEG4E32V  0x60006027
++#define MASK_VSSEG4E32V   0xfdf0707f
++#define MATCH_VLSEG5E32V  0x80006007
++#define MASK_VLSEG5E32V   0xfdf0707f
++#define MATCH_VSSEG5E32V  0x80006027
++#define MASK_VSSEG5E32V   0xfdf0707f
++#define MATCH_VLSEG6E32V  0xa0006007
++#define MASK_VLSEG6E32V   0xfdf0707f
++#define MATCH_VSSEG6E32V  0xa0006027
++#define MASK_VSSEG6E32V   0xfdf0707f
++#define MATCH_VLSEG7E32V  0xc0006007
++#define MASK_VLSEG7E32V   0xfdf0707f
++#define MATCH_VSSEG7E32V  0xc0006027
++#define MASK_VSSEG7E32V   0xfdf0707f
++#define MATCH_VLSEG8E32V  0xe0006007
++#define MASK_VLSEG8E32V   0xfdf0707f
++#define MATCH_VSSEG8E32V  0xe0006027
++#define MASK_VSSEG8E32V   0xfdf0707f
++
++#define MATCH_VLSEG2E64V  0x20007007
++#define MASK_VLSEG2E64V   0xfdf0707f
++#define MATCH_VSSEG2E64V  0x20007027
++#define MASK_VSSEG2E64V   0xfdf0707f
++#define MATCH_VLSEG3E64V  0x40007007
++#define MASK_VLSEG3E64V   0xfdf0707f
++#define MATCH_VSSEG3E64V  0x40007027
++#define MASK_VSSEG3E64V   0xfdf0707f
++#define MATCH_VLSEG4E64V  0x60007007
++#define MASK_VLSEG4E64V   0xfdf0707f
++#define MATCH_VSSEG4E64V  0x60007027
++#define MASK_VSSEG4E64V   0xfdf0707f
++#define MATCH_VLSEG5E64V  0x80007007
++#define MASK_VLSEG5E64V   0xfdf0707f
++#define MATCH_VSSEG5E64V  0x80007027
++#define MASK_VSSEG5E64V   0xfdf0707f
++#define MATCH_VLSEG6E64V  0xa0007007
++#define MASK_VLSEG6E64V   0xfdf0707f
++#define MATCH_VSSEG6E64V  0xa0007027
++#define MASK_VSSEG6E64V   0xfdf0707f
++#define MATCH_VLSEG7E64V  0xc0007007
++#define MASK_VLSEG7E64V   0xfdf0707f
++#define MATCH_VSSEG7E64V  0xc0007027
++#define MASK_VSSEG7E64V   0xfdf0707f
++#define MATCH_VLSEG8E64V  0xe0007007
++#define MASK_VLSEG8E64V   0xfdf0707f
++#define MATCH_VSSEG8E64V  0xe0007027
++#define MASK_VSSEG8E64V   0xfdf0707f
++
++#define MATCH_VLSSEG2E8V  0x28000007
++#define MASK_VLSSEG2E8V   0xfc00707f
++#define MATCH_VSSSEG2E8V  0x28000027
++#define MASK_VSSSEG2E8V   0xfc00707f
++#define MATCH_VLSSEG3E8V  0x48000007
++#define MASK_VLSSEG3E8V   0xfc00707f
++#define MATCH_VSSSEG3E8V  0x48000027
++#define MASK_VSSSEG3E8V   0xfc00707f
++#define MATCH_VLSSEG4E8V  0x68000007
++#define MASK_VLSSEG4E8V   0xfc00707f
++#define MATCH_VSSSEG4E8V  0x68000027
++#define MASK_VSSSEG4E8V   0xfc00707f
++#define MATCH_VLSSEG5E8V  0x88000007
++#define MASK_VLSSEG5E8V   0xfc00707f
++#define MATCH_VSSSEG5E8V  0x88000027
++#define MASK_VSSSEG5E8V   0xfc00707f
++#define MATCH_VLSSEG6E8V  0xa8000007
++#define MASK_VLSSEG6E8V   0xfc00707f
++#define MATCH_VSSSEG6E8V  0xa8000027
++#define MASK_VSSSEG6E8V   0xfc00707f
++#define MATCH_VLSSEG7E8V  0xc8000007
++#define MASK_VLSSEG7E8V   0xfc00707f
++#define MATCH_VSSSEG7E8V  0xc8000027
++#define MASK_VSSSEG7E8V   0xfc00707f
++#define MATCH_VLSSEG8E8V  0xe8000007
++#define MASK_VLSSEG8E8V   0xfc00707f
++#define MATCH_VSSSEG8E8V  0xe8000027
++#define MASK_VSSSEG8E8V   0xfc00707f
++
++#define MATCH_VLSSEG2E16V  0x28005007
++#define MASK_VLSSEG2E16V   0xfc00707f
++#define MATCH_VSSSEG2E16V  0x28005027
++#define MASK_VSSSEG2E16V   0xfc00707f
++#define MATCH_VLSSEG3E16V  0x48005007
++#define MASK_VLSSEG3E16V   0xfc00707f
++#define MATCH_VSSSEG3E16V  0x48005027
++#define MASK_VSSSEG3E16V   0xfc00707f
++#define MATCH_VLSSEG4E16V  0x68005007
++#define MASK_VLSSEG4E16V   0xfc00707f
++#define MATCH_VSSSEG4E16V  0x68005027
++#define MASK_VSSSEG4E16V   0xfc00707f
++#define MATCH_VLSSEG5E16V  0x88005007
++#define MASK_VLSSEG5E16V   0xfc00707f
++#define MATCH_VSSSEG5E16V  0x88005027
++#define MASK_VSSSEG5E16V   0xfc00707f
++#define MATCH_VLSSEG6E16V  0xa8005007
++#define MASK_VLSSEG6E16V   0xfc00707f
++#define MATCH_VSSSEG6E16V  0xa8005027
++#define MASK_VSSSEG6E16V   0xfc00707f
++#define MATCH_VLSSEG7E16V  0xc8005007
++#define MASK_VLSSEG7E16V   0xfc00707f
++#define MATCH_VSSSEG7E16V  0xc8005027
++#define MASK_VSSSEG7E16V   0xfc00707f
++#define MATCH_VLSSEG8E16V  0xe8005007
++#define MASK_VLSSEG8E16V   0xfc00707f
++#define MATCH_VSSSEG8E16V  0xe8005027
++#define MASK_VSSSEG8E16V   0xfc00707f
++
++#define MATCH_VLSSEG2E32V  0x28006007
++#define MASK_VLSSEG2E32V   0xfc00707f
++#define MATCH_VSSSEG2E32V  0x28006027
++#define MASK_VSSSEG2E32V   0xfc00707f
++#define MATCH_VLSSEG3E32V  0x48006007
++#define MASK_VLSSEG3E32V   0xfc00707f
++#define MATCH_VSSSEG3E32V  0x48006027
++#define MASK_VSSSEG3E32V   0xfc00707f
++#define MATCH_VLSSEG4E32V  0x68006007
++#define MASK_VLSSEG4E32V   0xfc00707f
++#define MATCH_VSSSEG4E32V  0x68006027
++#define MASK_VSSSEG4E32V   0xfc00707f
++#define MATCH_VLSSEG5E32V  0x88006007
++#define MASK_VLSSEG5E32V   0xfc00707f
++#define MATCH_VSSSEG5E32V  0x88006027
++#define MASK_VSSSEG5E32V   0xfc00707f
++#define MATCH_VLSSEG6E32V  0xa8006007
++#define MASK_VLSSEG6E32V   0xfc00707f
++#define MATCH_VSSSEG6E32V  0xa8006027
++#define MASK_VSSSEG6E32V   0xfc00707f
++#define MATCH_VLSSEG7E32V  0xc8006007
++#define MASK_VLSSEG7E32V   0xfc00707f
++#define MATCH_VSSSEG7E32V  0xc8006027
++#define MASK_VSSSEG7E32V   0xfc00707f
++#define MATCH_VLSSEG8E32V  0xe8006007
++#define MASK_VLSSEG8E32V   0xfc00707f
++#define MATCH_VSSSEG8E32V  0xe8006027
++#define MASK_VSSSEG8E32V   0xfc00707f
++
++#define MATCH_VLSSEG2E64V  0x28007007
++#define MASK_VLSSEG2E64V   0xfc00707f
++#define MATCH_VSSSEG2E64V  0x28007027
++#define MASK_VSSSEG2E64V   0xfc00707f
++#define MATCH_VLSSEG3E64V  0x48007007
++#define MASK_VLSSEG3E64V   0xfc00707f
++#define MATCH_VSSSEG3E64V  0x48007027
++#define MASK_VSSSEG3E64V   0xfc00707f
++#define MATCH_VLSSEG4E64V  0x68007007
++#define MASK_VLSSEG4E64V   0xfc00707f
++#define MATCH_VSSSEG4E64V  0x68007027
++#define MASK_VSSSEG4E64V   0xfc00707f
++#define MATCH_VLSSEG5E64V  0x88007007
++#define MASK_VLSSEG5E64V   0xfc00707f
++#define MATCH_VSSSEG5E64V  0x88007027
++#define MASK_VSSSEG5E64V   0xfc00707f
++#define MATCH_VLSSEG6E64V  0xa8007007
++#define MASK_VLSSEG6E64V   0xfc00707f
++#define MATCH_VSSSEG6E64V  0xa8007027
++#define MASK_VSSSEG6E64V   0xfc00707f
++#define MATCH_VLSSEG7E64V  0xc8007007
++#define MASK_VLSSEG7E64V   0xfc00707f
++#define MATCH_VSSSEG7E64V  0xc8007027
++#define MASK_VSSSEG7E64V   0xfc00707f
++#define MATCH_VLSSEG8E64V  0xe8007007
++#define MASK_VLSSEG8E64V   0xfc00707f
++#define MATCH_VSSSEG8E64V  0xe8007027
++#define MASK_VSSSEG8E64V   0xfc00707f
++
++#define MATCH_VLOXSEG2EI8V  0x2c000007
++#define MASK_VLOXSEG2EI8V   0xfc00707f
++#define MATCH_VSOXSEG2EI8V  0x2c000027
++#define MASK_VSOXSEG2EI8V   0xfc00707f
++#define MATCH_VLOXSEG3EI8V  0x4c000007
++#define MASK_VLOXSEG3EI8V   0xfc00707f
++#define MATCH_VSOXSEG3EI8V  0x4c000027
++#define MASK_VSOXSEG3EI8V   0xfc00707f
++#define MATCH_VLOXSEG4EI8V  0x6c000007
++#define MASK_VLOXSEG4EI8V   0xfc00707f
++#define MATCH_VSOXSEG4EI8V  0x6c000027
++#define MASK_VSOXSEG4EI8V   0xfc00707f
++#define MATCH_VLOXSEG5EI8V  0x8c000007
++#define MASK_VLOXSEG5EI8V   0xfc00707f
++#define MATCH_VSOXSEG5EI8V  0x8c000027
++#define MASK_VSOXSEG5EI8V   0xfc00707f
++#define MATCH_VLOXSEG6EI8V  0xac000007
++#define MASK_VLOXSEG6EI8V   0xfc00707f
++#define MATCH_VSOXSEG6EI8V  0xac000027
++#define MASK_VSOXSEG6EI8V   0xfc00707f
++#define MATCH_VLOXSEG7EI8V  0xcc000007
++#define MASK_VLOXSEG7EI8V   0xfc00707f
++#define MATCH_VSOXSEG7EI8V  0xcc000027
++#define MASK_VSOXSEG7EI8V   0xfc00707f
++#define MATCH_VLOXSEG8EI8V  0xec000007
++#define MASK_VLOXSEG8EI8V   0xfc00707f
++#define MATCH_VSOXSEG8EI8V  0xec000027
++#define MASK_VSOXSEG8EI8V   0xfc00707f
++
++#define MATCH_VLUXSEG2EI8V  0x24000007
++#define MASK_VLUXSEG2EI8V   0xfc00707f
++#define MATCH_VSUXSEG2EI8V  0x24000027
++#define MASK_VSUXSEG2EI8V   0xfc00707f
++#define MATCH_VLUXSEG3EI8V  0x44000007
++#define MASK_VLUXSEG3EI8V   0xfc00707f
++#define MATCH_VSUXSEG3EI8V  0x44000027
++#define MASK_VSUXSEG3EI8V   0xfc00707f
++#define MATCH_VLUXSEG4EI8V  0x64000007
++#define MASK_VLUXSEG4EI8V   0xfc00707f
++#define MATCH_VSUXSEG4EI8V  0x64000027
++#define MASK_VSUXSEG4EI8V   0xfc00707f
++#define MATCH_VLUXSEG5EI8V  0x84000007
++#define MASK_VLUXSEG5EI8V   0xfc00707f
++#define MATCH_VSUXSEG5EI8V  0x84000027
++#define MASK_VSUXSEG5EI8V   0xfc00707f
++#define MATCH_VLUXSEG6EI8V  0xa4000007
++#define MASK_VLUXSEG6EI8V   0xfc00707f
++#define MATCH_VSUXSEG6EI8V  0xa4000027
++#define MASK_VSUXSEG6EI8V   0xfc00707f
++#define MATCH_VLUXSEG7EI8V  0xc4000007
++#define MASK_VLUXSEG7EI8V   0xfc00707f
++#define MATCH_VSUXSEG7EI8V  0xc4000027
++#define MASK_VSUXSEG7EI8V   0xfc00707f
++#define MATCH_VLUXSEG8EI8V  0xe4000007
++#define MASK_VLUXSEG8EI8V   0xfc00707f
++#define MATCH_VSUXSEG8EI8V  0xe4000027
++#define MASK_VSUXSEG8EI8V   0xfc00707f
++
++#define MATCH_VLOXSEG2EI16V  0x2c005007
++#define MASK_VLOXSEG2EI16V   0xfc00707f
++#define MATCH_VSOXSEG2EI16V  0x2c005027
++#define MASK_VSOXSEG2EI16V   0xfc00707f
++#define MATCH_VLOXSEG3EI16V  0x4c005007
++#define MASK_VLOXSEG3EI16V   0xfc00707f
++#define MATCH_VSOXSEG3EI16V  0x4c005027
++#define MASK_VSOXSEG3EI16V   0xfc00707f
++#define MATCH_VLOXSEG4EI16V  0x6c005007
++#define MASK_VLOXSEG4EI16V   0xfc00707f
++#define MATCH_VSOXSEG4EI16V  0x6c005027
++#define MASK_VSOXSEG4EI16V   0xfc00707f
++#define MATCH_VLOXSEG5EI16V  0x8c005007
++#define MASK_VLOXSEG5EI16V   0xfc00707f
++#define MATCH_VSOXSEG5EI16V  0x8c005027
++#define MASK_VSOXSEG5EI16V   0xfc00707f
++#define MATCH_VLOXSEG6EI16V  0xac005007
++#define MASK_VLOXSEG6EI16V   0xfc00707f
++#define MATCH_VSOXSEG6EI16V  0xac005027
++#define MASK_VSOXSEG6EI16V   0xfc00707f
++#define MATCH_VLOXSEG7EI16V  0xcc005007
++#define MASK_VLOXSEG7EI16V   0xfc00707f
++#define MATCH_VSOXSEG7EI16V  0xcc005027
++#define MASK_VSOXSEG7EI16V   0xfc00707f
++#define MATCH_VLOXSEG8EI16V  0xec005007
++#define MASK_VLOXSEG8EI16V   0xfc00707f
++#define MATCH_VSOXSEG8EI16V  0xec005027
++#define MASK_VSOXSEG8EI16V   0xfc00707f
++
++#define MATCH_VLUXSEG2EI16V  0x24005007
++#define MASK_VLUXSEG2EI16V   0xfc00707f
++#define MATCH_VSUXSEG2EI16V  0x24005027
++#define MASK_VSUXSEG2EI16V   0xfc00707f
++#define MATCH_VLUXSEG3EI16V  0x44005007
++#define MASK_VLUXSEG3EI16V   0xfc00707f
++#define MATCH_VSUXSEG3EI16V  0x44005027
++#define MASK_VSUXSEG3EI16V   0xfc00707f
++#define MATCH_VLUXSEG4EI16V  0x64005007
++#define MASK_VLUXSEG4EI16V   0xfc00707f
++#define MATCH_VSUXSEG4EI16V  0x64005027
++#define MASK_VSUXSEG4EI16V   0xfc00707f
++#define MATCH_VLUXSEG5EI16V  0x84005007
++#define MASK_VLUXSEG5EI16V   0xfc00707f
++#define MATCH_VSUXSEG5EI16V  0x84005027
++#define MASK_VSUXSEG5EI16V   0xfc00707f
++#define MATCH_VLUXSEG6EI16V  0xa4005007
++#define MASK_VLUXSEG6EI16V   0xfc00707f
++#define MATCH_VSUXSEG6EI16V  0xa4005027
++#define MASK_VSUXSEG6EI16V   0xfc00707f
++#define MATCH_VLUXSEG7EI16V  0xc4005007
++#define MASK_VLUXSEG7EI16V   0xfc00707f
++#define MATCH_VSUXSEG7EI16V  0xc4005027
++#define MASK_VSUXSEG7EI16V   0xfc00707f
++#define MATCH_VLUXSEG8EI16V  0xe4005007
++#define MASK_VLUXSEG8EI16V   0xfc00707f
++#define MATCH_VSUXSEG8EI16V  0xe4005027
++#define MASK_VSUXSEG8EI16V   0xfc00707f
++
++#define MATCH_VLOXSEG2EI32V  0x2c006007
++#define MASK_VLOXSEG2EI32V   0xfc00707f
++#define MATCH_VSOXSEG2EI32V  0x2c006027
++#define MASK_VSOXSEG2EI32V   0xfc00707f
++#define MATCH_VLOXSEG3EI32V  0x4c006007
++#define MASK_VLOXSEG3EI32V   0xfc00707f
++#define MATCH_VSOXSEG3EI32V  0x4c006027
++#define MASK_VSOXSEG3EI32V   0xfc00707f
++#define MATCH_VLOXSEG4EI32V  0x6c006007
++#define MASK_VLOXSEG4EI32V   0xfc00707f
++#define MATCH_VSOXSEG4EI32V  0x6c006027
++#define MASK_VSOXSEG4EI32V   0xfc00707f
++#define MATCH_VLOXSEG5EI32V  0x8c006007
++#define MASK_VLOXSEG5EI32V   0xfc00707f
++#define MATCH_VSOXSEG5EI32V  0x8c006027
++#define MASK_VSOXSEG5EI32V   0xfc00707f
++#define MATCH_VLOXSEG6EI32V  0xac006007
++#define MASK_VLOXSEG6EI32V   0xfc00707f
++#define MATCH_VSOXSEG6EI32V  0xac006027
++#define MASK_VSOXSEG6EI32V   0xfc00707f
++#define MATCH_VLOXSEG7EI32V  0xcc006007
++#define MASK_VLOXSEG7EI32V   0xfc00707f
++#define MATCH_VSOXSEG7EI32V  0xcc006027
++#define MASK_VSOXSEG7EI32V   0xfc00707f
++#define MATCH_VLOXSEG8EI32V  0xec006007
++#define MASK_VLOXSEG8EI32V   0xfc00707f
++#define MATCH_VSOXSEG8EI32V  0xec006027
++#define MASK_VSOXSEG8EI32V   0xfc00707f
++
++#define MATCH_VLUXSEG2EI32V  0x24006007
++#define MASK_VLUXSEG2EI32V   0xfc00707f
++#define MATCH_VSUXSEG2EI32V  0x24006027
++#define MASK_VSUXSEG2EI32V   0xfc00707f
++#define MATCH_VLUXSEG3EI32V  0x44006007
++#define MASK_VLUXSEG3EI32V   0xfc00707f
++#define MATCH_VSUXSEG3EI32V  0x44006027
++#define MASK_VSUXSEG3EI32V   0xfc00707f
++#define MATCH_VLUXSEG4EI32V  0x64006007
++#define MASK_VLUXSEG4EI32V   0xfc00707f
++#define MATCH_VSUXSEG4EI32V  0x64006027
++#define MASK_VSUXSEG4EI32V   0xfc00707f
++#define MATCH_VLUXSEG5EI32V  0x84006007
++#define MASK_VLUXSEG5EI32V   0xfc00707f
++#define MATCH_VSUXSEG5EI32V  0x84006027
++#define MASK_VSUXSEG5EI32V   0xfc00707f
++#define MATCH_VLUXSEG6EI32V  0xa4006007
++#define MASK_VLUXSEG6EI32V   0xfc00707f
++#define MATCH_VSUXSEG6EI32V  0xa4006027
++#define MASK_VSUXSEG6EI32V   0xfc00707f
++#define MATCH_VLUXSEG7EI32V  0xc4006007
++#define MASK_VLUXSEG7EI32V   0xfc00707f
++#define MATCH_VSUXSEG7EI32V  0xc4006027
++#define MASK_VSUXSEG7EI32V   0xfc00707f
++#define MATCH_VLUXSEG8EI32V  0xe4006007
++#define MASK_VLUXSEG8EI32V   0xfc00707f
++#define MATCH_VSUXSEG8EI32V  0xe4006027
++#define MASK_VSUXSEG8EI32V   0xfc00707f
++
++#define MATCH_VLOXSEG2EI64V  0x2c007007
++#define MASK_VLOXSEG2EI64V   0xfc00707f
++#define MATCH_VSOXSEG2EI64V  0x2c007027
++#define MASK_VSOXSEG2EI64V   0xfc00707f
++#define MATCH_VLOXSEG3EI64V  0x4c007007
++#define MASK_VLOXSEG3EI64V   0xfc00707f
++#define MATCH_VSOXSEG3EI64V  0x4c007027
++#define MASK_VSOXSEG3EI64V   0xfc00707f
++#define MATCH_VLOXSEG4EI64V  0x6c007007
++#define MASK_VLOXSEG4EI64V   0xfc00707f
++#define MATCH_VSOXSEG4EI64V  0x6c007027
++#define MASK_VSOXSEG4EI64V   0xfc00707f
++#define MATCH_VLOXSEG5EI64V  0x8c007007
++#define MASK_VLOXSEG5EI64V   0xfc00707f
++#define MATCH_VSOXSEG5EI64V  0x8c007027
++#define MASK_VSOXSEG5EI64V   0xfc00707f
++#define MATCH_VLOXSEG6EI64V  0xac007007
++#define MASK_VLOXSEG6EI64V   0xfc00707f
++#define MATCH_VSOXSEG6EI64V  0xac007027
++#define MASK_VSOXSEG6EI64V   0xfc00707f
++#define MATCH_VLOXSEG7EI64V  0xcc007007
++#define MASK_VLOXSEG7EI64V   0xfc00707f
++#define MATCH_VSOXSEG7EI64V  0xcc007027
++#define MASK_VSOXSEG7EI64V   0xfc00707f
++#define MATCH_VLOXSEG8EI64V  0xec007007
++#define MASK_VLOXSEG8EI64V   0xfc00707f
++#define MATCH_VSOXSEG8EI64V  0xec007027
++#define MASK_VSOXSEG8EI64V   0xfc00707f
++
++#define MATCH_VLUXSEG2EI64V  0x24007007
++#define MASK_VLUXSEG2EI64V   0xfc00707f
++#define MATCH_VSUXSEG2EI64V  0x24007027
++#define MASK_VSUXSEG2EI64V   0xfc00707f
++#define MATCH_VLUXSEG3EI64V  0x44007007
++#define MASK_VLUXSEG3EI64V   0xfc00707f
++#define MATCH_VSUXSEG3EI64V  0x44007027
++#define MASK_VSUXSEG3EI64V   0xfc00707f
++#define MATCH_VLUXSEG4EI64V  0x64007007
++#define MASK_VLUXSEG4EI64V   0xfc00707f
++#define MATCH_VSUXSEG4EI64V  0x64007027
++#define MASK_VSUXSEG4EI64V   0xfc00707f
++#define MATCH_VLUXSEG5EI64V  0x84007007
++#define MASK_VLUXSEG5EI64V   0xfc00707f
++#define MATCH_VSUXSEG5EI64V  0x84007027
++#define MASK_VSUXSEG5EI64V   0xfc00707f
++#define MATCH_VLUXSEG6EI64V  0xa4007007
++#define MASK_VLUXSEG6EI64V   0xfc00707f
++#define MATCH_VSUXSEG6EI64V  0xa4007027
++#define MASK_VSUXSEG6EI64V   0xfc00707f
++#define MATCH_VLUXSEG7EI64V  0xc4007007
++#define MASK_VLUXSEG7EI64V   0xfc00707f
++#define MATCH_VSUXSEG7EI64V  0xc4007027
++#define MASK_VSUXSEG7EI64V   0xfc00707f
++#define MATCH_VLUXSEG8EI64V  0xe4007007
++#define MASK_VLUXSEG8EI64V   0xfc00707f
++#define MATCH_VSUXSEG8EI64V  0xe4007027
++#define MASK_VSUXSEG8EI64V   0xfc00707f
++
++#define MATCH_VLSEG2E8FFV  0x21000007
++#define MASK_VLSEG2E8FFV   0xfdf0707f
++#define MATCH_VLSEG3E8FFV  0x41000007
++#define MASK_VLSEG3E8FFV   0xfdf0707f
++#define MATCH_VLSEG4E8FFV  0x61000007
++#define MASK_VLSEG4E8FFV   0xfdf0707f
++#define MATCH_VLSEG5E8FFV  0x81000007
++#define MASK_VLSEG5E8FFV   0xfdf0707f
++#define MATCH_VLSEG6E8FFV  0xa1000007
++#define MASK_VLSEG6E8FFV   0xfdf0707f
++#define MATCH_VLSEG7E8FFV  0xc1000007
++#define MASK_VLSEG7E8FFV   0xfdf0707f
++#define MATCH_VLSEG8E8FFV  0xe1000007
++#define MASK_VLSEG8E8FFV   0xfdf0707f
++
++#define MATCH_VLSEG2E16FFV  0x21005007
++#define MASK_VLSEG2E16FFV   0xfdf0707f
++#define MATCH_VLSEG3E16FFV  0x41005007
++#define MASK_VLSEG3E16FFV   0xfdf0707f
++#define MATCH_VLSEG4E16FFV  0x61005007
++#define MASK_VLSEG4E16FFV   0xfdf0707f
++#define MATCH_VLSEG5E16FFV  0x81005007
++#define MASK_VLSEG5E16FFV   0xfdf0707f
++#define MATCH_VLSEG6E16FFV  0xa1005007
++#define MASK_VLSEG6E16FFV   0xfdf0707f
++#define MATCH_VLSEG7E16FFV  0xc1005007
++#define MASK_VLSEG7E16FFV   0xfdf0707f
++#define MATCH_VLSEG8E16FFV  0xe1005007
++#define MASK_VLSEG8E16FFV   0xfdf0707f
++
++#define MATCH_VLSEG2E32FFV  0x21006007
++#define MASK_VLSEG2E32FFV   0xfdf0707f
++#define MATCH_VLSEG3E32FFV  0x41006007
++#define MASK_VLSEG3E32FFV   0xfdf0707f
++#define MATCH_VLSEG4E32FFV  0x61006007
++#define MASK_VLSEG4E32FFV   0xfdf0707f
++#define MATCH_VLSEG5E32FFV  0x81006007
++#define MASK_VLSEG5E32FFV   0xfdf0707f
++#define MATCH_VLSEG6E32FFV  0xa1006007
++#define MASK_VLSEG6E32FFV   0xfdf0707f
++#define MATCH_VLSEG7E32FFV  0xc1006007
++#define MASK_VLSEG7E32FFV   0xfdf0707f
++#define MATCH_VLSEG8E32FFV  0xe1006007
++#define MASK_VLSEG8E32FFV   0xfdf0707f
++
++#define MATCH_VLSEG2E64FFV  0x21007007
++#define MASK_VLSEG2E64FFV   0xfdf0707f
++#define MATCH_VLSEG3E64FFV  0x41007007
++#define MASK_VLSEG3E64FFV   0xfdf0707f
++#define MATCH_VLSEG4E64FFV  0x61007007
++#define MASK_VLSEG4E64FFV   0xfdf0707f
++#define MATCH_VLSEG5E64FFV  0x81007007
++#define MASK_VLSEG5E64FFV   0xfdf0707f
++#define MATCH_VLSEG6E64FFV  0xa1007007
++#define MASK_VLSEG6E64FFV   0xfdf0707f
++#define MATCH_VLSEG7E64FFV  0xc1007007
++#define MASK_VLSEG7E64FFV   0xfdf0707f
++#define MATCH_VLSEG8E64FFV  0xe1007007
++#define MASK_VLSEG8E64FFV   0xfdf0707f
++
++#define MATCH_VL1RE8V    0x02800007
++#define MASK_VL1RE8V     0xfff0707f
++#define MATCH_VL1RE16V   0x02805007
++#define MASK_VL1RE16V    0xfff0707f
++#define MATCH_VL1RE32V   0x02806007
++#define MASK_VL1RE32V    0xfff0707f
++#define MATCH_VL1RE64V   0x02807007
++#define MASK_VL1RE64V    0xfff0707f
++
++#define MATCH_VL2RE8V    0x22800007
++#define MASK_VL2RE8V     0xfff0707f
++#define MATCH_VL2RE16V   0x22805007
++#define MASK_VL2RE16V    0xfff0707f
++#define MATCH_VL2RE32V   0x22806007
++#define MASK_VL2RE32V    0xfff0707f
++#define MATCH_VL2RE64V   0x22807007
++#define MASK_VL2RE64V    0xfff0707f
++
++#define MATCH_VL4RE8V    0x62800007
++#define MASK_VL4RE8V     0xfff0707f
++#define MATCH_VL4RE16V   0x62805007
++#define MASK_VL4RE16V    0xfff0707f
++#define MATCH_VL4RE32V   0x62806007
++#define MASK_VL4RE32V    0xfff0707f
++#define MATCH_VL4RE64V   0x62807007
++#define MASK_VL4RE64V    0xfff0707f
++
++#define MATCH_VL8RE8V    0xe2800007
++#define MASK_VL8RE8V     0xfff0707f
++#define MATCH_VL8RE16V   0xe2805007
++#define MASK_VL8RE16V    0xfff0707f
++#define MATCH_VL8RE32V   0xe2806007
++#define MASK_VL8RE32V    0xfff0707f
++#define MATCH_VL8RE64V   0xe2807007
++#define MASK_VL8RE64V    0xfff0707f
++
++#define MATCH_VS1RV  0x02800027
++#define MASK_VS1RV   0xfff0707f
++#define MATCH_VS2RV  0x22800027
++#define MASK_VS2RV   0xfff0707f
++#define MATCH_VS4RV  0x62800027
++#define MASK_VS4RV   0xfff0707f
++#define MATCH_VS8RV  0xe2800027
++#define MASK_VS8RV   0xfff0707f
++
++/* Temporary AMO encoding info
++
++width
++010 AMO*.W
++011 AMO*.D
++100 AMO*.Q
++000 VAMO*EI8.V
++101 VAMO*EI16.V
++110 VAMO*EI32.V
++111 VAMO*EI64.V
++
++amoop
++00001 vamoswap
++00000 vamoadd
++00100 vamoxor
++01100 vamoand
++01000 vamoor
++10000 vamomin
++10100 vamomax
++11000 vamominu
++11100 vamomaxu
++
++   31-27 26 25 24-20 19-15 14-12 11-7    6-0
++   amoop wd vm  vs2   rs1  width vs3/vd  opcode
++   00001 x 1 xxxxx xxxxx 110 xxxxx 0101111
++   0000 1x1x xxxx xxxx x110 xxxx x010 1111
++   1111 1010 0000 0000 0111 0000 0111 1111 */
++
++#define MATCH_VAMOADDEI8V   0x0000002f
++#define MASK_VAMOADDEI8V    0xf800707f
++#define MATCH_VAMOSWAPEI8V  0x0800002f
++#define MASK_VAMOSWAPEI8V   0xf800707f
++#define MATCH_VAMOXOREI8V   0x2000002f
++#define MASK_VAMOXOREI8V    0xf800707f
++#define MATCH_VAMOANDEI8V   0x6000002f
++#define MASK_VAMOANDEI8V    0xf800707f
++#define MATCH_VAMOOREI8V    0x4000002f
++#define MASK_VAMOOREI8V     0xf800707f
++#define MATCH_VAMOMINEI8V   0x8000002f
++#define MASK_VAMOMINEI8V    0xf800707f
++#define MATCH_VAMOMAXEI8V   0xa000002f
++#define MASK_VAMOMAXEI8V    0xf800707f
++#define MATCH_VAMOMINUEI8V  0xc000002f
++#define MASK_VAMOMINUEI8V   0xf800707f
++#define MATCH_VAMOMAXUEI8V  0xe000002f
++#define MASK_VAMOMAXUEI8V   0xf800707f
++
++#define MATCH_VAMOADDEI16V   0x0000502f
++#define MASK_VAMOADDEI16V    0xf800707f
++#define MATCH_VAMOSWAPEI16V  0x0800502f
++#define MASK_VAMOSWAPEI16V   0xf800707f
++#define MATCH_VAMOXOREI16V   0x2000502f
++#define MASK_VAMOXOREI16V    0xf800707f
++#define MATCH_VAMOANDEI16V   0x6000502f
++#define MASK_VAMOANDEI16V    0xf800707f
++#define MATCH_VAMOOREI16V    0x4000502f
++#define MASK_VAMOOREI16V     0xf800707f
++#define MATCH_VAMOMINEI16V   0x8000502f
++#define MASK_VAMOMINEI16V    0xf800707f
++#define MATCH_VAMOMAXEI16V   0xa000502f
++#define MASK_VAMOMAXEI16V    0xf800707f
++#define MATCH_VAMOMINUEI16V  0xc000502f
++#define MASK_VAMOMINUEI16V   0xf800707f
++#define MATCH_VAMOMAXUEI16V  0xe000502f
++#define MASK_VAMOMAXUEI16V   0xf800707f
++
++#define MATCH_VAMOADDEI32V   0x0000602f
++#define MASK_VAMOADDEI32V    0xf800707f
++#define MATCH_VAMOSWAPEI32V  0x0800602f
++#define MASK_VAMOSWAPEI32V   0xf800707f
++#define MATCH_VAMOXOREI32V   0x2000602f
++#define MASK_VAMOXOREI32V    0xf800707f
++#define MATCH_VAMOANDEI32V   0x6000602f
++#define MASK_VAMOANDEI32V    0xf800707f
++#define MATCH_VAMOOREI32V    0x4000602f
++#define MASK_VAMOOREI32V     0xf800707f
++#define MATCH_VAMOMINEI32V   0x8000602f
++#define MASK_VAMOMINEI32V    0xf800707f
++#define MATCH_VAMOMAXEI32V   0xa000602f
++#define MASK_VAMOMAXEI32V    0xf800707f
++#define MATCH_VAMOMINUEI32V  0xc000602f
++#define MASK_VAMOMINUEI32V   0xf800707f
++#define MATCH_VAMOMAXUEI32V  0xe000602f
++#define MASK_VAMOMAXUEI32V   0xf800707f
++
++#define MATCH_VAMOADDEI64V   0x0000702f
++#define MASK_VAMOADDEI64V    0xf800707f
++#define MATCH_VAMOSWAPEI64V  0x0800702f
++#define MASK_VAMOSWAPEI64V   0xf800707f
++#define MATCH_VAMOXOREI64V   0x2000702f
++#define MASK_VAMOXOREI64V    0xf800707f
++#define MATCH_VAMOANDEI64V   0x6000702f
++#define MASK_VAMOANDEI64V    0xf800707f
++#define MATCH_VAMOOREI64V    0x4000702f
++#define MASK_VAMOOREI64V     0xf800707f
++#define MATCH_VAMOMINEI64V   0x8000702f
++#define MASK_VAMOMINEI64V    0xf800707f
++#define MATCH_VAMOMAXEI64V   0xa000702f
++#define MASK_VAMOMAXEI64V    0xf800707f
++#define MATCH_VAMOMINUEI64V  0xc000702f
++#define MASK_VAMOMINUEI64V   0xf800707f
++#define MATCH_VAMOMAXUEI64V  0xe000702f
++#define MASK_VAMOMAXUEI64V   0xf800707f
++
++/* Temporary ALU encoding info
++
++funct3
++000 OPIVV vv
++001 OPFVV vv
++010 OPMVV vv
++011 OPIVI vi  simm[4:0]
++100 OPIVX vx  GPR x-reg rs1
++101 OPFVF vf  FP f-reg rs1
++110 OPMVX vx  GPR x-reg rs1
++111 OPCFG si  GPR x-reg rs1 & rs2/imm
++
++INT OPI
++funct6
++000000 vadd
++000001
++000010 vsub
++000011 vrsub
++000100 vminu
++000101 vmin
++000110 vmaxu
++000111 vmax
++001000
++001001 vand
++001010 vor
++001011 vxor
++001100 vrgather
++001101
++001110 vslideup, vrgatherei16
++001111 vslidedown
++010000 vadc
++010001 vmadc
++010010 vsbc
++010011 vmsbc
++010100
++010101
++010110
++010111 vmerge/vmv
++011000 vmseq
++011001 vmsne
++011010 vmsltu
++011011 vmslt
++011100 vmsleu
++011101 vmsle
++011110 vmsgtu
++011111 vmsgt
++100000 vsaddu
++100001 vsadd
++100010 vssubu
++100011 vssub
++100100
++100101 vsll
++100110
++100111 vmv<nf>r (nf = 1, 2, 4, 8)
++101000 vsrl
++101001 vsra
++101010 vssrl
++101011 vssra
++101100 vnsrl
++101101 vnsra
++101110 vnclipu
++101111 vnclip
++110000 vwredsumu
++110001 vwredsum
++110010
++110011
++110100
++110101
++110110
++110111
++111000 vdotu **
++111001 vdot **
++111010
++111011
++111100 vqmaccu
++111101 vqmacc
++111110 vqmaccus
++111111 vqmaccsu
++
++INT OPM
++funct6
++000000 vredsum
++000001 vredand
++000010 vredor
++000011 vredxor
++000100 vredminu
++000101 vredmin
++000110 vredmaxu
++000111 vredmax
++001000 vaaddu
++001001 vaadd
++001010 vasubu
++001011 vasub
++001100
++001101
++001110 vslide1up
++001111 vslide1down
++010000 VRXUNARY0/VWXUNARY0
++010001
++010010 VXUNARY0
++010011
++010100 VMUNARY0
++010101
++010110
++010111 vcompress
++011000 vmandnot
++011001 vmand
++011010 vmor
++011011 vmxor
++011100 vmornot
++011101 vmnand
++011110 vmnor
++011111 vmxnor
++100000 vdivu
++100001 vdiv
++100010 vremu
++100011 vrem
++100100 vmulhu
++100101 vmul
++100110 vmulhsu
++100111 vmulh
++101000
++101001 vmadd
++101010
++101011 vnmsub
++101100
++101101 vmacc
++101110
++101111 vnmsac
++110000 vwaddu
++110001 vwadd
++110010 vwsubu
++110011 vwsub
++110100 vwaddu.w
++110101 vwadd.w
++110110 vwsubu.w
++110111 vwsub.w
++111000 vwmulu
++111001
++111010 vwmulsu
++111011 vwmul
++111100 vwmaccu
++111101 vwmacc
++111110 vwmaccus
++111111 vwmaccsu
++
++VRXUNARY0
++vs2, funct3=X
++00000 vmv.s.x
++
++VWXUNARY0
++vs1, funct3=V
++00000 vmv.x.s
++10000 vpopc
++10001 vfirst
++
++VXUNARY0
++vs1, funct3=V
++00010 vzext.vf8
++00011 vsext.vf8
++00100 vzext.vf4
++00101 vsext.vf4
++00110 vzext.vf2
++00111 vsext.vf2
++
++VMUNARY0
++rs1
++00001 vmsbf
++00010 vmsof
++00011 vmsif
++10000 viota
++10001 vid
++
++VFLOAT
++funct6
++000000 vfadd
++000001 vfredsum
++000010 vfsub
++000011 vfredosum
++000100 vfmin
++000101 vfredmin
++000110 vfmax
++000111 vfredmax
++001000 vfsgnj
++001001 vfsgnn
++001010 vfsgnx
++001011
++001100
++001101
++001110 vfslide1up
++001111 vfslide1down
++010000 VRFUNARY0/VWFUNARY0
++010001
++010010 VFUNARY0
++010011 VFUNARY1
++010100
++010101
++010110
++010111 vfmerge/vfmv
++011000 vmfeq
++011001 vmfle
++011010
++011011 vmflt
++011100 vmfne
++011101 vmfgt
++011110
++011111 vmfge
++100000 vfdiv
++100001 vfrdiv
++100010
++100011
++100100 vfmul
++100101
++100110
++100111 vfrsub
++101000 vfmadd
++101001 vfnmadd
++101010 vfmsub
++101011 vfnmsub
++101100 vfmacc
++101101 vfnmacc
++101110 vfmsac
++101111 vfnmsac
++110000 vfwadd
++110001 vfwredsum
++110010 vfwsub
++110011 vfwredosum
++110100 vfwadd.w
++110101
++110110 vfwsub.w
++110111
++111000 vfwmul
++111001 vfdot
++111010
++111011
++111100 vfwmacc
++111101 vfwnmacc
++111110 vfwmsac
++111111 vfwnmsac
++
++VRFUNARY0
++vs2, funct3=F
++00000 vfmv.s.f
++
++VWFUNARY0
++vs1, funct3=V
++00000 vfmv.f.s
++
++VFUNARY0
++vs1
++00000 vfcvt.xu.f.v
++00001 vfcvt.x.f.v
++00010 vfcvt.f.xu.v
++00011 vfcvt.f.x.v
++00110 vfcvt.rtz.xu.f.v
++00111 vfcvt.rtz.x.f.v
++
++01000 vfwcvt.xu.f.v
++01001 vfwcvt.x.f.v
++01010 vfwcvt.f.xu.v
++01011 vfwcvt.f.x.v
++01100 vfwcvt.f.f.v
++01110 vfwcvt.rtz.xu.f.v
++01111 vfwcvt.rtz.x.f.v
++
++10000 vfncvt.xu.f.w
++10001 vfncvt.x.f.w
++10010 vfncvt.f.xu.w
++10011 vfncvt.f.x.w
++10100 vfncvt.f.f.w
++10101 vfncvt.rod.f.f.w
++10110 vfncvt.rtz.xu.f.v
++10111 vfncvt.rtz.x.f.v
++
++VFUNARY1
++vs1
++00000 vfsqrt.v
++00100 vfrsqrte7.v
++00101 vfrece7.v
++10000 vfclass.v
++
++31-26 25 24-20   19-15     14-12 11-7 6-0
++funct6 VM  VS2  VS1/RS1/IMM funct3 VD   opcode
++010000 x xxxxx 00000 001 xxxxx 1010111
++0100 00xx xxxx 0000 0001 xxxx x101 0111
++*/
++
++#define MATCH_VADDVV  0x00000057
++#define MASK_VADDVV   0xfc00707f
++#define MATCH_VADDVX  0x00004057
++#define MASK_VADDVX   0xfc00707f
++#define MATCH_VADDVI  0x00003057
++#define MASK_VADDVI   0xfc00707f
++#define MATCH_VSUBVV  0x08000057
++#define MASK_VSUBVV   0xfc00707f
++#define MATCH_VSUBVX  0x08004057
++#define MASK_VSUBVX   0xfc00707f
++#define MATCH_VRSUBVX 0x0c004057
++#define MASK_VRSUBVX  0xfc00707f
++#define MATCH_VRSUBVI 0x0c003057
++#define MASK_VRSUBVI  0xfc00707f
++
++#define MATCH_VWCVTXXV  0xc4006057
++#define MASK_VWCVTXXV   0xfc0ff07f
++#define MATCH_VWCVTUXXV 0xc0006057
++#define MASK_VWCVTUXXV  0xfc0ff07f
++
++#define MATCH_VWADDVV  0xc4002057
++#define MASK_VWADDVV   0xfc00707f
++#define MATCH_VWADDVX  0xc4006057
++#define MASK_VWADDVX   0xfc00707f
++#define MATCH_VWSUBVV  0xcc002057
++#define MASK_VWSUBVV   0xfc00707f
++#define MATCH_VWSUBVX  0xcc006057
++#define MASK_VWSUBVX   0xfc00707f
++#define MATCH_VWADDWV  0xd4002057
++#define MASK_VWADDWV   0xfc00707f
++#define MATCH_VWADDWX  0xd4006057
++#define MASK_VWADDWX   0xfc00707f
++#define MATCH_VWSUBWV  0xdc002057
++#define MASK_VWSUBWV   0xfc00707f
++#define MATCH_VWSUBWX  0xdc006057
++#define MASK_VWSUBWX   0xfc00707f
++#define MATCH_VWADDUVV  0xc0002057
++#define MASK_VWADDUVV   0xfc00707f
++#define MATCH_VWADDUVX  0xc0006057
++#define MASK_VWADDUVX   0xfc00707f
++#define MATCH_VWSUBUVV  0xc8002057
++#define MASK_VWSUBUVV   0xfc00707f
++#define MATCH_VWSUBUVX  0xc8006057
++#define MASK_VWSUBUVX   0xfc00707f
++#define MATCH_VWADDUWV  0xd0002057
++#define MASK_VWADDUWV   0xfc00707f
++#define MATCH_VWADDUWX  0xd0006057
++#define MASK_VWADDUWX   0xfc00707f
++#define MATCH_VWSUBUWV  0xd8002057
++#define MASK_VWSUBUWV   0xfc00707f
++#define MATCH_VWSUBUWX  0xd8006057
++#define MASK_VWSUBUWX   0xfc00707f
++
++#define MATCH_VZEXT_VF8 0x48012057
++#define MASK_VZEXT_VF8  0xfc0ff07f
++#define MATCH_VSEXT_VF8 0x4801a057
++#define MASK_VSEXT_VF8  0xfc0ff07f
++#define MATCH_VZEXT_VF4 0x48022057
++#define MASK_VZEXT_VF4  0xfc0ff07f
++#define MATCH_VSEXT_VF4 0x4802a057
++#define MASK_VSEXT_VF4  0xfc0ff07f
++#define MATCH_VZEXT_VF2 0x48032057
++#define MASK_VZEXT_VF2  0xfc0ff07f
++#define MATCH_VSEXT_VF2 0x4803a057
++#define MASK_VSEXT_VF2  0xfc0ff07f
++
++#define MATCH_VADCVVM  0x40000057
++#define MASK_VADCVVM   0xfe00707f
++#define MATCH_VADCVXM  0x40004057
++#define MASK_VADCVXM   0xfe00707f
++#define MATCH_VADCVIM  0x40003057
++#define MASK_VADCVIM   0xfe00707f
++#define MATCH_VMADCVVM 0x44000057
++#define MASK_VMADCVVM  0xfe00707f
++#define MATCH_VMADCVXM 0x44004057
++#define MASK_VMADCVXM  0xfe00707f
++#define MATCH_VMADCVIM 0x44003057
++#define MASK_VMADCVIM  0xfe00707f
++#define MATCH_VMADCVV  0x46000057
++#define MASK_VMADCVV   0xfe00707f
++#define MATCH_VMADCVX  0x46004057
++#define MASK_VMADCVX   0xfe00707f
++#define MATCH_VMADCVI  0x46003057
++#define MASK_VMADCVI   0xfe00707f
++#define MATCH_VSBCVVM  0x48000057
++#define MASK_VSBCVVM   0xfe00707f
++#define MATCH_VSBCVXM  0x48004057
++#define MASK_VSBCVXM   0xfe00707f
++#define MATCH_VMSBCVVM 0x4c000057
++#define MASK_VMSBCVVM  0xfe00707f
++#define MATCH_VMSBCVXM 0x4c004057
++#define MASK_VMSBCVXM  0xfe00707f
++#define MATCH_VMSBCVV  0x4e000057
++#define MASK_VMSBCVV   0xfe00707f
++#define MATCH_VMSBCVX  0x4e004057
++#define MASK_VMSBCVX   0xfe00707f
++
++#define MATCH_VNOTV   0x2c0fb057
++#define MASK_VNOTV    0xfc0ff07f
++
++#define MATCH_VANDVV  0x24000057
++#define MASK_VANDVV   0xfc00707f
++#define MATCH_VANDVX  0x24004057
++#define MASK_VANDVX   0xfc00707f
++#define MATCH_VANDVI  0x24003057
++#define MASK_VANDVI   0xfc00707f
++#define MATCH_VORVV   0x28000057
++#define MASK_VORVV    0xfc00707f
++#define MATCH_VORVX   0x28004057
++#define MASK_VORVX    0xfc00707f
++#define MATCH_VORVI   0x28003057
++#define MASK_VORVI    0xfc00707f
++#define MATCH_VXORVV  0x2c000057
++#define MASK_VXORVV   0xfc00707f
++#define MATCH_VXORVX  0x2c004057
++#define MASK_VXORVX   0xfc00707f
++#define MATCH_VXORVI  0x2c003057
++#define MASK_VXORVI   0xfc00707f
++
++#define MATCH_VSLLVV 0x94000057
++#define MASK_VSLLVV  0xfc00707f
++#define MATCH_VSLLVX 0x94004057
++#define MASK_VSLLVX  0xfc00707f
++#define MATCH_VSLLVI 0x94003057
++#define MASK_VSLLVI  0xfc00707f
++#define MATCH_VSRLVV 0xa0000057
++#define MASK_VSRLVV  0xfc00707f
++#define MATCH_VSRLVX 0xa0004057
++#define MASK_VSRLVX  0xfc00707f
++#define MATCH_VSRLVI 0xa0003057
++#define MASK_VSRLVI  0xfc00707f
++#define MATCH_VSRAVV 0xa4000057
++#define MASK_VSRAVV  0xfc00707f
++#define MATCH_VSRAVX 0xa4004057
++#define MASK_VSRAVX  0xfc00707f
++#define MATCH_VSRAVI 0xa4003057
++#define MASK_VSRAVI  0xfc00707f
++
++#define MATCH_VNCVTXXW 0xb0004057
++#define MASK_VNCVTXXW  0xfc0ff07f
++
++#define MATCH_VNSRLWV  0xb0000057
++#define MASK_VNSRLWV   0xfc00707f
++#define MATCH_VNSRLWX  0xb0004057
++#define MASK_VNSRLWX   0xfc00707f
++#define MATCH_VNSRLWI  0xb0003057
++#define MASK_VNSRLWI   0xfc00707f
++#define MATCH_VNSRAWV  0xb4000057
++#define MASK_VNSRAWV   0xfc00707f
++#define MATCH_VNSRAWX  0xb4004057
++#define MASK_VNSRAWX   0xfc00707f
++#define MATCH_VNSRAWI  0xb4003057
++#define MASK_VNSRAWI   0xfc00707f
++
++#define MATCH_VMSEQVV  0x60000057
++#define MASK_VMSEQVV   0xfc00707f
++#define MATCH_VMSEQVX  0x60004057
++#define MASK_VMSEQVX   0xfc00707f
++#define MATCH_VMSEQVI  0x60003057
++#define MASK_VMSEQVI   0xfc00707f
++#define MATCH_VMSNEVV  0x64000057
++#define MASK_VMSNEVV   0xfc00707f
++#define MATCH_VMSNEVX  0x64004057
++#define MASK_VMSNEVX   0xfc00707f
++#define MATCH_VMSNEVI  0x64003057
++#define MASK_VMSNEVI   0xfc00707f
++#define MATCH_VMSLTVV  0x6c000057
++#define MASK_VMSLTVV   0xfc00707f
++#define MATCH_VMSLTVX  0x6c004057
++#define MASK_VMSLTVX   0xfc00707f
++#define MATCH_VMSLTUVV 0x68000057
++#define MASK_VMSLTUVV  0xfc00707f
++#define MATCH_VMSLTUVX 0x68004057
++#define MASK_VMSLTUVX  0xfc00707f
++#define MATCH_VMSLEVV  0x74000057
++#define MASK_VMSLEVV   0xfc00707f
++#define MATCH_VMSLEVX  0x74004057
++#define MASK_VMSLEVX   0xfc00707f
++#define MATCH_VMSLEVI  0x74003057
++#define MASK_VMSLEVI   0xfc00707f
++#define MATCH_VMSLEUVV 0x70000057
++#define MASK_VMSLEUVV  0xfc00707f
++#define MATCH_VMSLEUVX 0x70004057
++#define MASK_VMSLEUVX  0xfc00707f
++#define MATCH_VMSLEUVI 0x70003057
++#define MASK_VMSLEUVI  0xfc00707f
++#define MATCH_VMSGTVX  0x7c004057
++#define MASK_VMSGTVX   0xfc00707f
++#define MATCH_VMSGTVI  0x7c003057
++#define MASK_VMSGTVI   0xfc00707f
++#define MATCH_VMSGTUVX 0x78004057
++#define MASK_VMSGTUVX  0xfc00707f
++#define MATCH_VMSGTUVI 0x78003057
++#define MASK_VMSGTUVI  0xfc00707f
++
++#define MATCH_VMINVV  0x14000057
++#define MASK_VMINVV   0xfc00707f
++#define MATCH_VMINVX  0x14004057
++#define MASK_VMINVX   0xfc00707f
++#define MATCH_VMAXVV  0x1c000057
++#define MASK_VMAXVV   0xfc00707f
++#define MATCH_VMAXVX  0x1c004057
++#define MASK_VMAXVX   0xfc00707f
++#define MATCH_VMINUVV 0x10000057
++#define MASK_VMINUVV  0xfc00707f
++#define MATCH_VMINUVX 0x10004057
++#define MASK_VMINUVX  0xfc00707f
++#define MATCH_VMAXUVV 0x18000057
++#define MASK_VMAXUVV  0xfc00707f
++#define MATCH_VMAXUVX 0x18004057
++#define MASK_VMAXUVX  0xfc00707f
++
++#define MATCH_VMULVV    0x94002057
++#define MASK_VMULVV     0xfc00707f
++#define MATCH_VMULVX    0x94006057
++#define MASK_VMULVX     0xfc00707f
++#define MATCH_VMULHVV   0x9c002057
++#define MASK_VMULHVV    0xfc00707f
++#define MATCH_VMULHVX   0x9c006057
++#define MASK_VMULHVX    0xfc00707f
++#define MATCH_VMULHUVV  0x90002057
++#define MASK_VMULHUVV   0xfc00707f
++#define MATCH_VMULHUVX  0x90006057
++#define MASK_VMULHUVX   0xfc00707f
++#define MATCH_VMULHSUVV 0x98002057
++#define MASK_VMULHSUVV  0xfc00707f
++#define MATCH_VMULHSUVX 0x98006057
++#define MASK_VMULHSUVX  0xfc00707f
++
++#define MATCH_VWMULVV   0xec002057
++#define MASK_VWMULVV    0xfc00707f
++#define MATCH_VWMULVX   0xec006057
++#define MASK_VWMULVX    0xfc00707f
++#define MATCH_VWMULUVV  0xe0002057
++#define MASK_VWMULUVV   0xfc00707f
++#define MATCH_VWMULUVX  0xe0006057
++#define MASK_VWMULUVX   0xfc00707f
++#define MATCH_VWMULSUVV 0xe8002057
++#define MASK_VWMULSUVV  0xfc00707f
++#define MATCH_VWMULSUVX 0xe8006057
++#define MASK_VWMULSUVX  0xfc00707f
++
++#define MATCH_VMACCVV  0xb4002057
++#define MASK_VMACCVV   0xfc00707f
++#define MATCH_VMACCVX  0xb4006057
++#define MASK_VMACCVX   0xfc00707f
++#define MATCH_VNMSACVV 0xbc002057
++#define MASK_VNMSACVV  0xfc00707f
++#define MATCH_VNMSACVX 0xbc006057
++#define MASK_VNMSACVX  0xfc00707f
++#define MATCH_VMADDVV  0xa4002057
++#define MASK_VMADDVV   0xfc00707f
++#define MATCH_VMADDVX  0xa4006057
++#define MASK_VMADDVX   0xfc00707f
++#define MATCH_VNMSUBVV 0xac002057
++#define MASK_VNMSUBVV  0xfc00707f
++#define MATCH_VNMSUBVX 0xac006057
++#define MASK_VNMSUBVX  0xfc00707f
++
++#define MATCH_VWMACCUVV  0xf0002057
++#define MASK_VWMACCUVV   0xfc00707f
++#define MATCH_VWMACCUVX  0xf0006057
++#define MASK_VWMACCUVX   0xfc00707f
++#define MATCH_VWMACCVV   0xf4002057
++#define MASK_VWMACCVV    0xfc00707f
++#define MATCH_VWMACCVX   0xf4006057
++#define MASK_VWMACCVX    0xfc00707f
++#define MATCH_VWMACCSUVV 0xfc002057
++#define MASK_VWMACCSUVV  0xfc00707f
++#define MATCH_VWMACCSUVX 0xfc006057
++#define MASK_VWMACCSUVX  0xfc00707f
++#define MATCH_VWMACCUSVX 0xf8006057
++#define MASK_VWMACCUSVX  0xfc00707f
++
++#define MATCH_VQMACCUVV  0xf0000057
++#define MASK_VQMACCUVV   0xfc00707f
++#define MATCH_VQMACCUVX  0xf0004057
++#define MASK_VQMACCUVX   0xfc00707f
++#define MATCH_VQMACCVV   0xf4000057
++#define MASK_VQMACCVV    0xfc00707f
++#define MATCH_VQMACCVX   0xf4004057
++#define MASK_VQMACCVX    0xfc00707f
++#define MATCH_VQMACCSUVV 0xfc000057
++#define MASK_VQMACCSUVV  0xfc00707f
++#define MATCH_VQMACCSUVX 0xfc004057
++#define MASK_VQMACCSUVX  0xfc00707f
++#define MATCH_VQMACCUSVX 0xf8004057
++#define MASK_VQMACCUSVX  0xfc00707f
++
++#define MATCH_VDIVVV  0x84002057
++#define MASK_VDIVVV   0xfc00707f
++#define MATCH_VDIVVX  0x84006057
++#define MASK_VDIVVX   0xfc00707f
++#define MATCH_VDIVUVV 0x80002057
++#define MASK_VDIVUVV  0xfc00707f
++#define MATCH_VDIVUVX 0x80006057
++#define MASK_VDIVUVX  0xfc00707f
++#define MATCH_VREMVV  0x8c002057
++#define MASK_VREMVV   0xfc00707f
++#define MATCH_VREMVX  0x8c006057
++#define MASK_VREMVX   0xfc00707f
++#define MATCH_VREMUVV 0x88002057
++#define MASK_VREMUVV  0xfc00707f
++#define MATCH_VREMUVX 0x88006057
++#define MASK_VREMUVX  0xfc00707f
++
++#define MATCH_VMERGEVVM 0x5c000057
++#define MASK_VMERGEVVM  0xfe00707f
++#define MATCH_VMERGEVXM 0x5c004057
++#define MASK_VMERGEVXM  0xfe00707f
++#define MATCH_VMERGEVIM 0x5c003057
++#define MASK_VMERGEVIM  0xfe00707f
++
++#define MATCH_VMVVV    0x5e000057
++#define MASK_VMVVV     0xfff0707f
++#define MATCH_VMVVX    0x5e004057
++#define MASK_VMVVX     0xfff0707f
++#define MATCH_VMVVI    0x5e003057
++#define MASK_VMVVI     0xfff0707f
++
++#define MATCH_VSADDUVV 0x80000057
++#define MASK_VSADDUVV  0xfc00707f
++#define MATCH_VSADDUVX 0x80004057
++#define MASK_VSADDUVX  0xfc00707f
++#define MATCH_VSADDUVI 0x80003057
++#define MASK_VSADDUVI  0xfc00707f
++#define MATCH_VSADDVV  0x84000057
++#define MASK_VSADDVV   0xfc00707f
++#define MATCH_VSADDVX  0x84004057
++#define MASK_VSADDVX   0xfc00707f
++#define MATCH_VSADDVI  0x84003057
++#define MASK_VSADDVI   0xfc00707f
++#define MATCH_VSSUBUVV 0x88000057
++#define MASK_VSSUBUVV  0xfc00707f
++#define MATCH_VSSUBUVX 0x88004057
++#define MASK_VSSUBUVX  0xfc00707f
++#define MATCH_VSSUBVV  0x8c000057
++#define MASK_VSSUBVV   0xfc00707f
++#define MATCH_VSSUBVX  0x8c004057
++#define MASK_VSSUBVX   0xfc00707f
++
++#define MATCH_VAADDUVV 0x20002057
++#define MASK_VAADDUVV  0xfc00707f
++#define MATCH_VAADDUVX 0x20006057
++#define MASK_VAADDUVX  0xfc00707f
++#define MATCH_VAADDVV  0x24002057
++#define MASK_VAADDVV   0xfc00707f
++#define MATCH_VAADDVX  0x24006057
++#define MASK_VAADDVX   0xfc00707f
++#define MATCH_VASUBUVV 0x28002057
++#define MASK_VASUBUVV  0xfc00707f
++#define MATCH_VASUBUVX 0x28006057
++#define MASK_VASUBUVX  0xfc00707f
++#define MATCH_VASUBVV  0x2c002057
++#define MASK_VASUBVV   0xfc00707f
++#define MATCH_VASUBVX  0x2c006057
++#define MASK_VASUBVX   0xfc00707f
++
++#define MATCH_VSMULVV  0x9c000057
++#define MASK_VSMULVV   0xfc00707f
++#define MATCH_VSMULVX  0x9c004057
++#define MASK_VSMULVX   0xfc00707f
++
++#define MATCH_VSSRLVV   0xa8000057
++#define MASK_VSSRLVV    0xfc00707f
++#define MATCH_VSSRLVX   0xa8004057
++#define MASK_VSSRLVX    0xfc00707f
++#define MATCH_VSSRLVI   0xa8003057
++#define MASK_VSSRLVI    0xfc00707f
++#define MATCH_VSSRAVV   0xac000057
++#define MASK_VSSRAVV    0xfc00707f
++#define MATCH_VSSRAVX   0xac004057
++#define MASK_VSSRAVX    0xfc00707f
++#define MATCH_VSSRAVI   0xac003057
++#define MASK_VSSRAVI    0xfc00707f
++
++#define MATCH_VNCLIPUWV 0xb8000057
++#define MASK_VNCLIPUWV  0xfc00707f
++#define MATCH_VNCLIPUWX 0xb8004057
++#define MASK_VNCLIPUWX  0xfc00707f
++#define MATCH_VNCLIPUWI 0xb8003057
++#define MASK_VNCLIPUWI  0xfc00707f
++#define MATCH_VNCLIPWV  0xbc000057
++#define MASK_VNCLIPWV   0xfc00707f
++#define MATCH_VNCLIPWX  0xbc004057
++#define MASK_VNCLIPWX   0xfc00707f
++#define MATCH_VNCLIPWI  0xbc003057
++#define MASK_VNCLIPWI   0xfc00707f
++
++#define MATCH_VFADDVV  0x00001057
++#define MASK_VFADDVV   0xfc00707f
++#define MATCH_VFADDVF  0x00005057
++#define MASK_VFADDVF   0xfc00707f
++#define MATCH_VFSUBVV  0x08001057
++#define MASK_VFSUBVV   0xfc00707f
++#define MATCH_VFSUBVF  0x08005057
++#define MASK_VFSUBVF   0xfc00707f
++#define MATCH_VFRSUBVF 0x9c005057
++#define MASK_VFRSUBVF  0xfc00707f
++
++#define MATCH_VFWADDVV  0xc0001057
++#define MASK_VFWADDVV   0xfc00707f
++#define MATCH_VFWADDVF  0xc0005057
++#define MASK_VFWADDVF   0xfc00707f
++#define MATCH_VFWSUBVV  0xc8001057
++#define MASK_VFWSUBVV   0xfc00707f
++#define MATCH_VFWSUBVF  0xc8005057
++#define MASK_VFWSUBVF   0xfc00707f
++#define MATCH_VFWADDWV  0xd0001057
++#define MASK_VFWADDWV   0xfc00707f
++#define MATCH_VFWADDWF  0xd0005057
++#define MASK_VFWADDWF   0xfc00707f
++#define MATCH_VFWSUBWV  0xd8001057
++#define MASK_VFWSUBWV   0xfc00707f
++#define MATCH_VFWSUBWF  0xd8005057
++#define MASK_VFWSUBWF   0xfc00707f
++
++#define MATCH_VFMULVV  0x90001057
++#define MASK_VFMULVV   0xfc00707f
++#define MATCH_VFMULVF  0x90005057
++#define MASK_VFMULVF   0xfc00707f
++#define MATCH_VFDIVVV  0x80001057
++#define MASK_VFDIVVV   0xfc00707f
++#define MATCH_VFDIVVF  0x80005057
++#define MASK_VFDIVVF   0xfc00707f
++#define MATCH_VFRDIVVF 0x84005057
++#define MASK_VFRDIVVF  0xfc00707f
++
++#define MATCH_VFWMULVV 0xe0001057
++#define MASK_VFWMULVV  0xfc00707f
++#define MATCH_VFWMULVF 0xe0005057
++#define MASK_VFWMULVF  0xfc00707f
++
++#define MATCH_VFMADDVV  0xa0001057
++#define MASK_VFMADDVV   0xfc00707f
++#define MATCH_VFMADDVF  0xa0005057
++#define MASK_VFMADDVF   0xfc00707f
++#define MATCH_VFNMADDVV 0xa4001057
++#define MASK_VFNMADDVV  0xfc00707f
++#define MATCH_VFNMADDVF 0xa4005057
++#define MASK_VFNMADDVF  0xfc00707f
++#define MATCH_VFMSUBVV  0xa8001057
++#define MASK_VFMSUBVV   0xfc00707f
++#define MATCH_VFMSUBVF  0xa8005057
++#define MASK_VFMSUBVF   0xfc00707f
++#define MATCH_VFNMSUBVV 0xac001057
++#define MASK_VFNMSUBVV  0xfc00707f
++#define MATCH_VFNMSUBVF 0xac005057
++#define MASK_VFNMSUBVF  0xfc00707f
++#define MATCH_VFMACCVV  0xb0001057
++#define MASK_VFMACCVV   0xfc00707f
++#define MATCH_VFMACCVF  0xb0005057
++#define MASK_VFMACCVF   0xfc00707f
++#define MATCH_VFNMACCVV 0xb4001057
++#define MASK_VFNMACCVV  0xfc00707f
++#define MATCH_VFNMACCVF 0xb4005057
++#define MASK_VFNMACCVF  0xfc00707f
++#define MATCH_VFMSACVV  0xb8001057
++#define MASK_VFMSACVV   0xfc00707f
++#define MATCH_VFMSACVF  0xb8005057
++#define MASK_VFMSACVF   0xfc00707f
++#define MATCH_VFNMSACVV 0xbc001057
++#define MASK_VFNMSACVV  0xfc00707f
++#define MATCH_VFNMSACVF 0xbc005057
++#define MASK_VFNMSACVF  0xfc00707f
++
++#define MATCH_VFWMACCVV  0xf0001057
++#define MASK_VFWMACCVV   0xfc00707f
++#define MATCH_VFWMACCVF  0xf0005057
++#define MASK_VFWMACCVF   0xfc00707f
++#define MATCH_VFWNMACCVV 0xf4001057
++#define MASK_VFWNMACCVV  0xfc00707f
++#define MATCH_VFWNMACCVF 0xf4005057
++#define MASK_VFWNMACCVF  0xfc00707f
++#define MATCH_VFWMSACVV  0xf8001057
++#define MASK_VFWMSACVV   0xfc00707f
++#define MATCH_VFWMSACVF  0xf8005057
++#define MASK_VFWMSACVF   0xfc00707f
++#define MATCH_VFWNMSACVV 0xfc001057
++#define MASK_VFWNMSACVV  0xfc00707f
++#define MATCH_VFWNMSACVF 0xfc005057
++#define MASK_VFWNMSACVF  0xfc00707f
++
++#define MATCH_VFSQRTV    0x4c001057
++#define MASK_VFSQRTV     0xfc0ff07f
++#define MATCH_VFRSQRT7V  0x4c021057
++#define MASK_VFRSQRT7V   0xfc0ff07f
++#define MATCH_VFREC7V    0x4c029057
++#define MASK_VFREC7V     0xfc0ff07f
++#define MATCH_VFCLASSV   0x4c081057
++#define MASK_VFCLASSV    0xfc0ff07f
++
++#define MATCH_VFMINVV  0x10001057
++#define MASK_VFMINVV   0xfc00707f
++#define MATCH_VFMINVF  0x10005057
++#define MASK_VFMINVF   0xfc00707f
++#define MATCH_VFMAXVV  0x18001057
++#define MASK_VFMAXVV   0xfc00707f
++#define MATCH_VFMAXVF  0x18005057
++#define MASK_VFMAXVF   0xfc00707f
++
++#define MATCH_VFSGNJVV  0x20001057
++#define MASK_VFSGNJVV   0xfc00707f
++#define MATCH_VFSGNJVF  0x20005057
++#define MASK_VFSGNJVF   0xfc00707f
++#define MATCH_VFSGNJNVV 0x24001057
++#define MASK_VFSGNJNVV  0xfc00707f
++#define MATCH_VFSGNJNVF 0x24005057
++#define MASK_VFSGNJNVF  0xfc00707f
++#define MATCH_VFSGNJXVV 0x28001057
++#define MASK_VFSGNJXVV  0xfc00707f
++#define MATCH_VFSGNJXVF 0x28005057
++#define MASK_VFSGNJXVF  0xfc00707f
++
++#define MATCH_VMFEQVV   0x60001057
++#define MASK_VMFEQVV    0xfc00707f
++#define MATCH_VMFEQVF   0x60005057
++#define MASK_VMFEQVF    0xfc00707f
++#define MATCH_VMFNEVV   0x70001057
++#define MASK_VMFNEVV    0xfc00707f
++#define MATCH_VMFNEVF   0x70005057
++#define MASK_VMFNEVF    0xfc00707f
++#define MATCH_VMFLTVV   0x6c001057
++#define MASK_VMFLTVV    0xfc00707f
++#define MATCH_VMFLTVF   0x6c005057
++#define MASK_VMFLTVF    0xfc00707f
++#define MATCH_VMFLEVV  0x64001057
++#define MASK_VMFLEVV   0xfc00707f
++#define MATCH_VMFLEVF  0x64005057
++#define MASK_VMFLEVF   0xfc00707f
++#define MATCH_VMFGTVF   0x74005057
++#define MASK_VMFGTVF    0xfc00707f
++#define MATCH_VMFGEVF  0x7c005057
++#define MASK_VMFGEVF   0xfc00707f
++
++#define MATCH_VFMERGEVFM 0x5c005057
++#define MASK_VFMERGEVFM  0xfe00707f
++#define MATCH_VFMVVF     0x5e005057
++#define MASK_VFMVVF      0xfff0707f
++
++#define MATCH_VFCVTXUFV 0x48001057
++#define MASK_VFCVTXUFV  0xfc0ff07f
++#define MATCH_VFCVTXFV 0x48009057
++#define MASK_VFCVTXFV  0xfc0ff07f
++#define MATCH_VFCVTFXUV 0x48011057
++#define MASK_VFCVTFXUV  0xfc0ff07f
++#define MATCH_VFCVTFXV 0x48019057
++#define MASK_VFCVTFXV  0xfc0ff07f
++#define MATCH_VFCVTRTZXUFV 0x48031057
++#define MASK_VFCVTRTZXUFV  0xfc0ff07f
++#define MATCH_VFCVTRTZXFV 0x48039057
++#define MASK_VFCVTRTZXFV  0xfc0ff07f
++#define MATCH_VFWCVTXUFV 0x48041057
++#define MASK_VFWCVTXUFV  0xfc0ff07f
++#define MATCH_VFWCVTXFV 0x48049057
++#define MASK_VFWCVTXFV  0xfc0ff07f
++#define MATCH_VFWCVTFXUV 0x48051057
++#define MASK_VFWCVTFXUV  0xfc0ff07f
++#define MATCH_VFWCVTFXV 0x48059057
++#define MASK_VFWCVTFXV  0xfc0ff07f
++#define MATCH_VFWCVTFFV 0x48061057
++#define MASK_VFWCVTFFV  0xfc0ff07f
++#define MATCH_VFWCVTRTZXUFV 0x48071057
++#define MASK_VFWCVTRTZXUFV  0xfc0ff07f
++#define MATCH_VFWCVTRTZXFV 0x48079057
++#define MASK_VFWCVTRTZXFV  0xfc0ff07f
++#define MATCH_VFNCVTXUFW 0x48081057
++#define MASK_VFNCVTXUFW  0xfc0ff07f
++#define MATCH_VFNCVTXFW 0x48089057
++#define MASK_VFNCVTXFW  0xfc0ff07f
++#define MATCH_VFNCVTFXUW 0x48091057
++#define MASK_VFNCVTFXUW  0xfc0ff07f
++#define MATCH_VFNCVTFXW 0x48099057
++#define MASK_VFNCVTFXW  0xfc0ff07f
++#define MATCH_VFNCVTFFW 0x480a1057
++#define MASK_VFNCVTFFW  0xfc0ff07f
++#define MATCH_VFNCVTRODFFW 0x480a9057
++#define MASK_VFNCVTRODFFW  0xfc0ff07f
++#define MATCH_VFNCVTRTZXUFW 0x480b1057
++#define MASK_VFNCVTRTZXUFW  0xfc0ff07f
++#define MATCH_VFNCVTRTZXFW 0x480b9057
++#define MASK_VFNCVTRTZXFW  0xfc0ff07f
++
++#define MATCH_VREDSUMVS  0x00002057
++#define MASK_VREDSUMVS   0xfc00707f
++#define MATCH_VREDMAXVS  0x1c002057
++#define MASK_VREDMAXVS   0xfc00707f
++#define MATCH_VREDMAXUVS 0x18002057
++#define MASK_VREDMAXUVS  0xfc00707f
++#define MATCH_VREDMINVS  0x14002057
++#define MASK_VREDMINVS   0xfc00707f
++#define MATCH_VREDMINUVS 0x10002057
++#define MASK_VREDMINUVS  0xfc00707f
++#define MATCH_VREDANDVS  0x04002057
++#define MASK_VREDANDVS   0xfc00707f
++#define MATCH_VREDORVS   0x08002057
++#define MASK_VREDORVS    0xfc00707f
++#define MATCH_VREDXORVS  0x0c002057
++#define MASK_VREDXORVS   0xfc00707f
++
++#define MATCH_VWREDSUMUVS 0xc0000057
++#define MASK_VWREDSUMUVS  0xfc00707f
++#define MATCH_VWREDSUMVS  0xc4000057
++#define MASK_VWREDSUMVS   0xfc00707f
++
++#define MATCH_VFREDOSUMVS 0x0c001057
++#define MASK_VFREDOSUMVS  0xfc00707f
++#define MATCH_VFREDSUMVS  0x04001057
++#define MASK_VFREDSUMVS   0xfc00707f
++#define MATCH_VFREDMAXVS  0x1c001057
++#define MASK_VFREDMAXVS   0xfc00707f
++#define MATCH_VFREDMINVS  0x14001057
++#define MASK_VFREDMINVS   0xfc00707f
++
++#define MATCH_VFWREDOSUMVS 0xcc001057
++#define MASK_VFWREDOSUMVS  0xfc00707f
++#define MATCH_VFWREDSUMVS  0xc4001057
++#define MASK_VFWREDSUMVS   0xfc00707f
++
++#define MATCH_VMANDMM    0x66002057
++#define MASK_VMANDMM     0xfe00707f
++#define MATCH_VMNANDMM   0x76002057
++#define MASK_VMNANDMM    0xfe00707f
++#define MATCH_VMANDNOTMM 0x62002057
++#define MASK_VMANDNOTMM  0xfe00707f
++#define MATCH_VMXORMM    0x6e002057
++#define MASK_VMXORMM     0xfe00707f
++#define MATCH_VMORMM     0x6a002057
++#define MASK_VMORMM      0xfe00707f
++#define MATCH_VMNORMM    0x7a002057
++#define MASK_VMNORMM     0xfe00707f
++#define MATCH_VMORNOTMM  0x72002057
++#define MASK_VMORNOTMM   0xfe00707f
++#define MATCH_VMXNORMM   0x7e002057
++#define MASK_VMXNORMM    0xfe00707f
++
++#define MATCH_VPOPCM   0x40082057
++#define MASK_VPOPCM    0xfc0ff07f
++#define MATCH_VFIRSTM  0x4008a057
++#define MASK_VFIRSTM   0xfc0ff07f
++
++#define MATCH_VMSBFM   0x5000a057
++#define MASK_VMSBFM    0xfc0ff07f
++#define MATCH_VMSIFM   0x5001a057
++#define MASK_VMSIFM    0xfc0ff07f
++#define MATCH_VMSOFM   0x50012057
++#define MASK_VMSOFM    0xfc0ff07f
++#define MATCH_VIOTAM   0x50082057
++#define MASK_VIOTAM    0xfc0ff07f
++#define MATCH_VIDV     0x5008a057
++#define MASK_VIDV      0xfdfff07f
++
++#define MATCH_VMVXS    0x42002057
++#define MASK_VMVXS     0xfe0ff07f
++#define MATCH_VMVSX    0x42006057
++#define MASK_VMVSX     0xfff0707f
++
++#define MATCH_VFMVFS   0x42001057
++#define MASK_VFMVFS    0xfe0ff07f
++#define MATCH_VFMVSF   0x42005057
++#define MASK_VFMVSF    0xfff0707f
++
++#define MATCH_VSLIDEUPVX   0x38004057
++#define MASK_VSLIDEUPVX    0xfc00707f
++#define MATCH_VSLIDEUPVI   0x38003057
++#define MASK_VSLIDEUPVI    0xfc00707f
++#define MATCH_VSLIDEDOWNVX 0x3c004057
++#define MASK_VSLIDEDOWNVX  0xfc00707f
++#define MATCH_VSLIDEDOWNVI 0x3c003057
++#define MASK_VSLIDEDOWNVI  0xfc00707f
++
++#define MATCH_VSLIDE1UPVX   0x38006057
++#define MASK_VSLIDE1UPVX    0xfc00707f
++#define MATCH_VSLIDE1DOWNVX 0x3c006057
++#define MASK_VSLIDE1DOWNVX  0xfc00707f
++
++#define MATCH_VFSLIDE1UPVF   0x38005057
++#define MASK_VFSLIDE1UPVF    0xfc00707f
++#define MATCH_VFSLIDE1DOWNVF 0x3c005057
++#define MASK_VFSLIDE1DOWNVF  0xfc00707f
++
++#define MATCH_VRGATHERVV      0x30000057
++#define MASK_VRGATHERVV       0xfc00707f
++#define MATCH_VRGATHERVX      0x30004057
++#define MASK_VRGATHERVX       0xfc00707f
++#define MATCH_VRGATHERVI      0x30003057
++#define MASK_VRGATHERVI       0xfc00707f
++#define MATCH_VRGATHEREI16VV  0x38000057
++#define MASK_VRGATHEREI16VV   0xfc00707f
++
++#define MATCH_VCOMPRESSVM   0x5e002057
++#define MASK_VCOMPRESSVM    0xfe00707f
++
++#define MATCH_VMV1RV 0x9e003057
++#define MASK_VMV1RV  0xfe0ff07f
++#define MATCH_VMV2RV 0x9e00b057
++#define MASK_VMV2RV  0xfe0ff07f
++#define MATCH_VMV4RV 0x9e01b057
++#define MASK_VMV4RV  0xfe0ff07f
++#define MATCH_VMV8RV 0x9e03b057
++#define MASK_VMV8RV  0xfe0ff07f
++
++#define MATCH_VDOTVV    0xe4000057
++#define MASK_VDOTVV     0xfc00707f
++#define MATCH_VDOTUVV   0xe0000057
++#define MASK_VDOTUVV    0xfc00707f
++#define MATCH_VFDOTVV   0xe4001057
++#define MASK_VFDOTVV    0xfc00707f
++/* END RVV */
++
+ #define MATCH_CUSTOM0 0xb
+ #define MASK_CUSTOM0  0x707f
+ #define MATCH_CUSTOM0_RS1 0x200b
+@@ -1034,6 +2954,13 @@
+ #define CSR_FFLAGS 0x1
+ #define CSR_FRM 0x2
+ #define CSR_FCSR 0x3
++#define CSR_VSTART 0x008
++#define CSR_VXSAT 0x009
++#define CSR_VXRM 0x00a
++#define CSR_VCSR 0x00f
++#define CSR_VL 0xc20
++#define CSR_VTYPE 0xc21
++#define CSR_VLENB 0xc22
+ #define CSR_DCSR 0x7b0
+ #define CSR_DPC 0x7b1
+ #define CSR_DSCRATCH0 0x7b2
+@@ -1192,6 +3119,22 @@ DECLARE_INSN(fmax_d, MATCH_FMAX_D, MASK_FMAX_D)
+ DECLARE_INSN(fcvt_s_d, MATCH_FCVT_S_D, MASK_FCVT_S_D)
+ DECLARE_INSN(fcvt_d_s, MATCH_FCVT_D_S, MASK_FCVT_D_S)
+ DECLARE_INSN(fsqrt_d, MATCH_FSQRT_D, MASK_FSQRT_D)
++DECLARE_INSN(fadd_h, MATCH_FADD_H, MASK_FADD_H)
++DECLARE_INSN(fsub_h, MATCH_FSUB_D, MASK_FSUB_H)
++DECLARE_INSN(fmul_h, MATCH_FMUL_D, MASK_FMUL_H)
++DECLARE_INSN(fdiv_h, MATCH_FDIV_D, MASK_FDIV_H)
++DECLARE_INSN(fsgnj_h, MATCH_FSGNJ_D, MASK_FSGNJ_H)
++DECLARE_INSN(fsgnjn_h, MATCH_FSGNJN_D, MASK_FSGNJN_H)
++DECLARE_INSN(fsgnjx_h, MATCH_FSGNJX_D, MASK_FSGNJX_H)
++DECLARE_INSN(fmin_h, MATCH_FMIN_D, MASK_FMIN_H)
++DECLARE_INSN(fmax_h, MATCH_FMAX_D, MASK_FMAX_H)
++DECLARE_INSN(fcvt_s_h, MATCH_FCVT_S_D, MASK_FCVT_S_H)
++DECLARE_INSN(fcvt_h_s, MATCH_FCVT_H_S, MASK_FCVT_H_S)
++DECLARE_INSN(fcvt_d_h, MATCH_FCVT_D_H, MASK_FCVT_D_H)
++DECLARE_INSN(fcvt_h_d, MATCH_FCVT_H_D, MASK_FCVT_H_D)
++DECLARE_INSN(fcvt_q_h, MATCH_FCVT_Q_H, MASK_FCVT_Q_H)
++DECLARE_INSN(fcvt_h_q, MATCH_FCVT_H_Q, MASK_FCVT_H_Q)
++DECLARE_INSN(fsqrt_h, MATCH_FSQRT_H, MASK_FSQRT_H)
+ DECLARE_INSN(fadd_q, MATCH_FADD_Q, MASK_FADD_Q)
+ DECLARE_INSN(fsub_q, MATCH_FSUB_Q, MASK_FSUB_Q)
+ DECLARE_INSN(fmul_q, MATCH_FMUL_Q, MASK_FMUL_Q)
+@@ -1212,6 +3155,9 @@ DECLARE_INSN(feq_s, MATCH_FEQ_S, MASK_FEQ_S)
+ DECLARE_INSN(fle_d, MATCH_FLE_D, MASK_FLE_D)
+ DECLARE_INSN(flt_d, MATCH_FLT_D, MASK_FLT_D)
+ DECLARE_INSN(feq_d, MATCH_FEQ_D, MASK_FEQ_D)
++DECLARE_INSN(fle_h, MATCH_FLE_H, MASK_FLE_H)
++DECLARE_INSN(flt_h, MATCH_FLT_H, MASK_FLT_H)
++DECLARE_INSN(feq_h, MATCH_FEQ_H, MASK_FEQ_H)
+ DECLARE_INSN(fle_q, MATCH_FLE_Q, MASK_FLE_Q)
+ DECLARE_INSN(flt_q, MATCH_FLT_Q, MASK_FLT_Q)
+ DECLARE_INSN(feq_q, MATCH_FEQ_Q, MASK_FEQ_Q)
+@@ -1227,6 +3173,12 @@ DECLARE_INSN(fcvt_l_d, MATCH_FCVT_L_D, MASK_FCVT_L_D)
+ DECLARE_INSN(fcvt_lu_d, MATCH_FCVT_LU_D, MASK_FCVT_LU_D)
+ DECLARE_INSN(fmv_x_d, MATCH_FMV_X_D, MASK_FMV_X_D)
+ DECLARE_INSN(fclass_d, MATCH_FCLASS_D, MASK_FCLASS_D)
++DECLARE_INSN(fcvt_w_h, MATCH_FCVT_W_H, MASK_FCVT_W_H)
++DECLARE_INSN(fcvt_wu_h, MATCH_FCVT_WU_H, MASK_FCVT_WU_H)
++DECLARE_INSN(fcvt_l_h, MATCH_FCVT_L_H, MASK_FCVT_L_H)
++DECLARE_INSN(fcvt_lu_h, MATCH_FCVT_LU_H, MASK_FCVT_LU_H)
++DECLARE_INSN(fmv_x_h, MATCH_FMV_X_H, MASK_FMV_X_H)
++DECLARE_INSN(fclass_h, MATCH_FCLASS_H, MASK_FCLASS_H)
+ DECLARE_INSN(fcvt_w_q, MATCH_FCVT_W_Q, MASK_FCVT_W_Q)
+ DECLARE_INSN(fcvt_wu_q, MATCH_FCVT_WU_Q, MASK_FCVT_WU_Q)
+ DECLARE_INSN(fcvt_l_q, MATCH_FCVT_L_Q, MASK_FCVT_L_Q)
+@@ -1243,6 +3195,11 @@ DECLARE_INSN(fcvt_d_wu, MATCH_FCVT_D_WU, MASK_FCVT_D_WU)
+ DECLARE_INSN(fcvt_d_l, MATCH_FCVT_D_L, MASK_FCVT_D_L)
+ DECLARE_INSN(fcvt_d_lu, MATCH_FCVT_D_LU, MASK_FCVT_D_LU)
+ DECLARE_INSN(fmv_d_x, MATCH_FMV_D_X, MASK_FMV_D_X)
++DECLARE_INSN(fcvt_h_w, MATCH_FCVT_H_W, MASK_FCVT_H_W)
++DECLARE_INSN(fcvt_h_wu, MATCH_FCVT_H_WU, MASK_FCVT_H_WU)
++DECLARE_INSN(fcvt_h_l, MATCH_FCVT_H_L, MASK_FCVT_H_L)
++DECLARE_INSN(fcvt_h_lu, MATCH_FCVT_H_LU, MASK_FCVT_H_LU)
++DECLARE_INSN(fmv_h_x, MATCH_FMV_H_X, MASK_FMV_H_X)
+ DECLARE_INSN(fcvt_q_w, MATCH_FCVT_Q_W, MASK_FCVT_Q_W)
+ DECLARE_INSN(fcvt_q_wu, MATCH_FCVT_Q_WU, MASK_FCVT_Q_WU)
+ DECLARE_INSN(fcvt_q_l, MATCH_FCVT_Q_L, MASK_FCVT_Q_L)
+@@ -1349,9 +3306,11 @@ DECLARE_INSN(fsri, MATCH_FSRI, MASK_FSRI)
+ DECLARE_INSN(fslw, MATCH_FSLW, MASK_FSLW)
+ DECLARE_INSN(fsrw, MATCH_FSRW, MASK_FSRW)
+ DECLARE_INSN(fsriw, MATCH_FSRIW, MASK_FSRIW)
++DECLARE_INSN(flh, MATCH_FLH, MASK_FLH)
+ DECLARE_INSN(flw, MATCH_FLW, MASK_FLW)
+ DECLARE_INSN(fld, MATCH_FLD, MASK_FLD)
+ DECLARE_INSN(flq, MATCH_FLQ, MASK_FLQ)
++DECLARE_INSN(fsh, MATCH_FSH, MASK_FSH)
+ DECLARE_INSN(fsw, MATCH_FSW, MASK_FSW)
+ DECLARE_INSN(fsd, MATCH_FSD, MASK_FSD)
+ DECLARE_INSN(fsq, MATCH_FSQ, MASK_FSQ)
+@@ -1363,6 +3322,10 @@ DECLARE_INSN(fmadd_d, MATCH_FMADD_D, MASK_FMADD_D)
+ DECLARE_INSN(fmsub_d, MATCH_FMSUB_D, MASK_FMSUB_D)
+ DECLARE_INSN(fnmsub_d, MATCH_FNMSUB_D, MASK_FNMSUB_D)
+ DECLARE_INSN(fnmadd_d, MATCH_FNMADD_D, MASK_FNMADD_D)
++DECLARE_INSN(fmadd_h, MATCH_FMADD_H, MASK_FMADD_H)
++DECLARE_INSN(fmsub_h, MATCH_FMSUB_H, MASK_FMSUB_H)
++DECLARE_INSN(fnmsub_h, MATCH_FNMSUB_H, MASK_FNMSUB_H)
++DECLARE_INSN(fnmadd_h, MATCH_FNMADD_H, MASK_FNMADD_H)
+ DECLARE_INSN(fmadd_q, MATCH_FMADD_Q, MASK_FMADD_Q)
+ DECLARE_INSN(fmsub_q, MATCH_FMSUB_Q, MASK_FMSUB_Q)
+ DECLARE_INSN(fnmsub_q, MATCH_FNMSUB_Q, MASK_FNMSUB_Q)
+@@ -1671,6 +3634,13 @@ DECLARE_CSR(mhcounteren, CSR_MHCOUNTEREN, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9P1, PR
+ DECLARE_CSR(fflags, CSR_FFLAGS, CSR_CLASS_F, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE)
+ DECLARE_CSR(frm, CSR_FRM, CSR_CLASS_F, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE)
+ DECLARE_CSR(fcsr, CSR_FCSR, CSR_CLASS_F, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE)
++DECLARE_CSR(vstart, CSR_VSTART, CSR_CLASS_V, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE)
++DECLARE_CSR(vxsat, CSR_VXSAT, CSR_CLASS_V, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE)
++DECLARE_CSR(vxrm, CSR_VXRM, CSR_CLASS_V, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE)
++DECLARE_CSR(vcsr, CSR_VCSR, CSR_CLASS_V, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE)
++DECLARE_CSR(vl, CSR_VL, CSR_CLASS_V, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE)
++DECLARE_CSR(vtype, CSR_VTYPE, CSR_CLASS_V, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE)
++DECLARE_CSR(vlenb, CSR_VLENB, CSR_CLASS_V, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE)
+ DECLARE_CSR(dcsr, CSR_DCSR, CSR_CLASS_DEBUG, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE)
+ DECLARE_CSR(dpc, CSR_DPC, CSR_CLASS_DEBUG, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE)
+ DECLARE_CSR(dscratch0, CSR_DSCRATCH0, CSR_CLASS_DEBUG, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE)
+diff --git a/include/opcode/riscv.h b/include/opcode/riscv.h
+index 87d1aedb40..524637a27b 100644
+--- a/include/opcode/riscv.h
++++ b/include/opcode/riscv.h
+@@ -52,6 +52,28 @@ static const char * const riscv_pred_succ[16] =
+   "i", "iw", "ir", "irw", "io", "iow", "ior", "iorw"
+ };
+ 
++/* List of vsetvli vsew constants.  */
++static const char * const riscv_vsew[8] =
++{
++  "e8", "e16", "e32", "e64", "e128", "e256", "e512", "e1024"
++};
++
++/* List of vsetvli vlmul constants.  */
++static const char * const riscv_vlmul[8] =
++{
++  "m1", "m2", "m4", "m8", 0, "mf8", "mf4", "mf2"
++};
++
++static const char * const riscv_vta[2] =
++{
++  "tu", "ta"
++};
++
++static const char * const riscv_vma[2] =
++{
++  "mu", "ma"
++};
++
+ #define RVC_JUMP_BITS 11
+ #define RVC_JUMP_REACH ((1ULL << RVC_JUMP_BITS) * RISCV_JUMP_ALIGN)
+ 
+@@ -99,6 +121,16 @@ static const char * const riscv_pred_succ[16] =
+   ((RV_X(x, 3, 2) << 1) | (RV_X(x, 10, 2) << 3) | (RV_X(x, 2, 1) << 5) | (RV_X(x, 5, 2) << 6) | (-RV_X(x, 12, 1) << 8))
+ #define EXTRACT_RVC_J_IMM(x) \
+   ((RV_X(x, 3, 3) << 1) | (RV_X(x, 11, 1) << 4) | (RV_X(x, 2, 1) << 5) | (RV_X(x, 7, 1) << 6) | (RV_X(x, 6, 1) << 7) | (RV_X(x, 9, 2) << 8) | (RV_X(x, 8, 1) << 10) | (-RV_X(x, 12, 1) << 11))
++#define EXTRACT_RVV_VI_IMM(x) \
++  (RV_X(x, 15, 5) | (-RV_X(x, 19, 1) << 5))
++#define EXTRACT_RVV_VI_UIMM(x) \
++  (RV_X(x, 15, 5))
++#define EXTRACT_RVV_OFFSET(x) \
++  (RV_X(x, 29, 3))
++#define EXTRACT_RVV_VB_IMM(x) \
++  (RV_X(x, 20, 10))
++#define EXTRACT_RVV_VC_IMM(x) \
++  (RV_X(x, 20, 11))
+ 
+ #define ENCODE_ITYPE_IMM(x) \
+   (RV_X(x, 0, 12) << 20)
+@@ -138,6 +170,10 @@ static const char * const riscv_pred_succ[16] =
+   ((RV_X(x, 1, 2) << 3) | (RV_X(x, 3, 2) << 10) | (RV_X(x, 5, 1) << 2) | (RV_X(x, 6, 2) << 5) | (RV_X(x, 8, 1) << 12))
+ #define ENCODE_RVC_J_IMM(x) \
+   ((RV_X(x, 1, 3) << 3) | (RV_X(x, 4, 1) << 11) | (RV_X(x, 5, 1) << 2) | (RV_X(x, 6, 1) << 7) | (RV_X(x, 7, 1) << 6) | (RV_X(x, 8, 2) << 9) | (RV_X(x, 10, 1) << 8) | (RV_X(x, 11, 1) << 12))
++#define ENCODE_RVV_VB_IMM(x) \
++  (RV_X(x, 0, 10) << 20)
++#define ENCODE_RVV_VC_IMM(x) \
++  (RV_X(x, 0, 11) << 20)
+ 
+ #define VALID_ITYPE_IMM(x) (EXTRACT_ITYPE_IMM(ENCODE_ITYPE_IMM(x)) == (x))
+ #define VALID_STYPE_IMM(x) (EXTRACT_STYPE_IMM(ENCODE_STYPE_IMM(x)) == (x))
+@@ -158,6 +194,8 @@ static const char * const riscv_pred_succ[16] =
+ #define VALID_RVC_SDSP_IMM(x) (EXTRACT_RVC_SDSP_IMM(ENCODE_RVC_SDSP_IMM(x)) == (x))
+ #define VALID_RVC_B_IMM(x) (EXTRACT_RVC_B_IMM(ENCODE_RVC_B_IMM(x)) == (x))
+ #define VALID_RVC_J_IMM(x) (EXTRACT_RVC_J_IMM(ENCODE_RVC_J_IMM(x)) == (x))
++#define VALID_RVV_VB_IMM(x) (EXTRACT_RVV_VB_IMM(ENCODE_RVV_VB_IMM(x)) == (x))
++#define VALID_RVV_VC_IMM(x) (EXTRACT_RVV_VC_IMM(ENCODE_RVV_VC_IMM(x)) == (x))
+ 
+ #define RISCV_RTYPE(insn, rd, rs1, rs2) \
+   ((MATCH_ ## insn) | ((rd) << OP_SH_RD) | ((rs1) << OP_SH_RS1) | ((rs2) << OP_SH_RS2))
+@@ -256,6 +294,35 @@ static const char * const riscv_pred_succ[16] =
+ #define OP_MASK_CFUNCT2                0x3
+ #define OP_SH_CFUNCT2          5
+ 
++/* RVV fields.  */
++
++#define OP_MASK_VD		0x1f
++#define OP_SH_VD		7
++#define OP_MASK_VS1		0x1f
++#define OP_SH_VS1		15
++#define OP_MASK_VS2		0x1f
++#define OP_SH_VS2		20
++#define OP_MASK_VIMM		0x1f
++#define OP_SH_VIMM		15
++#define OP_MASK_VMASK		0x1
++#define OP_SH_VMASK		25
++#define OP_MASK_VFUNCT6		0x3f
++#define OP_SH_VFUNCT6		26
++
++#define OP_MASK_VLMUL		0x7
++#define OP_SH_VLMUL		0
++#define OP_MASK_VSEW		0x7
++#define OP_SH_VSEW		3
++#define OP_MASK_VTA		0x1
++#define OP_SH_VTA		6
++#define OP_MASK_VMA		0x1
++#define OP_SH_VMA		7
++#define OP_MASK_VTYPE_RES	0x1
++#define OP_SH_VTYPE_RES 	10
++
++#define OP_MASK_VWD		0x1
++#define OP_SH_VWD		26
++
+ /* ABI names for selected x-registers.  */
+ 
+ #define X_RA 1
+@@ -269,6 +336,8 @@ static const char * const riscv_pred_succ[16] =
+ 
+ #define NGPR 32
+ #define NFPR 32
++#define NVECR 32
++#define NVECM 1
+ 
+ /* These fake label defines are use by both the assembler, and
+    libopcodes.  The assembler uses this when it needs to generate a fake
+@@ -327,6 +396,13 @@ enum riscv_insn_class
+    INSN_CLASS_ZBT,
+    INSN_CLASS_ZBP_OR_ZBE_OR_ZBF,
+    INSN_CLASS_ZBP_OR_ZBE_OR_ZBF_OR_ZBM,
++   INSN_CLASS_V,
++   INSN_CLASS_F_AND_ZFH,
++   INSN_CLASS_D_AND_ZFH,
++   INSN_CLASS_Q_AND_ZFH,
++   INSN_CLASS_V_AND_F,
++   INSN_CLASS_V_OR_ZVAMO,
++   INSN_CLASS_V_OR_ZVLSSEG,
+   };
+ 
+ /* This structure holds information for a particular instruction.  */
+@@ -394,6 +470,7 @@ enum riscv_csr_class
+   CSR_CLASS_I,
+   CSR_CLASS_I_32,      /* rv32 only */
+   CSR_CLASS_F,         /* f-ext only */
++  CSR_CLASS_V,         /* v-ext only */
+   CSR_CLASS_DEBUG      /* debug CSR */
+ };
+ 
+@@ -488,9 +565,11 @@ enum
+   M_SH,
+   M_SW,
+   M_SD,
++  M_FLH,
+   M_FLW,
+   M_FLD,
+   M_FLQ,
++  M_FSH,
+   M_FSW,
+   M_FSD,
+   M_FSQ,
+@@ -501,6 +580,8 @@ enum
+   M_ZEXTW,
+   M_SEXTB,
+   M_SEXTH,
++  M_VMSGE,
++  M_VMSGEU,
+   M_NUM_MACROS
+ };
+ 
+@@ -509,6 +590,8 @@ extern const char * const riscv_gpr_names_numeric[NGPR];
+ extern const char * const riscv_gpr_names_abi[NGPR];
+ extern const char * const riscv_fpr_names_numeric[NFPR];
+ extern const char * const riscv_fpr_names_abi[NFPR];
++extern const char * const riscv_vecr_names_numeric[NVECR];
++extern const char * const riscv_vecm_names_numeric[NVECM];
+ 
+ extern const struct riscv_opcode riscv_opcodes[];
+ extern const struct riscv_opcode riscv_insn_types[];
+diff --git a/opcodes/riscv-dis.c b/opcodes/riscv-dis.c
+index a169d013c4..065ea75b82 100644
+--- a/opcodes/riscv-dis.c
++++ b/opcodes/riscv-dis.c
+@@ -43,6 +43,7 @@ struct riscv_private_data
+ 
+ static const char * const *riscv_gpr_names;
+ static const char * const *riscv_fpr_names;
++static const char * const *riscv_vecr_names;
+ 
+ /* Other options.  */
+ static int no_aliases;	/* If set disassemble as most general inst.  */
+@@ -52,6 +53,7 @@ set_default_riscv_dis_options (void)
+ {
+   riscv_gpr_names = riscv_gpr_names_abi;
+   riscv_fpr_names = riscv_fpr_names_abi;
++  riscv_vecr_names = riscv_vecr_names_numeric;
+   no_aliases = 0;
+ }
+ 
+@@ -413,6 +415,88 @@ print_insn_args (const char *d, insn_t l, bfd_vma pc, disassemble_info *info)
+ 	  print (info->stream, "%d", rs1);
+ 	  break;
+ 
++	case 'V': /* RVV */
++	  switch (*++d)
++	    {
++	    case 'd':
++	    case 'f':
++	      print (info->stream, "%s",
++		      riscv_vecr_names[EXTRACT_OPERAND (VD, l)]);
++	      break;
++
++	    case 'e':
++	      if (!EXTRACT_OPERAND (VWD, l))
++		print (info->stream, "%s", riscv_gpr_names[0]);
++	      else
++		print (info->stream, "%s",
++		       riscv_vecr_names[EXTRACT_OPERAND (VD, l)]);
++	      break;
++
++	    case 's':
++	      print (info->stream, "%s",
++		      riscv_vecr_names[EXTRACT_OPERAND (VS1, l)]);
++	      break;
++
++	    case 't':
++	    case 'u': /* VS1 == VS2 already verified at this point.  */
++	    case 'v': /* VD == VS1 == VS2 already verified at this point.  */
++	      print (info->stream, "%s",
++		      riscv_vecr_names[EXTRACT_OPERAND (VS2, l)]);
++	      break;
++
++	    case '0':
++	      print (info->stream, "%s", riscv_vecr_names[0]);
++	      break;
++
++	    case 'b':
++	    case 'c':
++	      {
++		int imm = (*d == 'b') ? EXTRACT_RVV_VB_IMM (l)
++				      : EXTRACT_RVV_VC_IMM (l);
++		unsigned int imm_vlmul = EXTRACT_OPERAND (VLMUL, imm);
++		unsigned int imm_vsew = EXTRACT_OPERAND (VSEW, imm);
++		unsigned int imm_vta = EXTRACT_OPERAND (VTA, imm);
++		unsigned int imm_vma = EXTRACT_OPERAND (VMA, imm);
++		unsigned int imm_vtype_res = EXTRACT_OPERAND (VTYPE_RES, imm);
++
++		if (imm_vsew < ARRAY_SIZE (riscv_vsew)
++		    && imm_vlmul < ARRAY_SIZE (riscv_vlmul)
++		    && imm_vta < ARRAY_SIZE (riscv_vta)
++		    && imm_vma < ARRAY_SIZE (riscv_vma)
++		    && ! imm_vtype_res)
++		  print (info->stream, "%s,%s,%s,%s", riscv_vsew[imm_vsew],
++			 riscv_vlmul[imm_vlmul], riscv_vta[imm_vta],
++			 riscv_vma[imm_vma]);
++		else
++		  print (info->stream, "%d", imm);
++	      }
++	      break;
++
++	    case 'i':
++	      print (info->stream, "%d", (int)EXTRACT_RVV_VI_IMM (l));
++	      break;
++
++	    case 'j':
++	      print (info->stream, "%d", (int)EXTRACT_RVV_VI_UIMM (l));
++	      break;
++
++	    case 'k':
++	      print (info->stream, "%d", (int)EXTRACT_RVV_OFFSET (l));
++	      break;
++
++	    case 'm':
++	      if (! EXTRACT_OPERAND (VMASK, l))
++		print (info->stream, ",%s", riscv_vecm_names_numeric[0]);
++	      break;
++
++	    default:
++	      /* xgettext:c-format */
++	      print (info->stream, _("# internal error, undefined modifier (V%c)"),
++		     *d);
++	      return;
++	    }
++	  break;
++
+ 	default:
+ 	  /* xgettext:c-format */
+ 	  print (info->stream, _("# internal error, undefined modifier (%c)"),
+diff --git a/opcodes/riscv-opc.c b/opcodes/riscv-opc.c
+index d73c980acd..b51e876977 100644
+--- a/opcodes/riscv-opc.c
++++ b/opcodes/riscv-opc.c
+@@ -61,6 +61,19 @@ const char * const riscv_fpr_names_abi[NFPR] = {
+   "fs8", "fs9", "fs10", "fs11", "ft8", "ft9", "ft10", "ft11"
+ };
+ 
++const char * const riscv_vecr_names_numeric[NVECR] =
++{
++  "v0",   "v1",   "v2",   "v3",   "v4",   "v5",   "v6",   "v7",
++  "v8",   "v9",   "v10",  "v11",  "v12",  "v13",  "v14",  "v15",
++  "v16",  "v17",  "v18",  "v19",  "v20",  "v21",  "v22",  "v23",
++  "v24",  "v25",  "v26",  "v27",  "v28",  "v29",  "v30",  "v31"
++};
++
++const char * const riscv_vecm_names_numeric[NVECM] =
++{
++  "v0.t"
++};
++
+ /* The order of overloaded instructions matters.  Label arguments and
+    register arguments look the same. Instructions that can have either
+    for arguments must apear in the correct order in this table for the
+@@ -84,6 +97,10 @@ const char * const riscv_fpr_names_abi[NFPR] = {
+ #define MASK_AQ (OP_MASK_AQ << OP_SH_AQ)
+ #define MASK_RL (OP_MASK_RL << OP_SH_RL)
+ #define MASK_AQRL (MASK_AQ | MASK_RL)
++#define MASK_VD  (OP_MASK_VD << OP_SH_VD)
++#define MASK_VS1 (OP_MASK_VS1 << OP_SH_VS1)
++#define MASK_VS2 (OP_MASK_VS2 << OP_SH_VS2)
++#define MASK_VMASK (OP_MASK_VMASK << OP_SH_VMASK)
+ 
+ static int
+ match_opcode (const struct riscv_opcode *op, insn_t insn)
+@@ -106,6 +123,53 @@ match_rs1_eq_rs2 (const struct riscv_opcode *op, insn_t insn)
+   return match_opcode (op, insn) && rs1 == rs2;
+ }
+ 
++static int
++match_vs1_eq_vs2 (const struct riscv_opcode *op,
++		  insn_t insn,
++		  int constraints ATTRIBUTE_UNUSED,
++		  const char **error ATTRIBUTE_UNUSED)
++{
++  int vs1 = (insn & MASK_VS1) >> OP_SH_VS1;
++  int vs2 = (insn & MASK_VS2) >> OP_SH_VS2;
++
++  return match_opcode (op, insn) && vs1 == vs2;
++}
++
++static int
++match_vs1_eq_vs2_neq_vm (const struct riscv_opcode *op,
++			 insn_t insn)
++			 //int constraints,
++			 //const char **error)
++{
++  int vd = (insn & MASK_VD) >> OP_SH_VD;
++  int vs1 = (insn & MASK_VS1) >> OP_SH_VS1;
++  int vs2 = (insn & MASK_VS2) >> OP_SH_VS2;
++  int vm = (insn & MASK_VMASK) >> OP_SH_VMASK;
++
++  //if (!constraints || error == NULL)
++  //  return match_opcode (op, insn) && vs1 == vs2;
++
++  if (!vm && vm == vd) return 0;
++    //*error = "illegal operands vd cannot overlap vm";
++  else
++    return match_opcode (op, insn) && vs1 == vs2;
++  return 0;
++}
++
++static int
++match_vd_eq_vs1_eq_vs2 (const struct riscv_opcode *op,
++			insn_t insn)
++			//int constraints ATTRIBUTE_UNUSED,
++			//const char **error ATTRIBUTE_UNUSED)
++{
++  int vd =  (insn & MASK_VD) >> OP_SH_VD;
++  int vs1 = (insn & MASK_VS1) >> OP_SH_VS1;
++  int vs2 = (insn & MASK_VS2) >> OP_SH_VS2;
++
++  return match_opcode (op, insn) && vd == vs1 && vs1 == vs2;
++}
++
++
+ static int
+ match_rd_nonzero (const struct riscv_opcode *op, insn_t insn)
+ {
+@@ -200,6 +264,274 @@ match_srxi_as_c_srxi (const struct riscv_opcode *op, insn_t insn)
+   return match_opcode (op, insn) && EXTRACT_RVC_IMM (insn) != 0;
+ }
+ 
++
++/* These are used to check the vector constraints.  */
++
++static int
++match_widen_vd_neq_vs1_neq_vs2_neq_vm (const struct riscv_opcode *op,
++				       insn_t insn)
++				       //int constraints,
++				       //const char **error)
++{
++  int vd = (insn & MASK_VD) >> OP_SH_VD;
++  int vs1 = (insn & MASK_VS1) >> OP_SH_VS1;
++  int vs2 = (insn & MASK_VS2) >> OP_SH_VS2;
++  int vm = (insn & MASK_VMASK) >> OP_SH_VMASK;
++
++  //if (!constraints || error == NULL)
++  //  return match_opcode (op, insn);
++
++  if ((vd % 2) != 0)
++    return 0;
++    //*error = "illegal operands vd must be multiple of 2";
++  else if (vs1 >= vd && vs1 <= (vd + 1))
++    return 0;
++    //*error = "illegal operands vd cannot overlap vs1";
++  else if (vs2 >= vd && vs2 <= (vd + 1))
++    return 0;
++    //*error = "illegal operands vd cannot overlap vs2";
++  else if (!vm && vm >= vd && vm <= (vd + 1))
++    return 0;
++    //*error = "illegal operands vd cannot overlap vm";
++  else
++    return match_opcode (op, insn);
++  return 0;
++}
++
++static int
++match_widen_vd_neq_vs1_neq_vm (const struct riscv_opcode *op,
++			       insn_t insn)
++			       //int constraints,
++			       //const char **error)
++{
++  int vd = (insn & MASK_VD) >> OP_SH_VD;
++  int vs1 = (insn & MASK_VS1) >> OP_SH_VS1;
++  int vs2 = (insn & MASK_VS2) >> OP_SH_VS2;
++  int vm = (insn & MASK_VMASK) >> OP_SH_VMASK;
++
++  //if (!constraints || error == NULL)
++  //  return match_opcode (op, insn);
++
++  if ((vd % 2) != 0) return 0;
++    //*error = "illegal operands vd must be multiple of 2";
++  else if ((vs2 % 2) != 0) return 0;
++    //*error = "illegal operands vs2 must be multiple of 2";
++  else if (vs1 >= vd && vs1 <= (vd + 1)) return 0;
++    //*error = "illegal operands vd cannot overlap vs1";
++  else if (!vm && vm >= vd && vm <= (vd + 1)) return 0;
++    //*error = "illegal operands vd cannot overlap vm";
++  else
++    return match_opcode (op, insn);
++  return 0;
++}
++
++static int
++match_widen_vd_neq_vs2_neq_vm (const struct riscv_opcode *op,
++			       insn_t insn)
++			       //int constraints,
++			       //const char **error)
++{
++  int vd = (insn & MASK_VD) >> OP_SH_VD;
++  int vs2 = (insn & MASK_VS2) >> OP_SH_VS2;
++  int vm = (insn & MASK_VMASK) >> OP_SH_VMASK;
++
++  //if (!constraints || error == NULL)
++  //  return match_opcode (op, insn);
++
++  if ((vd % 2) != 0) return 0;
++    //*error = "illegal operands vd must be multiple of 2";
++  else if (vs2 >= vd && vs2 <= (vd + 1)) return 0;
++    //*error = "illegal operands vd cannot overlap vs2";
++  else if (!vm && vm >= vd && vm <= (vd + 1)) return 0;
++    //*error = "illegal operands vd cannot overlap vm";
++  else
++    return match_opcode (op, insn);
++  return 0;
++}
++
++static int
++match_widen_vd_neq_vm (const struct riscv_opcode *op,
++		       insn_t insn)
++		       //int constraints,
++		       //const char **error)
++{
++  int vd = (insn & MASK_VD) >> OP_SH_VD;
++  int vs2 = (insn & MASK_VS2) >> OP_SH_VS2;
++  int vm = (insn & MASK_VMASK) >> OP_SH_VMASK;
++
++  //if (!constraints || error == NULL)
++  //  return match_opcode (op, insn);
++
++  if ((vd % 2) != 0) return 0;
++   // *error = "illegal operands vd must be multiple of 2";
++  else if ((vs2 % 2) != 0) return 0;
++   // *error = "illegal operands vs2 must be multiple of 2";
++  else if (!vm && vm >= vd && vm <= (vd + 1)) return 0;
++   // *error = "illegal operands vd cannot overlap vm";
++  else
++    return match_opcode (op, insn);
++  return 0;
++}
++
++static int
++match_narrow_vd_neq_vs2_neq_vm (const struct riscv_opcode *op,
++				insn_t insn)
++				//int constraints,
++				//const char **error)
++{
++  int vd = (insn & MASK_VD) >> OP_SH_VD;
++  int vs2 = (insn & MASK_VS2) >> OP_SH_VS2;
++  int vm = (insn & MASK_VMASK) >> OP_SH_VMASK;
++
++  //if (!constraints || error == NULL)
++  //  return match_opcode (op, insn);
++
++  if ((vs2 % 2) != 0) return 0;
++    //*error = "illegal operands vd must be multiple of 2";
++  else if (vd >= vs2 && vd <= (vs2 + 1)) return 0;
++    //*error = "illegal operands vd cannot overlap vs2";
++  else if (!vm && vd >= vm && vd <= (vm + 1)) return 0;
++    //*error = "illegal operands vd cannot overlap vm";
++  else
++    return match_opcode (op, insn);
++  return 0;
++}
++
++static int
++match_vd_neq_vs1_neq_vs2 (const struct riscv_opcode *op,
++			  insn_t insn)
++			  //int constraints,
++			  //const char **error)
++{
++  int vd = (insn & MASK_VD) >> OP_SH_VD;
++  int vs1 = (insn & MASK_VS1) >> OP_SH_VS1;
++  int vs2 = (insn & MASK_VS2) >> OP_SH_VS2;
++
++  //if (!constraints || error == NULL)
++  //  return match_opcode (op, insn);
++
++  if (vs1 == vd) return 0;
++    //*error = "illegal operands vd cannot overlap vs1";
++  else if (vs2 == vd) return 0;
++    //*error = "illegal operands vd cannot overlap vs2";
++  else
++    return match_opcode (op, insn);
++  return 0;
++}
++
++static int
++match_vd_neq_vs1_neq_vs2_neq_vm (const struct riscv_opcode *op,
++				 insn_t insn,
++				 int constraints,
++				 const char **error)
++{
++  int vd = (insn & MASK_VD) >> OP_SH_VD;
++  int vs1 = (insn & MASK_VS1) >> OP_SH_VS1;
++  int vs2 = (insn & MASK_VS2) >> OP_SH_VS2;
++  int vm = (insn & MASK_VMASK) >> OP_SH_VMASK;
++
++  if (!constraints || error == NULL)
++    return match_opcode (op, insn);
++
++  if (vs1 == vd)
++    *error = "illegal operands vd cannot overlap vs1";
++  else if (vs2 == vd)
++    *error = "illegal operands vd cannot overlap vs2";
++  else if (!vm && vm == vd)
++    *error = "illegal operands vd cannot overlap vm";
++  else
++    return match_opcode (op, insn);
++  return 0;
++}
++
++static int
++match_vd_neq_vs2_neq_vm (const struct riscv_opcode *op,
++			 insn_t insn)
++			 //int constraints,
++			 //const char **error)
++{
++  int vd = (insn & MASK_VD) >> OP_SH_VD;
++  int vs2 = (insn & MASK_VS2) >> OP_SH_VS2;
++  int vm = (insn & MASK_VMASK) >> OP_SH_VMASK;
++
++  //if (!constraints || error == NULL)
++  //  return match_opcode (op, insn);
++
++  if (vs2 == vd) return 0;
++    //*error = "illegal operands vd cannot overlap vs2";
++  else if (!vm && vm == vd) return 0;
++    //*error = "illegal operands vd cannot overlap vm";
++  else 
++    return match_opcode (op, insn);
++  return 0;
++}
++
++/* v[m]adc and v[m]sbc use the vm encoding to encode the
++   carry-in v0 register.  The carry-in v0 register can not
++   overlap with the vd, too.  Therefore, we use the same
++   match_vd_neq_vm to check the overlap constraints.  */
++
++static int
++match_vd_neq_vm (const struct riscv_opcode *op,
++		 insn_t insn)
++		 //int constraints,
++		 //const char **error)
++{
++  int vd = (insn & MASK_VD) >> OP_SH_VD;
++  int vm = (insn & MASK_VMASK) >> OP_SH_VMASK;
++
++  //if (!constraints || error == NULL)
++  //  return match_opcode (op, insn);
++
++  if (!vm && vm == vd) return 0;
++    //*error = "illegal operands vd cannot overlap vm";
++  else
++    return match_opcode (op, insn);
++  return 0;
++}
++
++static int
++match_vls_nf_rv (const struct riscv_opcode *op,
++		 insn_t insn)
++		 //int constraints,
++		 //const char **error)
++{
++  int vd = (insn & MASK_VD) >> OP_SH_VD;
++  int nf = ((insn & (0x7 << 29) ) >> 29) + 1;
++
++  //if (!constraints || error == NULL)
++  //  return match_opcode (op, insn);
++
++  if ((vd % nf) != 0) return 0;
++    //*error = "illegal operands vd must be multiple of nf";
++  else
++    return match_opcode (op, insn);
++  return 0;
++}
++
++static int
++match_vmv_nf_rv (const struct riscv_opcode *op,
++		 insn_t insn)
++		 //int constraints,
++		 //const char **error)
++{
++  int vd = (insn & MASK_VD) >> OP_SH_VD;
++  int vs2 = (insn & MASK_VS2) >> OP_SH_VS2;
++  int nf = ((insn & (0x7 << 15) ) >> 15) + 1;
++
++  //if (!constraints || error == NULL)
++  //  return match_opcode (op, insn);
++
++  if ((vd % nf) != 0) return 0;
++    //*error = "illegal operands vd must be multiple of nf";
++  else if ((vs2 % nf) != 0) return 0;
++    //*error = "illegal operands vs2 must be multiple of nf";
++  else
++    return match_opcode (op, insn);
++  return 0;
++}
++
++
+ const struct riscv_opcode riscv_opcodes[] =
+ {
+ /* name,     xlen, isa,   operands, match, mask, match_func, pinfo.  */
+@@ -243,10 +575,7 @@ const struct riscv_opcode riscv_opcodes[] =
+ {"mv",          0, INSN_CLASS_I,   "d,s",  MATCH_ADDI, MASK_ADDI | MASK_IMM, match_opcode, INSN_ALIAS },
+ {"move",        0, INSN_CLASS_C,   "d,CV",  MATCH_C_MV, MASK_C_MV, match_c_add, INSN_ALIAS },
+ {"move",        0, INSN_CLASS_I,   "d,s",  MATCH_ADDI, MASK_ADDI | MASK_IMM, match_opcode, INSN_ALIAS },
+-{"sext.b",      0, INSN_CLASS_I,   "d,s",  0, (int) M_SEXTB, match_never, INSN_MACRO },
+-{"sext.h",      0, INSN_CLASS_I,   "d,s",  0, (int) M_SEXTH, match_never, INSN_MACRO },
+ {"zext.b",      0, INSN_CLASS_I,   "d,s",  MATCH_ANDI | ENCODE_ITYPE_IMM (255), MASK_ANDI | MASK_IMM, match_opcode, INSN_ALIAS },
+-{"zext.h",      0, INSN_CLASS_I,   "d,s",  0, (int) M_ZEXTH, match_never, INSN_MACRO },
+ {"andi",        0, INSN_CLASS_C,   "Cs,Cw,Co",  MATCH_C_ANDI, MASK_C_ANDI, match_opcode, INSN_ALIAS },
+ {"andi",        0, INSN_CLASS_I,   "d,s,j",  MATCH_ANDI, MASK_ANDI, match_opcode, 0 },
+ {"and",         0, INSN_CLASS_C,   "Cs,Cw,Ct",  MATCH_C_AND, MASK_C_AND, match_opcode, INSN_ALIAS },
+@@ -380,7 +709,6 @@ const struct riscv_opcode riscv_opcodes[] =
+ {"sd",         64, INSN_CLASS_C, "Ct,Cl(Cs)",  MATCH_C_SD, MASK_C_SD, match_opcode, INSN_ALIAS|INSN_DREF|INSN_8_BYTE },
+ {"sd",         64, INSN_CLASS_I, "t,q(s)",  MATCH_SD, MASK_SD, match_opcode, INSN_DREF|INSN_8_BYTE },
+ {"sd",         64, INSN_CLASS_I, "t,A,s",  0, (int) M_SD, match_never, INSN_MACRO },
+-{"zext.w",     64, INSN_CLASS_I, "d,s",    0, (int) M_ZEXTW, match_never, INSN_MACRO },
+ {"sext.w",     64, INSN_CLASS_C, "d,CU",  MATCH_C_ADDIW, MASK_C_ADDIW | MASK_RVC_IMM, match_rd_nonzero, INSN_ALIAS },
+ {"sext.w",     64, INSN_CLASS_I, "d,s",  MATCH_ADDIW, MASK_ADDIW | MASK_IMM, match_opcode, INSN_ALIAS },
+ {"addiw",      64, INSN_CLASS_C, "d,CU,Co",  MATCH_C_ADDIW, MASK_C_ADDIW, match_rd_nonzero, INSN_ALIAS },
+@@ -508,6 +836,71 @@ const struct riscv_opcode riscv_opcodes[] =
+ {"remw",     64, INSN_CLASS_M, "d,s,t",  MATCH_REMW, MASK_REMW, match_opcode, 0 },
+ {"remuw",    64, INSN_CLASS_M, "d,s,t",  MATCH_REMUW, MASK_REMUW, match_opcode, 0 },
+ 
++/* Half-precision floating-point instruction subset */
++{"flh",        0, INSN_CLASS_F_AND_ZFH,   "D,o(s)",  MATCH_FLH, MASK_FLH, match_opcode, INSN_DREF|INSN_2_BYTE },
++{"flh",        0, INSN_CLASS_F_AND_ZFH,   "D,A,s",  0, (int) M_FLH, match_never, INSN_MACRO },
++{"fsh",        0, INSN_CLASS_F_AND_ZFH,   "T,q(s)",  MATCH_FSH, MASK_FSH, match_opcode, INSN_DREF|INSN_2_BYTE },
++{"fsh",        0, INSN_CLASS_F_AND_ZFH,   "T,A,s",  0, (int) M_FSH, match_never, INSN_MACRO },
++{"fmv.h",      0, INSN_CLASS_F_AND_ZFH,   "D,U",  MATCH_FSGNJ_H, MASK_FSGNJ_H, match_rs1_eq_rs2, INSN_ALIAS },
++{"fneg.h",     0, INSN_CLASS_F_AND_ZFH,   "D,U",  MATCH_FSGNJN_H, MASK_FSGNJN_H, match_rs1_eq_rs2, INSN_ALIAS },
++{"fabs.h",     0, INSN_CLASS_F_AND_ZFH,   "D,U",  MATCH_FSGNJX_H, MASK_FSGNJX_H, match_rs1_eq_rs2, INSN_ALIAS },
++{"fsgnj.h",    0, INSN_CLASS_F_AND_ZFH,   "D,S,T",  MATCH_FSGNJ_H, MASK_FSGNJ_H, match_opcode, 0 },
++{"fsgnjn.h",   0, INSN_CLASS_F_AND_ZFH,   "D,S,T",  MATCH_FSGNJN_H, MASK_FSGNJN_H, match_opcode, 0 },
++{"fsgnjx.h",   0, INSN_CLASS_F_AND_ZFH,   "D,S,T",  MATCH_FSGNJX_H, MASK_FSGNJX_H, match_opcode, 0 },
++{"fadd.h",     0, INSN_CLASS_F_AND_ZFH,   "D,S,T",  MATCH_FADD_H | MASK_RM, MASK_FADD_H | MASK_RM, match_opcode, 0 },
++{"fadd.h",     0, INSN_CLASS_F_AND_ZFH,   "D,S,T,m",  MATCH_FADD_H, MASK_FADD_H, match_opcode, 0 },
++{"fsub.h",     0, INSN_CLASS_F_AND_ZFH,   "D,S,T",  MATCH_FSUB_H | MASK_RM, MASK_FSUB_H | MASK_RM, match_opcode, 0 },
++{"fsub.h",     0, INSN_CLASS_F_AND_ZFH,   "D,S,T,m",  MATCH_FSUB_H, MASK_FSUB_H, match_opcode, 0 },
++{"fmul.h",     0, INSN_CLASS_F_AND_ZFH,   "D,S,T",  MATCH_FMUL_H | MASK_RM, MASK_FMUL_H | MASK_RM, match_opcode, 0 },
++{"fmul.h",     0, INSN_CLASS_F_AND_ZFH,   "D,S,T,m",  MATCH_FMUL_H, MASK_FMUL_H, match_opcode, 0 },
++{"fdiv.h",     0, INSN_CLASS_F_AND_ZFH,   "D,S,T",  MATCH_FDIV_H | MASK_RM, MASK_FDIV_H | MASK_RM, match_opcode, 0 },
++{"fdiv.h",     0, INSN_CLASS_F_AND_ZFH,   "D,S,T,m",  MATCH_FDIV_H, MASK_FDIV_H, match_opcode, 0 },
++{"fsqrt.h",    0, INSN_CLASS_F_AND_ZFH,   "D,S",  MATCH_FSQRT_H | MASK_RM, MASK_FSQRT_H | MASK_RM, match_opcode, 0 },
++{"fsqrt.h",    0, INSN_CLASS_F_AND_ZFH,   "D,S,m",  MATCH_FSQRT_H, MASK_FSQRT_H, match_opcode, 0 },
++{"fmin.h",     0, INSN_CLASS_F_AND_ZFH,   "D,S,T",  MATCH_FMIN_H, MASK_FMIN_H, match_opcode, 0 },
++{"fmax.h",     0, INSN_CLASS_F_AND_ZFH,   "D,S,T",  MATCH_FMAX_H, MASK_FMAX_H, match_opcode, 0 },
++{"fmadd.h",    0, INSN_CLASS_F_AND_ZFH,   "D,S,T,R",  MATCH_FMADD_H | MASK_RM, MASK_FMADD_H | MASK_RM, match_opcode, 0 },
++{"fmadd.h",    0, INSN_CLASS_F_AND_ZFH,   "D,S,T,R,m",  MATCH_FMADD_H, MASK_FMADD_H, match_opcode, 0 },
++{"fnmadd.h",   0, INSN_CLASS_F_AND_ZFH,   "D,S,T,R",  MATCH_FNMADD_H | MASK_RM, MASK_FNMADD_H | MASK_RM, match_opcode, 0 },
++{"fnmadd.h",   0, INSN_CLASS_F_AND_ZFH,   "D,S,T,R,m",  MATCH_FNMADD_H, MASK_FNMADD_H, match_opcode, 0 },
++{"fmsub.h",    0, INSN_CLASS_F_AND_ZFH,   "D,S,T,R",  MATCH_FMSUB_H | MASK_RM, MASK_FMSUB_H | MASK_RM, match_opcode, 0 },
++{"fmsub.h",    0, INSN_CLASS_F_AND_ZFH,   "D,S,T,R,m",  MATCH_FMSUB_H, MASK_FMSUB_H, match_opcode, 0 },
++{"fnmsub.h",   0, INSN_CLASS_F_AND_ZFH,   "D,S,T,R",  MATCH_FNMSUB_H | MASK_RM, MASK_FNMSUB_H | MASK_RM, match_opcode, 0 },
++{"fnmsub.h",   0, INSN_CLASS_F_AND_ZFH,   "D,S,T,R,m",  MATCH_FNMSUB_H, MASK_FNMSUB_H, match_opcode, 0 },
++{"fcvt.w.h",   0, INSN_CLASS_F_AND_ZFH,   "d,S",  MATCH_FCVT_W_H | MASK_RM, MASK_FCVT_W_H | MASK_RM, match_opcode, 0 },
++{"fcvt.w.h",   0, INSN_CLASS_F_AND_ZFH,   "d,S,m",  MATCH_FCVT_W_H, MASK_FCVT_W_H, match_opcode, 0 },
++{"fcvt.wu.h",  0, INSN_CLASS_F_AND_ZFH,   "d,S",  MATCH_FCVT_WU_H | MASK_RM, MASK_FCVT_WU_H | MASK_RM, match_opcode, 0 },
++{"fcvt.wu.h",  0, INSN_CLASS_F_AND_ZFH,   "d,S,m",  MATCH_FCVT_WU_H, MASK_FCVT_WU_H, match_opcode, 0 },
++{"fcvt.h.w",   0, INSN_CLASS_F_AND_ZFH,   "D,s",  MATCH_FCVT_H_W | MASK_RM, MASK_FCVT_H_W | MASK_RM, match_opcode, 0 },
++{"fcvt.h.w",   0, INSN_CLASS_F_AND_ZFH,   "D,s,m",  MATCH_FCVT_H_W, MASK_FCVT_H_W, match_opcode, 0 },
++{"fcvt.h.wu",  0, INSN_CLASS_F_AND_ZFH,   "D,s",  MATCH_FCVT_H_WU | MASK_RM, MASK_FCVT_H_WU | MASK_RM, match_opcode, 0 },
++{"fcvt.h.wu",  0, INSN_CLASS_F_AND_ZFH,   "D,s,m",  MATCH_FCVT_H_WU, MASK_FCVT_H_WU, match_opcode, 0 },
++{"fcvt.s.h",   0, INSN_CLASS_F_AND_ZFH,   "D,S",  MATCH_FCVT_S_H, MASK_FCVT_S_H | MASK_RM, match_opcode, 0 },
++{"fcvt.d.h",   0, INSN_CLASS_D_AND_ZFH,   "D,S",  MATCH_FCVT_D_H, MASK_FCVT_D_H | MASK_RM, match_opcode, 0 },
++{"fcvt.q.h",   0, INSN_CLASS_Q_AND_ZFH,   "D,S",  MATCH_FCVT_Q_H, MASK_FCVT_Q_H | MASK_RM, match_opcode, 0 },
++{"fcvt.h.s",   0, INSN_CLASS_F_AND_ZFH,   "D,S",  MATCH_FCVT_H_S | MASK_RM, MASK_FCVT_H_S | MASK_RM, match_opcode, 0 },
++{"fcvt.h.s",   0, INSN_CLASS_F_AND_ZFH,   "D,S,m",  MATCH_FCVT_H_S, MASK_FCVT_H_S, match_opcode, 0 },
++{"fcvt.h.d",   0, INSN_CLASS_D_AND_ZFH,   "D,S",  MATCH_FCVT_H_D | MASK_RM, MASK_FCVT_H_D | MASK_RM, match_opcode, 0 },
++{"fcvt.h.d",   0, INSN_CLASS_D_AND_ZFH,   "D,S,m",  MATCH_FCVT_H_D, MASK_FCVT_H_D, match_opcode, 0 },
++{"fcvt.h.q",   0, INSN_CLASS_Q_AND_ZFH,   "D,S",  MATCH_FCVT_H_Q | MASK_RM, MASK_FCVT_H_Q | MASK_RM, match_opcode, 0 },
++{"fcvt.h.q",   0, INSN_CLASS_Q_AND_ZFH,   "D,S,m",  MATCH_FCVT_H_Q, MASK_FCVT_H_Q, match_opcode, 0 },
++{"fclass.h",   0, INSN_CLASS_F_AND_ZFH,   "d,S",  MATCH_FCLASS_H, MASK_FCLASS_H, match_opcode, 0 },
++{"feq.h",      0, INSN_CLASS_F_AND_ZFH,   "d,S,T",  MATCH_FEQ_H, MASK_FEQ_H, match_opcode, 0 },
++{"flt.h",      0, INSN_CLASS_F_AND_ZFH,   "d,S,T",  MATCH_FLT_H, MASK_FLT_H, match_opcode, 0 },
++{"fle.h",      0, INSN_CLASS_F_AND_ZFH,   "d,S,T",  MATCH_FLE_H, MASK_FLE_H, match_opcode, 0 },
++{"fgt.h",      0, INSN_CLASS_F_AND_ZFH,   "d,T,S",  MATCH_FLT_H, MASK_FLT_H, match_opcode, 0 },
++{"fge.h",      0, INSN_CLASS_F_AND_ZFH,   "d,T,S",  MATCH_FLE_H, MASK_FLE_H, match_opcode, 0 },
++{"fmv.x.h",    0, INSN_CLASS_F_AND_ZFH,   "d,S",  MATCH_FMV_X_H, MASK_FMV_X_H, match_opcode, 0 },
++{"fmv.h.x",    0, INSN_CLASS_F_AND_ZFH,   "D,s",  MATCH_FMV_H_X, MASK_FMV_H_X, match_opcode, 0 },
++{"fcvt.l.h",  64, INSN_CLASS_F_AND_ZFH,   "d,S",  MATCH_FCVT_L_H | MASK_RM, MASK_FCVT_L_H | MASK_RM, match_opcode, 0 },
++{"fcvt.l.h",  64, INSN_CLASS_F_AND_ZFH,   "d,S,m",  MATCH_FCVT_L_H, MASK_FCVT_L_H, match_opcode, 0 },
++{"fcvt.lu.h", 64, INSN_CLASS_F_AND_ZFH,   "d,S",  MATCH_FCVT_LU_H | MASK_RM, MASK_FCVT_LU_H | MASK_RM, match_opcode, 0 },
++{"fcvt.lu.h", 64, INSN_CLASS_F_AND_ZFH,   "d,S,m",  MATCH_FCVT_LU_H, MASK_FCVT_LU_H, match_opcode, 0 },
++{"fcvt.h.l",  64, INSN_CLASS_F_AND_ZFH,   "D,s",  MATCH_FCVT_H_L | MASK_RM, MASK_FCVT_H_L | MASK_RM, match_opcode, 0 },
++{"fcvt.h.l",  64, INSN_CLASS_F_AND_ZFH,   "D,s,m",  MATCH_FCVT_H_L, MASK_FCVT_H_L, match_opcode, 0 },
++{"fcvt.h.lu", 64, INSN_CLASS_F_AND_ZFH,   "D,s",  MATCH_FCVT_H_LU | MASK_RM, MASK_FCVT_H_L | MASK_RM, match_opcode, 0 },
++{"fcvt.h.lu", 64, INSN_CLASS_F_AND_ZFH,   "D,s,m",  MATCH_FCVT_H_LU, MASK_FCVT_H_LU, match_opcode, 0 },
++
+ /* Single-precision floating-point instruction subset */
+ {"frcsr",     0, INSN_CLASS_F,   "d",  MATCH_FRCSR, MASK_FRCSR, match_opcode, INSN_ALIAS },
+ {"frsr",      0, INSN_CLASS_F,   "d",  MATCH_FRCSR, MASK_FRCSR, match_opcode, INSN_ALIAS },
+@@ -912,6 +1305,804 @@ const struct riscv_opcode riscv_opcodes[] =
+ {"fslw",      64, INSN_CLASS_ZBT,  "d,s,<,r",  MATCH_FSLW, MASK_FSLW, match_opcode, 0 },
+ {"fsrw",      64, INSN_CLASS_ZBT,  "d,s,<,r",  MATCH_FSRW, MASK_FSRW, match_opcode, 0 },
+ {"fsriw",     64, INSN_CLASS_ZBT,  "d,s,<,r",  MATCH_FSRIW, MASK_FSRIW, match_opcode, 0 },
++
++/* RVV */
++{"vsetvl",     0, INSN_CLASS_V,  "d,s,t",  MATCH_VSETVL, MASK_VSETVL, match_opcode, 0},
++{"vsetvli",    0, INSN_CLASS_V,  "d,s,Vc", MATCH_VSETVLI, MASK_VSETVLI, match_opcode, 0},
++{"vsetivli",   0, INSN_CLASS_V,  "d,Z,Vb", MATCH_VSETIVLI, MASK_VSETIVLI, match_opcode, 0},
++
++{"vle1.v",     0, INSN_CLASS_V,  "Vd,0(s)", MATCH_VLE1V, MASK_VLE1V, match_opcode, INSN_DREF },
++{"vse1.v",     0, INSN_CLASS_V,  "Vd,0(s)", MATCH_VSE1V, MASK_VSE1V, match_opcode, INSN_DREF },
++
++{"vle8.v",     0, INSN_CLASS_V,  "Vd,0(s)Vm", MATCH_VLE8V, MASK_VLE8V, match_vd_neq_vm, INSN_DREF },
++{"vle16.v",    0, INSN_CLASS_V,  "Vd,0(s)Vm", MATCH_VLE16V, MASK_VLE16V, match_vd_neq_vm, INSN_DREF },
++{"vle32.v",    0, INSN_CLASS_V,  "Vd,0(s)Vm", MATCH_VLE32V, MASK_VLE32V, match_vd_neq_vm, INSN_DREF },
++{"vle64.v",    0, INSN_CLASS_V,  "Vd,0(s)Vm", MATCH_VLE64V, MASK_VLE64V, match_vd_neq_vm, INSN_DREF },
++
++{"vse8.v",     0, INSN_CLASS_V,  "Vd,0(s)Vm", MATCH_VSE8V, MASK_VSE8V, match_vd_neq_vm, INSN_DREF },
++{"vse16.v",    0, INSN_CLASS_V,  "Vd,0(s)Vm", MATCH_VSE16V, MASK_VSE16V, match_vd_neq_vm, INSN_DREF },
++{"vse32.v",    0, INSN_CLASS_V,  "Vd,0(s)Vm", MATCH_VSE32V, MASK_VSE32V, match_vd_neq_vm, INSN_DREF },
++{"vse64.v",    0, INSN_CLASS_V,  "Vd,0(s)Vm", MATCH_VSE64V, MASK_VSE64V, match_vd_neq_vm, INSN_DREF },
++
++{"vlse8.v",    0, INSN_CLASS_V,  "Vd,0(s),tVm", MATCH_VLSE8V, MASK_VLSE8V, match_vd_neq_vm, INSN_DREF },
++{"vlse16.v",   0, INSN_CLASS_V,  "Vd,0(s),tVm", MATCH_VLSE16V, MASK_VLSE16V, match_vd_neq_vm, INSN_DREF },
++{"vlse32.v",   0, INSN_CLASS_V,  "Vd,0(s),tVm", MATCH_VLSE32V, MASK_VLSE32V, match_vd_neq_vm, INSN_DREF },
++{"vlse64.v",   0, INSN_CLASS_V,  "Vd,0(s),tVm", MATCH_VLSE64V, MASK_VLSE64V, match_vd_neq_vm, INSN_DREF },
++
++{"vsse8.v",    0, INSN_CLASS_V,  "Vd,0(s),tVm", MATCH_VSSE8V, MASK_VSSE8V, match_vd_neq_vm, INSN_DREF },
++{"vsse16.v",   0, INSN_CLASS_V,  "Vd,0(s),tVm", MATCH_VSSE16V, MASK_VSSE16V, match_vd_neq_vm, INSN_DREF },
++{"vsse32.v",   0, INSN_CLASS_V,  "Vd,0(s),tVm", MATCH_VSSE32V, MASK_VSSE32V, match_vd_neq_vm, INSN_DREF },
++{"vsse64.v",   0, INSN_CLASS_V,  "Vd,0(s),tVm", MATCH_VSSE64V, MASK_VSSE64V, match_vd_neq_vm, INSN_DREF },
++
++{"vloxei8.v",   0, INSN_CLASS_V,  "Vd,0(s),VtVm", MATCH_VLOXEI8V, MASK_VLOXEI8V, match_vd_neq_vm, INSN_DREF },
++{"vloxei16.v",  0, INSN_CLASS_V,  "Vd,0(s),VtVm", MATCH_VLOXEI16V, MASK_VLOXEI16V, match_vd_neq_vm, INSN_DREF },
++{"vloxei32.v",  0, INSN_CLASS_V,  "Vd,0(s),VtVm", MATCH_VLOXEI32V, MASK_VLOXEI32V, match_vd_neq_vm, INSN_DREF },
++{"vloxei64.v",  0, INSN_CLASS_V,  "Vd,0(s),VtVm", MATCH_VLOXEI64V, MASK_VLOXEI64V, match_vd_neq_vm, INSN_DREF },
++
++{"vsoxei8.v",   0, INSN_CLASS_V,  "Vd,0(s),VtVm", MATCH_VSOXEI8V, MASK_VSOXEI8V, match_vd_neq_vm, INSN_DREF },
++{"vsoxei16.v",  0, INSN_CLASS_V,  "Vd,0(s),VtVm", MATCH_VSOXEI16V, MASK_VSOXEI16V, match_vd_neq_vm, INSN_DREF },
++{"vsoxei32.v",  0, INSN_CLASS_V,  "Vd,0(s),VtVm", MATCH_VSOXEI32V, MASK_VSOXEI32V, match_vd_neq_vm, INSN_DREF },
++{"vsoxei64.v",  0, INSN_CLASS_V,  "Vd,0(s),VtVm", MATCH_VSOXEI64V, MASK_VSOXEI64V, match_vd_neq_vm, INSN_DREF },
++
++{"vluxei8.v",   0, INSN_CLASS_V,  "Vd,0(s),VtVm", MATCH_VLUXEI8V, MASK_VLUXEI8V, match_vd_neq_vm, INSN_DREF },
++{"vluxei16.v",  0, INSN_CLASS_V,  "Vd,0(s),VtVm", MATCH_VLUXEI16V, MASK_VLUXEI16V, match_vd_neq_vm, INSN_DREF },
++{"vluxei32.v",  0, INSN_CLASS_V,  "Vd,0(s),VtVm", MATCH_VLUXEI32V, MASK_VLUXEI32V, match_vd_neq_vm, INSN_DREF },
++{"vluxei64.v",  0, INSN_CLASS_V,  "Vd,0(s),VtVm", MATCH_VLUXEI64V, MASK_VLUXEI64V, match_vd_neq_vm, INSN_DREF },
++
++{"vsuxei8.v",   0, INSN_CLASS_V,  "Vd,0(s),VtVm", MATCH_VSUXEI8V, MASK_VSUXEI8V, match_vd_neq_vm, INSN_DREF },
++{"vsuxei16.v",  0, INSN_CLASS_V,  "Vd,0(s),VtVm", MATCH_VSUXEI16V, MASK_VSUXEI16V, match_vd_neq_vm, INSN_DREF },
++{"vsuxei32.v",  0, INSN_CLASS_V,  "Vd,0(s),VtVm", MATCH_VSUXEI32V, MASK_VSUXEI32V, match_vd_neq_vm, INSN_DREF },
++{"vsuxei64.v",  0, INSN_CLASS_V,  "Vd,0(s),VtVm", MATCH_VSUXEI64V, MASK_VSUXEI64V, match_vd_neq_vm, INSN_DREF },
++
++{"vle8ff.v",    0, INSN_CLASS_V,  "Vd,0(s)Vm", MATCH_VLE8FFV, MASK_VLE8FFV, match_vd_neq_vm, INSN_DREF },
++{"vle16ff.v",   0, INSN_CLASS_V,  "Vd,0(s)Vm", MATCH_VLE16FFV, MASK_VLE16FFV, match_vd_neq_vm, INSN_DREF },
++{"vle32ff.v",   0, INSN_CLASS_V,  "Vd,0(s)Vm", MATCH_VLE32FFV, MASK_VLE32FFV, match_vd_neq_vm, INSN_DREF },
++{"vle64ff.v",   0, INSN_CLASS_V,  "Vd,0(s)Vm", MATCH_VLE64FFV, MASK_VLE64FFV, match_vd_neq_vm, INSN_DREF },
++
++{"vlseg2e8.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s)Vm", MATCH_VLSEG2E8V, MASK_VLSEG2E8V, match_vd_neq_vm, INSN_DREF },
++{"vsseg2e8.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s)Vm", MATCH_VSSEG2E8V, MASK_VSSEG2E8V, match_vd_neq_vm, INSN_DREF },
++{"vlseg3e8.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s)Vm", MATCH_VLSEG3E8V, MASK_VLSEG3E8V, match_vd_neq_vm, INSN_DREF },
++{"vsseg3e8.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s)Vm", MATCH_VSSEG3E8V, MASK_VSSEG3E8V, match_vd_neq_vm, INSN_DREF },
++{"vlseg4e8.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s)Vm", MATCH_VLSEG4E8V, MASK_VLSEG4E8V, match_vd_neq_vm, INSN_DREF },
++{"vsseg4e8.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s)Vm", MATCH_VSSEG4E8V, MASK_VSSEG4E8V, match_vd_neq_vm, INSN_DREF },
++{"vlseg5e8.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s)Vm", MATCH_VLSEG5E8V, MASK_VLSEG5E8V, match_vd_neq_vm, INSN_DREF },
++{"vsseg5e8.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s)Vm", MATCH_VSSEG5E8V, MASK_VSSEG5E8V, match_vd_neq_vm, INSN_DREF },
++{"vlseg6e8.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s)Vm", MATCH_VLSEG6E8V, MASK_VLSEG6E8V, match_vd_neq_vm, INSN_DREF },
++{"vsseg6e8.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s)Vm", MATCH_VSSEG6E8V, MASK_VSSEG6E8V, match_vd_neq_vm, INSN_DREF },
++{"vlseg7e8.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s)Vm", MATCH_VLSEG7E8V, MASK_VLSEG7E8V, match_vd_neq_vm, INSN_DREF },
++{"vsseg7e8.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s)Vm", MATCH_VSSEG7E8V, MASK_VSSEG7E8V, match_vd_neq_vm, INSN_DREF },
++{"vlseg8e8.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s)Vm", MATCH_VLSEG8E8V, MASK_VLSEG8E8V, match_vd_neq_vm, INSN_DREF },
++{"vsseg8e8.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s)Vm", MATCH_VSSEG8E8V, MASK_VSSEG8E8V, match_vd_neq_vm, INSN_DREF },
++
++{"vlseg2e16.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s)Vm", MATCH_VLSEG2E16V, MASK_VLSEG2E16V, match_vd_neq_vm, INSN_DREF },
++{"vsseg2e16.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s)Vm", MATCH_VSSEG2E16V, MASK_VSSEG2E16V, match_vd_neq_vm, INSN_DREF },
++{"vlseg3e16.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s)Vm", MATCH_VLSEG3E16V, MASK_VLSEG3E16V, match_vd_neq_vm, INSN_DREF },
++{"vsseg3e16.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s)Vm", MATCH_VSSEG3E16V, MASK_VSSEG3E16V, match_vd_neq_vm, INSN_DREF },
++{"vlseg4e16.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s)Vm", MATCH_VLSEG4E16V, MASK_VLSEG4E16V, match_vd_neq_vm, INSN_DREF },
++{"vsseg4e16.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s)Vm", MATCH_VSSEG4E16V, MASK_VSSEG4E16V, match_vd_neq_vm, INSN_DREF },
++{"vlseg5e16.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s)Vm", MATCH_VLSEG5E16V, MASK_VLSEG5E16V, match_vd_neq_vm, INSN_DREF },
++{"vsseg5e16.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s)Vm", MATCH_VSSEG5E16V, MASK_VSSEG5E16V, match_vd_neq_vm, INSN_DREF },
++{"vlseg6e16.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s)Vm", MATCH_VLSEG6E16V, MASK_VLSEG6E16V, match_vd_neq_vm, INSN_DREF },
++{"vsseg6e16.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s)Vm", MATCH_VSSEG6E16V, MASK_VSSEG6E16V, match_vd_neq_vm, INSN_DREF },
++{"vlseg7e16.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s)Vm", MATCH_VLSEG7E16V, MASK_VLSEG7E16V, match_vd_neq_vm, INSN_DREF },
++{"vsseg7e16.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s)Vm", MATCH_VSSEG7E16V, MASK_VSSEG7E16V, match_vd_neq_vm, INSN_DREF },
++{"vlseg8e16.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s)Vm", MATCH_VLSEG8E16V, MASK_VLSEG8E16V, match_vd_neq_vm, INSN_DREF },
++{"vsseg8e16.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s)Vm", MATCH_VSSEG8E16V, MASK_VSSEG8E16V, match_vd_neq_vm, INSN_DREF },
++
++{"vlseg2e32.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s)Vm", MATCH_VLSEG2E32V, MASK_VLSEG2E32V, match_vd_neq_vm, INSN_DREF },
++{"vsseg2e32.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s)Vm", MATCH_VSSEG2E32V, MASK_VSSEG2E32V, match_vd_neq_vm, INSN_DREF },
++{"vlseg3e32.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s)Vm", MATCH_VLSEG3E32V, MASK_VLSEG3E32V, match_vd_neq_vm, INSN_DREF },
++{"vsseg3e32.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s)Vm", MATCH_VSSEG3E32V, MASK_VSSEG3E32V, match_vd_neq_vm, INSN_DREF },
++{"vlseg4e32.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s)Vm", MATCH_VLSEG4E32V, MASK_VLSEG4E32V, match_vd_neq_vm, INSN_DREF },
++{"vsseg4e32.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s)Vm", MATCH_VSSEG4E32V, MASK_VSSEG4E32V, match_vd_neq_vm, INSN_DREF },
++{"vlseg5e32.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s)Vm", MATCH_VLSEG5E32V, MASK_VLSEG5E32V, match_vd_neq_vm, INSN_DREF },
++{"vsseg5e32.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s)Vm", MATCH_VSSEG5E32V, MASK_VSSEG5E32V, match_vd_neq_vm, INSN_DREF },
++{"vlseg6e32.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s)Vm", MATCH_VLSEG6E32V, MASK_VLSEG6E32V, match_vd_neq_vm, INSN_DREF },
++{"vsseg6e32.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s)Vm", MATCH_VSSEG6E32V, MASK_VSSEG6E32V, match_vd_neq_vm, INSN_DREF },
++{"vlseg7e32.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s)Vm", MATCH_VLSEG7E32V, MASK_VLSEG7E32V, match_vd_neq_vm, INSN_DREF },
++{"vsseg7e32.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s)Vm", MATCH_VSSEG7E32V, MASK_VSSEG7E32V, match_vd_neq_vm, INSN_DREF },
++{"vlseg8e32.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s)Vm", MATCH_VLSEG8E32V, MASK_VLSEG8E32V, match_vd_neq_vm, INSN_DREF },
++{"vsseg8e32.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s)Vm", MATCH_VSSEG8E32V, MASK_VSSEG8E32V, match_vd_neq_vm, INSN_DREF },
++
++{"vlseg2e64.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s)Vm", MATCH_VLSEG2E64V, MASK_VLSEG2E64V, match_vd_neq_vm, INSN_DREF },
++{"vsseg2e64.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s)Vm", MATCH_VSSEG2E64V, MASK_VSSEG2E64V, match_vd_neq_vm, INSN_DREF },
++{"vlseg3e64.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s)Vm", MATCH_VLSEG3E64V, MASK_VLSEG3E64V, match_vd_neq_vm, INSN_DREF },
++{"vsseg3e64.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s)Vm", MATCH_VSSEG3E64V, MASK_VSSEG3E64V, match_vd_neq_vm, INSN_DREF },
++{"vlseg4e64.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s)Vm", MATCH_VLSEG4E64V, MASK_VLSEG4E64V, match_vd_neq_vm, INSN_DREF },
++{"vsseg4e64.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s)Vm", MATCH_VSSEG4E64V, MASK_VSSEG4E64V, match_vd_neq_vm, INSN_DREF },
++{"vlseg5e64.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s)Vm", MATCH_VLSEG5E64V, MASK_VLSEG5E64V, match_vd_neq_vm, INSN_DREF },
++{"vsseg5e64.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s)Vm", MATCH_VSSEG5E64V, MASK_VSSEG5E64V, match_vd_neq_vm, INSN_DREF },
++{"vlseg6e64.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s)Vm", MATCH_VLSEG6E64V, MASK_VLSEG6E64V, match_vd_neq_vm, INSN_DREF },
++{"vsseg6e64.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s)Vm", MATCH_VSSEG6E64V, MASK_VSSEG6E64V, match_vd_neq_vm, INSN_DREF },
++{"vlseg7e64.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s)Vm", MATCH_VLSEG7E64V, MASK_VLSEG7E64V, match_vd_neq_vm, INSN_DREF },
++{"vsseg7e64.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s)Vm", MATCH_VSSEG7E64V, MASK_VSSEG7E64V, match_vd_neq_vm, INSN_DREF },
++{"vlseg8e64.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s)Vm", MATCH_VLSEG8E64V, MASK_VLSEG8E64V, match_vd_neq_vm, INSN_DREF },
++{"vsseg8e64.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s)Vm", MATCH_VSSEG8E64V, MASK_VSSEG8E64V, match_vd_neq_vm, INSN_DREF },
++
++{"vlsseg2e8.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),tVm", MATCH_VLSSEG2E8V, MASK_VLSSEG2E8V, match_vd_neq_vm, INSN_DREF },
++{"vssseg2e8.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),tVm", MATCH_VSSSEG2E8V, MASK_VSSSEG2E8V, match_vd_neq_vm, INSN_DREF },
++{"vlsseg3e8.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),tVm", MATCH_VLSSEG3E8V, MASK_VLSSEG3E8V, match_vd_neq_vm, INSN_DREF },
++{"vssseg3e8.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),tVm", MATCH_VSSSEG3E8V, MASK_VSSSEG3E8V, match_vd_neq_vm, INSN_DREF },
++{"vlsseg4e8.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),tVm", MATCH_VLSSEG4E8V, MASK_VLSSEG4E8V, match_vd_neq_vm, INSN_DREF },
++{"vssseg4e8.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),tVm", MATCH_VSSSEG4E8V, MASK_VSSSEG4E8V, match_vd_neq_vm, INSN_DREF },
++{"vlsseg5e8.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),tVm", MATCH_VLSSEG5E8V, MASK_VLSSEG5E8V, match_vd_neq_vm, INSN_DREF },
++{"vssseg5e8.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),tVm", MATCH_VSSSEG5E8V, MASK_VSSSEG5E8V, match_vd_neq_vm, INSN_DREF },
++{"vlsseg6e8.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),tVm", MATCH_VLSSEG6E8V, MASK_VLSSEG6E8V, match_vd_neq_vm, INSN_DREF },
++{"vssseg6e8.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),tVm", MATCH_VSSSEG6E8V, MASK_VSSSEG6E8V, match_vd_neq_vm, INSN_DREF },
++{"vlsseg7e8.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),tVm", MATCH_VLSSEG7E8V, MASK_VLSSEG7E8V, match_vd_neq_vm, INSN_DREF },
++{"vssseg7e8.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),tVm", MATCH_VSSSEG7E8V, MASK_VSSSEG7E8V, match_vd_neq_vm, INSN_DREF },
++{"vlsseg8e8.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),tVm", MATCH_VLSSEG8E8V, MASK_VLSSEG8E8V, match_vd_neq_vm, INSN_DREF },
++{"vssseg8e8.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),tVm", MATCH_VSSSEG8E8V, MASK_VSSSEG8E8V, match_vd_neq_vm, INSN_DREF },
++
++{"vlsseg2e16.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),tVm", MATCH_VLSSEG2E16V, MASK_VLSSEG2E16V, match_vd_neq_vm, INSN_DREF },
++{"vssseg2e16.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),tVm", MATCH_VSSSEG2E16V, MASK_VSSSEG2E16V, match_vd_neq_vm, INSN_DREF },
++{"vlsseg3e16.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),tVm", MATCH_VLSSEG3E16V, MASK_VLSSEG3E16V, match_vd_neq_vm, INSN_DREF },
++{"vssseg3e16.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),tVm", MATCH_VSSSEG3E16V, MASK_VSSSEG3E16V, match_vd_neq_vm, INSN_DREF },
++{"vlsseg4e16.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),tVm", MATCH_VLSSEG4E16V, MASK_VLSSEG4E16V, match_vd_neq_vm, INSN_DREF },
++{"vssseg4e16.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),tVm", MATCH_VSSSEG4E16V, MASK_VSSSEG4E16V, match_vd_neq_vm, INSN_DREF },
++{"vlsseg5e16.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),tVm", MATCH_VLSSEG5E16V, MASK_VLSSEG5E16V, match_vd_neq_vm, INSN_DREF },
++{"vssseg5e16.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),tVm", MATCH_VSSSEG5E16V, MASK_VSSSEG5E16V, match_vd_neq_vm, INSN_DREF },
++{"vlsseg6e16.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),tVm", MATCH_VLSSEG6E16V, MASK_VLSSEG6E16V, match_vd_neq_vm, INSN_DREF },
++{"vssseg6e16.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),tVm", MATCH_VSSSEG6E16V, MASK_VSSSEG6E16V, match_vd_neq_vm, INSN_DREF },
++{"vlsseg7e16.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),tVm", MATCH_VLSSEG7E16V, MASK_VLSSEG7E16V, match_vd_neq_vm, INSN_DREF },
++{"vssseg7e16.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),tVm", MATCH_VSSSEG7E16V, MASK_VSSSEG7E16V, match_vd_neq_vm, INSN_DREF },
++{"vlsseg8e16.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),tVm", MATCH_VLSSEG8E16V, MASK_VLSSEG8E16V, match_vd_neq_vm, INSN_DREF },
++{"vssseg8e16.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),tVm", MATCH_VSSSEG8E16V, MASK_VSSSEG8E16V, match_vd_neq_vm, INSN_DREF },
++
++{"vlsseg2e32.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),tVm", MATCH_VLSSEG2E32V, MASK_VLSSEG2E32V, match_vd_neq_vm, INSN_DREF },
++{"vssseg2e32.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),tVm", MATCH_VSSSEG2E32V, MASK_VSSSEG2E32V, match_vd_neq_vm, INSN_DREF },
++{"vlsseg3e32.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),tVm", MATCH_VLSSEG3E32V, MASK_VLSSEG3E32V, match_vd_neq_vm, INSN_DREF },
++{"vssseg3e32.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),tVm", MATCH_VSSSEG3E32V, MASK_VSSSEG3E32V, match_vd_neq_vm, INSN_DREF },
++{"vlsseg4e32.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),tVm", MATCH_VLSSEG4E32V, MASK_VLSSEG4E32V, match_vd_neq_vm, INSN_DREF },
++{"vssseg4e32.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),tVm", MATCH_VSSSEG4E32V, MASK_VSSSEG4E32V, match_vd_neq_vm, INSN_DREF },
++{"vlsseg5e32.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),tVm", MATCH_VLSSEG5E32V, MASK_VLSSEG5E32V, match_vd_neq_vm, INSN_DREF },
++{"vssseg5e32.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),tVm", MATCH_VSSSEG5E32V, MASK_VSSSEG5E32V, match_vd_neq_vm, INSN_DREF },
++{"vlsseg6e32.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),tVm", MATCH_VLSSEG6E32V, MASK_VLSSEG6E32V, match_vd_neq_vm, INSN_DREF },
++{"vssseg6e32.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),tVm", MATCH_VSSSEG6E32V, MASK_VSSSEG6E32V, match_vd_neq_vm, INSN_DREF },
++{"vlsseg7e32.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),tVm", MATCH_VLSSEG7E32V, MASK_VLSSEG7E32V, match_vd_neq_vm, INSN_DREF },
++{"vssseg7e32.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),tVm", MATCH_VSSSEG7E32V, MASK_VSSSEG7E32V, match_vd_neq_vm, INSN_DREF },
++{"vlsseg8e32.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),tVm", MATCH_VLSSEG8E32V, MASK_VLSSEG8E32V, match_vd_neq_vm, INSN_DREF },
++{"vssseg8e32.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),tVm", MATCH_VSSSEG8E32V, MASK_VSSSEG8E32V, match_vd_neq_vm, INSN_DREF },
++
++{"vlsseg2e64.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),tVm", MATCH_VLSSEG2E64V, MASK_VLSSEG2E64V, match_vd_neq_vm, INSN_DREF },
++{"vssseg2e64.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),tVm", MATCH_VSSSEG2E64V, MASK_VSSSEG2E64V, match_vd_neq_vm, INSN_DREF },
++{"vlsseg3e64.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),tVm", MATCH_VLSSEG3E64V, MASK_VLSSEG3E64V, match_vd_neq_vm, INSN_DREF },
++{"vssseg3e64.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),tVm", MATCH_VSSSEG3E64V, MASK_VSSSEG3E64V, match_vd_neq_vm, INSN_DREF },
++{"vlsseg4e64.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),tVm", MATCH_VLSSEG4E64V, MASK_VLSSEG4E64V, match_vd_neq_vm, INSN_DREF },
++{"vssseg4e64.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),tVm", MATCH_VSSSEG4E64V, MASK_VSSSEG4E64V, match_vd_neq_vm, INSN_DREF },
++{"vlsseg5e64.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),tVm", MATCH_VLSSEG5E64V, MASK_VLSSEG5E64V, match_vd_neq_vm, INSN_DREF },
++{"vssseg5e64.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),tVm", MATCH_VSSSEG5E64V, MASK_VSSSEG5E64V, match_vd_neq_vm, INSN_DREF },
++{"vlsseg6e64.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),tVm", MATCH_VLSSEG6E64V, MASK_VLSSEG6E64V, match_vd_neq_vm, INSN_DREF },
++{"vssseg6e64.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),tVm", MATCH_VSSSEG6E64V, MASK_VSSSEG6E64V, match_vd_neq_vm, INSN_DREF },
++{"vlsseg7e64.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),tVm", MATCH_VLSSEG7E64V, MASK_VLSSEG7E64V, match_vd_neq_vm, INSN_DREF },
++{"vssseg7e64.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),tVm", MATCH_VSSSEG7E64V, MASK_VSSSEG7E64V, match_vd_neq_vm, INSN_DREF },
++{"vlsseg8e64.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),tVm", MATCH_VLSSEG8E64V, MASK_VLSSEG8E64V, match_vd_neq_vm, INSN_DREF },
++{"vssseg8e64.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),tVm", MATCH_VSSSEG8E64V, MASK_VSSSEG8E64V, match_vd_neq_vm, INSN_DREF },
++
++{"vloxseg2ei8.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),VtVm", MATCH_VLOXSEG2EI8V, MASK_VLOXSEG2EI8V, match_vd_neq_vs2_neq_vm, INSN_DREF },
++{"vsoxseg2ei8.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),VtVm", MATCH_VSOXSEG2EI8V, MASK_VSOXSEG2EI8V, match_vd_neq_vs2_neq_vm, INSN_DREF },
++{"vloxseg3ei8.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),VtVm", MATCH_VLOXSEG3EI8V, MASK_VLOXSEG3EI8V, match_vd_neq_vs2_neq_vm, INSN_DREF },
++{"vsoxseg3ei8.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),VtVm", MATCH_VSOXSEG3EI8V, MASK_VSOXSEG3EI8V, match_vd_neq_vs2_neq_vm, INSN_DREF },
++{"vloxseg4ei8.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),VtVm", MATCH_VLOXSEG4EI8V, MASK_VLOXSEG4EI8V, match_vd_neq_vs2_neq_vm, INSN_DREF },
++{"vsoxseg4ei8.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),VtVm", MATCH_VSOXSEG4EI8V, MASK_VSOXSEG4EI8V, match_vd_neq_vs2_neq_vm, INSN_DREF },
++{"vloxseg5ei8.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),VtVm", MATCH_VLOXSEG5EI8V, MASK_VLOXSEG5EI8V, match_vd_neq_vs2_neq_vm, INSN_DREF },
++{"vsoxseg5ei8.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),VtVm", MATCH_VSOXSEG5EI8V, MASK_VSOXSEG5EI8V, match_vd_neq_vs2_neq_vm, INSN_DREF },
++{"vloxseg6ei8.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),VtVm", MATCH_VLOXSEG6EI8V, MASK_VLOXSEG6EI8V, match_vd_neq_vs2_neq_vm, INSN_DREF },
++{"vsoxseg6ei8.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),VtVm", MATCH_VSOXSEG6EI8V, MASK_VSOXSEG6EI8V, match_vd_neq_vs2_neq_vm, INSN_DREF },
++{"vloxseg7ei8.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),VtVm", MATCH_VLOXSEG7EI8V, MASK_VLOXSEG7EI8V, match_vd_neq_vs2_neq_vm, INSN_DREF },
++{"vsoxseg7ei8.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),VtVm", MATCH_VSOXSEG7EI8V, MASK_VSOXSEG7EI8V, match_vd_neq_vs2_neq_vm, INSN_DREF },
++{"vloxseg8ei8.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),VtVm", MATCH_VLOXSEG8EI8V, MASK_VLOXSEG8EI8V, match_vd_neq_vs2_neq_vm, INSN_DREF },
++{"vsoxseg8ei8.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),VtVm", MATCH_VSOXSEG8EI8V, MASK_VSOXSEG8EI8V, match_vd_neq_vs2_neq_vm, INSN_DREF },
++
++{"vloxseg2ei16.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),VtVm", MATCH_VLOXSEG2EI16V, MASK_VLOXSEG2EI16V, match_vd_neq_vs2_neq_vm, INSN_DREF },
++{"vsoxseg2ei16.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),VtVm", MATCH_VSOXSEG2EI16V, MASK_VSOXSEG2EI16V, match_vd_neq_vs2_neq_vm, INSN_DREF },
++{"vloxseg3ei16.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),VtVm", MATCH_VLOXSEG3EI16V, MASK_VLOXSEG3EI16V, match_vd_neq_vs2_neq_vm, INSN_DREF },
++{"vsoxseg3ei16.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),VtVm", MATCH_VSOXSEG3EI16V, MASK_VSOXSEG3EI16V, match_vd_neq_vs2_neq_vm, INSN_DREF },
++{"vloxseg4ei16.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),VtVm", MATCH_VLOXSEG4EI16V, MASK_VLOXSEG4EI16V, match_vd_neq_vs2_neq_vm, INSN_DREF },
++{"vsoxseg4ei16.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),VtVm", MATCH_VSOXSEG4EI16V, MASK_VSOXSEG4EI16V, match_vd_neq_vs2_neq_vm, INSN_DREF },
++{"vloxseg5ei16.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),VtVm", MATCH_VLOXSEG5EI16V, MASK_VLOXSEG5EI16V, match_vd_neq_vs2_neq_vm, INSN_DREF },
++{"vsoxseg5ei16.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),VtVm", MATCH_VSOXSEG5EI16V, MASK_VSOXSEG5EI16V, match_vd_neq_vs2_neq_vm, INSN_DREF },
++{"vloxseg6ei16.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),VtVm", MATCH_VLOXSEG6EI16V, MASK_VLOXSEG6EI16V, match_vd_neq_vs2_neq_vm, INSN_DREF },
++{"vsoxseg6ei16.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),VtVm", MATCH_VSOXSEG6EI16V, MASK_VSOXSEG6EI16V, match_vd_neq_vs2_neq_vm, INSN_DREF },
++{"vloxseg7ei16.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),VtVm", MATCH_VLOXSEG7EI16V, MASK_VLOXSEG7EI16V, match_vd_neq_vs2_neq_vm, INSN_DREF },
++{"vsoxseg7ei16.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),VtVm", MATCH_VSOXSEG7EI16V, MASK_VSOXSEG7EI16V, match_vd_neq_vs2_neq_vm, INSN_DREF },
++{"vloxseg8ei16.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),VtVm", MATCH_VLOXSEG8EI16V, MASK_VLOXSEG8EI16V, match_vd_neq_vs2_neq_vm, INSN_DREF },
++{"vsoxseg8ei16.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),VtVm", MATCH_VSOXSEG8EI16V, MASK_VSOXSEG8EI16V, match_vd_neq_vs2_neq_vm, INSN_DREF },
++
++{"vloxseg2ei32.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),VtVm", MATCH_VLOXSEG2EI32V, MASK_VLOXSEG2EI32V, match_vd_neq_vs2_neq_vm, INSN_DREF },
++{"vsoxseg2ei32.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),VtVm", MATCH_VSOXSEG2EI32V, MASK_VSOXSEG2EI32V, match_vd_neq_vs2_neq_vm, INSN_DREF },
++{"vloxseg3ei32.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),VtVm", MATCH_VLOXSEG3EI32V, MASK_VLOXSEG3EI32V, match_vd_neq_vs2_neq_vm, INSN_DREF },
++{"vsoxseg3ei32.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),VtVm", MATCH_VSOXSEG3EI32V, MASK_VSOXSEG3EI32V, match_vd_neq_vs2_neq_vm, INSN_DREF },
++{"vloxseg4ei32.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),VtVm", MATCH_VLOXSEG4EI32V, MASK_VLOXSEG4EI32V, match_vd_neq_vs2_neq_vm, INSN_DREF },
++{"vsoxseg4ei32.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),VtVm", MATCH_VSOXSEG4EI32V, MASK_VSOXSEG4EI32V, match_vd_neq_vs2_neq_vm, INSN_DREF },
++{"vloxseg5ei32.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),VtVm", MATCH_VLOXSEG5EI32V, MASK_VLOXSEG5EI32V, match_vd_neq_vs2_neq_vm, INSN_DREF },
++{"vsoxseg5ei32.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),VtVm", MATCH_VSOXSEG5EI32V, MASK_VSOXSEG5EI32V, match_vd_neq_vs2_neq_vm, INSN_DREF },
++{"vloxseg6ei32.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),VtVm", MATCH_VLOXSEG6EI32V, MASK_VLOXSEG6EI32V, match_vd_neq_vs2_neq_vm, INSN_DREF },
++{"vsoxseg6ei32.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),VtVm", MATCH_VSOXSEG6EI32V, MASK_VSOXSEG6EI32V, match_vd_neq_vs2_neq_vm, INSN_DREF },
++{"vloxseg7ei32.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),VtVm", MATCH_VLOXSEG7EI32V, MASK_VLOXSEG7EI32V, match_vd_neq_vs2_neq_vm, INSN_DREF },
++{"vsoxseg7ei32.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),VtVm", MATCH_VSOXSEG7EI32V, MASK_VSOXSEG7EI32V, match_vd_neq_vs2_neq_vm, INSN_DREF },
++{"vloxseg8ei32.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),VtVm", MATCH_VLOXSEG8EI32V, MASK_VLOXSEG8EI32V, match_vd_neq_vs2_neq_vm, INSN_DREF },
++{"vsoxseg8ei32.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),VtVm", MATCH_VSOXSEG8EI32V, MASK_VSOXSEG8EI32V, match_vd_neq_vs2_neq_vm, INSN_DREF },
++
++{"vloxseg2ei64.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),VtVm", MATCH_VLOXSEG2EI64V, MASK_VLOXSEG2EI64V, match_vd_neq_vs2_neq_vm, INSN_DREF },
++{"vsoxseg2ei64.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),VtVm", MATCH_VSOXSEG2EI64V, MASK_VSOXSEG2EI64V, match_vd_neq_vs2_neq_vm, INSN_DREF },
++{"vloxseg3ei64.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),VtVm", MATCH_VLOXSEG3EI64V, MASK_VLOXSEG3EI64V, match_vd_neq_vs2_neq_vm, INSN_DREF },
++{"vsoxseg3ei64.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),VtVm", MATCH_VSOXSEG3EI64V, MASK_VSOXSEG3EI64V, match_vd_neq_vs2_neq_vm, INSN_DREF },
++{"vloxseg4ei64.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),VtVm", MATCH_VLOXSEG4EI64V, MASK_VLOXSEG4EI64V, match_vd_neq_vs2_neq_vm, INSN_DREF },
++{"vsoxseg4ei64.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),VtVm", MATCH_VSOXSEG4EI64V, MASK_VSOXSEG4EI64V, match_vd_neq_vs2_neq_vm, INSN_DREF },
++{"vloxseg5ei64.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),VtVm", MATCH_VLOXSEG5EI64V, MASK_VLOXSEG5EI64V, match_vd_neq_vs2_neq_vm, INSN_DREF },
++{"vsoxseg5ei64.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),VtVm", MATCH_VSOXSEG5EI64V, MASK_VSOXSEG5EI64V, match_vd_neq_vs2_neq_vm, INSN_DREF },
++{"vloxseg6ei64.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),VtVm", MATCH_VLOXSEG6EI64V, MASK_VLOXSEG6EI64V, match_vd_neq_vs2_neq_vm, INSN_DREF },
++{"vsoxseg6ei64.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),VtVm", MATCH_VSOXSEG6EI64V, MASK_VSOXSEG6EI64V, match_vd_neq_vs2_neq_vm, INSN_DREF },
++{"vloxseg7ei64.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),VtVm", MATCH_VLOXSEG7EI64V, MASK_VLOXSEG7EI64V, match_vd_neq_vs2_neq_vm, INSN_DREF },
++{"vsoxseg7ei64.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),VtVm", MATCH_VSOXSEG7EI64V, MASK_VSOXSEG7EI64V, match_vd_neq_vs2_neq_vm, INSN_DREF },
++{"vloxseg8ei64.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),VtVm", MATCH_VLOXSEG8EI64V, MASK_VLOXSEG8EI64V, match_vd_neq_vs2_neq_vm, INSN_DREF },
++{"vsoxseg8ei64.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),VtVm", MATCH_VSOXSEG8EI64V, MASK_VSOXSEG8EI64V, match_vd_neq_vs2_neq_vm, INSN_DREF },
++
++{"vluxseg2ei8.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),VtVm", MATCH_VLUXSEG2EI8V, MASK_VLUXSEG2EI8V, match_vd_neq_vs2_neq_vm, INSN_DREF },
++{"vsuxseg2ei8.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),VtVm", MATCH_VSUXSEG2EI8V, MASK_VSUXSEG2EI8V, match_vd_neq_vs2_neq_vm, INSN_DREF },
++{"vluxseg3ei8.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),VtVm", MATCH_VLUXSEG3EI8V, MASK_VLUXSEG3EI8V, match_vd_neq_vs2_neq_vm, INSN_DREF },
++{"vsuxseg3ei8.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),VtVm", MATCH_VSUXSEG3EI8V, MASK_VSUXSEG3EI8V, match_vd_neq_vs2_neq_vm, INSN_DREF },
++{"vluxseg4ei8.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),VtVm", MATCH_VLUXSEG4EI8V, MASK_VLUXSEG4EI8V, match_vd_neq_vs2_neq_vm, INSN_DREF },
++{"vsuxseg4ei8.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),VtVm", MATCH_VSUXSEG4EI8V, MASK_VSUXSEG4EI8V, match_vd_neq_vs2_neq_vm, INSN_DREF },
++{"vluxseg5ei8.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),VtVm", MATCH_VLUXSEG5EI8V, MASK_VLUXSEG5EI8V, match_vd_neq_vs2_neq_vm, INSN_DREF },
++{"vsuxseg5ei8.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),VtVm", MATCH_VSUXSEG5EI8V, MASK_VSUXSEG5EI8V, match_vd_neq_vs2_neq_vm, INSN_DREF },
++{"vluxseg6ei8.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),VtVm", MATCH_VLUXSEG6EI8V, MASK_VLUXSEG6EI8V, match_vd_neq_vs2_neq_vm, INSN_DREF },
++{"vsuxseg6ei8.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),VtVm", MATCH_VSUXSEG6EI8V, MASK_VSUXSEG6EI8V, match_vd_neq_vs2_neq_vm, INSN_DREF },
++{"vluxseg7ei8.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),VtVm", MATCH_VLUXSEG7EI8V, MASK_VLUXSEG7EI8V, match_vd_neq_vs2_neq_vm, INSN_DREF },
++{"vsuxseg7ei8.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),VtVm", MATCH_VSUXSEG7EI8V, MASK_VSUXSEG7EI8V, match_vd_neq_vs2_neq_vm, INSN_DREF },
++{"vluxseg8ei8.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),VtVm", MATCH_VLUXSEG8EI8V, MASK_VLUXSEG8EI8V, match_vd_neq_vs2_neq_vm, INSN_DREF },
++{"vsuxseg8ei8.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),VtVm", MATCH_VSUXSEG8EI8V, MASK_VSUXSEG8EI8V, match_vd_neq_vs2_neq_vm, INSN_DREF },
++
++{"vluxseg2ei16.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),VtVm", MATCH_VLUXSEG2EI16V, MASK_VLUXSEG2EI16V, match_vd_neq_vs2_neq_vm, INSN_DREF },
++{"vsuxseg2ei16.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),VtVm", MATCH_VSUXSEG2EI16V, MASK_VSUXSEG2EI16V, match_vd_neq_vs2_neq_vm, INSN_DREF },
++{"vluxseg3ei16.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),VtVm", MATCH_VLUXSEG3EI16V, MASK_VLUXSEG3EI16V, match_vd_neq_vs2_neq_vm, INSN_DREF },
++{"vsuxseg3ei16.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),VtVm", MATCH_VSUXSEG3EI16V, MASK_VSUXSEG3EI16V, match_vd_neq_vs2_neq_vm, INSN_DREF },
++{"vluxseg4ei16.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),VtVm", MATCH_VLUXSEG4EI16V, MASK_VLUXSEG4EI16V, match_vd_neq_vs2_neq_vm, INSN_DREF },
++{"vsuxseg4ei16.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),VtVm", MATCH_VSUXSEG4EI16V, MASK_VSUXSEG4EI16V, match_vd_neq_vs2_neq_vm, INSN_DREF },
++{"vluxseg5ei16.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),VtVm", MATCH_VLUXSEG5EI16V, MASK_VLUXSEG5EI16V, match_vd_neq_vs2_neq_vm, INSN_DREF },
++{"vsuxseg5ei16.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),VtVm", MATCH_VSUXSEG5EI16V, MASK_VSUXSEG5EI16V, match_vd_neq_vs2_neq_vm, INSN_DREF },
++{"vluxseg6ei16.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),VtVm", MATCH_VLUXSEG6EI16V, MASK_VLUXSEG6EI16V, match_vd_neq_vs2_neq_vm, INSN_DREF },
++{"vsuxseg6ei16.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),VtVm", MATCH_VSUXSEG6EI16V, MASK_VSUXSEG6EI16V, match_vd_neq_vs2_neq_vm, INSN_DREF },
++{"vluxseg7ei16.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),VtVm", MATCH_VLUXSEG7EI16V, MASK_VLUXSEG7EI16V, match_vd_neq_vs2_neq_vm, INSN_DREF },
++{"vsuxseg7ei16.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),VtVm", MATCH_VSUXSEG7EI16V, MASK_VSUXSEG7EI16V, match_vd_neq_vs2_neq_vm, INSN_DREF },
++{"vluxseg8ei16.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),VtVm", MATCH_VLUXSEG8EI16V, MASK_VLUXSEG8EI16V, match_vd_neq_vs2_neq_vm, INSN_DREF },
++{"vsuxseg8ei16.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),VtVm", MATCH_VSUXSEG8EI16V, MASK_VSUXSEG8EI16V, match_vd_neq_vs2_neq_vm, INSN_DREF },
++
++{"vluxseg2ei32.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),VtVm", MATCH_VLUXSEG2EI32V, MASK_VLUXSEG2EI32V, match_vd_neq_vs2_neq_vm, INSN_DREF },
++{"vsuxseg2ei32.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),VtVm", MATCH_VSUXSEG2EI32V, MASK_VSUXSEG2EI32V, match_vd_neq_vs2_neq_vm, INSN_DREF },
++{"vluxseg3ei32.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),VtVm", MATCH_VLUXSEG3EI32V, MASK_VLUXSEG3EI32V, match_vd_neq_vs2_neq_vm, INSN_DREF },
++{"vsuxseg3ei32.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),VtVm", MATCH_VSUXSEG3EI32V, MASK_VSUXSEG3EI32V, match_vd_neq_vs2_neq_vm, INSN_DREF },
++{"vluxseg4ei32.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),VtVm", MATCH_VLUXSEG4EI32V, MASK_VLUXSEG4EI32V, match_vd_neq_vs2_neq_vm, INSN_DREF },
++{"vsuxseg4ei32.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),VtVm", MATCH_VSUXSEG4EI32V, MASK_VSUXSEG4EI32V, match_vd_neq_vs2_neq_vm, INSN_DREF },
++{"vluxseg5ei32.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),VtVm", MATCH_VLUXSEG5EI32V, MASK_VLUXSEG5EI32V, match_vd_neq_vs2_neq_vm, INSN_DREF },
++{"vsuxseg5ei32.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),VtVm", MATCH_VSUXSEG5EI32V, MASK_VSUXSEG5EI32V, match_vd_neq_vs2_neq_vm, INSN_DREF },
++{"vluxseg6ei32.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),VtVm", MATCH_VLUXSEG6EI32V, MASK_VLUXSEG6EI32V, match_vd_neq_vs2_neq_vm, INSN_DREF },
++{"vsuxseg6ei32.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),VtVm", MATCH_VSUXSEG6EI32V, MASK_VSUXSEG6EI32V, match_vd_neq_vs2_neq_vm, INSN_DREF },
++{"vluxseg7ei32.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),VtVm", MATCH_VLUXSEG7EI32V, MASK_VLUXSEG7EI32V, match_vd_neq_vs2_neq_vm, INSN_DREF },
++{"vsuxseg7ei32.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),VtVm", MATCH_VSUXSEG7EI32V, MASK_VSUXSEG7EI32V, match_vd_neq_vs2_neq_vm, INSN_DREF },
++{"vluxseg8ei32.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),VtVm", MATCH_VLUXSEG8EI32V, MASK_VLUXSEG8EI32V, match_vd_neq_vs2_neq_vm, INSN_DREF },
++{"vsuxseg8ei32.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),VtVm", MATCH_VSUXSEG8EI32V, MASK_VSUXSEG8EI32V, match_vd_neq_vs2_neq_vm, INSN_DREF },
++
++{"vluxseg2ei64.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),VtVm", MATCH_VLUXSEG2EI64V, MASK_VLUXSEG2EI64V, match_vd_neq_vs2_neq_vm, INSN_DREF },
++{"vsuxseg2ei64.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),VtVm", MATCH_VSUXSEG2EI64V, MASK_VSUXSEG2EI64V, match_vd_neq_vs2_neq_vm, INSN_DREF },
++{"vluxseg3ei64.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),VtVm", MATCH_VLUXSEG3EI64V, MASK_VLUXSEG3EI64V, match_vd_neq_vs2_neq_vm, INSN_DREF },
++{"vsuxseg3ei64.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),VtVm", MATCH_VSUXSEG3EI64V, MASK_VSUXSEG3EI64V, match_vd_neq_vs2_neq_vm, INSN_DREF },
++{"vluxseg4ei64.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),VtVm", MATCH_VLUXSEG4EI64V, MASK_VLUXSEG4EI64V, match_vd_neq_vs2_neq_vm, INSN_DREF },
++{"vsuxseg4ei64.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),VtVm", MATCH_VSUXSEG4EI64V, MASK_VSUXSEG4EI64V, match_vd_neq_vs2_neq_vm, INSN_DREF },
++{"vluxseg5ei64.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),VtVm", MATCH_VLUXSEG5EI64V, MASK_VLUXSEG5EI64V, match_vd_neq_vs2_neq_vm, INSN_DREF },
++{"vsuxseg5ei64.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),VtVm", MATCH_VSUXSEG5EI64V, MASK_VSUXSEG5EI64V, match_vd_neq_vs2_neq_vm, INSN_DREF },
++{"vluxseg6ei64.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),VtVm", MATCH_VLUXSEG6EI64V, MASK_VLUXSEG6EI64V, match_vd_neq_vs2_neq_vm, INSN_DREF },
++{"vsuxseg6ei64.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),VtVm", MATCH_VSUXSEG6EI64V, MASK_VSUXSEG6EI64V, match_vd_neq_vs2_neq_vm, INSN_DREF },
++{"vluxseg7ei64.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),VtVm", MATCH_VLUXSEG7EI64V, MASK_VLUXSEG7EI64V, match_vd_neq_vs2_neq_vm, INSN_DREF },
++{"vsuxseg7ei64.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),VtVm", MATCH_VSUXSEG7EI64V, MASK_VSUXSEG7EI64V, match_vd_neq_vs2_neq_vm, INSN_DREF },
++{"vluxseg8ei64.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),VtVm", MATCH_VLUXSEG8EI64V, MASK_VLUXSEG8EI64V, match_vd_neq_vs2_neq_vm, INSN_DREF },
++{"vsuxseg8ei64.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),VtVm", MATCH_VSUXSEG8EI64V, MASK_VSUXSEG8EI64V, match_vd_neq_vs2_neq_vm, INSN_DREF },
++
++{"vlseg2e8ff.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s)Vm", MATCH_VLSEG2E8FFV, MASK_VLSEG2E8FFV, match_vd_neq_vm, INSN_DREF },
++{"vlseg3e8ff.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s)Vm", MATCH_VLSEG3E8FFV, MASK_VLSEG3E8FFV, match_vd_neq_vm, INSN_DREF },
++{"vlseg4e8ff.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s)Vm", MATCH_VLSEG4E8FFV, MASK_VLSEG4E8FFV, match_vd_neq_vm, INSN_DREF },
++{"vlseg5e8ff.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s)Vm", MATCH_VLSEG5E8FFV, MASK_VLSEG5E8FFV, match_vd_neq_vm, INSN_DREF },
++{"vlseg6e8ff.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s)Vm", MATCH_VLSEG6E8FFV, MASK_VLSEG6E8FFV, match_vd_neq_vm, INSN_DREF },
++{"vlseg7e8ff.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s)Vm", MATCH_VLSEG7E8FFV, MASK_VLSEG7E8FFV, match_vd_neq_vm, INSN_DREF },
++{"vlseg8e8ff.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s)Vm", MATCH_VLSEG8E8FFV, MASK_VLSEG8E8FFV, match_vd_neq_vm, INSN_DREF },
++
++{"vlseg2e16ff.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s)Vm", MATCH_VLSEG2E16FFV, MASK_VLSEG2E16FFV, match_vd_neq_vm, INSN_DREF },
++{"vlseg3e16ff.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s)Vm", MATCH_VLSEG3E16FFV, MASK_VLSEG3E16FFV, match_vd_neq_vm, INSN_DREF },
++{"vlseg4e16ff.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s)Vm", MATCH_VLSEG4E16FFV, MASK_VLSEG4E16FFV, match_vd_neq_vm, INSN_DREF },
++{"vlseg5e16ff.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s)Vm", MATCH_VLSEG5E16FFV, MASK_VLSEG5E16FFV, match_vd_neq_vm, INSN_DREF },
++{"vlseg6e16ff.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s)Vm", MATCH_VLSEG6E16FFV, MASK_VLSEG6E16FFV, match_vd_neq_vm, INSN_DREF },
++{"vlseg7e16ff.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s)Vm", MATCH_VLSEG7E16FFV, MASK_VLSEG7E16FFV, match_vd_neq_vm, INSN_DREF },
++{"vlseg8e16ff.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s)Vm", MATCH_VLSEG8E16FFV, MASK_VLSEG8E16FFV, match_vd_neq_vm, INSN_DREF },
++
++{"vlseg2e32ff.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s)Vm", MATCH_VLSEG2E32FFV, MASK_VLSEG2E32FFV, match_vd_neq_vm, INSN_DREF },
++{"vlseg3e32ff.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s)Vm", MATCH_VLSEG3E32FFV, MASK_VLSEG3E32FFV, match_vd_neq_vm, INSN_DREF },
++{"vlseg4e32ff.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s)Vm", MATCH_VLSEG4E32FFV, MASK_VLSEG4E32FFV, match_vd_neq_vm, INSN_DREF },
++{"vlseg5e32ff.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s)Vm", MATCH_VLSEG5E32FFV, MASK_VLSEG5E32FFV, match_vd_neq_vm, INSN_DREF },
++{"vlseg6e32ff.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s)Vm", MATCH_VLSEG6E32FFV, MASK_VLSEG6E32FFV, match_vd_neq_vm, INSN_DREF },
++{"vlseg7e32ff.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s)Vm", MATCH_VLSEG7E32FFV, MASK_VLSEG7E32FFV, match_vd_neq_vm, INSN_DREF },
++{"vlseg8e32ff.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s)Vm", MATCH_VLSEG8E32FFV, MASK_VLSEG8E32FFV, match_vd_neq_vm, INSN_DREF },
++
++{"vlseg2e64ff.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s)Vm", MATCH_VLSEG2E64FFV, MASK_VLSEG2E64FFV, match_vd_neq_vm, INSN_DREF },
++{"vlseg3e64ff.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s)Vm", MATCH_VLSEG3E64FFV, MASK_VLSEG3E64FFV, match_vd_neq_vm, INSN_DREF },
++{"vlseg4e64ff.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s)Vm", MATCH_VLSEG4E64FFV, MASK_VLSEG4E64FFV, match_vd_neq_vm, INSN_DREF },
++{"vlseg5e64ff.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s)Vm", MATCH_VLSEG5E64FFV, MASK_VLSEG5E64FFV, match_vd_neq_vm, INSN_DREF },
++{"vlseg6e64ff.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s)Vm", MATCH_VLSEG6E64FFV, MASK_VLSEG6E64FFV, match_vd_neq_vm, INSN_DREF },
++{"vlseg7e64ff.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s)Vm", MATCH_VLSEG7E64FFV, MASK_VLSEG7E64FFV, match_vd_neq_vm, INSN_DREF },
++{"vlseg8e64ff.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s)Vm", MATCH_VLSEG8E64FFV, MASK_VLSEG8E64FFV, match_vd_neq_vm, INSN_DREF },
++
++{"vl1r.v",      0, INSN_CLASS_V,  "Vd,0(s)", MATCH_VL1RE8V, MASK_VL1RE8V, match_vls_nf_rv, INSN_DREF|INSN_ALIAS },
++{"vl1re8.v",    0, INSN_CLASS_V,  "Vd,0(s)", MATCH_VL1RE8V, MASK_VL1RE8V, match_vls_nf_rv, INSN_DREF },
++{"vl1re16.v",   0, INSN_CLASS_V,  "Vd,0(s)", MATCH_VL1RE16V, MASK_VL1RE16V, match_vls_nf_rv, INSN_DREF },
++{"vl1re32.v",   0, INSN_CLASS_V,  "Vd,0(s)", MATCH_VL1RE32V, MASK_VL1RE32V, match_vls_nf_rv, INSN_DREF },
++{"vl1re64.v",   0, INSN_CLASS_V,  "Vd,0(s)", MATCH_VL1RE64V, MASK_VL1RE64V, match_vls_nf_rv, INSN_DREF },
++
++{"vl2r.v",      0, INSN_CLASS_V,  "Vd,0(s)", MATCH_VL2RE8V, MASK_VL2RE8V, match_vls_nf_rv, INSN_DREF|INSN_ALIAS },
++{"vl2re8.v",    0, INSN_CLASS_V,  "Vd,0(s)", MATCH_VL2RE8V, MASK_VL2RE8V, match_vls_nf_rv, INSN_DREF },
++{"vl2re16.v",   0, INSN_CLASS_V,  "Vd,0(s)", MATCH_VL2RE16V, MASK_VL2RE16V, match_vls_nf_rv, INSN_DREF },
++{"vl2re32.v",   0, INSN_CLASS_V,  "Vd,0(s)", MATCH_VL2RE32V, MASK_VL2RE32V, match_vls_nf_rv, INSN_DREF },
++{"vl2re64.v",   0, INSN_CLASS_V,  "Vd,0(s)", MATCH_VL2RE64V, MASK_VL2RE64V, match_vls_nf_rv, INSN_DREF },
++
++{"vl4r.v",      0, INSN_CLASS_V,  "Vd,0(s)", MATCH_VL4RE8V, MASK_VL4RE8V, match_vls_nf_rv, INSN_DREF|INSN_ALIAS },
++{"vl4re8.v",    0, INSN_CLASS_V,  "Vd,0(s)", MATCH_VL4RE8V, MASK_VL4RE8V, match_vls_nf_rv, INSN_DREF },
++{"vl4re16.v",   0, INSN_CLASS_V,  "Vd,0(s)", MATCH_VL4RE16V, MASK_VL4RE16V, match_vls_nf_rv, INSN_DREF },
++{"vl4re32.v",   0, INSN_CLASS_V,  "Vd,0(s)", MATCH_VL4RE32V, MASK_VL4RE32V, match_vls_nf_rv, INSN_DREF },
++{"vl4re64.v",   0, INSN_CLASS_V,  "Vd,0(s)", MATCH_VL4RE64V, MASK_VL4RE64V, match_vls_nf_rv, INSN_DREF },
++
++{"vl8r.v",      0, INSN_CLASS_V,  "Vd,0(s)", MATCH_VL8RE8V, MASK_VL8RE8V, match_vls_nf_rv, INSN_DREF|INSN_ALIAS },
++{"vl8re8.v",    0, INSN_CLASS_V,  "Vd,0(s)", MATCH_VL8RE8V, MASK_VL8RE8V, match_vls_nf_rv, INSN_DREF },
++{"vl8re16.v",   0, INSN_CLASS_V,  "Vd,0(s)", MATCH_VL8RE16V, MASK_VL8RE16V, match_vls_nf_rv, INSN_DREF },
++{"vl8re32.v",   0, INSN_CLASS_V,  "Vd,0(s)", MATCH_VL8RE32V, MASK_VL8RE32V, match_vls_nf_rv, INSN_DREF },
++{"vl8re64.v",   0, INSN_CLASS_V,  "Vd,0(s)", MATCH_VL8RE64V, MASK_VL8RE64V, match_vls_nf_rv, INSN_DREF },
++
++{"vs1r.v",  0, INSN_CLASS_V,  "Vd,0(s)", MATCH_VS1RV, MASK_VS1RV, match_vls_nf_rv, INSN_DREF },
++{"vs2r.v",  0, INSN_CLASS_V,  "Vd,0(s)", MATCH_VS2RV, MASK_VS2RV, match_vls_nf_rv, INSN_DREF },
++{"vs4r.v",  0, INSN_CLASS_V,  "Vd,0(s)", MATCH_VS4RV, MASK_VS4RV, match_vls_nf_rv, INSN_DREF },
++{"vs8r.v",  0, INSN_CLASS_V,  "Vd,0(s)", MATCH_VS8RV, MASK_VS8RV, match_vls_nf_rv, INSN_DREF },
++
++{"vamoaddei8.v",   0, INSN_CLASS_V_OR_ZVAMO,  "Ve,0(s),Vt,VfVm", MATCH_VAMOADDEI8V, MASK_VAMOADDEI8V, match_vd_neq_vm, INSN_DREF},
++{"vamoswapei8.v",  0, INSN_CLASS_V_OR_ZVAMO,  "Ve,0(s),Vt,VfVm", MATCH_VAMOSWAPEI8V, MASK_VAMOSWAPEI8V, match_vd_neq_vm, INSN_DREF},
++{"vamoxorei8.v",   0, INSN_CLASS_V_OR_ZVAMO,  "Ve,0(s),Vt,VfVm", MATCH_VAMOXOREI8V, MASK_VAMOXOREI8V, match_vd_neq_vm, INSN_DREF},
++{"vamoandei8.v",   0, INSN_CLASS_V_OR_ZVAMO,  "Ve,0(s),Vt,VfVm", MATCH_VAMOANDEI8V, MASK_VAMOANDEI8V, match_vd_neq_vm, INSN_DREF},
++{"vamoorei8.v",    0, INSN_CLASS_V_OR_ZVAMO,  "Ve,0(s),Vt,VfVm", MATCH_VAMOOREI8V, MASK_VAMOOREI8V, match_vd_neq_vm, INSN_DREF},
++{"vamominei8.v",   0, INSN_CLASS_V_OR_ZVAMO,  "Ve,0(s),Vt,VfVm", MATCH_VAMOMINEI8V, MASK_VAMOMINEI8V, match_vd_neq_vm, INSN_DREF},
++{"vamomaxei8.v",   0, INSN_CLASS_V_OR_ZVAMO,  "Ve,0(s),Vt,VfVm", MATCH_VAMOMAXEI8V, MASK_VAMOMAXEI8V, match_vd_neq_vm, INSN_DREF},
++{"vamominuei8.v",  0, INSN_CLASS_V_OR_ZVAMO,  "Ve,0(s),Vt,VfVm", MATCH_VAMOMINUEI8V, MASK_VAMOMINUEI8V, match_vd_neq_vm, INSN_DREF},
++{"vamomaxuei8.v",  0, INSN_CLASS_V_OR_ZVAMO,  "Ve,0(s),Vt,VfVm", MATCH_VAMOMAXUEI8V, MASK_VAMOMAXUEI8V, match_vd_neq_vm, INSN_DREF},
++
++{"vamoaddei16.v",   0, INSN_CLASS_V_OR_ZVAMO,  "Ve,0(s),Vt,VfVm", MATCH_VAMOADDEI16V, MASK_VAMOADDEI16V, match_vd_neq_vm, INSN_DREF},
++{"vamoswapei16.v",  0, INSN_CLASS_V_OR_ZVAMO,  "Ve,0(s),Vt,VfVm", MATCH_VAMOSWAPEI16V, MASK_VAMOSWAPEI16V, match_vd_neq_vm, INSN_DREF},
++{"vamoxorei16.v",   0, INSN_CLASS_V_OR_ZVAMO,  "Ve,0(s),Vt,VfVm", MATCH_VAMOXOREI16V, MASK_VAMOXOREI16V, match_vd_neq_vm, INSN_DREF},
++{"vamoandei16.v",   0, INSN_CLASS_V_OR_ZVAMO,  "Ve,0(s),Vt,VfVm", MATCH_VAMOANDEI16V, MASK_VAMOANDEI16V, match_vd_neq_vm, INSN_DREF},
++{"vamoorei16.v",    0, INSN_CLASS_V_OR_ZVAMO,  "Ve,0(s),Vt,VfVm", MATCH_VAMOOREI16V, MASK_VAMOOREI16V, match_vd_neq_vm, INSN_DREF},
++{"vamominei16.v",   0, INSN_CLASS_V_OR_ZVAMO,  "Ve,0(s),Vt,VfVm", MATCH_VAMOMINEI16V, MASK_VAMOMINEI16V, match_vd_neq_vm, INSN_DREF},
++{"vamomaxei16.v",   0, INSN_CLASS_V_OR_ZVAMO,  "Ve,0(s),Vt,VfVm", MATCH_VAMOMAXEI16V, MASK_VAMOMAXEI16V, match_vd_neq_vm, INSN_DREF},
++{"vamominuei16.v",  0, INSN_CLASS_V_OR_ZVAMO,  "Ve,0(s),Vt,VfVm", MATCH_VAMOMINUEI16V, MASK_VAMOMINUEI16V, match_vd_neq_vm, INSN_DREF},
++{"vamomaxuei16.v",  0, INSN_CLASS_V_OR_ZVAMO,  "Ve,0(s),Vt,VfVm", MATCH_VAMOMAXUEI16V, MASK_VAMOMAXUEI16V, match_vd_neq_vm, INSN_DREF},
++
++{"vamoaddei32.v",   0, INSN_CLASS_V_OR_ZVAMO,  "Ve,0(s),Vt,VfVm", MATCH_VAMOADDEI32V, MASK_VAMOADDEI32V, match_vd_neq_vm, INSN_DREF},
++{"vamoswapei32.v",  0, INSN_CLASS_V_OR_ZVAMO,  "Ve,0(s),Vt,VfVm", MATCH_VAMOSWAPEI32V, MASK_VAMOSWAPEI32V, match_vd_neq_vm, INSN_DREF},
++{"vamoxorei32.v",   0, INSN_CLASS_V_OR_ZVAMO,  "Ve,0(s),Vt,VfVm", MATCH_VAMOXOREI32V, MASK_VAMOXOREI32V, match_vd_neq_vm, INSN_DREF},
++{"vamoandei32.v",   0, INSN_CLASS_V_OR_ZVAMO,  "Ve,0(s),Vt,VfVm", MATCH_VAMOANDEI32V, MASK_VAMOANDEI32V, match_vd_neq_vm, INSN_DREF},
++{"vamoorei32.v",    0, INSN_CLASS_V_OR_ZVAMO,  "Ve,0(s),Vt,VfVm", MATCH_VAMOOREI32V, MASK_VAMOOREI32V, match_vd_neq_vm, INSN_DREF},
++{"vamominei32.v",   0, INSN_CLASS_V_OR_ZVAMO,  "Ve,0(s),Vt,VfVm", MATCH_VAMOMINEI32V, MASK_VAMOMINEI32V, match_vd_neq_vm, INSN_DREF},
++{"vamomaxei32.v",   0, INSN_CLASS_V_OR_ZVAMO,  "Ve,0(s),Vt,VfVm", MATCH_VAMOMAXEI32V, MASK_VAMOMAXEI32V, match_vd_neq_vm, INSN_DREF},
++{"vamominuei32.v",  0, INSN_CLASS_V_OR_ZVAMO,  "Ve,0(s),Vt,VfVm", MATCH_VAMOMINUEI32V, MASK_VAMOMINUEI32V, match_vd_neq_vm, INSN_DREF},
++{"vamomaxuei32.v",  0, INSN_CLASS_V_OR_ZVAMO,  "Ve,0(s),Vt,VfVm", MATCH_VAMOMAXUEI32V, MASK_VAMOMAXUEI32V, match_vd_neq_vm, INSN_DREF},
++
++{"vamoaddei64.v",   0, INSN_CLASS_V_OR_ZVAMO,  "Ve,0(s),Vt,VfVm", MATCH_VAMOADDEI64V, MASK_VAMOADDEI64V, match_vd_neq_vm, INSN_DREF},
++{"vamoswapei64.v",  0, INSN_CLASS_V_OR_ZVAMO,  "Ve,0(s),Vt,VfVm", MATCH_VAMOSWAPEI64V, MASK_VAMOSWAPEI64V, match_vd_neq_vm, INSN_DREF},
++{"vamoxorei64.v",   0, INSN_CLASS_V_OR_ZVAMO,  "Ve,0(s),Vt,VfVm", MATCH_VAMOXOREI64V, MASK_VAMOXOREI64V, match_vd_neq_vm, INSN_DREF},
++{"vamoandei64.v",   0, INSN_CLASS_V_OR_ZVAMO,  "Ve,0(s),Vt,VfVm", MATCH_VAMOANDEI64V, MASK_VAMOANDEI64V, match_vd_neq_vm, INSN_DREF},
++{"vamoorei64.v",    0, INSN_CLASS_V_OR_ZVAMO,  "Ve,0(s),Vt,VfVm", MATCH_VAMOOREI64V, MASK_VAMOOREI64V, match_vd_neq_vm, INSN_DREF},
++{"vamominei64.v",   0, INSN_CLASS_V_OR_ZVAMO,  "Ve,0(s),Vt,VfVm", MATCH_VAMOMINEI64V, MASK_VAMOMINEI64V, match_vd_neq_vm, INSN_DREF},
++{"vamomaxei64.v",   0, INSN_CLASS_V_OR_ZVAMO,  "Ve,0(s),Vt,VfVm", MATCH_VAMOMAXEI64V, MASK_VAMOMAXEI64V, match_vd_neq_vm, INSN_DREF},
++{"vamominuei64.v",  0, INSN_CLASS_V_OR_ZVAMO,  "Ve,0(s),Vt,VfVm", MATCH_VAMOMINUEI64V, MASK_VAMOMINUEI64V, match_vd_neq_vm, INSN_DREF},
++{"vamomaxuei64.v",  0, INSN_CLASS_V_OR_ZVAMO,  "Ve,0(s),Vt,VfVm", MATCH_VAMOMAXUEI64V, MASK_VAMOMAXUEI64V, match_vd_neq_vm, INSN_DREF},
++
++{"vneg.v",     0, INSN_CLASS_V,  "Vd,VtVm",  MATCH_VRSUBVX, MASK_VRSUBVX | MASK_RS1, match_vd_neq_vm, INSN_ALIAS },
++
++{"vadd.vv",    0, INSN_CLASS_V,  "Vd,Vt,VsVm", MATCH_VADDVV, MASK_VADDVV, match_vd_neq_vm, 0 },
++{"vadd.vx",    0, INSN_CLASS_V,  "Vd,Vt,sVm", MATCH_VADDVX, MASK_VADDVX, match_vd_neq_vm, 0 },
++{"vadd.vi",    0, INSN_CLASS_V,  "Vd,Vt,ViVm", MATCH_VADDVI, MASK_VADDVI, match_vd_neq_vm, 0 },
++{"vsub.vv",    0, INSN_CLASS_V,  "Vd,Vt,VsVm", MATCH_VSUBVV, MASK_VSUBVV, match_vd_neq_vm, 0 },
++{"vsub.vx",    0, INSN_CLASS_V,  "Vd,Vt,sVm", MATCH_VSUBVX, MASK_VSUBVX, match_vd_neq_vm, 0 },
++{"vrsub.vx",   0, INSN_CLASS_V,  "Vd,Vt,sVm", MATCH_VRSUBVX, MASK_VRSUBVX, match_vd_neq_vm, 0 },
++{"vrsub.vi",   0, INSN_CLASS_V,  "Vd,Vt,ViVm", MATCH_VRSUBVI, MASK_VRSUBVI, match_vd_neq_vm, 0 },
++
++{"vwcvt.x.x.v",  0, INSN_CLASS_V,  "Vd,VtVm", MATCH_VWCVTXXV, MASK_VWCVTXXV, match_widen_vd_neq_vs2_neq_vm, INSN_ALIAS },
++{"vwcvtu.x.x.v", 0, INSN_CLASS_V,  "Vd,VtVm", MATCH_VWCVTUXXV, MASK_VWCVTUXXV, match_widen_vd_neq_vs2_neq_vm, INSN_ALIAS },
++
++{"vwaddu.vv",  0, INSN_CLASS_V,  "Vd,Vt,VsVm", MATCH_VWADDUVV, MASK_VWADDUVV, match_widen_vd_neq_vs1_neq_vs2_neq_vm, 0 },
++{"vwaddu.vx",  0, INSN_CLASS_V,  "Vd,Vt,sVm", MATCH_VWADDUVX, MASK_VWADDUVX, match_widen_vd_neq_vs2_neq_vm, 0 },
++{"vwsubu.vv",  0, INSN_CLASS_V,  "Vd,Vt,VsVm", MATCH_VWSUBUVV, MASK_VWSUBUVV, match_widen_vd_neq_vs1_neq_vs2_neq_vm, 0 },
++{"vwsubu.vx",  0, INSN_CLASS_V,  "Vd,Vt,sVm", MATCH_VWSUBUVX, MASK_VWSUBUVX, match_widen_vd_neq_vs2_neq_vm, 0 },
++{"vwadd.vv",   0, INSN_CLASS_V,  "Vd,Vt,VsVm", MATCH_VWADDVV, MASK_VWADDVV, match_widen_vd_neq_vs1_neq_vs2_neq_vm, 0 },
++{"vwadd.vx",   0, INSN_CLASS_V,  "Vd,Vt,sVm", MATCH_VWADDVX, MASK_VWADDVX, match_widen_vd_neq_vs2_neq_vm, 0 },
++{"vwsub.vv",   0, INSN_CLASS_V,  "Vd,Vt,VsVm", MATCH_VWSUBVV, MASK_VWSUBVV, match_widen_vd_neq_vs1_neq_vs2_neq_vm, 0 },
++{"vwsub.vx",   0, INSN_CLASS_V,  "Vd,Vt,sVm", MATCH_VWSUBVX, MASK_VWSUBVX, match_widen_vd_neq_vs2_neq_vm, 0 },
++{"vwaddu.wv",  0, INSN_CLASS_V,  "Vd,Vt,VsVm", MATCH_VWADDUWV, MASK_VWADDUWV, match_widen_vd_neq_vs1_neq_vm, 0 },
++{"vwaddu.wx",  0, INSN_CLASS_V,  "Vd,Vt,sVm", MATCH_VWADDUWX, MASK_VWADDUWX, match_widen_vd_neq_vm, 0 },
++{"vwsubu.wv",  0, INSN_CLASS_V,  "Vd,Vt,VsVm", MATCH_VWSUBUWV, MASK_VWSUBUWV, match_widen_vd_neq_vs1_neq_vm, 0 },
++{"vwsubu.wx",  0, INSN_CLASS_V,  "Vd,Vt,sVm", MATCH_VWSUBUWX, MASK_VWSUBUWX, match_widen_vd_neq_vm, 0 },
++{"vwadd.wv",   0, INSN_CLASS_V,  "Vd,Vt,VsVm", MATCH_VWADDWV, MASK_VWADDWV, match_widen_vd_neq_vs1_neq_vm, 0 },
++{"vwadd.wx",   0, INSN_CLASS_V,  "Vd,Vt,sVm", MATCH_VWADDWX, MASK_VWADDWX, match_widen_vd_neq_vm, 0 },
++{"vwsub.wv",   0, INSN_CLASS_V,  "Vd,Vt,VsVm", MATCH_VWSUBWV, MASK_VWSUBWV, match_widen_vd_neq_vs1_neq_vm, 0 },
++{"vwsub.wx",   0, INSN_CLASS_V,  "Vd,Vt,sVm", MATCH_VWSUBWX, MASK_VWSUBWX, match_widen_vd_neq_vm, 0 },
++
++{"vzext.vf2",  0, INSN_CLASS_V,  "Vd,VtVm", MATCH_VZEXT_VF2, MASK_VZEXT_VF2, match_vd_neq_vm, 0 },
++{"vsext.vf2",  0, INSN_CLASS_V,  "Vd,VtVm", MATCH_VSEXT_VF2, MASK_VSEXT_VF2, match_vd_neq_vm, 0 },
++{"vzext.vf4",  0, INSN_CLASS_V,  "Vd,VtVm", MATCH_VZEXT_VF4, MASK_VZEXT_VF4, match_vd_neq_vm, 0 },
++{"vsext.vf4",  0, INSN_CLASS_V,  "Vd,VtVm", MATCH_VSEXT_VF4, MASK_VSEXT_VF4, match_vd_neq_vm, 0 },
++{"vzext.vf8",  0, INSN_CLASS_V,  "Vd,VtVm", MATCH_VZEXT_VF8, MASK_VZEXT_VF8, match_vd_neq_vm, 0 },
++{"vsext.vf8",  0, INSN_CLASS_V,  "Vd,VtVm", MATCH_VSEXT_VF8, MASK_VSEXT_VF8, match_vd_neq_vm, 0 },
++
++{"vadc.vvm",   0, INSN_CLASS_V,  "Vd,Vt,Vs,V0", MATCH_VADCVVM, MASK_VADCVVM, match_vd_neq_vm, 0 },
++{"vadc.vxm",   0, INSN_CLASS_V,  "Vd,Vt,s,V0", MATCH_VADCVXM, MASK_VADCVXM, match_vd_neq_vm, 0 },
++{"vadc.vim",   0, INSN_CLASS_V,  "Vd,Vt,Vi,V0", MATCH_VADCVIM, MASK_VADCVIM, match_vd_neq_vm, 0 },
++{"vmadc.vvm",  0, INSN_CLASS_V,  "Vd,Vt,Vs,V0", MATCH_VMADCVVM, MASK_VMADCVVM, match_opcode, 0 },
++{"vmadc.vxm",  0, INSN_CLASS_V,  "Vd,Vt,s,V0", MATCH_VMADCVXM, MASK_VMADCVXM, match_opcode, 0 },
++{"vmadc.vim",  0, INSN_CLASS_V,  "Vd,Vt,Vi,V0", MATCH_VMADCVIM, MASK_VMADCVIM, match_opcode, 0 },
++{"vmadc.vv",   0, INSN_CLASS_V,  "Vd,Vt,Vs", MATCH_VMADCVV, MASK_VMADCVV, match_opcode, 0 },
++{"vmadc.vx",   0, INSN_CLASS_V,  "Vd,Vt,s", MATCH_VMADCVX, MASK_VMADCVX, match_opcode, 0 },
++{"vmadc.vi",   0, INSN_CLASS_V,  "Vd,Vt,Vi", MATCH_VMADCVI, MASK_VMADCVI, match_opcode, 0 },
++{"vsbc.vvm",   0, INSN_CLASS_V,  "Vd,Vt,Vs,V0", MATCH_VSBCVVM, MASK_VSBCVVM, match_vd_neq_vm, 0 },
++{"vsbc.vxm",   0, INSN_CLASS_V,  "Vd,Vt,s,V0", MATCH_VSBCVXM, MASK_VSBCVXM, match_vd_neq_vm, 0 },
++{"vmsbc.vvm",  0, INSN_CLASS_V,  "Vd,Vt,Vs,V0", MATCH_VMSBCVVM, MASK_VMSBCVVM, match_opcode, 0 },
++{"vmsbc.vxm",  0, INSN_CLASS_V,  "Vd,Vt,s,V0", MATCH_VMSBCVXM, MASK_VMSBCVXM, match_opcode, 0 },
++{"vmsbc.vv",   0, INSN_CLASS_V,  "Vd,Vt,Vs", MATCH_VMSBCVV, MASK_VMSBCVV, match_opcode, 0 },
++{"vmsbc.vx",   0, INSN_CLASS_V,  "Vd,Vt,s", MATCH_VMSBCVX, MASK_VMSBCVX, match_opcode, 0 },
++
++{"vnot.v",     0, INSN_CLASS_V,  "Vd,VtVm", MATCH_VNOTV, MASK_VNOTV, match_vd_neq_vm, INSN_ALIAS },
++
++{"vand.vv",    0, INSN_CLASS_V,  "Vd,Vt,VsVm", MATCH_VANDVV, MASK_VANDVV, match_vd_neq_vm, 0 },
++{"vand.vx",    0, INSN_CLASS_V,  "Vd,Vt,sVm", MATCH_VANDVX, MASK_VANDVX, match_vd_neq_vm, 0 },
++{"vand.vi",    0, INSN_CLASS_V,  "Vd,Vt,ViVm", MATCH_VANDVI, MASK_VANDVI, match_vd_neq_vm, 0 },
++{"vor.vv",     0, INSN_CLASS_V,  "Vd,Vt,VsVm", MATCH_VORVV, MASK_VORVV, match_vd_neq_vm, 0 },
++{"vor.vx",     0, INSN_CLASS_V,  "Vd,Vt,sVm", MATCH_VORVX, MASK_VORVX, match_vd_neq_vm, 0 },
++{"vor.vi",     0, INSN_CLASS_V,  "Vd,Vt,ViVm", MATCH_VORVI, MASK_VORVI, match_vd_neq_vm, 0 },
++{"vxor.vv",    0, INSN_CLASS_V,  "Vd,Vt,VsVm", MATCH_VXORVV, MASK_VXORVV, match_vd_neq_vm, 0 },
++{"vxor.vx",    0, INSN_CLASS_V,  "Vd,Vt,sVm", MATCH_VXORVX, MASK_VXORVX, match_vd_neq_vm, 0 },
++{"vxor.vi",    0, INSN_CLASS_V,  "Vd,Vt,ViVm", MATCH_VXORVI, MASK_VXORVI, match_vd_neq_vm, 0 },
++
++{"vsll.vv",    0, INSN_CLASS_V,  "Vd,Vt,VsVm", MATCH_VSLLVV, MASK_VSLLVV, match_vd_neq_vm, 0 },
++{"vsll.vx",    0, INSN_CLASS_V,  "Vd,Vt,sVm", MATCH_VSLLVX, MASK_VSLLVX, match_vd_neq_vm, 0 },
++{"vsll.vi",    0, INSN_CLASS_V,  "Vd,Vt,VjVm", MATCH_VSLLVI, MASK_VSLLVI, match_vd_neq_vm, 0 },
++{"vsrl.vv",    0, INSN_CLASS_V,  "Vd,Vt,VsVm", MATCH_VSRLVV, MASK_VSRLVV, match_vd_neq_vm, 0 },
++{"vsrl.vx",    0, INSN_CLASS_V,  "Vd,Vt,sVm", MATCH_VSRLVX, MASK_VSRLVX, match_vd_neq_vm, 0 },
++{"vsrl.vi",    0, INSN_CLASS_V,  "Vd,Vt,VjVm", MATCH_VSRLVI, MASK_VSRLVI, match_vd_neq_vm, 0 },
++{"vsra.vv",    0, INSN_CLASS_V,  "Vd,Vt,VsVm", MATCH_VSRAVV, MASK_VSRAVV, match_vd_neq_vm, 0 },
++{"vsra.vx",    0, INSN_CLASS_V,  "Vd,Vt,sVm", MATCH_VSRAVX, MASK_VSRAVX, match_vd_neq_vm, 0 },
++{"vsra.vi",    0, INSN_CLASS_V,  "Vd,Vt,VjVm", MATCH_VSRAVI, MASK_VSRAVI, match_vd_neq_vm, 0 },
++
++{"vncvt.x.x.w",0, INSN_CLASS_V,  "Vd,VtVm", MATCH_VNCVTXXW, MASK_VNCVTXXW, match_narrow_vd_neq_vs2_neq_vm, INSN_ALIAS },
++
++{"vnsrl.wv",   0, INSN_CLASS_V,  "Vd,Vt,VsVm", MATCH_VNSRLWV, MASK_VNSRLWV, match_narrow_vd_neq_vs2_neq_vm, 0 },
++{"vnsrl.wx",   0, INSN_CLASS_V,  "Vd,Vt,sVm", MATCH_VNSRLWX, MASK_VNSRLWX, match_narrow_vd_neq_vs2_neq_vm, 0 },
++{"vnsrl.wi",   0, INSN_CLASS_V,  "Vd,Vt,VjVm", MATCH_VNSRLWI, MASK_VNSRLWI, match_narrow_vd_neq_vs2_neq_vm, 0 },
++{"vnsra.wv",   0, INSN_CLASS_V,  "Vd,Vt,VsVm", MATCH_VNSRAWV, MASK_VNSRAWV, match_narrow_vd_neq_vs2_neq_vm, 0 },
++{"vnsra.wx",   0, INSN_CLASS_V,  "Vd,Vt,sVm", MATCH_VNSRAWX, MASK_VNSRAWX, match_narrow_vd_neq_vs2_neq_vm, 0 },
++{"vnsra.wi",   0, INSN_CLASS_V,  "Vd,Vt,VjVm", MATCH_VNSRAWI, MASK_VNSRAWI, match_narrow_vd_neq_vs2_neq_vm, 0 },
++
++{"vmseq.vv",   0, INSN_CLASS_V,  "Vd,Vt,VsVm", MATCH_VMSEQVV, MASK_VMSEQVV, match_opcode, 0 },
++{"vmseq.vx",   0, INSN_CLASS_V,  "Vd,Vt,sVm", MATCH_VMSEQVX, MASK_VMSEQVX, match_opcode, 0 },
++{"vmseq.vi",   0, INSN_CLASS_V,  "Vd,Vt,ViVm", MATCH_VMSEQVI, MASK_VMSEQVI, match_opcode, 0 },
++{"vmsne.vv",   0, INSN_CLASS_V,  "Vd,Vt,VsVm", MATCH_VMSNEVV, MASK_VMSNEVV, match_opcode, 0 },
++{"vmsne.vx",   0, INSN_CLASS_V,  "Vd,Vt,sVm", MATCH_VMSNEVX, MASK_VMSNEVX, match_opcode, 0 },
++{"vmsne.vi",   0, INSN_CLASS_V,  "Vd,Vt,ViVm", MATCH_VMSNEVI, MASK_VMSNEVI, match_opcode, 0 },
++{"vmsltu.vv",  0, INSN_CLASS_V,  "Vd,Vt,VsVm", MATCH_VMSLTUVV, MASK_VMSLTUVV, match_opcode, 0 },
++{"vmsltu.vx",  0, INSN_CLASS_V,  "Vd,Vt,sVm", MATCH_VMSLTUVX, MASK_VMSLTUVX, match_opcode, 0 },
++{"vmslt.vv",   0, INSN_CLASS_V,  "Vd,Vt,VsVm", MATCH_VMSLTVV, MASK_VMSLTVV, match_opcode, 0 },
++{"vmslt.vx",   0, INSN_CLASS_V,  "Vd,Vt,sVm", MATCH_VMSLTVX, MASK_VMSLTVX, match_opcode, 0 },
++{"vmsleu.vv",  0, INSN_CLASS_V,  "Vd,Vt,VsVm", MATCH_VMSLEUVV, MASK_VMSLEUVV, match_opcode, 0 },
++{"vmsleu.vx",  0, INSN_CLASS_V,  "Vd,Vt,sVm", MATCH_VMSLEUVX, MASK_VMSLEUVX, match_opcode, 0 },
++{"vmsleu.vi",  0, INSN_CLASS_V,  "Vd,Vt,ViVm", MATCH_VMSLEUVI, MASK_VMSLEUVI, match_opcode, 0 },
++{"vmsle.vv",   0, INSN_CLASS_V,  "Vd,Vt,VsVm", MATCH_VMSLEVV, MASK_VMSLEVV, match_opcode, 0 },
++{"vmsle.vx",   0, INSN_CLASS_V,  "Vd,Vt,sVm", MATCH_VMSLEVX, MASK_VMSLEVX, match_opcode, 0 },
++{"vmsle.vi",   0, INSN_CLASS_V,  "Vd,Vt,ViVm", MATCH_VMSLEVI, MASK_VMSLEVI, match_opcode, 0 },
++{"vmsgtu.vx",  0, INSN_CLASS_V,  "Vd,Vt,sVm", MATCH_VMSGTUVX, MASK_VMSGTUVX, match_opcode, 0 },
++{"vmsgtu.vi",  0, INSN_CLASS_V,  "Vd,Vt,ViVm", MATCH_VMSGTUVI, MASK_VMSGTUVI, match_opcode, 0 },
++{"vmsgt.vx",   0, INSN_CLASS_V,  "Vd,Vt,sVm", MATCH_VMSGTVX, MASK_VMSGTVX, match_opcode, 0 },
++{"vmsgt.vi",   0, INSN_CLASS_V,  "Vd,Vt,ViVm", MATCH_VMSGTVI, MASK_VMSGTVI, match_opcode, 0 },
++
++/* These aliases are for assembly but not disassembly.  */
++{"vmsgt.vv",   0, INSN_CLASS_V,  "Vd,Vs,VtVm", MATCH_VMSLTVV, MASK_VMSLTVV, match_opcode, INSN_ALIAS },
++{"vmsgtu.vv",  0, INSN_CLASS_V,  "Vd,Vs,VtVm", MATCH_VMSLTUVV, MASK_VMSLTUVV, match_opcode, INSN_ALIAS },
++{"vmsge.vv",   0, INSN_CLASS_V,  "Vd,Vs,VtVm", MATCH_VMSLEVV, MASK_VMSLEVV, match_opcode, INSN_ALIAS },
++{"vmsgeu.vv",  0, INSN_CLASS_V,  "Vd,Vs,VtVm", MATCH_VMSLEUVV, MASK_VMSLEUVV, match_opcode, INSN_ALIAS },
++{"vmslt.vi",   0, INSN_CLASS_V,  "Vd,Vt,VkVm", MATCH_VMSLEVI, MASK_VMSLEVI, match_opcode, INSN_ALIAS },
++{"vmsltu.vi",  0, INSN_CLASS_V,  "Vd,Vu,0Vm", MATCH_VMSNEVV, MASK_VMSNEVV, match_opcode, INSN_ALIAS },
++{"vmsltu.vi",  0, INSN_CLASS_V,  "Vd,Vt,VkVm", MATCH_VMSLEUVI, MASK_VMSLEUVI, match_opcode, INSN_ALIAS },
++{"vmsge.vi",   0, INSN_CLASS_V,  "Vd,Vt,VkVm", MATCH_VMSGTVI, MASK_VMSGTVI, match_opcode, INSN_ALIAS },
++{"vmsgeu.vi",  0, INSN_CLASS_V,  "Vd,Vu,0Vm", MATCH_VMSEQVV, MASK_VMSEQVV, match_opcode, INSN_ALIAS },
++{"vmsgeu.vi",  0, INSN_CLASS_V,  "Vd,Vt,VkVm", MATCH_VMSGTUVI, MASK_VMSGTUVI, match_opcode, INSN_ALIAS },
++
++{"vmsge.vx",   0, INSN_CLASS_V, "Vd,Vt,sVm", 0, (int) M_VMSGE, match_never, INSN_MACRO },
++{"vmsge.vx",   0, INSN_CLASS_V, "Vd,Vt,s,VM,VT", 0, (int) M_VMSGE, match_never, INSN_MACRO },
++{"vmsgeu.vx",  0, INSN_CLASS_V, "Vd,Vt,sVm", 0, (int) M_VMSGEU, match_never, INSN_MACRO },
++{"vmsgeu.vx",  0, INSN_CLASS_V, "Vd,Vt,s,VM,VT", 0, (int) M_VMSGEU, match_never, INSN_MACRO },
++
++{"vminu.vv",   0, INSN_CLASS_V,  "Vd,Vt,VsVm", MATCH_VMINUVV, MASK_VMINUVV, match_vd_neq_vm, 0},
++{"vminu.vx",   0, INSN_CLASS_V,  "Vd,Vt,sVm", MATCH_VMINUVX, MASK_VMINUVX, match_vd_neq_vm, 0},
++{"vmin.vv",    0, INSN_CLASS_V,  "Vd,Vt,VsVm", MATCH_VMINVV, MASK_VMINVV, match_vd_neq_vm, 0},
++{"vmin.vx",    0, INSN_CLASS_V,  "Vd,Vt,sVm", MATCH_VMINVX, MASK_VMINVX, match_vd_neq_vm, 0},
++{"vmaxu.vv",   0, INSN_CLASS_V,  "Vd,Vt,VsVm", MATCH_VMAXUVV, MASK_VMAXUVV, match_vd_neq_vm, 0},
++{"vmaxu.vx",   0, INSN_CLASS_V,  "Vd,Vt,sVm", MATCH_VMAXUVX, MASK_VMAXUVX, match_vd_neq_vm, 0},
++{"vmax.vv",    0, INSN_CLASS_V,  "Vd,Vt,VsVm", MATCH_VMAXVV, MASK_VMAXVV, match_vd_neq_vm, 0},
++{"vmax.vx",    0, INSN_CLASS_V,  "Vd,Vt,sVm", MATCH_VMAXVX, MASK_VMAXVX, match_vd_neq_vm, 0},
++
++{"vmul.vv",    0, INSN_CLASS_V,  "Vd,Vt,VsVm", MATCH_VMULVV, MASK_VMULVV, match_vd_neq_vm, 0 },
++{"vmul.vx",    0, INSN_CLASS_V,  "Vd,Vt,sVm", MATCH_VMULVX, MASK_VMULVX, match_vd_neq_vm, 0 },
++{"vmulh.vv",   0, INSN_CLASS_V,  "Vd,Vt,VsVm", MATCH_VMULHVV, MASK_VMULHVV, match_vd_neq_vm, 0 },
++{"vmulh.vx",   0, INSN_CLASS_V,  "Vd,Vt,sVm", MATCH_VMULHVX, MASK_VMULHVX, match_vd_neq_vm, 0 },
++{"vmulhu.vv",  0, INSN_CLASS_V,  "Vd,Vt,VsVm", MATCH_VMULHUVV, MASK_VMULHUVV, match_vd_neq_vm, 0 },
++{"vmulhu.vx",  0, INSN_CLASS_V,  "Vd,Vt,sVm", MATCH_VMULHUVX, MASK_VMULHUVX, match_vd_neq_vm, 0 },
++{"vmulhsu.vv", 0, INSN_CLASS_V,  "Vd,Vt,VsVm", MATCH_VMULHSUVV, MASK_VMULHSUVV, match_vd_neq_vm, 0 },
++{"vmulhsu.vx", 0, INSN_CLASS_V,  "Vd,Vt,sVm", MATCH_VMULHSUVX, MASK_VMULHSUVX, match_vd_neq_vm, 0 },
++
++{"vwmul.vv",   0, INSN_CLASS_V,  "Vd,Vt,VsVm", MATCH_VWMULVV, MASK_VWMULVV, match_widen_vd_neq_vs1_neq_vs2_neq_vm, 0 },
++{"vwmul.vx",   0, INSN_CLASS_V,  "Vd,Vt,sVm", MATCH_VWMULVX, MASK_VWMULVX, match_widen_vd_neq_vs2_neq_vm, 0 },
++{"vwmulu.vv",  0, INSN_CLASS_V,  "Vd,Vt,VsVm", MATCH_VWMULUVV, MASK_VWMULUVV, match_widen_vd_neq_vs1_neq_vs2_neq_vm, 0 },
++{"vwmulu.vx",  0, INSN_CLASS_V,  "Vd,Vt,sVm", MATCH_VWMULUVX, MASK_VWMULUVX, match_widen_vd_neq_vs2_neq_vm, 0 },
++{"vwmulsu.vv", 0, INSN_CLASS_V,  "Vd,Vt,VsVm", MATCH_VWMULSUVV, MASK_VWMULSUVV, match_widen_vd_neq_vs1_neq_vs2_neq_vm, 0 },
++{"vwmulsu.vx", 0, INSN_CLASS_V,  "Vd,Vt,sVm", MATCH_VWMULSUVX, MASK_VWMULSUVX, match_widen_vd_neq_vs2_neq_vm, 0 },
++
++{"vmacc.vv",   0, INSN_CLASS_V,  "Vd,Vs,VtVm", MATCH_VMACCVV, MASK_VMACCVV, match_vd_neq_vm, 0},
++{"vmacc.vx",   0, INSN_CLASS_V,  "Vd,s,VtVm", MATCH_VMACCVX, MASK_VMACCVX, match_vd_neq_vm, 0},
++{"vnmsac.vv",  0, INSN_CLASS_V,  "Vd,Vs,VtVm", MATCH_VNMSACVV, MASK_VNMSACVV, match_vd_neq_vm, 0},
++{"vnmsac.vx",  0, INSN_CLASS_V,  "Vd,s,VtVm", MATCH_VNMSACVX, MASK_VNMSACVX, match_vd_neq_vm, 0},
++{"vmadd.vv",   0, INSN_CLASS_V,  "Vd,Vs,VtVm", MATCH_VMADDVV, MASK_VMADDVV, match_vd_neq_vm, 0},
++{"vmadd.vx",   0, INSN_CLASS_V,  "Vd,s,VtVm", MATCH_VMADDVX, MASK_VMADDVX, match_vd_neq_vm, 0},
++{"vnmsub.vv",  0, INSN_CLASS_V,  "Vd,Vs,VtVm", MATCH_VNMSUBVV, MASK_VNMSUBVV, match_vd_neq_vm, 0},
++{"vnmsub.vx",  0, INSN_CLASS_V,  "Vd,s,VtVm", MATCH_VNMSUBVX, MASK_VNMSUBVX, match_vd_neq_vm, 0},
++
++{"vwmaccu.vv",  0, INSN_CLASS_V,  "Vd,Vs,VtVm", MATCH_VWMACCUVV, MASK_VWMACCUVV, match_widen_vd_neq_vs1_neq_vs2_neq_vm, 0},
++{"vwmaccu.vx",  0, INSN_CLASS_V,  "Vd,s,VtVm", MATCH_VWMACCUVX, MASK_VWMACCUVX, match_widen_vd_neq_vs2_neq_vm, 0},
++{"vwmacc.vv",   0, INSN_CLASS_V,  "Vd,Vs,VtVm", MATCH_VWMACCVV, MASK_VWMACCVV, match_widen_vd_neq_vs1_neq_vs2_neq_vm, 0},
++{"vwmacc.vx",   0, INSN_CLASS_V,  "Vd,s,VtVm", MATCH_VWMACCVX, MASK_VWMACCVX, match_widen_vd_neq_vs2_neq_vm, 0},
++{"vwmaccsu.vv", 0, INSN_CLASS_V,  "Vd,Vs,VtVm", MATCH_VWMACCSUVV, MASK_VWMACCSUVV, match_widen_vd_neq_vs1_neq_vs2_neq_vm, 0},
++{"vwmaccsu.vx", 0, INSN_CLASS_V,  "Vd,s,VtVm", MATCH_VWMACCSUVX, MASK_VWMACCSUVX, match_widen_vd_neq_vs2_neq_vm, 0},
++{"vwmaccus.vx", 0, INSN_CLASS_V,  "Vd,s,VtVm", MATCH_VWMACCUSVX, MASK_VWMACCUSVX, match_widen_vd_neq_vs2_neq_vm, 0},
++
++{"vdivu.vv",   0, INSN_CLASS_V,  "Vd,Vt,VsVm", MATCH_VDIVUVV, MASK_VDIVUVV, match_vd_neq_vm, 0 },
++{"vdivu.vx",   0, INSN_CLASS_V,  "Vd,Vt,sVm", MATCH_VDIVUVX, MASK_VDIVUVX, match_vd_neq_vm, 0 },
++{"vdiv.vv",    0, INSN_CLASS_V,  "Vd,Vt,VsVm", MATCH_VDIVVV, MASK_VDIVVV, match_vd_neq_vm, 0 },
++{"vdiv.vx",    0, INSN_CLASS_V,  "Vd,Vt,sVm", MATCH_VDIVVX, MASK_VDIVVX, match_vd_neq_vm, 0 },
++{"vremu.vv",   0, INSN_CLASS_V,  "Vd,Vt,VsVm", MATCH_VREMUVV, MASK_VREMUVV, match_vd_neq_vm, 0 },
++{"vremu.vx",   0, INSN_CLASS_V,  "Vd,Vt,sVm", MATCH_VREMUVX, MASK_VREMUVX, match_vd_neq_vm, 0 },
++{"vrem.vv",    0, INSN_CLASS_V,  "Vd,Vt,VsVm", MATCH_VREMVV, MASK_VREMVV, match_vd_neq_vm, 0 },
++{"vrem.vx",    0, INSN_CLASS_V,  "Vd,Vt,sVm", MATCH_VREMVX, MASK_VREMVX, match_vd_neq_vm, 0 },
++
++{"vmerge.vvm", 0, INSN_CLASS_V,  "Vd,Vt,Vs,V0", MATCH_VMERGEVVM, MASK_VMERGEVVM, match_opcode, 0 },
++{"vmerge.vxm", 0, INSN_CLASS_V,  "Vd,Vt,s,V0", MATCH_VMERGEVXM, MASK_VMERGEVXM, match_opcode, 0 },
++{"vmerge.vim", 0, INSN_CLASS_V,  "Vd,Vt,Vi,V0", MATCH_VMERGEVIM, MASK_VMERGEVIM, match_opcode, 0 },
++
++{"vmv.v.v",    0, INSN_CLASS_V,  "Vd,Vs", MATCH_VMVVV, MASK_VMVVV, match_opcode, 0 },
++{"vmv.v.x",    0, INSN_CLASS_V,  "Vd,s", MATCH_VMVVX, MASK_VMVVX, match_opcode, 0 },
++{"vmv.v.i",    0, INSN_CLASS_V,  "Vd,Vi", MATCH_VMVVI, MASK_VMVVI, match_opcode, 0 },
++
++{"vsaddu.vv",  0, INSN_CLASS_V,  "Vd,Vt,VsVm", MATCH_VSADDUVV, MASK_VSADDUVV, match_vd_neq_vm, 0 },
++{"vsaddu.vx",  0, INSN_CLASS_V,  "Vd,Vt,sVm", MATCH_VSADDUVX, MASK_VSADDUVX, match_vd_neq_vm, 0 },
++{"vsaddu.vi",  0, INSN_CLASS_V,  "Vd,Vt,ViVm", MATCH_VSADDUVI, MASK_VSADDUVI, match_vd_neq_vm, 0 },
++{"vsadd.vv",   0, INSN_CLASS_V,  "Vd,Vt,VsVm", MATCH_VSADDVV, MASK_VSADDVV, match_vd_neq_vm, 0 },
++{"vsadd.vx",   0, INSN_CLASS_V,  "Vd,Vt,sVm", MATCH_VSADDVX, MASK_VSADDVX, match_vd_neq_vm, 0 },
++{"vsadd.vi",   0, INSN_CLASS_V,  "Vd,Vt,ViVm", MATCH_VSADDVI, MASK_VSADDVI, match_vd_neq_vm, 0 },
++{"vssubu.vv",  0, INSN_CLASS_V,  "Vd,Vt,VsVm", MATCH_VSSUBUVV, MASK_VSSUBUVV, match_vd_neq_vm, 0 },
++{"vssubu.vx",  0, INSN_CLASS_V,  "Vd,Vt,sVm", MATCH_VSSUBUVX, MASK_VSSUBUVX, match_vd_neq_vm, 0 },
++{"vssub.vv",   0, INSN_CLASS_V,  "Vd,Vt,VsVm", MATCH_VSSUBVV, MASK_VSSUBVV, match_vd_neq_vm, 0 },
++{"vssub.vx",   0, INSN_CLASS_V,  "Vd,Vt,sVm", MATCH_VSSUBVX, MASK_VSSUBVX, match_vd_neq_vm, 0 },
++
++{"vaaddu.vv",  0, INSN_CLASS_V,  "Vd,Vt,VsVm", MATCH_VAADDUVV, MASK_VAADDUVV, match_vd_neq_vm, 0 },
++{"vaaddu.vx",  0, INSN_CLASS_V,  "Vd,Vt,sVm", MATCH_VAADDUVX, MASK_VAADDUVX, match_vd_neq_vm, 0 },
++{"vaadd.vv",   0, INSN_CLASS_V,  "Vd,Vt,VsVm", MATCH_VAADDVV, MASK_VAADDVV, match_vd_neq_vm, 0 },
++{"vaadd.vx",   0, INSN_CLASS_V,  "Vd,Vt,sVm", MATCH_VAADDVX, MASK_VAADDVX, match_vd_neq_vm, 0 },
++{"vasubu.vv",  0, INSN_CLASS_V,  "Vd,Vt,VsVm", MATCH_VASUBUVV, MASK_VASUBUVV, match_vd_neq_vm, 0 },
++{"vasubu.vx",  0, INSN_CLASS_V,  "Vd,Vt,sVm", MATCH_VASUBUVX, MASK_VASUBUVX, match_vd_neq_vm, 0 },
++{"vasub.vv",   0, INSN_CLASS_V,  "Vd,Vt,VsVm", MATCH_VASUBVV, MASK_VASUBVV, match_vd_neq_vm, 0 },
++{"vasub.vx",   0, INSN_CLASS_V,  "Vd,Vt,sVm", MATCH_VASUBVX, MASK_VASUBVX, match_vd_neq_vm, 0 },
++
++{"vsmul.vv",   0, INSN_CLASS_V,  "Vd,Vt,VsVm", MATCH_VSMULVV, MASK_VSMULVV, match_vd_neq_vm, 0 },
++{"vsmul.vx",   0, INSN_CLASS_V,  "Vd,Vt,sVm", MATCH_VSMULVX, MASK_VSMULVX, match_vd_neq_vm, 0 },
++
++{"vssrl.vv",    0, INSN_CLASS_V,  "Vd,Vt,VsVm", MATCH_VSSRLVV, MASK_VSSRLVV, match_vd_neq_vm, 0 },
++{"vssrl.vx",    0, INSN_CLASS_V,  "Vd,Vt,sVm", MATCH_VSSRLVX, MASK_VSSRLVX, match_vd_neq_vm, 0 },
++{"vssrl.vi",    0, INSN_CLASS_V,  "Vd,Vt,VjVm", MATCH_VSSRLVI, MASK_VSSRLVI, match_vd_neq_vm, 0 },
++{"vssra.vv",    0, INSN_CLASS_V,  "Vd,Vt,VsVm", MATCH_VSSRAVV, MASK_VSSRAVV, match_vd_neq_vm, 0 },
++{"vssra.vx",    0, INSN_CLASS_V,  "Vd,Vt,sVm", MATCH_VSSRAVX, MASK_VSSRAVX, match_vd_neq_vm, 0 },
++{"vssra.vi",    0, INSN_CLASS_V,  "Vd,Vt,VjVm", MATCH_VSSRAVI, MASK_VSSRAVI, match_vd_neq_vm, 0 },
++
++{"vnclipu.wv",   0, INSN_CLASS_V,  "Vd,Vt,VsVm", MATCH_VNCLIPUWV, MASK_VNCLIPUWV, match_narrow_vd_neq_vs2_neq_vm, 0 },
++{"vnclipu.wx",   0, INSN_CLASS_V,  "Vd,Vt,sVm", MATCH_VNCLIPUWX, MASK_VNCLIPUWX, match_narrow_vd_neq_vs2_neq_vm, 0 },
++{"vnclipu.wi",   0, INSN_CLASS_V,  "Vd,Vt,VjVm", MATCH_VNCLIPUWI, MASK_VNCLIPUWI, match_narrow_vd_neq_vs2_neq_vm, 0 },
++{"vnclip.wv",   0, INSN_CLASS_V,  "Vd,Vt,VsVm", MATCH_VNCLIPWV, MASK_VNCLIPWV, match_narrow_vd_neq_vs2_neq_vm, 0 },
++{"vnclip.wx",   0, INSN_CLASS_V,  "Vd,Vt,sVm", MATCH_VNCLIPWX, MASK_VNCLIPWX, match_narrow_vd_neq_vs2_neq_vm, 0 },
++{"vnclip.wi",   0, INSN_CLASS_V,  "Vd,Vt,VjVm", MATCH_VNCLIPWI, MASK_VNCLIPWI, match_narrow_vd_neq_vs2_neq_vm, 0 },
++
++{"vfadd.vv",   0, INSN_CLASS_V_AND_F, "Vd,Vt,VsVm", MATCH_VFADDVV, MASK_VFADDVV, match_vd_neq_vm, 0},
++{"vfadd.vf",   0, INSN_CLASS_V_AND_F, "Vd,Vt,SVm", MATCH_VFADDVF, MASK_VFADDVF, match_vd_neq_vm, 0},
++{"vfsub.vv",   0, INSN_CLASS_V_AND_F, "Vd,Vt,VsVm", MATCH_VFSUBVV, MASK_VFSUBVV, match_vd_neq_vm, 0},
++{"vfsub.vf",   0, INSN_CLASS_V_AND_F, "Vd,Vt,SVm", MATCH_VFSUBVF, MASK_VFSUBVF, match_vd_neq_vm, 0},
++{"vfrsub.vf",  0, INSN_CLASS_V_AND_F, "Vd,Vt,SVm", MATCH_VFRSUBVF, MASK_VFRSUBVF, match_vd_neq_vm, 0},
++
++{"vfwadd.vv",   0, INSN_CLASS_V_AND_F, "Vd,Vt,VsVm", MATCH_VFWADDVV, MASK_VFWADDVV, match_widen_vd_neq_vs1_neq_vs2_neq_vm, 0},
++{"vfwadd.vf",   0, INSN_CLASS_V_AND_F, "Vd,Vt,SVm", MATCH_VFWADDVF, MASK_VFWADDVF, match_widen_vd_neq_vs2_neq_vm, 0},
++{"vfwsub.vv",   0, INSN_CLASS_V_AND_F, "Vd,Vt,VsVm", MATCH_VFWSUBVV, MASK_VFWSUBVV, match_widen_vd_neq_vs1_neq_vs2_neq_vm, 0},
++{"vfwsub.vf",   0, INSN_CLASS_V_AND_F, "Vd,Vt,SVm", MATCH_VFWSUBVF, MASK_VFWSUBVF, match_widen_vd_neq_vs2_neq_vm, 0},
++{"vfwadd.wv",   0, INSN_CLASS_V_AND_F, "Vd,Vt,VsVm", MATCH_VFWADDWV, MASK_VFWADDWV, match_widen_vd_neq_vs1_neq_vm, 0},
++{"vfwadd.wf",   0, INSN_CLASS_V_AND_F, "Vd,Vt,SVm", MATCH_VFWADDWF, MASK_VFWADDWF, match_widen_vd_neq_vm, 0},
++{"vfwsub.wv",   0, INSN_CLASS_V_AND_F, "Vd,Vt,VsVm", MATCH_VFWSUBWV, MASK_VFWSUBWV, match_widen_vd_neq_vs1_neq_vm, 0},
++{"vfwsub.wf",   0, INSN_CLASS_V_AND_F, "Vd,Vt,SVm", MATCH_VFWSUBWF, MASK_VFWSUBWF, match_widen_vd_neq_vm, 0},
++
++{"vfmul.vv",   0, INSN_CLASS_V_AND_F, "Vd,Vt,VsVm", MATCH_VFMULVV, MASK_VFMULVV, match_vd_neq_vm, 0},
++{"vfmul.vf",   0, INSN_CLASS_V_AND_F, "Vd,Vt,SVm", MATCH_VFMULVF, MASK_VFMULVF, match_vd_neq_vm, 0},
++{"vfdiv.vv",   0, INSN_CLASS_V_AND_F, "Vd,Vt,VsVm", MATCH_VFDIVVV, MASK_VFDIVVV, match_vd_neq_vm, 0},
++{"vfdiv.vf",   0, INSN_CLASS_V_AND_F, "Vd,Vt,SVm", MATCH_VFDIVVF, MASK_VFDIVVF, match_vd_neq_vm, 0},
++{"vfrdiv.vf",  0, INSN_CLASS_V_AND_F, "Vd,Vt,SVm", MATCH_VFRDIVVF, MASK_VFRDIVVF, match_vd_neq_vm, 0},
++
++{"vfwmul.vv",  0, INSN_CLASS_V_AND_F, "Vd,Vt,VsVm", MATCH_VFWMULVV, MASK_VFWMULVV, match_widen_vd_neq_vs1_neq_vs2_neq_vm, 0},
++{"vfwmul.vf",  0, INSN_CLASS_V_AND_F, "Vd,Vt,SVm", MATCH_VFWMULVF, MASK_VFWMULVF, match_widen_vd_neq_vs2_neq_vm, 0},
++
++{"vfmadd.vv",  0, INSN_CLASS_V_AND_F, "Vd,Vs,VtVm", MATCH_VFMADDVV, MASK_VFMADDVV, match_vd_neq_vm, 0},
++{"vfmadd.vf",  0, INSN_CLASS_V_AND_F, "Vd,S,VtVm", MATCH_VFMADDVF, MASK_VFMADDVF, match_vd_neq_vm, 0},
++{"vfnmadd.vv", 0, INSN_CLASS_V_AND_F, "Vd,Vs,VtVm", MATCH_VFNMADDVV, MASK_VFNMADDVV, match_vd_neq_vm, 0},
++{"vfnmadd.vf", 0, INSN_CLASS_V_AND_F, "Vd,S,VtVm", MATCH_VFNMADDVF, MASK_VFNMADDVF, match_vd_neq_vm, 0},
++{"vfmsub.vv",  0, INSN_CLASS_V_AND_F, "Vd,Vs,VtVm", MATCH_VFMSUBVV, MASK_VFMSUBVV, match_vd_neq_vm, 0},
++{"vfmsub.vf",  0, INSN_CLASS_V_AND_F, "Vd,S,VtVm", MATCH_VFMSUBVF, MASK_VFMSUBVF, match_vd_neq_vm, 0},
++{"vfnmsub.vv", 0, INSN_CLASS_V_AND_F, "Vd,Vs,VtVm", MATCH_VFNMSUBVV, MASK_VFNMSUBVV, match_vd_neq_vm, 0},
++{"vfnmsub.vf", 0, INSN_CLASS_V_AND_F, "Vd,S,VtVm", MATCH_VFNMSUBVF, MASK_VFNMSUBVF, match_vd_neq_vm, 0},
++{"vfmacc.vv",  0, INSN_CLASS_V_AND_F, "Vd,Vs,VtVm", MATCH_VFMACCVV, MASK_VFMACCVV, match_vd_neq_vm, 0},
++{"vfmacc.vf",  0, INSN_CLASS_V_AND_F, "Vd,S,VtVm", MATCH_VFMACCVF, MASK_VFMACCVF, match_vd_neq_vm, 0},
++{"vfnmacc.vv", 0, INSN_CLASS_V_AND_F, "Vd,Vs,VtVm", MATCH_VFNMACCVV, MASK_VFNMACCVV, match_vd_neq_vm, 0},
++{"vfnmacc.vf", 0, INSN_CLASS_V_AND_F, "Vd,S,VtVm", MATCH_VFNMACCVF, MASK_VFNMACCVF, match_vd_neq_vm, 0},
++{"vfmsac.vv",  0, INSN_CLASS_V_AND_F, "Vd,Vs,VtVm", MATCH_VFMSACVV, MASK_VFMSACVV, match_vd_neq_vm, 0},
++{"vfmsac.vf",  0, INSN_CLASS_V_AND_F, "Vd,S,VtVm", MATCH_VFMSACVF, MASK_VFMSACVF, match_vd_neq_vm, 0},
++{"vfnmsac.vv", 0, INSN_CLASS_V_AND_F, "Vd,Vs,VtVm", MATCH_VFNMSACVV, MASK_VFNMSACVV, match_vd_neq_vm, 0},
++{"vfnmsac.vf", 0, INSN_CLASS_V_AND_F, "Vd,S,VtVm", MATCH_VFNMSACVF, MASK_VFNMSACVF, match_vd_neq_vm, 0},
++
++{"vfwmacc.vv",  0, INSN_CLASS_V_AND_F, "Vd,Vs,VtVm", MATCH_VFWMACCVV, MASK_VFWMACCVV, match_widen_vd_neq_vs1_neq_vs2_neq_vm, 0},
++{"vfwmacc.vf",  0, INSN_CLASS_V_AND_F, "Vd,S,VtVm", MATCH_VFWMACCVF, MASK_VFWMACCVF, match_widen_vd_neq_vs2_neq_vm, 0},
++{"vfwnmacc.vv", 0, INSN_CLASS_V_AND_F, "Vd,Vs,VtVm", MATCH_VFWNMACCVV, MASK_VFWNMACCVV, match_widen_vd_neq_vs1_neq_vs2_neq_vm, 0},
++{"vfwnmacc.vf", 0, INSN_CLASS_V_AND_F, "Vd,S,VtVm", MATCH_VFWNMACCVF, MASK_VFWNMACCVF, match_widen_vd_neq_vs2_neq_vm, 0},
++{"vfwmsac.vv",  0, INSN_CLASS_V_AND_F, "Vd,Vs,VtVm", MATCH_VFWMSACVV, MASK_VFWMSACVV, match_widen_vd_neq_vs1_neq_vs2_neq_vm, 0},
++{"vfwmsac.vf",  0, INSN_CLASS_V_AND_F, "Vd,S,VtVm", MATCH_VFWMSACVF, MASK_VFWMSACVF, match_widen_vd_neq_vs2_neq_vm, 0},
++{"vfwnmsac.vv", 0, INSN_CLASS_V_AND_F, "Vd,Vs,VtVm", MATCH_VFWNMSACVV, MASK_VFWNMSACVV, match_widen_vd_neq_vs1_neq_vs2_neq_vm, 0},
++{"vfwnmsac.vf", 0, INSN_CLASS_V_AND_F, "Vd,S,VtVm", MATCH_VFWNMSACVF, MASK_VFWNMSACVF, match_widen_vd_neq_vs2_neq_vm, 0},
++
++{"vfsqrt.v",   0, INSN_CLASS_V_AND_F, "Vd,VtVm", MATCH_VFSQRTV, MASK_VFSQRTV, match_vd_neq_vm, 0},
++{"vfrsqrt7.v", 0, INSN_CLASS_V_AND_F, "Vd,VtVm", MATCH_VFRSQRT7V, MASK_VFRSQRT7V, match_vd_neq_vm, 0},
++{"vfrsqrte7.v",0, INSN_CLASS_V_AND_F, "Vd,VtVm", MATCH_VFRSQRT7V, MASK_VFRSQRT7V, match_vd_neq_vm, 0},
++{"vfrec7.v",   0, INSN_CLASS_V_AND_F, "Vd,VtVm", MATCH_VFREC7V, MASK_VFREC7V, match_vd_neq_vm, 0},
++{"vfrece7.v",  0, INSN_CLASS_V_AND_F, "Vd,VtVm", MATCH_VFREC7V, MASK_VFREC7V, match_vd_neq_vm, 0},
++{"vfclass.v",  0, INSN_CLASS_V_AND_F, "Vd,VtVm", MATCH_VFCLASSV, MASK_VFCLASSV, match_vd_neq_vm, 0},
++
++{"vfmin.vv",   0, INSN_CLASS_V_AND_F, "Vd,Vt,VsVm", MATCH_VFMINVV, MASK_VFMINVV, match_vd_neq_vm, 0},
++{"vfmin.vf",   0, INSN_CLASS_V_AND_F, "Vd,Vt,SVm", MATCH_VFMINVF, MASK_VFMINVF, match_vd_neq_vm, 0},
++{"vfmax.vv",   0, INSN_CLASS_V_AND_F, "Vd,Vt,VsVm", MATCH_VFMAXVV, MASK_VFMAXVV, match_vd_neq_vm, 0},
++{"vfmax.vf",   0, INSN_CLASS_V_AND_F, "Vd,Vt,SVm", MATCH_VFMAXVF, MASK_VFMAXVF, match_vd_neq_vm, 0},
++
++{"vfneg.v",    0, INSN_CLASS_V_AND_F, "Vd,VuVm", MATCH_VFSGNJNVV, MASK_VFSGNJNVV, match_vs1_eq_vs2_neq_vm, INSN_ALIAS },
++{"vfabs.v",    0, INSN_CLASS_V_AND_F, "Vd,VuVm", MATCH_VFSGNJXVV, MASK_VFSGNJXVV, match_vs1_eq_vs2_neq_vm, INSN_ALIAS },
++
++{"vfsgnj.vv",  0, INSN_CLASS_V_AND_F, "Vd,Vt,VsVm", MATCH_VFSGNJVV, MASK_VFSGNJVV, match_vd_neq_vm, 0},
++{"vfsgnj.vf",  0, INSN_CLASS_V_AND_F, "Vd,Vt,SVm", MATCH_VFSGNJVF, MASK_VFSGNJVF, match_vd_neq_vm, 0},
++{"vfsgnjn.vv", 0, INSN_CLASS_V_AND_F, "Vd,Vt,VsVm", MATCH_VFSGNJNVV, MASK_VFSGNJNVV, match_vd_neq_vm, 0},
++{"vfsgnjn.vf", 0, INSN_CLASS_V_AND_F, "Vd,Vt,SVm", MATCH_VFSGNJNVF, MASK_VFSGNJNVF, match_vd_neq_vm, 0},
++{"vfsgnjx.vv", 0, INSN_CLASS_V_AND_F, "Vd,Vt,VsVm", MATCH_VFSGNJXVV, MASK_VFSGNJXVV, match_vd_neq_vm, 0},
++{"vfsgnjx.vf", 0, INSN_CLASS_V_AND_F, "Vd,Vt,SVm", MATCH_VFSGNJXVF, MASK_VFSGNJXVF, match_vd_neq_vm, 0},
++
++{"vmfeq.vv",   0, INSN_CLASS_V_AND_F, "Vd,Vt,VsVm", MATCH_VMFEQVV, MASK_VMFEQVV, match_opcode, 0},
++{"vmfeq.vf",   0, INSN_CLASS_V_AND_F, "Vd,Vt,SVm", MATCH_VMFEQVF, MASK_VMFEQVF, match_opcode, 0},
++{"vmfne.vv",   0, INSN_CLASS_V_AND_F, "Vd,Vt,VsVm", MATCH_VMFNEVV, MASK_VMFNEVV, match_opcode, 0},
++{"vmfne.vf",   0, INSN_CLASS_V_AND_F, "Vd,Vt,SVm", MATCH_VMFNEVF, MASK_VMFNEVF, match_opcode, 0},
++{"vmflt.vv",   0, INSN_CLASS_V_AND_F, "Vd,Vt,VsVm", MATCH_VMFLTVV, MASK_VMFLTVV, match_opcode, 0},
++{"vmflt.vf",   0, INSN_CLASS_V_AND_F, "Vd,Vt,SVm", MATCH_VMFLTVF, MASK_VMFLTVF, match_opcode, 0},
++{"vmfle.vv",   0, INSN_CLASS_V_AND_F, "Vd,Vt,VsVm", MATCH_VMFLEVV, MASK_VMFLEVV, match_opcode, 0},
++{"vmfle.vf",   0, INSN_CLASS_V_AND_F, "Vd,Vt,SVm", MATCH_VMFLEVF, MASK_VMFLEVF, match_opcode, 0},
++{"vmfgt.vf",   0, INSN_CLASS_V_AND_F, "Vd,Vt,SVm", MATCH_VMFGTVF, MASK_VMFGTVF, match_opcode, 0},
++{"vmfge.vf",   0, INSN_CLASS_V_AND_F, "Vd,Vt,SVm", MATCH_VMFGEVF, MASK_VMFGEVF, match_opcode, 0},
++
++/* These aliases are for assembly but not disassembly.  */
++{"vmfgt.vv",    0, INSN_CLASS_V_AND_F, "Vd,Vs,VtVm", MATCH_VMFLTVV, MASK_VMFLTVV, match_opcode, INSN_ALIAS},
++{"vmfge.vv",   0, INSN_CLASS_V_AND_F, "Vd,Vs,VtVm", MATCH_VMFLEVV, MASK_VMFLEVV, match_opcode, INSN_ALIAS},
++
++{"vfmerge.vfm",0, INSN_CLASS_V_AND_F, "Vd,Vt,S,V0", MATCH_VFMERGEVFM, MASK_VFMERGEVFM, match_opcode, 0},
++{"vfmv.v.f",   0, INSN_CLASS_V_AND_F, "Vd,S", MATCH_VFMVVF, MASK_VFMVVF, match_opcode, 0 },
++
++{"vfcvt.xu.f.v",     0, INSN_CLASS_V_AND_F, "Vd,VtVm", MATCH_VFCVTXUFV, MASK_VFCVTXUFV, match_vd_neq_vm, 0},
++{"vfcvt.x.f.v",      0, INSN_CLASS_V_AND_F, "Vd,VtVm", MATCH_VFCVTXFV, MASK_VFCVTXFV, match_vd_neq_vm, 0},
++{"vfcvt.rtz.xu.f.v", 0, INSN_CLASS_V_AND_F, "Vd,VtVm", MATCH_VFCVTRTZXUFV, MASK_VFCVTRTZXUFV, match_vd_neq_vm, 0},
++{"vfcvt.rtz.x.f.v",  0, INSN_CLASS_V_AND_F, "Vd,VtVm", MATCH_VFCVTRTZXFV, MASK_VFCVTRTZXFV, match_vd_neq_vm, 0},
++{"vfcvt.f.xu.v",     0, INSN_CLASS_V_AND_F, "Vd,VtVm", MATCH_VFCVTFXUV, MASK_VFCVTFXUV, match_vd_neq_vm, 0},
++{"vfcvt.f.x.v",      0, INSN_CLASS_V_AND_F, "Vd,VtVm", MATCH_VFCVTFXV, MASK_VFCVTFXV, match_vd_neq_vm, 0},
++
++{"vfwcvt.xu.f.v",     0, INSN_CLASS_V_AND_F, "Vd,VtVm", MATCH_VFWCVTXUFV, MASK_VFWCVTXUFV, match_widen_vd_neq_vs2_neq_vm, 0},
++{"vfwcvt.x.f.v",      0, INSN_CLASS_V_AND_F, "Vd,VtVm", MATCH_VFWCVTXFV, MASK_VFWCVTXFV, match_widen_vd_neq_vs2_neq_vm, 0},
++{"vfwcvt.rtz.xu.f.v", 0, INSN_CLASS_V_AND_F, "Vd,VtVm", MATCH_VFWCVTRTZXUFV, MASK_VFWCVTRTZXUFV, match_widen_vd_neq_vs2_neq_vm, 0},
++{"vfwcvt.rtz.x.f.v",  0, INSN_CLASS_V_AND_F, "Vd,VtVm", MATCH_VFWCVTRTZXFV, MASK_VFWCVTRTZXFV, match_widen_vd_neq_vs2_neq_vm, 0},
++{"vfwcvt.f.xu.v",     0, INSN_CLASS_V_AND_F, "Vd,VtVm", MATCH_VFWCVTFXUV, MASK_VFWCVTFXUV, match_widen_vd_neq_vs2_neq_vm, 0},
++{"vfwcvt.f.x.v",      0, INSN_CLASS_V_AND_F, "Vd,VtVm", MATCH_VFWCVTFXV, MASK_VFWCVTFXV, match_widen_vd_neq_vs2_neq_vm, 0},
++{"vfwcvt.f.f.v",      0, INSN_CLASS_V_AND_F, "Vd,VtVm", MATCH_VFWCVTFFV, MASK_VFWCVTFFV, match_widen_vd_neq_vs2_neq_vm, 0},
++
++{"vfncvt.xu.f.w",     0, INSN_CLASS_V_AND_F, "Vd,VtVm", MATCH_VFNCVTXUFW, MASK_VFNCVTXUFW, match_narrow_vd_neq_vs2_neq_vm, 0},
++{"vfncvt.x.f.w",      0, INSN_CLASS_V_AND_F, "Vd,VtVm", MATCH_VFNCVTXFW, MASK_VFNCVTXFW, match_narrow_vd_neq_vs2_neq_vm, 0},
++{"vfncvt.rtz.xu.f.w", 0, INSN_CLASS_V_AND_F, "Vd,VtVm", MATCH_VFNCVTRTZXUFW, MASK_VFNCVTRTZXUFW, match_narrow_vd_neq_vs2_neq_vm, 0},
++{"vfncvt.rtz.x.f.w",  0, INSN_CLASS_V_AND_F, "Vd,VtVm", MATCH_VFNCVTRTZXFW, MASK_VFNCVTRTZXFW, match_narrow_vd_neq_vs2_neq_vm, 0},
++{"vfncvt.f.xu.w",     0, INSN_CLASS_V_AND_F, "Vd,VtVm", MATCH_VFNCVTFXUW, MASK_VFNCVTFXUW, match_narrow_vd_neq_vs2_neq_vm, 0},
++{"vfncvt.f.x.w",      0, INSN_CLASS_V_AND_F, "Vd,VtVm", MATCH_VFNCVTFXW, MASK_VFNCVTFXW, match_narrow_vd_neq_vs2_neq_vm, 0},
++{"vfncvt.f.f.w",      0, INSN_CLASS_V_AND_F, "Vd,VtVm", MATCH_VFNCVTFFW, MASK_VFNCVTFFW, match_narrow_vd_neq_vs2_neq_vm, 0},
++{"vfncvt.rod.f.f.w",  0, INSN_CLASS_V_AND_F, "Vd,VtVm", MATCH_VFNCVTRODFFW, MASK_VFNCVTRODFFW, match_narrow_vd_neq_vs2_neq_vm, 0},
++
++{"vredsum.vs", 0, INSN_CLASS_V, "Vd,Vt,VsVm", MATCH_VREDSUMVS, MASK_VREDSUMVS, match_opcode, 0},
++{"vredmaxu.vs",0, INSN_CLASS_V, "Vd,Vt,VsVm", MATCH_VREDMAXUVS, MASK_VREDMAXUVS, match_opcode, 0},
++{"vredmax.vs", 0, INSN_CLASS_V, "Vd,Vt,VsVm", MATCH_VREDMAXVS, MASK_VREDMAXVS, match_opcode, 0},
++{"vredminu.vs",0, INSN_CLASS_V, "Vd,Vt,VsVm", MATCH_VREDMINUVS, MASK_VREDMINUVS, match_opcode, 0},
++{"vredmin.vs", 0, INSN_CLASS_V, "Vd,Vt,VsVm", MATCH_VREDMINVS, MASK_VREDMINVS, match_opcode, 0},
++{"vredand.vs", 0, INSN_CLASS_V, "Vd,Vt,VsVm", MATCH_VREDANDVS, MASK_VREDANDVS, match_opcode, 0},
++{"vredor.vs",  0, INSN_CLASS_V, "Vd,Vt,VsVm", MATCH_VREDORVS, MASK_VREDORVS, match_opcode, 0},
++{"vredxor.vs", 0, INSN_CLASS_V, "Vd,Vt,VsVm", MATCH_VREDXORVS, MASK_VREDXORVS, match_opcode, 0},
++
++{"vwredsumu.vs",0, INSN_CLASS_V, "Vd,Vt,VsVm", MATCH_VWREDSUMUVS, MASK_VWREDSUMUVS, match_opcode, 0},
++{"vwredsum.vs",0, INSN_CLASS_V, "Vd,Vt,VsVm", MATCH_VWREDSUMVS, MASK_VWREDSUMVS, match_opcode, 0},
++
++{"vfredosum.vs",0, INSN_CLASS_V_AND_F, "Vd,Vt,VsVm", MATCH_VFREDOSUMVS, MASK_VFREDOSUMVS, match_opcode, 0},
++{"vfredsum.vs", 0, INSN_CLASS_V_AND_F, "Vd,Vt,VsVm", MATCH_VFREDSUMVS, MASK_VFREDSUMVS, match_opcode, 0},
++{"vfredmax.vs", 0, INSN_CLASS_V_AND_F, "Vd,Vt,VsVm", MATCH_VFREDMAXVS, MASK_VFREDMAXVS, match_opcode, 0},
++{"vfredmin.vs", 0, INSN_CLASS_V_AND_F, "Vd,Vt,VsVm", MATCH_VFREDMINVS, MASK_VFREDMINVS, match_opcode, 0},
++
++{"vfwredosum.vs",0, INSN_CLASS_V_AND_F, "Vd,Vt,VsVm", MATCH_VFWREDOSUMVS, MASK_VFWREDOSUMVS, match_opcode, 0},
++{"vfwredsum.vs", 0, INSN_CLASS_V_AND_F, "Vd,Vt,VsVm", MATCH_VFWREDSUMVS, MASK_VFWREDSUMVS, match_opcode, 0},
++
++{"vmmv.m",     0, INSN_CLASS_V, "Vd,Vu", MATCH_VMANDMM, MASK_VMANDMM, match_vs1_eq_vs2, INSN_ALIAS},
++{"vmcpy.m",    0, INSN_CLASS_V, "Vd,Vu", MATCH_VMANDMM, MASK_VMANDMM, match_vs1_eq_vs2, INSN_ALIAS},
++{"vmclr.m",    0, INSN_CLASS_V, "Vv", MATCH_VMXORMM, MASK_VMXORMM, match_vd_eq_vs1_eq_vs2, INSN_ALIAS},
++{"vmset.m",    0, INSN_CLASS_V, "Vv", MATCH_VMXNORMM, MASK_VMXNORMM, match_vd_eq_vs1_eq_vs2, INSN_ALIAS},
++{"vmnot.m",    0, INSN_CLASS_V, "Vd,Vu", MATCH_VMNANDMM, MASK_VMNANDMM, match_vs1_eq_vs2, INSN_ALIAS},
++
++{"vmand.mm",   0, INSN_CLASS_V, "Vd,Vt,Vs", MATCH_VMANDMM, MASK_VMANDMM, match_opcode, 0},
++{"vmnand.mm",  0, INSN_CLASS_V, "Vd,Vt,Vs", MATCH_VMNANDMM, MASK_VMNANDMM, match_opcode, 0},
++{"vmandnot.mm",0, INSN_CLASS_V, "Vd,Vt,Vs", MATCH_VMANDNOTMM, MASK_VMANDNOTMM, match_opcode, 0},
++{"vmxor.mm",   0, INSN_CLASS_V, "Vd,Vt,Vs", MATCH_VMXORMM, MASK_VMXORMM, match_opcode, 0},
++{"vmor.mm",    0, INSN_CLASS_V, "Vd,Vt,Vs", MATCH_VMORMM, MASK_VMORMM, match_opcode, 0},
++{"vmnor.mm",   0, INSN_CLASS_V, "Vd,Vt,Vs", MATCH_VMNORMM, MASK_VMNORMM, match_opcode, 0},
++{"vmornot.mm", 0, INSN_CLASS_V, "Vd,Vt,Vs", MATCH_VMORNOTMM, MASK_VMORNOTMM, match_opcode, 0},
++{"vmxnor.mm",  0, INSN_CLASS_V, "Vd,Vt,Vs", MATCH_VMXNORMM, MASK_VMXNORMM, match_opcode, 0},
++
++{"vpopc.m",    0, INSN_CLASS_V, "d,VtVm", MATCH_VPOPCM, MASK_VPOPCM, match_opcode, 0},
++{"vfirst.m",   0, INSN_CLASS_V, "d,VtVm", MATCH_VFIRSTM, MASK_VFIRSTM, match_opcode, 0},
++{"vmsbf.m",    0, INSN_CLASS_V, "Vd,VtVm", MATCH_VMSBFM, MASK_VMSBFM, match_vd_neq_vs2_neq_vm, 0},
++{"vmsif.m",    0, INSN_CLASS_V, "Vd,VtVm", MATCH_VMSIFM, MASK_VMSIFM, match_vd_neq_vs2_neq_vm, 0},
++{"vmsof.m",    0, INSN_CLASS_V, "Vd,VtVm", MATCH_VMSOFM, MASK_VMSOFM, match_vd_neq_vs2_neq_vm, 0},
++{"viota.m",    0, INSN_CLASS_V, "Vd,VtVm", MATCH_VIOTAM, MASK_VIOTAM, match_vd_neq_vs2_neq_vm, 0},
++{"vid.v",      0, INSN_CLASS_V, "VdVm", MATCH_VIDV, MASK_VIDV, match_vd_neq_vm, 0},
++
++{"vmv.x.s",    0, INSN_CLASS_V, "d,Vt", MATCH_VMVXS, MASK_VMVXS, match_opcode, 0},
++{"vmv.s.x",    0, INSN_CLASS_V, "Vd,s", MATCH_VMVSX, MASK_VMVSX, match_opcode, 0},
++
++{"vfmv.f.s",   0, INSN_CLASS_V_AND_F, "D,Vt", MATCH_VFMVFS, MASK_VFMVFS, match_opcode, 0},
++{"vfmv.s.f",   0, INSN_CLASS_V_AND_F, "Vd,S", MATCH_VFMVSF, MASK_VFMVSF, match_opcode, 0},
++
++{"vslideup.vx",0, INSN_CLASS_V, "Vd,Vt,sVm", MATCH_VSLIDEUPVX, MASK_VSLIDEUPVX, match_vd_neq_vs2_neq_vm, 0},
++{"vslideup.vi",0, INSN_CLASS_V, "Vd,Vt,VjVm", MATCH_VSLIDEUPVI, MASK_VSLIDEUPVI, match_vd_neq_vs2_neq_vm, 0},
++{"vslidedown.vx",0,INSN_CLASS_V, "Vd,Vt,sVm", MATCH_VSLIDEDOWNVX, MASK_VSLIDEDOWNVX, match_vd_neq_vm, 0},
++{"vslidedown.vi",0,INSN_CLASS_V, "Vd,Vt,VjVm", MATCH_VSLIDEDOWNVI, MASK_VSLIDEDOWNVI, match_vd_neq_vm, 0},
++
++{"vslide1up.vx",    0, INSN_CLASS_V, "Vd,Vt,sVm", MATCH_VSLIDE1UPVX, MASK_VSLIDE1UPVX, match_vd_neq_vs2_neq_vm, 0},
++{"vslide1down.vx",  0, INSN_CLASS_V, "Vd,Vt,sVm", MATCH_VSLIDE1DOWNVX, MASK_VSLIDE1DOWNVX, match_vd_neq_vm, 0},
++{"vfslide1up.vf",   0, INSN_CLASS_V_AND_F, "Vd,Vt,SVm", MATCH_VFSLIDE1UPVF, MASK_VFSLIDE1UPVF, match_vd_neq_vs2_neq_vm, 0},
++{"vfslide1down.vf", 0, INSN_CLASS_V_AND_F, "Vd,Vt,SVm", MATCH_VFSLIDE1DOWNVF, MASK_VFSLIDE1DOWNVF, match_vd_neq_vm, 0},
++
++{"vrgather.vv",    0, INSN_CLASS_V, "Vd,Vt,VsVm", MATCH_VRGATHERVV, MASK_VRGATHERVV, match_vd_neq_vs1_neq_vs2_neq_vm, 0},
++{"vrgather.vx",    0, INSN_CLASS_V, "Vd,Vt,sVm", MATCH_VRGATHERVX, MASK_VRGATHERVX, match_vd_neq_vs2_neq_vm, 0},
++{"vrgather.vi",    0, INSN_CLASS_V, "Vd,Vt,VjVm", MATCH_VRGATHERVI, MASK_VRGATHERVI, match_vd_neq_vs2_neq_vm, 0},
++{"vrgatherei16.vv",0, INSN_CLASS_V, "Vd,Vt,VsVm", MATCH_VRGATHEREI16VV, MASK_VRGATHEREI16VV, match_vd_neq_vs1_neq_vs2_neq_vm, 0},
++
++{"vcompress.vm",0, INSN_CLASS_V, "Vd,Vt,Vs", MATCH_VCOMPRESSVM, MASK_VCOMPRESSVM, match_vd_neq_vs1_neq_vs2, 0},
++
++{"vmv1r.v",    0, INSN_CLASS_V, "Vd,Vt", MATCH_VMV1RV, MASK_VMV1RV, match_vmv_nf_rv, 0},
++{"vmv2r.v",    0, INSN_CLASS_V, "Vd,Vt", MATCH_VMV2RV, MASK_VMV2RV, match_vmv_nf_rv, 0},
++{"vmv4r.v",    0, INSN_CLASS_V, "Vd,Vt", MATCH_VMV4RV, MASK_VMV4RV, match_vmv_nf_rv, 0},
++{"vmv8r.v",    0, INSN_CLASS_V, "Vd,Vt", MATCH_VMV8RV, MASK_VMV8RV, match_vmv_nf_rv, 0},
++/* END RVV */
+ /* Terminate the list.  */
+ {0, 0, INSN_CLASS_NONE, 0, 0, 0, 0, 0}
+ };
+@@ -929,6 +2120,26 @@ const struct riscv_opcode riscv_insn_types[] =
+ {"r",       0, INSN_CLASS_F,  "O4,F3,F7,d,S,T",     0,    0,  match_opcode, 0 },
+ {"r",       0, INSN_CLASS_F,  "O4,F3,F7,D,S,T",     0,    0,  match_opcode, 0 },
+ 
++{"r",       0, INSN_CLASS_V,        "O4,F3,F7,Vd,s,t",    0,    0,  match_opcode, 0 },
++{"r",       0, INSN_CLASS_V_AND_F,  "O4,F3,F7,Vd,S,t",    0,    0,  match_opcode, 0 },
++{"r",       0, INSN_CLASS_V_AND_F,  "O4,F3,F7,Vd,s,T",    0,    0,  match_opcode, 0 },
++{"r",       0, INSN_CLASS_V_AND_F,  "O4,F3,F7,Vd,S,T",    0,    0,  match_opcode, 0 },
++{"r",       0, INSN_CLASS_V,        "O4,F3,F7,d,Vs,t",    0,    0,  match_opcode, 0 },
++{"r",       0, INSN_CLASS_V_AND_F,  "O4,F3,F7,D,Vs,t",    0,    0,  match_opcode, 0 },
++{"r",       0, INSN_CLASS_V_AND_F,  "O4,F3,F7,d,Vs,T",    0,    0,  match_opcode, 0 },
++{"r",       0, INSN_CLASS_V_AND_F,  "O4,F3,F7,D,Vs,T",    0,    0,  match_opcode, 0 },
++{"r",       0, INSN_CLASS_V,        "O4,F3,F7,d,s,Vt",    0,    0,  match_opcode, 0 },
++{"r",       0, INSN_CLASS_V_AND_F,  "O4,F3,F7,D,s,Vt",    0,    0,  match_opcode, 0 },
++{"r",       0, INSN_CLASS_V_AND_F,  "O4,F3,F7,d,S,Vt",    0,    0,  match_opcode, 0 },
++{"r",       0, INSN_CLASS_V_AND_F,  "O4,F3,F7,D,S,Vt",    0,    0,  match_opcode, 0 },
++{"r",       0, INSN_CLASS_V,        "O4,F3,F7,Vd,Vs,t",   0,    0,  match_opcode, 0 },
++{"r",       0, INSN_CLASS_V_AND_F,  "O4,F3,F7,Vd,Vs,T",   0,    0,  match_opcode, 0 },
++{"r",       0, INSN_CLASS_V,        "O4,F3,F7,Vd,s,Vt",   0,    0,  match_opcode, 0 },
++{"r",       0, INSN_CLASS_V_AND_F,  "O4,F3,F7,Vd,S,Vt",   0,    0,  match_opcode, 0 },
++{"r",       0, INSN_CLASS_V,        "O4,F3,F7,d,Vs,Vt",   0,    0,  match_opcode, 0 },
++{"r",       0, INSN_CLASS_V_AND_F,  "O4,F3,F7,D,Vs,Vt",   0,    0,  match_opcode, 0 },
++{"r",       0, INSN_CLASS_V,        "O4,F3,F7,Vd,Vs,Vt",  0,    0,  match_opcode, 0 },
++
+ {"r",       0, INSN_CLASS_I,  "O4,F3,F2,d,s,t,r",   0,    0,  match_opcode, 0 },
+ {"r",       0, INSN_CLASS_F,  "O4,F3,F2,D,s,t,r",   0,    0,  match_opcode, 0 },
+ {"r",       0, INSN_CLASS_F,  "O4,F3,F2,d,S,t,r",   0,    0,  match_opcode, 0 },
+@@ -1073,6 +2284,8 @@ const struct riscv_ext_version riscv_ext_version_table[] =
+ {"zbs",   ISA_SPEC_CLASS_DRAFT, 0, 93},
+ {"zbt",   ISA_SPEC_CLASS_DRAFT, 0, 93},
+ 
++{"zvamo",   ISA_SPEC_CLASS_NONE, 1, 0},
++{"zvlsseg", ISA_SPEC_CLASS_NONE, 1, 0},
+ 
+ /* Terminate the list.  */
+ {NULL, 0, 0, 0}
+-- 
+2.33.0
+

+ 523 - 0
recipes-devtools/binutils/binutils/0004-add-missed-sysroff-file.patch

@@ -0,0 +1,523 @@
+From 7a9c43b6434bdddd8557a8144369a0c9bcfba977 Mon Sep 17 00:00:00 2001
+From: "max.ma" <max.ma@starfivetech.com>
+Date: Wed, 2 Jun 2021 23:43:41 -0700
+Subject: [PATCH 04/28] add missed sysroff file
+
+---
+ binutils/sysroff.info | 504 ++++++++++++++++++++++++++++++++++++++++++
+ 1 file changed, 504 insertions(+)
+ create mode 100755 binutils/sysroff.info
+
+diff --git a/binutils/sysroff.info b/binutils/sysroff.info
+new file mode 100755
+index 0000000000..d82157669a
+--- /dev/null
++++ b/binutils/sysroff.info
+@@ -0,0 +1,504 @@
++("cs" 0x0
++ (("size") (1 byte) ("size"))
++
++ (("hd") (1 byte) ("hd"))
++ (("hs") (1 byte) ("hs"))
++ (("un") (1 byte) ("un"))
++ (("us") (1 byte) ("us"))
++
++ (("sc") (1 byte) ("sc"))
++ (("ss") (1 byte) ("ss"))
++ (("er") (1 byte) ("er"))
++ (("ed") (1 byte) ("ed"))
++
++ (("sh") (1 byte) ("sh"))
++ (("ob") (1 byte) ("ob"))
++ (("rl") (1 byte) ("rl"))
++ (("du") (1 byte) ("du"))
++
++ (("dps") (1 byte) ("dps"))
++ (("dsy") (1 byte) ("dsy"))
++ (("dty") (1 byte) ("dty"))
++ (("dln") (1 byte) ("dln"))
++
++ (("dso") (1 byte) ("dso"))
++ (("dus") (1 byte) ("dus"))
++ (("dss") (1 byte) ("dss"))
++ (("dbt") (1 byte) ("dbt"))
++
++ (("dpp") (1 byte) ("dpp"))
++ (("dfp") (1 byte) ("dfp"))
++ (("den") (1 byte) ("den"))
++ (("dds") (1 byte) ("dds"))
++
++ (("dar") (1 byte) ("dar"))
++ (("dpt") (1 byte) ("dpt"))
++ (("dul") (1 byte) ("dul"))
++ (("dse") (1 byte) ("dse"))
++
++ (("dot") (1 byte) ("dot")))
++
++
++("hd" 0x04
++ (("module type") (4 bits) ("mt")
++  (("MTYPE_ABS_LM" 	"0")
++   ("MTYPE_REL_LM" 	"1")
++   ("MTYPE_OMS_OR_LMS" 	"2")
++   ("MTYPE_UNSPEC" 	"0xf")))
++ (("spare")(4 bits) ("spare1"))
++ (("creation date")( chars 12 bytes)( "cd"))
++ (("number of units") (2 bytes) ("nu"))
++ (("code") (1 byte) ("code"))
++ (("version") (chars 4 bytes) ("ver"))
++ (("address update") (1 byte) ("au"))
++ (("segment identifier") (1 bit) ("si"))
++ (("address field length") (4 bits) ("afl"))
++ (("spare")(3 bits) ("spare2"))
++ (("space size within segment") (1 byte) ("spcsz"))
++ (("segment size")  	(1 byte) ("segsz"))
++ (("segment shift") 	(1 byte) ("segsh"))
++ (("entry point") 	(1 byte) ("ep"))
++ (cond "ptr->ep"
++       (cond "ptr->mt != MTYPE_ABS_LM"
++	     (("unit appearance number") (2 bytes) ("uan"))
++	     (("section appearance number") (2 bytes) ("sa")))
++       (cond "segmented_p"
++	     (("segment address") (segsize bytes) ("sad")))
++       (("address") (addrsize bytes) ("address")))
++ (("os name") (chars variable bytes) ("os"))
++ (("sys name") (chars variable bytes) ("sys"))
++ (("module name") (chars variable bytes) ("mn"))
++ (("cpu") (chars variable bytes) ("cpu")))
++
++
++("hs" 0x05
++ (("neg number") (2 bytes) ("neg")))
++
++
++("un" 0x06
++ (("format") (2 bits) ("format")
++  (("FORMAT_LM" "0")
++   ("FORMAT_OM" "1")
++   ("FORMAT_OMS_OR_LMS" "2")))
++ (("spare") (6 bits) ("spare1"))
++ (("number of sections") (2 bytes) ("nsections"))
++ (("number of external refs") (2 bytes) ("nextrefs"))
++ (("number of external defs") (2 bytes) ("nextdefs"))
++ (("unit name") (chars variable byte) ("name"))
++ (("tool name") (chars variable byte) ("tool"))
++ (("creation date") (chars 12 bytes) ("tcd"))
++ (("linker name") (chars variable byte) ("linker"))
++ (("creation date") (chars 12 bytes) ("lcd")))
++
++
++("us" 0x07
++ (("negotiation number") (2 bytes) ("neg")))
++
++
++("sc" 0x08
++ (("format") (2 bits) ("format"))
++ (("spare") (6 bits) ("spare"))
++ (("segment address") (segsize bytes) ("segadd"))
++ (("address") (addrsize bytes) ("addr"))
++ (("length") (addrsize bytes) ("length"))
++ (("alignment") (addrsize bytes) ("align"))
++ (("contents") (4 bits) ("contents")
++  (("CONTENTS_CODE" "0")
++   ("CONTENTS_DATA" "1")
++   ("CONTENTS_STACK" "2")
++   ("CONTENTS_DUMMY" "3")
++   ("CONTENTS_SPECIAL" "4")
++   ("CONTENTS_NONSPEC" "0xf")))
++ (("concat") (4 bits) ("concat")
++  (("CONCAT_SIMPLE" "0")
++   ("CONCAT_SHAREDC" "1")
++   ("CONCAT_DUMMY" "2")
++   ("CONCAT_GROUP" "3")
++   ("CONCAT_SHARED" "4")
++   ("CONCAT_PRIVATE" "5")
++   ("CONCAT_UNSPEC" "0xf")))
++ (("read") (2 bits) ("read"))
++ (("write") (2 bits) ("write"))
++ (("exec") (2 bits) ("exec"))
++ (("initialized") (2 bits) ("init"))
++ (("mode") (2 bits) ("mode"))
++ (("spare") (6 bits) ("spare1"))
++ (("name") (chars variable byte) ("name")))
++
++
++("ss" 0x09
++ (("neg number") (2 bytes) ("neg")))
++
++
++("er" 0x0c
++ (("symbol type") (2 bits) ("type")
++  (("ER_ENTRY" "0")
++   ("ER_DATA" "1")
++   ("ER_NOTDEF" "2")
++   ("ER_NOTSPEC" "3")))
++ (("spare") (6 bits) ("spare"))
++ (("symbol name") (chars variable byte) ("name")))
++
++
++("ed" 0x14
++ (("section appearance number") (2 bytes) ("section"))
++ (("symbol type") (3 bits) ("type")
++  (("ED_TYPE_ENTRY" "0")
++   ("ED_TYPE_DATA" "1")
++   ("ED_TYPE_CONST" "2")
++   ("ED_TYPE_NOTSPEC" "7")))
++ (("spare") (5 bits) ("spare"))
++ (cond "ptr->type==ED_TYPE_ENTRY || ptr->type==ED_TYPE_DATA"
++       (("symbol address") (addrsize bytes) ("address")))
++ (cond "ptr->type==ED_TYPE_CONST"
++       (("constant value") (addrsize bytes) ("constant")))
++ (("symbol name") (chars variable byte) ("name")))
++
++
++("sh" 0x1a
++ (("unit appearance number") (2 bytes) ("unit"))
++ (("section appearance number") (2 bytes) ("section")))
++
++
++("ob" 0x1c
++ (("starting address flag") (1 bit) ("saf"))
++ (("compression flag") (1 bit) ("cpf"))
++ (("spare") (6 bits) ("spare"))
++ (cond "ptr->saf"
++       ( ("starting address") (addrsize bytes) ("address")))
++ (cond "ptr->cpf"
++       (("comp reps") (addrsize bytes) ("compreps")))
++ (("data") (barray counted byte) ("data")))
++
++
++("rl" 0x20
++ (("boundary of relocatable area") (4 bits) ("boundary"))
++ (("address polarity") (1 bit) ("apol"))
++ (("segment number") (1 bit) ("segment"))
++ (("sign of relocation") (1 bit) ("sign"))
++ (("check range") (1 bit) ("check"))
++ (("reloc address") (addrsize bytes) ("addr"))
++
++ (("bit loc") (1 byte) ("bitloc"))
++ (("field length") (1 byte) ("flen"))
++ (("bcount") (1 byte) ("bcount"))
++ (("operator") (1 byte) ("op")
++  (("OP_RELOC_ADDR" "1")
++   ("OP_SEC_REF" "0")
++   ("OP_EXT_REF" "2")))
++ (cond "ptr->op == OP_EXT_REF"
++       (("symbol number") (2 bytes) ("symn"))	)
++
++ (cond "ptr->op == OP_SEC_REF"
++       (("section number") (2 bytes) ("secn"))
++       (("const opcode") (1 byte) ("copcode_is_3"))
++       (("addend length") (1 byte) ("alength_is_4"))
++       (("addend") (4 byte) ("addend"))
++       (("plus opcode") (1 byte) ("aopcode_is_0x20")))
++
++ (cond "ptr->op == OP_RELOC_ADDR"
++       (("dunno") (2 bytes) ("dunno")))
++
++ (("end")  (1 byte) ("end")))
++
++
++("du" 0x30
++ (("format") (2 bits) ("format"))
++ (("optimized") (1 bit) ("optimized"))
++ (("stackfrmt") (2 bits) ("stackfrmt"))
++ (("spare") (3 bits) ("spare"))
++ (("unit number") (2 bytes) ("unit"))
++ (("sections") (2 bytes) ("sections"))
++ (repeat "ptr->sections"
++	 (("section appearance number") (2 bytes) ("san"))
++	 (("address") (addrsize bytes) ("address"))
++	 (("section length") (addrsize bytes) ("length")))
++ (("tool name") (chars variable byte) ("tool"))
++ (("creation date") (chars 12 bytes) ("date")))
++
++
++("dsy" 0x34
++ (("symbol type") (7 bits) ("type")
++  (("STYPE_VAR" "0")
++   ("STYPE_LAB" "1")
++   ("STYPE_PROC" "2")
++   ("STYPE_FUNC" "3")
++   ("STYPE_TYPE" "4")
++   ("STYPE_CONST" "5")
++   ("STYPE_ENTRY" "6")
++   ("STYPE_MEMBER" "7")
++   ("STYPE_ENUM" "8")
++   ("STYPE_TAG" "9")
++   ("STYPE_PACKAGE" "10")
++   ("STYPE_GENERIC" "11")
++   ("STYPE_TASK" "12")
++   ("STYPE_EXCEPTION" "13")
++   ("STYPE_PARAMETER" "14")
++   ("STYPE_EQUATE" "15")
++   ("STYPE_UNSPEC" "0x7f")))
++ (("assignment info") (1 bit) ("assign"))
++ (("symbol id") (2 bytes) ("snumber"))
++ (("symbol name") (chars variable bytes) ("sname"))
++ (("nesting level") (2 bytes) ("nesting"))
++ (cond "ptr->assign"
++       (("assignment type") (1 byte)  ("ainfo")
++	(("AINFO_REG" "1")
++	 ("AINFO_STATIC_EXT_DEF" "2")
++	 ("AINFO_STATIC_EXT_REF" "3")
++	 ("AINFO_STATIC_INT" "4")
++	 ("AINFO_STATIC_COM" "5")
++	 ("AINFO_AUTO" "6")
++	 ("AINFO_CONST" "7")
++	 ("AINFO_UNSPEC" "0xff")))
++       (("data length") (addrsize bytes) ("dlength"))
++       (cond "ptr->ainfo == AINFO_STATIC_EXT_DEF
++            || ptr->ainfo == AINFO_STATIC_INT
++            || ptr->ainfo == AINFO_STATIC_COM"
++	     (("section number")  (2 bytes) ("section")))
++       (cond "ptr->ainfo == AINFO_STATIC_EXT_DEF
++            || ptr->ainfo == AINFO_STATIC_INT
++            || ptr->ainfo == AINFO_STATIC_COM
++            || ptr->ainfo == AINFO_AUTO"
++	     (("address") (addrsize bytes) ("address")))
++       (cond "ptr->ainfo == AINFO_REG"
++	     (("register name") (chars variable bytes) ("reg")))
++       (cond "ptr->ainfo == AINFO_STATIC_EXT_DEF
++	    || ptr->ainfo == AINFO_STATIC_EXT_REF"
++	     (("external name") (chars variable bytes) ("ename")))
++       (cond "ptr->ainfo == AINFO_CONST"
++	     (("constant") (chars variable bytes) ("constant"))))
++ (cond "ptr->type == STYPE_MEMBER"
++       (("assignment unit") (1 bit) ("bitunit"))
++       (("spare") (7 bits) ("spare2"))
++       (("field length") (addrsize bytes) ("field_len"))
++       (("field offset") (addrsize bytes) ("field_off"))
++       (cond "ptr->bitunit"
++	     (("bit offset") (addrsize bytes) ("field_bitoff"))))
++ (cond "ptr->type== STYPE_ENUM"
++       (("value length") (1 byte) ("evallen"))
++       (("value") (4 bytes) ("evalue")))
++ (cond "ptr->type == STYPE_CONST"
++       (("value") (chars variable bytes) ("cvalue")))
++ (cond "ptr->type == STYPE_EQUATE"
++       (("value length") (1 byte) ("qvallen"))
++       (("value") (4 bytes) ("qvalue"))
++       (("basic type") (1 byte) ("btype"))
++       (("size information") (addrsize bytes) ("sizeinfo"))
++       (("sign") (2 bits) ("sign"))
++       (("floating point type") (6 bits) ("flt_type")))
++ (("source file number") (2 bytes) ("sfn"))
++ (("source line number") (2 bytes) ("sln"))
++ (("negotiation number") (2 bytes) ("neg"))
++ (cond "ptr->type == STYPE_TAG"
++       (("magic") (1 byte) ("magic"))))
++
++
++
++("dul" 0x52
++ (("max declaration type flag") (1 bit) ("max_variable"))
++ (("max spare") (7 bits) ("maxspare"))
++ (cond "ptr->max_variable == 0"
++       (("maximum") (addrsize bytes) ("max"))
++       (("max mode") (chars variable bytes) ("maxmode")))
++
++ (("min declaration type flag") (1 bit) ("min_variable"))
++ (("min spare") (7 bits) ("minspare"))
++ (cond "ptr->min_variable == 0"
++       (("minimum") (addrsize bytes) ("min"))
++       (("min mode") (chars variable bytes) ("minmode"))))
++
++
++("dty" 0x36
++ (("end flag") (1 bit) ("end"))
++ (("spare") (7 bits) ("spare"))
++ (cond "!ptr->end"
++       (("negotiation") (2 bytes) ("neg"))))
++
++
++("dbt" 0x44
++ (("basic type") (1 byte) ("btype")
++  (("BTYPE_VOID" "0")
++   ("BTYPE_UNDEF" "1")
++   ("BTYPE_CHAR" "2")
++   ("BTYPE_INT" "3")
++   ("BTYPE_FLOAT" "4")
++   ("BTYPE_BIT" "5")
++   ("BTYPE_STRING" "6")
++   ("BTYPE_DECIMAL" "7")
++   ("BTYPE_ENUM" "8")
++   ("BTYPE_STRUCT" "9")
++   ("BTYPE_TYPE" "10")
++   ("BTYPE_TAG" "11")
++   ("BTYPE_UNSPEC" "0xff")))
++ (("size info") (addrsize bytes) ("bitsize"))
++ (("sign") (2 bits) ("sign")
++  (("SIGN_SIGNED" "0")
++   ("SIGN_UNSIGNED" "1")
++   ("SIGN_UNSPEC" "3")))
++ (("floating point type") (6 bits) ("fptype")
++  (("FPTYPE_SINGLE" "0")
++   ("FPTYPE_DOUBLE" "1")
++   ("FPTYPE_EXTENDED" "2")
++   ("FPTYPE_NOTSPEC" "0x3f")))
++ (cond "ptr->btype==BTYPE_TAG || ptr->btype == BTYPE_TYPE"
++       (("symbol id") (2 bytes) ("sid")))
++ (("negotiation") (2 bytes) ("neg")))
++
++("dar" 0x4e
++ (("element length" ) (addrsize bytes) ("length"))
++ (("dims") (1 byte) ("dims"))
++ (repeat "ptr->dims"
++	 (("variable flag") (1 bit) ("variable")
++	  (("VARIABLE_FIXED" "0")
++	   ("VARIABLE_VARIABLE" "1")))
++
++	 (("subscript type") (1 bit) ("subtype")
++	  (("SUB_INTEGER" "0")
++	   ("SUB_TYPE"    "1")))
++
++	 (("spare") (6 bits) ("spare"))
++
++	 (cond "ptr->subtype[n] == SUB_TYPE"
++	       (("sub symbol id") (2 bytes) ("sid")))
++
++	 (cond "ptr->subtype[n] == SUB_INTEGER"
++	       (("max declaration type flag") (1 bit) ("max_variable"))
++	       (("max spare") (7 bits) ("maxspare"))
++	       ;; FIXME: next field should be conditional on max_variable,
++	       (("maximum") (addrsize bytes) ("max"))
++
++	       (("min declaration type flag") (1 bit) ("min_variable"))
++	       (("min spare") (7 bits) ("minspare"))
++	       ;; FIXME: next field should be conditional on min_variable
++	       (("minimum") (addrsize bytes) ("min"))))
++ (("negotiation") (2 bytes) ("neg")))
++
++
++("dso" 0x3a
++ (("function name") (2 bytes) ("sid"))
++ (("sp update count") (4 bytes) ("spupdates"))
++ (repeat "ptr->spupdates"
++	 (("update address") (addrsize bytes) ("address"))
++	 (("offset") (addrsize bytes) ("offset"))))
++
++("dln" 0x38
++ (("number of lines") (2 bytes) ("nln"))
++ (repeat "ptr->nln"
++	 (("source file number") (2 bytes) ("sfn"))
++	 (("source line number") (2 bytes) ("sln"))
++	 (("section number") (2 bytes) ("section"))
++	 (("from address") (addrsize bytes) ("from_address"))
++	 (("to address") (addrsize bytes) ("to_address"))
++	 (("call count") (2 bytes) ("cc"))
++	 )
++ (("neg") (2 bytes) ("neg")))
++
++("dpp" 0x46
++ (("start/end") (1 bit) ("end"))
++ (("spare") (7 bits) ("spare"))
++ (cond "!ptr->end"
++       (("params") (1 byte) ("params"))
++       (("neg number") (2 bytes) ("neg"))))
++
++("den" 0x4a
++ (("start/end") (1 bit) ("end"))
++ (("spare") (7 bits) ("spare"))
++ (cond "!ptr->end"
++       (("neg number") (2 bytes) ("neg"))))
++
++("dfp" 0x48
++ (("start/end flag") (1 bit) ("end"))
++ (("spare") (7 bits) ("spare"))
++ (cond "!ptr->end"
++       (("number of parameters") (1 byte) ("nparams"))
++       (("neg number") (2 bytes) ("neg"))))
++
++("dds" 0x4c
++ (("start/end") (1 bit) ("end"))
++ (("spare") (7 bits) ("spare"))
++ (cond "!ptr->end"
++       (("neg number") (2 bytes) ("neg"))))
++
++("dpt" 0x50
++ (("neg number") (2 bytes) ("neg"))
++ (("dunno") (1 byte) ("dunno")))
++
++("dse" 0x54
++ (("neg number") (2 bytes) ("neg"))
++ (("dunno") (1 byte) ("dunno")))
++
++("dot" 0x56
++ (("unknown") (1 byte) ("unknown")))
++; FIXME: unknown field should be repeated symbol number?
++
++
++("dss" 0x42
++ (("type") (1 byte) ("type"))
++ (("external/internal") (1 bit) ("internal"))
++ (("spare") (7 bits) ("spare"))
++ (cond "!ptr->internal"
++       (  ("package name") (chars variable byte) ("package")))
++ (cond "ptr->internal"
++       (("symbol id") (2 bytes) ("id")))
++ (("record type") (2 bytes) ("record"))
++ (("rules") (chars variable byte) ("rules"))
++ (("number of symbols") (2 bytes) ("nsymbols"))
++ (("unknown" ) (2 bytes) ("fixme")))
++
++("pss" 0x40
++ (("negotiation number") (2 bytes) ("efn"))
++ (("number of source files") (2 bytes) ("ns"))
++ (repeat "ptr->ns"
++	 (("directory reference bit") (1 bit) ("drb"))
++	 (("spare") (7 bits) ("spare"))
++	 (("completed file name") (chars variable byte) ("fname"))
++	 (cond "ptr->drb[n]"
++	       (("directory apperance number") (2 bytes) ("dan"))))
++
++ (("number of directories") (2 bytes) ("ndir"))
++ (repeat "ptr->ndir"
++	 (("directory name") (chars variable bytes) ("dname"))))
++
++
++; FIXME: the tr block has no contents. sysinfo, etc. aren't prepared
++; to deal with that.
++; ("tr" 0x7f)
++
++
++("dus" 0x40
++ (("negotiation number") (2 bytes) ("efn"))
++ (("number of source files") (2 bytes) ("ns"))
++ (repeat "ptr->ns"
++	 (("directory reference bit") (1 bit) ("drb"))
++	 (("spare") (7 bits) ("spare"))
++	 (("completed file name") (chars variable byte) ("fname"))
++	 (cond "ptr->drb[n]"
++	       (("directory apperance number") (2 bytes) ("dan"))))
++ (("number of directories") (2 bytes) ("ndir"))
++ (repeat "ptr->ndir"
++	 (("directory name") (chars variable bytes) ("dname"))))
++
++
++("dps" 0x32
++ (("start/end flag") (1 bit) ("end"))
++ (("block type") (7 bits) ("type")
++  (("BLOCK_TYPE_COMPUNIT" "0")
++   ("BLOCK_TYPE_PROCEDURE" "2")
++   ("BLOCK_TYPE_FUNCTION" "3")
++   ("BLOCK_TYPE_BLOCK" "4")
++   ("BLOCK_TYPE_BASIC" "9")))
++ (cond "!ptr->end"
++       (("optimization") (1 byte) ("opt"))
++       (("section number") (2 bytes) ("san"))
++       (("address") (addrsize bytes) ("address"))
++       (("block size") (addrsize bytes) ("block_size"))
++       (("nesting") (1 byte) ("nesting"))
++       (cond "ptr->type == BLOCK_TYPE_PROCEDURE
++	    || ptr->type == BLOCK_TYPE_FUNCTION"
++	     (("return address") (1 bit) ("retaddr"))
++	     (("interrupt function flag") (1 bit) ("intrflag"))
++	     (("stack update flag") (1 bit) ("stackflag"))
++	     (("intra page JMP") (1 bit) ("intrpagejmp"))
++	     (("spare") (4 bits) ("spare")))
++       (("neg number") (2 bytes) ("neg"))))
++
+-- 
+2.33.0
+

+ 5703 - 0
recipes-devtools/binutils/binutils/0005-support-Dubhe-V-extension.patch

@@ -0,0 +1,5703 @@
+From 2824e8fad46464ac663d078f95ebcb4e69184c6f Mon Sep 17 00:00:00 2001
+From: "eric.tang" <eric.tang@starfivetech.com>
+Date: Fri, 4 Jun 2021 14:26:05 +0800
+Subject: [PATCH 05/28] support Dubhe V extension
+
+Signed-off-by: eric.tang <eric.tang@starfivetech.com>
+---
+ gas/testsuite/gas/riscv/insn.d                |   47 +-
+ gas/testsuite/gas/riscv/insn.s                |   64 +
+ gas/testsuite/gas/riscv/v-zero-imm.d          |   17 +
+ gas/testsuite/gas/riscv/v-zero-imm.s          |    8 +
+ .../riscv/vector-insns-fail-arith-floatp.d    |    3 +
+ .../riscv/vector-insns-fail-arith-floatp.l    |   39 +
+ .../riscv/vector-insns-fail-arith-floatp.s    |  123 ++
+ .../gas/riscv/vector-insns-fail-arith-int.d   |    3 +
+ .../gas/riscv/vector-insns-fail-arith-int.l   |   62 +
+ .../gas/riscv/vector-insns-fail-arith-int.s   |  187 ++
+ .../gas/riscv/vector-insns-fail-load-store.d  |    3 +
+ .../gas/riscv/vector-insns-fail-load-store.l  |   25 +
+ .../gas/riscv/vector-insns-fail-load-store.s  |   43 +
+ .../gas/riscv/vector-insns-fail-permutation.d |    3 +
+ .../gas/riscv/vector-insns-fail-permutation.l |   19 +
+ .../gas/riscv/vector-insns-fail-permutation.s |   37 +
+ .../gas/riscv/vector-insns-fail-unsupport.d   |    3 +
+ .../gas/riscv/vector-insns-fail-unsupport.l   | 1469 ++++++++++++++
+ .../gas/riscv/vector-insns-fail-unsupport.s   | 1679 +++++++++++++++++
+ .../gas/riscv/vector-insns-vmsgtvx.d          |   29 +
+ .../gas/riscv/vector-insns-vmsgtvx.s          |    9 +
+ gas/testsuite/gas/riscv/vector-insns.d        |  476 +++++
+ gas/testsuite/gas/riscv/vector-insns.s        |  521 +++++
+ opcodes/riscv-opc.c                           |  535 +-----
+ 24 files changed, 4869 insertions(+), 535 deletions(-)
+ create mode 100644 gas/testsuite/gas/riscv/v-zero-imm.d
+ create mode 100644 gas/testsuite/gas/riscv/v-zero-imm.s
+ create mode 100644 gas/testsuite/gas/riscv/vector-insns-fail-arith-floatp.d
+ create mode 100644 gas/testsuite/gas/riscv/vector-insns-fail-arith-floatp.l
+ create mode 100644 gas/testsuite/gas/riscv/vector-insns-fail-arith-floatp.s
+ create mode 100644 gas/testsuite/gas/riscv/vector-insns-fail-arith-int.d
+ create mode 100644 gas/testsuite/gas/riscv/vector-insns-fail-arith-int.l
+ create mode 100644 gas/testsuite/gas/riscv/vector-insns-fail-arith-int.s
+ create mode 100644 gas/testsuite/gas/riscv/vector-insns-fail-load-store.d
+ create mode 100644 gas/testsuite/gas/riscv/vector-insns-fail-load-store.l
+ create mode 100644 gas/testsuite/gas/riscv/vector-insns-fail-load-store.s
+ create mode 100644 gas/testsuite/gas/riscv/vector-insns-fail-permutation.d
+ create mode 100644 gas/testsuite/gas/riscv/vector-insns-fail-permutation.l
+ create mode 100644 gas/testsuite/gas/riscv/vector-insns-fail-permutation.s
+ create mode 100644 gas/testsuite/gas/riscv/vector-insns-fail-unsupport.d
+ create mode 100644 gas/testsuite/gas/riscv/vector-insns-fail-unsupport.l
+ create mode 100644 gas/testsuite/gas/riscv/vector-insns-fail-unsupport.s
+ create mode 100644 gas/testsuite/gas/riscv/vector-insns-vmsgtvx.d
+ create mode 100644 gas/testsuite/gas/riscv/vector-insns-vmsgtvx.s
+ create mode 100644 gas/testsuite/gas/riscv/vector-insns.d
+ create mode 100644 gas/testsuite/gas/riscv/vector-insns.s
+
+diff --git a/gas/testsuite/gas/riscv/insn.d b/gas/testsuite/gas/riscv/insn.d
+index 8f0badfce1..e7a17b11d5 100644
+--- a/gas/testsuite/gas/riscv/insn.d
++++ b/gas/testsuite/gas/riscv/insn.d
+@@ -1,4 +1,4 @@
+-#as: -march=rv32ifc
++#as: -march=rv32ifcv0p10
+ #objdump: -dr
+ 
+ .*:[ 	]+file format .*
+@@ -63,3 +63,48 @@ Disassembly of section .text:
+ [^:]+:[ 	]+00c58533[ 	]+add[ 	]+a0,a1,a2
+ [^:]+:[ 	]+00c58533[ 	]+add[ 	]+a0,a1,a2
+ [^:]+:[ 	]+00c58533[ 	]+add[ 	]+a0,a1,a2
++[^:]+:[ 	]+08d67587[ 	]+vlse64.v[ 	]+v11,\(a2\),a3,v0.t
++[^:]+:[ 	]+08d67587[ 	]+vlse64.v[ 	]+v11,\(a2\),a3,v0.t
++[^:]+:[ 	]+08d67587[ 	]+vlse64.v[ 	]+v11,\(a2\),a3,v0.t
++[^:]+:[ 	]+08d67587[ 	]+vlse64.v[ 	]+v11,\(a2\),a3,v0.t
++[^:]+:[ 	]+08d67587[ 	]+vlse64.v[ 	]+v11,\(a2\),a3,v0.t
++[^:]+:[ 	]+0ad67587[ 	]+vlse64.v[ 	]+v11,\(a2\),a3
++[^:]+:[ 	]+0ad67587[ 	]+vlse64.v[ 	]+v11,\(a2\),a3
++[^:]+:[ 	]+0ad67587[ 	]+vlse64.v[ 	]+v11,\(a2\),a3
++[^:]+:[ 	]+0ad67587[ 	]+vlse64.v[ 	]+v11,\(a2\),a3
++[^:]+:[ 	]+0ad67587[ 	]+vlse64.v[ 	]+v11,\(a2\),a3
++[^:]+:[ 	]+08d675a7[ 	]+vsse64.v[ 	]+v11,\(a2\),a3,v0.t
++[^:]+:[ 	]+08d675a7[ 	]+vsse64.v[ 	]+v11,\(a2\),a3,v0.t
++[^:]+:[ 	]+08d675a7[ 	]+vsse64.v[ 	]+v11,\(a2\),a3,v0.t
++[^:]+:[ 	]+08d675a7[ 	]+vsse64.v[ 	]+v11,\(a2\),a3,v0.t
++[^:]+:[ 	]+08d675a7[ 	]+vsse64.v[ 	]+v11,\(a2\),a3,v0.t
++[^:]+:[ 	]+0ad675a7[ 	]+vsse64.v[ 	]+v11,\(a2\),a3
++[^:]+:[ 	]+0ad675a7[ 	]+vsse64.v[ 	]+v11,\(a2\),a3
++[^:]+:[ 	]+0ad675a7[ 	]+vsse64.v[ 	]+v11,\(a2\),a3
++[^:]+:[ 	]+0ad675a7[ 	]+vsse64.v[ 	]+v11,\(a2\),a3
++[^:]+:[ 	]+0ad675a7[ 	]+vsse64.v[ 	]+v11,\(a2\),a3
++[^:]+:[ 	]+00067587[ 	]+vle64.v[ 	]+v11,\(a2\),v0.t
++[^:]+:[ 	]+000675a7[ 	]+vse64.v[ 	]+v11,\(a2\),v0.t
++[^:]+:[ 	]+00d605d7[ 	]+vadd.vv[ 	]+v11,v13,v12,v0.t
++[^:]+:[ 	]+00d605d7[ 	]+vadd.vv[ 	]+v11,v13,v12,v0.t
++[^:]+:[ 	]+00d605d7[ 	]+vadd.vv[ 	]+v11,v13,v12,v0.t
++[^:]+:[ 	]+00d605d7[ 	]+vadd.vv[ 	]+v11,v13,v12,v0.t
++[^:]+:[ 	]+00d605d7[ 	]+vadd.vv[ 	]+v11,v13,v12,v0.t
++[^:]+:[ 	]+00d605d7[ 	]+vadd.vv[ 	]+v11,v13,v12,v0.t
++[^:]+:[ 	]+00d605d7[ 	]+vadd.vv[ 	]+v11,v13,v12,v0.t
++[^:]+:[ 	]+00d615d7[ 	]+vfadd.vv[ 	]+v11,v13,v12,v0.t
++[^:]+:[ 	]+00d615d7[ 	]+vfadd.vv[ 	]+v11,v13,v12,v0.t
++[^:]+:[ 	]+00d645d7[ 	]+vadd.vx[ 	]+v11,v13,a2,v0.t
++[^:]+:[ 	]+00d645d7[ 	]+vadd.vx[ 	]+v11,v13,a2,v0.t
++[^:]+:[ 	]+00d655d7[ 	]+vfadd.vf[ 	]+v11,v13,fa2,v0.t
++[^:]+:[ 	]+00d655d7[ 	]+vfadd.vf[ 	]+v11,v13,fa2,v0.t
++[^:]+:[ 	]+38d665d7[ 	]+vslide1up.vx[ 	]+v11,v13,a2,v0.t
++[^:]+:[ 	]+3cd665d7[ 	]+vslide1down.vx[ 	]+v11,v13,a2,v0.t
++[^:]+:[ 	]+00d675d7[ 	]+vsetvli[ 	]+a1,a2,e16,mf8,tu,mu
++[^:]+:[ 	]+00d675d7[ 	]+vsetvli[ 	]+a1,a2,e16,mf8,tu,mu
++[^:]+:[ 	]+00d035d7[ 	]+vadd.vi[ 	]+v11,v13,0,v0.t
++[^:]+:[ 	]+00d0b5d7[ 	]+vadd.vi[ 	]+v11,v13,1,v0.t
++[^:]+:[ 	]+00d7b5d7[ 	]+vadd.vi[ 	]+v11,v13,15,v0.t
++[^:]+:[ 	]+00d835d7[ 	]+vadd.vi[ 	]+v11,v13,-16,v0.t
++[^:]+:[ 	]+00df35d7[ 	]+vadd.vi[ 	]+v11,v13,-2,v0.t
++[^:]+:[ 	]+00dfb5d7[ 	]+vadd.vi[ 	]+v11,v13,-1,v0.t
+diff --git a/gas/testsuite/gas/riscv/insn.s b/gas/testsuite/gas/riscv/insn.s
+index 6c08f49d43..5f2f75e88b 100644
+--- a/gas/testsuite/gas/riscv/insn.s
++++ b/gas/testsuite/gas/riscv/insn.s
+@@ -47,3 +47,67 @@ target:
+ 	.insn r  0x33,  0,  0, fa0, a1, fa2
+ 	.insn r  0x33,  0,  0, a0, fa1, fa2
+ 	.insn r  0x33,  0,  0, fa0, fa1, fa2
++
++# vamo
++# F3: width[14:12]
++# F7: amoop[31:27] + wd[26] + vm[25]
++
++# vmem
++# F3: width[14:12]
++# F7: nf[31:29] + mop[28:26] + vm[25]
++
++	.insn r LOAD_FP, 0x7, 0x4, v11, a2, a3
++	.insn r LOAD_FP, 0x7, 0x4, v11, a2, a3
++	.insn r LOAD_FP, 0x7, 0x4, v11, fa2, a3
++	.insn r LOAD_FP, 0x7, 0x4, v11, a2, fa3
++	.insn r LOAD_FP, 0x7, 0x4, v11, fa2, fa3
++	.insn r 0x7, 0x7, 0x5, a1, v12, a3
++	.insn r 0x7, 0x7, 0x5, fa1, v12, a3
++	.insn r 0x7, 0x7, 0x5, a1, v12, fa3
++	.insn r 0x7, 0x7, 0x5, fa1, v12, fa3
++	.insn r 0x7, 0x7, 0x5, a1, a2, v13
++	.insn r STORE_FP, 0x7, 0x4, fa1, a2, v13
++	.insn r STORE_FP, 0x7, 0x4, a1, fa2, v13
++	.insn r STORE_FP, 0x7, 0x4, fa1, fa2, v13
++	.insn r STORE_FP, 0x7, 0x4, a1, v12, v13
++	.insn r STORE_FP, 0x7, 0x4, fa1, v12, v13
++	.insn r 0x27, 0x7, 0x5, v11, a2, v13
++	.insn r 0x27, 0x7, 0x5, v11, fa2, v13
++	.insn r 0x27, 0x7, 0x5, v11, v12, a3
++	.insn r 0x27, 0x7, 0x5, v11, v12, fa3
++	.insn r 0x27, 0x7, 0x5, v11, v12, v13
++	# unit-stride
++	.insn r LOAD_FP, 0x7, 0x0, v11, a2, x0
++	#.insn r LOAD_FP, 0x7, 0x1, v11, a2, x16
++	.insn r STORE_FP, 0x7, 0x0, v11, a2, x0
++
++# valu and vcfg
++# F3: funct3[14:12]
++# F7: F6[31:26] + vm[25]
++
++	.insn r 0x57, 0x0, 0x0, v11, a2, a3
++	.insn r 0x57, 0x0, 0x0, v11, fa2, a3
++	.insn r 0x57, 0x0, 0x0, v11, a2, fa3
++	.insn r 0x57, 0x0, 0x0, v11, fa2, fa3
++	.insn r 0x57, 0x0, 0x0, a1, v12, a3
++	.insn r 0x57, 0x0, 0x0, fa1, v12, a3
++	.insn r 0x57, 0x0, 0x0, a1, v12, fa3
++	.insn r 0x57, 0x1, 0x0, fa1, v12, fa3
++	.insn r 0x57, 0x1, 0x0, a1, a2, v13
++	#.insn r 0x57, 0x2, 0x0, fa1, a2, v13
++	#.insn r 0x57, 0x2, 0x0, a1, fa2, v13
++	.insn r 0x57, 0x4, 0x0, fa1, fa2, v13
++	.insn r 0x57, 0x4, 0x0, a1, v12, v13
++	.insn r 0x57, 0x5, 0x0, fa1, v12, v13
++	.insn r 0x57, 0x5, 0x0, v11, a2, v13
++	.insn r 0x57, 0x6, 0x1c, v11, fa2, v13
++	.insn r 0x57, 0x6, 0x1e, v11, v12, a3
++	.insn r 0x57, 0x7, 0x0, v11, v12, fa3
++	.insn r 0x57, 0x7, 0x0, v11, v12, v13
++	# OPIVI
++	.insn r 0x57, 0x3, 0x0, v11, x0, a3
++	.insn r 0x57, 0x3, 0x0, v11, x1, a3
++	.insn r 0x57, 0x3, 0x0, v11, x15, a3
++	.insn r 0x57, 0x3, 0x0, v11, x16, a3
++	.insn r 0x57, 0x3, 0x0, v11, x30, a3
++	.insn r 0x57, 0x3, 0x0, v11, x31, a3
+diff --git a/gas/testsuite/gas/riscv/v-zero-imm.d b/gas/testsuite/gas/riscv/v-zero-imm.d
+new file mode 100644
+index 0000000000..b95c068a17
+--- /dev/null
++++ b/gas/testsuite/gas/riscv/v-zero-imm.d
+@@ -0,0 +1,17 @@
++#as: -march=rv32ifv0p10
++#objdump: -dr
++
++.*:[ 	]+file format .*
++
++
++Disassembly of section .text:
++
++0+000 <.text>:
++[ 	]+[0-9a-f]+:[ 	]+768fb257[ 	]+vmsle.vi[ 	]+v4,v8,-1
++[ 	]+[0-9a-f]+:[ 	]+748fb257[ 	]+vmsle.vi[ 	]+v4,v8,-1,v0.t
++[ 	]+[0-9a-f]+:[ 	]+66840257[ 	]+vmsne.vv[ 	]+v4,v8,v8
++[ 	]+[0-9a-f]+:[ 	]+64840257[ 	]+vmsne.vv[ 	]+v4,v8,v8,v0.t
++[ 	]+[0-9a-f]+:[ 	]+7e8fb257[ 	]+vmsgt.vi[ 	]+v4,v8,-1
++[ 	]+[0-9a-f]+:[ 	]+7c8fb257[ 	]+vmsgt.vi[ 	]+v4,v8,-1,v0.t
++[ 	]+[0-9a-f]+:[ 	]+62840257[ 	]+vmseq.vv[ 	]+v4,v8,v8
++[ 	]+[0-9a-f]+:[ 	]+60840257[ 	]+vmseq.vv[ 	]+v4,v8,v8,v0.t
+diff --git a/gas/testsuite/gas/riscv/v-zero-imm.s b/gas/testsuite/gas/riscv/v-zero-imm.s
+new file mode 100644
+index 0000000000..98b7063880
+--- /dev/null
++++ b/gas/testsuite/gas/riscv/v-zero-imm.s
+@@ -0,0 +1,8 @@
++	vmslt.vi v4, v8, 0
++	vmslt.vi v4, v8, 0, v0.t
++	vmsltu.vi v4, v8, 0
++	vmsltu.vi v4, v8, 0, v0.t
++	vmsge.vi v4, v8, 0
++	vmsge.vi v4, v8, 0, v0.t
++	vmsgeu.vi v4, v8, 0
++	vmsgeu.vi v4, v8, 0, v0.t
+diff --git a/gas/testsuite/gas/riscv/vector-insns-fail-arith-floatp.d b/gas/testsuite/gas/riscv/vector-insns-fail-arith-floatp.d
+new file mode 100644
+index 0000000000..d192761c06
+--- /dev/null
++++ b/gas/testsuite/gas/riscv/vector-insns-fail-arith-floatp.d
+@@ -0,0 +1,3 @@
++#as: -march=rv32ifv0p10
++#source: vector-insns-fail-arith-floatp.s
++#error_output: vector-insns-fail-arith-floatp.l
+diff --git a/gas/testsuite/gas/riscv/vector-insns-fail-arith-floatp.l b/gas/testsuite/gas/riscv/vector-insns-fail-arith-floatp.l
+new file mode 100644
+index 0000000000..b211327275
+--- /dev/null
++++ b/gas/testsuite/gas/riscv/vector-insns-fail-arith-floatp.l
+@@ -0,0 +1,39 @@
++.*: Assembler messages:
++.*Error: illegal operands `vfadd.vv v0,v4,v8,v0.t'
++.*Error: illegal operands `vfadd.vf v0,v4,fa1,v0.t'
++.*Error: illegal operands `vfsub.vv v0,v4,v8,v0.t'
++.*Error: illegal operands `vfsub.vf v0,v4,fa1,v0.t'
++.*Error: illegal operands `vfrsub.vf v0,v4,fa1,v0.t'
++.*Error: illegal operands `vfmul.vv v0,v4,v8,v0.t'
++.*Error: illegal operands `vfmul.vf v0,v4,fa1,v0.t'
++.*Error: illegal operands `vfdiv.vv v0,v4,v8,v0.t'
++.*Error: illegal operands `vfdiv.vf v0,v4,fa1,v0.t'
++.*Error: illegal operands `vfrdiv.vf v0,v4,fa1,v0.t'
++.*Error: illegal operands `vfmacc.vv v0,v4,v8,v0.t'
++.*Error: illegal operands `vfmacc.vf v0,fa1,v4,v0.t'
++.*Error: illegal operands `vfnmacc.vv v0,v4,v8,v0.t'
++.*Error: illegal operands `vfnmacc.vf v0,fa1,v4,v0.t'
++.*Error: illegal operands `vfmsac.vv v0,v4,v8,v0.t'
++.*Error: illegal operands `vfmsac.vf v0,fa1,v4,v0.t'
++.*Error: illegal operands `vfnmsac.vv v0,v4,v8,v0.t'
++.*Error: illegal operands `vfnmsac.vf v0,fa1,v4,v0.t'
++.*Error: illegal operands `vfmadd.vv v0,v4,v8,v0.t'
++.*Error: illegal operands `vfmadd.vf v0,fa1,v4,v0.t'
++.*Error: illegal operands `vfnmadd.vv v0,v4,v8,v0.t'
++.*Error: illegal operands `vfnmadd.vf v0,fa1,v4,v0.t'
++.*Error: illegal operands `vfmsub.vv v0,v4,v8,v0.t'
++.*Error: illegal operands `vfmsub.vf v0,fa1,v4,v0.t'
++.*Error: illegal operands `vfnmsub.vv v0,v4,v8,v0.t'
++.*Error: illegal operands `vfnmsub.vf v0,fa1,v4,v0.t'
++.*Error: illegal operands `vfmin.vv v0,v4,v8,v0.t'
++.*Error: illegal operands `vfmin.vf v0,v4,fa1,v0.t'
++.*Error: illegal operands `vfmax.vv v0,v4,v8,v0.t'
++.*Error: illegal operands `vfmax.vf v0,v4,fa1,v0.t'
++.*Error: illegal operands `vfneg.v v0,v4,v0.t'
++.*Error: illegal operands `vfabs.v v0,v4,v0.t'
++.*Error: illegal operands `vfsgnj.vv v0,v4,v8,v0.t'
++.*Error: illegal operands `vfsgnj.vf v0,v4,fa1,v0.t'
++.*Error: illegal operands `vfsgnjn.vv v0,v4,v8,v0.t'
++.*Error: illegal operands `vfsgnjn.vf v0,v4,fa1,v0.t'
++.*Error: illegal operands `vfsgnjx.vv v0,v4,v8,v0.t'
++.*Error: illegal operands `vfsgnjx.vf v0,v4,fa1,v0.t'
+diff --git a/gas/testsuite/gas/riscv/vector-insns-fail-arith-floatp.s b/gas/testsuite/gas/riscv/vector-insns-fail-arith-floatp.s
+new file mode 100644
+index 0000000000..28e1d35db7
+--- /dev/null
++++ b/gas/testsuite/gas/riscv/vector-insns-fail-arith-floatp.s
+@@ -0,0 +1,123 @@
++# Vector Single-Width Floating-Point Add/Subtract Instructions
++
++	vfadd.vv v4, v4, v8		# OK
++	vfadd.vv v8, v4, v8		# OK
++	vfadd.vv v0, v4, v8, v0.t	# vd overlap vm
++	vfadd.vf v4, v4, fa1		# OK
++	vfadd.vf v0, v4, fa1, v0.t	# vd overlap vm
++
++	vfsub.vv v4, v4, v8
++	vfsub.vv v8, v4, v8
++	vfsub.vv v0, v4, v8, v0.t
++	vfsub.vf v4, v4, fa1
++	vfsub.vf v0, v4, fa1, v0.t
++
++	vfrsub.vf v4, v4, fa1		# OK
++	vfrsub.vf v0, v4, fa1, v0.t	# vd overlap vm
++
++# Vector Single-Width Floating-Point Multiply/Divide Instructions
++
++	vfmul.vv v4, v4, v8		# OK
++	vfmul.vv v8, v4, v8		# OK
++	vfmul.vv v0, v4, v8, v0.t	# vd overlap vm
++	vfmul.vf v4, v4, fa1		# OK
++	vfmul.vf v0, v4, fa1, v0.t	# vd overlap vm
++
++	vfdiv.vv v4, v4, v8
++	vfdiv.vv v8, v4, v8
++	vfdiv.vv v0, v4, v8, v0.t
++	vfdiv.vf v4, v4, fa1
++	vfdiv.vf v0, v4, fa1, v0.t
++
++	vfrdiv.vf v4, v4, fa1		# OK
++	vfrdiv.vf v0, v4, fa1, v0.t	# vd overlap vm
++
++# Vector Single-Width Floating-Point Fused Multiply-Add Instructions
++
++	vfmacc.vv v4, v4, v8		# OK
++	vfmacc.vv v8, v4, v8		# OK
++	vfmacc.vv v0, v4, v8, v0.t	# vd overlap vm
++	vfmacc.vf v4, fa1, v4		# OK
++	vfmacc.vf v0, fa1, v4, v0.t	# vd overlap vm
++
++	vfnmacc.vv v4, v4, v8
++	vfnmacc.vv v8, v4, v8
++	vfnmacc.vv v0, v4, v8, v0.t
++	vfnmacc.vf v4, fa1, v4
++	vfnmacc.vf v0, fa1, v4, v0.t
++
++	vfmsac.vv v4, v4, v8
++	vfmsac.vv v8, v4, v8
++	vfmsac.vv v0, v4, v8, v0.t
++	vfmsac.vf v4, fa1, v4
++	vfmsac.vf v0, fa1, v4, v0.t
++
++	vfnmsac.vv v4, v4, v8
++	vfnmsac.vv v8, v4, v8
++	vfnmsac.vv v0, v4, v8, v0.t
++	vfnmsac.vf v4, fa1, v4
++	vfnmsac.vf v0, fa1, v4, v0.t
++
++	vfmadd.vv v4, v4, v8
++	vfmadd.vv v8, v4, v8
++	vfmadd.vv v0, v4, v8, v0.t
++	vfmadd.vf v4, fa1, v4
++	vfmadd.vf v0, fa1, v4, v0.t
++
++	vfnmadd.vv v4, v4, v8
++	vfnmadd.vv v8, v4, v8
++	vfnmadd.vv v0, v4, v8, v0.t
++	vfnmadd.vf v4, fa1, v4
++	vfnmadd.vf v0, fa1, v4, v0.t
++
++	vfmsub.vv v4, v4, v8
++	vfmsub.vv v8, v4, v8
++	vfmsub.vv v0, v4, v8, v0.t
++	vfmsub.vf v4, fa1, v4
++	vfmsub.vf v0, fa1, v4, v0.t
++
++	vfnmsub.vv v4, v4, v8
++	vfnmsub.vv v8, v4, v8
++	vfnmsub.vv v0, v4, v8, v0.t
++	vfnmsub.vf v4, fa1, v4
++	vfnmsub.vf v0, fa1, v4, v0.t
++
++# Vector Floating-Point MIN/MAX Instructions
++
++	vfmin.vv v4, v4, v8		# OK
++	vfmin.vv v8, v4, v8		# OK
++	vfmin.vv v0, v4, v8, v0.t	# vd overlap vm
++	vfmin.vf v4, v4, fa1		# OK
++	vfmin.vf v0, v4, fa1, v0.t	# vd overlap vm
++
++	vfmax.vv v4, v4, v8
++	vfmax.vv v8, v4, v8
++	vfmax.vv v0, v4, v8, v0.t
++	vfmax.vf v4, v4, fa1
++	vfmax.vf v0, v4, fa1, v0.t
++
++# Vector Floating-Point Sign-Injection Instructions
++
++	vfneg.v v4, v4			# OK
++	vfneg.v v0, v4, v0.t		# vd overlap vm
++	vfabs.v v4, v4			# OK
++	vfabs.v v0, v4, v0.t		# vd overlap vm
++
++	vfsgnj.vv v4, v4, v8		# OK
++	vfsgnj.vv v8, v4, v8		# OK
++	vfsgnj.vv v0, v4, v8, v0.t	# vd overlap vm
++	vfsgnj.vf v4, v4, fa1		# OK
++	vfsgnj.vf v0, v4, fa1, v0.t	# vd overlap vm
++
++	vfsgnjn.vv v4, v4, v8
++	vfsgnjn.vv v8, v4, v8
++	vfsgnjn.vv v0, v4, v8, v0.t
++	vfsgnjn.vf v4, v4, fa1
++	vfsgnjn.vf v0, v4, fa1, v0.t
++
++	vfsgnjx.vv v4, v4, v8
++	vfsgnjx.vv v8, v4, v8
++	vfsgnjx.vv v0, v4, v8, v0.t
++	vfsgnjx.vf v4, v4, fa1
++	vfsgnjx.vf v0, v4, fa1, v0.t
++
+diff --git a/gas/testsuite/gas/riscv/vector-insns-fail-arith-int.d b/gas/testsuite/gas/riscv/vector-insns-fail-arith-int.d
+new file mode 100644
+index 0000000000..746f8d1964
+--- /dev/null
++++ b/gas/testsuite/gas/riscv/vector-insns-fail-arith-int.d
+@@ -0,0 +1,3 @@
++#as: -march=rv32iv0p10
++#source: vector-insns-fail-arith-int.s
++#error_output: vector-insns-fail-arith-int.l
+diff --git a/gas/testsuite/gas/riscv/vector-insns-fail-arith-int.l b/gas/testsuite/gas/riscv/vector-insns-fail-arith-int.l
+new file mode 100644
+index 0000000000..40f4f7717e
+--- /dev/null
++++ b/gas/testsuite/gas/riscv/vector-insns-fail-arith-int.l
+@@ -0,0 +1,62 @@
++.*: Assembler messages:
++.*Error: illegal operands `vneg.v v0,v4,v0.t'
++.*Error: illegal operands `vadd.vv v0,v4,v8,v0.t'
++.*Error: illegal operands `vadd.vx v0,v4,a1,v0.t'
++.*Error: illegal operands `vadd.vi v0,v4,15,v0.t'
++.*Error: illegal operands `vsub.vv v0,v4,v8,v0.t'
++.*Error: illegal operands `vsub.vx v0,v4,a1,v0.t'
++.*Error: illegal operands `vrsub.vx v0,v4,a1,v0.t'
++.*Error: illegal operands `vrsub.vi v0,v4,15,v0.t'
++.*Error: illegal operands `vzext.vf2 v0,v4,v0.t'
++.*Error: illegal operands `vsext.vf2 v0,v4,v0.t'
++.*Error: illegal operands `vzext.vf4 v0,v4,v0.t'
++.*Error: illegal operands `vsext.vf4 v0,v4,v0.t'
++.*Error: illegal operands `vzext.vf8 v0,v4,v0.t'
++.*Error: illegal operands `vsext.vf8 v0,v4,v0.t'
++.*Error: illegal operands `vadc.vvm v0,v4,v8,v0'
++.*Error: illegal operands `vadc.vxm v0,v4,a1,v0'
++.*Error: illegal operands `vadc.vim v0,v4,15,v0'
++.*Error: illegal operands `vsbc.vvm v0,v4,v8,v0'
++.*Error: illegal operands `vsbc.vxm v0,v4,a1,v0'
++.*Error: illegal operands `vnot.v v0,v4,v0.t'
++.*Error: illegal operands `vand.vv v0,v4,v8,v0.t'
++.*Error: illegal operands `vand.vx v0,v4,a1,v0.t'
++.*Error: illegal operands `vand.vi v0,v4,15,v0.t'
++.*Error: illegal operands `vor.vv v0,v4,v8,v0.t'
++.*Error: illegal operands `vor.vx v0,v4,a1,v0.t'
++.*Error: illegal operands `vor.vi v0,v4,15,v0.t'
++.*Error: illegal operands `vxor.vv v0,v4,v8,v0.t'
++.*Error: illegal operands `vxor.vx v0,v4,a1,v0.t'
++.*Error: illegal operands `vxor.vi v0,v4,15,v0.t'
++.*Error: illegal operands `vminu.vv v0,v4,v8,v0.t'
++.*Error: illegal operands `vminu.vx v0,v4,a1,v0.t'
++.*Error: illegal operands `vmin.vv v0,v4,v8,v0.t'
++.*Error: illegal operands `vmin.vx v0,v4,a1,v0.t'
++.*Error: illegal operands `vmaxu.vv v0,v4,v8,v0.t'
++.*Error: illegal operands `vmaxu.vx v0,v4,a1,v0.t'
++.*Error: illegal operands `vmax.vv v0,v4,v8,v0.t'
++.*Error: illegal operands `vmax.vx v0,v4,a1,v0.t'
++.*Error: illegal operands `vmul.vv v0,v4,v8,v0.t'
++.*Error: illegal operands `vmul.vx v0,v4,a1,v0.t'
++.*Error: illegal operands `vmulh.vv v0,v4,v8,v0.t'
++.*Error: illegal operands `vmulh.vx v0,v4,a1,v0.t'
++.*Error: illegal operands `vmulhu.vv v0,v4,v8,v0.t'
++.*Error: illegal operands `vmulhu.vx v0,v4,a1,v0.t'
++.*Error: illegal operands `vmulhsu.vv v0,v4,v8,v0.t'
++.*Error: illegal operands `vmulhsu.vx v0,v4,a1,v0.t'
++.*Error: illegal operands `vdivu.vv v0,v4,v8,v0.t'
++.*Error: illegal operands `vdivu.vx v0,v4,a1,v0.t'
++.*Error: illegal operands `vdiv.vv v0,v4,v8,v0.t'
++.*Error: illegal operands `vdiv.vx v0,v4,a1,v0.t'
++.*Error: illegal operands `vremu.vv v0,v4,v8,v0.t'
++.*Error: illegal operands `vremu.vx v0,v4,a1,v0.t'
++.*Error: illegal operands `vrem.vv v0,v4,v8,v0.t'
++.*Error: illegal operands `vrem.vx v0,v4,a1,v0.t'
++.*Error: illegal operands `vmacc.vv v0,v4,v8,v0.t'
++.*Error: illegal operands `vmacc.vx v0,a1,v4,v0.t'
++.*Error: illegal operands `vnmsac.vv v0,v4,v8,v0.t'
++.*Error: illegal operands `vnmsac.vx v0,a1,v4,v0.t'
++.*Error: illegal operands `vmadd.vv v0,v4,v8,v0.t'
++.*Error: illegal operands `vmadd.vx v0,a1,v4,v0.t'
++.*Error: illegal operands `vnmsub.vv v0,v4,v8,v0.t'
++.*Error: illegal operands `vnmsub.vx v0,a1,v4,v0.t'
+diff --git a/gas/testsuite/gas/riscv/vector-insns-fail-arith-int.s b/gas/testsuite/gas/riscv/vector-insns-fail-arith-int.s
+new file mode 100644
+index 0000000000..af0d1737ff
+--- /dev/null
++++ b/gas/testsuite/gas/riscv/vector-insns-fail-arith-int.s
+@@ -0,0 +1,187 @@
++# Vector Single-Width Integer Add and Subtract
++
++	vneg.v v4, v4			# OK
++	vneg.v v0, v4, v0.t		# vd overlap vm
++
++	vadd.vv v4, v4, v8		# OK
++	vadd.vv v8, v4, v8		# OK
++	vadd.vv v0, v4, v8, v0.t	# vd overlap vm
++	vadd.vx v4, v4, a1		# OK
++	vadd.vx v0, v4, a1, v0.t	# vd overlap vm
++	vadd.vi v4, v4, 15		# OK
++	vadd.vi v0, v4, 15, v0.t	# vd overlap vm
++
++	vsub.vv v4, v4, v8		# OK
++	vsub.vv v8, v4, v8		# OK
++	vsub.vv v0, v4, v8, v0.t	# vd overlap vm
++	vsub.vx v4, v4, a1		# OK
++	vsub.vx v0, v4, a1, v0.t	# vd overlap vm
++
++	vrsub.vx v4, v4, a1		# OK
++	vrsub.vx v0, v4, a1, v0.t	# vd overlap vm
++	vrsub.vi v4, v4, 15		# OK
++	vrsub.vi v0, v4, 15, v0.t	# vd overlap vm
++
++# Vector Integer Extension
++
++	vzext.vf2 v4, v4		# OK
++	vzext.vf2 v0, v4, v0.t		# vd overlap vm
++	vsext.vf2 v4, v4
++	vsext.vf2 v0, v4, v0.t
++	vzext.vf4 v4, v4
++	vzext.vf4 v0, v4, v0.t
++	vsext.vf4 v4, v4
++	vsext.vf4 v0, v4, v0.t
++	vzext.vf8 v4, v4
++	vzext.vf8 v0, v4, v0.t
++	vsext.vf8 v4, v4
++	vsext.vf8 v0, v4, v0.t
++
++# Vector Integer Add-with-Carry / Subtract-with-Borrow Instructions
++
++	vadc.vvm v4, v4, v8, v0		# OK
++	vadc.vvm v8, v4, v8, v0		# OK
++	vadc.vvm v0, v4, v8, v0		# vd overlap vm
++	vadc.vxm v4, v4, a1, v0		# OK
++	vadc.vxm v0, v4, a1, v0		# vd overlap vm
++	vadc.vim v4, v4, 15, v0		# OK
++	vadc.vim v0, v4, 15, v0		# vd overlap vm
++
++	vsbc.vvm v4, v4, v8, v0		# OK
++	vsbc.vvm v8, v4, v8, v0		# OK
++	vsbc.vvm v0, v4, v8, v0		# vd overlap vm
++	vsbc.vxm v4, v4, a1, v0		# OK
++	vsbc.vxm v0, v4, a1, v0		# vd overlap vm
++
++# Vector Bitwise Logical Instructions
++
++	vnot.v v4, v4			# OK
++	vnot.v v0, v4, v0.t		# vd overlap vm
++
++	vand.vv	v4, v4, v8		# OK
++	vand.vv v8, v4, v8		# OK
++	vand.vv v0, v4, v8, v0.t	# vd overlap vm
++	vand.vx v4, v4, a1		# OK
++	vand.vx v0, v4, a1, v0.t	# vd overlap vm
++	vand.vi v4, v4, 15		# OK
++	vand.vi v0, v4, 15, v0.t	# vd overlap vm
++
++	vor.vv	v4, v4, v8
++	vor.vv v8, v4, v8
++	vor.vv v0, v4, v8, v0.t
++	vor.vx v4, v4, a1
++	vor.vx v0, v4, a1, v0.t
++	vor.vi v4, v4, 15
++	vor.vi v0, v4, 15, v0.t
++
++	vxor.vv	v4, v4, v8
++	vxor.vv v8, v4, v8
++	vxor.vv v0, v4, v8, v0.t
++	vxor.vx v4, v4, a1
++	vxor.vx v0, v4, a1, v0.t
++	vxor.vi v4, v4, 15
++	vxor.vi v0, v4, 15, v0.t
++
++# Vector Integer Min/Max Instructions
++
++	vminu.vv v4, v4, v8		# OK
++	vminu.vv v8, v4, v8		# OK
++	vminu.vv v0, v4, v8, v0.t	# vd overlap vm
++	vminu.vx v4, v4, a1		# OK
++	vminu.vx v0, v4, a1, v0.t	# vd overlap vm
++
++	vmin.vv v4, v4, v8
++	vmin.vv v8, v4, v8
++	vmin.vv v0, v4, v8, v0.t
++	vmin.vx v4, v4, a1
++	vmin.vx v0, v4, a1, v0.t
++
++	vmaxu.vv v4, v4, v8
++	vmaxu.vv v8, v4, v8
++	vmaxu.vv v0, v4, v8, v0.t
++	vmaxu.vx v4, v4, a1
++	vmaxu.vx v0, v4, a1, v0.t
++
++	vmax.vv v4, v4, v8
++	vmax.vv v8, v4, v8
++	vmax.vv v0, v4, v8, v0.t
++	vmax.vx v4, v4, a1
++	vmax.vx v0, v4, a1, v0.t
++
++# Vector Single-Width Integer Multiply Instructions
++
++	vmul.vv v4, v4, v8		# OK
++	vmul.vv v8, v4, v8		# OK
++	vmul.vv v0, v4, v8, v0.t	# vd overlap vm
++	vmul.vx v4, v4, a1		# OK
++	vmul.vx v0, v4, a1, v0.t	# vd overlap vm
++
++	vmulh.vv v4, v4, v8
++	vmulh.vv v8, v4, v8
++	vmulh.vv v0, v4, v8, v0.t
++	vmulh.vx v4, v4, a1
++	vmulh.vx v0, v4, a1, v0.t
++
++	vmulhu.vv v4, v4, v8
++	vmulhu.vv v8, v4, v8
++	vmulhu.vv v0, v4, v8, v0.t
++	vmulhu.vx v4, v4, a1
++	vmulhu.vx v0, v4, a1, v0.t
++
++	vmulhsu.vv v4, v4, v8
++	vmulhsu.vv v8, v4, v8
++	vmulhsu.vv v0, v4, v8, v0.t
++	vmulhsu.vx v4, v4, a1
++	vmulhsu.vx v0, v4, a1, v0.t
++
++# Vector Integer Divide Instructions
++
++	vdivu.vv v4, v4, v8		# OK
++	vdivu.vv v8, v4, v8		# OK
++	vdivu.vv v0, v4, v8, v0.t	# vd overlap vm
++	vdivu.vx v4, v4, a1		# OK
++	vdivu.vx v0, v4, a1, v0.t	# vd overlap vm
++
++	vdiv.vv v4, v4, v8
++	vdiv.vv v8, v4, v8
++	vdiv.vv v0, v4, v8, v0.t
++	vdiv.vx v4, v4, a1
++	vdiv.vx v0, v4, a1, v0.t
++
++	vremu.vv v4, v4, v8
++	vremu.vv v8, v4, v8
++	vremu.vv v0, v4, v8, v0.t
++	vremu.vx v4, v4, a1
++	vremu.vx v0, v4, a1, v0.t
++
++	vrem.vv v4, v4, v8
++	vrem.vv v8, v4, v8
++	vrem.vv v0, v4, v8, v0.t
++	vrem.vx v4, v4, a1
++	vrem.vx v0, v4, a1, v0.t
++
++# Vector Single-Width Integer Multiply-Add Instructions
++
++	vmacc.vv v4, v4, v8		# OK
++	vmacc.vv v8, v4, v8		# OK
++	vmacc.vv v0, v4, v8, v0.t	# vd overlap vm
++	vmacc.vx v4, a1, v4		# OK
++	vmacc.vx v0, a1, v4, v0.t	# vd overlap vm
++
++	vnmsac.vv v4, v4, v8
++	vnmsac.vv v8, v4, v8
++	vnmsac.vv v0, v4, v8, v0.t
++	vnmsac.vx v4, a1, v4
++	vnmsac.vx v0, a1, v4, v0.t
++
++	vmadd.vv v4, v4, v8
++	vmadd.vv v8, v4, v8
++	vmadd.vv v0, v4, v8, v0.t
++	vmadd.vx v4, a1, v4
++	vmadd.vx v0, a1, v4, v0.t
++
++	vnmsub.vv v4, v4, v8
++	vnmsub.vv v8, v4, v8
++	vnmsub.vv v0, v4, v8, v0.t
++	vnmsub.vx v4, a1, v4
++	vnmsub.vx v0, a1, v4, v0.t
+diff --git a/gas/testsuite/gas/riscv/vector-insns-fail-load-store.d b/gas/testsuite/gas/riscv/vector-insns-fail-load-store.d
+new file mode 100644
+index 0000000000..7d3d6bfe78
+--- /dev/null
++++ b/gas/testsuite/gas/riscv/vector-insns-fail-load-store.d
+@@ -0,0 +1,3 @@
++#as: -march=rv32iv0p10
++#source: vector-insns-fail-load-store.s
++#error_output: vector-insns-fail-load-store.l
+diff --git a/gas/testsuite/gas/riscv/vector-insns-fail-load-store.l b/gas/testsuite/gas/riscv/vector-insns-fail-load-store.l
+new file mode 100644
+index 0000000000..47259a3a7e
+--- /dev/null
++++ b/gas/testsuite/gas/riscv/vector-insns-fail-load-store.l
+@@ -0,0 +1,25 @@
++.*: Assembler messages:
++.*Error: illegal operands `vle8.v v0,\(a0\),v0.t'
++.*Error: illegal operands `vle16.v v0,\(a0\),v0.t'
++.*Error: illegal operands `vle32.v v0,\(a0\),v0.t'
++.*Error: illegal operands `vle64.v v0,\(a0\),v0.t'
++.*Error: illegal operands `vse8.v v0,\(a0\),v0.t'
++.*Error: illegal operands `vse16.v v0,\(a0\),v0.t'
++.*Error: illegal operands `vse32.v v0,\(a0\),v0.t'
++.*Error: illegal operands `vse64.v v0,\(a0\),v0.t'
++.*Error: illegal operands `vlse8.v v0,\(a0\),a1,v0.t'
++.*Error: illegal operands `vlse16.v v0,\(a0\),a1,v0.t'
++.*Error: illegal operands `vlse32.v v0,\(a0\),a1,v0.t'
++.*Error: illegal operands `vlse64.v v0,\(a0\),a1,v0.t'
++.*Error: illegal operands `vsse8.v v0,\(a0\),a1,v0.t'
++.*Error: illegal operands `vsse16.v v0,\(a0\),a1,v0.t'
++.*Error: illegal operands `vsse32.v v0,\(a0\),a1,v0.t'
++.*Error: illegal operands `vsse64.v v0,\(a0\),a1,v0.t'
++.*Error: illegal operands `vloxei8.v v0,\(a0\),v4,v0.t'
++.*Error: illegal operands `vloxei16.v v0,\(a0\),v4,v0.t'
++.*Error: illegal operands `vloxei32.v v0,\(a0\),v4,v0.t'
++.*Error: illegal operands `vloxei64.v v0,\(a0\),v4,v0.t'
++.*Error: illegal operands `vsoxei8.v v0,\(a0\),v4,v0.t'
++.*Error: illegal operands `vsoxei16.v v0,\(a0\),v4,v0.t'
++.*Error: illegal operands `vsoxei32.v v0,\(a0\),v4,v0.t'
++.*Error: illegal operands `vsoxei64.v v0,\(a0\),v4,v0.t'
+diff --git a/gas/testsuite/gas/riscv/vector-insns-fail-load-store.s b/gas/testsuite/gas/riscv/vector-insns-fail-load-store.s
+new file mode 100644
+index 0000000000..ce3b9ec013
+--- /dev/null
++++ b/gas/testsuite/gas/riscv/vector-insns-fail-load-store.s
+@@ -0,0 +1,43 @@
++# Vector Unit-Stride Loads and Stores
++
++	vle8.v v0, (a0), v0.t		# vd overlap vm
++	vle16.v v0, (a0), v0.t
++	vle32.v v0, (a0), v0.t
++	vle64.v v0, (a0), v0.t
++
++	vse8.v v0, (a0), v0.t		# vd overlap vm
++	vse16.v v0, (a0), v0.t
++	vse32.v v0, (a0), v0.t
++	vse64.v v0, (a0), v0.t
++
++# Vector Strided Loads and Stores
++
++	vlse8.v v0, (a0), a1, v0.t	# vd overlap vm
++	vlse16.v v0, (a0), a1, v0.t
++	vlse32.v v0, (a0), a1, v0.t
++	vlse64.v v0, (a0), a1, v0.t
++
++	vsse8.v v0, (a0), a1, v0.t
++	vsse16.v v0, (a0), a1, v0.t
++	vsse32.v v0, (a0), a1, v0.t
++	vsse64.v v0, (a0), a1, v0.t
++
++# Vector Ordered Indexed Loads and Stores
++
++	vloxei8.v v4, (a0), v4		# OK
++	vloxei8.v v0, (a0), v4, v0.t	# vd overlap vm
++	vloxei16.v v4, (a0), v4
++	vloxei16.v v0, (a0), v4, v0.t
++	vloxei32.v v4, (a0), v4
++	vloxei32.v v0, (a0), v4, v0.t
++	vloxei64.v v4, (a0), v4
++	vloxei64.v v0, (a0), v4, v0.t
++
++	vsoxei8.v v4, (a0), v4
++	vsoxei8.v v0, (a0), v4, v0.t
++	vsoxei16.v v4, (a0), v4
++	vsoxei16.v v0, (a0), v4, v0.t
++	vsoxei32.v v4, (a0), v4
++	vsoxei32.v v0, (a0), v4, v0.t
++	vsoxei64.v v4, (a0), v4
++	vsoxei64.v v0, (a0), v4, v0.t
+diff --git a/gas/testsuite/gas/riscv/vector-insns-fail-permutation.d b/gas/testsuite/gas/riscv/vector-insns-fail-permutation.d
+new file mode 100644
+index 0000000000..ebdd2b1051
+--- /dev/null
++++ b/gas/testsuite/gas/riscv/vector-insns-fail-permutation.d
+@@ -0,0 +1,3 @@
++#as: -march=rv32ifv0p10
++#source: vector-insns-fail-permutation.s
++#error_output: vector-insns-fail-permutation.l
+diff --git a/gas/testsuite/gas/riscv/vector-insns-fail-permutation.l b/gas/testsuite/gas/riscv/vector-insns-fail-permutation.l
+new file mode 100644
+index 0000000000..682f1cd9a4
+--- /dev/null
++++ b/gas/testsuite/gas/riscv/vector-insns-fail-permutation.l
+@@ -0,0 +1,19 @@
++.*: Assembler messages:
++.*Error: illegal operands `vslideup.vx v4,v4,a1'
++.*Error: illegal operands `vslideup.vx v0,v4,a1,v0.t'
++.*Error: illegal operands `vslideup.vi v4,v4,31'
++.*Error: illegal operands `vslideup.vi v0,v4,31,v0.t'
++.*Error: illegal operands `vslidedown.vx v0,v4,a1,v0.t'
++.*Error: illegal operands `vslidedown.vi v0,v4,31,v0.t'
++.*Error: illegal operands `vslide1up.vx v4,v4,a1'
++.*Error: illegal operands `vslide1up.vx v0,v4,a1,v0.t'
++.*Error: illegal operands `vfslide1up.vf v4,v4,fa1'
++.*Error: illegal operands `vfslide1up.vf v0,v4,fa1,v0.t'
++.*Error: illegal operands `vslide1down.vx v0,v4,a1,v0.t'
++.*Error: illegal operands `vfslide1down.vf v0,v4,fa1,v0.t'
++.*Error: illegal operands `vrgather.vx v4,v4,a1'
++.*Error: illegal operands `vrgather.vx v0,v4,a1,v0.t'
++.*Error: illegal operands `vrgather.vi v4,v4,31'
++.*Error: illegal operands `vrgather.vi v0,v4,31,v0.t'
++.*Error: illegal operands `vcompress.vm v4,v4,v8'
++.*Error: illegal operands `vcompress.vm v8,v4,v8'
+diff --git a/gas/testsuite/gas/riscv/vector-insns-fail-permutation.s b/gas/testsuite/gas/riscv/vector-insns-fail-permutation.s
+new file mode 100644
+index 0000000000..834bee925b
+--- /dev/null
++++ b/gas/testsuite/gas/riscv/vector-insns-fail-permutation.s
+@@ -0,0 +1,37 @@
++# Vector Slideup Instructions
++
++	vslideup.vx v4, v4, a1			# vd overlap vs2
++	vslideup.vx v0, v4, a1, v0.t		# vd overlap vm
++	vslideup.vi v4, v4, 31			# vd overlap vs2
++	vslideup.vi v0, v4, 31, v0.t		# vd overlap vm
++
++	vslidedown.vx v4, v4, a1		# OK
++	vslidedown.vx v0, v4, a1, v0.t		# vd overlap vm
++	vslidedown.vi v4, v4, 31		# OK
++	vslidedown.vi v0, v4, 31, v0.t		# vd overlap vm
++
++	vslide1up.vx v4, v4, a1			# vd overlap vs2
++	vslide1up.vx v0, v4, a1, v0.t		# vd overlap vm
++	vfslide1up.vf v4, v4, fa1		# vd overlap vs2
++	vfslide1up.vf v0, v4, fa1, v0.t		# vd overlap vm
++
++	vslide1down.vx v4, v4, a1		# OK
++	vslide1down.vx v0, v4, a1, v0.t		# vd overlap vm
++	vfslide1down.vf v4, v4, fa1		# OK
++	vfslide1down.vf v0, v4, fa1, v0.t	# vd overlap vm
++
++# Vector Register Gather Instructions
++
++	vrgather.vv v4, v4, v8			# vd overlap vs2
++	vrgather.vv v8, v4, v8			# vd overlap vs1
++	vrgather.vv v0, v4, v8, v0.t		# vd overlap vm
++	vrgather.vx v4, v4, a1			# vd overlap vs2
++	vrgather.vx v0, v4, a1, v0.t		# vd overlap vm
++	vrgather.vi v4, v4, 31			# vd overlap vs2
++	vrgather.vi v0, v4, 31, v0.t		# vd overlap vm
++
++# Vector Compress Instruction
++
++	vcompress.vm v4, v4, v8			# vd overlap vs2
++	vcompress.vm v8, v4, v8			# vd overlap vs1
++
+diff --git a/gas/testsuite/gas/riscv/vector-insns-fail-unsupport.d b/gas/testsuite/gas/riscv/vector-insns-fail-unsupport.d
+new file mode 100644
+index 0000000000..cca6928e7d
+--- /dev/null
++++ b/gas/testsuite/gas/riscv/vector-insns-fail-unsupport.d
+@@ -0,0 +1,3 @@
++#as: -march=rv32iv0p10 
++#source: vector-insns-fail-unsupport.s
++#error_output: vector-insns-fail-unsupport.l
+diff --git a/gas/testsuite/gas/riscv/vector-insns-fail-unsupport.l b/gas/testsuite/gas/riscv/vector-insns-fail-unsupport.l
+new file mode 100644
+index 0000000000..ae2230cb9e
+--- /dev/null
++++ b/gas/testsuite/gas/riscv/vector-insns-fail-unsupport.l
+@@ -0,0 +1,1469 @@
++.*: Assembler messages:
++.*: Error: unrecognized opcode `vsetivli a0,0xb,0'
++.*: Error: unrecognized opcode `vsetivli a0,0xb,0x3ff'
++.*: Error: unrecognized opcode `vsetivli a0,0xb,e16,m2'
++.*: Error: unrecognized opcode `vsetivli a0,0xb,e256,m8'
++.*: Error: unrecognized opcode `vsetivli a0,0xb,e512,m8'
++.*: Error: unrecognized opcode `vsetivli a0,0xb,e1024,m8'
++.*: Error: unrecognized opcode `vsetivli a0,0xb,e1024,m1'
++.*: Error: unrecognized opcode `vsetivli a0,0xb,e1024,mf2'
++.*: Error: unrecognized opcode `vsetivli a0,0xb,e512,mf4'
++.*: Error: unrecognized opcode `vsetivli a0,0xb,e256,mf8'
++.*: Error: unrecognized opcode `vsetivli a0,0xb,e256,m2,ta'
++.*: Error: unrecognized opcode `vsetivli a0,0xb,e256,m2,ma'
++.*: Error: unrecognized opcode `vsetivli a0,0xb,e256,m2,tu'
++.*: Error: unrecognized opcode `vsetivli a0,0xb,e256,m2,mu'
++.*: Error: unrecognized opcode `vsetivli a0,0xb,e256,m2,ta,ma'
++.*: Error: unrecognized opcode `vsetivli a0,0xb,e256,m2,tu,ma'
++.*: Error: unrecognized opcode `vsetivli a0,0xb,e256,m2,ta,mu'
++.*: Error: unrecognized opcode `vsetivli a0,0xb,e256,m2,tu,mu'
++.*: Error: unrecognized opcode `vle1.v v4,\(a0\)'
++.*: Error: unrecognized opcode `vle1.v v4,0\(a0\)'
++.*: Error: unrecognized opcode `vse1.v v4,\(a0\)'
++.*: Error: unrecognized opcode `vse1.v v4,0\(a0\)'
++.*: Error: unrecognized opcode `vluxei8.v v4,\(a0\),v12'
++.*: Error: unrecognized opcode `vluxei8.v v4,0\(a0\),v12'
++.*: Error: unrecognized opcode `vluxei8.v v4,\(a0\),v12,v0.t'
++.*: Error: unrecognized opcode `vsuxei8.v v4,\(a0\),v12'
++.*: Error: unrecognized opcode `vsuxei8.v v4,0\(a0\),v12'
++.*: Error: unrecognized opcode `vsuxei8.v v4,\(a0\),v12,v0.t'
++.*: Error: unrecognized opcode `vluxei16.v v4,\(a0\),v12'
++.*: Error: unrecognized opcode `vluxei16.v v4,0\(a0\),v12'
++.*: Error: unrecognized opcode `vluxei16.v v4,\(a0\),v12,v0.t'
++.*: Error: unrecognized opcode `vsuxei16.v v4,\(a0\),v12'
++.*: Error: unrecognized opcode `vsuxei16.v v4,0\(a0\),v12'
++.*: Error: unrecognized opcode `vsuxei16.v v4,\(a0\),v12,v0.t'
++.*: Error: unrecognized opcode `vluxei32.v v4,\(a0\),v12'
++.*: Error: unrecognized opcode `vluxei32.v v4,0\(a0\),v12'
++.*: Error: unrecognized opcode `vluxei32.v v4,\(a0\),v12,v0.t'
++.*: Error: unrecognized opcode `vsuxei32.v v4,\(a0\),v12'
++.*: Error: unrecognized opcode `vsuxei32.v v4,0\(a0\),v12'
++.*: Error: unrecognized opcode `vsuxei32.v v4,\(a0\),v12,v0.t'
++.*: Error: unrecognized opcode `vluxei64.v v4,\(a0\),v12'
++.*: Error: unrecognized opcode `vluxei64.v v4,0\(a0\),v12'
++.*: Error: unrecognized opcode `vluxei64.v v4,\(a0\),v12,v0.t'
++.*: Error: unrecognized opcode `vsuxei64.v v4,\(a0\),v12'
++.*: Error: unrecognized opcode `vsuxei64.v v4,0\(a0\),v12'
++.*: Error: unrecognized opcode `vsuxei64.v v4,\(a0\),v12,v0.t'
++.*: Error: unrecognized opcode `vle8ff.v v4,\(a0\)'
++.*: Error: unrecognized opcode `vle8ff.v v4,0\(a0\)'
++.*: Error: unrecognized opcode `vle8ff.v v4,\(a0\),v0.t'
++.*: Error: unrecognized opcode `vle16ff.v v4,\(a0\)'
++.*: Error: unrecognized opcode `vle16ff.v v4,0\(a0\)'
++.*: Error: unrecognized opcode `vle16ff.v v4,\(a0\),v0.t'
++.*: Error: unrecognized opcode `vle32ff.v v4,\(a0\)'
++.*: Error: unrecognized opcode `vle32ff.v v4,0\(a0\)'
++.*: Error: unrecognized opcode `vle32ff.v v4,\(a0\),v0.t'
++.*: Error: unrecognized opcode `vle64ff.v v4,\(a0\)'
++.*: Error: unrecognized opcode `vle64ff.v v4,0\(a0\)'
++.*: Error: unrecognized opcode `vle64ff.v v4,\(a0\),v0.t'
++.*: Error: unrecognized opcode `vlseg2e8.v v4,\(a0\)'
++.*: Error: unrecognized opcode `vlseg2e8.v v4,0\(a0\)'
++.*: Error: unrecognized opcode `vlseg2e8.v v4,\(a0\),v0.t'
++.*: Error: unrecognized opcode `vsseg2e8.v v4,\(a0\)'
++.*: Error: unrecognized opcode `vsseg2e8.v v4,0\(a0\)'
++.*: Error: unrecognized opcode `vsseg2e8.v v4,\(a0\),v0.t'
++.*: Error: unrecognized opcode `vlseg3e8.v v4,\(a0\)'
++.*: Error: unrecognized opcode `vlseg3e8.v v4,0\(a0\)'
++.*: Error: unrecognized opcode `vlseg3e8.v v4,\(a0\),v0.t'
++.*: Error: unrecognized opcode `vsseg3e8.v v4,\(a0\)'
++.*: Error: unrecognized opcode `vsseg3e8.v v4,0\(a0\)'
++.*: Error: unrecognized opcode `vsseg3e8.v v4,\(a0\),v0.t'
++.*: Error: unrecognized opcode `vlseg4e8.v v4,\(a0\)'
++.*: Error: unrecognized opcode `vlseg4e8.v v4,0\(a0\)'
++.*: Error: unrecognized opcode `vlseg4e8.v v4,\(a0\),v0.t'
++.*: Error: unrecognized opcode `vsseg4e8.v v4,\(a0\)'
++.*: Error: unrecognized opcode `vsseg4e8.v v4,0\(a0\)'
++.*: Error: unrecognized opcode `vsseg4e8.v v4,\(a0\),v0.t'
++.*: Error: unrecognized opcode `vlseg5e8.v v4,\(a0\)'
++.*: Error: unrecognized opcode `vlseg5e8.v v4,0\(a0\)'
++.*: Error: unrecognized opcode `vlseg5e8.v v4,\(a0\),v0.t'
++.*: Error: unrecognized opcode `vsseg5e8.v v4,\(a0\)'
++.*: Error: unrecognized opcode `vsseg5e8.v v4,0\(a0\)'
++.*: Error: unrecognized opcode `vsseg5e8.v v4,\(a0\),v0.t'
++.*: Error: unrecognized opcode `vlseg6e8.v v4,\(a0\)'
++.*: Error: unrecognized opcode `vlseg6e8.v v4,0\(a0\)'
++.*: Error: unrecognized opcode `vlseg6e8.v v4,\(a0\),v0.t'
++.*: Error: unrecognized opcode `vsseg6e8.v v4,\(a0\)'
++.*: Error: unrecognized opcode `vsseg6e8.v v4,0\(a0\)'
++.*: Error: unrecognized opcode `vsseg6e8.v v4,\(a0\),v0.t'
++.*: Error: unrecognized opcode `vlseg7e8.v v4,\(a0\)'
++.*: Error: unrecognized opcode `vlseg7e8.v v4,0\(a0\)'
++.*: Error: unrecognized opcode `vlseg7e8.v v4,\(a0\),v0.t'
++.*: Error: unrecognized opcode `vsseg7e8.v v4,\(a0\)'
++.*: Error: unrecognized opcode `vsseg7e8.v v4,0\(a0\)'
++.*: Error: unrecognized opcode `vsseg7e8.v v4,\(a0\),v0.t'
++.*: Error: unrecognized opcode `vlseg8e8.v v4,\(a0\)'
++.*: Error: unrecognized opcode `vlseg8e8.v v4,0\(a0\)'
++.*: Error: unrecognized opcode `vlseg8e8.v v4,\(a0\),v0.t'
++.*: Error: unrecognized opcode `vsseg8e8.v v4,\(a0\)'
++.*: Error: unrecognized opcode `vsseg8e8.v v4,0\(a0\)'
++.*: Error: unrecognized opcode `vsseg8e8.v v4,\(a0\),v0.t'
++.*: Error: unrecognized opcode `vlseg2e16.v v4,\(a0\)'
++.*: Error: unrecognized opcode `vlseg2e16.v v4,0\(a0\)'
++.*: Error: unrecognized opcode `vlseg2e16.v v4,\(a0\),v0.t'
++.*: Error: unrecognized opcode `vsseg2e16.v v4,\(a0\)'
++.*: Error: unrecognized opcode `vsseg2e16.v v4,0\(a0\)'
++.*: Error: unrecognized opcode `vsseg2e16.v v4,\(a0\),v0.t'
++.*: Error: unrecognized opcode `vlseg3e16.v v4,\(a0\)'
++.*: Error: unrecognized opcode `vlseg3e16.v v4,0\(a0\)'
++.*: Error: unrecognized opcode `vlseg3e16.v v4,\(a0\),v0.t'
++.*: Error: unrecognized opcode `vsseg3e16.v v4,\(a0\)'
++.*: Error: unrecognized opcode `vsseg3e16.v v4,0\(a0\)'
++.*: Error: unrecognized opcode `vsseg3e16.v v4,\(a0\),v0.t'
++.*: Error: unrecognized opcode `vlseg4e16.v v4,\(a0\)'
++.*: Error: unrecognized opcode `vlseg4e16.v v4,0\(a0\)'
++.*: Error: unrecognized opcode `vlseg4e16.v v4,\(a0\),v0.t'
++.*: Error: unrecognized opcode `vsseg4e16.v v4,\(a0\)'
++.*: Error: unrecognized opcode `vsseg4e16.v v4,0\(a0\)'
++.*: Error: unrecognized opcode `vsseg4e16.v v4,\(a0\),v0.t'
++.*: Error: unrecognized opcode `vlseg5e16.v v4,\(a0\)'
++.*: Error: unrecognized opcode `vlseg5e16.v v4,0\(a0\)'
++.*: Error: unrecognized opcode `vlseg5e16.v v4,\(a0\),v0.t'
++.*: Error: unrecognized opcode `vsseg5e16.v v4,\(a0\)'
++.*: Error: unrecognized opcode `vsseg5e16.v v4,0\(a0\)'
++.*: Error: unrecognized opcode `vsseg5e16.v v4,\(a0\),v0.t'
++.*: Error: unrecognized opcode `vlseg6e16.v v4,\(a0\)'
++.*: Error: unrecognized opcode `vlseg6e16.v v4,0\(a0\)'
++.*: Error: unrecognized opcode `vlseg6e16.v v4,\(a0\),v0.t'
++.*: Error: unrecognized opcode `vsseg6e16.v v4,\(a0\)'
++.*: Error: unrecognized opcode `vsseg6e16.v v4,0\(a0\)'
++.*: Error: unrecognized opcode `vsseg6e16.v v4,\(a0\),v0.t'
++.*: Error: unrecognized opcode `vlseg7e16.v v4,\(a0\)'
++.*: Error: unrecognized opcode `vlseg7e16.v v4,0\(a0\)'
++.*: Error: unrecognized opcode `vlseg7e16.v v4,\(a0\),v0.t'
++.*: Error: unrecognized opcode `vsseg7e16.v v4,\(a0\)'
++.*: Error: unrecognized opcode `vsseg7e16.v v4,0\(a0\)'
++.*: Error: unrecognized opcode `vsseg7e16.v v4,\(a0\),v0.t'
++.*: Error: unrecognized opcode `vlseg8e16.v v4,\(a0\)'
++.*: Error: unrecognized opcode `vlseg8e16.v v4,0\(a0\)'
++.*: Error: unrecognized opcode `vlseg8e16.v v4,\(a0\),v0.t'
++.*: Error: unrecognized opcode `vsseg8e16.v v4,\(a0\)'
++.*: Error: unrecognized opcode `vsseg8e16.v v4,0\(a0\)'
++.*: Error: unrecognized opcode `vsseg8e16.v v4,\(a0\),v0.t'
++.*: Error: unrecognized opcode `vlseg2e32.v v4,\(a0\)'
++.*: Error: unrecognized opcode `vlseg2e32.v v4,0\(a0\)'
++.*: Error: unrecognized opcode `vlseg2e32.v v4,\(a0\),v0.t'
++.*: Error: unrecognized opcode `vsseg2e32.v v4,\(a0\)'
++.*: Error: unrecognized opcode `vsseg2e32.v v4,0\(a0\)'
++.*: Error: unrecognized opcode `vsseg2e32.v v4,\(a0\),v0.t'
++.*: Error: unrecognized opcode `vlseg3e32.v v4,\(a0\)'
++.*: Error: unrecognized opcode `vlseg3e32.v v4,0\(a0\)'
++.*: Error: unrecognized opcode `vlseg3e32.v v4,\(a0\),v0.t'
++.*: Error: unrecognized opcode `vsseg3e32.v v4,\(a0\)'
++.*: Error: unrecognized opcode `vsseg3e32.v v4,0\(a0\)'
++.*: Error: unrecognized opcode `vsseg3e32.v v4,\(a0\),v0.t'
++.*: Error: unrecognized opcode `vlseg4e32.v v4,\(a0\)'
++.*: Error: unrecognized opcode `vlseg4e32.v v4,0\(a0\)'
++.*: Error: unrecognized opcode `vlseg4e32.v v4,\(a0\),v0.t'
++.*: Error: unrecognized opcode `vsseg4e32.v v4,\(a0\)'
++.*: Error: unrecognized opcode `vsseg4e32.v v4,0\(a0\)'
++.*: Error: unrecognized opcode `vsseg4e32.v v4,\(a0\),v0.t'
++.*: Error: unrecognized opcode `vlseg5e32.v v4,\(a0\)'
++.*: Error: unrecognized opcode `vlseg5e32.v v4,0\(a0\)'
++.*: Error: unrecognized opcode `vlseg5e32.v v4,\(a0\),v0.t'
++.*: Error: unrecognized opcode `vsseg5e32.v v4,\(a0\)'
++.*: Error: unrecognized opcode `vsseg5e32.v v4,0\(a0\)'
++.*: Error: unrecognized opcode `vsseg5e32.v v4,\(a0\),v0.t'
++.*: Error: unrecognized opcode `vlseg6e32.v v4,\(a0\)'
++.*: Error: unrecognized opcode `vlseg6e32.v v4,0\(a0\)'
++.*: Error: unrecognized opcode `vlseg6e32.v v4,\(a0\),v0.t'
++.*: Error: unrecognized opcode `vsseg6e32.v v4,\(a0\)'
++.*: Error: unrecognized opcode `vsseg6e32.v v4,0\(a0\)'
++.*: Error: unrecognized opcode `vsseg6e32.v v4,\(a0\),v0.t'
++.*: Error: unrecognized opcode `vlseg7e32.v v4,\(a0\)'
++.*: Error: unrecognized opcode `vlseg7e32.v v4,0\(a0\)'
++.*: Error: unrecognized opcode `vlseg7e32.v v4,\(a0\),v0.t'
++.*: Error: unrecognized opcode `vsseg7e32.v v4,\(a0\)'
++.*: Error: unrecognized opcode `vsseg7e32.v v4,0\(a0\)'
++.*: Error: unrecognized opcode `vsseg7e32.v v4,\(a0\),v0.t'
++.*: Error: unrecognized opcode `vlseg8e32.v v4,\(a0\)'
++.*: Error: unrecognized opcode `vlseg8e32.v v4,0\(a0\)'
++.*: Error: unrecognized opcode `vlseg8e32.v v4,\(a0\),v0.t'
++.*: Error: unrecognized opcode `vsseg8e32.v v4,\(a0\)'
++.*: Error: unrecognized opcode `vsseg8e32.v v4,0\(a0\)'
++.*: Error: unrecognized opcode `vsseg8e32.v v4,\(a0\),v0.t'
++.*: Error: unrecognized opcode `vlseg2e64.v v4,\(a0\)'
++.*: Error: unrecognized opcode `vlseg2e64.v v4,0\(a0\)'
++.*: Error: unrecognized opcode `vlseg2e64.v v4,\(a0\),v0.t'
++.*: Error: unrecognized opcode `vsseg2e64.v v4,\(a0\)'
++.*: Error: unrecognized opcode `vsseg2e64.v v4,0\(a0\)'
++.*: Error: unrecognized opcode `vsseg2e64.v v4,\(a0\),v0.t'
++.*: Error: unrecognized opcode `vlseg3e64.v v4,\(a0\)'
++.*: Error: unrecognized opcode `vlseg3e64.v v4,0\(a0\)'
++.*: Error: unrecognized opcode `vlseg3e64.v v4,\(a0\),v0.t'
++.*: Error: unrecognized opcode `vsseg3e64.v v4,\(a0\)'
++.*: Error: unrecognized opcode `vsseg3e64.v v4,0\(a0\)'
++.*: Error: unrecognized opcode `vsseg3e64.v v4,\(a0\),v0.t'
++.*: Error: unrecognized opcode `vlseg4e64.v v4,\(a0\)'
++.*: Error: unrecognized opcode `vlseg4e64.v v4,0\(a0\)'
++.*: Error: unrecognized opcode `vlseg4e64.v v4,\(a0\),v0.t'
++.*: Error: unrecognized opcode `vsseg4e64.v v4,\(a0\)'
++.*: Error: unrecognized opcode `vsseg4e64.v v4,0\(a0\)'
++.*: Error: unrecognized opcode `vsseg4e64.v v4,\(a0\),v0.t'
++.*: Error: unrecognized opcode `vlseg5e64.v v4,\(a0\)'
++.*: Error: unrecognized opcode `vlseg5e64.v v4,0\(a0\)'
++.*: Error: unrecognized opcode `vlseg5e64.v v4,\(a0\),v0.t'
++.*: Error: unrecognized opcode `vsseg5e64.v v4,\(a0\)'
++.*: Error: unrecognized opcode `vsseg5e64.v v4,0\(a0\)'
++.*: Error: unrecognized opcode `vsseg5e64.v v4,\(a0\),v0.t'
++.*: Error: unrecognized opcode `vlseg6e64.v v4,\(a0\)'
++.*: Error: unrecognized opcode `vlseg6e64.v v4,0\(a0\)'
++.*: Error: unrecognized opcode `vlseg6e64.v v4,\(a0\),v0.t'
++.*: Error: unrecognized opcode `vsseg6e64.v v4,\(a0\)'
++.*: Error: unrecognized opcode `vsseg6e64.v v4,0\(a0\)'
++.*: Error: unrecognized opcode `vsseg6e64.v v4,\(a0\),v0.t'
++.*: Error: unrecognized opcode `vlseg7e64.v v4,\(a0\)'
++.*: Error: unrecognized opcode `vlseg7e64.v v4,0\(a0\)'
++.*: Error: unrecognized opcode `vlseg7e64.v v4,\(a0\),v0.t'
++.*: Error: unrecognized opcode `vsseg7e64.v v4,\(a0\)'
++.*: Error: unrecognized opcode `vsseg7e64.v v4,0\(a0\)'
++.*: Error: unrecognized opcode `vsseg7e64.v v4,\(a0\),v0.t'
++.*: Error: unrecognized opcode `vlseg8e64.v v4,\(a0\)'
++.*: Error: unrecognized opcode `vlseg8e64.v v4,0\(a0\)'
++.*: Error: unrecognized opcode `vlseg8e64.v v4,\(a0\),v0.t'
++.*: Error: unrecognized opcode `vsseg8e64.v v4,\(a0\)'
++.*: Error: unrecognized opcode `vsseg8e64.v v4,0\(a0\)'
++.*: Error: unrecognized opcode `vsseg8e64.v v4,\(a0\),v0.t'
++.*: Error: unrecognized opcode `vlsseg2e8.v v4,\(a0\),a1'
++.*: Error: unrecognized opcode `vlsseg2e8.v v4,0\(a0\),a1'
++.*: Error: unrecognized opcode `vlsseg2e8.v v4,\(a0\),a1,v0.t'
++.*: Error: unrecognized opcode `vssseg2e8.v v4,\(a0\),a1'
++.*: Error: unrecognized opcode `vssseg2e8.v v4,0\(a0\),a1'
++.*: Error: unrecognized opcode `vssseg2e8.v v4,\(a0\),a1,v0.t'
++.*: Error: unrecognized opcode `vlsseg3e8.v v4,\(a0\),a1'
++.*: Error: unrecognized opcode `vlsseg3e8.v v4,0\(a0\),a1'
++.*: Error: unrecognized opcode `vlsseg3e8.v v4,\(a0\),a1,v0.t'
++.*: Error: unrecognized opcode `vssseg3e8.v v4,\(a0\),a1'
++.*: Error: unrecognized opcode `vssseg3e8.v v4,0\(a0\),a1'
++.*: Error: unrecognized opcode `vssseg3e8.v v4,\(a0\),a1,v0.t'
++.*: Error: unrecognized opcode `vlsseg4e8.v v4,\(a0\),a1'
++.*: Error: unrecognized opcode `vlsseg4e8.v v4,0\(a0\),a1'
++.*: Error: unrecognized opcode `vlsseg4e8.v v4,\(a0\),a1,v0.t'
++.*: Error: unrecognized opcode `vssseg4e8.v v4,\(a0\),a1'
++.*: Error: unrecognized opcode `vssseg4e8.v v4,0\(a0\),a1'
++.*: Error: unrecognized opcode `vssseg4e8.v v4,\(a0\),a1,v0.t'
++.*: Error: unrecognized opcode `vlsseg5e8.v v4,\(a0\),a1'
++.*: Error: unrecognized opcode `vlsseg5e8.v v4,0\(a0\),a1'
++.*: Error: unrecognized opcode `vlsseg5e8.v v4,\(a0\),a1,v0.t'
++.*: Error: unrecognized opcode `vssseg5e8.v v4,\(a0\),a1'
++.*: Error: unrecognized opcode `vssseg5e8.v v4,0\(a0\),a1'
++.*: Error: unrecognized opcode `vssseg5e8.v v4,\(a0\),a1,v0.t'
++.*: Error: unrecognized opcode `vlsseg6e8.v v4,\(a0\),a1'
++.*: Error: unrecognized opcode `vlsseg6e8.v v4,0\(a0\),a1'
++.*: Error: unrecognized opcode `vlsseg6e8.v v4,\(a0\),a1,v0.t'
++.*: Error: unrecognized opcode `vssseg6e8.v v4,\(a0\),a1'
++.*: Error: unrecognized opcode `vssseg6e8.v v4,0\(a0\),a1'
++.*: Error: unrecognized opcode `vssseg6e8.v v4,\(a0\),a1,v0.t'
++.*: Error: unrecognized opcode `vlsseg7e8.v v4,\(a0\),a1'
++.*: Error: unrecognized opcode `vlsseg7e8.v v4,0\(a0\),a1'
++.*: Error: unrecognized opcode `vlsseg7e8.v v4,\(a0\),a1,v0.t'
++.*: Error: unrecognized opcode `vssseg7e8.v v4,\(a0\),a1'
++.*: Error: unrecognized opcode `vssseg7e8.v v4,0\(a0\),a1'
++.*: Error: unrecognized opcode `vssseg7e8.v v4,\(a0\),a1,v0.t'
++.*: Error: unrecognized opcode `vlsseg8e8.v v4,\(a0\),a1'
++.*: Error: unrecognized opcode `vlsseg8e8.v v4,0\(a0\),a1'
++.*: Error: unrecognized opcode `vlsseg8e8.v v4,\(a0\),a1,v0.t'
++.*: Error: unrecognized opcode `vssseg8e8.v v4,\(a0\),a1'
++.*: Error: unrecognized opcode `vssseg8e8.v v4,0\(a0\),a1'
++.*: Error: unrecognized opcode `vssseg8e8.v v4,\(a0\),a1,v0.t'
++.*: Error: unrecognized opcode `vlsseg2e16.v v4,\(a0\),a1'
++.*: Error: unrecognized opcode `vlsseg2e16.v v4,0\(a0\),a1'
++.*: Error: unrecognized opcode `vlsseg2e16.v v4,\(a0\),a1,v0.t'
++.*: Error: unrecognized opcode `vssseg2e16.v v4,\(a0\),a1'
++.*: Error: unrecognized opcode `vssseg2e16.v v4,0\(a0\),a1'
++.*: Error: unrecognized opcode `vssseg2e16.v v4,\(a0\),a1,v0.t'
++.*: Error: unrecognized opcode `vlsseg3e16.v v4,\(a0\),a1'
++.*: Error: unrecognized opcode `vlsseg3e16.v v4,0\(a0\),a1'
++.*: Error: unrecognized opcode `vlsseg3e16.v v4,\(a0\),a1,v0.t'
++.*: Error: unrecognized opcode `vssseg3e16.v v4,\(a0\),a1'
++.*: Error: unrecognized opcode `vssseg3e16.v v4,0\(a0\),a1'
++.*: Error: unrecognized opcode `vssseg3e16.v v4,\(a0\),a1,v0.t'
++.*: Error: unrecognized opcode `vlsseg4e16.v v4,\(a0\),a1'
++.*: Error: unrecognized opcode `vlsseg4e16.v v4,0\(a0\),a1'
++.*: Error: unrecognized opcode `vlsseg4e16.v v4,\(a0\),a1,v0.t'
++.*: Error: unrecognized opcode `vssseg4e16.v v4,\(a0\),a1'
++.*: Error: unrecognized opcode `vssseg4e16.v v4,0\(a0\),a1'
++.*: Error: unrecognized opcode `vssseg4e16.v v4,\(a0\),a1,v0.t'
++.*: Error: unrecognized opcode `vlsseg5e16.v v4,\(a0\),a1'
++.*: Error: unrecognized opcode `vlsseg5e16.v v4,0\(a0\),a1'
++.*: Error: unrecognized opcode `vlsseg5e16.v v4,\(a0\),a1,v0.t'
++.*: Error: unrecognized opcode `vssseg5e16.v v4,\(a0\),a1'
++.*: Error: unrecognized opcode `vssseg5e16.v v4,0\(a0\),a1'
++.*: Error: unrecognized opcode `vssseg5e16.v v4,\(a0\),a1,v0.t'
++.*: Error: unrecognized opcode `vlsseg6e16.v v4,\(a0\),a1'
++.*: Error: unrecognized opcode `vlsseg6e16.v v4,0\(a0\),a1'
++.*: Error: unrecognized opcode `vlsseg6e16.v v4,\(a0\),a1,v0.t'
++.*: Error: unrecognized opcode `vssseg6e16.v v4,\(a0\),a1'
++.*: Error: unrecognized opcode `vssseg6e16.v v4,0\(a0\),a1'
++.*: Error: unrecognized opcode `vssseg6e16.v v4,\(a0\),a1,v0.t'
++.*: Error: unrecognized opcode `vlsseg7e16.v v4,\(a0\),a1'
++.*: Error: unrecognized opcode `vlsseg7e16.v v4,0\(a0\),a1'
++.*: Error: unrecognized opcode `vlsseg7e16.v v4,\(a0\),a1,v0.t'
++.*: Error: unrecognized opcode `vssseg7e16.v v4,\(a0\),a1'
++.*: Error: unrecognized opcode `vssseg7e16.v v4,0\(a0\),a1'
++.*: Error: unrecognized opcode `vssseg7e16.v v4,\(a0\),a1,v0.t'
++.*: Error: unrecognized opcode `vlsseg8e16.v v4,\(a0\),a1'
++.*: Error: unrecognized opcode `vlsseg8e16.v v4,0\(a0\),a1'
++.*: Error: unrecognized opcode `vlsseg8e16.v v4,\(a0\),a1,v0.t'
++.*: Error: unrecognized opcode `vssseg8e16.v v4,\(a0\),a1'
++.*: Error: unrecognized opcode `vssseg8e16.v v4,0\(a0\),a1'
++.*: Error: unrecognized opcode `vssseg8e16.v v4,\(a0\),a1,v0.t'
++.*: Error: unrecognized opcode `vlsseg2e32.v v4,\(a0\),a1'
++.*: Error: unrecognized opcode `vlsseg2e32.v v4,0\(a0\),a1'
++.*: Error: unrecognized opcode `vlsseg2e32.v v4,\(a0\),a1,v0.t'
++.*: Error: unrecognized opcode `vssseg2e32.v v4,\(a0\),a1'
++.*: Error: unrecognized opcode `vssseg2e32.v v4,0\(a0\),a1'
++.*: Error: unrecognized opcode `vssseg2e32.v v4,\(a0\),a1,v0.t'
++.*: Error: unrecognized opcode `vlsseg3e32.v v4,\(a0\),a1'
++.*: Error: unrecognized opcode `vlsseg3e32.v v4,0\(a0\),a1'
++.*: Error: unrecognized opcode `vlsseg3e32.v v4,\(a0\),a1,v0.t'
++.*: Error: unrecognized opcode `vssseg3e32.v v4,\(a0\),a1'
++.*: Error: unrecognized opcode `vssseg3e32.v v4,0\(a0\),a1'
++.*: Error: unrecognized opcode `vssseg3e32.v v4,\(a0\),a1,v0.t'
++.*: Error: unrecognized opcode `vlsseg4e32.v v4,\(a0\),a1'
++.*: Error: unrecognized opcode `vlsseg4e32.v v4,0\(a0\),a1'
++.*: Error: unrecognized opcode `vlsseg4e32.v v4,\(a0\),a1,v0.t'
++.*: Error: unrecognized opcode `vssseg4e32.v v4,\(a0\),a1'
++.*: Error: unrecognized opcode `vssseg4e32.v v4,0\(a0\),a1'
++.*: Error: unrecognized opcode `vssseg4e32.v v4,\(a0\),a1,v0.t'
++.*: Error: unrecognized opcode `vlsseg5e32.v v4,\(a0\),a1'
++.*: Error: unrecognized opcode `vlsseg5e32.v v4,0\(a0\),a1'
++.*: Error: unrecognized opcode `vlsseg5e32.v v4,\(a0\),a1,v0.t'
++.*: Error: unrecognized opcode `vssseg5e32.v v4,\(a0\),a1'
++.*: Error: unrecognized opcode `vssseg5e32.v v4,0\(a0\),a1'
++.*: Error: unrecognized opcode `vssseg5e32.v v4,\(a0\),a1,v0.t'
++.*: Error: unrecognized opcode `vlsseg6e32.v v4,\(a0\),a1'
++.*: Error: unrecognized opcode `vlsseg6e32.v v4,0\(a0\),a1'
++.*: Error: unrecognized opcode `vlsseg6e32.v v4,\(a0\),a1,v0.t'
++.*: Error: unrecognized opcode `vssseg6e32.v v4,\(a0\),a1'
++.*: Error: unrecognized opcode `vssseg6e32.v v4,0\(a0\),a1'
++.*: Error: unrecognized opcode `vssseg6e32.v v4,\(a0\),a1,v0.t'
++.*: Error: unrecognized opcode `vlsseg7e32.v v4,\(a0\),a1'
++.*: Error: unrecognized opcode `vlsseg7e32.v v4,0\(a0\),a1'
++.*: Error: unrecognized opcode `vlsseg7e32.v v4,\(a0\),a1,v0.t'
++.*: Error: unrecognized opcode `vssseg7e32.v v4,\(a0\),a1'
++.*: Error: unrecognized opcode `vssseg7e32.v v4,0\(a0\),a1'
++.*: Error: unrecognized opcode `vssseg7e32.v v4,\(a0\),a1,v0.t'
++.*: Error: unrecognized opcode `vlsseg8e32.v v4,\(a0\),a1'
++.*: Error: unrecognized opcode `vlsseg8e32.v v4,0\(a0\),a1'
++.*: Error: unrecognized opcode `vlsseg8e32.v v4,\(a0\),a1,v0.t'
++.*: Error: unrecognized opcode `vssseg8e32.v v4,\(a0\),a1'
++.*: Error: unrecognized opcode `vssseg8e32.v v4,0\(a0\),a1'
++.*: Error: unrecognized opcode `vssseg8e32.v v4,\(a0\),a1,v0.t'
++.*: Error: unrecognized opcode `vlsseg2e64.v v4,\(a0\),a1'
++.*: Error: unrecognized opcode `vlsseg2e64.v v4,0\(a0\),a1'
++.*: Error: unrecognized opcode `vlsseg2e64.v v4,\(a0\),a1,v0.t'
++.*: Error: unrecognized opcode `vssseg2e64.v v4,\(a0\),a1'
++.*: Error: unrecognized opcode `vssseg2e64.v v4,0\(a0\),a1'
++.*: Error: unrecognized opcode `vssseg2e64.v v4,\(a0\),a1,v0.t'
++.*: Error: unrecognized opcode `vlsseg3e64.v v4,\(a0\),a1'
++.*: Error: unrecognized opcode `vlsseg3e64.v v4,0\(a0\),a1'
++.*: Error: unrecognized opcode `vlsseg3e64.v v4,\(a0\),a1,v0.t'
++.*: Error: unrecognized opcode `vssseg3e64.v v4,\(a0\),a1'
++.*: Error: unrecognized opcode `vssseg3e64.v v4,0\(a0\),a1'
++.*: Error: unrecognized opcode `vssseg3e64.v v4,\(a0\),a1,v0.t'
++.*: Error: unrecognized opcode `vlsseg4e64.v v4,\(a0\),a1'
++.*: Error: unrecognized opcode `vlsseg4e64.v v4,0\(a0\),a1'
++.*: Error: unrecognized opcode `vlsseg4e64.v v4,\(a0\),a1,v0.t'
++.*: Error: unrecognized opcode `vssseg4e64.v v4,\(a0\),a1'
++.*: Error: unrecognized opcode `vssseg4e64.v v4,0\(a0\),a1'
++.*: Error: unrecognized opcode `vssseg4e64.v v4,\(a0\),a1,v0.t'
++.*: Error: unrecognized opcode `vlsseg5e64.v v4,\(a0\),a1'
++.*: Error: unrecognized opcode `vlsseg5e64.v v4,0\(a0\),a1'
++.*: Error: unrecognized opcode `vlsseg5e64.v v4,\(a0\),a1,v0.t'
++.*: Error: unrecognized opcode `vssseg5e64.v v4,\(a0\),a1'
++.*: Error: unrecognized opcode `vssseg5e64.v v4,0\(a0\),a1'
++.*: Error: unrecognized opcode `vssseg5e64.v v4,\(a0\),a1,v0.t'
++.*: Error: unrecognized opcode `vlsseg6e64.v v4,\(a0\),a1'
++.*: Error: unrecognized opcode `vlsseg6e64.v v4,0\(a0\),a1'
++.*: Error: unrecognized opcode `vlsseg6e64.v v4,\(a0\),a1,v0.t'
++.*: Error: unrecognized opcode `vssseg6e64.v v4,\(a0\),a1'
++.*: Error: unrecognized opcode `vssseg6e64.v v4,0\(a0\),a1'
++.*: Error: unrecognized opcode `vssseg6e64.v v4,\(a0\),a1,v0.t'
++.*: Error: unrecognized opcode `vlsseg7e64.v v4,\(a0\),a1'
++.*: Error: unrecognized opcode `vlsseg7e64.v v4,0\(a0\),a1'
++.*: Error: unrecognized opcode `vlsseg7e64.v v4,\(a0\),a1,v0.t'
++.*: Error: unrecognized opcode `vssseg7e64.v v4,\(a0\),a1'
++.*: Error: unrecognized opcode `vssseg7e64.v v4,0\(a0\),a1'
++.*: Error: unrecognized opcode `vssseg7e64.v v4,\(a0\),a1,v0.t'
++.*: Error: unrecognized opcode `vlsseg8e64.v v4,\(a0\),a1'
++.*: Error: unrecognized opcode `vlsseg8e64.v v4,0\(a0\),a1'
++.*: Error: unrecognized opcode `vlsseg8e64.v v4,\(a0\),a1,v0.t'
++.*: Error: unrecognized opcode `vssseg8e64.v v4,\(a0\),a1'
++.*: Error: unrecognized opcode `vssseg8e64.v v4,0\(a0\),a1'
++.*: Error: unrecognized opcode `vssseg8e64.v v4,\(a0\),a1,v0.t'
++.*: Error: unrecognized opcode `vloxseg2ei8.v v4,\(a0\),v12'
++.*: Error: unrecognized opcode `vloxseg2ei8.v v4,0\(a0\),v12'
++.*: Error: unrecognized opcode `vloxseg2ei8.v v4,\(a0\),v12,v0.t'
++.*: Error: unrecognized opcode `vsoxseg2ei8.v v4,\(a0\),v12'
++.*: Error: unrecognized opcode `vsoxseg2ei8.v v4,0\(a0\),v12'
++.*: Error: unrecognized opcode `vsoxseg2ei8.v v4,\(a0\),v12,v0.t'
++.*: Error: unrecognized opcode `vloxseg3ei8.v v4,\(a0\),v12'
++.*: Error: unrecognized opcode `vloxseg3ei8.v v4,0\(a0\),v12'
++.*: Error: unrecognized opcode `vloxseg3ei8.v v4,\(a0\),v12,v0.t'
++.*: Error: unrecognized opcode `vsoxseg3ei8.v v4,\(a0\),v12'
++.*: Error: unrecognized opcode `vsoxseg3ei8.v v4,0\(a0\),v12'
++.*: Error: unrecognized opcode `vsoxseg3ei8.v v4,\(a0\),v12,v0.t'
++.*: Error: unrecognized opcode `vloxseg4ei8.v v4,\(a0\),v12'
++.*: Error: unrecognized opcode `vloxseg4ei8.v v4,0\(a0\),v12'
++.*: Error: unrecognized opcode `vloxseg4ei8.v v4,\(a0\),v12,v0.t'
++.*: Error: unrecognized opcode `vsoxseg4ei8.v v4,\(a0\),v12'
++.*: Error: unrecognized opcode `vsoxseg4ei8.v v4,0\(a0\),v12'
++.*: Error: unrecognized opcode `vsoxseg4ei8.v v4,\(a0\),v12,v0.t'
++.*: Error: unrecognized opcode `vloxseg5ei8.v v4,\(a0\),v12'
++.*: Error: unrecognized opcode `vloxseg5ei8.v v4,0\(a0\),v12'
++.*: Error: unrecognized opcode `vloxseg5ei8.v v4,\(a0\),v12,v0.t'
++.*: Error: unrecognized opcode `vsoxseg5ei8.v v4,\(a0\),v12'
++.*: Error: unrecognized opcode `vsoxseg5ei8.v v4,0\(a0\),v12'
++.*: Error: unrecognized opcode `vsoxseg5ei8.v v4,\(a0\),v12,v0.t'
++.*: Error: unrecognized opcode `vloxseg6ei8.v v4,\(a0\),v12'
++.*: Error: unrecognized opcode `vloxseg6ei8.v v4,0\(a0\),v12'
++.*: Error: unrecognized opcode `vloxseg6ei8.v v4,\(a0\),v12,v0.t'
++.*: Error: unrecognized opcode `vsoxseg6ei8.v v4,\(a0\),v12'
++.*: Error: unrecognized opcode `vsoxseg6ei8.v v4,0\(a0\),v12'
++.*: Error: unrecognized opcode `vsoxseg6ei8.v v4,\(a0\),v12,v0.t'
++.*: Error: unrecognized opcode `vloxseg7ei8.v v4,\(a0\),v12'
++.*: Error: unrecognized opcode `vloxseg7ei8.v v4,0\(a0\),v12'
++.*: Error: unrecognized opcode `vloxseg7ei8.v v4,\(a0\),v12,v0.t'
++.*: Error: unrecognized opcode `vsoxseg7ei8.v v4,\(a0\),v12'
++.*: Error: unrecognized opcode `vsoxseg7ei8.v v4,0\(a0\),v12'
++.*: Error: unrecognized opcode `vsoxseg7ei8.v v4,\(a0\),v12,v0.t'
++.*: Error: unrecognized opcode `vloxseg8ei8.v v4,\(a0\),v12'
++.*: Error: unrecognized opcode `vloxseg8ei8.v v4,0\(a0\),v12'
++.*: Error: unrecognized opcode `vloxseg8ei8.v v4,\(a0\),v12,v0.t'
++.*: Error: unrecognized opcode `vsoxseg8ei8.v v4,\(a0\),v12'
++.*: Error: unrecognized opcode `vsoxseg8ei8.v v4,0\(a0\),v12'
++.*: Error: unrecognized opcode `vsoxseg8ei8.v v4,\(a0\),v12,v0.t'
++.*: Error: unrecognized opcode `vloxseg2ei16.v v4,\(a0\),v12'
++.*: Error: unrecognized opcode `vloxseg2ei16.v v4,0\(a0\),v12'
++.*: Error: unrecognized opcode `vloxseg2ei16.v v4,\(a0\),v12,v0.t'
++.*: Error: unrecognized opcode `vsoxseg2ei16.v v4,\(a0\),v12'
++.*: Error: unrecognized opcode `vsoxseg2ei16.v v4,0\(a0\),v12'
++.*: Error: unrecognized opcode `vsoxseg2ei16.v v4,\(a0\),v12,v0.t'
++.*: Error: unrecognized opcode `vloxseg3ei16.v v4,\(a0\),v12'
++.*: Error: unrecognized opcode `vloxseg3ei16.v v4,0\(a0\),v12'
++.*: Error: unrecognized opcode `vloxseg3ei16.v v4,\(a0\),v12,v0.t'
++.*: Error: unrecognized opcode `vsoxseg3ei16.v v4,\(a0\),v12'
++.*: Error: unrecognized opcode `vsoxseg3ei16.v v4,0\(a0\),v12'
++.*: Error: unrecognized opcode `vsoxseg3ei16.v v4,\(a0\),v12,v0.t'
++.*: Error: unrecognized opcode `vloxseg4ei16.v v4,\(a0\),v12'
++.*: Error: unrecognized opcode `vloxseg4ei16.v v4,0\(a0\),v12'
++.*: Error: unrecognized opcode `vloxseg4ei16.v v4,\(a0\),v12,v0.t'
++.*: Error: unrecognized opcode `vsoxseg4ei16.v v4,\(a0\),v12'
++.*: Error: unrecognized opcode `vsoxseg4ei16.v v4,0\(a0\),v12'
++.*: Error: unrecognized opcode `vsoxseg4ei16.v v4,\(a0\),v12,v0.t'
++.*: Error: unrecognized opcode `vloxseg5ei16.v v4,\(a0\),v12'
++.*: Error: unrecognized opcode `vloxseg5ei16.v v4,0\(a0\),v12'
++.*: Error: unrecognized opcode `vloxseg5ei16.v v4,\(a0\),v12,v0.t'
++.*: Error: unrecognized opcode `vsoxseg5ei16.v v4,\(a0\),v12'
++.*: Error: unrecognized opcode `vsoxseg5ei16.v v4,0\(a0\),v12'
++.*: Error: unrecognized opcode `vsoxseg5ei16.v v4,\(a0\),v12,v0.t'
++.*: Error: unrecognized opcode `vloxseg6ei16.v v4,\(a0\),v12'
++.*: Error: unrecognized opcode `vloxseg6ei16.v v4,0\(a0\),v12'
++.*: Error: unrecognized opcode `vloxseg6ei16.v v4,\(a0\),v12,v0.t'
++.*: Error: unrecognized opcode `vsoxseg6ei16.v v4,\(a0\),v12'
++.*: Error: unrecognized opcode `vsoxseg6ei16.v v4,0\(a0\),v12'
++.*: Error: unrecognized opcode `vsoxseg6ei16.v v4,\(a0\),v12,v0.t'
++.*: Error: unrecognized opcode `vloxseg7ei16.v v4,\(a0\),v12'
++.*: Error: unrecognized opcode `vloxseg7ei16.v v4,0\(a0\),v12'
++.*: Error: unrecognized opcode `vloxseg7ei16.v v4,\(a0\),v12,v0.t'
++.*: Error: unrecognized opcode `vsoxseg7ei16.v v4,\(a0\),v12'
++.*: Error: unrecognized opcode `vsoxseg7ei16.v v4,0\(a0\),v12'
++.*: Error: unrecognized opcode `vsoxseg7ei16.v v4,\(a0\),v12,v0.t'
++.*: Error: unrecognized opcode `vloxseg8ei16.v v4,\(a0\),v12'
++.*: Error: unrecognized opcode `vloxseg8ei16.v v4,0\(a0\),v12'
++.*: Error: unrecognized opcode `vloxseg8ei16.v v4,\(a0\),v12,v0.t'
++.*: Error: unrecognized opcode `vsoxseg8ei16.v v4,\(a0\),v12'
++.*: Error: unrecognized opcode `vsoxseg8ei16.v v4,0\(a0\),v12'
++.*: Error: unrecognized opcode `vsoxseg8ei16.v v4,\(a0\),v12,v0.t'
++.*: Error: unrecognized opcode `vloxseg2ei32.v v4,\(a0\),v12'
++.*: Error: unrecognized opcode `vloxseg2ei32.v v4,0\(a0\),v12'
++.*: Error: unrecognized opcode `vloxseg2ei32.v v4,\(a0\),v12,v0.t'
++.*: Error: unrecognized opcode `vsoxseg2ei32.v v4,\(a0\),v12'
++.*: Error: unrecognized opcode `vsoxseg2ei32.v v4,0\(a0\),v12'
++.*: Error: unrecognized opcode `vsoxseg2ei32.v v4,\(a0\),v12,v0.t'
++.*: Error: unrecognized opcode `vloxseg3ei32.v v4,\(a0\),v12'
++.*: Error: unrecognized opcode `vloxseg3ei32.v v4,0\(a0\),v12'
++.*: Error: unrecognized opcode `vloxseg3ei32.v v4,\(a0\),v12,v0.t'
++.*: Error: unrecognized opcode `vsoxseg3ei32.v v4,\(a0\),v12'
++.*: Error: unrecognized opcode `vsoxseg3ei32.v v4,0\(a0\),v12'
++.*: Error: unrecognized opcode `vsoxseg3ei32.v v4,\(a0\),v12,v0.t'
++.*: Error: unrecognized opcode `vloxseg4ei32.v v4,\(a0\),v12'
++.*: Error: unrecognized opcode `vloxseg4ei32.v v4,0\(a0\),v12'
++.*: Error: unrecognized opcode `vloxseg4ei32.v v4,\(a0\),v12,v0.t'
++.*: Error: unrecognized opcode `vsoxseg4ei32.v v4,\(a0\),v12'
++.*: Error: unrecognized opcode `vsoxseg4ei32.v v4,0\(a0\),v12'
++.*: Error: unrecognized opcode `vsoxseg4ei32.v v4,\(a0\),v12,v0.t'
++.*: Error: unrecognized opcode `vloxseg5ei32.v v4,\(a0\),v12'
++.*: Error: unrecognized opcode `vloxseg5ei32.v v4,0\(a0\),v12'
++.*: Error: unrecognized opcode `vloxseg5ei32.v v4,\(a0\),v12,v0.t'
++.*: Error: unrecognized opcode `vsoxseg5ei32.v v4,\(a0\),v12'
++.*: Error: unrecognized opcode `vsoxseg5ei32.v v4,0\(a0\),v12'
++.*: Error: unrecognized opcode `vsoxseg5ei32.v v4,\(a0\),v12,v0.t'
++.*: Error: unrecognized opcode `vloxseg6ei32.v v4,\(a0\),v12'
++.*: Error: unrecognized opcode `vloxseg6ei32.v v4,0\(a0\),v12'
++.*: Error: unrecognized opcode `vloxseg6ei32.v v4,\(a0\),v12,v0.t'
++.*: Error: unrecognized opcode `vsoxseg6ei32.v v4,\(a0\),v12'
++.*: Error: unrecognized opcode `vsoxseg6ei32.v v4,0\(a0\),v12'
++.*: Error: unrecognized opcode `vsoxseg6ei32.v v4,\(a0\),v12,v0.t'
++.*: Error: unrecognized opcode `vloxseg7ei32.v v4,\(a0\),v12'
++.*: Error: unrecognized opcode `vloxseg7ei32.v v4,0\(a0\),v12'
++.*: Error: unrecognized opcode `vloxseg7ei32.v v4,\(a0\),v12,v0.t'
++.*: Error: unrecognized opcode `vsoxseg7ei32.v v4,\(a0\),v12'
++.*: Error: unrecognized opcode `vsoxseg7ei32.v v4,0\(a0\),v12'
++.*: Error: unrecognized opcode `vsoxseg7ei32.v v4,\(a0\),v12,v0.t'
++.*: Error: unrecognized opcode `vloxseg8ei32.v v4,\(a0\),v12'
++.*: Error: unrecognized opcode `vloxseg8ei32.v v4,0\(a0\),v12'
++.*: Error: unrecognized opcode `vloxseg8ei32.v v4,\(a0\),v12,v0.t'
++.*: Error: unrecognized opcode `vsoxseg8ei32.v v4,\(a0\),v12'
++.*: Error: unrecognized opcode `vsoxseg8ei32.v v4,0\(a0\),v12'
++.*: Error: unrecognized opcode `vsoxseg8ei32.v v4,\(a0\),v12,v0.t'
++.*: Error: unrecognized opcode `vloxseg2ei64.v v4,\(a0\),v12'
++.*: Error: unrecognized opcode `vloxseg2ei64.v v4,0\(a0\),v12'
++.*: Error: unrecognized opcode `vloxseg2ei64.v v4,\(a0\),v12,v0.t'
++.*: Error: unrecognized opcode `vsoxseg2ei64.v v4,\(a0\),v12'
++.*: Error: unrecognized opcode `vsoxseg2ei64.v v4,0\(a0\),v12'
++.*: Error: unrecognized opcode `vsoxseg2ei64.v v4,\(a0\),v12,v0.t'
++.*: Error: unrecognized opcode `vloxseg3ei64.v v4,\(a0\),v12'
++.*: Error: unrecognized opcode `vloxseg3ei64.v v4,0\(a0\),v12'
++.*: Error: unrecognized opcode `vloxseg3ei64.v v4,\(a0\),v12,v0.t'
++.*: Error: unrecognized opcode `vsoxseg3ei64.v v4,\(a0\),v12'
++.*: Error: unrecognized opcode `vsoxseg3ei64.v v4,0\(a0\),v12'
++.*: Error: unrecognized opcode `vsoxseg3ei64.v v4,\(a0\),v12,v0.t'
++.*: Error: unrecognized opcode `vloxseg4ei64.v v4,\(a0\),v12'
++.*: Error: unrecognized opcode `vloxseg4ei64.v v4,0\(a0\),v12'
++.*: Error: unrecognized opcode `vloxseg4ei64.v v4,\(a0\),v12,v0.t'
++.*: Error: unrecognized opcode `vsoxseg4ei64.v v4,\(a0\),v12'
++.*: Error: unrecognized opcode `vsoxseg4ei64.v v4,0\(a0\),v12'
++.*: Error: unrecognized opcode `vsoxseg4ei64.v v4,\(a0\),v12,v0.t'
++.*: Error: unrecognized opcode `vloxseg5ei64.v v4,\(a0\),v12'
++.*: Error: unrecognized opcode `vloxseg5ei64.v v4,0\(a0\),v12'
++.*: Error: unrecognized opcode `vloxseg5ei64.v v4,\(a0\),v12,v0.t'
++.*: Error: unrecognized opcode `vsoxseg5ei64.v v4,\(a0\),v12'
++.*: Error: unrecognized opcode `vsoxseg5ei64.v v4,0\(a0\),v12'
++.*: Error: unrecognized opcode `vsoxseg5ei64.v v4,\(a0\),v12,v0.t'
++.*: Error: unrecognized opcode `vloxseg6ei64.v v4,\(a0\),v12'
++.*: Error: unrecognized opcode `vloxseg6ei64.v v4,0\(a0\),v12'
++.*: Error: unrecognized opcode `vloxseg6ei64.v v4,\(a0\),v12,v0.t'
++.*: Error: unrecognized opcode `vsoxseg6ei64.v v4,\(a0\),v12'
++.*: Error: unrecognized opcode `vsoxseg6ei64.v v4,0\(a0\),v12'
++.*: Error: unrecognized opcode `vsoxseg6ei64.v v4,\(a0\),v12,v0.t'
++.*: Error: unrecognized opcode `vloxseg7ei64.v v4,\(a0\),v12'
++.*: Error: unrecognized opcode `vloxseg7ei64.v v4,0\(a0\),v12'
++.*: Error: unrecognized opcode `vloxseg7ei64.v v4,\(a0\),v12,v0.t'
++.*: Error: unrecognized opcode `vsoxseg7ei64.v v4,\(a0\),v12'
++.*: Error: unrecognized opcode `vsoxseg7ei64.v v4,0\(a0\),v12'
++.*: Error: unrecognized opcode `vsoxseg7ei64.v v4,\(a0\),v12,v0.t'
++.*: Error: unrecognized opcode `vloxseg8ei64.v v4,\(a0\),v12'
++.*: Error: unrecognized opcode `vloxseg8ei64.v v4,0\(a0\),v12'
++.*: Error: unrecognized opcode `vloxseg8ei64.v v4,\(a0\),v12,v0.t'
++.*: Error: unrecognized opcode `vsoxseg8ei64.v v4,\(a0\),v12'
++.*: Error: unrecognized opcode `vsoxseg8ei64.v v4,0\(a0\),v12'
++.*: Error: unrecognized opcode `vsoxseg8ei64.v v4,\(a0\),v12,v0.t'
++.*: Error: unrecognized opcode `vluxseg2ei8.v v4,\(a0\),v12'
++.*: Error: unrecognized opcode `vluxseg2ei8.v v4,0\(a0\),v12'
++.*: Error: unrecognized opcode `vluxseg2ei8.v v4,\(a0\),v12,v0.t'
++.*: Error: unrecognized opcode `vsuxseg2ei8.v v4,\(a0\),v12'
++.*: Error: unrecognized opcode `vsuxseg2ei8.v v4,0\(a0\),v12'
++.*: Error: unrecognized opcode `vsuxseg2ei8.v v4,\(a0\),v12,v0.t'
++.*: Error: unrecognized opcode `vluxseg3ei8.v v4,\(a0\),v12'
++.*: Error: unrecognized opcode `vluxseg3ei8.v v4,0\(a0\),v12'
++.*: Error: unrecognized opcode `vluxseg3ei8.v v4,\(a0\),v12,v0.t'
++.*: Error: unrecognized opcode `vsuxseg3ei8.v v4,\(a0\),v12'
++.*: Error: unrecognized opcode `vsuxseg3ei8.v v4,0\(a0\),v12'
++.*: Error: unrecognized opcode `vsuxseg3ei8.v v4,\(a0\),v12,v0.t'
++.*: Error: unrecognized opcode `vluxseg4ei8.v v4,\(a0\),v12'
++.*: Error: unrecognized opcode `vluxseg4ei8.v v4,0\(a0\),v12'
++.*: Error: unrecognized opcode `vluxseg4ei8.v v4,\(a0\),v12,v0.t'
++.*: Error: unrecognized opcode `vsuxseg4ei8.v v4,\(a0\),v12'
++.*: Error: unrecognized opcode `vsuxseg4ei8.v v4,0\(a0\),v12'
++.*: Error: unrecognized opcode `vsuxseg4ei8.v v4,\(a0\),v12,v0.t'
++.*: Error: unrecognized opcode `vluxseg5ei8.v v4,\(a0\),v12'
++.*: Error: unrecognized opcode `vluxseg5ei8.v v4,0\(a0\),v12'
++.*: Error: unrecognized opcode `vluxseg5ei8.v v4,\(a0\),v12,v0.t'
++.*: Error: unrecognized opcode `vsuxseg5ei8.v v4,\(a0\),v12'
++.*: Error: unrecognized opcode `vsuxseg5ei8.v v4,0\(a0\),v12'
++.*: Error: unrecognized opcode `vsuxseg5ei8.v v4,\(a0\),v12,v0.t'
++.*: Error: unrecognized opcode `vluxseg6ei8.v v4,\(a0\),v12'
++.*: Error: unrecognized opcode `vluxseg6ei8.v v4,0\(a0\),v12'
++.*: Error: unrecognized opcode `vluxseg6ei8.v v4,\(a0\),v12,v0.t'
++.*: Error: unrecognized opcode `vsuxseg6ei8.v v4,\(a0\),v12'
++.*: Error: unrecognized opcode `vsuxseg6ei8.v v4,0\(a0\),v12'
++.*: Error: unrecognized opcode `vsuxseg6ei8.v v4,\(a0\),v12,v0.t'
++.*: Error: unrecognized opcode `vluxseg7ei8.v v4,\(a0\),v12'
++.*: Error: unrecognized opcode `vluxseg7ei8.v v4,0\(a0\),v12'
++.*: Error: unrecognized opcode `vluxseg7ei8.v v4,\(a0\),v12,v0.t'
++.*: Error: unrecognized opcode `vsuxseg7ei8.v v4,\(a0\),v12'
++.*: Error: unrecognized opcode `vsuxseg7ei8.v v4,0\(a0\),v12'
++.*: Error: unrecognized opcode `vsuxseg7ei8.v v4,\(a0\),v12,v0.t'
++.*: Error: unrecognized opcode `vluxseg8ei8.v v4,\(a0\),v12'
++.*: Error: unrecognized opcode `vluxseg8ei8.v v4,0\(a0\),v12'
++.*: Error: unrecognized opcode `vluxseg8ei8.v v4,\(a0\),v12,v0.t'
++.*: Error: unrecognized opcode `vsuxseg8ei8.v v4,\(a0\),v12'
++.*: Error: unrecognized opcode `vsuxseg8ei8.v v4,0\(a0\),v12'
++.*: Error: unrecognized opcode `vsuxseg8ei8.v v4,\(a0\),v12,v0.t'
++.*: Error: unrecognized opcode `vluxseg2ei16.v v4,\(a0\),v12'
++.*: Error: unrecognized opcode `vluxseg2ei16.v v4,0\(a0\),v12'
++.*: Error: unrecognized opcode `vluxseg2ei16.v v4,\(a0\),v12,v0.t'
++.*: Error: unrecognized opcode `vsuxseg2ei16.v v4,\(a0\),v12'
++.*: Error: unrecognized opcode `vsuxseg2ei16.v v4,0\(a0\),v12'
++.*: Error: unrecognized opcode `vsuxseg2ei16.v v4,\(a0\),v12,v0.t'
++.*: Error: unrecognized opcode `vluxseg3ei16.v v4,\(a0\),v12'
++.*: Error: unrecognized opcode `vluxseg3ei16.v v4,0\(a0\),v12'
++.*: Error: unrecognized opcode `vluxseg3ei16.v v4,\(a0\),v12,v0.t'
++.*: Error: unrecognized opcode `vsuxseg3ei16.v v4,\(a0\),v12'
++.*: Error: unrecognized opcode `vsuxseg3ei16.v v4,0\(a0\),v12'
++.*: Error: unrecognized opcode `vsuxseg3ei16.v v4,\(a0\),v12,v0.t'
++.*: Error: unrecognized opcode `vluxseg4ei16.v v4,\(a0\),v12'
++.*: Error: unrecognized opcode `vluxseg4ei16.v v4,0\(a0\),v12'
++.*: Error: unrecognized opcode `vluxseg4ei16.v v4,\(a0\),v12,v0.t'
++.*: Error: unrecognized opcode `vsuxseg4ei16.v v4,\(a0\),v12'
++.*: Error: unrecognized opcode `vsuxseg4ei16.v v4,0\(a0\),v12'
++.*: Error: unrecognized opcode `vsuxseg4ei16.v v4,\(a0\),v12,v0.t'
++.*: Error: unrecognized opcode `vluxseg5ei16.v v4,\(a0\),v12'
++.*: Error: unrecognized opcode `vluxseg5ei16.v v4,0\(a0\),v12'
++.*: Error: unrecognized opcode `vluxseg5ei16.v v4,\(a0\),v12,v0.t'
++.*: Error: unrecognized opcode `vsuxseg5ei16.v v4,\(a0\),v12'
++.*: Error: unrecognized opcode `vsuxseg5ei16.v v4,0\(a0\),v12'
++.*: Error: unrecognized opcode `vsuxseg5ei16.v v4,\(a0\),v12,v0.t'
++.*: Error: unrecognized opcode `vluxseg6ei16.v v4,\(a0\),v12'
++.*: Error: unrecognized opcode `vluxseg6ei16.v v4,0\(a0\),v12'
++.*: Error: unrecognized opcode `vluxseg6ei16.v v4,\(a0\),v12,v0.t'
++.*: Error: unrecognized opcode `vsuxseg6ei16.v v4,\(a0\),v12'
++.*: Error: unrecognized opcode `vsuxseg6ei16.v v4,0\(a0\),v12'
++.*: Error: unrecognized opcode `vsuxseg6ei16.v v4,\(a0\),v12,v0.t'
++.*: Error: unrecognized opcode `vluxseg7ei16.v v4,\(a0\),v12'
++.*: Error: unrecognized opcode `vluxseg7ei16.v v4,0\(a0\),v12'
++.*: Error: unrecognized opcode `vluxseg7ei16.v v4,\(a0\),v12,v0.t'
++.*: Error: unrecognized opcode `vsuxseg7ei16.v v4,\(a0\),v12'
++.*: Error: unrecognized opcode `vsuxseg7ei16.v v4,0\(a0\),v12'
++.*: Error: unrecognized opcode `vsuxseg7ei16.v v4,\(a0\),v12,v0.t'
++.*: Error: unrecognized opcode `vluxseg8ei16.v v4,\(a0\),v12'
++.*: Error: unrecognized opcode `vluxseg8ei16.v v4,0\(a0\),v12'
++.*: Error: unrecognized opcode `vluxseg8ei16.v v4,\(a0\),v12,v0.t'
++.*: Error: unrecognized opcode `vsuxseg8ei16.v v4,\(a0\),v12'
++.*: Error: unrecognized opcode `vsuxseg8ei16.v v4,0\(a0\),v12'
++.*: Error: unrecognized opcode `vsuxseg8ei16.v v4,\(a0\),v12,v0.t'
++.*: Error: unrecognized opcode `vluxseg2ei32.v v4,\(a0\),v12'
++.*: Error: unrecognized opcode `vluxseg2ei32.v v4,0\(a0\),v12'
++.*: Error: unrecognized opcode `vluxseg2ei32.v v4,\(a0\),v12,v0.t'
++.*: Error: unrecognized opcode `vsuxseg2ei32.v v4,\(a0\),v12'
++.*: Error: unrecognized opcode `vsuxseg2ei32.v v4,0\(a0\),v12'
++.*: Error: unrecognized opcode `vsuxseg2ei32.v v4,\(a0\),v12,v0.t'
++.*: Error: unrecognized opcode `vluxseg3ei32.v v4,\(a0\),v12'
++.*: Error: unrecognized opcode `vluxseg3ei32.v v4,0\(a0\),v12'
++.*: Error: unrecognized opcode `vluxseg3ei32.v v4,\(a0\),v12,v0.t'
++.*: Error: unrecognized opcode `vsuxseg3ei32.v v4,\(a0\),v12'
++.*: Error: unrecognized opcode `vsuxseg3ei32.v v4,0\(a0\),v12'
++.*: Error: unrecognized opcode `vsuxseg3ei32.v v4,\(a0\),v12,v0.t'
++.*: Error: unrecognized opcode `vluxseg4ei32.v v4,\(a0\),v12'
++.*: Error: unrecognized opcode `vluxseg4ei32.v v4,0\(a0\),v12'
++.*: Error: unrecognized opcode `vluxseg4ei32.v v4,\(a0\),v12,v0.t'
++.*: Error: unrecognized opcode `vsuxseg4ei32.v v4,\(a0\),v12'
++.*: Error: unrecognized opcode `vsuxseg4ei32.v v4,0\(a0\),v12'
++.*: Error: unrecognized opcode `vsuxseg4ei32.v v4,\(a0\),v12,v0.t'
++.*: Error: unrecognized opcode `vluxseg5ei32.v v4,\(a0\),v12'
++.*: Error: unrecognized opcode `vluxseg5ei32.v v4,0\(a0\),v12'
++.*: Error: unrecognized opcode `vluxseg5ei32.v v4,\(a0\),v12,v0.t'
++.*: Error: unrecognized opcode `vsuxseg5ei32.v v4,\(a0\),v12'
++.*: Error: unrecognized opcode `vsuxseg5ei32.v v4,0\(a0\),v12'
++.*: Error: unrecognized opcode `vsuxseg5ei32.v v4,\(a0\),v12,v0.t'
++.*: Error: unrecognized opcode `vluxseg6ei32.v v4,\(a0\),v12'
++.*: Error: unrecognized opcode `vluxseg6ei32.v v4,0\(a0\),v12'
++.*: Error: unrecognized opcode `vluxseg6ei32.v v4,\(a0\),v12,v0.t'
++.*: Error: unrecognized opcode `vsuxseg6ei32.v v4,\(a0\),v12'
++.*: Error: unrecognized opcode `vsuxseg6ei32.v v4,0\(a0\),v12'
++.*: Error: unrecognized opcode `vsuxseg6ei32.v v4,\(a0\),v12,v0.t'
++.*: Error: unrecognized opcode `vluxseg7ei32.v v4,\(a0\),v12'
++.*: Error: unrecognized opcode `vluxseg7ei32.v v4,0\(a0\),v12'
++.*: Error: unrecognized opcode `vluxseg7ei32.v v4,\(a0\),v12,v0.t'
++.*: Error: unrecognized opcode `vsuxseg7ei32.v v4,\(a0\),v12'
++.*: Error: unrecognized opcode `vsuxseg7ei32.v v4,0\(a0\),v12'
++.*: Error: unrecognized opcode `vsuxseg7ei32.v v4,\(a0\),v12,v0.t'
++.*: Error: unrecognized opcode `vluxseg8ei32.v v4,\(a0\),v12'
++.*: Error: unrecognized opcode `vluxseg8ei32.v v4,0\(a0\),v12'
++.*: Error: unrecognized opcode `vluxseg8ei32.v v4,\(a0\),v12,v0.t'
++.*: Error: unrecognized opcode `vsuxseg8ei32.v v4,\(a0\),v12'
++.*: Error: unrecognized opcode `vsuxseg8ei32.v v4,0\(a0\),v12'
++.*: Error: unrecognized opcode `vsuxseg8ei32.v v4,\(a0\),v12,v0.t'
++.*: Error: unrecognized opcode `vluxseg2ei64.v v4,\(a0\),v12'
++.*: Error: unrecognized opcode `vluxseg2ei64.v v4,0\(a0\),v12'
++.*: Error: unrecognized opcode `vluxseg2ei64.v v4,\(a0\),v12,v0.t'
++.*: Error: unrecognized opcode `vsuxseg2ei64.v v4,\(a0\),v12'
++.*: Error: unrecognized opcode `vsuxseg2ei64.v v4,0\(a0\),v12'
++.*: Error: unrecognized opcode `vsuxseg2ei64.v v4,\(a0\),v12,v0.t'
++.*: Error: unrecognized opcode `vluxseg3ei64.v v4,\(a0\),v12'
++.*: Error: unrecognized opcode `vluxseg3ei64.v v4,0\(a0\),v12'
++.*: Error: unrecognized opcode `vluxseg3ei64.v v4,\(a0\),v12,v0.t'
++.*: Error: unrecognized opcode `vsuxseg3ei64.v v4,\(a0\),v12'
++.*: Error: unrecognized opcode `vsuxseg3ei64.v v4,0\(a0\),v12'
++.*: Error: unrecognized opcode `vsuxseg3ei64.v v4,\(a0\),v12,v0.t'
++.*: Error: unrecognized opcode `vluxseg4ei64.v v4,\(a0\),v12'
++.*: Error: unrecognized opcode `vluxseg4ei64.v v4,0\(a0\),v12'
++.*: Error: unrecognized opcode `vluxseg4ei64.v v4,\(a0\),v12,v0.t'
++.*: Error: unrecognized opcode `vsuxseg4ei64.v v4,\(a0\),v12'
++.*: Error: unrecognized opcode `vsuxseg4ei64.v v4,0\(a0\),v12'
++.*: Error: unrecognized opcode `vsuxseg4ei64.v v4,\(a0\),v12,v0.t'
++.*: Error: unrecognized opcode `vluxseg5ei64.v v4,\(a0\),v12'
++.*: Error: unrecognized opcode `vluxseg5ei64.v v4,0\(a0\),v12'
++.*: Error: unrecognized opcode `vluxseg5ei64.v v4,\(a0\),v12,v0.t'
++.*: Error: unrecognized opcode `vsuxseg5ei64.v v4,\(a0\),v12'
++.*: Error: unrecognized opcode `vsuxseg5ei64.v v4,0\(a0\),v12'
++.*: Error: unrecognized opcode `vsuxseg5ei64.v v4,\(a0\),v12,v0.t'
++.*: Error: unrecognized opcode `vluxseg6ei64.v v4,\(a0\),v12'
++.*: Error: unrecognized opcode `vluxseg6ei64.v v4,0\(a0\),v12'
++.*: Error: unrecognized opcode `vluxseg6ei64.v v4,\(a0\),v12,v0.t'
++.*: Error: unrecognized opcode `vsuxseg6ei64.v v4,\(a0\),v12'
++.*: Error: unrecognized opcode `vsuxseg6ei64.v v4,0\(a0\),v12'
++.*: Error: unrecognized opcode `vsuxseg6ei64.v v4,\(a0\),v12,v0.t'
++.*: Error: unrecognized opcode `vluxseg7ei64.v v4,\(a0\),v12'
++.*: Error: unrecognized opcode `vluxseg7ei64.v v4,0\(a0\),v12'
++.*: Error: unrecognized opcode `vluxseg7ei64.v v4,\(a0\),v12,v0.t'
++.*: Error: unrecognized opcode `vsuxseg7ei64.v v4,\(a0\),v12'
++.*: Error: unrecognized opcode `vsuxseg7ei64.v v4,0\(a0\),v12'
++.*: Error: unrecognized opcode `vsuxseg7ei64.v v4,\(a0\),v12,v0.t'
++.*: Error: unrecognized opcode `vluxseg8ei64.v v4,\(a0\),v12'
++.*: Error: unrecognized opcode `vluxseg8ei64.v v4,0\(a0\),v12'
++.*: Error: unrecognized opcode `vluxseg8ei64.v v4,\(a0\),v12,v0.t'
++.*: Error: unrecognized opcode `vsuxseg8ei64.v v4,\(a0\),v12'
++.*: Error: unrecognized opcode `vsuxseg8ei64.v v4,0\(a0\),v12'
++.*: Error: unrecognized opcode `vsuxseg8ei64.v v4,\(a0\),v12,v0.t'
++.*: Error: unrecognized opcode `vlseg2e8ff.v v4,\(a0\)'
++.*: Error: unrecognized opcode `vlseg2e8ff.v v4,0\(a0\)'
++.*: Error: unrecognized opcode `vlseg2e8ff.v v4,\(a0\),v0.t'
++.*: Error: unrecognized opcode `vlseg3e8ff.v v4,\(a0\)'
++.*: Error: unrecognized opcode `vlseg3e8ff.v v4,0\(a0\)'
++.*: Error: unrecognized opcode `vlseg3e8ff.v v4,\(a0\),v0.t'
++.*: Error: unrecognized opcode `vlseg4e8ff.v v4,\(a0\)'
++.*: Error: unrecognized opcode `vlseg4e8ff.v v4,0\(a0\)'
++.*: Error: unrecognized opcode `vlseg4e8ff.v v4,\(a0\),v0.t'
++.*: Error: unrecognized opcode `vlseg5e8ff.v v4,\(a0\)'
++.*: Error: unrecognized opcode `vlseg5e8ff.v v4,0\(a0\)'
++.*: Error: unrecognized opcode `vlseg5e8ff.v v4,\(a0\),v0.t'
++.*: Error: unrecognized opcode `vlseg6e8ff.v v4,\(a0\)'
++.*: Error: unrecognized opcode `vlseg6e8ff.v v4,0\(a0\)'
++.*: Error: unrecognized opcode `vlseg6e8ff.v v4,\(a0\),v0.t'
++.*: Error: unrecognized opcode `vlseg7e8ff.v v4,\(a0\)'
++.*: Error: unrecognized opcode `vlseg7e8ff.v v4,0\(a0\)'
++.*: Error: unrecognized opcode `vlseg7e8ff.v v4,\(a0\),v0.t'
++.*: Error: unrecognized opcode `vlseg8e8ff.v v4,\(a0\)'
++.*: Error: unrecognized opcode `vlseg8e8ff.v v4,0\(a0\)'
++.*: Error: unrecognized opcode `vlseg8e8ff.v v4,\(a0\),v0.t'
++.*: Error: unrecognized opcode `vlseg2e16ff.v v4,\(a0\)'
++.*: Error: unrecognized opcode `vlseg2e16ff.v v4,0\(a0\)'
++.*: Error: unrecognized opcode `vlseg2e16ff.v v4,\(a0\),v0.t'
++.*: Error: unrecognized opcode `vlseg3e16ff.v v4,\(a0\)'
++.*: Error: unrecognized opcode `vlseg3e16ff.v v4,0\(a0\)'
++.*: Error: unrecognized opcode `vlseg3e16ff.v v4,\(a0\),v0.t'
++.*: Error: unrecognized opcode `vlseg4e16ff.v v4,\(a0\)'
++.*: Error: unrecognized opcode `vlseg4e16ff.v v4,0\(a0\)'
++.*: Error: unrecognized opcode `vlseg4e16ff.v v4,\(a0\),v0.t'
++.*: Error: unrecognized opcode `vlseg5e16ff.v v4,\(a0\)'
++.*: Error: unrecognized opcode `vlseg5e16ff.v v4,0\(a0\)'
++.*: Error: unrecognized opcode `vlseg5e16ff.v v4,\(a0\),v0.t'
++.*: Error: unrecognized opcode `vlseg6e16ff.v v4,\(a0\)'
++.*: Error: unrecognized opcode `vlseg6e16ff.v v4,0\(a0\)'
++.*: Error: unrecognized opcode `vlseg6e16ff.v v4,\(a0\),v0.t'
++.*: Error: unrecognized opcode `vlseg7e16ff.v v4,\(a0\)'
++.*: Error: unrecognized opcode `vlseg7e16ff.v v4,0\(a0\)'
++.*: Error: unrecognized opcode `vlseg7e16ff.v v4,\(a0\),v0.t'
++.*: Error: unrecognized opcode `vlseg8e16ff.v v4,\(a0\)'
++.*: Error: unrecognized opcode `vlseg8e16ff.v v4,0\(a0\)'
++.*: Error: unrecognized opcode `vlseg8e16ff.v v4,\(a0\),v0.t'
++.*: Error: unrecognized opcode `vlseg2e32ff.v v4,\(a0\)'
++.*: Error: unrecognized opcode `vlseg2e32ff.v v4,0\(a0\)'
++.*: Error: unrecognized opcode `vlseg2e32ff.v v4,\(a0\),v0.t'
++.*: Error: unrecognized opcode `vlseg3e32ff.v v4,\(a0\)'
++.*: Error: unrecognized opcode `vlseg3e32ff.v v4,0\(a0\)'
++.*: Error: unrecognized opcode `vlseg3e32ff.v v4,\(a0\),v0.t'
++.*: Error: unrecognized opcode `vlseg4e32ff.v v4,\(a0\)'
++.*: Error: unrecognized opcode `vlseg4e32ff.v v4,0\(a0\)'
++.*: Error: unrecognized opcode `vlseg4e32ff.v v4,\(a0\),v0.t'
++.*: Error: unrecognized opcode `vlseg5e32ff.v v4,\(a0\)'
++.*: Error: unrecognized opcode `vlseg5e32ff.v v4,0\(a0\)'
++.*: Error: unrecognized opcode `vlseg5e32ff.v v4,\(a0\),v0.t'
++.*: Error: unrecognized opcode `vlseg6e32ff.v v4,\(a0\)'
++.*: Error: unrecognized opcode `vlseg6e32ff.v v4,0\(a0\)'
++.*: Error: unrecognized opcode `vlseg6e32ff.v v4,\(a0\),v0.t'
++.*: Error: unrecognized opcode `vlseg7e32ff.v v4,\(a0\)'
++.*: Error: unrecognized opcode `vlseg7e32ff.v v4,0\(a0\)'
++.*: Error: unrecognized opcode `vlseg7e32ff.v v4,\(a0\),v0.t'
++.*: Error: unrecognized opcode `vlseg8e32ff.v v4,\(a0\)'
++.*: Error: unrecognized opcode `vlseg8e32ff.v v4,0\(a0\)'
++.*: Error: unrecognized opcode `vlseg8e32ff.v v4,\(a0\),v0.t'
++.*: Error: unrecognized opcode `vlseg2e64ff.v v4,\(a0\)'
++.*: Error: unrecognized opcode `vlseg2e64ff.v v4,0\(a0\)'
++.*: Error: unrecognized opcode `vlseg2e64ff.v v4,\(a0\),v0.t'
++.*: Error: unrecognized opcode `vlseg3e64ff.v v4,\(a0\)'
++.*: Error: unrecognized opcode `vlseg3e64ff.v v4,0\(a0\)'
++.*: Error: unrecognized opcode `vlseg3e64ff.v v4,\(a0\),v0.t'
++.*: Error: unrecognized opcode `vlseg4e64ff.v v4,\(a0\)'
++.*: Error: unrecognized opcode `vlseg4e64ff.v v4,0\(a0\)'
++.*: Error: unrecognized opcode `vlseg4e64ff.v v4,\(a0\),v0.t'
++.*: Error: unrecognized opcode `vlseg5e64ff.v v4,\(a0\)'
++.*: Error: unrecognized opcode `vlseg5e64ff.v v4,0\(a0\)'
++.*: Error: unrecognized opcode `vlseg5e64ff.v v4,\(a0\),v0.t'
++.*: Error: unrecognized opcode `vlseg6e64ff.v v4,\(a0\)'
++.*: Error: unrecognized opcode `vlseg6e64ff.v v4,0\(a0\)'
++.*: Error: unrecognized opcode `vlseg6e64ff.v v4,\(a0\),v0.t'
++.*: Error: unrecognized opcode `vlseg7e64ff.v v4,\(a0\)'
++.*: Error: unrecognized opcode `vlseg7e64ff.v v4,0\(a0\)'
++.*: Error: unrecognized opcode `vlseg7e64ff.v v4,\(a0\),v0.t'
++.*: Error: unrecognized opcode `vlseg8e64ff.v v4,\(a0\)'
++.*: Error: unrecognized opcode `vlseg8e64ff.v v4,0\(a0\)'
++.*: Error: unrecognized opcode `vlseg8e64ff.v v4,\(a0\),v0.t'
++.*: Error: unrecognized opcode `vl1r.v v3,\(a0\)'
++.*: Error: unrecognized opcode `vl1r.v v3,0\(a0\)'
++.*: Error: unrecognized opcode `vl1re8.v v3,\(a0\)'
++.*: Error: unrecognized opcode `vl1re8.v v3,0\(a0\)'
++.*: Error: unrecognized opcode `vl1re16.v v3,\(a0\)'
++.*: Error: unrecognized opcode `vl1re16.v v3,0\(a0\)'
++.*: Error: unrecognized opcode `vl1re32.v v3,\(a0\)'
++.*: Error: unrecognized opcode `vl1re32.v v3,0\(a0\)'
++.*: Error: unrecognized opcode `vl1re64.v v3,\(a0\)'
++.*: Error: unrecognized opcode `vl1re64.v v3,0\(a0\)'
++.*: Error: unrecognized opcode `vl2r.v v2,\(a0\)'
++.*: Error: unrecognized opcode `vl2r.v v2,0\(a0\)'
++.*: Error: unrecognized opcode `vl2re8.v v2,\(a0\)'
++.*: Error: unrecognized opcode `vl2re8.v v2,0\(a0\)'
++.*: Error: unrecognized opcode `vl2re16.v v2,\(a0\)'
++.*: Error: unrecognized opcode `vl2re16.v v2,0\(a0\)'
++.*: Error: unrecognized opcode `vl2re32.v v2,\(a0\)'
++.*: Error: unrecognized opcode `vl2re32.v v2,0\(a0\)'
++.*: Error: unrecognized opcode `vl2re64.v v2,\(a0\)'
++.*: Error: unrecognized opcode `vl2re64.v v2,0\(a0\)'
++.*: Error: unrecognized opcode `vl4r.v v4,\(a0\)'
++.*: Error: unrecognized opcode `vl4r.v v4,0\(a0\)'
++.*: Error: unrecognized opcode `vl4re8.v v4,\(a0\)'
++.*: Error: unrecognized opcode `vl4re8.v v4,0\(a0\)'
++.*: Error: unrecognized opcode `vl4re16.v v4,\(a0\)'
++.*: Error: unrecognized opcode `vl4re16.v v4,0\(a0\)'
++.*: Error: unrecognized opcode `vl4re32.v v4,\(a0\)'
++.*: Error: unrecognized opcode `vl4re32.v v4,0\(a0\)'
++.*: Error: unrecognized opcode `vl4re64.v v4,\(a0\)'
++.*: Error: unrecognized opcode `vl4re64.v v4,0\(a0\)'
++.*: Error: unrecognized opcode `vl8r.v v8,\(a0\)'
++.*: Error: unrecognized opcode `vl8r.v v8,0\(a0\)'
++.*: Error: unrecognized opcode `vl8re8.v v8,\(a0\)'
++.*: Error: unrecognized opcode `vl8re8.v v8,0\(a0\)'
++.*: Error: unrecognized opcode `vl8re16.v v8,\(a0\)'
++.*: Error: unrecognized opcode `vl8re16.v v8,0\(a0\)'
++.*: Error: unrecognized opcode `vl8re32.v v8,\(a0\)'
++.*: Error: unrecognized opcode `vl8re32.v v8,0\(a0\)'
++.*: Error: unrecognized opcode `vl8re64.v v8,\(a0\)'
++.*: Error: unrecognized opcode `vl8re64.v v8,0\(a0\)'
++.*: Error: unrecognized opcode `vs1r.v v3,\(a1\)'
++.*: Error: unrecognized opcode `vs1r.v v3,0\(a1\)'
++.*: Error: unrecognized opcode `vs2r.v v2,\(a1\)'
++.*: Error: unrecognized opcode `vs2r.v v2,0\(a1\)'
++.*: Error: unrecognized opcode `vs4r.v v4,\(a1\)'
++.*: Error: unrecognized opcode `vs4r.v v4,0\(a1\)'
++.*: Error: unrecognized opcode `vs8r.v v8,\(a1\)'
++.*: Error: unrecognized opcode `vs8r.v v8,0\(a1\)'
++.*: Error: unrecognized opcode `vamoaddei8.v v4,\(a1\),v8,v4'
++.*: Error: unrecognized opcode `vamoaddei8.v x0,\(a1\),v8,v4'
++.*: Error: unrecognized opcode `vamoaddei8.v v4,\(a1\),v8,v4,v0.t'
++.*: Error: unrecognized opcode `vamoaddei8.v x0,\(a1\),v8,v4,v0.t'
++.*: Error: unrecognized opcode `vamoswapei8.v v4,\(a1\),v8,v4'
++.*: Error: unrecognized opcode `vamoswapei8.v x0,\(a1\),v8,v4'
++.*: Error: unrecognized opcode `vamoswapei8.v v4,\(a1\),v8,v4,v0.t'
++.*: Error: unrecognized opcode `vamoswapei8.v x0,\(a1\),v8,v4,v0.t'
++.*: Error: unrecognized opcode `vamoxorei8.v v4,\(a1\),v8,v4'
++.*: Error: unrecognized opcode `vamoxorei8.v x0,\(a1\),v8,v4'
++.*: Error: unrecognized opcode `vamoxorei8.v v4,\(a1\),v8,v4,v0.t'
++.*: Error: unrecognized opcode `vamoxorei8.v x0,\(a1\),v8,v4,v0.t'
++.*: Error: unrecognized opcode `vamoandei8.v v4,\(a1\),v8,v4'
++.*: Error: unrecognized opcode `vamoandei8.v x0,\(a1\),v8,v4'
++.*: Error: unrecognized opcode `vamoandei8.v v4,\(a1\),v8,v4,v0.t'
++.*: Error: unrecognized opcode `vamoandei8.v x0,\(a1\),v8,v4,v0.t'
++.*: Error: unrecognized opcode `vamoorei8.v v4,\(a1\),v8,v4'
++.*: Error: unrecognized opcode `vamoorei8.v x0,\(a1\),v8,v4'
++.*: Error: unrecognized opcode `vamoorei8.v v4,\(a1\),v8,v4,v0.t'
++.*: Error: unrecognized opcode `vamoorei8.v x0,\(a1\),v8,v4,v0.t'
++.*: Error: unrecognized opcode `vamominei8.v v4,\(a1\),v8,v4'
++.*: Error: unrecognized opcode `vamominei8.v x0,\(a1\),v8,v4'
++.*: Error: unrecognized opcode `vamominei8.v v4,\(a1\),v8,v4,v0.t'
++.*: Error: unrecognized opcode `vamominei8.v x0,\(a1\),v8,v4,v0.t'
++.*: Error: unrecognized opcode `vamomaxei8.v v4,\(a1\),v8,v4'
++.*: Error: unrecognized opcode `vamomaxei8.v x0,\(a1\),v8,v4'
++.*: Error: unrecognized opcode `vamomaxei8.v v4,\(a1\),v8,v4,v0.t'
++.*: Error: unrecognized opcode `vamomaxei8.v x0,\(a1\),v8,v4,v0.t'
++.*: Error: unrecognized opcode `vamominuei8.v v4,\(a1\),v8,v4'
++.*: Error: unrecognized opcode `vamominuei8.v x0,\(a1\),v8,v4'
++.*: Error: unrecognized opcode `vamominuei8.v v4,\(a1\),v8,v4,v0.t'
++.*: Error: unrecognized opcode `vamominuei8.v x0,\(a1\),v8,v4,v0.t'
++.*: Error: unrecognized opcode `vamomaxuei8.v v4,\(a1\),v8,v4'
++.*: Error: unrecognized opcode `vamomaxuei8.v x0,\(a1\),v8,v4'
++.*: Error: unrecognized opcode `vamomaxuei8.v v4,\(a1\),v8,v4,v0.t'
++.*: Error: unrecognized opcode `vamomaxuei8.v x0,\(a1\),v8,v4,v0.t'
++.*: Error: unrecognized opcode `vamoaddei8.v v4,0\(a1\),v8,v4'
++.*: Error: unrecognized opcode `vamoaddei8.v x0,0\(a1\),v8,v4'
++.*: Error: unrecognized opcode `vamoaddei8.v v4,0\(a1\),v8,v4,v0.t'
++.*: Error: unrecognized opcode `vamoaddei8.v x0,0\(a1\),v8,v4,v0.t'
++.*: Error: unrecognized opcode `vamoswapei8.v v4,0\(a1\),v8,v4'
++.*: Error: unrecognized opcode `vamoswapei8.v x0,0\(a1\),v8,v4'
++.*: Error: unrecognized opcode `vamoswapei8.v v4,0\(a1\),v8,v4,v0.t'
++.*: Error: unrecognized opcode `vamoswapei8.v x0,0\(a1\),v8,v4,v0.t'
++.*: Error: unrecognized opcode `vamoxorei8.v v4,0\(a1\),v8,v4'
++.*: Error: unrecognized opcode `vamoxorei8.v x0,0\(a1\),v8,v4'
++.*: Error: unrecognized opcode `vamoxorei8.v v4,0\(a1\),v8,v4,v0.t'
++.*: Error: unrecognized opcode `vamoxorei8.v x0,0\(a1\),v8,v4,v0.t'
++.*: Error: unrecognized opcode `vamoandei8.v v4,0\(a1\),v8,v4'
++.*: Error: unrecognized opcode `vamoandei8.v x0,0\(a1\),v8,v4'
++.*: Error: unrecognized opcode `vamoandei8.v v4,0\(a1\),v8,v4,v0.t'
++.*: Error: unrecognized opcode `vamoandei8.v x0,0\(a1\),v8,v4,v0.t'
++.*: Error: unrecognized opcode `vamoorei8.v v4,0\(a1\),v8,v4'
++.*: Error: unrecognized opcode `vamoorei8.v x0,0\(a1\),v8,v4'
++.*: Error: unrecognized opcode `vamoorei8.v v4,0\(a1\),v8,v4,v0.t'
++.*: Error: unrecognized opcode `vamoorei8.v x0,0\(a1\),v8,v4,v0.t'
++.*: Error: unrecognized opcode `vamominei8.v v4,0\(a1\),v8,v4'
++.*: Error: unrecognized opcode `vamominei8.v x0,0\(a1\),v8,v4'
++.*: Error: unrecognized opcode `vamominei8.v v4,0\(a1\),v8,v4,v0.t'
++.*: Error: unrecognized opcode `vamominei8.v x0,0\(a1\),v8,v4,v0.t'
++.*: Error: unrecognized opcode `vamomaxei8.v v4,0\(a1\),v8,v4'
++.*: Error: unrecognized opcode `vamomaxei8.v x0,0\(a1\),v8,v4'
++.*: Error: unrecognized opcode `vamomaxei8.v v4,0\(a1\),v8,v4,v0.t'
++.*: Error: unrecognized opcode `vamomaxei8.v x0,0\(a1\),v8,v4,v0.t'
++.*: Error: unrecognized opcode `vamominuei8.v v4,0\(a1\),v8,v4'
++.*: Error: unrecognized opcode `vamominuei8.v x0,0\(a1\),v8,v4'
++.*: Error: unrecognized opcode `vamominuei8.v v4,0\(a1\),v8,v4,v0.t'
++.*: Error: unrecognized opcode `vamominuei8.v x0,0\(a1\),v8,v4,v0.t'
++.*: Error: unrecognized opcode `vamomaxuei8.v v4,0\(a1\),v8,v4'
++.*: Error: unrecognized opcode `vamomaxuei8.v x0,0\(a1\),v8,v4'
++.*: Error: unrecognized opcode `vamomaxuei8.v v4,0\(a1\),v8,v4,v0.t'
++.*: Error: unrecognized opcode `vamomaxuei8.v x0,0\(a1\),v8,v4,v0.t'
++.*: Error: unrecognized opcode `vamoaddei16.v v4,\(a1\),v8,v4'
++.*: Error: unrecognized opcode `vamoaddei16.v x0,\(a1\),v8,v4'
++.*: Error: unrecognized opcode `vamoaddei16.v v4,\(a1\),v8,v4,v0.t'
++.*: Error: unrecognized opcode `vamoaddei16.v x0,\(a1\),v8,v4,v0.t'
++.*: Error: unrecognized opcode `vamoswapei16.v v4,\(a1\),v8,v4'
++.*: Error: unrecognized opcode `vamoswapei16.v x0,\(a1\),v8,v4'
++.*: Error: unrecognized opcode `vamoswapei16.v v4,\(a1\),v8,v4,v0.t'
++.*: Error: unrecognized opcode `vamoswapei16.v x0,\(a1\),v8,v4,v0.t'
++.*: Error: unrecognized opcode `vamoxorei16.v v4,\(a1\),v8,v4'
++.*: Error: unrecognized opcode `vamoxorei16.v x0,\(a1\),v8,v4'
++.*: Error: unrecognized opcode `vamoxorei16.v v4,\(a1\),v8,v4,v0.t'
++.*: Error: unrecognized opcode `vamoxorei16.v x0,\(a1\),v8,v4,v0.t'
++.*: Error: unrecognized opcode `vamoandei16.v v4,\(a1\),v8,v4'
++.*: Error: unrecognized opcode `vamoandei16.v x0,\(a1\),v8,v4'
++.*: Error: unrecognized opcode `vamoandei16.v v4,\(a1\),v8,v4,v0.t'
++.*: Error: unrecognized opcode `vamoandei16.v x0,\(a1\),v8,v4,v0.t'
++.*: Error: unrecognized opcode `vamoorei16.v v4,\(a1\),v8,v4'
++.*: Error: unrecognized opcode `vamoorei16.v x0,\(a1\),v8,v4'
++.*: Error: unrecognized opcode `vamoorei16.v v4,\(a1\),v8,v4,v0.t'
++.*: Error: unrecognized opcode `vamoorei16.v x0,\(a1\),v8,v4,v0.t'
++.*: Error: unrecognized opcode `vamominei16.v v4,\(a1\),v8,v4'
++.*: Error: unrecognized opcode `vamominei16.v x0,\(a1\),v8,v4'
++.*: Error: unrecognized opcode `vamominei16.v v4,\(a1\),v8,v4,v0.t'
++.*: Error: unrecognized opcode `vamominei16.v x0,\(a1\),v8,v4,v0.t'
++.*: Error: unrecognized opcode `vamomaxei16.v v4,\(a1\),v8,v4'
++.*: Error: unrecognized opcode `vamomaxei16.v x0,\(a1\),v8,v4'
++.*: Error: unrecognized opcode `vamomaxei16.v v4,\(a1\),v8,v4,v0.t'
++.*: Error: unrecognized opcode `vamomaxei16.v x0,\(a1\),v8,v4,v0.t'
++.*: Error: unrecognized opcode `vamominuei16.v v4,\(a1\),v8,v4'
++.*: Error: unrecognized opcode `vamominuei16.v x0,\(a1\),v8,v4'
++.*: Error: unrecognized opcode `vamominuei16.v v4,\(a1\),v8,v4,v0.t'
++.*: Error: unrecognized opcode `vamominuei16.v x0,\(a1\),v8,v4,v0.t'
++.*: Error: unrecognized opcode `vamomaxuei16.v v4,\(a1\),v8,v4'
++.*: Error: unrecognized opcode `vamomaxuei16.v x0,\(a1\),v8,v4'
++.*: Error: unrecognized opcode `vamomaxuei16.v v4,\(a1\),v8,v4,v0.t'
++.*: Error: unrecognized opcode `vamomaxuei16.v x0,\(a1\),v8,v4,v0.t'
++.*: Error: unrecognized opcode `vamoaddei16.v v4,0\(a1\),v8,v4'
++.*: Error: unrecognized opcode `vamoaddei16.v x0,0\(a1\),v8,v4'
++.*: Error: unrecognized opcode `vamoaddei16.v v4,0\(a1\),v8,v4,v0.t'
++.*: Error: unrecognized opcode `vamoaddei16.v x0,0\(a1\),v8,v4,v0.t'
++.*: Error: unrecognized opcode `vamoswapei16.v v4,0\(a1\),v8,v4'
++.*: Error: unrecognized opcode `vamoswapei16.v x0,0\(a1\),v8,v4'
++.*: Error: unrecognized opcode `vamoswapei16.v v4,0\(a1\),v8,v4,v0.t'
++.*: Error: unrecognized opcode `vamoswapei16.v x0,0\(a1\),v8,v4,v0.t'
++.*: Error: unrecognized opcode `vamoxorei16.v v4,0\(a1\),v8,v4'
++.*: Error: unrecognized opcode `vamoxorei16.v x0,0\(a1\),v8,v4'
++.*: Error: unrecognized opcode `vamoxorei16.v v4,0\(a1\),v8,v4,v0.t'
++.*: Error: unrecognized opcode `vamoxorei16.v x0,0\(a1\),v8,v4,v0.t'
++.*: Error: unrecognized opcode `vamoandei16.v v4,0\(a1\),v8,v4'
++.*: Error: unrecognized opcode `vamoandei16.v x0,0\(a1\),v8,v4'
++.*: Error: unrecognized opcode `vamoandei16.v v4,0\(a1\),v8,v4,v0.t'
++.*: Error: unrecognized opcode `vamoandei16.v x0,0\(a1\),v8,v4,v0.t'
++.*: Error: unrecognized opcode `vamoorei16.v v4,0\(a1\),v8,v4'
++.*: Error: unrecognized opcode `vamoorei16.v x0,0\(a1\),v8,v4'
++.*: Error: unrecognized opcode `vamoorei16.v v4,0\(a1\),v8,v4,v0.t'
++.*: Error: unrecognized opcode `vamoorei16.v x0,0\(a1\),v8,v4,v0.t'
++.*: Error: unrecognized opcode `vamominei16.v v4,0\(a1\),v8,v4'
++.*: Error: unrecognized opcode `vamominei16.v x0,0\(a1\),v8,v4'
++.*: Error: unrecognized opcode `vamominei16.v v4,0\(a1\),v8,v4,v0.t'
++.*: Error: unrecognized opcode `vamominei16.v x0,0\(a1\),v8,v4,v0.t'
++.*: Error: unrecognized opcode `vamomaxei16.v v4,0\(a1\),v8,v4'
++.*: Error: unrecognized opcode `vamomaxei16.v x0,0\(a1\),v8,v4'
++.*: Error: unrecognized opcode `vamomaxei16.v v4,0\(a1\),v8,v4,v0.t'
++.*: Error: unrecognized opcode `vamomaxei16.v x0,0\(a1\),v8,v4,v0.t'
++.*: Error: unrecognized opcode `vamominuei16.v v4,0\(a1\),v8,v4'
++.*: Error: unrecognized opcode `vamominuei16.v x0,0\(a1\),v8,v4'
++.*: Error: unrecognized opcode `vamominuei16.v v4,0\(a1\),v8,v4,v0.t'
++.*: Error: unrecognized opcode `vamominuei16.v x0,0\(a1\),v8,v4,v0.t'
++.*: Error: unrecognized opcode `vamomaxuei16.v v4,0\(a1\),v8,v4'
++.*: Error: unrecognized opcode `vamomaxuei16.v x0,0\(a1\),v8,v4'
++.*: Error: unrecognized opcode `vamomaxuei16.v v4,0\(a1\),v8,v4,v0.t'
++.*: Error: unrecognized opcode `vamomaxuei16.v x0,0\(a1\),v8,v4,v0.t'
++.*: Error: unrecognized opcode `vamoaddei32.v v4,\(a1\),v8,v4'
++.*: Error: unrecognized opcode `vamoaddei32.v x0,\(a1\),v8,v4'
++.*: Error: unrecognized opcode `vamoaddei32.v v4,\(a1\),v8,v4,v0.t'
++.*: Error: unrecognized opcode `vamoaddei32.v x0,\(a1\),v8,v4,v0.t'
++.*: Error: unrecognized opcode `vamoswapei32.v v4,\(a1\),v8,v4'
++.*: Error: unrecognized opcode `vamoswapei32.v x0,\(a1\),v8,v4'
++.*: Error: unrecognized opcode `vamoswapei32.v v4,\(a1\),v8,v4,v0.t'
++.*: Error: unrecognized opcode `vamoswapei32.v x0,\(a1\),v8,v4,v0.t'
++.*: Error: unrecognized opcode `vamoxorei32.v v4,\(a1\),v8,v4'
++.*: Error: unrecognized opcode `vamoxorei32.v x0,\(a1\),v8,v4'
++.*: Error: unrecognized opcode `vamoxorei32.v v4,\(a1\),v8,v4,v0.t'
++.*: Error: unrecognized opcode `vamoxorei32.v x0,\(a1\),v8,v4,v0.t'
++.*: Error: unrecognized opcode `vamoandei32.v v4,\(a1\),v8,v4'
++.*: Error: unrecognized opcode `vamoandei32.v x0,\(a1\),v8,v4'
++.*: Error: unrecognized opcode `vamoandei32.v v4,\(a1\),v8,v4,v0.t'
++.*: Error: unrecognized opcode `vamoandei32.v x0,\(a1\),v8,v4,v0.t'
++.*: Error: unrecognized opcode `vamoorei32.v v4,\(a1\),v8,v4'
++.*: Error: unrecognized opcode `vamoorei32.v x0,\(a1\),v8,v4'
++.*: Error: unrecognized opcode `vamoorei32.v v4,\(a1\),v8,v4,v0.t'
++.*: Error: unrecognized opcode `vamoorei32.v x0,\(a1\),v8,v4,v0.t'
++.*: Error: unrecognized opcode `vamominei32.v v4,\(a1\),v8,v4'
++.*: Error: unrecognized opcode `vamominei32.v x0,\(a1\),v8,v4'
++.*: Error: unrecognized opcode `vamominei32.v v4,\(a1\),v8,v4,v0.t'
++.*: Error: unrecognized opcode `vamominei32.v x0,\(a1\),v8,v4,v0.t'
++.*: Error: unrecognized opcode `vamomaxei32.v v4,\(a1\),v8,v4'
++.*: Error: unrecognized opcode `vamomaxei32.v x0,\(a1\),v8,v4'
++.*: Error: unrecognized opcode `vamomaxei32.v v4,\(a1\),v8,v4,v0.t'
++.*: Error: unrecognized opcode `vamomaxei32.v x0,\(a1\),v8,v4,v0.t'
++.*: Error: unrecognized opcode `vamominuei32.v v4,\(a1\),v8,v4'
++.*: Error: unrecognized opcode `vamominuei32.v x0,\(a1\),v8,v4'
++.*: Error: unrecognized opcode `vamominuei32.v v4,\(a1\),v8,v4,v0.t'
++.*: Error: unrecognized opcode `vamominuei32.v x0,\(a1\),v8,v4,v0.t'
++.*: Error: unrecognized opcode `vamomaxuei32.v v4,\(a1\),v8,v4'
++.*: Error: unrecognized opcode `vamomaxuei32.v x0,\(a1\),v8,v4'
++.*: Error: unrecognized opcode `vamomaxuei32.v v4,\(a1\),v8,v4,v0.t'
++.*: Error: unrecognized opcode `vamomaxuei32.v x0,\(a1\),v8,v4,v0.t'
++.*: Error: unrecognized opcode `vamoaddei32.v v4,0\(a1\),v8,v4'
++.*: Error: unrecognized opcode `vamoaddei32.v x0,0\(a1\),v8,v4'
++.*: Error: unrecognized opcode `vamoaddei32.v v4,0\(a1\),v8,v4,v0.t'
++.*: Error: unrecognized opcode `vamoaddei32.v x0,0\(a1\),v8,v4,v0.t'
++.*: Error: unrecognized opcode `vamoswapei32.v v4,0\(a1\),v8,v4'
++.*: Error: unrecognized opcode `vamoswapei32.v x0,0\(a1\),v8,v4'
++.*: Error: unrecognized opcode `vamoswapei32.v v4,0\(a1\),v8,v4,v0.t'
++.*: Error: unrecognized opcode `vamoswapei32.v x0,0\(a1\),v8,v4,v0.t'
++.*: Error: unrecognized opcode `vamoxorei32.v v4,0\(a1\),v8,v4'
++.*: Error: unrecognized opcode `vamoxorei32.v x0,0\(a1\),v8,v4'
++.*: Error: unrecognized opcode `vamoxorei32.v v4,0\(a1\),v8,v4,v0.t'
++.*: Error: unrecognized opcode `vamoxorei32.v x0,0\(a1\),v8,v4,v0.t'
++.*: Error: unrecognized opcode `vamoandei32.v v4,0\(a1\),v8,v4'
++.*: Error: unrecognized opcode `vamoandei32.v x0,0\(a1\),v8,v4'
++.*: Error: unrecognized opcode `vamoandei32.v v4,0\(a1\),v8,v4,v0.t'
++.*: Error: unrecognized opcode `vamoandei32.v x0,0\(a1\),v8,v4,v0.t'
++.*: Error: unrecognized opcode `vamoorei32.v v4,0\(a1\),v8,v4'
++.*: Error: unrecognized opcode `vamoorei32.v x0,0\(a1\),v8,v4'
++.*: Error: unrecognized opcode `vamoorei32.v v4,0\(a1\),v8,v4,v0.t'
++.*: Error: unrecognized opcode `vamoorei32.v x0,0\(a1\),v8,v4,v0.t'
++.*: Error: unrecognized opcode `vamominei32.v v4,0\(a1\),v8,v4'
++.*: Error: unrecognized opcode `vamominei32.v x0,0\(a1\),v8,v4'
++.*: Error: unrecognized opcode `vamominei32.v v4,0\(a1\),v8,v4,v0.t'
++.*: Error: unrecognized opcode `vamominei32.v x0,0\(a1\),v8,v4,v0.t'
++.*: Error: unrecognized opcode `vamomaxei32.v v4,0\(a1\),v8,v4'
++.*: Error: unrecognized opcode `vamomaxei32.v x0,0\(a1\),v8,v4'
++.*: Error: unrecognized opcode `vamomaxei32.v v4,0\(a1\),v8,v4,v0.t'
++.*: Error: unrecognized opcode `vamomaxei32.v x0,0\(a1\),v8,v4,v0.t'
++.*: Error: unrecognized opcode `vamominuei32.v v4,0\(a1\),v8,v4'
++.*: Error: unrecognized opcode `vamominuei32.v x0,0\(a1\),v8,v4'
++.*: Error: unrecognized opcode `vamominuei32.v v4,0\(a1\),v8,v4,v0.t'
++.*: Error: unrecognized opcode `vamominuei32.v x0,0\(a1\),v8,v4,v0.t'
++.*: Error: unrecognized opcode `vamomaxuei32.v v4,0\(a1\),v8,v4'
++.*: Error: unrecognized opcode `vamomaxuei32.v x0,0\(a1\),v8,v4'
++.*: Error: unrecognized opcode `vamomaxuei32.v v4,0\(a1\),v8,v4,v0.t'
++.*: Error: unrecognized opcode `vamomaxuei32.v x0,0\(a1\),v8,v4,v0.t'
++.*: Error: unrecognized opcode `vamoaddei64.v v4,\(a1\),v8,v4'
++.*: Error: unrecognized opcode `vamoaddei64.v x0,\(a1\),v8,v4'
++.*: Error: unrecognized opcode `vamoaddei64.v v4,\(a1\),v8,v4,v0.t'
++.*: Error: unrecognized opcode `vamoaddei64.v x0,\(a1\),v8,v4,v0.t'
++.*: Error: unrecognized opcode `vamoswapei64.v v4,\(a1\),v8,v4'
++.*: Error: unrecognized opcode `vamoswapei64.v x0,\(a1\),v8,v4'
++.*: Error: unrecognized opcode `vamoswapei64.v v4,\(a1\),v8,v4,v0.t'
++.*: Error: unrecognized opcode `vamoswapei64.v x0,\(a1\),v8,v4,v0.t'
++.*: Error: unrecognized opcode `vamoxorei64.v v4,\(a1\),v8,v4'
++.*: Error: unrecognized opcode `vamoxorei64.v x0,\(a1\),v8,v4'
++.*: Error: unrecognized opcode `vamoxorei64.v v4,\(a1\),v8,v4,v0.t'
++.*: Error: unrecognized opcode `vamoxorei64.v x0,\(a1\),v8,v4,v0.t'
++.*: Error: unrecognized opcode `vamoandei64.v v4,\(a1\),v8,v4'
++.*: Error: unrecognized opcode `vamoandei64.v x0,\(a1\),v8,v4'
++.*: Error: unrecognized opcode `vamoandei64.v v4,\(a1\),v8,v4,v0.t'
++.*: Error: unrecognized opcode `vamoandei64.v x0,\(a1\),v8,v4,v0.t'
++.*: Error: unrecognized opcode `vamoorei64.v v4,\(a1\),v8,v4'
++.*: Error: unrecognized opcode `vamoorei64.v x0,\(a1\),v8,v4'
++.*: Error: unrecognized opcode `vamoorei64.v v4,\(a1\),v8,v4,v0.t'
++.*: Error: unrecognized opcode `vamoorei64.v x0,\(a1\),v8,v4,v0.t'
++.*: Error: unrecognized opcode `vamominei64.v v4,\(a1\),v8,v4'
++.*: Error: unrecognized opcode `vamominei64.v x0,\(a1\),v8,v4'
++.*: Error: unrecognized opcode `vamominei64.v v4,\(a1\),v8,v4,v0.t'
++.*: Error: unrecognized opcode `vamominei64.v x0,\(a1\),v8,v4,v0.t'
++.*: Error: unrecognized opcode `vamomaxei64.v v4,\(a1\),v8,v4'
++.*: Error: unrecognized opcode `vamomaxei64.v x0,\(a1\),v8,v4'
++.*: Error: unrecognized opcode `vamomaxei64.v v4,\(a1\),v8,v4,v0.t'
++.*: Error: unrecognized opcode `vamomaxei64.v x0,\(a1\),v8,v4,v0.t'
++.*: Error: unrecognized opcode `vamominuei64.v v4,\(a1\),v8,v4'
++.*: Error: unrecognized opcode `vamominuei64.v x0,\(a1\),v8,v4'
++.*: Error: unrecognized opcode `vamominuei64.v v4,\(a1\),v8,v4,v0.t'
++.*: Error: unrecognized opcode `vamominuei64.v x0,\(a1\),v8,v4,v0.t'
++.*: Error: unrecognized opcode `vamomaxuei64.v v4,\(a1\),v8,v4'
++.*: Error: unrecognized opcode `vamomaxuei64.v x0,\(a1\),v8,v4'
++.*: Error: unrecognized opcode `vamomaxuei64.v v4,\(a1\),v8,v4,v0.t'
++.*: Error: unrecognized opcode `vamomaxuei64.v x0,\(a1\),v8,v4,v0.t'
++.*: Error: unrecognized opcode `vamoaddei64.v v4,0\(a1\),v8,v4'
++.*: Error: unrecognized opcode `vamoaddei64.v x0,0\(a1\),v8,v4'
++.*: Error: unrecognized opcode `vamoaddei64.v v4,0\(a1\),v8,v4,v0.t'
++.*: Error: unrecognized opcode `vamoaddei64.v x0,0\(a1\),v8,v4,v0.t'
++.*: Error: unrecognized opcode `vamoswapei64.v v4,0\(a1\),v8,v4'
++.*: Error: unrecognized opcode `vamoswapei64.v x0,0\(a1\),v8,v4'
++.*: Error: unrecognized opcode `vamoswapei64.v v4,0\(a1\),v8,v4,v0.t'
++.*: Error: unrecognized opcode `vamoswapei64.v x0,0\(a1\),v8,v4,v0.t'
++.*: Error: unrecognized opcode `vamoxorei64.v v4,0\(a1\),v8,v4'
++.*: Error: unrecognized opcode `vamoxorei64.v x0,0\(a1\),v8,v4'
++.*: Error: unrecognized opcode `vamoxorei64.v v4,0\(a1\),v8,v4,v0.t'
++.*: Error: unrecognized opcode `vamoxorei64.v x0,0\(a1\),v8,v4,v0.t'
++.*: Error: unrecognized opcode `vamoandei64.v v4,0\(a1\),v8,v4'
++.*: Error: unrecognized opcode `vamoandei64.v x0,0\(a1\),v8,v4'
++.*: Error: unrecognized opcode `vamoandei64.v v4,0\(a1\),v8,v4,v0.t'
++.*: Error: unrecognized opcode `vamoandei64.v x0,0\(a1\),v8,v4,v0.t'
++.*: Error: unrecognized opcode `vamoorei64.v v4,0\(a1\),v8,v4'
++.*: Error: unrecognized opcode `vamoorei64.v x0,0\(a1\),v8,v4'
++.*: Error: unrecognized opcode `vamoorei64.v v4,0\(a1\),v8,v4,v0.t'
++.*: Error: unrecognized opcode `vamoorei64.v x0,0\(a1\),v8,v4,v0.t'
++.*: Error: unrecognized opcode `vamominei64.v v4,0\(a1\),v8,v4'
++.*: Error: unrecognized opcode `vamominei64.v x0,0\(a1\),v8,v4'
++.*: Error: unrecognized opcode `vamominei64.v v4,0\(a1\),v8,v4,v0.t'
++.*: Error: unrecognized opcode `vamominei64.v x0,0\(a1\),v8,v4,v0.t'
++.*: Error: unrecognized opcode `vamomaxei64.v v4,0\(a1\),v8,v4'
++.*: Error: unrecognized opcode `vamomaxei64.v x0,0\(a1\),v8,v4'
++.*: Error: unrecognized opcode `vamomaxei64.v v4,0\(a1\),v8,v4,v0.t'
++.*: Error: unrecognized opcode `vamomaxei64.v x0,0\(a1\),v8,v4,v0.t'
++.*: Error: unrecognized opcode `vamominuei64.v v4,0\(a1\),v8,v4'
++.*: Error: unrecognized opcode `vamominuei64.v x0,0\(a1\),v8,v4'
++.*: Error: unrecognized opcode `vamominuei64.v v4,0\(a1\),v8,v4,v0.t'
++.*: Error: unrecognized opcode `vamominuei64.v x0,0\(a1\),v8,v4,v0.t'
++.*: Error: unrecognized opcode `vamomaxuei64.v v4,0\(a1\),v8,v4'
++.*: Error: unrecognized opcode `vamomaxuei64.v x0,0\(a1\),v8,v4'
++.*: Error: unrecognized opcode `vamomaxuei64.v v4,0\(a1\),v8,v4,v0.t'
++.*: Error: unrecognized opcode `vamomaxuei64.v x0,0\(a1\),v8,v4,v0.t'
++.*: Error: unrecognized opcode `vwcvt.x.x.v v4,v8'
++.*: Error: unrecognized opcode `vwcvtu.x.x.v v4,v8'
++.*: Error: unrecognized opcode `vwcvt.x.x.v v4,v8,v0.t'
++.*: Error: unrecognized opcode `vwcvtu.x.x.v v4,v8,v0.t'
++.*: Error: unrecognized opcode `vwaddu.vv v4,v8,v12'
++.*: Error: unrecognized opcode `vwaddu.vx v4,v8,a1'
++.*: Error: unrecognized opcode `vwaddu.vv v4,v8,v12,v0.t'
++.*: Error: unrecognized opcode `vwaddu.vx v4,v8,a1,v0.t'
++.*: Error: unrecognized opcode `vwsubu.vv v4,v8,v12'
++.*: Error: unrecognized opcode `vwsubu.vx v4,v8,a1'
++.*: Error: unrecognized opcode `vwsubu.vv v4,v8,v12,v0.t'
++.*: Error: unrecognized opcode `vwsubu.vx v4,v8,a1,v0.t'
++.*: Error: unrecognized opcode `vwadd.vv v4,v8,v12'
++.*: Error: unrecognized opcode `vwadd.vx v4,v8,a1'
++.*: Error: unrecognized opcode `vwadd.vv v4,v8,v12,v0.t'
++.*: Error: unrecognized opcode `vwadd.vx v4,v8,a1,v0.t'
++.*: Error: unrecognized opcode `vwsub.vv v4,v8,v12'
++.*: Error: unrecognized opcode `vwsub.vx v4,v8,a1'
++.*: Error: unrecognized opcode `vwsub.vv v4,v8,v12,v0.t'
++.*: Error: unrecognized opcode `vwsub.vx v4,v8,a1,v0.t'
++.*: Error: unrecognized opcode `vwaddu.wv v4,v8,v12'
++.*: Error: unrecognized opcode `vwaddu.wx v4,v8,a1'
++.*: Error: unrecognized opcode `vwaddu.wv v4,v8,v12,v0.t'
++.*: Error: unrecognized opcode `vwaddu.wx v4,v8,a1,v0.t'
++.*: Error: unrecognized opcode `vwsubu.wv v4,v8,v12'
++.*: Error: unrecognized opcode `vwsubu.wx v4,v8,a1'
++.*: Error: unrecognized opcode `vwsubu.wv v4,v8,v12,v0.t'
++.*: Error: unrecognized opcode `vwsubu.wx v4,v8,a1,v0.t'
++.*: Error: unrecognized opcode `vwadd.wv v4,v8,v12'
++.*: Error: unrecognized opcode `vwadd.wx v4,v8,a1'
++.*: Error: unrecognized opcode `vwadd.wv v4,v8,v12,v0.t'
++.*: Error: unrecognized opcode `vwadd.wx v4,v8,a1,v0.t'
++.*: Error: unrecognized opcode `vwsub.wv v4,v8,v12'
++.*: Error: unrecognized opcode `vwsub.wx v4,v8,a1'
++.*: Error: unrecognized opcode `vwsub.wv v4,v8,v12,v0.t'
++.*: Error: unrecognized opcode `vwsub.wx v4,v8,a1,v0.t'
++.*: Error: unrecognized opcode `vsll.vv v4,v8,v12'
++.*: Error: unrecognized opcode `vsll.vx v4,v8,a1'
++.*: Error: unrecognized opcode `vsll.vi v4,v8,1'
++.*: Error: unrecognized opcode `vsll.vi v4,v8,31'
++.*: Error: unrecognized opcode `vsll.vv v4,v8,v12,v0.t'
++.*: Error: unrecognized opcode `vsll.vx v4,v8,a1,v0.t'
++.*: Error: unrecognized opcode `vsll.vi v4,v8,1,v0.t'
++.*: Error: unrecognized opcode `vsll.vi v4,v8,31,v0.t'
++.*: Error: unrecognized opcode `vsrl.vv v4,v8,v12'
++.*: Error: unrecognized opcode `vsrl.vx v4,v8,a1'
++.*: Error: unrecognized opcode `vsrl.vi v4,v8,1'
++.*: Error: unrecognized opcode `vsrl.vi v4,v8,31'
++.*: Error: unrecognized opcode `vsrl.vv v4,v8,v12,v0.t'
++.*: Error: unrecognized opcode `vsrl.vx v4,v8,a1,v0.t'
++.*: Error: unrecognized opcode `vsrl.vi v4,v8,1,v0.t'
++.*: Error: unrecognized opcode `vsrl.vi v4,v8,31,v0.t'
++.*: Error: unrecognized opcode `vsra.vv v4,v8,v12'
++.*: Error: unrecognized opcode `vsra.vx v4,v8,a1'
++.*: Error: unrecognized opcode `vsra.vi v4,v8,1'
++.*: Error: unrecognized opcode `vsra.vi v4,v8,31'
++.*: Error: unrecognized opcode `vsra.vv v4,v8,v12,v0.t'
++.*: Error: unrecognized opcode `vsra.vx v4,v8,a1,v0.t'
++.*: Error: unrecognized opcode `vsra.vi v4,v8,1,v0.t'
++.*: Error: unrecognized opcode `vsra.vi v4,v8,31,v0.t'
++.*: Error: unrecognized opcode `vncvt.x.x.w v4,v8'
++.*: Error: unrecognized opcode `vncvt.x.x.w v4,v8,v0.t'
++.*: Error: unrecognized opcode `vnsrl.wv v4,v8,v12'
++.*: Error: unrecognized opcode `vnsrl.wx v4,v8,a1'
++.*: Error: unrecognized opcode `vnsrl.wi v4,v8,1'
++.*: Error: unrecognized opcode `vnsrl.wi v4,v8,31'
++.*: Error: unrecognized opcode `vnsrl.wv v4,v8,v12,v0.t'
++.*: Error: unrecognized opcode `vnsrl.wx v4,v8,a1,v0.t'
++.*: Error: unrecognized opcode `vnsrl.wi v4,v8,1,v0.t'
++.*: Error: unrecognized opcode `vnsrl.wi v4,v8,31,v0.t'
++.*: Error: unrecognized opcode `vnsra.wv v4,v8,v12'
++.*: Error: unrecognized opcode `vnsra.wx v4,v8,a1'
++.*: Error: unrecognized opcode `vnsra.wi v4,v8,1'
++.*: Error: unrecognized opcode `vnsra.wi v4,v8,31'
++.*: Error: unrecognized opcode `vnsra.wv v4,v8,v12,v0.t'
++.*: Error: unrecognized opcode `vnsra.wx v4,v8,a1,v0.t'
++.*: Error: unrecognized opcode `vnsra.wi v4,v8,1,v0.t'
++.*: Error: unrecognized opcode `vnsra.wi v4,v8,31,v0.t'
++.*: Error: unrecognized opcode `vwmul.vv v4,v8,v12'
++.*: Error: unrecognized opcode `vwmul.vx v4,v8,a1'
++.*: Error: unrecognized opcode `vwmul.vv v4,v8,v12,v0.t'
++.*: Error: unrecognized opcode `vwmul.vx v4,v8,a1,v0.t'
++.*: Error: unrecognized opcode `vwmulu.vv v4,v8,v12'
++.*: Error: unrecognized opcode `vwmulu.vx v4,v8,a1'
++.*: Error: unrecognized opcode `vwmulu.vv v4,v8,v12,v0.t'
++.*: Error: unrecognized opcode `vwmulu.vx v4,v8,a1,v0.t'
++.*: Error: unrecognized opcode `vwmulsu.vv v4,v8,v12'
++.*: Error: unrecognized opcode `vwmulsu.vx v4,v8,a1'
++.*: Error: unrecognized opcode `vwmulsu.vv v4,v8,v12,v0.t'
++.*: Error: unrecognized opcode `vwmulsu.vx v4,v8,a1,v0.t'
++.*: Error: unrecognized opcode `vwmaccu.vv v4,v12,v8'
++.*: Error: unrecognized opcode `vwmaccu.vx v4,a1,v8'
++.*: Error: unrecognized opcode `vwmaccu.vv v4,v12,v8,v0.t'
++.*: Error: unrecognized opcode `vwmaccu.vx v4,a1,v8,v0.t'
++.*: Error: unrecognized opcode `vwmacc.vv v4,v12,v8'
++.*: Error: unrecognized opcode `vwmacc.vx v4,a1,v8'
++.*: Error: unrecognized opcode `vwmacc.vv v4,v12,v8,v0.t'
++.*: Error: unrecognized opcode `vwmacc.vx v4,a1,v8,v0.t'
++.*: Error: unrecognized opcode `vwmaccsu.vv v4,v12,v8'
++.*: Error: unrecognized opcode `vwmaccsu.vx v4,a1,v8'
++.*: Error: unrecognized opcode `vwmaccsu.vv v4,v12,v8,v0.t'
++.*: Error: unrecognized opcode `vwmaccsu.vx v4,a1,v8,v0.t'
++.*: Error: unrecognized opcode `vwmaccus.vx v4,a1,v8'
++.*: Error: unrecognized opcode `vwmaccus.vx v4,a1,v8,v0.t'
++.*: Error: unrecognized opcode `vsaddu.vv v4,v8,v12'
++.*: Error: unrecognized opcode `vsaddu.vx v4,v8,a1'
++.*: Error: unrecognized opcode `vsaddu.vi v4,v8,15'
++.*: Error: unrecognized opcode `vsaddu.vi v4,v8,-16'
++.*: Error: unrecognized opcode `vsaddu.vv v4,v8,v12,v0.t'
++.*: Error: unrecognized opcode `vsaddu.vx v4,v8,a1,v0.t'
++.*: Error: unrecognized opcode `vsaddu.vi v4,v8,15,v0.t'
++.*: Error: unrecognized opcode `vsaddu.vi v4,v8,-16,v0.t'
++.*: Error: unrecognized opcode `vsadd.vv v4,v8,v12'
++.*: Error: unrecognized opcode `vsadd.vx v4,v8,a1'
++.*: Error: unrecognized opcode `vsadd.vi v4,v8,15'
++.*: Error: unrecognized opcode `vsadd.vi v4,v8,-16'
++.*: Error: unrecognized opcode `vsadd.vv v4,v8,v12,v0.t'
++.*: Error: unrecognized opcode `vsadd.vx v4,v8,a1,v0.t'
++.*: Error: unrecognized opcode `vsadd.vi v4,v8,15,v0.t'
++.*: Error: unrecognized opcode `vsadd.vi v4,v8,-16,v0.t'
++.*: Error: unrecognized opcode `vssubu.vv v4,v8,v12'
++.*: Error: unrecognized opcode `vssubu.vx v4,v8,a1'
++.*: Error: unrecognized opcode `vssubu.vv v4,v8,v12,v0.t'
++.*: Error: unrecognized opcode `vssubu.vx v4,v8,a1,v0.t'
++.*: Error: unrecognized opcode `vssub.vv v4,v8,v12'
++.*: Error: unrecognized opcode `vssub.vx v4,v8,a1'
++.*: Error: unrecognized opcode `vssub.vv v4,v8,v12,v0.t'
++.*: Error: unrecognized opcode `vssub.vx v4,v8,a1,v0.t'
++.*: Error: unrecognized opcode `vaaddu.vv v4,v8,v12'
++.*: Error: unrecognized opcode `vaaddu.vx v4,v8,a1'
++.*: Error: unrecognized opcode `vaaddu.vv v4,v8,v12,v0.t'
++.*: Error: unrecognized opcode `vaaddu.vx v4,v8,a1,v0.t'
++.*: Error: unrecognized opcode `vaadd.vv v4,v8,v12'
++.*: Error: unrecognized opcode `vaadd.vx v4,v8,a1'
++.*: Error: unrecognized opcode `vaadd.vv v4,v8,v12,v0.t'
++.*: Error: unrecognized opcode `vaadd.vx v4,v8,a1,v0.t'
++.*: Error: unrecognized opcode `vasubu.vv v4,v8,v12'
++.*: Error: unrecognized opcode `vasubu.vx v4,v8,a1'
++.*: Error: unrecognized opcode `vasubu.vv v4,v8,v12,v0.t'
++.*: Error: unrecognized opcode `vasubu.vx v4,v8,a1,v0.t'
++.*: Error: unrecognized opcode `vasub.vv v4,v8,v12'
++.*: Error: unrecognized opcode `vasub.vx v4,v8,a1'
++.*: Error: unrecognized opcode `vasub.vv v4,v8,v12,v0.t'
++.*: Error: unrecognized opcode `vasub.vx v4,v8,a1,v0.t'
++.*: Error: unrecognized opcode `vsmul.vv v4,v8,v12'
++.*: Error: unrecognized opcode `vsmul.vx v4,v8,a1'
++.*: Error: unrecognized opcode `vsmul.vv v4,v8,v12,v0.t'
++.*: Error: unrecognized opcode `vsmul.vx v4,v8,a1,v0.t'
++.*: Error: unrecognized opcode `vssrl.vv v4,v8,v12'
++.*: Error: unrecognized opcode `vssrl.vx v4,v8,a1'
++.*: Error: unrecognized opcode `vssrl.vi v4,v8,1'
++.*: Error: unrecognized opcode `vssrl.vi v4,v8,31'
++.*: Error: unrecognized opcode `vssrl.vv v4,v8,v12,v0.t'
++.*: Error: unrecognized opcode `vssrl.vx v4,v8,a1,v0.t'
++.*: Error: unrecognized opcode `vssrl.vi v4,v8,1,v0.t'
++.*: Error: unrecognized opcode `vssrl.vi v4,v8,31,v0.t'
++.*: Error: unrecognized opcode `vssra.vv v4,v8,v12'
++.*: Error: unrecognized opcode `vssra.vx v4,v8,a1'
++.*: Error: unrecognized opcode `vssra.vi v4,v8,1'
++.*: Error: unrecognized opcode `vssra.vi v4,v8,31'
++.*: Error: unrecognized opcode `vssra.vv v4,v8,v12,v0.t'
++.*: Error: unrecognized opcode `vssra.vx v4,v8,a1,v0.t'
++.*: Error: unrecognized opcode `vssra.vi v4,v8,1,v0.t'
++.*: Error: unrecognized opcode `vssra.vi v4,v8,31,v0.t'
++.*: Error: unrecognized opcode `vnclipu.wv v4,v8,v12'
++.*: Error: unrecognized opcode `vnclipu.wx v4,v8,a1'
++.*: Error: unrecognized opcode `vnclipu.wi v4,v8,1'
++.*: Error: unrecognized opcode `vnclipu.wi v4,v8,31'
++.*: Error: unrecognized opcode `vnclipu.wv v4,v8,v12,v0.t'
++.*: Error: unrecognized opcode `vnclipu.wx v4,v8,a1,v0.t'
++.*: Error: unrecognized opcode `vnclipu.wi v4,v8,1,v0.t'
++.*: Error: unrecognized opcode `vnclipu.wi v4,v8,31,v0.t'
++.*: Error: unrecognized opcode `vnclip.wv v4,v8,v12'
++.*: Error: unrecognized opcode `vnclip.wx v4,v8,a1'
++.*: Error: unrecognized opcode `vnclip.wi v4,v8,1'
++.*: Error: unrecognized opcode `vnclip.wi v4,v8,31'
++.*: Error: unrecognized opcode `vnclip.wv v4,v8,v12,v0.t'
++.*: Error: unrecognized opcode `vnclip.wx v4,v8,a1,v0.t'
++.*: Error: unrecognized opcode `vnclip.wi v4,v8,1,v0.t'
++.*: Error: unrecognized opcode `vnclip.wi v4,v8,31,v0.t'
++.*: Error: unrecognized opcode `vfwadd.vv v4,v8,v12'
++.*: Error: unrecognized opcode `vfwadd.vf v4,v8,fa2'
++.*: Error: unrecognized opcode `vfwadd.vv v4,v8,v12,v0.t'
++.*: Error: unrecognized opcode `vfwadd.vf v4,v8,fa2,v0.t'
++.*: Error: unrecognized opcode `vfwsub.vv v4,v8,v12'
++.*: Error: unrecognized opcode `vfwsub.vf v4,v8,fa2'
++.*: Error: unrecognized opcode `vfwsub.vv v4,v8,v12,v0.t'
++.*: Error: unrecognized opcode `vfwsub.vf v4,v8,fa2,v0.t'
++.*: Error: unrecognized opcode `vfwadd.wv v4,v8,v12'
++.*: Error: unrecognized opcode `vfwadd.wf v4,v8,fa2'
++.*: Error: unrecognized opcode `vfwadd.wv v4,v8,v12,v0.t'
++.*: Error: unrecognized opcode `vfwadd.wf v4,v8,fa2,v0.t'
++.*: Error: unrecognized opcode `vfwsub.wv v4,v8,v12'
++.*: Error: unrecognized opcode `vfwsub.wf v4,v8,fa2'
++.*: Error: unrecognized opcode `vfwsub.wv v4,v8,v12,v0.t'
++.*: Error: unrecognized opcode `vfwsub.wf v4,v8,fa2,v0.t'
++.*: Error: unrecognized opcode `vfwmul.vv v4,v8,v12'
++.*: Error: unrecognized opcode `vfwmul.vf v4,v8,fa2'
++.*: Error: unrecognized opcode `vfwmul.vv v4,v8,v12,v0.t'
++.*: Error: unrecognized opcode `vfwmul.vf v4,v8,fa2,v0.t'
++.*: Error: unrecognized opcode `vfwmacc.vv v4,v12,v8'
++.*: Error: unrecognized opcode `vfwmacc.vf v4,fa2,v8'
++.*: Error: unrecognized opcode `vfwnmacc.vv v4,v12,v8'
++.*: Error: unrecognized opcode `vfwnmacc.vf v4,fa2,v8'
++.*: Error: unrecognized opcode `vfwmsac.vv v4,v12,v8'
++.*: Error: unrecognized opcode `vfwmsac.vf v4,fa2,v8'
++.*: Error: unrecognized opcode `vfwnmsac.vv v4,v12,v8'
++.*: Error: unrecognized opcode `vfwnmsac.vf v4,fa2,v8'
++.*: Error: unrecognized opcode `vfwmacc.vv v4,v12,v8,v0.t'
++.*: Error: unrecognized opcode `vfwmacc.vf v4,fa2,v8,v0.t'
++.*: Error: unrecognized opcode `vfwnmacc.vv v4,v12,v8,v0.t'
++.*: Error: unrecognized opcode `vfwnmacc.vf v4,fa2,v8,v0.t'
++.*: Error: unrecognized opcode `vfwmsac.vv v4,v12,v8,v0.t'
++.*: Error: unrecognized opcode `vfwmsac.vf v4,fa2,v8,v0.t'
++.*: Error: unrecognized opcode `vfwnmsac.vv v4,v12,v8,v0.t'
++.*: Error: unrecognized opcode `vfwnmsac.vf v4,fa2,v8,v0.t'
++.*: Error: unrecognized opcode `vfsqrt.v v4,v8'
++.*: Error: unrecognized opcode `vfsqrt.v v4,v8,v0.t'
++.*: Error: unrecognized opcode `vfrsqrte7.v v4,v8'
++.*: Error: unrecognized opcode `vfrsqrte7.v v4,v8,v0.t'
++.*: Error: unrecognized opcode `vfrsqrt7.v v4,v8'
++.*: Error: unrecognized opcode `vfrsqrt7.v v4,v8,v0.t'
++.*: Error: unrecognized opcode `vfrece7.v v4,v8'
++.*: Error: unrecognized opcode `vfrece7.v v4,v8,v0.t'
++.*: Error: unrecognized opcode `vfrec7.v v4,v8'
++.*: Error: unrecognized opcode `vfrec7.v v4,v8,v0.t'
++.*: Error: unrecognized opcode `vfclass.v v4,v8'
++.*: Error: unrecognized opcode `vfclass.v v4,v8,v0.t'
++.*: Error: unrecognized opcode `vfcvt.xu.f.v v4,v8'
++.*: Error: unrecognized opcode `vfcvt.x.f.v v4,v8'
++.*: Error: unrecognized opcode `vfcvt.rtz.xu.f.v v4,v8'
++.*: Error: unrecognized opcode `vfcvt.rtz.x.f.v v4,v8'
++.*: Error: unrecognized opcode `vfcvt.f.xu.v v4,v8'
++.*: Error: unrecognized opcode `vfcvt.f.x.v v4,v8'
++.*: Error: unrecognized opcode `vfcvt.xu.f.v v4,v8,v0.t'
++.*: Error: unrecognized opcode `vfcvt.x.f.v v4,v8,v0.t'
++.*: Error: unrecognized opcode `vfcvt.rtz.xu.f.v v4,v8,v0.t'
++.*: Error: unrecognized opcode `vfcvt.rtz.x.f.v v4,v8,v0.t'
++.*: Error: unrecognized opcode `vfcvt.f.xu.v v4,v8,v0.t'
++.*: Error: unrecognized opcode `vfcvt.f.x.v v4,v8,v0.t'
++.*: Error: unrecognized opcode `vfwcvt.xu.f.v v4,v8'
++.*: Error: unrecognized opcode `vfwcvt.x.f.v v4,v8'
++.*: Error: unrecognized opcode `vfwcvt.rtz.xu.f.v v4,v8'
++.*: Error: unrecognized opcode `vfwcvt.rtz.x.f.v v4,v8'
++.*: Error: unrecognized opcode `vfwcvt.f.xu.v v4,v8'
++.*: Error: unrecognized opcode `vfwcvt.f.x.v v4,v8'
++.*: Error: unrecognized opcode `vfwcvt.f.f.v v4,v8'
++.*: Error: unrecognized opcode `vfwcvt.xu.f.v v4,v8,v0.t'
++.*: Error: unrecognized opcode `vfwcvt.x.f.v v4,v8,v0.t'
++.*: Error: unrecognized opcode `vfwcvt.rtz.xu.f.v v4,v8,v0.t'
++.*: Error: unrecognized opcode `vfwcvt.rtz.x.f.v v4,v8,v0.t'
++.*: Error: unrecognized opcode `vfwcvt.f.xu.v v4,v8,v0.t'
++.*: Error: unrecognized opcode `vfwcvt.f.x.v v4,v8,v0.t'
++.*: Error: unrecognized opcode `vfwcvt.f.f.v v4,v8,v0.t'
++.*: Error: unrecognized opcode `vfncvt.xu.f.w v4,v8'
++.*: Error: unrecognized opcode `vfncvt.x.f.w v4,v8'
++.*: Error: unrecognized opcode `vfncvt.rtz.xu.f.w v4,v8'
++.*: Error: unrecognized opcode `vfncvt.rtz.x.f.w v4,v8'
++.*: Error: unrecognized opcode `vfncvt.f.xu.w v4,v8'
++.*: Error: unrecognized opcode `vfncvt.f.x.w v4,v8'
++.*: Error: unrecognized opcode `vfncvt.f.f.w v4,v8'
++.*: Error: unrecognized opcode `vfncvt.rod.f.f.w v4,v8'
++.*: Error: unrecognized opcode `vfncvt.xu.f.w v4,v8,v0.t'
++.*: Error: unrecognized opcode `vfncvt.x.f.w v4,v8,v0.t'
++.*: Error: unrecognized opcode `vfncvt.rtz.xu.f.w v4,v8,v0.t'
++.*: Error: unrecognized opcode `vfncvt.rtz.x.f.w v4,v8,v0.t'
++.*: Error: unrecognized opcode `vfncvt.f.xu.w v4,v8,v0.t'
++.*: Error: unrecognized opcode `vfncvt.f.x.w v4,v8,v0.t'
++.*: Error: unrecognized opcode `vfncvt.f.f.w v4,v8,v0.t'
++.*: Error: unrecognized opcode `vfncvt.rod.f.f.w v4,v8,v0.t'
++.*: Error: unrecognized opcode `vredsum.vs v4,v8,v12'
++.*: Error: unrecognized opcode `vredmaxu.vs v4,v8,v8'
++.*: Error: unrecognized opcode `vredmax.vs v4,v8,v8'
++.*: Error: unrecognized opcode `vredminu.vs v4,v8,v8'
++.*: Error: unrecognized opcode `vredmin.vs v4,v8,v8'
++.*: Error: unrecognized opcode `vredand.vs v4,v8,v12'
++.*: Error: unrecognized opcode `vredor.vs v4,v8,v12'
++.*: Error: unrecognized opcode `vredxor.vs v4,v8,v12'
++.*: Error: unrecognized opcode `vredsum.vs v4,v8,v12,v0.t'
++.*: Error: unrecognized opcode `vredmaxu.vs v4,v8,v8,v0.t'
++.*: Error: unrecognized opcode `vredmax.vs v4,v8,v8,v0.t'
++.*: Error: unrecognized opcode `vredminu.vs v4,v8,v8,v0.t'
++.*: Error: unrecognized opcode `vredmin.vs v4,v8,v8,v0.t'
++.*: Error: unrecognized opcode `vredand.vs v4,v8,v12,v0.t'
++.*: Error: unrecognized opcode `vredor.vs v4,v8,v12,v0.t'
++.*: Error: unrecognized opcode `vredxor.vs v4,v8,v12,v0.t'
++.*: Error: unrecognized opcode `vwredsumu.vs v4,v8,v12'
++.*: Error: unrecognized opcode `vwredsum.vs v4,v8,v12'
++.*: Error: unrecognized opcode `vwredsumu.vs v4,v8,v12,v0.t'
++.*: Error: unrecognized opcode `vwredsum.vs v4,v8,v12,v0.t'
++.*: Error: unrecognized opcode `vfredosum.vs v4,v8,v12'
++.*: Error: unrecognized opcode `vfredsum.vs v4,v8,v12'
++.*: Error: unrecognized opcode `vfredmax.vs v4,v8,v12'
++.*: Error: unrecognized opcode `vfredmin.vs v4,v8,v12'
++.*: Error: unrecognized opcode `vfredosum.vs v4,v8,v12,v0.t'
++.*: Error: unrecognized opcode `vfredsum.vs v4,v8,v12,v0.t'
++.*: Error: unrecognized opcode `vfredmax.vs v4,v8,v12,v0.t'
++.*: Error: unrecognized opcode `vfredmin.vs v4,v8,v12,v0.t'
++.*: Error: unrecognized opcode `vfwredosum.vs v4,v8,v12'
++.*: Error: unrecognized opcode `vfwredsum.vs v4,v8,v12'
++.*: Error: unrecognized opcode `vfwredosum.vs v4,v8,v12,v0.t'
++.*: Error: unrecognized opcode `vfwredsum.vs v4,v8,v12,v0.t'
++.*: Error: unrecognized opcode `vmsbf.m v4,v8'
++.*: Error: unrecognized opcode `vmsif.m v4,v8'
++.*: Error: unrecognized opcode `vmsof.m v4,v8'
++.*: Error: unrecognized opcode `viota.m v4,v8'
++.*: Error: unrecognized opcode `vid.v v4'
++.*: Error: unrecognized opcode `vmsbf.m v4,v8,v0.t'
++.*: Error: unrecognized opcode `vmsif.m v4,v8,v0.t'
++.*: Error: unrecognized opcode `vmsof.m v4,v8,v0.t'
++.*: Error: unrecognized opcode `viota.m v4,v8,v0.t'
++.*: Error: unrecognized opcode `vid.v v4,v0.t'
++.*: Error: unrecognized opcode `vrgatherei16.vv v4,v8,v12'
++.*: Error: unrecognized opcode `vrgatherei16.vv v4,v8,v12,v0.t'
++.*: Error: unrecognized opcode `vmv1r.v v1,v2'
++.*: Error: unrecognized opcode `vmv2r.v v2,v4'
++.*: Error: unrecognized opcode `vmv4r.v v4,v8'
++.*: Error: unrecognized opcode `vmv8r.v v0,v8'
+diff --git a/gas/testsuite/gas/riscv/vector-insns-fail-unsupport.s b/gas/testsuite/gas/riscv/vector-insns-fail-unsupport.s
+new file mode 100644
+index 0000000000..0116ac2c06
+--- /dev/null
++++ b/gas/testsuite/gas/riscv/vector-insns-fail-unsupport.s
+@@ -0,0 +1,1679 @@
++	
++	vsetivli a0, 0xb, 0
++	vsetivli a0, 0xb, 0x3ff
++	vsetivli a0, 0xb, e16, m2
++	vsetivli a0, 0xb, e256, m8
++	vsetivli a0, 0xb, e512, m8
++	vsetivli a0, 0xb, e1024, m8
++	vsetivli a0, 0xb, e1024, m1
++	vsetivli a0, 0xb, e1024, mf2
++	vsetivli a0, 0xb, e512, mf4
++	vsetivli a0, 0xb, e256, mf8
++	vsetivli a0, 0xb, e256, m2, ta
++	vsetivli a0, 0xb, e256, m2, ma
++	vsetivli a0, 0xb, e256, m2, tu
++	vsetivli a0, 0xb, e256, m2, mu
++	vsetivli a0, 0xb, e256, m2, ta, ma
++	vsetivli a0, 0xb, e256, m2, tu, ma
++	vsetivli a0, 0xb, e256, m2, ta, mu
++	vsetivli a0, 0xb, e256, m2, tu, mu
++
++	vle1.v v4, (a0)
++	vle1.v v4, 0(a0)
++	vse1.v v4, (a0)
++	vse1.v v4, 0(a0)
++
++	
++	vluxei8.v v4, (a0), v12
++	vluxei8.v v4, 0(a0), v12
++	vluxei8.v v4, (a0), v12, v0.t
++	vsuxei8.v v4, (a0), v12
++	vsuxei8.v v4, 0(a0), v12
++	vsuxei8.v v4, (a0), v12, v0.t
++
++	
++	vluxei16.v v4, (a0), v12
++	vluxei16.v v4, 0(a0), v12
++	vluxei16.v v4, (a0), v12, v0.t
++	vsuxei16.v v4, (a0), v12
++	vsuxei16.v v4, 0(a0), v12
++	vsuxei16.v v4, (a0), v12, v0.t
++
++	
++	vluxei32.v v4, (a0), v12
++	vluxei32.v v4, 0(a0), v12
++	vluxei32.v v4, (a0), v12, v0.t
++	vsuxei32.v v4, (a0), v12
++	vsuxei32.v v4, 0(a0), v12
++	vsuxei32.v v4, (a0), v12, v0.t
++
++	
++	vluxei64.v v4, (a0), v12
++	vluxei64.v v4, 0(a0), v12
++	vluxei64.v v4, (a0), v12, v0.t
++	vsuxei64.v v4, (a0), v12
++	vsuxei64.v v4, 0(a0), v12
++	vsuxei64.v v4, (a0), v12, v0.t
++
++	vle8ff.v v4, (a0)
++	vle8ff.v v4, 0(a0)
++	vle8ff.v v4, (a0), v0.t
++
++	vle16ff.v v4, (a0)
++	vle16ff.v v4, 0(a0)
++	vle16ff.v v4, (a0), v0.t
++
++	vle32ff.v v4, (a0)
++	vle32ff.v v4, 0(a0)
++	vle32ff.v v4, (a0), v0.t
++
++	vle64ff.v v4, (a0)
++	vle64ff.v v4, 0(a0)
++	vle64ff.v v4, (a0), v0.t
++
++	vlseg2e8.v v4, (a0)
++	vlseg2e8.v v4, 0(a0)
++	vlseg2e8.v v4, (a0), v0.t
++	vsseg2e8.v v4, (a0)
++	vsseg2e8.v v4, 0(a0)
++	vsseg2e8.v v4, (a0), v0.t
++
++	vlseg3e8.v v4, (a0)
++	vlseg3e8.v v4, 0(a0)
++	vlseg3e8.v v4, (a0), v0.t
++	vsseg3e8.v v4, (a0)
++	vsseg3e8.v v4, 0(a0)
++	vsseg3e8.v v4, (a0), v0.t
++
++	vlseg4e8.v v4, (a0)
++	vlseg4e8.v v4, 0(a0)
++	vlseg4e8.v v4, (a0), v0.t
++	vsseg4e8.v v4, (a0)
++	vsseg4e8.v v4, 0(a0)
++	vsseg4e8.v v4, (a0), v0.t
++
++	vlseg5e8.v v4, (a0)
++	vlseg5e8.v v4, 0(a0)
++	vlseg5e8.v v4, (a0), v0.t
++	vsseg5e8.v v4, (a0)
++	vsseg5e8.v v4, 0(a0)
++	vsseg5e8.v v4, (a0), v0.t
++
++	vlseg6e8.v v4, (a0)
++	vlseg6e8.v v4, 0(a0)
++	vlseg6e8.v v4, (a0), v0.t
++	vsseg6e8.v v4, (a0)
++	vsseg6e8.v v4, 0(a0)
++	vsseg6e8.v v4, (a0), v0.t
++
++	vlseg7e8.v v4, (a0)
++	vlseg7e8.v v4, 0(a0)
++	vlseg7e8.v v4, (a0), v0.t
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++
++	vlseg6e64ff.v v4, (a0)
++	vlseg6e64ff.v v4, 0(a0)
++	vlseg6e64ff.v v4, (a0), v0.t
++
++	vlseg7e64ff.v v4, (a0)
++	vlseg7e64ff.v v4, 0(a0)
++	vlseg7e64ff.v v4, (a0), v0.t
++
++	vlseg8e64ff.v v4, (a0)
++	vlseg8e64ff.v v4, 0(a0)
++	vlseg8e64ff.v v4, (a0), v0.t
++
++	vl1r.v v3, (a0)
++	vl1r.v v3, 0(a0)
++	vl1re8.v v3, (a0)
++	vl1re8.v v3, 0(a0)
++	vl1re16.v v3, (a0)
++	vl1re16.v v3, 0(a0)
++	vl1re32.v v3, (a0)
++	vl1re32.v v3, 0(a0)
++	vl1re64.v v3, (a0)
++	vl1re64.v v3, 0(a0)
++
++	vl2r.v v2, (a0)
++	vl2r.v v2, 0(a0)
++	vl2re8.v v2, (a0)
++	vl2re8.v v2, 0(a0)
++	vl2re16.v v2, (a0)
++	vl2re16.v v2, 0(a0)
++	vl2re32.v v2, (a0)
++	vl2re32.v v2, 0(a0)
++	vl2re64.v v2, (a0)
++	vl2re64.v v2, 0(a0)
++
++	vl4r.v v4, (a0)
++	vl4r.v v4, 0(a0)
++	vl4re8.v v4, (a0)
++	vl4re8.v v4, 0(a0)
++	vl4re16.v v4, (a0)
++	vl4re16.v v4, 0(a0)
++	vl4re32.v v4, (a0)
++	vl4re32.v v4, 0(a0)
++	vl4re64.v v4, (a0)
++	vl4re64.v v4, 0(a0)
++
++	vl8r.v v8, (a0)
++	vl8r.v v8, 0(a0)
++	vl8re8.v v8, (a0)
++	vl8re8.v v8, 0(a0)
++	vl8re16.v v8, (a0)
++	vl8re16.v v8, 0(a0)
++	vl8re32.v v8, (a0)
++	vl8re32.v v8, 0(a0)
++	vl8re64.v v8, (a0)
++	vl8re64.v v8, 0(a0)
++
++	vs1r.v v3, (a1)
++	vs1r.v v3, 0(a1)
++	vs2r.v v2, (a1)
++	vs2r.v v2, 0(a1)
++	vs4r.v v4, (a1)
++	vs4r.v v4, 0(a1)
++	vs8r.v v8, (a1)
++	vs8r.v v8, 0(a1)
++
++	vamoaddei8.v v4, (a1), v8, v4
++	vamoaddei8.v x0, (a1), v8, v4
++	vamoaddei8.v v4, (a1), v8, v4, v0.t
++	vamoaddei8.v x0, (a1), v8, v4, v0.t
++	vamoswapei8.v v4, (a1), v8, v4
++	vamoswapei8.v x0, (a1), v8, v4
++	vamoswapei8.v v4, (a1), v8, v4, v0.t
++	vamoswapei8.v x0, (a1), v8, v4, v0.t
++
++	vamoxorei8.v v4, (a1), v8, v4
++	vamoxorei8.v x0, (a1), v8, v4
++	vamoxorei8.v v4, (a1), v8, v4, v0.t
++	vamoxorei8.v x0, (a1), v8, v4, v0.t
++	vamoandei8.v v4, (a1), v8, v4
++	vamoandei8.v x0, (a1), v8, v4
++	vamoandei8.v v4, (a1), v8, v4, v0.t
++	vamoandei8.v x0, (a1), v8, v4, v0.t
++	vamoorei8.v v4, (a1), v8, v4
++	vamoorei8.v x0, (a1), v8, v4
++	vamoorei8.v v4, (a1), v8, v4, v0.t
++	vamoorei8.v x0, (a1), v8, v4, v0.t
++
++	vamominei8.v v4, (a1), v8, v4
++	vamominei8.v x0, (a1), v8, v4
++	vamominei8.v v4, (a1), v8, v4, v0.t
++	vamominei8.v x0, (a1), v8, v4, v0.t
++	vamomaxei8.v v4, (a1), v8, v4
++	vamomaxei8.v x0, (a1), v8, v4
++	vamomaxei8.v v4, (a1), v8, v4, v0.t
++	vamomaxei8.v x0, (a1), v8, v4, v0.t
++	vamominuei8.v v4, (a1), v8, v4
++	vamominuei8.v x0, (a1), v8, v4
++	vamominuei8.v v4, (a1), v8, v4, v0.t
++	vamominuei8.v x0, (a1), v8, v4, v0.t
++	vamomaxuei8.v v4, (a1), v8, v4
++	vamomaxuei8.v x0, (a1), v8, v4
++	vamomaxuei8.v v4, (a1), v8, v4, v0.t
++	vamomaxuei8.v x0, (a1), v8, v4, v0.t
++
++	vamoaddei8.v v4, 0(a1), v8, v4
++	vamoaddei8.v x0, 0(a1), v8, v4
++	vamoaddei8.v v4, 0(a1), v8, v4, v0.t
++	vamoaddei8.v x0, 0(a1), v8, v4, v0.t
++	vamoswapei8.v v4, 0(a1), v8, v4
++	vamoswapei8.v x0, 0(a1), v8, v4
++	vamoswapei8.v v4, 0(a1), v8, v4, v0.t
++	vamoswapei8.v x0, 0(a1), v8, v4, v0.t
++
++	vamoxorei8.v v4, 0(a1), v8, v4
++	vamoxorei8.v x0, 0(a1), v8, v4
++	vamoxorei8.v v4, 0(a1), v8, v4, v0.t
++	vamoxorei8.v x0, 0(a1), v8, v4, v0.t
++	vamoandei8.v v4, 0(a1), v8, v4
++	vamoandei8.v x0, 0(a1), v8, v4
++	vamoandei8.v v4, 0(a1), v8, v4, v0.t
++	vamoandei8.v x0, 0(a1), v8, v4, v0.t
++	vamoorei8.v v4, 0(a1), v8, v4
++	vamoorei8.v x0, 0(a1), v8, v4
++	vamoorei8.v v4, 0(a1), v8, v4, v0.t
++	vamoorei8.v x0, 0(a1), v8, v4, v0.t
++
++	vamominei8.v v4, 0(a1), v8, v4
++	vamominei8.v x0, 0(a1), v8, v4
++	vamominei8.v v4, 0(a1), v8, v4, v0.t
++	vamominei8.v x0, 0(a1), v8, v4, v0.t
++	vamomaxei8.v v4, 0(a1), v8, v4
++	vamomaxei8.v x0, 0(a1), v8, v4
++	vamomaxei8.v v4, 0(a1), v8, v4, v0.t
++	vamomaxei8.v x0, 0(a1), v8, v4, v0.t
++	vamominuei8.v v4, 0(a1), v8, v4
++	vamominuei8.v x0, 0(a1), v8, v4
++	vamominuei8.v v4, 0(a1), v8, v4, v0.t
++	vamominuei8.v x0, 0(a1), v8, v4, v0.t
++	vamomaxuei8.v v4, 0(a1), v8, v4
++	vamomaxuei8.v x0, 0(a1), v8, v4
++	vamomaxuei8.v v4, 0(a1), v8, v4, v0.t
++	vamomaxuei8.v x0, 0(a1), v8, v4, v0.t
++
++	vamoaddei16.v v4, (a1), v8, v4
++	vamoaddei16.v x0, (a1), v8, v4
++	vamoaddei16.v v4, (a1), v8, v4, v0.t
++	vamoaddei16.v x0, (a1), v8, v4, v0.t
++	vamoswapei16.v v4, (a1), v8, v4
++	vamoswapei16.v x0, (a1), v8, v4
++	vamoswapei16.v v4, (a1), v8, v4, v0.t
++	vamoswapei16.v x0, (a1), v8, v4, v0.t
++
++	vamoxorei16.v v4, (a1), v8, v4
++	vamoxorei16.v x0, (a1), v8, v4
++	vamoxorei16.v v4, (a1), v8, v4, v0.t
++	vamoxorei16.v x0, (a1), v8, v4, v0.t
++	vamoandei16.v v4, (a1), v8, v4
++	vamoandei16.v x0, (a1), v8, v4
++	vamoandei16.v v4, (a1), v8, v4, v0.t
++	vamoandei16.v x0, (a1), v8, v4, v0.t
++	vamoorei16.v v4, (a1), v8, v4
++	vamoorei16.v x0, (a1), v8, v4
++	vamoorei16.v v4, (a1), v8, v4, v0.t
++	vamoorei16.v x0, (a1), v8, v4, v0.t
++
++	vamominei16.v v4, (a1), v8, v4
++	vamominei16.v x0, (a1), v8, v4
++	vamominei16.v v4, (a1), v8, v4, v0.t
++	vamominei16.v x0, (a1), v8, v4, v0.t
++	vamomaxei16.v v4, (a1), v8, v4
++	vamomaxei16.v x0, (a1), v8, v4
++	vamomaxei16.v v4, (a1), v8, v4, v0.t
++	vamomaxei16.v x0, (a1), v8, v4, v0.t
++	vamominuei16.v v4, (a1), v8, v4
++	vamominuei16.v x0, (a1), v8, v4
++	vamominuei16.v v4, (a1), v8, v4, v0.t
++	vamominuei16.v x0, (a1), v8, v4, v0.t
++	vamomaxuei16.v v4, (a1), v8, v4
++	vamomaxuei16.v x0, (a1), v8, v4
++	vamomaxuei16.v v4, (a1), v8, v4, v0.t
++	vamomaxuei16.v x0, (a1), v8, v4, v0.t
++
++	vamoaddei16.v v4, 0(a1), v8, v4
++	vamoaddei16.v x0, 0(a1), v8, v4
++	vamoaddei16.v v4, 0(a1), v8, v4, v0.t
++	vamoaddei16.v x0, 0(a1), v8, v4, v0.t
++	vamoswapei16.v v4, 0(a1), v8, v4
++	vamoswapei16.v x0, 0(a1), v8, v4
++	vamoswapei16.v v4, 0(a1), v8, v4, v0.t
++	vamoswapei16.v x0, 0(a1), v8, v4, v0.t
++
++	vamoxorei16.v v4, 0(a1), v8, v4
++	vamoxorei16.v x0, 0(a1), v8, v4
++	vamoxorei16.v v4, 0(a1), v8, v4, v0.t
++	vamoxorei16.v x0, 0(a1), v8, v4, v0.t
++	vamoandei16.v v4, 0(a1), v8, v4
++	vamoandei16.v x0, 0(a1), v8, v4
++	vamoandei16.v v4, 0(a1), v8, v4, v0.t
++	vamoandei16.v x0, 0(a1), v8, v4, v0.t
++	vamoorei16.v v4, 0(a1), v8, v4
++	vamoorei16.v x0, 0(a1), v8, v4
++	vamoorei16.v v4, 0(a1), v8, v4, v0.t
++	vamoorei16.v x0, 0(a1), v8, v4, v0.t
++
++	vamominei16.v v4, 0(a1), v8, v4
++	vamominei16.v x0, 0(a1), v8, v4
++	vamominei16.v v4, 0(a1), v8, v4, v0.t
++	vamominei16.v x0, 0(a1), v8, v4, v0.t
++	vamomaxei16.v v4, 0(a1), v8, v4
++	vamomaxei16.v x0, 0(a1), v8, v4
++	vamomaxei16.v v4, 0(a1), v8, v4, v0.t
++	vamomaxei16.v x0, 0(a1), v8, v4, v0.t
++	vamominuei16.v v4, 0(a1), v8, v4
++	vamominuei16.v x0, 0(a1), v8, v4
++	vamominuei16.v v4, 0(a1), v8, v4, v0.t
++	vamominuei16.v x0, 0(a1), v8, v4, v0.t
++	vamomaxuei16.v v4, 0(a1), v8, v4
++	vamomaxuei16.v x0, 0(a1), v8, v4
++	vamomaxuei16.v v4, 0(a1), v8, v4, v0.t
++	vamomaxuei16.v x0, 0(a1), v8, v4, v0.t
++
++	vamoaddei32.v v4, (a1), v8, v4
++	vamoaddei32.v x0, (a1), v8, v4
++	vamoaddei32.v v4, (a1), v8, v4, v0.t
++	vamoaddei32.v x0, (a1), v8, v4, v0.t
++	vamoswapei32.v v4, (a1), v8, v4
++	vamoswapei32.v x0, (a1), v8, v4
++	vamoswapei32.v v4, (a1), v8, v4, v0.t
++	vamoswapei32.v x0, (a1), v8, v4, v0.t
++
++	vamoxorei32.v v4, (a1), v8, v4
++	vamoxorei32.v x0, (a1), v8, v4
++	vamoxorei32.v v4, (a1), v8, v4, v0.t
++	vamoxorei32.v x0, (a1), v8, v4, v0.t
++	vamoandei32.v v4, (a1), v8, v4
++	vamoandei32.v x0, (a1), v8, v4
++	vamoandei32.v v4, (a1), v8, v4, v0.t
++	vamoandei32.v x0, (a1), v8, v4, v0.t
++	vamoorei32.v v4, (a1), v8, v4
++	vamoorei32.v x0, (a1), v8, v4
++	vamoorei32.v v4, (a1), v8, v4, v0.t
++	vamoorei32.v x0, (a1), v8, v4, v0.t
++
++	vamominei32.v v4, (a1), v8, v4
++	vamominei32.v x0, (a1), v8, v4
++	vamominei32.v v4, (a1), v8, v4, v0.t
++	vamominei32.v x0, (a1), v8, v4, v0.t
++	vamomaxei32.v v4, (a1), v8, v4
++	vamomaxei32.v x0, (a1), v8, v4
++	vamomaxei32.v v4, (a1), v8, v4, v0.t
++	vamomaxei32.v x0, (a1), v8, v4, v0.t
++	vamominuei32.v v4, (a1), v8, v4
++	vamominuei32.v x0, (a1), v8, v4
++	vamominuei32.v v4, (a1), v8, v4, v0.t
++	vamominuei32.v x0, (a1), v8, v4, v0.t
++	vamomaxuei32.v v4, (a1), v8, v4
++	vamomaxuei32.v x0, (a1), v8, v4
++	vamomaxuei32.v v4, (a1), v8, v4, v0.t
++	vamomaxuei32.v x0, (a1), v8, v4, v0.t
++
++	vamoaddei32.v v4, 0(a1), v8, v4
++	vamoaddei32.v x0, 0(a1), v8, v4
++	vamoaddei32.v v4, 0(a1), v8, v4, v0.t
++	vamoaddei32.v x0, 0(a1), v8, v4, v0.t
++	vamoswapei32.v v4, 0(a1), v8, v4
++	vamoswapei32.v x0, 0(a1), v8, v4
++	vamoswapei32.v v4, 0(a1), v8, v4, v0.t
++	vamoswapei32.v x0, 0(a1), v8, v4, v0.t
++
++	vamoxorei32.v v4, 0(a1), v8, v4
++	vamoxorei32.v x0, 0(a1), v8, v4
++	vamoxorei32.v v4, 0(a1), v8, v4, v0.t
++	vamoxorei32.v x0, 0(a1), v8, v4, v0.t
++	vamoandei32.v v4, 0(a1), v8, v4
++	vamoandei32.v x0, 0(a1), v8, v4
++	vamoandei32.v v4, 0(a1), v8, v4, v0.t
++	vamoandei32.v x0, 0(a1), v8, v4, v0.t
++	vamoorei32.v v4, 0(a1), v8, v4
++	vamoorei32.v x0, 0(a1), v8, v4
++	vamoorei32.v v4, 0(a1), v8, v4, v0.t
++	vamoorei32.v x0, 0(a1), v8, v4, v0.t
++
++	vamominei32.v v4, 0(a1), v8, v4
++	vamominei32.v x0, 0(a1), v8, v4
++	vamominei32.v v4, 0(a1), v8, v4, v0.t
++	vamominei32.v x0, 0(a1), v8, v4, v0.t
++	vamomaxei32.v v4, 0(a1), v8, v4
++	vamomaxei32.v x0, 0(a1), v8, v4
++	vamomaxei32.v v4, 0(a1), v8, v4, v0.t
++	vamomaxei32.v x0, 0(a1), v8, v4, v0.t
++	vamominuei32.v v4, 0(a1), v8, v4
++	vamominuei32.v x0, 0(a1), v8, v4
++	vamominuei32.v v4, 0(a1), v8, v4, v0.t
++	vamominuei32.v x0, 0(a1), v8, v4, v0.t
++	vamomaxuei32.v v4, 0(a1), v8, v4
++	vamomaxuei32.v x0, 0(a1), v8, v4
++	vamomaxuei32.v v4, 0(a1), v8, v4, v0.t
++	vamomaxuei32.v x0, 0(a1), v8, v4, v0.t
++
++	vamoaddei64.v v4, (a1), v8, v4
++	vamoaddei64.v x0, (a1), v8, v4
++	vamoaddei64.v v4, (a1), v8, v4, v0.t
++	vamoaddei64.v x0, (a1), v8, v4, v0.t
++	vamoswapei64.v v4, (a1), v8, v4
++	vamoswapei64.v x0, (a1), v8, v4
++	vamoswapei64.v v4, (a1), v8, v4, v0.t
++	vamoswapei64.v x0, (a1), v8, v4, v0.t
++
++	vamoxorei64.v v4, (a1), v8, v4
++	vamoxorei64.v x0, (a1), v8, v4
++	vamoxorei64.v v4, (a1), v8, v4, v0.t
++	vamoxorei64.v x0, (a1), v8, v4, v0.t
++	vamoandei64.v v4, (a1), v8, v4
++	vamoandei64.v x0, (a1), v8, v4
++	vamoandei64.v v4, (a1), v8, v4, v0.t
++	vamoandei64.v x0, (a1), v8, v4, v0.t
++	vamoorei64.v v4, (a1), v8, v4
++	vamoorei64.v x0, (a1), v8, v4
++	vamoorei64.v v4, (a1), v8, v4, v0.t
++	vamoorei64.v x0, (a1), v8, v4, v0.t
++
++	vamominei64.v v4, (a1), v8, v4
++	vamominei64.v x0, (a1), v8, v4
++	vamominei64.v v4, (a1), v8, v4, v0.t
++	vamominei64.v x0, (a1), v8, v4, v0.t
++	vamomaxei64.v v4, (a1), v8, v4
++	vamomaxei64.v x0, (a1), v8, v4
++	vamomaxei64.v v4, (a1), v8, v4, v0.t
++	vamomaxei64.v x0, (a1), v8, v4, v0.t
++	vamominuei64.v v4, (a1), v8, v4
++	vamominuei64.v x0, (a1), v8, v4
++	vamominuei64.v v4, (a1), v8, v4, v0.t
++	vamominuei64.v x0, (a1), v8, v4, v0.t
++	vamomaxuei64.v v4, (a1), v8, v4
++	vamomaxuei64.v x0, (a1), v8, v4
++	vamomaxuei64.v v4, (a1), v8, v4, v0.t
++	vamomaxuei64.v x0, (a1), v8, v4, v0.t
++
++	vamoaddei64.v v4, 0(a1), v8, v4
++	vamoaddei64.v x0, 0(a1), v8, v4
++	vamoaddei64.v v4, 0(a1), v8, v4, v0.t
++	vamoaddei64.v x0, 0(a1), v8, v4, v0.t
++	vamoswapei64.v v4, 0(a1), v8, v4
++	vamoswapei64.v x0, 0(a1), v8, v4
++	vamoswapei64.v v4, 0(a1), v8, v4, v0.t
++	vamoswapei64.v x0, 0(a1), v8, v4, v0.t
++
++	vamoxorei64.v v4, 0(a1), v8, v4
++	vamoxorei64.v x0, 0(a1), v8, v4
++	vamoxorei64.v v4, 0(a1), v8, v4, v0.t
++	vamoxorei64.v x0, 0(a1), v8, v4, v0.t
++	vamoandei64.v v4, 0(a1), v8, v4
++	vamoandei64.v x0, 0(a1), v8, v4
++	vamoandei64.v v4, 0(a1), v8, v4, v0.t
++	vamoandei64.v x0, 0(a1), v8, v4, v0.t
++	vamoorei64.v v4, 0(a1), v8, v4
++	vamoorei64.v x0, 0(a1), v8, v4
++	vamoorei64.v v4, 0(a1), v8, v4, v0.t
++	vamoorei64.v x0, 0(a1), v8, v4, v0.t
++
++	vamominei64.v v4, 0(a1), v8, v4
++	vamominei64.v x0, 0(a1), v8, v4
++	vamominei64.v v4, 0(a1), v8, v4, v0.t
++	vamominei64.v x0, 0(a1), v8, v4, v0.t
++	vamomaxei64.v v4, 0(a1), v8, v4
++	vamomaxei64.v x0, 0(a1), v8, v4
++	vamomaxei64.v v4, 0(a1), v8, v4, v0.t
++	vamomaxei64.v x0, 0(a1), v8, v4, v0.t
++	vamominuei64.v v4, 0(a1), v8, v4
++	vamominuei64.v x0, 0(a1), v8, v4
++	vamominuei64.v v4, 0(a1), v8, v4, v0.t
++	vamominuei64.v x0, 0(a1), v8, v4, v0.t
++	vamomaxuei64.v v4, 0(a1), v8, v4
++	vamomaxuei64.v x0, 0(a1), v8, v4
++	vamomaxuei64.v v4, 0(a1), v8, v4, v0.t
++	vamomaxuei64.v x0, 0(a1), v8, v4, v0.t
++	# Aliases
++	vwcvt.x.x.v v4, v8
++	vwcvtu.x.x.v v4, v8
++	vwcvt.x.x.v v4, v8, v0.t
++	vwcvtu.x.x.v v4, v8, v0.t
++
++	vwaddu.vv v4, v8, v12
++	vwaddu.vx v4, v8, a1
++	vwaddu.vv v4, v8, v12, v0.t
++	vwaddu.vx v4, v8, a1, v0.t
++	vwsubu.vv v4, v8, v12
++	vwsubu.vx v4, v8, a1
++	vwsubu.vv v4, v8, v12, v0.t
++	vwsubu.vx v4, v8, a1, v0.t
++	vwadd.vv v4, v8, v12
++	vwadd.vx v4, v8, a1
++	vwadd.vv v4, v8, v12, v0.t
++	vwadd.vx v4, v8, a1, v0.t
++	vwsub.vv v4, v8, v12
++	vwsub.vx v4, v8, a1
++	vwsub.vv v4, v8, v12, v0.t
++	vwsub.vx v4, v8, a1, v0.t
++	vwaddu.wv v4, v8, v12
++	vwaddu.wx v4, v8, a1
++	vwaddu.wv v4, v8, v12, v0.t
++	vwaddu.wx v4, v8, a1, v0.t
++	vwsubu.wv v4, v8, v12
++	vwsubu.wx v4, v8, a1
++	vwsubu.wv v4, v8, v12, v0.t
++	vwsubu.wx v4, v8, a1, v0.t
++	vwadd.wv v4, v8, v12
++	vwadd.wx v4, v8, a1
++	vwadd.wv v4, v8, v12, v0.t
++	vwadd.wx v4, v8, a1, v0.t
++	vwsub.wv v4, v8, v12
++	vwsub.wx v4, v8, a1
++	vwsub.wv v4, v8, v12, v0.t
++	vwsub.wx v4, v8, a1, v0.t
++
++	vsll.vv v4, v8, v12
++	vsll.vx v4, v8, a1
++	vsll.vi v4, v8, 1
++	vsll.vi v4, v8, 31
++	vsll.vv v4, v8, v12, v0.t
++	vsll.vx v4, v8, a1, v0.t
++	vsll.vi v4, v8, 1, v0.t
++	vsll.vi v4, v8, 31, v0.t
++	vsrl.vv v4, v8, v12
++	vsrl.vx v4, v8, a1
++	vsrl.vi v4, v8, 1
++	vsrl.vi v4, v8, 31
++	vsrl.vv v4, v8, v12, v0.t
++	vsrl.vx v4, v8, a1, v0.t
++	vsrl.vi v4, v8, 1, v0.t
++	vsrl.vi v4, v8, 31, v0.t
++	vsra.vv v4, v8, v12
++	vsra.vx v4, v8, a1
++	vsra.vi v4, v8, 1
++	vsra.vi v4, v8, 31
++	vsra.vv v4, v8, v12, v0.t
++	vsra.vx v4, v8, a1, v0.t
++	vsra.vi v4, v8, 1, v0.t
++	vsra.vi v4, v8, 31, v0.t
++
++	# Aliases
++	vncvt.x.x.w v4, v8
++	vncvt.x.x.w v4, v8, v0.t
++
++	vnsrl.wv v4, v8, v12
++	vnsrl.wx v4, v8, a1
++	vnsrl.wi v4, v8, 1
++	vnsrl.wi v4, v8, 31
++	vnsrl.wv v4, v8, v12, v0.t
++	vnsrl.wx v4, v8, a1, v0.t
++	vnsrl.wi v4, v8, 1, v0.t
++	vnsrl.wi v4, v8, 31, v0.t
++	vnsra.wv v4, v8, v12
++	vnsra.wx v4, v8, a1
++	vnsra.wi v4, v8, 1
++	vnsra.wi v4, v8, 31
++	vnsra.wv v4, v8, v12, v0.t
++	vnsra.wx v4, v8, a1, v0.t
++	vnsra.wi v4, v8, 1, v0.t
++	vnsra.wi v4, v8, 31, v0.t
++
++	vwmul.vv v4, v8, v12
++	vwmul.vx v4, v8, a1
++	vwmul.vv v4, v8, v12, v0.t
++	vwmul.vx v4, v8, a1, v0.t
++	vwmulu.vv v4, v8, v12
++	vwmulu.vx v4, v8, a1
++	vwmulu.vv v4, v8, v12, v0.t
++	vwmulu.vx v4, v8, a1, v0.t
++	vwmulsu.vv v4, v8, v12
++	vwmulsu.vx v4, v8, a1
++	vwmulsu.vv v4, v8, v12, v0.t
++	vwmulsu.vx v4, v8, a1, v0.t
++
++	vwmaccu.vv v4, v12, v8
++	vwmaccu.vx v4, a1, v8
++	vwmaccu.vv v4, v12, v8, v0.t
++	vwmaccu.vx v4, a1, v8, v0.t
++	vwmacc.vv v4, v12, v8
++	vwmacc.vx v4, a1, v8
++	vwmacc.vv v4, v12, v8, v0.t
++	vwmacc.vx v4, a1, v8, v0.t
++	vwmaccsu.vv v4, v12, v8
++	vwmaccsu.vx v4, a1, v8
++	vwmaccsu.vv v4, v12, v8, v0.t
++	vwmaccsu.vx v4, a1, v8, v0.t
++	vwmaccus.vx v4, a1, v8
++	vwmaccus.vx v4, a1, v8, v0.t
++
++	vsaddu.vv v4, v8, v12
++	vsaddu.vx v4, v8, a1
++	vsaddu.vi v4, v8, 15
++	vsaddu.vi v4, v8, -16
++	vsaddu.vv v4, v8, v12, v0.t
++	vsaddu.vx v4, v8, a1, v0.t
++	vsaddu.vi v4, v8, 15, v0.t
++	vsaddu.vi v4, v8, -16, v0.t
++	vsadd.vv v4, v8, v12
++	vsadd.vx v4, v8, a1
++	vsadd.vi v4, v8, 15
++	vsadd.vi v4, v8, -16
++	vsadd.vv v4, v8, v12, v0.t
++	vsadd.vx v4, v8, a1, v0.t
++	vsadd.vi v4, v8, 15, v0.t
++	vsadd.vi v4, v8, -16, v0.t
++	vssubu.vv v4, v8, v12
++	vssubu.vx v4, v8, a1
++	vssubu.vv v4, v8, v12, v0.t
++	vssubu.vx v4, v8, a1, v0.t
++	vssub.vv v4, v8, v12
++	vssub.vx v4, v8, a1
++	vssub.vv v4, v8, v12, v0.t
++	vssub.vx v4, v8, a1, v0.t
++
++	vaaddu.vv v4, v8, v12
++	vaaddu.vx v4, v8, a1
++	vaaddu.vv v4, v8, v12, v0.t
++	vaaddu.vx v4, v8, a1, v0.t
++	vaadd.vv v4, v8, v12
++	vaadd.vx v4, v8, a1
++	vaadd.vv v4, v8, v12, v0.t
++	vaadd.vx v4, v8, a1, v0.t
++	vasubu.vv v4, v8, v12
++	vasubu.vx v4, v8, a1
++	vasubu.vv v4, v8, v12, v0.t
++	vasubu.vx v4, v8, a1, v0.t
++	vasub.vv v4, v8, v12
++	vasub.vx v4, v8, a1
++	vasub.vv v4, v8, v12, v0.t
++	vasub.vx v4, v8, a1, v0.t
++
++	vsmul.vv v4, v8, v12
++	vsmul.vx v4, v8, a1
++	vsmul.vv v4, v8, v12, v0.t
++	vsmul.vx v4, v8, a1, v0.t
++
++	vssrl.vv v4, v8, v12
++	vssrl.vx v4, v8, a1
++	vssrl.vi v4, v8, 1
++	vssrl.vi v4, v8, 31
++	vssrl.vv v4, v8, v12, v0.t
++	vssrl.vx v4, v8, a1, v0.t
++	vssrl.vi v4, v8, 1, v0.t
++	vssrl.vi v4, v8, 31, v0.t
++	vssra.vv v4, v8, v12
++	vssra.vx v4, v8, a1
++	vssra.vi v4, v8, 1
++	vssra.vi v4, v8, 31
++	vssra.vv v4, v8, v12, v0.t
++	vssra.vx v4, v8, a1, v0.t
++	vssra.vi v4, v8, 1, v0.t
++	vssra.vi v4, v8, 31, v0.t
++
++	vnclipu.wv v4, v8, v12
++	vnclipu.wx v4, v8, a1
++	vnclipu.wi v4, v8, 1
++	vnclipu.wi v4, v8, 31
++	vnclipu.wv v4, v8, v12, v0.t
++	vnclipu.wx v4, v8, a1, v0.t
++	vnclipu.wi v4, v8, 1, v0.t
++	vnclipu.wi v4, v8, 31, v0.t
++	vnclip.wv v4, v8, v12
++	vnclip.wx v4, v8, a1
++	vnclip.wi v4, v8, 1
++	vnclip.wi v4, v8, 31
++	vnclip.wv v4, v8, v12, v0.t
++	vnclip.wx v4, v8, a1, v0.t
++	vnclip.wi v4, v8, 1, v0.t
++	vnclip.wi v4, v8, 31, v0.t
++
++	vfwadd.vv v4, v8, v12
++	vfwadd.vf v4, v8, fa2
++	vfwadd.vv v4, v8, v12, v0.t
++	vfwadd.vf v4, v8, fa2, v0.t
++	vfwsub.vv v4, v8, v12
++	vfwsub.vf v4, v8, fa2
++	vfwsub.vv v4, v8, v12, v0.t
++	vfwsub.vf v4, v8, fa2, v0.t
++	vfwadd.wv v4, v8, v12
++	vfwadd.wf v4, v8, fa2
++	vfwadd.wv v4, v8, v12, v0.t
++	vfwadd.wf v4, v8, fa2, v0.t
++	vfwsub.wv v4, v8, v12
++	vfwsub.wf v4, v8, fa2
++	vfwsub.wv v4, v8, v12, v0.t
++	vfwsub.wf v4, v8, fa2, v0.t
++
++	vfwmul.vv v4, v8, v12
++	vfwmul.vf v4, v8, fa2
++	vfwmul.vv v4, v8, v12, v0.t
++	vfwmul.vf v4, v8, fa2, v0.t
++
++	vfwmacc.vv v4, v12, v8
++	vfwmacc.vf v4, fa2, v8
++	vfwnmacc.vv v4, v12, v8
++	vfwnmacc.vf v4, fa2, v8
++	vfwmsac.vv v4, v12, v8
++	vfwmsac.vf v4, fa2, v8
++	vfwnmsac.vv v4, v12, v8
++	vfwnmsac.vf v4, fa2, v8
++	vfwmacc.vv v4, v12, v8, v0.t
++	vfwmacc.vf v4, fa2, v8, v0.t
++	vfwnmacc.vv v4, v12, v8, v0.t
++	vfwnmacc.vf v4, fa2, v8, v0.t
++	vfwmsac.vv v4, v12, v8, v0.t
++	vfwmsac.vf v4, fa2, v8, v0.t
++	vfwnmsac.vv v4, v12, v8, v0.t
++	vfwnmsac.vf v4, fa2, v8, v0.t
++
++	vfsqrt.v v4, v8
++	vfsqrt.v v4, v8, v0.t
++	vfrsqrte7.v v4, v8
++	vfrsqrte7.v v4, v8, v0.t
++	vfrsqrt7.v v4, v8
++	vfrsqrt7.v v4, v8, v0.t
++	vfrece7.v v4, v8
++	vfrece7.v v4, v8, v0.t
++	vfrec7.v v4, v8
++	vfrec7.v v4, v8, v0.t
++	vfclass.v v4, v8
++	vfclass.v v4, v8, v0.t
++	
++	vfcvt.xu.f.v v4, v8
++	vfcvt.x.f.v v4, v8
++	vfcvt.rtz.xu.f.v v4, v8
++	vfcvt.rtz.x.f.v v4, v8
++	vfcvt.f.xu.v v4, v8
++	vfcvt.f.x.v v4, v8
++	vfcvt.xu.f.v v4, v8, v0.t
++	vfcvt.x.f.v v4, v8, v0.t
++	vfcvt.rtz.xu.f.v v4, v8, v0.t
++	vfcvt.rtz.x.f.v v4, v8, v0.t
++	vfcvt.f.xu.v v4, v8, v0.t
++	vfcvt.f.x.v v4, v8, v0.t
++
++	vfwcvt.xu.f.v v4, v8
++	vfwcvt.x.f.v v4, v8
++	vfwcvt.rtz.xu.f.v v4, v8
++	vfwcvt.rtz.x.f.v v4, v8
++	vfwcvt.f.xu.v v4, v8
++	vfwcvt.f.x.v v4, v8
++	vfwcvt.f.f.v v4, v8
++	vfwcvt.xu.f.v v4, v8, v0.t
++	vfwcvt.x.f.v v4, v8, v0.t
++	vfwcvt.rtz.xu.f.v v4, v8, v0.t
++	vfwcvt.rtz.x.f.v v4, v8, v0.t
++	vfwcvt.f.xu.v v4, v8, v0.t
++	vfwcvt.f.x.v v4, v8, v0.t
++	vfwcvt.f.f.v v4, v8, v0.t
++
++	vfncvt.xu.f.w v4, v8
++	vfncvt.x.f.w v4, v8
++	vfncvt.rtz.xu.f.w v4, v8
++	vfncvt.rtz.x.f.w v4, v8
++	vfncvt.f.xu.w v4, v8
++	vfncvt.f.x.w v4, v8
++	vfncvt.f.f.w v4, v8
++	vfncvt.rod.f.f.w v4, v8
++	vfncvt.xu.f.w v4, v8, v0.t
++	vfncvt.x.f.w v4, v8, v0.t
++	vfncvt.rtz.xu.f.w v4, v8, v0.t
++	vfncvt.rtz.x.f.w v4, v8, v0.t
++	vfncvt.f.xu.w v4, v8, v0.t
++	vfncvt.f.x.w v4, v8, v0.t
++	vfncvt.f.f.w v4, v8, v0.t
++	vfncvt.rod.f.f.w v4, v8, v0.t
++
++	vredsum.vs v4, v8, v12
++	vredmaxu.vs v4, v8, v8
++	vredmax.vs v4, v8, v8
++	vredminu.vs v4, v8, v8
++	vredmin.vs v4, v8, v8
++	vredand.vs v4, v8, v12
++	vredor.vs v4, v8, v12
++	vredxor.vs v4, v8, v12
++	vredsum.vs v4, v8, v12, v0.t
++	vredmaxu.vs v4, v8, v8, v0.t
++	vredmax.vs v4, v8, v8, v0.t
++	vredminu.vs v4, v8, v8, v0.t
++	vredmin.vs v4, v8, v8, v0.t
++	vredand.vs v4, v8, v12, v0.t
++	vredor.vs v4, v8, v12, v0.t
++	vredxor.vs v4, v8, v12, v0.t
++
++	vwredsumu.vs v4, v8, v12
++	vwredsum.vs v4, v8, v12
++	vwredsumu.vs v4, v8, v12, v0.t
++	vwredsum.vs v4, v8, v12, v0.t
++
++	vfredosum.vs v4, v8, v12
++	vfredsum.vs v4, v8, v12
++	vfredmax.vs v4, v8, v12
++	vfredmin.vs v4, v8, v12
++	vfredosum.vs v4, v8, v12, v0.t
++	vfredsum.vs v4, v8, v12, v0.t
++	vfredmax.vs v4, v8, v12, v0.t
++	vfredmin.vs v4, v8, v12, v0.t
++
++	vfwredosum.vs v4, v8, v12
++	vfwredsum.vs v4, v8, v12
++	vfwredosum.vs v4, v8, v12, v0.t
++	vfwredsum.vs v4, v8, v12, v0.t
++
++	vmsbf.m v4, v8
++	vmsif.m v4, v8
++	vmsof.m v4, v8
++	viota.m v4, v8
++	vid.v v4
++	
++	vmsbf.m v4, v8, v0.t
++	vmsif.m v4, v8, v0.t
++	vmsof.m v4, v8, v0.t
++	viota.m v4, v8, v0.t
++	vid.v v4, v0.t
++
++	vrgatherei16.vv v4, v8, v12
++	vrgatherei16.vv v4, v8, v12, v0.t
++
++	vmv1r.v v1, v2
++	vmv2r.v v2, v4
++	vmv4r.v v4, v8
++	vmv8r.v v0, v8
+diff --git a/gas/testsuite/gas/riscv/vector-insns-vmsgtvx.d b/gas/testsuite/gas/riscv/vector-insns-vmsgtvx.d
+new file mode 100644
+index 0000000000..207a410c28
+--- /dev/null
++++ b/gas/testsuite/gas/riscv/vector-insns-vmsgtvx.d
+@@ -0,0 +1,29 @@
++#as: -march=rv32iv0p10
++#objdump: -dr
++
++.*:[ 	]+file format .*
++
++
++Disassembly of section .text:
++
++0+000 <.text>:
++[ 	]+[0-9a-f]+:[ 	]+6e85c257[ 	]+vmslt.vx[ 	]+v4,v8,a1
++[ 	]+[0-9a-f]+:[ 	]+76422257[ 	]+vmnot.m[ 	]+v4,v4
++[ 	]+[0-9a-f]+:[ 	]+6cc64457[ 	]+vmslt.vx[ 	]+v8,v12,a2,v0.t
++[ 	]+[0-9a-f]+:[ 	]+6e802457[ 	]+vmxor.mm[ 	]+v8,v8,v0
++[ 	]+[0-9a-f]+:[ 	]+6c85c657[ 	]+vmslt.vx[ 	]+v12,v8,a1,v0.t
++[ 	]+[0-9a-f]+:[ 	]+62062057[ 	]+vmandnot.mm[ 	]+v0,v0,v12
++[ 	]+[0-9a-f]+:[ 	]+6c85c657[ 	]+vmslt.vx[ 	]+v12,v8,a1,v0.t
++[ 	]+[0-9a-f]+:[ 	]+62062657[ 	]+vmandnot.mm[ 	]+v12,v0,v12
++[ 	]+[0-9a-f]+:[ 	]+62402257[ 	]+vmandnot.mm[ 	]+v4,v4,v0
++[ 	]+[0-9a-f]+:[ 	]+6ac22257[ 	]+vmor.mm[ 	]+v4,v12,v4
++[ 	]+[0-9a-f]+:[ 	]+6a85c257[ 	]+vmsltu.vx[ 	]+v4,v8,a1
++[ 	]+[0-9a-f]+:[ 	]+76422257[ 	]+vmnot.m[ 	]+v4,v4
++[ 	]+[0-9a-f]+:[ 	]+68c64457[ 	]+vmsltu.vx[ 	]+v8,v12,a2,v0.t
++[ 	]+[0-9a-f]+:[ 	]+6e802457[ 	]+vmxor.mm[ 	]+v8,v8,v0
++[ 	]+[0-9a-f]+:[ 	]+6885c657[ 	]+vmsltu.vx[ 	]+v12,v8,a1,v0.t
++[ 	]+[0-9a-f]+:[ 	]+62062057[ 	]+vmandnot.mm[ 	]+v0,v0,v12
++[ 	]+[0-9a-f]+:[ 	]+6885c657[ 	]+vmsltu.vx[ 	]+v12,v8,a1,v0.t
++[ 	]+[0-9a-f]+:[ 	]+62062657[ 	]+vmandnot.mm[ 	]+v12,v0,v12
++[ 	]+[0-9a-f]+:[ 	]+62402257[ 	]+vmandnot.mm[ 	]+v4,v4,v0
++[ 	]+[0-9a-f]+:[ 	]+6ac22257[ 	]+vmor.mm[ 	]+v4,v12,v4
+diff --git a/gas/testsuite/gas/riscv/vector-insns-vmsgtvx.s b/gas/testsuite/gas/riscv/vector-insns-vmsgtvx.s
+new file mode 100644
+index 0000000000..afbb7ccb36
+--- /dev/null
++++ b/gas/testsuite/gas/riscv/vector-insns-vmsgtvx.s
+@@ -0,0 +1,9 @@
++	vmsge.vx v4, v8, a1		# unmasked va >= x
++	vmsge.vx v8, v12, a2, v0.t	# masked va >= x, vd != v0
++	vmsge.vx v0, v8, a1, v0.t, v12	# masked va >= x, vd == v0
++	vmsge.vx v4, v8, a1, v0.t, v12	# masked va >= x, any vd
++
++	vmsgeu.vx v4, v8, a1		# unmasked va >= x
++	vmsgeu.vx v8, v12, a2, v0.t	# masked va >= x, vd != v0
++	vmsgeu.vx v0, v8, a1, v0.t, v12	# masked va >= x, vd == v0
++	vmsgeu.vx v4, v8, a1, v0.t, v12	# masked va >= x, any vd
+diff --git a/gas/testsuite/gas/riscv/vector-insns.d b/gas/testsuite/gas/riscv/vector-insns.d
+new file mode 100644
+index 0000000000..fe6a95cba5
+--- /dev/null
++++ b/gas/testsuite/gas/riscv/vector-insns.d
+@@ -0,0 +1,476 @@
++#as: -march=rv32iafv0p10
++#objdump: -dr
++
++.*:[ 	]+file format .*
++
++
++Disassembly of section .text:
++
++0+000 <.text>:
++[ 	]+[0-9a-f]+:[ 	]+80c5f557[ 	]+vsetvl[ 	]+a0,a1,a2
++[ 	]+[0-9a-f]+:[ 	]+0005f557[ 	]+vsetvli[ 	]+a0,a1,e8,m1,tu,mu
++[ 	]+[0-9a-f]+:[ 	]+7ff5f557[ 	]+vsetvli[ 	]+a0,a1,2047
++[ 	]+[0-9a-f]+:[ 	]+0095f557[ 	]+vsetvli[ 	]+a0,a1,e16,m2,tu,mu
++[ 	]+[0-9a-f]+:[ 	]+02b5f557[ 	]+vsetvli[ 	]+a0,a1,e256,m8,tu,mu
++[ 	]+[0-9a-f]+:[ 	]+0335f557[ 	]+vsetvli[ 	]+a0,a1,e512,m8,tu,mu
++[ 	]+[0-9a-f]+:[ 	]+03b5f557[ 	]+vsetvli[ 	]+a0,a1,e1024,m8,tu,mu
++[ 	]+[0-9a-f]+:[ 	]+0385f557[ 	]+vsetvli[ 	]+a0,a1,e1024,m1,tu,mu
++[ 	]+[0-9a-f]+:[ 	]+03f5f557[ 	]+vsetvli[ 	]+a0,a1,e1024,mf2,tu,mu
++[ 	]+[0-9a-f]+:[ 	]+0365f557[ 	]+vsetvli[ 	]+a0,a1,e512,mf4,tu,mu
++[ 	]+[0-9a-f]+:[ 	]+02d5f557[ 	]+vsetvli[ 	]+a0,a1,e256,mf8,tu,mu
++[ 	]+[0-9a-f]+:[ 	]+0695f557[ 	]+vsetvli[ 	]+a0,a1,e256,m2,ta,mu
++[ 	]+[0-9a-f]+:[ 	]+0a95f557[ 	]+vsetvli[ 	]+a0,a1,e256,m2,tu,ma
++[ 	]+[0-9a-f]+:[ 	]+0295f557[ 	]+vsetvli[ 	]+a0,a1,e256,m2,tu,mu
++[ 	]+[0-9a-f]+:[ 	]+0295f557[ 	]+vsetvli[ 	]+a0,a1,e256,m2,tu,mu
++[ 	]+[0-9a-f]+:[ 	]+0e95f557[ 	]+vsetvli[ 	]+a0,a1,e256,m2,ta,ma
++[ 	]+[0-9a-f]+:[ 	]+0a95f557[ 	]+vsetvli[ 	]+a0,a1,e256,m2,tu,ma
++[ 	]+[0-9a-f]+:[ 	]+0695f557[ 	]+vsetvli[ 	]+a0,a1,e256,m2,ta,mu
++[ 	]+[0-9a-f]+:[ 	]+0295f557[ 	]+vsetvli[ 	]+a0,a1,e256,m2,tu,mu
++[ 	]+[0-9a-f]+:[ 	]+02050207[ 	]+vle8.v[ 	]+v4,\(a0\)
++[ 	]+[0-9a-f]+:[ 	]+02050207[ 	]+vle8.v[ 	]+v4,\(a0\)
++[ 	]+[0-9a-f]+:[ 	]+00050207[ 	]+vle8.v[ 	]+v4,\(a0\),v0.t
++[ 	]+[0-9a-f]+:[ 	]+02050227[ 	]+vse8.v[ 	]+v4,\(a0\)
++[ 	]+[0-9a-f]+:[ 	]+02050227[ 	]+vse8.v[ 	]+v4,\(a0\)
++[ 	]+[0-9a-f]+:[ 	]+00050227[ 	]+vse8.v[ 	]+v4,\(a0\),v0.t
++[ 	]+[0-9a-f]+:[ 	]+02055207[ 	]+vle16.v[ 	]+v4,\(a0\)
++[ 	]+[0-9a-f]+:[ 	]+02055207[ 	]+vle16.v[ 	]+v4,\(a0\)
++[ 	]+[0-9a-f]+:[ 	]+00055207[ 	]+vle16.v[ 	]+v4,\(a0\),v0.t
++[ 	]+[0-9a-f]+:[ 	]+02055227[ 	]+vse16.v[ 	]+v4,\(a0\)
++[ 	]+[0-9a-f]+:[ 	]+02055227[ 	]+vse16.v[ 	]+v4,\(a0\)
++[ 	]+[0-9a-f]+:[ 	]+00055227[ 	]+vse16.v[ 	]+v4,\(a0\),v0.t
++[ 	]+[0-9a-f]+:[ 	]+02056207[ 	]+vle32.v[ 	]+v4,\(a0\)
++[ 	]+[0-9a-f]+:[ 	]+02056207[ 	]+vle32.v[ 	]+v4,\(a0\)
++[ 	]+[0-9a-f]+:[ 	]+00056207[ 	]+vle32.v[ 	]+v4,\(a0\),v0.t
++[ 	]+[0-9a-f]+:[ 	]+02056227[ 	]+vse32.v[ 	]+v4,\(a0\)
++[ 	]+[0-9a-f]+:[ 	]+02056227[ 	]+vse32.v[ 	]+v4,\(a0\)
++[ 	]+[0-9a-f]+:[ 	]+00056227[ 	]+vse32.v[ 	]+v4,\(a0\),v0.t
++[ 	]+[0-9a-f]+:[ 	]+02057207[ 	]+vle64.v[ 	]+v4,\(a0\)
++[ 	]+[0-9a-f]+:[ 	]+02057207[ 	]+vle64.v[ 	]+v4,\(a0\)
++[ 	]+[0-9a-f]+:[ 	]+00057207[ 	]+vle64.v[ 	]+v4,\(a0\),v0.t
++[ 	]+[0-9a-f]+:[ 	]+02057227[ 	]+vse64.v[ 	]+v4,\(a0\)
++[ 	]+[0-9a-f]+:[ 	]+02057227[ 	]+vse64.v[ 	]+v4,\(a0\)
++[ 	]+[0-9a-f]+:[ 	]+00057227[ 	]+vse64.v[ 	]+v4,\(a0\),v0.t
++[ 	]+[0-9a-f]+:[ 	]+0ab50207[ 	]+vlse8.v[ 	]+v4,\(a0\),a1
++[ 	]+[0-9a-f]+:[ 	]+0ab50207[ 	]+vlse8.v[ 	]+v4,\(a0\),a1
++[ 	]+[0-9a-f]+:[ 	]+08b50207[ 	]+vlse8.v[ 	]+v4,\(a0\),a1,v0.t
++[ 	]+[0-9a-f]+:[ 	]+0ab50227[ 	]+vsse8.v[ 	]+v4,\(a0\),a1
++[ 	]+[0-9a-f]+:[ 	]+0ab50227[ 	]+vsse8.v[ 	]+v4,\(a0\),a1
++[ 	]+[0-9a-f]+:[ 	]+08b50227[ 	]+vsse8.v[ 	]+v4,\(a0\),a1,v0.t
++[ 	]+[0-9a-f]+:[ 	]+0ab55207[ 	]+vlse16.v[ 	]+v4,\(a0\),a1
++[ 	]+[0-9a-f]+:[ 	]+0ab55207[ 	]+vlse16.v[ 	]+v4,\(a0\),a1
++[ 	]+[0-9a-f]+:[ 	]+08b55207[ 	]+vlse16.v[ 	]+v4,\(a0\),a1,v0.t
++[ 	]+[0-9a-f]+:[ 	]+0ab55227[ 	]+vsse16.v[ 	]+v4,\(a0\),a1
++[ 	]+[0-9a-f]+:[ 	]+0ab55227[ 	]+vsse16.v[ 	]+v4,\(a0\),a1
++[ 	]+[0-9a-f]+:[ 	]+08b55227[ 	]+vsse16.v[ 	]+v4,\(a0\),a1,v0.t
++[ 	]+[0-9a-f]+:[ 	]+0ab56207[ 	]+vlse32.v[ 	]+v4,\(a0\),a1
++[ 	]+[0-9a-f]+:[ 	]+0ab56207[ 	]+vlse32.v[ 	]+v4,\(a0\),a1
++[ 	]+[0-9a-f]+:[ 	]+08b56207[ 	]+vlse32.v[ 	]+v4,\(a0\),a1,v0.t
++[ 	]+[0-9a-f]+:[ 	]+0ab56227[ 	]+vsse32.v[ 	]+v4,\(a0\),a1
++[ 	]+[0-9a-f]+:[ 	]+0ab56227[ 	]+vsse32.v[ 	]+v4,\(a0\),a1
++[ 	]+[0-9a-f]+:[ 	]+08b56227[ 	]+vsse32.v[ 	]+v4,\(a0\),a1,v0.t
++[ 	]+[0-9a-f]+:[ 	]+0ab57207[ 	]+vlse64.v[ 	]+v4,\(a0\),a1
++[ 	]+[0-9a-f]+:[ 	]+0ab57207[ 	]+vlse64.v[ 	]+v4,\(a0\),a1
++[ 	]+[0-9a-f]+:[ 	]+08b57207[ 	]+vlse64.v[ 	]+v4,\(a0\),a1,v0.t
++[ 	]+[0-9a-f]+:[ 	]+0ab57227[ 	]+vsse64.v[ 	]+v4,\(a0\),a1
++[ 	]+[0-9a-f]+:[ 	]+0ab57227[ 	]+vsse64.v[ 	]+v4,\(a0\),a1
++[ 	]+[0-9a-f]+:[ 	]+08b57227[ 	]+vsse64.v[ 	]+v4,\(a0\),a1,v0.t
++[ 	]+[0-9a-f]+:[ 	]+0ec50207[ 	]+vloxei8.v[ 	]+v4,\(a0\),v12
++[ 	]+[0-9a-f]+:[ 	]+0ec50207[ 	]+vloxei8.v[ 	]+v4,\(a0\),v12
++[ 	]+[0-9a-f]+:[ 	]+0cc50207[ 	]+vloxei8.v[ 	]+v4,\(a0\),v12,v0.t
++[ 	]+[0-9a-f]+:[ 	]+0ec50227[ 	]+vsoxei8.v[ 	]+v4,\(a0\),v12
++[ 	]+[0-9a-f]+:[ 	]+0ec50227[ 	]+vsoxei8.v[ 	]+v4,\(a0\),v12
++[ 	]+[0-9a-f]+:[ 	]+0cc50227[ 	]+vsoxei8.v[ 	]+v4,\(a0\),v12,v0.t
++[ 	]+[0-9a-f]+:[ 	]+0ec55207[ 	]+vloxei16.v[ 	]+v4,\(a0\),v12
++[ 	]+[0-9a-f]+:[ 	]+0ec55207[ 	]+vloxei16.v[ 	]+v4,\(a0\),v12
++[ 	]+[0-9a-f]+:[ 	]+0cc55207[ 	]+vloxei16.v[ 	]+v4,\(a0\),v12,v0.t
++[ 	]+[0-9a-f]+:[ 	]+0ec55227[ 	]+vsoxei16.v[ 	]+v4,\(a0\),v12
++[ 	]+[0-9a-f]+:[ 	]+0ec55227[ 	]+vsoxei16.v[ 	]+v4,\(a0\),v12
++[ 	]+[0-9a-f]+:[ 	]+0cc55227[ 	]+vsoxei16.v[ 	]+v4,\(a0\),v12,v0.t
++[ 	]+[0-9a-f]+:[ 	]+0ec56207[ 	]+vloxei32.v[ 	]+v4,\(a0\),v12
++[ 	]+[0-9a-f]+:[ 	]+0ec56207[ 	]+vloxei32.v[ 	]+v4,\(a0\),v12
++[ 	]+[0-9a-f]+:[ 	]+0cc56207[ 	]+vloxei32.v[ 	]+v4,\(a0\),v12,v0.t
++[ 	]+[0-9a-f]+:[ 	]+0ec56227[ 	]+vsoxei32.v[ 	]+v4,\(a0\),v12
++[ 	]+[0-9a-f]+:[ 	]+0ec56227[ 	]+vsoxei32.v[ 	]+v4,\(a0\),v12
++[ 	]+[0-9a-f]+:[ 	]+0cc56227[ 	]+vsoxei32.v[ 	]+v4,\(a0\),v12,v0.t
++[ 	]+[0-9a-f]+:[ 	]+0ec57207[ 	]+vloxei64.v[ 	]+v4,\(a0\),v12
++[ 	]+[0-9a-f]+:[ 	]+0ec57207[ 	]+vloxei64.v[ 	]+v4,\(a0\),v12
++[ 	]+[0-9a-f]+:[ 	]+0cc57207[ 	]+vloxei64.v[ 	]+v4,\(a0\),v12,v0.t
++[ 	]+[0-9a-f]+:[ 	]+0ec57227[ 	]+vsoxei64.v[ 	]+v4,\(a0\),v12
++[ 	]+[0-9a-f]+:[ 	]+0ec57227[ 	]+vsoxei64.v[ 	]+v4,\(a0\),v12
++[ 	]+[0-9a-f]+:[ 	]+0cc57227[ 	]+vsoxei64.v[ 	]+v4,\(a0\),v12,v0.t
++[ 	]+[0-9a-f]+:[ 	]+0e804257[ 	]+vneg.v[ 	]+v4,v8
++[ 	]+[0-9a-f]+:[ 	]+0c804257[ 	]+vneg.v[ 	]+v4,v8,v0.t
++[ 	]+[0-9a-f]+:[ 	]+02860257[ 	]+vadd.vv[ 	]+v4,v8,v12
++[ 	]+[0-9a-f]+:[ 	]+0285c257[ 	]+vadd.vx[ 	]+v4,v8,a1
++[ 	]+[0-9a-f]+:[ 	]+0287b257[ 	]+vadd.vi[ 	]+v4,v8,15
++[ 	]+[0-9a-f]+:[ 	]+02883257[ 	]+vadd.vi[ 	]+v4,v8,-16
++[ 	]+[0-9a-f]+:[ 	]+00860257[ 	]+vadd.vv[ 	]+v4,v8,v12,v0.t
++[ 	]+[0-9a-f]+:[ 	]+0085c257[ 	]+vadd.vx[ 	]+v4,v8,a1,v0.t
++[ 	]+[0-9a-f]+:[ 	]+0087b257[ 	]+vadd.vi[ 	]+v4,v8,15,v0.t
++[ 	]+[0-9a-f]+:[ 	]+00883257[ 	]+vadd.vi[ 	]+v4,v8,-16,v0.t
++[ 	]+[0-9a-f]+:[ 	]+0a860257[ 	]+vsub.vv[ 	]+v4,v8,v12
++[ 	]+[0-9a-f]+:[ 	]+0a85c257[ 	]+vsub.vx[ 	]+v4,v8,a1
++[ 	]+[0-9a-f]+:[ 	]+0e85c257[ 	]+vrsub.vx[ 	]+v4,v8,a1
++[ 	]+[0-9a-f]+:[ 	]+0e87b257[ 	]+vrsub.vi[ 	]+v4,v8,15
++[ 	]+[0-9a-f]+:[ 	]+0e883257[ 	]+vrsub.vi[ 	]+v4,v8,-16
++[ 	]+[0-9a-f]+:[ 	]+08860257[ 	]+vsub.vv[ 	]+v4,v8,v12,v0.t
++[ 	]+[0-9a-f]+:[ 	]+0885c257[ 	]+vsub.vx[ 	]+v4,v8,a1,v0.t
++[ 	]+[0-9a-f]+:[ 	]+0c85c257[ 	]+vrsub.vx[ 	]+v4,v8,a1,v0.t
++[ 	]+[0-9a-f]+:[ 	]+0c87b257[ 	]+vrsub.vi[ 	]+v4,v8,15,v0.t
++[ 	]+[0-9a-f]+:[ 	]+0c883257[ 	]+vrsub.vi[ 	]+v4,v8,-16,v0.t
++[ 	]+[0-9a-f]+:[ 	]+4a832257[ 	]+vzext.vf2[ 	]+v4,v8
++[ 	]+[0-9a-f]+:[ 	]+48832257[ 	]+vzext.vf2[ 	]+v4,v8,v0.t
++[ 	]+[0-9a-f]+:[ 	]+4a83a257[ 	]+vsext.vf2[ 	]+v4,v8
++[ 	]+[0-9a-f]+:[ 	]+4883a257[ 	]+vsext.vf2[ 	]+v4,v8,v0.t
++[ 	]+[0-9a-f]+:[ 	]+4a822257[ 	]+vzext.vf4[ 	]+v4,v8
++[ 	]+[0-9a-f]+:[ 	]+48822257[ 	]+vzext.vf4[ 	]+v4,v8,v0.t
++[ 	]+[0-9a-f]+:[ 	]+4a82a257[ 	]+vsext.vf4[ 	]+v4,v8
++[ 	]+[0-9a-f]+:[ 	]+4882a257[ 	]+vsext.vf4[ 	]+v4,v8,v0.t
++[ 	]+[0-9a-f]+:[ 	]+4a812257[ 	]+vzext.vf8[ 	]+v4,v8
++[ 	]+[0-9a-f]+:[ 	]+48812257[ 	]+vzext.vf8[ 	]+v4,v8,v0.t
++[ 	]+[0-9a-f]+:[ 	]+4a81a257[ 	]+vsext.vf8[ 	]+v4,v8
++[ 	]+[0-9a-f]+:[ 	]+4881a257[ 	]+vsext.vf8[ 	]+v4,v8,v0.t
++[ 	]+[0-9a-f]+:[ 	]+40860257[ 	]+vadc.vvm[ 	]+v4,v8,v12,v0
++[ 	]+[0-9a-f]+:[ 	]+4085c257[ 	]+vadc.vxm[ 	]+v4,v8,a1,v0
++[ 	]+[0-9a-f]+:[ 	]+4087b257[ 	]+vadc.vim[ 	]+v4,v8,15,v0
++[ 	]+[0-9a-f]+:[ 	]+40883257[ 	]+vadc.vim[ 	]+v4,v8,-16,v0
++[ 	]+[0-9a-f]+:[ 	]+44860257[ 	]+vmadc.vvm[ 	]+v4,v8,v12,v0
++[ 	]+[0-9a-f]+:[ 	]+4485c257[ 	]+vmadc.vxm[ 	]+v4,v8,a1,v0
++[ 	]+[0-9a-f]+:[ 	]+4487b257[ 	]+vmadc.vim[ 	]+v4,v8,15,v0
++[ 	]+[0-9a-f]+:[ 	]+44883257[ 	]+vmadc.vim[ 	]+v4,v8,-16,v0
++[ 	]+[0-9a-f]+:[ 	]+46860257[ 	]+vmadc.vv[ 	]+v4,v8,v12
++[ 	]+[0-9a-f]+:[ 	]+4685c257[ 	]+vmadc.vx[ 	]+v4,v8,a1
++[ 	]+[0-9a-f]+:[ 	]+4687b257[ 	]+vmadc.vi[ 	]+v4,v8,15
++[ 	]+[0-9a-f]+:[ 	]+46883257[ 	]+vmadc.vi[ 	]+v4,v8,-16
++[ 	]+[0-9a-f]+:[ 	]+48860257[ 	]+vsbc.vvm[ 	]+v4,v8,v12,v0
++[ 	]+[0-9a-f]+:[ 	]+4885c257[ 	]+vsbc.vxm[ 	]+v4,v8,a1,v0
++[ 	]+[0-9a-f]+:[ 	]+4c860257[ 	]+vmsbc.vvm[ 	]+v4,v8,v12,v0
++[ 	]+[0-9a-f]+:[ 	]+4c85c257[ 	]+vmsbc.vxm[ 	]+v4,v8,a1,v0
++[ 	]+[0-9a-f]+:[ 	]+4e860257[ 	]+vmsbc.vv[ 	]+v4,v8,v12
++[ 	]+[0-9a-f]+:[ 	]+4e85c257[ 	]+vmsbc.vx[ 	]+v4,v8,a1
++[ 	]+[0-9a-f]+:[ 	]+2e8fb257[ 	]+vnot.v[ 	]+v4,v8
++[ 	]+[0-9a-f]+:[ 	]+2c8fb257[ 	]+vnot.v[ 	]+v4,v8,v0.t
++[ 	]+[0-9a-f]+:[ 	]+26860257[ 	]+vand.vv[ 	]+v4,v8,v12
++[ 	]+[0-9a-f]+:[ 	]+2685c257[ 	]+vand.vx[ 	]+v4,v8,a1
++[ 	]+[0-9a-f]+:[ 	]+2687b257[ 	]+vand.vi[ 	]+v4,v8,15
++[ 	]+[0-9a-f]+:[ 	]+26883257[ 	]+vand.vi[ 	]+v4,v8,-16
++[ 	]+[0-9a-f]+:[ 	]+24860257[ 	]+vand.vv[ 	]+v4,v8,v12,v0.t
++[ 	]+[0-9a-f]+:[ 	]+2485c257[ 	]+vand.vx[ 	]+v4,v8,a1,v0.t
++[ 	]+[0-9a-f]+:[ 	]+2487b257[ 	]+vand.vi[ 	]+v4,v8,15,v0.t
++[ 	]+[0-9a-f]+:[ 	]+24883257[ 	]+vand.vi[ 	]+v4,v8,-16,v0.t
++[ 	]+[0-9a-f]+:[ 	]+2a860257[ 	]+vor.vv[ 	]+v4,v8,v12
++[ 	]+[0-9a-f]+:[ 	]+2a85c257[ 	]+vor.vx[ 	]+v4,v8,a1
++[ 	]+[0-9a-f]+:[ 	]+2a87b257[ 	]+vor.vi[ 	]+v4,v8,15
++[ 	]+[0-9a-f]+:[ 	]+2a883257[ 	]+vor.vi[ 	]+v4,v8,-16
++[ 	]+[0-9a-f]+:[ 	]+28860257[ 	]+vor.vv[ 	]+v4,v8,v12,v0.t
++[ 	]+[0-9a-f]+:[ 	]+2885c257[ 	]+vor.vx[ 	]+v4,v8,a1,v0.t
++[ 	]+[0-9a-f]+:[ 	]+2887b257[ 	]+vor.vi[ 	]+v4,v8,15,v0.t
++[ 	]+[0-9a-f]+:[ 	]+28883257[ 	]+vor.vi[ 	]+v4,v8,-16,v0.t
++[ 	]+[0-9a-f]+:[ 	]+2e860257[ 	]+vxor.vv[ 	]+v4,v8,v12
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++[ 	]+[0-9a-f]+:[ 	]+a2865257[ 	]+vfmadd.vf[ 	]+v4,fa2,v8
++[ 	]+[0-9a-f]+:[ 	]+a6861257[ 	]+vfnmadd.vv[ 	]+v4,v12,v8
++[ 	]+[0-9a-f]+:[ 	]+a6865257[ 	]+vfnmadd.vf[ 	]+v4,fa2,v8
++[ 	]+[0-9a-f]+:[ 	]+aa861257[ 	]+vfmsub.vv[ 	]+v4,v12,v8
++[ 	]+[0-9a-f]+:[ 	]+aa865257[ 	]+vfmsub.vf[ 	]+v4,fa2,v8
++[ 	]+[0-9a-f]+:[ 	]+ae861257[ 	]+vfnmsub.vv[ 	]+v4,v12,v8
++[ 	]+[0-9a-f]+:[ 	]+ae865257[ 	]+vfnmsub.vf[ 	]+v4,fa2,v8
++[ 	]+[0-9a-f]+:[ 	]+a0861257[ 	]+vfmadd.vv[ 	]+v4,v12,v8,v0.t
++[ 	]+[0-9a-f]+:[ 	]+a0865257[ 	]+vfmadd.vf[ 	]+v4,fa2,v8,v0.t
++[ 	]+[0-9a-f]+:[ 	]+a4861257[ 	]+vfnmadd.vv[ 	]+v4,v12,v8,v0.t
++[ 	]+[0-9a-f]+:[ 	]+a4865257[ 	]+vfnmadd.vf[ 	]+v4,fa2,v8,v0.t
++[ 	]+[0-9a-f]+:[ 	]+a8861257[ 	]+vfmsub.vv[ 	]+v4,v12,v8,v0.t
++[ 	]+[0-9a-f]+:[ 	]+a8865257[ 	]+vfmsub.vf[ 	]+v4,fa2,v8,v0.t
++[ 	]+[0-9a-f]+:[ 	]+ac861257[ 	]+vfnmsub.vv[ 	]+v4,v12,v8,v0.t
++[ 	]+[0-9a-f]+:[ 	]+ac865257[ 	]+vfnmsub.vf[ 	]+v4,fa2,v8,v0.t
++[ 	]+[0-9a-f]+:[ 	]+b2861257[ 	]+vfmacc.vv[ 	]+v4,v12,v8
++[ 	]+[0-9a-f]+:[ 	]+b2865257[ 	]+vfmacc.vf[ 	]+v4,fa2,v8
++[ 	]+[0-9a-f]+:[ 	]+b6861257[ 	]+vfnmacc.vv[ 	]+v4,v12,v8
++[ 	]+[0-9a-f]+:[ 	]+b6865257[ 	]+vfnmacc.vf[ 	]+v4,fa2,v8
++[ 	]+[0-9a-f]+:[ 	]+ba861257[ 	]+vfmsac.vv[ 	]+v4,v12,v8
++[ 	]+[0-9a-f]+:[ 	]+ba865257[ 	]+vfmsac.vf[ 	]+v4,fa2,v8
++[ 	]+[0-9a-f]+:[ 	]+be861257[ 	]+vfnmsac.vv[ 	]+v4,v12,v8
++[ 	]+[0-9a-f]+:[ 	]+be865257[ 	]+vfnmsac.vf[ 	]+v4,fa2,v8
++[ 	]+[0-9a-f]+:[ 	]+b0861257[ 	]+vfmacc.vv[ 	]+v4,v12,v8,v0.t
++[ 	]+[0-9a-f]+:[ 	]+b0865257[ 	]+vfmacc.vf[ 	]+v4,fa2,v8,v0.t
++[ 	]+[0-9a-f]+:[ 	]+b4861257[ 	]+vfnmacc.vv[ 	]+v4,v12,v8,v0.t
++[ 	]+[0-9a-f]+:[ 	]+b4865257[ 	]+vfnmacc.vf[ 	]+v4,fa2,v8,v0.t
++[ 	]+[0-9a-f]+:[ 	]+b8861257[ 	]+vfmsac.vv[ 	]+v4,v12,v8,v0.t
++[ 	]+[0-9a-f]+:[ 	]+b8865257[ 	]+vfmsac.vf[ 	]+v4,fa2,v8,v0.t
++[ 	]+[0-9a-f]+:[ 	]+bc861257[ 	]+vfnmsac.vv[ 	]+v4,v12,v8,v0.t
++[ 	]+[0-9a-f]+:[ 	]+bc865257[ 	]+vfnmsac.vf[ 	]+v4,fa2,v8,v0.t
++[ 	]+[0-9a-f]+:[ 	]+12861257[ 	]+vfmin.vv[ 	]+v4,v8,v12
++[ 	]+[0-9a-f]+:[ 	]+12865257[ 	]+vfmin.vf[ 	]+v4,v8,fa2
++[ 	]+[0-9a-f]+:[ 	]+1a861257[ 	]+vfmax.vv[ 	]+v4,v8,v12
++[ 	]+[0-9a-f]+:[ 	]+1a865257[ 	]+vfmax.vf[ 	]+v4,v8,fa2
++[ 	]+[0-9a-f]+:[ 	]+10861257[ 	]+vfmin.vv[ 	]+v4,v8,v12,v0.t
++[ 	]+[0-9a-f]+:[ 	]+10865257[ 	]+vfmin.vf[ 	]+v4,v8,fa2,v0.t
++[ 	]+[0-9a-f]+:[ 	]+18861257[ 	]+vfmax.vv[ 	]+v4,v8,v12,v0.t
++[ 	]+[0-9a-f]+:[ 	]+18865257[ 	]+vfmax.vf[ 	]+v4,v8,fa2,v0.t
++[ 	]+[0-9a-f]+:[ 	]+26841257[ 	]+vfneg.v[ 	]+v4,v8
++[ 	]+[0-9a-f]+:[ 	]+24841257[ 	]+vfneg.v[ 	]+v4,v8,v0.t
++[ 	]+[0-9a-f]+:[ 	]+2a841257[ 	]+vfabs.v[ 	]+v4,v8
++[ 	]+[0-9a-f]+:[ 	]+28841257[ 	]+vfabs.v[ 	]+v4,v8,v0.t
++[ 	]+[0-9a-f]+:[ 	]+22861257[ 	]+vfsgnj.vv[ 	]+v4,v8,v12
++[ 	]+[0-9a-f]+:[ 	]+22865257[ 	]+vfsgnj.vf[ 	]+v4,v8,fa2
++[ 	]+[0-9a-f]+:[ 	]+26861257[ 	]+vfsgnjn.vv[ 	]+v4,v8,v12
++[ 	]+[0-9a-f]+:[ 	]+26865257[ 	]+vfsgnjn.vf[ 	]+v4,v8,fa2
++[ 	]+[0-9a-f]+:[ 	]+2a861257[ 	]+vfsgnjx.vv[ 	]+v4,v8,v12
++[ 	]+[0-9a-f]+:[ 	]+2a865257[ 	]+vfsgnjx.vf[ 	]+v4,v8,fa2
++[ 	]+[0-9a-f]+:[ 	]+20861257[ 	]+vfsgnj.vv[ 	]+v4,v8,v12,v0.t
++[ 	]+[0-9a-f]+:[ 	]+20865257[ 	]+vfsgnj.vf[ 	]+v4,v8,fa2,v0.t
++[ 	]+[0-9a-f]+:[ 	]+24861257[ 	]+vfsgnjn.vv[ 	]+v4,v8,v12,v0.t
++[ 	]+[0-9a-f]+:[ 	]+24865257[ 	]+vfsgnjn.vf[ 	]+v4,v8,fa2,v0.t
++[ 	]+[0-9a-f]+:[ 	]+28861257[ 	]+vfsgnjx.vv[ 	]+v4,v8,v12,v0.t
++[ 	]+[0-9a-f]+:[ 	]+28865257[ 	]+vfsgnjx.vf[ 	]+v4,v8,fa2,v0.t
++[ 	]+[0-9a-f]+:[ 	]+6ec41257[ 	]+vmflt.vv[ 	]+v4,v12,v8
++[ 	]+[0-9a-f]+:[ 	]+66c41257[ 	]+vmfle.vv[ 	]+v4,v12,v8
++[ 	]+[0-9a-f]+:[ 	]+6cc41257[ 	]+vmflt.vv[ 	]+v4,v12,v8,v0.t
++[ 	]+[0-9a-f]+:[ 	]+64c41257[ 	]+vmfle.vv[ 	]+v4,v12,v8,v0.t
++[ 	]+[0-9a-f]+:[ 	]+62861257[ 	]+vmfeq.vv[ 	]+v4,v8,v12
++[ 	]+[0-9a-f]+:[ 	]+62865257[ 	]+vmfeq.vf[ 	]+v4,v8,fa2
++[ 	]+[0-9a-f]+:[ 	]+72861257[ 	]+vmfne.vv[ 	]+v4,v8,v12
++[ 	]+[0-9a-f]+:[ 	]+72865257[ 	]+vmfne.vf[ 	]+v4,v8,fa2
++[ 	]+[0-9a-f]+:[ 	]+6e861257[ 	]+vmflt.vv[ 	]+v4,v8,v12
++[ 	]+[0-9a-f]+:[ 	]+6e865257[ 	]+vmflt.vf[ 	]+v4,v8,fa2
++[ 	]+[0-9a-f]+:[ 	]+66861257[ 	]+vmfle.vv[ 	]+v4,v8,v12
++[ 	]+[0-9a-f]+:[ 	]+66865257[ 	]+vmfle.vf[ 	]+v4,v8,fa2
++[ 	]+[0-9a-f]+:[ 	]+76865257[ 	]+vmfgt.vf[ 	]+v4,v8,fa2
++[ 	]+[0-9a-f]+:[ 	]+7e865257[ 	]+vmfge.vf[ 	]+v4,v8,fa2
++[ 	]+[0-9a-f]+:[ 	]+60861257[ 	]+vmfeq.vv[ 	]+v4,v8,v12,v0.t
++[ 	]+[0-9a-f]+:[ 	]+60865257[ 	]+vmfeq.vf[ 	]+v4,v8,fa2,v0.t
++[ 	]+[0-9a-f]+:[ 	]+70861257[ 	]+vmfne.vv[ 	]+v4,v8,v12,v0.t
++[ 	]+[0-9a-f]+:[ 	]+70865257[ 	]+vmfne.vf[ 	]+v4,v8,fa2,v0.t
++[ 	]+[0-9a-f]+:[ 	]+6c861257[ 	]+vmflt.vv[ 	]+v4,v8,v12,v0.t
++[ 	]+[0-9a-f]+:[ 	]+6c865257[ 	]+vmflt.vf[ 	]+v4,v8,fa2,v0.t
++[ 	]+[0-9a-f]+:[ 	]+64861257[ 	]+vmfle.vv[ 	]+v4,v8,v12,v0.t
++[ 	]+[0-9a-f]+:[ 	]+64865257[ 	]+vmfle.vf[ 	]+v4,v8,fa2,v0.t
++[ 	]+[0-9a-f]+:[ 	]+74865257[ 	]+vmfgt.vf[ 	]+v4,v8,fa2,v0.t
++[ 	]+[0-9a-f]+:[ 	]+7c865257[ 	]+vmfge.vf[ 	]+v4,v8,fa2,v0.t
++[ 	]+[0-9a-f]+:[ 	]+5c865257[ 	]+vfmerge.vfm[ 	]+v4,v8,fa2,v0
++[ 	]+[0-9a-f]+:[ 	]+5e05d257[ 	]+vfmv.v.f[ 	]+v4,fa1
++[ 	]+[0-9a-f]+:[ 	]+66842257[ 	]+vmmv.m[ 	]+v4,v8
++[ 	]+[0-9a-f]+:[ 	]+66842257[ 	]+vmmv.m[ 	]+v4,v8
++[ 	]+[0-9a-f]+:[ 	]+6e422257[ 	]+vmclr.m[ 	]+v4
++[ 	]+[0-9a-f]+:[ 	]+7e422257[ 	]+vmset.m[ 	]+v4
++[ 	]+[0-9a-f]+:[ 	]+76842257[ 	]+vmnot.m[ 	]+v4,v8
++[ 	]+[0-9a-f]+:[ 	]+66862257[ 	]+vmand.mm[ 	]+v4,v8,v12
++[ 	]+[0-9a-f]+:[ 	]+76862257[ 	]+vmnand.mm[ 	]+v4,v8,v12
++[ 	]+[0-9a-f]+:[ 	]+62862257[ 	]+vmandnot.mm[ 	]+v4,v8,v12
++[ 	]+[0-9a-f]+:[ 	]+6e862257[ 	]+vmxor.mm[ 	]+v4,v8,v12
++[ 	]+[0-9a-f]+:[ 	]+6a862257[ 	]+vmor.mm[ 	]+v4,v8,v12
++[ 	]+[0-9a-f]+:[ 	]+7a862257[ 	]+vmnor.mm[ 	]+v4,v8,v12
++[ 	]+[0-9a-f]+:[ 	]+72862257[ 	]+vmornot.mm[ 	]+v4,v8,v12
++[ 	]+[0-9a-f]+:[ 	]+7e862257[ 	]+vmxnor.mm[ 	]+v4,v8,v12
++[ 	]+[0-9a-f]+:[ 	]+42c82557[ 	]+vpopc.m[ 	]+a0,v12
++[ 	]+[0-9a-f]+:[ 	]+42c8a557[ 	]+vfirst.m[ 	]+a0,v12
++[ 	]+[0-9a-f]+:[ 	]+40c82557[ 	]+vpopc.m[ 	]+a0,v12,v0.t
++[ 	]+[0-9a-f]+:[ 	]+40c8a557[ 	]+vfirst.m[ 	]+a0,v12,v0.t
++[ 	]+[0-9a-f]+:[ 	]+42c02557[ 	]+vmv.x.s[ 	]+a0,v12
++[ 	]+[0-9a-f]+:[ 	]+42056257[ 	]+vmv.s.x[ 	]+v4,a0
++[ 	]+[0-9a-f]+:[ 	]+42801557[ 	]+vfmv.f.s[ 	]+fa0,v8
++[ 	]+[0-9a-f]+:[ 	]+4205d257[ 	]+vfmv.s.f[ 	]+v4,fa1
++[ 	]+[0-9a-f]+:[ 	]+3a85c257[ 	]+vslideup.vx[ 	]+v4,v8,a1
++[ 	]+[0-9a-f]+:[ 	]+3a803257[ 	]+vslideup.vi[ 	]+v4,v8,0
++[ 	]+[0-9a-f]+:[ 	]+3a8fb257[ 	]+vslideup.vi[ 	]+v4,v8,31
++[ 	]+[0-9a-f]+:[ 	]+3e85c257[ 	]+vslidedown.vx[ 	]+v4,v8,a1
++[ 	]+[0-9a-f]+:[ 	]+3e803257[ 	]+vslidedown.vi[ 	]+v4,v8,0
++[ 	]+[0-9a-f]+:[ 	]+3e8fb257[ 	]+vslidedown.vi[ 	]+v4,v8,31
++[ 	]+[0-9a-f]+:[ 	]+3885c257[ 	]+vslideup.vx[ 	]+v4,v8,a1,v0.t
++[ 	]+[0-9a-f]+:[ 	]+38803257[ 	]+vslideup.vi[ 	]+v4,v8,0,v0.t
++[ 	]+[0-9a-f]+:[ 	]+388fb257[ 	]+vslideup.vi[ 	]+v4,v8,31,v0.t
++[ 	]+[0-9a-f]+:[ 	]+3c85c257[ 	]+vslidedown.vx[ 	]+v4,v8,a1,v0.t
++[ 	]+[0-9a-f]+:[ 	]+3c803257[ 	]+vslidedown.vi[ 	]+v4,v8,0,v0.t
++[ 	]+[0-9a-f]+:[ 	]+3c8fb257[ 	]+vslidedown.vi[ 	]+v4,v8,31,v0.t
++[ 	]+[0-9a-f]+:[ 	]+3a85e257[ 	]+vslide1up.vx[ 	]+v4,v8,a1
++[ 	]+[0-9a-f]+:[ 	]+3e85e257[ 	]+vslide1down.vx[ 	]+v4,v8,a1
++[ 	]+[0-9a-f]+:[ 	]+3885e257[ 	]+vslide1up.vx[ 	]+v4,v8,a1,v0.t
++[ 	]+[0-9a-f]+:[ 	]+3c85e257[ 	]+vslide1down.vx[ 	]+v4,v8,a1,v0.t
++[ 	]+[0-9a-f]+:[ 	]+3a85d257[ 	]+vfslide1up.vf[ 	]+v4,v8,fa1
++[ 	]+[0-9a-f]+:[ 	]+3e85d257[ 	]+vfslide1down.vf[ 	]+v4,v8,fa1
++[ 	]+[0-9a-f]+:[ 	]+3885d257[ 	]+vfslide1up.vf[ 	]+v4,v8,fa1,v0.t
++[ 	]+[0-9a-f]+:[ 	]+3c85d257[ 	]+vfslide1down.vf[ 	]+v4,v8,fa1,v0.t
++[ 	]+[0-9a-f]+:[ 	]+32860257[ 	]+vrgather.vv[ 	]+v4,v8,v12
++[ 	]+[0-9a-f]+:[ 	]+3285c257[ 	]+vrgather.vx[ 	]+v4,v8,a1
++[ 	]+[0-9a-f]+:[ 	]+32803257[ 	]+vrgather.vi[ 	]+v4,v8,0
++[ 	]+[0-9a-f]+:[ 	]+328fb257[ 	]+vrgather.vi[ 	]+v4,v8,31
++[ 	]+[0-9a-f]+:[ 	]+30860257[ 	]+vrgather.vv[ 	]+v4,v8,v12,v0.t
++[ 	]+[0-9a-f]+:[ 	]+3085c257[ 	]+vrgather.vx[ 	]+v4,v8,a1,v0.t
++[ 	]+[0-9a-f]+:[ 	]+30803257[ 	]+vrgather.vi[ 	]+v4,v8,0,v0.t
++[ 	]+[0-9a-f]+:[ 	]+308fb257[ 	]+vrgather.vi[ 	]+v4,v8,31,v0.t
++[ 	]+[0-9a-f]+:[ 	]+5e862257[ 	]+vcompress.vm[ 	]+v4,v8,v12
+diff --git a/gas/testsuite/gas/riscv/vector-insns.s b/gas/testsuite/gas/riscv/vector-insns.s
+new file mode 100644
+index 0000000000..a6f906e416
+--- /dev/null
++++ b/gas/testsuite/gas/riscv/vector-insns.s
+@@ -0,0 +1,521 @@
++	vsetvl a0, a1, a2
++	vsetvli a0, a1, 0
++	vsetvli a0, a1, 0x7ff
++	vsetvli a0, a1, e16, m2
++	vsetvli a0, a1, e256, m8
++	vsetvli a0, a1, e512, m8
++	vsetvli a0, a1, e1024, m8
++	vsetvli a0, a1, e1024, m1
++	vsetvli a0, a1, e1024, mf2
++	vsetvli a0, a1, e512, mf4
++	vsetvli a0, a1, e256, mf8
++	vsetvli a0, a1, e256, m2, ta
++	vsetvli a0, a1, e256, m2, ma
++	vsetvli a0, a1, e256, m2, tu
++	vsetvli a0, a1, e256, m2, mu
++	vsetvli a0, a1, e256, m2, ta, ma
++	vsetvli a0, a1, e256, m2, tu, ma
++	vsetvli a0, a1, e256, m2, ta, mu
++	vsetvli a0, a1, e256, m2, tu, mu
++
++	vle8.v v4, (a0)
++	vle8.v v4, 0(a0)
++	vle8.v v4, (a0), v0.t
++	vse8.v v4, (a0)
++	vse8.v v4, 0(a0)
++	vse8.v v4, (a0), v0.t
++
++	vle16.v v4, (a0)
++	vle16.v v4, 0(a0)
++	vle16.v v4, (a0), v0.t
++	vse16.v v4, (a0)
++	vse16.v v4, 0(a0)
++	vse16.v v4, (a0), v0.t
++
++	vle32.v v4, (a0)
++	vle32.v v4, 0(a0)
++	vle32.v v4, (a0), v0.t
++	vse32.v v4, (a0)
++	vse32.v v4, 0(a0)
++	vse32.v v4, (a0), v0.t
++
++	vle64.v v4, (a0)
++	vle64.v v4, 0(a0)
++	vle64.v v4, (a0), v0.t
++	vse64.v v4, (a0)
++	vse64.v v4, 0(a0)
++	vse64.v v4, (a0), v0.t
++
++	vlse8.v v4, (a0), a1
++	vlse8.v v4, 0(a0), a1
++	vlse8.v v4, (a0), a1, v0.t
++	vsse8.v v4, (a0), a1
++	vsse8.v v4, 0(a0), a1
++	vsse8.v v4, (a0), a1, v0.t
++
++	vlse16.v v4, (a0), a1
++	vlse16.v v4, 0(a0), a1
++	vlse16.v v4, (a0), a1, v0.t
++	vsse16.v v4, (a0), a1
++	vsse16.v v4, 0(a0), a1
++	vsse16.v v4, (a0), a1, v0.t
++
++	vlse32.v v4, (a0), a1
++	vlse32.v v4, 0(a0), a1
++	vlse32.v v4, (a0), a1, v0.t
++	vsse32.v v4, (a0), a1
++	vsse32.v v4, 0(a0), a1
++	vsse32.v v4, (a0), a1, v0.t
++
++	vlse64.v v4, (a0), a1
++	vlse64.v v4, 0(a0), a1
++	vlse64.v v4, (a0), a1, v0.t
++	vsse64.v v4, (a0), a1
++	vsse64.v v4, 0(a0), a1
++	vsse64.v v4, (a0), a1, v0.t
++
++	vloxei8.v v4, (a0), v12
++	vloxei8.v v4, 0(a0), v12
++	vloxei8.v v4, (a0), v12, v0.t
++	vsoxei8.v v4, (a0), v12
++	vsoxei8.v v4, 0(a0), v12
++	vsoxei8.v v4, (a0), v12, v0.t
++
++	vloxei16.v v4, (a0), v12
++	vloxei16.v v4, 0(a0), v12
++	vloxei16.v v4, (a0), v12, v0.t
++	vsoxei16.v v4, (a0), v12
++	vsoxei16.v v4, 0(a0), v12
++	vsoxei16.v v4, (a0), v12, v0.t
++
++	vloxei32.v v4, (a0), v12
++	vloxei32.v v4, 0(a0), v12
++	vloxei32.v v4, (a0), v12, v0.t
++	vsoxei32.v v4, (a0), v12
++	vsoxei32.v v4, 0(a0), v12
++	vsoxei32.v v4, (a0), v12, v0.t
++
++	vloxei64.v v4, (a0), v12
++	vloxei64.v v4, 0(a0), v12
++	vloxei64.v v4, (a0), v12, v0.t
++	vsoxei64.v v4, (a0), v12
++	vsoxei64.v v4, 0(a0), v12
++	vsoxei64.v v4, (a0), v12, v0.t
++
++	vneg.v v4, v8
++	vneg.v v4, v8, v0.t
++
++	vadd.vv v4, v8, v12
++	vadd.vx v4, v8, a1
++	vadd.vi v4, v8, 15
++	vadd.vi v4, v8, -16
++	vadd.vv v4, v8, v12, v0.t
++	vadd.vx v4, v8, a1, v0.t
++	vadd.vi v4, v8, 15, v0.t
++	vadd.vi v4, v8, -16, v0.t
++	vsub.vv v4, v8, v12
++	vsub.vx v4, v8, a1
++	vrsub.vx v4, v8, a1
++	vrsub.vi v4, v8, 15
++	vrsub.vi v4, v8, -16
++	vsub.vv v4, v8, v12, v0.t
++	vsub.vx v4, v8, a1, v0.t
++	vrsub.vx v4, v8, a1, v0.t
++	vrsub.vi v4, v8, 15, v0.t
++	vrsub.vi v4, v8, -16, v0.t
++
++	# Aliases
++	vzext.vf2 v4, v8
++	vzext.vf2 v4, v8, v0.t
++	vsext.vf2 v4, v8
++	vsext.vf2 v4, v8, v0.t
++	vzext.vf4 v4, v8
++	vzext.vf4 v4, v8, v0.t
++	vsext.vf4 v4, v8
++	vsext.vf4 v4, v8, v0.t
++	vzext.vf8 v4, v8
++	vzext.vf8 v4, v8, v0.t
++	vsext.vf8 v4, v8
++	vsext.vf8 v4, v8, v0.t
++
++	vadc.vvm v4, v8, v12, v0
++	vadc.vxm v4, v8, a1, v0
++	vadc.vim v4, v8, 15, v0
++	vadc.vim v4, v8, -16, v0
++	vmadc.vvm v4, v8, v12, v0
++	vmadc.vxm v4, v8, a1, v0
++	vmadc.vim v4, v8, 15, v0
++	vmadc.vim v4, v8, -16, v0
++	vmadc.vv v4, v8, v12
++	vmadc.vx v4, v8, a1
++	vmadc.vi v4, v8, 15
++	vmadc.vi v4, v8, -16
++	vsbc.vvm v4, v8, v12, v0
++	vsbc.vxm v4, v8, a1, v0
++	vmsbc.vvm v4, v8, v12, v0
++	vmsbc.vxm v4, v8, a1, v0
++	vmsbc.vv v4, v8, v12
++	vmsbc.vx v4, v8, a1
++
++	# Aliases
++	vnot.v v4, v8
++	vnot.v v4, v8, v0.t
++
++	vand.vv v4, v8, v12
++	vand.vx v4, v8, a1
++	vand.vi v4, v8, 15
++	vand.vi v4, v8, -16
++	vand.vv v4, v8, v12, v0.t
++	vand.vx v4, v8, a1, v0.t
++	vand.vi v4, v8, 15, v0.t
++	vand.vi v4, v8, -16, v0.t
++	vor.vv v4, v8, v12
++	vor.vx v4, v8, a1
++	vor.vi v4, v8, 15
++	vor.vi v4, v8, -16
++	vor.vv v4, v8, v12, v0.t
++	vor.vx v4, v8, a1, v0.t
++	vor.vi v4, v8, 15, v0.t
++	vor.vi v4, v8, -16, v0.t
++	vxor.vv v4, v8, v12
++	vxor.vx v4, v8, a1
++	vxor.vi v4, v8, 15
++	vxor.vi v4, v8, -16
++	vxor.vv v4, v8, v12, v0.t
++	vxor.vx v4, v8, a1, v0.t
++	vxor.vi v4, v8, 15, v0.t
++	vxor.vi v4, v8, -16, v0.t
++
++	# Aliases
++	vmsgt.vv v4, v8, v12
++	vmsgtu.vv v4, v8, v12
++	vmsge.vv v4, v8, v12
++	vmsgeu.vv v4, v8, v12
++	vmsgt.vv v4, v8, v12, v0.t
++	vmsgtu.vv v4, v8, v12, v0.t
++	vmsge.vv v4, v8, v12, v0.t
++	vmsgeu.vv v4, v8, v12, v0.t
++	vmslt.vi v4, v8, 16
++	vmslt.vi v4, v8, -15
++	vmsltu.vi v4, v8, 16
++	vmsltu.vi v4, v8, -15
++	vmsge.vi v4, v8, 16
++	vmsge.vi v4, v8, -15
++	vmsgeu.vi v4, v8, 16
++	vmsgeu.vi v4, v8, -15
++	vmslt.vi v4, v8, 16, v0.t
++	vmslt.vi v4, v8, -15, v0.t
++	vmsltu.vi v4, v8, 16, v0.t
++	vmsltu.vi v4, v8, -15, v0.t
++	vmsge.vi v4, v8, 16, v0.t
++	vmsge.vi v4, v8, -15, v0.t
++	vmsgeu.vi v4, v8, 16, v0.t
++	vmsgeu.vi v4, v8, -15, v0.t
++
++	vmseq.vv v4, v8, v12
++	vmseq.vx v4, v8, a1
++	vmseq.vi v4, v8, 15
++	vmseq.vi v4, v8, -16
++	vmseq.vv v4, v8, v12, v0.t
++	vmseq.vx v4, v8, a1, v0.t
++	vmseq.vi v4, v8, 15, v0.t
++	vmseq.vi v4, v8, -16, v0.t
++	vmsne.vv v4, v8, v12
++	vmsne.vx v4, v8, a1
++	vmsne.vi v4, v8, 15
++	vmsne.vi v4, v8, -16
++	vmsne.vv v4, v8, v12, v0.t
++	vmsne.vx v4, v8, a1, v0.t
++	vmsne.vi v4, v8, 15, v0.t
++	vmsne.vi v4, v8, -16, v0.t
++	vmsltu.vv v4, v8, v12
++	vmsltu.vx v4, v8, a1
++	vmsltu.vv v4, v8, v12, v0.t
++	vmsltu.vx v4, v8, a1, v0.t
++	vmslt.vv v4, v8, v12
++	vmslt.vx v4, v8, a1
++	vmslt.vv v4, v8, v12, v0.t
++	vmslt.vx v4, v8, a1, v0.t
++	vmsleu.vv v4, v8, v12
++	vmsleu.vx v4, v8, a1
++	vmsleu.vi v4, v8, 15
++	vmsleu.vi v4, v8, -16
++	vmsleu.vv v4, v8, v12, v0.t
++	vmsleu.vx v4, v8, a1, v0.t
++	vmsleu.vi v4, v8, 15, v0.t
++	vmsleu.vi v4, v8, -16, v0.t
++	vmsle.vv v4, v8, v12
++	vmsle.vx v4, v8, a1
++	vmsle.vi v4, v8, 15
++	vmsle.vi v4, v8, -16
++	vmsle.vv v4, v8, v12, v0.t
++	vmsle.vx v4, v8, a1, v0.t
++	vmsle.vi v4, v8, 15, v0.t
++	vmsle.vi v4, v8, -16, v0.t
++	vmsgtu.vx v4, v8, a1
++	vmsgtu.vi v4, v8, 15
++	vmsgtu.vi v4, v8, -16
++	vmsgtu.vx v4, v8, a1, v0.t
++	vmsgtu.vi v4, v8, 15, v0.t
++	vmsgtu.vi v4, v8, -16, v0.t
++	vmsgt.vx v4, v8, a1
++	vmsgt.vi v4, v8, 15
++	vmsgt.vi v4, v8, -16
++	vmsgt.vx v4, v8, a1, v0.t
++	vmsgt.vi v4, v8, 15, v0.t
++	vmsgt.vi v4, v8, -16, v0.t
++
++	vminu.vv v4, v8, v12
++	vminu.vx v4, v8, a1
++	vminu.vv v4, v8, v12, v0.t
++	vminu.vx v4, v8, a1, v0.t
++	vmin.vv v4, v8, v12
++	vmin.vx v4, v8, a1
++	vmin.vv v4, v8, v12, v0.t
++	vmin.vx v4, v8, a1, v0.t
++	vmaxu.vv v4, v8, v12
++	vmaxu.vx v4, v8, a1
++	vmaxu.vv v4, v8, v12, v0.t
++	vmaxu.vx v4, v8, a1, v0.t
++	vmax.vv v4, v8, v12
++	vmax.vx v4, v8, a1
++	vmax.vv v4, v8, v12, v0.t
++	vmax.vx v4, v8, a1, v0.t
++
++	vmul.vv v4, v8, v12
++	vmul.vx v4, v8, a1
++	vmul.vv v4, v8, v12, v0.t
++	vmul.vx v4, v8, a1, v0.t
++	vmulh.vv v4, v8, v12
++	vmulh.vx v4, v8, a1
++	vmulh.vv v4, v8, v12, v0.t
++	vmulh.vx v4, v8, a1, v0.t
++	vmulhu.vv v4, v8, v12
++	vmulhu.vx v4, v8, a1
++	vmulhu.vv v4, v8, v12, v0.t
++	vmulhu.vx v4, v8, a1, v0.t
++	vmulhsu.vv v4, v8, v12
++	vmulhsu.vx v4, v8, a1
++	vmulhsu.vv v4, v8, v12, v0.t
++	vmulhsu.vx v4, v8, a1, v0.t
++
++	vmacc.vv v4, v12, v8
++	vmacc.vx v4, a1, v8
++	vmacc.vv v4, v12, v8, v0.t
++	vmacc.vx v4, a1, v8, v0.t
++	vnmsac.vv v4, v12, v8
++	vnmsac.vx v4, a1, v8
++	vnmsac.vv v4, v12, v8, v0.t
++	vnmsac.vx v4, a1, v8, v0.t
++	vmadd.vv v4, v12, v8
++	vmadd.vx v4, a1, v8
++	vmadd.vv v4, v12, v8, v0.t
++	vmadd.vx v4, a1, v8, v0.t
++	vnmsub.vv v4, v12, v8
++	vnmsub.vx v4, a1, v8
++	vnmsub.vv v4, v12, v8, v0.t
++	vnmsub.vx v4, a1, v8, v0.t
++
++	vdivu.vv v4, v8, v12
++	vdivu.vx v4, v8, a1
++	vdivu.vv v4, v8, v12, v0.t
++	vdivu.vx v4, v8, a1, v0.t
++	vdiv.vv v4, v8, v12
++	vdiv.vx v4, v8, a1
++	vdiv.vv v4, v8, v12, v0.t
++	vdiv.vx v4, v8, a1, v0.t
++	vremu.vv v4, v8, v12
++	vremu.vx v4, v8, a1
++	vremu.vv v4, v8, v12, v0.t
++	vremu.vx v4, v8, a1, v0.t
++	vrem.vv v4, v8, v12
++	vrem.vx v4, v8, a1
++	vrem.vv v4, v8, v12, v0.t
++	vrem.vx v4, v8, a1, v0.t
++
++	vmerge.vvm v4, v8, v12, v0
++	vmerge.vxm v4, v8, a1, v0
++	vmerge.vim v4, v8, 15, v0
++	vmerge.vim v4, v8, -16, v0
++
++	vmv.v.v v8, v12
++	vmv.v.x v8, a1
++	vmv.v.i v8, 15
++	vmv.v.i v8, -16
++
++
++
++	vfadd.vv v4, v8, v12
++	vfadd.vf v4, v8, fa2
++	vfadd.vv v4, v8, v12, v0.t
++	vfadd.vf v4, v8, fa2, v0.t
++	vfsub.vv v4, v8, v12
++	vfsub.vf v4, v8, fa2
++	vfsub.vv v4, v8, v12, v0.t
++	vfsub.vf v4, v8, fa2, v0.t
++	vfrsub.vf v4, v8, fa2
++	vfrsub.vf v4, v8, fa2, v0.t
++
++
++	vfmul.vv v4, v8, v12
++	vfmul.vf v4, v8, fa2
++	vfmul.vv v4, v8, v12, v0.t
++	vfmul.vf v4, v8, fa2, v0.t
++	vfdiv.vv v4, v8, v12
++	vfdiv.vf v4, v8, fa2
++	vfdiv.vv v4, v8, v12, v0.t
++	vfdiv.vf v4, v8, fa2, v0.t
++	vfrdiv.vf v4, v8, fa2
++	vfrdiv.vf v4, v8, fa2, v0.t
++
++	vfmadd.vv v4, v12, v8
++	vfmadd.vf v4, fa2, v8
++	vfnmadd.vv v4, v12, v8
++	vfnmadd.vf v4, fa2, v8
++	vfmsub.vv v4, v12, v8
++	vfmsub.vf v4, fa2, v8
++	vfnmsub.vv v4, v12, v8
++	vfnmsub.vf v4, fa2, v8
++	vfmadd.vv v4, v12, v8, v0.t
++	vfmadd.vf v4, fa2, v8, v0.t
++	vfnmadd.vv v4, v12, v8, v0.t
++	vfnmadd.vf v4, fa2, v8, v0.t
++	vfmsub.vv v4, v12, v8, v0.t
++	vfmsub.vf v4, fa2, v8, v0.t
++	vfnmsub.vv v4, v12, v8, v0.t
++	vfnmsub.vf v4, fa2, v8, v0.t
++	vfmacc.vv v4, v12, v8
++	vfmacc.vf v4, fa2, v8
++	vfnmacc.vv v4, v12, v8
++	vfnmacc.vf v4, fa2, v8
++	vfmsac.vv v4, v12, v8
++	vfmsac.vf v4, fa2, v8
++	vfnmsac.vv v4, v12, v8
++	vfnmsac.vf v4, fa2, v8
++	vfmacc.vv v4, v12, v8, v0.t
++	vfmacc.vf v4, fa2, v8, v0.t
++	vfnmacc.vv v4, v12, v8, v0.t
++	vfnmacc.vf v4, fa2, v8, v0.t
++	vfmsac.vv v4, v12, v8, v0.t
++	vfmsac.vf v4, fa2, v8, v0.t
++	vfnmsac.vv v4, v12, v8, v0.t
++	vfnmsac.vf v4, fa2, v8, v0.t
++
++	vfmin.vv v4, v8, v12
++	vfmin.vf v4, v8, fa2
++	vfmax.vv v4, v8, v12
++	vfmax.vf v4, v8, fa2
++	vfmin.vv v4, v8, v12, v0.t
++	vfmin.vf v4, v8, fa2, v0.t
++	vfmax.vv v4, v8, v12, v0.t
++	vfmax.vf v4, v8, fa2, v0.t
++
++	vfneg.v v4, v8
++	vfneg.v v4, v8, v0.t
++	vfabs.v v4, v8
++	vfabs.v v4, v8, v0.t
++
++	vfsgnj.vv v4, v8, v12
++	vfsgnj.vf v4, v8, fa2
++	vfsgnjn.vv v4, v8, v12
++	vfsgnjn.vf v4, v8, fa2
++	vfsgnjx.vv v4, v8, v12
++	vfsgnjx.vf v4, v8, fa2
++	vfsgnj.vv v4, v8, v12, v0.t
++	vfsgnj.vf v4, v8, fa2, v0.t
++	vfsgnjn.vv v4, v8, v12, v0.t
++	vfsgnjn.vf v4, v8, fa2, v0.t
++	vfsgnjx.vv v4, v8, v12, v0.t
++	vfsgnjx.vf v4, v8, fa2, v0.t
++
++	# Aliases
++	vmfgt.vv v4, v8, v12
++	vmfge.vv v4, v8, v12
++	vmfgt.vv v4, v8, v12, v0.t
++	vmfge.vv v4, v8, v12, v0.t
++
++	vmfeq.vv v4, v8, v12
++	vmfeq.vf v4, v8, fa2
++	vmfne.vv v4, v8, v12
++	vmfne.vf v4, v8, fa2
++	vmflt.vv v4, v8, v12
++	vmflt.vf v4, v8, fa2
++	vmfle.vv v4, v8, v12
++	vmfle.vf v4, v8, fa2
++	vmfgt.vf v4, v8, fa2
++	vmfge.vf v4, v8, fa2
++	vmfeq.vv v4, v8, v12, v0.t
++	vmfeq.vf v4, v8, fa2, v0.t
++	vmfne.vv v4, v8, v12, v0.t
++	vmfne.vf v4, v8, fa2, v0.t
++	vmflt.vv v4, v8, v12, v0.t
++	vmflt.vf v4, v8, fa2, v0.t
++	vmfle.vv v4, v8, v12, v0.t
++	vmfle.vf v4, v8, fa2, v0.t
++	vmfgt.vf v4, v8, fa2, v0.t
++	vmfge.vf v4, v8, fa2, v0.t
++
++	vfmerge.vfm v4, v8, fa2, v0
++	vfmv.v.f v4, fa1
++
++	# Aliases
++	vmcpy.m v4, v8
++	vmmv.m v4, v8
++	vmclr.m v4
++	vmset.m v4
++	vmnot.m v4, v8
++
++	vmand.mm v4, v8, v12
++	vmnand.mm v4, v8, v12
++	vmandnot.mm v4, v8, v12
++	vmxor.mm v4, v8, v12
++	vmor.mm v4, v8, v12
++	vmnor.mm v4, v8, v12
++	vmornot.mm v4, v8, v12
++	vmxnor.mm v4, v8, v12
++
++	vpopc.m a0, v12
++	vfirst.m a0, v12
++	vpopc.m a0, v12, v0.t
++	vfirst.m a0, v12, v0.t
++
++	vmv.x.s a0, v12
++	vmv.s.x v4, a0
++
++	vfmv.f.s fa0, v8
++	vfmv.s.f v4, fa1
++
++	vslideup.vx v4, v8, a1
++	vslideup.vi v4, v8, 0
++	vslideup.vi v4, v8, 31
++	vslidedown.vx v4, v8, a1
++	vslidedown.vi v4, v8, 0
++	vslidedown.vi v4, v8, 31
++	vslideup.vx v4, v8, a1, v0.t
++	vslideup.vi v4, v8, 0, v0.t
++	vslideup.vi v4, v8, 31, v0.t
++	vslidedown.vx v4, v8, a1, v0.t
++	vslidedown.vi v4, v8, 0, v0.t
++	vslidedown.vi v4, v8, 31, v0.t
++
++	vslide1up.vx v4, v8, a1
++	vslide1down.vx v4, v8, a1
++	vslide1up.vx v4, v8, a1, v0.t
++	vslide1down.vx v4, v8, a1, v0.t
++
++	vfslide1up.vf v4, v8, fa1
++	vfslide1down.vf v4, v8, fa1
++	vfslide1up.vf v4, v8, fa1, v0.t
++	vfslide1down.vf v4, v8, fa1, v0.t
++
++	vrgather.vv v4, v8, v12
++	vrgather.vx v4, v8, a1
++	vrgather.vi v4, v8, 0
++	vrgather.vi v4, v8, 31
++	vrgather.vv v4, v8, v12, v0.t
++	vrgather.vx v4, v8, a1, v0.t
++	vrgather.vi v4, v8, 0, v0.t
++	vrgather.vi v4, v8, 31, v0.t
++
++	vcompress.vm v4, v8, v12
++
+diff --git a/opcodes/riscv-opc.c b/opcodes/riscv-opc.c
+index b51e876977..df6b1659f8 100644
+--- a/opcodes/riscv-opc.c
++++ b/opcodes/riscv-opc.c
+@@ -1309,10 +1309,6 @@ const struct riscv_opcode riscv_opcodes[] =
+ /* RVV */
+ {"vsetvl",     0, INSN_CLASS_V,  "d,s,t",  MATCH_VSETVL, MASK_VSETVL, match_opcode, 0},
+ {"vsetvli",    0, INSN_CLASS_V,  "d,s,Vc", MATCH_VSETVLI, MASK_VSETVLI, match_opcode, 0},
+-{"vsetivli",   0, INSN_CLASS_V,  "d,Z,Vb", MATCH_VSETIVLI, MASK_VSETIVLI, match_opcode, 0},
+-
+-{"vle1.v",     0, INSN_CLASS_V,  "Vd,0(s)", MATCH_VLE1V, MASK_VLE1V, match_opcode, INSN_DREF },
+-{"vse1.v",     0, INSN_CLASS_V,  "Vd,0(s)", MATCH_VSE1V, MASK_VSE1V, match_opcode, INSN_DREF },
+ 
+ {"vle8.v",     0, INSN_CLASS_V,  "Vd,0(s)Vm", MATCH_VLE8V, MASK_VLE8V, match_vd_neq_vm, INSN_DREF },
+ {"vle16.v",    0, INSN_CLASS_V,  "Vd,0(s)Vm", MATCH_VLE16V, MASK_VLE16V, match_vd_neq_vm, INSN_DREF },
+@@ -1344,362 +1340,6 @@ const struct riscv_opcode riscv_opcodes[] =
+ {"vsoxei32.v",  0, INSN_CLASS_V,  "Vd,0(s),VtVm", MATCH_VSOXEI32V, MASK_VSOXEI32V, match_vd_neq_vm, INSN_DREF },
+ {"vsoxei64.v",  0, INSN_CLASS_V,  "Vd,0(s),VtVm", MATCH_VSOXEI64V, MASK_VSOXEI64V, match_vd_neq_vm, INSN_DREF },
+ 
+-{"vluxei8.v",   0, INSN_CLASS_V,  "Vd,0(s),VtVm", MATCH_VLUXEI8V, MASK_VLUXEI8V, match_vd_neq_vm, INSN_DREF },
+-{"vluxei16.v",  0, INSN_CLASS_V,  "Vd,0(s),VtVm", MATCH_VLUXEI16V, MASK_VLUXEI16V, match_vd_neq_vm, INSN_DREF },
+-{"vluxei32.v",  0, INSN_CLASS_V,  "Vd,0(s),VtVm", MATCH_VLUXEI32V, MASK_VLUXEI32V, match_vd_neq_vm, INSN_DREF },
+-{"vluxei64.v",  0, INSN_CLASS_V,  "Vd,0(s),VtVm", MATCH_VLUXEI64V, MASK_VLUXEI64V, match_vd_neq_vm, INSN_DREF },
+-
+-{"vsuxei8.v",   0, INSN_CLASS_V,  "Vd,0(s),VtVm", MATCH_VSUXEI8V, MASK_VSUXEI8V, match_vd_neq_vm, INSN_DREF },
+-{"vsuxei16.v",  0, INSN_CLASS_V,  "Vd,0(s),VtVm", MATCH_VSUXEI16V, MASK_VSUXEI16V, match_vd_neq_vm, INSN_DREF },
+-{"vsuxei32.v",  0, INSN_CLASS_V,  "Vd,0(s),VtVm", MATCH_VSUXEI32V, MASK_VSUXEI32V, match_vd_neq_vm, INSN_DREF },
+-{"vsuxei64.v",  0, INSN_CLASS_V,  "Vd,0(s),VtVm", MATCH_VSUXEI64V, MASK_VSUXEI64V, match_vd_neq_vm, INSN_DREF },
+-
+-{"vle8ff.v",    0, INSN_CLASS_V,  "Vd,0(s)Vm", MATCH_VLE8FFV, MASK_VLE8FFV, match_vd_neq_vm, INSN_DREF },
+-{"vle16ff.v",   0, INSN_CLASS_V,  "Vd,0(s)Vm", MATCH_VLE16FFV, MASK_VLE16FFV, match_vd_neq_vm, INSN_DREF },
+-{"vle32ff.v",   0, INSN_CLASS_V,  "Vd,0(s)Vm", MATCH_VLE32FFV, MASK_VLE32FFV, match_vd_neq_vm, INSN_DREF },
+-{"vle64ff.v",   0, INSN_CLASS_V,  "Vd,0(s)Vm", MATCH_VLE64FFV, MASK_VLE64FFV, match_vd_neq_vm, INSN_DREF },
+-
+-{"vlseg2e8.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s)Vm", MATCH_VLSEG2E8V, MASK_VLSEG2E8V, match_vd_neq_vm, INSN_DREF },
+-{"vsseg2e8.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s)Vm", MATCH_VSSEG2E8V, MASK_VSSEG2E8V, match_vd_neq_vm, INSN_DREF },
+-{"vlseg3e8.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s)Vm", MATCH_VLSEG3E8V, MASK_VLSEG3E8V, match_vd_neq_vm, INSN_DREF },
+-{"vsseg3e8.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s)Vm", MATCH_VSSEG3E8V, MASK_VSSEG3E8V, match_vd_neq_vm, INSN_DREF },
+-{"vlseg4e8.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s)Vm", MATCH_VLSEG4E8V, MASK_VLSEG4E8V, match_vd_neq_vm, INSN_DREF },
+-{"vsseg4e8.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s)Vm", MATCH_VSSEG4E8V, MASK_VSSEG4E8V, match_vd_neq_vm, INSN_DREF },
+-{"vlseg5e8.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s)Vm", MATCH_VLSEG5E8V, MASK_VLSEG5E8V, match_vd_neq_vm, INSN_DREF },
+-{"vsseg5e8.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s)Vm", MATCH_VSSEG5E8V, MASK_VSSEG5E8V, match_vd_neq_vm, INSN_DREF },
+-{"vlseg6e8.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s)Vm", MATCH_VLSEG6E8V, MASK_VLSEG6E8V, match_vd_neq_vm, INSN_DREF },
+-{"vsseg6e8.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s)Vm", MATCH_VSSEG6E8V, MASK_VSSEG6E8V, match_vd_neq_vm, INSN_DREF },
+-{"vlseg7e8.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s)Vm", MATCH_VLSEG7E8V, MASK_VLSEG7E8V, match_vd_neq_vm, INSN_DREF },
+-{"vsseg7e8.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s)Vm", MATCH_VSSEG7E8V, MASK_VSSEG7E8V, match_vd_neq_vm, INSN_DREF },
+-{"vlseg8e8.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s)Vm", MATCH_VLSEG8E8V, MASK_VLSEG8E8V, match_vd_neq_vm, INSN_DREF },
+-{"vsseg8e8.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s)Vm", MATCH_VSSEG8E8V, MASK_VSSEG8E8V, match_vd_neq_vm, INSN_DREF },
+-
+-{"vlseg2e16.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s)Vm", MATCH_VLSEG2E16V, MASK_VLSEG2E16V, match_vd_neq_vm, INSN_DREF },
+-{"vsseg2e16.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s)Vm", MATCH_VSSEG2E16V, MASK_VSSEG2E16V, match_vd_neq_vm, INSN_DREF },
+-{"vlseg3e16.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s)Vm", MATCH_VLSEG3E16V, MASK_VLSEG3E16V, match_vd_neq_vm, INSN_DREF },
+-{"vsseg3e16.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s)Vm", MATCH_VSSEG3E16V, MASK_VSSEG3E16V, match_vd_neq_vm, INSN_DREF },
+-{"vlseg4e16.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s)Vm", MATCH_VLSEG4E16V, MASK_VLSEG4E16V, match_vd_neq_vm, INSN_DREF },
+-{"vsseg4e16.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s)Vm", MATCH_VSSEG4E16V, MASK_VSSEG4E16V, match_vd_neq_vm, INSN_DREF },
+-{"vlseg5e16.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s)Vm", MATCH_VLSEG5E16V, MASK_VLSEG5E16V, match_vd_neq_vm, INSN_DREF },
+-{"vsseg5e16.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s)Vm", MATCH_VSSEG5E16V, MASK_VSSEG5E16V, match_vd_neq_vm, INSN_DREF },
+-{"vlseg6e16.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s)Vm", MATCH_VLSEG6E16V, MASK_VLSEG6E16V, match_vd_neq_vm, INSN_DREF },
+-{"vsseg6e16.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s)Vm", MATCH_VSSEG6E16V, MASK_VSSEG6E16V, match_vd_neq_vm, INSN_DREF },
+-{"vlseg7e16.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s)Vm", MATCH_VLSEG7E16V, MASK_VLSEG7E16V, match_vd_neq_vm, INSN_DREF },
+-{"vsseg7e16.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s)Vm", MATCH_VSSEG7E16V, MASK_VSSEG7E16V, match_vd_neq_vm, INSN_DREF },
+-{"vlseg8e16.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s)Vm", MATCH_VLSEG8E16V, MASK_VLSEG8E16V, match_vd_neq_vm, INSN_DREF },
+-{"vsseg8e16.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s)Vm", MATCH_VSSEG8E16V, MASK_VSSEG8E16V, match_vd_neq_vm, INSN_DREF },
+-
+-{"vlseg2e32.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s)Vm", MATCH_VLSEG2E32V, MASK_VLSEG2E32V, match_vd_neq_vm, INSN_DREF },
+-{"vsseg2e32.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s)Vm", MATCH_VSSEG2E32V, MASK_VSSEG2E32V, match_vd_neq_vm, INSN_DREF },
+-{"vlseg3e32.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s)Vm", MATCH_VLSEG3E32V, MASK_VLSEG3E32V, match_vd_neq_vm, INSN_DREF },
+-{"vsseg3e32.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s)Vm", MATCH_VSSEG3E32V, MASK_VSSEG3E32V, match_vd_neq_vm, INSN_DREF },
+-{"vlseg4e32.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s)Vm", MATCH_VLSEG4E32V, MASK_VLSEG4E32V, match_vd_neq_vm, INSN_DREF },
+-{"vsseg4e32.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s)Vm", MATCH_VSSEG4E32V, MASK_VSSEG4E32V, match_vd_neq_vm, INSN_DREF },
+-{"vlseg5e32.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s)Vm", MATCH_VLSEG5E32V, MASK_VLSEG5E32V, match_vd_neq_vm, INSN_DREF },
+-{"vsseg5e32.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s)Vm", MATCH_VSSEG5E32V, MASK_VSSEG5E32V, match_vd_neq_vm, INSN_DREF },
+-{"vlseg6e32.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s)Vm", MATCH_VLSEG6E32V, MASK_VLSEG6E32V, match_vd_neq_vm, INSN_DREF },
+-{"vsseg6e32.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s)Vm", MATCH_VSSEG6E32V, MASK_VSSEG6E32V, match_vd_neq_vm, INSN_DREF },
+-{"vlseg7e32.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s)Vm", MATCH_VLSEG7E32V, MASK_VLSEG7E32V, match_vd_neq_vm, INSN_DREF },
+-{"vsseg7e32.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s)Vm", MATCH_VSSEG7E32V, MASK_VSSEG7E32V, match_vd_neq_vm, INSN_DREF },
+-{"vlseg8e32.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s)Vm", MATCH_VLSEG8E32V, MASK_VLSEG8E32V, match_vd_neq_vm, INSN_DREF },
+-{"vsseg8e32.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s)Vm", MATCH_VSSEG8E32V, MASK_VSSEG8E32V, match_vd_neq_vm, INSN_DREF },
+-
+-{"vlseg2e64.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s)Vm", MATCH_VLSEG2E64V, MASK_VLSEG2E64V, match_vd_neq_vm, INSN_DREF },
+-{"vsseg2e64.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s)Vm", MATCH_VSSEG2E64V, MASK_VSSEG2E64V, match_vd_neq_vm, INSN_DREF },
+-{"vlseg3e64.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s)Vm", MATCH_VLSEG3E64V, MASK_VLSEG3E64V, match_vd_neq_vm, INSN_DREF },
+-{"vsseg3e64.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s)Vm", MATCH_VSSEG3E64V, MASK_VSSEG3E64V, match_vd_neq_vm, INSN_DREF },
+-{"vlseg4e64.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s)Vm", MATCH_VLSEG4E64V, MASK_VLSEG4E64V, match_vd_neq_vm, INSN_DREF },
+-{"vsseg4e64.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s)Vm", MATCH_VSSEG4E64V, MASK_VSSEG4E64V, match_vd_neq_vm, INSN_DREF },
+-{"vlseg5e64.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s)Vm", MATCH_VLSEG5E64V, MASK_VLSEG5E64V, match_vd_neq_vm, INSN_DREF },
+-{"vsseg5e64.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s)Vm", MATCH_VSSEG5E64V, MASK_VSSEG5E64V, match_vd_neq_vm, INSN_DREF },
+-{"vlseg6e64.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s)Vm", MATCH_VLSEG6E64V, MASK_VLSEG6E64V, match_vd_neq_vm, INSN_DREF },
+-{"vsseg6e64.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s)Vm", MATCH_VSSEG6E64V, MASK_VSSEG6E64V, match_vd_neq_vm, INSN_DREF },
+-{"vlseg7e64.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s)Vm", MATCH_VLSEG7E64V, MASK_VLSEG7E64V, match_vd_neq_vm, INSN_DREF },
+-{"vsseg7e64.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s)Vm", MATCH_VSSEG7E64V, MASK_VSSEG7E64V, match_vd_neq_vm, INSN_DREF },
+-{"vlseg8e64.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s)Vm", MATCH_VLSEG8E64V, MASK_VLSEG8E64V, match_vd_neq_vm, INSN_DREF },
+-{"vsseg8e64.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s)Vm", MATCH_VSSEG8E64V, MASK_VSSEG8E64V, match_vd_neq_vm, INSN_DREF },
+-
+-{"vlsseg2e8.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),tVm", MATCH_VLSSEG2E8V, MASK_VLSSEG2E8V, match_vd_neq_vm, INSN_DREF },
+-{"vssseg2e8.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),tVm", MATCH_VSSSEG2E8V, MASK_VSSSEG2E8V, match_vd_neq_vm, INSN_DREF },
+-{"vlsseg3e8.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),tVm", MATCH_VLSSEG3E8V, MASK_VLSSEG3E8V, match_vd_neq_vm, INSN_DREF },
+-{"vssseg3e8.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),tVm", MATCH_VSSSEG3E8V, MASK_VSSSEG3E8V, match_vd_neq_vm, INSN_DREF },
+-{"vlsseg4e8.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),tVm", MATCH_VLSSEG4E8V, MASK_VLSSEG4E8V, match_vd_neq_vm, INSN_DREF },
+-{"vssseg4e8.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),tVm", MATCH_VSSSEG4E8V, MASK_VSSSEG4E8V, match_vd_neq_vm, INSN_DREF },
+-{"vlsseg5e8.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),tVm", MATCH_VLSSEG5E8V, MASK_VLSSEG5E8V, match_vd_neq_vm, INSN_DREF },
+-{"vssseg5e8.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),tVm", MATCH_VSSSEG5E8V, MASK_VSSSEG5E8V, match_vd_neq_vm, INSN_DREF },
+-{"vlsseg6e8.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),tVm", MATCH_VLSSEG6E8V, MASK_VLSSEG6E8V, match_vd_neq_vm, INSN_DREF },
+-{"vssseg6e8.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),tVm", MATCH_VSSSEG6E8V, MASK_VSSSEG6E8V, match_vd_neq_vm, INSN_DREF },
+-{"vlsseg7e8.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),tVm", MATCH_VLSSEG7E8V, MASK_VLSSEG7E8V, match_vd_neq_vm, INSN_DREF },
+-{"vssseg7e8.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),tVm", MATCH_VSSSEG7E8V, MASK_VSSSEG7E8V, match_vd_neq_vm, INSN_DREF },
+-{"vlsseg8e8.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),tVm", MATCH_VLSSEG8E8V, MASK_VLSSEG8E8V, match_vd_neq_vm, INSN_DREF },
+-{"vssseg8e8.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),tVm", MATCH_VSSSEG8E8V, MASK_VSSSEG8E8V, match_vd_neq_vm, INSN_DREF },
+-
+-{"vlsseg2e16.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),tVm", MATCH_VLSSEG2E16V, MASK_VLSSEG2E16V, match_vd_neq_vm, INSN_DREF },
+-{"vssseg2e16.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),tVm", MATCH_VSSSEG2E16V, MASK_VSSSEG2E16V, match_vd_neq_vm, INSN_DREF },
+-{"vlsseg3e16.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),tVm", MATCH_VLSSEG3E16V, MASK_VLSSEG3E16V, match_vd_neq_vm, INSN_DREF },
+-{"vssseg3e16.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),tVm", MATCH_VSSSEG3E16V, MASK_VSSSEG3E16V, match_vd_neq_vm, INSN_DREF },
+-{"vlsseg4e16.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),tVm", MATCH_VLSSEG4E16V, MASK_VLSSEG4E16V, match_vd_neq_vm, INSN_DREF },
+-{"vssseg4e16.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),tVm", MATCH_VSSSEG4E16V, MASK_VSSSEG4E16V, match_vd_neq_vm, INSN_DREF },
+-{"vlsseg5e16.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),tVm", MATCH_VLSSEG5E16V, MASK_VLSSEG5E16V, match_vd_neq_vm, INSN_DREF },
+-{"vssseg5e16.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),tVm", MATCH_VSSSEG5E16V, MASK_VSSSEG5E16V, match_vd_neq_vm, INSN_DREF },
+-{"vlsseg6e16.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),tVm", MATCH_VLSSEG6E16V, MASK_VLSSEG6E16V, match_vd_neq_vm, INSN_DREF },
+-{"vssseg6e16.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),tVm", MATCH_VSSSEG6E16V, MASK_VSSSEG6E16V, match_vd_neq_vm, INSN_DREF },
+-{"vlsseg7e16.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),tVm", MATCH_VLSSEG7E16V, MASK_VLSSEG7E16V, match_vd_neq_vm, INSN_DREF },
+-{"vssseg7e16.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),tVm", MATCH_VSSSEG7E16V, MASK_VSSSEG7E16V, match_vd_neq_vm, INSN_DREF },
+-{"vlsseg8e16.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),tVm", MATCH_VLSSEG8E16V, MASK_VLSSEG8E16V, match_vd_neq_vm, INSN_DREF },
+-{"vssseg8e16.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),tVm", MATCH_VSSSEG8E16V, MASK_VSSSEG8E16V, match_vd_neq_vm, INSN_DREF },
+-
+-{"vlsseg2e32.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),tVm", MATCH_VLSSEG2E32V, MASK_VLSSEG2E32V, match_vd_neq_vm, INSN_DREF },
+-{"vssseg2e32.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),tVm", MATCH_VSSSEG2E32V, MASK_VSSSEG2E32V, match_vd_neq_vm, INSN_DREF },
+-{"vlsseg3e32.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),tVm", MATCH_VLSSEG3E32V, MASK_VLSSEG3E32V, match_vd_neq_vm, INSN_DREF },
+-{"vssseg3e32.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),tVm", MATCH_VSSSEG3E32V, MASK_VSSSEG3E32V, match_vd_neq_vm, INSN_DREF },
+-{"vlsseg4e32.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),tVm", MATCH_VLSSEG4E32V, MASK_VLSSEG4E32V, match_vd_neq_vm, INSN_DREF },
+-{"vssseg4e32.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),tVm", MATCH_VSSSEG4E32V, MASK_VSSSEG4E32V, match_vd_neq_vm, INSN_DREF },
+-{"vlsseg5e32.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),tVm", MATCH_VLSSEG5E32V, MASK_VLSSEG5E32V, match_vd_neq_vm, INSN_DREF },
+-{"vssseg5e32.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),tVm", MATCH_VSSSEG5E32V, MASK_VSSSEG5E32V, match_vd_neq_vm, INSN_DREF },
+-{"vlsseg6e32.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),tVm", MATCH_VLSSEG6E32V, MASK_VLSSEG6E32V, match_vd_neq_vm, INSN_DREF },
+-{"vssseg6e32.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),tVm", MATCH_VSSSEG6E32V, MASK_VSSSEG6E32V, match_vd_neq_vm, INSN_DREF },
+-{"vlsseg7e32.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),tVm", MATCH_VLSSEG7E32V, MASK_VLSSEG7E32V, match_vd_neq_vm, INSN_DREF },
+-{"vssseg7e32.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),tVm", MATCH_VSSSEG7E32V, MASK_VSSSEG7E32V, match_vd_neq_vm, INSN_DREF },
+-{"vlsseg8e32.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),tVm", MATCH_VLSSEG8E32V, MASK_VLSSEG8E32V, match_vd_neq_vm, INSN_DREF },
+-{"vssseg8e32.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),tVm", MATCH_VSSSEG8E32V, MASK_VSSSEG8E32V, match_vd_neq_vm, INSN_DREF },
+-
+-{"vlsseg2e64.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),tVm", MATCH_VLSSEG2E64V, MASK_VLSSEG2E64V, match_vd_neq_vm, INSN_DREF },
+-{"vssseg2e64.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),tVm", MATCH_VSSSEG2E64V, MASK_VSSSEG2E64V, match_vd_neq_vm, INSN_DREF },
+-{"vlsseg3e64.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),tVm", MATCH_VLSSEG3E64V, MASK_VLSSEG3E64V, match_vd_neq_vm, INSN_DREF },
+-{"vssseg3e64.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),tVm", MATCH_VSSSEG3E64V, MASK_VSSSEG3E64V, match_vd_neq_vm, INSN_DREF },
+-{"vlsseg4e64.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),tVm", MATCH_VLSSEG4E64V, MASK_VLSSEG4E64V, match_vd_neq_vm, INSN_DREF },
+-{"vssseg4e64.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),tVm", MATCH_VSSSEG4E64V, MASK_VSSSEG4E64V, match_vd_neq_vm, INSN_DREF },
+-{"vlsseg5e64.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),tVm", MATCH_VLSSEG5E64V, MASK_VLSSEG5E64V, match_vd_neq_vm, INSN_DREF },
+-{"vssseg5e64.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),tVm", MATCH_VSSSEG5E64V, MASK_VSSSEG5E64V, match_vd_neq_vm, INSN_DREF },
+-{"vlsseg6e64.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),tVm", MATCH_VLSSEG6E64V, MASK_VLSSEG6E64V, match_vd_neq_vm, INSN_DREF },
+-{"vssseg6e64.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),tVm", MATCH_VSSSEG6E64V, MASK_VSSSEG6E64V, match_vd_neq_vm, INSN_DREF },
+-{"vlsseg7e64.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),tVm", MATCH_VLSSEG7E64V, MASK_VLSSEG7E64V, match_vd_neq_vm, INSN_DREF },
+-{"vssseg7e64.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),tVm", MATCH_VSSSEG7E64V, MASK_VSSSEG7E64V, match_vd_neq_vm, INSN_DREF },
+-{"vlsseg8e64.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),tVm", MATCH_VLSSEG8E64V, MASK_VLSSEG8E64V, match_vd_neq_vm, INSN_DREF },
+-{"vssseg8e64.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),tVm", MATCH_VSSSEG8E64V, MASK_VSSSEG8E64V, match_vd_neq_vm, INSN_DREF },
+-
+-{"vloxseg2ei8.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),VtVm", MATCH_VLOXSEG2EI8V, MASK_VLOXSEG2EI8V, match_vd_neq_vs2_neq_vm, INSN_DREF },
+-{"vsoxseg2ei8.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),VtVm", MATCH_VSOXSEG2EI8V, MASK_VSOXSEG2EI8V, match_vd_neq_vs2_neq_vm, INSN_DREF },
+-{"vloxseg3ei8.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),VtVm", MATCH_VLOXSEG3EI8V, MASK_VLOXSEG3EI8V, match_vd_neq_vs2_neq_vm, INSN_DREF },
+-{"vsoxseg3ei8.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),VtVm", MATCH_VSOXSEG3EI8V, MASK_VSOXSEG3EI8V, match_vd_neq_vs2_neq_vm, INSN_DREF },
+-{"vloxseg4ei8.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),VtVm", MATCH_VLOXSEG4EI8V, MASK_VLOXSEG4EI8V, match_vd_neq_vs2_neq_vm, INSN_DREF },
+-{"vsoxseg4ei8.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),VtVm", MATCH_VSOXSEG4EI8V, MASK_VSOXSEG4EI8V, match_vd_neq_vs2_neq_vm, INSN_DREF },
+-{"vloxseg5ei8.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),VtVm", MATCH_VLOXSEG5EI8V, MASK_VLOXSEG5EI8V, match_vd_neq_vs2_neq_vm, INSN_DREF },
+-{"vsoxseg5ei8.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),VtVm", MATCH_VSOXSEG5EI8V, MASK_VSOXSEG5EI8V, match_vd_neq_vs2_neq_vm, INSN_DREF },
+-{"vloxseg6ei8.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),VtVm", MATCH_VLOXSEG6EI8V, MASK_VLOXSEG6EI8V, match_vd_neq_vs2_neq_vm, INSN_DREF },
+-{"vsoxseg6ei8.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),VtVm", MATCH_VSOXSEG6EI8V, MASK_VSOXSEG6EI8V, match_vd_neq_vs2_neq_vm, INSN_DREF },
+-{"vloxseg7ei8.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),VtVm", MATCH_VLOXSEG7EI8V, MASK_VLOXSEG7EI8V, match_vd_neq_vs2_neq_vm, INSN_DREF },
+-{"vsoxseg7ei8.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),VtVm", MATCH_VSOXSEG7EI8V, MASK_VSOXSEG7EI8V, match_vd_neq_vs2_neq_vm, INSN_DREF },
+-{"vloxseg8ei8.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),VtVm", MATCH_VLOXSEG8EI8V, MASK_VLOXSEG8EI8V, match_vd_neq_vs2_neq_vm, INSN_DREF },
+-{"vsoxseg8ei8.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),VtVm", MATCH_VSOXSEG8EI8V, MASK_VSOXSEG8EI8V, match_vd_neq_vs2_neq_vm, INSN_DREF },
+-
+-{"vloxseg2ei16.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),VtVm", MATCH_VLOXSEG2EI16V, MASK_VLOXSEG2EI16V, match_vd_neq_vs2_neq_vm, INSN_DREF },
+-{"vsoxseg2ei16.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),VtVm", MATCH_VSOXSEG2EI16V, MASK_VSOXSEG2EI16V, match_vd_neq_vs2_neq_vm, INSN_DREF },
+-{"vloxseg3ei16.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),VtVm", MATCH_VLOXSEG3EI16V, MASK_VLOXSEG3EI16V, match_vd_neq_vs2_neq_vm, INSN_DREF },
+-{"vsoxseg3ei16.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),VtVm", MATCH_VSOXSEG3EI16V, MASK_VSOXSEG3EI16V, match_vd_neq_vs2_neq_vm, INSN_DREF },
+-{"vloxseg4ei16.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),VtVm", MATCH_VLOXSEG4EI16V, MASK_VLOXSEG4EI16V, match_vd_neq_vs2_neq_vm, INSN_DREF },
+-{"vsoxseg4ei16.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),VtVm", MATCH_VSOXSEG4EI16V, MASK_VSOXSEG4EI16V, match_vd_neq_vs2_neq_vm, INSN_DREF },
+-{"vloxseg5ei16.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),VtVm", MATCH_VLOXSEG5EI16V, MASK_VLOXSEG5EI16V, match_vd_neq_vs2_neq_vm, INSN_DREF },
+-{"vsoxseg5ei16.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),VtVm", MATCH_VSOXSEG5EI16V, MASK_VSOXSEG5EI16V, match_vd_neq_vs2_neq_vm, INSN_DREF },
+-{"vloxseg6ei16.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),VtVm", MATCH_VLOXSEG6EI16V, MASK_VLOXSEG6EI16V, match_vd_neq_vs2_neq_vm, INSN_DREF },
+-{"vsoxseg6ei16.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),VtVm", MATCH_VSOXSEG6EI16V, MASK_VSOXSEG6EI16V, match_vd_neq_vs2_neq_vm, INSN_DREF },
+-{"vloxseg7ei16.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),VtVm", MATCH_VLOXSEG7EI16V, MASK_VLOXSEG7EI16V, match_vd_neq_vs2_neq_vm, INSN_DREF },
+-{"vsoxseg7ei16.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),VtVm", MATCH_VSOXSEG7EI16V, MASK_VSOXSEG7EI16V, match_vd_neq_vs2_neq_vm, INSN_DREF },
+-{"vloxseg8ei16.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),VtVm", MATCH_VLOXSEG8EI16V, MASK_VLOXSEG8EI16V, match_vd_neq_vs2_neq_vm, INSN_DREF },
+-{"vsoxseg8ei16.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),VtVm", MATCH_VSOXSEG8EI16V, MASK_VSOXSEG8EI16V, match_vd_neq_vs2_neq_vm, INSN_DREF },
+-
+-{"vloxseg2ei32.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),VtVm", MATCH_VLOXSEG2EI32V, MASK_VLOXSEG2EI32V, match_vd_neq_vs2_neq_vm, INSN_DREF },
+-{"vsoxseg2ei32.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),VtVm", MATCH_VSOXSEG2EI32V, MASK_VSOXSEG2EI32V, match_vd_neq_vs2_neq_vm, INSN_DREF },
+-{"vloxseg3ei32.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),VtVm", MATCH_VLOXSEG3EI32V, MASK_VLOXSEG3EI32V, match_vd_neq_vs2_neq_vm, INSN_DREF },
+-{"vsoxseg3ei32.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),VtVm", MATCH_VSOXSEG3EI32V, MASK_VSOXSEG3EI32V, match_vd_neq_vs2_neq_vm, INSN_DREF },
+-{"vloxseg4ei32.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),VtVm", MATCH_VLOXSEG4EI32V, MASK_VLOXSEG4EI32V, match_vd_neq_vs2_neq_vm, INSN_DREF },
+-{"vsoxseg4ei32.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),VtVm", MATCH_VSOXSEG4EI32V, MASK_VSOXSEG4EI32V, match_vd_neq_vs2_neq_vm, INSN_DREF },
+-{"vloxseg5ei32.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),VtVm", MATCH_VLOXSEG5EI32V, MASK_VLOXSEG5EI32V, match_vd_neq_vs2_neq_vm, INSN_DREF },
+-{"vsoxseg5ei32.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),VtVm", MATCH_VSOXSEG5EI32V, MASK_VSOXSEG5EI32V, match_vd_neq_vs2_neq_vm, INSN_DREF },
+-{"vloxseg6ei32.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),VtVm", MATCH_VLOXSEG6EI32V, MASK_VLOXSEG6EI32V, match_vd_neq_vs2_neq_vm, INSN_DREF },
+-{"vsoxseg6ei32.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),VtVm", MATCH_VSOXSEG6EI32V, MASK_VSOXSEG6EI32V, match_vd_neq_vs2_neq_vm, INSN_DREF },
+-{"vloxseg7ei32.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),VtVm", MATCH_VLOXSEG7EI32V, MASK_VLOXSEG7EI32V, match_vd_neq_vs2_neq_vm, INSN_DREF },
+-{"vsoxseg7ei32.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),VtVm", MATCH_VSOXSEG7EI32V, MASK_VSOXSEG7EI32V, match_vd_neq_vs2_neq_vm, INSN_DREF },
+-{"vloxseg8ei32.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),VtVm", MATCH_VLOXSEG8EI32V, MASK_VLOXSEG8EI32V, match_vd_neq_vs2_neq_vm, INSN_DREF },
+-{"vsoxseg8ei32.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),VtVm", MATCH_VSOXSEG8EI32V, MASK_VSOXSEG8EI32V, match_vd_neq_vs2_neq_vm, INSN_DREF },
+-
+-{"vloxseg2ei64.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),VtVm", MATCH_VLOXSEG2EI64V, MASK_VLOXSEG2EI64V, match_vd_neq_vs2_neq_vm, INSN_DREF },
+-{"vsoxseg2ei64.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),VtVm", MATCH_VSOXSEG2EI64V, MASK_VSOXSEG2EI64V, match_vd_neq_vs2_neq_vm, INSN_DREF },
+-{"vloxseg3ei64.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),VtVm", MATCH_VLOXSEG3EI64V, MASK_VLOXSEG3EI64V, match_vd_neq_vs2_neq_vm, INSN_DREF },
+-{"vsoxseg3ei64.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),VtVm", MATCH_VSOXSEG3EI64V, MASK_VSOXSEG3EI64V, match_vd_neq_vs2_neq_vm, INSN_DREF },
+-{"vloxseg4ei64.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),VtVm", MATCH_VLOXSEG4EI64V, MASK_VLOXSEG4EI64V, match_vd_neq_vs2_neq_vm, INSN_DREF },
+-{"vsoxseg4ei64.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),VtVm", MATCH_VSOXSEG4EI64V, MASK_VSOXSEG4EI64V, match_vd_neq_vs2_neq_vm, INSN_DREF },
+-{"vloxseg5ei64.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),VtVm", MATCH_VLOXSEG5EI64V, MASK_VLOXSEG5EI64V, match_vd_neq_vs2_neq_vm, INSN_DREF },
+-{"vsoxseg5ei64.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),VtVm", MATCH_VSOXSEG5EI64V, MASK_VSOXSEG5EI64V, match_vd_neq_vs2_neq_vm, INSN_DREF },
+-{"vloxseg6ei64.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),VtVm", MATCH_VLOXSEG6EI64V, MASK_VLOXSEG6EI64V, match_vd_neq_vs2_neq_vm, INSN_DREF },
+-{"vsoxseg6ei64.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),VtVm", MATCH_VSOXSEG6EI64V, MASK_VSOXSEG6EI64V, match_vd_neq_vs2_neq_vm, INSN_DREF },
+-{"vloxseg7ei64.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),VtVm", MATCH_VLOXSEG7EI64V, MASK_VLOXSEG7EI64V, match_vd_neq_vs2_neq_vm, INSN_DREF },
+-{"vsoxseg7ei64.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),VtVm", MATCH_VSOXSEG7EI64V, MASK_VSOXSEG7EI64V, match_vd_neq_vs2_neq_vm, INSN_DREF },
+-{"vloxseg8ei64.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),VtVm", MATCH_VLOXSEG8EI64V, MASK_VLOXSEG8EI64V, match_vd_neq_vs2_neq_vm, INSN_DREF },
+-{"vsoxseg8ei64.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),VtVm", MATCH_VSOXSEG8EI64V, MASK_VSOXSEG8EI64V, match_vd_neq_vs2_neq_vm, INSN_DREF },
+-
+-{"vluxseg2ei8.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),VtVm", MATCH_VLUXSEG2EI8V, MASK_VLUXSEG2EI8V, match_vd_neq_vs2_neq_vm, INSN_DREF },
+-{"vsuxseg2ei8.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),VtVm", MATCH_VSUXSEG2EI8V, MASK_VSUXSEG2EI8V, match_vd_neq_vs2_neq_vm, INSN_DREF },
+-{"vluxseg3ei8.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),VtVm", MATCH_VLUXSEG3EI8V, MASK_VLUXSEG3EI8V, match_vd_neq_vs2_neq_vm, INSN_DREF },
+-{"vsuxseg3ei8.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),VtVm", MATCH_VSUXSEG3EI8V, MASK_VSUXSEG3EI8V, match_vd_neq_vs2_neq_vm, INSN_DREF },
+-{"vluxseg4ei8.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),VtVm", MATCH_VLUXSEG4EI8V, MASK_VLUXSEG4EI8V, match_vd_neq_vs2_neq_vm, INSN_DREF },
+-{"vsuxseg4ei8.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),VtVm", MATCH_VSUXSEG4EI8V, MASK_VSUXSEG4EI8V, match_vd_neq_vs2_neq_vm, INSN_DREF },
+-{"vluxseg5ei8.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),VtVm", MATCH_VLUXSEG5EI8V, MASK_VLUXSEG5EI8V, match_vd_neq_vs2_neq_vm, INSN_DREF },
+-{"vsuxseg5ei8.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),VtVm", MATCH_VSUXSEG5EI8V, MASK_VSUXSEG5EI8V, match_vd_neq_vs2_neq_vm, INSN_DREF },
+-{"vluxseg6ei8.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),VtVm", MATCH_VLUXSEG6EI8V, MASK_VLUXSEG6EI8V, match_vd_neq_vs2_neq_vm, INSN_DREF },
+-{"vsuxseg6ei8.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),VtVm", MATCH_VSUXSEG6EI8V, MASK_VSUXSEG6EI8V, match_vd_neq_vs2_neq_vm, INSN_DREF },
+-{"vluxseg7ei8.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),VtVm", MATCH_VLUXSEG7EI8V, MASK_VLUXSEG7EI8V, match_vd_neq_vs2_neq_vm, INSN_DREF },
+-{"vsuxseg7ei8.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),VtVm", MATCH_VSUXSEG7EI8V, MASK_VSUXSEG7EI8V, match_vd_neq_vs2_neq_vm, INSN_DREF },
+-{"vluxseg8ei8.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),VtVm", MATCH_VLUXSEG8EI8V, MASK_VLUXSEG8EI8V, match_vd_neq_vs2_neq_vm, INSN_DREF },
+-{"vsuxseg8ei8.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),VtVm", MATCH_VSUXSEG8EI8V, MASK_VSUXSEG8EI8V, match_vd_neq_vs2_neq_vm, INSN_DREF },
+-
+-{"vluxseg2ei16.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),VtVm", MATCH_VLUXSEG2EI16V, MASK_VLUXSEG2EI16V, match_vd_neq_vs2_neq_vm, INSN_DREF },
+-{"vsuxseg2ei16.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),VtVm", MATCH_VSUXSEG2EI16V, MASK_VSUXSEG2EI16V, match_vd_neq_vs2_neq_vm, INSN_DREF },
+-{"vluxseg3ei16.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),VtVm", MATCH_VLUXSEG3EI16V, MASK_VLUXSEG3EI16V, match_vd_neq_vs2_neq_vm, INSN_DREF },
+-{"vsuxseg3ei16.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),VtVm", MATCH_VSUXSEG3EI16V, MASK_VSUXSEG3EI16V, match_vd_neq_vs2_neq_vm, INSN_DREF },
+-{"vluxseg4ei16.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),VtVm", MATCH_VLUXSEG4EI16V, MASK_VLUXSEG4EI16V, match_vd_neq_vs2_neq_vm, INSN_DREF },
+-{"vsuxseg4ei16.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),VtVm", MATCH_VSUXSEG4EI16V, MASK_VSUXSEG4EI16V, match_vd_neq_vs2_neq_vm, INSN_DREF },
+-{"vluxseg5ei16.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),VtVm", MATCH_VLUXSEG5EI16V, MASK_VLUXSEG5EI16V, match_vd_neq_vs2_neq_vm, INSN_DREF },
+-{"vsuxseg5ei16.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),VtVm", MATCH_VSUXSEG5EI16V, MASK_VSUXSEG5EI16V, match_vd_neq_vs2_neq_vm, INSN_DREF },
+-{"vluxseg6ei16.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),VtVm", MATCH_VLUXSEG6EI16V, MASK_VLUXSEG6EI16V, match_vd_neq_vs2_neq_vm, INSN_DREF },
+-{"vsuxseg6ei16.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),VtVm", MATCH_VSUXSEG6EI16V, MASK_VSUXSEG6EI16V, match_vd_neq_vs2_neq_vm, INSN_DREF },
+-{"vluxseg7ei16.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),VtVm", MATCH_VLUXSEG7EI16V, MASK_VLUXSEG7EI16V, match_vd_neq_vs2_neq_vm, INSN_DREF },
+-{"vsuxseg7ei16.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),VtVm", MATCH_VSUXSEG7EI16V, MASK_VSUXSEG7EI16V, match_vd_neq_vs2_neq_vm, INSN_DREF },
+-{"vluxseg8ei16.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),VtVm", MATCH_VLUXSEG8EI16V, MASK_VLUXSEG8EI16V, match_vd_neq_vs2_neq_vm, INSN_DREF },
+-{"vsuxseg8ei16.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),VtVm", MATCH_VSUXSEG8EI16V, MASK_VSUXSEG8EI16V, match_vd_neq_vs2_neq_vm, INSN_DREF },
+-
+-{"vluxseg2ei32.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),VtVm", MATCH_VLUXSEG2EI32V, MASK_VLUXSEG2EI32V, match_vd_neq_vs2_neq_vm, INSN_DREF },
+-{"vsuxseg2ei32.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),VtVm", MATCH_VSUXSEG2EI32V, MASK_VSUXSEG2EI32V, match_vd_neq_vs2_neq_vm, INSN_DREF },
+-{"vluxseg3ei32.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),VtVm", MATCH_VLUXSEG3EI32V, MASK_VLUXSEG3EI32V, match_vd_neq_vs2_neq_vm, INSN_DREF },
+-{"vsuxseg3ei32.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),VtVm", MATCH_VSUXSEG3EI32V, MASK_VSUXSEG3EI32V, match_vd_neq_vs2_neq_vm, INSN_DREF },
+-{"vluxseg4ei32.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),VtVm", MATCH_VLUXSEG4EI32V, MASK_VLUXSEG4EI32V, match_vd_neq_vs2_neq_vm, INSN_DREF },
+-{"vsuxseg4ei32.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),VtVm", MATCH_VSUXSEG4EI32V, MASK_VSUXSEG4EI32V, match_vd_neq_vs2_neq_vm, INSN_DREF },
+-{"vluxseg5ei32.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),VtVm", MATCH_VLUXSEG5EI32V, MASK_VLUXSEG5EI32V, match_vd_neq_vs2_neq_vm, INSN_DREF },
+-{"vsuxseg5ei32.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),VtVm", MATCH_VSUXSEG5EI32V, MASK_VSUXSEG5EI32V, match_vd_neq_vs2_neq_vm, INSN_DREF },
+-{"vluxseg6ei32.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),VtVm", MATCH_VLUXSEG6EI32V, MASK_VLUXSEG6EI32V, match_vd_neq_vs2_neq_vm, INSN_DREF },
+-{"vsuxseg6ei32.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),VtVm", MATCH_VSUXSEG6EI32V, MASK_VSUXSEG6EI32V, match_vd_neq_vs2_neq_vm, INSN_DREF },
+-{"vluxseg7ei32.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),VtVm", MATCH_VLUXSEG7EI32V, MASK_VLUXSEG7EI32V, match_vd_neq_vs2_neq_vm, INSN_DREF },
+-{"vsuxseg7ei32.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),VtVm", MATCH_VSUXSEG7EI32V, MASK_VSUXSEG7EI32V, match_vd_neq_vs2_neq_vm, INSN_DREF },
+-{"vluxseg8ei32.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),VtVm", MATCH_VLUXSEG8EI32V, MASK_VLUXSEG8EI32V, match_vd_neq_vs2_neq_vm, INSN_DREF },
+-{"vsuxseg8ei32.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),VtVm", MATCH_VSUXSEG8EI32V, MASK_VSUXSEG8EI32V, match_vd_neq_vs2_neq_vm, INSN_DREF },
+-
+-{"vluxseg2ei64.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),VtVm", MATCH_VLUXSEG2EI64V, MASK_VLUXSEG2EI64V, match_vd_neq_vs2_neq_vm, INSN_DREF },
+-{"vsuxseg2ei64.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),VtVm", MATCH_VSUXSEG2EI64V, MASK_VSUXSEG2EI64V, match_vd_neq_vs2_neq_vm, INSN_DREF },
+-{"vluxseg3ei64.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),VtVm", MATCH_VLUXSEG3EI64V, MASK_VLUXSEG3EI64V, match_vd_neq_vs2_neq_vm, INSN_DREF },
+-{"vsuxseg3ei64.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),VtVm", MATCH_VSUXSEG3EI64V, MASK_VSUXSEG3EI64V, match_vd_neq_vs2_neq_vm, INSN_DREF },
+-{"vluxseg4ei64.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),VtVm", MATCH_VLUXSEG4EI64V, MASK_VLUXSEG4EI64V, match_vd_neq_vs2_neq_vm, INSN_DREF },
+-{"vsuxseg4ei64.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),VtVm", MATCH_VSUXSEG4EI64V, MASK_VSUXSEG4EI64V, match_vd_neq_vs2_neq_vm, INSN_DREF },
+-{"vluxseg5ei64.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),VtVm", MATCH_VLUXSEG5EI64V, MASK_VLUXSEG5EI64V, match_vd_neq_vs2_neq_vm, INSN_DREF },
+-{"vsuxseg5ei64.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),VtVm", MATCH_VSUXSEG5EI64V, MASK_VSUXSEG5EI64V, match_vd_neq_vs2_neq_vm, INSN_DREF },
+-{"vluxseg6ei64.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),VtVm", MATCH_VLUXSEG6EI64V, MASK_VLUXSEG6EI64V, match_vd_neq_vs2_neq_vm, INSN_DREF },
+-{"vsuxseg6ei64.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),VtVm", MATCH_VSUXSEG6EI64V, MASK_VSUXSEG6EI64V, match_vd_neq_vs2_neq_vm, INSN_DREF },
+-{"vluxseg7ei64.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),VtVm", MATCH_VLUXSEG7EI64V, MASK_VLUXSEG7EI64V, match_vd_neq_vs2_neq_vm, INSN_DREF },
+-{"vsuxseg7ei64.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),VtVm", MATCH_VSUXSEG7EI64V, MASK_VSUXSEG7EI64V, match_vd_neq_vs2_neq_vm, INSN_DREF },
+-{"vluxseg8ei64.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),VtVm", MATCH_VLUXSEG8EI64V, MASK_VLUXSEG8EI64V, match_vd_neq_vs2_neq_vm, INSN_DREF },
+-{"vsuxseg8ei64.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),VtVm", MATCH_VSUXSEG8EI64V, MASK_VSUXSEG8EI64V, match_vd_neq_vs2_neq_vm, INSN_DREF },
+-
+-{"vlseg2e8ff.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s)Vm", MATCH_VLSEG2E8FFV, MASK_VLSEG2E8FFV, match_vd_neq_vm, INSN_DREF },
+-{"vlseg3e8ff.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s)Vm", MATCH_VLSEG3E8FFV, MASK_VLSEG3E8FFV, match_vd_neq_vm, INSN_DREF },
+-{"vlseg4e8ff.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s)Vm", MATCH_VLSEG4E8FFV, MASK_VLSEG4E8FFV, match_vd_neq_vm, INSN_DREF },
+-{"vlseg5e8ff.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s)Vm", MATCH_VLSEG5E8FFV, MASK_VLSEG5E8FFV, match_vd_neq_vm, INSN_DREF },
+-{"vlseg6e8ff.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s)Vm", MATCH_VLSEG6E8FFV, MASK_VLSEG6E8FFV, match_vd_neq_vm, INSN_DREF },
+-{"vlseg7e8ff.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s)Vm", MATCH_VLSEG7E8FFV, MASK_VLSEG7E8FFV, match_vd_neq_vm, INSN_DREF },
+-{"vlseg8e8ff.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s)Vm", MATCH_VLSEG8E8FFV, MASK_VLSEG8E8FFV, match_vd_neq_vm, INSN_DREF },
+-
+-{"vlseg2e16ff.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s)Vm", MATCH_VLSEG2E16FFV, MASK_VLSEG2E16FFV, match_vd_neq_vm, INSN_DREF },
+-{"vlseg3e16ff.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s)Vm", MATCH_VLSEG3E16FFV, MASK_VLSEG3E16FFV, match_vd_neq_vm, INSN_DREF },
+-{"vlseg4e16ff.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s)Vm", MATCH_VLSEG4E16FFV, MASK_VLSEG4E16FFV, match_vd_neq_vm, INSN_DREF },
+-{"vlseg5e16ff.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s)Vm", MATCH_VLSEG5E16FFV, MASK_VLSEG5E16FFV, match_vd_neq_vm, INSN_DREF },
+-{"vlseg6e16ff.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s)Vm", MATCH_VLSEG6E16FFV, MASK_VLSEG6E16FFV, match_vd_neq_vm, INSN_DREF },
+-{"vlseg7e16ff.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s)Vm", MATCH_VLSEG7E16FFV, MASK_VLSEG7E16FFV, match_vd_neq_vm, INSN_DREF },
+-{"vlseg8e16ff.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s)Vm", MATCH_VLSEG8E16FFV, MASK_VLSEG8E16FFV, match_vd_neq_vm, INSN_DREF },
+-
+-{"vlseg2e32ff.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s)Vm", MATCH_VLSEG2E32FFV, MASK_VLSEG2E32FFV, match_vd_neq_vm, INSN_DREF },
+-{"vlseg3e32ff.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s)Vm", MATCH_VLSEG3E32FFV, MASK_VLSEG3E32FFV, match_vd_neq_vm, INSN_DREF },
+-{"vlseg4e32ff.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s)Vm", MATCH_VLSEG4E32FFV, MASK_VLSEG4E32FFV, match_vd_neq_vm, INSN_DREF },
+-{"vlseg5e32ff.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s)Vm", MATCH_VLSEG5E32FFV, MASK_VLSEG5E32FFV, match_vd_neq_vm, INSN_DREF },
+-{"vlseg6e32ff.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s)Vm", MATCH_VLSEG6E32FFV, MASK_VLSEG6E32FFV, match_vd_neq_vm, INSN_DREF },
+-{"vlseg7e32ff.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s)Vm", MATCH_VLSEG7E32FFV, MASK_VLSEG7E32FFV, match_vd_neq_vm, INSN_DREF },
+-{"vlseg8e32ff.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s)Vm", MATCH_VLSEG8E32FFV, MASK_VLSEG8E32FFV, match_vd_neq_vm, INSN_DREF },
+-
+-{"vlseg2e64ff.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s)Vm", MATCH_VLSEG2E64FFV, MASK_VLSEG2E64FFV, match_vd_neq_vm, INSN_DREF },
+-{"vlseg3e64ff.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s)Vm", MATCH_VLSEG3E64FFV, MASK_VLSEG3E64FFV, match_vd_neq_vm, INSN_DREF },
+-{"vlseg4e64ff.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s)Vm", MATCH_VLSEG4E64FFV, MASK_VLSEG4E64FFV, match_vd_neq_vm, INSN_DREF },
+-{"vlseg5e64ff.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s)Vm", MATCH_VLSEG5E64FFV, MASK_VLSEG5E64FFV, match_vd_neq_vm, INSN_DREF },
+-{"vlseg6e64ff.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s)Vm", MATCH_VLSEG6E64FFV, MASK_VLSEG6E64FFV, match_vd_neq_vm, INSN_DREF },
+-{"vlseg7e64ff.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s)Vm", MATCH_VLSEG7E64FFV, MASK_VLSEG7E64FFV, match_vd_neq_vm, INSN_DREF },
+-{"vlseg8e64ff.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s)Vm", MATCH_VLSEG8E64FFV, MASK_VLSEG8E64FFV, match_vd_neq_vm, INSN_DREF },
+-
+-{"vl1r.v",      0, INSN_CLASS_V,  "Vd,0(s)", MATCH_VL1RE8V, MASK_VL1RE8V, match_vls_nf_rv, INSN_DREF|INSN_ALIAS },
+-{"vl1re8.v",    0, INSN_CLASS_V,  "Vd,0(s)", MATCH_VL1RE8V, MASK_VL1RE8V, match_vls_nf_rv, INSN_DREF },
+-{"vl1re16.v",   0, INSN_CLASS_V,  "Vd,0(s)", MATCH_VL1RE16V, MASK_VL1RE16V, match_vls_nf_rv, INSN_DREF },
+-{"vl1re32.v",   0, INSN_CLASS_V,  "Vd,0(s)", MATCH_VL1RE32V, MASK_VL1RE32V, match_vls_nf_rv, INSN_DREF },
+-{"vl1re64.v",   0, INSN_CLASS_V,  "Vd,0(s)", MATCH_VL1RE64V, MASK_VL1RE64V, match_vls_nf_rv, INSN_DREF },
+-
+-{"vl2r.v",      0, INSN_CLASS_V,  "Vd,0(s)", MATCH_VL2RE8V, MASK_VL2RE8V, match_vls_nf_rv, INSN_DREF|INSN_ALIAS },
+-{"vl2re8.v",    0, INSN_CLASS_V,  "Vd,0(s)", MATCH_VL2RE8V, MASK_VL2RE8V, match_vls_nf_rv, INSN_DREF },
+-{"vl2re16.v",   0, INSN_CLASS_V,  "Vd,0(s)", MATCH_VL2RE16V, MASK_VL2RE16V, match_vls_nf_rv, INSN_DREF },
+-{"vl2re32.v",   0, INSN_CLASS_V,  "Vd,0(s)", MATCH_VL2RE32V, MASK_VL2RE32V, match_vls_nf_rv, INSN_DREF },
+-{"vl2re64.v",   0, INSN_CLASS_V,  "Vd,0(s)", MATCH_VL2RE64V, MASK_VL2RE64V, match_vls_nf_rv, INSN_DREF },
+-
+-{"vl4r.v",      0, INSN_CLASS_V,  "Vd,0(s)", MATCH_VL4RE8V, MASK_VL4RE8V, match_vls_nf_rv, INSN_DREF|INSN_ALIAS },
+-{"vl4re8.v",    0, INSN_CLASS_V,  "Vd,0(s)", MATCH_VL4RE8V, MASK_VL4RE8V, match_vls_nf_rv, INSN_DREF },
+-{"vl4re16.v",   0, INSN_CLASS_V,  "Vd,0(s)", MATCH_VL4RE16V, MASK_VL4RE16V, match_vls_nf_rv, INSN_DREF },
+-{"vl4re32.v",   0, INSN_CLASS_V,  "Vd,0(s)", MATCH_VL4RE32V, MASK_VL4RE32V, match_vls_nf_rv, INSN_DREF },
+-{"vl4re64.v",   0, INSN_CLASS_V,  "Vd,0(s)", MATCH_VL4RE64V, MASK_VL4RE64V, match_vls_nf_rv, INSN_DREF },
+-
+-{"vl8r.v",      0, INSN_CLASS_V,  "Vd,0(s)", MATCH_VL8RE8V, MASK_VL8RE8V, match_vls_nf_rv, INSN_DREF|INSN_ALIAS },
+-{"vl8re8.v",    0, INSN_CLASS_V,  "Vd,0(s)", MATCH_VL8RE8V, MASK_VL8RE8V, match_vls_nf_rv, INSN_DREF },
+-{"vl8re16.v",   0, INSN_CLASS_V,  "Vd,0(s)", MATCH_VL8RE16V, MASK_VL8RE16V, match_vls_nf_rv, INSN_DREF },
+-{"vl8re32.v",   0, INSN_CLASS_V,  "Vd,0(s)", MATCH_VL8RE32V, MASK_VL8RE32V, match_vls_nf_rv, INSN_DREF },
+-{"vl8re64.v",   0, INSN_CLASS_V,  "Vd,0(s)", MATCH_VL8RE64V, MASK_VL8RE64V, match_vls_nf_rv, INSN_DREF },
+-
+-{"vs1r.v",  0, INSN_CLASS_V,  "Vd,0(s)", MATCH_VS1RV, MASK_VS1RV, match_vls_nf_rv, INSN_DREF },
+-{"vs2r.v",  0, INSN_CLASS_V,  "Vd,0(s)", MATCH_VS2RV, MASK_VS2RV, match_vls_nf_rv, INSN_DREF },
+-{"vs4r.v",  0, INSN_CLASS_V,  "Vd,0(s)", MATCH_VS4RV, MASK_VS4RV, match_vls_nf_rv, INSN_DREF },
+-{"vs8r.v",  0, INSN_CLASS_V,  "Vd,0(s)", MATCH_VS8RV, MASK_VS8RV, match_vls_nf_rv, INSN_DREF },
+-
+-{"vamoaddei8.v",   0, INSN_CLASS_V_OR_ZVAMO,  "Ve,0(s),Vt,VfVm", MATCH_VAMOADDEI8V, MASK_VAMOADDEI8V, match_vd_neq_vm, INSN_DREF},
+-{"vamoswapei8.v",  0, INSN_CLASS_V_OR_ZVAMO,  "Ve,0(s),Vt,VfVm", MATCH_VAMOSWAPEI8V, MASK_VAMOSWAPEI8V, match_vd_neq_vm, INSN_DREF},
+-{"vamoxorei8.v",   0, INSN_CLASS_V_OR_ZVAMO,  "Ve,0(s),Vt,VfVm", MATCH_VAMOXOREI8V, MASK_VAMOXOREI8V, match_vd_neq_vm, INSN_DREF},
+-{"vamoandei8.v",   0, INSN_CLASS_V_OR_ZVAMO,  "Ve,0(s),Vt,VfVm", MATCH_VAMOANDEI8V, MASK_VAMOANDEI8V, match_vd_neq_vm, INSN_DREF},
+-{"vamoorei8.v",    0, INSN_CLASS_V_OR_ZVAMO,  "Ve,0(s),Vt,VfVm", MATCH_VAMOOREI8V, MASK_VAMOOREI8V, match_vd_neq_vm, INSN_DREF},
+-{"vamominei8.v",   0, INSN_CLASS_V_OR_ZVAMO,  "Ve,0(s),Vt,VfVm", MATCH_VAMOMINEI8V, MASK_VAMOMINEI8V, match_vd_neq_vm, INSN_DREF},
+-{"vamomaxei8.v",   0, INSN_CLASS_V_OR_ZVAMO,  "Ve,0(s),Vt,VfVm", MATCH_VAMOMAXEI8V, MASK_VAMOMAXEI8V, match_vd_neq_vm, INSN_DREF},
+-{"vamominuei8.v",  0, INSN_CLASS_V_OR_ZVAMO,  "Ve,0(s),Vt,VfVm", MATCH_VAMOMINUEI8V, MASK_VAMOMINUEI8V, match_vd_neq_vm, INSN_DREF},
+-{"vamomaxuei8.v",  0, INSN_CLASS_V_OR_ZVAMO,  "Ve,0(s),Vt,VfVm", MATCH_VAMOMAXUEI8V, MASK_VAMOMAXUEI8V, match_vd_neq_vm, INSN_DREF},
+-
+-{"vamoaddei16.v",   0, INSN_CLASS_V_OR_ZVAMO,  "Ve,0(s),Vt,VfVm", MATCH_VAMOADDEI16V, MASK_VAMOADDEI16V, match_vd_neq_vm, INSN_DREF},
+-{"vamoswapei16.v",  0, INSN_CLASS_V_OR_ZVAMO,  "Ve,0(s),Vt,VfVm", MATCH_VAMOSWAPEI16V, MASK_VAMOSWAPEI16V, match_vd_neq_vm, INSN_DREF},
+-{"vamoxorei16.v",   0, INSN_CLASS_V_OR_ZVAMO,  "Ve,0(s),Vt,VfVm", MATCH_VAMOXOREI16V, MASK_VAMOXOREI16V, match_vd_neq_vm, INSN_DREF},
+-{"vamoandei16.v",   0, INSN_CLASS_V_OR_ZVAMO,  "Ve,0(s),Vt,VfVm", MATCH_VAMOANDEI16V, MASK_VAMOANDEI16V, match_vd_neq_vm, INSN_DREF},
+-{"vamoorei16.v",    0, INSN_CLASS_V_OR_ZVAMO,  "Ve,0(s),Vt,VfVm", MATCH_VAMOOREI16V, MASK_VAMOOREI16V, match_vd_neq_vm, INSN_DREF},
+-{"vamominei16.v",   0, INSN_CLASS_V_OR_ZVAMO,  "Ve,0(s),Vt,VfVm", MATCH_VAMOMINEI16V, MASK_VAMOMINEI16V, match_vd_neq_vm, INSN_DREF},
+-{"vamomaxei16.v",   0, INSN_CLASS_V_OR_ZVAMO,  "Ve,0(s),Vt,VfVm", MATCH_VAMOMAXEI16V, MASK_VAMOMAXEI16V, match_vd_neq_vm, INSN_DREF},
+-{"vamominuei16.v",  0, INSN_CLASS_V_OR_ZVAMO,  "Ve,0(s),Vt,VfVm", MATCH_VAMOMINUEI16V, MASK_VAMOMINUEI16V, match_vd_neq_vm, INSN_DREF},
+-{"vamomaxuei16.v",  0, INSN_CLASS_V_OR_ZVAMO,  "Ve,0(s),Vt,VfVm", MATCH_VAMOMAXUEI16V, MASK_VAMOMAXUEI16V, match_vd_neq_vm, INSN_DREF},
+-
+-{"vamoaddei32.v",   0, INSN_CLASS_V_OR_ZVAMO,  "Ve,0(s),Vt,VfVm", MATCH_VAMOADDEI32V, MASK_VAMOADDEI32V, match_vd_neq_vm, INSN_DREF},
+-{"vamoswapei32.v",  0, INSN_CLASS_V_OR_ZVAMO,  "Ve,0(s),Vt,VfVm", MATCH_VAMOSWAPEI32V, MASK_VAMOSWAPEI32V, match_vd_neq_vm, INSN_DREF},
+-{"vamoxorei32.v",   0, INSN_CLASS_V_OR_ZVAMO,  "Ve,0(s),Vt,VfVm", MATCH_VAMOXOREI32V, MASK_VAMOXOREI32V, match_vd_neq_vm, INSN_DREF},
+-{"vamoandei32.v",   0, INSN_CLASS_V_OR_ZVAMO,  "Ve,0(s),Vt,VfVm", MATCH_VAMOANDEI32V, MASK_VAMOANDEI32V, match_vd_neq_vm, INSN_DREF},
+-{"vamoorei32.v",    0, INSN_CLASS_V_OR_ZVAMO,  "Ve,0(s),Vt,VfVm", MATCH_VAMOOREI32V, MASK_VAMOOREI32V, match_vd_neq_vm, INSN_DREF},
+-{"vamominei32.v",   0, INSN_CLASS_V_OR_ZVAMO,  "Ve,0(s),Vt,VfVm", MATCH_VAMOMINEI32V, MASK_VAMOMINEI32V, match_vd_neq_vm, INSN_DREF},
+-{"vamomaxei32.v",   0, INSN_CLASS_V_OR_ZVAMO,  "Ve,0(s),Vt,VfVm", MATCH_VAMOMAXEI32V, MASK_VAMOMAXEI32V, match_vd_neq_vm, INSN_DREF},
+-{"vamominuei32.v",  0, INSN_CLASS_V_OR_ZVAMO,  "Ve,0(s),Vt,VfVm", MATCH_VAMOMINUEI32V, MASK_VAMOMINUEI32V, match_vd_neq_vm, INSN_DREF},
+-{"vamomaxuei32.v",  0, INSN_CLASS_V_OR_ZVAMO,  "Ve,0(s),Vt,VfVm", MATCH_VAMOMAXUEI32V, MASK_VAMOMAXUEI32V, match_vd_neq_vm, INSN_DREF},
+-
+-{"vamoaddei64.v",   0, INSN_CLASS_V_OR_ZVAMO,  "Ve,0(s),Vt,VfVm", MATCH_VAMOADDEI64V, MASK_VAMOADDEI64V, match_vd_neq_vm, INSN_DREF},
+-{"vamoswapei64.v",  0, INSN_CLASS_V_OR_ZVAMO,  "Ve,0(s),Vt,VfVm", MATCH_VAMOSWAPEI64V, MASK_VAMOSWAPEI64V, match_vd_neq_vm, INSN_DREF},
+-{"vamoxorei64.v",   0, INSN_CLASS_V_OR_ZVAMO,  "Ve,0(s),Vt,VfVm", MATCH_VAMOXOREI64V, MASK_VAMOXOREI64V, match_vd_neq_vm, INSN_DREF},
+-{"vamoandei64.v",   0, INSN_CLASS_V_OR_ZVAMO,  "Ve,0(s),Vt,VfVm", MATCH_VAMOANDEI64V, MASK_VAMOANDEI64V, match_vd_neq_vm, INSN_DREF},
+-{"vamoorei64.v",    0, INSN_CLASS_V_OR_ZVAMO,  "Ve,0(s),Vt,VfVm", MATCH_VAMOOREI64V, MASK_VAMOOREI64V, match_vd_neq_vm, INSN_DREF},
+-{"vamominei64.v",   0, INSN_CLASS_V_OR_ZVAMO,  "Ve,0(s),Vt,VfVm", MATCH_VAMOMINEI64V, MASK_VAMOMINEI64V, match_vd_neq_vm, INSN_DREF},
+-{"vamomaxei64.v",   0, INSN_CLASS_V_OR_ZVAMO,  "Ve,0(s),Vt,VfVm", MATCH_VAMOMAXEI64V, MASK_VAMOMAXEI64V, match_vd_neq_vm, INSN_DREF},
+-{"vamominuei64.v",  0, INSN_CLASS_V_OR_ZVAMO,  "Ve,0(s),Vt,VfVm", MATCH_VAMOMINUEI64V, MASK_VAMOMINUEI64V, match_vd_neq_vm, INSN_DREF},
+-{"vamomaxuei64.v",  0, INSN_CLASS_V_OR_ZVAMO,  "Ve,0(s),Vt,VfVm", MATCH_VAMOMAXUEI64V, MASK_VAMOMAXUEI64V, match_vd_neq_vm, INSN_DREF},
+-
+ {"vneg.v",     0, INSN_CLASS_V,  "Vd,VtVm",  MATCH_VRSUBVX, MASK_VRSUBVX | MASK_RS1, match_vd_neq_vm, INSN_ALIAS },
+ 
+ {"vadd.vv",    0, INSN_CLASS_V,  "Vd,Vt,VsVm", MATCH_VADDVV, MASK_VADDVV, match_vd_neq_vm, 0 },
+@@ -1710,26 +1350,6 @@ const struct riscv_opcode riscv_opcodes[] =
+ {"vrsub.vx",   0, INSN_CLASS_V,  "Vd,Vt,sVm", MATCH_VRSUBVX, MASK_VRSUBVX, match_vd_neq_vm, 0 },
+ {"vrsub.vi",   0, INSN_CLASS_V,  "Vd,Vt,ViVm", MATCH_VRSUBVI, MASK_VRSUBVI, match_vd_neq_vm, 0 },
+ 
+-{"vwcvt.x.x.v",  0, INSN_CLASS_V,  "Vd,VtVm", MATCH_VWCVTXXV, MASK_VWCVTXXV, match_widen_vd_neq_vs2_neq_vm, INSN_ALIAS },
+-{"vwcvtu.x.x.v", 0, INSN_CLASS_V,  "Vd,VtVm", MATCH_VWCVTUXXV, MASK_VWCVTUXXV, match_widen_vd_neq_vs2_neq_vm, INSN_ALIAS },
+-
+-{"vwaddu.vv",  0, INSN_CLASS_V,  "Vd,Vt,VsVm", MATCH_VWADDUVV, MASK_VWADDUVV, match_widen_vd_neq_vs1_neq_vs2_neq_vm, 0 },
+-{"vwaddu.vx",  0, INSN_CLASS_V,  "Vd,Vt,sVm", MATCH_VWADDUVX, MASK_VWADDUVX, match_widen_vd_neq_vs2_neq_vm, 0 },
+-{"vwsubu.vv",  0, INSN_CLASS_V,  "Vd,Vt,VsVm", MATCH_VWSUBUVV, MASK_VWSUBUVV, match_widen_vd_neq_vs1_neq_vs2_neq_vm, 0 },
+-{"vwsubu.vx",  0, INSN_CLASS_V,  "Vd,Vt,sVm", MATCH_VWSUBUVX, MASK_VWSUBUVX, match_widen_vd_neq_vs2_neq_vm, 0 },
+-{"vwadd.vv",   0, INSN_CLASS_V,  "Vd,Vt,VsVm", MATCH_VWADDVV, MASK_VWADDVV, match_widen_vd_neq_vs1_neq_vs2_neq_vm, 0 },
+-{"vwadd.vx",   0, INSN_CLASS_V,  "Vd,Vt,sVm", MATCH_VWADDVX, MASK_VWADDVX, match_widen_vd_neq_vs2_neq_vm, 0 },
+-{"vwsub.vv",   0, INSN_CLASS_V,  "Vd,Vt,VsVm", MATCH_VWSUBVV, MASK_VWSUBVV, match_widen_vd_neq_vs1_neq_vs2_neq_vm, 0 },
+-{"vwsub.vx",   0, INSN_CLASS_V,  "Vd,Vt,sVm", MATCH_VWSUBVX, MASK_VWSUBVX, match_widen_vd_neq_vs2_neq_vm, 0 },
+-{"vwaddu.wv",  0, INSN_CLASS_V,  "Vd,Vt,VsVm", MATCH_VWADDUWV, MASK_VWADDUWV, match_widen_vd_neq_vs1_neq_vm, 0 },
+-{"vwaddu.wx",  0, INSN_CLASS_V,  "Vd,Vt,sVm", MATCH_VWADDUWX, MASK_VWADDUWX, match_widen_vd_neq_vm, 0 },
+-{"vwsubu.wv",  0, INSN_CLASS_V,  "Vd,Vt,VsVm", MATCH_VWSUBUWV, MASK_VWSUBUWV, match_widen_vd_neq_vs1_neq_vm, 0 },
+-{"vwsubu.wx",  0, INSN_CLASS_V,  "Vd,Vt,sVm", MATCH_VWSUBUWX, MASK_VWSUBUWX, match_widen_vd_neq_vm, 0 },
+-{"vwadd.wv",   0, INSN_CLASS_V,  "Vd,Vt,VsVm", MATCH_VWADDWV, MASK_VWADDWV, match_widen_vd_neq_vs1_neq_vm, 0 },
+-{"vwadd.wx",   0, INSN_CLASS_V,  "Vd,Vt,sVm", MATCH_VWADDWX, MASK_VWADDWX, match_widen_vd_neq_vm, 0 },
+-{"vwsub.wv",   0, INSN_CLASS_V,  "Vd,Vt,VsVm", MATCH_VWSUBWV, MASK_VWSUBWV, match_widen_vd_neq_vs1_neq_vm, 0 },
+-{"vwsub.wx",   0, INSN_CLASS_V,  "Vd,Vt,sVm", MATCH_VWSUBWX, MASK_VWSUBWX, match_widen_vd_neq_vm, 0 },
+-
+ {"vzext.vf2",  0, INSN_CLASS_V,  "Vd,VtVm", MATCH_VZEXT_VF2, MASK_VZEXT_VF2, match_vd_neq_vm, 0 },
+ {"vsext.vf2",  0, INSN_CLASS_V,  "Vd,VtVm", MATCH_VSEXT_VF2, MASK_VSEXT_VF2, match_vd_neq_vm, 0 },
+ {"vzext.vf4",  0, INSN_CLASS_V,  "Vd,VtVm", MATCH_VZEXT_VF4, MASK_VZEXT_VF4, match_vd_neq_vm, 0 },
+@@ -1765,25 +1385,6 @@ const struct riscv_opcode riscv_opcodes[] =
+ {"vxor.vx",    0, INSN_CLASS_V,  "Vd,Vt,sVm", MATCH_VXORVX, MASK_VXORVX, match_vd_neq_vm, 0 },
+ {"vxor.vi",    0, INSN_CLASS_V,  "Vd,Vt,ViVm", MATCH_VXORVI, MASK_VXORVI, match_vd_neq_vm, 0 },
+ 
+-{"vsll.vv",    0, INSN_CLASS_V,  "Vd,Vt,VsVm", MATCH_VSLLVV, MASK_VSLLVV, match_vd_neq_vm, 0 },
+-{"vsll.vx",    0, INSN_CLASS_V,  "Vd,Vt,sVm", MATCH_VSLLVX, MASK_VSLLVX, match_vd_neq_vm, 0 },
+-{"vsll.vi",    0, INSN_CLASS_V,  "Vd,Vt,VjVm", MATCH_VSLLVI, MASK_VSLLVI, match_vd_neq_vm, 0 },
+-{"vsrl.vv",    0, INSN_CLASS_V,  "Vd,Vt,VsVm", MATCH_VSRLVV, MASK_VSRLVV, match_vd_neq_vm, 0 },
+-{"vsrl.vx",    0, INSN_CLASS_V,  "Vd,Vt,sVm", MATCH_VSRLVX, MASK_VSRLVX, match_vd_neq_vm, 0 },
+-{"vsrl.vi",    0, INSN_CLASS_V,  "Vd,Vt,VjVm", MATCH_VSRLVI, MASK_VSRLVI, match_vd_neq_vm, 0 },
+-{"vsra.vv",    0, INSN_CLASS_V,  "Vd,Vt,VsVm", MATCH_VSRAVV, MASK_VSRAVV, match_vd_neq_vm, 0 },
+-{"vsra.vx",    0, INSN_CLASS_V,  "Vd,Vt,sVm", MATCH_VSRAVX, MASK_VSRAVX, match_vd_neq_vm, 0 },
+-{"vsra.vi",    0, INSN_CLASS_V,  "Vd,Vt,VjVm", MATCH_VSRAVI, MASK_VSRAVI, match_vd_neq_vm, 0 },
+-
+-{"vncvt.x.x.w",0, INSN_CLASS_V,  "Vd,VtVm", MATCH_VNCVTXXW, MASK_VNCVTXXW, match_narrow_vd_neq_vs2_neq_vm, INSN_ALIAS },
+-
+-{"vnsrl.wv",   0, INSN_CLASS_V,  "Vd,Vt,VsVm", MATCH_VNSRLWV, MASK_VNSRLWV, match_narrow_vd_neq_vs2_neq_vm, 0 },
+-{"vnsrl.wx",   0, INSN_CLASS_V,  "Vd,Vt,sVm", MATCH_VNSRLWX, MASK_VNSRLWX, match_narrow_vd_neq_vs2_neq_vm, 0 },
+-{"vnsrl.wi",   0, INSN_CLASS_V,  "Vd,Vt,VjVm", MATCH_VNSRLWI, MASK_VNSRLWI, match_narrow_vd_neq_vs2_neq_vm, 0 },
+-{"vnsra.wv",   0, INSN_CLASS_V,  "Vd,Vt,VsVm", MATCH_VNSRAWV, MASK_VNSRAWV, match_narrow_vd_neq_vs2_neq_vm, 0 },
+-{"vnsra.wx",   0, INSN_CLASS_V,  "Vd,Vt,sVm", MATCH_VNSRAWX, MASK_VNSRAWX, match_narrow_vd_neq_vs2_neq_vm, 0 },
+-{"vnsra.wi",   0, INSN_CLASS_V,  "Vd,Vt,VjVm", MATCH_VNSRAWI, MASK_VNSRAWI, match_narrow_vd_neq_vs2_neq_vm, 0 },
+-
+ {"vmseq.vv",   0, INSN_CLASS_V,  "Vd,Vt,VsVm", MATCH_VMSEQVV, MASK_VMSEQVV, match_opcode, 0 },
+ {"vmseq.vx",   0, INSN_CLASS_V,  "Vd,Vt,sVm", MATCH_VMSEQVX, MASK_VMSEQVX, match_opcode, 0 },
+ {"vmseq.vi",   0, INSN_CLASS_V,  "Vd,Vt,ViVm", MATCH_VMSEQVI, MASK_VMSEQVI, match_opcode, 0 },
+@@ -1840,13 +1441,6 @@ const struct riscv_opcode riscv_opcodes[] =
+ {"vmulhsu.vv", 0, INSN_CLASS_V,  "Vd,Vt,VsVm", MATCH_VMULHSUVV, MASK_VMULHSUVV, match_vd_neq_vm, 0 },
+ {"vmulhsu.vx", 0, INSN_CLASS_V,  "Vd,Vt,sVm", MATCH_VMULHSUVX, MASK_VMULHSUVX, match_vd_neq_vm, 0 },
+ 
+-{"vwmul.vv",   0, INSN_CLASS_V,  "Vd,Vt,VsVm", MATCH_VWMULVV, MASK_VWMULVV, match_widen_vd_neq_vs1_neq_vs2_neq_vm, 0 },
+-{"vwmul.vx",   0, INSN_CLASS_V,  "Vd,Vt,sVm", MATCH_VWMULVX, MASK_VWMULVX, match_widen_vd_neq_vs2_neq_vm, 0 },
+-{"vwmulu.vv",  0, INSN_CLASS_V,  "Vd,Vt,VsVm", MATCH_VWMULUVV, MASK_VWMULUVV, match_widen_vd_neq_vs1_neq_vs2_neq_vm, 0 },
+-{"vwmulu.vx",  0, INSN_CLASS_V,  "Vd,Vt,sVm", MATCH_VWMULUVX, MASK_VWMULUVX, match_widen_vd_neq_vs2_neq_vm, 0 },
+-{"vwmulsu.vv", 0, INSN_CLASS_V,  "Vd,Vt,VsVm", MATCH_VWMULSUVV, MASK_VWMULSUVV, match_widen_vd_neq_vs1_neq_vs2_neq_vm, 0 },
+-{"vwmulsu.vx", 0, INSN_CLASS_V,  "Vd,Vt,sVm", MATCH_VWMULSUVX, MASK_VWMULSUVX, match_widen_vd_neq_vs2_neq_vm, 0 },
+-
+ {"vmacc.vv",   0, INSN_CLASS_V,  "Vd,Vs,VtVm", MATCH_VMACCVV, MASK_VMACCVV, match_vd_neq_vm, 0},
+ {"vmacc.vx",   0, INSN_CLASS_V,  "Vd,s,VtVm", MATCH_VMACCVX, MASK_VMACCVX, match_vd_neq_vm, 0},
+ {"vnmsac.vv",  0, INSN_CLASS_V,  "Vd,Vs,VtVm", MATCH_VNMSACVV, MASK_VNMSACVV, match_vd_neq_vm, 0},
+@@ -1856,14 +1450,6 @@ const struct riscv_opcode riscv_opcodes[] =
+ {"vnmsub.vv",  0, INSN_CLASS_V,  "Vd,Vs,VtVm", MATCH_VNMSUBVV, MASK_VNMSUBVV, match_vd_neq_vm, 0},
+ {"vnmsub.vx",  0, INSN_CLASS_V,  "Vd,s,VtVm", MATCH_VNMSUBVX, MASK_VNMSUBVX, match_vd_neq_vm, 0},
+ 
+-{"vwmaccu.vv",  0, INSN_CLASS_V,  "Vd,Vs,VtVm", MATCH_VWMACCUVV, MASK_VWMACCUVV, match_widen_vd_neq_vs1_neq_vs2_neq_vm, 0},
+-{"vwmaccu.vx",  0, INSN_CLASS_V,  "Vd,s,VtVm", MATCH_VWMACCUVX, MASK_VWMACCUVX, match_widen_vd_neq_vs2_neq_vm, 0},
+-{"vwmacc.vv",   0, INSN_CLASS_V,  "Vd,Vs,VtVm", MATCH_VWMACCVV, MASK_VWMACCVV, match_widen_vd_neq_vs1_neq_vs2_neq_vm, 0},
+-{"vwmacc.vx",   0, INSN_CLASS_V,  "Vd,s,VtVm", MATCH_VWMACCVX, MASK_VWMACCVX, match_widen_vd_neq_vs2_neq_vm, 0},
+-{"vwmaccsu.vv", 0, INSN_CLASS_V,  "Vd,Vs,VtVm", MATCH_VWMACCSUVV, MASK_VWMACCSUVV, match_widen_vd_neq_vs1_neq_vs2_neq_vm, 0},
+-{"vwmaccsu.vx", 0, INSN_CLASS_V,  "Vd,s,VtVm", MATCH_VWMACCSUVX, MASK_VWMACCSUVX, match_widen_vd_neq_vs2_neq_vm, 0},
+-{"vwmaccus.vx", 0, INSN_CLASS_V,  "Vd,s,VtVm", MATCH_VWMACCUSVX, MASK_VWMACCUSVX, match_widen_vd_neq_vs2_neq_vm, 0},
+-
+ {"vdivu.vv",   0, INSN_CLASS_V,  "Vd,Vt,VsVm", MATCH_VDIVUVV, MASK_VDIVUVV, match_vd_neq_vm, 0 },
+ {"vdivu.vx",   0, INSN_CLASS_V,  "Vd,Vt,sVm", MATCH_VDIVUVX, MASK_VDIVUVX, match_vd_neq_vm, 0 },
+ {"vdiv.vv",    0, INSN_CLASS_V,  "Vd,Vt,VsVm", MATCH_VDIVVV, MASK_VDIVVV, match_vd_neq_vm, 0 },
+@@ -1881,67 +1467,18 @@ const struct riscv_opcode riscv_opcodes[] =
+ {"vmv.v.x",    0, INSN_CLASS_V,  "Vd,s", MATCH_VMVVX, MASK_VMVVX, match_opcode, 0 },
+ {"vmv.v.i",    0, INSN_CLASS_V,  "Vd,Vi", MATCH_VMVVI, MASK_VMVVI, match_opcode, 0 },
+ 
+-{"vsaddu.vv",  0, INSN_CLASS_V,  "Vd,Vt,VsVm", MATCH_VSADDUVV, MASK_VSADDUVV, match_vd_neq_vm, 0 },
+-{"vsaddu.vx",  0, INSN_CLASS_V,  "Vd,Vt,sVm", MATCH_VSADDUVX, MASK_VSADDUVX, match_vd_neq_vm, 0 },
+-{"vsaddu.vi",  0, INSN_CLASS_V,  "Vd,Vt,ViVm", MATCH_VSADDUVI, MASK_VSADDUVI, match_vd_neq_vm, 0 },
+-{"vsadd.vv",   0, INSN_CLASS_V,  "Vd,Vt,VsVm", MATCH_VSADDVV, MASK_VSADDVV, match_vd_neq_vm, 0 },
+-{"vsadd.vx",   0, INSN_CLASS_V,  "Vd,Vt,sVm", MATCH_VSADDVX, MASK_VSADDVX, match_vd_neq_vm, 0 },
+-{"vsadd.vi",   0, INSN_CLASS_V,  "Vd,Vt,ViVm", MATCH_VSADDVI, MASK_VSADDVI, match_vd_neq_vm, 0 },
+-{"vssubu.vv",  0, INSN_CLASS_V,  "Vd,Vt,VsVm", MATCH_VSSUBUVV, MASK_VSSUBUVV, match_vd_neq_vm, 0 },
+-{"vssubu.vx",  0, INSN_CLASS_V,  "Vd,Vt,sVm", MATCH_VSSUBUVX, MASK_VSSUBUVX, match_vd_neq_vm, 0 },
+-{"vssub.vv",   0, INSN_CLASS_V,  "Vd,Vt,VsVm", MATCH_VSSUBVV, MASK_VSSUBVV, match_vd_neq_vm, 0 },
+-{"vssub.vx",   0, INSN_CLASS_V,  "Vd,Vt,sVm", MATCH_VSSUBVX, MASK_VSSUBVX, match_vd_neq_vm, 0 },
+-
+-{"vaaddu.vv",  0, INSN_CLASS_V,  "Vd,Vt,VsVm", MATCH_VAADDUVV, MASK_VAADDUVV, match_vd_neq_vm, 0 },
+-{"vaaddu.vx",  0, INSN_CLASS_V,  "Vd,Vt,sVm", MATCH_VAADDUVX, MASK_VAADDUVX, match_vd_neq_vm, 0 },
+-{"vaadd.vv",   0, INSN_CLASS_V,  "Vd,Vt,VsVm", MATCH_VAADDVV, MASK_VAADDVV, match_vd_neq_vm, 0 },
+-{"vaadd.vx",   0, INSN_CLASS_V,  "Vd,Vt,sVm", MATCH_VAADDVX, MASK_VAADDVX, match_vd_neq_vm, 0 },
+-{"vasubu.vv",  0, INSN_CLASS_V,  "Vd,Vt,VsVm", MATCH_VASUBUVV, MASK_VASUBUVV, match_vd_neq_vm, 0 },
+-{"vasubu.vx",  0, INSN_CLASS_V,  "Vd,Vt,sVm", MATCH_VASUBUVX, MASK_VASUBUVX, match_vd_neq_vm, 0 },
+-{"vasub.vv",   0, INSN_CLASS_V,  "Vd,Vt,VsVm", MATCH_VASUBVV, MASK_VASUBVV, match_vd_neq_vm, 0 },
+-{"vasub.vx",   0, INSN_CLASS_V,  "Vd,Vt,sVm", MATCH_VASUBVX, MASK_VASUBVX, match_vd_neq_vm, 0 },
+-
+-{"vsmul.vv",   0, INSN_CLASS_V,  "Vd,Vt,VsVm", MATCH_VSMULVV, MASK_VSMULVV, match_vd_neq_vm, 0 },
+-{"vsmul.vx",   0, INSN_CLASS_V,  "Vd,Vt,sVm", MATCH_VSMULVX, MASK_VSMULVX, match_vd_neq_vm, 0 },
+-
+-{"vssrl.vv",    0, INSN_CLASS_V,  "Vd,Vt,VsVm", MATCH_VSSRLVV, MASK_VSSRLVV, match_vd_neq_vm, 0 },
+-{"vssrl.vx",    0, INSN_CLASS_V,  "Vd,Vt,sVm", MATCH_VSSRLVX, MASK_VSSRLVX, match_vd_neq_vm, 0 },
+-{"vssrl.vi",    0, INSN_CLASS_V,  "Vd,Vt,VjVm", MATCH_VSSRLVI, MASK_VSSRLVI, match_vd_neq_vm, 0 },
+-{"vssra.vv",    0, INSN_CLASS_V,  "Vd,Vt,VsVm", MATCH_VSSRAVV, MASK_VSSRAVV, match_vd_neq_vm, 0 },
+-{"vssra.vx",    0, INSN_CLASS_V,  "Vd,Vt,sVm", MATCH_VSSRAVX, MASK_VSSRAVX, match_vd_neq_vm, 0 },
+-{"vssra.vi",    0, INSN_CLASS_V,  "Vd,Vt,VjVm", MATCH_VSSRAVI, MASK_VSSRAVI, match_vd_neq_vm, 0 },
+-
+-{"vnclipu.wv",   0, INSN_CLASS_V,  "Vd,Vt,VsVm", MATCH_VNCLIPUWV, MASK_VNCLIPUWV, match_narrow_vd_neq_vs2_neq_vm, 0 },
+-{"vnclipu.wx",   0, INSN_CLASS_V,  "Vd,Vt,sVm", MATCH_VNCLIPUWX, MASK_VNCLIPUWX, match_narrow_vd_neq_vs2_neq_vm, 0 },
+-{"vnclipu.wi",   0, INSN_CLASS_V,  "Vd,Vt,VjVm", MATCH_VNCLIPUWI, MASK_VNCLIPUWI, match_narrow_vd_neq_vs2_neq_vm, 0 },
+-{"vnclip.wv",   0, INSN_CLASS_V,  "Vd,Vt,VsVm", MATCH_VNCLIPWV, MASK_VNCLIPWV, match_narrow_vd_neq_vs2_neq_vm, 0 },
+-{"vnclip.wx",   0, INSN_CLASS_V,  "Vd,Vt,sVm", MATCH_VNCLIPWX, MASK_VNCLIPWX, match_narrow_vd_neq_vs2_neq_vm, 0 },
+-{"vnclip.wi",   0, INSN_CLASS_V,  "Vd,Vt,VjVm", MATCH_VNCLIPWI, MASK_VNCLIPWI, match_narrow_vd_neq_vs2_neq_vm, 0 },
+-
+ {"vfadd.vv",   0, INSN_CLASS_V_AND_F, "Vd,Vt,VsVm", MATCH_VFADDVV, MASK_VFADDVV, match_vd_neq_vm, 0},
+ {"vfadd.vf",   0, INSN_CLASS_V_AND_F, "Vd,Vt,SVm", MATCH_VFADDVF, MASK_VFADDVF, match_vd_neq_vm, 0},
+ {"vfsub.vv",   0, INSN_CLASS_V_AND_F, "Vd,Vt,VsVm", MATCH_VFSUBVV, MASK_VFSUBVV, match_vd_neq_vm, 0},
+ {"vfsub.vf",   0, INSN_CLASS_V_AND_F, "Vd,Vt,SVm", MATCH_VFSUBVF, MASK_VFSUBVF, match_vd_neq_vm, 0},
+ {"vfrsub.vf",  0, INSN_CLASS_V_AND_F, "Vd,Vt,SVm", MATCH_VFRSUBVF, MASK_VFRSUBVF, match_vd_neq_vm, 0},
+ 
+-{"vfwadd.vv",   0, INSN_CLASS_V_AND_F, "Vd,Vt,VsVm", MATCH_VFWADDVV, MASK_VFWADDVV, match_widen_vd_neq_vs1_neq_vs2_neq_vm, 0},
+-{"vfwadd.vf",   0, INSN_CLASS_V_AND_F, "Vd,Vt,SVm", MATCH_VFWADDVF, MASK_VFWADDVF, match_widen_vd_neq_vs2_neq_vm, 0},
+-{"vfwsub.vv",   0, INSN_CLASS_V_AND_F, "Vd,Vt,VsVm", MATCH_VFWSUBVV, MASK_VFWSUBVV, match_widen_vd_neq_vs1_neq_vs2_neq_vm, 0},
+-{"vfwsub.vf",   0, INSN_CLASS_V_AND_F, "Vd,Vt,SVm", MATCH_VFWSUBVF, MASK_VFWSUBVF, match_widen_vd_neq_vs2_neq_vm, 0},
+-{"vfwadd.wv",   0, INSN_CLASS_V_AND_F, "Vd,Vt,VsVm", MATCH_VFWADDWV, MASK_VFWADDWV, match_widen_vd_neq_vs1_neq_vm, 0},
+-{"vfwadd.wf",   0, INSN_CLASS_V_AND_F, "Vd,Vt,SVm", MATCH_VFWADDWF, MASK_VFWADDWF, match_widen_vd_neq_vm, 0},
+-{"vfwsub.wv",   0, INSN_CLASS_V_AND_F, "Vd,Vt,VsVm", MATCH_VFWSUBWV, MASK_VFWSUBWV, match_widen_vd_neq_vs1_neq_vm, 0},
+-{"vfwsub.wf",   0, INSN_CLASS_V_AND_F, "Vd,Vt,SVm", MATCH_VFWSUBWF, MASK_VFWSUBWF, match_widen_vd_neq_vm, 0},
+-
+ {"vfmul.vv",   0, INSN_CLASS_V_AND_F, "Vd,Vt,VsVm", MATCH_VFMULVV, MASK_VFMULVV, match_vd_neq_vm, 0},
+ {"vfmul.vf",   0, INSN_CLASS_V_AND_F, "Vd,Vt,SVm", MATCH_VFMULVF, MASK_VFMULVF, match_vd_neq_vm, 0},
+ {"vfdiv.vv",   0, INSN_CLASS_V_AND_F, "Vd,Vt,VsVm", MATCH_VFDIVVV, MASK_VFDIVVV, match_vd_neq_vm, 0},
+ {"vfdiv.vf",   0, INSN_CLASS_V_AND_F, "Vd,Vt,SVm", MATCH_VFDIVVF, MASK_VFDIVVF, match_vd_neq_vm, 0},
+ {"vfrdiv.vf",  0, INSN_CLASS_V_AND_F, "Vd,Vt,SVm", MATCH_VFRDIVVF, MASK_VFRDIVVF, match_vd_neq_vm, 0},
+ 
+-{"vfwmul.vv",  0, INSN_CLASS_V_AND_F, "Vd,Vt,VsVm", MATCH_VFWMULVV, MASK_VFWMULVV, match_widen_vd_neq_vs1_neq_vs2_neq_vm, 0},
+-{"vfwmul.vf",  0, INSN_CLASS_V_AND_F, "Vd,Vt,SVm", MATCH_VFWMULVF, MASK_VFWMULVF, match_widen_vd_neq_vs2_neq_vm, 0},
+-
+ {"vfmadd.vv",  0, INSN_CLASS_V_AND_F, "Vd,Vs,VtVm", MATCH_VFMADDVV, MASK_VFMADDVV, match_vd_neq_vm, 0},
+ {"vfmadd.vf",  0, INSN_CLASS_V_AND_F, "Vd,S,VtVm", MATCH_VFMADDVF, MASK_VFMADDVF, match_vd_neq_vm, 0},
+ {"vfnmadd.vv", 0, INSN_CLASS_V_AND_F, "Vd,Vs,VtVm", MATCH_VFNMADDVV, MASK_VFNMADDVV, match_vd_neq_vm, 0},
+@@ -1959,22 +1496,6 @@ const struct riscv_opcode riscv_opcodes[] =
+ {"vfnmsac.vv", 0, INSN_CLASS_V_AND_F, "Vd,Vs,VtVm", MATCH_VFNMSACVV, MASK_VFNMSACVV, match_vd_neq_vm, 0},
+ {"vfnmsac.vf", 0, INSN_CLASS_V_AND_F, "Vd,S,VtVm", MATCH_VFNMSACVF, MASK_VFNMSACVF, match_vd_neq_vm, 0},
+ 
+-{"vfwmacc.vv",  0, INSN_CLASS_V_AND_F, "Vd,Vs,VtVm", MATCH_VFWMACCVV, MASK_VFWMACCVV, match_widen_vd_neq_vs1_neq_vs2_neq_vm, 0},
+-{"vfwmacc.vf",  0, INSN_CLASS_V_AND_F, "Vd,S,VtVm", MATCH_VFWMACCVF, MASK_VFWMACCVF, match_widen_vd_neq_vs2_neq_vm, 0},
+-{"vfwnmacc.vv", 0, INSN_CLASS_V_AND_F, "Vd,Vs,VtVm", MATCH_VFWNMACCVV, MASK_VFWNMACCVV, match_widen_vd_neq_vs1_neq_vs2_neq_vm, 0},
+-{"vfwnmacc.vf", 0, INSN_CLASS_V_AND_F, "Vd,S,VtVm", MATCH_VFWNMACCVF, MASK_VFWNMACCVF, match_widen_vd_neq_vs2_neq_vm, 0},
+-{"vfwmsac.vv",  0, INSN_CLASS_V_AND_F, "Vd,Vs,VtVm", MATCH_VFWMSACVV, MASK_VFWMSACVV, match_widen_vd_neq_vs1_neq_vs2_neq_vm, 0},
+-{"vfwmsac.vf",  0, INSN_CLASS_V_AND_F, "Vd,S,VtVm", MATCH_VFWMSACVF, MASK_VFWMSACVF, match_widen_vd_neq_vs2_neq_vm, 0},
+-{"vfwnmsac.vv", 0, INSN_CLASS_V_AND_F, "Vd,Vs,VtVm", MATCH_VFWNMSACVV, MASK_VFWNMSACVV, match_widen_vd_neq_vs1_neq_vs2_neq_vm, 0},
+-{"vfwnmsac.vf", 0, INSN_CLASS_V_AND_F, "Vd,S,VtVm", MATCH_VFWNMSACVF, MASK_VFWNMSACVF, match_widen_vd_neq_vs2_neq_vm, 0},
+-
+-{"vfsqrt.v",   0, INSN_CLASS_V_AND_F, "Vd,VtVm", MATCH_VFSQRTV, MASK_VFSQRTV, match_vd_neq_vm, 0},
+-{"vfrsqrt7.v", 0, INSN_CLASS_V_AND_F, "Vd,VtVm", MATCH_VFRSQRT7V, MASK_VFRSQRT7V, match_vd_neq_vm, 0},
+-{"vfrsqrte7.v",0, INSN_CLASS_V_AND_F, "Vd,VtVm", MATCH_VFRSQRT7V, MASK_VFRSQRT7V, match_vd_neq_vm, 0},
+-{"vfrec7.v",   0, INSN_CLASS_V_AND_F, "Vd,VtVm", MATCH_VFREC7V, MASK_VFREC7V, match_vd_neq_vm, 0},
+-{"vfrece7.v",  0, INSN_CLASS_V_AND_F, "Vd,VtVm", MATCH_VFREC7V, MASK_VFREC7V, match_vd_neq_vm, 0},
+-{"vfclass.v",  0, INSN_CLASS_V_AND_F, "Vd,VtVm", MATCH_VFCLASSV, MASK_VFCLASSV, match_vd_neq_vm, 0},
+-
+ {"vfmin.vv",   0, INSN_CLASS_V_AND_F, "Vd,Vt,VsVm", MATCH_VFMINVV, MASK_VFMINVV, match_vd_neq_vm, 0},
+ {"vfmin.vf",   0, INSN_CLASS_V_AND_F, "Vd,Vt,SVm", MATCH_VFMINVF, MASK_VFMINVF, match_vd_neq_vm, 0},
+ {"vfmax.vv",   0, INSN_CLASS_V_AND_F, "Vd,Vt,VsVm", MATCH_VFMAXVV, MASK_VFMAXVV, match_vd_neq_vm, 0},
+@@ -2008,50 +1529,6 @@ const struct riscv_opcode riscv_opcodes[] =
+ {"vfmerge.vfm",0, INSN_CLASS_V_AND_F, "Vd,Vt,S,V0", MATCH_VFMERGEVFM, MASK_VFMERGEVFM, match_opcode, 0},
+ {"vfmv.v.f",   0, INSN_CLASS_V_AND_F, "Vd,S", MATCH_VFMVVF, MASK_VFMVVF, match_opcode, 0 },
+ 
+-{"vfcvt.xu.f.v",     0, INSN_CLASS_V_AND_F, "Vd,VtVm", MATCH_VFCVTXUFV, MASK_VFCVTXUFV, match_vd_neq_vm, 0},
+-{"vfcvt.x.f.v",      0, INSN_CLASS_V_AND_F, "Vd,VtVm", MATCH_VFCVTXFV, MASK_VFCVTXFV, match_vd_neq_vm, 0},
+-{"vfcvt.rtz.xu.f.v", 0, INSN_CLASS_V_AND_F, "Vd,VtVm", MATCH_VFCVTRTZXUFV, MASK_VFCVTRTZXUFV, match_vd_neq_vm, 0},
+-{"vfcvt.rtz.x.f.v",  0, INSN_CLASS_V_AND_F, "Vd,VtVm", MATCH_VFCVTRTZXFV, MASK_VFCVTRTZXFV, match_vd_neq_vm, 0},
+-{"vfcvt.f.xu.v",     0, INSN_CLASS_V_AND_F, "Vd,VtVm", MATCH_VFCVTFXUV, MASK_VFCVTFXUV, match_vd_neq_vm, 0},
+-{"vfcvt.f.x.v",      0, INSN_CLASS_V_AND_F, "Vd,VtVm", MATCH_VFCVTFXV, MASK_VFCVTFXV, match_vd_neq_vm, 0},
+-
+-{"vfwcvt.xu.f.v",     0, INSN_CLASS_V_AND_F, "Vd,VtVm", MATCH_VFWCVTXUFV, MASK_VFWCVTXUFV, match_widen_vd_neq_vs2_neq_vm, 0},
+-{"vfwcvt.x.f.v",      0, INSN_CLASS_V_AND_F, "Vd,VtVm", MATCH_VFWCVTXFV, MASK_VFWCVTXFV, match_widen_vd_neq_vs2_neq_vm, 0},
+-{"vfwcvt.rtz.xu.f.v", 0, INSN_CLASS_V_AND_F, "Vd,VtVm", MATCH_VFWCVTRTZXUFV, MASK_VFWCVTRTZXUFV, match_widen_vd_neq_vs2_neq_vm, 0},
+-{"vfwcvt.rtz.x.f.v",  0, INSN_CLASS_V_AND_F, "Vd,VtVm", MATCH_VFWCVTRTZXFV, MASK_VFWCVTRTZXFV, match_widen_vd_neq_vs2_neq_vm, 0},
+-{"vfwcvt.f.xu.v",     0, INSN_CLASS_V_AND_F, "Vd,VtVm", MATCH_VFWCVTFXUV, MASK_VFWCVTFXUV, match_widen_vd_neq_vs2_neq_vm, 0},
+-{"vfwcvt.f.x.v",      0, INSN_CLASS_V_AND_F, "Vd,VtVm", MATCH_VFWCVTFXV, MASK_VFWCVTFXV, match_widen_vd_neq_vs2_neq_vm, 0},
+-{"vfwcvt.f.f.v",      0, INSN_CLASS_V_AND_F, "Vd,VtVm", MATCH_VFWCVTFFV, MASK_VFWCVTFFV, match_widen_vd_neq_vs2_neq_vm, 0},
+-
+-{"vfncvt.xu.f.w",     0, INSN_CLASS_V_AND_F, "Vd,VtVm", MATCH_VFNCVTXUFW, MASK_VFNCVTXUFW, match_narrow_vd_neq_vs2_neq_vm, 0},
+-{"vfncvt.x.f.w",      0, INSN_CLASS_V_AND_F, "Vd,VtVm", MATCH_VFNCVTXFW, MASK_VFNCVTXFW, match_narrow_vd_neq_vs2_neq_vm, 0},
+-{"vfncvt.rtz.xu.f.w", 0, INSN_CLASS_V_AND_F, "Vd,VtVm", MATCH_VFNCVTRTZXUFW, MASK_VFNCVTRTZXUFW, match_narrow_vd_neq_vs2_neq_vm, 0},
+-{"vfncvt.rtz.x.f.w",  0, INSN_CLASS_V_AND_F, "Vd,VtVm", MATCH_VFNCVTRTZXFW, MASK_VFNCVTRTZXFW, match_narrow_vd_neq_vs2_neq_vm, 0},
+-{"vfncvt.f.xu.w",     0, INSN_CLASS_V_AND_F, "Vd,VtVm", MATCH_VFNCVTFXUW, MASK_VFNCVTFXUW, match_narrow_vd_neq_vs2_neq_vm, 0},
+-{"vfncvt.f.x.w",      0, INSN_CLASS_V_AND_F, "Vd,VtVm", MATCH_VFNCVTFXW, MASK_VFNCVTFXW, match_narrow_vd_neq_vs2_neq_vm, 0},
+-{"vfncvt.f.f.w",      0, INSN_CLASS_V_AND_F, "Vd,VtVm", MATCH_VFNCVTFFW, MASK_VFNCVTFFW, match_narrow_vd_neq_vs2_neq_vm, 0},
+-{"vfncvt.rod.f.f.w",  0, INSN_CLASS_V_AND_F, "Vd,VtVm", MATCH_VFNCVTRODFFW, MASK_VFNCVTRODFFW, match_narrow_vd_neq_vs2_neq_vm, 0},
+-
+-{"vredsum.vs", 0, INSN_CLASS_V, "Vd,Vt,VsVm", MATCH_VREDSUMVS, MASK_VREDSUMVS, match_opcode, 0},
+-{"vredmaxu.vs",0, INSN_CLASS_V, "Vd,Vt,VsVm", MATCH_VREDMAXUVS, MASK_VREDMAXUVS, match_opcode, 0},
+-{"vredmax.vs", 0, INSN_CLASS_V, "Vd,Vt,VsVm", MATCH_VREDMAXVS, MASK_VREDMAXVS, match_opcode, 0},
+-{"vredminu.vs",0, INSN_CLASS_V, "Vd,Vt,VsVm", MATCH_VREDMINUVS, MASK_VREDMINUVS, match_opcode, 0},
+-{"vredmin.vs", 0, INSN_CLASS_V, "Vd,Vt,VsVm", MATCH_VREDMINVS, MASK_VREDMINVS, match_opcode, 0},
+-{"vredand.vs", 0, INSN_CLASS_V, "Vd,Vt,VsVm", MATCH_VREDANDVS, MASK_VREDANDVS, match_opcode, 0},
+-{"vredor.vs",  0, INSN_CLASS_V, "Vd,Vt,VsVm", MATCH_VREDORVS, MASK_VREDORVS, match_opcode, 0},
+-{"vredxor.vs", 0, INSN_CLASS_V, "Vd,Vt,VsVm", MATCH_VREDXORVS, MASK_VREDXORVS, match_opcode, 0},
+-
+-{"vwredsumu.vs",0, INSN_CLASS_V, "Vd,Vt,VsVm", MATCH_VWREDSUMUVS, MASK_VWREDSUMUVS, match_opcode, 0},
+-{"vwredsum.vs",0, INSN_CLASS_V, "Vd,Vt,VsVm", MATCH_VWREDSUMVS, MASK_VWREDSUMVS, match_opcode, 0},
+-
+-{"vfredosum.vs",0, INSN_CLASS_V_AND_F, "Vd,Vt,VsVm", MATCH_VFREDOSUMVS, MASK_VFREDOSUMVS, match_opcode, 0},
+-{"vfredsum.vs", 0, INSN_CLASS_V_AND_F, "Vd,Vt,VsVm", MATCH_VFREDSUMVS, MASK_VFREDSUMVS, match_opcode, 0},
+-{"vfredmax.vs", 0, INSN_CLASS_V_AND_F, "Vd,Vt,VsVm", MATCH_VFREDMAXVS, MASK_VFREDMAXVS, match_opcode, 0},
+-{"vfredmin.vs", 0, INSN_CLASS_V_AND_F, "Vd,Vt,VsVm", MATCH_VFREDMINVS, MASK_VFREDMINVS, match_opcode, 0},
+-
+-{"vfwredosum.vs",0, INSN_CLASS_V_AND_F, "Vd,Vt,VsVm", MATCH_VFWREDOSUMVS, MASK_VFWREDOSUMVS, match_opcode, 0},
+-{"vfwredsum.vs", 0, INSN_CLASS_V_AND_F, "Vd,Vt,VsVm", MATCH_VFWREDSUMVS, MASK_VFWREDSUMVS, match_opcode, 0},
+-
+ {"vmmv.m",     0, INSN_CLASS_V, "Vd,Vu", MATCH_VMANDMM, MASK_VMANDMM, match_vs1_eq_vs2, INSN_ALIAS},
+ {"vmcpy.m",    0, INSN_CLASS_V, "Vd,Vu", MATCH_VMANDMM, MASK_VMANDMM, match_vs1_eq_vs2, INSN_ALIAS},
+ {"vmclr.m",    0, INSN_CLASS_V, "Vv", MATCH_VMXORMM, MASK_VMXORMM, match_vd_eq_vs1_eq_vs2, INSN_ALIAS},
+@@ -2069,11 +1546,6 @@ const struct riscv_opcode riscv_opcodes[] =
+ 
+ {"vpopc.m",    0, INSN_CLASS_V, "d,VtVm", MATCH_VPOPCM, MASK_VPOPCM, match_opcode, 0},
+ {"vfirst.m",   0, INSN_CLASS_V, "d,VtVm", MATCH_VFIRSTM, MASK_VFIRSTM, match_opcode, 0},
+-{"vmsbf.m",    0, INSN_CLASS_V, "Vd,VtVm", MATCH_VMSBFM, MASK_VMSBFM, match_vd_neq_vs2_neq_vm, 0},
+-{"vmsif.m",    0, INSN_CLASS_V, "Vd,VtVm", MATCH_VMSIFM, MASK_VMSIFM, match_vd_neq_vs2_neq_vm, 0},
+-{"vmsof.m",    0, INSN_CLASS_V, "Vd,VtVm", MATCH_VMSOFM, MASK_VMSOFM, match_vd_neq_vs2_neq_vm, 0},
+-{"viota.m",    0, INSN_CLASS_V, "Vd,VtVm", MATCH_VIOTAM, MASK_VIOTAM, match_vd_neq_vs2_neq_vm, 0},
+-{"vid.v",      0, INSN_CLASS_V, "VdVm", MATCH_VIDV, MASK_VIDV, match_vd_neq_vm, 0},
+ 
+ {"vmv.x.s",    0, INSN_CLASS_V, "d,Vt", MATCH_VMVXS, MASK_VMVXS, match_opcode, 0},
+ {"vmv.s.x",    0, INSN_CLASS_V, "Vd,s", MATCH_VMVSX, MASK_VMVSX, match_opcode, 0},
+@@ -2094,15 +1566,10 @@ const struct riscv_opcode riscv_opcodes[] =
+ {"vrgather.vv",    0, INSN_CLASS_V, "Vd,Vt,VsVm", MATCH_VRGATHERVV, MASK_VRGATHERVV, match_vd_neq_vs1_neq_vs2_neq_vm, 0},
+ {"vrgather.vx",    0, INSN_CLASS_V, "Vd,Vt,sVm", MATCH_VRGATHERVX, MASK_VRGATHERVX, match_vd_neq_vs2_neq_vm, 0},
+ {"vrgather.vi",    0, INSN_CLASS_V, "Vd,Vt,VjVm", MATCH_VRGATHERVI, MASK_VRGATHERVI, match_vd_neq_vs2_neq_vm, 0},
+-{"vrgatherei16.vv",0, INSN_CLASS_V, "Vd,Vt,VsVm", MATCH_VRGATHEREI16VV, MASK_VRGATHEREI16VV, match_vd_neq_vs1_neq_vs2_neq_vm, 0},
+ 
+ {"vcompress.vm",0, INSN_CLASS_V, "Vd,Vt,Vs", MATCH_VCOMPRESSVM, MASK_VCOMPRESSVM, match_vd_neq_vs1_neq_vs2, 0},
+-
+-{"vmv1r.v",    0, INSN_CLASS_V, "Vd,Vt", MATCH_VMV1RV, MASK_VMV1RV, match_vmv_nf_rv, 0},
+-{"vmv2r.v",    0, INSN_CLASS_V, "Vd,Vt", MATCH_VMV2RV, MASK_VMV2RV, match_vmv_nf_rv, 0},
+-{"vmv4r.v",    0, INSN_CLASS_V, "Vd,Vt", MATCH_VMV4RV, MASK_VMV4RV, match_vmv_nf_rv, 0},
+-{"vmv8r.v",    0, INSN_CLASS_V, "Vd,Vt", MATCH_VMV8RV, MASK_VMV8RV, match_vmv_nf_rv, 0},
+ /* END RVV */
++
+ /* Terminate the list.  */
+ {0, 0, INSN_CLASS_NONE, 0, 0, 0, 0, 0}
+ };
+-- 
+2.33.0
+

+ 281 - 0
recipes-devtools/binutils/binutils/0006-Add-pseudo-instructions-for-B-extension.patch

@@ -0,0 +1,281 @@
+From 32134df31c001130ac0ad9b3975827aaa9c8f42c Mon Sep 17 00:00:00 2001
+From: LevyHsu <admin@levyhsu.com>
+Date: Tue, 8 Jun 2021 15:04:36 +0800
+Subject: [PATCH 06/28] Add pseudo-instructions for B extension
+
+rev[2/4/8/16].[p/n/b/w]
+[un]zip[2/4/8/16].[p/n/b/w]
+orc[2/4/8/16].[p/n/b/w]
+---
+ opcodes/riscv-opc.c | 246 +++++++++++++++++++++++++++++++++++++++++++-
+ 1 file changed, 242 insertions(+), 4 deletions(-)
+
+diff --git a/opcodes/riscv-opc.c b/opcodes/riscv-opc.c
+index df6b1659f8..dc7c1fb428 100644
+--- a/opcodes/riscv-opc.c
++++ b/opcodes/riscv-opc.c
+@@ -25,9 +25,128 @@
+ #include <stdio.h>
+ 
+ #define MASK_SHAMT (OP_MASK_SHAMT << OP_SH_SHAMT)
+-#define MATCH_SHAMT_REV8_32 (0b11000 << OP_SH_SHAMT)
+-#define MATCH_SHAMT_REV8_64 (0b111000 << OP_SH_SHAMT)
+-#define MATCH_SHAMT_ORC_B (0b00111 << OP_SH_SHAMT)
++#define MATCH_SHAMT_REV_32     (0b11111 << OP_SH_SHAMT)
++#define MATCH_SHAMT_REV_64     (0b111111 << OP_SH_SHAMT)
++#define MATCH_SHAMT_REV_P_32   (0b00001 << OP_SH_SHAMT)
++#define MATCH_SHAMT_REV_P_64   (0b000001 << OP_SH_SHAMT)
++#define MATCH_SHAMT_REV_N_32   (0b00011 << OP_SH_SHAMT)
++#define MATCH_SHAMT_REV_N_64   (0b000011 << OP_SH_SHAMT)
++#define MATCH_SHAMT_REV_B_32   (0b00111 << OP_SH_SHAMT)
++#define MATCH_SHAMT_REV_B_64   (0b000111 << OP_SH_SHAMT)
++#define MATCH_SHAMT_REV_H_32   (0b01111 << OP_SH_SHAMT)
++#define MATCH_SHAMT_REV_H_64   (0b001111 << OP_SH_SHAMT)
++#define MATCH_SHAMT_REV_W_64   (0b011111 << OP_SH_SHAMT)
++#define MATCH_SHAMT_REV2_32    (0b11110 << OP_SH_SHAMT)
++#define MATCH_SHAMT_REV2_64    (0b111110 << OP_SH_SHAMT)
++#define MATCH_SHAMT_REV2_N_32  (0b00010 << OP_SH_SHAMT)
++#define MATCH_SHAMT_REV2_N_64  (0b000010 << OP_SH_SHAMT)
++#define MATCH_SHAMT_REV2_B_32  (0b00110 << OP_SH_SHAMT)
++#define MATCH_SHAMT_REV2_B_64  (0b000110 << OP_SH_SHAMT)
++#define MATCH_SHAMT_REV2_H_32  (0b01110 << OP_SH_SHAMT)
++#define MATCH_SHAMT_REV2_H_64  (0b001110 << OP_SH_SHAMT)
++#define MATCH_SHAMT_REV2_W_64  (0b011110 << OP_SH_SHAMT)
++#define MATCH_SHAMT_REV4_32    (0b11100 << OP_SH_SHAMT)
++#define MATCH_SHAMT_REV4_64    (0b111100 << OP_SH_SHAMT)
++#define MATCH_SHAMT_REV4_B_32  (0b00100 << OP_SH_SHAMT)
++#define MATCH_SHAMT_REV4_B_64  (0b000100 << OP_SH_SHAMT)
++#define MATCH_SHAMT_REV4_H_32  (0b01100 << OP_SH_SHAMT)
++#define MATCH_SHAMT_REV4_H_64  (0b001100 << OP_SH_SHAMT)
++#define MATCH_SHAMT_REV4_W_64  (0b011100 << OP_SH_SHAMT)
++#define MATCH_SHAMT_REV8_32    (0b11000 << OP_SH_SHAMT)
++#define MATCH_SHAMT_REV8_64    (0b111000 << OP_SH_SHAMT)
++#define MATCH_SHAMT_REV8_H_32  (0b01000 << OP_SH_SHAMT)
++#define MATCH_SHAMT_REV8_H_64  (0b001000 << OP_SH_SHAMT)
++#define MATCH_SHAMT_REV8_W_64  (0b011000 << OP_SH_SHAMT)
++#define MATCH_SHAMT_REV16_32   (0b10000 << OP_SH_SHAMT)
++#define MATCH_SHAMT_REV16_64   (0b110000 << OP_SH_SHAMT)
++#define MATCH_SHAMT_REV16_W_64 (0b010000 << OP_SH_SHAMT)
++#define MATCH_SHAMT_REV32_64   (0b100000 << OP_SH_SHAMT)
++#define MATCH_SHAMT_ZIP_32     (0b11110 << OP_SH_SHAMT)
++#define MATCH_SHAMT_ZIP_64     (0b111110 << OP_SH_SHAMT)
++#define MATCH_SHAMT_ZIP_N_32   (0b00010 << OP_SH_SHAMT)
++#define MATCH_SHAMT_ZIP_N_64   (0b000010 << OP_SH_SHAMT)
++#define MATCH_SHAMT_ZIP_B_32   (0b00110 << OP_SH_SHAMT)
++#define MATCH_SHAMT_ZIP_B_64   (0b000110 << OP_SH_SHAMT)
++#define MATCH_SHAMT_ZIP_H_32   (0b01110 << OP_SH_SHAMT)
++#define MATCH_SHAMT_ZIP_H_64   (0b001110 << OP_SH_SHAMT)
++#define MATCH_SHAMT_ZIP_W_64   (0b011110 << OP_SH_SHAMT)
++#define MATCH_SHAMT_ZIP2_32    (0b11100 << OP_SH_SHAMT)
++#define MATCH_SHAMT_ZIP2_64    (0b111100 << OP_SH_SHAMT)
++#define MATCH_SHAMT_ZIP2_B_32  (0b00100 << OP_SH_SHAMT)
++#define MATCH_SHAMT_ZIP2_B_64  (0b000100 << OP_SH_SHAMT)
++#define MATCH_SHAMT_ZIP2_H_32  (0b01100 << OP_SH_SHAMT)
++#define MATCH_SHAMT_ZIP2_H_64  (0b001100 << OP_SH_SHAMT)
++#define MATCH_SHAMT_ZIP2_W_64  (0b011100 << OP_SH_SHAMT)
++#define MATCH_SHAMT_ZIP4_32    (0b11000 << OP_SH_SHAMT)
++#define MATCH_SHAMT_ZIP4_64    (0b111000 << OP_SH_SHAMT)
++#define MATCH_SHAMT_ZIP4_H_32  (0b01000 << OP_SH_SHAMT)
++#define MATCH_SHAMT_ZIP4_H_64  (0b001000 << OP_SH_SHAMT)
++#define MATCH_SHAMT_ZIP4_W_64  (0b011000 << OP_SH_SHAMT)
++#define MATCH_SHAMT_ZIP8_32    (0b10000 << OP_SH_SHAMT)
++#define MATCH_SHAMT_ZIP8_64    (0b110000 << OP_SH_SHAMT)
++#define MATCH_SHAMT_ZIP8_W_64  (0b010000 << OP_SH_SHAMT)
++#define MATCH_SHAMT_ZIP16_64   (0b100000 << OP_SH_SHAMT)
++#define MATCH_SHAMT_UNZIP_32     (0b11111 << OP_SH_SHAMT)
++#define MATCH_SHAMT_UNZIP_64     (0b111111 << OP_SH_SHAMT)
++#define MATCH_SHAMT_UNZIP_N_32   (0b00011 << OP_SH_SHAMT)
++#define MATCH_SHAMT_UNZIP_N_64   (0b000011 << OP_SH_SHAMT)
++#define MATCH_SHAMT_UNZIP_B_32   (0b00111 << OP_SH_SHAMT)
++#define MATCH_SHAMT_UNZIP_B_64   (0b000111 << OP_SH_SHAMT)
++#define MATCH_SHAMT_UNZIP_H_32   (0b01111 << OP_SH_SHAMT)
++#define MATCH_SHAMT_UNZIP_H_64   (0b001111 << OP_SH_SHAMT)
++#define MATCH_SHAMT_UNZIP_W_64   (0b011111 << OP_SH_SHAMT)
++#define MATCH_SHAMT_UNZIP2_32    (0b11101 << OP_SH_SHAMT)
++#define MATCH_SHAMT_UNZIP2_64    (0b111101 << OP_SH_SHAMT)
++#define MATCH_SHAMT_UNZIP2_B_32  (0b00101 << OP_SH_SHAMT)
++#define MATCH_SHAMT_UNZIP2_B_64  (0b000101 << OP_SH_SHAMT)
++#define MATCH_SHAMT_UNZIP2_H_32  (0b01101 << OP_SH_SHAMT)
++#define MATCH_SHAMT_UNZIP2_H_64  (0b001101 << OP_SH_SHAMT)
++#define MATCH_SHAMT_UNZIP2_W_64  (0b011101 << OP_SH_SHAMT)
++#define MATCH_SHAMT_UNZIP4_32    (0b11001 << OP_SH_SHAMT)
++#define MATCH_SHAMT_UNZIP4_64    (0b111001 << OP_SH_SHAMT)
++#define MATCH_SHAMT_UNZIP4_H_32  (0b01001 << OP_SH_SHAMT)
++#define MATCH_SHAMT_UNZIP4_H_64  (0b001001 << OP_SH_SHAMT)
++#define MATCH_SHAMT_UNZIP4_W_64  (0b011001 << OP_SH_SHAMT)
++#define MATCH_SHAMT_UNZIP8_32    (0b10001 << OP_SH_SHAMT)
++#define MATCH_SHAMT_UNZIP8_64    (0b110001 << OP_SH_SHAMT)
++#define MATCH_SHAMT_UNZIP8_W_64  (0b010001 << OP_SH_SHAMT)
++#define MATCH_SHAMT_UNZIP16_64   (0b100001 << OP_SH_SHAMT)
++#define MATCH_SHAMT_ORC_32     (0b11111 << OP_SH_SHAMT)
++#define MATCH_SHAMT_ORC_64     (0b111111 << OP_SH_SHAMT)
++#define MATCH_SHAMT_ORC_P_32   (0b00001 << OP_SH_SHAMT)
++#define MATCH_SHAMT_ORC_P_64   (0b000001 << OP_SH_SHAMT)
++#define MATCH_SHAMT_ORC_N_32   (0b00011 << OP_SH_SHAMT)
++#define MATCH_SHAMT_ORC_N_64   (0b000011 << OP_SH_SHAMT)
++#define MATCH_SHAMT_ORC_B_32   (0b00111 << OP_SH_SHAMT)
++#define MATCH_SHAMT_ORC_B_64   (0b000111 << OP_SH_SHAMT)
++#define MATCH_SHAMT_ORC_H_32   (0b01111 << OP_SH_SHAMT)
++#define MATCH_SHAMT_ORC_H_64   (0b001111 << OP_SH_SHAMT)
++#define MATCH_SHAMT_ORC_W_64   (0b011111 << OP_SH_SHAMT)
++#define MATCH_SHAMT_ORC2_32    (0b11110 << OP_SH_SHAMT)
++#define MATCH_SHAMT_ORC2_64    (0b111110 << OP_SH_SHAMT)
++#define MATCH_SHAMT_ORC2_N_32  (0b00010 << OP_SH_SHAMT)
++#define MATCH_SHAMT_ORC2_N_64  (0b000010 << OP_SH_SHAMT)
++#define MATCH_SHAMT_ORC2_B_32  (0b00110 << OP_SH_SHAMT)
++#define MATCH_SHAMT_ORC2_B_64  (0b000110 << OP_SH_SHAMT)
++#define MATCH_SHAMT_ORC2_H_32  (0b01110 << OP_SH_SHAMT)
++#define MATCH_SHAMT_ORC2_H_64  (0b001110 << OP_SH_SHAMT)
++#define MATCH_SHAMT_ORC2_W_64  (0b011110 << OP_SH_SHAMT)
++#define MATCH_SHAMT_ORC4_32    (0b11100 << OP_SH_SHAMT)
++#define MATCH_SHAMT_ORC4_64    (0b111100 << OP_SH_SHAMT)
++#define MATCH_SHAMT_ORC4_B_32  (0b00100 << OP_SH_SHAMT)
++#define MATCH_SHAMT_ORC4_B_64  (0b000100 << OP_SH_SHAMT)
++#define MATCH_SHAMT_ORC4_H_32  (0b01100 << OP_SH_SHAMT)
++#define MATCH_SHAMT_ORC4_H_64  (0b001100 << OP_SH_SHAMT)
++#define MATCH_SHAMT_ORC4_W_64  (0b011100 << OP_SH_SHAMT)
++#define MATCH_SHAMT_ORC8_32    (0b11000 << OP_SH_SHAMT)
++#define MATCH_SHAMT_ORC8_64    (0b111000 << OP_SH_SHAMT)
++#define MATCH_SHAMT_ORC8_H_32  (0b01000 << OP_SH_SHAMT)
++#define MATCH_SHAMT_ORC8_H_64  (0b001000 << OP_SH_SHAMT)
++#define MATCH_SHAMT_ORC8_W_64  (0b011000 << OP_SH_SHAMT)
++#define MATCH_SHAMT_ORC16_32   (0b10000 << OP_SH_SHAMT)
++#define MATCH_SHAMT_ORC16_64   (0b110000 << OP_SH_SHAMT)
++#define MATCH_SHAMT_ORC16_W_64 (0b010000 << OP_SH_SHAMT)
++#define MATCH_SHAMT_ORC32_64   (0b100000 << OP_SH_SHAMT)
+ 
+ /* Register names used by gas and objdump.  */
+ 
+@@ -1207,9 +1326,128 @@ const struct riscv_opcode riscv_opcodes[] =
+ {"rori",       0, INSN_CLASS_ZBB_OR_ZBP,  "d,s,>",    MATCH_RORI, MASK_RORI, match_opcode, 0 },
+ {"ror",        0, INSN_CLASS_ZBB_OR_ZBP,  "d,s,t",    MATCH_ROR, MASK_ROR, match_opcode, 0 },
+ {"ror",        0, INSN_CLASS_ZBB_OR_ZBP,  "d,s,>",    MATCH_RORI, MASK_RORI, match_opcode, INSN_ALIAS },
++{"rev",       32, INSN_CLASS_ZBP,  "d,s",      MATCH_GREVI|MATCH_SHAMT_REV_32, MASK_GREVI|MASK_SHAMT, match_opcode, 0 },
++{"rev",       64, INSN_CLASS_ZBP,  "d,s",      MATCH_GREVI|MATCH_SHAMT_REV_64, MASK_GREVI|MASK_SHAMT, match_opcode, 0 },
++{"rev.p",     32, INSN_CLASS_ZBP,  "d,s",      MATCH_GREVI|MATCH_SHAMT_REV_P_32, MASK_GREVI|MASK_SHAMT, match_opcode, 0 },
++{"rev.p",     64, INSN_CLASS_ZBP,  "d,s",      MATCH_GREVI|MATCH_SHAMT_REV_P_64, MASK_GREVI|MASK_SHAMT, match_opcode, 0 },
++{"rev.n",     32, INSN_CLASS_ZBP,  "d,s",      MATCH_GREVI|MATCH_SHAMT_REV_N_32, MASK_GREVI|MASK_SHAMT, match_opcode, 0 },
++{"rev.n",     64, INSN_CLASS_ZBP,  "d,s",      MATCH_GREVI|MATCH_SHAMT_REV_N_64, MASK_GREVI|MASK_SHAMT, match_opcode, 0 },
++{"rev.b",     32, INSN_CLASS_ZBP,  "d,s",      MATCH_GREVI|MATCH_SHAMT_REV_B_32, MASK_GREVI|MASK_SHAMT, match_opcode, 0 },
++{"rev.b",     64, INSN_CLASS_ZBP,  "d,s",      MATCH_GREVI|MATCH_SHAMT_REV_B_64, MASK_GREVI|MASK_SHAMT, match_opcode, 0 },
++{"rev.h",     32, INSN_CLASS_ZBP,  "d,s",      MATCH_GREVI|MATCH_SHAMT_REV_H_32, MASK_GREVI|MASK_SHAMT, match_opcode, 0 },
++{"rev.h",     64, INSN_CLASS_ZBP,  "d,s",      MATCH_GREVI|MATCH_SHAMT_REV_H_64, MASK_GREVI|MASK_SHAMT, match_opcode, 0 },
++{"rev.w",     64, INSN_CLASS_ZBP,  "d,s",      MATCH_GREVI|MATCH_SHAMT_REV_W_64, MASK_GREVI|MASK_SHAMT, match_opcode, 0 },
++{"rev2",      32, INSN_CLASS_ZBP,  "d,s",      MATCH_GREVI|MATCH_SHAMT_REV2_32, MASK_GREVI|MASK_SHAMT, match_opcode, 0 },
++{"rev2",      64, INSN_CLASS_ZBP,  "d,s",      MATCH_GREVI|MATCH_SHAMT_REV2_64, MASK_GREVI|MASK_SHAMT, match_opcode, 0 },
++{"rev2.n",    32, INSN_CLASS_ZBP,  "d,s",      MATCH_GREVI|MATCH_SHAMT_REV2_N_32, MASK_GREVI|MASK_SHAMT, match_opcode, 0 },
++{"rev2.n",    64, INSN_CLASS_ZBP,  "d,s",      MATCH_GREVI|MATCH_SHAMT_REV2_N_64, MASK_GREVI|MASK_SHAMT, match_opcode, 0 },
++{"rev2.b",    32, INSN_CLASS_ZBP,  "d,s",      MATCH_GREVI|MATCH_SHAMT_REV2_B_32, MASK_GREVI|MASK_SHAMT, match_opcode, 0 },
++{"rev2.b",    64, INSN_CLASS_ZBP,  "d,s",      MATCH_GREVI|MATCH_SHAMT_REV2_B_64, MASK_GREVI|MASK_SHAMT, match_opcode, 0 },
++{"rev2.h",    32, INSN_CLASS_ZBP,  "d,s",      MATCH_GREVI|MATCH_SHAMT_REV2_H_32, MASK_GREVI|MASK_SHAMT, match_opcode, 0 },
++{"rev2.h",    64, INSN_CLASS_ZBP,  "d,s",      MATCH_GREVI|MATCH_SHAMT_REV2_H_64, MASK_GREVI|MASK_SHAMT, match_opcode, 0 },
++{"rev2.w",    64, INSN_CLASS_ZBP,  "d,s",      MATCH_GREVI|MATCH_SHAMT_REV2_W_64, MASK_GREVI|MASK_SHAMT, match_opcode, 0 },
++{"rev4",      32, INSN_CLASS_ZBP,  "d,s",      MATCH_GREVI|MATCH_SHAMT_REV4_32, MASK_GREVI|MASK_SHAMT, match_opcode, 0 },
++{"rev4",      64, INSN_CLASS_ZBP,  "d,s",      MATCH_GREVI|MATCH_SHAMT_REV4_64, MASK_GREVI|MASK_SHAMT, match_opcode, 0 },
++{"rev4.b",    32, INSN_CLASS_ZBP,  "d,s",      MATCH_GREVI|MATCH_SHAMT_REV4_B_32, MASK_GREVI|MASK_SHAMT, match_opcode, 0 },
++{"rev4.b",    64, INSN_CLASS_ZBP,  "d,s",      MATCH_GREVI|MATCH_SHAMT_REV4_B_64, MASK_GREVI|MASK_SHAMT, match_opcode, 0 },
++{"rev4.h",    32, INSN_CLASS_ZBP,  "d,s",      MATCH_GREVI|MATCH_SHAMT_REV4_H_32, MASK_GREVI|MASK_SHAMT, match_opcode, 0 },
++{"rev4.h",    64, INSN_CLASS_ZBP,  "d,s",      MATCH_GREVI|MATCH_SHAMT_REV4_H_64, MASK_GREVI|MASK_SHAMT, match_opcode, 0 },
++{"rev4.w",    64, INSN_CLASS_ZBP,  "d,s",      MATCH_GREVI|MATCH_SHAMT_REV4_W_64, MASK_GREVI|MASK_SHAMT, match_opcode, 0 },
+ {"rev8",      32, INSN_CLASS_ZBB,  "d,s",      MATCH_GREVI|MATCH_SHAMT_REV8_32, MASK_GREVI|MASK_SHAMT, match_opcode, 0 },
+ {"rev8",      64, INSN_CLASS_ZBB,  "d,s",      MATCH_GREVI|MATCH_SHAMT_REV8_64, MASK_GREVI|MASK_SHAMT, match_opcode, 0 },
+-{"orc.b",      0, INSN_CLASS_ZBB,  "d,s",      MATCH_GORCI|MATCH_SHAMT_ORC_B, MASK_GORCI|MASK_SHAMT, match_opcode, 0 },
++{"rev8.h",    32, INSN_CLASS_ZBP,  "d,s",      MATCH_GREVI|MATCH_SHAMT_REV8_H_32, MASK_GREVI|MASK_SHAMT, match_opcode, 0 },
++{"rev8.h",    64, INSN_CLASS_ZBP,  "d,s",      MATCH_GREVI|MATCH_SHAMT_REV8_H_64, MASK_GREVI|MASK_SHAMT, match_opcode, 0 },
++{"rev8.w",    64, INSN_CLASS_ZBP,  "d,s",      MATCH_GREVI|MATCH_SHAMT_REV8_W_64, MASK_GREVI|MASK_SHAMT, match_opcode, 0 },
++{"rev16",     32, INSN_CLASS_ZBP,  "d,s",      MATCH_GREVI|MATCH_SHAMT_REV16_32, MASK_GREVI|MASK_SHAMT, match_opcode, 0 },
++{"rev16",     64, INSN_CLASS_ZBP,  "d,s",      MATCH_GREVI|MATCH_SHAMT_REV16_64, MASK_GREVI|MASK_SHAMT, match_opcode, 0 },
++{"rev16.w",   64, INSN_CLASS_ZBP,  "d,s",      MATCH_GREVI|MATCH_SHAMT_REV16_W_64, MASK_GREVI|MASK_SHAMT, match_opcode, 0 },
++{"rev32",     64, INSN_CLASS_ZBP,  "d,s",      MATCH_GREVI|MATCH_SHAMT_REV32_64, MASK_GREVI|MASK_SHAMT, match_opcode, 0 },
++{"zip",       32, INSN_CLASS_ZBP,  "d,s",      MATCH_SHFLI|MATCH_SHAMT_ZIP_32, MASK_SHFLI|MASK_SHAMT, match_opcode, 0 },
++{"zip",       64, INSN_CLASS_ZBP,  "d,s",      MATCH_SHFLI|MATCH_SHAMT_ZIP_64, MASK_SHFLI|MASK_SHAMT, match_opcode, 0 },
++{"zip.n",     32, INSN_CLASS_ZBP,  "d,s",      MATCH_SHFLI|MATCH_SHAMT_ZIP_N_32, MASK_SHFLI|MASK_SHAMT, match_opcode, 0 },
++{"zip.n",     64, INSN_CLASS_ZBP,  "d,s",      MATCH_SHFLI|MATCH_SHAMT_ZIP_N_64, MASK_SHFLI|MASK_SHAMT, match_opcode, 0 },
++{"zip.b",     32, INSN_CLASS_ZBP,  "d,s",      MATCH_SHFLI|MATCH_SHAMT_ZIP_B_32, MASK_SHFLI|MASK_SHAMT, match_opcode, 0 },
++{"zip.b",     64, INSN_CLASS_ZBP,  "d,s",      MATCH_SHFLI|MATCH_SHAMT_ZIP_B_64, MASK_SHFLI|MASK_SHAMT, match_opcode, 0 },
++{"zip.h",     32, INSN_CLASS_ZBP,  "d,s",      MATCH_SHFLI|MATCH_SHAMT_ZIP_H_32, MASK_SHFLI|MASK_SHAMT, match_opcode, 0 },
++{"zip.h",     64, INSN_CLASS_ZBP,  "d,s",      MATCH_SHFLI|MATCH_SHAMT_ZIP_H_64, MASK_SHFLI|MASK_SHAMT, match_opcode, 0 },
++{"zip.w",     64, INSN_CLASS_ZBP,  "d,s",      MATCH_SHFLI|MATCH_SHAMT_ZIP_W_64, MASK_SHFLI|MASK_SHAMT, match_opcode, 0 },
++{"zip2",      32, INSN_CLASS_ZBP,  "d,s",      MATCH_SHFLI|MATCH_SHAMT_ZIP2_32, MASK_SHFLI|MASK_SHAMT, match_opcode, 0 },
++{"zip2",      64, INSN_CLASS_ZBP,  "d,s",      MATCH_SHFLI|MATCH_SHAMT_ZIP2_64, MASK_SHFLI|MASK_SHAMT, match_opcode, 0 },
++{"zip2.b",    32, INSN_CLASS_ZBP,  "d,s",      MATCH_SHFLI|MATCH_SHAMT_ZIP2_B_32, MASK_SHFLI|MASK_SHAMT, match_opcode, 0 },
++{"zip2.b",    64, INSN_CLASS_ZBP,  "d,s",      MATCH_SHFLI|MATCH_SHAMT_ZIP2_B_64, MASK_SHFLI|MASK_SHAMT, match_opcode, 0 },
++{"zip2.h",    32, INSN_CLASS_ZBP,  "d,s",      MATCH_SHFLI|MATCH_SHAMT_ZIP2_H_32, MASK_SHFLI|MASK_SHAMT, match_opcode, 0 },
++{"zip2.h",    64, INSN_CLASS_ZBP,  "d,s",      MATCH_SHFLI|MATCH_SHAMT_ZIP2_H_64, MASK_SHFLI|MASK_SHAMT, match_opcode, 0 },
++{"zip2.w",    64, INSN_CLASS_ZBP,  "d,s",      MATCH_SHFLI|MATCH_SHAMT_ZIP2_W_64, MASK_SHFLI|MASK_SHAMT, match_opcode, 0 },
++{"zip4",      32, INSN_CLASS_ZBP,  "d,s",      MATCH_SHFLI|MATCH_SHAMT_ZIP4_32, MASK_SHFLI|MASK_SHAMT, match_opcode, 0 },
++{"zip4",      64, INSN_CLASS_ZBP,  "d,s",      MATCH_SHFLI|MATCH_SHAMT_ZIP4_64, MASK_SHFLI|MASK_SHAMT, match_opcode, 0 },
++{"zip4.h",    32, INSN_CLASS_ZBP,  "d,s",      MATCH_SHFLI|MATCH_SHAMT_ZIP4_H_32, MASK_SHFLI|MASK_SHAMT, match_opcode, 0 },
++{"zip4.h",    64, INSN_CLASS_ZBP,  "d,s",      MATCH_SHFLI|MATCH_SHAMT_ZIP4_H_64, MASK_SHFLI|MASK_SHAMT, match_opcode, 0 },
++{"zip4.w",    64, INSN_CLASS_ZBP,  "d,s",      MATCH_SHFLI|MATCH_SHAMT_ZIP4_W_64, MASK_SHFLI|MASK_SHAMT, match_opcode, 0 },
++{"zip8",      32, INSN_CLASS_ZBP,  "d,s",      MATCH_SHFLI|MATCH_SHAMT_ZIP8_32, MASK_SHFLI|MASK_SHAMT, match_opcode, 0 },
++{"zip8",      64, INSN_CLASS_ZBP,  "d,s",      MATCH_SHFLI|MATCH_SHAMT_ZIP8_64, MASK_SHFLI|MASK_SHAMT, match_opcode, 0 },
++{"zip8.w",    64, INSN_CLASS_ZBP,  "d,s",      MATCH_SHFLI|MATCH_SHAMT_ZIP8_W_64, MASK_SHFLI|MASK_SHAMT, match_opcode, 0 },
++{"zip16",     64, INSN_CLASS_ZBP,  "d,s",      MATCH_SHFLI|MATCH_SHAMT_ZIP16_64, MASK_SHFLI|MASK_SHAMT, match_opcode, 0 },
++{"unzip",     32, INSN_CLASS_ZBP,  "d,s",      MATCH_UNSHFLI|MATCH_SHAMT_UNZIP_32, MASK_UNSHFLI|MASK_SHAMT, match_opcode, 0 },
++{"unzip",     64, INSN_CLASS_ZBP,  "d,s",      MATCH_UNSHFLI|MATCH_SHAMT_UNZIP_64, MASK_UNSHFLI|MASK_SHAMT, match_opcode, 0 },
++{"unzip.n",   32, INSN_CLASS_ZBP,  "d,s",      MATCH_UNSHFLI|MATCH_SHAMT_UNZIP_N_32, MASK_UNSHFLI|MASK_SHAMT, match_opcode, 0 },
++{"unzip.n",   64, INSN_CLASS_ZBP,  "d,s",      MATCH_UNSHFLI|MATCH_SHAMT_UNZIP_N_64, MASK_UNSHFLI|MASK_SHAMT, match_opcode, 0 },
++{"unzip.b",   32, INSN_CLASS_ZBP,  "d,s",      MATCH_UNSHFLI|MATCH_SHAMT_UNZIP_B_32, MASK_UNSHFLI|MASK_SHAMT, match_opcode, 0 },
++{"unzip.b",   64, INSN_CLASS_ZBP,  "d,s",      MATCH_UNSHFLI|MATCH_SHAMT_UNZIP_B_64, MASK_UNSHFLI|MASK_SHAMT, match_opcode, 0 },
++{"unzip.h",   32, INSN_CLASS_ZBP,  "d,s",      MATCH_UNSHFLI|MATCH_SHAMT_UNZIP_H_32, MASK_UNSHFLI|MASK_SHAMT, match_opcode, 0 },
++{"unzip.h",   64, INSN_CLASS_ZBP,  "d,s",      MATCH_UNSHFLI|MATCH_SHAMT_UNZIP_H_64, MASK_UNSHFLI|MASK_SHAMT, match_opcode, 0 },
++{"unzip.w",   64, INSN_CLASS_ZBP,  "d,s",      MATCH_UNSHFLI|MATCH_SHAMT_UNZIP_W_64, MASK_UNSHFLI|MASK_SHAMT, match_opcode, 0 },
++{"unzip2",    32, INSN_CLASS_ZBP,  "d,s",      MATCH_UNSHFLI|MATCH_SHAMT_UNZIP2_32, MASK_UNSHFLI|MASK_SHAMT, match_opcode, 0 },
++{"unzip2",    64, INSN_CLASS_ZBP,  "d,s",      MATCH_UNSHFLI|MATCH_SHAMT_UNZIP2_64, MASK_UNSHFLI|MASK_SHAMT, match_opcode, 0 },
++{"unzip2.b",  32, INSN_CLASS_ZBP,  "d,s",      MATCH_UNSHFLI|MATCH_SHAMT_UNZIP2_B_32, MASK_UNSHFLI|MASK_SHAMT, match_opcode, 0 },
++{"unzip2.b",  64, INSN_CLASS_ZBP,  "d,s",      MATCH_UNSHFLI|MATCH_SHAMT_UNZIP2_B_64, MASK_UNSHFLI|MASK_SHAMT, match_opcode, 0 },
++{"unzip2.h",  32, INSN_CLASS_ZBP,  "d,s",      MATCH_UNSHFLI|MATCH_SHAMT_UNZIP2_H_32, MASK_UNSHFLI|MASK_SHAMT, match_opcode, 0 },
++{"unzip2.h",  64, INSN_CLASS_ZBP,  "d,s",      MATCH_UNSHFLI|MATCH_SHAMT_UNZIP2_H_64, MASK_UNSHFLI|MASK_SHAMT, match_opcode, 0 },
++{"unzip2.w",  64, INSN_CLASS_ZBP,  "d,s",      MATCH_UNSHFLI|MATCH_SHAMT_UNZIP2_W_64, MASK_UNSHFLI|MASK_SHAMT, match_opcode, 0 },
++{"unzip4",    32, INSN_CLASS_ZBP,  "d,s",      MATCH_UNSHFLI|MATCH_SHAMT_UNZIP4_32, MASK_UNSHFLI|MASK_SHAMT, match_opcode, 0 },
++{"unzip4",    64, INSN_CLASS_ZBP,  "d,s",      MATCH_UNSHFLI|MATCH_SHAMT_UNZIP4_64, MASK_UNSHFLI|MASK_SHAMT, match_opcode, 0 },
++{"unzip4.h",  32, INSN_CLASS_ZBP,  "d,s",      MATCH_UNSHFLI|MATCH_SHAMT_UNZIP4_H_32, MASK_UNSHFLI|MASK_SHAMT, match_opcode, 0 },
++{"unzip4.h",  64, INSN_CLASS_ZBP,  "d,s",      MATCH_UNSHFLI|MATCH_SHAMT_UNZIP4_H_64, MASK_UNSHFLI|MASK_SHAMT, match_opcode, 0 },
++{"unzip4.w",  64, INSN_CLASS_ZBP,  "d,s",      MATCH_UNSHFLI|MATCH_SHAMT_UNZIP4_W_64, MASK_UNSHFLI|MASK_SHAMT, match_opcode, 0 },
++{"unzip8",    32, INSN_CLASS_ZBP,  "d,s",      MATCH_UNSHFLI|MATCH_SHAMT_UNZIP8_32, MASK_UNSHFLI|MASK_SHAMT, match_opcode, 0 },
++{"unzip8",    64, INSN_CLASS_ZBP,  "d,s",      MATCH_UNSHFLI|MATCH_SHAMT_UNZIP8_64, MASK_UNSHFLI|MASK_SHAMT, match_opcode, 0 },
++{"unzip8.w",  64, INSN_CLASS_ZBP,  "d,s",      MATCH_UNSHFLI|MATCH_SHAMT_UNZIP8_W_64, MASK_UNSHFLI|MASK_SHAMT, match_opcode, 0 },
++{"unzip16",   64, INSN_CLASS_ZBP,  "d,s",      MATCH_UNSHFLI|MATCH_SHAMT_UNZIP16_64, MASK_UNSHFLI|MASK_SHAMT, match_opcode, 0 },
++{"orc",       32, INSN_CLASS_ZBP,  "d,s",      MATCH_GORCI|MATCH_SHAMT_ORC_32, MASK_GORCI|MASK_SHAMT, match_opcode, 0 },
++{"orc",       64, INSN_CLASS_ZBP,  "d,s",      MATCH_GORCI|MATCH_SHAMT_ORC_64, MASK_GORCI|MASK_SHAMT, match_opcode, 0 },
++{"orc.p",     32, INSN_CLASS_ZBP,  "d,s",      MATCH_GORCI|MATCH_SHAMT_ORC_P_32, MASK_GORCI|MASK_SHAMT, match_opcode, 0 },
++{"orc.p",     64, INSN_CLASS_ZBP,  "d,s",      MATCH_GORCI|MATCH_SHAMT_ORC_P_64, MASK_GORCI|MASK_SHAMT, match_opcode, 0 },
++{"orc.n",     32, INSN_CLASS_ZBP,  "d,s",      MATCH_GORCI|MATCH_SHAMT_ORC_N_32, MASK_GORCI|MASK_SHAMT, match_opcode, 0 },
++{"orc.n",     64, INSN_CLASS_ZBP,  "d,s",      MATCH_GORCI|MATCH_SHAMT_ORC_N_64, MASK_GORCI|MASK_SHAMT, match_opcode, 0 },
++{"orc.b",     32, INSN_CLASS_ZBB,  "d,s",      MATCH_GORCI|MATCH_SHAMT_ORC_B_32, MASK_GORCI|MASK_SHAMT, match_opcode, 0 },
++{"orc.b",     64, INSN_CLASS_ZBB,  "d,s",      MATCH_GORCI|MATCH_SHAMT_ORC_B_64, MASK_GORCI|MASK_SHAMT, match_opcode, 0 },
++{"orc.h",     32, INSN_CLASS_ZBP,  "d,s",      MATCH_GORCI|MATCH_SHAMT_ORC_H_32, MASK_GORCI|MASK_SHAMT, match_opcode, 0 },
++{"orc.h",     64, INSN_CLASS_ZBP,  "d,s",      MATCH_GORCI|MATCH_SHAMT_ORC_H_64, MASK_GORCI|MASK_SHAMT, match_opcode, 0 },
++{"orc.w",     64, INSN_CLASS_ZBP,  "d,s",      MATCH_GORCI|MATCH_SHAMT_ORC_W_64, MASK_GORCI|MASK_SHAMT, match_opcode, 0 },
++{"orc2",      32, INSN_CLASS_ZBP,  "d,s",      MATCH_GORCI|MATCH_SHAMT_ORC2_32, MASK_GORCI|MASK_SHAMT, match_opcode, 0 },
++{"orc2",      64, INSN_CLASS_ZBP,  "d,s",      MATCH_GORCI|MATCH_SHAMT_ORC2_64, MASK_GORCI|MASK_SHAMT, match_opcode, 0 },
++{"orc2.n",    32, INSN_CLASS_ZBP,  "d,s",      MATCH_GORCI|MATCH_SHAMT_ORC2_N_32, MASK_GORCI|MASK_SHAMT, match_opcode, 0 },
++{"orc2.n",    64, INSN_CLASS_ZBP,  "d,s",      MATCH_GORCI|MATCH_SHAMT_ORC2_N_64, MASK_GORCI|MASK_SHAMT, match_opcode, 0 },
++{"orc2.b",    32, INSN_CLASS_ZBP,  "d,s",      MATCH_GORCI|MATCH_SHAMT_ORC2_B_32, MASK_GORCI|MASK_SHAMT, match_opcode, 0 },
++{"orc2.b",    64, INSN_CLASS_ZBP,  "d,s",      MATCH_GORCI|MATCH_SHAMT_ORC2_B_64, MASK_GORCI|MASK_SHAMT, match_opcode, 0 },
++{"orc2.h",    32, INSN_CLASS_ZBP,  "d,s",      MATCH_GORCI|MATCH_SHAMT_ORC2_H_32, MASK_GORCI|MASK_SHAMT, match_opcode, 0 },
++{"orc2.h",    64, INSN_CLASS_ZBP,  "d,s",      MATCH_GORCI|MATCH_SHAMT_ORC2_H_64, MASK_GORCI|MASK_SHAMT, match_opcode, 0 },
++{"orc2.w",    64, INSN_CLASS_ZBP,  "d,s",      MATCH_GORCI|MATCH_SHAMT_ORC2_W_64, MASK_GORCI|MASK_SHAMT, match_opcode, 0 },
++{"orc4",      32, INSN_CLASS_ZBP,  "d,s",      MATCH_GORCI|MATCH_SHAMT_ORC4_32, MASK_GORCI|MASK_SHAMT, match_opcode, 0 },
++{"orc4",      64, INSN_CLASS_ZBP,  "d,s",      MATCH_GORCI|MATCH_SHAMT_ORC4_64, MASK_GORCI|MASK_SHAMT, match_opcode, 0 },
++{"orc4.b",    32, INSN_CLASS_ZBP,  "d,s",      MATCH_GORCI|MATCH_SHAMT_ORC4_B_32, MASK_GORCI|MASK_SHAMT, match_opcode, 0 },
++{"orc4.b",    64, INSN_CLASS_ZBP,  "d,s",      MATCH_GORCI|MATCH_SHAMT_ORC4_B_64, MASK_GORCI|MASK_SHAMT, match_opcode, 0 },
++{"orc4.h",    32, INSN_CLASS_ZBP,  "d,s",      MATCH_GORCI|MATCH_SHAMT_ORC4_H_32, MASK_GORCI|MASK_SHAMT, match_opcode, 0 },
++{"orc4.h",    64, INSN_CLASS_ZBP,  "d,s",      MATCH_GORCI|MATCH_SHAMT_ORC4_H_64, MASK_GORCI|MASK_SHAMT, match_opcode, 0 },
++{"orc4.w",    64, INSN_CLASS_ZBP,  "d,s",      MATCH_GORCI|MATCH_SHAMT_ORC4_W_64, MASK_GORCI|MASK_SHAMT, match_opcode, 0 },
++{"orc8",      32, INSN_CLASS_ZBP,  "d,s",      MATCH_GORCI|MATCH_SHAMT_ORC8_32, MASK_GORCI|MASK_SHAMT, match_opcode, 0 },
++{"orc8",      64, INSN_CLASS_ZBP,  "d,s",      MATCH_GORCI|MATCH_SHAMT_ORC8_64, MASK_GORCI|MASK_SHAMT, match_opcode, 0 },
++{"orc8.h",    32, INSN_CLASS_ZBP,  "d,s",      MATCH_GORCI|MATCH_SHAMT_ORC8_H_32, MASK_GORCI|MASK_SHAMT, match_opcode, 0 },
++{"orc8.h",    64, INSN_CLASS_ZBP,  "d,s",      MATCH_GORCI|MATCH_SHAMT_ORC8_H_64, MASK_GORCI|MASK_SHAMT, match_opcode, 0 },
++{"orc8.w",    64, INSN_CLASS_ZBP,  "d,s",      MATCH_GORCI|MATCH_SHAMT_ORC8_W_64, MASK_GORCI|MASK_SHAMT, match_opcode, 0 },
++{"orc16",     32, INSN_CLASS_ZBP,  "d,s",      MATCH_GORCI|MATCH_SHAMT_ORC16_32, MASK_GORCI|MASK_SHAMT, match_opcode, 0 },
++{"orc16",     64, INSN_CLASS_ZBP,  "d,s",      MATCH_GORCI|MATCH_SHAMT_ORC16_64, MASK_GORCI|MASK_SHAMT, match_opcode, 0 },
++{"orc16.w",   64, INSN_CLASS_ZBP,  "d,s",      MATCH_GORCI|MATCH_SHAMT_ORC16_W_64, MASK_GORCI|MASK_SHAMT, match_opcode, 0 },
++{"orc32",     64, INSN_CLASS_ZBP,  "d,s",      MATCH_GORCI|MATCH_SHAMT_ORC32_64, MASK_GORCI|MASK_SHAMT, match_opcode, 0 },
+ {"clzw",      64, INSN_CLASS_ZBB,  "d,s",      MATCH_CLZW, MASK_CLZW, match_opcode, 0 },
+ {"ctzw",      64, INSN_CLASS_ZBB,  "d,s",      MATCH_CTZW, MASK_CTZW, match_opcode, 0 },
+ {"cpopw",     64, INSN_CLASS_ZBB,  "d,s",      MATCH_CPOPW, MASK_CPOPW, match_opcode, 0 },
+-- 
+2.33.0
+

+ 81 - 0
recipes-devtools/binutils/binutils/0007-Rename-bdep-to-bdecompress.patch

@@ -0,0 +1,81 @@
+From 84473196ba4b0c79bc9cb7a36d029fe6510d26a6 Mon Sep 17 00:00:00 2001
+From: LevyHsu <admin@levyhsu.com>
+Date: Tue, 8 Jun 2021 16:24:03 +0800
+Subject: [PATCH 07/28] Rename bdep to bdecompress
+
+MATCH_BDECOMPRESS
+MASK_BDECOMPRESS
+---
+ include/opcode/riscv-opc.h | 12 ++++++------
+ opcodes/riscv-opc.c        |  4 ++--
+ 2 files changed, 8 insertions(+), 8 deletions(-)
+
+diff --git a/include/opcode/riscv-opc.h b/include/opcode/riscv-opc.h
+index 5bb3803d03..fc08a3be7e 100644
+--- a/include/opcode/riscv-opc.h
++++ b/include/opcode/riscv-opc.h
+@@ -535,8 +535,8 @@
+ #define MASK_UNSHFL  0xfe00707f
+ #define MATCH_UNSHFLI 0x8005013
+ #define MASK_UNSHFLI  0xfc00707f
+-#define MATCH_BDEP 0x48006033
+-#define MASK_BDEP  0xfe00707f
++#define MATCH_BDECOMPRESS 0x48006033
++#define MASK_BDECOMPRESS  0xfe00707f
+ #define MATCH_SEXT_B 0x60401013
+ #define MASK_SEXT_B  0xfff0707f
+ #define MATCH_SEXT_H 0x60501013
+@@ -663,8 +663,8 @@
+ #define MASK_SHFLW  0xfe00707f
+ #define MATCH_UNSHFLW 0x800503b
+ #define MASK_UNSHFLW  0xfe00707f
+-#define MATCH_BDEPW 0x4800603b
+-#define MASK_BDEPW  0xfe00707f
++#define MATCH_BDECOMPRESSW 0x4800603b
++#define MASK_BDECOMPRESSW  0xfe00707f
+ #define MATCH_BFPW 0x4800703b
+ #define MASK_BFPW  0xfe00707f
+ #define MATCH_XPERM_N 0x28002033
+@@ -3264,7 +3264,7 @@ DECLARE_INSN(bset, MATCH_BSET, MASK_BSET)
+ DECLARE_INSN(bclr, MATCH_BCLR, MASK_BCLR)
+ DECLARE_INSN(binv, MATCH_BINV, MASK_BINV)
+ DECLARE_INSN(bext, MATCH_BEXT, MASK_BEXT)
+-DECLARE_INSN(bdep, MATCH_BDEP, MASK_BDEP)
++DECLARE_INSN(bdecompress, MATCH_BDECOMPRESS, MASK_BDECOMPRESS)
+ DECLARE_INSN(bseti, MATCH_BSETI, MASK_BSETI)
+ DECLARE_INSN(bclri, MATCH_BCLRI, MASK_BCLRI)
+ DECLARE_INSN(binvi, MATCH_BINVI, MASK_BINVI)
+@@ -3273,7 +3273,7 @@ DECLARE_INSN(bsetw, MATCH_BSETW, MASK_BSETW)
+ DECLARE_INSN(bclrw, MATCH_BCLRW, MASK_BCLRW)
+ DECLARE_INSN(binvw, MATCH_BINVW, MASK_BINVW)
+ DECLARE_INSN(bextw, MATCH_BEXTW, MASK_BEXTW)
+-DECLARE_INSN(bdepw, MATCH_BDEPW, MASK_BDEPW)
++DECLARE_INSN(bdecompressw, MATCH_BDECOMPRESSW, MASK_BDECOMPRESSW)
+ DECLARE_INSN(bsetiw, MATCH_BSETIW, MASK_BSETIW)
+ DECLARE_INSN(bclriw, MATCH_BCLRIW, MASK_BCLRIW)
+ DECLARE_INSN(binviw, MATCH_BINVIW, MASK_BINVIW)
+diff --git a/opcodes/riscv-opc.c b/opcodes/riscv-opc.c
+index dc7c1fb428..5783c79df9 100644
+--- a/opcodes/riscv-opc.c
++++ b/opcodes/riscv-opc.c
+@@ -1497,7 +1497,7 @@ const struct riscv_opcode riscv_opcodes[] =
+ {"bclr",       0, INSN_CLASS_ZBS,  "d,s,t",    MATCH_BCLR, MASK_BCLR, match_opcode, 0 },
+ {"binv",       0, INSN_CLASS_ZBS,  "d,s,t",    MATCH_BINV, MASK_BINV, match_opcode, 0 },
+ {"bext",       0, INSN_CLASS_ZBS_OR_ZBE,  "d,s,t",    MATCH_BEXT, MASK_BEXT, match_opcode, 0 },
+-{"bdep",       0, INSN_CLASS_ZBE,  "d,s,t",    MATCH_BDEP, MASK_BDEP, match_opcode, 0 },
++{"bdecompress",0, INSN_CLASS_ZBE,  "d,s,t",    MATCH_BDECOMPRESS, MASK_BDECOMPRESS, match_opcode, 0 },
+ {"bseti",      0, INSN_CLASS_ZBS,  "d,s,>",    MATCH_BSETI, MASK_BSETI, match_opcode, 0 },
+ {"bclri",      0, INSN_CLASS_ZBS,  "d,s,>",    MATCH_BCLRI, MASK_BCLRI, match_opcode, 0 },
+ {"binvi",      0, INSN_CLASS_ZBS,  "d,s,>",    MATCH_BINVI, MASK_BINVI, match_opcode, 0 },
+@@ -1506,7 +1506,7 @@ const struct riscv_opcode riscv_opcodes[] =
+ {"bclrw",     64, INSN_CLASS_ZBS,  "d,s,t",    MATCH_BCLRW, MASK_BCLRW, match_opcode, 0 },
+ {"binvw",     64, INSN_CLASS_ZBS,  "d,s,t",    MATCH_BINVW, MASK_BINVW, match_opcode, 0 },
+ {"bextw",     64, INSN_CLASS_ZBS_OR_ZBE,  "d,s,t",    MATCH_BEXTW, MASK_BEXTW, match_opcode, 0 },
+-{"bdepw",     64, INSN_CLASS_ZBE,  "d,s,<",    MATCH_BDEPW, MASK_BDEPW, match_opcode, 0 },
++{"bdecompressw",64, INSN_CLASS_ZBE,  "d,s,<",    MATCH_BDECOMPRESSW, MASK_BDECOMPRESSW, match_opcode, 0 },
+ {"bsetiw",    64, INSN_CLASS_ZBS,  "d,s,<",    MATCH_BSETIW, MASK_BSETIW, match_opcode, 0 },
+ {"bclriw",    64, INSN_CLASS_ZBS,  "d,s,<",    MATCH_BCLRIW, MASK_BCLRIW, match_opcode, 0 },
+ {"binviw",    64, INSN_CLASS_ZBS,  "d,s,<",    MATCH_BINVIW, MASK_BINVIW, match_opcode, 0 },
+-- 
+2.33.0
+

+ 76 - 0
recipes-devtools/binutils/binutils/0008-RISCV-Add-support-for-bcompress.patch

@@ -0,0 +1,76 @@
+From 4046c346a88fd00f032e7ef6766a3fd0431e6c1a Mon Sep 17 00:00:00 2001
+From: LevyHsu <admin@levyhsu.com>
+Date: Tue, 8 Jun 2021 17:09:36 +0800
+Subject: [PATCH 08/28] [RISCV] Add support for bcompress
+
+Add coding for bcompress:
+#define MATCH_BCOMPRESS 0x8006033
+#define MASK_BCOMPRESS  0xfe00707f
+#define MATCH_BCOMPRESSW 0x4800603b
+#define MASK_BCOMPRESSW  0xfe00707f
+---
+ include/opcode/riscv-opc.h | 6 ++++++
+ opcodes/riscv-opc.c        | 2 ++
+ 2 files changed, 8 insertions(+)
+
+diff --git a/include/opcode/riscv-opc.h b/include/opcode/riscv-opc.h
+index fc08a3be7e..8a25e90f65 100644
+--- a/include/opcode/riscv-opc.h
++++ b/include/opcode/riscv-opc.h
+@@ -535,6 +535,8 @@
+ #define MASK_UNSHFL  0xfe00707f
+ #define MATCH_UNSHFLI 0x8005013
+ #define MASK_UNSHFLI  0xfc00707f
++#define MATCH_BCOMPRESS 0x8006033
++#define MASK_BCOMPRESS  0xfe00707f
+ #define MATCH_BDECOMPRESS 0x48006033
+ #define MASK_BDECOMPRESS  0xfe00707f
+ #define MATCH_SEXT_B 0x60401013
+@@ -663,6 +665,8 @@
+ #define MASK_SHFLW  0xfe00707f
+ #define MATCH_UNSHFLW 0x800503b
+ #define MASK_UNSHFLW  0xfe00707f
++#define MATCH_BCOMPRESSW 0x4800603b
++#define MASK_BCOMPRESSW  0xfe00707f
+ #define MATCH_BDECOMPRESSW 0x4800603b
+ #define MASK_BDECOMPRESSW  0xfe00707f
+ #define MATCH_BFPW 0x4800703b
+@@ -3264,6 +3268,7 @@ DECLARE_INSN(bset, MATCH_BSET, MASK_BSET)
+ DECLARE_INSN(bclr, MATCH_BCLR, MASK_BCLR)
+ DECLARE_INSN(binv, MATCH_BINV, MASK_BINV)
+ DECLARE_INSN(bext, MATCH_BEXT, MASK_BEXT)
++DECLARE_INSN(bcompress, MATCH_BCOMPRESS, MASK_BCOMPRESS)
+ DECLARE_INSN(bdecompress, MATCH_BDECOMPRESS, MASK_BDECOMPRESS)
+ DECLARE_INSN(bseti, MATCH_BSETI, MASK_BSETI)
+ DECLARE_INSN(bclri, MATCH_BCLRI, MASK_BCLRI)
+@@ -3273,6 +3278,7 @@ DECLARE_INSN(bsetw, MATCH_BSETW, MASK_BSETW)
+ DECLARE_INSN(bclrw, MATCH_BCLRW, MASK_BCLRW)
+ DECLARE_INSN(binvw, MATCH_BINVW, MASK_BINVW)
+ DECLARE_INSN(bextw, MATCH_BEXTW, MASK_BEXTW)
++DECLARE_INSN(bcompressw, MATCH_BCOMPRESSW, MASK_BCOMPRESSW)
+ DECLARE_INSN(bdecompressw, MATCH_BDECOMPRESSW, MASK_BDECOMPRESSW)
+ DECLARE_INSN(bsetiw, MATCH_BSETIW, MASK_BSETIW)
+ DECLARE_INSN(bclriw, MATCH_BCLRIW, MASK_BCLRIW)
+diff --git a/opcodes/riscv-opc.c b/opcodes/riscv-opc.c
+index 5783c79df9..ab2f80d00f 100644
+--- a/opcodes/riscv-opc.c
++++ b/opcodes/riscv-opc.c
+@@ -1497,6 +1497,7 @@ const struct riscv_opcode riscv_opcodes[] =
+ {"bclr",       0, INSN_CLASS_ZBS,  "d,s,t",    MATCH_BCLR, MASK_BCLR, match_opcode, 0 },
+ {"binv",       0, INSN_CLASS_ZBS,  "d,s,t",    MATCH_BINV, MASK_BINV, match_opcode, 0 },
+ {"bext",       0, INSN_CLASS_ZBS_OR_ZBE,  "d,s,t",    MATCH_BEXT, MASK_BEXT, match_opcode, 0 },
++{"bcompress",0, INSN_CLASS_ZBE,  "d,s,t",    MATCH_BCOMPRESS, MASK_BCOMPRESS, match_opcode, 0 },
+ {"bdecompress",0, INSN_CLASS_ZBE,  "d,s,t",    MATCH_BDECOMPRESS, MASK_BDECOMPRESS, match_opcode, 0 },
+ {"bseti",      0, INSN_CLASS_ZBS,  "d,s,>",    MATCH_BSETI, MASK_BSETI, match_opcode, 0 },
+ {"bclri",      0, INSN_CLASS_ZBS,  "d,s,>",    MATCH_BCLRI, MASK_BCLRI, match_opcode, 0 },
+@@ -1506,6 +1507,7 @@ const struct riscv_opcode riscv_opcodes[] =
+ {"bclrw",     64, INSN_CLASS_ZBS,  "d,s,t",    MATCH_BCLRW, MASK_BCLRW, match_opcode, 0 },
+ {"binvw",     64, INSN_CLASS_ZBS,  "d,s,t",    MATCH_BINVW, MASK_BINVW, match_opcode, 0 },
+ {"bextw",     64, INSN_CLASS_ZBS_OR_ZBE,  "d,s,t",    MATCH_BEXTW, MASK_BEXTW, match_opcode, 0 },
++{"bcompressw",64, INSN_CLASS_ZBE,  "d,s,<",    MATCH_BCOMPRESSW, MASK_BCOMPRESSW, match_opcode, 0 },
+ {"bdecompressw",64, INSN_CLASS_ZBE,  "d,s,<",    MATCH_BDECOMPRESSW, MASK_BDECOMPRESSW, match_opcode, 0 },
+ {"bsetiw",    64, INSN_CLASS_ZBS,  "d,s,<",    MATCH_BSETIW, MASK_BSETIW, match_opcode, 0 },
+ {"bclriw",    64, INSN_CLASS_ZBS,  "d,s,<",    MATCH_BCLRIW, MASK_BCLRIW, match_opcode, 0 },
+-- 
+2.33.0
+

+ 25 - 0
recipes-devtools/binutils/binutils/0009-RISCV-Coding-bug-Fix-for-FSRW.patch

@@ -0,0 +1,25 @@
+From 85e66e4e2dbcb44c17f00833cf0abfc338ced168 Mon Sep 17 00:00:00 2001
+From: LevyHsu <admin@levyhsu.com>
+Date: Thu, 10 Jun 2021 15:45:29 +0800
+Subject: [PATCH 09/28] [RISCV] Coding bug Fix for FSRW
+
+---
+ include/opcode/riscv-opc.h | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+diff --git a/include/opcode/riscv-opc.h b/include/opcode/riscv-opc.h
+index 8a25e90f65..5bc9345178 100644
+--- a/include/opcode/riscv-opc.h
++++ b/include/opcode/riscv-opc.h
+@@ -657,7 +657,7 @@
+ #define MASK_GREVIW  0xfe00707f
+ #define MATCH_FSLW 0x400103b
+ #define MASK_FSLW  0x600707f
+-#define MATCH_FSRW 0x400303b
++#define MATCH_FSRW 0x400503B
+ #define MASK_FSRW  0x600707f
+ #define MATCH_FSRIW 0x400301b
+ #define MASK_FSRIW  0x600707f
+-- 
+2.33.0
+

+ 25 - 0
recipes-devtools/binutils/binutils/0010-RISCV-Coding-bug-Fix-for-FSRIW.patch

@@ -0,0 +1,25 @@
+From 0f7de0c56b144b5ea2c76289766e2ffd9dc212cc Mon Sep 17 00:00:00 2001
+From: LevyHsu <admin@levyhsu.com>
+Date: Thu, 10 Jun 2021 16:11:19 +0800
+Subject: [PATCH 10/28] [RISCV] Coding bug Fix for FSRIW
+
+---
+ include/opcode/riscv-opc.h | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+diff --git a/include/opcode/riscv-opc.h b/include/opcode/riscv-opc.h
+index 5bc9345178..3a86dfc17d 100644
+--- a/include/opcode/riscv-opc.h
++++ b/include/opcode/riscv-opc.h
+@@ -659,7 +659,7 @@
+ #define MASK_FSLW  0x600707f
+ #define MATCH_FSRW 0x400503B
+ #define MASK_FSRW  0x600707f
+-#define MATCH_FSRIW 0x400301b
++#define MATCH_FSRIW 0x400501B
+ #define MASK_FSRIW  0x600707f
+ #define MATCH_SHFLW 0x800103b
+ #define MASK_SHFLW  0xfe00707f
+-- 
+2.33.0
+

+ 274 - 0
recipes-devtools/binutils/binutils/0011-RISCV-Fix-coding-for-un-zip-2-4-8-16-n-b-h-w.patch

@@ -0,0 +1,274 @@
+From 67096c46a4874962ca87030abe6dc77158c97dc9 Mon Sep 17 00:00:00 2001
+From: LevyHsu <admin@levyhsu.com>
+Date: Wed, 16 Jun 2021 10:34:18 +0800
+Subject: [PATCH 11/28] [RISCV] Fix coding for [un]zip[2/4//8/16][n/b/h/w]
+
+---
+ .vscode/launch.json |  27 ++++++
+ opcodes/riscv-opc.c | 201 ++++++++++++++++++++++----------------------
+ 2 files changed, 128 insertions(+), 100 deletions(-)
+ create mode 100644 .vscode/launch.json
+
+diff --git a/.vscode/launch.json b/.vscode/launch.json
+new file mode 100644
+index 0000000000..6da48c352b
+--- /dev/null
++++ b/.vscode/launch.json
+@@ -0,0 +1,27 @@
++{
++    // Use IntelliSense to learn about possible attributes.
++    // Hover to view descriptions of existing attributes.
++    // For more information, visit: https://go.microsoft.com/fwlink/?linkid=830387
++    "version": "0.2.0",
++    "configurations": [
++        {
++            "name": "(gdb) Launch",
++            "type": "cppdbg",
++            "request": "launch",
++            "program": "/home/levy/Desktop/freelight-e-studio/llvm-packaging-tool/install/bin/riscv64-unknown-elf-objdump",
++            "args": ["-S", "/home/levy/Desktop/freelight-e-studio/llvm-packaging-tool/test/b-ext/a.out"],
++            "stopAtEntry": true,
++            "cwd": "${fileDirname}",
++            "environment": [],
++            "externalConsole": false,
++            "MIMode": "gdb",
++            "setupCommands": [
++                {
++                    "description": "Enable pretty-printing for gdb",
++                    "text": "-enable-pretty-printing",
++                    "ignoreFailures": true
++                }
++            ]
++        }
++    ]
++}
+\ No newline at end of file
+diff --git a/opcodes/riscv-opc.c b/opcodes/riscv-opc.c
+index ab2f80d00f..a01a5c9202 100644
+--- a/opcodes/riscv-opc.c
++++ b/opcodes/riscv-opc.c
+@@ -25,6 +25,7 @@
+ #include <stdio.h>
+ 
+ #define MASK_SHAMT (OP_MASK_SHAMT << OP_SH_SHAMT)
++#define MASK_SHAMT2 (OP_MASK_RS2 << OP_SH_SHAMT)
+ #define MATCH_SHAMT_REV_32     (0b11111 << OP_SH_SHAMT)
+ #define MATCH_SHAMT_REV_64     (0b111111 << OP_SH_SHAMT)
+ #define MATCH_SHAMT_REV_P_32   (0b00001 << OP_SH_SHAMT)
+@@ -61,56 +62,56 @@
+ #define MATCH_SHAMT_REV16_64   (0b110000 << OP_SH_SHAMT)
+ #define MATCH_SHAMT_REV16_W_64 (0b010000 << OP_SH_SHAMT)
+ #define MATCH_SHAMT_REV32_64   (0b100000 << OP_SH_SHAMT)
+-#define MATCH_SHAMT_ZIP_32     (0b11110 << OP_SH_SHAMT)
+-#define MATCH_SHAMT_ZIP_64     (0b111110 << OP_SH_SHAMT)
+-#define MATCH_SHAMT_ZIP_N_32   (0b00010 << OP_SH_SHAMT)
+-#define MATCH_SHAMT_ZIP_N_64   (0b000010 << OP_SH_SHAMT)
+-#define MATCH_SHAMT_ZIP_B_32   (0b00110 << OP_SH_SHAMT)
+-#define MATCH_SHAMT_ZIP_B_64   (0b000110 << OP_SH_SHAMT)
+-#define MATCH_SHAMT_ZIP_H_32   (0b01110 << OP_SH_SHAMT)
+-#define MATCH_SHAMT_ZIP_H_64   (0b001110 << OP_SH_SHAMT)
+-#define MATCH_SHAMT_ZIP_W_64   (0b011110 << OP_SH_SHAMT)
+-#define MATCH_SHAMT_ZIP2_32    (0b11100 << OP_SH_SHAMT)
+-#define MATCH_SHAMT_ZIP2_64    (0b111100 << OP_SH_SHAMT)
+-#define MATCH_SHAMT_ZIP2_B_32  (0b00100 << OP_SH_SHAMT)
+-#define MATCH_SHAMT_ZIP2_B_64  (0b000100 << OP_SH_SHAMT)
+-#define MATCH_SHAMT_ZIP2_H_32  (0b01100 << OP_SH_SHAMT)
+-#define MATCH_SHAMT_ZIP2_H_64  (0b001100 << OP_SH_SHAMT)
+-#define MATCH_SHAMT_ZIP2_W_64  (0b011100 << OP_SH_SHAMT)
+-#define MATCH_SHAMT_ZIP4_32    (0b11000 << OP_SH_SHAMT)
+-#define MATCH_SHAMT_ZIP4_64    (0b111000 << OP_SH_SHAMT)
+-#define MATCH_SHAMT_ZIP4_H_32  (0b01000 << OP_SH_SHAMT)
+-#define MATCH_SHAMT_ZIP4_H_64  (0b001000 << OP_SH_SHAMT)
+-#define MATCH_SHAMT_ZIP4_W_64  (0b011000 << OP_SH_SHAMT)
+-#define MATCH_SHAMT_ZIP8_32    (0b10000 << OP_SH_SHAMT)
+-#define MATCH_SHAMT_ZIP8_64    (0b110000 << OP_SH_SHAMT)
+-#define MATCH_SHAMT_ZIP8_W_64  (0b010000 << OP_SH_SHAMT)
+-#define MATCH_SHAMT_ZIP16_64   (0b100000 << OP_SH_SHAMT)
+-#define MATCH_SHAMT_UNZIP_32     (0b11111 << OP_SH_SHAMT)
+-#define MATCH_SHAMT_UNZIP_64     (0b111111 << OP_SH_SHAMT)
+-#define MATCH_SHAMT_UNZIP_N_32   (0b00011 << OP_SH_SHAMT)
+-#define MATCH_SHAMT_UNZIP_N_64   (0b000011 << OP_SH_SHAMT)
+-#define MATCH_SHAMT_UNZIP_B_32   (0b00111 << OP_SH_SHAMT)
+-#define MATCH_SHAMT_UNZIP_B_64   (0b000111 << OP_SH_SHAMT)
+-#define MATCH_SHAMT_UNZIP_H_32   (0b01111 << OP_SH_SHAMT)
+-#define MATCH_SHAMT_UNZIP_H_64   (0b001111 << OP_SH_SHAMT)
+-#define MATCH_SHAMT_UNZIP_W_64   (0b011111 << OP_SH_SHAMT)
+-#define MATCH_SHAMT_UNZIP2_32    (0b11101 << OP_SH_SHAMT)
+-#define MATCH_SHAMT_UNZIP2_64    (0b111101 << OP_SH_SHAMT)
+-#define MATCH_SHAMT_UNZIP2_B_32  (0b00101 << OP_SH_SHAMT)
+-#define MATCH_SHAMT_UNZIP2_B_64  (0b000101 << OP_SH_SHAMT)
+-#define MATCH_SHAMT_UNZIP2_H_32  (0b01101 << OP_SH_SHAMT)
+-#define MATCH_SHAMT_UNZIP2_H_64  (0b001101 << OP_SH_SHAMT)
+-#define MATCH_SHAMT_UNZIP2_W_64  (0b011101 << OP_SH_SHAMT)
+-#define MATCH_SHAMT_UNZIP4_32    (0b11001 << OP_SH_SHAMT)
+-#define MATCH_SHAMT_UNZIP4_64    (0b111001 << OP_SH_SHAMT)
+-#define MATCH_SHAMT_UNZIP4_H_32  (0b01001 << OP_SH_SHAMT)
+-#define MATCH_SHAMT_UNZIP4_H_64  (0b001001 << OP_SH_SHAMT)
+-#define MATCH_SHAMT_UNZIP4_W_64  (0b011001 << OP_SH_SHAMT)
+-#define MATCH_SHAMT_UNZIP8_32    (0b10001 << OP_SH_SHAMT)
+-#define MATCH_SHAMT_UNZIP8_64    (0b110001 << OP_SH_SHAMT)
+-#define MATCH_SHAMT_UNZIP8_W_64  (0b010001 << OP_SH_SHAMT)
+-#define MATCH_SHAMT_UNZIP16_64   (0b100001 << OP_SH_SHAMT)
++#define MATCH_SHAMT_ZIP_32     (0b1111 << OP_SH_SHAMT)
++#define MATCH_SHAMT_ZIP_64     (0b11111 << OP_SH_SHAMT)
++#define MATCH_SHAMT_ZIP_N_32   (0b0001 << OP_SH_SHAMT)
++#define MATCH_SHAMT_ZIP_N_64   (0b00001 << OP_SH_SHAMT)
++#define MATCH_SHAMT_ZIP_B_32   (0b0011 << OP_SH_SHAMT)
++#define MATCH_SHAMT_ZIP_B_64   (0b00011 << OP_SH_SHAMT)
++#define MATCH_SHAMT_ZIP_H_32   (0b0111 << OP_SH_SHAMT)
++#define MATCH_SHAMT_ZIP_H_64   (0b00111 << OP_SH_SHAMT)
++#define MATCH_SHAMT_ZIP_W_64   (0b01111 << OP_SH_SHAMT)
++#define MATCH_SHAMT_ZIP2_32    (0b1110 << OP_SH_SHAMT)
++#define MATCH_SHAMT_ZIP2_64    (0b11110 << OP_SH_SHAMT)
++#define MATCH_SHAMT_ZIP2_B_32  (0b0010 << OP_SH_SHAMT)
++#define MATCH_SHAMT_ZIP2_B_64  (0b00010 << OP_SH_SHAMT)
++#define MATCH_SHAMT_ZIP2_H_32  (0b0110 << OP_SH_SHAMT)
++#define MATCH_SHAMT_ZIP2_H_64  (0b00110 << OP_SH_SHAMT)
++#define MATCH_SHAMT_ZIP2_W_64  (0b01110 << OP_SH_SHAMT)
++#define MATCH_SHAMT_ZIP4_32    (0b1100 << OP_SH_SHAMT)
++#define MATCH_SHAMT_ZIP4_64    (0b11100 << OP_SH_SHAMT)
++#define MATCH_SHAMT_ZIP4_H_32  (0b0100 << OP_SH_SHAMT)
++#define MATCH_SHAMT_ZIP4_H_64  (0b00100 << OP_SH_SHAMT)
++#define MATCH_SHAMT_ZIP4_W_64  (0b01100 << OP_SH_SHAMT)
++#define MATCH_SHAMT_ZIP8_32    (0b1000 << OP_SH_SHAMT)
++#define MATCH_SHAMT_ZIP8_64    (0b11000 << OP_SH_SHAMT)
++#define MATCH_SHAMT_ZIP8_W_64  (0b01000 << OP_SH_SHAMT)
++#define MATCH_SHAMT_ZIP16_64   (0b10000 << OP_SH_SHAMT)
++#define MATCH_SHAMT_UNZIP_32     (0b1111 << OP_SH_SHAMT)
++#define MATCH_SHAMT_UNZIP_64     (0b11111 << OP_SH_SHAMT)
++#define MATCH_SHAMT_UNZIP_N_32   (0b0001 << OP_SH_SHAMT)
++#define MATCH_SHAMT_UNZIP_N_64   (0b00001 << OP_SH_SHAMT)
++#define MATCH_SHAMT_UNZIP_B_32   (0b0011 << OP_SH_SHAMT)
++#define MATCH_SHAMT_UNZIP_B_64   (0b00011 << OP_SH_SHAMT)
++#define MATCH_SHAMT_UNZIP_H_32   (0b0111 << OP_SH_SHAMT)
++#define MATCH_SHAMT_UNZIP_H_64   (0b00111 << OP_SH_SHAMT)
++#define MATCH_SHAMT_UNZIP_W_64   (0b01111 << OP_SH_SHAMT)
++#define MATCH_SHAMT_UNZIP2_32    (0b1110 << OP_SH_SHAMT)
++#define MATCH_SHAMT_UNZIP2_64    (0b11110 << OP_SH_SHAMT)
++#define MATCH_SHAMT_UNZIP2_B_32  (0b0010 << OP_SH_SHAMT)
++#define MATCH_SHAMT_UNZIP2_B_64  (0b00010 << OP_SH_SHAMT)
++#define MATCH_SHAMT_UNZIP2_H_32  (0b0110 << OP_SH_SHAMT)
++#define MATCH_SHAMT_UNZIP2_H_64  (0b00110 << OP_SH_SHAMT)
++#define MATCH_SHAMT_UNZIP2_W_64  (0b01110 << OP_SH_SHAMT)
++#define MATCH_SHAMT_UNZIP4_32    (0b1100 << OP_SH_SHAMT)
++#define MATCH_SHAMT_UNZIP4_64    (0b11100 << OP_SH_SHAMT)
++#define MATCH_SHAMT_UNZIP4_H_32  (0b0100 << OP_SH_SHAMT)
++#define MATCH_SHAMT_UNZIP4_H_64  (0b00100 << OP_SH_SHAMT)
++#define MATCH_SHAMT_UNZIP4_W_64  (0b01100 << OP_SH_SHAMT)
++#define MATCH_SHAMT_UNZIP8_32    (0b1000 << OP_SH_SHAMT)
++#define MATCH_SHAMT_UNZIP8_64    (0b11000 << OP_SH_SHAMT)
++#define MATCH_SHAMT_UNZIP8_W_64  (0b01000 << OP_SH_SHAMT)
++#define MATCH_SHAMT_UNZIP16_64   (0b10000 << OP_SH_SHAMT)
+ #define MATCH_SHAMT_ORC_32     (0b11111 << OP_SH_SHAMT)
+ #define MATCH_SHAMT_ORC_64     (0b111111 << OP_SH_SHAMT)
+ #define MATCH_SHAMT_ORC_P_32   (0b00001 << OP_SH_SHAMT)
+@@ -1362,56 +1363,56 @@ const struct riscv_opcode riscv_opcodes[] =
+ {"rev16",     64, INSN_CLASS_ZBP,  "d,s",      MATCH_GREVI|MATCH_SHAMT_REV16_64, MASK_GREVI|MASK_SHAMT, match_opcode, 0 },
+ {"rev16.w",   64, INSN_CLASS_ZBP,  "d,s",      MATCH_GREVI|MATCH_SHAMT_REV16_W_64, MASK_GREVI|MASK_SHAMT, match_opcode, 0 },
+ {"rev32",     64, INSN_CLASS_ZBP,  "d,s",      MATCH_GREVI|MATCH_SHAMT_REV32_64, MASK_GREVI|MASK_SHAMT, match_opcode, 0 },
+-{"zip",       32, INSN_CLASS_ZBP,  "d,s",      MATCH_SHFLI|MATCH_SHAMT_ZIP_32, MASK_SHFLI|MASK_SHAMT, match_opcode, 0 },
+-{"zip",       64, INSN_CLASS_ZBP,  "d,s",      MATCH_SHFLI|MATCH_SHAMT_ZIP_64, MASK_SHFLI|MASK_SHAMT, match_opcode, 0 },
+-{"zip.n",     32, INSN_CLASS_ZBP,  "d,s",      MATCH_SHFLI|MATCH_SHAMT_ZIP_N_32, MASK_SHFLI|MASK_SHAMT, match_opcode, 0 },
+-{"zip.n",     64, INSN_CLASS_ZBP,  "d,s",      MATCH_SHFLI|MATCH_SHAMT_ZIP_N_64, MASK_SHFLI|MASK_SHAMT, match_opcode, 0 },
+-{"zip.b",     32, INSN_CLASS_ZBP,  "d,s",      MATCH_SHFLI|MATCH_SHAMT_ZIP_B_32, MASK_SHFLI|MASK_SHAMT, match_opcode, 0 },
+-{"zip.b",     64, INSN_CLASS_ZBP,  "d,s",      MATCH_SHFLI|MATCH_SHAMT_ZIP_B_64, MASK_SHFLI|MASK_SHAMT, match_opcode, 0 },
+-{"zip.h",     32, INSN_CLASS_ZBP,  "d,s",      MATCH_SHFLI|MATCH_SHAMT_ZIP_H_32, MASK_SHFLI|MASK_SHAMT, match_opcode, 0 },
+-{"zip.h",     64, INSN_CLASS_ZBP,  "d,s",      MATCH_SHFLI|MATCH_SHAMT_ZIP_H_64, MASK_SHFLI|MASK_SHAMT, match_opcode, 0 },
+-{"zip.w",     64, INSN_CLASS_ZBP,  "d,s",      MATCH_SHFLI|MATCH_SHAMT_ZIP_W_64, MASK_SHFLI|MASK_SHAMT, match_opcode, 0 },
+-{"zip2",      32, INSN_CLASS_ZBP,  "d,s",      MATCH_SHFLI|MATCH_SHAMT_ZIP2_32, MASK_SHFLI|MASK_SHAMT, match_opcode, 0 },
+-{"zip2",      64, INSN_CLASS_ZBP,  "d,s",      MATCH_SHFLI|MATCH_SHAMT_ZIP2_64, MASK_SHFLI|MASK_SHAMT, match_opcode, 0 },
+-{"zip2.b",    32, INSN_CLASS_ZBP,  "d,s",      MATCH_SHFLI|MATCH_SHAMT_ZIP2_B_32, MASK_SHFLI|MASK_SHAMT, match_opcode, 0 },
+-{"zip2.b",    64, INSN_CLASS_ZBP,  "d,s",      MATCH_SHFLI|MATCH_SHAMT_ZIP2_B_64, MASK_SHFLI|MASK_SHAMT, match_opcode, 0 },
+-{"zip2.h",    32, INSN_CLASS_ZBP,  "d,s",      MATCH_SHFLI|MATCH_SHAMT_ZIP2_H_32, MASK_SHFLI|MASK_SHAMT, match_opcode, 0 },
+-{"zip2.h",    64, INSN_CLASS_ZBP,  "d,s",      MATCH_SHFLI|MATCH_SHAMT_ZIP2_H_64, MASK_SHFLI|MASK_SHAMT, match_opcode, 0 },
+-{"zip2.w",    64, INSN_CLASS_ZBP,  "d,s",      MATCH_SHFLI|MATCH_SHAMT_ZIP2_W_64, MASK_SHFLI|MASK_SHAMT, match_opcode, 0 },
+-{"zip4",      32, INSN_CLASS_ZBP,  "d,s",      MATCH_SHFLI|MATCH_SHAMT_ZIP4_32, MASK_SHFLI|MASK_SHAMT, match_opcode, 0 },
+-{"zip4",      64, INSN_CLASS_ZBP,  "d,s",      MATCH_SHFLI|MATCH_SHAMT_ZIP4_64, MASK_SHFLI|MASK_SHAMT, match_opcode, 0 },
+-{"zip4.h",    32, INSN_CLASS_ZBP,  "d,s",      MATCH_SHFLI|MATCH_SHAMT_ZIP4_H_32, MASK_SHFLI|MASK_SHAMT, match_opcode, 0 },
+-{"zip4.h",    64, INSN_CLASS_ZBP,  "d,s",      MATCH_SHFLI|MATCH_SHAMT_ZIP4_H_64, MASK_SHFLI|MASK_SHAMT, match_opcode, 0 },
+-{"zip4.w",    64, INSN_CLASS_ZBP,  "d,s",      MATCH_SHFLI|MATCH_SHAMT_ZIP4_W_64, MASK_SHFLI|MASK_SHAMT, match_opcode, 0 },
+-{"zip8",      32, INSN_CLASS_ZBP,  "d,s",      MATCH_SHFLI|MATCH_SHAMT_ZIP8_32, MASK_SHFLI|MASK_SHAMT, match_opcode, 0 },
+-{"zip8",      64, INSN_CLASS_ZBP,  "d,s",      MATCH_SHFLI|MATCH_SHAMT_ZIP8_64, MASK_SHFLI|MASK_SHAMT, match_opcode, 0 },
+-{"zip8.w",    64, INSN_CLASS_ZBP,  "d,s",      MATCH_SHFLI|MATCH_SHAMT_ZIP8_W_64, MASK_SHFLI|MASK_SHAMT, match_opcode, 0 },
+-{"zip16",     64, INSN_CLASS_ZBP,  "d,s",      MATCH_SHFLI|MATCH_SHAMT_ZIP16_64, MASK_SHFLI|MASK_SHAMT, match_opcode, 0 },
+-{"unzip",     32, INSN_CLASS_ZBP,  "d,s",      MATCH_UNSHFLI|MATCH_SHAMT_UNZIP_32, MASK_UNSHFLI|MASK_SHAMT, match_opcode, 0 },
+-{"unzip",     64, INSN_CLASS_ZBP,  "d,s",      MATCH_UNSHFLI|MATCH_SHAMT_UNZIP_64, MASK_UNSHFLI|MASK_SHAMT, match_opcode, 0 },
+-{"unzip.n",   32, INSN_CLASS_ZBP,  "d,s",      MATCH_UNSHFLI|MATCH_SHAMT_UNZIP_N_32, MASK_UNSHFLI|MASK_SHAMT, match_opcode, 0 },
+-{"unzip.n",   64, INSN_CLASS_ZBP,  "d,s",      MATCH_UNSHFLI|MATCH_SHAMT_UNZIP_N_64, MASK_UNSHFLI|MASK_SHAMT, match_opcode, 0 },
+-{"unzip.b",   32, INSN_CLASS_ZBP,  "d,s",      MATCH_UNSHFLI|MATCH_SHAMT_UNZIP_B_32, MASK_UNSHFLI|MASK_SHAMT, match_opcode, 0 },
+-{"unzip.b",   64, INSN_CLASS_ZBP,  "d,s",      MATCH_UNSHFLI|MATCH_SHAMT_UNZIP_B_64, MASK_UNSHFLI|MASK_SHAMT, match_opcode, 0 },
+-{"unzip.h",   32, INSN_CLASS_ZBP,  "d,s",      MATCH_UNSHFLI|MATCH_SHAMT_UNZIP_H_32, MASK_UNSHFLI|MASK_SHAMT, match_opcode, 0 },
+-{"unzip.h",   64, INSN_CLASS_ZBP,  "d,s",      MATCH_UNSHFLI|MATCH_SHAMT_UNZIP_H_64, MASK_UNSHFLI|MASK_SHAMT, match_opcode, 0 },
+-{"unzip.w",   64, INSN_CLASS_ZBP,  "d,s",      MATCH_UNSHFLI|MATCH_SHAMT_UNZIP_W_64, MASK_UNSHFLI|MASK_SHAMT, match_opcode, 0 },
+-{"unzip2",    32, INSN_CLASS_ZBP,  "d,s",      MATCH_UNSHFLI|MATCH_SHAMT_UNZIP2_32, MASK_UNSHFLI|MASK_SHAMT, match_opcode, 0 },
+-{"unzip2",    64, INSN_CLASS_ZBP,  "d,s",      MATCH_UNSHFLI|MATCH_SHAMT_UNZIP2_64, MASK_UNSHFLI|MASK_SHAMT, match_opcode, 0 },
+-{"unzip2.b",  32, INSN_CLASS_ZBP,  "d,s",      MATCH_UNSHFLI|MATCH_SHAMT_UNZIP2_B_32, MASK_UNSHFLI|MASK_SHAMT, match_opcode, 0 },
+-{"unzip2.b",  64, INSN_CLASS_ZBP,  "d,s",      MATCH_UNSHFLI|MATCH_SHAMT_UNZIP2_B_64, MASK_UNSHFLI|MASK_SHAMT, match_opcode, 0 },
+-{"unzip2.h",  32, INSN_CLASS_ZBP,  "d,s",      MATCH_UNSHFLI|MATCH_SHAMT_UNZIP2_H_32, MASK_UNSHFLI|MASK_SHAMT, match_opcode, 0 },
+-{"unzip2.h",  64, INSN_CLASS_ZBP,  "d,s",      MATCH_UNSHFLI|MATCH_SHAMT_UNZIP2_H_64, MASK_UNSHFLI|MASK_SHAMT, match_opcode, 0 },
+-{"unzip2.w",  64, INSN_CLASS_ZBP,  "d,s",      MATCH_UNSHFLI|MATCH_SHAMT_UNZIP2_W_64, MASK_UNSHFLI|MASK_SHAMT, match_opcode, 0 },
+-{"unzip4",    32, INSN_CLASS_ZBP,  "d,s",      MATCH_UNSHFLI|MATCH_SHAMT_UNZIP4_32, MASK_UNSHFLI|MASK_SHAMT, match_opcode, 0 },
+-{"unzip4",    64, INSN_CLASS_ZBP,  "d,s",      MATCH_UNSHFLI|MATCH_SHAMT_UNZIP4_64, MASK_UNSHFLI|MASK_SHAMT, match_opcode, 0 },
+-{"unzip4.h",  32, INSN_CLASS_ZBP,  "d,s",      MATCH_UNSHFLI|MATCH_SHAMT_UNZIP4_H_32, MASK_UNSHFLI|MASK_SHAMT, match_opcode, 0 },
+-{"unzip4.h",  64, INSN_CLASS_ZBP,  "d,s",      MATCH_UNSHFLI|MATCH_SHAMT_UNZIP4_H_64, MASK_UNSHFLI|MASK_SHAMT, match_opcode, 0 },
+-{"unzip4.w",  64, INSN_CLASS_ZBP,  "d,s",      MATCH_UNSHFLI|MATCH_SHAMT_UNZIP4_W_64, MASK_UNSHFLI|MASK_SHAMT, match_opcode, 0 },
+-{"unzip8",    32, INSN_CLASS_ZBP,  "d,s",      MATCH_UNSHFLI|MATCH_SHAMT_UNZIP8_32, MASK_UNSHFLI|MASK_SHAMT, match_opcode, 0 },
+-{"unzip8",    64, INSN_CLASS_ZBP,  "d,s",      MATCH_UNSHFLI|MATCH_SHAMT_UNZIP8_64, MASK_UNSHFLI|MASK_SHAMT, match_opcode, 0 },
+-{"unzip8.w",  64, INSN_CLASS_ZBP,  "d,s",      MATCH_UNSHFLI|MATCH_SHAMT_UNZIP8_W_64, MASK_UNSHFLI|MASK_SHAMT, match_opcode, 0 },
+-{"unzip16",   64, INSN_CLASS_ZBP,  "d,s",      MATCH_UNSHFLI|MATCH_SHAMT_UNZIP16_64, MASK_UNSHFLI|MASK_SHAMT, match_opcode, 0 },
++{"zip",       32, INSN_CLASS_ZBP,  "d,s",      MATCH_SHFLI|MATCH_SHAMT_ZIP_32, MASK_SHFLI|MASK_SHAMT2, match_opcode, 0 },
++{"zip",       64, INSN_CLASS_ZBP,  "d,s",      MATCH_SHFLI|MATCH_SHAMT_ZIP_64, MASK_SHFLI|MASK_SHAMT2, match_opcode, 0 },
++{"zip.n",     32, INSN_CLASS_ZBP,  "d,s",      MATCH_SHFLI|MATCH_SHAMT_ZIP_N_32, MASK_SHFLI|MASK_SHAMT2, match_opcode, 0 },
++{"zip.n",     64, INSN_CLASS_ZBP,  "d,s",      MATCH_SHFLI|MATCH_SHAMT_ZIP_N_64, MASK_SHFLI|MASK_SHAMT2, match_opcode, 0 },
++{"zip.b",     32, INSN_CLASS_ZBP,  "d,s",      MATCH_SHFLI|MATCH_SHAMT_ZIP_B_32, MASK_SHFLI|MASK_SHAMT2, match_opcode, 0 },
++{"zip.b",     64, INSN_CLASS_ZBP,  "d,s",      MATCH_SHFLI|MATCH_SHAMT_ZIP_B_64, MASK_SHFLI|MASK_SHAMT2, match_opcode, 0 },
++{"zip.h",     32, INSN_CLASS_ZBP,  "d,s",      MATCH_SHFLI|MATCH_SHAMT_ZIP_H_32, MASK_SHFLI|MASK_SHAMT2, match_opcode, 0 },
++{"zip.h",     64, INSN_CLASS_ZBP,  "d,s",      MATCH_SHFLI|MATCH_SHAMT_ZIP_H_64, MASK_SHFLI|MASK_SHAMT2, match_opcode, 0 },
++{"zip.w",     64, INSN_CLASS_ZBP,  "d,s",      MATCH_SHFLI|MATCH_SHAMT_ZIP_W_64, MASK_SHFLI|MASK_SHAMT2, match_opcode, 0 },
++{"zip2",      32, INSN_CLASS_ZBP,  "d,s",      MATCH_SHFLI|MATCH_SHAMT_ZIP2_32, MASK_SHFLI|MASK_SHAMT2, match_opcode, 0 },
++{"zip2",      64, INSN_CLASS_ZBP,  "d,s",      MATCH_SHFLI|MATCH_SHAMT_ZIP2_64, MASK_SHFLI|MASK_SHAMT2, match_opcode, 0 },
++{"zip2.b",    32, INSN_CLASS_ZBP,  "d,s",      MATCH_SHFLI|MATCH_SHAMT_ZIP2_B_32, MASK_SHFLI|MASK_SHAMT2, match_opcode, 0 },
++{"zip2.b",    64, INSN_CLASS_ZBP,  "d,s",      MATCH_SHFLI|MATCH_SHAMT_ZIP2_B_64, MASK_SHFLI|MASK_SHAMT2, match_opcode, 0 },
++{"zip2.h",    32, INSN_CLASS_ZBP,  "d,s",      MATCH_SHFLI|MATCH_SHAMT_ZIP2_H_32, MASK_SHFLI|MASK_SHAMT2, match_opcode, 0 },
++{"zip2.h",    64, INSN_CLASS_ZBP,  "d,s",      MATCH_SHFLI|MATCH_SHAMT_ZIP2_H_64, MASK_SHFLI|MASK_SHAMT2, match_opcode, 0 },
++{"zip2.w",    64, INSN_CLASS_ZBP,  "d,s",      MATCH_SHFLI|MATCH_SHAMT_ZIP2_W_64, MASK_SHFLI|MASK_SHAMT2, match_opcode, 0 },
++{"zip4",      32, INSN_CLASS_ZBP,  "d,s",      MATCH_SHFLI|MATCH_SHAMT_ZIP4_32, MASK_SHFLI|MASK_SHAMT2, match_opcode, 0 },
++{"zip4",      64, INSN_CLASS_ZBP,  "d,s",      MATCH_SHFLI|MATCH_SHAMT_ZIP4_64, MASK_SHFLI|MASK_SHAMT2, match_opcode, 0 },
++{"zip4.h",    32, INSN_CLASS_ZBP,  "d,s",      MATCH_SHFLI|MATCH_SHAMT_ZIP4_H_32, MASK_SHFLI|MASK_SHAMT2, match_opcode, 0 },
++{"zip4.h",    64, INSN_CLASS_ZBP,  "d,s",      MATCH_SHFLI|MATCH_SHAMT_ZIP4_H_64, MASK_SHFLI|MASK_SHAMT2, match_opcode, 0 },
++{"zip4.w",    64, INSN_CLASS_ZBP,  "d,s",      MATCH_SHFLI|MATCH_SHAMT_ZIP4_W_64, MASK_SHFLI|MASK_SHAMT2, match_opcode, 0 },
++{"zip8",      32, INSN_CLASS_ZBP,  "d,s",      MATCH_SHFLI|MATCH_SHAMT_ZIP8_32, MASK_SHFLI|MASK_SHAMT2, match_opcode, 0 },
++{"zip8",      64, INSN_CLASS_ZBP,  "d,s",      MATCH_SHFLI|MATCH_SHAMT_ZIP8_64, MASK_SHFLI|MASK_SHAMT2, match_opcode, 0 },
++{"zip8.w",    64, INSN_CLASS_ZBP,  "d,s",      MATCH_SHFLI|MATCH_SHAMT_ZIP8_W_64, MASK_SHFLI|MASK_SHAMT2, match_opcode, 0 },
++{"zip16",     64, INSN_CLASS_ZBP,  "d,s",      MATCH_SHFLI|MATCH_SHAMT_ZIP16_64, MASK_SHFLI|MASK_SHAMT2, match_opcode, 0 },
++{"unzip",     32, INSN_CLASS_ZBP,  "d,s",      MATCH_UNSHFLI|MATCH_SHAMT_UNZIP_32, MASK_UNSHFLI|MASK_SHAMT2, match_opcode, 0 },
++{"unzip",     64, INSN_CLASS_ZBP,  "d,s",      MATCH_UNSHFLI|MATCH_SHAMT_UNZIP_64, MASK_UNSHFLI|MASK_SHAMT2, match_opcode, 0 },
++{"unzip.n",   32, INSN_CLASS_ZBP,  "d,s",      MATCH_UNSHFLI|MATCH_SHAMT_UNZIP_N_32, MASK_UNSHFLI|MASK_SHAMT2, match_opcode, 0 },
++{"unzip.n",   64, INSN_CLASS_ZBP,  "d,s",      MATCH_UNSHFLI|MATCH_SHAMT_UNZIP_N_64, MASK_UNSHFLI|MASK_SHAMT2, match_opcode, 0 },
++{"unzip.b",   32, INSN_CLASS_ZBP,  "d,s",      MATCH_UNSHFLI|MATCH_SHAMT_UNZIP_B_32, MASK_UNSHFLI|MASK_SHAMT2, match_opcode, 0 },
++{"unzip.b",   64, INSN_CLASS_ZBP,  "d,s",      MATCH_UNSHFLI|MATCH_SHAMT_UNZIP_B_64, MASK_UNSHFLI|MASK_SHAMT2, match_opcode, 0 },
++{"unzip.h",   32, INSN_CLASS_ZBP,  "d,s",      MATCH_UNSHFLI|MATCH_SHAMT_UNZIP_H_32, MASK_UNSHFLI|MASK_SHAMT2, match_opcode, 0 },
++{"unzip.h",   64, INSN_CLASS_ZBP,  "d,s",      MATCH_UNSHFLI|MATCH_SHAMT_UNZIP_H_64, MASK_UNSHFLI|MASK_SHAMT2, match_opcode, 0 },
++{"unzip.w",   64, INSN_CLASS_ZBP,  "d,s",      MATCH_UNSHFLI|MATCH_SHAMT_UNZIP_W_64, MASK_UNSHFLI|MASK_SHAMT2, match_opcode, 0 },
++{"unzip2",    32, INSN_CLASS_ZBP,  "d,s",      MATCH_UNSHFLI|MATCH_SHAMT_UNZIP2_32, MASK_UNSHFLI|MASK_SHAMT2, match_opcode, 0 },
++{"unzip2",    64, INSN_CLASS_ZBP,  "d,s",      MATCH_UNSHFLI|MATCH_SHAMT_UNZIP2_64, MASK_UNSHFLI|MASK_SHAMT2, match_opcode, 0 },
++{"unzip2.b",  32, INSN_CLASS_ZBP,  "d,s",      MATCH_UNSHFLI|MATCH_SHAMT_UNZIP2_B_32, MASK_UNSHFLI|MASK_SHAMT2, match_opcode, 0 },
++{"unzip2.b",  64, INSN_CLASS_ZBP,  "d,s",      MATCH_UNSHFLI|MATCH_SHAMT_UNZIP2_B_64, MASK_UNSHFLI|MASK_SHAMT2, match_opcode, 0 },
++{"unzip2.h",  32, INSN_CLASS_ZBP,  "d,s",      MATCH_UNSHFLI|MATCH_SHAMT_UNZIP2_H_32, MASK_UNSHFLI|MASK_SHAMT2, match_opcode, 0 },
++{"unzip2.h",  64, INSN_CLASS_ZBP,  "d,s",      MATCH_UNSHFLI|MATCH_SHAMT_UNZIP2_H_64, MASK_UNSHFLI|MASK_SHAMT2, match_opcode, 0 },
++{"unzip2.w",  64, INSN_CLASS_ZBP,  "d,s",      MATCH_UNSHFLI|MATCH_SHAMT_UNZIP2_W_64, MASK_UNSHFLI|MASK_SHAMT2, match_opcode, 0 },
++{"unzip4",    32, INSN_CLASS_ZBP,  "d,s",      MATCH_UNSHFLI|MATCH_SHAMT_UNZIP4_32, MASK_UNSHFLI|MASK_SHAMT2, match_opcode, 0 },
++{"unzip4",    64, INSN_CLASS_ZBP,  "d,s",      MATCH_UNSHFLI|MATCH_SHAMT_UNZIP4_64, MASK_UNSHFLI|MASK_SHAMT2, match_opcode, 0 },
++{"unzip4.h",  32, INSN_CLASS_ZBP,  "d,s",      MATCH_UNSHFLI|MATCH_SHAMT_UNZIP4_H_32, MASK_UNSHFLI|MASK_SHAMT2, match_opcode, 0 },
++{"unzip4.h",  64, INSN_CLASS_ZBP,  "d,s",      MATCH_UNSHFLI|MATCH_SHAMT_UNZIP4_H_64, MASK_UNSHFLI|MASK_SHAMT2, match_opcode, 0 },
++{"unzip4.w",  64, INSN_CLASS_ZBP,  "d,s",      MATCH_UNSHFLI|MATCH_SHAMT_UNZIP4_W_64, MASK_UNSHFLI|MASK_SHAMT2, match_opcode, 0 },
++{"unzip8",    32, INSN_CLASS_ZBP,  "d,s",      MATCH_UNSHFLI|MATCH_SHAMT_UNZIP8_32, MASK_UNSHFLI|MASK_SHAMT2, match_opcode, 0 },
++{"unzip8",    64, INSN_CLASS_ZBP,  "d,s",      MATCH_UNSHFLI|MATCH_SHAMT_UNZIP8_64, MASK_UNSHFLI|MASK_SHAMT2, match_opcode, 0 },
++{"unzip8.w",  64, INSN_CLASS_ZBP,  "d,s",      MATCH_UNSHFLI|MATCH_SHAMT_UNZIP8_W_64, MASK_UNSHFLI|MASK_SHAMT2, match_opcode, 0 },
++{"unzip16",   64, INSN_CLASS_ZBP,  "d,s",      MATCH_UNSHFLI|MATCH_SHAMT_UNZIP16_64, MASK_UNSHFLI|MASK_SHAMT2, match_opcode, 0 },
+ {"orc",       32, INSN_CLASS_ZBP,  "d,s",      MATCH_GORCI|MATCH_SHAMT_ORC_32, MASK_GORCI|MASK_SHAMT, match_opcode, 0 },
+ {"orc",       64, INSN_CLASS_ZBP,  "d,s",      MATCH_GORCI|MATCH_SHAMT_ORC_64, MASK_GORCI|MASK_SHAMT, match_opcode, 0 },
+ {"orc.p",     32, INSN_CLASS_ZBP,  "d,s",      MATCH_GORCI|MATCH_SHAMT_ORC_P_32, MASK_GORCI|MASK_SHAMT, match_opcode, 0 },
+-- 
+2.33.0
+

+ 45 - 0
recipes-devtools/binutils/binutils/0012-update-bitmap-version-number-from-0.93-to-0.94.patch

@@ -0,0 +1,45 @@
+From cc69150cd40ddd6be172341cd9d19960b99e63db Mon Sep 17 00:00:00 2001
+From: LevyHsu <admin@levyhsu.com>
+Date: Thu, 17 Jun 2021 13:57:47 +0800
+Subject: [PATCH 12/28] update bitmap version number from 0.93 to 0.94
+
+---
+ opcodes/riscv-opc.c | 22 +++++++++++-----------
+ 1 file changed, 11 insertions(+), 11 deletions(-)
+
+diff --git a/opcodes/riscv-opc.c b/opcodes/riscv-opc.c
+index a01a5c9202..230bbdf11e 100644
+--- a/opcodes/riscv-opc.c
++++ b/opcodes/riscv-opc.c
+@@ -1980,17 +1980,17 @@ const struct riscv_ext_version riscv_ext_version_table[] =
+ 
+ {"zihintpause", ISA_SPEC_CLASS_DRAFT, 1, 0},
+ 
+-{"b",     ISA_SPEC_CLASS_DRAFT, 0, 93},
+-{"zbb",   ISA_SPEC_CLASS_DRAFT, 0, 93},
+-{"zba",   ISA_SPEC_CLASS_DRAFT, 0, 93},
+-{"zbc",   ISA_SPEC_CLASS_DRAFT, 0, 93},
+-{"zbe",   ISA_SPEC_CLASS_DRAFT, 0, 93},
+-{"zbf",   ISA_SPEC_CLASS_DRAFT, 0, 93},
+-{"zbm",   ISA_SPEC_CLASS_DRAFT, 0, 93},
+-{"zbp",   ISA_SPEC_CLASS_DRAFT, 0, 93},
+-{"zbr",   ISA_SPEC_CLASS_DRAFT, 0, 93},
+-{"zbs",   ISA_SPEC_CLASS_DRAFT, 0, 93},
+-{"zbt",   ISA_SPEC_CLASS_DRAFT, 0, 93},
++{"b",     ISA_SPEC_CLASS_DRAFT, 0, 94},
++{"zbb",   ISA_SPEC_CLASS_DRAFT, 0, 94},
++{"zba",   ISA_SPEC_CLASS_DRAFT, 0, 94},
++{"zbc",   ISA_SPEC_CLASS_DRAFT, 0, 94},
++{"zbe",   ISA_SPEC_CLASS_DRAFT, 0, 94},
++{"zbf",   ISA_SPEC_CLASS_DRAFT, 0, 94},
++{"zbm",   ISA_SPEC_CLASS_DRAFT, 0, 94},
++{"zbp",   ISA_SPEC_CLASS_DRAFT, 0, 94},
++{"zbr",   ISA_SPEC_CLASS_DRAFT, 0, 94},
++{"zbs",   ISA_SPEC_CLASS_DRAFT, 0, 94},
++{"zbt",   ISA_SPEC_CLASS_DRAFT, 0, 94},
+ 
+ {"zvamo",   ISA_SPEC_CLASS_NONE, 1, 0},
+ {"zvlsseg", ISA_SPEC_CLASS_NONE, 1, 0},
+-- 
+2.33.0
+

+ 93 - 0
recipes-devtools/binutils/binutils/0013-Fix-gas-test-cases.patch

@@ -0,0 +1,93 @@
+From aba02c462271b8d844aeea6906cadeb810ad9407 Mon Sep 17 00:00:00 2001
+From: LevyHsu <admin@levyhsu.com>
+Date: Tue, 22 Jun 2021 14:58:23 +0800
+Subject: [PATCH 13/28] Fix gas test cases
+
+---
+ gas/testsuite/gas/riscv/b-ext-64.d | 8 ++++----
+ gas/testsuite/gas/riscv/b-ext-64.s | 4 ++--
+ gas/testsuite/gas/riscv/b-ext.d    | 2 +-
+ gas/testsuite/gas/riscv/b-ext.s    | 2 +-
+ 4 files changed, 8 insertions(+), 8 deletions(-)
+
+diff --git a/gas/testsuite/gas/riscv/b-ext-64.d b/gas/testsuite/gas/riscv/b-ext-64.d
+index 23da2e0d58..8a1daf2766 100755
+--- a/gas/testsuite/gas/riscv/b-ext-64.d
++++ b/gas/testsuite/gas/riscv/b-ext-64.d
+@@ -73,7 +73,7 @@ Disassembly of section .text:
+ [ 	]+f8:[ 	]+48c59533[ 	]+bclr[ 	]+a0,a1,a2
+ [ 	]+fc:[ 	]+68c59533[ 	]+binv[ 	]+a0,a1,a2
+ [ 	]+100:[ 	]+48c5d533[ 	]+bext[ 	]+a0,a1,a2
+-[ 	]+104:[ 	]+48c5e533[ 	]+bdep[ 	]+a0,a1,a2
++[ 	]+104:[ 	]+48c5e533[ 	]+bdecompress[ 	]+a0,a1,a2
+ [ 	]+108:[ 	]+28259513[ 	]+bseti[ 	]+a0,a1,0x2
+ [ 	]+10c:[ 	]+48259513[ 	]+bclri[ 	]+a0,a1,0x2
+ [ 	]+110:[ 	]+68259513[ 	]+binvi[ 	]+a0,a1,0x2
+@@ -82,7 +82,7 @@ Disassembly of section .text:
+ [ 	]+11c:[ 	]+48c5953b[ 	]+bclrw[ 	]+a0,a1,a2
+ [ 	]+120:[ 	]+68c5953b[ 	]+binvw[ 	]+a0,a1,a2
+ [ 	]+124:[ 	]+48c5d53b[ 	]+bextw[ 	]+a0,a1,a2
+-[ 	]+128:[ 	]+4825e53b[ 	]+bdepw[ 	]+a0,a1,0x2
++[ 	]+128:[ 	]+4825e53b[ 	]+bdecompressw[ 	]+a0,a1,0x2
+ [ 	]+12c:[ 	]+2825951b[ 	]+bsetiw[ 	]+a0,a1,0x2
+ [ 	]+130:[ 	]+4825951b[ 	]+bclriw[ 	]+a0,a1,0x2
+ [ 	]+134:[ 	]+6825951b[ 	]+binviw[ 	]+a0,a1,0x2
+@@ -113,5 +113,5 @@ Disassembly of section .text:
+ [ 	]+198:[ 	]+6cc5d533[ 	]+fsr[ 	]+a0,a1,a2,a3
+ [ 	]+19c:[ 	]+6c25d513[ 	]+fsri[ 	]+a0,a1,0x2,a3
+ [ 	]+1a0:[ 	]+6c25953b[ 	]+fslw[ 	]+a0,a1,0x2,a3
+-[ 	]+1a4:[ 	]+6c25b53b[ 	]+fsrw[ 	]+a0,a1,0x2,a3
+-[ 	]+1a8:[ 	]+6c25b51b[ 	]+fsriw[ 	]+a0,a1,0x2,a3
++[ 	]+1a4:[ 	]+6c25d53b[ 	]+fsrw[ 	]+a0,a1,0x2,a3
++[ 	]+1a8:[ 	]+6c25d51b[ 	]+fsriw[ 	]+a0,a1,0x2,a3
+diff --git a/gas/testsuite/gas/riscv/b-ext-64.s b/gas/testsuite/gas/riscv/b-ext-64.s
+index 176d617be5..945ce167dd 100755
+--- a/gas/testsuite/gas/riscv/b-ext-64.s
++++ b/gas/testsuite/gas/riscv/b-ext-64.s
+@@ -64,7 +64,7 @@ target:
+ 	bclr	a0, a1, a2
+ 	binv	a0, a1, a2
+ 	bext	a0, a1, a2
+-	bdep	a0, a1, a2
++	bdecompress	a0, a1, a2
+ 	bseti	a0, a1, 2
+ 	bclri	a0, a1, 2
+ 	binvi	a0, a1, 2
+@@ -73,7 +73,7 @@ target:
+ 	bclrw	a0, a1, a2
+ 	binvw	a0, a1, a2
+ 	bextw	a0, a1, a2
+-	bdepw	a0, a1, 2
++	bdecompressw	a0, a1, 2
+ 	bsetiw	a0, a1, 2
+ 	bclriw	a0, a1, 2
+ 	binviw	a0, a1, 2
+diff --git a/gas/testsuite/gas/riscv/b-ext.d b/gas/testsuite/gas/riscv/b-ext.d
+index 4df9e90693..82c22b3cdf 100755
+--- a/gas/testsuite/gas/riscv/b-ext.d
++++ b/gas/testsuite/gas/riscv/b-ext.d
+@@ -51,7 +51,7 @@ Disassembly of section .text:
+ [ 	]+a0:[ 	]+48c59533[ 	]+bclr[ 	]+a0,a1,a2
+ [ 	]+a4:[ 	]+68c59533[ 	]+binv[ 	]+a0,a1,a2
+ [ 	]+a8:[ 	]+48c5d533[ 	]+bext[ 	]+a0,a1,a2
+-[ 	]+ac:[ 	]+48c5e533[ 	]+bdep[ 	]+a0,a1,a2
++[ 	]+ac:[ 	]+48c5e533[ 	]+bdecompress[ 	]+a0,a1,a2
+ [ 	]+b0:[ 	]+28259513[ 	]+bseti[ 	]+a0,a1,0x2
+ [ 	]+b4:[ 	]+48259513[ 	]+bclri[ 	]+a0,a1,0x2
+ [ 	]+b8:[ 	]+68259513[ 	]+binvi[ 	]+a0,a1,0x2
+diff --git a/gas/testsuite/gas/riscv/b-ext.s b/gas/testsuite/gas/riscv/b-ext.s
+index 429c005849..e41223b627 100755
+--- a/gas/testsuite/gas/riscv/b-ext.s
++++ b/gas/testsuite/gas/riscv/b-ext.s
+@@ -42,7 +42,7 @@ target:
+ 	bclr	 a0, a1, a2
+ 	binv	 a0, a1, a2
+ 	bext	 a0, a1, a2
+-	bdep	 a0, a1, a2
++	bdecompress	 a0, a1, a2
+ 	bseti	 a0, a1, 2
+ 	bclri	 a0, a1, 2
+ 	binvi	 a0, a1, 2
+-- 
+2.33.0
+

+ 36 - 0
recipes-devtools/binutils/binutils/0014-resolve-crash-issue-when-objdump-encounter-unrecogni.patch

@@ -0,0 +1,36 @@
+From 86c531ca0575841766e539f556436275ec782fe7 Mon Sep 17 00:00:00 2001
+From: "max.ma" <max.ma@starfivetech.com>
+Date: Tue, 22 Jun 2021 00:40:19 -0700
+Subject: [PATCH 14/28] resolve crash issue when objdump encounter unrecognized
+ v instruction
+
+---
+ opcodes/riscv-opc.c | 12 ++++++------
+ 1 file changed, 6 insertions(+), 6 deletions(-)
+
+diff --git a/opcodes/riscv-opc.c b/opcodes/riscv-opc.c
+index 230bbdf11e..13ed6500ac 100644
+--- a/opcodes/riscv-opc.c
++++ b/opcodes/riscv-opc.c
+@@ -553,12 +553,12 @@ match_vd_neq_vs1_neq_vs2_neq_vm (const struct riscv_opcode *op,
+   if (!constraints || error == NULL)
+     return match_opcode (op, insn);
+ 
+-  if (vs1 == vd)
+-    *error = "illegal operands vd cannot overlap vs1";
+-  else if (vs2 == vd)
+-    *error = "illegal operands vd cannot overlap vs2";
+-  else if (!vm && vm == vd)
+-    *error = "illegal operands vd cannot overlap vm";
++  if (vs1 == vd) return 0;
++    //*error = "illegal operands vd cannot overlap vs1";
++  else if (vs2 == vd) return 0;
++    //*error = "illegal operands vd cannot overlap vs2";
++  else if (!vm && vm == vd) return 0;
++    //*error = "illegal operands vd cannot overlap vm";
+   else
+     return match_opcode (op, insn);
+   return 0;
+-- 
+2.33.0
+

+ 131 - 0
recipes-devtools/binutils/binutils/0015-Remove-MASK_SHAMT2.patch

@@ -0,0 +1,131 @@
+From 7260a0fb82b208485194d813e4e595419667e3c3 Mon Sep 17 00:00:00 2001
+From: LevyHsu <admin@levyhsu.com>
+Date: Tue, 22 Jun 2021 18:36:11 +0800
+Subject: [PATCH 15/28] Remove MASK_SHAMT2
+
+---
+ opcodes/riscv-opc.c | 101 ++++++++++++++++++++++----------------------
+ 1 file changed, 50 insertions(+), 51 deletions(-)
+
+diff --git a/opcodes/riscv-opc.c b/opcodes/riscv-opc.c
+index 13ed6500ac..067ebe3115 100644
+--- a/opcodes/riscv-opc.c
++++ b/opcodes/riscv-opc.c
+@@ -25,7 +25,6 @@
+ #include <stdio.h>
+ 
+ #define MASK_SHAMT (OP_MASK_SHAMT << OP_SH_SHAMT)
+-#define MASK_SHAMT2 (OP_MASK_RS2 << OP_SH_SHAMT)
+ #define MATCH_SHAMT_REV_32     (0b11111 << OP_SH_SHAMT)
+ #define MATCH_SHAMT_REV_64     (0b111111 << OP_SH_SHAMT)
+ #define MATCH_SHAMT_REV_P_32   (0b00001 << OP_SH_SHAMT)
+@@ -1363,56 +1362,56 @@ const struct riscv_opcode riscv_opcodes[] =
+ {"rev16",     64, INSN_CLASS_ZBP,  "d,s",      MATCH_GREVI|MATCH_SHAMT_REV16_64, MASK_GREVI|MASK_SHAMT, match_opcode, 0 },
+ {"rev16.w",   64, INSN_CLASS_ZBP,  "d,s",      MATCH_GREVI|MATCH_SHAMT_REV16_W_64, MASK_GREVI|MASK_SHAMT, match_opcode, 0 },
+ {"rev32",     64, INSN_CLASS_ZBP,  "d,s",      MATCH_GREVI|MATCH_SHAMT_REV32_64, MASK_GREVI|MASK_SHAMT, match_opcode, 0 },
+-{"zip",       32, INSN_CLASS_ZBP,  "d,s",      MATCH_SHFLI|MATCH_SHAMT_ZIP_32, MASK_SHFLI|MASK_SHAMT2, match_opcode, 0 },
+-{"zip",       64, INSN_CLASS_ZBP,  "d,s",      MATCH_SHFLI|MATCH_SHAMT_ZIP_64, MASK_SHFLI|MASK_SHAMT2, match_opcode, 0 },
+-{"zip.n",     32, INSN_CLASS_ZBP,  "d,s",      MATCH_SHFLI|MATCH_SHAMT_ZIP_N_32, MASK_SHFLI|MASK_SHAMT2, match_opcode, 0 },
+-{"zip.n",     64, INSN_CLASS_ZBP,  "d,s",      MATCH_SHFLI|MATCH_SHAMT_ZIP_N_64, MASK_SHFLI|MASK_SHAMT2, match_opcode, 0 },
+-{"zip.b",     32, INSN_CLASS_ZBP,  "d,s",      MATCH_SHFLI|MATCH_SHAMT_ZIP_B_32, MASK_SHFLI|MASK_SHAMT2, match_opcode, 0 },
+-{"zip.b",     64, INSN_CLASS_ZBP,  "d,s",      MATCH_SHFLI|MATCH_SHAMT_ZIP_B_64, MASK_SHFLI|MASK_SHAMT2, match_opcode, 0 },
+-{"zip.h",     32, INSN_CLASS_ZBP,  "d,s",      MATCH_SHFLI|MATCH_SHAMT_ZIP_H_32, MASK_SHFLI|MASK_SHAMT2, match_opcode, 0 },
+-{"zip.h",     64, INSN_CLASS_ZBP,  "d,s",      MATCH_SHFLI|MATCH_SHAMT_ZIP_H_64, MASK_SHFLI|MASK_SHAMT2, match_opcode, 0 },
+-{"zip.w",     64, INSN_CLASS_ZBP,  "d,s",      MATCH_SHFLI|MATCH_SHAMT_ZIP_W_64, MASK_SHFLI|MASK_SHAMT2, match_opcode, 0 },
+-{"zip2",      32, INSN_CLASS_ZBP,  "d,s",      MATCH_SHFLI|MATCH_SHAMT_ZIP2_32, MASK_SHFLI|MASK_SHAMT2, match_opcode, 0 },
+-{"zip2",      64, INSN_CLASS_ZBP,  "d,s",      MATCH_SHFLI|MATCH_SHAMT_ZIP2_64, MASK_SHFLI|MASK_SHAMT2, match_opcode, 0 },
+-{"zip2.b",    32, INSN_CLASS_ZBP,  "d,s",      MATCH_SHFLI|MATCH_SHAMT_ZIP2_B_32, MASK_SHFLI|MASK_SHAMT2, match_opcode, 0 },
+-{"zip2.b",    64, INSN_CLASS_ZBP,  "d,s",      MATCH_SHFLI|MATCH_SHAMT_ZIP2_B_64, MASK_SHFLI|MASK_SHAMT2, match_opcode, 0 },
+-{"zip2.h",    32, INSN_CLASS_ZBP,  "d,s",      MATCH_SHFLI|MATCH_SHAMT_ZIP2_H_32, MASK_SHFLI|MASK_SHAMT2, match_opcode, 0 },
+-{"zip2.h",    64, INSN_CLASS_ZBP,  "d,s",      MATCH_SHFLI|MATCH_SHAMT_ZIP2_H_64, MASK_SHFLI|MASK_SHAMT2, match_opcode, 0 },
+-{"zip2.w",    64, INSN_CLASS_ZBP,  "d,s",      MATCH_SHFLI|MATCH_SHAMT_ZIP2_W_64, MASK_SHFLI|MASK_SHAMT2, match_opcode, 0 },
+-{"zip4",      32, INSN_CLASS_ZBP,  "d,s",      MATCH_SHFLI|MATCH_SHAMT_ZIP4_32, MASK_SHFLI|MASK_SHAMT2, match_opcode, 0 },
+-{"zip4",      64, INSN_CLASS_ZBP,  "d,s",      MATCH_SHFLI|MATCH_SHAMT_ZIP4_64, MASK_SHFLI|MASK_SHAMT2, match_opcode, 0 },
+-{"zip4.h",    32, INSN_CLASS_ZBP,  "d,s",      MATCH_SHFLI|MATCH_SHAMT_ZIP4_H_32, MASK_SHFLI|MASK_SHAMT2, match_opcode, 0 },
+-{"zip4.h",    64, INSN_CLASS_ZBP,  "d,s",      MATCH_SHFLI|MATCH_SHAMT_ZIP4_H_64, MASK_SHFLI|MASK_SHAMT2, match_opcode, 0 },
+-{"zip4.w",    64, INSN_CLASS_ZBP,  "d,s",      MATCH_SHFLI|MATCH_SHAMT_ZIP4_W_64, MASK_SHFLI|MASK_SHAMT2, match_opcode, 0 },
+-{"zip8",      32, INSN_CLASS_ZBP,  "d,s",      MATCH_SHFLI|MATCH_SHAMT_ZIP8_32, MASK_SHFLI|MASK_SHAMT2, match_opcode, 0 },
+-{"zip8",      64, INSN_CLASS_ZBP,  "d,s",      MATCH_SHFLI|MATCH_SHAMT_ZIP8_64, MASK_SHFLI|MASK_SHAMT2, match_opcode, 0 },
+-{"zip8.w",    64, INSN_CLASS_ZBP,  "d,s",      MATCH_SHFLI|MATCH_SHAMT_ZIP8_W_64, MASK_SHFLI|MASK_SHAMT2, match_opcode, 0 },
+-{"zip16",     64, INSN_CLASS_ZBP,  "d,s",      MATCH_SHFLI|MATCH_SHAMT_ZIP16_64, MASK_SHFLI|MASK_SHAMT2, match_opcode, 0 },
+-{"unzip",     32, INSN_CLASS_ZBP,  "d,s",      MATCH_UNSHFLI|MATCH_SHAMT_UNZIP_32, MASK_UNSHFLI|MASK_SHAMT2, match_opcode, 0 },
+-{"unzip",     64, INSN_CLASS_ZBP,  "d,s",      MATCH_UNSHFLI|MATCH_SHAMT_UNZIP_64, MASK_UNSHFLI|MASK_SHAMT2, match_opcode, 0 },
+-{"unzip.n",   32, INSN_CLASS_ZBP,  "d,s",      MATCH_UNSHFLI|MATCH_SHAMT_UNZIP_N_32, MASK_UNSHFLI|MASK_SHAMT2, match_opcode, 0 },
+-{"unzip.n",   64, INSN_CLASS_ZBP,  "d,s",      MATCH_UNSHFLI|MATCH_SHAMT_UNZIP_N_64, MASK_UNSHFLI|MASK_SHAMT2, match_opcode, 0 },
+-{"unzip.b",   32, INSN_CLASS_ZBP,  "d,s",      MATCH_UNSHFLI|MATCH_SHAMT_UNZIP_B_32, MASK_UNSHFLI|MASK_SHAMT2, match_opcode, 0 },
+-{"unzip.b",   64, INSN_CLASS_ZBP,  "d,s",      MATCH_UNSHFLI|MATCH_SHAMT_UNZIP_B_64, MASK_UNSHFLI|MASK_SHAMT2, match_opcode, 0 },
+-{"unzip.h",   32, INSN_CLASS_ZBP,  "d,s",      MATCH_UNSHFLI|MATCH_SHAMT_UNZIP_H_32, MASK_UNSHFLI|MASK_SHAMT2, match_opcode, 0 },
+-{"unzip.h",   64, INSN_CLASS_ZBP,  "d,s",      MATCH_UNSHFLI|MATCH_SHAMT_UNZIP_H_64, MASK_UNSHFLI|MASK_SHAMT2, match_opcode, 0 },
+-{"unzip.w",   64, INSN_CLASS_ZBP,  "d,s",      MATCH_UNSHFLI|MATCH_SHAMT_UNZIP_W_64, MASK_UNSHFLI|MASK_SHAMT2, match_opcode, 0 },
+-{"unzip2",    32, INSN_CLASS_ZBP,  "d,s",      MATCH_UNSHFLI|MATCH_SHAMT_UNZIP2_32, MASK_UNSHFLI|MASK_SHAMT2, match_opcode, 0 },
+-{"unzip2",    64, INSN_CLASS_ZBP,  "d,s",      MATCH_UNSHFLI|MATCH_SHAMT_UNZIP2_64, MASK_UNSHFLI|MASK_SHAMT2, match_opcode, 0 },
+-{"unzip2.b",  32, INSN_CLASS_ZBP,  "d,s",      MATCH_UNSHFLI|MATCH_SHAMT_UNZIP2_B_32, MASK_UNSHFLI|MASK_SHAMT2, match_opcode, 0 },
+-{"unzip2.b",  64, INSN_CLASS_ZBP,  "d,s",      MATCH_UNSHFLI|MATCH_SHAMT_UNZIP2_B_64, MASK_UNSHFLI|MASK_SHAMT2, match_opcode, 0 },
+-{"unzip2.h",  32, INSN_CLASS_ZBP,  "d,s",      MATCH_UNSHFLI|MATCH_SHAMT_UNZIP2_H_32, MASK_UNSHFLI|MASK_SHAMT2, match_opcode, 0 },
+-{"unzip2.h",  64, INSN_CLASS_ZBP,  "d,s",      MATCH_UNSHFLI|MATCH_SHAMT_UNZIP2_H_64, MASK_UNSHFLI|MASK_SHAMT2, match_opcode, 0 },
+-{"unzip2.w",  64, INSN_CLASS_ZBP,  "d,s",      MATCH_UNSHFLI|MATCH_SHAMT_UNZIP2_W_64, MASK_UNSHFLI|MASK_SHAMT2, match_opcode, 0 },
+-{"unzip4",    32, INSN_CLASS_ZBP,  "d,s",      MATCH_UNSHFLI|MATCH_SHAMT_UNZIP4_32, MASK_UNSHFLI|MASK_SHAMT2, match_opcode, 0 },
+-{"unzip4",    64, INSN_CLASS_ZBP,  "d,s",      MATCH_UNSHFLI|MATCH_SHAMT_UNZIP4_64, MASK_UNSHFLI|MASK_SHAMT2, match_opcode, 0 },
+-{"unzip4.h",  32, INSN_CLASS_ZBP,  "d,s",      MATCH_UNSHFLI|MATCH_SHAMT_UNZIP4_H_32, MASK_UNSHFLI|MASK_SHAMT2, match_opcode, 0 },
+-{"unzip4.h",  64, INSN_CLASS_ZBP,  "d,s",      MATCH_UNSHFLI|MATCH_SHAMT_UNZIP4_H_64, MASK_UNSHFLI|MASK_SHAMT2, match_opcode, 0 },
+-{"unzip4.w",  64, INSN_CLASS_ZBP,  "d,s",      MATCH_UNSHFLI|MATCH_SHAMT_UNZIP4_W_64, MASK_UNSHFLI|MASK_SHAMT2, match_opcode, 0 },
+-{"unzip8",    32, INSN_CLASS_ZBP,  "d,s",      MATCH_UNSHFLI|MATCH_SHAMT_UNZIP8_32, MASK_UNSHFLI|MASK_SHAMT2, match_opcode, 0 },
+-{"unzip8",    64, INSN_CLASS_ZBP,  "d,s",      MATCH_UNSHFLI|MATCH_SHAMT_UNZIP8_64, MASK_UNSHFLI|MASK_SHAMT2, match_opcode, 0 },
+-{"unzip8.w",  64, INSN_CLASS_ZBP,  "d,s",      MATCH_UNSHFLI|MATCH_SHAMT_UNZIP8_W_64, MASK_UNSHFLI|MASK_SHAMT2, match_opcode, 0 },
+-{"unzip16",   64, INSN_CLASS_ZBP,  "d,s",      MATCH_UNSHFLI|MATCH_SHAMT_UNZIP16_64, MASK_UNSHFLI|MASK_SHAMT2, match_opcode, 0 },
++{"zip",       32, INSN_CLASS_ZBP,  "d,s",      MATCH_SHFLI|MATCH_SHAMT_ZIP_32, MASK_SHFLI|MASK_SHAMT, match_opcode, 0 },
++{"zip",       64, INSN_CLASS_ZBP,  "d,s",      MATCH_SHFLI|MATCH_SHAMT_ZIP_64, MASK_SHFLI|MASK_SHAMT, match_opcode, 0 },
++{"zip.n",     32, INSN_CLASS_ZBP,  "d,s",      MATCH_SHFLI|MATCH_SHAMT_ZIP_N_32, MASK_SHFLI|MASK_SHAMT, match_opcode, 0 },
++{"zip.n",     64, INSN_CLASS_ZBP,  "d,s",      MATCH_SHFLI|MATCH_SHAMT_ZIP_N_64, MASK_SHFLI|MASK_SHAMT, match_opcode, 0 },
++{"zip.b",     32, INSN_CLASS_ZBP,  "d,s",      MATCH_SHFLI|MATCH_SHAMT_ZIP_B_32, MASK_SHFLI|MASK_SHAMT, match_opcode, 0 },
++{"zip.b",     64, INSN_CLASS_ZBP,  "d,s",      MATCH_SHFLI|MATCH_SHAMT_ZIP_B_64, MASK_SHFLI|MASK_SHAMT, match_opcode, 0 },
++{"zip.h",     32, INSN_CLASS_ZBP,  "d,s",      MATCH_SHFLI|MATCH_SHAMT_ZIP_H_32, MASK_SHFLI|MASK_SHAMT, match_opcode, 0 },
++{"zip.h",     64, INSN_CLASS_ZBP,  "d,s",      MATCH_SHFLI|MATCH_SHAMT_ZIP_H_64, MASK_SHFLI|MASK_SHAMT, match_opcode, 0 },
++{"zip.w",     64, INSN_CLASS_ZBP,  "d,s",      MATCH_SHFLI|MATCH_SHAMT_ZIP_W_64, MASK_SHFLI|MASK_SHAMT, match_opcode, 0 },
++{"zip2",      32, INSN_CLASS_ZBP,  "d,s",      MATCH_SHFLI|MATCH_SHAMT_ZIP2_32, MASK_SHFLI|MASK_SHAMT, match_opcode, 0 },
++{"zip2",      64, INSN_CLASS_ZBP,  "d,s",      MATCH_SHFLI|MATCH_SHAMT_ZIP2_64, MASK_SHFLI|MASK_SHAMT, match_opcode, 0 },
++{"zip2.b",    32, INSN_CLASS_ZBP,  "d,s",      MATCH_SHFLI|MATCH_SHAMT_ZIP2_B_32, MASK_SHFLI|MASK_SHAMT, match_opcode, 0 },
++{"zip2.b",    64, INSN_CLASS_ZBP,  "d,s",      MATCH_SHFLI|MATCH_SHAMT_ZIP2_B_64, MASK_SHFLI|MASK_SHAMT, match_opcode, 0 },
++{"zip2.h",    32, INSN_CLASS_ZBP,  "d,s",      MATCH_SHFLI|MATCH_SHAMT_ZIP2_H_32, MASK_SHFLI|MASK_SHAMT, match_opcode, 0 },
++{"zip2.h",    64, INSN_CLASS_ZBP,  "d,s",      MATCH_SHFLI|MATCH_SHAMT_ZIP2_H_64, MASK_SHFLI|MASK_SHAMT, match_opcode, 0 },
++{"zip2.w",    64, INSN_CLASS_ZBP,  "d,s",      MATCH_SHFLI|MATCH_SHAMT_ZIP2_W_64, MASK_SHFLI|MASK_SHAMT, match_opcode, 0 },
++{"zip4",      32, INSN_CLASS_ZBP,  "d,s",      MATCH_SHFLI|MATCH_SHAMT_ZIP4_32, MASK_SHFLI|MASK_SHAMT, match_opcode, 0 },
++{"zip4",      64, INSN_CLASS_ZBP,  "d,s",      MATCH_SHFLI|MATCH_SHAMT_ZIP4_64, MASK_SHFLI|MASK_SHAMT, match_opcode, 0 },
++{"zip4.h",    32, INSN_CLASS_ZBP,  "d,s",      MATCH_SHFLI|MATCH_SHAMT_ZIP4_H_32, MASK_SHFLI|MASK_SHAMT, match_opcode, 0 },
++{"zip4.h",    64, INSN_CLASS_ZBP,  "d,s",      MATCH_SHFLI|MATCH_SHAMT_ZIP4_H_64, MASK_SHFLI|MASK_SHAMT, match_opcode, 0 },
++{"zip4.w",    64, INSN_CLASS_ZBP,  "d,s",      MATCH_SHFLI|MATCH_SHAMT_ZIP4_W_64, MASK_SHFLI|MASK_SHAMT, match_opcode, 0 },
++{"zip8",      32, INSN_CLASS_ZBP,  "d,s",      MATCH_SHFLI|MATCH_SHAMT_ZIP8_32, MASK_SHFLI|MASK_SHAMT, match_opcode, 0 },
++{"zip8",      64, INSN_CLASS_ZBP,  "d,s",      MATCH_SHFLI|MATCH_SHAMT_ZIP8_64, MASK_SHFLI|MASK_SHAMT, match_opcode, 0 },
++{"zip8.w",    64, INSN_CLASS_ZBP,  "d,s",      MATCH_SHFLI|MATCH_SHAMT_ZIP8_W_64, MASK_SHFLI|MASK_SHAMT, match_opcode, 0 },
++{"zip16",     64, INSN_CLASS_ZBP,  "d,s",      MATCH_SHFLI|MATCH_SHAMT_ZIP16_64, MASK_SHFLI|MASK_SHAMT, match_opcode, 0 },
++{"unzip",     32, INSN_CLASS_ZBP,  "d,s",      MATCH_UNSHFLI|MATCH_SHAMT_UNZIP_32, MASK_UNSHFLI|MASK_SHAMT, match_opcode, 0 },
++{"unzip",     64, INSN_CLASS_ZBP,  "d,s",      MATCH_UNSHFLI|MATCH_SHAMT_UNZIP_64, MASK_UNSHFLI|MASK_SHAMT, match_opcode, 0 },
++{"unzip.n",   32, INSN_CLASS_ZBP,  "d,s",      MATCH_UNSHFLI|MATCH_SHAMT_UNZIP_N_32, MASK_UNSHFLI|MASK_SHAMT, match_opcode, 0 },
++{"unzip.n",   64, INSN_CLASS_ZBP,  "d,s",      MATCH_UNSHFLI|MATCH_SHAMT_UNZIP_N_64, MASK_UNSHFLI|MASK_SHAMT, match_opcode, 0 },
++{"unzip.b",   32, INSN_CLASS_ZBP,  "d,s",      MATCH_UNSHFLI|MATCH_SHAMT_UNZIP_B_32, MASK_UNSHFLI|MASK_SHAMT, match_opcode, 0 },
++{"unzip.b",   64, INSN_CLASS_ZBP,  "d,s",      MATCH_UNSHFLI|MATCH_SHAMT_UNZIP_B_64, MASK_UNSHFLI|MASK_SHAMT, match_opcode, 0 },
++{"unzip.h",   32, INSN_CLASS_ZBP,  "d,s",      MATCH_UNSHFLI|MATCH_SHAMT_UNZIP_H_32, MASK_UNSHFLI|MASK_SHAMT, match_opcode, 0 },
++{"unzip.h",   64, INSN_CLASS_ZBP,  "d,s",      MATCH_UNSHFLI|MATCH_SHAMT_UNZIP_H_64, MASK_UNSHFLI|MASK_SHAMT, match_opcode, 0 },
++{"unzip.w",   64, INSN_CLASS_ZBP,  "d,s",      MATCH_UNSHFLI|MATCH_SHAMT_UNZIP_W_64, MASK_UNSHFLI|MASK_SHAMT, match_opcode, 0 },
++{"unzip2",    32, INSN_CLASS_ZBP,  "d,s",      MATCH_UNSHFLI|MATCH_SHAMT_UNZIP2_32, MASK_UNSHFLI|MASK_SHAMT, match_opcode, 0 },
++{"unzip2",    64, INSN_CLASS_ZBP,  "d,s",      MATCH_UNSHFLI|MATCH_SHAMT_UNZIP2_64, MASK_UNSHFLI|MASK_SHAMT, match_opcode, 0 },
++{"unzip2.b",  32, INSN_CLASS_ZBP,  "d,s",      MATCH_UNSHFLI|MATCH_SHAMT_UNZIP2_B_32, MASK_UNSHFLI|MASK_SHAMT, match_opcode, 0 },
++{"unzip2.b",  64, INSN_CLASS_ZBP,  "d,s",      MATCH_UNSHFLI|MATCH_SHAMT_UNZIP2_B_64, MASK_UNSHFLI|MASK_SHAMT, match_opcode, 0 },
++{"unzip2.h",  32, INSN_CLASS_ZBP,  "d,s",      MATCH_UNSHFLI|MATCH_SHAMT_UNZIP2_H_32, MASK_UNSHFLI|MASK_SHAMT, match_opcode, 0 },
++{"unzip2.h",  64, INSN_CLASS_ZBP,  "d,s",      MATCH_UNSHFLI|MATCH_SHAMT_UNZIP2_H_64, MASK_UNSHFLI|MASK_SHAMT, match_opcode, 0 },
++{"unzip2.w",  64, INSN_CLASS_ZBP,  "d,s",      MATCH_UNSHFLI|MATCH_SHAMT_UNZIP2_W_64, MASK_UNSHFLI|MASK_SHAMT, match_opcode, 0 },
++{"unzip4",    32, INSN_CLASS_ZBP,  "d,s",      MATCH_UNSHFLI|MATCH_SHAMT_UNZIP4_32, MASK_UNSHFLI|MASK_SHAMT, match_opcode, 0 },
++{"unzip4",    64, INSN_CLASS_ZBP,  "d,s",      MATCH_UNSHFLI|MATCH_SHAMT_UNZIP4_64, MASK_UNSHFLI|MASK_SHAMT, match_opcode, 0 },
++{"unzip4.h",  32, INSN_CLASS_ZBP,  "d,s",      MATCH_UNSHFLI|MATCH_SHAMT_UNZIP4_H_32, MASK_UNSHFLI|MASK_SHAMT, match_opcode, 0 },
++{"unzip4.h",  64, INSN_CLASS_ZBP,  "d,s",      MATCH_UNSHFLI|MATCH_SHAMT_UNZIP4_H_64, MASK_UNSHFLI|MASK_SHAMT, match_opcode, 0 },
++{"unzip4.w",  64, INSN_CLASS_ZBP,  "d,s",      MATCH_UNSHFLI|MATCH_SHAMT_UNZIP4_W_64, MASK_UNSHFLI|MASK_SHAMT, match_opcode, 0 },
++{"unzip8",    32, INSN_CLASS_ZBP,  "d,s",      MATCH_UNSHFLI|MATCH_SHAMT_UNZIP8_32, MASK_UNSHFLI|MASK_SHAMT, match_opcode, 0 },
++{"unzip8",    64, INSN_CLASS_ZBP,  "d,s",      MATCH_UNSHFLI|MATCH_SHAMT_UNZIP8_64, MASK_UNSHFLI|MASK_SHAMT, match_opcode, 0 },
++{"unzip8.w",  64, INSN_CLASS_ZBP,  "d,s",      MATCH_UNSHFLI|MATCH_SHAMT_UNZIP8_W_64, MASK_UNSHFLI|MASK_SHAMT, match_opcode, 0 },
++{"unzip16",   64, INSN_CLASS_ZBP,  "d,s",      MATCH_UNSHFLI|MATCH_SHAMT_UNZIP16_64, MASK_UNSHFLI|MASK_SHAMT, match_opcode, 0 },
+ {"orc",       32, INSN_CLASS_ZBP,  "d,s",      MATCH_GORCI|MATCH_SHAMT_ORC_32, MASK_GORCI|MASK_SHAMT, match_opcode, 0 },
+ {"orc",       64, INSN_CLASS_ZBP,  "d,s",      MATCH_GORCI|MATCH_SHAMT_ORC_64, MASK_GORCI|MASK_SHAMT, match_opcode, 0 },
+ {"orc.p",     32, INSN_CLASS_ZBP,  "d,s",      MATCH_GORCI|MATCH_SHAMT_ORC_P_32, MASK_GORCI|MASK_SHAMT, match_opcode, 0 },
+-- 
+2.33.0
+

+ 50 - 0
recipes-devtools/binutils/binutils/0016-Fix-internal-error-undefined-modifier-r.patch

@@ -0,0 +1,50 @@
+From 8e76ea22bbdb344e224c9c7bd795c52012a08cf0 Mon Sep 17 00:00:00 2001
+From: LevyHsu <admin@levyhsu.com>
+Date: Thu, 24 Jun 2021 14:59:01 +0800
+Subject: [PATCH 16/28] Fix internal error, undefined modifier (r)
+
+This bug is locate to this commit:
+https://github.com/pz9115/riscv-binutils-gdb/commit/85dd8e06472e4cee3bd7d78cb820df8a6c311e3d
+
+Where operands case 'r' was accidentally put under
+case 'C': /* RVC */
+	  switch (*++d)
+	    {...}
+which caused  print_insn_args() to
+print (info->stream, _("# internal error, undefined modifier (V%c)"),
+		     *d);
+---
+ gas/config/tc-riscv.c | 2 +-
+ opcodes/riscv-dis.c   | 3 ++-
+ 2 files changed, 3 insertions(+), 2 deletions(-)
+
+diff --git a/gas/config/tc-riscv.c b/gas/config/tc-riscv.c
+index 405ef3278a..1cc76db7cc 100644
+--- a/gas/config/tc-riscv.c
++++ b/gas/config/tc-riscv.c
+@@ -1044,7 +1044,7 @@ validate_riscv_insn (const struct riscv_opcode *opc, int length)
+       case 'm':	USE_BITS (OP_MASK_RM,		OP_SH_RM);	break;
+       case 's':	USE_BITS (OP_MASK_RS1,		OP_SH_RS1);	break;
+       case 't':	USE_BITS (OP_MASK_RS2,		OP_SH_RS2);	break;
+-      case 'r':	USE_BITS (OP_MASK_RS3,          OP_SH_RS3);     break;
++      case 'r':	USE_BITS (OP_MASK_RS3,    OP_SH_RS3); break;
+       case 'P':	USE_BITS (OP_MASK_PRED,		OP_SH_PRED); break;
+       case 'Q':	USE_BITS (OP_MASK_SUCC,		OP_SH_SUCC); break;
+       case 'o':
+diff --git a/opcodes/riscv-dis.c b/opcodes/riscv-dis.c
+index 065ea75b82..e3ee7b9d9b 100644
+--- a/opcodes/riscv-dis.c
++++ b/opcodes/riscv-dis.c
+@@ -370,7 +370,8 @@ print_insn_args (const char *d, insn_t l, bfd_vma pc, disassemble_info *info)
+ 	case 'D':
+ 	  print (info->stream, "%s", riscv_fpr_names[rd]);
+ 	  break;
+-
++	
++	case 'r':
+ 	case 'R':
+ 	  print (info->stream, "%s", riscv_fpr_names[EXTRACT_OPERAND (RS3, l)]);
+ 	  break;
+-- 
+2.33.0
+

+ 25 - 0
recipes-devtools/binutils/binutils/0017-Fix-coding-for-Bcompressw.patch

@@ -0,0 +1,25 @@
+From 11fdd0a46602d7c6f21801772eccc54ebafbba43 Mon Sep 17 00:00:00 2001
+From: LevyHsu <admin@levyhsu.com>
+Date: Thu, 24 Jun 2021 14:59:31 +0800
+Subject: [PATCH 17/28] Fix coding for Bcompressw
+
+---
+ include/opcode/riscv-opc.h | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+diff --git a/include/opcode/riscv-opc.h b/include/opcode/riscv-opc.h
+index 3a86dfc17d..71962e19f0 100644
+--- a/include/opcode/riscv-opc.h
++++ b/include/opcode/riscv-opc.h
+@@ -665,7 +665,7 @@
+ #define MASK_SHFLW  0xfe00707f
+ #define MATCH_UNSHFLW 0x800503b
+ #define MASK_UNSHFLW  0xfe00707f
+-#define MATCH_BCOMPRESSW 0x4800603b
++#define MATCH_BCOMPRESSW 0x800603B
+ #define MASK_BCOMPRESSW  0xfe00707f
+ #define MATCH_BDECOMPRESSW 0x4800603b
+ #define MASK_BDECOMPRESSW  0xfe00707f
+-- 
+2.33.0
+

+ 25 - 0
recipes-devtools/binutils/binutils/0018-Fix-zip2.b-testcase.patch

@@ -0,0 +1,25 @@
+From ac21c6c5a0ac15f33da81820b03ae493ad1e1e8b Mon Sep 17 00:00:00 2001
+From: LevyHsu <admin@levyhsu.com>
+Date: Thu, 24 Jun 2021 15:08:51 +0800
+Subject: [PATCH 18/28] Fix zip2.b testcase
+
+---
+ gas/testsuite/gas/riscv/b-ext-64.d | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+diff --git a/gas/testsuite/gas/riscv/b-ext-64.d b/gas/testsuite/gas/riscv/b-ext-64.d
+index 8a1daf2766..094ee2d554 100755
+--- a/gas/testsuite/gas/riscv/b-ext-64.d
++++ b/gas/testsuite/gas/riscv/b-ext-64.d
+@@ -60,7 +60,7 @@ Disassembly of section .text:
+ [ 	]+c4:[ 	]+2825d53b[ 	]+gorcw[ 	]+a0,a1,0x2
+ [ 	]+c8:[ 	]+2825d51b[ 	]+gorciw[ 	]+a0,a1,0x2
+ [ 	]+cc:[ 	]+08c59533[ 	]+shfl[ 	]+a0,a1,a2
+-[ 	]+d0:[ 	]+08259513[ 	]+shfli[ 	]+a0,a1,0x2
++[ 	]+d0:[ 	]+08259513[ 	]+zip2.b[ 	]+a0,a1
+ [ 	]+d4:[ 	]+0825953b[ 	]+shflw[ 	]+a0,a1,0x2
+ [ 	]+d8:[ 	]+08c5d533[ 	]+unshfl[ 	]+a0,a1,a2
+ [ 	]+dc:[ 	]+0825d513[ 	]+unshfli[ 	]+a0,a1,0x2
+-- 
+2.33.0
+

+ 25 - 0
recipes-devtools/binutils/binutils/0019-Fix-orc2.n-testcase.patch

@@ -0,0 +1,25 @@
+From 1a450f0c0489c69b0079923c6cc84445126880c8 Mon Sep 17 00:00:00 2001
+From: LevyHsu <admin@levyhsu.com>
+Date: Thu, 24 Jun 2021 15:12:30 +0800
+Subject: [PATCH 19/28] Fix orc2.n testcase
+
+---
+ gas/testsuite/gas/riscv/b-ext-64.d | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+diff --git a/gas/testsuite/gas/riscv/b-ext-64.d b/gas/testsuite/gas/riscv/b-ext-64.d
+index 094ee2d554..eeb5087229 100755
+--- a/gas/testsuite/gas/riscv/b-ext-64.d
++++ b/gas/testsuite/gas/riscv/b-ext-64.d
+@@ -56,7 +56,7 @@ Disassembly of section .text:
+ [ 	]+b4:[ 	]+6825d53b[ 	]+grevw[ 	]+a0,a1,0x2
+ [ 	]+b8:[ 	]+6825d51b[ 	]+greviw[ 	]+a0,a1,0x2
+ [ 	]+bc:[ 	]+28c5d533[ 	]+gorc[ 	]+a0,a1,a2
+-[ 	]+c0:[ 	]+2825d513[ 	]+gorci[ 	]+a0,a1,0x2
++[ 	]+c0:[ 	]+2825d513[ 	]+orc2.n[ 	]+a0,a1
+ [ 	]+c4:[ 	]+2825d53b[ 	]+gorcw[ 	]+a0,a1,0x2
+ [ 	]+c8:[ 	]+2825d51b[ 	]+gorciw[ 	]+a0,a1,0x2
+ [ 	]+cc:[ 	]+08c59533[ 	]+shfl[ 	]+a0,a1,a2
+-- 
+2.33.0
+

+ 25 - 0
recipes-devtools/binutils/binutils/0020-Fix-rev2.n-test-case.patch

@@ -0,0 +1,25 @@
+From 7043dfdd782f25eee672658049af6c2271c2571d Mon Sep 17 00:00:00 2001
+From: LevyHsu <admin@levyhsu.com>
+Date: Thu, 24 Jun 2021 15:15:58 +0800
+Subject: [PATCH 20/28] Fix rev2.n test case
+
+---
+ gas/testsuite/gas/riscv/b-ext-64.d | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+diff --git a/gas/testsuite/gas/riscv/b-ext-64.d b/gas/testsuite/gas/riscv/b-ext-64.d
+index eeb5087229..10aaf70c8a 100755
+--- a/gas/testsuite/gas/riscv/b-ext-64.d
++++ b/gas/testsuite/gas/riscv/b-ext-64.d
+@@ -52,7 +52,7 @@ Disassembly of section .text:
+ [ 	]+a4:[ 	]+0825c53b[ 	]+packw[ 	]+a0,a1,0x2
+ [ 	]+a8:[ 	]+4825c53b[ 	]+packuw[ 	]+a0,a1,0x2
+ [ 	]+ac:[ 	]+68c5d533[ 	]+grev[ 	]+a0,a1,a2
+-[ 	]+b0:[ 	]+6825d513[ 	]+grevi[ 	]+a0,a1,0x2
++[ 	]+b0:[ 	]+6825d513[ 	]+rev2.n[ 	]+a0,a1
+ [ 	]+b4:[ 	]+6825d53b[ 	]+grevw[ 	]+a0,a1,0x2
+ [ 	]+b8:[ 	]+6825d51b[ 	]+greviw[ 	]+a0,a1,0x2
+ [ 	]+bc:[ 	]+28c5d533[ 	]+gorc[ 	]+a0,a1,a2
+-- 
+2.33.0
+

+ 34 - 0
recipes-devtools/binutils/binutils/0021-Fix-testcase-for-zip2.b-and-rev2.n.patch

@@ -0,0 +1,34 @@
+From 09a4ef2adddc0478e1ac752c42ecef181dd32bc5 Mon Sep 17 00:00:00 2001
+From: LevyHsu <admin@levyhsu.com>
+Date: Thu, 24 Jun 2021 15:57:47 +0800
+Subject: [PATCH 21/28] Fix testcase for zip2.b and rev2.n
+
+---
+ gas/testsuite/gas/riscv/b-ext-64.d | 4 ++--
+ 1 file changed, 2 insertions(+), 2 deletions(-)
+
+diff --git a/gas/testsuite/gas/riscv/b-ext-64.d b/gas/testsuite/gas/riscv/b-ext-64.d
+index 10aaf70c8a..e27787a3f5 100755
+--- a/gas/testsuite/gas/riscv/b-ext-64.d
++++ b/gas/testsuite/gas/riscv/b-ext-64.d
+@@ -52,7 +52,7 @@ Disassembly of section .text:
+ [ 	]+a4:[ 	]+0825c53b[ 	]+packw[ 	]+a0,a1,0x2
+ [ 	]+a8:[ 	]+4825c53b[ 	]+packuw[ 	]+a0,a1,0x2
+ [ 	]+ac:[ 	]+68c5d533[ 	]+grev[ 	]+a0,a1,a2
+-[ 	]+b0:[ 	]+6825d513[ 	]+rev2.n[ 	]+a0,a1
++[ 	]+b0:[ 	]+6825d513[ 	]+rev2.n[ 	]+a0,a1,0x2
+ [ 	]+b4:[ 	]+6825d53b[ 	]+grevw[ 	]+a0,a1,0x2
+ [ 	]+b8:[ 	]+6825d51b[ 	]+greviw[ 	]+a0,a1,0x2
+ [ 	]+bc:[ 	]+28c5d533[ 	]+gorc[ 	]+a0,a1,a2
+@@ -63,7 +63,7 @@ Disassembly of section .text:
+ [ 	]+d0:[ 	]+08259513[ 	]+zip2.b[ 	]+a0,a1
+ [ 	]+d4:[ 	]+0825953b[ 	]+shflw[ 	]+a0,a1,0x2
+ [ 	]+d8:[ 	]+08c5d533[ 	]+unshfl[ 	]+a0,a1,a2
+-[ 	]+dc:[ 	]+0825d513[ 	]+unshfli[ 	]+a0,a1,0x2
++[ 	]+dc:[ 	]+0825d513[ 	]+unzip2.b[ 	]+a0,a1,0x2
+ [ 	]+e0:[ 	]+0825d53b[ 	]+unshflw[ 	]+a0,a1,0x2
+ [ 	]+e4:[ 	]+28c5a533[ 	]+xperm.n[ 	]+a0,a1,a2
+ [ 	]+e8:[ 	]+28c5c533[ 	]+xperm.b[ 	]+a0,a1,a2
+-- 
+2.33.0
+

+ 27 - 0
recipes-devtools/binutils/binutils/0022-Fix-r-operands-type-from-fpr-to-gpr.patch

@@ -0,0 +1,27 @@
+From c7d793a52e9a523c646a5b465bb1750f4b5348da Mon Sep 17 00:00:00 2001
+From: LevyHsu <admin@levyhsu.com>
+Date: Thu, 24 Jun 2021 16:10:23 +0800
+Subject: [PATCH 22/28] Fix r operands type from fpr to gpr
+
+riscv_fpr_names riscv_gpr_names
+---
+ opcodes/riscv-dis.c | 3 +++
+ 1 file changed, 3 insertions(+)
+
+diff --git a/opcodes/riscv-dis.c b/opcodes/riscv-dis.c
+index e3ee7b9d9b..b3bd43347f 100644
+--- a/opcodes/riscv-dis.c
++++ b/opcodes/riscv-dis.c
+@@ -372,6 +372,9 @@ print_insn_args (const char *d, insn_t l, bfd_vma pc, disassemble_info *info)
+ 	  break;
+ 	
+ 	case 'r':
++	  print (info->stream, "%s", riscv_gpr_names[EXTRACT_OPERAND (RS3, l)]);
++      break;
++
+ 	case 'R':
+ 	  print (info->stream, "%s", riscv_fpr_names[EXTRACT_OPERAND (RS3, l)]);
+ 	  break;
+-- 
+2.33.0
+

+ 99 - 0
recipes-devtools/binutils/binutils/0023-support-vid-vmv1r-vl1r-vs1r-instruction.patch

@@ -0,0 +1,99 @@
+From 392661532fdf03c24d3b3715145f655b5c259986 Mon Sep 17 00:00:00 2001
+From: "eric.tang" <eric.tang@starfivetech.com>
+Date: Thu, 24 Jun 2021 11:40:56 +0800
+Subject: [PATCH 23/28] support vid vmv1r vl1r vs1r instruction
+
+Signed-off-by: eric.tang <eric.tang@starfivetech.com>
+---
+ gas/testsuite/gas/riscv/vector-insns.d | 13 +++++++++++++
+ gas/testsuite/gas/riscv/vector-insns.s | 13 +++++++++++++
+ opcodes/riscv-opc.c                    | 10 ++++++++++
+ 3 files changed, 36 insertions(+)
+
+diff --git a/gas/testsuite/gas/riscv/vector-insns.d b/gas/testsuite/gas/riscv/vector-insns.d
+index fe6a95cba5..d8d6608fb3 100644
+--- a/gas/testsuite/gas/riscv/vector-insns.d
++++ b/gas/testsuite/gas/riscv/vector-insns.d
+@@ -98,6 +98,18 @@ Disassembly of section .text:
+ [ 	]+[0-9a-f]+:[ 	]+0ec57227[ 	]+vsoxei64.v[ 	]+v4,\(a0\),v12
+ [ 	]+[0-9a-f]+:[ 	]+0ec57227[ 	]+vsoxei64.v[ 	]+v4,\(a0\),v12
+ [ 	]+[0-9a-f]+:[ 	]+0cc57227[ 	]+vsoxei64.v[ 	]+v4,\(a0\),v12,v0.t
++[ 	]+[0-9a-f]+:[   ]+02850187[     ]+vl1r.v[       ]+v3,\(a0\)
++[ 	]+[0-9a-f]+:[   ]+02850187[     ]+vl1r.v[       ]+v3,\(a0\)
++[ 	]+[0-9a-f]+:[   ]+02850187[     ]+vl1r.v[       ]+v3,\(a0\)
++[ 	]+[0-9a-f]+:[   ]+02850187[     ]+vl1r.v[       ]+v3,\(a0\)
++[ 	]+[0-9a-f]+:[   ]+02855187[     ]+vl1re16.v[    ]+v3,\(a0\)
++[ 	]+[0-9a-f]+:[   ]+02855187[     ]+vl1re16.v[    ]+v3,\(a0\)
++[ 	]+[0-9a-f]+:[   ]+02856187[     ]+vl1re32.v[    ]+v3,\(a0\)
++[ 	]+[0-9a-f]+:[   ]+02856187[     ]+vl1re32.v[    ]+v3,\(a0\)
++[ 	]+[0-9a-f]+:[   ]+02857187[     ]+vl1re64.v[    ]+v3,\(a0\)
++[ 	]+[0-9a-f]+:[   ]+02857187[     ]+vl1re64.v[    ]+v3,\(a0\)
++[ 	]+[0-9a-f]+:[   ]+028581a7[     ]+vs1r.v[       ]+v3,\(a1\)
++[ 	]+[0-9a-f]+:[   ]+028581a7[     ]+vs1r.v[       ]+v3,\(a1\)
+ [ 	]+[0-9a-f]+:[ 	]+0e804257[ 	]+vneg.v[ 	]+v4,v8
+ [ 	]+[0-9a-f]+:[ 	]+0c804257[ 	]+vneg.v[ 	]+v4,v8,v0.t
+ [ 	]+[0-9a-f]+:[ 	]+02860257[ 	]+vadd.vv[ 	]+v4,v8,v12
+@@ -474,3 +486,4 @@ Disassembly of section .text:
+ [ 	]+[0-9a-f]+:[ 	]+30803257[ 	]+vrgather.vi[ 	]+v4,v8,0,v0.t
+ [ 	]+[0-9a-f]+:[ 	]+308fb257[ 	]+vrgather.vi[ 	]+v4,v8,31,v0.t
+ [ 	]+[0-9a-f]+:[ 	]+5e862257[ 	]+vcompress.vm[ 	]+v4,v8,v12
++[ 	]+[0-9a-f]+:[   ]+9e2030d7[     ]+vmv1r.v[      ]+v1,v2
+diff --git a/gas/testsuite/gas/riscv/vector-insns.s b/gas/testsuite/gas/riscv/vector-insns.s
+index a6f906e416..5cb7c7a5e2 100644
+--- a/gas/testsuite/gas/riscv/vector-insns.s
++++ b/gas/testsuite/gas/riscv/vector-insns.s
+@@ -102,6 +102,18 @@
+ 	vsoxei64.v v4, 0(a0), v12
+ 	vsoxei64.v v4, (a0), v12, v0.t
+ 
++        vl1r.v v3, (a0)
++        vl1r.v v3, 0(a0)
++        vl1re8.v v3, (a0)
++        vl1re8.v v3, 0(a0)
++        vl1re16.v v3, (a0)
++        vl1re16.v v3, 0(a0)
++        vl1re32.v v3, (a0)
++        vl1re32.v v3, 0(a0)
++        vl1re64.v v3, (a0)
++        vl1re64.v v3, 0(a0)
++        vs1r.v v3, (a1)
++        vs1r.v v3, 0(a1)
+ 	vneg.v v4, v8
+ 	vneg.v v4, v8, v0.t
+ 
+@@ -519,3 +531,4 @@
+ 
+ 	vcompress.vm v4, v8, v12
+ 
++        vmv1r.v v1, v2
+diff --git a/opcodes/riscv-opc.c b/opcodes/riscv-opc.c
+index 067ebe3115..9229f7f87a 100644
+--- a/opcodes/riscv-opc.c
++++ b/opcodes/riscv-opc.c
+@@ -1580,6 +1580,14 @@ const struct riscv_opcode riscv_opcodes[] =
+ {"vsoxei32.v",  0, INSN_CLASS_V,  "Vd,0(s),VtVm", MATCH_VSOXEI32V, MASK_VSOXEI32V, match_vd_neq_vm, INSN_DREF },
+ {"vsoxei64.v",  0, INSN_CLASS_V,  "Vd,0(s),VtVm", MATCH_VSOXEI64V, MASK_VSOXEI64V, match_vd_neq_vm, INSN_DREF },
+ 
++{"vl1r.v",      0, INSN_CLASS_V,  "Vd,0(s)", MATCH_VL1RE8V, MASK_VL1RE8V, match_vls_nf_rv, INSN_DREF|INSN_ALIAS },
++{"vl1re8.v",    0, INSN_CLASS_V,  "Vd,0(s)", MATCH_VL1RE8V, MASK_VL1RE8V, match_vls_nf_rv, INSN_DREF },
++{"vl1re16.v",   0, INSN_CLASS_V,  "Vd,0(s)", MATCH_VL1RE16V, MASK_VL1RE16V, match_vls_nf_rv, INSN_DREF },
++{"vl1re32.v",   0, INSN_CLASS_V,  "Vd,0(s)", MATCH_VL1RE32V, MASK_VL1RE32V, match_vls_nf_rv, INSN_DREF },
++{"vl1re64.v",   0, INSN_CLASS_V,  "Vd,0(s)", MATCH_VL1RE64V, MASK_VL1RE64V, match_vls_nf_rv, INSN_DREF },
++
++{"vs1r.v",  0, INSN_CLASS_V,  "Vd,0(s)", MATCH_VS1RV, MASK_VS1RV, match_vls_nf_rv, INSN_DREF },
++
+ {"vneg.v",     0, INSN_CLASS_V,  "Vd,VtVm",  MATCH_VRSUBVX, MASK_VRSUBVX | MASK_RS1, match_vd_neq_vm, INSN_ALIAS },
+ 
+ {"vadd.vv",    0, INSN_CLASS_V,  "Vd,Vt,VsVm", MATCH_VADDVV, MASK_VADDVV, match_vd_neq_vm, 0 },
+@@ -1808,6 +1816,8 @@ const struct riscv_opcode riscv_opcodes[] =
+ {"vrgather.vi",    0, INSN_CLASS_V, "Vd,Vt,VjVm", MATCH_VRGATHERVI, MASK_VRGATHERVI, match_vd_neq_vs2_neq_vm, 0},
+ 
+ {"vcompress.vm",0, INSN_CLASS_V, "Vd,Vt,Vs", MATCH_VCOMPRESSVM, MASK_VCOMPRESSVM, match_vd_neq_vs1_neq_vs2, 0},
++
++{"vmv1r.v",    0, INSN_CLASS_V, "Vd,Vt", MATCH_VMV1RV, MASK_VMV1RV, match_vmv_nf_rv, 0},
+ /* END RVV */
+ 
+ /* Terminate the list.  */
+-- 
+2.33.0
+

+ 214 - 0
recipes-devtools/binutils/binutils/0024-add-vid-instruction-support.patch

@@ -0,0 +1,214 @@
+From 4dce782d6beccc91ce1723fd07e4706ee632a092 Mon Sep 17 00:00:00 2001
+From: "eric.tang" <eric.tang@starfivetech.com>
+Date: Tue, 22 Jun 2021 15:44:01 +0800
+Subject: [PATCH 24/28] add vid instruction support
+
+Signed-off-by: eric.tang <eric.tang@starfivetech.com>
+---
+ .../gas/riscv/vector-insns-fail-unsupport.l   | 15 ----------
+ .../gas/riscv/vector-insns-fail-unsupport.s   | 16 ----------
+ gas/testsuite/gas/riscv/vector-insns.d        | 30 +++++++++++--------
+ gas/testsuite/gas/riscv/vector-insns.s        | 28 +++++++++--------
+ opcodes/riscv-opc.c                           |  1 +
+ 5 files changed, 33 insertions(+), 57 deletions(-)
+
+diff --git a/gas/testsuite/gas/riscv/vector-insns-fail-unsupport.l b/gas/testsuite/gas/riscv/vector-insns-fail-unsupport.l
+index ae2230cb9e..2b726b0268 100644
+--- a/gas/testsuite/gas/riscv/vector-insns-fail-unsupport.l
++++ b/gas/testsuite/gas/riscv/vector-insns-fail-unsupport.l
+@@ -813,16 +813,6 @@
+ .*: Error: unrecognized opcode `vlseg8e64ff.v v4,\(a0\)'
+ .*: Error: unrecognized opcode `vlseg8e64ff.v v4,0\(a0\)'
+ .*: Error: unrecognized opcode `vlseg8e64ff.v v4,\(a0\),v0.t'
+-.*: Error: unrecognized opcode `vl1r.v v3,\(a0\)'
+-.*: Error: unrecognized opcode `vl1r.v v3,0\(a0\)'
+-.*: Error: unrecognized opcode `vl1re8.v v3,\(a0\)'
+-.*: Error: unrecognized opcode `vl1re8.v v3,0\(a0\)'
+-.*: Error: unrecognized opcode `vl1re16.v v3,\(a0\)'
+-.*: Error: unrecognized opcode `vl1re16.v v3,0\(a0\)'
+-.*: Error: unrecognized opcode `vl1re32.v v3,\(a0\)'
+-.*: Error: unrecognized opcode `vl1re32.v v3,0\(a0\)'
+-.*: Error: unrecognized opcode `vl1re64.v v3,\(a0\)'
+-.*: Error: unrecognized opcode `vl1re64.v v3,0\(a0\)'
+ .*: Error: unrecognized opcode `vl2r.v v2,\(a0\)'
+ .*: Error: unrecognized opcode `vl2r.v v2,0\(a0\)'
+ .*: Error: unrecognized opcode `vl2re8.v v2,\(a0\)'
+@@ -853,8 +843,6 @@
+ .*: Error: unrecognized opcode `vl8re32.v v8,0\(a0\)'
+ .*: Error: unrecognized opcode `vl8re64.v v8,\(a0\)'
+ .*: Error: unrecognized opcode `vl8re64.v v8,0\(a0\)'
+-.*: Error: unrecognized opcode `vs1r.v v3,\(a1\)'
+-.*: Error: unrecognized opcode `vs1r.v v3,0\(a1\)'
+ .*: Error: unrecognized opcode `vs2r.v v2,\(a1\)'
+ .*: Error: unrecognized opcode `vs2r.v v2,0\(a1\)'
+ .*: Error: unrecognized opcode `vs4r.v v4,\(a1\)'
+@@ -1455,15 +1443,12 @@
+ .*: Error: unrecognized opcode `vmsif.m v4,v8'
+ .*: Error: unrecognized opcode `vmsof.m v4,v8'
+ .*: Error: unrecognized opcode `viota.m v4,v8'
+-.*: Error: unrecognized opcode `vid.v v4'
+ .*: Error: unrecognized opcode `vmsbf.m v4,v8,v0.t'
+ .*: Error: unrecognized opcode `vmsif.m v4,v8,v0.t'
+ .*: Error: unrecognized opcode `vmsof.m v4,v8,v0.t'
+ .*: Error: unrecognized opcode `viota.m v4,v8,v0.t'
+-.*: Error: unrecognized opcode `vid.v v4,v0.t'
+ .*: Error: unrecognized opcode `vrgatherei16.vv v4,v8,v12'
+ .*: Error: unrecognized opcode `vrgatherei16.vv v4,v8,v12,v0.t'
+-.*: Error: unrecognized opcode `vmv1r.v v1,v2'
+ .*: Error: unrecognized opcode `vmv2r.v v2,v4'
+ .*: Error: unrecognized opcode `vmv4r.v v4,v8'
+ .*: Error: unrecognized opcode `vmv8r.v v0,v8'
+diff --git a/gas/testsuite/gas/riscv/vector-insns-fail-unsupport.s b/gas/testsuite/gas/riscv/vector-insns-fail-unsupport.s
+index 0116ac2c06..0112d0bce7 100644
+--- a/gas/testsuite/gas/riscv/vector-insns-fail-unsupport.s
++++ b/gas/testsuite/gas/riscv/vector-insns-fail-unsupport.s
+@@ -967,17 +967,6 @@
+ 	vlseg8e64ff.v v4, 0(a0)
+ 	vlseg8e64ff.v v4, (a0), v0.t
+ 
+-	vl1r.v v3, (a0)
+-	vl1r.v v3, 0(a0)
+-	vl1re8.v v3, (a0)
+-	vl1re8.v v3, 0(a0)
+-	vl1re16.v v3, (a0)
+-	vl1re16.v v3, 0(a0)
+-	vl1re32.v v3, (a0)
+-	vl1re32.v v3, 0(a0)
+-	vl1re64.v v3, (a0)
+-	vl1re64.v v3, 0(a0)
+-
+ 	vl2r.v v2, (a0)
+ 	vl2r.v v2, 0(a0)
+ 	vl2re8.v v2, (a0)
+@@ -1011,8 +1000,6 @@
+ 	vl8re64.v v8, (a0)
+ 	vl8re64.v v8, 0(a0)
+ 
+-	vs1r.v v3, (a1)
+-	vs1r.v v3, 0(a1)
+ 	vs2r.v v2, (a1)
+ 	vs2r.v v2, 0(a1)
+ 	vs4r.v v4, (a1)
+@@ -1662,18 +1649,15 @@
+ 	vmsif.m v4, v8
+ 	vmsof.m v4, v8
+ 	viota.m v4, v8
+-	vid.v v4
+ 	
+ 	vmsbf.m v4, v8, v0.t
+ 	vmsif.m v4, v8, v0.t
+ 	vmsof.m v4, v8, v0.t
+ 	viota.m v4, v8, v0.t
+-	vid.v v4, v0.t
+ 
+ 	vrgatherei16.vv v4, v8, v12
+ 	vrgatherei16.vv v4, v8, v12, v0.t
+ 
+-	vmv1r.v v1, v2
+ 	vmv2r.v v2, v4
+ 	vmv4r.v v4, v8
+ 	vmv8r.v v0, v8
+diff --git a/gas/testsuite/gas/riscv/vector-insns.d b/gas/testsuite/gas/riscv/vector-insns.d
+index d8d6608fb3..09c12ddfef 100644
+--- a/gas/testsuite/gas/riscv/vector-insns.d
++++ b/gas/testsuite/gas/riscv/vector-insns.d
+@@ -98,18 +98,6 @@ Disassembly of section .text:
+ [ 	]+[0-9a-f]+:[ 	]+0ec57227[ 	]+vsoxei64.v[ 	]+v4,\(a0\),v12
+ [ 	]+[0-9a-f]+:[ 	]+0ec57227[ 	]+vsoxei64.v[ 	]+v4,\(a0\),v12
+ [ 	]+[0-9a-f]+:[ 	]+0cc57227[ 	]+vsoxei64.v[ 	]+v4,\(a0\),v12,v0.t
+-[ 	]+[0-9a-f]+:[   ]+02850187[     ]+vl1r.v[       ]+v3,\(a0\)
+-[ 	]+[0-9a-f]+:[   ]+02850187[     ]+vl1r.v[       ]+v3,\(a0\)
+-[ 	]+[0-9a-f]+:[   ]+02850187[     ]+vl1r.v[       ]+v3,\(a0\)
+-[ 	]+[0-9a-f]+:[   ]+02850187[     ]+vl1r.v[       ]+v3,\(a0\)
+-[ 	]+[0-9a-f]+:[   ]+02855187[     ]+vl1re16.v[    ]+v3,\(a0\)
+-[ 	]+[0-9a-f]+:[   ]+02855187[     ]+vl1re16.v[    ]+v3,\(a0\)
+-[ 	]+[0-9a-f]+:[   ]+02856187[     ]+vl1re32.v[    ]+v3,\(a0\)
+-[ 	]+[0-9a-f]+:[   ]+02856187[     ]+vl1re32.v[    ]+v3,\(a0\)
+-[ 	]+[0-9a-f]+:[   ]+02857187[     ]+vl1re64.v[    ]+v3,\(a0\)
+-[ 	]+[0-9a-f]+:[   ]+02857187[     ]+vl1re64.v[    ]+v3,\(a0\)
+-[ 	]+[0-9a-f]+:[   ]+028581a7[     ]+vs1r.v[       ]+v3,\(a1\)
+-[ 	]+[0-9a-f]+:[   ]+028581a7[     ]+vs1r.v[       ]+v3,\(a1\)
+ [ 	]+[0-9a-f]+:[ 	]+0e804257[ 	]+vneg.v[ 	]+v4,v8
+ [ 	]+[0-9a-f]+:[ 	]+0c804257[ 	]+vneg.v[ 	]+v4,v8,v0.t
+ [ 	]+[0-9a-f]+:[ 	]+02860257[ 	]+vadd.vv[ 	]+v4,v8,v12
+@@ -486,4 +474,20 @@ Disassembly of section .text:
+ [ 	]+[0-9a-f]+:[ 	]+30803257[ 	]+vrgather.vi[ 	]+v4,v8,0,v0.t
+ [ 	]+[0-9a-f]+:[ 	]+308fb257[ 	]+vrgather.vi[ 	]+v4,v8,31,v0.t
+ [ 	]+[0-9a-f]+:[ 	]+5e862257[ 	]+vcompress.vm[ 	]+v4,v8,v12
+-[ 	]+[0-9a-f]+:[   ]+9e2030d7[     ]+vmv1r.v[      ]+v1,v2
++[ 	]+[0-9a-f]+:[ 	]+9e2030d7[ 	]+vmv1r.v[ 	]+v1,v2
++[ 	]+[0-9a-f]+:[ 	]+5208a257[ 	]+vid.v[ 	]+v4
++[ 	]+[0-9a-f]+:[ 	]+5008a257[ 	]+vid.v[ 	]+v4,v0.t
++[ 	]+[0-9a-f]+:[ 	]++02850187[     ]+vl1r.v[       ]+v3,\(a0\)
++[ 	]+[0-9a-f]+:[ 	]++02850187[     ]+vl1r.v[       ]+v3,\(a0\)
++[ 	]+[0-9a-f]+:[ 	]++02850187[     ]+vl1r.v[       ]+v3,\(a0\)
++[ 	]+[0-9a-f]+:[ 	]++02850187[     ]+vl1r.v[       ]+v3,\(a0\)
++[ 	]+[0-9a-f]+:[ 	]++02855187[     ]+vl1re16.v[    ]+v3,\(a0\)
++[ 	]+[0-9a-f]+:[ 	]++02855187[     ]+vl1re16.v[    ]+v3,\(a0\)
++[ 	]+[0-9a-f]+:[ 	]++02856187[     ]+vl1re32.v[    ]+v3,\(a0\)
++[ 	]+[0-9a-f]+:[ 	]++02856187[     ]+vl1re32.v[    ]+v3,\(a0\)
++[ 	]+[0-9a-f]+:[ 	]++02857187[     ]+vl1re64.v[    ]+v3,\(a0\)
++[ 	]+[0-9a-f]+:[ 	]++02857187[     ]+vl1re64.v[    ]+v3,\(a0\)
++[ 	]+[0-9a-f]+:[ 	]++028581a7[     ]+vs1r.v[       ]+v3,\(a1\)
++[ 	]+[0-9a-f]+:[ 	]++028581a7[     ]+vs1r.v[       ]+v3,\(a1\)
++
++
+diff --git a/gas/testsuite/gas/riscv/vector-insns.s b/gas/testsuite/gas/riscv/vector-insns.s
+index 5cb7c7a5e2..81ef661af9 100644
+--- a/gas/testsuite/gas/riscv/vector-insns.s
++++ b/gas/testsuite/gas/riscv/vector-insns.s
+@@ -102,18 +102,6 @@
+ 	vsoxei64.v v4, 0(a0), v12
+ 	vsoxei64.v v4, (a0), v12, v0.t
+ 
+-        vl1r.v v3, (a0)
+-        vl1r.v v3, 0(a0)
+-        vl1re8.v v3, (a0)
+-        vl1re8.v v3, 0(a0)
+-        vl1re16.v v3, (a0)
+-        vl1re16.v v3, 0(a0)
+-        vl1re32.v v3, (a0)
+-        vl1re32.v v3, 0(a0)
+-        vl1re64.v v3, (a0)
+-        vl1re64.v v3, 0(a0)
+-        vs1r.v v3, (a1)
+-        vs1r.v v3, 0(a1)
+ 	vneg.v v4, v8
+ 	vneg.v v4, v8, v0.t
+ 
+@@ -530,5 +518,19 @@
+ 	vrgather.vi v4, v8, 31, v0.t
+ 
+ 	vcompress.vm v4, v8, v12
+-
+         vmv1r.v v1, v2
++        vid.v v4
++        vid.v v4, v0.t
++        vl1r.v v3, (a0)
++        vl1r.v v3, 0(a0)
++        vl1re8.v v3, (a0)
++        vl1re8.v v3, 0(a0)
++        vl1re16.v v3, (a0)
++        vl1re16.v v3, 0(a0)
++        vl1re32.v v3, (a0)
++        vl1re32.v v3, 0(a0)
++        vl1re64.v v3, (a0)
++        vl1re64.v v3, 0(a0)
++        vs1r.v v3, (a1)
++        vs1r.v v3, 0(a1)
++
+diff --git a/opcodes/riscv-opc.c b/opcodes/riscv-opc.c
+index 9229f7f87a..7052d965d5 100644
+--- a/opcodes/riscv-opc.c
++++ b/opcodes/riscv-opc.c
+@@ -1794,6 +1794,7 @@ const struct riscv_opcode riscv_opcodes[] =
+ 
+ {"vpopc.m",    0, INSN_CLASS_V, "d,VtVm", MATCH_VPOPCM, MASK_VPOPCM, match_opcode, 0},
+ {"vfirst.m",   0, INSN_CLASS_V, "d,VtVm", MATCH_VFIRSTM, MASK_VFIRSTM, match_opcode, 0},
++{"vid.v",      0, INSN_CLASS_V, "VdVm", MATCH_VIDV, MASK_VIDV, match_vd_neq_vm, 0},
+ 
+ {"vmv.x.s",    0, INSN_CLASS_V, "d,Vt", MATCH_VMVXS, MASK_VMVXS, match_opcode, 0},
+ {"vmv.s.x",    0, INSN_CLASS_V, "Vd,s", MATCH_VMVSX, MASK_VMVSX, match_opcode, 0},
+-- 
+2.33.0
+

+ 34 - 0
recipes-devtools/binutils/binutils/0025-Fix-all-issues-in-b-ext-64.d.patch

@@ -0,0 +1,34 @@
+From ab2ea57b423cb06fcd0abfebbb7ad89f701012f9 Mon Sep 17 00:00:00 2001
+From: LevyHsu <admin@levyhsu.com>
+Date: Thu, 24 Jun 2021 16:21:29 +0800
+Subject: [PATCH 25/28] Fix all issues in b-ext-64.d
+
+---
+ gas/testsuite/gas/riscv/b-ext-64.d | 4 ++--
+ 1 file changed, 2 insertions(+), 2 deletions(-)
+
+diff --git a/gas/testsuite/gas/riscv/b-ext-64.d b/gas/testsuite/gas/riscv/b-ext-64.d
+index e27787a3f5..cab096cc78 100755
+--- a/gas/testsuite/gas/riscv/b-ext-64.d
++++ b/gas/testsuite/gas/riscv/b-ext-64.d
+@@ -52,7 +52,7 @@ Disassembly of section .text:
+ [ 	]+a4:[ 	]+0825c53b[ 	]+packw[ 	]+a0,a1,0x2
+ [ 	]+a8:[ 	]+4825c53b[ 	]+packuw[ 	]+a0,a1,0x2
+ [ 	]+ac:[ 	]+68c5d533[ 	]+grev[ 	]+a0,a1,a2
+-[ 	]+b0:[ 	]+6825d513[ 	]+rev2.n[ 	]+a0,a1,0x2
++[ 	]+b0:[ 	]+6825d513[ 	]+rev2.n[ 	]+a0,a1
+ [ 	]+b4:[ 	]+6825d53b[ 	]+grevw[ 	]+a0,a1,0x2
+ [ 	]+b8:[ 	]+6825d51b[ 	]+greviw[ 	]+a0,a1,0x2
+ [ 	]+bc:[ 	]+28c5d533[ 	]+gorc[ 	]+a0,a1,a2
+@@ -63,7 +63,7 @@ Disassembly of section .text:
+ [ 	]+d0:[ 	]+08259513[ 	]+zip2.b[ 	]+a0,a1
+ [ 	]+d4:[ 	]+0825953b[ 	]+shflw[ 	]+a0,a1,0x2
+ [ 	]+d8:[ 	]+08c5d533[ 	]+unshfl[ 	]+a0,a1,a2
+-[ 	]+dc:[ 	]+0825d513[ 	]+unzip2.b[ 	]+a0,a1,0x2
++[ 	]+dc:[ 	]+0825d513[ 	]+unzip2.b[ 	]+a0,a1
+ [ 	]+e0:[ 	]+0825d53b[ 	]+unshflw[ 	]+a0,a1,0x2
+ [ 	]+e4:[ 	]+28c5a533[ 	]+xperm.n[ 	]+a0,a1,a2
+ [ 	]+e8:[ 	]+28c5c533[ 	]+xperm.b[ 	]+a0,a1,a2
+-- 
+2.33.0
+

+ 34 - 0
recipes-devtools/binutils/binutils/0026-Apply-same-fix-on-b-ext.d.patch

@@ -0,0 +1,34 @@
+From 336cafb0229b2e1c36e98ff94c0fb38b391eab00 Mon Sep 17 00:00:00 2001
+From: LevyHsu <admin@levyhsu.com>
+Date: Thu, 24 Jun 2021 16:29:33 +0800
+Subject: [PATCH 26/28] Apply same fix on b-ext.d
+
+---
+ gas/testsuite/gas/riscv/b-ext.d | 8 ++++----
+ 1 file changed, 4 insertions(+), 4 deletions(-)
+
+diff --git a/gas/testsuite/gas/riscv/b-ext.d b/gas/testsuite/gas/riscv/b-ext.d
+index 82c22b3cdf..6a9245976e 100755
+--- a/gas/testsuite/gas/riscv/b-ext.d
++++ b/gas/testsuite/gas/riscv/b-ext.d
+@@ -37,13 +37,13 @@ Disassembly of section .text:
+ [ 	]+68:[ 	]+48c5c533[ 	]+packu[ 	]+a0,a1,a2
+ [ 	]+6c:[ 	]+08c5f533[ 	]+packh[ 	]+a0,a1,a2
+ [ 	]+70:[ 	]+68c5d533[ 	]+grev[ 	]+a0,a1,a2
+-[ 	]+74:[ 	]+6825d513[ 	]+grevi[ 	]+a0,a1,0x2
++[ 	]+74:[ 	]+6825d513[ 	]+rev2.n[ 	]+a0,a1
+ [ 	]+78:[ 	]+28c5d533[ 	]+gorc[ 	]+a0,a1,a2
+-[ 	]+7c:[ 	]+2825d513[ 	]+gorci[ 	]+a0,a1,0x2
++[ 	]+7c:[ 	]+2825d513[ 	]+orc2.n[ 	]+a0,a1
+ [ 	]+80:[ 	]+08c59533[ 	]+shfl[ 	]+a0,a1,a2
+-[ 	]+84:[ 	]+08259513[ 	]+shfli[ 	]+a0,a1,0x2
++[ 	]+84:[ 	]+08259513[ 	]+zip2.b[ 	]+a0,a1
+ [ 	]+88:[ 	]+08c5d533[ 	]+unshfl[ 	]+a0,a1,a2
+-[ 	]+8c:[ 	]+0825d513[ 	]+unshfli[ 	]+a0,a1,0x2
++[ 	]+8c:[ 	]+0825d513[ 	]+unzip2.b[ 	]+a0,a1
+ [ 	]+90:[ 	]+28c5a533[ 	]+xperm.n[ 	]+a0,a1,a2
+ [ 	]+94:[ 	]+28c5c533[ 	]+xperm.b[ 	]+a0,a1,a2
+ [ 	]+98:[ 	]+28c5e533[ 	]+xperm.h[ 	]+a0,a1,a2
+-- 
+2.33.0
+

+ 47 - 0
recipes-devtools/binutils/binutils/0027-remove-redundant-symbol.patch

@@ -0,0 +1,47 @@
+From 49e0e89c7b030c388472159c4111ff9b0fde3d5e Mon Sep 17 00:00:00 2001
+From: "eric.tang" <eric.tang@starfivetech.com>
+Date: Fri, 25 Jun 2021 08:58:17 +0800
+Subject: [PATCH 27/28] remove redundant symbol +
+
+Signed-off-by: eric.tang <eric.tang@starfivetech.com>
+---
+ gas/testsuite/gas/riscv/vector-insns.d | 24 ++++++++++++------------
+ 1 file changed, 12 insertions(+), 12 deletions(-)
+
+diff --git a/gas/testsuite/gas/riscv/vector-insns.d b/gas/testsuite/gas/riscv/vector-insns.d
+index 09c12ddfef..a264d1ee68 100644
+--- a/gas/testsuite/gas/riscv/vector-insns.d
++++ b/gas/testsuite/gas/riscv/vector-insns.d
+@@ -477,17 +477,17 @@ Disassembly of section .text:
+ [ 	]+[0-9a-f]+:[ 	]+9e2030d7[ 	]+vmv1r.v[ 	]+v1,v2
+ [ 	]+[0-9a-f]+:[ 	]+5208a257[ 	]+vid.v[ 	]+v4
+ [ 	]+[0-9a-f]+:[ 	]+5008a257[ 	]+vid.v[ 	]+v4,v0.t
+-[ 	]+[0-9a-f]+:[ 	]++02850187[     ]+vl1r.v[       ]+v3,\(a0\)
+-[ 	]+[0-9a-f]+:[ 	]++02850187[     ]+vl1r.v[       ]+v3,\(a0\)
+-[ 	]+[0-9a-f]+:[ 	]++02850187[     ]+vl1r.v[       ]+v3,\(a0\)
+-[ 	]+[0-9a-f]+:[ 	]++02850187[     ]+vl1r.v[       ]+v3,\(a0\)
+-[ 	]+[0-9a-f]+:[ 	]++02855187[     ]+vl1re16.v[    ]+v3,\(a0\)
+-[ 	]+[0-9a-f]+:[ 	]++02855187[     ]+vl1re16.v[    ]+v3,\(a0\)
+-[ 	]+[0-9a-f]+:[ 	]++02856187[     ]+vl1re32.v[    ]+v3,\(a0\)
+-[ 	]+[0-9a-f]+:[ 	]++02856187[     ]+vl1re32.v[    ]+v3,\(a0\)
+-[ 	]+[0-9a-f]+:[ 	]++02857187[     ]+vl1re64.v[    ]+v3,\(a0\)
+-[ 	]+[0-9a-f]+:[ 	]++02857187[     ]+vl1re64.v[    ]+v3,\(a0\)
+-[ 	]+[0-9a-f]+:[ 	]++028581a7[     ]+vs1r.v[       ]+v3,\(a1\)
+-[ 	]+[0-9a-f]+:[ 	]++028581a7[     ]+vs1r.v[       ]+v3,\(a1\)
++[ 	]+[0-9a-f]+:[ 	]+02850187[     ]+vl1r.v[       ]+v3,\(a0\)
++[ 	]+[0-9a-f]+:[ 	]+02850187[     ]+vl1r.v[       ]+v3,\(a0\)
++[ 	]+[0-9a-f]+:[ 	]+02850187[     ]+vl1r.v[       ]+v3,\(a0\)
++[ 	]+[0-9a-f]+:[ 	]+02850187[     ]+vl1r.v[       ]+v3,\(a0\)
++[ 	]+[0-9a-f]+:[ 	]+02855187[     ]+vl1re16.v[    ]+v3,\(a0\)
++[ 	]+[0-9a-f]+:[ 	]+02855187[     ]+vl1re16.v[    ]+v3,\(a0\)
++[ 	]+[0-9a-f]+:[ 	]+02856187[     ]+vl1re32.v[    ]+v3,\(a0\)
++[ 	]+[0-9a-f]+:[ 	]+02856187[     ]+vl1re32.v[    ]+v3,\(a0\)
++[ 	]+[0-9a-f]+:[ 	]+02857187[     ]+vl1re64.v[    ]+v3,\(a0\)
++[ 	]+[0-9a-f]+:[ 	]+02857187[     ]+vl1re64.v[    ]+v3,\(a0\)
++[ 	]+[0-9a-f]+:[ 	]+028581a7[     ]+vs1r.v[       ]+v3,\(a1\)
++[ 	]+[0-9a-f]+:[ 	]+028581a7[     ]+vs1r.v[       ]+v3,\(a1\)
+ 
+ 
+-- 
+2.33.0
+

+ 87 - 0
recipes-devtools/binutils/binutils/0028-solved-vector-insns-test-failed-n.patch

@@ -0,0 +1,87 @@
+From 9ede311a493d8d49c3c3aa5aa736dfcfc6bbabe3 Mon Sep 17 00:00:00 2001
+From: "eric.tang" <eric.tang@starfivetech.com>
+Date: Fri, 9 Jul 2021 09:30:28 +0800
+Subject: [PATCH 28/28] solved vector-insns test failed\n
+
+Signed-off-by: eric.tang <eric.tang@starfivetech.com>
+---
+ gas/testsuite/gas/riscv/vector-insns.d | 24 ++++++++++-----------
+ gas/testsuite/gas/riscv/vector-insns.s | 30 +++++++++++++-------------
+ 2 files changed, 27 insertions(+), 27 deletions(-)
+
+diff --git a/gas/testsuite/gas/riscv/vector-insns.d b/gas/testsuite/gas/riscv/vector-insns.d
+index a264d1ee68..3e1a99bb39 100644
+--- a/gas/testsuite/gas/riscv/vector-insns.d
++++ b/gas/testsuite/gas/riscv/vector-insns.d
+@@ -477,17 +477,17 @@ Disassembly of section .text:
+ [ 	]+[0-9a-f]+:[ 	]+9e2030d7[ 	]+vmv1r.v[ 	]+v1,v2
+ [ 	]+[0-9a-f]+:[ 	]+5208a257[ 	]+vid.v[ 	]+v4
+ [ 	]+[0-9a-f]+:[ 	]+5008a257[ 	]+vid.v[ 	]+v4,v0.t
+-[ 	]+[0-9a-f]+:[ 	]+02850187[     ]+vl1r.v[       ]+v3,\(a0\)
+-[ 	]+[0-9a-f]+:[ 	]+02850187[     ]+vl1r.v[       ]+v3,\(a0\)
+-[ 	]+[0-9a-f]+:[ 	]+02850187[     ]+vl1r.v[       ]+v3,\(a0\)
+-[ 	]+[0-9a-f]+:[ 	]+02850187[     ]+vl1r.v[       ]+v3,\(a0\)
+-[ 	]+[0-9a-f]+:[ 	]+02855187[     ]+vl1re16.v[    ]+v3,\(a0\)
+-[ 	]+[0-9a-f]+:[ 	]+02855187[     ]+vl1re16.v[    ]+v3,\(a0\)
+-[ 	]+[0-9a-f]+:[ 	]+02856187[     ]+vl1re32.v[    ]+v3,\(a0\)
+-[ 	]+[0-9a-f]+:[ 	]+02856187[     ]+vl1re32.v[    ]+v3,\(a0\)
+-[ 	]+[0-9a-f]+:[ 	]+02857187[     ]+vl1re64.v[    ]+v3,\(a0\)
+-[ 	]+[0-9a-f]+:[ 	]+02857187[     ]+vl1re64.v[    ]+v3,\(a0\)
+-[ 	]+[0-9a-f]+:[ 	]+028581a7[     ]+vs1r.v[       ]+v3,\(a1\)
+-[ 	]+[0-9a-f]+:[ 	]+028581a7[     ]+vs1r.v[       ]+v3,\(a1\)
++[ 	]+[0-9a-f]+:[ 	]+02850187[ 	]+vl1r.v[ 	]+v3,\(a0\)
++[ 	]+[0-9a-f]+:[ 	]+02850187[ 	]+vl1r.v[ 	]+v3,\(a0\)
++[ 	]+[0-9a-f]+:[ 	]+02850187[ 	]+vl1r.v[ 	]+v3,\(a0\)
++[ 	]+[0-9a-f]+:[ 	]+02850187[ 	]+vl1r.v[ 	]+v3,\(a0\)
++[ 	]+[0-9a-f]+:[ 	]+02855187[ 	]+vl1re16.v[ 	]+v3,\(a0\)
++[ 	]+[0-9a-f]+:[ 	]+02855187[ 	]+vl1re16.v[ 	]+v3,\(a0\)
++[ 	]+[0-9a-f]+:[ 	]+02856187[ 	]+vl1re32.v[ 	]+v3,\(a0\)
++[ 	]+[0-9a-f]+:[ 	]+02856187[ 	]+vl1re32.v[ 	]+v3,\(a0\)
++[ 	]+[0-9a-f]+:[ 	]+02857187[ 	]+vl1re64.v[ 	]+v3,\(a0\)
++[ 	]+[0-9a-f]+:[ 	]+02857187[ 	]+vl1re64.v[ 	]+v3,\(a0\)
++[ 	]+[0-9a-f]+:[ 	]+028581a7[ 	]+vs1r.v[ 	]+v3,\(a1\)
++[ 	]+[0-9a-f]+:[ 	]+028581a7[ 	]+vs1r.v[ 	]+v3,\(a1\)
+ 
+ 
+diff --git a/gas/testsuite/gas/riscv/vector-insns.s b/gas/testsuite/gas/riscv/vector-insns.s
+index 81ef661af9..c1e826007f 100644
+--- a/gas/testsuite/gas/riscv/vector-insns.s
++++ b/gas/testsuite/gas/riscv/vector-insns.s
+@@ -518,19 +518,19 @@
+ 	vrgather.vi v4, v8, 31, v0.t
+ 
+ 	vcompress.vm v4, v8, v12
+-        vmv1r.v v1, v2
+-        vid.v v4
+-        vid.v v4, v0.t
+-        vl1r.v v3, (a0)
+-        vl1r.v v3, 0(a0)
+-        vl1re8.v v3, (a0)
+-        vl1re8.v v3, 0(a0)
+-        vl1re16.v v3, (a0)
+-        vl1re16.v v3, 0(a0)
+-        vl1re32.v v3, (a0)
+-        vl1re32.v v3, 0(a0)
+-        vl1re64.v v3, (a0)
+-        vl1re64.v v3, 0(a0)
+-        vs1r.v v3, (a1)
+-        vs1r.v v3, 0(a1)
++	vmv1r.v v1, v2
++	vid.v v4
++	vid.v v4, v0.t
++	vl1r.v v3, (a0)
++	vl1r.v v3, 0(a0)
++	vl1re8.v v3, (a0)
++	vl1re8.v v3, 0(a0)
++	vl1re16.v v3, (a0)
++	vl1re16.v v3, 0(a0)
++	vl1re32.v v3, (a0)
++	vl1re32.v v3, 0(a0)
++	vl1re64.v v3, (a0)
++	vl1re64.v v3, 0(a0)
++	vs1r.v v3, (a1)
++	vs1r.v v3, 0(a1)
+ 
+-- 
+2.33.0
+

+ 32 - 5
recipes-devtools/binutils/binutils_2.36.bbappend

@@ -1,11 +1,38 @@
-SRCBRANCH = "sifive-rvv-1.0.x-zfh-rvb"
+FILESEXTRAPATHS_prepend := "${THISDIR}/binutils:"
+SRCBRANCH = "riscv-binutils-2.36.1"
 
-SRCREV = "75d2236ce26a3048f52bbd5186602e27bd635e2b"
+SRCREV = "f35674005e609660f5f45005a9e095541ca4c5fe"
 
-BINUTILS_GIT_URI = "git://github.com/sifive/riscv-binutils-gdb.git;branch=${SRCBRANCH};protocol=git"
+BINUTILS_GIT_URI = "git://github.com/riscv/riscv-binutils-gdb.git;branch=${SRCBRANCH};protocol=git"
 
 SRC_URI = "\
       ${BINUTILS_GIT_URI} \
-      file://0005-Point-scripts-location-to-libdir.patch \
+      file://0001-resolve-bug-1-unsupported-zvmo-extension.patch \
+      file://0002-Add-support-for-B-extension.patch \
+      file://0003-merge-rvv1.0-branch.patch \
+      file://0005-support-Dubhe-V-extension.patch \
+      file://0005-Point-scripts-location-to-libdir.patch \ 
+      file://0006-Add-pseudo-instructions-for-B-extension.patch \
+      file://0007-Rename-bdep-to-bdecompress.patch \
+      file://0008-RISCV-Add-support-for-bcompress.patch \
+      file://0009-RISCV-Coding-bug-Fix-for-FSRW.patch \
+      file://0010-RISCV-Coding-bug-Fix-for-FSRIW.patch \
+      file://0011-RISCV-Fix-coding-for-un-zip-2-4-8-16-n-b-h-w.patch \
+      file://0012-update-bitmap-version-number-from-0.93-to-0.94.patch \
+      file://0013-Fix-gas-test-cases.patch \
+      file://0014-resolve-crash-issue-when-objdump-encounter-unrecogni.patch \
+      file://0015-Remove-MASK_SHAMT2.patch \
+      file://0016-Fix-internal-error-undefined-modifier-r.patch \
+      file://0017-Fix-coding-for-Bcompressw.patch \
+      file://0018-Fix-zip2.b-testcase.patch \
+      file://0019-Fix-orc2.n-testcase.patch \
+      file://0020-Fix-rev2.n-test-case.patch \
+      file://0021-Fix-testcase-for-zip2.b-and-rev2.n.patch \
+      file://0022-Fix-r-operands-type-from-fpr-to-gpr.patch \
+      file://0023-support-vid-vmv1r-vl1r-vs1r-instruction.patch \
+      file://0024-add-vid-instruction-support.patch \
+      file://0025-Fix-all-issues-in-b-ext-64.d.patch \
+      file://0026-Apply-same-fix-on-b-ext.d.patch \
+      file://0027-remove-redundant-symbol.patch \
+      file://0028-solved-vector-insns-test-failed-n.patch \
 "
-

+ 0 - 23
recipes-devtools/gcc/files/0001-Fix-compilation-issue-when-building-multilib.patch

@@ -1,23 +0,0 @@
-From 652ad832889d6a5516defe42b3ab8ec6d9b43eb8 Mon Sep 17 00:00:00 2001
-From: Tien Hock Loh <tienhock.loh@starfivetech.com>
-Date: Thu, 5 Aug 2021 05:08:09 +0000
-Subject: [PATCH 1/1] Fix compilation issue when building multilib
-
-Signed-off-by: Tien Hock Loh <tienhock.loh@starfivetech.com>
----
- gcc/common/common-targhooks.h | 1 +
- 1 file changed, 1 insertion(+)
-
-diff --git a/gcc/common/common-targhooks.h b/gcc/common/common-targhooks.h
-index 66a54c2cb9c..3af6446db03 100644
---- a/gcc/common/common-targhooks.h
-+++ b/gcc/common/common-targhooks.h
-@@ -32,4 +32,5 @@ extern vec<const char *> default_get_valid_option_values (int, const char *);
- 
- extern const struct default_options empty_optimization_table[];
- 
-+extern const char *default_compute_multilib(const struct switchstr *, int, const char *multilib, const char *, const char *, const char *, const char *, const char *);
- #endif
--- 
-2.25.1
-

+ 185 - 0
recipes-devtools/gcc/files/0060-Initial-support-for-0.94-Bitmap.patch

@@ -0,0 +1,185 @@
+From bdbe5285f467bf85dba7fa1413738dd26d78210f Mon Sep 17 00:00:00 2001
+From: LevyHsu <admin@levyhsu.com>
+Date: Fri, 9 Jul 2021 16:28:04 +0800
+Subject: [PATCH 60/61] Initial support for 0.94 Bitmap
+
+---
+ gcc/common/common-targhooks.h          |  9 ++-
+ gcc/common/config/riscv/riscv-common.c | 22 ++++----
+ gcc/config/riscv/bitmanip.md           | 76 --------------------------
+ gcc/config/riscv/riscv.c               |  3 +-
+ 4 files changed, 20 insertions(+), 90 deletions(-)
+
+diff --git a/gcc/common/common-targhooks.h b/gcc/common/common-targhooks.h
+index 66a54c2cb9c..0c1c326b74e 100644
+--- a/gcc/common/common-targhooks.h
++++ b/gcc/common/common-targhooks.h
+@@ -31,5 +31,12 @@ extern bool default_target_handle_option (struct gcc_options *,
+ extern vec<const char *> default_get_valid_option_values (int, const char *);
+ 
+ extern const struct default_options empty_optimization_table[];
+-
++extern const char *default_compute_multilib(const struct switchstr *,
++  					  int,
++  					  const char *multilib,
++  					  const char *,
++  					  const char *,
++  					  const char *,
++   					  const char *,
++  					  const char *);
+ #endif
+diff --git a/gcc/common/config/riscv/riscv-common.c b/gcc/common/config/riscv/riscv-common.c
+index 11180307064..a2a9b2cc3ab 100644
+--- a/gcc/common/config/riscv/riscv-common.c
++++ b/gcc/common/config/riscv/riscv-common.c
+@@ -116,17 +116,17 @@ static const struct riscv_ext_version riscv_ext_version_table[] =
+   {"zvlsseg", ISA_SPEC_CLASS_NONE, 1, 0},
+   {"zvqmac",  ISA_SPEC_CLASS_NONE, 1, 0},
+ 
+-  {"b",   ISA_SPEC_CLASS_NONE, 0, 93},
+-  {"zba", ISA_SPEC_CLASS_NONE, 0, 93},
+-  {"zbb", ISA_SPEC_CLASS_NONE, 0, 93},
+-  {"zbc", ISA_SPEC_CLASS_NONE, 0, 93},
+-  {"zbe", ISA_SPEC_CLASS_NONE, 0, 93},
+-  {"zbf", ISA_SPEC_CLASS_NONE, 0, 93},
+-  {"zbr", ISA_SPEC_CLASS_NONE, 0, 93},
+-  {"zbm", ISA_SPEC_CLASS_NONE, 0, 93},
+-  {"zbs", ISA_SPEC_CLASS_NONE, 0, 93},
+-  {"zbt", ISA_SPEC_CLASS_NONE, 0, 93},
+-  {"zbp", ISA_SPEC_CLASS_NONE, 0, 93},
++  {"b",   ISA_SPEC_CLASS_NONE, 0, 94},
++  {"zba", ISA_SPEC_CLASS_NONE, 0, 94},
++  {"zbb", ISA_SPEC_CLASS_NONE, 0, 94},
++  {"zbc", ISA_SPEC_CLASS_NONE, 0, 94},
++  {"zbe", ISA_SPEC_CLASS_NONE, 0, 94},
++  {"zbf", ISA_SPEC_CLASS_NONE, 0, 94},
++  {"zbr", ISA_SPEC_CLASS_NONE, 0, 94},
++  {"zbm", ISA_SPEC_CLASS_NONE, 0, 94},
++  {"zbs", ISA_SPEC_CLASS_NONE, 0, 94},
++  {"zbt", ISA_SPEC_CLASS_NONE, 0, 94},
++  {"zbp", ISA_SPEC_CLASS_NONE, 0, 94},
+ 
+   /* Terminate the list.  */
+   {NULL, ISA_SPEC_CLASS_NONE, 0, 0}
+diff --git a/gcc/config/riscv/bitmanip.md b/gcc/config/riscv/bitmanip.md
+index 3cd6bdc2de1..3026883fc0e 100644
+--- a/gcc/config/riscv/bitmanip.md
++++ b/gcc/config/riscv/bitmanip.md
+@@ -153,41 +153,6 @@
+   "bseti\t%0,%1,%S2"
+   [(set_attr "type" "bitmanip")])
+ 
+-(define_insn "*bsetw"
+-  [(set (match_operand:DI 0 "register_operand" "=r")
+-	(sign_extend:DI
+-	 (subreg:SI
+-	  (ior:DI (subreg:DI
+-		   (ashift:SI (const_int 1)
+-			      (match_operand:QI 2 "register_operand" "r")) 0)
+-		  (match_operand:DI 1 "register_operand" "r")) 0)))]
+-  "TARGET_64BIT && TARGET_ZBS"
+-  "bsetw\t%0,%1,%2"
+-  [(set_attr "type" "bitmanip")])
+-
+-(define_insn "*bsetw_mask"
+-  [(set (match_operand:DI 0 "register_operand" "=r")
+-	(sign_extend:DI
+-	 (subreg:SI
+-	  (ior:DI (subreg:DI
+-		   (ashift:SI
+-		    (const_int 1)
+-		    (subreg:QI
+-		     (and:DI (match_operand:DI 2 "register_operand" "r")
+-			     (match_operand 3 "const31_operand" "i")) 0)) 0)
+-		  (match_operand:DI 1 "register_operand" "r")) 0)))]
+-  "TARGET_64BIT && TARGET_ZBS"
+-  "bsetw\t%0,%1,%2"
+-  [(set_attr "type" "bitmanip")])
+-
+-(define_insn "*bsetiw"
+-  [(set (match_operand:DI 0 "register_operand" "=r")
+-	(ior:DI (sign_extend:DI (match_operand:SI 1 "register_operand" "r"))
+-		(match_operand 2 "single_bit_mask_operand" "i")))]
+-  "TARGET_64BIT && TARGET_ZBS"
+-  "bsetiw\t%0,%1,%S2"
+-  [(set_attr "type" "bitmanip")])
+-
+ (define_insn "*bclr<mode>"
+   [(set (match_operand:X 0 "register_operand" "=r")
+ 	(and:X (rotate:X (const_int -2)
+@@ -205,27 +170,6 @@
+   "bclri\t%0,%1,%T2"
+   [(set_attr "type" "bitmanip")])
+ 
+-(define_insn "*bclrw"
+-  [(set (match_operand:DI 0 "register_operand" "=r")
+-	(sign_extend:DI
+-	 (subreg:SI
+-	  (and:DI
+-	   (not:DI (subreg:DI
+-		    (ashift:SI (const_int 1)
+-			       (match_operand:QI 2 "register_operand" "r")) 0))
+-	   (match_operand:DI 1 "register_operand" "r")) 0)))]
+-  "TARGET_64BIT && TARGET_ZBS"
+-  "bclrw\t%0,%1,%2"
+-  [(set_attr "type" "bitmanip")])
+-
+-(define_insn "*bclriw"
+-  [(set (match_operand:DI 0 "register_operand" "=r")
+-	(and:DI (sign_extend:DI (match_operand:SI 1 "register_operand" "r"))
+-		(match_operand 2 "not_single_bit_mask_operand" "i")))]
+-  "TARGET_64BIT && TARGET_ZBS"
+-  "bclriw\t%0,%1,%T2"
+-  [(set_attr "type" "bitmanip")])
+-
+ (define_insn "*binv<mode>"
+   [(set (match_operand:X 0 "register_operand" "=r")
+ 	(xor:X (ashift:X (const_int 1)
+@@ -243,26 +187,6 @@
+   "binvi\t%0,%1,%S2"
+   [(set_attr "type" "bitmanip")])
+ 
+-(define_insn "*binvw"
+-  [(set (match_operand:DI 0 "register_operand" "=r")
+-	(sign_extend:DI
+-	 (subreg:SI
+-	  (xor:DI (subreg:DI
+-		   (ashift:SI (const_int 1)
+-			      (match_operand:QI 2 "register_operand" "r")) 0)
+-		  (match_operand:DI 1 "register_operand" "r")) 0)))]
+-  "TARGET_64BIT && TARGET_ZBS"
+-  "binvw\t%0,%1,%2"
+-  [(set_attr "type" "bitmanip")])
+-
+-(define_insn "*binviw"
+-  [(set (match_operand:DI 0 "register_operand" "=r")
+-	(xor:DI (sign_extend:DI (match_operand:SI 1 "register_operand" "r"))
+-		(match_operand 2 "single_bit_mask_operand" "i")))]
+-  "TARGET_64BIT && TARGET_ZBS"
+-  "binviw\t%0,%1,%S2"
+-  [(set_attr "type" "bitmanip")])
+-
+ (define_insn "*bext<mode>"
+   [(set (match_operand:X 0 "register_operand" "=r")
+ 	(zero_extract:X (match_operand:X 1 "register_operand" "r")
+diff --git a/gcc/config/riscv/riscv.c b/gcc/config/riscv/riscv.c
+index 0bbeeb51f2f..a31e97be399 100644
+--- a/gcc/config/riscv/riscv.c
++++ b/gcc/config/riscv/riscv.c
+@@ -2342,12 +2342,11 @@ riscv_output_move (rtx dest, rtx src)
+ 
+ 	  if (TARGET_64BIT && TARGET_ZBS
+ 	      && SINGLE_BIT_MASK_OPERAND (INTVAL (src)))
+-	    return "sbseti\t%0,zero,%S1";
++	    return "bseti\t%0,zero,%S1";
+ 
+ 	  /* Should never reach here.  */
+ 	  abort ();
+ 	}
+-
+       if (src_code == HIGH)
+ 	return "lui\t%0,%h1";
+ 
+-- 
+2.33.0
+

+ 47 - 0
recipes-devtools/gcc/files/0061-Remove-unsupported-bext.w-in-gcc.patch

@@ -0,0 +1,47 @@
+From 31a09167fdc4b53e618d3ac2639767bf5eb431f8 Mon Sep 17 00:00:00 2001
+From: LevyHsu <admin@levyhsu.com>
+Date: Fri, 16 Jul 2021 10:29:25 +0800
+Subject: [PATCH 61/61] Remove unsupported bext.w in gcc
+
+Followiing code was removed to prevent bextw being generated:
+
+
+(define_insn "*bextw"
+  [(set (match_operand:DI 0 "register_operand" "=r")
+	(and:DI
+	 (subreg:DI
+	  (lshiftrt:SI (match_operand:SI 1 "register_operand" "r")
+		       (match_operand:QI 2 "register_operand" "r")) 0)
+	 (const_int 1)))]
+  "TARGET_64BIT && TARGET_ZBS"
+  "bextw\t%0,%1,%2"
+  [(set_attr "type" "bitmanip")])
+---
+ gcc/config/riscv/bitmanip.md | 11 -----------
+ 1 file changed, 11 deletions(-)
+
+diff --git a/gcc/config/riscv/bitmanip.md b/gcc/config/riscv/bitmanip.md
+index 3026883fc0e..930549a90fc 100644
+--- a/gcc/config/riscv/bitmanip.md
++++ b/gcc/config/riscv/bitmanip.md
+@@ -206,17 +206,6 @@
+   "bexti\t%0,%1,%2"
+   [(set_attr "type" "bitmanip")])
+ 
+-(define_insn "*bextw"
+-  [(set (match_operand:DI 0 "register_operand" "=r")
+-	(and:DI
+-	 (subreg:DI
+-	  (lshiftrt:SI (match_operand:SI 1 "register_operand" "r")
+-		       (match_operand:QI 2 "register_operand" "r")) 0)
+-	 (const_int 1)))]
+-  "TARGET_64BIT && TARGET_ZBS"
+-  "bextw\t%0,%1,%2"
+-  [(set_attr "type" "bitmanip")])
+-
+ ;;; ??? s[lr]o*
+ 
+ (define_insn "rotrsi3"
+-- 
+2.33.0
+

+ 1 - 1
recipes-devtools/gcc/gcc-cross-canadian_10.2.bbappend

@@ -1 +1 @@
-EXTRA_OECONF_append_riscv64 = " --with-arch=rv64gcv_zba_zbb --with-cmodel=medany"
+EXTRA_OECONF_append_riscv64 = " --with-arch=rv64gcb CFLAGS_FOR_TARGET="-O2 -mcmodel=medany"  CXXFLAGS_FOR_TARGET="-O2 -mcmodel=medany""

+ 1 - 1
recipes-devtools/gcc/gcc-cross_10.2.bbappend

@@ -1 +1 @@
-EXTRA_OECONF_append_riscv64 = " --with-arch=rv64gcv_zba_zbb --with-cmodel=medany"
+EXTRA_OECONF_append_riscv64 = " --with-arch=rv64gcb CFLAGS_FOR_TARGET="-O2 -mcmodel=medany"  CXXFLAGS_FOR_TARGET="-O2 -mcmodel=medany""

+ 1 - 1
recipes-devtools/gcc/gcc-crosssdk_10.2.bbappend

@@ -1 +1 @@
-EXTRA_OECONF_append_riscv64 = " --with-arch=rv64gcv_zba_zbb --with-cmodel=medany"
+EXTRA_OECONF_append_riscv64 = " --with-arch=rv64gcb CFLAGS_FOR_TARGET="-O2 -mcmodel=medany"  CXXFLAGS_FOR_TARGET="-O2 -mcmodel=medany""

+ 4 - 2
recipes-devtools/gcc/gcc-source_10.2.bbappend

@@ -59,7 +59,9 @@ file://0057-Fix-riscv_check_other_cond-for-non-multi-lib-build.patch \
 file://0058-Add-more-comment-for-riscv_check_other_cond.patch \
 file://0059-Do-not-install-riscv_vector.h-and-riscv_vector_itr.h.patch \
 file://0060-Avoid-to-use-same-temp-register-to-adjust-stack-poin.patch \
+file://0060-Initial-support-for-0.94-Bitmap.patch \
+file://0061-Remove-unsupported-bext.w-in-gcc.patch \
 file://0001-Yocto-patch-for-arch-canonicalize-to-use-python3.patch \
-file://0001-Fix-compilation-issue-when-building-multilib.patch \
 "
-EXTRA_OECONF_append_riscv64 = " --with-arch=rv64gcv_zba_zbb --with-cmodel=medany"
+
+EXTRA_OECONF_append_riscv64 = " --with-arch=rv64gcb CFLAGS_FOR_TARGET="-O2 -mcmodel=medany"  CXXFLAGS_FOR_TARGET="-O2 -mcmodel=medany""