0016-Fix-internal-error-undefined-modifier-r.patch 1.8 KB

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  1. From 8e76ea22bbdb344e224c9c7bd795c52012a08cf0 Mon Sep 17 00:00:00 2001
  2. From: LevyHsu <admin@levyhsu.com>
  3. Date: Thu, 24 Jun 2021 14:59:01 +0800
  4. Subject: [PATCH 16/28] Fix internal error, undefined modifier (r)
  5. This bug is locate to this commit:
  6. https://github.com/pz9115/riscv-binutils-gdb/commit/85dd8e06472e4cee3bd7d78cb820df8a6c311e3d
  7. Where operands case 'r' was accidentally put under
  8. case 'C': /* RVC */
  9. switch (*++d)
  10. {...}
  11. which caused print_insn_args() to
  12. print (info->stream, _("# internal error, undefined modifier (V%c)"),
  13. *d);
  14. ---
  15. gas/config/tc-riscv.c | 2 +-
  16. opcodes/riscv-dis.c | 3 ++-
  17. 2 files changed, 3 insertions(+), 2 deletions(-)
  18. diff --git a/gas/config/tc-riscv.c b/gas/config/tc-riscv.c
  19. index 405ef3278a..1cc76db7cc 100644
  20. --- a/gas/config/tc-riscv.c
  21. +++ b/gas/config/tc-riscv.c
  22. @@ -1044,7 +1044,7 @@ validate_riscv_insn (const struct riscv_opcode *opc, int length)
  23. case 'm': USE_BITS (OP_MASK_RM, OP_SH_RM); break;
  24. case 's': USE_BITS (OP_MASK_RS1, OP_SH_RS1); break;
  25. case 't': USE_BITS (OP_MASK_RS2, OP_SH_RS2); break;
  26. - case 'r': USE_BITS (OP_MASK_RS3, OP_SH_RS3); break;
  27. + case 'r': USE_BITS (OP_MASK_RS3, OP_SH_RS3); break;
  28. case 'P': USE_BITS (OP_MASK_PRED, OP_SH_PRED); break;
  29. case 'Q': USE_BITS (OP_MASK_SUCC, OP_SH_SUCC); break;
  30. case 'o':
  31. diff --git a/opcodes/riscv-dis.c b/opcodes/riscv-dis.c
  32. index 065ea75b82..e3ee7b9d9b 100644
  33. --- a/opcodes/riscv-dis.c
  34. +++ b/opcodes/riscv-dis.c
  35. @@ -370,7 +370,8 @@ print_insn_args (const char *d, insn_t l, bfd_vma pc, disassemble_info *info)
  36. case 'D':
  37. print (info->stream, "%s", riscv_fpr_names[rd]);
  38. break;
  39. -
  40. +
  41. + case 'r':
  42. case 'R':
  43. print (info->stream, "%s", riscv_fpr_names[EXTRACT_OPERAND (RS3, l)]);
  44. break;
  45. --
  46. 2.33.0