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- From 8e76ea22bbdb344e224c9c7bd795c52012a08cf0 Mon Sep 17 00:00:00 2001
- From: LevyHsu <admin@levyhsu.com>
- Date: Thu, 24 Jun 2021 14:59:01 +0800
- Subject: [PATCH 16/28] Fix internal error, undefined modifier (r)
- This bug is locate to this commit:
- https://github.com/pz9115/riscv-binutils-gdb/commit/85dd8e06472e4cee3bd7d78cb820df8a6c311e3d
- Where operands case 'r' was accidentally put under
- case 'C': /* RVC */
- switch (*++d)
- {...}
- which caused print_insn_args() to
- print (info->stream, _("# internal error, undefined modifier (V%c)"),
- *d);
- ---
- gas/config/tc-riscv.c | 2 +-
- opcodes/riscv-dis.c | 3 ++-
- 2 files changed, 3 insertions(+), 2 deletions(-)
- diff --git a/gas/config/tc-riscv.c b/gas/config/tc-riscv.c
- index 405ef3278a..1cc76db7cc 100644
- --- a/gas/config/tc-riscv.c
- +++ b/gas/config/tc-riscv.c
- @@ -1044,7 +1044,7 @@ validate_riscv_insn (const struct riscv_opcode *opc, int length)
- case 'm': USE_BITS (OP_MASK_RM, OP_SH_RM); break;
- case 's': USE_BITS (OP_MASK_RS1, OP_SH_RS1); break;
- case 't': USE_BITS (OP_MASK_RS2, OP_SH_RS2); break;
- - case 'r': USE_BITS (OP_MASK_RS3, OP_SH_RS3); break;
- + case 'r': USE_BITS (OP_MASK_RS3, OP_SH_RS3); break;
- case 'P': USE_BITS (OP_MASK_PRED, OP_SH_PRED); break;
- case 'Q': USE_BITS (OP_MASK_SUCC, OP_SH_SUCC); break;
- case 'o':
- diff --git a/opcodes/riscv-dis.c b/opcodes/riscv-dis.c
- index 065ea75b82..e3ee7b9d9b 100644
- --- a/opcodes/riscv-dis.c
- +++ b/opcodes/riscv-dis.c
- @@ -370,7 +370,8 @@ print_insn_args (const char *d, insn_t l, bfd_vma pc, disassemble_info *info)
- case 'D':
- print (info->stream, "%s", riscv_fpr_names[rd]);
- break;
- -
- +
- + case 'r':
- case 'R':
- print (info->stream, "%s", riscv_fpr_names[EXTRACT_OPERAND (RS3, l)]);
- break;
- --
- 2.33.0
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