0023-support-vid-vmv1r-vl1r-vs1r-instruction.patch 4.6 KB

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  1. From 392661532fdf03c24d3b3715145f655b5c259986 Mon Sep 17 00:00:00 2001
  2. From: "eric.tang" <eric.tang@starfivetech.com>
  3. Date: Thu, 24 Jun 2021 11:40:56 +0800
  4. Subject: [PATCH 23/28] support vid vmv1r vl1r vs1r instruction
  5. Signed-off-by: eric.tang <eric.tang@starfivetech.com>
  6. ---
  7. gas/testsuite/gas/riscv/vector-insns.d | 13 +++++++++++++
  8. gas/testsuite/gas/riscv/vector-insns.s | 13 +++++++++++++
  9. opcodes/riscv-opc.c | 10 ++++++++++
  10. 3 files changed, 36 insertions(+)
  11. diff --git a/gas/testsuite/gas/riscv/vector-insns.d b/gas/testsuite/gas/riscv/vector-insns.d
  12. index fe6a95cba5..d8d6608fb3 100644
  13. --- a/gas/testsuite/gas/riscv/vector-insns.d
  14. +++ b/gas/testsuite/gas/riscv/vector-insns.d
  15. @@ -98,6 +98,18 @@ Disassembly of section .text:
  16. [ ]+[0-9a-f]+:[ ]+0ec57227[ ]+vsoxei64.v[ ]+v4,\(a0\),v12
  17. [ ]+[0-9a-f]+:[ ]+0ec57227[ ]+vsoxei64.v[ ]+v4,\(a0\),v12
  18. [ ]+[0-9a-f]+:[ ]+0cc57227[ ]+vsoxei64.v[ ]+v4,\(a0\),v12,v0.t
  19. +[ ]+[0-9a-f]+:[ ]+02850187[ ]+vl1r.v[ ]+v3,\(a0\)
  20. +[ ]+[0-9a-f]+:[ ]+02850187[ ]+vl1r.v[ ]+v3,\(a0\)
  21. +[ ]+[0-9a-f]+:[ ]+02850187[ ]+vl1r.v[ ]+v3,\(a0\)
  22. +[ ]+[0-9a-f]+:[ ]+02850187[ ]+vl1r.v[ ]+v3,\(a0\)
  23. +[ ]+[0-9a-f]+:[ ]+02855187[ ]+vl1re16.v[ ]+v3,\(a0\)
  24. +[ ]+[0-9a-f]+:[ ]+02855187[ ]+vl1re16.v[ ]+v3,\(a0\)
  25. +[ ]+[0-9a-f]+:[ ]+02856187[ ]+vl1re32.v[ ]+v3,\(a0\)
  26. +[ ]+[0-9a-f]+:[ ]+02856187[ ]+vl1re32.v[ ]+v3,\(a0\)
  27. +[ ]+[0-9a-f]+:[ ]+02857187[ ]+vl1re64.v[ ]+v3,\(a0\)
  28. +[ ]+[0-9a-f]+:[ ]+02857187[ ]+vl1re64.v[ ]+v3,\(a0\)
  29. +[ ]+[0-9a-f]+:[ ]+028581a7[ ]+vs1r.v[ ]+v3,\(a1\)
  30. +[ ]+[0-9a-f]+:[ ]+028581a7[ ]+vs1r.v[ ]+v3,\(a1\)
  31. [ ]+[0-9a-f]+:[ ]+0e804257[ ]+vneg.v[ ]+v4,v8
  32. [ ]+[0-9a-f]+:[ ]+0c804257[ ]+vneg.v[ ]+v4,v8,v0.t
  33. [ ]+[0-9a-f]+:[ ]+02860257[ ]+vadd.vv[ ]+v4,v8,v12
  34. @@ -474,3 +486,4 @@ Disassembly of section .text:
  35. [ ]+[0-9a-f]+:[ ]+30803257[ ]+vrgather.vi[ ]+v4,v8,0,v0.t
  36. [ ]+[0-9a-f]+:[ ]+308fb257[ ]+vrgather.vi[ ]+v4,v8,31,v0.t
  37. [ ]+[0-9a-f]+:[ ]+5e862257[ ]+vcompress.vm[ ]+v4,v8,v12
  38. +[ ]+[0-9a-f]+:[ ]+9e2030d7[ ]+vmv1r.v[ ]+v1,v2
  39. diff --git a/gas/testsuite/gas/riscv/vector-insns.s b/gas/testsuite/gas/riscv/vector-insns.s
  40. index a6f906e416..5cb7c7a5e2 100644
  41. --- a/gas/testsuite/gas/riscv/vector-insns.s
  42. +++ b/gas/testsuite/gas/riscv/vector-insns.s
  43. @@ -102,6 +102,18 @@
  44. vsoxei64.v v4, 0(a0), v12
  45. vsoxei64.v v4, (a0), v12, v0.t
  46. + vl1r.v v3, (a0)
  47. + vl1r.v v3, 0(a0)
  48. + vl1re8.v v3, (a0)
  49. + vl1re8.v v3, 0(a0)
  50. + vl1re16.v v3, (a0)
  51. + vl1re16.v v3, 0(a0)
  52. + vl1re32.v v3, (a0)
  53. + vl1re32.v v3, 0(a0)
  54. + vl1re64.v v3, (a0)
  55. + vl1re64.v v3, 0(a0)
  56. + vs1r.v v3, (a1)
  57. + vs1r.v v3, 0(a1)
  58. vneg.v v4, v8
  59. vneg.v v4, v8, v0.t
  60. @@ -519,3 +531,4 @@
  61. vcompress.vm v4, v8, v12
  62. + vmv1r.v v1, v2
  63. diff --git a/opcodes/riscv-opc.c b/opcodes/riscv-opc.c
  64. index 067ebe3115..9229f7f87a 100644
  65. --- a/opcodes/riscv-opc.c
  66. +++ b/opcodes/riscv-opc.c
  67. @@ -1580,6 +1580,14 @@ const struct riscv_opcode riscv_opcodes[] =
  68. {"vsoxei32.v", 0, INSN_CLASS_V, "Vd,0(s),VtVm", MATCH_VSOXEI32V, MASK_VSOXEI32V, match_vd_neq_vm, INSN_DREF },
  69. {"vsoxei64.v", 0, INSN_CLASS_V, "Vd,0(s),VtVm", MATCH_VSOXEI64V, MASK_VSOXEI64V, match_vd_neq_vm, INSN_DREF },
  70. +{"vl1r.v", 0, INSN_CLASS_V, "Vd,0(s)", MATCH_VL1RE8V, MASK_VL1RE8V, match_vls_nf_rv, INSN_DREF|INSN_ALIAS },
  71. +{"vl1re8.v", 0, INSN_CLASS_V, "Vd,0(s)", MATCH_VL1RE8V, MASK_VL1RE8V, match_vls_nf_rv, INSN_DREF },
  72. +{"vl1re16.v", 0, INSN_CLASS_V, "Vd,0(s)", MATCH_VL1RE16V, MASK_VL1RE16V, match_vls_nf_rv, INSN_DREF },
  73. +{"vl1re32.v", 0, INSN_CLASS_V, "Vd,0(s)", MATCH_VL1RE32V, MASK_VL1RE32V, match_vls_nf_rv, INSN_DREF },
  74. +{"vl1re64.v", 0, INSN_CLASS_V, "Vd,0(s)", MATCH_VL1RE64V, MASK_VL1RE64V, match_vls_nf_rv, INSN_DREF },
  75. +
  76. +{"vs1r.v", 0, INSN_CLASS_V, "Vd,0(s)", MATCH_VS1RV, MASK_VS1RV, match_vls_nf_rv, INSN_DREF },
  77. +
  78. {"vneg.v", 0, INSN_CLASS_V, "Vd,VtVm", MATCH_VRSUBVX, MASK_VRSUBVX | MASK_RS1, match_vd_neq_vm, INSN_ALIAS },
  79. {"vadd.vv", 0, INSN_CLASS_V, "Vd,Vt,VsVm", MATCH_VADDVV, MASK_VADDVV, match_vd_neq_vm, 0 },
  80. @@ -1808,6 +1816,8 @@ const struct riscv_opcode riscv_opcodes[] =
  81. {"vrgather.vi", 0, INSN_CLASS_V, "Vd,Vt,VjVm", MATCH_VRGATHERVI, MASK_VRGATHERVI, match_vd_neq_vs2_neq_vm, 0},
  82. {"vcompress.vm",0, INSN_CLASS_V, "Vd,Vt,Vs", MATCH_VCOMPRESSVM, MASK_VCOMPRESSVM, match_vd_neq_vs1_neq_vs2, 0},
  83. +
  84. +{"vmv1r.v", 0, INSN_CLASS_V, "Vd,Vt", MATCH_VMV1RV, MASK_VMV1RV, match_vmv_nf_rv, 0},
  85. /* END RVV */
  86. /* Terminate the list. */
  87. --
  88. 2.33.0