0060-Initial-support-for-0.94-Bitmap.patch 6.1 KB

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  1. From bdbe5285f467bf85dba7fa1413738dd26d78210f Mon Sep 17 00:00:00 2001
  2. From: LevyHsu <admin@levyhsu.com>
  3. Date: Fri, 9 Jul 2021 16:28:04 +0800
  4. Subject: [PATCH 60/61] Initial support for 0.94 Bitmap
  5. ---
  6. gcc/common/common-targhooks.h | 9 ++-
  7. gcc/common/config/riscv/riscv-common.c | 22 ++++----
  8. gcc/config/riscv/bitmanip.md | 76 --------------------------
  9. gcc/config/riscv/riscv.c | 3 +-
  10. 4 files changed, 20 insertions(+), 90 deletions(-)
  11. diff --git a/gcc/common/common-targhooks.h b/gcc/common/common-targhooks.h
  12. index 66a54c2cb9c..0c1c326b74e 100644
  13. --- a/gcc/common/common-targhooks.h
  14. +++ b/gcc/common/common-targhooks.h
  15. @@ -31,5 +31,12 @@ extern bool default_target_handle_option (struct gcc_options *,
  16. extern vec<const char *> default_get_valid_option_values (int, const char *);
  17. extern const struct default_options empty_optimization_table[];
  18. -
  19. +extern const char *default_compute_multilib(const struct switchstr *,
  20. + int,
  21. + const char *multilib,
  22. + const char *,
  23. + const char *,
  24. + const char *,
  25. + const char *,
  26. + const char *);
  27. #endif
  28. diff --git a/gcc/common/config/riscv/riscv-common.c b/gcc/common/config/riscv/riscv-common.c
  29. index 11180307064..a2a9b2cc3ab 100644
  30. --- a/gcc/common/config/riscv/riscv-common.c
  31. +++ b/gcc/common/config/riscv/riscv-common.c
  32. @@ -116,17 +116,17 @@ static const struct riscv_ext_version riscv_ext_version_table[] =
  33. {"zvlsseg", ISA_SPEC_CLASS_NONE, 1, 0},
  34. {"zvqmac", ISA_SPEC_CLASS_NONE, 1, 0},
  35. - {"b", ISA_SPEC_CLASS_NONE, 0, 93},
  36. - {"zba", ISA_SPEC_CLASS_NONE, 0, 93},
  37. - {"zbb", ISA_SPEC_CLASS_NONE, 0, 93},
  38. - {"zbc", ISA_SPEC_CLASS_NONE, 0, 93},
  39. - {"zbe", ISA_SPEC_CLASS_NONE, 0, 93},
  40. - {"zbf", ISA_SPEC_CLASS_NONE, 0, 93},
  41. - {"zbr", ISA_SPEC_CLASS_NONE, 0, 93},
  42. - {"zbm", ISA_SPEC_CLASS_NONE, 0, 93},
  43. - {"zbs", ISA_SPEC_CLASS_NONE, 0, 93},
  44. - {"zbt", ISA_SPEC_CLASS_NONE, 0, 93},
  45. - {"zbp", ISA_SPEC_CLASS_NONE, 0, 93},
  46. + {"b", ISA_SPEC_CLASS_NONE, 0, 94},
  47. + {"zba", ISA_SPEC_CLASS_NONE, 0, 94},
  48. + {"zbb", ISA_SPEC_CLASS_NONE, 0, 94},
  49. + {"zbc", ISA_SPEC_CLASS_NONE, 0, 94},
  50. + {"zbe", ISA_SPEC_CLASS_NONE, 0, 94},
  51. + {"zbf", ISA_SPEC_CLASS_NONE, 0, 94},
  52. + {"zbr", ISA_SPEC_CLASS_NONE, 0, 94},
  53. + {"zbm", ISA_SPEC_CLASS_NONE, 0, 94},
  54. + {"zbs", ISA_SPEC_CLASS_NONE, 0, 94},
  55. + {"zbt", ISA_SPEC_CLASS_NONE, 0, 94},
  56. + {"zbp", ISA_SPEC_CLASS_NONE, 0, 94},
  57. /* Terminate the list. */
  58. {NULL, ISA_SPEC_CLASS_NONE, 0, 0}
  59. diff --git a/gcc/config/riscv/bitmanip.md b/gcc/config/riscv/bitmanip.md
  60. index 3cd6bdc2de1..3026883fc0e 100644
  61. --- a/gcc/config/riscv/bitmanip.md
  62. +++ b/gcc/config/riscv/bitmanip.md
  63. @@ -153,41 +153,6 @@
  64. "bseti\t%0,%1,%S2"
  65. [(set_attr "type" "bitmanip")])
  66. -(define_insn "*bsetw"
  67. - [(set (match_operand:DI 0 "register_operand" "=r")
  68. - (sign_extend:DI
  69. - (subreg:SI
  70. - (ior:DI (subreg:DI
  71. - (ashift:SI (const_int 1)
  72. - (match_operand:QI 2 "register_operand" "r")) 0)
  73. - (match_operand:DI 1 "register_operand" "r")) 0)))]
  74. - "TARGET_64BIT && TARGET_ZBS"
  75. - "bsetw\t%0,%1,%2"
  76. - [(set_attr "type" "bitmanip")])
  77. -
  78. -(define_insn "*bsetw_mask"
  79. - [(set (match_operand:DI 0 "register_operand" "=r")
  80. - (sign_extend:DI
  81. - (subreg:SI
  82. - (ior:DI (subreg:DI
  83. - (ashift:SI
  84. - (const_int 1)
  85. - (subreg:QI
  86. - (and:DI (match_operand:DI 2 "register_operand" "r")
  87. - (match_operand 3 "const31_operand" "i")) 0)) 0)
  88. - (match_operand:DI 1 "register_operand" "r")) 0)))]
  89. - "TARGET_64BIT && TARGET_ZBS"
  90. - "bsetw\t%0,%1,%2"
  91. - [(set_attr "type" "bitmanip")])
  92. -
  93. -(define_insn "*bsetiw"
  94. - [(set (match_operand:DI 0 "register_operand" "=r")
  95. - (ior:DI (sign_extend:DI (match_operand:SI 1 "register_operand" "r"))
  96. - (match_operand 2 "single_bit_mask_operand" "i")))]
  97. - "TARGET_64BIT && TARGET_ZBS"
  98. - "bsetiw\t%0,%1,%S2"
  99. - [(set_attr "type" "bitmanip")])
  100. -
  101. (define_insn "*bclr<mode>"
  102. [(set (match_operand:X 0 "register_operand" "=r")
  103. (and:X (rotate:X (const_int -2)
  104. @@ -205,27 +170,6 @@
  105. "bclri\t%0,%1,%T2"
  106. [(set_attr "type" "bitmanip")])
  107. -(define_insn "*bclrw"
  108. - [(set (match_operand:DI 0 "register_operand" "=r")
  109. - (sign_extend:DI
  110. - (subreg:SI
  111. - (and:DI
  112. - (not:DI (subreg:DI
  113. - (ashift:SI (const_int 1)
  114. - (match_operand:QI 2 "register_operand" "r")) 0))
  115. - (match_operand:DI 1 "register_operand" "r")) 0)))]
  116. - "TARGET_64BIT && TARGET_ZBS"
  117. - "bclrw\t%0,%1,%2"
  118. - [(set_attr "type" "bitmanip")])
  119. -
  120. -(define_insn "*bclriw"
  121. - [(set (match_operand:DI 0 "register_operand" "=r")
  122. - (and:DI (sign_extend:DI (match_operand:SI 1 "register_operand" "r"))
  123. - (match_operand 2 "not_single_bit_mask_operand" "i")))]
  124. - "TARGET_64BIT && TARGET_ZBS"
  125. - "bclriw\t%0,%1,%T2"
  126. - [(set_attr "type" "bitmanip")])
  127. -
  128. (define_insn "*binv<mode>"
  129. [(set (match_operand:X 0 "register_operand" "=r")
  130. (xor:X (ashift:X (const_int 1)
  131. @@ -243,26 +187,6 @@
  132. "binvi\t%0,%1,%S2"
  133. [(set_attr "type" "bitmanip")])
  134. -(define_insn "*binvw"
  135. - [(set (match_operand:DI 0 "register_operand" "=r")
  136. - (sign_extend:DI
  137. - (subreg:SI
  138. - (xor:DI (subreg:DI
  139. - (ashift:SI (const_int 1)
  140. - (match_operand:QI 2 "register_operand" "r")) 0)
  141. - (match_operand:DI 1 "register_operand" "r")) 0)))]
  142. - "TARGET_64BIT && TARGET_ZBS"
  143. - "binvw\t%0,%1,%2"
  144. - [(set_attr "type" "bitmanip")])
  145. -
  146. -(define_insn "*binviw"
  147. - [(set (match_operand:DI 0 "register_operand" "=r")
  148. - (xor:DI (sign_extend:DI (match_operand:SI 1 "register_operand" "r"))
  149. - (match_operand 2 "single_bit_mask_operand" "i")))]
  150. - "TARGET_64BIT && TARGET_ZBS"
  151. - "binviw\t%0,%1,%S2"
  152. - [(set_attr "type" "bitmanip")])
  153. -
  154. (define_insn "*bext<mode>"
  155. [(set (match_operand:X 0 "register_operand" "=r")
  156. (zero_extract:X (match_operand:X 1 "register_operand" "r")
  157. diff --git a/gcc/config/riscv/riscv.c b/gcc/config/riscv/riscv.c
  158. index 0bbeeb51f2f..a31e97be399 100644
  159. --- a/gcc/config/riscv/riscv.c
  160. +++ b/gcc/config/riscv/riscv.c
  161. @@ -2342,12 +2342,11 @@ riscv_output_move (rtx dest, rtx src)
  162. if (TARGET_64BIT && TARGET_ZBS
  163. && SINGLE_BIT_MASK_OPERAND (INTVAL (src)))
  164. - return "sbseti\t%0,zero,%S1";
  165. + return "bseti\t%0,zero,%S1";
  166. /* Should never reach here. */
  167. abort ();
  168. }
  169. -
  170. if (src_code == HIGH)
  171. return "lui\t%0,%h1";
  172. --
  173. 2.33.0