123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185 |
- From bdbe5285f467bf85dba7fa1413738dd26d78210f Mon Sep 17 00:00:00 2001
- From: LevyHsu <admin@levyhsu.com>
- Date: Fri, 9 Jul 2021 16:28:04 +0800
- Subject: [PATCH 60/61] Initial support for 0.94 Bitmap
- ---
- gcc/common/common-targhooks.h | 9 ++-
- gcc/common/config/riscv/riscv-common.c | 22 ++++----
- gcc/config/riscv/bitmanip.md | 76 --------------------------
- gcc/config/riscv/riscv.c | 3 +-
- 4 files changed, 20 insertions(+), 90 deletions(-)
- diff --git a/gcc/common/common-targhooks.h b/gcc/common/common-targhooks.h
- index 66a54c2cb9c..0c1c326b74e 100644
- --- a/gcc/common/common-targhooks.h
- +++ b/gcc/common/common-targhooks.h
- @@ -31,5 +31,12 @@ extern bool default_target_handle_option (struct gcc_options *,
- extern vec<const char *> default_get_valid_option_values (int, const char *);
-
- extern const struct default_options empty_optimization_table[];
- -
- +extern const char *default_compute_multilib(const struct switchstr *,
- + int,
- + const char *multilib,
- + const char *,
- + const char *,
- + const char *,
- + const char *,
- + const char *);
- #endif
- diff --git a/gcc/common/config/riscv/riscv-common.c b/gcc/common/config/riscv/riscv-common.c
- index 11180307064..a2a9b2cc3ab 100644
- --- a/gcc/common/config/riscv/riscv-common.c
- +++ b/gcc/common/config/riscv/riscv-common.c
- @@ -116,17 +116,17 @@ static const struct riscv_ext_version riscv_ext_version_table[] =
- {"zvlsseg", ISA_SPEC_CLASS_NONE, 1, 0},
- {"zvqmac", ISA_SPEC_CLASS_NONE, 1, 0},
-
- - {"b", ISA_SPEC_CLASS_NONE, 0, 93},
- - {"zba", ISA_SPEC_CLASS_NONE, 0, 93},
- - {"zbb", ISA_SPEC_CLASS_NONE, 0, 93},
- - {"zbc", ISA_SPEC_CLASS_NONE, 0, 93},
- - {"zbe", ISA_SPEC_CLASS_NONE, 0, 93},
- - {"zbf", ISA_SPEC_CLASS_NONE, 0, 93},
- - {"zbr", ISA_SPEC_CLASS_NONE, 0, 93},
- - {"zbm", ISA_SPEC_CLASS_NONE, 0, 93},
- - {"zbs", ISA_SPEC_CLASS_NONE, 0, 93},
- - {"zbt", ISA_SPEC_CLASS_NONE, 0, 93},
- - {"zbp", ISA_SPEC_CLASS_NONE, 0, 93},
- + {"b", ISA_SPEC_CLASS_NONE, 0, 94},
- + {"zba", ISA_SPEC_CLASS_NONE, 0, 94},
- + {"zbb", ISA_SPEC_CLASS_NONE, 0, 94},
- + {"zbc", ISA_SPEC_CLASS_NONE, 0, 94},
- + {"zbe", ISA_SPEC_CLASS_NONE, 0, 94},
- + {"zbf", ISA_SPEC_CLASS_NONE, 0, 94},
- + {"zbr", ISA_SPEC_CLASS_NONE, 0, 94},
- + {"zbm", ISA_SPEC_CLASS_NONE, 0, 94},
- + {"zbs", ISA_SPEC_CLASS_NONE, 0, 94},
- + {"zbt", ISA_SPEC_CLASS_NONE, 0, 94},
- + {"zbp", ISA_SPEC_CLASS_NONE, 0, 94},
-
- /* Terminate the list. */
- {NULL, ISA_SPEC_CLASS_NONE, 0, 0}
- diff --git a/gcc/config/riscv/bitmanip.md b/gcc/config/riscv/bitmanip.md
- index 3cd6bdc2de1..3026883fc0e 100644
- --- a/gcc/config/riscv/bitmanip.md
- +++ b/gcc/config/riscv/bitmanip.md
- @@ -153,41 +153,6 @@
- "bseti\t%0,%1,%S2"
- [(set_attr "type" "bitmanip")])
-
- -(define_insn "*bsetw"
- - [(set (match_operand:DI 0 "register_operand" "=r")
- - (sign_extend:DI
- - (subreg:SI
- - (ior:DI (subreg:DI
- - (ashift:SI (const_int 1)
- - (match_operand:QI 2 "register_operand" "r")) 0)
- - (match_operand:DI 1 "register_operand" "r")) 0)))]
- - "TARGET_64BIT && TARGET_ZBS"
- - "bsetw\t%0,%1,%2"
- - [(set_attr "type" "bitmanip")])
- -
- -(define_insn "*bsetw_mask"
- - [(set (match_operand:DI 0 "register_operand" "=r")
- - (sign_extend:DI
- - (subreg:SI
- - (ior:DI (subreg:DI
- - (ashift:SI
- - (const_int 1)
- - (subreg:QI
- - (and:DI (match_operand:DI 2 "register_operand" "r")
- - (match_operand 3 "const31_operand" "i")) 0)) 0)
- - (match_operand:DI 1 "register_operand" "r")) 0)))]
- - "TARGET_64BIT && TARGET_ZBS"
- - "bsetw\t%0,%1,%2"
- - [(set_attr "type" "bitmanip")])
- -
- -(define_insn "*bsetiw"
- - [(set (match_operand:DI 0 "register_operand" "=r")
- - (ior:DI (sign_extend:DI (match_operand:SI 1 "register_operand" "r"))
- - (match_operand 2 "single_bit_mask_operand" "i")))]
- - "TARGET_64BIT && TARGET_ZBS"
- - "bsetiw\t%0,%1,%S2"
- - [(set_attr "type" "bitmanip")])
- -
- (define_insn "*bclr<mode>"
- [(set (match_operand:X 0 "register_operand" "=r")
- (and:X (rotate:X (const_int -2)
- @@ -205,27 +170,6 @@
- "bclri\t%0,%1,%T2"
- [(set_attr "type" "bitmanip")])
-
- -(define_insn "*bclrw"
- - [(set (match_operand:DI 0 "register_operand" "=r")
- - (sign_extend:DI
- - (subreg:SI
- - (and:DI
- - (not:DI (subreg:DI
- - (ashift:SI (const_int 1)
- - (match_operand:QI 2 "register_operand" "r")) 0))
- - (match_operand:DI 1 "register_operand" "r")) 0)))]
- - "TARGET_64BIT && TARGET_ZBS"
- - "bclrw\t%0,%1,%2"
- - [(set_attr "type" "bitmanip")])
- -
- -(define_insn "*bclriw"
- - [(set (match_operand:DI 0 "register_operand" "=r")
- - (and:DI (sign_extend:DI (match_operand:SI 1 "register_operand" "r"))
- - (match_operand 2 "not_single_bit_mask_operand" "i")))]
- - "TARGET_64BIT && TARGET_ZBS"
- - "bclriw\t%0,%1,%T2"
- - [(set_attr "type" "bitmanip")])
- -
- (define_insn "*binv<mode>"
- [(set (match_operand:X 0 "register_operand" "=r")
- (xor:X (ashift:X (const_int 1)
- @@ -243,26 +187,6 @@
- "binvi\t%0,%1,%S2"
- [(set_attr "type" "bitmanip")])
-
- -(define_insn "*binvw"
- - [(set (match_operand:DI 0 "register_operand" "=r")
- - (sign_extend:DI
- - (subreg:SI
- - (xor:DI (subreg:DI
- - (ashift:SI (const_int 1)
- - (match_operand:QI 2 "register_operand" "r")) 0)
- - (match_operand:DI 1 "register_operand" "r")) 0)))]
- - "TARGET_64BIT && TARGET_ZBS"
- - "binvw\t%0,%1,%2"
- - [(set_attr "type" "bitmanip")])
- -
- -(define_insn "*binviw"
- - [(set (match_operand:DI 0 "register_operand" "=r")
- - (xor:DI (sign_extend:DI (match_operand:SI 1 "register_operand" "r"))
- - (match_operand 2 "single_bit_mask_operand" "i")))]
- - "TARGET_64BIT && TARGET_ZBS"
- - "binviw\t%0,%1,%S2"
- - [(set_attr "type" "bitmanip")])
- -
- (define_insn "*bext<mode>"
- [(set (match_operand:X 0 "register_operand" "=r")
- (zero_extract:X (match_operand:X 1 "register_operand" "r")
- diff --git a/gcc/config/riscv/riscv.c b/gcc/config/riscv/riscv.c
- index 0bbeeb51f2f..a31e97be399 100644
- --- a/gcc/config/riscv/riscv.c
- +++ b/gcc/config/riscv/riscv.c
- @@ -2342,12 +2342,11 @@ riscv_output_move (rtx dest, rtx src)
-
- if (TARGET_64BIT && TARGET_ZBS
- && SINGLE_BIT_MASK_OPERAND (INTVAL (src)))
- - return "sbseti\t%0,zero,%S1";
- + return "bseti\t%0,zero,%S1";
-
- /* Should never reach here. */
- abort ();
- }
- -
- if (src_code == HIGH)
- return "lui\t%0,%h1";
-
- --
- 2.33.0
|