0024-add-vid-instruction-support.patch 8.4 KB

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  1. From 4dce782d6beccc91ce1723fd07e4706ee632a092 Mon Sep 17 00:00:00 2001
  2. From: "eric.tang" <eric.tang@starfivetech.com>
  3. Date: Tue, 22 Jun 2021 15:44:01 +0800
  4. Subject: [PATCH 24/28] add vid instruction support
  5. Signed-off-by: eric.tang <eric.tang@starfivetech.com>
  6. ---
  7. .../gas/riscv/vector-insns-fail-unsupport.l | 15 ----------
  8. .../gas/riscv/vector-insns-fail-unsupport.s | 16 ----------
  9. gas/testsuite/gas/riscv/vector-insns.d | 30 +++++++++++--------
  10. gas/testsuite/gas/riscv/vector-insns.s | 28 +++++++++--------
  11. opcodes/riscv-opc.c | 1 +
  12. 5 files changed, 33 insertions(+), 57 deletions(-)
  13. diff --git a/gas/testsuite/gas/riscv/vector-insns-fail-unsupport.l b/gas/testsuite/gas/riscv/vector-insns-fail-unsupport.l
  14. index ae2230cb9e..2b726b0268 100644
  15. --- a/gas/testsuite/gas/riscv/vector-insns-fail-unsupport.l
  16. +++ b/gas/testsuite/gas/riscv/vector-insns-fail-unsupport.l
  17. @@ -813,16 +813,6 @@
  18. .*: Error: unrecognized opcode `vlseg8e64ff.v v4,\(a0\)'
  19. .*: Error: unrecognized opcode `vlseg8e64ff.v v4,0\(a0\)'
  20. .*: Error: unrecognized opcode `vlseg8e64ff.v v4,\(a0\),v0.t'
  21. -.*: Error: unrecognized opcode `vl1r.v v3,\(a0\)'
  22. -.*: Error: unrecognized opcode `vl1r.v v3,0\(a0\)'
  23. -.*: Error: unrecognized opcode `vl1re8.v v3,\(a0\)'
  24. -.*: Error: unrecognized opcode `vl1re8.v v3,0\(a0\)'
  25. -.*: Error: unrecognized opcode `vl1re16.v v3,\(a0\)'
  26. -.*: Error: unrecognized opcode `vl1re16.v v3,0\(a0\)'
  27. -.*: Error: unrecognized opcode `vl1re32.v v3,\(a0\)'
  28. -.*: Error: unrecognized opcode `vl1re32.v v3,0\(a0\)'
  29. -.*: Error: unrecognized opcode `vl1re64.v v3,\(a0\)'
  30. -.*: Error: unrecognized opcode `vl1re64.v v3,0\(a0\)'
  31. .*: Error: unrecognized opcode `vl2r.v v2,\(a0\)'
  32. .*: Error: unrecognized opcode `vl2r.v v2,0\(a0\)'
  33. .*: Error: unrecognized opcode `vl2re8.v v2,\(a0\)'
  34. @@ -853,8 +843,6 @@
  35. .*: Error: unrecognized opcode `vl8re32.v v8,0\(a0\)'
  36. .*: Error: unrecognized opcode `vl8re64.v v8,\(a0\)'
  37. .*: Error: unrecognized opcode `vl8re64.v v8,0\(a0\)'
  38. -.*: Error: unrecognized opcode `vs1r.v v3,\(a1\)'
  39. -.*: Error: unrecognized opcode `vs1r.v v3,0\(a1\)'
  40. .*: Error: unrecognized opcode `vs2r.v v2,\(a1\)'
  41. .*: Error: unrecognized opcode `vs2r.v v2,0\(a1\)'
  42. .*: Error: unrecognized opcode `vs4r.v v4,\(a1\)'
  43. @@ -1455,15 +1443,12 @@
  44. .*: Error: unrecognized opcode `vmsif.m v4,v8'
  45. .*: Error: unrecognized opcode `vmsof.m v4,v8'
  46. .*: Error: unrecognized opcode `viota.m v4,v8'
  47. -.*: Error: unrecognized opcode `vid.v v4'
  48. .*: Error: unrecognized opcode `vmsbf.m v4,v8,v0.t'
  49. .*: Error: unrecognized opcode `vmsif.m v4,v8,v0.t'
  50. .*: Error: unrecognized opcode `vmsof.m v4,v8,v0.t'
  51. .*: Error: unrecognized opcode `viota.m v4,v8,v0.t'
  52. -.*: Error: unrecognized opcode `vid.v v4,v0.t'
  53. .*: Error: unrecognized opcode `vrgatherei16.vv v4,v8,v12'
  54. .*: Error: unrecognized opcode `vrgatherei16.vv v4,v8,v12,v0.t'
  55. -.*: Error: unrecognized opcode `vmv1r.v v1,v2'
  56. .*: Error: unrecognized opcode `vmv2r.v v2,v4'
  57. .*: Error: unrecognized opcode `vmv4r.v v4,v8'
  58. .*: Error: unrecognized opcode `vmv8r.v v0,v8'
  59. diff --git a/gas/testsuite/gas/riscv/vector-insns-fail-unsupport.s b/gas/testsuite/gas/riscv/vector-insns-fail-unsupport.s
  60. index 0116ac2c06..0112d0bce7 100644
  61. --- a/gas/testsuite/gas/riscv/vector-insns-fail-unsupport.s
  62. +++ b/gas/testsuite/gas/riscv/vector-insns-fail-unsupport.s
  63. @@ -967,17 +967,6 @@
  64. vlseg8e64ff.v v4, 0(a0)
  65. vlseg8e64ff.v v4, (a0), v0.t
  66. - vl1r.v v3, (a0)
  67. - vl1r.v v3, 0(a0)
  68. - vl1re8.v v3, (a0)
  69. - vl1re8.v v3, 0(a0)
  70. - vl1re16.v v3, (a0)
  71. - vl1re16.v v3, 0(a0)
  72. - vl1re32.v v3, (a0)
  73. - vl1re32.v v3, 0(a0)
  74. - vl1re64.v v3, (a0)
  75. - vl1re64.v v3, 0(a0)
  76. -
  77. vl2r.v v2, (a0)
  78. vl2r.v v2, 0(a0)
  79. vl2re8.v v2, (a0)
  80. @@ -1011,8 +1000,6 @@
  81. vl8re64.v v8, (a0)
  82. vl8re64.v v8, 0(a0)
  83. - vs1r.v v3, (a1)
  84. - vs1r.v v3, 0(a1)
  85. vs2r.v v2, (a1)
  86. vs2r.v v2, 0(a1)
  87. vs4r.v v4, (a1)
  88. @@ -1662,18 +1649,15 @@
  89. vmsif.m v4, v8
  90. vmsof.m v4, v8
  91. viota.m v4, v8
  92. - vid.v v4
  93. vmsbf.m v4, v8, v0.t
  94. vmsif.m v4, v8, v0.t
  95. vmsof.m v4, v8, v0.t
  96. viota.m v4, v8, v0.t
  97. - vid.v v4, v0.t
  98. vrgatherei16.vv v4, v8, v12
  99. vrgatherei16.vv v4, v8, v12, v0.t
  100. - vmv1r.v v1, v2
  101. vmv2r.v v2, v4
  102. vmv4r.v v4, v8
  103. vmv8r.v v0, v8
  104. diff --git a/gas/testsuite/gas/riscv/vector-insns.d b/gas/testsuite/gas/riscv/vector-insns.d
  105. index d8d6608fb3..09c12ddfef 100644
  106. --- a/gas/testsuite/gas/riscv/vector-insns.d
  107. +++ b/gas/testsuite/gas/riscv/vector-insns.d
  108. @@ -98,18 +98,6 @@ Disassembly of section .text:
  109. [ ]+[0-9a-f]+:[ ]+0ec57227[ ]+vsoxei64.v[ ]+v4,\(a0\),v12
  110. [ ]+[0-9a-f]+:[ ]+0ec57227[ ]+vsoxei64.v[ ]+v4,\(a0\),v12
  111. [ ]+[0-9a-f]+:[ ]+0cc57227[ ]+vsoxei64.v[ ]+v4,\(a0\),v12,v0.t
  112. -[ ]+[0-9a-f]+:[ ]+02850187[ ]+vl1r.v[ ]+v3,\(a0\)
  113. -[ ]+[0-9a-f]+:[ ]+02850187[ ]+vl1r.v[ ]+v3,\(a0\)
  114. -[ ]+[0-9a-f]+:[ ]+02850187[ ]+vl1r.v[ ]+v3,\(a0\)
  115. -[ ]+[0-9a-f]+:[ ]+02850187[ ]+vl1r.v[ ]+v3,\(a0\)
  116. -[ ]+[0-9a-f]+:[ ]+02855187[ ]+vl1re16.v[ ]+v3,\(a0\)
  117. -[ ]+[0-9a-f]+:[ ]+02855187[ ]+vl1re16.v[ ]+v3,\(a0\)
  118. -[ ]+[0-9a-f]+:[ ]+02856187[ ]+vl1re32.v[ ]+v3,\(a0\)
  119. -[ ]+[0-9a-f]+:[ ]+02856187[ ]+vl1re32.v[ ]+v3,\(a0\)
  120. -[ ]+[0-9a-f]+:[ ]+02857187[ ]+vl1re64.v[ ]+v3,\(a0\)
  121. -[ ]+[0-9a-f]+:[ ]+02857187[ ]+vl1re64.v[ ]+v3,\(a0\)
  122. -[ ]+[0-9a-f]+:[ ]+028581a7[ ]+vs1r.v[ ]+v3,\(a1\)
  123. -[ ]+[0-9a-f]+:[ ]+028581a7[ ]+vs1r.v[ ]+v3,\(a1\)
  124. [ ]+[0-9a-f]+:[ ]+0e804257[ ]+vneg.v[ ]+v4,v8
  125. [ ]+[0-9a-f]+:[ ]+0c804257[ ]+vneg.v[ ]+v4,v8,v0.t
  126. [ ]+[0-9a-f]+:[ ]+02860257[ ]+vadd.vv[ ]+v4,v8,v12
  127. @@ -486,4 +474,20 @@ Disassembly of section .text:
  128. [ ]+[0-9a-f]+:[ ]+30803257[ ]+vrgather.vi[ ]+v4,v8,0,v0.t
  129. [ ]+[0-9a-f]+:[ ]+308fb257[ ]+vrgather.vi[ ]+v4,v8,31,v0.t
  130. [ ]+[0-9a-f]+:[ ]+5e862257[ ]+vcompress.vm[ ]+v4,v8,v12
  131. -[ ]+[0-9a-f]+:[ ]+9e2030d7[ ]+vmv1r.v[ ]+v1,v2
  132. +[ ]+[0-9a-f]+:[ ]+9e2030d7[ ]+vmv1r.v[ ]+v1,v2
  133. +[ ]+[0-9a-f]+:[ ]+5208a257[ ]+vid.v[ ]+v4
  134. +[ ]+[0-9a-f]+:[ ]+5008a257[ ]+vid.v[ ]+v4,v0.t
  135. +[ ]+[0-9a-f]+:[ ]++02850187[ ]+vl1r.v[ ]+v3,\(a0\)
  136. +[ ]+[0-9a-f]+:[ ]++02850187[ ]+vl1r.v[ ]+v3,\(a0\)
  137. +[ ]+[0-9a-f]+:[ ]++02850187[ ]+vl1r.v[ ]+v3,\(a0\)
  138. +[ ]+[0-9a-f]+:[ ]++02850187[ ]+vl1r.v[ ]+v3,\(a0\)
  139. +[ ]+[0-9a-f]+:[ ]++02855187[ ]+vl1re16.v[ ]+v3,\(a0\)
  140. +[ ]+[0-9a-f]+:[ ]++02855187[ ]+vl1re16.v[ ]+v3,\(a0\)
  141. +[ ]+[0-9a-f]+:[ ]++02856187[ ]+vl1re32.v[ ]+v3,\(a0\)
  142. +[ ]+[0-9a-f]+:[ ]++02856187[ ]+vl1re32.v[ ]+v3,\(a0\)
  143. +[ ]+[0-9a-f]+:[ ]++02857187[ ]+vl1re64.v[ ]+v3,\(a0\)
  144. +[ ]+[0-9a-f]+:[ ]++02857187[ ]+vl1re64.v[ ]+v3,\(a0\)
  145. +[ ]+[0-9a-f]+:[ ]++028581a7[ ]+vs1r.v[ ]+v3,\(a1\)
  146. +[ ]+[0-9a-f]+:[ ]++028581a7[ ]+vs1r.v[ ]+v3,\(a1\)
  147. +
  148. +
  149. diff --git a/gas/testsuite/gas/riscv/vector-insns.s b/gas/testsuite/gas/riscv/vector-insns.s
  150. index 5cb7c7a5e2..81ef661af9 100644
  151. --- a/gas/testsuite/gas/riscv/vector-insns.s
  152. +++ b/gas/testsuite/gas/riscv/vector-insns.s
  153. @@ -102,18 +102,6 @@
  154. vsoxei64.v v4, 0(a0), v12
  155. vsoxei64.v v4, (a0), v12, v0.t
  156. - vl1r.v v3, (a0)
  157. - vl1r.v v3, 0(a0)
  158. - vl1re8.v v3, (a0)
  159. - vl1re8.v v3, 0(a0)
  160. - vl1re16.v v3, (a0)
  161. - vl1re16.v v3, 0(a0)
  162. - vl1re32.v v3, (a0)
  163. - vl1re32.v v3, 0(a0)
  164. - vl1re64.v v3, (a0)
  165. - vl1re64.v v3, 0(a0)
  166. - vs1r.v v3, (a1)
  167. - vs1r.v v3, 0(a1)
  168. vneg.v v4, v8
  169. vneg.v v4, v8, v0.t
  170. @@ -530,5 +518,19 @@
  171. vrgather.vi v4, v8, 31, v0.t
  172. vcompress.vm v4, v8, v12
  173. -
  174. vmv1r.v v1, v2
  175. + vid.v v4
  176. + vid.v v4, v0.t
  177. + vl1r.v v3, (a0)
  178. + vl1r.v v3, 0(a0)
  179. + vl1re8.v v3, (a0)
  180. + vl1re8.v v3, 0(a0)
  181. + vl1re16.v v3, (a0)
  182. + vl1re16.v v3, 0(a0)
  183. + vl1re32.v v3, (a0)
  184. + vl1re32.v v3, 0(a0)
  185. + vl1re64.v v3, (a0)
  186. + vl1re64.v v3, 0(a0)
  187. + vs1r.v v3, (a1)
  188. + vs1r.v v3, 0(a1)
  189. +
  190. diff --git a/opcodes/riscv-opc.c b/opcodes/riscv-opc.c
  191. index 9229f7f87a..7052d965d5 100644
  192. --- a/opcodes/riscv-opc.c
  193. +++ b/opcodes/riscv-opc.c
  194. @@ -1794,6 +1794,7 @@ const struct riscv_opcode riscv_opcodes[] =
  195. {"vpopc.m", 0, INSN_CLASS_V, "d,VtVm", MATCH_VPOPCM, MASK_VPOPCM, match_opcode, 0},
  196. {"vfirst.m", 0, INSN_CLASS_V, "d,VtVm", MATCH_VFIRSTM, MASK_VFIRSTM, match_opcode, 0},
  197. +{"vid.v", 0, INSN_CLASS_V, "VdVm", MATCH_VIDV, MASK_VIDV, match_vd_neq_vm, 0},
  198. {"vmv.x.s", 0, INSN_CLASS_V, "d,Vt", MATCH_VMVXS, MASK_VMVXS, match_opcode, 0},
  199. {"vmv.s.x", 0, INSN_CLASS_V, "Vd,s", MATCH_VMVSX, MASK_VMVSX, match_opcode, 0},
  200. --
  201. 2.33.0